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tactcomplabs/xbgas-binutils-gdb
| 3,813
|
gas/testsuite/gas/aarch64/armv8_4-a.s
|
# Print a 4 operand instruction
.macro print_gen4reg op, d, pd1=, pd2=, n, pn1=, pn2=, m, pm1=, pm2=, w , pw1=, pw2=
.ifnb \d
\op \pd1\d\()\pd2, \pn1\n\()\pn2, \pm1\m\()\pm2, \pw1\w\()\pw2
.else
.ifnb \n
\op \pn1\n\()\pn2, \pm1\m\()\pm2, \pw1\w\()\pw2
.else
\op \pm1\m\()\pm2, \pw1\w\()\pw2
.endif
.endif
.endm
.macro gen4reg_iter_d_offset op, d, pd1=, pd2=, r
.irp m, 03, 82, 13
\op \pd1\d\()\pd2, [\r, \m]
.endr
.endm
.macro gen4reg_iter_d_n_w op, d, pd1=, pd2=, n, pn1=, pn2=, m, pm1=, pm2=, pw1=, pw2=
.irp w, 3, 11, 15
print_gen4reg \op, \d, \pd1, \pd2, \n, \pn1, \pn2, \m, \pm1, \pm2, \w, \pw1, \pw2
.endr
.endm
.macro gen4reg_iter_d_n op, d, pd1=, pd2=, n, pn1=, pn2=, pm1=, pm2=, pw1=, pw2=
.irp m, 0, 8, 12
gen4reg_iter_d_n_w \op, \d, \pd1, \pd2, \n, \pn1, \pn2, \m, \pm1, \pm2, \pw1, \pw2
.endr
.endm
.macro gen4reg_iter_d op, d, pd1=, pd2=, pn1=, pn2=, pm1=, pm2=, pw1=, pw2=
.irp n, 2, 15, 30
gen4reg_iter_d_n \op, \d, \pd1, \pd2, \n, \pn1, \pn2, \pm1, \pm2, \pw1, \pw2
.endr
.endm
.macro gen4reg_iter op, pd1=, pd2=, pn1=, pn2=, pm1=, pm2=, pw1=, pw2=
.irp d, 0, 7, 16, 30
gen4reg_iter_d \op, \d, \pd1, \pd2, \pn1, \pn2, \pm1, \pm2, \pw1, \pw2
.endr
.endm
# Print a 3 operand instruction
.macro gen3reg_iter op, pd1=, pd2=, pn1=, pn2=, pm1=, pm2=
.irp d, 0, 7, 16, 30
gen4reg_iter_d \op,,, \d, \pd1, \pd2, \pn1, \pn2, \pm1, \pm2
.endr
.endm
.macro gen3reg_iter_lane op, pn1=, pn2=, pm1=, pm2=, pw1=, pw2=, x:vararg
.irp l, \x
gen4reg_iter_d \op,,,, \pn1, \pn2, \pm1, \pm2, \pw1, \pw2[\l]
.endr
.endm
# Print a 2 operand instruction
.macro gen2reg_iter op, pd1=, pd2=, pn1=, pn2=
.irp d, 0, 7, 16, 30
gen4reg_iter_d_n \op,,,,,, \d, \pd1, \pd2, \pn1, \pn2
.endr
.endm
.macro gen2reg_iter_offset op, pd1=, pd2=, r
.irp d, 0, 7, 16, 30
gen4reg_iter_d_offset \op, \d, \pd1, \pd2, \r,
.endr
.endm
# Print a 1 operand instruction
.macro gen1reg_iter op, pd1=, pd2=
.irp d, 0, 7, 16, 30
\op \pd1\d\()\pd2
.endr
.endm
.text
func:
gen3reg_iter rmif x,,,,,,
gen1reg_iter setf8 w,,
gen1reg_iter setf16 w,,
gen2reg_iter stlurb w,,[x,]
gen1reg_iter stlurb w,", [sp]"
gen3reg_iter stlurb w,, [x,,,]
gen2reg_iter_offset stlurb w,,sp
gen2reg_iter ldapurb w,,[x,]
gen1reg_iter ldapurb w,", [sp]"
gen3reg_iter ldapurb w,, [x,,,]
gen2reg_iter_offset ldapurb w,,sp
gen2reg_iter ldapursb w,,[x,]
gen1reg_iter ldapursb w,", [sp]"
gen3reg_iter ldapursb w,, [x,,,]
gen2reg_iter_offset ldapursb w,,sp
gen2reg_iter ldapursb x,,[x,]
gen1reg_iter ldapursb x,", [sp]"
gen3reg_iter ldapursb x,, [x,,,]
gen2reg_iter_offset ldapursb x,,sp
gen2reg_iter stlurh w,,[x,]
gen1reg_iter stlurh w,", [sp]"
gen3reg_iter stlurh w,, [x,,,]
gen2reg_iter_offset stlurh w,,sp
gen2reg_iter ldapurh w,,[x,]
gen1reg_iter ldapurh w,", [sp]"
gen3reg_iter ldapurh w,, [x,,,]
gen2reg_iter_offset ldapurh w,,sp
gen2reg_iter ldapursh w,,[x,]
gen1reg_iter ldapursh w,", [sp]"
gen3reg_iter ldapursh w,, [x,,,]
gen2reg_iter_offset ldapursh w,,sp
gen2reg_iter ldapursh x,,[x,]
gen1reg_iter ldapursh x,", [sp]"
gen3reg_iter ldapursh x,, [x,,,]
gen2reg_iter_offset ldapursh x,,sp
gen2reg_iter stlur w,,[x,]
gen1reg_iter stlur w,", [sp]"
gen3reg_iter stlur w,, [x,,,]
gen2reg_iter_offset stlur w,,sp
gen2reg_iter stlur x,,[x,]
gen1reg_iter stlur x,", [sp]"
gen3reg_iter stlur x,, [x,,,]
gen2reg_iter_offset stlur x,,sp
gen2reg_iter ldapur w,,[x,]
gen1reg_iter ldapur w,", [sp]"
gen3reg_iter ldapur w,, [x,,,]
gen2reg_iter_offset ldapur w,,sp
gen2reg_iter ldapur x,,[x,]
gen1reg_iter ldapur x,", [sp]"
gen3reg_iter ldapur x,, [x,,,]
gen2reg_iter_offset ldapur x,,sp
gen2reg_iter ldapursw x,,[x,]
gen1reg_iter ldapursw x,", [sp]"
gen3reg_iter ldapursw x,, [x,,,]
gen2reg_iter_offset ldapursw x,,sp
cfinv
|
tactcomplabs/xbgas-binutils-gdb
| 1,110
|
gas/testsuite/gas/aarch64/system.s
|
.text
drps
//
// HINTS
//
nop
yield
wfe
wfi
sev
sevl
.macro all_hints from=0, to=127
hint \from
.if \to-\from
all_hints "(\from+1)", \to
.endif
.endm
all_hints from=0, to=63
all_hints from=64, to=127
//
// SYSL
//
sysl x7, #3, C15, C7, #7
//
// BARRIERS
//
.macro all_barriers op, from=0, to=15
\op \from
.if \to-\from
all_barriers \op, "(\from+1)", \to
.endif
.endm
all_barriers op=dsb, from=0, to=15
all_barriers op=dmb, from=0, to=15
all_barriers op=isb, from=0, to=15
isb
isb sy
ssbb
pssbb
dsb oshld
dsb oshst
dsb osh
dsb nshld
dsb nshst
dsb nsh
dsb #0x08
dsb ishld
dsb ishst
dsb ish
dsb #0x0c
dsb ld
dsb st
dsb sy
//
// PREFETCHS
//
.macro all_prefetchs op, from=0, to=31
\op \from, LABEL1
\op \from, [sp, x15, lsl #0]
\op \from, [x7, w30, uxtw #3]
\op \from, [x3, #24]
.if \to-\from
all_prefetchs \op, "(\from+1)", \to
.endif
.endm
all_prefetchs op=prfm, from=0, to=31
//
// PREFETCHS with named operation
//
.irp op, pld, pli, pst
.irp l, l1, l2, l3
.irp t, keep, strm
prfm \op\l\t, [x3, #24]
.endr
.endr
.endr
|
tactcomplabs/xbgas-binutils-gdb
| 3,543
|
gas/testsuite/gas/aarch64/shifted.s
|
/* shifted.s Test file for AArch64 add-substract (extended reg.) and
add-substract (shifted reg.) instructions.
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, or
(at your option) any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
.macro op3_64 op, shift
\op x1, x2, x3, \shift #0
\op x1, x2, x3, \shift #1
\op x1, x2, x3, \shift #3
\op x1, x2, x3, \shift #7
\op x1, x2, x3, \shift #15
\op x1, x2, x3, \shift #31
\op x1, x2, x3, \shift #63
.endm
.macro op3_32 op, shift
\op w1, w2, w3, \shift #0
\op w1, w2, w3, \shift #1
\op w1, w2, w3, \shift #3
\op w1, w2, w3, \shift #7
\op w1, w2, w3, \shift #15
\op w1, w2, w3, \shift #31
.endm
.macro op3_64x op, shift
\op x1, x2, w3, \shift
\op x1, x2, w3, \shift #1
\op x1, x2, w3, \shift #2
\op x1, x2, w3, \shift #3
\op x1, x2, w3, \shift #4
.endm
.macro op3_64x_more op, shift
\op x1, x2, x3, \shift
\op x1, x2, x3, \shift #1
\op x1, x2, x3, \shift #2
\op x1, x2, x3, \shift #3
\op x1, x2, x3, \shift #4
.endm
.macro op3_32x op, shift
\op w1, w2, w3, \shift
\op w1, w2, w3, \shift #1
\op w1, w2, w3, \shift #2
\op w1, w2, w3, \shift #3
\op w1, w2, w3, \shift #4
.endm
.macro op2_64 op, shift
\op x2, x3, \shift #0
\op x2, x3, \shift #1
\op x2, x3, \shift #3
\op x2, x3, \shift #7
\op x2, x3, \shift #15
\op x2, x3, \shift #31
\op x2, x3, \shift #63
.endm
.macro op2_32 op, shift
\op w2, w3, \shift #0
\op w2, w3, \shift #1
\op w2, w3, \shift #3
\op w2, w3, \shift #7
\op w2, w3, \shift #15
\op w2, w3, \shift #31
.endm
.macro op2_64x op, shift
\op x2, w3, \shift
\op x2, w3, \shift #1
\op x2, w3, \shift #2
\op x2, w3, \shift #3
\op x2, w3, \shift #4
.endm
.macro op2_32x op, shift
\op w2, w3, \shift
\op w2, w3, \shift #1
\op w2, w3, \shift #2
\op w2, w3, \shift #3
\op w2, w3, \shift #4
.endm
.macro logical op
op3_64 \op, lsl
op3_64 \op, lsr
op3_64 \op, asr
op3_64 \op, ror
op3_32 \op, lsl
op3_32 \op, lsr
op3_32 \op, asr
op3_32 \op, ror
.endm
.macro arith3 op
op3_64 \op, lsl
op3_64 \op, lsr
op3_64 \op, asr
op3_64x \op, uxtb
op3_64x \op, uxth
op3_64x \op, uxtw
op3_64x_more \op, uxtx
op3_64x \op, sxtb
op3_64x \op, sxth
op3_64x \op, sxtw
op3_64x_more \op, sxtx
op3_32 \op, lsl
op3_32 \op, lsr
op3_32 \op, asr
op3_32x \op, uxtb
op3_32x \op, uxth
op3_32x \op, sxtb
op3_32x \op, sxth
.endm
.macro arith2 op, if_ext=1
op2_64 \op, lsl
op2_64 \op, lsr
op2_64 \op, asr
.if \if_ext
op2_64x \op, uxtb
op2_64x \op, uxth
op2_64x \op, uxtw
op2_64x \op, sxtb
op2_64x \op, sxth
op2_64x \op, sxtw
.endif
op2_32 \op, lsl
op2_32 \op, lsr
op2_32 \op, asr
.if \if_ext
op2_32x \op, uxtb
op2_32x \op, uxth
op2_32x \op, sxtb
op2_32x \op, sxth
.endif
.endm
func:
logical orr
logical and
logical eor
logical bic
logical orn
logical eon
arith3 add
arith3 sub
arith2 neg, 0
arith2 cmp
arith2 cmn
|
tactcomplabs/xbgas-binutils-gdb
| 6,553
|
gas/testsuite/gas/aarch64/sysreg-1.s
|
/* sysreg-1.s Test file for AArch64 system registers.
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, or
(at your option) any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
.macro rw_sys_reg sys_reg xreg r w
.ifc \w, 1
msr \sys_reg, \xreg
.endif
.ifc \r, 1
mrs \xreg, \sys_reg
.endif
.endm
.text
rw_sys_reg sys_reg=id_aa64afr0_el1 xreg=x7 r=1 w=0
rw_sys_reg sys_reg=id_aa64afr1_el1 xreg=x7 r=1 w=0
rw_sys_reg sys_reg=mvfr2_el1 xreg=x7 r=1 w=0
rw_sys_reg sys_reg=dlr_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=dspsr_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=sder32_el3 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=mdcr_el3 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=mdccint_el1 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=dbgvcr32_el2 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=fpexc32_el2 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=teecr32_el1 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=teehbr32_el1 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=cntp_tval_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=cntp_ctl_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=cntp_cval_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=cntps_tval_el1 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=cntps_ctl_el1 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=cntps_cval_el1 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmccntr_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevcntr0_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevcntr1_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevcntr2_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevcntr3_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevcntr4_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevcntr5_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevcntr6_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevcntr7_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevcntr8_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevcntr9_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevcntr10_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevcntr11_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevcntr12_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevcntr13_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevcntr14_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevcntr15_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevcntr16_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevcntr17_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevcntr18_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevcntr19_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevcntr20_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevcntr21_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevcntr22_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevcntr23_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevcntr24_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevcntr25_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevcntr26_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevcntr27_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevcntr28_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevcntr29_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevcntr30_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevtyper0_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevtyper1_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevtyper2_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevtyper3_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevtyper4_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevtyper5_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevtyper6_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevtyper7_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevtyper8_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevtyper9_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevtyper10_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevtyper11_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevtyper12_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevtyper13_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevtyper14_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevtyper15_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevtyper16_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevtyper17_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevtyper18_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevtyper19_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevtyper20_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevtyper21_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevtyper22_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevtyper23_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevtyper24_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevtyper25_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevtyper26_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevtyper27_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevtyper28_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevtyper29_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmevtyper30_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=pmccfiltr_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=tpidrro_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=tpidr_el0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=cntfrq_el0 xreg=x7 r=1 w=1
//
// Macros to generate MRS and MSR with all the implementation defined
// system registers in the form of S3_<op1>_<Cn>_<Cm>_<op2>.
.altmacro
.macro all_op2 op1, crn, crm, from=0, to=7
rw_sys_reg S3_\op1\()_C\crn\()_C\crm\()_\from x15 1 1
.if (\to-\from > 0)
all_op2 \op1, \crn, \crm, %(\from+1), \to
.endif
.endm
.macro all_crm op1, crn, from=0, to=15
all_op2 \op1, \crn, \from, 0, 7
.if (\to-\from > 0)
all_crm \op1, \crn, %(\from+1), \to
.endif
.endm
.macro all_imple_defined from=0, to=7
.irp crn, 11, 15
all_crm \from, \crn, 0, 15
.endr
.if \to-\from
all_imple_defined %(\from+1), \to
.endif
.endm
all_imple_defined 0, 7
.noaltmacro
rw_sys_reg sys_reg=dbgdtr_el0 xreg=x15 r=1 w=1
rw_sys_reg sys_reg=dbgdtrrx_el0 xreg=x15 r=1 w=0
rw_sys_reg sys_reg=rmr_el1 xreg=x15 r=1 w=1
rw_sys_reg sys_reg=rmr_el2 xreg=x15 r=1 w=1
rw_sys_reg sys_reg=rmr_el3 xreg=x15 r=1 w=1
rw_sys_reg sys_reg=spsr_el1 xreg=x15 r=1 w=1
rw_sys_reg sys_reg=spsr_el2 xreg=x15 r=1 w=1
rw_sys_reg sys_reg=spsr_el3 xreg=x15 r=1 w=1
rw_sys_reg sys_reg=s0_0_C0_C0_0 xreg=x15 r=1 w=1
rw_sys_reg sys_reg=s1_7_C15_C15_7 xreg=x27 r=1 w=1
rw_sys_reg sys_reg=s2_4_C6_C8_0 xreg=x14 r=1 w=1
rw_sys_reg sys_reg=s1_2_C14_C4_2 xreg=x4 r=1 w=1
rw_sys_reg sys_reg=s0_1_C13_C1_3 xreg=x7 r=1 w=1
|
tactcomplabs/xbgas-binutils-gdb
| 3,583
|
gas/testsuite/gas/aarch64/armv8_2-a-crypto-fp16.s
|
# Print a 4 operand instruction
.macro print_gen4reg op, d, pd1=, pd2=, n, pn1=, pn2=, m, pm1=, pm2=, w , pw1=, pw2=
.ifnb \d
\op \pd1\d\()\pd2, \pn1\n\()\pn2, \pm1\m\()\pm2, \pw1\w\()\pw2
.else
.ifnb \n
\op \pn1\n\()\pn2, \pm1\m\()\pm2, \pw1\w\()\pw2
.else
\op \pm1\m\()\pm2, \pw1\w\()\pw2
.endif
.endif
.endm
.macro gen4reg_iter_d_offset op, d, pd1=, pd2=, r
.irp m, 03, 82, 13
\op \pd1\d\()\pd2, [\r, \m]
.endr
.endm
.macro gen4reg_iter_d_n_w op, d, pd1=, pd2=, n, pn1=, pn2=, m, pm1=, pm2=, pw1=, pw2=
.irp w, 3, 11, 15
print_gen4reg \op, \d, \pd1, \pd2, \n, \pn1, \pn2, \m, \pm1, \pm2, \w, \pw1, \pw2
.endr
.endm
.macro gen4reg_iter_d_n op, d, pd1=, pd2=, n, pn1=, pn2=, pm1=, pm2=, pw1=, pw2=
.irp m, 0, 8, 12
gen4reg_iter_d_n_w \op, \d, \pd1, \pd2, \n, \pn1, \pn2, \m, \pm1, \pm2, \pw1, \pw2
.endr
.endm
.macro gen4reg_iter_d op, d, pd1=, pd2=, pn1=, pn2=, pm1=, pm2=, pw1=, pw2=
.irp n, 2, 15, 30
gen4reg_iter_d_n \op, \d, \pd1, \pd2, \n, \pn1, \pn2, \pm1, \pm2, \pw1, \pw2
.endr
.endm
.macro gen4reg_iter op, pd1=, pd2=, pn1=, pn2=, pm1=, pm2=, pw1=, pw2=
.irp d, 0, 7, 16, 30
gen4reg_iter_d \op, \d, \pd1, \pd2, \pn1, \pn2, \pm1, \pm2, \pw1, \pw2
.endr
.endm
# Print a 3 operand instruction
.macro gen3reg_iter op, pd1=, pd2=, pn1=, pn2=, pm1=, pm2=
.irp d, 0, 7, 16, 30
gen4reg_iter_d \op,,, \d, \pd1, \pd2, \pn1, \pn2, \pm1, \pm2
.endr
.endm
.macro gen3reg_iter_lane op, pn1=, pn2=, pm1=, pm2=, pw1=, pw2=, x:vararg
.irp l, \x
gen4reg_iter_d \op,,,, \pn1, \pn2, \pm1, \pm2, \pw1, \pw2[\l]
.endr
.endm
# Print a 2 operand instruction
.macro gen2reg_iter op, pd1=, pd2=, pn1=, pn2=
.irp d, 0, 7, 16, 30
gen4reg_iter_d_n \op,,,,,, \d, \pd1, \pd2, \pn1, \pn2
.endr
.endm
.macro gen2reg_iter_offset op, pd1=, pd2=, r
.irp d, 0, 7, 16, 30
gen4reg_iter_d_offset \op, \d, \pd1, \pd2, \r,
.endr
.endm
# Print a 1 operand instruction
.macro gen1reg_iter op, pd1=, pd2=
.irp d, 0, 7, 16, 30
\op \pd1\d\()\pd2
.endr
.endm
.text
func:
gen3reg_iter sha512h q,, q,, v,.2d
gen3reg_iter sha512h2 q,, q,, v,.2d
gen2reg_iter sha512su0 v,.2d, v,.2d
gen3reg_iter sha512su1 v,.2d, v,.2d, v,.2d
gen4reg_iter eor3 v,.16b, v,.16b, v,.16b, v,.16b
gen3reg_iter rax1 v,.2d, v,.2d, v,.2d
gen4reg_iter xar v,.2d, v,.2d, v,.2d,,
gen4reg_iter bcax v,.16b, v,.16b, v,.16b, v,.16b
gen4reg_iter sm3ss1 v,.4s, v,.4s, v,.4s, v,.4s
gen3reg_iter_lane sm3tt1a v,.4s, v,.4s, v,.s, 0, 1, 2, 3
gen3reg_iter_lane sm3tt1b v,.4s, v,.4s, v,.s, 0, 1, 2, 3
gen3reg_iter_lane sm3tt2a v,.4s, v,.4s, v,.s, 0, 1, 2, 3
gen3reg_iter_lane sm3tt2b v,.4s, v,.4s, v,.s, 0, 1, 2, 3
gen3reg_iter sm3partw1 v,.4s, v,.4s, v,.4s
gen3reg_iter sm3partw2 v,.4s, v,.4s, v,.4s
gen2reg_iter sm4e v,.4s, v,.4s
gen3reg_iter sm4ekey v,.4s, v,.4s, v,.4s
gen3reg_iter fmlal v,.2s, v,.2h, v,.2h
gen3reg_iter fmlal v,.4s, v,.4h, v,.4h
gen3reg_iter fmlsl v,.2s, v,.2h, v,.2h
gen3reg_iter fmlsl v,.4s, v,.4h, v,.4h
gen3reg_iter fmlal2 v,.2s, v,.2h, v,.2h
gen3reg_iter fmlal2 v,.4s, v,.4h, v,.4h
gen3reg_iter fmlsl2 v,.2s, v,.2h, v,.2h
gen3reg_iter fmlsl2 v,.4s, v,.4h, v,.4h
gen3reg_iter_lane fmlal v,.2s, v,.2h, v,.h, 0, 1, 5, 7
gen3reg_iter_lane fmlal v,.4s, v,.4h, v,.h, 0, 1, 5, 7
gen3reg_iter_lane fmlsl v,.2s, v,.2h, v,.h, 0, 1, 5, 7
gen3reg_iter_lane fmlsl v,.4s, v,.4h, v,.h, 0, 1, 5, 7
gen3reg_iter_lane fmlal2 v,.2s, v,.2h, v,.h, 0, 1, 5, 7
gen3reg_iter_lane fmlal2 v,.4s, v,.4h, v,.h, 0, 1, 5, 7
gen3reg_iter_lane fmlsl2 v,.2s, v,.2h, v,.h, 0, 1, 5, 7
gen3reg_iter_lane fmlsl2 v,.4s, v,.4h, v,.h, 0, 1, 5, 7
|
tactcomplabs/xbgas-binutils-gdb
| 35,779
|
gas/testsuite/gas/aarch64/sve-invalid.s
|
// Instructions in this file are invalid unless explicitly marked "OK".
// Other files provide more extensive testing of valid instructions;
// the only purpose of the valid instructions in this file is to show
// that the general form of the operands is correct.
fmov z1, z2
fmov z1, #1.0
fmov z1, #0.0
not z0.s,p1/
not z0.s,p1/,z2.s
not z0.s,p1/c,z2.s
movprfx z0.h, z1.h
movprfx z0, z1.h
movprfx z0.h, z1
movprfx z0.h, z1.s
movprfx z0, p1/m, z1
movprfx z0, p1/z, z1
movprfx z0.b, p1/m, z1
movprfx z0.b, p1/z, z1
movprfx z0, p1/m, z1.b
movprfx z0, p1/z, z1.b
movprfx z0.h, p1/m, z1.b
movprfx z0.h, p1/z, z1.b
movprfx z0.b, p1, z1.b
movprfx p0, p1
ldr p0.b, [x1]
ldr z0.b, [x1]
str p0.b, [x1]
str z0.b, [x1]
mov z0, b0
mov z0, z1
mov p0, p1
add z0, z0, z2
add z0, z0, #2
add z0, z1, z2
add z0, z1, #1
add z0.b, z1.b, #1
add z0.b, z0.h, #1
mov z0.b, z32.b
mov p0.b, p16.b
cmpeq p0.b, p8/z, z1.b, z2.b
cmpeq p0.b, p15/z, z1.b, z2.b
ld1w z0.s, p0, [x0]
ld1w z0.s, p0/m, [x0]
cmpeq p0.b, p0, z1.b, z2.b
cmpeq p0.b, p0/m, z1.b, z2.b
add z0.s, p0, z0.s, z1.s
add z0.s, p0/z, z0.s, z1.s
st1w z0.s, p0/z, [x0]
st1w z0.s, p0/m, [x0]
ld1b z0, p1/z, [x1]
ld1h z0, p1/z, [x1]
ld1w z0, p1/z, [x1]
ld1d z0, p1/z, [x1]
ldff1b z0, p1/z, [x1, xzr]
ldff1h z0, p1/z, [x1, xzr, lsl #1]
ldff1w z0, p1/z, [x1, xzr, lsl #2]
ldff1d z0, p1/z, [x1, xzr, lsl #3]
ldnf1b z0, p1/z, [x1]
ldnf1h z0, p1/z, [x1]
ldnf1w z0, p1/z, [x1]
ldnf1d z0, p1/z, [x1]
ldnt1b z0, p1/z, [x1]
ldnt1h z0, p1/z, [x1]
ldnt1w z0, p1/z, [x1]
ldnt1d z0, p1/z, [x1]
st1b z0, p1/z, [x1]
st1h z0, p1/z, [x1]
st1w z0, p1/z, [x1]
st1d z0, p1/z, [x1]
stnt1b z0, p1/z, [x1]
stnt1h z0, p1/z, [x1]
stnt1w z0, p1/z, [x1]
stnt1d z0, p1/z, [x1]
ld1b {z0}, p1/z, [x1]
ld1h {z0}, p1/z, [x1]
ld1w {z0}, p1/z, [x1]
ld1d {z0}, p1/z, [x1]
ldff1b {z0}, p1/z, [x1, xzr]
ldff1h {z0}, p1/z, [x1, xzr, lsl #1]
ldff1w {z0}, p1/z, [x1, xzr, lsl #2]
ldff1d {z0}, p1/z, [x1, xzr, lsl #3]
ldnf1b {z0}, p1/z, [x1]
ldnf1h {z0}, p1/z, [x1]
ldnf1w {z0}, p1/z, [x1]
ldnf1d {z0}, p1/z, [x1]
ldnt1b {z0}, p1/z, [x1]
ldnt1h {z0}, p1/z, [x1]
ldnt1w {z0}, p1/z, [x1]
ldnt1d {z0}, p1/z, [x1]
st1b {z0}, p1/z, [x1]
st1h {z0}, p1/z, [x1]
st1w {z0}, p1/z, [x1]
st1d {z0}, p1/z, [x1]
stnt1b {z0}, p1/z, [x1]
stnt1h {z0}, p1/z, [x1]
stnt1w {z0}, p1/z, [x1]
stnt1d {z0}, p1/z, [x1]
ld1b {x0}, p1/z, [x1]
ld1b {b0}, p1/z, [x1]
ld1b {h0}, p1/z, [x1]
ld1b {s0}, p1/z, [x1]
ld1b {d0}, p1/z, [x1]
ld1b {v0.2s}, p1/z, [x1]
ld2b {z0.b, z1}, p1/z, [x1]
ld2b {z0.b, z1.h}, p1/z, [x1]
ld2b {z0.b, z1.s}, p1/z, [x1]
ld2b {z0.b, z1.d}, p1/z, [x1]
ld2b {z0.h, z1}, p1/z, [x1]
ld2b {z0.h, z1.s}, p1/z, [x1]
ld2b {z0.h, z1.d}, p1/z, [x1]
ld2b {z0.s, z1}, p1/z, [x1]
ld2b {z0.s, z1.d}, p1/z, [x1]
ld2b {z0.d, z1}, p1/z, [x1]
ld1b z0.b, p1/z, [x1, #-9, mul vl]
ld1b z0.b, p1/z, [x1, #-8, mul vl] // OK
ld1b z0.b, p1/z, [x1, #0, mul #1]
ld1b z0.b, p1/z, [x1, #0, mul vl #1]
ld1b z0.b, p1/z, [x1, #foo, mul vl]
ld1b z0.b, p1/z, [x1, #1]
ld1b z0.b, p1/z, [x1, #7, mul vl] // OK
ld1b z0.b, p1/z, [x1, #7, mul vl]!
ld1b z0.b, p1/z, [x1, #8, mul vl]
ld2b {z0.b, z1.b}, p1/z, [x1, #-18, mul vl]
ld2b {z0.b, z1.b}, p1/z, [x1, #-17, mul vl]
ld2b {z0.b, z1.b}, p1/z, [x1, #-16, mul vl] // OK
ld2b {z0.b, z1.b}, p1/z, [x1, #foo, mul vl]
ld2b {z0.b, z1.b}, p1/z, [x1, #1, mul vl]
ld2b {z0.b, z1.b}, p1/z, [x1, #14, mul vl] // OK
ld2b {z0.b, z1.b}, p1/z, [x1, #14, mul vl]!
ld2b {z0.b, z1.b}, p1/z, [x1, #16, mul vl]
ld3b {z0.b-z2.b}, p1/z, [x1, #-27, mul vl]
ld3b {z0.b-z2.b}, p1/z, [x1, #-26, mul vl]
ld3b {z0.b-z2.b}, p1/z, [x1, #-25, mul vl]
ld3b {z0.b-z2.b}, p1/z, [x1, #-24, mul vl] // OK
ld3b {z0.b-z2.b}, p1/z, [x1, #foo, mul vl]
ld3b {z0.b-z2.b}, p1/z, [x1, #1, mul vl]
ld3b {z0.b-z2.b}, p1/z, [x1, #2, mul vl]
ld3b {z0.b-z2.b}, p1/z, [x1, #21, mul vl] // OK
ld3b {z0.b-z2.b}, p1/z, [x1, #21, mul vl]!
ld3b {z0.b-z2.b}, p1/z, [x1, #24, mul vl]
ld4b {z0.b-z3.b}, p1/z, [x1, #-36, mul vl]
ld4b {z0.b-z3.b}, p1/z, [x1, #-35, mul vl]
ld4b {z0.b-z3.b}, p1/z, [x1, #-34, mul vl]
ld4b {z0.b-z3.b}, p1/z, [x1, #-33, mul vl]
ld4b {z0.b-z3.b}, p1/z, [x1, #-32, mul vl] // OK
ld4b {z0.b-z3.b}, p1/z, [x1, #foo, mul vl]
ld4b {z0.b-z3.b}, p1/z, [x1, #1, mul vl]
ld4b {z0.b-z3.b}, p1/z, [x1, #2, mul vl]
ld4b {z0.b-z3.b}, p1/z, [x1, #3, mul vl]
ld4b {z0.b-z3.b}, p1/z, [x1, #28, mul vl] // OK
ld4b {z0.b-z3.b}, p1/z, [x1, #28, mul vl]!
ld4b {z0.b-z3.b}, p1/z, [x1, #32, mul vl]
prfb pldl1keep, p1, [x1, #-33, mul vl]
prfb pldl1keep, p1, [x1, #-32, mul vl] // OK
prfb pldl1keep, p1, [x1, #foo, mul vl]
prfb pldl1keep, p1, [x1, #1]
prfb pldl1keep, p1, [x1, #31, mul vl] // OK
prfb pldl1keep, p1, [x1, #31, mul vl]!
prfb pldl1keep, p1, [x1, #32, mul vl]
ldr z0, [x1, #-257, mul vl]
ldr z0, [x1, #-256, mul vl] // OK
ldr z0, [x1, #foo, mul vl]
ldr z0, [x1, #1]
ldr z0, [x1, #255, mul vl] // OK
ldr z0, [x1, #255, mul vl]!
ldr z0, [x1, #256, mul vl]
ld1rb z0.b, p1/z, [x1, #-1]
ld1rb z0.b, p1/z, [x1, #0] // OK
ld1rb z0.b, p1/z, [x1, #foo]
ld1rb z0.b, p1/z, [x1, #1,mul vl]
ld1rb z0.b, p1/z, [x1, #63] // OK
ld1rb z0.b, p1/z, [x1, #63]!
ld1rb z0.b, p1/z, [x1], #63
ld1rb z0.b, p1/z, [x1, #64]
ld1rh z0.h, p1/z, [x1, #-2]
ld1rh z0.h, p1/z, [x1, #-1]
ld1rh z0.h, p1/z, [x1, #0] // OK
ld1rh z0.h, p1/z, [x1, #foo]
ld1rh z0.h, p1/z, [x1, #1]
ld1rh z0.h, p1/z, [x1, #2,mul vl]
ld1rh z0.h, p1/z, [x1, #126] // OK
ld1rh z0.h, p1/z, [x1, #126]!
ld1rh z0.h, p1/z, [x1], #126
ld1rh z0.h, p1/z, [x1, #128]
ld1rw z0.s, p1/z, [x1, #-4]
ld1rw z0.s, p1/z, [x1, #-1]
ld1rw z0.s, p1/z, [x1, #0] // OK
ld1rw z0.s, p1/z, [x1, #foo]
ld1rw z0.s, p1/z, [x1, #1]
ld1rw z0.s, p1/z, [x1, #2]
ld1rw z0.s, p1/z, [x1, #4,mul vl]
ld1rw z0.s, p1/z, [x1, #252] // OK
ld1rw z0.s, p1/z, [x1, #252]!
ld1rw z0.s, p1/z, [x1], #252
ld1rw z0.s, p1/z, [x1, #256]
ld1rd z0.d, p1/z, [x1, #-8]
ld1rd z0.d, p1/z, [x1, #-1]
ld1rd z0.d, p1/z, [x1, #0] // OK
ld1rd z0.d, p1/z, [x1, #foo]
ld1rd z0.d, p1/z, [x1, #1]
ld1rd z0.d, p1/z, [x1, #2]
ld1rd z0.d, p1/z, [x1, #4]
ld1rd z0.d, p1/z, [x1, #8,mul vl]
ld1rd z0.d, p1/z, [x1, #504] // OK
ld1rd z0.d, p1/z, [x1, #504]!
ld1rd z0.d, p1/z, [x1], #504
ld1rd z0.d, p1/z, [x1, #512]
ld1b z0.b, p1/z, [x1,x2] // OK
ld1b z0.b, p1/z, [x1,x2]!
ld1b z0.b, p1/z, [x1], x2
ld1b z0.b, p1/z, [x1,x2,lsl #1]
ld1b z0.b, p1/z, [x1,x2,lsl #2]
ld1b z0.b, p1/z, [x1,x2,lsl #3]
ld1b z0.b, p1/z, [x1,x2,lsl x3]
ld1b z0.b, p1/z, [x1,w2,sxtw]
ld1b z0.b, p1/z, [x1,w2,uxtw]
ld1h z0.h, p1/z, [x1,x2]
ld1h z0.h, p1/z, [x1,x2,lsl #1] // OK
ld1h z0.h, p1/z, [x1,x2,lsl #1]!
ld1h z0.h, p1/z, [x1,x2,lsl #2]
ld1h z0.h, p1/z, [x1,x2,lsl #3]
ld1h z0.h, p1/z, [x1,x2,lsl x3]
ld1h z0.h, p1/z, [x1,w2,sxtw]
ld1h z0.h, p1/z, [x1,w2,uxtw]
ld1w z0.s, p1/z, [x1,x2]
ld1w z0.s, p1/z, [x1,x2,lsl #1]
ld1w z0.s, p1/z, [x1,x2,lsl #2] // OK
ld1w z0.s, p1/z, [x1,x2,lsl #2]!
ld1w z0.s, p1/z, [x1,x2,lsl #3]
ld1w z0.s, p1/z, [x1,x2,lsl x3]
ld1w z0.s, p1/z, [x1,w2,sxtw]
ld1w z0.s, p1/z, [x1,w2,uxtw]
ld1d z0.d, p1/z, [x1,x2]
ld1d z0.d, p1/z, [x1,x2,lsl #1]
ld1d z0.d, p1/z, [x1,x2,lsl #2]
ld1d z0.d, p1/z, [x1,x2,lsl #3] // OK
ld1d z0.d, p1/z, [x1,x2,lsl #3]!
ld1d z0.d, p1/z, [x1,x2,lsl x3]
ld1d z0.d, p1/z, [x1,w2,sxtw]
ld1d z0.d, p1/z, [x1,w2,uxtw]
ld1b z0.d, p1/z, [x1,z2.d] // OK
ld1b z0.d, p1/z, [x1,z2.d,lsl #1]
ld1b z0.d, p1/z, [x1,z2.d,lsl #2]
ld1b z0.d, p1/z, [x1,z2.d,lsl #3]
ld1b z0.d, p1/z, [x1,z2.d,lsl x3]
ld1h z0.d, p1/z, [x1,z2.d] // OK
ld1h z0.d, p1/z, [x1,z2.d,lsl #1] // OK
ld1h z0.d, p1/z, [x1,z2.d,lsl #2]
ld1h z0.d, p1/z, [x1,z2.d,lsl #3]
ld1h z0.d, p1/z, [x1,z2.d,lsl x3]
ld1w z0.d, p1/z, [x1,z2.d] // OK
ld1w z0.d, p1/z, [x1,z2.d,lsl #1]
ld1w z0.d, p1/z, [x1,z2.d,lsl #2] // OK
ld1w z0.d, p1/z, [x1,z2.d,lsl #3]
ld1w z0.d, p1/z, [x1,z2.d,lsl x3]
ld1d z0.d, p1/z, [x1,z2.d] // OK
ld1d z0.d, p1/z, [x1,z2.d,lsl #1]
ld1d z0.d, p1/z, [x1,z2.d,lsl #2]
ld1d z0.d, p1/z, [x1,z2.d,lsl #3] // OK
ld1d z0.d, p1/z, [x1,z2.d,lsl x3]
ld1b z0.s, p1/z, [x1,z2.s,sxtw] // OK
ld1b z0.s, p1/z, [x1,z2.s,sxtw #1]
ld1b z0.s, p1/z, [x1,z2.s,sxtw #2]
ld1b z0.s, p1/z, [x1,z2.s,sxtw #3]
ld1b z0.s, p1/z, [x1,z2.s,sxtw x3]
ld1h z0.s, p1/z, [x1,z2.s,sxtw] // OK
ld1h z0.s, p1/z, [x1,z2.s,sxtw #1] // OK
ld1h z0.s, p1/z, [x1,z2.s,sxtw #2]
ld1h z0.s, p1/z, [x1,z2.s,sxtw #3]
ld1h z0.s, p1/z, [x1,z2.s,sxtw x3]
ld1w z0.s, p1/z, [x1,z2.s,sxtw] // OK
ld1w z0.s, p1/z, [x1,z2.s,sxtw #1]
ld1w z0.s, p1/z, [x1,z2.s,sxtw #2] // OK
ld1w z0.s, p1/z, [x1,z2.s,sxtw #3]
ld1w z0.s, p1/z, [x1,z2.s,sxtw x3]
ld1b z0.s, p1/z, [x1,z2.s,uxtw] // OK
ld1b z0.s, p1/z, [x1,z2.s,uxtw #1]
ld1b z0.s, p1/z, [x1,z2.s,uxtw #2]
ld1b z0.s, p1/z, [x1,z2.s,uxtw #3]
ld1b z0.s, p1/z, [x1,z2.s,uxtw x3]
ld1h z0.s, p1/z, [x1,z2.s,uxtw] // OK
ld1h z0.s, p1/z, [x1,z2.s,uxtw #1] // OK
ld1h z0.s, p1/z, [x1,z2.s,uxtw #2]
ld1h z0.s, p1/z, [x1,z2.s,uxtw #3]
ld1h z0.s, p1/z, [x1,z2.s,uxtw x3]
ld1w z0.s, p1/z, [x1,z2.s,uxtw] // OK
ld1w z0.s, p1/z, [x1,z2.s,uxtw #1]
ld1w z0.s, p1/z, [x1,z2.s,uxtw #2] // OK
ld1w z0.s, p1/z, [x1,z2.s,uxtw #3]
ld1w z0.s, p1/z, [x1,z2.s,uxtw x3]
ld1b z0.d, p1/z, [x1,z2.d,sxtw] // OK
ld1b z0.d, p1/z, [x1,z2.d,sxtw #1]
ld1b z0.d, p1/z, [x1,z2.d,sxtw #2]
ld1b z0.d, p1/z, [x1,z2.d,sxtw #3]
ld1b z0.d, p1/z, [x1,z2.d,sxtw x3]
ld1h z0.d, p1/z, [x1,z2.d,sxtw] // OK
ld1h z0.d, p1/z, [x1,z2.d,sxtw #1] // OK
ld1h z0.d, p1/z, [x1,z2.d,sxtw #2]
ld1h z0.d, p1/z, [x1,z2.d,sxtw #3]
ld1h z0.d, p1/z, [x1,z2.d,sxtw x3]
ld1w z0.d, p1/z, [x1,z2.d,sxtw] // OK
ld1w z0.d, p1/z, [x1,z2.d,sxtw #1]
ld1w z0.d, p1/z, [x1,z2.d,sxtw #2] // OK
ld1w z0.d, p1/z, [x1,z2.d,sxtw #3]
ld1w z0.d, p1/z, [x1,z2.d,sxtw x3]
ld1d z0.d, p1/z, [x1,z2.d,sxtw] // OK
ld1d z0.d, p1/z, [x1,z2.d,sxtw #1]
ld1d z0.d, p1/z, [x1,z2.d,sxtw #2]
ld1d z0.d, p1/z, [x1,z2.d,sxtw #3] // OK
ld1d z0.d, p1/z, [x1,z2.d,sxtw x3]
ld1b z0.d, p1/z, [x1,z2.d,uxtw] // OK
ld1b z0.d, p1/z, [x1,z2.d,uxtw #1]
ld1b z0.d, p1/z, [x1,z2.d,uxtw #2]
ld1b z0.d, p1/z, [x1,z2.d,uxtw #3]
ld1b z0.d, p1/z, [x1,z2.d,uxtw x3]
ld1h z0.d, p1/z, [x1,z2.d,uxtw] // OK
ld1h z0.d, p1/z, [x1,z2.d,uxtw #1] // OK
ld1h z0.d, p1/z, [x1,z2.d,uxtw #2]
ld1h z0.d, p1/z, [x1,z2.d,uxtw #3]
ld1h z0.d, p1/z, [x1,z2.d,uxtw x3]
ld1w z0.d, p1/z, [x1,z2.d,uxtw] // OK
ld1w z0.d, p1/z, [x1,z2.d,uxtw #1]
ld1w z0.d, p1/z, [x1,z2.d,uxtw #2] // OK
ld1w z0.d, p1/z, [x1,z2.d,uxtw #3]
ld1w z0.d, p1/z, [x1,z2.d,uxtw x3]
ld1d z0.d, p1/z, [x1,z2.d,uxtw] // OK
ld1d z0.d, p1/z, [x1,z2.d,uxtw #1]
ld1d z0.d, p1/z, [x1,z2.d,uxtw #2]
ld1d z0.d, p1/z, [x1,z2.d,uxtw #3] // OK
ld1d z0.d, p1/z, [x1,z2.d,uxtw x3]
ld1b z0.d, p1/z, [z2.d,#-1]
ld1b z0.d, p1/z, [z2.d,#0] // OK
ld1b z0.d, p1/z, [z2.d,#foo]
ld1b z0.d, p1/z, [z2.d,#1,mul vl]
ld1b z0.d, p1/z, [z2.d,#31] // OK
ld1b z0.d, p1/z, [z2.d,#32]
ld1h z0.d, p1/z, [z2.d,#-2]
ld1h z0.d, p1/z, [z2.d,#-1]
ld1h z0.d, p1/z, [z2.d,#0] // OK
ld1h z0.d, p1/z, [z2.d,#foo]
ld1h z0.d, p1/z, [z2.d,#1]
ld1h z0.d, p1/z, [z2.d,#2,mul vl]
ld1h z0.d, p1/z, [z2.d,#62] // OK
ld1h z0.d, p1/z, [z2.d,#64]
ld1w z0.d, p1/z, [z2.d,#-4]
ld1w z0.d, p1/z, [z2.d,#-1]
ld1w z0.d, p1/z, [z2.d,#0] // OK
ld1w z0.d, p1/z, [z2.d,#foo]
ld1w z0.d, p1/z, [z2.d,#1]
ld1w z0.d, p1/z, [z2.d,#2]
ld1w z0.d, p1/z, [z2.d,#4,mul vl]
ld1w z0.d, p1/z, [z2.d,#124] // OK
ld1w z0.d, p1/z, [z2.d,#128]
ld1d z0.d, p1/z, [z2.d,#-8]
ld1d z0.d, p1/z, [z2.d,#-1]
ld1d z0.d, p1/z, [z2.d,#0] // OK
ld1d z0.d, p1/z, [z2.d,#foo]
ld1d z0.d, p1/z, [z2.d,#1]
ld1d z0.d, p1/z, [z2.d,#2]
ld1d z0.d, p1/z, [z2.d,#4]
ld1d z0.d, p1/z, [z2.d,#8,mul vl]
ld1d z0.d, p1/z, [z2.d,#248] // OK
ld1d z0.d, p1/z, [z2.d,#256]
adr z0.s, [z1.s,z2.s,lsl #-1]
adr z0.s, [z1.s,z2.s] // OK
adr z0.s, [z1.s,z2.s,lsl #1] // OK
adr z0.s, [z1.s,z2.s,lsl #2] // OK
adr z0.s, [z1.s,z2.s,lsl #3] // OK
adr z0.s, [z1.s,z2.s,lsl #4]
adr z0.s, [z1.s,z2.s,lsl x3]
adr z0.s, [z1.s,z2.d]
adr z0.s, [z1.s,x2]
adr z0.s, [z1.d,z2.s]
adr z0.s, [z1.d,w2]
adr z0.s, [x1,z2.s]
adr z0.s, [x1,z2.d]
adr z0.s, [z1.d,x2]
adr z0.s, [x1,x2]
adr z0.d, [z1.d,z2.d,lsl #-1]
adr z0.d, [z1.d,z2.d] // OK
adr z0.d, [z1.d,z2.d,lsl #1] // OK
adr z0.d, [z1.d,z2.d,lsl #2] // OK
adr z0.d, [z1.d,z2.d,lsl #3] // OK
adr z0.d, [z1.d,z2.d,lsl #4]
adr z0.d, [z1.d,z2.d,lsl x3]
adr z0.s, [z1.s,z2.s,sxtw]
adr z0.d, [z1.d,z2.d,sxtw #-1]
adr z0.d, [z1.d,z2.d,sxtw] // OK
adr z0.d, [z1.d,z2.d,sxtw #1] // OK
adr z0.d, [z1.d,z2.d,sxtw #2] // OK
adr z0.d, [z1.d,z2.d,sxtw #3] // OK
adr z0.d, [z1.d,z2.d,sxtw #4]
adr z0.d, [z1.d,z2.d,sxtw x3]
adr z0.s, [z1.s,z2.s,uxtw]
adr z0.d, [z1.d,z2.d,uxtw #-1]
adr z0.d, [z1.d,z2.d,uxtw] // OK
adr z0.d, [z1.d,z2.d,uxtw #1] // OK
adr z0.d, [z1.d,z2.d,uxtw #2] // OK
adr z0.d, [z1.d,z2.d,uxtw #3] // OK
adr z0.d, [z1.d,z2.d,uxtw #4]
adr z0.d, [z1.d,z2.d,uxtw x3]
ld1b z0.b, p0/z, [x1,xzr]
ld1b z0.h, p0/z, [x1,xzr]
ld1b z0.s, p0/z, [x1,xzr]
ld1b z0.d, p0/z, [x1,xzr]
ld1sb z0.h, p0/z, [x1,xzr]
ld1sb z0.s, p0/z, [x1,xzr]
ld1sb z0.d, p0/z, [x1,xzr]
ld1h z0.h, p0/z, [x1,xzr,lsl #1]
ld1h z0.s, p0/z, [x1,xzr,lsl #1]
ld1h z0.d, p0/z, [x1,xzr,lsl #1]
ld1sh z0.s, p0/z, [x1,xzr,lsl #1]
ld1sh z0.d, p0/z, [x1,xzr,lsl #1]
ld1w z0.s, p0/z, [x1,xzr,lsl #2]
ld1w z0.d, p0/z, [x1,xzr,lsl #2]
ld1sw z0.d, p0/z, [x1,xzr,lsl #2]
ld1d z0.d, p0/z, [x1,xzr,lsl #3]
ld2b {z0.b-z1.b}, p0/z, [x1,xzr]
ld2h {z0.h-z1.h}, p0/z, [x1,xzr,lsl #1]
ld2w {z0.s-z1.s}, p0/z, [x1,xzr,lsl #2]
ld2d {z0.d-z1.d}, p0/z, [x1,xzr,lsl #3]
ld3b {z0.b-z2.b}, p0/z, [x1,xzr]
ld3h {z0.h-z2.h}, p0/z, [x1,xzr,lsl #1]
ld3w {z0.s-z2.s}, p0/z, [x1,xzr,lsl #2]
ld3d {z0.d-z2.d}, p0/z, [x1,xzr,lsl #3]
ld4b {z0.b-z3.b}, p0/z, [x1,xzr]
ld4h {z0.h-z3.h}, p0/z, [x1,xzr,lsl #1]
ld4w {z0.s-z3.s}, p0/z, [x1,xzr,lsl #2]
ld4d {z0.d-z3.d}, p0/z, [x1,xzr,lsl #3]
ldff1b z0.b, p0/z, [x1,xzr] // OK
ldff1b z0.h, p0/z, [x1,xzr] // OK
ldff1b z0.s, p0/z, [x1,xzr] // OK
ldff1b z0.d, p0/z, [x1,xzr] // OK
ldff1sb z0.h, p0/z, [x1,xzr] // OK
ldff1sb z0.s, p0/z, [x1,xzr] // OK
ldff1sb z0.d, p0/z, [x1,xzr] // OK
ldff1h z0.h, p0/z, [x1,xzr,lsl #1] // OK
ldff1h z0.s, p0/z, [x1,xzr,lsl #1] // OK
ldff1h z0.d, p0/z, [x1,xzr,lsl #1] // OK
ldff1sh z0.s, p0/z, [x1,xzr,lsl #1] // OK
ldff1sh z0.d, p0/z, [x1,xzr,lsl #1] // OK
ldff1w z0.s, p0/z, [x1,xzr,lsl #2] // OK
ldff1w z0.d, p0/z, [x1,xzr,lsl #2] // OK
ldff1sw z0.d, p0/z, [x1,xzr,lsl #2] // OK
ldff1d z0.d, p0/z, [x1,xzr,lsl #3] // OK
ldnt1b z0.b, p0/z, [x1,xzr]
ldnt1h z0.h, p0/z, [x1,xzr,lsl #1]
ldnt1w z0.s, p0/z, [x1,xzr,lsl #2]
ldnt1d z0.d, p0/z, [x1,xzr,lsl #3]
st1b z0.b, p0, [x1,xzr]
st1b z0.h, p0, [x1,xzr]
st1b z0.s, p0, [x1,xzr]
st1b z0.d, p0, [x1,xzr]
st1h z0.h, p0, [x1,xzr,lsl #1]
st1h z0.s, p0, [x1,xzr,lsl #1]
st1h z0.d, p0, [x1,xzr,lsl #1]
st1w z0.s, p0, [x1,xzr,lsl #2]
st1w z0.d, p0, [x1,xzr,lsl #2]
st1d z0.d, p0, [x1,xzr,lsl #3]
st2b {z0.b-z1.b}, p0, [x1,xzr]
st2h {z0.h-z1.h}, p0, [x1,xzr,lsl #1]
st2w {z0.s-z1.s}, p0, [x1,xzr,lsl #2]
st2d {z0.d-z1.d}, p0, [x1,xzr,lsl #3]
st3b {z0.b-z2.b}, p0, [x1,xzr]
st3h {z0.h-z2.h}, p0, [x1,xzr,lsl #1]
st3w {z0.s-z2.s}, p0, [x1,xzr,lsl #2]
st3d {z0.d-z2.d}, p0, [x1,xzr,lsl #3]
st4b {z0.b-z3.b}, p0, [x1,xzr]
st4h {z0.h-z3.h}, p0, [x1,xzr,lsl #1]
st4w {z0.s-z3.s}, p0, [x1,xzr,lsl #2]
st4d {z0.d-z3.d}, p0, [x1,xzr,lsl #3]
stnt1b z0.b, p0, [x1,xzr]
stnt1h z0.h, p0, [x1,xzr,lsl #1]
stnt1w z0.s, p0, [x1,xzr,lsl #2]
stnt1d z0.d, p0, [x1,xzr,lsl #3]
prfb pldl1keep, p0, [x1,xzr]
prfh pldl1keep, p0, [x1,xzr,lsl #1]
prfw pldl1keep, p0, [x1,xzr,lsl #2]
prfd pldl1keep, p0, [x1,xzr,lsl #3]
add z0.b, z0.b, #-257
add z0.b, z0.b, #-256 // OK
add z0.b, z0.b, #255 // OK
add z0.b, z0.b, #256
add z0.b, z0.b, #1, lsl #1
add z0.b, z0.b, #0, lsl #8
add z0.b, z0.b, #1, lsl #8
add z0.h, z0.h, #-65537
add z0.h, z0.h, #-65536 + 257
add z0.h, z0.h, #-32767
add z0.h, z0.h, #-32768 + 255
add z0.h, z0.h, #-257
add z0.h, z0.h, #-255
add z0.h, z0.h, #-129
add z0.h, z0.h, #-128
add z0.h, z0.h, #-127
add z0.h, z0.h, #-1
add z0.h, z0.h, #0 // OK
add z0.h, z0.h, #256 // OK
add z0.h, z0.h, #257
add z0.h, z0.h, #32768-255
add z0.h, z0.h, #32767
add z0.h, z0.h, #65536 - 255
add z0.h, z0.h, #65536 - 129
add z0.h, z0.h, #65536 - 128
add z0.h, z0.h, #65535
add z0.h, z0.h, #65536
add z0.h, z0.h, #1, lsl #1
add z0.h, z0.h, #-257, lsl #8
add z0.h, z0.h, #256, lsl #8
add z0.s, z0.s, #-256
add z0.s, z0.s, #-255
add z0.s, z0.s, #-129
add z0.s, z0.s, #-128
add z0.s, z0.s, #-1
add z0.s, z0.s, #0 // OK
add z0.s, z0.s, #256 // OK
add z0.s, z0.s, #257
add z0.s, z0.s, #32768-255
add z0.s, z0.s, #32767
add z0.s, z0.s, #65536
add z0.s, z0.s, #0x100000000
add z0.s, z0.s, #1, lsl #1
add z0.s, z0.s, #-1, lsl #8
add z0.s, z0.s, #256, lsl #8
add z0.d, z0.d, #-256
add z0.d, z0.d, #-255
add z0.d, z0.d, #-129
add z0.d, z0.d, #-128
add z0.d, z0.d, #-1
add z0.d, z0.d, #0 // OK
add z0.d, z0.d, #256 // OK
add z0.d, z0.d, #257
add z0.d, z0.d, #32768-255
add z0.d, z0.d, #32767
add z0.d, z0.d, #65536
add z0.d, z0.d, #0x100000000
add z0.d, z0.d, #1, lsl #1
add z0.d, z0.d, #-1, lsl #8
add z0.d, z0.d, #256, lsl #8
dup z0.b, #-257
dup z0.b, #-256 // OK
dup z0.b, #255 // OK
dup z0.b, #256
dup z0.b, #1, lsl #1
dup z0.b, #0, lsl #8
dup z0.b, #1, lsl #8
dup z0.h, #-65537
dup z0.h, #-32767
dup z0.h, #-32768 + 255
dup z0.h, #-257
dup z0.h, #-255
dup z0.h, #-129
dup z0.h, #-128 // OK
dup z0.h, #127 // OK
dup z0.h, #128
dup z0.h, #255
dup z0.h, #257
dup z0.h, #32768-255
dup z0.h, #32767
dup z0.h, #65536 - 255
dup z0.h, #65536 - 129
dup z0.h, #65536
dup z0.h, #1, lsl #1
dup z0.h, #-257, lsl #8
dup z0.h, #256, lsl #8
dup z0.s, #-65536
dup z0.s, #-32769
dup z0.s, #-32767
dup z0.s, #-32768 + 255
dup z0.s, #-257
dup z0.s, #-255
dup z0.s, #-129
dup z0.s, #-128 // OK
dup z0.s, #127 // OK
dup z0.s, #128
dup z0.s, #255
dup z0.s, #257
dup z0.s, #32768-255
dup z0.s, #32767
dup z0.s, #32768
dup z0.s, #65536
dup z0.s, #0xffffff7f
dup z0.s, #0x100000000
dup z0.s, #1, lsl #1
dup z0.s, #-129, lsl #8
dup z0.s, #128, lsl #8
dup z0.d, #-65536
dup z0.d, #-32769
dup z0.d, #-32767
dup z0.d, #-32768 + 255
dup z0.d, #-257
dup z0.d, #-255
dup z0.d, #-129
dup z0.d, #-128 // OK
dup z0.d, #127 // OK
dup z0.d, #128
dup z0.d, #255
dup z0.d, #257
dup z0.d, #32768-255
dup z0.d, #32767
dup z0.d, #32768
dup z0.d, #65536
dup z0.d, #0xffffff7f
dup z0.d, #0x100000000
dup z0.d, #1, lsl #1
dup z0.d, #-129, lsl #8
dup z0.d, #128, lsl #8
and z0.b, z0.b, #0x01 // OK
and z0.b, z0.b, #0x0101
and z0.b, z0.b, #0x01010101
and z0.b, z0.b, #0x0101010101010101
and z0.b, z0.b, #0x7f // OK
and z0.b, z0.b, #0x7f7f
and z0.b, z0.b, #0x7f7f7f7f
and z0.b, z0.b, #0x7f7f7f7f7f7f7f7f
and z0.b, z0.b, #0x80 // OK
and z0.b, z0.b, #0x8080
and z0.b, z0.b, #0x80808080
and z0.b, z0.b, #0x8080808080808080
and z0.b, z0.b, #0xfe // OK
and z0.b, z0.b, #0xfefe
and z0.b, z0.b, #0xfefefefe
and z0.b, z0.b, #0xfefefefefefefefe
and z0.b, z0.b, #0x00010001
and z0.b, z0.b, #0x0001000100010001
and z0.b, z0.b, #0x7fff
and z0.b, z0.b, #0x7fff7fff
and z0.b, z0.b, #0x7fff7fff7fff7fff
and z0.b, z0.b, #0x8000
and z0.b, z0.b, #0x80008000
and z0.b, z0.b, #0x8000800080008000
and z0.b, z0.b, #0xfffe
and z0.b, z0.b, #0xfffefffe
and z0.b, z0.b, #0xfffefffefffefffe
and z0.b, z0.b, #0x0000000100000001
and z0.b, z0.b, #0x7fffffff
and z0.b, z0.b, #0x7fffffff7fffffff
and z0.b, z0.b, #0x80000000
and z0.b, z0.b, #0x8000000080000000
and z0.b, z0.b, #0xfffffffe
and z0.b, z0.b, #0xfffffffefffffffe
and z0.b, z0.b, #0x7fffffffffffffff
and z0.b, z0.b, #0x8000000000000000
and z0.b, z0.b, #0xfffffffffffffffe // OK
and z0.h, z0.h, #0x0101 // OK
and z0.h, z0.h, #0x01010101
and z0.h, z0.h, #0x0101010101010101
and z0.h, z0.h, #0x7f7f // OK
and z0.h, z0.h, #0x7f7f7f7f
and z0.h, z0.h, #0x7f7f7f7f7f7f7f7f
and z0.h, z0.h, #0x8080 // OK
and z0.h, z0.h, #0x80808080
and z0.h, z0.h, #0x8080808080808080
and z0.h, z0.h, #0xfefe // OK
and z0.h, z0.h, #0xfefefefe
and z0.h, z0.h, #0xfefefefefefefefe
and z0.h, z0.h, #0x00010001
and z0.h, z0.h, #0x0001000100010001
and z0.h, z0.h, #0x7fff // OK
and z0.h, z0.h, #0x7fff7fff
and z0.h, z0.h, #0x7fff7fff7fff7fff
and z0.h, z0.h, #0x8000 // OK
and z0.h, z0.h, #0x80008000
and z0.h, z0.h, #0x8000800080008000
and z0.h, z0.h, #0xfffe // OK
and z0.h, z0.h, #0xfffefffe
and z0.h, z0.h, #0xfffefffefffefffe
and z0.h, z0.h, #0x0000000100000001
and z0.h, z0.h, #0x7fffffff
and z0.h, z0.h, #0x7fffffff7fffffff
and z0.h, z0.h, #0x80000000
and z0.h, z0.h, #0x8000000080000000
and z0.h, z0.h, #0xfffffffe
and z0.h, z0.h, #0xfffffffefffffffe
and z0.h, z0.h, #0x7fffffffffffffff
and z0.h, z0.h, #0x8000000000000000
and z0.s, z0.s, #0x01010101 // OK
and z0.s, z0.s, #0x0101010101010101
and z0.s, z0.s, #0x7f7f7f7f // OK
and z0.s, z0.s, #0x7f7f7f7f7f7f7f7f
and z0.s, z0.s, #0x80808080 // OK
and z0.s, z0.s, #0x8080808080808080
and z0.s, z0.s, #0xfefefefe // OK
and z0.s, z0.s, #0xfefefefefefefefe
and z0.s, z0.s, #0x00010001 // OK
and z0.s, z0.s, #0x0001000100010001
and z0.s, z0.s, #0x7fff7fff // OK
and z0.s, z0.s, #0x7fff7fff7fff7fff
and z0.s, z0.s, #0x80008000 // OK
and z0.s, z0.s, #0x8000800080008000
and z0.s, z0.s, #0xfffefffe // OK
and z0.s, z0.s, #0xfffefffefffefffe
and z0.s, z0.s, #0x0000000100000001
and z0.s, z0.s, #0x7fffffff // OK
and z0.s, z0.s, #0x7fffffff7fffffff
and z0.s, z0.s, #0x80000000 // OK
and z0.s, z0.s, #0x8000000080000000
and z0.s, z0.s, #0xfffffffe // OK
and z0.s, z0.s, #0xfffffffefffffffe
and z0.s, z0.s, #0x7fffffffffffffff
and z0.s, z0.s, #0x8000000000000000
and z0.d, z0.d, #0xc // OK
and z0.d, z0.d, #0xd
and z0.d, z0.d, #0xe // OK
bic z0.b, z0.b, #0x01 // OK
bic z0.b, z0.b, #0x0101
bic z0.b, z0.b, #0x01010101
bic z0.b, z0.b, #0x0101010101010101
bic z0.b, z0.b, #0x7f // OK
bic z0.b, z0.b, #0x7f7f
bic z0.b, z0.b, #0x7f7f7f7f
bic z0.b, z0.b, #0x7f7f7f7f7f7f7f7f
bic z0.b, z0.b, #0x80 // OK
bic z0.b, z0.b, #0x8080
bic z0.b, z0.b, #0x80808080
bic z0.b, z0.b, #0x8080808080808080
bic z0.b, z0.b, #0xfe // OK
bic z0.b, z0.b, #0xfefe
bic z0.b, z0.b, #0xfefefefe
bic z0.b, z0.b, #0xfefefefefefefefe
bic z0.b, z0.b, #0x00010001
bic z0.b, z0.b, #0x0001000100010001
bic z0.b, z0.b, #0x7fff
bic z0.b, z0.b, #0x7fff7fff
bic z0.b, z0.b, #0x7fff7fff7fff7fff
bic z0.b, z0.b, #0x8000
bic z0.b, z0.b, #0x80008000
bic z0.b, z0.b, #0x8000800080008000
bic z0.b, z0.b, #0xfffe
bic z0.b, z0.b, #0xfffefffe
bic z0.b, z0.b, #0xfffefffefffefffe
bic z0.b, z0.b, #0x0000000100000001
bic z0.b, z0.b, #0x7fffffff
bic z0.b, z0.b, #0x7fffffff7fffffff
bic z0.b, z0.b, #0x80000000
bic z0.b, z0.b, #0x8000000080000000
bic z0.b, z0.b, #0xfffffffe
bic z0.b, z0.b, #0xfffffffefffffffe
bic z0.b, z0.b, #0x7fffffffffffffff
bic z0.b, z0.b, #0x8000000000000000
bic z0.b, z0.b, #0xfffffffffffffffe // OK
bic z0.h, z0.h, #0x0101 // OK
bic z0.h, z0.h, #0x01010101
bic z0.h, z0.h, #0x0101010101010101
bic z0.h, z0.h, #0x7f7f // OK
bic z0.h, z0.h, #0x7f7f7f7f
bic z0.h, z0.h, #0x7f7f7f7f7f7f7f7f
bic z0.h, z0.h, #0x8080 // OK
bic z0.h, z0.h, #0x80808080
bic z0.h, z0.h, #0x8080808080808080
bic z0.h, z0.h, #0xfefe // OK
bic z0.h, z0.h, #0xfefefefe
bic z0.h, z0.h, #0xfefefefefefefefe
bic z0.h, z0.h, #0x00010001
bic z0.h, z0.h, #0x0001000100010001
bic z0.h, z0.h, #0x7fff // OK
bic z0.h, z0.h, #0x7fff7fff
bic z0.h, z0.h, #0x7fff7fff7fff7fff
bic z0.h, z0.h, #0x8000 // OK
bic z0.h, z0.h, #0x80008000
bic z0.h, z0.h, #0x8000800080008000
bic z0.h, z0.h, #0xfffe // OK
bic z0.h, z0.h, #0xfffefffe
bic z0.h, z0.h, #0xfffefffefffefffe
bic z0.h, z0.h, #0x0000000100000001
bic z0.h, z0.h, #0x7fffffff
bic z0.h, z0.h, #0x7fffffff7fffffff
bic z0.h, z0.h, #0x80000000
bic z0.h, z0.h, #0x8000000080000000
bic z0.h, z0.h, #0xfffffffe
bic z0.h, z0.h, #0xfffffffefffffffe
bic z0.h, z0.h, #0x7fffffffffffffff
bic z0.h, z0.h, #0x8000000000000000
bic z0.s, z0.s, #0x01010101 // OK
bic z0.s, z0.s, #0x0101010101010101
bic z0.s, z0.s, #0x7f7f7f7f // OK
bic z0.s, z0.s, #0x7f7f7f7f7f7f7f7f
bic z0.s, z0.s, #0x80808080 // OK
bic z0.s, z0.s, #0x8080808080808080
bic z0.s, z0.s, #0xfefefefe // OK
bic z0.s, z0.s, #0xfefefefefefefefe
bic z0.s, z0.s, #0x00010001 // OK
bic z0.s, z0.s, #0x0001000100010001
bic z0.s, z0.s, #0x7fff7fff // OK
bic z0.s, z0.s, #0x7fff7fff7fff7fff
bic z0.s, z0.s, #0x80008000 // OK
bic z0.s, z0.s, #0x8000800080008000
bic z0.s, z0.s, #0xfffefffe // OK
bic z0.s, z0.s, #0xfffefffefffefffe
bic z0.s, z0.s, #0x0000000100000001
bic z0.s, z0.s, #0x7fffffff // OK
bic z0.s, z0.s, #0x7fffffff7fffffff
bic z0.s, z0.s, #0x80000000 // OK
bic z0.s, z0.s, #0x8000000080000000
bic z0.s, z0.s, #0xfffffffe // OK
bic z0.s, z0.s, #0xfffffffefffffffe
bic z0.s, z0.s, #0x7fffffffffffffff
bic z0.s, z0.s, #0x8000000000000000
bic z0.d, z0.d, #0xc // OK
bic z0.d, z0.d, #0xd
bic z0.d, z0.d, #0xe // OK
fcmeq p0.s, p1/z, z2.s, #0 // OK
fcmeq p0.s, p1/z, z2.s, #0.0 // OK
fcmeq p0.s, p1/z, z2.s, #1
fcmeq p0.s, p1/z, z2.s, #1.0
fadd z0.s, p1/m, z0.s, #0
fadd z0.s, p1/m, z0.s, #0.0
fadd z0.s, p1/m, z0.s, #0.5 // OK
fadd z0.s, p1/m, z0.s, #1 // OK
fadd z0.s, p1/m, z0.s, #1.0 // OK
fadd z0.s, p1/m, z0.s, #1.5
fadd z0.s, p1/m, z0.s, #2
fadd z0.s, p1/m, z0.s, #2.0
fmul z0.s, p1/m, z0.s, #0
fmul z0.s, p1/m, z0.s, #0.0
fmul z0.s, p1/m, z0.s, #0.5 // OK
fmul z0.s, p1/m, z0.s, #1 // OK
fmul z0.s, p1/m, z0.s, #1.0
fmul z0.s, p1/m, z0.s, #1.5
fmul z0.s, p1/m, z0.s, #2 // OK
fmul z0.s, p1/m, z0.s, #2.0 // OK
fmax z0.s, p1/m, z0.s, #0 // OK
fmax z0.s, p1/m, z0.s, #0.0 // OK
fmax z0.s, p1/m, z0.s, #0.5
fmax z0.s, p1/m, z0.s, #1 // OK
fmax z0.s, p1/m, z0.s, #1.0 // OK
fmax z0.s, p1/m, z0.s, #1.5
fmax z0.s, p1/m, z0.s, #2
fmax z0.s, p1/m, z0.s, #2.0
ptrue p1.b, vl0
ptrue p1.b, vl255
ptrue p1.b, #-1
ptrue p1.b, #0 // OK
ptrue p1.b, #31 // OK
ptrue p1.b, #32
ptrue p1.b, x0
ptrue p1.b, z0.s
cntb x0, vl0
cntb x0, vl255
cntb x0, #-1
cntb x0, #0 // OK
cntb x0, #31 // OK
cntb x0, #32
cntb x0, x0
cntb x0, z0.s
cntb x0, mul #1
cntb x0, pow2, mul #0
cntb x0, pow2, mul #1 // OK
cntb x0, pow2, mul #16 // OK
cntb x0, pow2, mul #17
cntb x0, pow2, #1
prfb pldl0keep, p1, [x0]
prfb pldl1keep, p1, [x0] // OK
prfb pldl2keep, p1, [x0] // OK
prfb pldl3keep, p1, [x0] // OK
prfb pldl4keep, p1, [x0]
prfb #-1, p1, [x0]
prfb #0, p1, [x0] // OK
prfb #15, p1, [x0] // OK
prfb #16, p1, [x0]
prfb x0, p1, [x0]
prfb z0.s, p1, [x0]
lsl z0.b, z0.b, #-1
lsl z0.b, z0.b, #0 // OK
lsl z0.b, z0.b, #1 // OK
lsl z0.b, z0.b, #7 // OK
lsl z0.b, z0.b, #8
lsl z0.b, z0.b, #9
lsl z0.b, z0.b, x0
lsl z0.h, z0.h, #-1
lsl z0.h, z0.h, #0 // OK
lsl z0.h, z0.h, #1 // OK
lsl z0.h, z0.h, #15 // OK
lsl z0.h, z0.h, #16
lsl z0.h, z0.h, #17
lsl z0.s, z0.s, #-1
lsl z0.s, z0.s, #0 // OK
lsl z0.s, z0.s, #1 // OK
lsl z0.s, z0.s, #31 // OK
lsl z0.s, z0.s, #32
lsl z0.s, z0.s, #33
lsl z0.d, z0.d, #-1
lsl z0.d, z0.d, #0 // OK
lsl z0.d, z0.d, #1 // OK
lsl z0.d, z0.d, #63 // OK
lsl z0.d, z0.d, #64
lsl z0.d, z0.d, #65
lsl z0.b, p1/m, z0.b, #-1
lsl z0.b, p1/m, z0.b, #0 // OK
lsl z0.b, p1/m, z0.b, #1 // OK
lsl z0.b, p1/m, z0.b, #7 // OK
lsl z0.b, p1/m, z0.b, #8
lsl z0.b, p1/m, z0.b, #9
lsl z0.b, p1/m, z0.b, x0
lsl z0.h, p1/m, z0.h, #-1
lsl z0.h, p1/m, z0.h, #0 // OK
lsl z0.h, p1/m, z0.h, #1 // OK
lsl z0.h, p1/m, z0.h, #15 // OK
lsl z0.h, p1/m, z0.h, #16
lsl z0.h, p1/m, z0.h, #17
lsl z0.s, p1/m, z0.s, #-1
lsl z0.s, p1/m, z0.s, #0 // OK
lsl z0.s, p1/m, z0.s, #1 // OK
lsl z0.s, p1/m, z0.s, #31 // OK
lsl z0.s, p1/m, z0.s, #32
lsl z0.s, p1/m, z0.s, #33
lsl z0.d, p1/m, z0.d, #-1
lsl z0.d, p1/m, z0.d, #0 // OK
lsl z0.d, p1/m, z0.d, #1 // OK
lsl z0.d, p1/m, z0.d, #63 // OK
lsl z0.d, p1/m, z0.d, #64
lsl z0.d, p1/m, z0.d, #65
lsr z0.b, z0.b, #-1
lsr z0.b, z0.b, #0
lsr z0.b, z0.b, #1 // OK
lsr z0.b, z0.b, #7 // OK
lsr z0.b, z0.b, #8 // OK
lsr z0.b, z0.b, #9
lsr z0.b, z0.b, x0
lsr z0.h, z0.h, #-1
lsr z0.h, z0.h, #0
lsr z0.h, z0.h, #1 // OK
lsr z0.h, z0.h, #15 // OK
lsr z0.h, z0.h, #16 // OK
lsr z0.h, z0.h, #17
lsr z0.s, z0.s, #-1
lsr z0.s, z0.s, #0
lsr z0.s, z0.s, #1 // OK
lsr z0.s, z0.s, #31 // OK
lsr z0.s, z0.s, #32 // OK
lsr z0.s, z0.s, #33
lsr z0.d, z0.d, #-1
lsr z0.d, z0.d, #0
lsr z0.d, z0.d, #1 // OK
lsr z0.d, z0.d, #63 // OK
lsr z0.d, z0.d, #64 // OK
lsr z0.d, z0.d, #65
lsr z0.b, p1/m, z0.b, #-1
lsr z0.b, p1/m, z0.b, #0
lsr z0.b, p1/m, z0.b, #1 // OK
lsr z0.b, p1/m, z0.b, #7 // OK
lsr z0.b, p1/m, z0.b, #8 // OK
lsr z0.b, p1/m, z0.b, #9
lsr z0.b, p1/m, z0.b, x0
lsr z0.h, p1/m, z0.h, #-1
lsr z0.h, p1/m, z0.h, #0
lsr z0.h, p1/m, z0.h, #1 // OK
lsr z0.h, p1/m, z0.h, #15 // OK
lsr z0.h, p1/m, z0.h, #16 // OK
lsr z0.h, p1/m, z0.h, #17
lsr z0.s, p1/m, z0.s, #-1
lsr z0.s, p1/m, z0.s, #0
lsr z0.s, p1/m, z0.s, #1 // OK
lsr z0.s, p1/m, z0.s, #31 // OK
lsr z0.s, p1/m, z0.s, #32 // OK
lsr z0.s, p1/m, z0.s, #33
lsr z0.d, p1/m, z0.d, #-1
lsr z0.d, p1/m, z0.d, #0
lsr z0.d, p1/m, z0.d, #1 // OK
lsr z0.d, p1/m, z0.d, #63 // OK
lsr z0.d, p1/m, z0.d, #64 // OK
lsr z0.d, p1/m, z0.d, #65
index z0.s, #-17, #1
index z0.s, #-16, #1 // OK
index z0.s, #15, #1 // OK
index z0.s, #16, #1
index z0.s, #0, #-17
index z0.s, #0, #-16 // OK
index z0.s, #0, #15 // OK
index z0.s, #0, #16
addpl x0, sp, #-33
addpl x0, sp, #-32 // OK
addpl sp, x0, #31 // OK
addpl sp, x0, #32
addpl x0, xzr, #1
addpl xzr, x0, #1
mul z0.b, z0.b, #-129
mul z0.b, z0.b, #-128 // OK
mul z0.b, z0.b, #127 // OK
mul z0.b, z0.b, #128
mul z0.s, z0.s, #-129
mul z0.s, z0.s, #-128 // OK
mul z0.s, z0.s, #127 // OK
mul z0.s, z0.s, #128
ftmad z0.s, z0.s, z1.s, #-1
ftmad z0.s, z0.s, z1.s, #0 // OK
ftmad z0.s, z0.s, z1.s, #7 // OK
ftmad z0.s, z0.s, z1.s, #8
ftmad z0.s, z0.s, z1.s, z2.s
cmphi p0.s,p1/z,z2.s,#-1
cmphi p0.s,p1/z,z2.s,#0 // OK
cmphi p0.s,p1/z,z2.s,#127 // OK
cmphi p0.s,p1/z,z2.s,#128
umax z0.s, z0.s, #-1
umax z0.s, z0.s, #0 // OK
umax z0.s, z0.s, #255 // OK
umax z0.s, z0.s, #256
ext z0.b, z0.b, z1.b, #-1
ext z0.b, z0.b, z1.b, #0 // OK
ext z0.b, z0.b, z1.b, #255 // OK
ext z0.b, z0.b, z1.b, #256
dup z0.b, z1.b[-1]
dup z0.b, z1.b[0] // OK
dup z0.b, z1.b[63] // OK
dup z0.b, z1.b[64]
dup z0.b, z1.b[x0]
dup z0.h, z1.h[-1]
dup z0.h, z1.h[0] // OK
dup z0.h, z1.h[31] // OK
dup z0.h, z1.h[32]
dup z0.h, z1.h[x0]
dup z0.s, z1.s[-1]
dup z0.s, z1.s[0] // OK
dup z0.s, z1.s[15] // OK
dup z0.s, z1.s[16]
dup z0.s, z1.s[x0]
dup z0.d, z1.d[-1]
dup z0.d, z1.d[0] // OK
dup z0.d, z1.d[7] // OK
dup z0.d, z1.d[8]
dup z0.d, z1.d[x0]
fabd z0.b, p0/m, z0.b, z0.b
fabd z0.q, p0/m, z0.q, z0.q
fcadd z0.b, p0/m, z0.b, z0.b, #90
fcadd z0.h, p0/m, z0.h, z0.h, #-180
fcadd z0.h, p0/m, z0.h, z0.h, #-90
fcadd z0.h, p0/m, z0.h, z0.h, #0
fcadd z0.h, p0/m, z0.h, z0.h, #89
fcadd z0.h, p0/m, z0.h, z0.h, #90.0
fcadd z0.h, p0/m, z0.h, z0.h, #180
fcadd z0.h, p0/m, z0.h, z0.h, #360
fcadd z0.h, p0/m, z0.h, z0.h, #450
fcadd z0.h, p0/z, z0.h, z0.h, #90
fcadd z0.h, p0/m, z1.h, z0.h, #90
fcadd z0.q, p0/m, z0.q, z0.q, #90
fcmla z0.b, p0/m, z0.b, z0.b, #90
fcmla z0.h, p0/m, z0.h, z0.h, #-180
fcmla z0.h, p0/m, z0.h, z0.h, #-90
fcmla z0.h, p0/m, z0.h, z0.h, #89
fcmla z0.h, p0/m, z0.h, z0.h, #90.0
fcmla z0.h, p0/m, z0.h, z0.h, #360
fcmla z0.h, p0/m, z0.h, z0.h, #450
fcmla z0.h, p0/z, z0.h, z0.h, #90
fcmla z0.q, p0/m, z0.q, z0.q, #90
fcmla z0.b, z1.b, z2.b[0], #0
fcmla z0.h, z1.h, z2.h[-1], #0
fcmla z0.h, z1.h, z2.h[4], #0
fcmla z0.h, z1.h, z8.h[0], #0
fcmla z0.h, z1.h, z2.h[0], #-180
fcmla z0.h, z1.h, z2.h[0], #-90
fcmla z0.h, z1.h, z2.h[0], #89
fcmla z0.h, z1.h, z2.h[0], #90.0
fcmla z0.h, z1.h, z2.h[0], #360
fcmla z0.h, z1.h, z2.h[0], #450
fcmla z0.s, z1.s, z2.s[-1], #0
fcmla z0.s, z1.s, z2.s[2], #0
fcmla z0.s, z1.s, z16.s[0], #0
fcmla z0.s, z1.s, z2.s[0], #-180
fcmla z0.s, z1.s, z2.s[0], #-90
fcmla z0.s, z1.s, z2.s[0], #89
fcmla z0.s, z1.s, z2.s[0], #90.0
fcmla z0.s, z1.s, z2.s[0], #360
fcmla z0.s, z1.s, z2.s[0], #450
fcmla z0.q, z1.q, z2.q[0], #0
fmla z0.b, z1.b, z2.b[0]
fmla z0.h, z1.h, z2.h[-1]
fmla z0.h, z1.h, z2.h[8]
fmla z0.h, z1.h, z8.h[0]
fmla z0.s, z1.s, z2.s[-1]
fmla z0.s, z1.s, z2.s[4]
fmla z0.s, z1.s, z8.s[0]
fmla z0.d, z1.d, z2.d[-1]
fmla z0.d, z1.d, z2.d[2]
fmla z0.d, z1.d, z16.d[0]
fmla z0.q, z1.q, z2.q[0]
fmls z0.b, z1.b, z2.b[0]
fmls z0.h, z1.h, z2.h[-1]
fmls z0.h, z1.h, z2.h[8]
fmls z0.h, z1.h, z8.h[0]
fmls z0.s, z1.s, z2.s[-1]
fmls z0.s, z1.s, z2.s[4]
fmls z0.s, z1.s, z8.s[0]
fmls z0.d, z1.d, z2.d[-1]
fmls z0.d, z1.d, z2.d[2]
fmls z0.d, z1.d, z16.d[0]
fmls z0.q, z1.q, z2.q[0]
fmul z0.b, z1.b, z2.b[0]
fmul z0.h, z1.h, z2.h[-1]
fmul z0.h, z1.h, z2.h[8]
fmul z0.h, z1.h, z8.h[0]
fmul z0.s, z1.s, z2.s[-1]
fmul z0.s, z1.s, z2.s[4]
fmul z0.s, z1.s, z8.s[0]
fmul z0.d, z1.d, z2.d[-1]
fmul z0.d, z1.d, z2.d[2]
fmul z0.d, z1.d, z16.d[0]
fmul z0.q, z1.q, z2.q[0]
ld1rqb {z0.b}, p0, [x0, #0]
ld1rqb {z0.b}, p0/m, [x0, #0]
ld1rqb {z0.b}, p8/z, [x0, #0]
ld1rqb {z0.b}, p0/z, [x0, #-144]
ld1rqb {z0.b}, p0/z, [x0, #-15]
ld1rqb {z0.b}, p0/z, [x0, #-14]
ld1rqb {z0.b}, p0/z, [x0, #-13]
ld1rqb {z0.b}, p0/z, [x0, #-12]
ld1rqb {z0.b}, p0/z, [x0, #-11]
ld1rqb {z0.b}, p0/z, [x0, #-10]
ld1rqb {z0.b}, p0/z, [x0, #-9]
ld1rqb {z0.b}, p0/z, [x0, #-8]
ld1rqb {z0.b}, p0/z, [x0, #-7]
ld1rqb {z0.b}, p0/z, [x0, #-6]
ld1rqb {z0.b}, p0/z, [x0, #-5]
ld1rqb {z0.b}, p0/z, [x0, #-4]
ld1rqb {z0.b}, p0/z, [x0, #-3]
ld1rqb {z0.b}, p0/z, [x0, #-2]
ld1rqb {z0.b}, p0/z, [x0, #-1]
ld1rqb {z0.b}, p0/z, [x0, #1]
ld1rqb {z0.b}, p0/z, [x0, #2]
ld1rqb {z0.b}, p0/z, [x0, #3]
ld1rqb {z0.b}, p0/z, [x0, #4]
ld1rqb {z0.b}, p0/z, [x0, #5]
ld1rqb {z0.b}, p0/z, [x0, #6]
ld1rqb {z0.b}, p0/z, [x0, #7]
ld1rqb {z0.b}, p0/z, [x0, #8]
ld1rqb {z0.b}, p0/z, [x0, #9]
ld1rqb {z0.b}, p0/z, [x0, #10]
ld1rqb {z0.b}, p0/z, [x0, #11]
ld1rqb {z0.b}, p0/z, [x0, #12]
ld1rqb {z0.b}, p0/z, [x0, #13]
ld1rqb {z0.b}, p0/z, [x0, #14]
ld1rqb {z0.b}, p0/z, [x0, #15]
ld1rqb {z0.b}, p0/z, [x0, #128]
ld1rqb {z0.h}, p0/z, [x0, #0]
ld1rqb {z0.s}, p0/z, [x0, #0]
ld1rqb {z0.d}, p0/z, [x0, #0]
ld1rqb {z0.q}, p0/z, [x0, #0]
ld1rqb {z0.b}, p0/z, [x0, xzr]
ld1rqb {z0.b}, p0/z, [x0, x1, lsl #1]
ld1rqb {z0.b}, p0/z, [x0, x1, lsl #2]
ld1rqb {z0.b}, p0/z, [x0, x1, lsl #3]
ld1rqh {z0.h}, p0/z, [x0, xzr, lsl #1]
ld1rqh {z0.h}, p0/z, [x0, x1]
ld1rqh {z0.h}, p0/z, [x0, x1, lsl #2]
ld1rqh {z0.h}, p0/z, [x0, x1, lsl #3]
ld1rqw {z0.s}, p0/z, [x0, xzr, lsl #2]
ld1rqw {z0.s}, p0/z, [x0, x1]
ld1rqw {z0.s}, p0/z, [x0, x1, lsl #1]
ld1rqw {z0.s}, p0/z, [x0, x1, lsl #3]
ld1rqd {z0.d}, p0/z, [x0, xzr, lsl #3]
ld1rqd {z0.d}, p0/z, [x0, x1]
ld1rqd {z0.d}, p0/z, [x0, x1, lsl #1]
ld1rqd {z0.d}, p0/z, [x0, x1, lsl #2]
sdot z0.b, z1.b, z2.b
sdot z0.h, z1.h, z2.h
sdot z0.s, z1.s, z2.s
sdot z0.d, z1.d, z2.d
sdot z0.b, z1.b, z2.b[0]
sdot z0.h, z1.h, z2.h[0]
sdot z0.s, z1.s, z2.s[0]
sdot z0.d, z1.d, z2.d[0]
udot z0.b, z1.b, z2.b
udot z0.h, z1.h, z2.h
udot z0.s, z1.s, z2.s
udot z0.d, z1.d, z2.d
udot z0.b, z1.b, z2.b[0]
udot z0.h, z1.h, z2.h[0]
udot z0.s, z1.s, z2.s[0]
udot z0.d, z1.d, z2.d[0]
|
tactcomplabs/xbgas-binutils-gdb
| 2,107
|
gas/testsuite/gas/aarch64/sme-5-illegal.s
|
/* Scalable Matrix Extension (SME). */
ld1b {za0h.b[w11, 0]}, p0/z, [x0]
ld1h {za0h.h[w16, 0]}, p0/z, [x0]
ld1h {za0v.h[w12, 0]}, p0/z, [x0, x0, lsl #3]
ld1w {za3v.s[w15, 3]}, p7/z, [sp, lsl #2]
ld1d {za0h.d[w12, 0]}, p0/z, [sp, x0, lsl #12]
ld1q {za0v.q[w12]}, p0/z, [x0, x0, lsl #2]
ld1b {za1h.b[w12, 0]}, p0/z, [x0]
ld1b {za1v.b[w12, 0]}, p0/z, [sp]
ld1b {za1h.b[w12, 0]}, p0/z, [sp, x0]
ld1b {za0v.b[w15, 16]}, p7/z, [x17]
ld1b {za0h.b[w15, 16]}, p7/z, [sp]
ld1b {za0v.b[w15, 16]}, p7/z, [sp, x17]
ld1h {za2v.h[w12, 0]}, p0/z, [x0]
ld1h {za2h.h[w12, 0]}, p0/z, [sp]
ld1h {za2v.h[w12, 0]}, p0/z, [x0, x0, lsl #1]
ld1h {za2h.h[w12, 0]}, p0/z, [sp, x0, lsl #1]
ld1h {za1v.h[w15, 8]}, p7/z, [x17]
ld1h {za1h.h[w15, 8]}, p7/z, [sp]
ld1h {za1v.h[w15, 8]}, p7/z, [x0, x17, lsl #1]
ld1h {za1h.h[w15, 8]}, p7/z, [sp, x17, lsl #1]
ld1w {za4h.s[w12, 0]}, p0/z, [x0]
ld1w {za4v.s[w12, 0]}, p0/z, [sp]
ld1w {za4h.s[w12, 0]}, p0/z, [x0, x0, lsl #2]
ld1w {za4v.s[w12, 0]}, p0/z, [sp, x0, lsl #2]
ld1w {za3h.s[w15, 4]}, p7/z, [x17]
ld1w {za3v.s[w15, 4]}, p7/z, [sp]
ld1w {za3h.s[w15, 4]}, p7/z, [x0, x17, lsl #2]
ld1w {za3v.s[w15, 4]}, p7/z, [sp, x17, lsl #2]
ld1d {za8v.d[w12, 0]}, p0/z, [x0]
ld1d {za8h.d[w12, 0]}, p0/z, [sp]
ld1d {za8v.d[w12, 0]}, p0/z, [x0, x0, lsl #3]
ld1d {za8h.d[w12, 0]}, p0/z, [sp, x0, lsl #3]
ld1d {za7v.d[w15, 2]}, p7/z, [x17]
ld1d {za7h.d[w15, 2]}, p7/z, [sp]
ld1d {za7v.d[w15, 2]}, p7/z, [x0, x17, lsl #3]
ld1d {za7h.d[w15, 2]}, p7/z, [sp, x17, lsl #3]
ld1q {za16v.q[w12]}, p0/z, [x0]
ld1q {za16h.q[w12]}, p0/z, [sp]
ld1q {za16v.q[w12]}, p0/z, [x0, x0, lsl #4]
ld1q {za16h.q[w12]}, p0/z, [sp, x0, lsl #4]
ld1q {za15v.q[w15, 1]}, p7/z, [x17]
ld1q {za15h.q[w15, 1]}, p7/z, [sp]
ld1q {za15v.q[w15, 1]}, p7/z, [x0, x17, lsl #4]
ld1q {za15h.q[w15, 1]}, p7/z, [sp, x17, lsl #4]
/* Illegal operand 3 addressing modes. */
ld1b {za0h.b[w12, 0]}, p0/z, [x0, x1, lsl #1]
ld1h {za0h.h[w12, 0]}, p0/z, [x0, x1, lsl #2]
ld1w {za3v.s[w12, 3]}, p7/z, [x0, x1, lsl #3]
ld1d {za0h.d[w12, 0]}, p0/z, [x0, x1, lsl #4]
ld1q {za0v.q[w12, 0]}, p0/z, [x0, x1, lsl #1]
ld1q {za0v.q[w12]}, p0/z, [x0, x1, lsl #1]
|
tactcomplabs/xbgas-binutils-gdb
| 1,840
|
gas/testsuite/gas/aarch64/bfloat16.s
|
/* The instructions with non-zero register numbers are there to ensure we have
the correct argument positioning (i.e. check that the first argument is at
the end of the word etc).
The instructions with all-zero register numbers are to ensure the previous
encoding didn't just "happen" to fit -- so that if we change the registers
that changes the correct part of the word.
Each of the numbered patterns begin and end with a 1, so we can replace
them with all-zeros and see the entire range has changed. */
// SVE
bfdot z17.s, z21.h, z27.h
bfdot z0.s, z0.h, z0.h
bfdot z17.s, z21.h, z5.h[3]
bfdot z0.s, z0.h, z0.h[3]
bfdot z0.s, z0.h, z0.h[0]
bfmmla z17.s, z21.h, z27.h
bfmmla z0.s, z0.h, z0.h
bfcvt z17.h, p5/m, z21.s
bfcvt z0.h, p0/m, z0.s
bfcvtnt z17.h, p5/m, z21.s
bfcvtnt z0.h, p0/m, z0.s
bfmlalt z17.s, z21.h, z27.h
bfmlalt z0.s, z0.h, z0.h
bfmlalb z17.s, z21.h, z27.h
bfmlalb z0.s, z0.h, z0.h
bfmlalt z17.s, z21.h, z5.h[0]
bfmlalt z0.s, z0.h, z0.h[7]
bfmlalb z17.s, z21.h, z5.h[0]
bfmlalb z0.s, z0.h, z0.h[7]
// SIMD
bfdot v17.2s, v21.4h, v27.4h
bfdot v0.2s, v0.4h, v0.4h
bfdot v17.4s, v21.8h, v27.8h
bfdot v0.4s, v0.8h, v0.8h
bfdot v17.2s, v21.4h, v27.2h[3]
bfdot v0.2s, v0.4h, v0.2h[3]
bfdot v17.4s, v21.8h, v27.2h[3]
bfdot v0.4s, v0.8h, v0.2h[3]
bfdot v17.2s, v21.4h, v27.2h[0]
bfdot v0.2s, v0.4h, v0.2h[0]
bfdot v17.4s, v21.8h, v27.2h[0]
bfdot v0.4s, v0.8h, v0.2h[0]
bfmmla v17.4s, v21.8h, v27.8h
bfmmla v0.4s, v0.8h, v0.8h
bfmlalb v17.4s, v21.8h, v27.8h
bfmlalb v0.4s, v0.8h, v0.8h
bfmlalt v17.4s, v21.8h, v27.8h
bfmlalt v0.4s, v0.8h, v0.8h
bfmlalb v17.4s, v21.8h, v15.h[0]
bfmlalb v0.4s, v0.8h, v0.h[7]
bfmlalt v17.4s, v21.8h, v15.h[0]
bfmlalt v0.4s, v0.8h, v0.h[7]
bfcvtn v17.4h, v21.4s
bfcvtn v0.4h, v0.4s
bfcvtn2 v17.8h, v21.4s
bfcvtn2 v0.8h, v0.4s
bfcvt h17, s21
bfcvt h0, s0
|
tactcomplabs/xbgas-binutils-gdb
| 1,171
|
gas/testsuite/gas/aarch64/verbose-error.s
|
// verbose-error.s Test file for -mverbose-error
.text
strb w7, [x30, x0, lsl]
ubfm w0, x1, 8, 31
bfm w0, w1, 8, 43
strb w7, [x30, x0, lsl #1]
st2 {v4.2d,v5.2d},[x3,#3]
fmov v1.D[0],x0
ld1r {v1.4s, v2.4s, v3.4s}, [x3], x4
svc
add v0.4s, v1.4s, v2.2s
urecpe v0.1d,v7.1d
adds w0, wsp, x0, uxtx #1
fmov d0, s0
ldnp h3, h7, [sp], #16
# QL_V2SAME
suqadd v0.8b, v1.16b
# QL_V2SAME
ursqrte v2.8b, v3.8b
# QL_V2SAMEBH
rev32 v4.2s, v5.2s
#QL_V2SAMESD
frintn v6.8b, v7.8b
#QL_V2SAMEBHS
rev64 v8.2d, v9.2d
#QL_V2SAMEB
rev16 v10.2s, v11.2s
#QL_V2PAIRWISELONGBHS
saddlp v12.8b, v13.8b
#QL_V2LONGBHS
shll v14.8b, v15.8h, #1
#QL_V2LONGBHS2
shll2 v14.8b, v15.8h, #1
#QL_V2NARRS
fcvtxn v22.8b, v23.8b
#QL_V2NARRS2
fcvtxn2 v24.8b, v25.8b
#QL_V2NARRHS
fcvtn v25.4s, v26.4s
#QL_V2NARRHS2
fcvtn2 v27.4s, v28.4s
#QL_V2LONGHS
fcvtl v29.8b, v30.8b
#QL_V2LONGHS2
fcvtl2 v1.2d, v2.2d
#QL_V3SAME
sqadd v16.8b, v17.8h, v18.8h
#QL_V3SAMEBHS
shadd v19.8b, v20.8h, v21.8h
#QL_V3SAME4S
sha1su0 v1.16b, v2.16b, v3.16b
#QL_V3SAMEEB
shadd v1.2d, v2.2d, v3.2d
#QL_V3SAMEEHS
sqdmulh v1.16b, v2.16b, v3.16b
#QL_V3LONGHS2
sqdmlal2 v1.16b, v2.16b, v3.16b
|
tactcomplabs/xbgas-binutils-gdb
| 3,885
|
gas/testsuite/gas/aarch64/bitfield-bfm.s
|
/* bitfield-bfm.s Test file for AArch64 bitfield instructions
sbfm, bfm and ubfm mnemonics.
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, or
(at your option) any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
/* This file tests the GAS's ability in assembling sbfm, bfm and ubfm
instructions. Disassembler should use alias mnemonics to display
{[u|s]}bfm instructions. bitfield-bfm.s and bitfield-alias.s will be
assembled into idential binary, which is why the two tests share the
same dump match file 'bitfield-dump'. */
// <op> <Wd>, <Wn>
.macro bf_32r op
\op wzr, w7
.endm
// <op> <Xd>, <Wn>
.macro bf_64x op
\op xzr, w7
.endm
// <op> <Wd>, <Wn>, #<shift>
.macro bf_32s op, shift
\op wzr, w7, \shift
.endm
// <op> <Xd>, <Xn>, #<shift>
.macro bf_64s op, shift
\op xzr, x7, \shift
.endm
.macro op_bfm signed, reg, immr, imms
\signed\()bfm \reg\()zr, \reg\()7, #\immr, #\imms // e.g. sbfm xzr, x7, #0, #15
.endm
.macro ext2bfm signed, reg, imms
op_bfm signed=\signed, reg=\reg, immr=0, imms=\imms
.endm
// shift right -> bfm
.macro sr2bfm signed, reg, shift, imms
op_bfm signed=\signed, reg=\reg, immr=\shift, imms=\imms
.endm
// shift left -> bfm
.macro sl2bfm signed, reg, shift
.ifc \reg, w
op_bfm signed=\signed, reg=\reg, immr="((32-\shift)&31)", imms="(31-\shift)"
.else
op_bfm signed=\signed, reg=\reg, immr="((64-\shift)&63)", imms="(63-\shift)"
.endif
.endm
// bitfield insert -> bfm
.macro ins2bfm signed, reg, lsb, width
.ifc \reg, w
op_bfm signed=\signed, reg=\reg, immr="((32-\lsb)&31)", imms="(\width-1)"
.else
op_bfm signed=\signed, reg=\reg, immr="((64-\lsb)&63)", imms="(\width-1)"
.endif
.endm
// bitfield extract -> bfm
.macro x2bfm signed, reg, lsb, width
op_bfm signed=\signed, reg=\reg, immr=\lsb, imms="(\lsb+\width-1)"
.endm
.text
/*
* aliasing extend
*/
ext2bfm s, w, 7 // sxtb wzr, w7
ext2bfm s, x, 7 // sxtb xzr, x7
ext2bfm s, w, 15 // sxth wzr, w7
ext2bfm s, x, 15 // sxth xzr, x7
ext2bfm s, x, 31 // sxtw xzr, x7
ext2bfm u, w, 7 // uxtb wzr, w7
ext2bfm u, w, 7 // uxtb xzr, w7
ext2bfm u, w, 15 // uxth wzr, w7
ext2bfm u, w, 15 // uxth xzr, w7
orr wzr, wzr, w7 // uxtw wzr, w7
orr wzr, wzr, w7 // uxtw wzr, w7
/*
* aliasing shift
*/
.irp shift 0, 16, 31 // asr wzr, w7, #\shift
sr2bfm s, w, \shift, 31
.endr
.irp shift 0, 31, 63 // asr xzr, x7, #\shift
sr2bfm s, x, \shift, 63
.endr
.irp shift 0, 16, 31 // lsr wzr, w7, #\shift
sr2bfm u, w, \shift, 31
.endr
.irp shift 0, 31, 63 // lsr xzr, x7, #\shift
sr2bfm u, x, \shift, 63
.endr
.irp shift 0, 16, 31 // lsl wzr, w7, #\shift
sl2bfm u, w, \shift
.endr
.irp shift 0, 31, 63 // lsl xzr, x7, #\shift
sl2bfm u, x, \shift
.endr
/*
* aliasing insert and extract
*/
.irp signed, s, , u
.irp whichm, ins2bfm, x2bfm
\whichm \signed, w, 0, 1
\whichm \signed, w, 0, 16
\whichm \signed, w, 0, 32
\whichm \signed, w, 16, 1
\whichm \signed, w, 16, 8
\whichm \signed, w, 16, 16
\whichm \signed, w, 31, 1
\whichm \signed, x, 0, 1
\whichm \signed, x, 0, 32
\whichm \signed, x, 0, 64
\whichm \signed, x, 32, 1
\whichm \signed, x, 32, 16
\whichm \signed, x, 32, 32
\whichm \signed, x, 63, 1
.endr
.endr
|
tactcomplabs/xbgas-binutils-gdb
| 2,246
|
gas/testsuite/gas/aarch64/ldst-reg-unscaled-imm.s
|
/* ldst-reg-unscaled-imm.s Test file for AArch64
load-store reg. (unscaled imm.) instructions.
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, or
(at your option) any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
/* Prefetch memory instruction is not tested here.
Also note that a programmer-friendly disassembler could display
LDUR/STUR instructions using the standard LDR/STR mnemonics when
the encoded immediate is negative or unaligned. However this behaviour
is not required by the architectural assembly language. */
.macro op2_no_imm op, reg
\op \reg\()7, [sp]
.endm
.macro op2 op, reg, simm
\op \reg\()7, [sp, #\simm]
.endm
// load to or store from core register
.macro ld_or_st op, suffix, reg
.irp simm, -256, -171
op2 \op\suffix, \reg, \simm
.endr
op2_no_imm \op\suffix, \reg
.irp simm, 0, 2, 4, 8, 16, 85, 255
op2 \op\suffix, \reg, \simm
.endr
.endm
// load to or store from FP/SIMD register
.macro ld_or_st_v op
.irp reg, b, h, s, d, q
.irp simm, -256, -171
op2 \op, \reg, \simm
.endr
op2_no_imm \op, \reg
.irp simm, 0, 2, 4, 8, 16, 85, 255
op2 \op, \reg, \simm
.endr
.endr
.endm
func:
// load to or store from FP/SIMD register
ld_or_st_v stur
ld_or_st_v ldur
// load to or store from core register
// op, suffix, reg
ld_or_st stur, b, w
ld_or_st stur, h, w
ld_or_st stur, , w
ld_or_st stur, , x
ld_or_st ldur, b, w
ld_or_st ldur, h, w
ld_or_st ldur, , w
ld_or_st ldur, , x
ld_or_st ldur, sb, x
ld_or_st ldur, sh, x
ld_or_st ldur, sw, x
ld_or_st ldur, sb, w
ld_or_st ldur, sh, w
|
tactcomplabs/xbgas-binutils-gdb
| 2,579
|
gas/testsuite/gas/aarch64/ldst-reg-pair.s
|
/* ldst-reg-pair.s Test file for AArch64 load-store reg.pair instructions.
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, or
(at your option) any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
/* Includes:
* Load-store reg.pair (offset)
* Load-store reg.pair (post-ind.)
* Load-store reg.pair (pre-ind.)
* Load-store na.pair (pre-ind.)
*/
// offset format
.macro op3_offset op, reg, imm
\op \reg\()7, \reg\()15, [sp, #\imm]
.endm
// post-ind. format
.macro op3_post_ind op, reg, imm
\op \reg\()7, \reg\()15, [sp], #\imm
.endm
// pre-ind. format
.macro op3_pre_ind op, reg, imm
\op \reg\()7, \reg\()15, [sp, #\imm]!
.endm
.macro op3 op, reg, size, type
// a variety of values for the imm7 field
.irp imm7, -64, -31, -1, 0, 15, 63
// offset format
.ifc \type, 1
op3_offset \op, \reg, "(\imm7*\size)"
.endif
// post-ind. format
.ifc \type, 2
op3_post_ind \op, \reg, "(\imm7*\size)"
.endif
// pre-ind. format
.ifc \type, 3
op3_pre_ind \op, \reg, "(\imm7*\size)"
.endif
.endr
.endm
.macro ldst_reg_pair type
// op, reg, size(in byte) of one of the pair, type
op3 stp, w, 4, \type
op3 ldp, w, 4, \type
op3 ldpsw, x, 4, \type
op3 stp, x, 8, \type
op3 ldp, x, 8, \type
op3 stp, s, 4, \type
op3 ldp, s, 4, \type
op3 stp, d, 8, \type
op3 ldp, d, 8, \type
op3 stp, q, 16, \type
op3 ldp, q, 16, \type
.endm
.macro ldst_reg_na_pair type
// op, reg, size(in byte) of one of the pair, type
op3 stnp, w, 4, \type
op3 ldnp, w, 4, \type
op3 stnp, x, 8, \type
op3 ldnp, x, 8, \type
op3 stnp, s, 4, \type
op3 ldnp, s, 4, \type
op3 stnp, d, 8, \type
op3 ldnp, d, 8, \type
op3 stnp, q, 16, \type
op3 ldnp, q, 16, \type
.endm
func:
// Load-store reg.pair (offset)
ldst_reg_pair 1
// Load-store reg.pair (post-ind.)
ldst_reg_pair 2
// Load-store reg.pair (pre-ind.)
ldst_reg_pair 3
// Load-store na.pair (offset)
ldst_reg_na_pair 1
|
tactcomplabs/xbgas-binutils-gdb
| 1,704
|
gas/testsuite/gas/aarch64/sme-6-illegal.s
|
/* Scalable Matrix Extension (SME). */
st1b {za0h.b[w11, 0]}, p0, [x0]
st1h {za0h.h[w16, 0]}, p0, [x0]
st1h {za0v.h[w12, 0]}, p0, [x0, x0, lsl #3]
st1w {za3v.s[w15, 3]}, p7, [sp, lsl #2]
st1d {za0h.d[w12, 0]}, p0, [sp, x0, lsl #12]
st1q {za0v.q[w12]}, p0, [x0, x0, lsl #2]
st1b {za1h.b[w12, 0]}, p0, [x0]
st1b {za1v.b[w12, 0]}, p0, [sp]
st1b {za1h.b[w12, 0]}, p0, [sp, x0]
st1b {za0v.b[w15, 16]}, p7, [x17]
st1b {za0h.b[w15, 16]}, p7, [sp]
st1b {za0v.b[w15, 16]}, p7, [sp, x17]
st1h {za2v.h[w12, 0]}, p0, [x0]
st1h {za2h.h[w12, 0]}, p0, [sp]
st1h {za2v.h[w12, 0]}, p0, [x0, x0, lsl #1]
st1h {za2h.h[w12, 0]}, p0, [sp, x0, lsl #1]
st1h {za1v.h[w15, 8]}, p7, [x17]
st1h {za1h.h[w15, 8]}, p7, [sp]
st1h {za1v.h[w15, 8]}, p7, [x0, x17, lsl #1]
st1h {za1h.h[w15, 8]}, p7, [sp, x17, lsl #1]
st1w {za4h.s[w12, 0]}, p0, [x0]
st1w {za4v.s[w12, 0]}, p0, [sp]
st1w {za4h.s[w12, 0]}, p0, [x0, x0, lsl #2]
st1w {za4v.s[w12, 0]}, p0, [sp, x0, lsl #2]
st1w {za3h.s[w15, 4]}, p7, [x17]
st1w {za3v.s[w15, 4]}, p7, [sp]
st1w {za3h.s[w15, 4]}, p7, [x0, x17, lsl #2]
st1w {za3v.s[w15, 4]}, p7, [sp, x17, lsl #2]
st1d {za8v.d[w12, 0]}, p0, [x0]
st1d {za8h.d[w12, 0]}, p0, [sp]
st1d {za8v.d[w12, 0]}, p0, [x0, x0, lsl #3]
st1d {za8h.d[w12, 0]}, p0, [sp, x0, lsl #3]
st1d {za7v.d[w15, 2]}, p7, [x17]
st1d {za7h.d[w15, 2]}, p7, [sp]
st1d {za7v.d[w15, 2]}, p7, [x0, x17, lsl #3]
st1d {za7h.d[w15, 2]}, p7, [sp, x17, lsl #3]
st1q {za16v.q[w12]}, p0, [x0]
st1q {za16h.q[w12]}, p0, [sp]
st1q {za16v.q[w12]}, p0, [x0, x0, lsl #4]
st1q {za16h.q[w12]}, p0, [sp, x0, lsl #4]
st1q {za15v.q[w15, 1]}, p7, [x17]
st1q {za15h.q[w15, 1]}, p7, [sp]
st1q {za15v.q[w15, 1]}, p7, [x0, x17, lsl #4]
st1q {za15h.q[w15, 1]}, p7, [sp, x17, lsl #4]
|
tactcomplabs/xbgas-binutils-gdb
| 3,639
|
gas/testsuite/gas/aarch64/sve-add.s
|
add z0.b, z0.b, #-255
add z0.b, z0.b, #-129
add z0.b, z0.b, #-128
add z0.b, z0.b, #-127
add z0.b, z0.b, #-1
add z0.b, z0.b, #0
add z0.b, z0.b, #1
add z0.b, z0.b, #127
add z0.b, z0.b, #128
add z0.b, z0.b, #255
add z0.h, z0.h, #-65536
add z0.h, z0.h, #-65535
add z0.h, z0.h, #-65536 + 127
add z0.h, z0.h, #-65536 + 128
add z0.h, z0.h, #-65536 + 129
add z0.h, z0.h, #-65536 + 255
add z0.h, z0.h, #-65536 + 256
add z0.h, z0.h, #-32768 - 256
add z0.h, z0.h, #-32768
add z0.h, z0.h, #-32768 + 256
add z0.h, z0.h, #0
add z0.h, z0.h, #1
add z0.h, z0.h, #127
add z0.h, z0.h, #128
add z0.h, z0.h, #129
add z0.h, z0.h, #255
add z0.h, z0.h, #256
add z0.h, z0.h, #32768 - 256
add z0.h, z0.h, #32768
add z0.h, z0.h, #32768 + 256
add z0.h, z0.h, #65536 - 256
add z0.h, z0.h, #-255, lsl #8
add z0.h, z0.h, #-129, lsl #8
add z0.h, z0.h, #-128, lsl #8
add z0.h, z0.h, #-127, lsl #8
add z0.h, z0.h, #-1, lsl #8
add z0.h, z0.h, #0, lsl #8
add z0.h, z0.h, #1, lsl #8
add z0.h, z0.h, #127, lsl #8
add z0.h, z0.h, #128, lsl #8
add z0.h, z0.h, #255, lsl #8
add z0.s, z0.s, #0
add z0.s, z0.s, #1
add z0.s, z0.s, #127
add z0.s, z0.s, #128
add z0.s, z0.s, #129
add z0.s, z0.s, #255
add z0.s, z0.s, #256
add z0.s, z0.s, #0x7f00
add z0.s, z0.s, #0x8000
add z0.s, z0.s, #0xff00
add z0.s, z0.s, #0, lsl #8
add z0.s, z0.s, #1, lsl #8
add z0.s, z0.s, #127, lsl #8
add z0.s, z0.s, #128, lsl #8
add z0.s, z0.s, #255, lsl #8
add z0.d, z0.d, #0
add z0.d, z0.d, #1
add z0.d, z0.d, #127
add z0.d, z0.d, #128
add z0.d, z0.d, #129
add z0.d, z0.d, #255
add z0.d, z0.d, #256
add z0.d, z0.d, #0x7f00
add z0.d, z0.d, #0x8000
add z0.d, z0.d, #0xff00
add z0.d, z0.d, #0, lsl #8
add z0.d, z0.d, #1, lsl #8
add z0.d, z0.d, #127, lsl #8
add z0.d, z0.d, #128, lsl #8
add z0.d, z0.d, #255, lsl #8
sub z0.b, z0.b, #-255
sub z0.b, z0.b, #-129
sub z0.b, z0.b, #-128
sub z0.b, z0.b, #-127
sub z0.b, z0.b, #-1
sub z0.b, z0.b, #0
sub z0.b, z0.b, #1
sub z0.b, z0.b, #127
sub z0.b, z0.b, #128
sub z0.b, z0.b, #255
sub z0.h, z0.h, #-65536
sub z0.h, z0.h, #-65535
sub z0.h, z0.h, #-65536 + 127
sub z0.h, z0.h, #-65536 + 128
sub z0.h, z0.h, #-65536 + 129
sub z0.h, z0.h, #-65536 + 255
sub z0.h, z0.h, #-65536 + 256
sub z0.h, z0.h, #-32768 - 256
sub z0.h, z0.h, #-32768
sub z0.h, z0.h, #-32768 + 256
sub z0.h, z0.h, #0
sub z0.h, z0.h, #1
sub z0.h, z0.h, #127
sub z0.h, z0.h, #128
sub z0.h, z0.h, #129
sub z0.h, z0.h, #255
sub z0.h, z0.h, #256
sub z0.h, z0.h, #32768 - 256
sub z0.h, z0.h, #32768
sub z0.h, z0.h, #32768 + 256
sub z0.h, z0.h, #65536 - 256
sub z0.h, z0.h, #-255, lsl #8
sub z0.h, z0.h, #-129, lsl #8
sub z0.h, z0.h, #-128, lsl #8
sub z0.h, z0.h, #-127, lsl #8
sub z0.h, z0.h, #-1, lsl #8
sub z0.h, z0.h, #0, lsl #8
sub z0.h, z0.h, #1, lsl #8
sub z0.h, z0.h, #127, lsl #8
sub z0.h, z0.h, #128, lsl #8
sub z0.h, z0.h, #255, lsl #8
sub z0.s, z0.s, #0
sub z0.s, z0.s, #1
sub z0.s, z0.s, #127
sub z0.s, z0.s, #128
sub z0.s, z0.s, #129
sub z0.s, z0.s, #255
sub z0.s, z0.s, #256
sub z0.s, z0.s, #0x7f00
sub z0.s, z0.s, #0x8000
sub z0.s, z0.s, #0xff00
sub z0.s, z0.s, #0, lsl #8
sub z0.s, z0.s, #1, lsl #8
sub z0.s, z0.s, #127, lsl #8
sub z0.s, z0.s, #128, lsl #8
sub z0.s, z0.s, #255, lsl #8
sub z0.d, z0.d, #0
sub z0.d, z0.d, #1
sub z0.d, z0.d, #127
sub z0.d, z0.d, #128
sub z0.d, z0.d, #129
sub z0.d, z0.d, #255
sub z0.d, z0.d, #256
sub z0.d, z0.d, #0x7f00
sub z0.d, z0.d, #0x8000
sub z0.d, z0.d, #0xff00
sub z0.d, z0.d, #0, lsl #8
sub z0.d, z0.d, #1, lsl #8
sub z0.d, z0.d, #127, lsl #8
sub z0.d, z0.d, #128, lsl #8
sub z0.d, z0.d, #255, lsl #8
|
tactcomplabs/xbgas-binutils-gdb
| 2,433
|
gas/testsuite/gas/aarch64/bitfield-alias.s
|
/* bitfield-alias.s Test file for AArch64 bitfield instructions
alias mnemonics.
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, or
(at your option) any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
/* This file tests the GAS's ability in assembling the alias mnemonics
of sbfm, bfm and ubfm. Disassembler should prefer to use alias
mnemonics to display {[u|s]}bfm instructions.
bitfield-bfm.s and bitfield-alias.s will be assembled into idential
binary, which is why the two tests share the same dump match
file 'bitfield-dump'.
This assembly file is also used for the bitfield-no-aliases test. */
// <op> <Wd>, <Wn>
.macro bf_32r op
\op wzr, w7
.endm
// <op> <Xd>, <Wn>
.macro bf_64x op
\op xzr, w7
.endm
// <op> <Wd>, <Wn>, #<shift>
.macro bf_32s op, shift
\op wzr, w7, \shift
.endm
// <op> <Xd>, <Xn>, #<shift>
.macro bf_64s op, shift
\op xzr, x7, \shift
.endm
// <op> <Wd>, <Wn>, #<lsb>, #<width>
.macro bf_32 op, lsb, width
\op wzr, w7, #\lsb, #\width
.endm
// <op> <Xd>, <Xn>, #<lsb>, #<width>
.macro bf_64 op, lsb, width
\op xzr, x7, #\lsb, #\width
.endm
.text
/*
* extend
*/
bf_32r sxtb
bf_64x sxtb
bf_32r sxth
bf_64x sxth
bf_64x sxtw
bf_32r uxtb
bf_64x uxtb
bf_32r uxth
bf_64x uxth
bf_32r uxtw
bf_64x uxtw
/*
* shift
*/
.irp op, asr, lsr, lsl
.irp shift, 0, 16, 31
bf_32s \op, \shift
.endr
.irp shift, 0, 31, 63
bf_64s \op, \shift
.endr
.endr
/*
* Insert & Extract
*/
.irp op, sbfiz, sbfx, bfi, bfxil, ubfiz, ubfx
bf_32 \op, 0, 1
bf_32 \op, 0, 16
bf_32 \op, 0, 32
bf_32 \op, 16, 1
bf_32 \op, 16, 8
bf_32 \op, 16, 16
bf_32 \op, 31, 1
bf_64 \op, 0, 1
bf_64 \op, 0, 32
bf_64 \op, 0, 64
bf_64 \op, 32, 1
bf_64 \op, 32, 16
bf_64 \op, 32, 32
bf_64 \op, 63, 1
.endr
|
tactcomplabs/xbgas-binutils-gdb
| 6,813
|
gas/testsuite/gas/aarch64/etm.s
|
/* ETMv4 system registers. */
/* Read from system register. */
mrs x0, trcacatr0
mrs x0, trcacatr1
mrs x0, trcacatr2
mrs x0, trcacatr3
mrs x0, trcacatr4
mrs x0, trcacatr5
mrs x0, trcacatr6
mrs x0, trcacatr7
mrs x0, trcacatr8
mrs x0, trcacatr9
mrs x0, trcacatr10
mrs x0, trcacatr11
mrs x0, trcacatr12
mrs x0, trcacatr13
mrs x0, trcacatr14
mrs x0, trcacatr15
mrs x0, trcacvr0
mrs x0, trcacvr1
mrs x0, trcacvr2
mrs x0, trcacvr3
mrs x0, trcacvr4
mrs x0, trcacvr5
mrs x0, trcacvr6
mrs x0, trcacvr7
mrs x0, trcacvr8
mrs x0, trcacvr9
mrs x0, trcacvr10
mrs x0, trcacvr11
mrs x0, trcacvr12
mrs x0, trcacvr13
mrs x0, trcacvr14
mrs x0, trcacvr15
mrs x0, trcauxctlr
mrs x0, trcbbctlr
mrs x0, trcccctlr
mrs x0, trccidcctlr0
mrs x0, trccidcctlr1
mrs x0, trccidcvr0
mrs x0, trccidcvr1
mrs x0, trccidcvr2
mrs x0, trccidcvr3
mrs x0, trccidcvr4
mrs x0, trccidcvr5
mrs x0, trccidcvr6
mrs x0, trccidcvr7
mrs x0, trcclaimclr
mrs x0, trcclaimset
mrs x0, trccntctlr0
mrs x0, trccntctlr1
mrs x0, trccntctlr2
mrs x0, trccntctlr3
mrs x0, trccntrldvr0
mrs x0, trccntrldvr1
mrs x0, trccntrldvr2
mrs x0, trccntrldvr3
mrs x0, trccntvr0
mrs x0, trccntvr1
mrs x0, trccntvr2
mrs x0, trccntvr3
mrs x0, trcconfigr
mrs x0, trcdvcmr0
mrs x0, trcdvcmr1
mrs x0, trcdvcmr2
mrs x0, trcdvcmr3
mrs x0, trcdvcmr4
mrs x0, trcdvcmr5
mrs x0, trcdvcmr6
mrs x0, trcdvcmr7
mrs x0, trcdvcvr0
mrs x0, trcdvcvr1
mrs x0, trcdvcvr2
mrs x0, trcdvcvr3
mrs x0, trcdvcvr4
mrs x0, trcdvcvr5
mrs x0, trcdvcvr6
mrs x0, trcdvcvr7
mrs x0, trceventctl0r
mrs x0, trceventctl1r
mrs x0, trcextinselr0
mrs x0, trcextinselr
mrs x0, trcextinselr1
mrs x0, trcextinselr2
mrs x0, trcextinselr3
mrs x0, trcimspec0
mrs x0, trcimspec1
mrs x0, trcimspec2
mrs x0, trcimspec3
mrs x0, trcimspec4
mrs x0, trcimspec5
mrs x0, trcimspec6
mrs x0, trcimspec7
mrs x0, trcitctrl
mrs x0, trcpdcr
mrs x0, trcprgctlr
mrs x0, trcprocselr
mrs x0, trcqctlr
mrs x0, trcrsctlr2
mrs x0, trcrsctlr3
mrs x0, trcrsctlr4
mrs x0, trcrsctlr5
mrs x0, trcrsctlr6
mrs x0, trcrsctlr7
mrs x0, trcrsctlr8
mrs x0, trcrsctlr9
mrs x0, trcrsctlr10
mrs x0, trcrsctlr11
mrs x0, trcrsctlr12
mrs x0, trcrsctlr13
mrs x0, trcrsctlr14
mrs x0, trcrsctlr15
mrs x0, trcrsctlr16
mrs x0, trcrsctlr17
mrs x0, trcrsctlr18
mrs x0, trcrsctlr19
mrs x0, trcrsctlr20
mrs x0, trcrsctlr21
mrs x0, trcrsctlr22
mrs x0, trcrsctlr23
mrs x0, trcrsctlr24
mrs x0, trcrsctlr25
mrs x0, trcrsctlr26
mrs x0, trcrsctlr27
mrs x0, trcrsctlr28
mrs x0, trcrsctlr29
mrs x0, trcrsctlr30
mrs x0, trcrsctlr31
mrs x0, trcseqevr0
mrs x0, trcseqevr1
mrs x0, trcseqevr2
mrs x0, trcseqrstevr
mrs x0, trcseqstr
mrs x0, trcssccr0
mrs x0, trcssccr1
mrs x0, trcssccr2
mrs x0, trcssccr3
mrs x0, trcssccr4
mrs x0, trcssccr5
mrs x0, trcssccr6
mrs x0, trcssccr7
mrs x0, trcsscsr0
mrs x0, trcsscsr1
mrs x0, trcsscsr2
mrs x0, trcsscsr3
mrs x0, trcsscsr4
mrs x0, trcsscsr5
mrs x0, trcsscsr6
mrs x0, trcsscsr7
mrs x0, trcsspcicr0
mrs x0, trcsspcicr1
mrs x0, trcsspcicr2
mrs x0, trcsspcicr3
mrs x0, trcsspcicr4
mrs x0, trcsspcicr5
mrs x0, trcsspcicr6
mrs x0, trcsspcicr7
mrs x0, trcstallctlr
mrs x0, trcsyncpr
mrs x0, trctraceidr
mrs x0, trctsctlr
mrs x0, trcvdarcctlr
mrs x0, trcvdctlr
mrs x0, trcvdsacctlr
mrs x0, trcvictlr
mrs x0, trcviiectlr
mrs x0, trcvipcssctlr
mrs x0, trcvissctlr
mrs x0, trcvmidcctlr0
mrs x0, trcvmidcctlr1
mrs x0, trcvmidcvr0
mrs x0, trcvmidcvr1
mrs x0, trcvmidcvr2
mrs x0, trcvmidcvr3
mrs x0, trcvmidcvr4
mrs x0, trcvmidcvr5
mrs x0, trcvmidcvr6
mrs x0, trcvmidcvr7
/* Write to system register. */
msr trcacatr0, x0
msr trcacatr1, x0
msr trcacatr2, x0
msr trcacatr3, x0
msr trcacatr4, x0
msr trcacatr5, x0
msr trcacatr6, x0
msr trcacatr7, x0
msr trcacatr8, x0
msr trcacatr9, x0
msr trcacatr10, x0
msr trcacatr11, x0
msr trcacatr12, x0
msr trcacatr13, x0
msr trcacatr14, x0
msr trcacatr15, x0
msr trcacvr0, x0
msr trcacvr1, x0
msr trcacvr2, x0
msr trcacvr3, x0
msr trcacvr4, x0
msr trcacvr5, x0
msr trcacvr6, x0
msr trcacvr7, x0
msr trcacvr8, x0
msr trcacvr9, x0
msr trcacvr10, x0
msr trcacvr11, x0
msr trcacvr12, x0
msr trcacvr13, x0
msr trcacvr14, x0
msr trcacvr15, x0
msr trcauxctlr, x0
msr trcbbctlr, x0
msr trcccctlr, x0
msr trccidcctlr0, x0
msr trccidcctlr1, x0
msr trccidcvr0, x0
msr trccidcvr1, x0
msr trccidcvr2, x0
msr trccidcvr3, x0
msr trccidcvr4, x0
msr trccidcvr5, x0
msr trccidcvr6, x0
msr trccidcvr7, x0
msr trcclaimclr, x0
msr trcclaimset, x0
msr trccntctlr0, x0
msr trccntctlr1, x0
msr trccntctlr2, x0
msr trccntctlr3, x0
msr trccntrldvr0, x0
msr trccntrldvr1, x0
msr trccntrldvr2, x0
msr trccntrldvr3, x0
msr trccntvr0, x0
msr trccntvr1, x0
msr trccntvr2, x0
msr trccntvr3, x0
msr trcconfigr, x0
msr trcdvcmr0, x0
msr trcdvcmr1, x0
msr trcdvcmr2, x0
msr trcdvcmr3, x0
msr trcdvcmr4, x0
msr trcdvcmr5, x0
msr trcdvcmr6, x0
msr trcdvcmr7, x0
msr trcdvcvr0, x0
msr trcdvcvr1, x0
msr trcdvcvr2, x0
msr trcdvcvr3, x0
msr trcdvcvr4, x0
msr trcdvcvr5, x0
msr trcdvcvr6, x0
msr trcdvcvr7, x0
msr trceventctl0r, x0
msr trceventctl1r, x0
msr trcextinselr0, x0
msr trcextinselr, x0
msr trcextinselr1, x0
msr trcextinselr2, x0
msr trcextinselr3, x0
msr trcimspec0, x0
msr trcimspec1, x0
msr trcimspec2, x0
msr trcimspec3, x0
msr trcimspec4, x0
msr trcimspec5, x0
msr trcimspec6, x0
msr trcimspec7, x0
msr trcitctrl, x0
msr trcpdcr, x0
msr trcprgctlr, x0
msr trcprocselr, x0
msr trcqctlr, x0
msr trcrsctlr2, x0
msr trcrsctlr3, x0
msr trcrsctlr4, x0
msr trcrsctlr5, x0
msr trcrsctlr6, x0
msr trcrsctlr7, x0
msr trcrsctlr8, x0
msr trcrsctlr9, x0
msr trcrsctlr10, x0
msr trcrsctlr11, x0
msr trcrsctlr12, x0
msr trcrsctlr13, x0
msr trcrsctlr14, x0
msr trcrsctlr15, x0
msr trcrsctlr16, x0
msr trcrsctlr17, x0
msr trcrsctlr18, x0
msr trcrsctlr19, x0
msr trcrsctlr20, x0
msr trcrsctlr21, x0
msr trcrsctlr22, x0
msr trcrsctlr23, x0
msr trcrsctlr24, x0
msr trcrsctlr25, x0
msr trcrsctlr26, x0
msr trcrsctlr27, x0
msr trcrsctlr28, x0
msr trcrsctlr29, x0
msr trcrsctlr30, x0
msr trcrsctlr31, x0
msr trcseqevr0, x0
msr trcseqevr1, x0
msr trcseqevr2, x0
msr trcseqrstevr, x0
msr trcseqstr, x0
msr trcssccr0, x0
msr trcssccr1, x0
msr trcssccr2, x0
msr trcssccr3, x0
msr trcssccr4, x0
msr trcssccr5, x0
msr trcssccr6, x0
msr trcssccr7, x0
msr trcsscsr0, x0
msr trcsscsr1, x0
msr trcsscsr2, x0
msr trcsscsr3, x0
msr trcsscsr4, x0
msr trcsscsr5, x0
msr trcsscsr6, x0
msr trcsscsr7, x0
msr trcsspcicr0, x0
msr trcsspcicr1, x0
msr trcsspcicr2, x0
msr trcsspcicr3, x0
msr trcsspcicr4, x0
msr trcsspcicr5, x0
msr trcsspcicr6, x0
msr trcsspcicr7, x0
msr trcstallctlr, x0
msr trcsyncpr, x0
msr trctraceidr, x0
msr trctsctlr, x0
msr trcvdarcctlr, x0
msr trcvdctlr, x0
msr trcvdsacctlr, x0
msr trcvictlr, x0
msr trcviiectlr, x0
msr trcvipcssctlr, x0
msr trcvissctlr, x0
msr trcvmidcctlr0, x0
msr trcvmidcctlr1, x0
msr trcvmidcvr0, x0
msr trcvmidcvr1, x0
msr trcvmidcvr2, x0
msr trcvmidcvr3, x0
msr trcvmidcvr4, x0
msr trcvmidcvr5, x0
msr trcvmidcvr6, x0
msr trcvmidcvr7, x0
|
tactcomplabs/xbgas-binutils-gdb
| 1,061
|
gas/testsuite/gas/aarch64/undefined_by_elem_sz_l.s
|
# Generates tests to see if setting bit 22 (sz) and 21 (L) together correctly
# marks the instruction as undefined. This pattern can't be created by the
# assembler so instead manually encode it.
.macro gen_insns opc
.inst \opc
.inst (\opc | 0x600000)
.endm
# fmul s0, s0, v16.s[0]
gen_insns 0x5f909000
# fmla s0, s0, v16.s[0]
gen_insns 0x5f901000
# fmls s0, s0, v16.s[0]
gen_insns 0x5f905000
# fmulx s0, s0, v16.s[0]
gen_insns 0x7f909000
# fmul d0, d0, v16.d[0]
gen_insns 0x5fd09000
# fmla d0, d0, v16.d[0]
gen_insns 0x5fd01000
# fmls d0, d0, v16.d[0]
gen_insns 0x5fd05000
# fmulx d0, d0, v16.d[0]
gen_insns 0x7fd09000
# fmul v0.4s, v0.4s, v16.s[0]
gen_insns 0x4f909000
# fmla v0.4s, v0.4s, v16.s[0]
gen_insns 0x4f901000
# fmls v0.4s, v0.4s, v16.s[0]
gen_insns 0x4f905000
# fmulx v0.4s, v0.4s, v16.s[0]
gen_insns 0x6f909000
# fmul v0.2d, v0.2d, v16.d[0]
gen_insns 0x4fd09000
# fmla v0.2d, v0.2d, v16.d[0]
gen_insns 0x4fd01000
# fmls v0.2d, v0.2d, v16.d[0]
gen_insns 0x4fd05000
# fmulx v0.2d, v0.2d, v16.d[0]
gen_insns 0x6fd09000
|
tactcomplabs/xbgas-binutils-gdb
| 4,198
|
gas/testsuite/gas/aarch64/sve1-extended-sve2.s
|
/*
Those instructions from the sve2.s file that share mnemonics with
instructions in SVE.
Created with the below command
`grep -E '^(ext|ldnt1b|ldnt1d|ldnt1h|ldnt1w|mla|mls|mul|smulh|splice|sqadd|sqsub|stnt1b|stnt1d|stnt1h|stnt1w|tbl|umulh|uqadd|uqsub)\b' sve2.s`
This test file is here to ensure those instructions with shared mnemonics do
not work when assembled with only +sve enabled.
*/
ext z17.b, { z21.b, z22.b }, #221
ext z0.b, { z0.b, z1.b }, #0
ext z0.b, { z31.b, z0.b }, #0
ldnt1b { z17.d }, p5/z, [z21.d, x27]
ldnt1b { z0.d }, p0/z, [z0.d, x0]
ldnt1b { z0.d }, p0/z, [z0.d]
ldnt1b { z0.d }, p0/z, [z0.d, xzr]
ldnt1b { z17.s }, p5/z, [z21.s, x27]
ldnt1b { z0.s }, p0/z, [z0.s, x0]
ldnt1b { z0.s }, p0/z, [z0.s]
ldnt1b { z0.s }, p0/z, [z0.s, xzr]
ldnt1d { z17.d }, p5/z, [z21.d, x27]
ldnt1d { z0.d }, p0/z, [z0.d, x0]
ldnt1d { z0.d }, p0/z, [z0.d]
ldnt1d { z0.d }, p0/z, [z0.d, xzr]
ldnt1h { z17.d }, p5/z, [z21.d, x27]
ldnt1h { z0.d }, p0/z, [z0.d, x0]
ldnt1h { z0.d }, p0/z, [z0.d]
ldnt1h { z0.d }, p0/z, [z0.d, xzr]
ldnt1h { z17.s }, p5/z, [z21.s, x27]
ldnt1h { z0.s }, p0/z, [z0.s, x0]
ldnt1h { z0.s }, p0/z, [z0.s]
ldnt1h { z0.s }, p0/z, [z0.s, xzr]
ldnt1w { z17.s }, p5/z, [z21.s, x27]
ldnt1w { z0.s }, p0/z, [z0.s, x0]
ldnt1w { z0.s }, p0/z, [z0.s]
ldnt1w { z0.s }, p0/z, [z0.s, xzr]
ldnt1w { z17.d }, p5/z, [z21.d, x27]
ldnt1w { z0.d }, p0/z, [z0.d, x0]
ldnt1w { z0.d }, p0/z, [z0.d]
ldnt1w { z0.d }, p0/z, [z0.d, xzr]
mla z17.h, z21.h, z3.h[3]
mla z0.h, z0.h, z0.h[4]
mla z0.h, z0.h, z0.h[0]
mla z17.s, z21.s, z3.s[3]
mla z0.s, z0.s, z0.s[0]
mla z17.d, z21.d, z11.d[1]
mla z0.d, z0.d, z0.d[0]
mls z17.h, z21.h, z3.h[3]
mls z0.h, z0.h, z0.h[4]
mls z0.h, z0.h, z0.h[0]
mls z17.s, z21.s, z3.s[3]
mls z0.s, z0.s, z0.s[0]
mls z17.d, z21.d, z11.d[1]
mls z0.d, z0.d, z0.d[0]
mul z17.h, z21.h, z3.h[3]
mul z0.h, z0.h, z0.h[4]
mul z0.h, z0.h, z0.h[0]
mul z17.s, z21.s, z3.s[3]
mul z0.s, z0.s, z0.s[0]
mul z17.d, z21.d, z11.d[1]
mul z0.d, z0.d, z0.d[0]
mul z17.b, z21.b, z27.b
mul z0.b, z0.b, z0.b
mul z0.h, z0.h, z0.h
mul z0.s, z0.s, z0.s
mul z0.d, z0.d, z0.d
smulh z17.b, z21.b, z27.b
smulh z0.b, z0.b, z0.b
smulh z0.h, z0.h, z0.h
smulh z0.s, z0.s, z0.s
smulh z0.d, z0.d, z0.d
splice z17.b, p5, { z21.b, z22.b }
splice z0.b, p0, { z0.b, z1.b }
splice z0.h, p0, { z0.h, z1.h }
splice z0.s, p0, { z0.s, z1.s }
splice z0.d, p0, { z0.d, z1.d }
splice z0.b, p0, { z31.b, z0.b }
sqadd z17.b, p5/m, z17.b, z21.b
sqadd z0.b, p0/m, z0.b, z0.b
sqadd z0.h, p0/m, z0.h, z0.h
sqadd z0.s, p0/m, z0.s, z0.s
sqadd z0.d, p0/m, z0.d, z0.d
sqsub z17.b, p5/m, z17.b, z21.b
sqsub z0.b, p0/m, z0.b, z0.b
sqsub z0.h, p0/m, z0.h, z0.h
sqsub z0.s, p0/m, z0.s, z0.s
sqsub z0.d, p0/m, z0.d, z0.d
stnt1b { z17.s }, p5, [z21.s, x27]
stnt1b { z0.s }, p0, [z0.s, x0]
stnt1b { z0.s }, p0, [z0.s]
stnt1b { z0.s }, p0, [z0.s, xzr]
stnt1b { z17.d }, p5, [z21.d, x27]
stnt1b { z0.d }, p0, [z0.d, x0]
stnt1b { z0.d }, p0, [z0.d]
stnt1b { z0.d }, p0, [z0.d, xzr]
stnt1d { z17.d }, p5, [z21.d, x27]
stnt1d { z0.d }, p0, [z0.d, x0]
stnt1d { z0.d }, p0, [z0.d]
stnt1d { z0.d }, p0, [z0.d, xzr]
stnt1h { z17.s }, p5, [z21.s, x27]
stnt1h { z0.s }, p0, [z0.s, x0]
stnt1h { z0.s }, p0, [z0.s]
stnt1h { z0.s }, p0, [z0.s, xzr]
stnt1h { z17.d }, p5, [z21.d, x27]
stnt1h { z0.d }, p0, [z0.d, x0]
stnt1h { z0.d }, p0, [z0.d]
stnt1h { z0.d }, p0, [z0.d, xzr]
stnt1w { z17.s }, p5, [z21.s, x27]
stnt1w { z0.s }, p0, [z0.s, x0]
stnt1w { z0.s }, p0, [z0.s]
stnt1w { z0.s }, p0, [z0.s, xzr]
stnt1w { z17.d }, p5, [z21.d, x27]
stnt1w { z0.d }, p0, [z0.d, x0]
stnt1w { z0.d }, p0, [z0.d]
stnt1w { z0.d }, p0, [z0.d, xzr]
tbl z17.b, { z21.b, z22.b }, z27.b
tbl z0.b, { z0.b, z1.b }, z0.b
tbl z0.h, { z0.h, z1.h }, z0.h
tbl z0.s, { z0.s, z1.s }, z0.s
tbl z0.d, { z0.d, z1.d }, z0.d
tbl z0.b, { z31.b, z0.b }, z0.b
umulh z17.b, z21.b, z27.b
umulh z0.b, z0.b, z0.b
umulh z0.h, z0.h, z0.h
umulh z0.s, z0.s, z0.s
umulh z0.d, z0.d, z0.d
uqadd z17.b, p5/m, z17.b, z21.b
uqadd z0.b, p0/m, z0.b, z0.b
uqadd z0.h, p0/m, z0.h, z0.h
uqadd z0.s, p0/m, z0.s, z0.s
uqadd z0.d, p0/m, z0.d, z0.d
uqsub z17.b, p5/m, z17.b, z21.b
uqsub z0.b, p0/m, z0.b, z0.b
uqsub z0.h, p0/m, z0.h, z0.h
uqsub z0.s, p0/m, z0.s, z0.s
uqsub z0.d, p0/m, z0.d, z0.d
|
tactcomplabs/xbgas-binutils-gdb
| 1,378
|
gas/testsuite/gas/aarch64/sysreg-2.s
|
/* sysreg-2.s Test file for ARMv8.2 system registers. */
.macro rw_sys_reg sys_reg xreg r w
.ifc \w, 1
msr \sys_reg, \xreg
.endif
.ifc \r, 1
mrs \xreg, \sys_reg
.endif
.endm
.text
rw_sys_reg sys_reg=id_aa64mmfr1_el1 xreg=x5 r=1 w=0
rw_sys_reg sys_reg=id_aa64mmfr2_el1 xreg=x7 r=1 w=0
/* RAS extension. */
rw_sys_reg sys_reg=erridr_el1 xreg=x5 r=1 w=0
rw_sys_reg sys_reg=errselr_el1 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=erxfr_el1 xreg=x5 r=1 w=0
rw_sys_reg sys_reg=erxctlr_el1 xreg=x5 r=1 w=1
rw_sys_reg sys_reg=erxstatus_el1 xreg=x5 r=1 w=1
rw_sys_reg sys_reg=erxaddr_el1 xreg=x5 r=1 w=1
rw_sys_reg sys_reg=erxmisc0_el1 xreg=x5 r=1 w=1
rw_sys_reg sys_reg=erxmisc1_el1 xreg=x5 r=1 w=1
rw_sys_reg sys_reg=vsesr_el2 xreg=x5 r=1 w=0
rw_sys_reg sys_reg=disr_el1 xreg=x5 r=1 w=1
rw_sys_reg sys_reg=vdisr_el2 xreg=x5 r=1 w=0
/* DC CVAP. */
dc cvac, x0
dc cvau, x1
dc cvap, x2
/* AT. */
at s1e1rp, x0
at s1e1wp, x1
/* Statistical profiling. */
.irp reg, pmblimitr_el1, pmbptr_el1, pmbsr_el1
rw_sys_reg sys_reg=\reg xreg=x7 r=1 w=1
.endr
.irp reg, pmscr_el1, pmsicr_el1, pmsirr_el1, pmsfcr_el1
rw_sys_reg sys_reg=\reg xreg=x7 r=1 w=1
.endr
.irp reg, pmsevfr_el1, pmslatfr_el1, pmscr_el2, pmscr_el12
rw_sys_reg sys_reg=\reg xreg=x7 r=1 w=1
.endr
.irp reg, pmbidr_el1, pmsidr_el1
rw_sys_reg sys_reg=\reg xreg=x7 r=1 w=0
.endr
|
tactcomplabs/xbgas-binutils-gdb
| 1,947
|
gas/testsuite/gas/aarch64/armv8_5-a-memtag.s
|
func:
# OP x[0,30], x[0,30], x[0,30]
.macro expand_3_reg op
\op x0, x0, x0
\op x27, x0, x0
\op x0, x27, x0
\op x0, x0, x27
\op x27, x27, x27
.endm
# OP x[0,30], x[0,30], #[0,30], #[0,14]
.macro expand_2_reg op
\op x0, x0, #0, #0
\op x27, x0, #0, #0
\op x0, x27, #0, #0
\op x27, x27, #0, #0
.endm
.macro expand_stg op
\op x0, [x0, #0]
\op x0, [x27, #0]
\op sp, [x0, #0]
\op x27, [x0, #-80]
\op x0, [x0, #0]!
\op sp, [x0, #0]!
\op x27, [x0, #160]!
\op x0, [x0], #0
\op sp, [x0], #0
\op x27, [x0], #-1440
\op x0, [sp, #4080]
\op sp, [sp, #4080]
\op x27, [sp, #-4096]
\op x0, [sp, #4080]!
\op sp, [sp], #-4096
.endm
.macro expand_ldg_bulk op
\op x0, [x0]
\op x27, [x0]
\op x0, [x27]
\op x25, [x27]
\op x0, [sp]
\op xzr, [x0]
.endm
# IRG
expand_3_reg irg
irg sp, x0
irg x0, sp
# GMI
expand_3_reg gmi
gmi x0, sp, x0
gmi xzr, x0, x0
# ADDG
expand_2_reg addg
addg x0, sp, #0x3f0, #0xf
addg sp, x0, #0x2a0, #0xf
# SUBG
expand_2_reg subg
subg x0, sp, #0x3f0, #0xf
subg sp, x0, #0x3f0, #0x5
# SUBP
expand_3_reg subp
subp x0, sp, x0
subp x0, x0, sp
subp xzr, x0, x0
# SUBPS
expand_3_reg subps
subps x0, sp, x0
subps x0, x0, sp
subps xzr, x0, x0
# CMPP
cmpp x0, x0
cmpp x27, x0
cmpp x0, x27
cmpp x27, x27
cmpp sp, x0
cmpp x0, sp
expand_stg stg
expand_stg stzg
expand_stg st2g
expand_stg stz2g
stgp x0, x0, [x0, #0]
stgp x0, x27, [x0, #0]
stgp x27, x0, [x0, #0]
stgp x27, x27, [x0, #0]
stgp x0, x0, [x27, #0]
stgp x0, x0, [x0, #-80]
stgp x0, x0, [x0, #0]!
stgp x0, x0, [x0, #160]!
stgp x0, x0, [x0], #0
stgp x0, x0, [x0], #-144
stgp xzr, x0, [x0, #1008]
stgp x0, xzr, [x0, #-1024]
stgp x0, x0, [sp, #1008]!
stgp x0, x0, [sp], #-1024
ldg x0, [x0, #0]
ldg x27, [x0, #0]
ldg x0, [x27, #0]
ldg x27, [x27, #0]
ldg x0, [sp, #0]
ldg xzr, [x0, #0]
ldg x0, [x0, #4080]
ldg x0, [x0, #-4096]
expand_ldg_bulk stzgm
expand_ldg_bulk ldgm
expand_ldg_bulk stgm
|
tactcomplabs/xbgas-binutils-gdb
| 3,034
|
gas/testsuite/gas/aarch64/sme-illegal.s
|
/* Scalable Matrix Extension (SME). */
/* ADDHA 32-bit variant. */
addha za4.s, p0/m, p1/m, z1.s
addha za15.s, p2/m, p3/m, z2.s
addha za0.s, p2/m, p3/m, z2.d
/* ADDHA 64-bit variant. */
addha za8.d, p0/m, p1/m, z1.d
addha za15.d, p2/m, p3/m, z2.d
addha za0.d, p2/m, p3/m, z2.s
/* ADDVA 32-bit variant. */
addva za4.s, p0/m, p1/m, z1.s
addva za15.s, p2/m, p3/m, z2.s
addva za0.s, p2/m, p3/m, z2.d
/* ADDVA 64-bit variant. */
addva za8.d, p0/m, p1/m, z1.d
addva za15.d, p2/m, p3/m, z2.d
addva za0.d, p2/m, p3/m, z2.s
/* BFMOPA. */
bfmopa za4.s, p0/m, p1/m, z1.h, z4.h
bfmopa za0.s, p2/m, p3/m, z2.s, z3.s
/* BFMOPS. */
bfmops za4.s, p0/m, p1/m, z1.h, z4.h
bfmops za0.s, p2/m, p3/m, z2.s, z3.s
/* FMOPA (non-widening), single-precision. */
fmopa za4.s, p0/m, p1/m, z1.s, z4.s
fmopa za0.s, p6/m, p7/m, z4.d, z1.d
/* FMOPA (non-widening), double-precision. */
fmopa za8.d, p0/m, p1/m, z1.d, z8.d
fmopa za0.d, p2/m, p3/m, z2.s, z7.s
/* FMOPA (widening) */
fmopa za4.s, p0/m, p1/m, z1.h, z4.h
fmopa za1.s, p2/m, p3/m, z2.q, z3.q
/* FMOPS (non-widening), single-precision. */
fmops za4.s, p0/m, p1/m, z1.s, z4.s
fmops za1.s, p2/m, p3/m, z2.q, z3.q
/* FMOPS (non-widening), double-precision. */
fmops za8.d, p0/m, p1/m, z1.d, z8.d
fmops za0.d, p2/m, p3/m, z2.s, z7.s
/* FMOPS (widening) */
fmops za8.s, p0/m, p1/m, z1.h, z4.h
fmops za1.q, p2/m, p3/m, z2.h, z3.h
/* SMOPA 32-bit variant. */
smopa za4.s, p0/m, p1/m, z1.b, z4.b
smopa za1.q, p2/m, p3/m, z2.b, z3.b
/* SMOPA 64-bit variant. */
smopa za8.d, p0/m, p1/m, z1.h, z8.h
smopa za1.d, p2/m, p3/m, z2.h, z7.q
/* SMOPS 32-bit variant. */
smops za4.s, p0/m, p1/m, z1.b, z4.b
smops za1.q, p2/m, p3/m, z2.b, z3.b
/* SMOPS 64-bit variant. */
smops za8.d, p0/m, p1/m, z1.h, z8.h
smops za1.d, p2/m, p3/m, z2.h, z7.q
/* SUMOPA 32-bit variant. */
sumopa za4.s, p0/m, p1/m, z1.b, z4.b
sumopa za1.q, p2/m, p3/m, z2.s, z3.s
/* SUMOPA 64-bit variant. */
sumopa za8.d, p0/m, p1/m, z1.h, z8.h
sumopa za1.d, p2/m, p3/m, z2.h, z7.q
/* SUMOPS 32-bit variant. */
sumops za4.s, p0/m, p1/m, z1.b, z4.b
sumops za1.q, p2/m, p3/m, z2.b, z3.b
/* SUMOPS 64-bit variant. */
sumops za8.d, p0/m, p1/m, z1.h, z8.h
sumops za1.q, p2/m, p3/m, z2.h, z7.h
/* UMOPA 32-bit variant. */
umopa za4.s, p0/m, p1/m, z1.b, z4.b
umopa za1.q, p2/m, p3/m, z2.b, z3.b
/* UMOPA 64-bit variant. */
umopa za8.d, p0/m, p1/m, z1.h, z8.h
umopa za1.q, p2/m, p3/m, z2.h, z7.h
/* UMOPS 32-bit variant. */
umops za4.s, p0/m, p1/m, z1.b, z4.b
umops za1.q, p2/m, p3/m, z2.b, z3.b
/* UMOPS 64-bit variant. */
umops za8.d, p0/m, p1/m, z1.h, z8.h
umops za1.d, p2/m, p3/m, z2.d, z7.d
/* USMOPA 32-bit variant. */
usmopa za4.s, p0/m, p1/m, z1.b, z4.b
usmopa za1.q, p2/m, p3/m, z2.b, z3.b
/* USMOPA 64-bit variant. */
usmopa za8.d, p0/m, p1/m, z1.h, z8.h
usmopa za1.q, p2/m, p3/m, z2.h, z7.h
/* USMOPS 32-bit variant. */
usmops za4.s, p0/m, p1/m, z1.b, z4.b
usmops za1.s, p2/m, p3/m, z2.s, z3.b
/* USMOPS 64-bit variant. */
usmops za8.d, p0/m, p1/m, z1.h, z8.h
usmops za1.d, p2/m, p3/m, z2.d, z7.d
|
tactcomplabs/xbgas-binutils-gdb
| 5,190
|
gas/testsuite/gas/aarch64/addsub.s
|
/* addsub.s Test file for AArch64 add-subtract instructions.
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, or
(at your option) any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
// TODO: also cover the addsub_imm instructions.
/*
* Adjust Rm
*/
.macro adjust_rm op, rd, rn, rm_r, rm_n, extend, amount
// for 64-bit instruction, Rm is Xm when <extend> is explicitely
// or implicitly UXTX, SXTX or LSL; otherwise it Wm.
.ifc \rm_r, X
.ifnc \extend, UXTX
.ifnc \extend, SXTX
.ifnc \extend, LSL
.ifb \amount
\op \rd, \rn, W\()\rm_n, \extend
.else
\op \rd, \rn, W\()\rm_n, \extend #\amount
.endif
.exitm
.endif
.endif
.endif
.endif
.ifb \amount
\op \rd, \rn, \rm_r\()\rm_n, \extend
.else
\op \rd, \rn, \rm_r\()\rm_n, \extend #\amount
.endif
.endm
/*
* Emitting addsub_ext instruction
*/
.macro do_addsub_ext type, op, Rn, reg, extend, amount
.ifc \type, 0
// normal add/adds/sub/subs
.ifb \extend
\op \reg\()16, \Rn, \reg\()1
.else
.ifb \amount
adjust_rm \op, \reg\()16, \Rn, \reg, 1, \extend
.else
adjust_rm \op, \reg\()16, \Rn, \reg, 1, \extend, \amount
.endif
.endif
.else
.ifc \type, 1
// adds/subs with ZR as Rd
.ifb \extend
\op \reg\()ZR, \Rn, \reg\()1
.else
.ifb \amount
adjust_rm \op, \reg\()ZR, \Rn, \reg, 1, \extend
.else
adjust_rm \op, \reg\()ZR, \Rn, \reg, 1, \extend, \amount
.endif
.endif
.else
// cmn/cmp
.ifb \extend
\op \Rn, \reg\()1
.else
.ifb \amount
\op \Rn, \reg\()1, \extend
.else
\op \Rn, \reg\()1, \extend #\amount
.endif
.endif
.endif
.endif
.endm
/*
* Optional extension and optional shift amount
*/
.macro do_extend type, op, Rn, reg
// <extend> absent
// note that when SP is not used, the GAS will encode it as addsub_shift
do_addsub_ext \type, \op, \Rn, \reg
// optional absent <amount>
.irp extend, UXTB, UXTH, UXTW, UXTX, SXTB, SXTH, SXTW, SXTX
.irp amount, , 0, 1, 2, 3, 4
do_addsub_ext \type, \op, \Rn, \reg, \extend, \amount
.endr
.endr
// when <extend> is LSL, <amount> cannot be absent
// note that when SP is not used, the GAS will encode it as addsub_shift
.irp amount, 0, 1, 2, 3, 4
do_addsub_ext \type, \op, \Rn, \reg, LSL, \amount
.endr
.endm
/*
* Leaf macro emitting addsub_shift instruction
*/
.macro do_addsub_shift type, op, R, reg, shift, amount
.ifc \type, 0
// normal add/adds/sub/subs
.ifb \shift
\op \reg\()16, \R, \reg\()1
.else
\op \reg\()16, \R, \reg\()1, \shift #\amount
.endif
.else
.ifc \type, 1
// adds/subs with ZR as Rd
.ifb \shift
\op \reg\()ZR, \R, \reg\()1
.else
\op \reg\()ZR, \R, \reg\()1, \shift #\amount
.endif
.else
.ifc \type, 2
// cmn/cmp/neg/negs
.ifb \shift
\op \R, \reg\()1
.else
\op \R, \reg\()1, \shift #\amount
.endif
.else
// sub/subs with ZR as Rn
.ifb \shift
\op \R, \reg\()ZR, \reg\()1
.else
\op \R, \reg\()ZR, \reg\()1, \shift #\amount
.endif
.endif
.endif
.endif
.endm
/*
* Optional shift and optional shift amount
*/
.macro do_shift type, op, R, reg
// <shift> absent
do_addsub_shift \type, \op, \R, \reg
// optional absent <amount>
.irp shift, LSL, LSR, ASR
.irp amount, 0, 1, 2, 3, 4, 5, 16, 31
// amount cannot be absent when shift is present.
do_addsub_shift \type, \op, \R, \reg, \shift, \amount
.endr
.ifc \reg, X
do_addsub_shift \type, \op, \R, \reg, \shift, 63
.endif
.endr
.endm
func:
/*
* Add-subtract (extended register)
*/
.irp op, ADD, ADDS, SUB, SUBS
do_extend 0, \op, W7, W
do_extend 0, \op, WSP, W
do_extend 0, \op, X7, X
do_extend 0, \op, SP, X
.endr
.irp op, ADDS, SUBS
do_extend 1, \op, W7, W
do_extend 1, \op, WSP, W
do_extend 1, \op, X7, X
do_extend 1, \op, SP, X
.endr
.irp op, CMN, CMP
do_extend 2, \op, W7, W
do_extend 2, \op, WSP, W
do_extend 2, \op, X7, X
do_extend 2, \op, SP, X
.endr
/*
* Add-subtract (shift register)
*/
.irp op, ADD, ADDS, SUB, SUBS
do_shift 0, \op, W7, W
do_shift 0, \op, X7, X
.endr
.irp op, ADDS, SUBS
do_shift 1, \op, W7, W
do_shift 1, \op, X7, X
.endr
.irp op, CMN, CMP
do_shift 2, \op, W7, W
do_shift 2, \op, X7, X
.endr
.irp op, SUB, SUBS
do_shift 3, \op, W7, W
do_shift 3, \op, X7, X
.endr
.irp op, NEG, NEGS
do_shift 2, \op, W7, W
do_shift 2, \op, X7, X
.endr
/*
* Check for correct aliasing
*/
.irp op, NEGS
do_shift 2, \op, WZR, W
do_shift 2, \op, XZR, X
.endr
.irp op, SUBS
do_shift 3, \op, W7, W
do_shift 3, \op, X7, X
do_shift 0, \op, WZR, W
do_shift 0, \op, XZR, X
.endr
|
tactcomplabs/xbgas-binutils-gdb
| 2,279
|
gas/testsuite/gas/aarch64/brbe.s
|
/* Branch Record Buffer Extension system registers. */
/* Read from BRBE system registers. */
mrs x0, brbcr_el1
mrs x0, brbcr_el12
mrs x0, brbfcr_el1
mrs x0, brbts_el1
mrs x0, brbinfinj_el1
mrs x0, brbsrcinj_el1
mrs x0, brbtgtinj_el1
mrs x0, brbidr0_el1
mrs x0, brbcr_el2
mrs x0, brbsrc0_el1
mrs x0, brbsrc10_el1
mrs x0, brbsrc11_el1
mrs x0, brbsrc12_el1
mrs x0, brbsrc13_el1
mrs x0, brbsrc14_el1
mrs x0, brbsrc15_el1
mrs x0, brbsrc16_el1
mrs x0, brbsrc17_el1
mrs x0, brbsrc18_el1
mrs x0, brbsrc19_el1
mrs x0, brbsrc20_el1
mrs x0, brbsrc21_el1
mrs x0, brbsrc22_el1
mrs x0, brbsrc23_el1
mrs x0, brbsrc24_el1
mrs x0, brbsrc25_el1
mrs x0, brbsrc26_el1
mrs x0, brbsrc27_el1
mrs x0, brbsrc28_el1
mrs x0, brbsrc29_el1
mrs x0, brbsrc30_el1
mrs x0, brbsrc31_el1
mrs x0, brbtgt0_el1
mrs x0, brbtgt1_el1
mrs x0, brbtgt2_el1
mrs x0, brbtgt3_el1
mrs x0, brbtgt4_el1
mrs x0, brbtgt5_el1
mrs x0, brbtgt6_el1
mrs x0, brbtgt7_el1
mrs x0, brbtgt8_el1
mrs x0, brbtgt9_el1
mrs x0, brbtgt10_el1
mrs x0, brbtgt11_el1
mrs x0, brbtgt12_el1
mrs x0, brbtgt13_el1
mrs x0, brbtgt14_el1
mrs x0, brbtgt15_el1
mrs x0, brbtgt16_el1
mrs x0, brbtgt17_el1
mrs x0, brbtgt18_el1
mrs x0, brbtgt19_el1
mrs x0, brbtgt20_el1
mrs x0, brbtgt21_el1
mrs x0, brbtgt22_el1
mrs x0, brbtgt23_el1
mrs x0, brbtgt24_el1
mrs x0, brbtgt25_el1
mrs x0, brbtgt26_el1
mrs x0, brbtgt27_el1
mrs x0, brbtgt28_el1
mrs x0, brbtgt29_el1
mrs x0, brbtgt30_el1
mrs x0, brbtgt31_el1
mrs x0, brbinf0_el1
mrs x0, brbinf1_el1
mrs x0, brbinf2_el1
mrs x0, brbinf3_el1
mrs x0, brbinf4_el1
mrs x0, brbinf5_el1
mrs x0, brbinf6_el1
mrs x0, brbinf7_el1
mrs x0, brbinf8_el1
mrs x0, brbinf9_el1
mrs x0, brbinf10_el1
mrs x0, brbinf11_el1
mrs x0, brbinf12_el1
mrs x0, brbinf13_el1
mrs x0, brbinf14_el1
mrs x0, brbinf15_el1
mrs x0, brbinf16_el1
mrs x0, brbinf17_el1
mrs x0, brbinf18_el1
mrs x0, brbinf19_el1
mrs x0, brbinf20_el1
mrs x0, brbinf21_el1
mrs x0, brbinf22_el1
mrs x0, brbinf23_el1
mrs x0, brbinf24_el1
mrs x0, brbinf25_el1
mrs x0, brbinf26_el1
mrs x0, brbinf27_el1
mrs x0, brbinf28_el1
mrs x0, brbinf29_el1
mrs x0, brbinf30_el1
mrs x0, brbinf31_el1
/* Write to BRBE system registers. */
msr brbcr_el1, x0
msr brbcr_el12, x0
msr brbfcr_el1, x0
msr brbts_el1, x0
msr brbinfinj_el1, x0
msr brbsrcinj_el1, x0
msr brbtgtinj_el1, x0
msr brbcr_el2, x0
|
tactcomplabs/xbgas-binutils-gdb
| 1,280,904
|
gas/testsuite/gas/aarch64/sve.s
|
.equ z0, 1
.equ z0.b, 1
.equ z0.h, 1
.equ z0.s, 1
.equ z0.d, 1
.equ p0, 1
.equ p0.b, 1
.equ p0.h, 1
.equ p0.s, 1
.equ p0.d, 1
.equ b0, 1
.equ h0, 1
.equ s0, 1
.equ d0, 1
.equ w0, 1
.equ x0, 1
fmov z0.h, #2.0000000000
FMOV Z0.H, #2.0000000000
fmov z1.h, #2.0000000000
FMOV Z1.H, #2.0000000000
fmov z31.h, #2.0000000000
FMOV Z31.H, #2.0000000000
fmov z0.h, #16.0000000000
FMOV Z0.H, #16.0000000000
fmov z0.h, #0.1875000000
FMOV Z0.H, #0.1875000000
fmov z0.h, #1.9375000000
FMOV Z0.H, #1.9375000000
fmov z0.h, #-3.0000000000
FMOV Z0.H, #-3.0000000000
fmov z0.h, #-0.1250000000
FMOV Z0.H, #-0.1250000000
fmov z0.h, #-1.9375000000
FMOV Z0.H, #-1.9375000000
fmov z0.s, #2.0000000000
FMOV Z0.S, #2.0000000000
fmov z1.s, #2.0000000000
FMOV Z1.S, #2.0000000000
fmov z31.s, #2.0000000000
FMOV Z31.S, #2.0000000000
fmov z0.s, #16.0000000000
FMOV Z0.S, #16.0000000000
fmov z0.s, #0.1875000000
FMOV Z0.S, #0.1875000000
fmov z0.s, #1.9375000000
FMOV Z0.S, #1.9375000000
fmov z0.s, #-3.0000000000
FMOV Z0.S, #-3.0000000000
fmov z0.s, #-0.1250000000
FMOV Z0.S, #-0.1250000000
fmov z0.s, #-1.9375000000
FMOV Z0.S, #-1.9375000000
fmov z0.d, #2.0000000000
FMOV Z0.D, #2.0000000000
fmov z1.d, #2.0000000000
FMOV Z1.D, #2.0000000000
fmov z31.d, #2.0000000000
FMOV Z31.D, #2.0000000000
fmov z0.d, #16.0000000000
FMOV Z0.D, #16.0000000000
fmov z0.d, #0.1875000000
FMOV Z0.D, #0.1875000000
fmov z0.d, #1.9375000000
FMOV Z0.D, #1.9375000000
fmov z0.d, #-3.0000000000
FMOV Z0.D, #-3.0000000000
fmov z0.d, #-0.1250000000
FMOV Z0.D, #-0.1250000000
fmov z0.d, #-1.9375000000
FMOV Z0.D, #-1.9375000000
fmov z0.h, p0/m, #2.0000000000
FMOV Z0.H, P0/M, #2.0000000000
fmov z1.h, p0/m, #2.0000000000
FMOV Z1.H, P0/M, #2.0000000000
fmov z31.h, p0/m, #2.0000000000
FMOV Z31.H, P0/M, #2.0000000000
fmov z0.h, p2/m, #2.0000000000
FMOV Z0.H, P2/M, #2.0000000000
fmov z0.h, p15/m, #2.0000000000
FMOV Z0.H, P15/M, #2.0000000000
fmov z0.h, p0/m, #16.0000000000
FMOV Z0.H, P0/M, #16.0000000000
fmov z0.h, p0/m, #0.1875000000
FMOV Z0.H, P0/M, #0.1875000000
fmov z0.h, p0/m, #1.9375000000
FMOV Z0.H, P0/M, #1.9375000000
fmov z0.h, p0/m, #-3.0000000000
FMOV Z0.H, P0/M, #-3.0000000000
fmov z0.h, p0/m, #-0.1250000000
FMOV Z0.H, P0/M, #-0.1250000000
fmov z0.h, p0/m, #-1.9375000000
FMOV Z0.H, P0/M, #-1.9375000000
fmov z0.s, p0/m, #2.0000000000
FMOV Z0.S, P0/M, #2.0000000000
fmov z1.s, p0/m, #2.0000000000
FMOV Z1.S, P0/M, #2.0000000000
fmov z31.s, p0/m, #2.0000000000
FMOV Z31.S, P0/M, #2.0000000000
fmov z0.s, p2/m, #2.0000000000
FMOV Z0.S, P2/M, #2.0000000000
fmov z0.s, p15/m, #2.0000000000
FMOV Z0.S, P15/M, #2.0000000000
fmov z0.s, p0/m, #16.0000000000
FMOV Z0.S, P0/M, #16.0000000000
fmov z0.s, p0/m, #0.1875000000
FMOV Z0.S, P0/M, #0.1875000000
fmov z0.s, p0/m, #1.9375000000
FMOV Z0.S, P0/M, #1.9375000000
fmov z0.s, p0/m, #-3.0000000000
FMOV Z0.S, P0/M, #-3.0000000000
fmov z0.s, p0/m, #-0.1250000000
FMOV Z0.S, P0/M, #-0.1250000000
fmov z0.s, p0/m, #-1.9375000000
FMOV Z0.S, P0/M, #-1.9375000000
fmov z0.d, p0/m, #2.0000000000
FMOV Z0.D, P0/M, #2.0000000000
fmov z1.d, p0/m, #2.0000000000
FMOV Z1.D, P0/M, #2.0000000000
fmov z31.d, p0/m, #2.0000000000
FMOV Z31.D, P0/M, #2.0000000000
fmov z0.d, p2/m, #2.0000000000
FMOV Z0.D, P2/M, #2.0000000000
fmov z0.d, p15/m, #2.0000000000
FMOV Z0.D, P15/M, #2.0000000000
fmov z0.d, p0/m, #16.0000000000
FMOV Z0.D, P0/M, #16.0000000000
fmov z0.d, p0/m, #0.1875000000
FMOV Z0.D, P0/M, #0.1875000000
fmov z0.d, p0/m, #1.9375000000
FMOV Z0.D, P0/M, #1.9375000000
fmov z0.d, p0/m, #-3.0000000000
FMOV Z0.D, P0/M, #-3.0000000000
fmov z0.d, p0/m, #-0.1250000000
FMOV Z0.D, P0/M, #-0.1250000000
fmov z0.d, p0/m, #-1.9375000000
FMOV Z0.D, P0/M, #-1.9375000000
mov z0.d, z0.d
MOV Z0.D, Z0.D
mov z1.d, z0.d
MOV Z1.D, Z0.D
mov z31.d, z0.d
MOV Z31.D, Z0.D
mov z0.d, z2.d
MOV Z0.D, Z2.D
mov z0.d, z31.d
MOV Z0.D, Z31.D
mov z0.b, b0
MOV Z0.B, B0
mov z1.b, b0
MOV Z1.B, B0
mov z31.b, b0
MOV Z31.B, B0
mov z0.b, b2
MOV Z0.B, B2
mov z0.b, b31
MOV Z0.B, B31
mov z0.h, h0
MOV Z0.H, H0
mov z1.h, h0
MOV Z1.H, H0
mov z31.h, h0
MOV Z31.H, H0
mov z0.h, h2
MOV Z0.H, H2
mov z0.h, h31
MOV Z0.H, H31
mov z0.s, s0
MOV Z0.S, S0
mov z1.s, s0
MOV Z1.S, S0
mov z31.s, s0
MOV Z31.S, S0
mov z0.s, s2
MOV Z0.S, S2
mov z0.s, s31
MOV Z0.S, S31
mov z0.d, d0
MOV Z0.D, D0
mov z1.d, d0
MOV Z1.D, D0
mov z31.d, d0
MOV Z31.D, D0
mov z0.d, d2
MOV Z0.D, D2
mov z0.d, d31
MOV Z0.D, D31
mov z0.q, q0
mov z0.Q, Q0
mov z1.q, q0
mov z1.Q, Q0
mov z31.q, q0
mov z31.Q, Q0
mov z0.q, q2
mov z0.Q, Q2
mov z0.q, q31
mov z0.Q, Q31
mov z0.b, w0
MOV Z0.B, W0
mov z1.b, w0
MOV Z1.B, W0
mov z31.b, w0
MOV Z31.B, W0
mov z0.b, w2
MOV Z0.B, W2
mov z0.b, wsp
MOV Z0.B, WSP
mov z0.h, w0
MOV Z0.H, W0
mov z1.h, w0
MOV Z1.H, W0
mov z31.h, w0
MOV Z31.H, W0
mov z0.h, w2
MOV Z0.H, W2
mov z0.h, wsp
MOV Z0.H, WSP
mov z0.s, w0
MOV Z0.S, W0
mov z1.s, w0
MOV Z1.S, W0
mov z31.s, w0
MOV Z31.S, W0
mov z0.s, w2
MOV Z0.S, W2
mov z0.s, wsp
MOV Z0.S, WSP
mov z0.d, x0
MOV Z0.D, X0
mov z1.d, x0
MOV Z1.D, X0
mov z31.d, x0
MOV Z31.D, X0
mov z0.d, x2
MOV Z0.D, X2
mov z0.d, sp
MOV Z0.D, SP
mov p0.b, p0.b
MOV P0.B, P0.B
mov p1.b, p0.b
MOV P1.B, P0.B
mov p15.b, p0.b
MOV P15.B, P0.B
mov p0.b, p2.b
MOV P0.B, P2.B
mov p0.b, p15.b
MOV P0.B, P15.B
mov z0.b, z0.b[1]
MOV Z0.B, Z0.B[1]
mov z1.b, z0.b[1]
MOV Z1.B, Z0.B[1]
mov z31.b, z0.b[1]
MOV Z31.B, Z0.B[1]
mov z0.b, z2.b[1]
MOV Z0.B, Z2.B[1]
mov z0.b, z31.b[1]
MOV Z0.B, Z31.B[1]
mov z0.b, z0.b[2]
MOV Z0.B, Z0.B[2]
mov z0.b, z0.b[62]
MOV Z0.B, Z0.B[62]
mov z0.b, z0.b[63]
MOV Z0.B, Z0.B[63]
mov z1.b, z0.b[2]
MOV Z1.B, Z0.B[2]
mov z31.b, z0.b[2]
MOV Z31.B, Z0.B[2]
mov z0.b, z2.b[2]
MOV Z0.B, Z2.B[2]
mov z0.b, z31.b[2]
MOV Z0.B, Z31.B[2]
mov z0.b, z0.b[3]
MOV Z0.B, Z0.B[3]
mov z0.h, z0.h[1]
MOV Z0.H, Z0.H[1]
mov z1.h, z0.h[1]
MOV Z1.H, Z0.H[1]
mov z31.h, z0.h[1]
MOV Z31.H, Z0.H[1]
mov z0.h, z2.h[1]
MOV Z0.H, Z2.H[1]
mov z0.h, z31.h[1]
MOV Z0.H, Z31.H[1]
mov z0.h, z0.h[2]
MOV Z0.H, Z0.H[2]
mov z0.h, z0.h[30]
MOV Z0.H, Z0.H[30]
mov z0.h, z0.h[31]
MOV Z0.H, Z0.H[31]
mov z1.b, z0.b[3]
MOV Z1.B, Z0.B[3]
mov z31.b, z0.b[3]
MOV Z31.B, Z0.B[3]
mov z0.b, z2.b[3]
MOV Z0.B, Z2.B[3]
mov z0.b, z31.b[3]
MOV Z0.B, Z31.B[3]
mov z0.b, z0.b[4]
MOV Z0.B, Z0.B[4]
mov z1.b, z0.b[4]
MOV Z1.B, Z0.B[4]
mov z31.b, z0.b[4]
MOV Z31.B, Z0.B[4]
mov z0.b, z2.b[4]
MOV Z0.B, Z2.B[4]
mov z0.b, z31.b[4]
MOV Z0.B, Z31.B[4]
mov z0.b, z0.b[5]
MOV Z0.B, Z0.B[5]
mov z1.h, z0.h[2]
MOV Z1.H, Z0.H[2]
mov z31.h, z0.h[2]
MOV Z31.H, Z0.H[2]
mov z0.h, z2.h[2]
MOV Z0.H, Z2.H[2]
mov z0.h, z31.h[2]
MOV Z0.H, Z31.H[2]
mov z0.h, z0.h[3]
MOV Z0.H, Z0.H[3]
mov z1.b, z0.b[5]
MOV Z1.B, Z0.B[5]
mov z31.b, z0.b[5]
MOV Z31.B, Z0.B[5]
mov z0.b, z2.b[5]
MOV Z0.B, Z2.B[5]
mov z0.b, z31.b[5]
MOV Z0.B, Z31.B[5]
mov z0.b, z0.b[6]
MOV Z0.B, Z0.B[6]
mov z0.s, z0.s[1]
MOV Z0.S, Z0.S[1]
mov z1.s, z0.s[1]
MOV Z1.S, Z0.S[1]
mov z31.s, z0.s[1]
MOV Z31.S, Z0.S[1]
mov z0.s, z2.s[1]
MOV Z0.S, Z2.S[1]
mov z0.s, z31.s[1]
MOV Z0.S, Z31.S[1]
mov z0.s, z0.s[2]
MOV Z0.S, Z0.S[2]
mov z0.s, z0.s[14]
MOV Z0.S, Z0.S[14]
mov z0.s, z0.s[15]
MOV Z0.S, Z0.S[15]
mov z1.b, z0.b[6]
MOV Z1.B, Z0.B[6]
mov z31.b, z0.b[6]
MOV Z31.B, Z0.B[6]
mov z0.b, z2.b[6]
MOV Z0.B, Z2.B[6]
mov z0.b, z31.b[6]
MOV Z0.B, Z31.B[6]
mov z0.b, z0.b[7]
MOV Z0.B, Z0.B[7]
mov z1.h, z0.h[3]
MOV Z1.H, Z0.H[3]
mov z31.h, z0.h[3]
MOV Z31.H, Z0.H[3]
mov z0.h, z2.h[3]
MOV Z0.H, Z2.H[3]
mov z0.h, z31.h[3]
MOV Z0.H, Z31.H[3]
mov z0.h, z0.h[4]
MOV Z0.H, Z0.H[4]
mov z1.b, z0.b[7]
MOV Z1.B, Z0.B[7]
mov z31.b, z0.b[7]
MOV Z31.B, Z0.B[7]
mov z0.b, z2.b[7]
MOV Z0.B, Z2.B[7]
mov z0.b, z31.b[7]
MOV Z0.B, Z31.B[7]
mov z0.b, z0.b[8]
MOV Z0.B, Z0.B[8]
mov z0.q, z0.q[1]
MOV Z0.Q, Z0.Q[1]
mov z1.q, z0.q[1]
MOV Z1.Q, Z0.Q[1]
mov z31.q, z0.q[1]
MOV Z31.Q, Z0.Q[1]
mov z0.q, z2.q[1]
MOV Z0.Q, Z2.Q[1]
mov z0.q, z31.q[1]
MOV Z0.Q, Z31.Q[1]
mov z0.q, z0.q[0]
MOV Z0.Q, Z0.Q[0]
mov z0.q, z0.q[2]
MOV Z0.Q, Z0.Q[2]
mov z0.q, z0.q[3]
MOV Z0.Q, Z0.Q[3]
mov z0.s, #0xff
MOV Z0.S, #0XFF
mov z0.d, #0xff000000ff
mov z1.s, #0xff
MOV Z1.S, #0XFF
mov z1.d, #0xff000000ff
mov z31.s, #0xff
MOV Z31.S, #0XFF
mov z31.d, #0xff000000ff
mov z0.h, #0x3fff
MOV Z0.H, #0X3FFF
mov z0.s, #0x3fff3fff
mov z0.d, #0x3fff3fff3fff3fff
mov z0.s, #0x80000fff
MOV Z0.S, #0X80000FFF
mov z0.d, #0x80000fff80000fff
mov z0.s, #0x807fffff
MOV Z0.S, #0X807FFFFF
mov z0.d, #0x807fffff807fffff
mov z0.h, #0x83ff
MOV Z0.H, #0X83FF
mov z0.s, #0x83ff83ff
mov z0.d, #0x83ff83ff83ff83ff
mov z0.s, #0xc0000000
MOV Z0.S, #0XC0000000
mov z0.d, #0xc0000000c0000000
mov z0.s, #0xfe00ffff
MOV Z0.S, #0XFE00FFFF
mov z0.d, #0xfe00fffffe00ffff
mov z0.d, #0xc000ffffffffffff
MOV Z0.D, #0XC000FFFFFFFFFFFF
mov z0.d, #0xfffffffffc001fff
MOV Z0.D, #0XFFFFFFFFFC001FFF
mov z0.d, #0x7ffffffffffffffe
MOV Z0.D, #0X7FFFFFFFFFFFFFFE
mov z0.b, #0
MOV Z0.B, #0
mov z0.b, #0, lsl #0
mov z1.b, #0
MOV Z1.B, #0
mov z1.b, #0, lsl #0
mov z31.b, #0
MOV Z31.B, #0
mov z31.b, #0, lsl #0
mov z0.b, #127
MOV Z0.B, #127
mov z0.b, #127, lsl #0
mov z0.b, #-128
MOV Z0.B, #-128
mov z0.b, #-128, lsl #0
mov z0.b, #-127
MOV Z0.B, #-127
mov z0.b, #-127, lsl #0
mov z0.b, #-1
MOV Z0.B, #-1
mov z0.b, #-1, lsl #0
mov z0.h, #0
MOV Z0.H, #0
mov z0.h, #0, lsl #0
mov z1.h, #0
MOV Z1.H, #0
mov z1.h, #0, lsl #0
mov z31.h, #0
MOV Z31.H, #0
mov z31.h, #0, lsl #0
mov z0.h, #127
MOV Z0.H, #127
mov z0.h, #127, lsl #0
mov z0.h, #-128
MOV Z0.H, #-128
mov z0.h, #-128, lsl #0
mov z0.h, #-127
MOV Z0.H, #-127
mov z0.h, #-127, lsl #0
mov z0.h, #-1
MOV Z0.H, #-1
mov z0.h, #-1, lsl #0
mov z0.h, #0, lsl #8
MOV Z0.H, #0, LSL #8
mov z0.h, #32512
MOV Z0.H, #32512
mov z0.h, #32512, lsl #0
mov z0.h, #127, lsl #8
mov z0.h, #-32768
MOV Z0.H, #-32768
mov z0.h, #-32768, lsl #0
mov z0.h, #-128, lsl #8
mov z0.h, #-32512
MOV Z0.H, #-32512
mov z0.h, #-32512, lsl #0
mov z0.h, #-127, lsl #8
mov z0.h, #-256
MOV Z0.H, #-256
mov z0.h, #-256, lsl #0
mov z0.h, #-1, lsl #8
mov z0.s, #0
MOV Z0.S, #0
mov z0.s, #0, lsl #0
mov z1.s, #0
MOV Z1.S, #0
mov z1.s, #0, lsl #0
mov z31.s, #0
MOV Z31.S, #0
mov z31.s, #0, lsl #0
mov z0.s, #127
MOV Z0.S, #127
mov z0.s, #127, lsl #0
mov z0.s, #-128
MOV Z0.S, #-128
mov z0.s, #-128, lsl #0
mov z0.s, #-127
MOV Z0.S, #-127
mov z0.s, #-127, lsl #0
mov z0.s, #-1
MOV Z0.S, #-1
mov z0.s, #-1, lsl #0
mov z0.s, #0, lsl #8
MOV Z0.S, #0, LSL #8
mov z0.s, #32512
MOV Z0.S, #32512
mov z0.s, #32512, lsl #0
mov z0.s, #127, lsl #8
mov z0.s, #-32768
MOV Z0.S, #-32768
mov z0.s, #-32768, lsl #0
mov z0.s, #-128, lsl #8
mov z0.s, #-32512
MOV Z0.S, #-32512
mov z0.s, #-32512, lsl #0
mov z0.s, #-127, lsl #8
mov z0.s, #-256
MOV Z0.S, #-256
mov z0.s, #-256, lsl #0
mov z0.s, #-1, lsl #8
mov z0.d, #0
MOV Z0.D, #0
mov z0.d, #0, lsl #0
mov z1.d, #0
MOV Z1.D, #0
mov z1.d, #0, lsl #0
mov z31.d, #0
MOV Z31.D, #0
mov z31.d, #0, lsl #0
mov z0.d, #127
MOV Z0.D, #127
mov z0.d, #127, lsl #0
mov z0.d, #-128
MOV Z0.D, #-128
mov z0.d, #-128, lsl #0
mov z0.d, #-127
MOV Z0.D, #-127
mov z0.d, #-127, lsl #0
mov z0.d, #-1
MOV Z0.D, #-1
mov z0.d, #-1, lsl #0
mov z0.d, #0, lsl #8
MOV Z0.D, #0, LSL #8
mov z0.d, #32512
MOV Z0.D, #32512
mov z0.d, #32512, lsl #0
mov z0.d, #127, lsl #8
mov z0.d, #-32768
MOV Z0.D, #-32768
mov z0.d, #-32768, lsl #0
mov z0.d, #-128, lsl #8
mov z0.d, #-32512
MOV Z0.D, #-32512
mov z0.d, #-32512, lsl #0
mov z0.d, #-127, lsl #8
mov z0.d, #-256
MOV Z0.D, #-256
mov z0.d, #-256, lsl #0
mov z0.d, #-1, lsl #8
mov z0.b, p0/m, b0
MOV Z0.B, P0/M, B0
mov z1.b, p0/m, b0
MOV Z1.B, P0/M, B0
mov z31.b, p0/m, b0
MOV Z31.B, P0/M, B0
mov z0.b, p2/m, b0
MOV Z0.B, P2/M, B0
mov z0.b, p7/m, b0
MOV Z0.B, P7/M, B0
mov z0.b, p0/m, b3
MOV Z0.B, P0/M, B3
mov z0.b, p0/m, b31
MOV Z0.B, P0/M, B31
mov z0.h, p0/m, h0
MOV Z0.H, P0/M, H0
mov z1.h, p0/m, h0
MOV Z1.H, P0/M, H0
mov z31.h, p0/m, h0
MOV Z31.H, P0/M, H0
mov z0.h, p2/m, h0
MOV Z0.H, P2/M, H0
mov z0.h, p7/m, h0
MOV Z0.H, P7/M, H0
mov z0.h, p0/m, h3
MOV Z0.H, P0/M, H3
mov z0.h, p0/m, h31
MOV Z0.H, P0/M, H31
mov z0.s, p0/m, s0
MOV Z0.S, P0/M, S0
mov z1.s, p0/m, s0
MOV Z1.S, P0/M, S0
mov z31.s, p0/m, s0
MOV Z31.S, P0/M, S0
mov z0.s, p2/m, s0
MOV Z0.S, P2/M, S0
mov z0.s, p7/m, s0
MOV Z0.S, P7/M, S0
mov z0.s, p0/m, s3
MOV Z0.S, P0/M, S3
mov z0.s, p0/m, s31
MOV Z0.S, P0/M, S31
mov z0.d, p0/m, d0
MOV Z0.D, P0/M, D0
mov z1.d, p0/m, d0
MOV Z1.D, P0/M, D0
mov z31.d, p0/m, d0
MOV Z31.D, P0/M, D0
mov z0.d, p2/m, d0
MOV Z0.D, P2/M, D0
mov z0.d, p7/m, d0
MOV Z0.D, P7/M, D0
mov z0.d, p0/m, d3
MOV Z0.D, P0/M, D3
mov z0.d, p0/m, d31
MOV Z0.D, P0/M, D31
mov z0.b, p0/m, z0.b
MOV Z0.B, P0/M, Z0.B
mov z1.b, p0/m, z0.b
MOV Z1.B, P0/M, Z0.B
mov z31.b, p0/m, z0.b
MOV Z31.B, P0/M, Z0.B
mov z0.b, p2/m, z0.b
MOV Z0.B, P2/M, Z0.B
mov z0.b, p15/m, z0.b
MOV Z0.B, P15/M, Z0.B
mov z0.b, p0/m, z3.b
MOV Z0.B, P0/M, Z3.B
mov z0.b, p0/m, z31.b
MOV Z0.B, P0/M, Z31.B
mov z0.h, p0/m, z0.h
MOV Z0.H, P0/M, Z0.H
mov z1.h, p0/m, z0.h
MOV Z1.H, P0/M, Z0.H
mov z31.h, p0/m, z0.h
MOV Z31.H, P0/M, Z0.H
mov z0.h, p2/m, z0.h
MOV Z0.H, P2/M, Z0.H
mov z0.h, p15/m, z0.h
MOV Z0.H, P15/M, Z0.H
mov z0.h, p0/m, z3.h
MOV Z0.H, P0/M, Z3.H
mov z0.h, p0/m, z31.h
MOV Z0.H, P0/M, Z31.H
mov z0.s, p0/m, z0.s
MOV Z0.S, P0/M, Z0.S
mov z1.s, p0/m, z0.s
MOV Z1.S, P0/M, Z0.S
mov z31.s, p0/m, z0.s
MOV Z31.S, P0/M, Z0.S
mov z0.s, p2/m, z0.s
MOV Z0.S, P2/M, Z0.S
mov z0.s, p15/m, z0.s
MOV Z0.S, P15/M, Z0.S
mov z0.s, p0/m, z3.s
MOV Z0.S, P0/M, Z3.S
mov z0.s, p0/m, z31.s
MOV Z0.S, P0/M, Z31.S
mov z0.d, p0/m, z0.d
MOV Z0.D, P0/M, Z0.D
mov z1.d, p0/m, z0.d
MOV Z1.D, P0/M, Z0.D
mov z31.d, p0/m, z0.d
MOV Z31.D, P0/M, Z0.D
mov z0.d, p2/m, z0.d
MOV Z0.D, P2/M, Z0.D
mov z0.d, p15/m, z0.d
MOV Z0.D, P15/M, Z0.D
mov z0.d, p0/m, z3.d
MOV Z0.D, P0/M, Z3.D
mov z0.d, p0/m, z31.d
MOV Z0.D, P0/M, Z31.D
mov z0.b, p0/m, w0
MOV Z0.B, P0/M, W0
mov z1.b, p0/m, w0
MOV Z1.B, P0/M, W0
mov z31.b, p0/m, w0
MOV Z31.B, P0/M, W0
mov z0.b, p2/m, w0
MOV Z0.B, P2/M, W0
mov z0.b, p7/m, w0
MOV Z0.B, P7/M, W0
mov z0.b, p0/m, w3
MOV Z0.B, P0/M, W3
mov z0.b, p0/m, wsp
MOV Z0.B, P0/M, WSP
mov z0.h, p0/m, w0
MOV Z0.H, P0/M, W0
mov z1.h, p0/m, w0
MOV Z1.H, P0/M, W0
mov z31.h, p0/m, w0
MOV Z31.H, P0/M, W0
mov z0.h, p2/m, w0
MOV Z0.H, P2/M, W0
mov z0.h, p7/m, w0
MOV Z0.H, P7/M, W0
mov z0.h, p0/m, w3
MOV Z0.H, P0/M, W3
mov z0.h, p0/m, wsp
MOV Z0.H, P0/M, WSP
mov z0.s, p0/m, w0
MOV Z0.S, P0/M, W0
mov z1.s, p0/m, w0
MOV Z1.S, P0/M, W0
mov z31.s, p0/m, w0
MOV Z31.S, P0/M, W0
mov z0.s, p2/m, w0
MOV Z0.S, P2/M, W0
mov z0.s, p7/m, w0
MOV Z0.S, P7/M, W0
mov z0.s, p0/m, w3
MOV Z0.S, P0/M, W3
mov z0.s, p0/m, wsp
MOV Z0.S, P0/M, WSP
mov z0.d, p0/m, x0
MOV Z0.D, P0/M, X0
mov z1.d, p0/m, x0
MOV Z1.D, P0/M, X0
mov z31.d, p0/m, x0
MOV Z31.D, P0/M, X0
mov z0.d, p2/m, x0
MOV Z0.D, P2/M, X0
mov z0.d, p7/m, x0
MOV Z0.D, P7/M, X0
mov z0.d, p0/m, x3
MOV Z0.D, P0/M, X3
mov z0.d, p0/m, sp
MOV Z0.D, P0/M, SP
mov p0.b, p0/z, p0.b
MOV P0.B, P0/Z, P0.B
mov p1.b, p0/z, p0.b
MOV P1.B, P0/Z, P0.B
mov p15.b, p0/z, p0.b
MOV P15.B, P0/Z, P0.B
mov p0.b, p2/z, p0.b
MOV P0.B, P2/Z, P0.B
mov p0.b, p15/z, p0.b
MOV P0.B, P15/Z, P0.B
mov p0.b, p0/z, p3.b
MOV P0.B, P0/Z, P3.B
mov p0.b, p0/z, p15.b
MOV P0.B, P0/Z, P15.B
mov p0.b, p0/m, p0.b
MOV P0.B, P0/M, P0.B
mov p1.b, p0/m, p0.b
MOV P1.B, P0/M, P0.B
mov p15.b, p0/m, p0.b
MOV P15.B, P0/M, P0.B
mov p0.b, p2/m, p0.b
MOV P0.B, P2/M, P0.B
mov p0.b, p15/m, p0.b
MOV P0.B, P15/M, P0.B
mov p0.b, p0/m, p3.b
MOV P0.B, P0/M, P3.B
mov p0.b, p0/m, p15.b
MOV P0.B, P0/M, P15.B
mov z0.b, p0/z, #0
MOV Z0.B, P0/Z, #0
mov z0.b, p0/z, #0, lsl #0
mov z1.b, p0/z, #0
MOV Z1.B, P0/Z, #0
mov z1.b, p0/z, #0, lsl #0
mov z31.b, p0/z, #0
MOV Z31.B, P0/Z, #0
mov z31.b, p0/z, #0, lsl #0
mov z0.b, p2/z, #0
MOV Z0.B, P2/Z, #0
mov z0.b, p2/z, #0, lsl #0
mov z0.b, p15/z, #0
MOV Z0.B, P15/Z, #0
mov z0.b, p15/z, #0, lsl #0
mov z0.b, p0/z, #127
MOV Z0.B, P0/Z, #127
mov z0.b, p0/z, #127, lsl #0
mov z0.b, p0/z, #-128
MOV Z0.B, P0/Z, #-128
mov z0.b, p0/z, #-128, lsl #0
mov z0.b, p0/z, #-127
MOV Z0.B, P0/Z, #-127
mov z0.b, p0/z, #-127, lsl #0
mov z0.b, p0/z, #-1
MOV Z0.B, P0/Z, #-1
mov z0.b, p0/z, #-1, lsl #0
mov z0.b, p0/m, #0
MOV Z0.B, P0/M, #0
mov z0.b, p0/m, #0, lsl #0
mov z1.b, p0/m, #0
MOV Z1.B, P0/M, #0
mov z1.b, p0/m, #0, lsl #0
mov z31.b, p0/m, #0
MOV Z31.B, P0/M, #0
mov z31.b, p0/m, #0, lsl #0
mov z0.b, p2/m, #0
MOV Z0.B, P2/M, #0
mov z0.b, p2/m, #0, lsl #0
mov z0.b, p15/m, #0
MOV Z0.B, P15/M, #0
mov z0.b, p15/m, #0, lsl #0
mov z0.b, p0/m, #127
MOV Z0.B, P0/M, #127
mov z0.b, p0/m, #127, lsl #0
mov z0.b, p0/m, #-128
MOV Z0.B, P0/M, #-128
mov z0.b, p0/m, #-128, lsl #0
mov z0.b, p0/m, #-127
MOV Z0.B, P0/M, #-127
mov z0.b, p0/m, #-127, lsl #0
mov z0.b, p0/m, #-1
MOV Z0.B, P0/M, #-1
mov z0.b, p0/m, #-1, lsl #0
mov z0.h, p0/z, #0
MOV Z0.H, P0/Z, #0
mov z0.h, p0/z, #0, lsl #0
mov z1.h, p0/z, #0
MOV Z1.H, P0/Z, #0
mov z1.h, p0/z, #0, lsl #0
mov z31.h, p0/z, #0
MOV Z31.H, P0/Z, #0
mov z31.h, p0/z, #0, lsl #0
mov z0.h, p2/z, #0
MOV Z0.H, P2/Z, #0
mov z0.h, p2/z, #0, lsl #0
mov z0.h, p15/z, #0
MOV Z0.H, P15/Z, #0
mov z0.h, p15/z, #0, lsl #0
mov z0.h, p0/z, #127
MOV Z0.H, P0/Z, #127
mov z0.h, p0/z, #127, lsl #0
mov z0.h, p0/z, #-128
MOV Z0.H, P0/Z, #-128
mov z0.h, p0/z, #-128, lsl #0
mov z0.h, p0/z, #-127
MOV Z0.H, P0/Z, #-127
mov z0.h, p0/z, #-127, lsl #0
mov z0.h, p0/z, #-1
MOV Z0.H, P0/Z, #-1
mov z0.h, p0/z, #-1, lsl #0
mov z0.h, p0/z, #0, lsl #8
MOV Z0.H, P0/Z, #0, LSL #8
mov z0.h, p0/z, #32512
MOV Z0.H, P0/Z, #32512
mov z0.h, p0/z, #32512, lsl #0
mov z0.h, p0/z, #127, lsl #8
mov z0.h, p0/z, #-32768
MOV Z0.H, P0/Z, #-32768
mov z0.h, p0/z, #-32768, lsl #0
mov z0.h, p0/z, #-128, lsl #8
mov z0.h, p0/z, #-32512
MOV Z0.H, P0/Z, #-32512
mov z0.h, p0/z, #-32512, lsl #0
mov z0.h, p0/z, #-127, lsl #8
mov z0.h, p0/z, #-256
MOV Z0.H, P0/Z, #-256
mov z0.h, p0/z, #-256, lsl #0
mov z0.h, p0/z, #-1, lsl #8
mov z0.h, p0/m, #0
MOV Z0.H, P0/M, #0
mov z0.h, p0/m, #0, lsl #0
mov z1.h, p0/m, #0
MOV Z1.H, P0/M, #0
mov z1.h, p0/m, #0, lsl #0
mov z31.h, p0/m, #0
MOV Z31.H, P0/M, #0
mov z31.h, p0/m, #0, lsl #0
mov z0.h, p2/m, #0
MOV Z0.H, P2/M, #0
mov z0.h, p2/m, #0, lsl #0
mov z0.h, p15/m, #0
MOV Z0.H, P15/M, #0
mov z0.h, p15/m, #0, lsl #0
mov z0.h, p0/m, #127
MOV Z0.H, P0/M, #127
mov z0.h, p0/m, #127, lsl #0
mov z0.h, p0/m, #-128
MOV Z0.H, P0/M, #-128
mov z0.h, p0/m, #-128, lsl #0
mov z0.h, p0/m, #-127
MOV Z0.H, P0/M, #-127
mov z0.h, p0/m, #-127, lsl #0
mov z0.h, p0/m, #-1
MOV Z0.H, P0/M, #-1
mov z0.h, p0/m, #-1, lsl #0
mov z0.h, p0/m, #0, lsl #8
MOV Z0.H, P0/M, #0, LSL #8
mov z0.h, p0/m, #32512
MOV Z0.H, P0/M, #32512
mov z0.h, p0/m, #32512, lsl #0
mov z0.h, p0/m, #127, lsl #8
mov z0.h, p0/m, #-32768
MOV Z0.H, P0/M, #-32768
mov z0.h, p0/m, #-32768, lsl #0
mov z0.h, p0/m, #-128, lsl #8
mov z0.h, p0/m, #-32512
MOV Z0.H, P0/M, #-32512
mov z0.h, p0/m, #-32512, lsl #0
mov z0.h, p0/m, #-127, lsl #8
mov z0.h, p0/m, #-256
MOV Z0.H, P0/M, #-256
mov z0.h, p0/m, #-256, lsl #0
mov z0.h, p0/m, #-1, lsl #8
mov z0.s, p0/z, #0
MOV Z0.S, P0/Z, #0
mov z0.s, p0/z, #0, lsl #0
mov z1.s, p0/z, #0
MOV Z1.S, P0/Z, #0
mov z1.s, p0/z, #0, lsl #0
mov z31.s, p0/z, #0
MOV Z31.S, P0/Z, #0
mov z31.s, p0/z, #0, lsl #0
mov z0.s, p2/z, #0
MOV Z0.S, P2/Z, #0
mov z0.s, p2/z, #0, lsl #0
mov z0.s, p15/z, #0
MOV Z0.S, P15/Z, #0
mov z0.s, p15/z, #0, lsl #0
mov z0.s, p0/z, #127
MOV Z0.S, P0/Z, #127
mov z0.s, p0/z, #127, lsl #0
mov z0.s, p0/z, #-128
MOV Z0.S, P0/Z, #-128
mov z0.s, p0/z, #-128, lsl #0
mov z0.s, p0/z, #-127
MOV Z0.S, P0/Z, #-127
mov z0.s, p0/z, #-127, lsl #0
mov z0.s, p0/z, #-1
MOV Z0.S, P0/Z, #-1
mov z0.s, p0/z, #-1, lsl #0
mov z0.s, p0/z, #0, lsl #8
MOV Z0.S, P0/Z, #0, LSL #8
mov z0.s, p0/z, #32512
MOV Z0.S, P0/Z, #32512
mov z0.s, p0/z, #32512, lsl #0
mov z0.s, p0/z, #127, lsl #8
mov z0.s, p0/z, #-32768
MOV Z0.S, P0/Z, #-32768
mov z0.s, p0/z, #-32768, lsl #0
mov z0.s, p0/z, #-128, lsl #8
mov z0.s, p0/z, #-32512
MOV Z0.S, P0/Z, #-32512
mov z0.s, p0/z, #-32512, lsl #0
mov z0.s, p0/z, #-127, lsl #8
mov z0.s, p0/z, #-256
MOV Z0.S, P0/Z, #-256
mov z0.s, p0/z, #-256, lsl #0
mov z0.s, p0/z, #-1, lsl #8
mov z0.s, p0/m, #0
MOV Z0.S, P0/M, #0
mov z0.s, p0/m, #0, lsl #0
mov z1.s, p0/m, #0
MOV Z1.S, P0/M, #0
mov z1.s, p0/m, #0, lsl #0
mov z31.s, p0/m, #0
MOV Z31.S, P0/M, #0
mov z31.s, p0/m, #0, lsl #0
mov z0.s, p2/m, #0
MOV Z0.S, P2/M, #0
mov z0.s, p2/m, #0, lsl #0
mov z0.s, p15/m, #0
MOV Z0.S, P15/M, #0
mov z0.s, p15/m, #0, lsl #0
mov z0.s, p0/m, #127
MOV Z0.S, P0/M, #127
mov z0.s, p0/m, #127, lsl #0
mov z0.s, p0/m, #-128
MOV Z0.S, P0/M, #-128
mov z0.s, p0/m, #-128, lsl #0
mov z0.s, p0/m, #-127
MOV Z0.S, P0/M, #-127
mov z0.s, p0/m, #-127, lsl #0
mov z0.s, p0/m, #-1
MOV Z0.S, P0/M, #-1
mov z0.s, p0/m, #-1, lsl #0
mov z0.s, p0/m, #0, lsl #8
MOV Z0.S, P0/M, #0, LSL #8
mov z0.s, p0/m, #32512
MOV Z0.S, P0/M, #32512
mov z0.s, p0/m, #32512, lsl #0
mov z0.s, p0/m, #127, lsl #8
mov z0.s, p0/m, #-32768
MOV Z0.S, P0/M, #-32768
mov z0.s, p0/m, #-32768, lsl #0
mov z0.s, p0/m, #-128, lsl #8
mov z0.s, p0/m, #-32512
MOV Z0.S, P0/M, #-32512
mov z0.s, p0/m, #-32512, lsl #0
mov z0.s, p0/m, #-127, lsl #8
mov z0.s, p0/m, #-256
MOV Z0.S, P0/M, #-256
mov z0.s, p0/m, #-256, lsl #0
mov z0.s, p0/m, #-1, lsl #8
mov z0.d, p0/z, #0
MOV Z0.D, P0/Z, #0
mov z0.d, p0/z, #0, lsl #0
mov z1.d, p0/z, #0
MOV Z1.D, P0/Z, #0
mov z1.d, p0/z, #0, lsl #0
mov z31.d, p0/z, #0
MOV Z31.D, P0/Z, #0
mov z31.d, p0/z, #0, lsl #0
mov z0.d, p2/z, #0
MOV Z0.D, P2/Z, #0
mov z0.d, p2/z, #0, lsl #0
mov z0.d, p15/z, #0
MOV Z0.D, P15/Z, #0
mov z0.d, p15/z, #0, lsl #0
mov z0.d, p0/z, #127
MOV Z0.D, P0/Z, #127
mov z0.d, p0/z, #127, lsl #0
mov z0.d, p0/z, #-128
MOV Z0.D, P0/Z, #-128
mov z0.d, p0/z, #-128, lsl #0
mov z0.d, p0/z, #-127
MOV Z0.D, P0/Z, #-127
mov z0.d, p0/z, #-127, lsl #0
mov z0.d, p0/z, #-1
MOV Z0.D, P0/Z, #-1
mov z0.d, p0/z, #-1, lsl #0
mov z0.d, p0/z, #0, lsl #8
MOV Z0.D, P0/Z, #0, LSL #8
mov z0.d, p0/z, #32512
MOV Z0.D, P0/Z, #32512
mov z0.d, p0/z, #32512, lsl #0
mov z0.d, p0/z, #127, lsl #8
mov z0.d, p0/z, #-32768
MOV Z0.D, P0/Z, #-32768
mov z0.d, p0/z, #-32768, lsl #0
mov z0.d, p0/z, #-128, lsl #8
mov z0.d, p0/z, #-32512
MOV Z0.D, P0/Z, #-32512
mov z0.d, p0/z, #-32512, lsl #0
mov z0.d, p0/z, #-127, lsl #8
mov z0.d, p0/z, #-256
MOV Z0.D, P0/Z, #-256
mov z0.d, p0/z, #-256, lsl #0
mov z0.d, p0/z, #-1, lsl #8
mov z0.d, p0/m, #0
MOV Z0.D, P0/M, #0
mov z0.d, p0/m, #0, lsl #0
mov z1.d, p0/m, #0
MOV Z1.D, P0/M, #0
mov z1.d, p0/m, #0, lsl #0
mov z31.d, p0/m, #0
MOV Z31.D, P0/M, #0
mov z31.d, p0/m, #0, lsl #0
mov z0.d, p2/m, #0
MOV Z0.D, P2/M, #0
mov z0.d, p2/m, #0, lsl #0
mov z0.d, p15/m, #0
MOV Z0.D, P15/M, #0
mov z0.d, p15/m, #0, lsl #0
mov z0.d, p0/m, #127
MOV Z0.D, P0/M, #127
mov z0.d, p0/m, #127, lsl #0
mov z0.d, p0/m, #-128
MOV Z0.D, P0/M, #-128
mov z0.d, p0/m, #-128, lsl #0
mov z0.d, p0/m, #-127
MOV Z0.D, P0/M, #-127
mov z0.d, p0/m, #-127, lsl #0
mov z0.d, p0/m, #-1
MOV Z0.D, P0/M, #-1
mov z0.d, p0/m, #-1, lsl #0
mov z0.d, p0/m, #0, lsl #8
MOV Z0.D, P0/M, #0, LSL #8
mov z0.d, p0/m, #32512
MOV Z0.D, P0/M, #32512
mov z0.d, p0/m, #32512, lsl #0
mov z0.d, p0/m, #127, lsl #8
mov z0.d, p0/m, #-32768
MOV Z0.D, P0/M, #-32768
mov z0.d, p0/m, #-32768, lsl #0
mov z0.d, p0/m, #-128, lsl #8
mov z0.d, p0/m, #-32512
MOV Z0.D, P0/M, #-32512
mov z0.d, p0/m, #-32512, lsl #0
mov z0.d, p0/m, #-127, lsl #8
mov z0.d, p0/m, #-256
MOV Z0.D, P0/M, #-256
mov z0.d, p0/m, #-256, lsl #0
mov z0.d, p0/m, #-1, lsl #8
movs p0.b, p0.b
MOVS P0.B, P0.B
movs p1.b, p0.b
MOVS P1.B, P0.B
movs p15.b, p0.b
MOVS P15.B, P0.B
movs p0.b, p2.b
MOVS P0.B, P2.B
movs p0.b, p15.b
MOVS P0.B, P15.B
movs p0.b, p0/z, p0.b
MOVS P0.B, P0/Z, P0.B
movs p1.b, p0/z, p0.b
MOVS P1.B, P0/Z, P0.B
movs p15.b, p0/z, p0.b
MOVS P15.B, P0/Z, P0.B
movs p0.b, p2/z, p0.b
MOVS P0.B, P2/Z, P0.B
movs p0.b, p15/z, p0.b
MOVS P0.B, P15/Z, P0.B
movs p0.b, p0/z, p3.b
MOVS P0.B, P0/Z, P3.B
movs p0.b, p0/z, p15.b
MOVS P0.B, P0/Z, P15.B
not p0.b, p0/z, p0.b
NOT P0.B, P0/Z, P0.B
not p1.b, p0/z, p0.b
NOT P1.B, P0/Z, P0.B
not p15.b, p0/z, p0.b
NOT P15.B, P0/Z, P0.B
not p0.b, p2/z, p0.b
NOT P0.B, P2/Z, P0.B
not p0.b, p15/z, p0.b
NOT P0.B, P15/Z, P0.B
not p0.b, p0/z, p3.b
NOT P0.B, P0/Z, P3.B
not p0.b, p0/z, p15.b
NOT P0.B, P0/Z, P15.B
nots p0.b, p0/z, p0.b
NOTS P0.B, P0/Z, P0.B
nots p1.b, p0/z, p0.b
NOTS P1.B, P0/Z, P0.B
nots p15.b, p0/z, p0.b
NOTS P15.B, P0/Z, P0.B
nots p0.b, p2/z, p0.b
NOTS P0.B, P2/Z, P0.B
nots p0.b, p15/z, p0.b
NOTS P0.B, P15/Z, P0.B
nots p0.b, p0/z, p3.b
NOTS P0.B, P0/Z, P3.B
nots p0.b, p0/z, p15.b
NOTS P0.B, P0/Z, P15.B
abs z0.b, p0/m, z0.b
ABS Z0.B, P0/M, Z0.B
abs z1.b, p0/m, z0.b
ABS Z1.B, P0/M, Z0.B
abs z31.b, p0/m, z0.b
ABS Z31.B, P0/M, Z0.B
abs z0.b, p2/m, z0.b
ABS Z0.B, P2/M, Z0.B
abs z0.b, p7/m, z0.b
ABS Z0.B, P7/M, Z0.B
abs z0.b, p0/m, z3.b
ABS Z0.B, P0/M, Z3.B
abs z0.b, p0/m, z31.b
ABS Z0.B, P0/M, Z31.B
abs z0.h, p0/m, z0.h
ABS Z0.H, P0/M, Z0.H
abs z1.h, p0/m, z0.h
ABS Z1.H, P0/M, Z0.H
abs z31.h, p0/m, z0.h
ABS Z31.H, P0/M, Z0.H
abs z0.h, p2/m, z0.h
ABS Z0.H, P2/M, Z0.H
abs z0.h, p7/m, z0.h
ABS Z0.H, P7/M, Z0.H
abs z0.h, p0/m, z3.h
ABS Z0.H, P0/M, Z3.H
abs z0.h, p0/m, z31.h
ABS Z0.H, P0/M, Z31.H
abs z0.s, p0/m, z0.s
ABS Z0.S, P0/M, Z0.S
abs z1.s, p0/m, z0.s
ABS Z1.S, P0/M, Z0.S
abs z31.s, p0/m, z0.s
ABS Z31.S, P0/M, Z0.S
abs z0.s, p2/m, z0.s
ABS Z0.S, P2/M, Z0.S
abs z0.s, p7/m, z0.s
ABS Z0.S, P7/M, Z0.S
abs z0.s, p0/m, z3.s
ABS Z0.S, P0/M, Z3.S
abs z0.s, p0/m, z31.s
ABS Z0.S, P0/M, Z31.S
abs z0.d, p0/m, z0.d
ABS Z0.D, P0/M, Z0.D
abs z1.d, p0/m, z0.d
ABS Z1.D, P0/M, Z0.D
abs z31.d, p0/m, z0.d
ABS Z31.D, P0/M, Z0.D
abs z0.d, p2/m, z0.d
ABS Z0.D, P2/M, Z0.D
abs z0.d, p7/m, z0.d
ABS Z0.D, P7/M, Z0.D
abs z0.d, p0/m, z3.d
ABS Z0.D, P0/M, Z3.D
abs z0.d, p0/m, z31.d
ABS Z0.D, P0/M, Z31.D
add z0.b, z0.b, z0.b
ADD Z0.B, Z0.B, Z0.B
add z1.b, z0.b, z0.b
ADD Z1.B, Z0.B, Z0.B
add z31.b, z0.b, z0.b
ADD Z31.B, Z0.B, Z0.B
add z0.b, z2.b, z0.b
ADD Z0.B, Z2.B, Z0.B
add z0.b, z31.b, z0.b
ADD Z0.B, Z31.B, Z0.B
add z0.b, z0.b, z3.b
ADD Z0.B, Z0.B, Z3.B
add z0.b, z0.b, z31.b
ADD Z0.B, Z0.B, Z31.B
add z0.h, z0.h, z0.h
ADD Z0.H, Z0.H, Z0.H
add z1.h, z0.h, z0.h
ADD Z1.H, Z0.H, Z0.H
add z31.h, z0.h, z0.h
ADD Z31.H, Z0.H, Z0.H
add z0.h, z2.h, z0.h
ADD Z0.H, Z2.H, Z0.H
add z0.h, z31.h, z0.h
ADD Z0.H, Z31.H, Z0.H
add z0.h, z0.h, z3.h
ADD Z0.H, Z0.H, Z3.H
add z0.h, z0.h, z31.h
ADD Z0.H, Z0.H, Z31.H
add z0.s, z0.s, z0.s
ADD Z0.S, Z0.S, Z0.S
add z1.s, z0.s, z0.s
ADD Z1.S, Z0.S, Z0.S
add z31.s, z0.s, z0.s
ADD Z31.S, Z0.S, Z0.S
add z0.s, z2.s, z0.s
ADD Z0.S, Z2.S, Z0.S
add z0.s, z31.s, z0.s
ADD Z0.S, Z31.S, Z0.S
add z0.s, z0.s, z3.s
ADD Z0.S, Z0.S, Z3.S
add z0.s, z0.s, z31.s
ADD Z0.S, Z0.S, Z31.S
add z0.d, z0.d, z0.d
ADD Z0.D, Z0.D, Z0.D
add z1.d, z0.d, z0.d
ADD Z1.D, Z0.D, Z0.D
add z31.d, z0.d, z0.d
ADD Z31.D, Z0.D, Z0.D
add z0.d, z2.d, z0.d
ADD Z0.D, Z2.D, Z0.D
add z0.d, z31.d, z0.d
ADD Z0.D, Z31.D, Z0.D
add z0.d, z0.d, z3.d
ADD Z0.D, Z0.D, Z3.D
add z0.d, z0.d, z31.d
ADD Z0.D, Z0.D, Z31.D
add z0.b, z0.b, #0
ADD Z0.B, Z0.B, #0
add z0.b, z0.b, #0, lsl #0
add z1.b, z1.b, #0
ADD Z1.B, Z1.B, #0
add z1.b, z1.b, #0, lsl #0
add z31.b, z31.b, #0
ADD Z31.B, Z31.B, #0
add z31.b, z31.b, #0, lsl #0
add z2.b, z2.b, #0
ADD Z2.B, Z2.B, #0
add z2.b, z2.b, #0, lsl #0
add z0.b, z0.b, #127
ADD Z0.B, Z0.B, #127
add z0.b, z0.b, #127, lsl #0
add z0.b, z0.b, #128
ADD Z0.B, Z0.B, #128
add z0.b, z0.b, #128, lsl #0
add z0.b, z0.b, #129
ADD Z0.B, Z0.B, #129
add z0.b, z0.b, #129, lsl #0
add z0.b, z0.b, #255
ADD Z0.B, Z0.B, #255
add z0.b, z0.b, #255, lsl #0
add z0.h, z0.h, #0
ADD Z0.H, Z0.H, #0
add z0.h, z0.h, #0, lsl #0
add z1.h, z1.h, #0
ADD Z1.H, Z1.H, #0
add z1.h, z1.h, #0, lsl #0
add z31.h, z31.h, #0
ADD Z31.H, Z31.H, #0
add z31.h, z31.h, #0, lsl #0
add z2.h, z2.h, #0
ADD Z2.H, Z2.H, #0
add z2.h, z2.h, #0, lsl #0
add z0.h, z0.h, #127
ADD Z0.H, Z0.H, #127
add z0.h, z0.h, #127, lsl #0
add z0.h, z0.h, #128
ADD Z0.H, Z0.H, #128
add z0.h, z0.h, #128, lsl #0
add z0.h, z0.h, #129
ADD Z0.H, Z0.H, #129
add z0.h, z0.h, #129, lsl #0
add z0.h, z0.h, #255
ADD Z0.H, Z0.H, #255
add z0.h, z0.h, #255, lsl #0
add z0.h, z0.h, #0, lsl #8
ADD Z0.H, Z0.H, #0, LSL #8
add z0.h, z0.h, #32512
ADD Z0.H, Z0.H, #32512
add z0.h, z0.h, #32512, lsl #0
add z0.h, z0.h, #127, lsl #8
add z0.h, z0.h, #32768
ADD Z0.H, Z0.H, #32768
add z0.h, z0.h, #32768, lsl #0
add z0.h, z0.h, #128, lsl #8
add z0.h, z0.h, #33024
ADD Z0.H, Z0.H, #33024
add z0.h, z0.h, #33024, lsl #0
add z0.h, z0.h, #129, lsl #8
add z0.h, z0.h, #65280
ADD Z0.H, Z0.H, #65280
add z0.h, z0.h, #65280, lsl #0
add z0.h, z0.h, #255, lsl #8
add z0.s, z0.s, #0
ADD Z0.S, Z0.S, #0
add z0.s, z0.s, #0, lsl #0
add z1.s, z1.s, #0
ADD Z1.S, Z1.S, #0
add z1.s, z1.s, #0, lsl #0
add z31.s, z31.s, #0
ADD Z31.S, Z31.S, #0
add z31.s, z31.s, #0, lsl #0
add z2.s, z2.s, #0
ADD Z2.S, Z2.S, #0
add z2.s, z2.s, #0, lsl #0
add z0.s, z0.s, #127
ADD Z0.S, Z0.S, #127
add z0.s, z0.s, #127, lsl #0
add z0.s, z0.s, #128
ADD Z0.S, Z0.S, #128
add z0.s, z0.s, #128, lsl #0
add z0.s, z0.s, #129
ADD Z0.S, Z0.S, #129
add z0.s, z0.s, #129, lsl #0
add z0.s, z0.s, #255
ADD Z0.S, Z0.S, #255
add z0.s, z0.s, #255, lsl #0
add z0.s, z0.s, #0, lsl #8
ADD Z0.S, Z0.S, #0, LSL #8
add z0.s, z0.s, #32512
ADD Z0.S, Z0.S, #32512
add z0.s, z0.s, #32512, lsl #0
add z0.s, z0.s, #127, lsl #8
add z0.s, z0.s, #32768
ADD Z0.S, Z0.S, #32768
add z0.s, z0.s, #32768, lsl #0
add z0.s, z0.s, #128, lsl #8
add z0.s, z0.s, #33024
ADD Z0.S, Z0.S, #33024
add z0.s, z0.s, #33024, lsl #0
add z0.s, z0.s, #129, lsl #8
add z0.s, z0.s, #65280
ADD Z0.S, Z0.S, #65280
add z0.s, z0.s, #65280, lsl #0
add z0.s, z0.s, #255, lsl #8
add z0.d, z0.d, #0
ADD Z0.D, Z0.D, #0
add z0.d, z0.d, #0, lsl #0
add z1.d, z1.d, #0
ADD Z1.D, Z1.D, #0
add z1.d, z1.d, #0, lsl #0
add z31.d, z31.d, #0
ADD Z31.D, Z31.D, #0
add z31.d, z31.d, #0, lsl #0
add z2.d, z2.d, #0
ADD Z2.D, Z2.D, #0
add z2.d, z2.d, #0, lsl #0
add z0.d, z0.d, #127
ADD Z0.D, Z0.D, #127
add z0.d, z0.d, #127, lsl #0
add z0.d, z0.d, #128
ADD Z0.D, Z0.D, #128
add z0.d, z0.d, #128, lsl #0
add z0.d, z0.d, #129
ADD Z0.D, Z0.D, #129
add z0.d, z0.d, #129, lsl #0
add z0.d, z0.d, #255
ADD Z0.D, Z0.D, #255
add z0.d, z0.d, #255, lsl #0
add z0.d, z0.d, #0, lsl #8
ADD Z0.D, Z0.D, #0, LSL #8
add z0.d, z0.d, #32512
ADD Z0.D, Z0.D, #32512
add z0.d, z0.d, #32512, lsl #0
add z0.d, z0.d, #127, lsl #8
add z0.d, z0.d, #32768
ADD Z0.D, Z0.D, #32768
add z0.d, z0.d, #32768, lsl #0
add z0.d, z0.d, #128, lsl #8
add z0.d, z0.d, #33024
ADD Z0.D, Z0.D, #33024
add z0.d, z0.d, #33024, lsl #0
add z0.d, z0.d, #129, lsl #8
add z0.d, z0.d, #65280
ADD Z0.D, Z0.D, #65280
add z0.d, z0.d, #65280, lsl #0
add z0.d, z0.d, #255, lsl #8
add z0.b, p0/m, z0.b, z0.b
ADD Z0.B, P0/M, Z0.B, Z0.B
add z1.b, p0/m, z1.b, z0.b
ADD Z1.B, P0/M, Z1.B, Z0.B
add z31.b, p0/m, z31.b, z0.b
ADD Z31.B, P0/M, Z31.B, Z0.B
add z0.b, p2/m, z0.b, z0.b
ADD Z0.B, P2/M, Z0.B, Z0.B
add z0.b, p7/m, z0.b, z0.b
ADD Z0.B, P7/M, Z0.B, Z0.B
add z3.b, p0/m, z3.b, z0.b
ADD Z3.B, P0/M, Z3.B, Z0.B
add z0.b, p0/m, z0.b, z4.b
ADD Z0.B, P0/M, Z0.B, Z4.B
add z0.b, p0/m, z0.b, z31.b
ADD Z0.B, P0/M, Z0.B, Z31.B
add z0.h, p0/m, z0.h, z0.h
ADD Z0.H, P0/M, Z0.H, Z0.H
add z1.h, p0/m, z1.h, z0.h
ADD Z1.H, P0/M, Z1.H, Z0.H
add z31.h, p0/m, z31.h, z0.h
ADD Z31.H, P0/M, Z31.H, Z0.H
add z0.h, p2/m, z0.h, z0.h
ADD Z0.H, P2/M, Z0.H, Z0.H
add z0.h, p7/m, z0.h, z0.h
ADD Z0.H, P7/M, Z0.H, Z0.H
add z3.h, p0/m, z3.h, z0.h
ADD Z3.H, P0/M, Z3.H, Z0.H
add z0.h, p0/m, z0.h, z4.h
ADD Z0.H, P0/M, Z0.H, Z4.H
add z0.h, p0/m, z0.h, z31.h
ADD Z0.H, P0/M, Z0.H, Z31.H
add z0.s, p0/m, z0.s, z0.s
ADD Z0.S, P0/M, Z0.S, Z0.S
add z1.s, p0/m, z1.s, z0.s
ADD Z1.S, P0/M, Z1.S, Z0.S
add z31.s, p0/m, z31.s, z0.s
ADD Z31.S, P0/M, Z31.S, Z0.S
add z0.s, p2/m, z0.s, z0.s
ADD Z0.S, P2/M, Z0.S, Z0.S
add z0.s, p7/m, z0.s, z0.s
ADD Z0.S, P7/M, Z0.S, Z0.S
add z3.s, p0/m, z3.s, z0.s
ADD Z3.S, P0/M, Z3.S, Z0.S
add z0.s, p0/m, z0.s, z4.s
ADD Z0.S, P0/M, Z0.S, Z4.S
add z0.s, p0/m, z0.s, z31.s
ADD Z0.S, P0/M, Z0.S, Z31.S
add z0.d, p0/m, z0.d, z0.d
ADD Z0.D, P0/M, Z0.D, Z0.D
add z1.d, p0/m, z1.d, z0.d
ADD Z1.D, P0/M, Z1.D, Z0.D
add z31.d, p0/m, z31.d, z0.d
ADD Z31.D, P0/M, Z31.D, Z0.D
add z0.d, p2/m, z0.d, z0.d
ADD Z0.D, P2/M, Z0.D, Z0.D
add z0.d, p7/m, z0.d, z0.d
ADD Z0.D, P7/M, Z0.D, Z0.D
add z3.d, p0/m, z3.d, z0.d
ADD Z3.D, P0/M, Z3.D, Z0.D
add z0.d, p0/m, z0.d, z4.d
ADD Z0.D, P0/M, Z0.D, Z4.D
add z0.d, p0/m, z0.d, z31.d
ADD Z0.D, P0/M, Z0.D, Z31.D
addpl x0, x0, #0
ADDPL X0, X0, #0
addpl x1, x0, #0
ADDPL X1, X0, #0
addpl sp, x0, #0
ADDPL SP, X0, #0
addpl x0, x2, #0
ADDPL X0, X2, #0
addpl x0, sp, #0
ADDPL X0, SP, #0
addpl x0, x0, #31
ADDPL X0, X0, #31
addpl x0, x0, #-32
ADDPL X0, X0, #-32
addpl x0, x0, #-31
ADDPL X0, X0, #-31
addpl x0, x0, #-1
ADDPL X0, X0, #-1
addvl x0, x0, #0
ADDVL X0, X0, #0
addvl x1, x0, #0
ADDVL X1, X0, #0
addvl sp, x0, #0
ADDVL SP, X0, #0
addvl x0, x2, #0
ADDVL X0, X2, #0
addvl x0, sp, #0
ADDVL X0, SP, #0
addvl x0, x0, #31
ADDVL X0, X0, #31
addvl x0, x0, #-32
ADDVL X0, X0, #-32
addvl x0, x0, #-31
ADDVL X0, X0, #-31
addvl x0, x0, #-1
ADDVL X0, X0, #-1
adr z0.d, [z0.d,z0.d,sxtw]
ADR Z0.D, [Z0.D,Z0.D,SXTW]
adr z0.d, [z0.d,z0.d,sxtw #0]
adr z1.d, [z0.d,z0.d,sxtw]
ADR Z1.D, [Z0.D,Z0.D,SXTW]
adr z1.d, [z0.d,z0.d,sxtw #0]
adr z31.d, [z0.d,z0.d,sxtw]
ADR Z31.D, [Z0.D,Z0.D,SXTW]
adr z31.d, [z0.d,z0.d,sxtw #0]
adr z0.d, [z2.d,z0.d,sxtw]
ADR Z0.D, [Z2.D,Z0.D,SXTW]
adr z0.d, [z2.d,z0.d,sxtw #0]
adr z0.d, [z31.d,z0.d,sxtw]
ADR Z0.D, [Z31.D,Z0.D,SXTW]
adr z0.d, [z31.d,z0.d,sxtw #0]
adr z0.d, [z0.d,z3.d,sxtw]
ADR Z0.D, [Z0.D,Z3.D,SXTW]
adr z0.d, [z0.d,z3.d,sxtw #0]
adr z0.d, [z0.d,z31.d,sxtw]
ADR Z0.D, [Z0.D,Z31.D,SXTW]
adr z0.d, [z0.d,z31.d,sxtw #0]
adr z0.d, [z0.d,z0.d,sxtw #1]
ADR Z0.D, [Z0.D,Z0.D,SXTW #1]
adr z1.d, [z0.d,z0.d,sxtw #1]
ADR Z1.D, [Z0.D,Z0.D,SXTW #1]
adr z31.d, [z0.d,z0.d,sxtw #1]
ADR Z31.D, [Z0.D,Z0.D,SXTW #1]
adr z0.d, [z2.d,z0.d,sxtw #1]
ADR Z0.D, [Z2.D,Z0.D,SXTW #1]
adr z0.d, [z31.d,z0.d,sxtw #1]
ADR Z0.D, [Z31.D,Z0.D,SXTW #1]
adr z0.d, [z0.d,z3.d,sxtw #1]
ADR Z0.D, [Z0.D,Z3.D,SXTW #1]
adr z0.d, [z0.d,z31.d,sxtw #1]
ADR Z0.D, [Z0.D,Z31.D,SXTW #1]
adr z0.d, [z0.d,z0.d,sxtw #2]
ADR Z0.D, [Z0.D,Z0.D,SXTW #2]
adr z1.d, [z0.d,z0.d,sxtw #2]
ADR Z1.D, [Z0.D,Z0.D,SXTW #2]
adr z31.d, [z0.d,z0.d,sxtw #2]
ADR Z31.D, [Z0.D,Z0.D,SXTW #2]
adr z0.d, [z2.d,z0.d,sxtw #2]
ADR Z0.D, [Z2.D,Z0.D,SXTW #2]
adr z0.d, [z31.d,z0.d,sxtw #2]
ADR Z0.D, [Z31.D,Z0.D,SXTW #2]
adr z0.d, [z0.d,z3.d,sxtw #2]
ADR Z0.D, [Z0.D,Z3.D,SXTW #2]
adr z0.d, [z0.d,z31.d,sxtw #2]
ADR Z0.D, [Z0.D,Z31.D,SXTW #2]
adr z0.d, [z0.d,z0.d,sxtw #3]
ADR Z0.D, [Z0.D,Z0.D,SXTW #3]
adr z1.d, [z0.d,z0.d,sxtw #3]
ADR Z1.D, [Z0.D,Z0.D,SXTW #3]
adr z31.d, [z0.d,z0.d,sxtw #3]
ADR Z31.D, [Z0.D,Z0.D,SXTW #3]
adr z0.d, [z2.d,z0.d,sxtw #3]
ADR Z0.D, [Z2.D,Z0.D,SXTW #3]
adr z0.d, [z31.d,z0.d,sxtw #3]
ADR Z0.D, [Z31.D,Z0.D,SXTW #3]
adr z0.d, [z0.d,z3.d,sxtw #3]
ADR Z0.D, [Z0.D,Z3.D,SXTW #3]
adr z0.d, [z0.d,z31.d,sxtw #3]
ADR Z0.D, [Z0.D,Z31.D,SXTW #3]
adr z0.d, [z0.d,z0.d,uxtw]
ADR Z0.D, [Z0.D,Z0.D,UXTW]
adr z0.d, [z0.d,z0.d,uxtw #0]
adr z1.d, [z0.d,z0.d,uxtw]
ADR Z1.D, [Z0.D,Z0.D,UXTW]
adr z1.d, [z0.d,z0.d,uxtw #0]
adr z31.d, [z0.d,z0.d,uxtw]
ADR Z31.D, [Z0.D,Z0.D,UXTW]
adr z31.d, [z0.d,z0.d,uxtw #0]
adr z0.d, [z2.d,z0.d,uxtw]
ADR Z0.D, [Z2.D,Z0.D,UXTW]
adr z0.d, [z2.d,z0.d,uxtw #0]
adr z0.d, [z31.d,z0.d,uxtw]
ADR Z0.D, [Z31.D,Z0.D,UXTW]
adr z0.d, [z31.d,z0.d,uxtw #0]
adr z0.d, [z0.d,z3.d,uxtw]
ADR Z0.D, [Z0.D,Z3.D,UXTW]
adr z0.d, [z0.d,z3.d,uxtw #0]
adr z0.d, [z0.d,z31.d,uxtw]
ADR Z0.D, [Z0.D,Z31.D,UXTW]
adr z0.d, [z0.d,z31.d,uxtw #0]
adr z0.d, [z0.d,z0.d,uxtw #1]
ADR Z0.D, [Z0.D,Z0.D,UXTW #1]
adr z1.d, [z0.d,z0.d,uxtw #1]
ADR Z1.D, [Z0.D,Z0.D,UXTW #1]
adr z31.d, [z0.d,z0.d,uxtw #1]
ADR Z31.D, [Z0.D,Z0.D,UXTW #1]
adr z0.d, [z2.d,z0.d,uxtw #1]
ADR Z0.D, [Z2.D,Z0.D,UXTW #1]
adr z0.d, [z31.d,z0.d,uxtw #1]
ADR Z0.D, [Z31.D,Z0.D,UXTW #1]
adr z0.d, [z0.d,z3.d,uxtw #1]
ADR Z0.D, [Z0.D,Z3.D,UXTW #1]
adr z0.d, [z0.d,z31.d,uxtw #1]
ADR Z0.D, [Z0.D,Z31.D,UXTW #1]
adr z0.d, [z0.d,z0.d,uxtw #2]
ADR Z0.D, [Z0.D,Z0.D,UXTW #2]
adr z1.d, [z0.d,z0.d,uxtw #2]
ADR Z1.D, [Z0.D,Z0.D,UXTW #2]
adr z31.d, [z0.d,z0.d,uxtw #2]
ADR Z31.D, [Z0.D,Z0.D,UXTW #2]
adr z0.d, [z2.d,z0.d,uxtw #2]
ADR Z0.D, [Z2.D,Z0.D,UXTW #2]
adr z0.d, [z31.d,z0.d,uxtw #2]
ADR Z0.D, [Z31.D,Z0.D,UXTW #2]
adr z0.d, [z0.d,z3.d,uxtw #2]
ADR Z0.D, [Z0.D,Z3.D,UXTW #2]
adr z0.d, [z0.d,z31.d,uxtw #2]
ADR Z0.D, [Z0.D,Z31.D,UXTW #2]
adr z0.d, [z0.d,z0.d,uxtw #3]
ADR Z0.D, [Z0.D,Z0.D,UXTW #3]
adr z1.d, [z0.d,z0.d,uxtw #3]
ADR Z1.D, [Z0.D,Z0.D,UXTW #3]
adr z31.d, [z0.d,z0.d,uxtw #3]
ADR Z31.D, [Z0.D,Z0.D,UXTW #3]
adr z0.d, [z2.d,z0.d,uxtw #3]
ADR Z0.D, [Z2.D,Z0.D,UXTW #3]
adr z0.d, [z31.d,z0.d,uxtw #3]
ADR Z0.D, [Z31.D,Z0.D,UXTW #3]
adr z0.d, [z0.d,z3.d,uxtw #3]
ADR Z0.D, [Z0.D,Z3.D,UXTW #3]
adr z0.d, [z0.d,z31.d,uxtw #3]
ADR Z0.D, [Z0.D,Z31.D,UXTW #3]
adr z0.s, [z0.s,z0.s]
ADR Z0.S, [Z0.S,Z0.S]
adr z0.s, [z0.s,z0.s,lsl #0]
adr z1.s, [z0.s,z0.s]
ADR Z1.S, [Z0.S,Z0.S]
adr z1.s, [z0.s,z0.s,lsl #0]
adr z31.s, [z0.s,z0.s]
ADR Z31.S, [Z0.S,Z0.S]
adr z31.s, [z0.s,z0.s,lsl #0]
adr z0.s, [z2.s,z0.s]
ADR Z0.S, [Z2.S,Z0.S]
adr z0.s, [z2.s,z0.s,lsl #0]
adr z0.s, [z31.s,z0.s]
ADR Z0.S, [Z31.S,Z0.S]
adr z0.s, [z31.s,z0.s,lsl #0]
adr z0.s, [z0.s,z3.s]
ADR Z0.S, [Z0.S,Z3.S]
adr z0.s, [z0.s,z3.s,lsl #0]
adr z0.s, [z0.s,z31.s]
ADR Z0.S, [Z0.S,Z31.S]
adr z0.s, [z0.s,z31.s,lsl #0]
adr z0.s, [z0.s,z0.s,lsl #1]
ADR Z0.S, [Z0.S,Z0.S,LSL #1]
adr z1.s, [z0.s,z0.s,lsl #1]
ADR Z1.S, [Z0.S,Z0.S,LSL #1]
adr z31.s, [z0.s,z0.s,lsl #1]
ADR Z31.S, [Z0.S,Z0.S,LSL #1]
adr z0.s, [z2.s,z0.s,lsl #1]
ADR Z0.S, [Z2.S,Z0.S,LSL #1]
adr z0.s, [z31.s,z0.s,lsl #1]
ADR Z0.S, [Z31.S,Z0.S,LSL #1]
adr z0.s, [z0.s,z3.s,lsl #1]
ADR Z0.S, [Z0.S,Z3.S,LSL #1]
adr z0.s, [z0.s,z31.s,lsl #1]
ADR Z0.S, [Z0.S,Z31.S,LSL #1]
adr z0.s, [z0.s,z0.s,lsl #2]
ADR Z0.S, [Z0.S,Z0.S,LSL #2]
adr z1.s, [z0.s,z0.s,lsl #2]
ADR Z1.S, [Z0.S,Z0.S,LSL #2]
adr z31.s, [z0.s,z0.s,lsl #2]
ADR Z31.S, [Z0.S,Z0.S,LSL #2]
adr z0.s, [z2.s,z0.s,lsl #2]
ADR Z0.S, [Z2.S,Z0.S,LSL #2]
adr z0.s, [z31.s,z0.s,lsl #2]
ADR Z0.S, [Z31.S,Z0.S,LSL #2]
adr z0.s, [z0.s,z3.s,lsl #2]
ADR Z0.S, [Z0.S,Z3.S,LSL #2]
adr z0.s, [z0.s,z31.s,lsl #2]
ADR Z0.S, [Z0.S,Z31.S,LSL #2]
adr z0.s, [z0.s,z0.s,lsl #3]
ADR Z0.S, [Z0.S,Z0.S,LSL #3]
adr z1.s, [z0.s,z0.s,lsl #3]
ADR Z1.S, [Z0.S,Z0.S,LSL #3]
adr z31.s, [z0.s,z0.s,lsl #3]
ADR Z31.S, [Z0.S,Z0.S,LSL #3]
adr z0.s, [z2.s,z0.s,lsl #3]
ADR Z0.S, [Z2.S,Z0.S,LSL #3]
adr z0.s, [z31.s,z0.s,lsl #3]
ADR Z0.S, [Z31.S,Z0.S,LSL #3]
adr z0.s, [z0.s,z3.s,lsl #3]
ADR Z0.S, [Z0.S,Z3.S,LSL #3]
adr z0.s, [z0.s,z31.s,lsl #3]
ADR Z0.S, [Z0.S,Z31.S,LSL #3]
adr z0.d, [z0.d,z0.d]
ADR Z0.D, [Z0.D,Z0.D]
adr z0.d, [z0.d,z0.d,lsl #0]
adr z1.d, [z0.d,z0.d]
ADR Z1.D, [Z0.D,Z0.D]
adr z1.d, [z0.d,z0.d,lsl #0]
adr z31.d, [z0.d,z0.d]
ADR Z31.D, [Z0.D,Z0.D]
adr z31.d, [z0.d,z0.d,lsl #0]
adr z0.d, [z2.d,z0.d]
ADR Z0.D, [Z2.D,Z0.D]
adr z0.d, [z2.d,z0.d,lsl #0]
adr z0.d, [z31.d,z0.d]
ADR Z0.D, [Z31.D,Z0.D]
adr z0.d, [z31.d,z0.d,lsl #0]
adr z0.d, [z0.d,z3.d]
ADR Z0.D, [Z0.D,Z3.D]
adr z0.d, [z0.d,z3.d,lsl #0]
adr z0.d, [z0.d,z31.d]
ADR Z0.D, [Z0.D,Z31.D]
adr z0.d, [z0.d,z31.d,lsl #0]
adr z0.d, [z0.d,z0.d,lsl #1]
ADR Z0.D, [Z0.D,Z0.D,LSL #1]
adr z1.d, [z0.d,z0.d,lsl #1]
ADR Z1.D, [Z0.D,Z0.D,LSL #1]
adr z31.d, [z0.d,z0.d,lsl #1]
ADR Z31.D, [Z0.D,Z0.D,LSL #1]
adr z0.d, [z2.d,z0.d,lsl #1]
ADR Z0.D, [Z2.D,Z0.D,LSL #1]
adr z0.d, [z31.d,z0.d,lsl #1]
ADR Z0.D, [Z31.D,Z0.D,LSL #1]
adr z0.d, [z0.d,z3.d,lsl #1]
ADR Z0.D, [Z0.D,Z3.D,LSL #1]
adr z0.d, [z0.d,z31.d,lsl #1]
ADR Z0.D, [Z0.D,Z31.D,LSL #1]
adr z0.d, [z0.d,z0.d,lsl #2]
ADR Z0.D, [Z0.D,Z0.D,LSL #2]
adr z1.d, [z0.d,z0.d,lsl #2]
ADR Z1.D, [Z0.D,Z0.D,LSL #2]
adr z31.d, [z0.d,z0.d,lsl #2]
ADR Z31.D, [Z0.D,Z0.D,LSL #2]
adr z0.d, [z2.d,z0.d,lsl #2]
ADR Z0.D, [Z2.D,Z0.D,LSL #2]
adr z0.d, [z31.d,z0.d,lsl #2]
ADR Z0.D, [Z31.D,Z0.D,LSL #2]
adr z0.d, [z0.d,z3.d,lsl #2]
ADR Z0.D, [Z0.D,Z3.D,LSL #2]
adr z0.d, [z0.d,z31.d,lsl #2]
ADR Z0.D, [Z0.D,Z31.D,LSL #2]
adr z0.d, [z0.d,z0.d,lsl #3]
ADR Z0.D, [Z0.D,Z0.D,LSL #3]
adr z1.d, [z0.d,z0.d,lsl #3]
ADR Z1.D, [Z0.D,Z0.D,LSL #3]
adr z31.d, [z0.d,z0.d,lsl #3]
ADR Z31.D, [Z0.D,Z0.D,LSL #3]
adr z0.d, [z2.d,z0.d,lsl #3]
ADR Z0.D, [Z2.D,Z0.D,LSL #3]
adr z0.d, [z31.d,z0.d,lsl #3]
ADR Z0.D, [Z31.D,Z0.D,LSL #3]
adr z0.d, [z0.d,z3.d,lsl #3]
ADR Z0.D, [Z0.D,Z3.D,LSL #3]
adr z0.d, [z0.d,z31.d,lsl #3]
ADR Z0.D, [Z0.D,Z31.D,LSL #3]
and z0.d, z0.d, z0.d
AND Z0.D, Z0.D, Z0.D
and z1.d, z0.d, z0.d
AND Z1.D, Z0.D, Z0.D
and z31.d, z0.d, z0.d
AND Z31.D, Z0.D, Z0.D
and z0.d, z2.d, z0.d
AND Z0.D, Z2.D, Z0.D
and z0.d, z31.d, z0.d
AND Z0.D, Z31.D, Z0.D
and z0.d, z0.d, z3.d
AND Z0.D, Z0.D, Z3.D
and z0.d, z0.d, z31.d
AND Z0.D, Z0.D, Z31.D
and z0.s, z0.s, #0x1
AND Z0.S, Z0.S, #0X1
and z0.d, z0.d, #0x100000001
and z1.s, z1.s, #0x1
AND Z1.S, Z1.S, #0X1
and z1.d, z1.d, #0x100000001
and z31.s, z31.s, #0x1
AND Z31.S, Z31.S, #0X1
and z31.d, z31.d, #0x100000001
and z2.s, z2.s, #0x1
AND Z2.S, Z2.S, #0X1
and z2.d, z2.d, #0x100000001
and z0.s, z0.s, #0x7f
AND Z0.S, Z0.S, #0X7F
and z0.d, z0.d, #0x7f0000007f
and z0.s, z0.s, #0x7fffffff
AND Z0.S, Z0.S, #0X7FFFFFFF
and z0.d, z0.d, #0x7fffffff7fffffff
and z0.h, z0.h, #0x1
AND Z0.H, Z0.H, #0X1
and z0.s, z0.s, #0x10001
and z0.d, z0.d, #0x1000100010001
and z0.h, z0.h, #0x7fff
AND Z0.H, Z0.H, #0X7FFF
and z0.s, z0.s, #0x7fff7fff
and z0.d, z0.d, #0x7fff7fff7fff7fff
and z0.b, z0.b, #0x1
AND Z0.B, Z0.B, #0X1
and z0.h, z0.h, #0x101
and z0.s, z0.s, #0x1010101
and z0.d, z0.d, #0x101010101010101
and z0.b, z0.b, #0x55
AND Z0.B, Z0.B, #0X55
and z0.h, z0.h, #0x5555
and z0.s, z0.s, #0x55555555
and z0.d, z0.d, #0x5555555555555555
and z0.s, z0.s, #0x80000000
AND Z0.S, Z0.S, #0X80000000
and z0.d, z0.d, #0x8000000080000000
and z0.s, z0.s, #0xbfffffff
AND Z0.S, Z0.S, #0XBFFFFFFF
and z0.d, z0.d, #0xbfffffffbfffffff
and z0.h, z0.h, #0x8000
AND Z0.H, Z0.H, #0X8000
and z0.s, z0.s, #0x80008000
and z0.d, z0.d, #0x8000800080008000
and z0.b, z0.b, #0xbf
AND Z0.B, Z0.B, #0XBF
and z0.h, z0.h, #0xbfbf
and z0.s, z0.s, #0xbfbfbfbf
and z0.d, z0.d, #0xbfbfbfbfbfbfbfbf
and z0.b, z0.b, #0xe3
AND Z0.B, Z0.B, #0XE3
and z0.h, z0.h, #0xe3e3
and z0.s, z0.s, #0xe3e3e3e3
and z0.d, z0.d, #0xe3e3e3e3e3e3e3e3
and z0.s, z0.s, #0xfffffeff
AND Z0.S, Z0.S, #0XFFFFFEFF
and z0.d, z0.d, #0xfffffefffffffeff
and z0.d, z0.d, #0xfffffffffffffffe
AND Z0.D, Z0.D, #0XFFFFFFFFFFFFFFFE
and z0.b, p0/m, z0.b, z0.b
AND Z0.B, P0/M, Z0.B, Z0.B
and z1.b, p0/m, z1.b, z0.b
AND Z1.B, P0/M, Z1.B, Z0.B
and z31.b, p0/m, z31.b, z0.b
AND Z31.B, P0/M, Z31.B, Z0.B
and z0.b, p2/m, z0.b, z0.b
AND Z0.B, P2/M, Z0.B, Z0.B
and z0.b, p7/m, z0.b, z0.b
AND Z0.B, P7/M, Z0.B, Z0.B
and z3.b, p0/m, z3.b, z0.b
AND Z3.B, P0/M, Z3.B, Z0.B
and z0.b, p0/m, z0.b, z4.b
AND Z0.B, P0/M, Z0.B, Z4.B
and z0.b, p0/m, z0.b, z31.b
AND Z0.B, P0/M, Z0.B, Z31.B
and z0.h, p0/m, z0.h, z0.h
AND Z0.H, P0/M, Z0.H, Z0.H
and z1.h, p0/m, z1.h, z0.h
AND Z1.H, P0/M, Z1.H, Z0.H
and z31.h, p0/m, z31.h, z0.h
AND Z31.H, P0/M, Z31.H, Z0.H
and z0.h, p2/m, z0.h, z0.h
AND Z0.H, P2/M, Z0.H, Z0.H
and z0.h, p7/m, z0.h, z0.h
AND Z0.H, P7/M, Z0.H, Z0.H
and z3.h, p0/m, z3.h, z0.h
AND Z3.H, P0/M, Z3.H, Z0.H
and z0.h, p0/m, z0.h, z4.h
AND Z0.H, P0/M, Z0.H, Z4.H
and z0.h, p0/m, z0.h, z31.h
AND Z0.H, P0/M, Z0.H, Z31.H
and z0.s, p0/m, z0.s, z0.s
AND Z0.S, P0/M, Z0.S, Z0.S
and z1.s, p0/m, z1.s, z0.s
AND Z1.S, P0/M, Z1.S, Z0.S
and z31.s, p0/m, z31.s, z0.s
AND Z31.S, P0/M, Z31.S, Z0.S
and z0.s, p2/m, z0.s, z0.s
AND Z0.S, P2/M, Z0.S, Z0.S
and z0.s, p7/m, z0.s, z0.s
AND Z0.S, P7/M, Z0.S, Z0.S
and z3.s, p0/m, z3.s, z0.s
AND Z3.S, P0/M, Z3.S, Z0.S
and z0.s, p0/m, z0.s, z4.s
AND Z0.S, P0/M, Z0.S, Z4.S
and z0.s, p0/m, z0.s, z31.s
AND Z0.S, P0/M, Z0.S, Z31.S
and z0.d, p0/m, z0.d, z0.d
AND Z0.D, P0/M, Z0.D, Z0.D
and z1.d, p0/m, z1.d, z0.d
AND Z1.D, P0/M, Z1.D, Z0.D
and z31.d, p0/m, z31.d, z0.d
AND Z31.D, P0/M, Z31.D, Z0.D
and z0.d, p2/m, z0.d, z0.d
AND Z0.D, P2/M, Z0.D, Z0.D
and z0.d, p7/m, z0.d, z0.d
AND Z0.D, P7/M, Z0.D, Z0.D
and z3.d, p0/m, z3.d, z0.d
AND Z3.D, P0/M, Z3.D, Z0.D
and z0.d, p0/m, z0.d, z4.d
AND Z0.D, P0/M, Z0.D, Z4.D
and z0.d, p0/m, z0.d, z31.d
AND Z0.D, P0/M, Z0.D, Z31.D
and p0.b, p0/z, p0.b, p0.b
AND P0.B, P0/Z, P0.B, P0.B
and p1.b, p0/z, p0.b, p0.b
AND P1.B, P0/Z, P0.B, P0.B
and p15.b, p0/z, p0.b, p0.b
AND P15.B, P0/Z, P0.B, P0.B
and p0.b, p2/z, p0.b, p0.b
AND P0.B, P2/Z, P0.B, P0.B
and p0.b, p15/z, p0.b, p0.b
AND P0.B, P15/Z, P0.B, P0.B
and p0.b, p0/z, p3.b, p0.b
AND P0.B, P0/Z, P3.B, P0.B
and p0.b, p0/z, p15.b, p0.b
AND P0.B, P0/Z, P15.B, P0.B
and p0.b, p0/z, p0.b, p4.b
AND P0.B, P0/Z, P0.B, P4.B
and p0.b, p0/z, p0.b, p15.b
AND P0.B, P0/Z, P0.B, P15.B
ands p0.b, p0/z, p0.b, p0.b
ANDS P0.B, P0/Z, P0.B, P0.B
ands p1.b, p0/z, p0.b, p0.b
ANDS P1.B, P0/Z, P0.B, P0.B
ands p15.b, p0/z, p0.b, p0.b
ANDS P15.B, P0/Z, P0.B, P0.B
ands p0.b, p2/z, p0.b, p0.b
ANDS P0.B, P2/Z, P0.B, P0.B
ands p0.b, p15/z, p0.b, p0.b
ANDS P0.B, P15/Z, P0.B, P0.B
ands p0.b, p0/z, p3.b, p0.b
ANDS P0.B, P0/Z, P3.B, P0.B
ands p0.b, p0/z, p15.b, p0.b
ANDS P0.B, P0/Z, P15.B, P0.B
ands p0.b, p0/z, p0.b, p4.b
ANDS P0.B, P0/Z, P0.B, P4.B
ands p0.b, p0/z, p0.b, p15.b
ANDS P0.B, P0/Z, P0.B, P15.B
andv b0, p0, z0.b
ANDV B0, P0, Z0.B
andv b1, p0, z0.b
ANDV B1, P0, Z0.B
andv b31, p0, z0.b
ANDV B31, P0, Z0.B
andv b0, p2, z0.b
ANDV B0, P2, Z0.B
andv b0, p7, z0.b
ANDV B0, P7, Z0.B
andv b0, p0, z3.b
ANDV B0, P0, Z3.B
andv b0, p0, z31.b
ANDV B0, P0, Z31.B
andv h0, p0, z0.h
ANDV H0, P0, Z0.H
andv h1, p0, z0.h
ANDV H1, P0, Z0.H
andv h31, p0, z0.h
ANDV H31, P0, Z0.H
andv h0, p2, z0.h
ANDV H0, P2, Z0.H
andv h0, p7, z0.h
ANDV H0, P7, Z0.H
andv h0, p0, z3.h
ANDV H0, P0, Z3.H
andv h0, p0, z31.h
ANDV H0, P0, Z31.H
andv s0, p0, z0.s
ANDV S0, P0, Z0.S
andv s1, p0, z0.s
ANDV S1, P0, Z0.S
andv s31, p0, z0.s
ANDV S31, P0, Z0.S
andv s0, p2, z0.s
ANDV S0, P2, Z0.S
andv s0, p7, z0.s
ANDV S0, P7, Z0.S
andv s0, p0, z3.s
ANDV S0, P0, Z3.S
andv s0, p0, z31.s
ANDV S0, P0, Z31.S
andv d0, p0, z0.d
ANDV D0, P0, Z0.D
andv d1, p0, z0.d
ANDV D1, P0, Z0.D
andv d31, p0, z0.d
ANDV D31, P0, Z0.D
andv d0, p2, z0.d
ANDV D0, P2, Z0.D
andv d0, p7, z0.d
ANDV D0, P7, Z0.D
andv d0, p0, z3.d
ANDV D0, P0, Z3.D
andv d0, p0, z31.d
ANDV D0, P0, Z31.D
asr z0.b, z0.b, z0.d
ASR Z0.B, Z0.B, Z0.D
asr z1.b, z0.b, z0.d
ASR Z1.B, Z0.B, Z0.D
asr z31.b, z0.b, z0.d
ASR Z31.B, Z0.B, Z0.D
asr z0.b, z2.b, z0.d
ASR Z0.B, Z2.B, Z0.D
asr z0.b, z31.b, z0.d
ASR Z0.B, Z31.B, Z0.D
asr z0.b, z0.b, z3.d
ASR Z0.B, Z0.B, Z3.D
asr z0.b, z0.b, z31.d
ASR Z0.B, Z0.B, Z31.D
asr z0.h, z0.h, z0.d
ASR Z0.H, Z0.H, Z0.D
asr z1.h, z0.h, z0.d
ASR Z1.H, Z0.H, Z0.D
asr z31.h, z0.h, z0.d
ASR Z31.H, Z0.H, Z0.D
asr z0.h, z2.h, z0.d
ASR Z0.H, Z2.H, Z0.D
asr z0.h, z31.h, z0.d
ASR Z0.H, Z31.H, Z0.D
asr z0.h, z0.h, z3.d
ASR Z0.H, Z0.H, Z3.D
asr z0.h, z0.h, z31.d
ASR Z0.H, Z0.H, Z31.D
asr z0.s, z0.s, z0.d
ASR Z0.S, Z0.S, Z0.D
asr z1.s, z0.s, z0.d
ASR Z1.S, Z0.S, Z0.D
asr z31.s, z0.s, z0.d
ASR Z31.S, Z0.S, Z0.D
asr z0.s, z2.s, z0.d
ASR Z0.S, Z2.S, Z0.D
asr z0.s, z31.s, z0.d
ASR Z0.S, Z31.S, Z0.D
asr z0.s, z0.s, z3.d
ASR Z0.S, Z0.S, Z3.D
asr z0.s, z0.s, z31.d
ASR Z0.S, Z0.S, Z31.D
asr z0.b, z0.b, #8
ASR Z0.B, Z0.B, #8
asr z1.b, z0.b, #8
ASR Z1.B, Z0.B, #8
asr z31.b, z0.b, #8
ASR Z31.B, Z0.B, #8
asr z0.b, z2.b, #8
ASR Z0.B, Z2.B, #8
asr z0.b, z31.b, #8
ASR Z0.B, Z31.B, #8
asr z0.b, z0.b, #7
ASR Z0.B, Z0.B, #7
asr z0.b, z0.b, #2
ASR Z0.B, Z0.B, #2
asr z0.b, z0.b, #1
ASR Z0.B, Z0.B, #1
asr z0.h, z0.h, #16
ASR Z0.H, Z0.H, #16
asr z1.h, z0.h, #16
ASR Z1.H, Z0.H, #16
asr z31.h, z0.h, #16
ASR Z31.H, Z0.H, #16
asr z0.h, z2.h, #16
ASR Z0.H, Z2.H, #16
asr z0.h, z31.h, #16
ASR Z0.H, Z31.H, #16
asr z0.h, z0.h, #15
ASR Z0.H, Z0.H, #15
asr z0.h, z0.h, #2
ASR Z0.H, Z0.H, #2
asr z0.h, z0.h, #1
ASR Z0.H, Z0.H, #1
asr z0.h, z0.h, #8
ASR Z0.H, Z0.H, #8
asr z1.h, z0.h, #8
ASR Z1.H, Z0.H, #8
asr z31.h, z0.h, #8
ASR Z31.H, Z0.H, #8
asr z0.h, z2.h, #8
ASR Z0.H, Z2.H, #8
asr z0.h, z31.h, #8
ASR Z0.H, Z31.H, #8
asr z0.h, z0.h, #7
ASR Z0.H, Z0.H, #7
asr z0.s, z0.s, #18
ASR Z0.S, Z0.S, #18
asr z0.s, z0.s, #17
ASR Z0.S, Z0.S, #17
asr z0.s, z0.s, #32
ASR Z0.S, Z0.S, #32
asr z1.s, z0.s, #32
ASR Z1.S, Z0.S, #32
asr z31.s, z0.s, #32
ASR Z31.S, Z0.S, #32
asr z0.s, z2.s, #32
ASR Z0.S, Z2.S, #32
asr z0.s, z31.s, #32
ASR Z0.S, Z31.S, #32
asr z0.s, z0.s, #31
ASR Z0.S, Z0.S, #31
asr z0.s, z0.s, #2
ASR Z0.S, Z0.S, #2
asr z0.s, z0.s, #1
ASR Z0.S, Z0.S, #1
asr z0.s, z0.s, #24
ASR Z0.S, Z0.S, #24
asr z1.s, z0.s, #24
ASR Z1.S, Z0.S, #24
asr z31.s, z0.s, #24
ASR Z31.S, Z0.S, #24
asr z0.s, z2.s, #24
ASR Z0.S, Z2.S, #24
asr z0.s, z31.s, #24
ASR Z0.S, Z31.S, #24
asr z0.s, z0.s, #23
ASR Z0.S, Z0.S, #23
asr z0.d, z0.d, #50
ASR Z0.D, Z0.D, #50
asr z0.d, z0.d, #49
ASR Z0.D, Z0.D, #49
asr z0.s, z0.s, #16
ASR Z0.S, Z0.S, #16
asr z1.s, z0.s, #16
ASR Z1.S, Z0.S, #16
asr z31.s, z0.s, #16
ASR Z31.S, Z0.S, #16
asr z0.s, z2.s, #16
ASR Z0.S, Z2.S, #16
asr z0.s, z31.s, #16
ASR Z0.S, Z31.S, #16
asr z0.s, z0.s, #15
ASR Z0.S, Z0.S, #15
asr z0.d, z0.d, #34
ASR Z0.D, Z0.D, #34
asr z0.d, z0.d, #33
ASR Z0.D, Z0.D, #33
asr z0.s, z0.s, #8
ASR Z0.S, Z0.S, #8
asr z1.s, z0.s, #8
ASR Z1.S, Z0.S, #8
asr z31.s, z0.s, #8
ASR Z31.S, Z0.S, #8
asr z0.s, z2.s, #8
ASR Z0.S, Z2.S, #8
asr z0.s, z31.s, #8
ASR Z0.S, Z31.S, #8
asr z0.s, z0.s, #7
ASR Z0.S, Z0.S, #7
asr z0.d, z0.d, #18
ASR Z0.D, Z0.D, #18
asr z0.d, z0.d, #17
ASR Z0.D, Z0.D, #17
asr z0.d, z0.d, #64
ASR Z0.D, Z0.D, #64
asr z1.d, z0.d, #64
ASR Z1.D, Z0.D, #64
asr z31.d, z0.d, #64
ASR Z31.D, Z0.D, #64
asr z0.d, z2.d, #64
ASR Z0.D, Z2.D, #64
asr z0.d, z31.d, #64
ASR Z0.D, Z31.D, #64
asr z0.d, z0.d, #63
ASR Z0.D, Z0.D, #63
asr z0.d, z0.d, #2
ASR Z0.D, Z0.D, #2
asr z0.d, z0.d, #1
ASR Z0.D, Z0.D, #1
asr z0.d, z0.d, #56
ASR Z0.D, Z0.D, #56
asr z1.d, z0.d, #56
ASR Z1.D, Z0.D, #56
asr z31.d, z0.d, #56
ASR Z31.D, Z0.D, #56
asr z0.d, z2.d, #56
ASR Z0.D, Z2.D, #56
asr z0.d, z31.d, #56
ASR Z0.D, Z31.D, #56
asr z0.d, z0.d, #55
ASR Z0.D, Z0.D, #55
asr z0.d, z0.d, #48
ASR Z0.D, Z0.D, #48
asr z1.d, z0.d, #48
ASR Z1.D, Z0.D, #48
asr z31.d, z0.d, #48
ASR Z31.D, Z0.D, #48
asr z0.d, z2.d, #48
ASR Z0.D, Z2.D, #48
asr z0.d, z31.d, #48
ASR Z0.D, Z31.D, #48
asr z0.d, z0.d, #47
ASR Z0.D, Z0.D, #47
asr z0.d, z0.d, #40
ASR Z0.D, Z0.D, #40
asr z1.d, z0.d, #40
ASR Z1.D, Z0.D, #40
asr z31.d, z0.d, #40
ASR Z31.D, Z0.D, #40
asr z0.d, z2.d, #40
ASR Z0.D, Z2.D, #40
asr z0.d, z31.d, #40
ASR Z0.D, Z31.D, #40
asr z0.d, z0.d, #39
ASR Z0.D, Z0.D, #39
asr z0.d, z0.d, #32
ASR Z0.D, Z0.D, #32
asr z1.d, z0.d, #32
ASR Z1.D, Z0.D, #32
asr z31.d, z0.d, #32
ASR Z31.D, Z0.D, #32
asr z0.d, z2.d, #32
ASR Z0.D, Z2.D, #32
asr z0.d, z31.d, #32
ASR Z0.D, Z31.D, #32
asr z0.d, z0.d, #31
ASR Z0.D, Z0.D, #31
asr z0.d, z0.d, #24
ASR Z0.D, Z0.D, #24
asr z1.d, z0.d, #24
ASR Z1.D, Z0.D, #24
asr z31.d, z0.d, #24
ASR Z31.D, Z0.D, #24
asr z0.d, z2.d, #24
ASR Z0.D, Z2.D, #24
asr z0.d, z31.d, #24
ASR Z0.D, Z31.D, #24
asr z0.d, z0.d, #23
ASR Z0.D, Z0.D, #23
asr z0.d, z0.d, #16
ASR Z0.D, Z0.D, #16
asr z1.d, z0.d, #16
ASR Z1.D, Z0.D, #16
asr z31.d, z0.d, #16
ASR Z31.D, Z0.D, #16
asr z0.d, z2.d, #16
ASR Z0.D, Z2.D, #16
asr z0.d, z31.d, #16
ASR Z0.D, Z31.D, #16
asr z0.d, z0.d, #15
ASR Z0.D, Z0.D, #15
asr z0.d, z0.d, #8
ASR Z0.D, Z0.D, #8
asr z1.d, z0.d, #8
ASR Z1.D, Z0.D, #8
asr z31.d, z0.d, #8
ASR Z31.D, Z0.D, #8
asr z0.d, z2.d, #8
ASR Z0.D, Z2.D, #8
asr z0.d, z31.d, #8
ASR Z0.D, Z31.D, #8
asr z0.d, z0.d, #7
ASR Z0.D, Z0.D, #7
asr z0.b, p0/m, z0.b, z0.b
ASR Z0.B, P0/M, Z0.B, Z0.B
asr z1.b, p0/m, z1.b, z0.b
ASR Z1.B, P0/M, Z1.B, Z0.B
asr z31.b, p0/m, z31.b, z0.b
ASR Z31.B, P0/M, Z31.B, Z0.B
asr z0.b, p2/m, z0.b, z0.b
ASR Z0.B, P2/M, Z0.B, Z0.B
asr z0.b, p7/m, z0.b, z0.b
ASR Z0.B, P7/M, Z0.B, Z0.B
asr z3.b, p0/m, z3.b, z0.b
ASR Z3.B, P0/M, Z3.B, Z0.B
asr z0.b, p0/m, z0.b, z4.b
ASR Z0.B, P0/M, Z0.B, Z4.B
asr z0.b, p0/m, z0.b, z31.b
ASR Z0.B, P0/M, Z0.B, Z31.B
asr z0.h, p0/m, z0.h, z0.h
ASR Z0.H, P0/M, Z0.H, Z0.H
asr z1.h, p0/m, z1.h, z0.h
ASR Z1.H, P0/M, Z1.H, Z0.H
asr z31.h, p0/m, z31.h, z0.h
ASR Z31.H, P0/M, Z31.H, Z0.H
asr z0.h, p2/m, z0.h, z0.h
ASR Z0.H, P2/M, Z0.H, Z0.H
asr z0.h, p7/m, z0.h, z0.h
ASR Z0.H, P7/M, Z0.H, Z0.H
asr z3.h, p0/m, z3.h, z0.h
ASR Z3.H, P0/M, Z3.H, Z0.H
asr z0.h, p0/m, z0.h, z4.h
ASR Z0.H, P0/M, Z0.H, Z4.H
asr z0.h, p0/m, z0.h, z31.h
ASR Z0.H, P0/M, Z0.H, Z31.H
asr z0.s, p0/m, z0.s, z0.s
ASR Z0.S, P0/M, Z0.S, Z0.S
asr z1.s, p0/m, z1.s, z0.s
ASR Z1.S, P0/M, Z1.S, Z0.S
asr z31.s, p0/m, z31.s, z0.s
ASR Z31.S, P0/M, Z31.S, Z0.S
asr z0.s, p2/m, z0.s, z0.s
ASR Z0.S, P2/M, Z0.S, Z0.S
asr z0.s, p7/m, z0.s, z0.s
ASR Z0.S, P7/M, Z0.S, Z0.S
asr z3.s, p0/m, z3.s, z0.s
ASR Z3.S, P0/M, Z3.S, Z0.S
asr z0.s, p0/m, z0.s, z4.s
ASR Z0.S, P0/M, Z0.S, Z4.S
asr z0.s, p0/m, z0.s, z31.s
ASR Z0.S, P0/M, Z0.S, Z31.S
asr z0.d, p0/m, z0.d, z0.d
ASR Z0.D, P0/M, Z0.D, Z0.D
asr z1.d, p0/m, z1.d, z0.d
ASR Z1.D, P0/M, Z1.D, Z0.D
asr z31.d, p0/m, z31.d, z0.d
ASR Z31.D, P0/M, Z31.D, Z0.D
asr z0.d, p2/m, z0.d, z0.d
ASR Z0.D, P2/M, Z0.D, Z0.D
asr z0.d, p7/m, z0.d, z0.d
ASR Z0.D, P7/M, Z0.D, Z0.D
asr z3.d, p0/m, z3.d, z0.d
ASR Z3.D, P0/M, Z3.D, Z0.D
asr z0.d, p0/m, z0.d, z4.d
ASR Z0.D, P0/M, Z0.D, Z4.D
asr z0.d, p0/m, z0.d, z31.d
ASR Z0.D, P0/M, Z0.D, Z31.D
asr z0.b, p0/m, z0.b, z0.d
ASR Z0.B, P0/M, Z0.B, Z0.D
asr z1.b, p0/m, z1.b, z0.d
ASR Z1.B, P0/M, Z1.B, Z0.D
asr z31.b, p0/m, z31.b, z0.d
ASR Z31.B, P0/M, Z31.B, Z0.D
asr z0.b, p2/m, z0.b, z0.d
ASR Z0.B, P2/M, Z0.B, Z0.D
asr z0.b, p7/m, z0.b, z0.d
ASR Z0.B, P7/M, Z0.B, Z0.D
asr z3.b, p0/m, z3.b, z0.d
ASR Z3.B, P0/M, Z3.B, Z0.D
asr z0.b, p0/m, z0.b, z4.d
ASR Z0.B, P0/M, Z0.B, Z4.D
asr z0.b, p0/m, z0.b, z31.d
ASR Z0.B, P0/M, Z0.B, Z31.D
asr z0.h, p0/m, z0.h, z0.d
ASR Z0.H, P0/M, Z0.H, Z0.D
asr z1.h, p0/m, z1.h, z0.d
ASR Z1.H, P0/M, Z1.H, Z0.D
asr z31.h, p0/m, z31.h, z0.d
ASR Z31.H, P0/M, Z31.H, Z0.D
asr z0.h, p2/m, z0.h, z0.d
ASR Z0.H, P2/M, Z0.H, Z0.D
asr z0.h, p7/m, z0.h, z0.d
ASR Z0.H, P7/M, Z0.H, Z0.D
asr z3.h, p0/m, z3.h, z0.d
ASR Z3.H, P0/M, Z3.H, Z0.D
asr z0.h, p0/m, z0.h, z4.d
ASR Z0.H, P0/M, Z0.H, Z4.D
asr z0.h, p0/m, z0.h, z31.d
ASR Z0.H, P0/M, Z0.H, Z31.D
asr z0.s, p0/m, z0.s, z0.d
ASR Z0.S, P0/M, Z0.S, Z0.D
asr z1.s, p0/m, z1.s, z0.d
ASR Z1.S, P0/M, Z1.S, Z0.D
asr z31.s, p0/m, z31.s, z0.d
ASR Z31.S, P0/M, Z31.S, Z0.D
asr z0.s, p2/m, z0.s, z0.d
ASR Z0.S, P2/M, Z0.S, Z0.D
asr z0.s, p7/m, z0.s, z0.d
ASR Z0.S, P7/M, Z0.S, Z0.D
asr z3.s, p0/m, z3.s, z0.d
ASR Z3.S, P0/M, Z3.S, Z0.D
asr z0.s, p0/m, z0.s, z4.d
ASR Z0.S, P0/M, Z0.S, Z4.D
asr z0.s, p0/m, z0.s, z31.d
ASR Z0.S, P0/M, Z0.S, Z31.D
asr z0.b, p0/m, z0.b, #8
ASR Z0.B, P0/M, Z0.B, #8
asr z1.b, p0/m, z1.b, #8
ASR Z1.B, P0/M, Z1.B, #8
asr z31.b, p0/m, z31.b, #8
ASR Z31.B, P0/M, Z31.B, #8
asr z0.b, p2/m, z0.b, #8
ASR Z0.B, P2/M, Z0.B, #8
asr z0.b, p7/m, z0.b, #8
ASR Z0.B, P7/M, Z0.B, #8
asr z3.b, p0/m, z3.b, #8
ASR Z3.B, P0/M, Z3.B, #8
asr z0.b, p0/m, z0.b, #7
ASR Z0.B, P0/M, Z0.B, #7
asr z0.b, p0/m, z0.b, #2
ASR Z0.B, P0/M, Z0.B, #2
asr z0.b, p0/m, z0.b, #1
ASR Z0.B, P0/M, Z0.B, #1
asr z0.h, p0/m, z0.h, #16
ASR Z0.H, P0/M, Z0.H, #16
asr z1.h, p0/m, z1.h, #16
ASR Z1.H, P0/M, Z1.H, #16
asr z31.h, p0/m, z31.h, #16
ASR Z31.H, P0/M, Z31.H, #16
asr z0.h, p2/m, z0.h, #16
ASR Z0.H, P2/M, Z0.H, #16
asr z0.h, p7/m, z0.h, #16
ASR Z0.H, P7/M, Z0.H, #16
asr z3.h, p0/m, z3.h, #16
ASR Z3.H, P0/M, Z3.H, #16
asr z0.h, p0/m, z0.h, #15
ASR Z0.H, P0/M, Z0.H, #15
asr z0.h, p0/m, z0.h, #2
ASR Z0.H, P0/M, Z0.H, #2
asr z0.h, p0/m, z0.h, #1
ASR Z0.H, P0/M, Z0.H, #1
asr z0.h, p0/m, z0.h, #8
ASR Z0.H, P0/M, Z0.H, #8
asr z1.h, p0/m, z1.h, #8
ASR Z1.H, P0/M, Z1.H, #8
asr z31.h, p0/m, z31.h, #8
ASR Z31.H, P0/M, Z31.H, #8
asr z0.h, p2/m, z0.h, #8
ASR Z0.H, P2/M, Z0.H, #8
asr z0.h, p7/m, z0.h, #8
ASR Z0.H, P7/M, Z0.H, #8
asr z3.h, p0/m, z3.h, #8
ASR Z3.H, P0/M, Z3.H, #8
asr z0.h, p0/m, z0.h, #7
ASR Z0.H, P0/M, Z0.H, #7
asr z0.s, p0/m, z0.s, #18
ASR Z0.S, P0/M, Z0.S, #18
asr z0.s, p0/m, z0.s, #17
ASR Z0.S, P0/M, Z0.S, #17
asr z0.s, p0/m, z0.s, #32
ASR Z0.S, P0/M, Z0.S, #32
asr z1.s, p0/m, z1.s, #32
ASR Z1.S, P0/M, Z1.S, #32
asr z31.s, p0/m, z31.s, #32
ASR Z31.S, P0/M, Z31.S, #32
asr z0.s, p2/m, z0.s, #32
ASR Z0.S, P2/M, Z0.S, #32
asr z0.s, p7/m, z0.s, #32
ASR Z0.S, P7/M, Z0.S, #32
asr z3.s, p0/m, z3.s, #32
ASR Z3.S, P0/M, Z3.S, #32
asr z0.s, p0/m, z0.s, #31
ASR Z0.S, P0/M, Z0.S, #31
asr z0.s, p0/m, z0.s, #2
ASR Z0.S, P0/M, Z0.S, #2
asr z0.s, p0/m, z0.s, #1
ASR Z0.S, P0/M, Z0.S, #1
asr z0.s, p0/m, z0.s, #24
ASR Z0.S, P0/M, Z0.S, #24
asr z1.s, p0/m, z1.s, #24
ASR Z1.S, P0/M, Z1.S, #24
asr z31.s, p0/m, z31.s, #24
ASR Z31.S, P0/M, Z31.S, #24
asr z0.s, p2/m, z0.s, #24
ASR Z0.S, P2/M, Z0.S, #24
asr z0.s, p7/m, z0.s, #24
ASR Z0.S, P7/M, Z0.S, #24
asr z3.s, p0/m, z3.s, #24
ASR Z3.S, P0/M, Z3.S, #24
asr z0.s, p0/m, z0.s, #23
ASR Z0.S, P0/M, Z0.S, #23
asr z0.d, p0/m, z0.d, #50
ASR Z0.D, P0/M, Z0.D, #50
asr z0.d, p0/m, z0.d, #49
ASR Z0.D, P0/M, Z0.D, #49
asr z0.s, p0/m, z0.s, #16
ASR Z0.S, P0/M, Z0.S, #16
asr z1.s, p0/m, z1.s, #16
ASR Z1.S, P0/M, Z1.S, #16
asr z31.s, p0/m, z31.s, #16
ASR Z31.S, P0/M, Z31.S, #16
asr z0.s, p2/m, z0.s, #16
ASR Z0.S, P2/M, Z0.S, #16
asr z0.s, p7/m, z0.s, #16
ASR Z0.S, P7/M, Z0.S, #16
asr z3.s, p0/m, z3.s, #16
ASR Z3.S, P0/M, Z3.S, #16
asr z0.s, p0/m, z0.s, #15
ASR Z0.S, P0/M, Z0.S, #15
asr z0.d, p0/m, z0.d, #34
ASR Z0.D, P0/M, Z0.D, #34
asr z0.d, p0/m, z0.d, #33
ASR Z0.D, P0/M, Z0.D, #33
asr z0.s, p0/m, z0.s, #8
ASR Z0.S, P0/M, Z0.S, #8
asr z1.s, p0/m, z1.s, #8
ASR Z1.S, P0/M, Z1.S, #8
asr z31.s, p0/m, z31.s, #8
ASR Z31.S, P0/M, Z31.S, #8
asr z0.s, p2/m, z0.s, #8
ASR Z0.S, P2/M, Z0.S, #8
asr z0.s, p7/m, z0.s, #8
ASR Z0.S, P7/M, Z0.S, #8
asr z3.s, p0/m, z3.s, #8
ASR Z3.S, P0/M, Z3.S, #8
asr z0.s, p0/m, z0.s, #7
ASR Z0.S, P0/M, Z0.S, #7
asr z0.d, p0/m, z0.d, #18
ASR Z0.D, P0/M, Z0.D, #18
asr z0.d, p0/m, z0.d, #17
ASR Z0.D, P0/M, Z0.D, #17
asr z0.d, p0/m, z0.d, #64
ASR Z0.D, P0/M, Z0.D, #64
asr z1.d, p0/m, z1.d, #64
ASR Z1.D, P0/M, Z1.D, #64
asr z31.d, p0/m, z31.d, #64
ASR Z31.D, P0/M, Z31.D, #64
asr z0.d, p2/m, z0.d, #64
ASR Z0.D, P2/M, Z0.D, #64
asr z0.d, p7/m, z0.d, #64
ASR Z0.D, P7/M, Z0.D, #64
asr z3.d, p0/m, z3.d, #64
ASR Z3.D, P0/M, Z3.D, #64
asr z0.d, p0/m, z0.d, #63
ASR Z0.D, P0/M, Z0.D, #63
asr z0.d, p0/m, z0.d, #2
ASR Z0.D, P0/M, Z0.D, #2
asr z0.d, p0/m, z0.d, #1
ASR Z0.D, P0/M, Z0.D, #1
asr z0.d, p0/m, z0.d, #56
ASR Z0.D, P0/M, Z0.D, #56
asr z1.d, p0/m, z1.d, #56
ASR Z1.D, P0/M, Z1.D, #56
asr z31.d, p0/m, z31.d, #56
ASR Z31.D, P0/M, Z31.D, #56
asr z0.d, p2/m, z0.d, #56
ASR Z0.D, P2/M, Z0.D, #56
asr z0.d, p7/m, z0.d, #56
ASR Z0.D, P7/M, Z0.D, #56
asr z3.d, p0/m, z3.d, #56
ASR Z3.D, P0/M, Z3.D, #56
asr z0.d, p0/m, z0.d, #55
ASR Z0.D, P0/M, Z0.D, #55
asr z0.d, p0/m, z0.d, #48
ASR Z0.D, P0/M, Z0.D, #48
asr z1.d, p0/m, z1.d, #48
ASR Z1.D, P0/M, Z1.D, #48
asr z31.d, p0/m, z31.d, #48
ASR Z31.D, P0/M, Z31.D, #48
asr z0.d, p2/m, z0.d, #48
ASR Z0.D, P2/M, Z0.D, #48
asr z0.d, p7/m, z0.d, #48
ASR Z0.D, P7/M, Z0.D, #48
asr z3.d, p0/m, z3.d, #48
ASR Z3.D, P0/M, Z3.D, #48
asr z0.d, p0/m, z0.d, #47
ASR Z0.D, P0/M, Z0.D, #47
asr z0.d, p0/m, z0.d, #40
ASR Z0.D, P0/M, Z0.D, #40
asr z1.d, p0/m, z1.d, #40
ASR Z1.D, P0/M, Z1.D, #40
asr z31.d, p0/m, z31.d, #40
ASR Z31.D, P0/M, Z31.D, #40
asr z0.d, p2/m, z0.d, #40
ASR Z0.D, P2/M, Z0.D, #40
asr z0.d, p7/m, z0.d, #40
ASR Z0.D, P7/M, Z0.D, #40
asr z3.d, p0/m, z3.d, #40
ASR Z3.D, P0/M, Z3.D, #40
asr z0.d, p0/m, z0.d, #39
ASR Z0.D, P0/M, Z0.D, #39
asr z0.d, p0/m, z0.d, #32
ASR Z0.D, P0/M, Z0.D, #32
asr z1.d, p0/m, z1.d, #32
ASR Z1.D, P0/M, Z1.D, #32
asr z31.d, p0/m, z31.d, #32
ASR Z31.D, P0/M, Z31.D, #32
asr z0.d, p2/m, z0.d, #32
ASR Z0.D, P2/M, Z0.D, #32
asr z0.d, p7/m, z0.d, #32
ASR Z0.D, P7/M, Z0.D, #32
asr z3.d, p0/m, z3.d, #32
ASR Z3.D, P0/M, Z3.D, #32
asr z0.d, p0/m, z0.d, #31
ASR Z0.D, P0/M, Z0.D, #31
asr z0.d, p0/m, z0.d, #24
ASR Z0.D, P0/M, Z0.D, #24
asr z1.d, p0/m, z1.d, #24
ASR Z1.D, P0/M, Z1.D, #24
asr z31.d, p0/m, z31.d, #24
ASR Z31.D, P0/M, Z31.D, #24
asr z0.d, p2/m, z0.d, #24
ASR Z0.D, P2/M, Z0.D, #24
asr z0.d, p7/m, z0.d, #24
ASR Z0.D, P7/M, Z0.D, #24
asr z3.d, p0/m, z3.d, #24
ASR Z3.D, P0/M, Z3.D, #24
asr z0.d, p0/m, z0.d, #23
ASR Z0.D, P0/M, Z0.D, #23
asr z0.d, p0/m, z0.d, #16
ASR Z0.D, P0/M, Z0.D, #16
asr z1.d, p0/m, z1.d, #16
ASR Z1.D, P0/M, Z1.D, #16
asr z31.d, p0/m, z31.d, #16
ASR Z31.D, P0/M, Z31.D, #16
asr z0.d, p2/m, z0.d, #16
ASR Z0.D, P2/M, Z0.D, #16
asr z0.d, p7/m, z0.d, #16
ASR Z0.D, P7/M, Z0.D, #16
asr z3.d, p0/m, z3.d, #16
ASR Z3.D, P0/M, Z3.D, #16
asr z0.d, p0/m, z0.d, #15
ASR Z0.D, P0/M, Z0.D, #15
asr z0.d, p0/m, z0.d, #8
ASR Z0.D, P0/M, Z0.D, #8
asr z1.d, p0/m, z1.d, #8
ASR Z1.D, P0/M, Z1.D, #8
asr z31.d, p0/m, z31.d, #8
ASR Z31.D, P0/M, Z31.D, #8
asr z0.d, p2/m, z0.d, #8
ASR Z0.D, P2/M, Z0.D, #8
asr z0.d, p7/m, z0.d, #8
ASR Z0.D, P7/M, Z0.D, #8
asr z3.d, p0/m, z3.d, #8
ASR Z3.D, P0/M, Z3.D, #8
asr z0.d, p0/m, z0.d, #7
ASR Z0.D, P0/M, Z0.D, #7
asrd z0.b, p0/m, z0.b, #8
ASRD Z0.B, P0/M, Z0.B, #8
asrd z1.b, p0/m, z1.b, #8
ASRD Z1.B, P0/M, Z1.B, #8
asrd z31.b, p0/m, z31.b, #8
ASRD Z31.B, P0/M, Z31.B, #8
asrd z0.b, p2/m, z0.b, #8
ASRD Z0.B, P2/M, Z0.B, #8
asrd z0.b, p7/m, z0.b, #8
ASRD Z0.B, P7/M, Z0.B, #8
asrd z3.b, p0/m, z3.b, #8
ASRD Z3.B, P0/M, Z3.B, #8
asrd z0.b, p0/m, z0.b, #7
ASRD Z0.B, P0/M, Z0.B, #7
asrd z0.b, p0/m, z0.b, #2
ASRD Z0.B, P0/M, Z0.B, #2
asrd z0.b, p0/m, z0.b, #1
ASRD Z0.B, P0/M, Z0.B, #1
asrd z0.h, p0/m, z0.h, #16
ASRD Z0.H, P0/M, Z0.H, #16
asrd z1.h, p0/m, z1.h, #16
ASRD Z1.H, P0/M, Z1.H, #16
asrd z31.h, p0/m, z31.h, #16
ASRD Z31.H, P0/M, Z31.H, #16
asrd z0.h, p2/m, z0.h, #16
ASRD Z0.H, P2/M, Z0.H, #16
asrd z0.h, p7/m, z0.h, #16
ASRD Z0.H, P7/M, Z0.H, #16
asrd z3.h, p0/m, z3.h, #16
ASRD Z3.H, P0/M, Z3.H, #16
asrd z0.h, p0/m, z0.h, #15
ASRD Z0.H, P0/M, Z0.H, #15
asrd z0.h, p0/m, z0.h, #2
ASRD Z0.H, P0/M, Z0.H, #2
asrd z0.h, p0/m, z0.h, #1
ASRD Z0.H, P0/M, Z0.H, #1
asrd z0.h, p0/m, z0.h, #8
ASRD Z0.H, P0/M, Z0.H, #8
asrd z1.h, p0/m, z1.h, #8
ASRD Z1.H, P0/M, Z1.H, #8
asrd z31.h, p0/m, z31.h, #8
ASRD Z31.H, P0/M, Z31.H, #8
asrd z0.h, p2/m, z0.h, #8
ASRD Z0.H, P2/M, Z0.H, #8
asrd z0.h, p7/m, z0.h, #8
ASRD Z0.H, P7/M, Z0.H, #8
asrd z3.h, p0/m, z3.h, #8
ASRD Z3.H, P0/M, Z3.H, #8
asrd z0.h, p0/m, z0.h, #7
ASRD Z0.H, P0/M, Z0.H, #7
asrd z0.s, p0/m, z0.s, #18
ASRD Z0.S, P0/M, Z0.S, #18
asrd z0.s, p0/m, z0.s, #17
ASRD Z0.S, P0/M, Z0.S, #17
asrd z0.s, p0/m, z0.s, #32
ASRD Z0.S, P0/M, Z0.S, #32
asrd z1.s, p0/m, z1.s, #32
ASRD Z1.S, P0/M, Z1.S, #32
asrd z31.s, p0/m, z31.s, #32
ASRD Z31.S, P0/M, Z31.S, #32
asrd z0.s, p2/m, z0.s, #32
ASRD Z0.S, P2/M, Z0.S, #32
asrd z0.s, p7/m, z0.s, #32
ASRD Z0.S, P7/M, Z0.S, #32
asrd z3.s, p0/m, z3.s, #32
ASRD Z3.S, P0/M, Z3.S, #32
asrd z0.s, p0/m, z0.s, #31
ASRD Z0.S, P0/M, Z0.S, #31
asrd z0.s, p0/m, z0.s, #2
ASRD Z0.S, P0/M, Z0.S, #2
asrd z0.s, p0/m, z0.s, #1
ASRD Z0.S, P0/M, Z0.S, #1
asrd z0.s, p0/m, z0.s, #24
ASRD Z0.S, P0/M, Z0.S, #24
asrd z1.s, p0/m, z1.s, #24
ASRD Z1.S, P0/M, Z1.S, #24
asrd z31.s, p0/m, z31.s, #24
ASRD Z31.S, P0/M, Z31.S, #24
asrd z0.s, p2/m, z0.s, #24
ASRD Z0.S, P2/M, Z0.S, #24
asrd z0.s, p7/m, z0.s, #24
ASRD Z0.S, P7/M, Z0.S, #24
asrd z3.s, p0/m, z3.s, #24
ASRD Z3.S, P0/M, Z3.S, #24
asrd z0.s, p0/m, z0.s, #23
ASRD Z0.S, P0/M, Z0.S, #23
asrd z0.d, p0/m, z0.d, #50
ASRD Z0.D, P0/M, Z0.D, #50
asrd z0.d, p0/m, z0.d, #49
ASRD Z0.D, P0/M, Z0.D, #49
asrd z0.s, p0/m, z0.s, #16
ASRD Z0.S, P0/M, Z0.S, #16
asrd z1.s, p0/m, z1.s, #16
ASRD Z1.S, P0/M, Z1.S, #16
asrd z31.s, p0/m, z31.s, #16
ASRD Z31.S, P0/M, Z31.S, #16
asrd z0.s, p2/m, z0.s, #16
ASRD Z0.S, P2/M, Z0.S, #16
asrd z0.s, p7/m, z0.s, #16
ASRD Z0.S, P7/M, Z0.S, #16
asrd z3.s, p0/m, z3.s, #16
ASRD Z3.S, P0/M, Z3.S, #16
asrd z0.s, p0/m, z0.s, #15
ASRD Z0.S, P0/M, Z0.S, #15
asrd z0.d, p0/m, z0.d, #34
ASRD Z0.D, P0/M, Z0.D, #34
asrd z0.d, p0/m, z0.d, #33
ASRD Z0.D, P0/M, Z0.D, #33
asrd z0.s, p0/m, z0.s, #8
ASRD Z0.S, P0/M, Z0.S, #8
asrd z1.s, p0/m, z1.s, #8
ASRD Z1.S, P0/M, Z1.S, #8
asrd z31.s, p0/m, z31.s, #8
ASRD Z31.S, P0/M, Z31.S, #8
asrd z0.s, p2/m, z0.s, #8
ASRD Z0.S, P2/M, Z0.S, #8
asrd z0.s, p7/m, z0.s, #8
ASRD Z0.S, P7/M, Z0.S, #8
asrd z3.s, p0/m, z3.s, #8
ASRD Z3.S, P0/M, Z3.S, #8
asrd z0.s, p0/m, z0.s, #7
ASRD Z0.S, P0/M, Z0.S, #7
asrd z0.d, p0/m, z0.d, #18
ASRD Z0.D, P0/M, Z0.D, #18
asrd z0.d, p0/m, z0.d, #17
ASRD Z0.D, P0/M, Z0.D, #17
asrd z0.d, p0/m, z0.d, #64
ASRD Z0.D, P0/M, Z0.D, #64
asrd z1.d, p0/m, z1.d, #64
ASRD Z1.D, P0/M, Z1.D, #64
asrd z31.d, p0/m, z31.d, #64
ASRD Z31.D, P0/M, Z31.D, #64
asrd z0.d, p2/m, z0.d, #64
ASRD Z0.D, P2/M, Z0.D, #64
asrd z0.d, p7/m, z0.d, #64
ASRD Z0.D, P7/M, Z0.D, #64
asrd z3.d, p0/m, z3.d, #64
ASRD Z3.D, P0/M, Z3.D, #64
asrd z0.d, p0/m, z0.d, #63
ASRD Z0.D, P0/M, Z0.D, #63
asrd z0.d, p0/m, z0.d, #2
ASRD Z0.D, P0/M, Z0.D, #2
asrd z0.d, p0/m, z0.d, #1
ASRD Z0.D, P0/M, Z0.D, #1
asrd z0.d, p0/m, z0.d, #56
ASRD Z0.D, P0/M, Z0.D, #56
asrd z1.d, p0/m, z1.d, #56
ASRD Z1.D, P0/M, Z1.D, #56
asrd z31.d, p0/m, z31.d, #56
ASRD Z31.D, P0/M, Z31.D, #56
asrd z0.d, p2/m, z0.d, #56
ASRD Z0.D, P2/M, Z0.D, #56
asrd z0.d, p7/m, z0.d, #56
ASRD Z0.D, P7/M, Z0.D, #56
asrd z3.d, p0/m, z3.d, #56
ASRD Z3.D, P0/M, Z3.D, #56
asrd z0.d, p0/m, z0.d, #55
ASRD Z0.D, P0/M, Z0.D, #55
asrd z0.d, p0/m, z0.d, #48
ASRD Z0.D, P0/M, Z0.D, #48
asrd z1.d, p0/m, z1.d, #48
ASRD Z1.D, P0/M, Z1.D, #48
asrd z31.d, p0/m, z31.d, #48
ASRD Z31.D, P0/M, Z31.D, #48
asrd z0.d, p2/m, z0.d, #48
ASRD Z0.D, P2/M, Z0.D, #48
asrd z0.d, p7/m, z0.d, #48
ASRD Z0.D, P7/M, Z0.D, #48
asrd z3.d, p0/m, z3.d, #48
ASRD Z3.D, P0/M, Z3.D, #48
asrd z0.d, p0/m, z0.d, #47
ASRD Z0.D, P0/M, Z0.D, #47
asrd z0.d, p0/m, z0.d, #40
ASRD Z0.D, P0/M, Z0.D, #40
asrd z1.d, p0/m, z1.d, #40
ASRD Z1.D, P0/M, Z1.D, #40
asrd z31.d, p0/m, z31.d, #40
ASRD Z31.D, P0/M, Z31.D, #40
asrd z0.d, p2/m, z0.d, #40
ASRD Z0.D, P2/M, Z0.D, #40
asrd z0.d, p7/m, z0.d, #40
ASRD Z0.D, P7/M, Z0.D, #40
asrd z3.d, p0/m, z3.d, #40
ASRD Z3.D, P0/M, Z3.D, #40
asrd z0.d, p0/m, z0.d, #39
ASRD Z0.D, P0/M, Z0.D, #39
asrd z0.d, p0/m, z0.d, #32
ASRD Z0.D, P0/M, Z0.D, #32
asrd z1.d, p0/m, z1.d, #32
ASRD Z1.D, P0/M, Z1.D, #32
asrd z31.d, p0/m, z31.d, #32
ASRD Z31.D, P0/M, Z31.D, #32
asrd z0.d, p2/m, z0.d, #32
ASRD Z0.D, P2/M, Z0.D, #32
asrd z0.d, p7/m, z0.d, #32
ASRD Z0.D, P7/M, Z0.D, #32
asrd z3.d, p0/m, z3.d, #32
ASRD Z3.D, P0/M, Z3.D, #32
asrd z0.d, p0/m, z0.d, #31
ASRD Z0.D, P0/M, Z0.D, #31
asrd z0.d, p0/m, z0.d, #24
ASRD Z0.D, P0/M, Z0.D, #24
asrd z1.d, p0/m, z1.d, #24
ASRD Z1.D, P0/M, Z1.D, #24
asrd z31.d, p0/m, z31.d, #24
ASRD Z31.D, P0/M, Z31.D, #24
asrd z0.d, p2/m, z0.d, #24
ASRD Z0.D, P2/M, Z0.D, #24
asrd z0.d, p7/m, z0.d, #24
ASRD Z0.D, P7/M, Z0.D, #24
asrd z3.d, p0/m, z3.d, #24
ASRD Z3.D, P0/M, Z3.D, #24
asrd z0.d, p0/m, z0.d, #23
ASRD Z0.D, P0/M, Z0.D, #23
asrd z0.d, p0/m, z0.d, #16
ASRD Z0.D, P0/M, Z0.D, #16
asrd z1.d, p0/m, z1.d, #16
ASRD Z1.D, P0/M, Z1.D, #16
asrd z31.d, p0/m, z31.d, #16
ASRD Z31.D, P0/M, Z31.D, #16
asrd z0.d, p2/m, z0.d, #16
ASRD Z0.D, P2/M, Z0.D, #16
asrd z0.d, p7/m, z0.d, #16
ASRD Z0.D, P7/M, Z0.D, #16
asrd z3.d, p0/m, z3.d, #16
ASRD Z3.D, P0/M, Z3.D, #16
asrd z0.d, p0/m, z0.d, #15
ASRD Z0.D, P0/M, Z0.D, #15
asrd z0.d, p0/m, z0.d, #8
ASRD Z0.D, P0/M, Z0.D, #8
asrd z1.d, p0/m, z1.d, #8
ASRD Z1.D, P0/M, Z1.D, #8
asrd z31.d, p0/m, z31.d, #8
ASRD Z31.D, P0/M, Z31.D, #8
asrd z0.d, p2/m, z0.d, #8
ASRD Z0.D, P2/M, Z0.D, #8
asrd z0.d, p7/m, z0.d, #8
ASRD Z0.D, P7/M, Z0.D, #8
asrd z3.d, p0/m, z3.d, #8
ASRD Z3.D, P0/M, Z3.D, #8
asrd z0.d, p0/m, z0.d, #7
ASRD Z0.D, P0/M, Z0.D, #7
asrr z0.b, p0/m, z0.b, z0.b
ASRR Z0.B, P0/M, Z0.B, Z0.B
asrr z1.b, p0/m, z1.b, z0.b
ASRR Z1.B, P0/M, Z1.B, Z0.B
asrr z31.b, p0/m, z31.b, z0.b
ASRR Z31.B, P0/M, Z31.B, Z0.B
asrr z0.b, p2/m, z0.b, z0.b
ASRR Z0.B, P2/M, Z0.B, Z0.B
asrr z0.b, p7/m, z0.b, z0.b
ASRR Z0.B, P7/M, Z0.B, Z0.B
asrr z3.b, p0/m, z3.b, z0.b
ASRR Z3.B, P0/M, Z3.B, Z0.B
asrr z0.b, p0/m, z0.b, z4.b
ASRR Z0.B, P0/M, Z0.B, Z4.B
asrr z0.b, p0/m, z0.b, z31.b
ASRR Z0.B, P0/M, Z0.B, Z31.B
asrr z0.h, p0/m, z0.h, z0.h
ASRR Z0.H, P0/M, Z0.H, Z0.H
asrr z1.h, p0/m, z1.h, z0.h
ASRR Z1.H, P0/M, Z1.H, Z0.H
asrr z31.h, p0/m, z31.h, z0.h
ASRR Z31.H, P0/M, Z31.H, Z0.H
asrr z0.h, p2/m, z0.h, z0.h
ASRR Z0.H, P2/M, Z0.H, Z0.H
asrr z0.h, p7/m, z0.h, z0.h
ASRR Z0.H, P7/M, Z0.H, Z0.H
asrr z3.h, p0/m, z3.h, z0.h
ASRR Z3.H, P0/M, Z3.H, Z0.H
asrr z0.h, p0/m, z0.h, z4.h
ASRR Z0.H, P0/M, Z0.H, Z4.H
asrr z0.h, p0/m, z0.h, z31.h
ASRR Z0.H, P0/M, Z0.H, Z31.H
asrr z0.s, p0/m, z0.s, z0.s
ASRR Z0.S, P0/M, Z0.S, Z0.S
asrr z1.s, p0/m, z1.s, z0.s
ASRR Z1.S, P0/M, Z1.S, Z0.S
asrr z31.s, p0/m, z31.s, z0.s
ASRR Z31.S, P0/M, Z31.S, Z0.S
asrr z0.s, p2/m, z0.s, z0.s
ASRR Z0.S, P2/M, Z0.S, Z0.S
asrr z0.s, p7/m, z0.s, z0.s
ASRR Z0.S, P7/M, Z0.S, Z0.S
asrr z3.s, p0/m, z3.s, z0.s
ASRR Z3.S, P0/M, Z3.S, Z0.S
asrr z0.s, p0/m, z0.s, z4.s
ASRR Z0.S, P0/M, Z0.S, Z4.S
asrr z0.s, p0/m, z0.s, z31.s
ASRR Z0.S, P0/M, Z0.S, Z31.S
asrr z0.d, p0/m, z0.d, z0.d
ASRR Z0.D, P0/M, Z0.D, Z0.D
asrr z1.d, p0/m, z1.d, z0.d
ASRR Z1.D, P0/M, Z1.D, Z0.D
asrr z31.d, p0/m, z31.d, z0.d
ASRR Z31.D, P0/M, Z31.D, Z0.D
asrr z0.d, p2/m, z0.d, z0.d
ASRR Z0.D, P2/M, Z0.D, Z0.D
asrr z0.d, p7/m, z0.d, z0.d
ASRR Z0.D, P7/M, Z0.D, Z0.D
asrr z3.d, p0/m, z3.d, z0.d
ASRR Z3.D, P0/M, Z3.D, Z0.D
asrr z0.d, p0/m, z0.d, z4.d
ASRR Z0.D, P0/M, Z0.D, Z4.D
asrr z0.d, p0/m, z0.d, z31.d
ASRR Z0.D, P0/M, Z0.D, Z31.D
bic z0.d, z0.d, z0.d
BIC Z0.D, Z0.D, Z0.D
bic z1.d, z0.d, z0.d
BIC Z1.D, Z0.D, Z0.D
bic z31.d, z0.d, z0.d
BIC Z31.D, Z0.D, Z0.D
bic z0.d, z2.d, z0.d
BIC Z0.D, Z2.D, Z0.D
bic z0.d, z31.d, z0.d
BIC Z0.D, Z31.D, Z0.D
bic z0.d, z0.d, z3.d
BIC Z0.D, Z0.D, Z3.D
bic z0.d, z0.d, z31.d
BIC Z0.D, Z0.D, Z31.D
bic z0.b, p0/m, z0.b, z0.b
BIC Z0.B, P0/M, Z0.B, Z0.B
bic z1.b, p0/m, z1.b, z0.b
BIC Z1.B, P0/M, Z1.B, Z0.B
bic z31.b, p0/m, z31.b, z0.b
BIC Z31.B, P0/M, Z31.B, Z0.B
bic z0.b, p2/m, z0.b, z0.b
BIC Z0.B, P2/M, Z0.B, Z0.B
bic z0.b, p7/m, z0.b, z0.b
BIC Z0.B, P7/M, Z0.B, Z0.B
bic z3.b, p0/m, z3.b, z0.b
BIC Z3.B, P0/M, Z3.B, Z0.B
bic z0.b, p0/m, z0.b, z4.b
BIC Z0.B, P0/M, Z0.B, Z4.B
bic z0.b, p0/m, z0.b, z31.b
BIC Z0.B, P0/M, Z0.B, Z31.B
bic z0.h, p0/m, z0.h, z0.h
BIC Z0.H, P0/M, Z0.H, Z0.H
bic z1.h, p0/m, z1.h, z0.h
BIC Z1.H, P0/M, Z1.H, Z0.H
bic z31.h, p0/m, z31.h, z0.h
BIC Z31.H, P0/M, Z31.H, Z0.H
bic z0.h, p2/m, z0.h, z0.h
BIC Z0.H, P2/M, Z0.H, Z0.H
bic z0.h, p7/m, z0.h, z0.h
BIC Z0.H, P7/M, Z0.H, Z0.H
bic z3.h, p0/m, z3.h, z0.h
BIC Z3.H, P0/M, Z3.H, Z0.H
bic z0.h, p0/m, z0.h, z4.h
BIC Z0.H, P0/M, Z0.H, Z4.H
bic z0.h, p0/m, z0.h, z31.h
BIC Z0.H, P0/M, Z0.H, Z31.H
bic z0.s, p0/m, z0.s, z0.s
BIC Z0.S, P0/M, Z0.S, Z0.S
bic z1.s, p0/m, z1.s, z0.s
BIC Z1.S, P0/M, Z1.S, Z0.S
bic z31.s, p0/m, z31.s, z0.s
BIC Z31.S, P0/M, Z31.S, Z0.S
bic z0.s, p2/m, z0.s, z0.s
BIC Z0.S, P2/M, Z0.S, Z0.S
bic z0.s, p7/m, z0.s, z0.s
BIC Z0.S, P7/M, Z0.S, Z0.S
bic z3.s, p0/m, z3.s, z0.s
BIC Z3.S, P0/M, Z3.S, Z0.S
bic z0.s, p0/m, z0.s, z4.s
BIC Z0.S, P0/M, Z0.S, Z4.S
bic z0.s, p0/m, z0.s, z31.s
BIC Z0.S, P0/M, Z0.S, Z31.S
bic z0.d, p0/m, z0.d, z0.d
BIC Z0.D, P0/M, Z0.D, Z0.D
bic z1.d, p0/m, z1.d, z0.d
BIC Z1.D, P0/M, Z1.D, Z0.D
bic z31.d, p0/m, z31.d, z0.d
BIC Z31.D, P0/M, Z31.D, Z0.D
bic z0.d, p2/m, z0.d, z0.d
BIC Z0.D, P2/M, Z0.D, Z0.D
bic z0.d, p7/m, z0.d, z0.d
BIC Z0.D, P7/M, Z0.D, Z0.D
bic z3.d, p0/m, z3.d, z0.d
BIC Z3.D, P0/M, Z3.D, Z0.D
bic z0.d, p0/m, z0.d, z4.d
BIC Z0.D, P0/M, Z0.D, Z4.D
bic z0.d, p0/m, z0.d, z31.d
BIC Z0.D, P0/M, Z0.D, Z31.D
bic p0.b, p0/z, p0.b, p0.b
BIC P0.B, P0/Z, P0.B, P0.B
bic p1.b, p0/z, p0.b, p0.b
BIC P1.B, P0/Z, P0.B, P0.B
bic p15.b, p0/z, p0.b, p0.b
BIC P15.B, P0/Z, P0.B, P0.B
bic p0.b, p2/z, p0.b, p0.b
BIC P0.B, P2/Z, P0.B, P0.B
bic p0.b, p15/z, p0.b, p0.b
BIC P0.B, P15/Z, P0.B, P0.B
bic p0.b, p0/z, p3.b, p0.b
BIC P0.B, P0/Z, P3.B, P0.B
bic p0.b, p0/z, p15.b, p0.b
BIC P0.B, P0/Z, P15.B, P0.B
bic p0.b, p0/z, p0.b, p4.b
BIC P0.B, P0/Z, P0.B, P4.B
bic p0.b, p0/z, p0.b, p15.b
BIC P0.B, P0/Z, P0.B, P15.B
bics p0.b, p0/z, p0.b, p0.b
BICS P0.B, P0/Z, P0.B, P0.B
bics p1.b, p0/z, p0.b, p0.b
BICS P1.B, P0/Z, P0.B, P0.B
bics p15.b, p0/z, p0.b, p0.b
BICS P15.B, P0/Z, P0.B, P0.B
bics p0.b, p2/z, p0.b, p0.b
BICS P0.B, P2/Z, P0.B, P0.B
bics p0.b, p15/z, p0.b, p0.b
BICS P0.B, P15/Z, P0.B, P0.B
bics p0.b, p0/z, p3.b, p0.b
BICS P0.B, P0/Z, P3.B, P0.B
bics p0.b, p0/z, p15.b, p0.b
BICS P0.B, P0/Z, P15.B, P0.B
bics p0.b, p0/z, p0.b, p4.b
BICS P0.B, P0/Z, P0.B, P4.B
bics p0.b, p0/z, p0.b, p15.b
BICS P0.B, P0/Z, P0.B, P15.B
brka p0.b, p0/z, p0.b
BRKA P0.B, P0/Z, P0.B
brka p1.b, p0/z, p0.b
BRKA P1.B, P0/Z, P0.B
brka p15.b, p0/z, p0.b
BRKA P15.B, P0/Z, P0.B
brka p0.b, p2/z, p0.b
BRKA P0.B, P2/Z, P0.B
brka p0.b, p15/z, p0.b
BRKA P0.B, P15/Z, P0.B
brka p0.b, p0/z, p3.b
BRKA P0.B, P0/Z, P3.B
brka p0.b, p0/z, p15.b
BRKA P0.B, P0/Z, P15.B
brka p0.b, p0/m, p0.b
BRKA P0.B, P0/M, P0.B
brka p1.b, p0/m, p0.b
BRKA P1.B, P0/M, P0.B
brka p15.b, p0/m, p0.b
BRKA P15.B, P0/M, P0.B
brka p0.b, p2/m, p0.b
BRKA P0.B, P2/M, P0.B
brka p0.b, p15/m, p0.b
BRKA P0.B, P15/M, P0.B
brka p0.b, p0/m, p3.b
BRKA P0.B, P0/M, P3.B
brka p0.b, p0/m, p15.b
BRKA P0.B, P0/M, P15.B
brkas p0.b, p0/z, p0.b
BRKAS P0.B, P0/Z, P0.B
brkas p1.b, p0/z, p0.b
BRKAS P1.B, P0/Z, P0.B
brkas p15.b, p0/z, p0.b
BRKAS P15.B, P0/Z, P0.B
brkas p0.b, p2/z, p0.b
BRKAS P0.B, P2/Z, P0.B
brkas p0.b, p15/z, p0.b
BRKAS P0.B, P15/Z, P0.B
brkas p0.b, p0/z, p3.b
BRKAS P0.B, P0/Z, P3.B
brkas p0.b, p0/z, p15.b
BRKAS P0.B, P0/Z, P15.B
brkb p0.b, p0/z, p0.b
BRKB P0.B, P0/Z, P0.B
brkb p1.b, p0/z, p0.b
BRKB P1.B, P0/Z, P0.B
brkb p15.b, p0/z, p0.b
BRKB P15.B, P0/Z, P0.B
brkb p0.b, p2/z, p0.b
BRKB P0.B, P2/Z, P0.B
brkb p0.b, p15/z, p0.b
BRKB P0.B, P15/Z, P0.B
brkb p0.b, p0/z, p3.b
BRKB P0.B, P0/Z, P3.B
brkb p0.b, p0/z, p15.b
BRKB P0.B, P0/Z, P15.B
brkb p0.b, p0/m, p0.b
BRKB P0.B, P0/M, P0.B
brkb p1.b, p0/m, p0.b
BRKB P1.B, P0/M, P0.B
brkb p15.b, p0/m, p0.b
BRKB P15.B, P0/M, P0.B
brkb p0.b, p2/m, p0.b
BRKB P0.B, P2/M, P0.B
brkb p0.b, p15/m, p0.b
BRKB P0.B, P15/M, P0.B
brkb p0.b, p0/m, p3.b
BRKB P0.B, P0/M, P3.B
brkb p0.b, p0/m, p15.b
BRKB P0.B, P0/M, P15.B
brkbs p0.b, p0/z, p0.b
BRKBS P0.B, P0/Z, P0.B
brkbs p1.b, p0/z, p0.b
BRKBS P1.B, P0/Z, P0.B
brkbs p15.b, p0/z, p0.b
BRKBS P15.B, P0/Z, P0.B
brkbs p0.b, p2/z, p0.b
BRKBS P0.B, P2/Z, P0.B
brkbs p0.b, p15/z, p0.b
BRKBS P0.B, P15/Z, P0.B
brkbs p0.b, p0/z, p3.b
BRKBS P0.B, P0/Z, P3.B
brkbs p0.b, p0/z, p15.b
BRKBS P0.B, P0/Z, P15.B
brkn p0.b, p0/z, p0.b, p0.b
BRKN P0.B, P0/Z, P0.B, P0.B
brkn p1.b, p0/z, p0.b, p1.b
BRKN P1.B, P0/Z, P0.B, P1.B
brkn p15.b, p0/z, p0.b, p15.b
BRKN P15.B, P0/Z, P0.B, P15.B
brkn p0.b, p2/z, p0.b, p0.b
BRKN P0.B, P2/Z, P0.B, P0.B
brkn p0.b, p15/z, p0.b, p0.b
BRKN P0.B, P15/Z, P0.B, P0.B
brkn p0.b, p0/z, p3.b, p0.b
BRKN P0.B, P0/Z, P3.B, P0.B
brkn p0.b, p0/z, p15.b, p0.b
BRKN P0.B, P0/Z, P15.B, P0.B
brkn p4.b, p0/z, p0.b, p4.b
BRKN P4.B, P0/Z, P0.B, P4.B
brkns p0.b, p0/z, p0.b, p0.b
BRKNS P0.B, P0/Z, P0.B, P0.B
brkns p1.b, p0/z, p0.b, p1.b
BRKNS P1.B, P0/Z, P0.B, P1.B
brkns p15.b, p0/z, p0.b, p15.b
BRKNS P15.B, P0/Z, P0.B, P15.B
brkns p0.b, p2/z, p0.b, p0.b
BRKNS P0.B, P2/Z, P0.B, P0.B
brkns p0.b, p15/z, p0.b, p0.b
BRKNS P0.B, P15/Z, P0.B, P0.B
brkns p0.b, p0/z, p3.b, p0.b
BRKNS P0.B, P0/Z, P3.B, P0.B
brkns p0.b, p0/z, p15.b, p0.b
BRKNS P0.B, P0/Z, P15.B, P0.B
brkns p4.b, p0/z, p0.b, p4.b
BRKNS P4.B, P0/Z, P0.B, P4.B
brkpa p0.b, p0/z, p0.b, p0.b
BRKPA P0.B, P0/Z, P0.B, P0.B
brkpa p1.b, p0/z, p0.b, p0.b
BRKPA P1.B, P0/Z, P0.B, P0.B
brkpa p15.b, p0/z, p0.b, p0.b
BRKPA P15.B, P0/Z, P0.B, P0.B
brkpa p0.b, p2/z, p0.b, p0.b
BRKPA P0.B, P2/Z, P0.B, P0.B
brkpa p0.b, p15/z, p0.b, p0.b
BRKPA P0.B, P15/Z, P0.B, P0.B
brkpa p0.b, p0/z, p3.b, p0.b
BRKPA P0.B, P0/Z, P3.B, P0.B
brkpa p0.b, p0/z, p15.b, p0.b
BRKPA P0.B, P0/Z, P15.B, P0.B
brkpa p0.b, p0/z, p0.b, p4.b
BRKPA P0.B, P0/Z, P0.B, P4.B
brkpa p0.b, p0/z, p0.b, p15.b
BRKPA P0.B, P0/Z, P0.B, P15.B
brkpas p0.b, p0/z, p0.b, p0.b
BRKPAS P0.B, P0/Z, P0.B, P0.B
brkpas p1.b, p0/z, p0.b, p0.b
BRKPAS P1.B, P0/Z, P0.B, P0.B
brkpas p15.b, p0/z, p0.b, p0.b
BRKPAS P15.B, P0/Z, P0.B, P0.B
brkpas p0.b, p2/z, p0.b, p0.b
BRKPAS P0.B, P2/Z, P0.B, P0.B
brkpas p0.b, p15/z, p0.b, p0.b
BRKPAS P0.B, P15/Z, P0.B, P0.B
brkpas p0.b, p0/z, p3.b, p0.b
BRKPAS P0.B, P0/Z, P3.B, P0.B
brkpas p0.b, p0/z, p15.b, p0.b
BRKPAS P0.B, P0/Z, P15.B, P0.B
brkpas p0.b, p0/z, p0.b, p4.b
BRKPAS P0.B, P0/Z, P0.B, P4.B
brkpas p0.b, p0/z, p0.b, p15.b
BRKPAS P0.B, P0/Z, P0.B, P15.B
brkpb p0.b, p0/z, p0.b, p0.b
BRKPB P0.B, P0/Z, P0.B, P0.B
brkpb p1.b, p0/z, p0.b, p0.b
BRKPB P1.B, P0/Z, P0.B, P0.B
brkpb p15.b, p0/z, p0.b, p0.b
BRKPB P15.B, P0/Z, P0.B, P0.B
brkpb p0.b, p2/z, p0.b, p0.b
BRKPB P0.B, P2/Z, P0.B, P0.B
brkpb p0.b, p15/z, p0.b, p0.b
BRKPB P0.B, P15/Z, P0.B, P0.B
brkpb p0.b, p0/z, p3.b, p0.b
BRKPB P0.B, P0/Z, P3.B, P0.B
brkpb p0.b, p0/z, p15.b, p0.b
BRKPB P0.B, P0/Z, P15.B, P0.B
brkpb p0.b, p0/z, p0.b, p4.b
BRKPB P0.B, P0/Z, P0.B, P4.B
brkpb p0.b, p0/z, p0.b, p15.b
BRKPB P0.B, P0/Z, P0.B, P15.B
brkpbs p0.b, p0/z, p0.b, p0.b
BRKPBS P0.B, P0/Z, P0.B, P0.B
brkpbs p1.b, p0/z, p0.b, p0.b
BRKPBS P1.B, P0/Z, P0.B, P0.B
brkpbs p15.b, p0/z, p0.b, p0.b
BRKPBS P15.B, P0/Z, P0.B, P0.B
brkpbs p0.b, p2/z, p0.b, p0.b
BRKPBS P0.B, P2/Z, P0.B, P0.B
brkpbs p0.b, p15/z, p0.b, p0.b
BRKPBS P0.B, P15/Z, P0.B, P0.B
brkpbs p0.b, p0/z, p3.b, p0.b
BRKPBS P0.B, P0/Z, P3.B, P0.B
brkpbs p0.b, p0/z, p15.b, p0.b
BRKPBS P0.B, P0/Z, P15.B, P0.B
brkpbs p0.b, p0/z, p0.b, p4.b
BRKPBS P0.B, P0/Z, P0.B, P4.B
brkpbs p0.b, p0/z, p0.b, p15.b
BRKPBS P0.B, P0/Z, P0.B, P15.B
clasta z0.b, p0, z0.b, z0.b
CLASTA Z0.B, P0, Z0.B, Z0.B
clasta z1.b, p0, z1.b, z0.b
CLASTA Z1.B, P0, Z1.B, Z0.B
clasta z31.b, p0, z31.b, z0.b
CLASTA Z31.B, P0, Z31.B, Z0.B
clasta z0.b, p2, z0.b, z0.b
CLASTA Z0.B, P2, Z0.B, Z0.B
clasta z0.b, p7, z0.b, z0.b
CLASTA Z0.B, P7, Z0.B, Z0.B
clasta z3.b, p0, z3.b, z0.b
CLASTA Z3.B, P0, Z3.B, Z0.B
clasta z0.b, p0, z0.b, z4.b
CLASTA Z0.B, P0, Z0.B, Z4.B
clasta z0.b, p0, z0.b, z31.b
CLASTA Z0.B, P0, Z0.B, Z31.B
clasta z0.h, p0, z0.h, z0.h
CLASTA Z0.H, P0, Z0.H, Z0.H
clasta z1.h, p0, z1.h, z0.h
CLASTA Z1.H, P0, Z1.H, Z0.H
clasta z31.h, p0, z31.h, z0.h
CLASTA Z31.H, P0, Z31.H, Z0.H
clasta z0.h, p2, z0.h, z0.h
CLASTA Z0.H, P2, Z0.H, Z0.H
clasta z0.h, p7, z0.h, z0.h
CLASTA Z0.H, P7, Z0.H, Z0.H
clasta z3.h, p0, z3.h, z0.h
CLASTA Z3.H, P0, Z3.H, Z0.H
clasta z0.h, p0, z0.h, z4.h
CLASTA Z0.H, P0, Z0.H, Z4.H
clasta z0.h, p0, z0.h, z31.h
CLASTA Z0.H, P0, Z0.H, Z31.H
clasta z0.s, p0, z0.s, z0.s
CLASTA Z0.S, P0, Z0.S, Z0.S
clasta z1.s, p0, z1.s, z0.s
CLASTA Z1.S, P0, Z1.S, Z0.S
clasta z31.s, p0, z31.s, z0.s
CLASTA Z31.S, P0, Z31.S, Z0.S
clasta z0.s, p2, z0.s, z0.s
CLASTA Z0.S, P2, Z0.S, Z0.S
clasta z0.s, p7, z0.s, z0.s
CLASTA Z0.S, P7, Z0.S, Z0.S
clasta z3.s, p0, z3.s, z0.s
CLASTA Z3.S, P0, Z3.S, Z0.S
clasta z0.s, p0, z0.s, z4.s
CLASTA Z0.S, P0, Z0.S, Z4.S
clasta z0.s, p0, z0.s, z31.s
CLASTA Z0.S, P0, Z0.S, Z31.S
clasta z0.d, p0, z0.d, z0.d
CLASTA Z0.D, P0, Z0.D, Z0.D
clasta z1.d, p0, z1.d, z0.d
CLASTA Z1.D, P0, Z1.D, Z0.D
clasta z31.d, p0, z31.d, z0.d
CLASTA Z31.D, P0, Z31.D, Z0.D
clasta z0.d, p2, z0.d, z0.d
CLASTA Z0.D, P2, Z0.D, Z0.D
clasta z0.d, p7, z0.d, z0.d
CLASTA Z0.D, P7, Z0.D, Z0.D
clasta z3.d, p0, z3.d, z0.d
CLASTA Z3.D, P0, Z3.D, Z0.D
clasta z0.d, p0, z0.d, z4.d
CLASTA Z0.D, P0, Z0.D, Z4.D
clasta z0.d, p0, z0.d, z31.d
CLASTA Z0.D, P0, Z0.D, Z31.D
clasta b0, p0, b0, z0.b
CLASTA B0, P0, B0, Z0.B
clasta b1, p0, b1, z0.b
CLASTA B1, P0, B1, Z0.B
clasta b31, p0, b31, z0.b
CLASTA B31, P0, B31, Z0.B
clasta b0, p2, b0, z0.b
CLASTA B0, P2, B0, Z0.B
clasta b0, p7, b0, z0.b
CLASTA B0, P7, B0, Z0.B
clasta b3, p0, b3, z0.b
CLASTA B3, P0, B3, Z0.B
clasta b0, p0, b0, z4.b
CLASTA B0, P0, B0, Z4.B
clasta b0, p0, b0, z31.b
CLASTA B0, P0, B0, Z31.B
clasta h0, p0, h0, z0.h
CLASTA H0, P0, H0, Z0.H
clasta h1, p0, h1, z0.h
CLASTA H1, P0, H1, Z0.H
clasta h31, p0, h31, z0.h
CLASTA H31, P0, H31, Z0.H
clasta h0, p2, h0, z0.h
CLASTA H0, P2, H0, Z0.H
clasta h0, p7, h0, z0.h
CLASTA H0, P7, H0, Z0.H
clasta h3, p0, h3, z0.h
CLASTA H3, P0, H3, Z0.H
clasta h0, p0, h0, z4.h
CLASTA H0, P0, H0, Z4.H
clasta h0, p0, h0, z31.h
CLASTA H0, P0, H0, Z31.H
clasta s0, p0, s0, z0.s
CLASTA S0, P0, S0, Z0.S
clasta s1, p0, s1, z0.s
CLASTA S1, P0, S1, Z0.S
clasta s31, p0, s31, z0.s
CLASTA S31, P0, S31, Z0.S
clasta s0, p2, s0, z0.s
CLASTA S0, P2, S0, Z0.S
clasta s0, p7, s0, z0.s
CLASTA S0, P7, S0, Z0.S
clasta s3, p0, s3, z0.s
CLASTA S3, P0, S3, Z0.S
clasta s0, p0, s0, z4.s
CLASTA S0, P0, S0, Z4.S
clasta s0, p0, s0, z31.s
CLASTA S0, P0, S0, Z31.S
clasta d0, p0, d0, z0.d
CLASTA D0, P0, D0, Z0.D
clasta d1, p0, d1, z0.d
CLASTA D1, P0, D1, Z0.D
clasta d31, p0, d31, z0.d
CLASTA D31, P0, D31, Z0.D
clasta d0, p2, d0, z0.d
CLASTA D0, P2, D0, Z0.D
clasta d0, p7, d0, z0.d
CLASTA D0, P7, D0, Z0.D
clasta d3, p0, d3, z0.d
CLASTA D3, P0, D3, Z0.D
clasta d0, p0, d0, z4.d
CLASTA D0, P0, D0, Z4.D
clasta d0, p0, d0, z31.d
CLASTA D0, P0, D0, Z31.D
clasta w0, p0, w0, z0.b
CLASTA W0, P0, W0, Z0.B
clasta w1, p0, w1, z0.b
CLASTA W1, P0, W1, Z0.B
clasta wzr, p0, wzr, z0.b
CLASTA WZR, P0, WZR, Z0.B
clasta w0, p2, w0, z0.b
CLASTA W0, P2, W0, Z0.B
clasta w0, p7, w0, z0.b
CLASTA W0, P7, W0, Z0.B
clasta w3, p0, w3, z0.b
CLASTA W3, P0, W3, Z0.B
clasta w0, p0, w0, z4.b
CLASTA W0, P0, W0, Z4.B
clasta w0, p0, w0, z31.b
CLASTA W0, P0, W0, Z31.B
clasta w0, p0, w0, z0.h
CLASTA W0, P0, W0, Z0.H
clasta w1, p0, w1, z0.h
CLASTA W1, P0, W1, Z0.H
clasta wzr, p0, wzr, z0.h
CLASTA WZR, P0, WZR, Z0.H
clasta w0, p2, w0, z0.h
CLASTA W0, P2, W0, Z0.H
clasta w0, p7, w0, z0.h
CLASTA W0, P7, W0, Z0.H
clasta w3, p0, w3, z0.h
CLASTA W3, P0, W3, Z0.H
clasta w0, p0, w0, z4.h
CLASTA W0, P0, W0, Z4.H
clasta w0, p0, w0, z31.h
CLASTA W0, P0, W0, Z31.H
clasta w0, p0, w0, z0.s
CLASTA W0, P0, W0, Z0.S
clasta w1, p0, w1, z0.s
CLASTA W1, P0, W1, Z0.S
clasta wzr, p0, wzr, z0.s
CLASTA WZR, P0, WZR, Z0.S
clasta w0, p2, w0, z0.s
CLASTA W0, P2, W0, Z0.S
clasta w0, p7, w0, z0.s
CLASTA W0, P7, W0, Z0.S
clasta w3, p0, w3, z0.s
CLASTA W3, P0, W3, Z0.S
clasta w0, p0, w0, z4.s
CLASTA W0, P0, W0, Z4.S
clasta w0, p0, w0, z31.s
CLASTA W0, P0, W0, Z31.S
clasta x0, p0, x0, z0.d
CLASTA X0, P0, X0, Z0.D
clasta x1, p0, x1, z0.d
CLASTA X1, P0, X1, Z0.D
clasta xzr, p0, xzr, z0.d
CLASTA XZR, P0, XZR, Z0.D
clasta x0, p2, x0, z0.d
CLASTA X0, P2, X0, Z0.D
clasta x0, p7, x0, z0.d
CLASTA X0, P7, X0, Z0.D
clasta x3, p0, x3, z0.d
CLASTA X3, P0, X3, Z0.D
clasta x0, p0, x0, z4.d
CLASTA X0, P0, X0, Z4.D
clasta x0, p0, x0, z31.d
CLASTA X0, P0, X0, Z31.D
clastb z0.b, p0, z0.b, z0.b
CLASTB Z0.B, P0, Z0.B, Z0.B
clastb z1.b, p0, z1.b, z0.b
CLASTB Z1.B, P0, Z1.B, Z0.B
clastb z31.b, p0, z31.b, z0.b
CLASTB Z31.B, P0, Z31.B, Z0.B
clastb z0.b, p2, z0.b, z0.b
CLASTB Z0.B, P2, Z0.B, Z0.B
clastb z0.b, p7, z0.b, z0.b
CLASTB Z0.B, P7, Z0.B, Z0.B
clastb z3.b, p0, z3.b, z0.b
CLASTB Z3.B, P0, Z3.B, Z0.B
clastb z0.b, p0, z0.b, z4.b
CLASTB Z0.B, P0, Z0.B, Z4.B
clastb z0.b, p0, z0.b, z31.b
CLASTB Z0.B, P0, Z0.B, Z31.B
clastb z0.h, p0, z0.h, z0.h
CLASTB Z0.H, P0, Z0.H, Z0.H
clastb z1.h, p0, z1.h, z0.h
CLASTB Z1.H, P0, Z1.H, Z0.H
clastb z31.h, p0, z31.h, z0.h
CLASTB Z31.H, P0, Z31.H, Z0.H
clastb z0.h, p2, z0.h, z0.h
CLASTB Z0.H, P2, Z0.H, Z0.H
clastb z0.h, p7, z0.h, z0.h
CLASTB Z0.H, P7, Z0.H, Z0.H
clastb z3.h, p0, z3.h, z0.h
CLASTB Z3.H, P0, Z3.H, Z0.H
clastb z0.h, p0, z0.h, z4.h
CLASTB Z0.H, P0, Z0.H, Z4.H
clastb z0.h, p0, z0.h, z31.h
CLASTB Z0.H, P0, Z0.H, Z31.H
clastb z0.s, p0, z0.s, z0.s
CLASTB Z0.S, P0, Z0.S, Z0.S
clastb z1.s, p0, z1.s, z0.s
CLASTB Z1.S, P0, Z1.S, Z0.S
clastb z31.s, p0, z31.s, z0.s
CLASTB Z31.S, P0, Z31.S, Z0.S
clastb z0.s, p2, z0.s, z0.s
CLASTB Z0.S, P2, Z0.S, Z0.S
clastb z0.s, p7, z0.s, z0.s
CLASTB Z0.S, P7, Z0.S, Z0.S
clastb z3.s, p0, z3.s, z0.s
CLASTB Z3.S, P0, Z3.S, Z0.S
clastb z0.s, p0, z0.s, z4.s
CLASTB Z0.S, P0, Z0.S, Z4.S
clastb z0.s, p0, z0.s, z31.s
CLASTB Z0.S, P0, Z0.S, Z31.S
clastb z0.d, p0, z0.d, z0.d
CLASTB Z0.D, P0, Z0.D, Z0.D
clastb z1.d, p0, z1.d, z0.d
CLASTB Z1.D, P0, Z1.D, Z0.D
clastb z31.d, p0, z31.d, z0.d
CLASTB Z31.D, P0, Z31.D, Z0.D
clastb z0.d, p2, z0.d, z0.d
CLASTB Z0.D, P2, Z0.D, Z0.D
clastb z0.d, p7, z0.d, z0.d
CLASTB Z0.D, P7, Z0.D, Z0.D
clastb z3.d, p0, z3.d, z0.d
CLASTB Z3.D, P0, Z3.D, Z0.D
clastb z0.d, p0, z0.d, z4.d
CLASTB Z0.D, P0, Z0.D, Z4.D
clastb z0.d, p0, z0.d, z31.d
CLASTB Z0.D, P0, Z0.D, Z31.D
clastb b0, p0, b0, z0.b
CLASTB B0, P0, B0, Z0.B
clastb b1, p0, b1, z0.b
CLASTB B1, P0, B1, Z0.B
clastb b31, p0, b31, z0.b
CLASTB B31, P0, B31, Z0.B
clastb b0, p2, b0, z0.b
CLASTB B0, P2, B0, Z0.B
clastb b0, p7, b0, z0.b
CLASTB B0, P7, B0, Z0.B
clastb b3, p0, b3, z0.b
CLASTB B3, P0, B3, Z0.B
clastb b0, p0, b0, z4.b
CLASTB B0, P0, B0, Z4.B
clastb b0, p0, b0, z31.b
CLASTB B0, P0, B0, Z31.B
clastb h0, p0, h0, z0.h
CLASTB H0, P0, H0, Z0.H
clastb h1, p0, h1, z0.h
CLASTB H1, P0, H1, Z0.H
clastb h31, p0, h31, z0.h
CLASTB H31, P0, H31, Z0.H
clastb h0, p2, h0, z0.h
CLASTB H0, P2, H0, Z0.H
clastb h0, p7, h0, z0.h
CLASTB H0, P7, H0, Z0.H
clastb h3, p0, h3, z0.h
CLASTB H3, P0, H3, Z0.H
clastb h0, p0, h0, z4.h
CLASTB H0, P0, H0, Z4.H
clastb h0, p0, h0, z31.h
CLASTB H0, P0, H0, Z31.H
clastb s0, p0, s0, z0.s
CLASTB S0, P0, S0, Z0.S
clastb s1, p0, s1, z0.s
CLASTB S1, P0, S1, Z0.S
clastb s31, p0, s31, z0.s
CLASTB S31, P0, S31, Z0.S
clastb s0, p2, s0, z0.s
CLASTB S0, P2, S0, Z0.S
clastb s0, p7, s0, z0.s
CLASTB S0, P7, S0, Z0.S
clastb s3, p0, s3, z0.s
CLASTB S3, P0, S3, Z0.S
clastb s0, p0, s0, z4.s
CLASTB S0, P0, S0, Z4.S
clastb s0, p0, s0, z31.s
CLASTB S0, P0, S0, Z31.S
clastb d0, p0, d0, z0.d
CLASTB D0, P0, D0, Z0.D
clastb d1, p0, d1, z0.d
CLASTB D1, P0, D1, Z0.D
clastb d31, p0, d31, z0.d
CLASTB D31, P0, D31, Z0.D
clastb d0, p2, d0, z0.d
CLASTB D0, P2, D0, Z0.D
clastb d0, p7, d0, z0.d
CLASTB D0, P7, D0, Z0.D
clastb d3, p0, d3, z0.d
CLASTB D3, P0, D3, Z0.D
clastb d0, p0, d0, z4.d
CLASTB D0, P0, D0, Z4.D
clastb d0, p0, d0, z31.d
CLASTB D0, P0, D0, Z31.D
clastb w0, p0, w0, z0.b
CLASTB W0, P0, W0, Z0.B
clastb w1, p0, w1, z0.b
CLASTB W1, P0, W1, Z0.B
clastb wzr, p0, wzr, z0.b
CLASTB WZR, P0, WZR, Z0.B
clastb w0, p2, w0, z0.b
CLASTB W0, P2, W0, Z0.B
clastb w0, p7, w0, z0.b
CLASTB W0, P7, W0, Z0.B
clastb w3, p0, w3, z0.b
CLASTB W3, P0, W3, Z0.B
clastb w0, p0, w0, z4.b
CLASTB W0, P0, W0, Z4.B
clastb w0, p0, w0, z31.b
CLASTB W0, P0, W0, Z31.B
clastb w0, p0, w0, z0.h
CLASTB W0, P0, W0, Z0.H
clastb w1, p0, w1, z0.h
CLASTB W1, P0, W1, Z0.H
clastb wzr, p0, wzr, z0.h
CLASTB WZR, P0, WZR, Z0.H
clastb w0, p2, w0, z0.h
CLASTB W0, P2, W0, Z0.H
clastb w0, p7, w0, z0.h
CLASTB W0, P7, W0, Z0.H
clastb w3, p0, w3, z0.h
CLASTB W3, P0, W3, Z0.H
clastb w0, p0, w0, z4.h
CLASTB W0, P0, W0, Z4.H
clastb w0, p0, w0, z31.h
CLASTB W0, P0, W0, Z31.H
clastb w0, p0, w0, z0.s
CLASTB W0, P0, W0, Z0.S
clastb w1, p0, w1, z0.s
CLASTB W1, P0, W1, Z0.S
clastb wzr, p0, wzr, z0.s
CLASTB WZR, P0, WZR, Z0.S
clastb w0, p2, w0, z0.s
CLASTB W0, P2, W0, Z0.S
clastb w0, p7, w0, z0.s
CLASTB W0, P7, W0, Z0.S
clastb w3, p0, w3, z0.s
CLASTB W3, P0, W3, Z0.S
clastb w0, p0, w0, z4.s
CLASTB W0, P0, W0, Z4.S
clastb w0, p0, w0, z31.s
CLASTB W0, P0, W0, Z31.S
clastb x0, p0, x0, z0.d
CLASTB X0, P0, X0, Z0.D
clastb x1, p0, x1, z0.d
CLASTB X1, P0, X1, Z0.D
clastb xzr, p0, xzr, z0.d
CLASTB XZR, P0, XZR, Z0.D
clastb x0, p2, x0, z0.d
CLASTB X0, P2, X0, Z0.D
clastb x0, p7, x0, z0.d
CLASTB X0, P7, X0, Z0.D
clastb x3, p0, x3, z0.d
CLASTB X3, P0, X3, Z0.D
clastb x0, p0, x0, z4.d
CLASTB X0, P0, X0, Z4.D
clastb x0, p0, x0, z31.d
CLASTB X0, P0, X0, Z31.D
cls z0.b, p0/m, z0.b
CLS Z0.B, P0/M, Z0.B
cls z1.b, p0/m, z0.b
CLS Z1.B, P0/M, Z0.B
cls z31.b, p0/m, z0.b
CLS Z31.B, P0/M, Z0.B
cls z0.b, p2/m, z0.b
CLS Z0.B, P2/M, Z0.B
cls z0.b, p7/m, z0.b
CLS Z0.B, P7/M, Z0.B
cls z0.b, p0/m, z3.b
CLS Z0.B, P0/M, Z3.B
cls z0.b, p0/m, z31.b
CLS Z0.B, P0/M, Z31.B
cls z0.h, p0/m, z0.h
CLS Z0.H, P0/M, Z0.H
cls z1.h, p0/m, z0.h
CLS Z1.H, P0/M, Z0.H
cls z31.h, p0/m, z0.h
CLS Z31.H, P0/M, Z0.H
cls z0.h, p2/m, z0.h
CLS Z0.H, P2/M, Z0.H
cls z0.h, p7/m, z0.h
CLS Z0.H, P7/M, Z0.H
cls z0.h, p0/m, z3.h
CLS Z0.H, P0/M, Z3.H
cls z0.h, p0/m, z31.h
CLS Z0.H, P0/M, Z31.H
cls z0.s, p0/m, z0.s
CLS Z0.S, P0/M, Z0.S
cls z1.s, p0/m, z0.s
CLS Z1.S, P0/M, Z0.S
cls z31.s, p0/m, z0.s
CLS Z31.S, P0/M, Z0.S
cls z0.s, p2/m, z0.s
CLS Z0.S, P2/M, Z0.S
cls z0.s, p7/m, z0.s
CLS Z0.S, P7/M, Z0.S
cls z0.s, p0/m, z3.s
CLS Z0.S, P0/M, Z3.S
cls z0.s, p0/m, z31.s
CLS Z0.S, P0/M, Z31.S
cls z0.d, p0/m, z0.d
CLS Z0.D, P0/M, Z0.D
cls z1.d, p0/m, z0.d
CLS Z1.D, P0/M, Z0.D
cls z31.d, p0/m, z0.d
CLS Z31.D, P0/M, Z0.D
cls z0.d, p2/m, z0.d
CLS Z0.D, P2/M, Z0.D
cls z0.d, p7/m, z0.d
CLS Z0.D, P7/M, Z0.D
cls z0.d, p0/m, z3.d
CLS Z0.D, P0/M, Z3.D
cls z0.d, p0/m, z31.d
CLS Z0.D, P0/M, Z31.D
clz z0.b, p0/m, z0.b
CLZ Z0.B, P0/M, Z0.B
clz z1.b, p0/m, z0.b
CLZ Z1.B, P0/M, Z0.B
clz z31.b, p0/m, z0.b
CLZ Z31.B, P0/M, Z0.B
clz z0.b, p2/m, z0.b
CLZ Z0.B, P2/M, Z0.B
clz z0.b, p7/m, z0.b
CLZ Z0.B, P7/M, Z0.B
clz z0.b, p0/m, z3.b
CLZ Z0.B, P0/M, Z3.B
clz z0.b, p0/m, z31.b
CLZ Z0.B, P0/M, Z31.B
clz z0.h, p0/m, z0.h
CLZ Z0.H, P0/M, Z0.H
clz z1.h, p0/m, z0.h
CLZ Z1.H, P0/M, Z0.H
clz z31.h, p0/m, z0.h
CLZ Z31.H, P0/M, Z0.H
clz z0.h, p2/m, z0.h
CLZ Z0.H, P2/M, Z0.H
clz z0.h, p7/m, z0.h
CLZ Z0.H, P7/M, Z0.H
clz z0.h, p0/m, z3.h
CLZ Z0.H, P0/M, Z3.H
clz z0.h, p0/m, z31.h
CLZ Z0.H, P0/M, Z31.H
clz z0.s, p0/m, z0.s
CLZ Z0.S, P0/M, Z0.S
clz z1.s, p0/m, z0.s
CLZ Z1.S, P0/M, Z0.S
clz z31.s, p0/m, z0.s
CLZ Z31.S, P0/M, Z0.S
clz z0.s, p2/m, z0.s
CLZ Z0.S, P2/M, Z0.S
clz z0.s, p7/m, z0.s
CLZ Z0.S, P7/M, Z0.S
clz z0.s, p0/m, z3.s
CLZ Z0.S, P0/M, Z3.S
clz z0.s, p0/m, z31.s
CLZ Z0.S, P0/M, Z31.S
clz z0.d, p0/m, z0.d
CLZ Z0.D, P0/M, Z0.D
clz z1.d, p0/m, z0.d
CLZ Z1.D, P0/M, Z0.D
clz z31.d, p0/m, z0.d
CLZ Z31.D, P0/M, Z0.D
clz z0.d, p2/m, z0.d
CLZ Z0.D, P2/M, Z0.D
clz z0.d, p7/m, z0.d
CLZ Z0.D, P7/M, Z0.D
clz z0.d, p0/m, z3.d
CLZ Z0.D, P0/M, Z3.D
clz z0.d, p0/m, z31.d
CLZ Z0.D, P0/M, Z31.D
cmpeq p0.b, p0/z, z0.b, z0.d
CMPEQ P0.B, P0/Z, Z0.B, Z0.D
cmpeq p1.b, p0/z, z0.b, z0.d
CMPEQ P1.B, P0/Z, Z0.B, Z0.D
cmpeq p15.b, p0/z, z0.b, z0.d
CMPEQ P15.B, P0/Z, Z0.B, Z0.D
cmpeq p0.b, p2/z, z0.b, z0.d
CMPEQ P0.B, P2/Z, Z0.B, Z0.D
cmpeq p0.b, p7/z, z0.b, z0.d
CMPEQ P0.B, P7/Z, Z0.B, Z0.D
cmpeq p0.b, p0/z, z3.b, z0.d
CMPEQ P0.B, P0/Z, Z3.B, Z0.D
cmpeq p0.b, p0/z, z31.b, z0.d
CMPEQ P0.B, P0/Z, Z31.B, Z0.D
cmpeq p0.b, p0/z, z0.b, z4.d
CMPEQ P0.B, P0/Z, Z0.B, Z4.D
cmpeq p0.b, p0/z, z0.b, z31.d
CMPEQ P0.B, P0/Z, Z0.B, Z31.D
cmpeq p0.h, p0/z, z0.h, z0.d
CMPEQ P0.H, P0/Z, Z0.H, Z0.D
cmpeq p1.h, p0/z, z0.h, z0.d
CMPEQ P1.H, P0/Z, Z0.H, Z0.D
cmpeq p15.h, p0/z, z0.h, z0.d
CMPEQ P15.H, P0/Z, Z0.H, Z0.D
cmpeq p0.h, p2/z, z0.h, z0.d
CMPEQ P0.H, P2/Z, Z0.H, Z0.D
cmpeq p0.h, p7/z, z0.h, z0.d
CMPEQ P0.H, P7/Z, Z0.H, Z0.D
cmpeq p0.h, p0/z, z3.h, z0.d
CMPEQ P0.H, P0/Z, Z3.H, Z0.D
cmpeq p0.h, p0/z, z31.h, z0.d
CMPEQ P0.H, P0/Z, Z31.H, Z0.D
cmpeq p0.h, p0/z, z0.h, z4.d
CMPEQ P0.H, P0/Z, Z0.H, Z4.D
cmpeq p0.h, p0/z, z0.h, z31.d
CMPEQ P0.H, P0/Z, Z0.H, Z31.D
cmpeq p0.s, p0/z, z0.s, z0.d
CMPEQ P0.S, P0/Z, Z0.S, Z0.D
cmpeq p1.s, p0/z, z0.s, z0.d
CMPEQ P1.S, P0/Z, Z0.S, Z0.D
cmpeq p15.s, p0/z, z0.s, z0.d
CMPEQ P15.S, P0/Z, Z0.S, Z0.D
cmpeq p0.s, p2/z, z0.s, z0.d
CMPEQ P0.S, P2/Z, Z0.S, Z0.D
cmpeq p0.s, p7/z, z0.s, z0.d
CMPEQ P0.S, P7/Z, Z0.S, Z0.D
cmpeq p0.s, p0/z, z3.s, z0.d
CMPEQ P0.S, P0/Z, Z3.S, Z0.D
cmpeq p0.s, p0/z, z31.s, z0.d
CMPEQ P0.S, P0/Z, Z31.S, Z0.D
cmpeq p0.s, p0/z, z0.s, z4.d
CMPEQ P0.S, P0/Z, Z0.S, Z4.D
cmpeq p0.s, p0/z, z0.s, z31.d
CMPEQ P0.S, P0/Z, Z0.S, Z31.D
cmpeq p0.b, p0/z, z0.b, z0.b
CMPEQ P0.B, P0/Z, Z0.B, Z0.B
cmpeq p1.b, p0/z, z0.b, z0.b
CMPEQ P1.B, P0/Z, Z0.B, Z0.B
cmpeq p15.b, p0/z, z0.b, z0.b
CMPEQ P15.B, P0/Z, Z0.B, Z0.B
cmpeq p0.b, p2/z, z0.b, z0.b
CMPEQ P0.B, P2/Z, Z0.B, Z0.B
cmpeq p0.b, p7/z, z0.b, z0.b
CMPEQ P0.B, P7/Z, Z0.B, Z0.B
cmpeq p0.b, p0/z, z3.b, z0.b
CMPEQ P0.B, P0/Z, Z3.B, Z0.B
cmpeq p0.b, p0/z, z31.b, z0.b
CMPEQ P0.B, P0/Z, Z31.B, Z0.B
cmpeq p0.b, p0/z, z0.b, z4.b
CMPEQ P0.B, P0/Z, Z0.B, Z4.B
cmpeq p0.b, p0/z, z0.b, z31.b
CMPEQ P0.B, P0/Z, Z0.B, Z31.B
cmpeq p0.h, p0/z, z0.h, z0.h
CMPEQ P0.H, P0/Z, Z0.H, Z0.H
cmpeq p1.h, p0/z, z0.h, z0.h
CMPEQ P1.H, P0/Z, Z0.H, Z0.H
cmpeq p15.h, p0/z, z0.h, z0.h
CMPEQ P15.H, P0/Z, Z0.H, Z0.H
cmpeq p0.h, p2/z, z0.h, z0.h
CMPEQ P0.H, P2/Z, Z0.H, Z0.H
cmpeq p0.h, p7/z, z0.h, z0.h
CMPEQ P0.H, P7/Z, Z0.H, Z0.H
cmpeq p0.h, p0/z, z3.h, z0.h
CMPEQ P0.H, P0/Z, Z3.H, Z0.H
cmpeq p0.h, p0/z, z31.h, z0.h
CMPEQ P0.H, P0/Z, Z31.H, Z0.H
cmpeq p0.h, p0/z, z0.h, z4.h
CMPEQ P0.H, P0/Z, Z0.H, Z4.H
cmpeq p0.h, p0/z, z0.h, z31.h
CMPEQ P0.H, P0/Z, Z0.H, Z31.H
cmpeq p0.s, p0/z, z0.s, z0.s
CMPEQ P0.S, P0/Z, Z0.S, Z0.S
cmpeq p1.s, p0/z, z0.s, z0.s
CMPEQ P1.S, P0/Z, Z0.S, Z0.S
cmpeq p15.s, p0/z, z0.s, z0.s
CMPEQ P15.S, P0/Z, Z0.S, Z0.S
cmpeq p0.s, p2/z, z0.s, z0.s
CMPEQ P0.S, P2/Z, Z0.S, Z0.S
cmpeq p0.s, p7/z, z0.s, z0.s
CMPEQ P0.S, P7/Z, Z0.S, Z0.S
cmpeq p0.s, p0/z, z3.s, z0.s
CMPEQ P0.S, P0/Z, Z3.S, Z0.S
cmpeq p0.s, p0/z, z31.s, z0.s
CMPEQ P0.S, P0/Z, Z31.S, Z0.S
cmpeq p0.s, p0/z, z0.s, z4.s
CMPEQ P0.S, P0/Z, Z0.S, Z4.S
cmpeq p0.s, p0/z, z0.s, z31.s
CMPEQ P0.S, P0/Z, Z0.S, Z31.S
cmpeq p0.d, p0/z, z0.d, z0.d
CMPEQ P0.D, P0/Z, Z0.D, Z0.D
cmpeq p1.d, p0/z, z0.d, z0.d
CMPEQ P1.D, P0/Z, Z0.D, Z0.D
cmpeq p15.d, p0/z, z0.d, z0.d
CMPEQ P15.D, P0/Z, Z0.D, Z0.D
cmpeq p0.d, p2/z, z0.d, z0.d
CMPEQ P0.D, P2/Z, Z0.D, Z0.D
cmpeq p0.d, p7/z, z0.d, z0.d
CMPEQ P0.D, P7/Z, Z0.D, Z0.D
cmpeq p0.d, p0/z, z3.d, z0.d
CMPEQ P0.D, P0/Z, Z3.D, Z0.D
cmpeq p0.d, p0/z, z31.d, z0.d
CMPEQ P0.D, P0/Z, Z31.D, Z0.D
cmpeq p0.d, p0/z, z0.d, z4.d
CMPEQ P0.D, P0/Z, Z0.D, Z4.D
cmpeq p0.d, p0/z, z0.d, z31.d
CMPEQ P0.D, P0/Z, Z0.D, Z31.D
cmpeq p0.b, p0/z, z0.b, #0
CMPEQ P0.B, P0/Z, Z0.B, #0
cmpeq p1.b, p0/z, z0.b, #0
CMPEQ P1.B, P0/Z, Z0.B, #0
cmpeq p15.b, p0/z, z0.b, #0
CMPEQ P15.B, P0/Z, Z0.B, #0
cmpeq p0.b, p2/z, z0.b, #0
CMPEQ P0.B, P2/Z, Z0.B, #0
cmpeq p0.b, p7/z, z0.b, #0
CMPEQ P0.B, P7/Z, Z0.B, #0
cmpeq p0.b, p0/z, z3.b, #0
CMPEQ P0.B, P0/Z, Z3.B, #0
cmpeq p0.b, p0/z, z31.b, #0
CMPEQ P0.B, P0/Z, Z31.B, #0
cmpeq p0.b, p0/z, z0.b, #15
CMPEQ P0.B, P0/Z, Z0.B, #15
cmpeq p0.b, p0/z, z0.b, #-16
CMPEQ P0.B, P0/Z, Z0.B, #-16
cmpeq p0.b, p0/z, z0.b, #-15
CMPEQ P0.B, P0/Z, Z0.B, #-15
cmpeq p0.b, p0/z, z0.b, #-1
CMPEQ P0.B, P0/Z, Z0.B, #-1
cmpeq p0.h, p0/z, z0.h, #0
CMPEQ P0.H, P0/Z, Z0.H, #0
cmpeq p1.h, p0/z, z0.h, #0
CMPEQ P1.H, P0/Z, Z0.H, #0
cmpeq p15.h, p0/z, z0.h, #0
CMPEQ P15.H, P0/Z, Z0.H, #0
cmpeq p0.h, p2/z, z0.h, #0
CMPEQ P0.H, P2/Z, Z0.H, #0
cmpeq p0.h, p7/z, z0.h, #0
CMPEQ P0.H, P7/Z, Z0.H, #0
cmpeq p0.h, p0/z, z3.h, #0
CMPEQ P0.H, P0/Z, Z3.H, #0
cmpeq p0.h, p0/z, z31.h, #0
CMPEQ P0.H, P0/Z, Z31.H, #0
cmpeq p0.h, p0/z, z0.h, #15
CMPEQ P0.H, P0/Z, Z0.H, #15
cmpeq p0.h, p0/z, z0.h, #-16
CMPEQ P0.H, P0/Z, Z0.H, #-16
cmpeq p0.h, p0/z, z0.h, #-15
CMPEQ P0.H, P0/Z, Z0.H, #-15
cmpeq p0.h, p0/z, z0.h, #-1
CMPEQ P0.H, P0/Z, Z0.H, #-1
cmpeq p0.s, p0/z, z0.s, #0
CMPEQ P0.S, P0/Z, Z0.S, #0
cmpeq p1.s, p0/z, z0.s, #0
CMPEQ P1.S, P0/Z, Z0.S, #0
cmpeq p15.s, p0/z, z0.s, #0
CMPEQ P15.S, P0/Z, Z0.S, #0
cmpeq p0.s, p2/z, z0.s, #0
CMPEQ P0.S, P2/Z, Z0.S, #0
cmpeq p0.s, p7/z, z0.s, #0
CMPEQ P0.S, P7/Z, Z0.S, #0
cmpeq p0.s, p0/z, z3.s, #0
CMPEQ P0.S, P0/Z, Z3.S, #0
cmpeq p0.s, p0/z, z31.s, #0
CMPEQ P0.S, P0/Z, Z31.S, #0
cmpeq p0.s, p0/z, z0.s, #15
CMPEQ P0.S, P0/Z, Z0.S, #15
cmpeq p0.s, p0/z, z0.s, #-16
CMPEQ P0.S, P0/Z, Z0.S, #-16
cmpeq p0.s, p0/z, z0.s, #-15
CMPEQ P0.S, P0/Z, Z0.S, #-15
cmpeq p0.s, p0/z, z0.s, #-1
CMPEQ P0.S, P0/Z, Z0.S, #-1
cmpeq p0.d, p0/z, z0.d, #0
CMPEQ P0.D, P0/Z, Z0.D, #0
cmpeq p1.d, p0/z, z0.d, #0
CMPEQ P1.D, P0/Z, Z0.D, #0
cmpeq p15.d, p0/z, z0.d, #0
CMPEQ P15.D, P0/Z, Z0.D, #0
cmpeq p0.d, p2/z, z0.d, #0
CMPEQ P0.D, P2/Z, Z0.D, #0
cmpeq p0.d, p7/z, z0.d, #0
CMPEQ P0.D, P7/Z, Z0.D, #0
cmpeq p0.d, p0/z, z3.d, #0
CMPEQ P0.D, P0/Z, Z3.D, #0
cmpeq p0.d, p0/z, z31.d, #0
CMPEQ P0.D, P0/Z, Z31.D, #0
cmpeq p0.d, p0/z, z0.d, #15
CMPEQ P0.D, P0/Z, Z0.D, #15
cmpeq p0.d, p0/z, z0.d, #-16
CMPEQ P0.D, P0/Z, Z0.D, #-16
cmpeq p0.d, p0/z, z0.d, #-15
CMPEQ P0.D, P0/Z, Z0.D, #-15
cmpeq p0.d, p0/z, z0.d, #-1
CMPEQ P0.D, P0/Z, Z0.D, #-1
cmpge p0.b, p0/z, z0.b, z0.d
CMPGE P0.B, P0/Z, Z0.B, Z0.D
cmpge p1.b, p0/z, z0.b, z0.d
CMPGE P1.B, P0/Z, Z0.B, Z0.D
cmpge p15.b, p0/z, z0.b, z0.d
CMPGE P15.B, P0/Z, Z0.B, Z0.D
cmpge p0.b, p2/z, z0.b, z0.d
CMPGE P0.B, P2/Z, Z0.B, Z0.D
cmpge p0.b, p7/z, z0.b, z0.d
CMPGE P0.B, P7/Z, Z0.B, Z0.D
cmpge p0.b, p0/z, z3.b, z0.d
CMPGE P0.B, P0/Z, Z3.B, Z0.D
cmpge p0.b, p0/z, z31.b, z0.d
CMPGE P0.B, P0/Z, Z31.B, Z0.D
cmpge p0.b, p0/z, z0.b, z4.d
CMPGE P0.B, P0/Z, Z0.B, Z4.D
cmpge p0.b, p0/z, z0.b, z31.d
CMPGE P0.B, P0/Z, Z0.B, Z31.D
cmpge p0.h, p0/z, z0.h, z0.d
CMPGE P0.H, P0/Z, Z0.H, Z0.D
cmpge p1.h, p0/z, z0.h, z0.d
CMPGE P1.H, P0/Z, Z0.H, Z0.D
cmpge p15.h, p0/z, z0.h, z0.d
CMPGE P15.H, P0/Z, Z0.H, Z0.D
cmpge p0.h, p2/z, z0.h, z0.d
CMPGE P0.H, P2/Z, Z0.H, Z0.D
cmpge p0.h, p7/z, z0.h, z0.d
CMPGE P0.H, P7/Z, Z0.H, Z0.D
cmpge p0.h, p0/z, z3.h, z0.d
CMPGE P0.H, P0/Z, Z3.H, Z0.D
cmpge p0.h, p0/z, z31.h, z0.d
CMPGE P0.H, P0/Z, Z31.H, Z0.D
cmpge p0.h, p0/z, z0.h, z4.d
CMPGE P0.H, P0/Z, Z0.H, Z4.D
cmpge p0.h, p0/z, z0.h, z31.d
CMPGE P0.H, P0/Z, Z0.H, Z31.D
cmpge p0.s, p0/z, z0.s, z0.d
CMPGE P0.S, P0/Z, Z0.S, Z0.D
cmpge p1.s, p0/z, z0.s, z0.d
CMPGE P1.S, P0/Z, Z0.S, Z0.D
cmpge p15.s, p0/z, z0.s, z0.d
CMPGE P15.S, P0/Z, Z0.S, Z0.D
cmpge p0.s, p2/z, z0.s, z0.d
CMPGE P0.S, P2/Z, Z0.S, Z0.D
cmpge p0.s, p7/z, z0.s, z0.d
CMPGE P0.S, P7/Z, Z0.S, Z0.D
cmpge p0.s, p0/z, z3.s, z0.d
CMPGE P0.S, P0/Z, Z3.S, Z0.D
cmpge p0.s, p0/z, z31.s, z0.d
CMPGE P0.S, P0/Z, Z31.S, Z0.D
cmpge p0.s, p0/z, z0.s, z4.d
CMPGE P0.S, P0/Z, Z0.S, Z4.D
cmpge p0.s, p0/z, z0.s, z31.d
CMPGE P0.S, P0/Z, Z0.S, Z31.D
cmpge p0.b, p0/z, z0.b, z0.b
CMPGE P0.B, P0/Z, Z0.B, Z0.B
cmpge p1.b, p0/z, z0.b, z0.b
CMPGE P1.B, P0/Z, Z0.B, Z0.B
cmpge p15.b, p0/z, z0.b, z0.b
CMPGE P15.B, P0/Z, Z0.B, Z0.B
cmpge p0.b, p2/z, z0.b, z0.b
CMPGE P0.B, P2/Z, Z0.B, Z0.B
cmpge p0.b, p7/z, z0.b, z0.b
CMPGE P0.B, P7/Z, Z0.B, Z0.B
cmpge p0.b, p0/z, z3.b, z0.b
CMPGE P0.B, P0/Z, Z3.B, Z0.B
cmpge p0.b, p0/z, z31.b, z0.b
CMPGE P0.B, P0/Z, Z31.B, Z0.B
cmpge p0.b, p0/z, z0.b, z4.b
CMPGE P0.B, P0/Z, Z0.B, Z4.B
cmpge p0.b, p0/z, z0.b, z31.b
CMPGE P0.B, P0/Z, Z0.B, Z31.B
cmpge p0.h, p0/z, z0.h, z0.h
CMPGE P0.H, P0/Z, Z0.H, Z0.H
cmpge p1.h, p0/z, z0.h, z0.h
CMPGE P1.H, P0/Z, Z0.H, Z0.H
cmpge p15.h, p0/z, z0.h, z0.h
CMPGE P15.H, P0/Z, Z0.H, Z0.H
cmpge p0.h, p2/z, z0.h, z0.h
CMPGE P0.H, P2/Z, Z0.H, Z0.H
cmpge p0.h, p7/z, z0.h, z0.h
CMPGE P0.H, P7/Z, Z0.H, Z0.H
cmpge p0.h, p0/z, z3.h, z0.h
CMPGE P0.H, P0/Z, Z3.H, Z0.H
cmpge p0.h, p0/z, z31.h, z0.h
CMPGE P0.H, P0/Z, Z31.H, Z0.H
cmpge p0.h, p0/z, z0.h, z4.h
CMPGE P0.H, P0/Z, Z0.H, Z4.H
cmpge p0.h, p0/z, z0.h, z31.h
CMPGE P0.H, P0/Z, Z0.H, Z31.H
cmpge p0.s, p0/z, z0.s, z0.s
CMPGE P0.S, P0/Z, Z0.S, Z0.S
cmpge p1.s, p0/z, z0.s, z0.s
CMPGE P1.S, P0/Z, Z0.S, Z0.S
cmpge p15.s, p0/z, z0.s, z0.s
CMPGE P15.S, P0/Z, Z0.S, Z0.S
cmpge p0.s, p2/z, z0.s, z0.s
CMPGE P0.S, P2/Z, Z0.S, Z0.S
cmpge p0.s, p7/z, z0.s, z0.s
CMPGE P0.S, P7/Z, Z0.S, Z0.S
cmpge p0.s, p0/z, z3.s, z0.s
CMPGE P0.S, P0/Z, Z3.S, Z0.S
cmpge p0.s, p0/z, z31.s, z0.s
CMPGE P0.S, P0/Z, Z31.S, Z0.S
cmpge p0.s, p0/z, z0.s, z4.s
CMPGE P0.S, P0/Z, Z0.S, Z4.S
cmpge p0.s, p0/z, z0.s, z31.s
CMPGE P0.S, P0/Z, Z0.S, Z31.S
cmpge p0.d, p0/z, z0.d, z0.d
CMPGE P0.D, P0/Z, Z0.D, Z0.D
cmpge p1.d, p0/z, z0.d, z0.d
CMPGE P1.D, P0/Z, Z0.D, Z0.D
cmpge p15.d, p0/z, z0.d, z0.d
CMPGE P15.D, P0/Z, Z0.D, Z0.D
cmpge p0.d, p2/z, z0.d, z0.d
CMPGE P0.D, P2/Z, Z0.D, Z0.D
cmpge p0.d, p7/z, z0.d, z0.d
CMPGE P0.D, P7/Z, Z0.D, Z0.D
cmpge p0.d, p0/z, z3.d, z0.d
CMPGE P0.D, P0/Z, Z3.D, Z0.D
cmpge p0.d, p0/z, z31.d, z0.d
CMPGE P0.D, P0/Z, Z31.D, Z0.D
cmpge p0.d, p0/z, z0.d, z4.d
CMPGE P0.D, P0/Z, Z0.D, Z4.D
cmpge p0.d, p0/z, z0.d, z31.d
CMPGE P0.D, P0/Z, Z0.D, Z31.D
cmpge p0.b, p0/z, z0.b, #0
CMPGE P0.B, P0/Z, Z0.B, #0
cmpge p1.b, p0/z, z0.b, #0
CMPGE P1.B, P0/Z, Z0.B, #0
cmpge p15.b, p0/z, z0.b, #0
CMPGE P15.B, P0/Z, Z0.B, #0
cmpge p0.b, p2/z, z0.b, #0
CMPGE P0.B, P2/Z, Z0.B, #0
cmpge p0.b, p7/z, z0.b, #0
CMPGE P0.B, P7/Z, Z0.B, #0
cmpge p0.b, p0/z, z3.b, #0
CMPGE P0.B, P0/Z, Z3.B, #0
cmpge p0.b, p0/z, z31.b, #0
CMPGE P0.B, P0/Z, Z31.B, #0
cmpge p0.b, p0/z, z0.b, #15
CMPGE P0.B, P0/Z, Z0.B, #15
cmpge p0.b, p0/z, z0.b, #-16
CMPGE P0.B, P0/Z, Z0.B, #-16
cmpge p0.b, p0/z, z0.b, #-15
CMPGE P0.B, P0/Z, Z0.B, #-15
cmpge p0.b, p0/z, z0.b, #-1
CMPGE P0.B, P0/Z, Z0.B, #-1
cmpge p0.h, p0/z, z0.h, #0
CMPGE P0.H, P0/Z, Z0.H, #0
cmpge p1.h, p0/z, z0.h, #0
CMPGE P1.H, P0/Z, Z0.H, #0
cmpge p15.h, p0/z, z0.h, #0
CMPGE P15.H, P0/Z, Z0.H, #0
cmpge p0.h, p2/z, z0.h, #0
CMPGE P0.H, P2/Z, Z0.H, #0
cmpge p0.h, p7/z, z0.h, #0
CMPGE P0.H, P7/Z, Z0.H, #0
cmpge p0.h, p0/z, z3.h, #0
CMPGE P0.H, P0/Z, Z3.H, #0
cmpge p0.h, p0/z, z31.h, #0
CMPGE P0.H, P0/Z, Z31.H, #0
cmpge p0.h, p0/z, z0.h, #15
CMPGE P0.H, P0/Z, Z0.H, #15
cmpge p0.h, p0/z, z0.h, #-16
CMPGE P0.H, P0/Z, Z0.H, #-16
cmpge p0.h, p0/z, z0.h, #-15
CMPGE P0.H, P0/Z, Z0.H, #-15
cmpge p0.h, p0/z, z0.h, #-1
CMPGE P0.H, P0/Z, Z0.H, #-1
cmpge p0.s, p0/z, z0.s, #0
CMPGE P0.S, P0/Z, Z0.S, #0
cmpge p1.s, p0/z, z0.s, #0
CMPGE P1.S, P0/Z, Z0.S, #0
cmpge p15.s, p0/z, z0.s, #0
CMPGE P15.S, P0/Z, Z0.S, #0
cmpge p0.s, p2/z, z0.s, #0
CMPGE P0.S, P2/Z, Z0.S, #0
cmpge p0.s, p7/z, z0.s, #0
CMPGE P0.S, P7/Z, Z0.S, #0
cmpge p0.s, p0/z, z3.s, #0
CMPGE P0.S, P0/Z, Z3.S, #0
cmpge p0.s, p0/z, z31.s, #0
CMPGE P0.S, P0/Z, Z31.S, #0
cmpge p0.s, p0/z, z0.s, #15
CMPGE P0.S, P0/Z, Z0.S, #15
cmpge p0.s, p0/z, z0.s, #-16
CMPGE P0.S, P0/Z, Z0.S, #-16
cmpge p0.s, p0/z, z0.s, #-15
CMPGE P0.S, P0/Z, Z0.S, #-15
cmpge p0.s, p0/z, z0.s, #-1
CMPGE P0.S, P0/Z, Z0.S, #-1
cmpge p0.d, p0/z, z0.d, #0
CMPGE P0.D, P0/Z, Z0.D, #0
cmpge p1.d, p0/z, z0.d, #0
CMPGE P1.D, P0/Z, Z0.D, #0
cmpge p15.d, p0/z, z0.d, #0
CMPGE P15.D, P0/Z, Z0.D, #0
cmpge p0.d, p2/z, z0.d, #0
CMPGE P0.D, P2/Z, Z0.D, #0
cmpge p0.d, p7/z, z0.d, #0
CMPGE P0.D, P7/Z, Z0.D, #0
cmpge p0.d, p0/z, z3.d, #0
CMPGE P0.D, P0/Z, Z3.D, #0
cmpge p0.d, p0/z, z31.d, #0
CMPGE P0.D, P0/Z, Z31.D, #0
cmpge p0.d, p0/z, z0.d, #15
CMPGE P0.D, P0/Z, Z0.D, #15
cmpge p0.d, p0/z, z0.d, #-16
CMPGE P0.D, P0/Z, Z0.D, #-16
cmpge p0.d, p0/z, z0.d, #-15
CMPGE P0.D, P0/Z, Z0.D, #-15
cmpge p0.d, p0/z, z0.d, #-1
CMPGE P0.D, P0/Z, Z0.D, #-1
cmpgt p0.b, p0/z, z0.b, z0.d
CMPGT P0.B, P0/Z, Z0.B, Z0.D
cmpgt p1.b, p0/z, z0.b, z0.d
CMPGT P1.B, P0/Z, Z0.B, Z0.D
cmpgt p15.b, p0/z, z0.b, z0.d
CMPGT P15.B, P0/Z, Z0.B, Z0.D
cmpgt p0.b, p2/z, z0.b, z0.d
CMPGT P0.B, P2/Z, Z0.B, Z0.D
cmpgt p0.b, p7/z, z0.b, z0.d
CMPGT P0.B, P7/Z, Z0.B, Z0.D
cmpgt p0.b, p0/z, z3.b, z0.d
CMPGT P0.B, P0/Z, Z3.B, Z0.D
cmpgt p0.b, p0/z, z31.b, z0.d
CMPGT P0.B, P0/Z, Z31.B, Z0.D
cmpgt p0.b, p0/z, z0.b, z4.d
CMPGT P0.B, P0/Z, Z0.B, Z4.D
cmpgt p0.b, p0/z, z0.b, z31.d
CMPGT P0.B, P0/Z, Z0.B, Z31.D
cmpgt p0.h, p0/z, z0.h, z0.d
CMPGT P0.H, P0/Z, Z0.H, Z0.D
cmpgt p1.h, p0/z, z0.h, z0.d
CMPGT P1.H, P0/Z, Z0.H, Z0.D
cmpgt p15.h, p0/z, z0.h, z0.d
CMPGT P15.H, P0/Z, Z0.H, Z0.D
cmpgt p0.h, p2/z, z0.h, z0.d
CMPGT P0.H, P2/Z, Z0.H, Z0.D
cmpgt p0.h, p7/z, z0.h, z0.d
CMPGT P0.H, P7/Z, Z0.H, Z0.D
cmpgt p0.h, p0/z, z3.h, z0.d
CMPGT P0.H, P0/Z, Z3.H, Z0.D
cmpgt p0.h, p0/z, z31.h, z0.d
CMPGT P0.H, P0/Z, Z31.H, Z0.D
cmpgt p0.h, p0/z, z0.h, z4.d
CMPGT P0.H, P0/Z, Z0.H, Z4.D
cmpgt p0.h, p0/z, z0.h, z31.d
CMPGT P0.H, P0/Z, Z0.H, Z31.D
cmpgt p0.s, p0/z, z0.s, z0.d
CMPGT P0.S, P0/Z, Z0.S, Z0.D
cmpgt p1.s, p0/z, z0.s, z0.d
CMPGT P1.S, P0/Z, Z0.S, Z0.D
cmpgt p15.s, p0/z, z0.s, z0.d
CMPGT P15.S, P0/Z, Z0.S, Z0.D
cmpgt p0.s, p2/z, z0.s, z0.d
CMPGT P0.S, P2/Z, Z0.S, Z0.D
cmpgt p0.s, p7/z, z0.s, z0.d
CMPGT P0.S, P7/Z, Z0.S, Z0.D
cmpgt p0.s, p0/z, z3.s, z0.d
CMPGT P0.S, P0/Z, Z3.S, Z0.D
cmpgt p0.s, p0/z, z31.s, z0.d
CMPGT P0.S, P0/Z, Z31.S, Z0.D
cmpgt p0.s, p0/z, z0.s, z4.d
CMPGT P0.S, P0/Z, Z0.S, Z4.D
cmpgt p0.s, p0/z, z0.s, z31.d
CMPGT P0.S, P0/Z, Z0.S, Z31.D
cmpgt p0.b, p0/z, z0.b, z0.b
CMPGT P0.B, P0/Z, Z0.B, Z0.B
cmpgt p1.b, p0/z, z0.b, z0.b
CMPGT P1.B, P0/Z, Z0.B, Z0.B
cmpgt p15.b, p0/z, z0.b, z0.b
CMPGT P15.B, P0/Z, Z0.B, Z0.B
cmpgt p0.b, p2/z, z0.b, z0.b
CMPGT P0.B, P2/Z, Z0.B, Z0.B
cmpgt p0.b, p7/z, z0.b, z0.b
CMPGT P0.B, P7/Z, Z0.B, Z0.B
cmpgt p0.b, p0/z, z3.b, z0.b
CMPGT P0.B, P0/Z, Z3.B, Z0.B
cmpgt p0.b, p0/z, z31.b, z0.b
CMPGT P0.B, P0/Z, Z31.B, Z0.B
cmpgt p0.b, p0/z, z0.b, z4.b
CMPGT P0.B, P0/Z, Z0.B, Z4.B
cmpgt p0.b, p0/z, z0.b, z31.b
CMPGT P0.B, P0/Z, Z0.B, Z31.B
cmpgt p0.h, p0/z, z0.h, z0.h
CMPGT P0.H, P0/Z, Z0.H, Z0.H
cmpgt p1.h, p0/z, z0.h, z0.h
CMPGT P1.H, P0/Z, Z0.H, Z0.H
cmpgt p15.h, p0/z, z0.h, z0.h
CMPGT P15.H, P0/Z, Z0.H, Z0.H
cmpgt p0.h, p2/z, z0.h, z0.h
CMPGT P0.H, P2/Z, Z0.H, Z0.H
cmpgt p0.h, p7/z, z0.h, z0.h
CMPGT P0.H, P7/Z, Z0.H, Z0.H
cmpgt p0.h, p0/z, z3.h, z0.h
CMPGT P0.H, P0/Z, Z3.H, Z0.H
cmpgt p0.h, p0/z, z31.h, z0.h
CMPGT P0.H, P0/Z, Z31.H, Z0.H
cmpgt p0.h, p0/z, z0.h, z4.h
CMPGT P0.H, P0/Z, Z0.H, Z4.H
cmpgt p0.h, p0/z, z0.h, z31.h
CMPGT P0.H, P0/Z, Z0.H, Z31.H
cmpgt p0.s, p0/z, z0.s, z0.s
CMPGT P0.S, P0/Z, Z0.S, Z0.S
cmpgt p1.s, p0/z, z0.s, z0.s
CMPGT P1.S, P0/Z, Z0.S, Z0.S
cmpgt p15.s, p0/z, z0.s, z0.s
CMPGT P15.S, P0/Z, Z0.S, Z0.S
cmpgt p0.s, p2/z, z0.s, z0.s
CMPGT P0.S, P2/Z, Z0.S, Z0.S
cmpgt p0.s, p7/z, z0.s, z0.s
CMPGT P0.S, P7/Z, Z0.S, Z0.S
cmpgt p0.s, p0/z, z3.s, z0.s
CMPGT P0.S, P0/Z, Z3.S, Z0.S
cmpgt p0.s, p0/z, z31.s, z0.s
CMPGT P0.S, P0/Z, Z31.S, Z0.S
cmpgt p0.s, p0/z, z0.s, z4.s
CMPGT P0.S, P0/Z, Z0.S, Z4.S
cmpgt p0.s, p0/z, z0.s, z31.s
CMPGT P0.S, P0/Z, Z0.S, Z31.S
cmpgt p0.d, p0/z, z0.d, z0.d
CMPGT P0.D, P0/Z, Z0.D, Z0.D
cmpgt p1.d, p0/z, z0.d, z0.d
CMPGT P1.D, P0/Z, Z0.D, Z0.D
cmpgt p15.d, p0/z, z0.d, z0.d
CMPGT P15.D, P0/Z, Z0.D, Z0.D
cmpgt p0.d, p2/z, z0.d, z0.d
CMPGT P0.D, P2/Z, Z0.D, Z0.D
cmpgt p0.d, p7/z, z0.d, z0.d
CMPGT P0.D, P7/Z, Z0.D, Z0.D
cmpgt p0.d, p0/z, z3.d, z0.d
CMPGT P0.D, P0/Z, Z3.D, Z0.D
cmpgt p0.d, p0/z, z31.d, z0.d
CMPGT P0.D, P0/Z, Z31.D, Z0.D
cmpgt p0.d, p0/z, z0.d, z4.d
CMPGT P0.D, P0/Z, Z0.D, Z4.D
cmpgt p0.d, p0/z, z0.d, z31.d
CMPGT P0.D, P0/Z, Z0.D, Z31.D
cmpgt p0.b, p0/z, z0.b, #0
CMPGT P0.B, P0/Z, Z0.B, #0
cmpgt p1.b, p0/z, z0.b, #0
CMPGT P1.B, P0/Z, Z0.B, #0
cmpgt p15.b, p0/z, z0.b, #0
CMPGT P15.B, P0/Z, Z0.B, #0
cmpgt p0.b, p2/z, z0.b, #0
CMPGT P0.B, P2/Z, Z0.B, #0
cmpgt p0.b, p7/z, z0.b, #0
CMPGT P0.B, P7/Z, Z0.B, #0
cmpgt p0.b, p0/z, z3.b, #0
CMPGT P0.B, P0/Z, Z3.B, #0
cmpgt p0.b, p0/z, z31.b, #0
CMPGT P0.B, P0/Z, Z31.B, #0
cmpgt p0.b, p0/z, z0.b, #15
CMPGT P0.B, P0/Z, Z0.B, #15
cmpgt p0.b, p0/z, z0.b, #-16
CMPGT P0.B, P0/Z, Z0.B, #-16
cmpgt p0.b, p0/z, z0.b, #-15
CMPGT P0.B, P0/Z, Z0.B, #-15
cmpgt p0.b, p0/z, z0.b, #-1
CMPGT P0.B, P0/Z, Z0.B, #-1
cmpgt p0.h, p0/z, z0.h, #0
CMPGT P0.H, P0/Z, Z0.H, #0
cmpgt p1.h, p0/z, z0.h, #0
CMPGT P1.H, P0/Z, Z0.H, #0
cmpgt p15.h, p0/z, z0.h, #0
CMPGT P15.H, P0/Z, Z0.H, #0
cmpgt p0.h, p2/z, z0.h, #0
CMPGT P0.H, P2/Z, Z0.H, #0
cmpgt p0.h, p7/z, z0.h, #0
CMPGT P0.H, P7/Z, Z0.H, #0
cmpgt p0.h, p0/z, z3.h, #0
CMPGT P0.H, P0/Z, Z3.H, #0
cmpgt p0.h, p0/z, z31.h, #0
CMPGT P0.H, P0/Z, Z31.H, #0
cmpgt p0.h, p0/z, z0.h, #15
CMPGT P0.H, P0/Z, Z0.H, #15
cmpgt p0.h, p0/z, z0.h, #-16
CMPGT P0.H, P0/Z, Z0.H, #-16
cmpgt p0.h, p0/z, z0.h, #-15
CMPGT P0.H, P0/Z, Z0.H, #-15
cmpgt p0.h, p0/z, z0.h, #-1
CMPGT P0.H, P0/Z, Z0.H, #-1
cmpgt p0.s, p0/z, z0.s, #0
CMPGT P0.S, P0/Z, Z0.S, #0
cmpgt p1.s, p0/z, z0.s, #0
CMPGT P1.S, P0/Z, Z0.S, #0
cmpgt p15.s, p0/z, z0.s, #0
CMPGT P15.S, P0/Z, Z0.S, #0
cmpgt p0.s, p2/z, z0.s, #0
CMPGT P0.S, P2/Z, Z0.S, #0
cmpgt p0.s, p7/z, z0.s, #0
CMPGT P0.S, P7/Z, Z0.S, #0
cmpgt p0.s, p0/z, z3.s, #0
CMPGT P0.S, P0/Z, Z3.S, #0
cmpgt p0.s, p0/z, z31.s, #0
CMPGT P0.S, P0/Z, Z31.S, #0
cmpgt p0.s, p0/z, z0.s, #15
CMPGT P0.S, P0/Z, Z0.S, #15
cmpgt p0.s, p0/z, z0.s, #-16
CMPGT P0.S, P0/Z, Z0.S, #-16
cmpgt p0.s, p0/z, z0.s, #-15
CMPGT P0.S, P0/Z, Z0.S, #-15
cmpgt p0.s, p0/z, z0.s, #-1
CMPGT P0.S, P0/Z, Z0.S, #-1
cmpgt p0.d, p0/z, z0.d, #0
CMPGT P0.D, P0/Z, Z0.D, #0
cmpgt p1.d, p0/z, z0.d, #0
CMPGT P1.D, P0/Z, Z0.D, #0
cmpgt p15.d, p0/z, z0.d, #0
CMPGT P15.D, P0/Z, Z0.D, #0
cmpgt p0.d, p2/z, z0.d, #0
CMPGT P0.D, P2/Z, Z0.D, #0
cmpgt p0.d, p7/z, z0.d, #0
CMPGT P0.D, P7/Z, Z0.D, #0
cmpgt p0.d, p0/z, z3.d, #0
CMPGT P0.D, P0/Z, Z3.D, #0
cmpgt p0.d, p0/z, z31.d, #0
CMPGT P0.D, P0/Z, Z31.D, #0
cmpgt p0.d, p0/z, z0.d, #15
CMPGT P0.D, P0/Z, Z0.D, #15
cmpgt p0.d, p0/z, z0.d, #-16
CMPGT P0.D, P0/Z, Z0.D, #-16
cmpgt p0.d, p0/z, z0.d, #-15
CMPGT P0.D, P0/Z, Z0.D, #-15
cmpgt p0.d, p0/z, z0.d, #-1
CMPGT P0.D, P0/Z, Z0.D, #-1
cmphi p0.b, p0/z, z0.b, z0.b
CMPHI P0.B, P0/Z, Z0.B, Z0.B
cmphi p1.b, p0/z, z0.b, z0.b
CMPHI P1.B, P0/Z, Z0.B, Z0.B
cmphi p15.b, p0/z, z0.b, z0.b
CMPHI P15.B, P0/Z, Z0.B, Z0.B
cmphi p0.b, p2/z, z0.b, z0.b
CMPHI P0.B, P2/Z, Z0.B, Z0.B
cmphi p0.b, p7/z, z0.b, z0.b
CMPHI P0.B, P7/Z, Z0.B, Z0.B
cmphi p0.b, p0/z, z3.b, z0.b
CMPHI P0.B, P0/Z, Z3.B, Z0.B
cmphi p0.b, p0/z, z31.b, z0.b
CMPHI P0.B, P0/Z, Z31.B, Z0.B
cmphi p0.b, p0/z, z0.b, z4.b
CMPHI P0.B, P0/Z, Z0.B, Z4.B
cmphi p0.b, p0/z, z0.b, z31.b
CMPHI P0.B, P0/Z, Z0.B, Z31.B
cmphi p0.h, p0/z, z0.h, z0.h
CMPHI P0.H, P0/Z, Z0.H, Z0.H
cmphi p1.h, p0/z, z0.h, z0.h
CMPHI P1.H, P0/Z, Z0.H, Z0.H
cmphi p15.h, p0/z, z0.h, z0.h
CMPHI P15.H, P0/Z, Z0.H, Z0.H
cmphi p0.h, p2/z, z0.h, z0.h
CMPHI P0.H, P2/Z, Z0.H, Z0.H
cmphi p0.h, p7/z, z0.h, z0.h
CMPHI P0.H, P7/Z, Z0.H, Z0.H
cmphi p0.h, p0/z, z3.h, z0.h
CMPHI P0.H, P0/Z, Z3.H, Z0.H
cmphi p0.h, p0/z, z31.h, z0.h
CMPHI P0.H, P0/Z, Z31.H, Z0.H
cmphi p0.h, p0/z, z0.h, z4.h
CMPHI P0.H, P0/Z, Z0.H, Z4.H
cmphi p0.h, p0/z, z0.h, z31.h
CMPHI P0.H, P0/Z, Z0.H, Z31.H
cmphi p0.s, p0/z, z0.s, z0.s
CMPHI P0.S, P0/Z, Z0.S, Z0.S
cmphi p1.s, p0/z, z0.s, z0.s
CMPHI P1.S, P0/Z, Z0.S, Z0.S
cmphi p15.s, p0/z, z0.s, z0.s
CMPHI P15.S, P0/Z, Z0.S, Z0.S
cmphi p0.s, p2/z, z0.s, z0.s
CMPHI P0.S, P2/Z, Z0.S, Z0.S
cmphi p0.s, p7/z, z0.s, z0.s
CMPHI P0.S, P7/Z, Z0.S, Z0.S
cmphi p0.s, p0/z, z3.s, z0.s
CMPHI P0.S, P0/Z, Z3.S, Z0.S
cmphi p0.s, p0/z, z31.s, z0.s
CMPHI P0.S, P0/Z, Z31.S, Z0.S
cmphi p0.s, p0/z, z0.s, z4.s
CMPHI P0.S, P0/Z, Z0.S, Z4.S
cmphi p0.s, p0/z, z0.s, z31.s
CMPHI P0.S, P0/Z, Z0.S, Z31.S
cmphi p0.d, p0/z, z0.d, z0.d
CMPHI P0.D, P0/Z, Z0.D, Z0.D
cmphi p1.d, p0/z, z0.d, z0.d
CMPHI P1.D, P0/Z, Z0.D, Z0.D
cmphi p15.d, p0/z, z0.d, z0.d
CMPHI P15.D, P0/Z, Z0.D, Z0.D
cmphi p0.d, p2/z, z0.d, z0.d
CMPHI P0.D, P2/Z, Z0.D, Z0.D
cmphi p0.d, p7/z, z0.d, z0.d
CMPHI P0.D, P7/Z, Z0.D, Z0.D
cmphi p0.d, p0/z, z3.d, z0.d
CMPHI P0.D, P0/Z, Z3.D, Z0.D
cmphi p0.d, p0/z, z31.d, z0.d
CMPHI P0.D, P0/Z, Z31.D, Z0.D
cmphi p0.d, p0/z, z0.d, z4.d
CMPHI P0.D, P0/Z, Z0.D, Z4.D
cmphi p0.d, p0/z, z0.d, z31.d
CMPHI P0.D, P0/Z, Z0.D, Z31.D
cmphi p0.b, p0/z, z0.b, z0.d
CMPHI P0.B, P0/Z, Z0.B, Z0.D
cmphi p1.b, p0/z, z0.b, z0.d
CMPHI P1.B, P0/Z, Z0.B, Z0.D
cmphi p15.b, p0/z, z0.b, z0.d
CMPHI P15.B, P0/Z, Z0.B, Z0.D
cmphi p0.b, p2/z, z0.b, z0.d
CMPHI P0.B, P2/Z, Z0.B, Z0.D
cmphi p0.b, p7/z, z0.b, z0.d
CMPHI P0.B, P7/Z, Z0.B, Z0.D
cmphi p0.b, p0/z, z3.b, z0.d
CMPHI P0.B, P0/Z, Z3.B, Z0.D
cmphi p0.b, p0/z, z31.b, z0.d
CMPHI P0.B, P0/Z, Z31.B, Z0.D
cmphi p0.b, p0/z, z0.b, z4.d
CMPHI P0.B, P0/Z, Z0.B, Z4.D
cmphi p0.b, p0/z, z0.b, z31.d
CMPHI P0.B, P0/Z, Z0.B, Z31.D
cmphi p0.h, p0/z, z0.h, z0.d
CMPHI P0.H, P0/Z, Z0.H, Z0.D
cmphi p1.h, p0/z, z0.h, z0.d
CMPHI P1.H, P0/Z, Z0.H, Z0.D
cmphi p15.h, p0/z, z0.h, z0.d
CMPHI P15.H, P0/Z, Z0.H, Z0.D
cmphi p0.h, p2/z, z0.h, z0.d
CMPHI P0.H, P2/Z, Z0.H, Z0.D
cmphi p0.h, p7/z, z0.h, z0.d
CMPHI P0.H, P7/Z, Z0.H, Z0.D
cmphi p0.h, p0/z, z3.h, z0.d
CMPHI P0.H, P0/Z, Z3.H, Z0.D
cmphi p0.h, p0/z, z31.h, z0.d
CMPHI P0.H, P0/Z, Z31.H, Z0.D
cmphi p0.h, p0/z, z0.h, z4.d
CMPHI P0.H, P0/Z, Z0.H, Z4.D
cmphi p0.h, p0/z, z0.h, z31.d
CMPHI P0.H, P0/Z, Z0.H, Z31.D
cmphi p0.s, p0/z, z0.s, z0.d
CMPHI P0.S, P0/Z, Z0.S, Z0.D
cmphi p1.s, p0/z, z0.s, z0.d
CMPHI P1.S, P0/Z, Z0.S, Z0.D
cmphi p15.s, p0/z, z0.s, z0.d
CMPHI P15.S, P0/Z, Z0.S, Z0.D
cmphi p0.s, p2/z, z0.s, z0.d
CMPHI P0.S, P2/Z, Z0.S, Z0.D
cmphi p0.s, p7/z, z0.s, z0.d
CMPHI P0.S, P7/Z, Z0.S, Z0.D
cmphi p0.s, p0/z, z3.s, z0.d
CMPHI P0.S, P0/Z, Z3.S, Z0.D
cmphi p0.s, p0/z, z31.s, z0.d
CMPHI P0.S, P0/Z, Z31.S, Z0.D
cmphi p0.s, p0/z, z0.s, z4.d
CMPHI P0.S, P0/Z, Z0.S, Z4.D
cmphi p0.s, p0/z, z0.s, z31.d
CMPHI P0.S, P0/Z, Z0.S, Z31.D
cmphi p0.b, p0/z, z0.b, #0
CMPHI P0.B, P0/Z, Z0.B, #0
cmphi p1.b, p0/z, z0.b, #0
CMPHI P1.B, P0/Z, Z0.B, #0
cmphi p15.b, p0/z, z0.b, #0
CMPHI P15.B, P0/Z, Z0.B, #0
cmphi p0.b, p2/z, z0.b, #0
CMPHI P0.B, P2/Z, Z0.B, #0
cmphi p0.b, p7/z, z0.b, #0
CMPHI P0.B, P7/Z, Z0.B, #0
cmphi p0.b, p0/z, z3.b, #0
CMPHI P0.B, P0/Z, Z3.B, #0
cmphi p0.b, p0/z, z31.b, #0
CMPHI P0.B, P0/Z, Z31.B, #0
cmphi p0.b, p0/z, z0.b, #63
CMPHI P0.B, P0/Z, Z0.B, #63
cmphi p0.b, p0/z, z0.b, #64
CMPHI P0.B, P0/Z, Z0.B, #64
cmphi p0.b, p0/z, z0.b, #65
CMPHI P0.B, P0/Z, Z0.B, #65
cmphi p0.b, p0/z, z0.b, #127
CMPHI P0.B, P0/Z, Z0.B, #127
cmphi p0.h, p0/z, z0.h, #0
CMPHI P0.H, P0/Z, Z0.H, #0
cmphi p1.h, p0/z, z0.h, #0
CMPHI P1.H, P0/Z, Z0.H, #0
cmphi p15.h, p0/z, z0.h, #0
CMPHI P15.H, P0/Z, Z0.H, #0
cmphi p0.h, p2/z, z0.h, #0
CMPHI P0.H, P2/Z, Z0.H, #0
cmphi p0.h, p7/z, z0.h, #0
CMPHI P0.H, P7/Z, Z0.H, #0
cmphi p0.h, p0/z, z3.h, #0
CMPHI P0.H, P0/Z, Z3.H, #0
cmphi p0.h, p0/z, z31.h, #0
CMPHI P0.H, P0/Z, Z31.H, #0
cmphi p0.h, p0/z, z0.h, #63
CMPHI P0.H, P0/Z, Z0.H, #63
cmphi p0.h, p0/z, z0.h, #64
CMPHI P0.H, P0/Z, Z0.H, #64
cmphi p0.h, p0/z, z0.h, #65
CMPHI P0.H, P0/Z, Z0.H, #65
cmphi p0.h, p0/z, z0.h, #127
CMPHI P0.H, P0/Z, Z0.H, #127
cmphi p0.s, p0/z, z0.s, #0
CMPHI P0.S, P0/Z, Z0.S, #0
cmphi p1.s, p0/z, z0.s, #0
CMPHI P1.S, P0/Z, Z0.S, #0
cmphi p15.s, p0/z, z0.s, #0
CMPHI P15.S, P0/Z, Z0.S, #0
cmphi p0.s, p2/z, z0.s, #0
CMPHI P0.S, P2/Z, Z0.S, #0
cmphi p0.s, p7/z, z0.s, #0
CMPHI P0.S, P7/Z, Z0.S, #0
cmphi p0.s, p0/z, z3.s, #0
CMPHI P0.S, P0/Z, Z3.S, #0
cmphi p0.s, p0/z, z31.s, #0
CMPHI P0.S, P0/Z, Z31.S, #0
cmphi p0.s, p0/z, z0.s, #63
CMPHI P0.S, P0/Z, Z0.S, #63
cmphi p0.s, p0/z, z0.s, #64
CMPHI P0.S, P0/Z, Z0.S, #64
cmphi p0.s, p0/z, z0.s, #65
CMPHI P0.S, P0/Z, Z0.S, #65
cmphi p0.s, p0/z, z0.s, #127
CMPHI P0.S, P0/Z, Z0.S, #127
cmphi p0.d, p0/z, z0.d, #0
CMPHI P0.D, P0/Z, Z0.D, #0
cmphi p1.d, p0/z, z0.d, #0
CMPHI P1.D, P0/Z, Z0.D, #0
cmphi p15.d, p0/z, z0.d, #0
CMPHI P15.D, P0/Z, Z0.D, #0
cmphi p0.d, p2/z, z0.d, #0
CMPHI P0.D, P2/Z, Z0.D, #0
cmphi p0.d, p7/z, z0.d, #0
CMPHI P0.D, P7/Z, Z0.D, #0
cmphi p0.d, p0/z, z3.d, #0
CMPHI P0.D, P0/Z, Z3.D, #0
cmphi p0.d, p0/z, z31.d, #0
CMPHI P0.D, P0/Z, Z31.D, #0
cmphi p0.d, p0/z, z0.d, #63
CMPHI P0.D, P0/Z, Z0.D, #63
cmphi p0.d, p0/z, z0.d, #64
CMPHI P0.D, P0/Z, Z0.D, #64
cmphi p0.d, p0/z, z0.d, #65
CMPHI P0.D, P0/Z, Z0.D, #65
cmphi p0.d, p0/z, z0.d, #127
CMPHI P0.D, P0/Z, Z0.D, #127
cmphs p0.b, p0/z, z0.b, z0.b
CMPHS P0.B, P0/Z, Z0.B, Z0.B
cmphs p1.b, p0/z, z0.b, z0.b
CMPHS P1.B, P0/Z, Z0.B, Z0.B
cmphs p15.b, p0/z, z0.b, z0.b
CMPHS P15.B, P0/Z, Z0.B, Z0.B
cmphs p0.b, p2/z, z0.b, z0.b
CMPHS P0.B, P2/Z, Z0.B, Z0.B
cmphs p0.b, p7/z, z0.b, z0.b
CMPHS P0.B, P7/Z, Z0.B, Z0.B
cmphs p0.b, p0/z, z3.b, z0.b
CMPHS P0.B, P0/Z, Z3.B, Z0.B
cmphs p0.b, p0/z, z31.b, z0.b
CMPHS P0.B, P0/Z, Z31.B, Z0.B
cmphs p0.b, p0/z, z0.b, z4.b
CMPHS P0.B, P0/Z, Z0.B, Z4.B
cmphs p0.b, p0/z, z0.b, z31.b
CMPHS P0.B, P0/Z, Z0.B, Z31.B
cmphs p0.h, p0/z, z0.h, z0.h
CMPHS P0.H, P0/Z, Z0.H, Z0.H
cmphs p1.h, p0/z, z0.h, z0.h
CMPHS P1.H, P0/Z, Z0.H, Z0.H
cmphs p15.h, p0/z, z0.h, z0.h
CMPHS P15.H, P0/Z, Z0.H, Z0.H
cmphs p0.h, p2/z, z0.h, z0.h
CMPHS P0.H, P2/Z, Z0.H, Z0.H
cmphs p0.h, p7/z, z0.h, z0.h
CMPHS P0.H, P7/Z, Z0.H, Z0.H
cmphs p0.h, p0/z, z3.h, z0.h
CMPHS P0.H, P0/Z, Z3.H, Z0.H
cmphs p0.h, p0/z, z31.h, z0.h
CMPHS P0.H, P0/Z, Z31.H, Z0.H
cmphs p0.h, p0/z, z0.h, z4.h
CMPHS P0.H, P0/Z, Z0.H, Z4.H
cmphs p0.h, p0/z, z0.h, z31.h
CMPHS P0.H, P0/Z, Z0.H, Z31.H
cmphs p0.s, p0/z, z0.s, z0.s
CMPHS P0.S, P0/Z, Z0.S, Z0.S
cmphs p1.s, p0/z, z0.s, z0.s
CMPHS P1.S, P0/Z, Z0.S, Z0.S
cmphs p15.s, p0/z, z0.s, z0.s
CMPHS P15.S, P0/Z, Z0.S, Z0.S
cmphs p0.s, p2/z, z0.s, z0.s
CMPHS P0.S, P2/Z, Z0.S, Z0.S
cmphs p0.s, p7/z, z0.s, z0.s
CMPHS P0.S, P7/Z, Z0.S, Z0.S
cmphs p0.s, p0/z, z3.s, z0.s
CMPHS P0.S, P0/Z, Z3.S, Z0.S
cmphs p0.s, p0/z, z31.s, z0.s
CMPHS P0.S, P0/Z, Z31.S, Z0.S
cmphs p0.s, p0/z, z0.s, z4.s
CMPHS P0.S, P0/Z, Z0.S, Z4.S
cmphs p0.s, p0/z, z0.s, z31.s
CMPHS P0.S, P0/Z, Z0.S, Z31.S
cmphs p0.d, p0/z, z0.d, z0.d
CMPHS P0.D, P0/Z, Z0.D, Z0.D
cmphs p1.d, p0/z, z0.d, z0.d
CMPHS P1.D, P0/Z, Z0.D, Z0.D
cmphs p15.d, p0/z, z0.d, z0.d
CMPHS P15.D, P0/Z, Z0.D, Z0.D
cmphs p0.d, p2/z, z0.d, z0.d
CMPHS P0.D, P2/Z, Z0.D, Z0.D
cmphs p0.d, p7/z, z0.d, z0.d
CMPHS P0.D, P7/Z, Z0.D, Z0.D
cmphs p0.d, p0/z, z3.d, z0.d
CMPHS P0.D, P0/Z, Z3.D, Z0.D
cmphs p0.d, p0/z, z31.d, z0.d
CMPHS P0.D, P0/Z, Z31.D, Z0.D
cmphs p0.d, p0/z, z0.d, z4.d
CMPHS P0.D, P0/Z, Z0.D, Z4.D
cmphs p0.d, p0/z, z0.d, z31.d
CMPHS P0.D, P0/Z, Z0.D, Z31.D
cmphs p0.b, p0/z, z0.b, z0.d
CMPHS P0.B, P0/Z, Z0.B, Z0.D
cmphs p1.b, p0/z, z0.b, z0.d
CMPHS P1.B, P0/Z, Z0.B, Z0.D
cmphs p15.b, p0/z, z0.b, z0.d
CMPHS P15.B, P0/Z, Z0.B, Z0.D
cmphs p0.b, p2/z, z0.b, z0.d
CMPHS P0.B, P2/Z, Z0.B, Z0.D
cmphs p0.b, p7/z, z0.b, z0.d
CMPHS P0.B, P7/Z, Z0.B, Z0.D
cmphs p0.b, p0/z, z3.b, z0.d
CMPHS P0.B, P0/Z, Z3.B, Z0.D
cmphs p0.b, p0/z, z31.b, z0.d
CMPHS P0.B, P0/Z, Z31.B, Z0.D
cmphs p0.b, p0/z, z0.b, z4.d
CMPHS P0.B, P0/Z, Z0.B, Z4.D
cmphs p0.b, p0/z, z0.b, z31.d
CMPHS P0.B, P0/Z, Z0.B, Z31.D
cmphs p0.h, p0/z, z0.h, z0.d
CMPHS P0.H, P0/Z, Z0.H, Z0.D
cmphs p1.h, p0/z, z0.h, z0.d
CMPHS P1.H, P0/Z, Z0.H, Z0.D
cmphs p15.h, p0/z, z0.h, z0.d
CMPHS P15.H, P0/Z, Z0.H, Z0.D
cmphs p0.h, p2/z, z0.h, z0.d
CMPHS P0.H, P2/Z, Z0.H, Z0.D
cmphs p0.h, p7/z, z0.h, z0.d
CMPHS P0.H, P7/Z, Z0.H, Z0.D
cmphs p0.h, p0/z, z3.h, z0.d
CMPHS P0.H, P0/Z, Z3.H, Z0.D
cmphs p0.h, p0/z, z31.h, z0.d
CMPHS P0.H, P0/Z, Z31.H, Z0.D
cmphs p0.h, p0/z, z0.h, z4.d
CMPHS P0.H, P0/Z, Z0.H, Z4.D
cmphs p0.h, p0/z, z0.h, z31.d
CMPHS P0.H, P0/Z, Z0.H, Z31.D
cmphs p0.s, p0/z, z0.s, z0.d
CMPHS P0.S, P0/Z, Z0.S, Z0.D
cmphs p1.s, p0/z, z0.s, z0.d
CMPHS P1.S, P0/Z, Z0.S, Z0.D
cmphs p15.s, p0/z, z0.s, z0.d
CMPHS P15.S, P0/Z, Z0.S, Z0.D
cmphs p0.s, p2/z, z0.s, z0.d
CMPHS P0.S, P2/Z, Z0.S, Z0.D
cmphs p0.s, p7/z, z0.s, z0.d
CMPHS P0.S, P7/Z, Z0.S, Z0.D
cmphs p0.s, p0/z, z3.s, z0.d
CMPHS P0.S, P0/Z, Z3.S, Z0.D
cmphs p0.s, p0/z, z31.s, z0.d
CMPHS P0.S, P0/Z, Z31.S, Z0.D
cmphs p0.s, p0/z, z0.s, z4.d
CMPHS P0.S, P0/Z, Z0.S, Z4.D
cmphs p0.s, p0/z, z0.s, z31.d
CMPHS P0.S, P0/Z, Z0.S, Z31.D
cmphs p0.b, p0/z, z0.b, #0
CMPHS P0.B, P0/Z, Z0.B, #0
cmphs p1.b, p0/z, z0.b, #0
CMPHS P1.B, P0/Z, Z0.B, #0
cmphs p15.b, p0/z, z0.b, #0
CMPHS P15.B, P0/Z, Z0.B, #0
cmphs p0.b, p2/z, z0.b, #0
CMPHS P0.B, P2/Z, Z0.B, #0
cmphs p0.b, p7/z, z0.b, #0
CMPHS P0.B, P7/Z, Z0.B, #0
cmphs p0.b, p0/z, z3.b, #0
CMPHS P0.B, P0/Z, Z3.B, #0
cmphs p0.b, p0/z, z31.b, #0
CMPHS P0.B, P0/Z, Z31.B, #0
cmphs p0.b, p0/z, z0.b, #63
CMPHS P0.B, P0/Z, Z0.B, #63
cmphs p0.b, p0/z, z0.b, #64
CMPHS P0.B, P0/Z, Z0.B, #64
cmphs p0.b, p0/z, z0.b, #65
CMPHS P0.B, P0/Z, Z0.B, #65
cmphs p0.b, p0/z, z0.b, #127
CMPHS P0.B, P0/Z, Z0.B, #127
cmphs p0.h, p0/z, z0.h, #0
CMPHS P0.H, P0/Z, Z0.H, #0
cmphs p1.h, p0/z, z0.h, #0
CMPHS P1.H, P0/Z, Z0.H, #0
cmphs p15.h, p0/z, z0.h, #0
CMPHS P15.H, P0/Z, Z0.H, #0
cmphs p0.h, p2/z, z0.h, #0
CMPHS P0.H, P2/Z, Z0.H, #0
cmphs p0.h, p7/z, z0.h, #0
CMPHS P0.H, P7/Z, Z0.H, #0
cmphs p0.h, p0/z, z3.h, #0
CMPHS P0.H, P0/Z, Z3.H, #0
cmphs p0.h, p0/z, z31.h, #0
CMPHS P0.H, P0/Z, Z31.H, #0
cmphs p0.h, p0/z, z0.h, #63
CMPHS P0.H, P0/Z, Z0.H, #63
cmphs p0.h, p0/z, z0.h, #64
CMPHS P0.H, P0/Z, Z0.H, #64
cmphs p0.h, p0/z, z0.h, #65
CMPHS P0.H, P0/Z, Z0.H, #65
cmphs p0.h, p0/z, z0.h, #127
CMPHS P0.H, P0/Z, Z0.H, #127
cmphs p0.s, p0/z, z0.s, #0
CMPHS P0.S, P0/Z, Z0.S, #0
cmphs p1.s, p0/z, z0.s, #0
CMPHS P1.S, P0/Z, Z0.S, #0
cmphs p15.s, p0/z, z0.s, #0
CMPHS P15.S, P0/Z, Z0.S, #0
cmphs p0.s, p2/z, z0.s, #0
CMPHS P0.S, P2/Z, Z0.S, #0
cmphs p0.s, p7/z, z0.s, #0
CMPHS P0.S, P7/Z, Z0.S, #0
cmphs p0.s, p0/z, z3.s, #0
CMPHS P0.S, P0/Z, Z3.S, #0
cmphs p0.s, p0/z, z31.s, #0
CMPHS P0.S, P0/Z, Z31.S, #0
cmphs p0.s, p0/z, z0.s, #63
CMPHS P0.S, P0/Z, Z0.S, #63
cmphs p0.s, p0/z, z0.s, #64
CMPHS P0.S, P0/Z, Z0.S, #64
cmphs p0.s, p0/z, z0.s, #65
CMPHS P0.S, P0/Z, Z0.S, #65
cmphs p0.s, p0/z, z0.s, #127
CMPHS P0.S, P0/Z, Z0.S, #127
cmphs p0.d, p0/z, z0.d, #0
CMPHS P0.D, P0/Z, Z0.D, #0
cmphs p1.d, p0/z, z0.d, #0
CMPHS P1.D, P0/Z, Z0.D, #0
cmphs p15.d, p0/z, z0.d, #0
CMPHS P15.D, P0/Z, Z0.D, #0
cmphs p0.d, p2/z, z0.d, #0
CMPHS P0.D, P2/Z, Z0.D, #0
cmphs p0.d, p7/z, z0.d, #0
CMPHS P0.D, P7/Z, Z0.D, #0
cmphs p0.d, p0/z, z3.d, #0
CMPHS P0.D, P0/Z, Z3.D, #0
cmphs p0.d, p0/z, z31.d, #0
CMPHS P0.D, P0/Z, Z31.D, #0
cmphs p0.d, p0/z, z0.d, #63
CMPHS P0.D, P0/Z, Z0.D, #63
cmphs p0.d, p0/z, z0.d, #64
CMPHS P0.D, P0/Z, Z0.D, #64
cmphs p0.d, p0/z, z0.d, #65
CMPHS P0.D, P0/Z, Z0.D, #65
cmphs p0.d, p0/z, z0.d, #127
CMPHS P0.D, P0/Z, Z0.D, #127
cmple p0.b, p0/z, z0.b, z0.d
CMPLE P0.B, P0/Z, Z0.B, Z0.D
cmple p1.b, p0/z, z0.b, z0.d
CMPLE P1.B, P0/Z, Z0.B, Z0.D
cmple p15.b, p0/z, z0.b, z0.d
CMPLE P15.B, P0/Z, Z0.B, Z0.D
cmple p0.b, p2/z, z0.b, z0.d
CMPLE P0.B, P2/Z, Z0.B, Z0.D
cmple p0.b, p7/z, z0.b, z0.d
CMPLE P0.B, P7/Z, Z0.B, Z0.D
cmple p0.b, p0/z, z3.b, z0.d
CMPLE P0.B, P0/Z, Z3.B, Z0.D
cmple p0.b, p0/z, z31.b, z0.d
CMPLE P0.B, P0/Z, Z31.B, Z0.D
cmple p0.b, p0/z, z0.b, z4.d
CMPLE P0.B, P0/Z, Z0.B, Z4.D
cmple p0.b, p0/z, z0.b, z31.d
CMPLE P0.B, P0/Z, Z0.B, Z31.D
cmple p0.h, p0/z, z0.h, z0.d
CMPLE P0.H, P0/Z, Z0.H, Z0.D
cmple p1.h, p0/z, z0.h, z0.d
CMPLE P1.H, P0/Z, Z0.H, Z0.D
cmple p15.h, p0/z, z0.h, z0.d
CMPLE P15.H, P0/Z, Z0.H, Z0.D
cmple p0.h, p2/z, z0.h, z0.d
CMPLE P0.H, P2/Z, Z0.H, Z0.D
cmple p0.h, p7/z, z0.h, z0.d
CMPLE P0.H, P7/Z, Z0.H, Z0.D
cmple p0.h, p0/z, z3.h, z0.d
CMPLE P0.H, P0/Z, Z3.H, Z0.D
cmple p0.h, p0/z, z31.h, z0.d
CMPLE P0.H, P0/Z, Z31.H, Z0.D
cmple p0.h, p0/z, z0.h, z4.d
CMPLE P0.H, P0/Z, Z0.H, Z4.D
cmple p0.h, p0/z, z0.h, z31.d
CMPLE P0.H, P0/Z, Z0.H, Z31.D
cmple p0.s, p0/z, z0.s, z0.d
CMPLE P0.S, P0/Z, Z0.S, Z0.D
cmple p1.s, p0/z, z0.s, z0.d
CMPLE P1.S, P0/Z, Z0.S, Z0.D
cmple p15.s, p0/z, z0.s, z0.d
CMPLE P15.S, P0/Z, Z0.S, Z0.D
cmple p0.s, p2/z, z0.s, z0.d
CMPLE P0.S, P2/Z, Z0.S, Z0.D
cmple p0.s, p7/z, z0.s, z0.d
CMPLE P0.S, P7/Z, Z0.S, Z0.D
cmple p0.s, p0/z, z3.s, z0.d
CMPLE P0.S, P0/Z, Z3.S, Z0.D
cmple p0.s, p0/z, z31.s, z0.d
CMPLE P0.S, P0/Z, Z31.S, Z0.D
cmple p0.s, p0/z, z0.s, z4.d
CMPLE P0.S, P0/Z, Z0.S, Z4.D
cmple p0.s, p0/z, z0.s, z31.d
CMPLE P0.S, P0/Z, Z0.S, Z31.D
cmple p0.b, p0/z, z0.b, #0
CMPLE P0.B, P0/Z, Z0.B, #0
cmple p1.b, p0/z, z0.b, #0
CMPLE P1.B, P0/Z, Z0.B, #0
cmple p15.b, p0/z, z0.b, #0
CMPLE P15.B, P0/Z, Z0.B, #0
cmple p0.b, p2/z, z0.b, #0
CMPLE P0.B, P2/Z, Z0.B, #0
cmple p0.b, p7/z, z0.b, #0
CMPLE P0.B, P7/Z, Z0.B, #0
cmple p0.b, p0/z, z3.b, #0
CMPLE P0.B, P0/Z, Z3.B, #0
cmple p0.b, p0/z, z31.b, #0
CMPLE P0.B, P0/Z, Z31.B, #0
cmple p0.b, p0/z, z0.b, #15
CMPLE P0.B, P0/Z, Z0.B, #15
cmple p0.b, p0/z, z0.b, #-16
CMPLE P0.B, P0/Z, Z0.B, #-16
cmple p0.b, p0/z, z0.b, #-15
CMPLE P0.B, P0/Z, Z0.B, #-15
cmple p0.b, p0/z, z0.b, #-1
CMPLE P0.B, P0/Z, Z0.B, #-1
cmple p0.h, p0/z, z0.h, #0
CMPLE P0.H, P0/Z, Z0.H, #0
cmple p1.h, p0/z, z0.h, #0
CMPLE P1.H, P0/Z, Z0.H, #0
cmple p15.h, p0/z, z0.h, #0
CMPLE P15.H, P0/Z, Z0.H, #0
cmple p0.h, p2/z, z0.h, #0
CMPLE P0.H, P2/Z, Z0.H, #0
cmple p0.h, p7/z, z0.h, #0
CMPLE P0.H, P7/Z, Z0.H, #0
cmple p0.h, p0/z, z3.h, #0
CMPLE P0.H, P0/Z, Z3.H, #0
cmple p0.h, p0/z, z31.h, #0
CMPLE P0.H, P0/Z, Z31.H, #0
cmple p0.h, p0/z, z0.h, #15
CMPLE P0.H, P0/Z, Z0.H, #15
cmple p0.h, p0/z, z0.h, #-16
CMPLE P0.H, P0/Z, Z0.H, #-16
cmple p0.h, p0/z, z0.h, #-15
CMPLE P0.H, P0/Z, Z0.H, #-15
cmple p0.h, p0/z, z0.h, #-1
CMPLE P0.H, P0/Z, Z0.H, #-1
cmple p0.s, p0/z, z0.s, #0
CMPLE P0.S, P0/Z, Z0.S, #0
cmple p1.s, p0/z, z0.s, #0
CMPLE P1.S, P0/Z, Z0.S, #0
cmple p15.s, p0/z, z0.s, #0
CMPLE P15.S, P0/Z, Z0.S, #0
cmple p0.s, p2/z, z0.s, #0
CMPLE P0.S, P2/Z, Z0.S, #0
cmple p0.s, p7/z, z0.s, #0
CMPLE P0.S, P7/Z, Z0.S, #0
cmple p0.s, p0/z, z3.s, #0
CMPLE P0.S, P0/Z, Z3.S, #0
cmple p0.s, p0/z, z31.s, #0
CMPLE P0.S, P0/Z, Z31.S, #0
cmple p0.s, p0/z, z0.s, #15
CMPLE P0.S, P0/Z, Z0.S, #15
cmple p0.s, p0/z, z0.s, #-16
CMPLE P0.S, P0/Z, Z0.S, #-16
cmple p0.s, p0/z, z0.s, #-15
CMPLE P0.S, P0/Z, Z0.S, #-15
cmple p0.s, p0/z, z0.s, #-1
CMPLE P0.S, P0/Z, Z0.S, #-1
cmple p0.d, p0/z, z0.d, #0
CMPLE P0.D, P0/Z, Z0.D, #0
cmple p1.d, p0/z, z0.d, #0
CMPLE P1.D, P0/Z, Z0.D, #0
cmple p15.d, p0/z, z0.d, #0
CMPLE P15.D, P0/Z, Z0.D, #0
cmple p0.d, p2/z, z0.d, #0
CMPLE P0.D, P2/Z, Z0.D, #0
cmple p0.d, p7/z, z0.d, #0
CMPLE P0.D, P7/Z, Z0.D, #0
cmple p0.d, p0/z, z3.d, #0
CMPLE P0.D, P0/Z, Z3.D, #0
cmple p0.d, p0/z, z31.d, #0
CMPLE P0.D, P0/Z, Z31.D, #0
cmple p0.d, p0/z, z0.d, #15
CMPLE P0.D, P0/Z, Z0.D, #15
cmple p0.d, p0/z, z0.d, #-16
CMPLE P0.D, P0/Z, Z0.D, #-16
cmple p0.d, p0/z, z0.d, #-15
CMPLE P0.D, P0/Z, Z0.D, #-15
cmple p0.d, p0/z, z0.d, #-1
CMPLE P0.D, P0/Z, Z0.D, #-1
cmplo p0.b, p0/z, z0.b, z0.d
CMPLO P0.B, P0/Z, Z0.B, Z0.D
cmplo p1.b, p0/z, z0.b, z0.d
CMPLO P1.B, P0/Z, Z0.B, Z0.D
cmplo p15.b, p0/z, z0.b, z0.d
CMPLO P15.B, P0/Z, Z0.B, Z0.D
cmplo p0.b, p2/z, z0.b, z0.d
CMPLO P0.B, P2/Z, Z0.B, Z0.D
cmplo p0.b, p7/z, z0.b, z0.d
CMPLO P0.B, P7/Z, Z0.B, Z0.D
cmplo p0.b, p0/z, z3.b, z0.d
CMPLO P0.B, P0/Z, Z3.B, Z0.D
cmplo p0.b, p0/z, z31.b, z0.d
CMPLO P0.B, P0/Z, Z31.B, Z0.D
cmplo p0.b, p0/z, z0.b, z4.d
CMPLO P0.B, P0/Z, Z0.B, Z4.D
cmplo p0.b, p0/z, z0.b, z31.d
CMPLO P0.B, P0/Z, Z0.B, Z31.D
cmplo p0.h, p0/z, z0.h, z0.d
CMPLO P0.H, P0/Z, Z0.H, Z0.D
cmplo p1.h, p0/z, z0.h, z0.d
CMPLO P1.H, P0/Z, Z0.H, Z0.D
cmplo p15.h, p0/z, z0.h, z0.d
CMPLO P15.H, P0/Z, Z0.H, Z0.D
cmplo p0.h, p2/z, z0.h, z0.d
CMPLO P0.H, P2/Z, Z0.H, Z0.D
cmplo p0.h, p7/z, z0.h, z0.d
CMPLO P0.H, P7/Z, Z0.H, Z0.D
cmplo p0.h, p0/z, z3.h, z0.d
CMPLO P0.H, P0/Z, Z3.H, Z0.D
cmplo p0.h, p0/z, z31.h, z0.d
CMPLO P0.H, P0/Z, Z31.H, Z0.D
cmplo p0.h, p0/z, z0.h, z4.d
CMPLO P0.H, P0/Z, Z0.H, Z4.D
cmplo p0.h, p0/z, z0.h, z31.d
CMPLO P0.H, P0/Z, Z0.H, Z31.D
cmplo p0.s, p0/z, z0.s, z0.d
CMPLO P0.S, P0/Z, Z0.S, Z0.D
cmplo p1.s, p0/z, z0.s, z0.d
CMPLO P1.S, P0/Z, Z0.S, Z0.D
cmplo p15.s, p0/z, z0.s, z0.d
CMPLO P15.S, P0/Z, Z0.S, Z0.D
cmplo p0.s, p2/z, z0.s, z0.d
CMPLO P0.S, P2/Z, Z0.S, Z0.D
cmplo p0.s, p7/z, z0.s, z0.d
CMPLO P0.S, P7/Z, Z0.S, Z0.D
cmplo p0.s, p0/z, z3.s, z0.d
CMPLO P0.S, P0/Z, Z3.S, Z0.D
cmplo p0.s, p0/z, z31.s, z0.d
CMPLO P0.S, P0/Z, Z31.S, Z0.D
cmplo p0.s, p0/z, z0.s, z4.d
CMPLO P0.S, P0/Z, Z0.S, Z4.D
cmplo p0.s, p0/z, z0.s, z31.d
CMPLO P0.S, P0/Z, Z0.S, Z31.D
cmplo p0.b, p0/z, z0.b, #0
CMPLO P0.B, P0/Z, Z0.B, #0
cmplo p1.b, p0/z, z0.b, #0
CMPLO P1.B, P0/Z, Z0.B, #0
cmplo p15.b, p0/z, z0.b, #0
CMPLO P15.B, P0/Z, Z0.B, #0
cmplo p0.b, p2/z, z0.b, #0
CMPLO P0.B, P2/Z, Z0.B, #0
cmplo p0.b, p7/z, z0.b, #0
CMPLO P0.B, P7/Z, Z0.B, #0
cmplo p0.b, p0/z, z3.b, #0
CMPLO P0.B, P0/Z, Z3.B, #0
cmplo p0.b, p0/z, z31.b, #0
CMPLO P0.B, P0/Z, Z31.B, #0
cmplo p0.b, p0/z, z0.b, #63
CMPLO P0.B, P0/Z, Z0.B, #63
cmplo p0.b, p0/z, z0.b, #64
CMPLO P0.B, P0/Z, Z0.B, #64
cmplo p0.b, p0/z, z0.b, #65
CMPLO P0.B, P0/Z, Z0.B, #65
cmplo p0.b, p0/z, z0.b, #127
CMPLO P0.B, P0/Z, Z0.B, #127
cmplo p0.h, p0/z, z0.h, #0
CMPLO P0.H, P0/Z, Z0.H, #0
cmplo p1.h, p0/z, z0.h, #0
CMPLO P1.H, P0/Z, Z0.H, #0
cmplo p15.h, p0/z, z0.h, #0
CMPLO P15.H, P0/Z, Z0.H, #0
cmplo p0.h, p2/z, z0.h, #0
CMPLO P0.H, P2/Z, Z0.H, #0
cmplo p0.h, p7/z, z0.h, #0
CMPLO P0.H, P7/Z, Z0.H, #0
cmplo p0.h, p0/z, z3.h, #0
CMPLO P0.H, P0/Z, Z3.H, #0
cmplo p0.h, p0/z, z31.h, #0
CMPLO P0.H, P0/Z, Z31.H, #0
cmplo p0.h, p0/z, z0.h, #63
CMPLO P0.H, P0/Z, Z0.H, #63
cmplo p0.h, p0/z, z0.h, #64
CMPLO P0.H, P0/Z, Z0.H, #64
cmplo p0.h, p0/z, z0.h, #65
CMPLO P0.H, P0/Z, Z0.H, #65
cmplo p0.h, p0/z, z0.h, #127
CMPLO P0.H, P0/Z, Z0.H, #127
cmplo p0.s, p0/z, z0.s, #0
CMPLO P0.S, P0/Z, Z0.S, #0
cmplo p1.s, p0/z, z0.s, #0
CMPLO P1.S, P0/Z, Z0.S, #0
cmplo p15.s, p0/z, z0.s, #0
CMPLO P15.S, P0/Z, Z0.S, #0
cmplo p0.s, p2/z, z0.s, #0
CMPLO P0.S, P2/Z, Z0.S, #0
cmplo p0.s, p7/z, z0.s, #0
CMPLO P0.S, P7/Z, Z0.S, #0
cmplo p0.s, p0/z, z3.s, #0
CMPLO P0.S, P0/Z, Z3.S, #0
cmplo p0.s, p0/z, z31.s, #0
CMPLO P0.S, P0/Z, Z31.S, #0
cmplo p0.s, p0/z, z0.s, #63
CMPLO P0.S, P0/Z, Z0.S, #63
cmplo p0.s, p0/z, z0.s, #64
CMPLO P0.S, P0/Z, Z0.S, #64
cmplo p0.s, p0/z, z0.s, #65
CMPLO P0.S, P0/Z, Z0.S, #65
cmplo p0.s, p0/z, z0.s, #127
CMPLO P0.S, P0/Z, Z0.S, #127
cmplo p0.d, p0/z, z0.d, #0
CMPLO P0.D, P0/Z, Z0.D, #0
cmplo p1.d, p0/z, z0.d, #0
CMPLO P1.D, P0/Z, Z0.D, #0
cmplo p15.d, p0/z, z0.d, #0
CMPLO P15.D, P0/Z, Z0.D, #0
cmplo p0.d, p2/z, z0.d, #0
CMPLO P0.D, P2/Z, Z0.D, #0
cmplo p0.d, p7/z, z0.d, #0
CMPLO P0.D, P7/Z, Z0.D, #0
cmplo p0.d, p0/z, z3.d, #0
CMPLO P0.D, P0/Z, Z3.D, #0
cmplo p0.d, p0/z, z31.d, #0
CMPLO P0.D, P0/Z, Z31.D, #0
cmplo p0.d, p0/z, z0.d, #63
CMPLO P0.D, P0/Z, Z0.D, #63
cmplo p0.d, p0/z, z0.d, #64
CMPLO P0.D, P0/Z, Z0.D, #64
cmplo p0.d, p0/z, z0.d, #65
CMPLO P0.D, P0/Z, Z0.D, #65
cmplo p0.d, p0/z, z0.d, #127
CMPLO P0.D, P0/Z, Z0.D, #127
cmpls p0.b, p0/z, z0.b, z0.d
CMPLS P0.B, P0/Z, Z0.B, Z0.D
cmpls p1.b, p0/z, z0.b, z0.d
CMPLS P1.B, P0/Z, Z0.B, Z0.D
cmpls p15.b, p0/z, z0.b, z0.d
CMPLS P15.B, P0/Z, Z0.B, Z0.D
cmpls p0.b, p2/z, z0.b, z0.d
CMPLS P0.B, P2/Z, Z0.B, Z0.D
cmpls p0.b, p7/z, z0.b, z0.d
CMPLS P0.B, P7/Z, Z0.B, Z0.D
cmpls p0.b, p0/z, z3.b, z0.d
CMPLS P0.B, P0/Z, Z3.B, Z0.D
cmpls p0.b, p0/z, z31.b, z0.d
CMPLS P0.B, P0/Z, Z31.B, Z0.D
cmpls p0.b, p0/z, z0.b, z4.d
CMPLS P0.B, P0/Z, Z0.B, Z4.D
cmpls p0.b, p0/z, z0.b, z31.d
CMPLS P0.B, P0/Z, Z0.B, Z31.D
cmpls p0.h, p0/z, z0.h, z0.d
CMPLS P0.H, P0/Z, Z0.H, Z0.D
cmpls p1.h, p0/z, z0.h, z0.d
CMPLS P1.H, P0/Z, Z0.H, Z0.D
cmpls p15.h, p0/z, z0.h, z0.d
CMPLS P15.H, P0/Z, Z0.H, Z0.D
cmpls p0.h, p2/z, z0.h, z0.d
CMPLS P0.H, P2/Z, Z0.H, Z0.D
cmpls p0.h, p7/z, z0.h, z0.d
CMPLS P0.H, P7/Z, Z0.H, Z0.D
cmpls p0.h, p0/z, z3.h, z0.d
CMPLS P0.H, P0/Z, Z3.H, Z0.D
cmpls p0.h, p0/z, z31.h, z0.d
CMPLS P0.H, P0/Z, Z31.H, Z0.D
cmpls p0.h, p0/z, z0.h, z4.d
CMPLS P0.H, P0/Z, Z0.H, Z4.D
cmpls p0.h, p0/z, z0.h, z31.d
CMPLS P0.H, P0/Z, Z0.H, Z31.D
cmpls p0.s, p0/z, z0.s, z0.d
CMPLS P0.S, P0/Z, Z0.S, Z0.D
cmpls p1.s, p0/z, z0.s, z0.d
CMPLS P1.S, P0/Z, Z0.S, Z0.D
cmpls p15.s, p0/z, z0.s, z0.d
CMPLS P15.S, P0/Z, Z0.S, Z0.D
cmpls p0.s, p2/z, z0.s, z0.d
CMPLS P0.S, P2/Z, Z0.S, Z0.D
cmpls p0.s, p7/z, z0.s, z0.d
CMPLS P0.S, P7/Z, Z0.S, Z0.D
cmpls p0.s, p0/z, z3.s, z0.d
CMPLS P0.S, P0/Z, Z3.S, Z0.D
cmpls p0.s, p0/z, z31.s, z0.d
CMPLS P0.S, P0/Z, Z31.S, Z0.D
cmpls p0.s, p0/z, z0.s, z4.d
CMPLS P0.S, P0/Z, Z0.S, Z4.D
cmpls p0.s, p0/z, z0.s, z31.d
CMPLS P0.S, P0/Z, Z0.S, Z31.D
cmpls p0.b, p0/z, z0.b, #0
CMPLS P0.B, P0/Z, Z0.B, #0
cmpls p1.b, p0/z, z0.b, #0
CMPLS P1.B, P0/Z, Z0.B, #0
cmpls p15.b, p0/z, z0.b, #0
CMPLS P15.B, P0/Z, Z0.B, #0
cmpls p0.b, p2/z, z0.b, #0
CMPLS P0.B, P2/Z, Z0.B, #0
cmpls p0.b, p7/z, z0.b, #0
CMPLS P0.B, P7/Z, Z0.B, #0
cmpls p0.b, p0/z, z3.b, #0
CMPLS P0.B, P0/Z, Z3.B, #0
cmpls p0.b, p0/z, z31.b, #0
CMPLS P0.B, P0/Z, Z31.B, #0
cmpls p0.b, p0/z, z0.b, #63
CMPLS P0.B, P0/Z, Z0.B, #63
cmpls p0.b, p0/z, z0.b, #64
CMPLS P0.B, P0/Z, Z0.B, #64
cmpls p0.b, p0/z, z0.b, #65
CMPLS P0.B, P0/Z, Z0.B, #65
cmpls p0.b, p0/z, z0.b, #127
CMPLS P0.B, P0/Z, Z0.B, #127
cmpls p0.h, p0/z, z0.h, #0
CMPLS P0.H, P0/Z, Z0.H, #0
cmpls p1.h, p0/z, z0.h, #0
CMPLS P1.H, P0/Z, Z0.H, #0
cmpls p15.h, p0/z, z0.h, #0
CMPLS P15.H, P0/Z, Z0.H, #0
cmpls p0.h, p2/z, z0.h, #0
CMPLS P0.H, P2/Z, Z0.H, #0
cmpls p0.h, p7/z, z0.h, #0
CMPLS P0.H, P7/Z, Z0.H, #0
cmpls p0.h, p0/z, z3.h, #0
CMPLS P0.H, P0/Z, Z3.H, #0
cmpls p0.h, p0/z, z31.h, #0
CMPLS P0.H, P0/Z, Z31.H, #0
cmpls p0.h, p0/z, z0.h, #63
CMPLS P0.H, P0/Z, Z0.H, #63
cmpls p0.h, p0/z, z0.h, #64
CMPLS P0.H, P0/Z, Z0.H, #64
cmpls p0.h, p0/z, z0.h, #65
CMPLS P0.H, P0/Z, Z0.H, #65
cmpls p0.h, p0/z, z0.h, #127
CMPLS P0.H, P0/Z, Z0.H, #127
cmpls p0.s, p0/z, z0.s, #0
CMPLS P0.S, P0/Z, Z0.S, #0
cmpls p1.s, p0/z, z0.s, #0
CMPLS P1.S, P0/Z, Z0.S, #0
cmpls p15.s, p0/z, z0.s, #0
CMPLS P15.S, P0/Z, Z0.S, #0
cmpls p0.s, p2/z, z0.s, #0
CMPLS P0.S, P2/Z, Z0.S, #0
cmpls p0.s, p7/z, z0.s, #0
CMPLS P0.S, P7/Z, Z0.S, #0
cmpls p0.s, p0/z, z3.s, #0
CMPLS P0.S, P0/Z, Z3.S, #0
cmpls p0.s, p0/z, z31.s, #0
CMPLS P0.S, P0/Z, Z31.S, #0
cmpls p0.s, p0/z, z0.s, #63
CMPLS P0.S, P0/Z, Z0.S, #63
cmpls p0.s, p0/z, z0.s, #64
CMPLS P0.S, P0/Z, Z0.S, #64
cmpls p0.s, p0/z, z0.s, #65
CMPLS P0.S, P0/Z, Z0.S, #65
cmpls p0.s, p0/z, z0.s, #127
CMPLS P0.S, P0/Z, Z0.S, #127
cmpls p0.d, p0/z, z0.d, #0
CMPLS P0.D, P0/Z, Z0.D, #0
cmpls p1.d, p0/z, z0.d, #0
CMPLS P1.D, P0/Z, Z0.D, #0
cmpls p15.d, p0/z, z0.d, #0
CMPLS P15.D, P0/Z, Z0.D, #0
cmpls p0.d, p2/z, z0.d, #0
CMPLS P0.D, P2/Z, Z0.D, #0
cmpls p0.d, p7/z, z0.d, #0
CMPLS P0.D, P7/Z, Z0.D, #0
cmpls p0.d, p0/z, z3.d, #0
CMPLS P0.D, P0/Z, Z3.D, #0
cmpls p0.d, p0/z, z31.d, #0
CMPLS P0.D, P0/Z, Z31.D, #0
cmpls p0.d, p0/z, z0.d, #63
CMPLS P0.D, P0/Z, Z0.D, #63
cmpls p0.d, p0/z, z0.d, #64
CMPLS P0.D, P0/Z, Z0.D, #64
cmpls p0.d, p0/z, z0.d, #65
CMPLS P0.D, P0/Z, Z0.D, #65
cmpls p0.d, p0/z, z0.d, #127
CMPLS P0.D, P0/Z, Z0.D, #127
cmplt p0.b, p0/z, z0.b, z0.d
CMPLT P0.B, P0/Z, Z0.B, Z0.D
cmplt p1.b, p0/z, z0.b, z0.d
CMPLT P1.B, P0/Z, Z0.B, Z0.D
cmplt p15.b, p0/z, z0.b, z0.d
CMPLT P15.B, P0/Z, Z0.B, Z0.D
cmplt p0.b, p2/z, z0.b, z0.d
CMPLT P0.B, P2/Z, Z0.B, Z0.D
cmplt p0.b, p7/z, z0.b, z0.d
CMPLT P0.B, P7/Z, Z0.B, Z0.D
cmplt p0.b, p0/z, z3.b, z0.d
CMPLT P0.B, P0/Z, Z3.B, Z0.D
cmplt p0.b, p0/z, z31.b, z0.d
CMPLT P0.B, P0/Z, Z31.B, Z0.D
cmplt p0.b, p0/z, z0.b, z4.d
CMPLT P0.B, P0/Z, Z0.B, Z4.D
cmplt p0.b, p0/z, z0.b, z31.d
CMPLT P0.B, P0/Z, Z0.B, Z31.D
cmplt p0.h, p0/z, z0.h, z0.d
CMPLT P0.H, P0/Z, Z0.H, Z0.D
cmplt p1.h, p0/z, z0.h, z0.d
CMPLT P1.H, P0/Z, Z0.H, Z0.D
cmplt p15.h, p0/z, z0.h, z0.d
CMPLT P15.H, P0/Z, Z0.H, Z0.D
cmplt p0.h, p2/z, z0.h, z0.d
CMPLT P0.H, P2/Z, Z0.H, Z0.D
cmplt p0.h, p7/z, z0.h, z0.d
CMPLT P0.H, P7/Z, Z0.H, Z0.D
cmplt p0.h, p0/z, z3.h, z0.d
CMPLT P0.H, P0/Z, Z3.H, Z0.D
cmplt p0.h, p0/z, z31.h, z0.d
CMPLT P0.H, P0/Z, Z31.H, Z0.D
cmplt p0.h, p0/z, z0.h, z4.d
CMPLT P0.H, P0/Z, Z0.H, Z4.D
cmplt p0.h, p0/z, z0.h, z31.d
CMPLT P0.H, P0/Z, Z0.H, Z31.D
cmplt p0.s, p0/z, z0.s, z0.d
CMPLT P0.S, P0/Z, Z0.S, Z0.D
cmplt p1.s, p0/z, z0.s, z0.d
CMPLT P1.S, P0/Z, Z0.S, Z0.D
cmplt p15.s, p0/z, z0.s, z0.d
CMPLT P15.S, P0/Z, Z0.S, Z0.D
cmplt p0.s, p2/z, z0.s, z0.d
CMPLT P0.S, P2/Z, Z0.S, Z0.D
cmplt p0.s, p7/z, z0.s, z0.d
CMPLT P0.S, P7/Z, Z0.S, Z0.D
cmplt p0.s, p0/z, z3.s, z0.d
CMPLT P0.S, P0/Z, Z3.S, Z0.D
cmplt p0.s, p0/z, z31.s, z0.d
CMPLT P0.S, P0/Z, Z31.S, Z0.D
cmplt p0.s, p0/z, z0.s, z4.d
CMPLT P0.S, P0/Z, Z0.S, Z4.D
cmplt p0.s, p0/z, z0.s, z31.d
CMPLT P0.S, P0/Z, Z0.S, Z31.D
cmplt p0.b, p0/z, z0.b, #0
CMPLT P0.B, P0/Z, Z0.B, #0
cmplt p1.b, p0/z, z0.b, #0
CMPLT P1.B, P0/Z, Z0.B, #0
cmplt p15.b, p0/z, z0.b, #0
CMPLT P15.B, P0/Z, Z0.B, #0
cmplt p0.b, p2/z, z0.b, #0
CMPLT P0.B, P2/Z, Z0.B, #0
cmplt p0.b, p7/z, z0.b, #0
CMPLT P0.B, P7/Z, Z0.B, #0
cmplt p0.b, p0/z, z3.b, #0
CMPLT P0.B, P0/Z, Z3.B, #0
cmplt p0.b, p0/z, z31.b, #0
CMPLT P0.B, P0/Z, Z31.B, #0
cmplt p0.b, p0/z, z0.b, #15
CMPLT P0.B, P0/Z, Z0.B, #15
cmplt p0.b, p0/z, z0.b, #-16
CMPLT P0.B, P0/Z, Z0.B, #-16
cmplt p0.b, p0/z, z0.b, #-15
CMPLT P0.B, P0/Z, Z0.B, #-15
cmplt p0.b, p0/z, z0.b, #-1
CMPLT P0.B, P0/Z, Z0.B, #-1
cmplt p0.h, p0/z, z0.h, #0
CMPLT P0.H, P0/Z, Z0.H, #0
cmplt p1.h, p0/z, z0.h, #0
CMPLT P1.H, P0/Z, Z0.H, #0
cmplt p15.h, p0/z, z0.h, #0
CMPLT P15.H, P0/Z, Z0.H, #0
cmplt p0.h, p2/z, z0.h, #0
CMPLT P0.H, P2/Z, Z0.H, #0
cmplt p0.h, p7/z, z0.h, #0
CMPLT P0.H, P7/Z, Z0.H, #0
cmplt p0.h, p0/z, z3.h, #0
CMPLT P0.H, P0/Z, Z3.H, #0
cmplt p0.h, p0/z, z31.h, #0
CMPLT P0.H, P0/Z, Z31.H, #0
cmplt p0.h, p0/z, z0.h, #15
CMPLT P0.H, P0/Z, Z0.H, #15
cmplt p0.h, p0/z, z0.h, #-16
CMPLT P0.H, P0/Z, Z0.H, #-16
cmplt p0.h, p0/z, z0.h, #-15
CMPLT P0.H, P0/Z, Z0.H, #-15
cmplt p0.h, p0/z, z0.h, #-1
CMPLT P0.H, P0/Z, Z0.H, #-1
cmplt p0.s, p0/z, z0.s, #0
CMPLT P0.S, P0/Z, Z0.S, #0
cmplt p1.s, p0/z, z0.s, #0
CMPLT P1.S, P0/Z, Z0.S, #0
cmplt p15.s, p0/z, z0.s, #0
CMPLT P15.S, P0/Z, Z0.S, #0
cmplt p0.s, p2/z, z0.s, #0
CMPLT P0.S, P2/Z, Z0.S, #0
cmplt p0.s, p7/z, z0.s, #0
CMPLT P0.S, P7/Z, Z0.S, #0
cmplt p0.s, p0/z, z3.s, #0
CMPLT P0.S, P0/Z, Z3.S, #0
cmplt p0.s, p0/z, z31.s, #0
CMPLT P0.S, P0/Z, Z31.S, #0
cmplt p0.s, p0/z, z0.s, #15
CMPLT P0.S, P0/Z, Z0.S, #15
cmplt p0.s, p0/z, z0.s, #-16
CMPLT P0.S, P0/Z, Z0.S, #-16
cmplt p0.s, p0/z, z0.s, #-15
CMPLT P0.S, P0/Z, Z0.S, #-15
cmplt p0.s, p0/z, z0.s, #-1
CMPLT P0.S, P0/Z, Z0.S, #-1
cmplt p0.d, p0/z, z0.d, #0
CMPLT P0.D, P0/Z, Z0.D, #0
cmplt p1.d, p0/z, z0.d, #0
CMPLT P1.D, P0/Z, Z0.D, #0
cmplt p15.d, p0/z, z0.d, #0
CMPLT P15.D, P0/Z, Z0.D, #0
cmplt p0.d, p2/z, z0.d, #0
CMPLT P0.D, P2/Z, Z0.D, #0
cmplt p0.d, p7/z, z0.d, #0
CMPLT P0.D, P7/Z, Z0.D, #0
cmplt p0.d, p0/z, z3.d, #0
CMPLT P0.D, P0/Z, Z3.D, #0
cmplt p0.d, p0/z, z31.d, #0
CMPLT P0.D, P0/Z, Z31.D, #0
cmplt p0.d, p0/z, z0.d, #15
CMPLT P0.D, P0/Z, Z0.D, #15
cmplt p0.d, p0/z, z0.d, #-16
CMPLT P0.D, P0/Z, Z0.D, #-16
cmplt p0.d, p0/z, z0.d, #-15
CMPLT P0.D, P0/Z, Z0.D, #-15
cmplt p0.d, p0/z, z0.d, #-1
CMPLT P0.D, P0/Z, Z0.D, #-1
cmpne p0.b, p0/z, z0.b, z0.d
CMPNE P0.B, P0/Z, Z0.B, Z0.D
cmpne p1.b, p0/z, z0.b, z0.d
CMPNE P1.B, P0/Z, Z0.B, Z0.D
cmpne p15.b, p0/z, z0.b, z0.d
CMPNE P15.B, P0/Z, Z0.B, Z0.D
cmpne p0.b, p2/z, z0.b, z0.d
CMPNE P0.B, P2/Z, Z0.B, Z0.D
cmpne p0.b, p7/z, z0.b, z0.d
CMPNE P0.B, P7/Z, Z0.B, Z0.D
cmpne p0.b, p0/z, z3.b, z0.d
CMPNE P0.B, P0/Z, Z3.B, Z0.D
cmpne p0.b, p0/z, z31.b, z0.d
CMPNE P0.B, P0/Z, Z31.B, Z0.D
cmpne p0.b, p0/z, z0.b, z4.d
CMPNE P0.B, P0/Z, Z0.B, Z4.D
cmpne p0.b, p0/z, z0.b, z31.d
CMPNE P0.B, P0/Z, Z0.B, Z31.D
cmpne p0.h, p0/z, z0.h, z0.d
CMPNE P0.H, P0/Z, Z0.H, Z0.D
cmpne p1.h, p0/z, z0.h, z0.d
CMPNE P1.H, P0/Z, Z0.H, Z0.D
cmpne p15.h, p0/z, z0.h, z0.d
CMPNE P15.H, P0/Z, Z0.H, Z0.D
cmpne p0.h, p2/z, z0.h, z0.d
CMPNE P0.H, P2/Z, Z0.H, Z0.D
cmpne p0.h, p7/z, z0.h, z0.d
CMPNE P0.H, P7/Z, Z0.H, Z0.D
cmpne p0.h, p0/z, z3.h, z0.d
CMPNE P0.H, P0/Z, Z3.H, Z0.D
cmpne p0.h, p0/z, z31.h, z0.d
CMPNE P0.H, P0/Z, Z31.H, Z0.D
cmpne p0.h, p0/z, z0.h, z4.d
CMPNE P0.H, P0/Z, Z0.H, Z4.D
cmpne p0.h, p0/z, z0.h, z31.d
CMPNE P0.H, P0/Z, Z0.H, Z31.D
cmpne p0.s, p0/z, z0.s, z0.d
CMPNE P0.S, P0/Z, Z0.S, Z0.D
cmpne p1.s, p0/z, z0.s, z0.d
CMPNE P1.S, P0/Z, Z0.S, Z0.D
cmpne p15.s, p0/z, z0.s, z0.d
CMPNE P15.S, P0/Z, Z0.S, Z0.D
cmpne p0.s, p2/z, z0.s, z0.d
CMPNE P0.S, P2/Z, Z0.S, Z0.D
cmpne p0.s, p7/z, z0.s, z0.d
CMPNE P0.S, P7/Z, Z0.S, Z0.D
cmpne p0.s, p0/z, z3.s, z0.d
CMPNE P0.S, P0/Z, Z3.S, Z0.D
cmpne p0.s, p0/z, z31.s, z0.d
CMPNE P0.S, P0/Z, Z31.S, Z0.D
cmpne p0.s, p0/z, z0.s, z4.d
CMPNE P0.S, P0/Z, Z0.S, Z4.D
cmpne p0.s, p0/z, z0.s, z31.d
CMPNE P0.S, P0/Z, Z0.S, Z31.D
cmpne p0.b, p0/z, z0.b, z0.b
CMPNE P0.B, P0/Z, Z0.B, Z0.B
cmpne p1.b, p0/z, z0.b, z0.b
CMPNE P1.B, P0/Z, Z0.B, Z0.B
cmpne p15.b, p0/z, z0.b, z0.b
CMPNE P15.B, P0/Z, Z0.B, Z0.B
cmpne p0.b, p2/z, z0.b, z0.b
CMPNE P0.B, P2/Z, Z0.B, Z0.B
cmpne p0.b, p7/z, z0.b, z0.b
CMPNE P0.B, P7/Z, Z0.B, Z0.B
cmpne p0.b, p0/z, z3.b, z0.b
CMPNE P0.B, P0/Z, Z3.B, Z0.B
cmpne p0.b, p0/z, z31.b, z0.b
CMPNE P0.B, P0/Z, Z31.B, Z0.B
cmpne p0.b, p0/z, z0.b, z4.b
CMPNE P0.B, P0/Z, Z0.B, Z4.B
cmpne p0.b, p0/z, z0.b, z31.b
CMPNE P0.B, P0/Z, Z0.B, Z31.B
cmpne p0.h, p0/z, z0.h, z0.h
CMPNE P0.H, P0/Z, Z0.H, Z0.H
cmpne p1.h, p0/z, z0.h, z0.h
CMPNE P1.H, P0/Z, Z0.H, Z0.H
cmpne p15.h, p0/z, z0.h, z0.h
CMPNE P15.H, P0/Z, Z0.H, Z0.H
cmpne p0.h, p2/z, z0.h, z0.h
CMPNE P0.H, P2/Z, Z0.H, Z0.H
cmpne p0.h, p7/z, z0.h, z0.h
CMPNE P0.H, P7/Z, Z0.H, Z0.H
cmpne p0.h, p0/z, z3.h, z0.h
CMPNE P0.H, P0/Z, Z3.H, Z0.H
cmpne p0.h, p0/z, z31.h, z0.h
CMPNE P0.H, P0/Z, Z31.H, Z0.H
cmpne p0.h, p0/z, z0.h, z4.h
CMPNE P0.H, P0/Z, Z0.H, Z4.H
cmpne p0.h, p0/z, z0.h, z31.h
CMPNE P0.H, P0/Z, Z0.H, Z31.H
cmpne p0.s, p0/z, z0.s, z0.s
CMPNE P0.S, P0/Z, Z0.S, Z0.S
cmpne p1.s, p0/z, z0.s, z0.s
CMPNE P1.S, P0/Z, Z0.S, Z0.S
cmpne p15.s, p0/z, z0.s, z0.s
CMPNE P15.S, P0/Z, Z0.S, Z0.S
cmpne p0.s, p2/z, z0.s, z0.s
CMPNE P0.S, P2/Z, Z0.S, Z0.S
cmpne p0.s, p7/z, z0.s, z0.s
CMPNE P0.S, P7/Z, Z0.S, Z0.S
cmpne p0.s, p0/z, z3.s, z0.s
CMPNE P0.S, P0/Z, Z3.S, Z0.S
cmpne p0.s, p0/z, z31.s, z0.s
CMPNE P0.S, P0/Z, Z31.S, Z0.S
cmpne p0.s, p0/z, z0.s, z4.s
CMPNE P0.S, P0/Z, Z0.S, Z4.S
cmpne p0.s, p0/z, z0.s, z31.s
CMPNE P0.S, P0/Z, Z0.S, Z31.S
cmpne p0.d, p0/z, z0.d, z0.d
CMPNE P0.D, P0/Z, Z0.D, Z0.D
cmpne p1.d, p0/z, z0.d, z0.d
CMPNE P1.D, P0/Z, Z0.D, Z0.D
cmpne p15.d, p0/z, z0.d, z0.d
CMPNE P15.D, P0/Z, Z0.D, Z0.D
cmpne p0.d, p2/z, z0.d, z0.d
CMPNE P0.D, P2/Z, Z0.D, Z0.D
cmpne p0.d, p7/z, z0.d, z0.d
CMPNE P0.D, P7/Z, Z0.D, Z0.D
cmpne p0.d, p0/z, z3.d, z0.d
CMPNE P0.D, P0/Z, Z3.D, Z0.D
cmpne p0.d, p0/z, z31.d, z0.d
CMPNE P0.D, P0/Z, Z31.D, Z0.D
cmpne p0.d, p0/z, z0.d, z4.d
CMPNE P0.D, P0/Z, Z0.D, Z4.D
cmpne p0.d, p0/z, z0.d, z31.d
CMPNE P0.D, P0/Z, Z0.D, Z31.D
cmpne p0.b, p0/z, z0.b, #0
CMPNE P0.B, P0/Z, Z0.B, #0
cmpne p1.b, p0/z, z0.b, #0
CMPNE P1.B, P0/Z, Z0.B, #0
cmpne p15.b, p0/z, z0.b, #0
CMPNE P15.B, P0/Z, Z0.B, #0
cmpne p0.b, p2/z, z0.b, #0
CMPNE P0.B, P2/Z, Z0.B, #0
cmpne p0.b, p7/z, z0.b, #0
CMPNE P0.B, P7/Z, Z0.B, #0
cmpne p0.b, p0/z, z3.b, #0
CMPNE P0.B, P0/Z, Z3.B, #0
cmpne p0.b, p0/z, z31.b, #0
CMPNE P0.B, P0/Z, Z31.B, #0
cmpne p0.b, p0/z, z0.b, #15
CMPNE P0.B, P0/Z, Z0.B, #15
cmpne p0.b, p0/z, z0.b, #-16
CMPNE P0.B, P0/Z, Z0.B, #-16
cmpne p0.b, p0/z, z0.b, #-15
CMPNE P0.B, P0/Z, Z0.B, #-15
cmpne p0.b, p0/z, z0.b, #-1
CMPNE P0.B, P0/Z, Z0.B, #-1
cmpne p0.h, p0/z, z0.h, #0
CMPNE P0.H, P0/Z, Z0.H, #0
cmpne p1.h, p0/z, z0.h, #0
CMPNE P1.H, P0/Z, Z0.H, #0
cmpne p15.h, p0/z, z0.h, #0
CMPNE P15.H, P0/Z, Z0.H, #0
cmpne p0.h, p2/z, z0.h, #0
CMPNE P0.H, P2/Z, Z0.H, #0
cmpne p0.h, p7/z, z0.h, #0
CMPNE P0.H, P7/Z, Z0.H, #0
cmpne p0.h, p0/z, z3.h, #0
CMPNE P0.H, P0/Z, Z3.H, #0
cmpne p0.h, p0/z, z31.h, #0
CMPNE P0.H, P0/Z, Z31.H, #0
cmpne p0.h, p0/z, z0.h, #15
CMPNE P0.H, P0/Z, Z0.H, #15
cmpne p0.h, p0/z, z0.h, #-16
CMPNE P0.H, P0/Z, Z0.H, #-16
cmpne p0.h, p0/z, z0.h, #-15
CMPNE P0.H, P0/Z, Z0.H, #-15
cmpne p0.h, p0/z, z0.h, #-1
CMPNE P0.H, P0/Z, Z0.H, #-1
cmpne p0.s, p0/z, z0.s, #0
CMPNE P0.S, P0/Z, Z0.S, #0
cmpne p1.s, p0/z, z0.s, #0
CMPNE P1.S, P0/Z, Z0.S, #0
cmpne p15.s, p0/z, z0.s, #0
CMPNE P15.S, P0/Z, Z0.S, #0
cmpne p0.s, p2/z, z0.s, #0
CMPNE P0.S, P2/Z, Z0.S, #0
cmpne p0.s, p7/z, z0.s, #0
CMPNE P0.S, P7/Z, Z0.S, #0
cmpne p0.s, p0/z, z3.s, #0
CMPNE P0.S, P0/Z, Z3.S, #0
cmpne p0.s, p0/z, z31.s, #0
CMPNE P0.S, P0/Z, Z31.S, #0
cmpne p0.s, p0/z, z0.s, #15
CMPNE P0.S, P0/Z, Z0.S, #15
cmpne p0.s, p0/z, z0.s, #-16
CMPNE P0.S, P0/Z, Z0.S, #-16
cmpne p0.s, p0/z, z0.s, #-15
CMPNE P0.S, P0/Z, Z0.S, #-15
cmpne p0.s, p0/z, z0.s, #-1
CMPNE P0.S, P0/Z, Z0.S, #-1
cmpne p0.d, p0/z, z0.d, #0
CMPNE P0.D, P0/Z, Z0.D, #0
cmpne p1.d, p0/z, z0.d, #0
CMPNE P1.D, P0/Z, Z0.D, #0
cmpne p15.d, p0/z, z0.d, #0
CMPNE P15.D, P0/Z, Z0.D, #0
cmpne p0.d, p2/z, z0.d, #0
CMPNE P0.D, P2/Z, Z0.D, #0
cmpne p0.d, p7/z, z0.d, #0
CMPNE P0.D, P7/Z, Z0.D, #0
cmpne p0.d, p0/z, z3.d, #0
CMPNE P0.D, P0/Z, Z3.D, #0
cmpne p0.d, p0/z, z31.d, #0
CMPNE P0.D, P0/Z, Z31.D, #0
cmpne p0.d, p0/z, z0.d, #15
CMPNE P0.D, P0/Z, Z0.D, #15
cmpne p0.d, p0/z, z0.d, #-16
CMPNE P0.D, P0/Z, Z0.D, #-16
cmpne p0.d, p0/z, z0.d, #-15
CMPNE P0.D, P0/Z, Z0.D, #-15
cmpne p0.d, p0/z, z0.d, #-1
CMPNE P0.D, P0/Z, Z0.D, #-1
cnot z0.b, p0/m, z0.b
CNOT Z0.B, P0/M, Z0.B
cnot z1.b, p0/m, z0.b
CNOT Z1.B, P0/M, Z0.B
cnot z31.b, p0/m, z0.b
CNOT Z31.B, P0/M, Z0.B
cnot z0.b, p2/m, z0.b
CNOT Z0.B, P2/M, Z0.B
cnot z0.b, p7/m, z0.b
CNOT Z0.B, P7/M, Z0.B
cnot z0.b, p0/m, z3.b
CNOT Z0.B, P0/M, Z3.B
cnot z0.b, p0/m, z31.b
CNOT Z0.B, P0/M, Z31.B
cnot z0.h, p0/m, z0.h
CNOT Z0.H, P0/M, Z0.H
cnot z1.h, p0/m, z0.h
CNOT Z1.H, P0/M, Z0.H
cnot z31.h, p0/m, z0.h
CNOT Z31.H, P0/M, Z0.H
cnot z0.h, p2/m, z0.h
CNOT Z0.H, P2/M, Z0.H
cnot z0.h, p7/m, z0.h
CNOT Z0.H, P7/M, Z0.H
cnot z0.h, p0/m, z3.h
CNOT Z0.H, P0/M, Z3.H
cnot z0.h, p0/m, z31.h
CNOT Z0.H, P0/M, Z31.H
cnot z0.s, p0/m, z0.s
CNOT Z0.S, P0/M, Z0.S
cnot z1.s, p0/m, z0.s
CNOT Z1.S, P0/M, Z0.S
cnot z31.s, p0/m, z0.s
CNOT Z31.S, P0/M, Z0.S
cnot z0.s, p2/m, z0.s
CNOT Z0.S, P2/M, Z0.S
cnot z0.s, p7/m, z0.s
CNOT Z0.S, P7/M, Z0.S
cnot z0.s, p0/m, z3.s
CNOT Z0.S, P0/M, Z3.S
cnot z0.s, p0/m, z31.s
CNOT Z0.S, P0/M, Z31.S
cnot z0.d, p0/m, z0.d
CNOT Z0.D, P0/M, Z0.D
cnot z1.d, p0/m, z0.d
CNOT Z1.D, P0/M, Z0.D
cnot z31.d, p0/m, z0.d
CNOT Z31.D, P0/M, Z0.D
cnot z0.d, p2/m, z0.d
CNOT Z0.D, P2/M, Z0.D
cnot z0.d, p7/m, z0.d
CNOT Z0.D, P7/M, Z0.D
cnot z0.d, p0/m, z3.d
CNOT Z0.D, P0/M, Z3.D
cnot z0.d, p0/m, z31.d
CNOT Z0.D, P0/M, Z31.D
cnt z0.b, p0/m, z0.b
CNT Z0.B, P0/M, Z0.B
cnt z1.b, p0/m, z0.b
CNT Z1.B, P0/M, Z0.B
cnt z31.b, p0/m, z0.b
CNT Z31.B, P0/M, Z0.B
cnt z0.b, p2/m, z0.b
CNT Z0.B, P2/M, Z0.B
cnt z0.b, p7/m, z0.b
CNT Z0.B, P7/M, Z0.B
cnt z0.b, p0/m, z3.b
CNT Z0.B, P0/M, Z3.B
cnt z0.b, p0/m, z31.b
CNT Z0.B, P0/M, Z31.B
cnt z0.h, p0/m, z0.h
CNT Z0.H, P0/M, Z0.H
cnt z1.h, p0/m, z0.h
CNT Z1.H, P0/M, Z0.H
cnt z31.h, p0/m, z0.h
CNT Z31.H, P0/M, Z0.H
cnt z0.h, p2/m, z0.h
CNT Z0.H, P2/M, Z0.H
cnt z0.h, p7/m, z0.h
CNT Z0.H, P7/M, Z0.H
cnt z0.h, p0/m, z3.h
CNT Z0.H, P0/M, Z3.H
cnt z0.h, p0/m, z31.h
CNT Z0.H, P0/M, Z31.H
cnt z0.s, p0/m, z0.s
CNT Z0.S, P0/M, Z0.S
cnt z1.s, p0/m, z0.s
CNT Z1.S, P0/M, Z0.S
cnt z31.s, p0/m, z0.s
CNT Z31.S, P0/M, Z0.S
cnt z0.s, p2/m, z0.s
CNT Z0.S, P2/M, Z0.S
cnt z0.s, p7/m, z0.s
CNT Z0.S, P7/M, Z0.S
cnt z0.s, p0/m, z3.s
CNT Z0.S, P0/M, Z3.S
cnt z0.s, p0/m, z31.s
CNT Z0.S, P0/M, Z31.S
cnt z0.d, p0/m, z0.d
CNT Z0.D, P0/M, Z0.D
cnt z1.d, p0/m, z0.d
CNT Z1.D, P0/M, Z0.D
cnt z31.d, p0/m, z0.d
CNT Z31.D, P0/M, Z0.D
cnt z0.d, p2/m, z0.d
CNT Z0.D, P2/M, Z0.D
cnt z0.d, p7/m, z0.d
CNT Z0.D, P7/M, Z0.D
cnt z0.d, p0/m, z3.d
CNT Z0.D, P0/M, Z3.D
cnt z0.d, p0/m, z31.d
CNT Z0.D, P0/M, Z31.D
cntb x0, pow2
CNTB X0, POW2
cntb x0, pow2, mul #1
cntb x1, pow2
CNTB X1, POW2
cntb x1, pow2, mul #1
cntb xzr, pow2
CNTB XZR, POW2
cntb xzr, pow2, mul #1
cntb x0, vl1
CNTB X0, VL1
cntb x0, vl1, mul #1
cntb x0, vl2
CNTB X0, VL2
cntb x0, vl2, mul #1
cntb x0, vl3
CNTB X0, VL3
cntb x0, vl3, mul #1
cntb x0, vl4
CNTB X0, VL4
cntb x0, vl4, mul #1
cntb x0, vl5
CNTB X0, VL5
cntb x0, vl5, mul #1
cntb x0, vl6
CNTB X0, VL6
cntb x0, vl6, mul #1
cntb x0, vl7
CNTB X0, VL7
cntb x0, vl7, mul #1
cntb x0, vl8
CNTB X0, VL8
cntb x0, vl8, mul #1
cntb x0, vl16
CNTB X0, VL16
cntb x0, vl16, mul #1
cntb x0, vl32
CNTB X0, VL32
cntb x0, vl32, mul #1
cntb x0, vl64
CNTB X0, VL64
cntb x0, vl64, mul #1
cntb x0, vl128
CNTB X0, VL128
cntb x0, vl128, mul #1
cntb x0, vl256
CNTB X0, VL256
cntb x0, vl256, mul #1
cntb x0, #14
CNTB X0, #14
cntb x0, #14, mul #1
cntb x0, #15
CNTB X0, #15
cntb x0, #15, mul #1
cntb x0, #16
CNTB X0, #16
cntb x0, #16, mul #1
cntb x0, #17
CNTB X0, #17
cntb x0, #17, mul #1
cntb x0, #18
CNTB X0, #18
cntb x0, #18, mul #1
cntb x0, #19
CNTB X0, #19
cntb x0, #19, mul #1
cntb x0, #20
CNTB X0, #20
cntb x0, #20, mul #1
cntb x0, #21
CNTB X0, #21
cntb x0, #21, mul #1
cntb x0, #22
CNTB X0, #22
cntb x0, #22, mul #1
cntb x0, #23
CNTB X0, #23
cntb x0, #23, mul #1
cntb x0, #24
CNTB X0, #24
cntb x0, #24, mul #1
cntb x0, #25
CNTB X0, #25
cntb x0, #25, mul #1
cntb x0, #26
CNTB X0, #26
cntb x0, #26, mul #1
cntb x0, #27
CNTB X0, #27
cntb x0, #27, mul #1
cntb x0, #28
CNTB X0, #28
cntb x0, #28, mul #1
cntb x0, mul4
CNTB X0, MUL4
cntb x0, mul4, mul #1
cntb x0, mul3
CNTB X0, MUL3
cntb x0, mul3, mul #1
cntb x0
CNTB X0
cntb x0, all
cntb x0, all, mul #1
cntb x0, pow2, mul #8
CNTB X0, POW2, MUL #8
cntb x0, pow2, mul #9
CNTB X0, POW2, MUL #9
cntb x0, pow2, mul #10
CNTB X0, POW2, MUL #10
cntb x0, pow2, mul #16
CNTB X0, POW2, MUL #16
cntd x0, pow2
CNTD X0, POW2
cntd x0, pow2, mul #1
cntd x1, pow2
CNTD X1, POW2
cntd x1, pow2, mul #1
cntd xzr, pow2
CNTD XZR, POW2
cntd xzr, pow2, mul #1
cntd x0, vl1
CNTD X0, VL1
cntd x0, vl1, mul #1
cntd x0, vl2
CNTD X0, VL2
cntd x0, vl2, mul #1
cntd x0, vl3
CNTD X0, VL3
cntd x0, vl3, mul #1
cntd x0, vl4
CNTD X0, VL4
cntd x0, vl4, mul #1
cntd x0, vl5
CNTD X0, VL5
cntd x0, vl5, mul #1
cntd x0, vl6
CNTD X0, VL6
cntd x0, vl6, mul #1
cntd x0, vl7
CNTD X0, VL7
cntd x0, vl7, mul #1
cntd x0, vl8
CNTD X0, VL8
cntd x0, vl8, mul #1
cntd x0, vl16
CNTD X0, VL16
cntd x0, vl16, mul #1
cntd x0, vl32
CNTD X0, VL32
cntd x0, vl32, mul #1
cntd x0, vl64
CNTD X0, VL64
cntd x0, vl64, mul #1
cntd x0, vl128
CNTD X0, VL128
cntd x0, vl128, mul #1
cntd x0, vl256
CNTD X0, VL256
cntd x0, vl256, mul #1
cntd x0, #14
CNTD X0, #14
cntd x0, #14, mul #1
cntd x0, #15
CNTD X0, #15
cntd x0, #15, mul #1
cntd x0, #16
CNTD X0, #16
cntd x0, #16, mul #1
cntd x0, #17
CNTD X0, #17
cntd x0, #17, mul #1
cntd x0, #18
CNTD X0, #18
cntd x0, #18, mul #1
cntd x0, #19
CNTD X0, #19
cntd x0, #19, mul #1
cntd x0, #20
CNTD X0, #20
cntd x0, #20, mul #1
cntd x0, #21
CNTD X0, #21
cntd x0, #21, mul #1
cntd x0, #22
CNTD X0, #22
cntd x0, #22, mul #1
cntd x0, #23
CNTD X0, #23
cntd x0, #23, mul #1
cntd x0, #24
CNTD X0, #24
cntd x0, #24, mul #1
cntd x0, #25
CNTD X0, #25
cntd x0, #25, mul #1
cntd x0, #26
CNTD X0, #26
cntd x0, #26, mul #1
cntd x0, #27
CNTD X0, #27
cntd x0, #27, mul #1
cntd x0, #28
CNTD X0, #28
cntd x0, #28, mul #1
cntd x0, mul4
CNTD X0, MUL4
cntd x0, mul4, mul #1
cntd x0, mul3
CNTD X0, MUL3
cntd x0, mul3, mul #1
cntd x0
CNTD X0
cntd x0, all
cntd x0, all, mul #1
cntd x0, pow2, mul #8
CNTD X0, POW2, MUL #8
cntd x0, pow2, mul #9
CNTD X0, POW2, MUL #9
cntd x0, pow2, mul #10
CNTD X0, POW2, MUL #10
cntd x0, pow2, mul #16
CNTD X0, POW2, MUL #16
cnth x0, pow2
CNTH X0, POW2
cnth x0, pow2, mul #1
cnth x1, pow2
CNTH X1, POW2
cnth x1, pow2, mul #1
cnth xzr, pow2
CNTH XZR, POW2
cnth xzr, pow2, mul #1
cnth x0, vl1
CNTH X0, VL1
cnth x0, vl1, mul #1
cnth x0, vl2
CNTH X0, VL2
cnth x0, vl2, mul #1
cnth x0, vl3
CNTH X0, VL3
cnth x0, vl3, mul #1
cnth x0, vl4
CNTH X0, VL4
cnth x0, vl4, mul #1
cnth x0, vl5
CNTH X0, VL5
cnth x0, vl5, mul #1
cnth x0, vl6
CNTH X0, VL6
cnth x0, vl6, mul #1
cnth x0, vl7
CNTH X0, VL7
cnth x0, vl7, mul #1
cnth x0, vl8
CNTH X0, VL8
cnth x0, vl8, mul #1
cnth x0, vl16
CNTH X0, VL16
cnth x0, vl16, mul #1
cnth x0, vl32
CNTH X0, VL32
cnth x0, vl32, mul #1
cnth x0, vl64
CNTH X0, VL64
cnth x0, vl64, mul #1
cnth x0, vl128
CNTH X0, VL128
cnth x0, vl128, mul #1
cnth x0, vl256
CNTH X0, VL256
cnth x0, vl256, mul #1
cnth x0, #14
CNTH X0, #14
cnth x0, #14, mul #1
cnth x0, #15
CNTH X0, #15
cnth x0, #15, mul #1
cnth x0, #16
CNTH X0, #16
cnth x0, #16, mul #1
cnth x0, #17
CNTH X0, #17
cnth x0, #17, mul #1
cnth x0, #18
CNTH X0, #18
cnth x0, #18, mul #1
cnth x0, #19
CNTH X0, #19
cnth x0, #19, mul #1
cnth x0, #20
CNTH X0, #20
cnth x0, #20, mul #1
cnth x0, #21
CNTH X0, #21
cnth x0, #21, mul #1
cnth x0, #22
CNTH X0, #22
cnth x0, #22, mul #1
cnth x0, #23
CNTH X0, #23
cnth x0, #23, mul #1
cnth x0, #24
CNTH X0, #24
cnth x0, #24, mul #1
cnth x0, #25
CNTH X0, #25
cnth x0, #25, mul #1
cnth x0, #26
CNTH X0, #26
cnth x0, #26, mul #1
cnth x0, #27
CNTH X0, #27
cnth x0, #27, mul #1
cnth x0, #28
CNTH X0, #28
cnth x0, #28, mul #1
cnth x0, mul4
CNTH X0, MUL4
cnth x0, mul4, mul #1
cnth x0, mul3
CNTH X0, MUL3
cnth x0, mul3, mul #1
cnth x0
CNTH X0
cnth x0, all
cnth x0, all, mul #1
cnth x0, pow2, mul #8
CNTH X0, POW2, MUL #8
cnth x0, pow2, mul #9
CNTH X0, POW2, MUL #9
cnth x0, pow2, mul #10
CNTH X0, POW2, MUL #10
cnth x0, pow2, mul #16
CNTH X0, POW2, MUL #16
cntp x0, p0, p0.b
CNTP X0, P0, P0.B
cntp x1, p0, p0.b
CNTP X1, P0, P0.B
cntp xzr, p0, p0.b
CNTP XZR, P0, P0.B
cntp x0, p2, p0.b
CNTP X0, P2, P0.B
cntp x0, p15, p0.b
CNTP X0, P15, P0.B
cntp x0, p0, p3.b
CNTP X0, P0, P3.B
cntp x0, p0, p15.b
CNTP X0, P0, P15.B
cntp x0, p0, p0.h
CNTP X0, P0, P0.H
cntp x1, p0, p0.h
CNTP X1, P0, P0.H
cntp xzr, p0, p0.h
CNTP XZR, P0, P0.H
cntp x0, p2, p0.h
CNTP X0, P2, P0.H
cntp x0, p15, p0.h
CNTP X0, P15, P0.H
cntp x0, p0, p3.h
CNTP X0, P0, P3.H
cntp x0, p0, p15.h
CNTP X0, P0, P15.H
cntp x0, p0, p0.s
CNTP X0, P0, P0.S
cntp x1, p0, p0.s
CNTP X1, P0, P0.S
cntp xzr, p0, p0.s
CNTP XZR, P0, P0.S
cntp x0, p2, p0.s
CNTP X0, P2, P0.S
cntp x0, p15, p0.s
CNTP X0, P15, P0.S
cntp x0, p0, p3.s
CNTP X0, P0, P3.S
cntp x0, p0, p15.s
CNTP X0, P0, P15.S
cntp x0, p0, p0.d
CNTP X0, P0, P0.D
cntp x1, p0, p0.d
CNTP X1, P0, P0.D
cntp xzr, p0, p0.d
CNTP XZR, P0, P0.D
cntp x0, p2, p0.d
CNTP X0, P2, P0.D
cntp x0, p15, p0.d
CNTP X0, P15, P0.D
cntp x0, p0, p3.d
CNTP X0, P0, P3.D
cntp x0, p0, p15.d
CNTP X0, P0, P15.D
cntw x0, pow2
CNTW X0, POW2
cntw x0, pow2, mul #1
cntw x1, pow2
CNTW X1, POW2
cntw x1, pow2, mul #1
cntw xzr, pow2
CNTW XZR, POW2
cntw xzr, pow2, mul #1
cntw x0, vl1
CNTW X0, VL1
cntw x0, vl1, mul #1
cntw x0, vl2
CNTW X0, VL2
cntw x0, vl2, mul #1
cntw x0, vl3
CNTW X0, VL3
cntw x0, vl3, mul #1
cntw x0, vl4
CNTW X0, VL4
cntw x0, vl4, mul #1
cntw x0, vl5
CNTW X0, VL5
cntw x0, vl5, mul #1
cntw x0, vl6
CNTW X0, VL6
cntw x0, vl6, mul #1
cntw x0, vl7
CNTW X0, VL7
cntw x0, vl7, mul #1
cntw x0, vl8
CNTW X0, VL8
cntw x0, vl8, mul #1
cntw x0, vl16
CNTW X0, VL16
cntw x0, vl16, mul #1
cntw x0, vl32
CNTW X0, VL32
cntw x0, vl32, mul #1
cntw x0, vl64
CNTW X0, VL64
cntw x0, vl64, mul #1
cntw x0, vl128
CNTW X0, VL128
cntw x0, vl128, mul #1
cntw x0, vl256
CNTW X0, VL256
cntw x0, vl256, mul #1
cntw x0, #14
CNTW X0, #14
cntw x0, #14, mul #1
cntw x0, #15
CNTW X0, #15
cntw x0, #15, mul #1
cntw x0, #16
CNTW X0, #16
cntw x0, #16, mul #1
cntw x0, #17
CNTW X0, #17
cntw x0, #17, mul #1
cntw x0, #18
CNTW X0, #18
cntw x0, #18, mul #1
cntw x0, #19
CNTW X0, #19
cntw x0, #19, mul #1
cntw x0, #20
CNTW X0, #20
cntw x0, #20, mul #1
cntw x0, #21
CNTW X0, #21
cntw x0, #21, mul #1
cntw x0, #22
CNTW X0, #22
cntw x0, #22, mul #1
cntw x0, #23
CNTW X0, #23
cntw x0, #23, mul #1
cntw x0, #24
CNTW X0, #24
cntw x0, #24, mul #1
cntw x0, #25
CNTW X0, #25
cntw x0, #25, mul #1
cntw x0, #26
CNTW X0, #26
cntw x0, #26, mul #1
cntw x0, #27
CNTW X0, #27
cntw x0, #27, mul #1
cntw x0, #28
CNTW X0, #28
cntw x0, #28, mul #1
cntw x0, mul4
CNTW X0, MUL4
cntw x0, mul4, mul #1
cntw x0, mul3
CNTW X0, MUL3
cntw x0, mul3, mul #1
cntw x0
CNTW X0
cntw x0, all
cntw x0, all, mul #1
cntw x0, pow2, mul #8
CNTW X0, POW2, MUL #8
cntw x0, pow2, mul #9
CNTW X0, POW2, MUL #9
cntw x0, pow2, mul #10
CNTW X0, POW2, MUL #10
cntw x0, pow2, mul #16
CNTW X0, POW2, MUL #16
compact z0.s, p0, z0.s
COMPACT Z0.S, P0, Z0.S
compact z1.s, p0, z0.s
COMPACT Z1.S, P0, Z0.S
compact z31.s, p0, z0.s
COMPACT Z31.S, P0, Z0.S
compact z0.s, p2, z0.s
COMPACT Z0.S, P2, Z0.S
compact z0.s, p7, z0.s
COMPACT Z0.S, P7, Z0.S
compact z0.s, p0, z3.s
COMPACT Z0.S, P0, Z3.S
compact z0.s, p0, z31.s
COMPACT Z0.S, P0, Z31.S
compact z0.d, p0, z0.d
COMPACT Z0.D, P0, Z0.D
compact z1.d, p0, z0.d
COMPACT Z1.D, P0, Z0.D
compact z31.d, p0, z0.d
COMPACT Z31.D, P0, Z0.D
compact z0.d, p2, z0.d
COMPACT Z0.D, P2, Z0.D
compact z0.d, p7, z0.d
COMPACT Z0.D, P7, Z0.D
compact z0.d, p0, z3.d
COMPACT Z0.D, P0, Z3.D
compact z0.d, p0, z31.d
COMPACT Z0.D, P0, Z31.D
cpy z0.b, p0/m, b0
CPY Z0.B, P0/M, B0
cpy z1.b, p0/m, b0
CPY Z1.B, P0/M, B0
cpy z31.b, p0/m, b0
CPY Z31.B, P0/M, B0
cpy z0.b, p2/m, b0
CPY Z0.B, P2/M, B0
cpy z0.b, p7/m, b0
CPY Z0.B, P7/M, B0
cpy z0.b, p0/m, b3
CPY Z0.B, P0/M, B3
cpy z0.b, p0/m, b31
CPY Z0.B, P0/M, B31
cpy z0.h, p0/m, h0
CPY Z0.H, P0/M, H0
cpy z1.h, p0/m, h0
CPY Z1.H, P0/M, H0
cpy z31.h, p0/m, h0
CPY Z31.H, P0/M, H0
cpy z0.h, p2/m, h0
CPY Z0.H, P2/M, H0
cpy z0.h, p7/m, h0
CPY Z0.H, P7/M, H0
cpy z0.h, p0/m, h3
CPY Z0.H, P0/M, H3
cpy z0.h, p0/m, h31
CPY Z0.H, P0/M, H31
cpy z0.s, p0/m, s0
CPY Z0.S, P0/M, S0
cpy z1.s, p0/m, s0
CPY Z1.S, P0/M, S0
cpy z31.s, p0/m, s0
CPY Z31.S, P0/M, S0
cpy z0.s, p2/m, s0
CPY Z0.S, P2/M, S0
cpy z0.s, p7/m, s0
CPY Z0.S, P7/M, S0
cpy z0.s, p0/m, s3
CPY Z0.S, P0/M, S3
cpy z0.s, p0/m, s31
CPY Z0.S, P0/M, S31
cpy z0.d, p0/m, d0
CPY Z0.D, P0/M, D0
cpy z1.d, p0/m, d0
CPY Z1.D, P0/M, D0
cpy z31.d, p0/m, d0
CPY Z31.D, P0/M, D0
cpy z0.d, p2/m, d0
CPY Z0.D, P2/M, D0
cpy z0.d, p7/m, d0
CPY Z0.D, P7/M, D0
cpy z0.d, p0/m, d3
CPY Z0.D, P0/M, D3
cpy z0.d, p0/m, d31
CPY Z0.D, P0/M, D31
cpy z0.b, p0/m, w0
CPY Z0.B, P0/M, W0
cpy z1.b, p0/m, w0
CPY Z1.B, P0/M, W0
cpy z31.b, p0/m, w0
CPY Z31.B, P0/M, W0
cpy z0.b, p2/m, w0
CPY Z0.B, P2/M, W0
cpy z0.b, p7/m, w0
CPY Z0.B, P7/M, W0
cpy z0.b, p0/m, w3
CPY Z0.B, P0/M, W3
cpy z0.b, p0/m, wsp
CPY Z0.B, P0/M, WSP
cpy z0.h, p0/m, w0
CPY Z0.H, P0/M, W0
cpy z1.h, p0/m, w0
CPY Z1.H, P0/M, W0
cpy z31.h, p0/m, w0
CPY Z31.H, P0/M, W0
cpy z0.h, p2/m, w0
CPY Z0.H, P2/M, W0
cpy z0.h, p7/m, w0
CPY Z0.H, P7/M, W0
cpy z0.h, p0/m, w3
CPY Z0.H, P0/M, W3
cpy z0.h, p0/m, wsp
CPY Z0.H, P0/M, WSP
cpy z0.s, p0/m, w0
CPY Z0.S, P0/M, W0
cpy z1.s, p0/m, w0
CPY Z1.S, P0/M, W0
cpy z31.s, p0/m, w0
CPY Z31.S, P0/M, W0
cpy z0.s, p2/m, w0
CPY Z0.S, P2/M, W0
cpy z0.s, p7/m, w0
CPY Z0.S, P7/M, W0
cpy z0.s, p0/m, w3
CPY Z0.S, P0/M, W3
cpy z0.s, p0/m, wsp
CPY Z0.S, P0/M, WSP
cpy z0.d, p0/m, x0
CPY Z0.D, P0/M, X0
cpy z1.d, p0/m, x0
CPY Z1.D, P0/M, X0
cpy z31.d, p0/m, x0
CPY Z31.D, P0/M, X0
cpy z0.d, p2/m, x0
CPY Z0.D, P2/M, X0
cpy z0.d, p7/m, x0
CPY Z0.D, P7/M, X0
cpy z0.d, p0/m, x3
CPY Z0.D, P0/M, X3
cpy z0.d, p0/m, sp
CPY Z0.D, P0/M, SP
cpy z0.b, p0/z, #0
CPY Z0.B, P0/Z, #0
cpy z0.b, p0/z, #0, lsl #0
cpy z1.b, p0/z, #0
CPY Z1.B, P0/Z, #0
cpy z1.b, p0/z, #0, lsl #0
cpy z31.b, p0/z, #0
CPY Z31.B, P0/Z, #0
cpy z31.b, p0/z, #0, lsl #0
cpy z0.b, p2/z, #0
CPY Z0.B, P2/Z, #0
cpy z0.b, p2/z, #0, lsl #0
cpy z0.b, p15/z, #0
CPY Z0.B, P15/Z, #0
cpy z0.b, p15/z, #0, lsl #0
cpy z0.b, p0/z, #127
CPY Z0.B, P0/Z, #127
cpy z0.b, p0/z, #127, lsl #0
cpy z0.b, p0/z, #-128
CPY Z0.B, P0/Z, #-128
cpy z0.b, p0/z, #-128, lsl #0
cpy z0.b, p0/z, #-127
CPY Z0.B, P0/Z, #-127
cpy z0.b, p0/z, #-127, lsl #0
cpy z0.b, p0/z, #-1
CPY Z0.B, P0/Z, #-1
cpy z0.b, p0/z, #-1, lsl #0
cpy z0.b, p0/m, #0
CPY Z0.B, P0/M, #0
cpy z0.b, p0/m, #0, lsl #0
cpy z1.b, p0/m, #0
CPY Z1.B, P0/M, #0
cpy z1.b, p0/m, #0, lsl #0
cpy z31.b, p0/m, #0
CPY Z31.B, P0/M, #0
cpy z31.b, p0/m, #0, lsl #0
cpy z0.b, p2/m, #0
CPY Z0.B, P2/M, #0
cpy z0.b, p2/m, #0, lsl #0
cpy z0.b, p15/m, #0
CPY Z0.B, P15/M, #0
cpy z0.b, p15/m, #0, lsl #0
cpy z0.b, p0/m, #127
CPY Z0.B, P0/M, #127
cpy z0.b, p0/m, #127, lsl #0
cpy z0.b, p0/m, #-128
CPY Z0.B, P0/M, #-128
cpy z0.b, p0/m, #-128, lsl #0
cpy z0.b, p0/m, #-127
CPY Z0.B, P0/M, #-127
cpy z0.b, p0/m, #-127, lsl #0
cpy z0.b, p0/m, #-1
CPY Z0.B, P0/M, #-1
cpy z0.b, p0/m, #-1, lsl #0
cpy z0.h, p0/z, #0
CPY Z0.H, P0/Z, #0
cpy z0.h, p0/z, #0, lsl #0
cpy z1.h, p0/z, #0
CPY Z1.H, P0/Z, #0
cpy z1.h, p0/z, #0, lsl #0
cpy z31.h, p0/z, #0
CPY Z31.H, P0/Z, #0
cpy z31.h, p0/z, #0, lsl #0
cpy z0.h, p2/z, #0
CPY Z0.H, P2/Z, #0
cpy z0.h, p2/z, #0, lsl #0
cpy z0.h, p15/z, #0
CPY Z0.H, P15/Z, #0
cpy z0.h, p15/z, #0, lsl #0
cpy z0.h, p0/z, #127
CPY Z0.H, P0/Z, #127
cpy z0.h, p0/z, #127, lsl #0
cpy z0.h, p0/z, #-128
CPY Z0.H, P0/Z, #-128
cpy z0.h, p0/z, #-128, lsl #0
cpy z0.h, p0/z, #-127
CPY Z0.H, P0/Z, #-127
cpy z0.h, p0/z, #-127, lsl #0
cpy z0.h, p0/z, #-1
CPY Z0.H, P0/Z, #-1
cpy z0.h, p0/z, #-1, lsl #0
cpy z0.h, p0/z, #0, lsl #8
CPY Z0.H, P0/Z, #0, LSL #8
cpy z0.h, p0/z, #32512
CPY Z0.H, P0/Z, #32512
cpy z0.h, p0/z, #32512, lsl #0
cpy z0.h, p0/z, #127, lsl #8
cpy z0.h, p0/z, #-32768
CPY Z0.H, P0/Z, #-32768
cpy z0.h, p0/z, #-32768, lsl #0
cpy z0.h, p0/z, #-128, lsl #8
cpy z0.h, p0/z, #-32512
CPY Z0.H, P0/Z, #-32512
cpy z0.h, p0/z, #-32512, lsl #0
cpy z0.h, p0/z, #-127, lsl #8
cpy z0.h, p0/z, #-256
CPY Z0.H, P0/Z, #-256
cpy z0.h, p0/z, #-256, lsl #0
cpy z0.h, p0/z, #-1, lsl #8
cpy z0.h, p0/m, #0
CPY Z0.H, P0/M, #0
cpy z0.h, p0/m, #0, lsl #0
cpy z1.h, p0/m, #0
CPY Z1.H, P0/M, #0
cpy z1.h, p0/m, #0, lsl #0
cpy z31.h, p0/m, #0
CPY Z31.H, P0/M, #0
cpy z31.h, p0/m, #0, lsl #0
cpy z0.h, p2/m, #0
CPY Z0.H, P2/M, #0
cpy z0.h, p2/m, #0, lsl #0
cpy z0.h, p15/m, #0
CPY Z0.H, P15/M, #0
cpy z0.h, p15/m, #0, lsl #0
cpy z0.h, p0/m, #127
CPY Z0.H, P0/M, #127
cpy z0.h, p0/m, #127, lsl #0
cpy z0.h, p0/m, #-128
CPY Z0.H, P0/M, #-128
cpy z0.h, p0/m, #-128, lsl #0
cpy z0.h, p0/m, #-127
CPY Z0.H, P0/M, #-127
cpy z0.h, p0/m, #-127, lsl #0
cpy z0.h, p0/m, #-1
CPY Z0.H, P0/M, #-1
cpy z0.h, p0/m, #-1, lsl #0
cpy z0.h, p0/m, #0, lsl #8
CPY Z0.H, P0/M, #0, LSL #8
cpy z0.h, p0/m, #32512
CPY Z0.H, P0/M, #32512
cpy z0.h, p0/m, #32512, lsl #0
cpy z0.h, p0/m, #127, lsl #8
cpy z0.h, p0/m, #-32768
CPY Z0.H, P0/M, #-32768
cpy z0.h, p0/m, #-32768, lsl #0
cpy z0.h, p0/m, #-128, lsl #8
cpy z0.h, p0/m, #-32512
CPY Z0.H, P0/M, #-32512
cpy z0.h, p0/m, #-32512, lsl #0
cpy z0.h, p0/m, #-127, lsl #8
cpy z0.h, p0/m, #-256
CPY Z0.H, P0/M, #-256
cpy z0.h, p0/m, #-256, lsl #0
cpy z0.h, p0/m, #-1, lsl #8
cpy z0.s, p0/z, #0
CPY Z0.S, P0/Z, #0
cpy z0.s, p0/z, #0, lsl #0
cpy z1.s, p0/z, #0
CPY Z1.S, P0/Z, #0
cpy z1.s, p0/z, #0, lsl #0
cpy z31.s, p0/z, #0
CPY Z31.S, P0/Z, #0
cpy z31.s, p0/z, #0, lsl #0
cpy z0.s, p2/z, #0
CPY Z0.S, P2/Z, #0
cpy z0.s, p2/z, #0, lsl #0
cpy z0.s, p15/z, #0
CPY Z0.S, P15/Z, #0
cpy z0.s, p15/z, #0, lsl #0
cpy z0.s, p0/z, #127
CPY Z0.S, P0/Z, #127
cpy z0.s, p0/z, #127, lsl #0
cpy z0.s, p0/z, #-128
CPY Z0.S, P0/Z, #-128
cpy z0.s, p0/z, #-128, lsl #0
cpy z0.s, p0/z, #-127
CPY Z0.S, P0/Z, #-127
cpy z0.s, p0/z, #-127, lsl #0
cpy z0.s, p0/z, #-1
CPY Z0.S, P0/Z, #-1
cpy z0.s, p0/z, #-1, lsl #0
cpy z0.s, p0/z, #0, lsl #8
CPY Z0.S, P0/Z, #0, LSL #8
cpy z0.s, p0/z, #32512
CPY Z0.S, P0/Z, #32512
cpy z0.s, p0/z, #32512, lsl #0
cpy z0.s, p0/z, #127, lsl #8
cpy z0.s, p0/z, #-32768
CPY Z0.S, P0/Z, #-32768
cpy z0.s, p0/z, #-32768, lsl #0
cpy z0.s, p0/z, #-128, lsl #8
cpy z0.s, p0/z, #-32512
CPY Z0.S, P0/Z, #-32512
cpy z0.s, p0/z, #-32512, lsl #0
cpy z0.s, p0/z, #-127, lsl #8
cpy z0.s, p0/z, #-256
CPY Z0.S, P0/Z, #-256
cpy z0.s, p0/z, #-256, lsl #0
cpy z0.s, p0/z, #-1, lsl #8
cpy z0.s, p0/m, #0
CPY Z0.S, P0/M, #0
cpy z0.s, p0/m, #0, lsl #0
cpy z1.s, p0/m, #0
CPY Z1.S, P0/M, #0
cpy z1.s, p0/m, #0, lsl #0
cpy z31.s, p0/m, #0
CPY Z31.S, P0/M, #0
cpy z31.s, p0/m, #0, lsl #0
cpy z0.s, p2/m, #0
CPY Z0.S, P2/M, #0
cpy z0.s, p2/m, #0, lsl #0
cpy z0.s, p15/m, #0
CPY Z0.S, P15/M, #0
cpy z0.s, p15/m, #0, lsl #0
cpy z0.s, p0/m, #127
CPY Z0.S, P0/M, #127
cpy z0.s, p0/m, #127, lsl #0
cpy z0.s, p0/m, #-128
CPY Z0.S, P0/M, #-128
cpy z0.s, p0/m, #-128, lsl #0
cpy z0.s, p0/m, #-127
CPY Z0.S, P0/M, #-127
cpy z0.s, p0/m, #-127, lsl #0
cpy z0.s, p0/m, #-1
CPY Z0.S, P0/M, #-1
cpy z0.s, p0/m, #-1, lsl #0
cpy z0.s, p0/m, #0, lsl #8
CPY Z0.S, P0/M, #0, LSL #8
cpy z0.s, p0/m, #32512
CPY Z0.S, P0/M, #32512
cpy z0.s, p0/m, #32512, lsl #0
cpy z0.s, p0/m, #127, lsl #8
cpy z0.s, p0/m, #-32768
CPY Z0.S, P0/M, #-32768
cpy z0.s, p0/m, #-32768, lsl #0
cpy z0.s, p0/m, #-128, lsl #8
cpy z0.s, p0/m, #-32512
CPY Z0.S, P0/M, #-32512
cpy z0.s, p0/m, #-32512, lsl #0
cpy z0.s, p0/m, #-127, lsl #8
cpy z0.s, p0/m, #-256
CPY Z0.S, P0/M, #-256
cpy z0.s, p0/m, #-256, lsl #0
cpy z0.s, p0/m, #-1, lsl #8
cpy z0.d, p0/z, #0
CPY Z0.D, P0/Z, #0
cpy z0.d, p0/z, #0, lsl #0
cpy z1.d, p0/z, #0
CPY Z1.D, P0/Z, #0
cpy z1.d, p0/z, #0, lsl #0
cpy z31.d, p0/z, #0
CPY Z31.D, P0/Z, #0
cpy z31.d, p0/z, #0, lsl #0
cpy z0.d, p2/z, #0
CPY Z0.D, P2/Z, #0
cpy z0.d, p2/z, #0, lsl #0
cpy z0.d, p15/z, #0
CPY Z0.D, P15/Z, #0
cpy z0.d, p15/z, #0, lsl #0
cpy z0.d, p0/z, #127
CPY Z0.D, P0/Z, #127
cpy z0.d, p0/z, #127, lsl #0
cpy z0.d, p0/z, #-128
CPY Z0.D, P0/Z, #-128
cpy z0.d, p0/z, #-128, lsl #0
cpy z0.d, p0/z, #-127
CPY Z0.D, P0/Z, #-127
cpy z0.d, p0/z, #-127, lsl #0
cpy z0.d, p0/z, #-1
CPY Z0.D, P0/Z, #-1
cpy z0.d, p0/z, #-1, lsl #0
cpy z0.d, p0/z, #0, lsl #8
CPY Z0.D, P0/Z, #0, LSL #8
cpy z0.d, p0/z, #32512
CPY Z0.D, P0/Z, #32512
cpy z0.d, p0/z, #32512, lsl #0
cpy z0.d, p0/z, #127, lsl #8
cpy z0.d, p0/z, #-32768
CPY Z0.D, P0/Z, #-32768
cpy z0.d, p0/z, #-32768, lsl #0
cpy z0.d, p0/z, #-128, lsl #8
cpy z0.d, p0/z, #-32512
CPY Z0.D, P0/Z, #-32512
cpy z0.d, p0/z, #-32512, lsl #0
cpy z0.d, p0/z, #-127, lsl #8
cpy z0.d, p0/z, #-256
CPY Z0.D, P0/Z, #-256
cpy z0.d, p0/z, #-256, lsl #0
cpy z0.d, p0/z, #-1, lsl #8
cpy z0.d, p0/m, #0
CPY Z0.D, P0/M, #0
cpy z0.d, p0/m, #0, lsl #0
cpy z1.d, p0/m, #0
CPY Z1.D, P0/M, #0
cpy z1.d, p0/m, #0, lsl #0
cpy z31.d, p0/m, #0
CPY Z31.D, P0/M, #0
cpy z31.d, p0/m, #0, lsl #0
cpy z0.d, p2/m, #0
CPY Z0.D, P2/M, #0
cpy z0.d, p2/m, #0, lsl #0
cpy z0.d, p15/m, #0
CPY Z0.D, P15/M, #0
cpy z0.d, p15/m, #0, lsl #0
cpy z0.d, p0/m, #127
CPY Z0.D, P0/M, #127
cpy z0.d, p0/m, #127, lsl #0
cpy z0.d, p0/m, #-128
CPY Z0.D, P0/M, #-128
cpy z0.d, p0/m, #-128, lsl #0
cpy z0.d, p0/m, #-127
CPY Z0.D, P0/M, #-127
cpy z0.d, p0/m, #-127, lsl #0
cpy z0.d, p0/m, #-1
CPY Z0.D, P0/M, #-1
cpy z0.d, p0/m, #-1, lsl #0
cpy z0.d, p0/m, #0, lsl #8
CPY Z0.D, P0/M, #0, LSL #8
cpy z0.d, p0/m, #32512
CPY Z0.D, P0/M, #32512
cpy z0.d, p0/m, #32512, lsl #0
cpy z0.d, p0/m, #127, lsl #8
cpy z0.d, p0/m, #-32768
CPY Z0.D, P0/M, #-32768
cpy z0.d, p0/m, #-32768, lsl #0
cpy z0.d, p0/m, #-128, lsl #8
cpy z0.d, p0/m, #-32512
CPY Z0.D, P0/M, #-32512
cpy z0.d, p0/m, #-32512, lsl #0
cpy z0.d, p0/m, #-127, lsl #8
cpy z0.d, p0/m, #-256
CPY Z0.D, P0/M, #-256
cpy z0.d, p0/m, #-256, lsl #0
cpy z0.d, p0/m, #-1, lsl #8
ctermeq w0, w0
CTERMEQ W0, W0
ctermeq w1, w0
CTERMEQ W1, W0
ctermeq wzr, w0
CTERMEQ WZR, W0
ctermeq w0, w2
CTERMEQ W0, W2
ctermeq w0, wzr
CTERMEQ W0, WZR
ctermeq x0, x0
CTERMEQ X0, X0
ctermeq x1, x0
CTERMEQ X1, X0
ctermeq xzr, x0
CTERMEQ XZR, X0
ctermeq x0, x2
CTERMEQ X0, X2
ctermeq x0, xzr
CTERMEQ X0, XZR
ctermne w0, w0
CTERMNE W0, W0
ctermne w1, w0
CTERMNE W1, W0
ctermne wzr, w0
CTERMNE WZR, W0
ctermne w0, w2
CTERMNE W0, W2
ctermne w0, wzr
CTERMNE W0, WZR
ctermne x0, x0
CTERMNE X0, X0
ctermne x1, x0
CTERMNE X1, X0
ctermne xzr, x0
CTERMNE XZR, X0
ctermne x0, x2
CTERMNE X0, X2
ctermne x0, xzr
CTERMNE X0, XZR
decb x0, pow2
DECB X0, POW2
decb x0, pow2, mul #1
decb x1, pow2
DECB X1, POW2
decb x1, pow2, mul #1
decb xzr, pow2
DECB XZR, POW2
decb xzr, pow2, mul #1
decb x0, vl1
DECB X0, VL1
decb x0, vl1, mul #1
decb x0, vl2
DECB X0, VL2
decb x0, vl2, mul #1
decb x0, vl3
DECB X0, VL3
decb x0, vl3, mul #1
decb x0, vl4
DECB X0, VL4
decb x0, vl4, mul #1
decb x0, vl5
DECB X0, VL5
decb x0, vl5, mul #1
decb x0, vl6
DECB X0, VL6
decb x0, vl6, mul #1
decb x0, vl7
DECB X0, VL7
decb x0, vl7, mul #1
decb x0, vl8
DECB X0, VL8
decb x0, vl8, mul #1
decb x0, vl16
DECB X0, VL16
decb x0, vl16, mul #1
decb x0, vl32
DECB X0, VL32
decb x0, vl32, mul #1
decb x0, vl64
DECB X0, VL64
decb x0, vl64, mul #1
decb x0, vl128
DECB X0, VL128
decb x0, vl128, mul #1
decb x0, vl256
DECB X0, VL256
decb x0, vl256, mul #1
decb x0, #14
DECB X0, #14
decb x0, #14, mul #1
decb x0, #15
DECB X0, #15
decb x0, #15, mul #1
decb x0, #16
DECB X0, #16
decb x0, #16, mul #1
decb x0, #17
DECB X0, #17
decb x0, #17, mul #1
decb x0, #18
DECB X0, #18
decb x0, #18, mul #1
decb x0, #19
DECB X0, #19
decb x0, #19, mul #1
decb x0, #20
DECB X0, #20
decb x0, #20, mul #1
decb x0, #21
DECB X0, #21
decb x0, #21, mul #1
decb x0, #22
DECB X0, #22
decb x0, #22, mul #1
decb x0, #23
DECB X0, #23
decb x0, #23, mul #1
decb x0, #24
DECB X0, #24
decb x0, #24, mul #1
decb x0, #25
DECB X0, #25
decb x0, #25, mul #1
decb x0, #26
DECB X0, #26
decb x0, #26, mul #1
decb x0, #27
DECB X0, #27
decb x0, #27, mul #1
decb x0, #28
DECB X0, #28
decb x0, #28, mul #1
decb x0, mul4
DECB X0, MUL4
decb x0, mul4, mul #1
decb x0, mul3
DECB X0, MUL3
decb x0, mul3, mul #1
decb x0
DECB X0
decb x0, all
decb x0, all, mul #1
decb x0, pow2, mul #8
DECB X0, POW2, MUL #8
decb x0, pow2, mul #9
DECB X0, POW2, MUL #9
decb x0, pow2, mul #10
DECB X0, POW2, MUL #10
decb x0, pow2, mul #16
DECB X0, POW2, MUL #16
decd z0.d, pow2
DECD Z0.D, POW2
decd z0.d, pow2, mul #1
decd z1.d, pow2
DECD Z1.D, POW2
decd z1.d, pow2, mul #1
decd z31.d, pow2
DECD Z31.D, POW2
decd z31.d, pow2, mul #1
decd z0.d, vl1
DECD Z0.D, VL1
decd z0.d, vl1, mul #1
decd z0.d, vl2
DECD Z0.D, VL2
decd z0.d, vl2, mul #1
decd z0.d, vl3
DECD Z0.D, VL3
decd z0.d, vl3, mul #1
decd z0.d, vl4
DECD Z0.D, VL4
decd z0.d, vl4, mul #1
decd z0.d, vl5
DECD Z0.D, VL5
decd z0.d, vl5, mul #1
decd z0.d, vl6
DECD Z0.D, VL6
decd z0.d, vl6, mul #1
decd z0.d, vl7
DECD Z0.D, VL7
decd z0.d, vl7, mul #1
decd z0.d, vl8
DECD Z0.D, VL8
decd z0.d, vl8, mul #1
decd z0.d, vl16
DECD Z0.D, VL16
decd z0.d, vl16, mul #1
decd z0.d, vl32
DECD Z0.D, VL32
decd z0.d, vl32, mul #1
decd z0.d, vl64
DECD Z0.D, VL64
decd z0.d, vl64, mul #1
decd z0.d, vl128
DECD Z0.D, VL128
decd z0.d, vl128, mul #1
decd z0.d, vl256
DECD Z0.D, VL256
decd z0.d, vl256, mul #1
decd z0.d, #14
DECD Z0.D, #14
decd z0.d, #14, mul #1
decd z0.d, #15
DECD Z0.D, #15
decd z0.d, #15, mul #1
decd z0.d, #16
DECD Z0.D, #16
decd z0.d, #16, mul #1
decd z0.d, #17
DECD Z0.D, #17
decd z0.d, #17, mul #1
decd z0.d, #18
DECD Z0.D, #18
decd z0.d, #18, mul #1
decd z0.d, #19
DECD Z0.D, #19
decd z0.d, #19, mul #1
decd z0.d, #20
DECD Z0.D, #20
decd z0.d, #20, mul #1
decd z0.d, #21
DECD Z0.D, #21
decd z0.d, #21, mul #1
decd z0.d, #22
DECD Z0.D, #22
decd z0.d, #22, mul #1
decd z0.d, #23
DECD Z0.D, #23
decd z0.d, #23, mul #1
decd z0.d, #24
DECD Z0.D, #24
decd z0.d, #24, mul #1
decd z0.d, #25
DECD Z0.D, #25
decd z0.d, #25, mul #1
decd z0.d, #26
DECD Z0.D, #26
decd z0.d, #26, mul #1
decd z0.d, #27
DECD Z0.D, #27
decd z0.d, #27, mul #1
decd z0.d, #28
DECD Z0.D, #28
decd z0.d, #28, mul #1
decd z0.d, mul4
DECD Z0.D, MUL4
decd z0.d, mul4, mul #1
decd z0.d, mul3
DECD Z0.D, MUL3
decd z0.d, mul3, mul #1
decd z0.d
DECD Z0.D
decd z0.d, all
decd z0.d, all, mul #1
decd z0.d, pow2, mul #8
DECD Z0.D, POW2, MUL #8
decd z0.d, pow2, mul #9
DECD Z0.D, POW2, MUL #9
decd z0.d, pow2, mul #10
DECD Z0.D, POW2, MUL #10
decd z0.d, pow2, mul #16
DECD Z0.D, POW2, MUL #16
decd x0, pow2
DECD X0, POW2
decd x0, pow2, mul #1
decd x1, pow2
DECD X1, POW2
decd x1, pow2, mul #1
decd xzr, pow2
DECD XZR, POW2
decd xzr, pow2, mul #1
decd x0, vl1
DECD X0, VL1
decd x0, vl1, mul #1
decd x0, vl2
DECD X0, VL2
decd x0, vl2, mul #1
decd x0, vl3
DECD X0, VL3
decd x0, vl3, mul #1
decd x0, vl4
DECD X0, VL4
decd x0, vl4, mul #1
decd x0, vl5
DECD X0, VL5
decd x0, vl5, mul #1
decd x0, vl6
DECD X0, VL6
decd x0, vl6, mul #1
decd x0, vl7
DECD X0, VL7
decd x0, vl7, mul #1
decd x0, vl8
DECD X0, VL8
decd x0, vl8, mul #1
decd x0, vl16
DECD X0, VL16
decd x0, vl16, mul #1
decd x0, vl32
DECD X0, VL32
decd x0, vl32, mul #1
decd x0, vl64
DECD X0, VL64
decd x0, vl64, mul #1
decd x0, vl128
DECD X0, VL128
decd x0, vl128, mul #1
decd x0, vl256
DECD X0, VL256
decd x0, vl256, mul #1
decd x0, #14
DECD X0, #14
decd x0, #14, mul #1
decd x0, #15
DECD X0, #15
decd x0, #15, mul #1
decd x0, #16
DECD X0, #16
decd x0, #16, mul #1
decd x0, #17
DECD X0, #17
decd x0, #17, mul #1
decd x0, #18
DECD X0, #18
decd x0, #18, mul #1
decd x0, #19
DECD X0, #19
decd x0, #19, mul #1
decd x0, #20
DECD X0, #20
decd x0, #20, mul #1
decd x0, #21
DECD X0, #21
decd x0, #21, mul #1
decd x0, #22
DECD X0, #22
decd x0, #22, mul #1
decd x0, #23
DECD X0, #23
decd x0, #23, mul #1
decd x0, #24
DECD X0, #24
decd x0, #24, mul #1
decd x0, #25
DECD X0, #25
decd x0, #25, mul #1
decd x0, #26
DECD X0, #26
decd x0, #26, mul #1
decd x0, #27
DECD X0, #27
decd x0, #27, mul #1
decd x0, #28
DECD X0, #28
decd x0, #28, mul #1
decd x0, mul4
DECD X0, MUL4
decd x0, mul4, mul #1
decd x0, mul3
DECD X0, MUL3
decd x0, mul3, mul #1
decd x0
DECD X0
decd x0, all
decd x0, all, mul #1
decd x0, pow2, mul #8
DECD X0, POW2, MUL #8
decd x0, pow2, mul #9
DECD X0, POW2, MUL #9
decd x0, pow2, mul #10
DECD X0, POW2, MUL #10
decd x0, pow2, mul #16
DECD X0, POW2, MUL #16
dech z0.h, pow2
DECH Z0.H, POW2
dech z0.h, pow2, mul #1
dech z1.h, pow2
DECH Z1.H, POW2
dech z1.h, pow2, mul #1
dech z31.h, pow2
DECH Z31.H, POW2
dech z31.h, pow2, mul #1
dech z0.h, vl1
DECH Z0.H, VL1
dech z0.h, vl1, mul #1
dech z0.h, vl2
DECH Z0.H, VL2
dech z0.h, vl2, mul #1
dech z0.h, vl3
DECH Z0.H, VL3
dech z0.h, vl3, mul #1
dech z0.h, vl4
DECH Z0.H, VL4
dech z0.h, vl4, mul #1
dech z0.h, vl5
DECH Z0.H, VL5
dech z0.h, vl5, mul #1
dech z0.h, vl6
DECH Z0.H, VL6
dech z0.h, vl6, mul #1
dech z0.h, vl7
DECH Z0.H, VL7
dech z0.h, vl7, mul #1
dech z0.h, vl8
DECH Z0.H, VL8
dech z0.h, vl8, mul #1
dech z0.h, vl16
DECH Z0.H, VL16
dech z0.h, vl16, mul #1
dech z0.h, vl32
DECH Z0.H, VL32
dech z0.h, vl32, mul #1
dech z0.h, vl64
DECH Z0.H, VL64
dech z0.h, vl64, mul #1
dech z0.h, vl128
DECH Z0.H, VL128
dech z0.h, vl128, mul #1
dech z0.h, vl256
DECH Z0.H, VL256
dech z0.h, vl256, mul #1
dech z0.h, #14
DECH Z0.H, #14
dech z0.h, #14, mul #1
dech z0.h, #15
DECH Z0.H, #15
dech z0.h, #15, mul #1
dech z0.h, #16
DECH Z0.H, #16
dech z0.h, #16, mul #1
dech z0.h, #17
DECH Z0.H, #17
dech z0.h, #17, mul #1
dech z0.h, #18
DECH Z0.H, #18
dech z0.h, #18, mul #1
dech z0.h, #19
DECH Z0.H, #19
dech z0.h, #19, mul #1
dech z0.h, #20
DECH Z0.H, #20
dech z0.h, #20, mul #1
dech z0.h, #21
DECH Z0.H, #21
dech z0.h, #21, mul #1
dech z0.h, #22
DECH Z0.H, #22
dech z0.h, #22, mul #1
dech z0.h, #23
DECH Z0.H, #23
dech z0.h, #23, mul #1
dech z0.h, #24
DECH Z0.H, #24
dech z0.h, #24, mul #1
dech z0.h, #25
DECH Z0.H, #25
dech z0.h, #25, mul #1
dech z0.h, #26
DECH Z0.H, #26
dech z0.h, #26, mul #1
dech z0.h, #27
DECH Z0.H, #27
dech z0.h, #27, mul #1
dech z0.h, #28
DECH Z0.H, #28
dech z0.h, #28, mul #1
dech z0.h, mul4
DECH Z0.H, MUL4
dech z0.h, mul4, mul #1
dech z0.h, mul3
DECH Z0.H, MUL3
dech z0.h, mul3, mul #1
dech z0.h
DECH Z0.H
dech z0.h, all
dech z0.h, all, mul #1
dech z0.h, pow2, mul #8
DECH Z0.H, POW2, MUL #8
dech z0.h, pow2, mul #9
DECH Z0.H, POW2, MUL #9
dech z0.h, pow2, mul #10
DECH Z0.H, POW2, MUL #10
dech z0.h, pow2, mul #16
DECH Z0.H, POW2, MUL #16
dech x0, pow2
DECH X0, POW2
dech x0, pow2, mul #1
dech x1, pow2
DECH X1, POW2
dech x1, pow2, mul #1
dech xzr, pow2
DECH XZR, POW2
dech xzr, pow2, mul #1
dech x0, vl1
DECH X0, VL1
dech x0, vl1, mul #1
dech x0, vl2
DECH X0, VL2
dech x0, vl2, mul #1
dech x0, vl3
DECH X0, VL3
dech x0, vl3, mul #1
dech x0, vl4
DECH X0, VL4
dech x0, vl4, mul #1
dech x0, vl5
DECH X0, VL5
dech x0, vl5, mul #1
dech x0, vl6
DECH X0, VL6
dech x0, vl6, mul #1
dech x0, vl7
DECH X0, VL7
dech x0, vl7, mul #1
dech x0, vl8
DECH X0, VL8
dech x0, vl8, mul #1
dech x0, vl16
DECH X0, VL16
dech x0, vl16, mul #1
dech x0, vl32
DECH X0, VL32
dech x0, vl32, mul #1
dech x0, vl64
DECH X0, VL64
dech x0, vl64, mul #1
dech x0, vl128
DECH X0, VL128
dech x0, vl128, mul #1
dech x0, vl256
DECH X0, VL256
dech x0, vl256, mul #1
dech x0, #14
DECH X0, #14
dech x0, #14, mul #1
dech x0, #15
DECH X0, #15
dech x0, #15, mul #1
dech x0, #16
DECH X0, #16
dech x0, #16, mul #1
dech x0, #17
DECH X0, #17
dech x0, #17, mul #1
dech x0, #18
DECH X0, #18
dech x0, #18, mul #1
dech x0, #19
DECH X0, #19
dech x0, #19, mul #1
dech x0, #20
DECH X0, #20
dech x0, #20, mul #1
dech x0, #21
DECH X0, #21
dech x0, #21, mul #1
dech x0, #22
DECH X0, #22
dech x0, #22, mul #1
dech x0, #23
DECH X0, #23
dech x0, #23, mul #1
dech x0, #24
DECH X0, #24
dech x0, #24, mul #1
dech x0, #25
DECH X0, #25
dech x0, #25, mul #1
dech x0, #26
DECH X0, #26
dech x0, #26, mul #1
dech x0, #27
DECH X0, #27
dech x0, #27, mul #1
dech x0, #28
DECH X0, #28
dech x0, #28, mul #1
dech x0, mul4
DECH X0, MUL4
dech x0, mul4, mul #1
dech x0, mul3
DECH X0, MUL3
dech x0, mul3, mul #1
dech x0
DECH X0
dech x0, all
dech x0, all, mul #1
dech x0, pow2, mul #8
DECH X0, POW2, MUL #8
dech x0, pow2, mul #9
DECH X0, POW2, MUL #9
dech x0, pow2, mul #10
DECH X0, POW2, MUL #10
dech x0, pow2, mul #16
DECH X0, POW2, MUL #16
decp z0.h, p0
DECP Z0.H, P0
decp z1.h, p0
DECP Z1.H, P0
decp z31.h, p0
DECP Z31.H, P0
decp z0.h, p2
DECP Z0.H, P2
decp z0.h, p15
DECP Z0.H, P15
decp z0.s, p0
DECP Z0.S, P0
decp z1.s, p0
DECP Z1.S, P0
decp z31.s, p0
DECP Z31.S, P0
decp z0.s, p2
DECP Z0.S, P2
decp z0.s, p15
DECP Z0.S, P15
decp z0.d, p0
DECP Z0.D, P0
decp z1.d, p0
DECP Z1.D, P0
decp z31.d, p0
DECP Z31.D, P0
decp z0.d, p2
DECP Z0.D, P2
decp z0.d, p15
DECP Z0.D, P15
decp x0, p0.b
DECP X0, P0.B
decp x1, p0.b
DECP X1, P0.B
decp xzr, p0.b
DECP XZR, P0.B
decp x0, p2.b
DECP X0, P2.B
decp x0, p15.b
DECP X0, P15.B
decp x0, p0.h
DECP X0, P0.H
decp x1, p0.h
DECP X1, P0.H
decp xzr, p0.h
DECP XZR, P0.H
decp x0, p2.h
DECP X0, P2.H
decp x0, p15.h
DECP X0, P15.H
decp x0, p0.s
DECP X0, P0.S
decp x1, p0.s
DECP X1, P0.S
decp xzr, p0.s
DECP XZR, P0.S
decp x0, p2.s
DECP X0, P2.S
decp x0, p15.s
DECP X0, P15.S
decp x0, p0.d
DECP X0, P0.D
decp x1, p0.d
DECP X1, P0.D
decp xzr, p0.d
DECP XZR, P0.D
decp x0, p2.d
DECP X0, P2.D
decp x0, p15.d
DECP X0, P15.D
decw z0.s, pow2
DECW Z0.S, POW2
decw z0.s, pow2, mul #1
decw z1.s, pow2
DECW Z1.S, POW2
decw z1.s, pow2, mul #1
decw z31.s, pow2
DECW Z31.S, POW2
decw z31.s, pow2, mul #1
decw z0.s, vl1
DECW Z0.S, VL1
decw z0.s, vl1, mul #1
decw z0.s, vl2
DECW Z0.S, VL2
decw z0.s, vl2, mul #1
decw z0.s, vl3
DECW Z0.S, VL3
decw z0.s, vl3, mul #1
decw z0.s, vl4
DECW Z0.S, VL4
decw z0.s, vl4, mul #1
decw z0.s, vl5
DECW Z0.S, VL5
decw z0.s, vl5, mul #1
decw z0.s, vl6
DECW Z0.S, VL6
decw z0.s, vl6, mul #1
decw z0.s, vl7
DECW Z0.S, VL7
decw z0.s, vl7, mul #1
decw z0.s, vl8
DECW Z0.S, VL8
decw z0.s, vl8, mul #1
decw z0.s, vl16
DECW Z0.S, VL16
decw z0.s, vl16, mul #1
decw z0.s, vl32
DECW Z0.S, VL32
decw z0.s, vl32, mul #1
decw z0.s, vl64
DECW Z0.S, VL64
decw z0.s, vl64, mul #1
decw z0.s, vl128
DECW Z0.S, VL128
decw z0.s, vl128, mul #1
decw z0.s, vl256
DECW Z0.S, VL256
decw z0.s, vl256, mul #1
decw z0.s, #14
DECW Z0.S, #14
decw z0.s, #14, mul #1
decw z0.s, #15
DECW Z0.S, #15
decw z0.s, #15, mul #1
decw z0.s, #16
DECW Z0.S, #16
decw z0.s, #16, mul #1
decw z0.s, #17
DECW Z0.S, #17
decw z0.s, #17, mul #1
decw z0.s, #18
DECW Z0.S, #18
decw z0.s, #18, mul #1
decw z0.s, #19
DECW Z0.S, #19
decw z0.s, #19, mul #1
decw z0.s, #20
DECW Z0.S, #20
decw z0.s, #20, mul #1
decw z0.s, #21
DECW Z0.S, #21
decw z0.s, #21, mul #1
decw z0.s, #22
DECW Z0.S, #22
decw z0.s, #22, mul #1
decw z0.s, #23
DECW Z0.S, #23
decw z0.s, #23, mul #1
decw z0.s, #24
DECW Z0.S, #24
decw z0.s, #24, mul #1
decw z0.s, #25
DECW Z0.S, #25
decw z0.s, #25, mul #1
decw z0.s, #26
DECW Z0.S, #26
decw z0.s, #26, mul #1
decw z0.s, #27
DECW Z0.S, #27
decw z0.s, #27, mul #1
decw z0.s, #28
DECW Z0.S, #28
decw z0.s, #28, mul #1
decw z0.s, mul4
DECW Z0.S, MUL4
decw z0.s, mul4, mul #1
decw z0.s, mul3
DECW Z0.S, MUL3
decw z0.s, mul3, mul #1
decw z0.s
DECW Z0.S
decw z0.s, all
decw z0.s, all, mul #1
decw z0.s, pow2, mul #8
DECW Z0.S, POW2, MUL #8
decw z0.s, pow2, mul #9
DECW Z0.S, POW2, MUL #9
decw z0.s, pow2, mul #10
DECW Z0.S, POW2, MUL #10
decw z0.s, pow2, mul #16
DECW Z0.S, POW2, MUL #16
decw x0, pow2
DECW X0, POW2
decw x0, pow2, mul #1
decw x1, pow2
DECW X1, POW2
decw x1, pow2, mul #1
decw xzr, pow2
DECW XZR, POW2
decw xzr, pow2, mul #1
decw x0, vl1
DECW X0, VL1
decw x0, vl1, mul #1
decw x0, vl2
DECW X0, VL2
decw x0, vl2, mul #1
decw x0, vl3
DECW X0, VL3
decw x0, vl3, mul #1
decw x0, vl4
DECW X0, VL4
decw x0, vl4, mul #1
decw x0, vl5
DECW X0, VL5
decw x0, vl5, mul #1
decw x0, vl6
DECW X0, VL6
decw x0, vl6, mul #1
decw x0, vl7
DECW X0, VL7
decw x0, vl7, mul #1
decw x0, vl8
DECW X0, VL8
decw x0, vl8, mul #1
decw x0, vl16
DECW X0, VL16
decw x0, vl16, mul #1
decw x0, vl32
DECW X0, VL32
decw x0, vl32, mul #1
decw x0, vl64
DECW X0, VL64
decw x0, vl64, mul #1
decw x0, vl128
DECW X0, VL128
decw x0, vl128, mul #1
decw x0, vl256
DECW X0, VL256
decw x0, vl256, mul #1
decw x0, #14
DECW X0, #14
decw x0, #14, mul #1
decw x0, #15
DECW X0, #15
decw x0, #15, mul #1
decw x0, #16
DECW X0, #16
decw x0, #16, mul #1
decw x0, #17
DECW X0, #17
decw x0, #17, mul #1
decw x0, #18
DECW X0, #18
decw x0, #18, mul #1
decw x0, #19
DECW X0, #19
decw x0, #19, mul #1
decw x0, #20
DECW X0, #20
decw x0, #20, mul #1
decw x0, #21
DECW X0, #21
decw x0, #21, mul #1
decw x0, #22
DECW X0, #22
decw x0, #22, mul #1
decw x0, #23
DECW X0, #23
decw x0, #23, mul #1
decw x0, #24
DECW X0, #24
decw x0, #24, mul #1
decw x0, #25
DECW X0, #25
decw x0, #25, mul #1
decw x0, #26
DECW X0, #26
decw x0, #26, mul #1
decw x0, #27
DECW X0, #27
decw x0, #27, mul #1
decw x0, #28
DECW X0, #28
decw x0, #28, mul #1
decw x0, mul4
DECW X0, MUL4
decw x0, mul4, mul #1
decw x0, mul3
DECW X0, MUL3
decw x0, mul3, mul #1
decw x0
DECW X0
decw x0, all
decw x0, all, mul #1
decw x0, pow2, mul #8
DECW X0, POW2, MUL #8
decw x0, pow2, mul #9
DECW X0, POW2, MUL #9
decw x0, pow2, mul #10
DECW X0, POW2, MUL #10
decw x0, pow2, mul #16
DECW X0, POW2, MUL #16
dup z0.b, w0
DUP Z0.B, W0
dup z1.b, w0
DUP Z1.B, W0
dup z31.b, w0
DUP Z31.B, W0
dup z0.b, w2
DUP Z0.B, W2
dup z0.b, wsp
DUP Z0.B, WSP
dup z0.h, w0
DUP Z0.H, W0
dup z1.h, w0
DUP Z1.H, W0
dup z31.h, w0
DUP Z31.H, W0
dup z0.h, w2
DUP Z0.H, W2
dup z0.h, wsp
DUP Z0.H, WSP
dup z0.s, w0
DUP Z0.S, W0
dup z1.s, w0
DUP Z1.S, W0
dup z31.s, w0
DUP Z31.S, W0
dup z0.s, w2
DUP Z0.S, W2
dup z0.s, wsp
DUP Z0.S, WSP
dup z0.d, x0
DUP Z0.D, X0
dup z1.d, x0
DUP Z1.D, X0
dup z31.d, x0
DUP Z31.D, X0
dup z0.d, x2
DUP Z0.D, X2
dup z0.d, sp
DUP Z0.D, SP
dup z0.b, z0.b[0]
DUP Z0.B, Z0.B[0]
dup z1.b, z0.b[0]
DUP Z1.B, Z0.B[0]
dup z31.b, z0.b[0]
DUP Z31.B, Z0.B[0]
dup z0.b, z2.b[0]
DUP Z0.B, Z2.B[0]
dup z0.b, z31.b[0]
DUP Z0.B, Z31.B[0]
dup z0.b, z0.b[1]
DUP Z0.B, Z0.B[1]
dup z0.b, z0.b[62]
DUP Z0.B, Z0.B[62]
dup z0.b, z0.b[63]
DUP Z0.B, Z0.B[63]
dup z0.h, z0.h[0]
DUP Z0.H, Z0.H[0]
dup z1.h, z0.h[0]
DUP Z1.H, Z0.H[0]
dup z31.h, z0.h[0]
DUP Z31.H, Z0.H[0]
dup z0.h, z2.h[0]
DUP Z0.H, Z2.H[0]
dup z0.h, z31.h[0]
DUP Z0.H, Z31.H[0]
dup z0.h, z0.h[1]
DUP Z0.H, Z0.H[1]
dup z0.h, z0.h[30]
DUP Z0.H, Z0.H[30]
dup z0.h, z0.h[31]
DUP Z0.H, Z0.H[31]
dup z1.b, z0.b[1]
DUP Z1.B, Z0.B[1]
dup z31.b, z0.b[1]
DUP Z31.B, Z0.B[1]
dup z0.b, z2.b[1]
DUP Z0.B, Z2.B[1]
dup z0.b, z31.b[1]
DUP Z0.B, Z31.B[1]
dup z0.b, z0.b[2]
DUP Z0.B, Z0.B[2]
dup z0.s, z0.s[0]
DUP Z0.S, Z0.S[0]
dup z1.s, z0.s[0]
DUP Z1.S, Z0.S[0]
dup z31.s, z0.s[0]
DUP Z31.S, Z0.S[0]
dup z0.s, z2.s[0]
DUP Z0.S, Z2.S[0]
dup z0.s, z31.s[0]
DUP Z0.S, Z31.S[0]
dup z0.s, z0.s[1]
DUP Z0.S, Z0.S[1]
dup z0.s, z0.s[14]
DUP Z0.S, Z0.S[14]
dup z0.s, z0.s[15]
DUP Z0.S, Z0.S[15]
dup z1.b, z0.b[2]
DUP Z1.B, Z0.B[2]
dup z31.b, z0.b[2]
DUP Z31.B, Z0.B[2]
dup z0.b, z2.b[2]
DUP Z0.B, Z2.B[2]
dup z0.b, z31.b[2]
DUP Z0.B, Z31.B[2]
dup z0.b, z0.b[3]
DUP Z0.B, Z0.B[3]
dup z1.h, z0.h[1]
DUP Z1.H, Z0.H[1]
dup z31.h, z0.h[1]
DUP Z31.H, Z0.H[1]
dup z0.h, z2.h[1]
DUP Z0.H, Z2.H[1]
dup z0.h, z31.h[1]
DUP Z0.H, Z31.H[1]
dup z0.h, z0.h[2]
DUP Z0.H, Z0.H[2]
dup z1.b, z0.b[3]
DUP Z1.B, Z0.B[3]
dup z31.b, z0.b[3]
DUP Z31.B, Z0.B[3]
dup z0.b, z2.b[3]
DUP Z0.B, Z2.B[3]
dup z0.b, z31.b[3]
DUP Z0.B, Z31.B[3]
dup z0.b, z0.b[4]
DUP Z0.B, Z0.B[4]
dup z0.d, z0.d[0]
DUP Z0.D, Z0.D[0]
dup z1.d, z0.d[0]
DUP Z1.D, Z0.D[0]
dup z31.d, z0.d[0]
DUP Z31.D, Z0.D[0]
dup z0.d, z2.d[0]
DUP Z0.D, Z2.D[0]
dup z0.d, z31.d[0]
DUP Z0.D, Z31.D[0]
dup z0.d, z0.d[1]
DUP Z0.D, Z0.D[1]
dup z0.d, z0.d[6]
DUP Z0.D, Z0.D[6]
dup z0.d, z0.d[7]
DUP Z0.D, Z0.D[7]
dup z1.b, z0.b[4]
DUP Z1.B, Z0.B[4]
dup z31.b, z0.b[4]
DUP Z31.B, Z0.B[4]
dup z0.b, z2.b[4]
DUP Z0.B, Z2.B[4]
dup z0.b, z31.b[4]
DUP Z0.B, Z31.B[4]
dup z0.b, z0.b[5]
DUP Z0.B, Z0.B[5]
dup z1.h, z0.h[2]
DUP Z1.H, Z0.H[2]
dup z31.h, z0.h[2]
DUP Z31.H, Z0.H[2]
dup z0.h, z2.h[2]
DUP Z0.H, Z2.H[2]
dup z0.h, z31.h[2]
DUP Z0.H, Z31.H[2]
dup z0.h, z0.h[3]
DUP Z0.H, Z0.H[3]
dup z1.b, z0.b[5]
DUP Z1.B, Z0.B[5]
dup z31.b, z0.b[5]
DUP Z31.B, Z0.B[5]
dup z0.b, z2.b[5]
DUP Z0.B, Z2.B[5]
dup z0.b, z31.b[5]
DUP Z0.B, Z31.B[5]
dup z0.b, z0.b[6]
DUP Z0.B, Z0.B[6]
dup z1.s, z0.s[1]
DUP Z1.S, Z0.S[1]
dup z31.s, z0.s[1]
DUP Z31.S, Z0.S[1]
dup z0.s, z2.s[1]
DUP Z0.S, Z2.S[1]
dup z0.s, z31.s[1]
DUP Z0.S, Z31.S[1]
dup z0.s, z0.s[2]
DUP Z0.S, Z0.S[2]
dup z1.b, z0.b[6]
DUP Z1.B, Z0.B[6]
dup z31.b, z0.b[6]
DUP Z31.B, Z0.B[6]
dup z0.b, z2.b[6]
DUP Z0.B, Z2.B[6]
dup z0.b, z31.b[6]
DUP Z0.B, Z31.B[6]
dup z0.b, z0.b[7]
DUP Z0.B, Z0.B[7]
dup z1.h, z0.h[3]
DUP Z1.H, Z0.H[3]
dup z31.h, z0.h[3]
DUP Z31.H, Z0.H[3]
dup z0.h, z2.h[3]
DUP Z0.H, Z2.H[3]
dup z0.h, z31.h[3]
DUP Z0.H, Z31.H[3]
dup z0.h, z0.h[4]
DUP Z0.H, Z0.H[4]
dup z1.b, z0.b[7]
DUP Z1.B, Z0.B[7]
dup z31.b, z0.b[7]
DUP Z31.B, Z0.B[7]
dup z0.b, z2.b[7]
DUP Z0.B, Z2.B[7]
dup z0.b, z31.b[7]
DUP Z0.B, Z31.B[7]
dup z0.b, z0.b[8]
DUP Z0.B, Z0.B[8]
dup z0.q, z0.q[1]
DUP Z0.Q, Z0.Q[1]
dup z1.q, z0.q[1]
DUP Z1.Q, Z0.Q[1]
dup z31.q, z0.q[1]
DUP Z31.Q, Z0.Q[1]
dup z0.q, z2.q[1]
DUP Z0.Q, Z2.Q[1]
dup z0.q, z31.q[1]
DUP Z0.Q, Z31.Q[1]
dup z0.q, z0.q[0]
DUP Z0.Q, Z0.Q[0]
dup z0.q, z0.q[2]
DUP Z0.Q, Z0.Q[2]
dup z0.q, z0.q[3]
DUP Z0.Q, Z0.Q[3]
dup z0.b, #0
DUP Z0.B, #0
dup z0.b, #0, lsl #0
dup z1.b, #0
DUP Z1.B, #0
dup z1.b, #0, lsl #0
dup z31.b, #0
DUP Z31.B, #0
dup z31.b, #0, lsl #0
dup z0.b, #127
DUP Z0.B, #127
dup z0.b, #127, lsl #0
dup z0.b, #-128
DUP Z0.B, #-128
dup z0.b, #-128, lsl #0
dup z0.b, #-127
DUP Z0.B, #-127
dup z0.b, #-127, lsl #0
dup z0.b, #-1
DUP Z0.B, #-1
dup z0.b, #-1, lsl #0
dup z0.h, #0
DUP Z0.H, #0
dup z0.h, #0, lsl #0
dup z1.h, #0
DUP Z1.H, #0
dup z1.h, #0, lsl #0
dup z31.h, #0
DUP Z31.H, #0
dup z31.h, #0, lsl #0
dup z0.h, #127
DUP Z0.H, #127
dup z0.h, #127, lsl #0
dup z0.h, #-128
DUP Z0.H, #-128
dup z0.h, #-128, lsl #0
dup z0.h, #-127
DUP Z0.H, #-127
dup z0.h, #-127, lsl #0
dup z0.h, #-1
DUP Z0.H, #-1
dup z0.h, #-1, lsl #0
dup z0.h, #0, lsl #8
DUP Z0.H, #0, LSL #8
dup z0.h, #32512
DUP Z0.H, #32512
dup z0.h, #32512, lsl #0
dup z0.h, #127, lsl #8
dup z0.h, #-32768
DUP Z0.H, #-32768
dup z0.h, #-32768, lsl #0
dup z0.h, #-128, lsl #8
dup z0.h, #-32512
DUP Z0.H, #-32512
dup z0.h, #-32512, lsl #0
dup z0.h, #-127, lsl #8
dup z0.h, #-256
DUP Z0.H, #-256
dup z0.h, #-256, lsl #0
dup z0.h, #-1, lsl #8
dup z0.s, #0
DUP Z0.S, #0
dup z0.s, #0, lsl #0
dup z1.s, #0
DUP Z1.S, #0
dup z1.s, #0, lsl #0
dup z31.s, #0
DUP Z31.S, #0
dup z31.s, #0, lsl #0
dup z0.s, #127
DUP Z0.S, #127
dup z0.s, #127, lsl #0
dup z0.s, #-128
DUP Z0.S, #-128
dup z0.s, #-128, lsl #0
dup z0.s, #-127
DUP Z0.S, #-127
dup z0.s, #-127, lsl #0
dup z0.s, #-1
DUP Z0.S, #-1
dup z0.s, #-1, lsl #0
dup z0.s, #0, lsl #8
DUP Z0.S, #0, LSL #8
dup z0.s, #32512
DUP Z0.S, #32512
dup z0.s, #32512, lsl #0
dup z0.s, #127, lsl #8
dup z0.s, #-32768
DUP Z0.S, #-32768
dup z0.s, #-32768, lsl #0
dup z0.s, #-128, lsl #8
dup z0.s, #-32512
DUP Z0.S, #-32512
dup z0.s, #-32512, lsl #0
dup z0.s, #-127, lsl #8
dup z0.s, #-256
DUP Z0.S, #-256
dup z0.s, #-256, lsl #0
dup z0.s, #-1, lsl #8
dup z0.d, #0
DUP Z0.D, #0
dup z0.d, #0, lsl #0
dup z1.d, #0
DUP Z1.D, #0
dup z1.d, #0, lsl #0
dup z31.d, #0
DUP Z31.D, #0
dup z31.d, #0, lsl #0
dup z0.d, #127
DUP Z0.D, #127
dup z0.d, #127, lsl #0
dup z0.d, #-128
DUP Z0.D, #-128
dup z0.d, #-128, lsl #0
dup z0.d, #-127
DUP Z0.D, #-127
dup z0.d, #-127, lsl #0
dup z0.d, #-1
DUP Z0.D, #-1
dup z0.d, #-1, lsl #0
dup z0.d, #0, lsl #8
DUP Z0.D, #0, LSL #8
dup z0.d, #32512
DUP Z0.D, #32512
dup z0.d, #32512, lsl #0
dup z0.d, #127, lsl #8
dup z0.d, #-32768
DUP Z0.D, #-32768
dup z0.d, #-32768, lsl #0
dup z0.d, #-128, lsl #8
dup z0.d, #-32512
DUP Z0.D, #-32512
dup z0.d, #-32512, lsl #0
dup z0.d, #-127, lsl #8
dup z0.d, #-256
DUP Z0.D, #-256
dup z0.d, #-256, lsl #0
dup z0.d, #-1, lsl #8
dupm z0.s, #0x1
DUPM Z0.S, #0X1
dupm z0.d, #0x100000001
dupm z1.s, #0x1
DUPM Z1.S, #0X1
dupm z1.d, #0x100000001
dupm z31.s, #0x1
DUPM Z31.S, #0X1
dupm z31.d, #0x100000001
dupm z0.s, #0x7f
DUPM Z0.S, #0X7F
dupm z0.d, #0x7f0000007f
dupm z0.s, #0x7fffffff
DUPM Z0.S, #0X7FFFFFFF
dupm z0.d, #0x7fffffff7fffffff
dupm z0.h, #0x1
DUPM Z0.H, #0X1
dupm z0.s, #0x10001
dupm z0.d, #0x1000100010001
dupm z0.h, #0x7fff
DUPM Z0.H, #0X7FFF
dupm z0.s, #0x7fff7fff
dupm z0.d, #0x7fff7fff7fff7fff
dupm z0.b, #0x1
DUPM Z0.B, #0X1
dupm z0.h, #0x101
dupm z0.s, #0x1010101
dupm z0.d, #0x101010101010101
dupm z0.b, #0x55
DUPM Z0.B, #0X55
dupm z0.h, #0x5555
dupm z0.s, #0x55555555
dupm z0.d, #0x5555555555555555
dupm z0.s, #0x80000000
DUPM Z0.S, #0X80000000
dupm z0.d, #0x8000000080000000
dupm z0.s, #0xbfffffff
DUPM Z0.S, #0XBFFFFFFF
dupm z0.d, #0xbfffffffbfffffff
dupm z0.h, #0x8000
DUPM Z0.H, #0X8000
dupm z0.s, #0x80008000
dupm z0.d, #0x8000800080008000
dupm z0.b, #0xbf
DUPM Z0.B, #0XBF
dupm z0.h, #0xbfbf
dupm z0.s, #0xbfbfbfbf
dupm z0.d, #0xbfbfbfbfbfbfbfbf
dupm z0.b, #0xe3
DUPM Z0.B, #0XE3
dupm z0.h, #0xe3e3
dupm z0.s, #0xe3e3e3e3
dupm z0.d, #0xe3e3e3e3e3e3e3e3
dupm z0.s, #0xfffffeff
DUPM Z0.S, #0XFFFFFEFF
dupm z0.d, #0xfffffefffffffeff
dupm z0.d, #0xfffffffffffffffe
DUPM Z0.D, #0XFFFFFFFFFFFFFFFE
eor z0.d, z0.d, z0.d
EOR Z0.D, Z0.D, Z0.D
eor z1.d, z0.d, z0.d
EOR Z1.D, Z0.D, Z0.D
eor z31.d, z0.d, z0.d
EOR Z31.D, Z0.D, Z0.D
eor z0.d, z2.d, z0.d
EOR Z0.D, Z2.D, Z0.D
eor z0.d, z31.d, z0.d
EOR Z0.D, Z31.D, Z0.D
eor z0.d, z0.d, z3.d
EOR Z0.D, Z0.D, Z3.D
eor z0.d, z0.d, z31.d
EOR Z0.D, Z0.D, Z31.D
eor z0.s, z0.s, #0x1
EOR Z0.S, Z0.S, #0X1
eor z0.d, z0.d, #0x100000001
eor z1.s, z1.s, #0x1
EOR Z1.S, Z1.S, #0X1
eor z1.d, z1.d, #0x100000001
eor z31.s, z31.s, #0x1
EOR Z31.S, Z31.S, #0X1
eor z31.d, z31.d, #0x100000001
eor z2.s, z2.s, #0x1
EOR Z2.S, Z2.S, #0X1
eor z2.d, z2.d, #0x100000001
eor z0.s, z0.s, #0x7f
EOR Z0.S, Z0.S, #0X7F
eor z0.d, z0.d, #0x7f0000007f
eor z0.s, z0.s, #0x7fffffff
EOR Z0.S, Z0.S, #0X7FFFFFFF
eor z0.d, z0.d, #0x7fffffff7fffffff
eor z0.h, z0.h, #0x1
EOR Z0.H, Z0.H, #0X1
eor z0.s, z0.s, #0x10001
eor z0.d, z0.d, #0x1000100010001
eor z0.h, z0.h, #0x7fff
EOR Z0.H, Z0.H, #0X7FFF
eor z0.s, z0.s, #0x7fff7fff
eor z0.d, z0.d, #0x7fff7fff7fff7fff
eor z0.b, z0.b, #0x1
EOR Z0.B, Z0.B, #0X1
eor z0.h, z0.h, #0x101
eor z0.s, z0.s, #0x1010101
eor z0.d, z0.d, #0x101010101010101
eor z0.b, z0.b, #0x55
EOR Z0.B, Z0.B, #0X55
eor z0.h, z0.h, #0x5555
eor z0.s, z0.s, #0x55555555
eor z0.d, z0.d, #0x5555555555555555
eor z0.s, z0.s, #0x80000000
EOR Z0.S, Z0.S, #0X80000000
eor z0.d, z0.d, #0x8000000080000000
eor z0.s, z0.s, #0xbfffffff
EOR Z0.S, Z0.S, #0XBFFFFFFF
eor z0.d, z0.d, #0xbfffffffbfffffff
eor z0.h, z0.h, #0x8000
EOR Z0.H, Z0.H, #0X8000
eor z0.s, z0.s, #0x80008000
eor z0.d, z0.d, #0x8000800080008000
eor z0.b, z0.b, #0xbf
EOR Z0.B, Z0.B, #0XBF
eor z0.h, z0.h, #0xbfbf
eor z0.s, z0.s, #0xbfbfbfbf
eor z0.d, z0.d, #0xbfbfbfbfbfbfbfbf
eor z0.b, z0.b, #0xe3
EOR Z0.B, Z0.B, #0XE3
eor z0.h, z0.h, #0xe3e3
eor z0.s, z0.s, #0xe3e3e3e3
eor z0.d, z0.d, #0xe3e3e3e3e3e3e3e3
eor z0.s, z0.s, #0xfffffeff
EOR Z0.S, Z0.S, #0XFFFFFEFF
eor z0.d, z0.d, #0xfffffefffffffeff
eor z0.d, z0.d, #0xfffffffffffffffe
EOR Z0.D, Z0.D, #0XFFFFFFFFFFFFFFFE
eor z0.b, p0/m, z0.b, z0.b
EOR Z0.B, P0/M, Z0.B, Z0.B
eor z1.b, p0/m, z1.b, z0.b
EOR Z1.B, P0/M, Z1.B, Z0.B
eor z31.b, p0/m, z31.b, z0.b
EOR Z31.B, P0/M, Z31.B, Z0.B
eor z0.b, p2/m, z0.b, z0.b
EOR Z0.B, P2/M, Z0.B, Z0.B
eor z0.b, p7/m, z0.b, z0.b
EOR Z0.B, P7/M, Z0.B, Z0.B
eor z3.b, p0/m, z3.b, z0.b
EOR Z3.B, P0/M, Z3.B, Z0.B
eor z0.b, p0/m, z0.b, z4.b
EOR Z0.B, P0/M, Z0.B, Z4.B
eor z0.b, p0/m, z0.b, z31.b
EOR Z0.B, P0/M, Z0.B, Z31.B
eor z0.h, p0/m, z0.h, z0.h
EOR Z0.H, P0/M, Z0.H, Z0.H
eor z1.h, p0/m, z1.h, z0.h
EOR Z1.H, P0/M, Z1.H, Z0.H
eor z31.h, p0/m, z31.h, z0.h
EOR Z31.H, P0/M, Z31.H, Z0.H
eor z0.h, p2/m, z0.h, z0.h
EOR Z0.H, P2/M, Z0.H, Z0.H
eor z0.h, p7/m, z0.h, z0.h
EOR Z0.H, P7/M, Z0.H, Z0.H
eor z3.h, p0/m, z3.h, z0.h
EOR Z3.H, P0/M, Z3.H, Z0.H
eor z0.h, p0/m, z0.h, z4.h
EOR Z0.H, P0/M, Z0.H, Z4.H
eor z0.h, p0/m, z0.h, z31.h
EOR Z0.H, P0/M, Z0.H, Z31.H
eor z0.s, p0/m, z0.s, z0.s
EOR Z0.S, P0/M, Z0.S, Z0.S
eor z1.s, p0/m, z1.s, z0.s
EOR Z1.S, P0/M, Z1.S, Z0.S
eor z31.s, p0/m, z31.s, z0.s
EOR Z31.S, P0/M, Z31.S, Z0.S
eor z0.s, p2/m, z0.s, z0.s
EOR Z0.S, P2/M, Z0.S, Z0.S
eor z0.s, p7/m, z0.s, z0.s
EOR Z0.S, P7/M, Z0.S, Z0.S
eor z3.s, p0/m, z3.s, z0.s
EOR Z3.S, P0/M, Z3.S, Z0.S
eor z0.s, p0/m, z0.s, z4.s
EOR Z0.S, P0/M, Z0.S, Z4.S
eor z0.s, p0/m, z0.s, z31.s
EOR Z0.S, P0/M, Z0.S, Z31.S
eor z0.d, p0/m, z0.d, z0.d
EOR Z0.D, P0/M, Z0.D, Z0.D
eor z1.d, p0/m, z1.d, z0.d
EOR Z1.D, P0/M, Z1.D, Z0.D
eor z31.d, p0/m, z31.d, z0.d
EOR Z31.D, P0/M, Z31.D, Z0.D
eor z0.d, p2/m, z0.d, z0.d
EOR Z0.D, P2/M, Z0.D, Z0.D
eor z0.d, p7/m, z0.d, z0.d
EOR Z0.D, P7/M, Z0.D, Z0.D
eor z3.d, p0/m, z3.d, z0.d
EOR Z3.D, P0/M, Z3.D, Z0.D
eor z0.d, p0/m, z0.d, z4.d
EOR Z0.D, P0/M, Z0.D, Z4.D
eor z0.d, p0/m, z0.d, z31.d
EOR Z0.D, P0/M, Z0.D, Z31.D
eor p0.b, p0/z, p0.b, p0.b
EOR P0.B, P0/Z, P0.B, P0.B
eor p1.b, p0/z, p0.b, p0.b
EOR P1.B, P0/Z, P0.B, P0.B
eor p15.b, p0/z, p0.b, p0.b
EOR P15.B, P0/Z, P0.B, P0.B
eor p0.b, p2/z, p0.b, p0.b
EOR P0.B, P2/Z, P0.B, P0.B
eor p0.b, p15/z, p0.b, p0.b
EOR P0.B, P15/Z, P0.B, P0.B
eor p0.b, p0/z, p3.b, p0.b
EOR P0.B, P0/Z, P3.B, P0.B
eor p0.b, p0/z, p15.b, p0.b
EOR P0.B, P0/Z, P15.B, P0.B
eor p0.b, p0/z, p0.b, p4.b
EOR P0.B, P0/Z, P0.B, P4.B
eor p0.b, p0/z, p0.b, p15.b
EOR P0.B, P0/Z, P0.B, P15.B
eors p0.b, p0/z, p0.b, p0.b
EORS P0.B, P0/Z, P0.B, P0.B
eors p1.b, p0/z, p0.b, p0.b
EORS P1.B, P0/Z, P0.B, P0.B
eors p15.b, p0/z, p0.b, p0.b
EORS P15.B, P0/Z, P0.B, P0.B
eors p0.b, p2/z, p0.b, p0.b
EORS P0.B, P2/Z, P0.B, P0.B
eors p0.b, p15/z, p0.b, p0.b
EORS P0.B, P15/Z, P0.B, P0.B
eors p0.b, p0/z, p3.b, p0.b
EORS P0.B, P0/Z, P3.B, P0.B
eors p0.b, p0/z, p15.b, p0.b
EORS P0.B, P0/Z, P15.B, P0.B
eors p0.b, p0/z, p0.b, p4.b
EORS P0.B, P0/Z, P0.B, P4.B
eors p0.b, p0/z, p0.b, p15.b
EORS P0.B, P0/Z, P0.B, P15.B
eorv b0, p0, z0.b
EORV B0, P0, Z0.B
eorv b1, p0, z0.b
EORV B1, P0, Z0.B
eorv b31, p0, z0.b
EORV B31, P0, Z0.B
eorv b0, p2, z0.b
EORV B0, P2, Z0.B
eorv b0, p7, z0.b
EORV B0, P7, Z0.B
eorv b0, p0, z3.b
EORV B0, P0, Z3.B
eorv b0, p0, z31.b
EORV B0, P0, Z31.B
eorv h0, p0, z0.h
EORV H0, P0, Z0.H
eorv h1, p0, z0.h
EORV H1, P0, Z0.H
eorv h31, p0, z0.h
EORV H31, P0, Z0.H
eorv h0, p2, z0.h
EORV H0, P2, Z0.H
eorv h0, p7, z0.h
EORV H0, P7, Z0.H
eorv h0, p0, z3.h
EORV H0, P0, Z3.H
eorv h0, p0, z31.h
EORV H0, P0, Z31.H
eorv s0, p0, z0.s
EORV S0, P0, Z0.S
eorv s1, p0, z0.s
EORV S1, P0, Z0.S
eorv s31, p0, z0.s
EORV S31, P0, Z0.S
eorv s0, p2, z0.s
EORV S0, P2, Z0.S
eorv s0, p7, z0.s
EORV S0, P7, Z0.S
eorv s0, p0, z3.s
EORV S0, P0, Z3.S
eorv s0, p0, z31.s
EORV S0, P0, Z31.S
eorv d0, p0, z0.d
EORV D0, P0, Z0.D
eorv d1, p0, z0.d
EORV D1, P0, Z0.D
eorv d31, p0, z0.d
EORV D31, P0, Z0.D
eorv d0, p2, z0.d
EORV D0, P2, Z0.D
eorv d0, p7, z0.d
EORV D0, P7, Z0.D
eorv d0, p0, z3.d
EORV D0, P0, Z3.D
eorv d0, p0, z31.d
EORV D0, P0, Z31.D
ext z0.b, z0.b, z0.b, #0
EXT Z0.B, Z0.B, Z0.B, #0
ext z1.b, z1.b, z0.b, #0
EXT Z1.B, Z1.B, Z0.B, #0
ext z31.b, z31.b, z0.b, #0
EXT Z31.B, Z31.B, Z0.B, #0
ext z2.b, z2.b, z0.b, #0
EXT Z2.B, Z2.B, Z0.B, #0
ext z0.b, z0.b, z3.b, #0
EXT Z0.B, Z0.B, Z3.B, #0
ext z0.b, z0.b, z31.b, #0
EXT Z0.B, Z0.B, Z31.B, #0
ext z0.b, z0.b, z0.b, #127
EXT Z0.B, Z0.B, Z0.B, #127
ext z0.b, z0.b, z0.b, #128
EXT Z0.B, Z0.B, Z0.B, #128
ext z0.b, z0.b, z0.b, #129
EXT Z0.B, Z0.B, Z0.B, #129
ext z0.b, z0.b, z0.b, #255
EXT Z0.B, Z0.B, Z0.B, #255
fabd z0.h, p0/m, z0.h, z0.h
FABD Z0.H, P0/M, Z0.H, Z0.H
fabd z1.h, p0/m, z1.h, z0.h
FABD Z1.H, P0/M, Z1.H, Z0.H
fabd z31.h, p0/m, z31.h, z0.h
FABD Z31.H, P0/M, Z31.H, Z0.H
fabd z0.h, p2/m, z0.h, z0.h
FABD Z0.H, P2/M, Z0.H, Z0.H
fabd z0.h, p7/m, z0.h, z0.h
FABD Z0.H, P7/M, Z0.H, Z0.H
fabd z3.h, p0/m, z3.h, z0.h
FABD Z3.H, P0/M, Z3.H, Z0.H
fabd z0.h, p0/m, z0.h, z4.h
FABD Z0.H, P0/M, Z0.H, Z4.H
fabd z0.h, p0/m, z0.h, z31.h
FABD Z0.H, P0/M, Z0.H, Z31.H
fabd z0.s, p0/m, z0.s, z0.s
FABD Z0.S, P0/M, Z0.S, Z0.S
fabd z1.s, p0/m, z1.s, z0.s
FABD Z1.S, P0/M, Z1.S, Z0.S
fabd z31.s, p0/m, z31.s, z0.s
FABD Z31.S, P0/M, Z31.S, Z0.S
fabd z0.s, p2/m, z0.s, z0.s
FABD Z0.S, P2/M, Z0.S, Z0.S
fabd z0.s, p7/m, z0.s, z0.s
FABD Z0.S, P7/M, Z0.S, Z0.S
fabd z3.s, p0/m, z3.s, z0.s
FABD Z3.S, P0/M, Z3.S, Z0.S
fabd z0.s, p0/m, z0.s, z4.s
FABD Z0.S, P0/M, Z0.S, Z4.S
fabd z0.s, p0/m, z0.s, z31.s
FABD Z0.S, P0/M, Z0.S, Z31.S
fabd z0.d, p0/m, z0.d, z0.d
FABD Z0.D, P0/M, Z0.D, Z0.D
fabd z1.d, p0/m, z1.d, z0.d
FABD Z1.D, P0/M, Z1.D, Z0.D
fabd z31.d, p0/m, z31.d, z0.d
FABD Z31.D, P0/M, Z31.D, Z0.D
fabd z0.d, p2/m, z0.d, z0.d
FABD Z0.D, P2/M, Z0.D, Z0.D
fabd z0.d, p7/m, z0.d, z0.d
FABD Z0.D, P7/M, Z0.D, Z0.D
fabd z3.d, p0/m, z3.d, z0.d
FABD Z3.D, P0/M, Z3.D, Z0.D
fabd z0.d, p0/m, z0.d, z4.d
FABD Z0.D, P0/M, Z0.D, Z4.D
fabd z0.d, p0/m, z0.d, z31.d
FABD Z0.D, P0/M, Z0.D, Z31.D
fabs z0.h, p0/m, z0.h
FABS Z0.H, P0/M, Z0.H
fabs z1.h, p0/m, z0.h
FABS Z1.H, P0/M, Z0.H
fabs z31.h, p0/m, z0.h
FABS Z31.H, P0/M, Z0.H
fabs z0.h, p2/m, z0.h
FABS Z0.H, P2/M, Z0.H
fabs z0.h, p7/m, z0.h
FABS Z0.H, P7/M, Z0.H
fabs z0.h, p0/m, z3.h
FABS Z0.H, P0/M, Z3.H
fabs z0.h, p0/m, z31.h
FABS Z0.H, P0/M, Z31.H
fabs z0.s, p0/m, z0.s
FABS Z0.S, P0/M, Z0.S
fabs z1.s, p0/m, z0.s
FABS Z1.S, P0/M, Z0.S
fabs z31.s, p0/m, z0.s
FABS Z31.S, P0/M, Z0.S
fabs z0.s, p2/m, z0.s
FABS Z0.S, P2/M, Z0.S
fabs z0.s, p7/m, z0.s
FABS Z0.S, P7/M, Z0.S
fabs z0.s, p0/m, z3.s
FABS Z0.S, P0/M, Z3.S
fabs z0.s, p0/m, z31.s
FABS Z0.S, P0/M, Z31.S
fabs z0.d, p0/m, z0.d
FABS Z0.D, P0/M, Z0.D
fabs z1.d, p0/m, z0.d
FABS Z1.D, P0/M, Z0.D
fabs z31.d, p0/m, z0.d
FABS Z31.D, P0/M, Z0.D
fabs z0.d, p2/m, z0.d
FABS Z0.D, P2/M, Z0.D
fabs z0.d, p7/m, z0.d
FABS Z0.D, P7/M, Z0.D
fabs z0.d, p0/m, z3.d
FABS Z0.D, P0/M, Z3.D
fabs z0.d, p0/m, z31.d
FABS Z0.D, P0/M, Z31.D
facge p0.h, p0/z, z0.h, z0.h
FACGE P0.H, P0/Z, Z0.H, Z0.H
facge p1.h, p0/z, z0.h, z0.h
FACGE P1.H, P0/Z, Z0.H, Z0.H
facge p15.h, p0/z, z0.h, z0.h
FACGE P15.H, P0/Z, Z0.H, Z0.H
facge p0.h, p2/z, z0.h, z0.h
FACGE P0.H, P2/Z, Z0.H, Z0.H
facge p0.h, p7/z, z0.h, z0.h
FACGE P0.H, P7/Z, Z0.H, Z0.H
facge p0.h, p0/z, z3.h, z0.h
FACGE P0.H, P0/Z, Z3.H, Z0.H
facge p0.h, p0/z, z31.h, z0.h
FACGE P0.H, P0/Z, Z31.H, Z0.H
facge p0.h, p0/z, z0.h, z4.h
FACGE P0.H, P0/Z, Z0.H, Z4.H
facge p0.h, p0/z, z0.h, z31.h
FACGE P0.H, P0/Z, Z0.H, Z31.H
facge p0.s, p0/z, z0.s, z0.s
FACGE P0.S, P0/Z, Z0.S, Z0.S
facge p1.s, p0/z, z0.s, z0.s
FACGE P1.S, P0/Z, Z0.S, Z0.S
facge p15.s, p0/z, z0.s, z0.s
FACGE P15.S, P0/Z, Z0.S, Z0.S
facge p0.s, p2/z, z0.s, z0.s
FACGE P0.S, P2/Z, Z0.S, Z0.S
facge p0.s, p7/z, z0.s, z0.s
FACGE P0.S, P7/Z, Z0.S, Z0.S
facge p0.s, p0/z, z3.s, z0.s
FACGE P0.S, P0/Z, Z3.S, Z0.S
facge p0.s, p0/z, z31.s, z0.s
FACGE P0.S, P0/Z, Z31.S, Z0.S
facge p0.s, p0/z, z0.s, z4.s
FACGE P0.S, P0/Z, Z0.S, Z4.S
facge p0.s, p0/z, z0.s, z31.s
FACGE P0.S, P0/Z, Z0.S, Z31.S
facge p0.d, p0/z, z0.d, z0.d
FACGE P0.D, P0/Z, Z0.D, Z0.D
facge p1.d, p0/z, z0.d, z0.d
FACGE P1.D, P0/Z, Z0.D, Z0.D
facge p15.d, p0/z, z0.d, z0.d
FACGE P15.D, P0/Z, Z0.D, Z0.D
facge p0.d, p2/z, z0.d, z0.d
FACGE P0.D, P2/Z, Z0.D, Z0.D
facge p0.d, p7/z, z0.d, z0.d
FACGE P0.D, P7/Z, Z0.D, Z0.D
facge p0.d, p0/z, z3.d, z0.d
FACGE P0.D, P0/Z, Z3.D, Z0.D
facge p0.d, p0/z, z31.d, z0.d
FACGE P0.D, P0/Z, Z31.D, Z0.D
facge p0.d, p0/z, z0.d, z4.d
FACGE P0.D, P0/Z, Z0.D, Z4.D
facge p0.d, p0/z, z0.d, z31.d
FACGE P0.D, P0/Z, Z0.D, Z31.D
facgt p0.h, p0/z, z0.h, z0.h
FACGT P0.H, P0/Z, Z0.H, Z0.H
facgt p1.h, p0/z, z0.h, z0.h
FACGT P1.H, P0/Z, Z0.H, Z0.H
facgt p15.h, p0/z, z0.h, z0.h
FACGT P15.H, P0/Z, Z0.H, Z0.H
facgt p0.h, p2/z, z0.h, z0.h
FACGT P0.H, P2/Z, Z0.H, Z0.H
facgt p0.h, p7/z, z0.h, z0.h
FACGT P0.H, P7/Z, Z0.H, Z0.H
facgt p0.h, p0/z, z3.h, z0.h
FACGT P0.H, P0/Z, Z3.H, Z0.H
facgt p0.h, p0/z, z31.h, z0.h
FACGT P0.H, P0/Z, Z31.H, Z0.H
facgt p0.h, p0/z, z0.h, z4.h
FACGT P0.H, P0/Z, Z0.H, Z4.H
facgt p0.h, p0/z, z0.h, z31.h
FACGT P0.H, P0/Z, Z0.H, Z31.H
facgt p0.s, p0/z, z0.s, z0.s
FACGT P0.S, P0/Z, Z0.S, Z0.S
facgt p1.s, p0/z, z0.s, z0.s
FACGT P1.S, P0/Z, Z0.S, Z0.S
facgt p15.s, p0/z, z0.s, z0.s
FACGT P15.S, P0/Z, Z0.S, Z0.S
facgt p0.s, p2/z, z0.s, z0.s
FACGT P0.S, P2/Z, Z0.S, Z0.S
facgt p0.s, p7/z, z0.s, z0.s
FACGT P0.S, P7/Z, Z0.S, Z0.S
facgt p0.s, p0/z, z3.s, z0.s
FACGT P0.S, P0/Z, Z3.S, Z0.S
facgt p0.s, p0/z, z31.s, z0.s
FACGT P0.S, P0/Z, Z31.S, Z0.S
facgt p0.s, p0/z, z0.s, z4.s
FACGT P0.S, P0/Z, Z0.S, Z4.S
facgt p0.s, p0/z, z0.s, z31.s
FACGT P0.S, P0/Z, Z0.S, Z31.S
facgt p0.d, p0/z, z0.d, z0.d
FACGT P0.D, P0/Z, Z0.D, Z0.D
facgt p1.d, p0/z, z0.d, z0.d
FACGT P1.D, P0/Z, Z0.D, Z0.D
facgt p15.d, p0/z, z0.d, z0.d
FACGT P15.D, P0/Z, Z0.D, Z0.D
facgt p0.d, p2/z, z0.d, z0.d
FACGT P0.D, P2/Z, Z0.D, Z0.D
facgt p0.d, p7/z, z0.d, z0.d
FACGT P0.D, P7/Z, Z0.D, Z0.D
facgt p0.d, p0/z, z3.d, z0.d
FACGT P0.D, P0/Z, Z3.D, Z0.D
facgt p0.d, p0/z, z31.d, z0.d
FACGT P0.D, P0/Z, Z31.D, Z0.D
facgt p0.d, p0/z, z0.d, z4.d
FACGT P0.D, P0/Z, Z0.D, Z4.D
facgt p0.d, p0/z, z0.d, z31.d
FACGT P0.D, P0/Z, Z0.D, Z31.D
fadd z0.h, z0.h, z0.h
FADD Z0.H, Z0.H, Z0.H
fadd z1.h, z0.h, z0.h
FADD Z1.H, Z0.H, Z0.H
fadd z31.h, z0.h, z0.h
FADD Z31.H, Z0.H, Z0.H
fadd z0.h, z2.h, z0.h
FADD Z0.H, Z2.H, Z0.H
fadd z0.h, z31.h, z0.h
FADD Z0.H, Z31.H, Z0.H
fadd z0.h, z0.h, z3.h
FADD Z0.H, Z0.H, Z3.H
fadd z0.h, z0.h, z31.h
FADD Z0.H, Z0.H, Z31.H
fadd z0.s, z0.s, z0.s
FADD Z0.S, Z0.S, Z0.S
fadd z1.s, z0.s, z0.s
FADD Z1.S, Z0.S, Z0.S
fadd z31.s, z0.s, z0.s
FADD Z31.S, Z0.S, Z0.S
fadd z0.s, z2.s, z0.s
FADD Z0.S, Z2.S, Z0.S
fadd z0.s, z31.s, z0.s
FADD Z0.S, Z31.S, Z0.S
fadd z0.s, z0.s, z3.s
FADD Z0.S, Z0.S, Z3.S
fadd z0.s, z0.s, z31.s
FADD Z0.S, Z0.S, Z31.S
fadd z0.d, z0.d, z0.d
FADD Z0.D, Z0.D, Z0.D
fadd z1.d, z0.d, z0.d
FADD Z1.D, Z0.D, Z0.D
fadd z31.d, z0.d, z0.d
FADD Z31.D, Z0.D, Z0.D
fadd z0.d, z2.d, z0.d
FADD Z0.D, Z2.D, Z0.D
fadd z0.d, z31.d, z0.d
FADD Z0.D, Z31.D, Z0.D
fadd z0.d, z0.d, z3.d
FADD Z0.D, Z0.D, Z3.D
fadd z0.d, z0.d, z31.d
FADD Z0.D, Z0.D, Z31.D
fadd z0.h, p0/m, z0.h, z0.h
FADD Z0.H, P0/M, Z0.H, Z0.H
fadd z1.h, p0/m, z1.h, z0.h
FADD Z1.H, P0/M, Z1.H, Z0.H
fadd z31.h, p0/m, z31.h, z0.h
FADD Z31.H, P0/M, Z31.H, Z0.H
fadd z0.h, p2/m, z0.h, z0.h
FADD Z0.H, P2/M, Z0.H, Z0.H
fadd z0.h, p7/m, z0.h, z0.h
FADD Z0.H, P7/M, Z0.H, Z0.H
fadd z3.h, p0/m, z3.h, z0.h
FADD Z3.H, P0/M, Z3.H, Z0.H
fadd z0.h, p0/m, z0.h, z4.h
FADD Z0.H, P0/M, Z0.H, Z4.H
fadd z0.h, p0/m, z0.h, z31.h
FADD Z0.H, P0/M, Z0.H, Z31.H
fadd z0.s, p0/m, z0.s, z0.s
FADD Z0.S, P0/M, Z0.S, Z0.S
fadd z1.s, p0/m, z1.s, z0.s
FADD Z1.S, P0/M, Z1.S, Z0.S
fadd z31.s, p0/m, z31.s, z0.s
FADD Z31.S, P0/M, Z31.S, Z0.S
fadd z0.s, p2/m, z0.s, z0.s
FADD Z0.S, P2/M, Z0.S, Z0.S
fadd z0.s, p7/m, z0.s, z0.s
FADD Z0.S, P7/M, Z0.S, Z0.S
fadd z3.s, p0/m, z3.s, z0.s
FADD Z3.S, P0/M, Z3.S, Z0.S
fadd z0.s, p0/m, z0.s, z4.s
FADD Z0.S, P0/M, Z0.S, Z4.S
fadd z0.s, p0/m, z0.s, z31.s
FADD Z0.S, P0/M, Z0.S, Z31.S
fadd z0.d, p0/m, z0.d, z0.d
FADD Z0.D, P0/M, Z0.D, Z0.D
fadd z1.d, p0/m, z1.d, z0.d
FADD Z1.D, P0/M, Z1.D, Z0.D
fadd z31.d, p0/m, z31.d, z0.d
FADD Z31.D, P0/M, Z31.D, Z0.D
fadd z0.d, p2/m, z0.d, z0.d
FADD Z0.D, P2/M, Z0.D, Z0.D
fadd z0.d, p7/m, z0.d, z0.d
FADD Z0.D, P7/M, Z0.D, Z0.D
fadd z3.d, p0/m, z3.d, z0.d
FADD Z3.D, P0/M, Z3.D, Z0.D
fadd z0.d, p0/m, z0.d, z4.d
FADD Z0.D, P0/M, Z0.D, Z4.D
fadd z0.d, p0/m, z0.d, z31.d
FADD Z0.D, P0/M, Z0.D, Z31.D
fadd z0.h, p0/m, z0.h, #0.5
FADD Z0.H, P0/M, Z0.H, #0.5
fadd z0.h, p0/m, z0.h, #0.50000
fadd z0.h, p0/m, z0.h, #5.0000000000e-01
fadd z1.h, p0/m, z1.h, #0.5
FADD Z1.H, P0/M, Z1.H, #0.5
fadd z1.h, p0/m, z1.h, #0.50000
fadd z1.h, p0/m, z1.h, #5.0000000000e-01
fadd z31.h, p0/m, z31.h, #0.5
FADD Z31.H, P0/M, Z31.H, #0.5
fadd z31.h, p0/m, z31.h, #0.50000
fadd z31.h, p0/m, z31.h, #5.0000000000e-01
fadd z0.h, p2/m, z0.h, #0.5
FADD Z0.H, P2/M, Z0.H, #0.5
fadd z0.h, p2/m, z0.h, #0.50000
fadd z0.h, p2/m, z0.h, #5.0000000000e-01
fadd z0.h, p7/m, z0.h, #0.5
FADD Z0.H, P7/M, Z0.H, #0.5
fadd z0.h, p7/m, z0.h, #0.50000
fadd z0.h, p7/m, z0.h, #5.0000000000e-01
fadd z3.h, p0/m, z3.h, #0.5
FADD Z3.H, P0/M, Z3.H, #0.5
fadd z3.h, p0/m, z3.h, #0.50000
fadd z3.h, p0/m, z3.h, #5.0000000000e-01
fadd z0.h, p0/m, z0.h, #1.0
FADD Z0.H, P0/M, Z0.H, #1.0
fadd z0.h, p0/m, z0.h, #1.00000
fadd z0.h, p0/m, z0.h, #1.0000000000e+00
fadd z0.s, p0/m, z0.s, #0.5
FADD Z0.S, P0/M, Z0.S, #0.5
fadd z0.s, p0/m, z0.s, #0.50000
fadd z0.s, p0/m, z0.s, #5.0000000000e-01
fadd z1.s, p0/m, z1.s, #0.5
FADD Z1.S, P0/M, Z1.S, #0.5
fadd z1.s, p0/m, z1.s, #0.50000
fadd z1.s, p0/m, z1.s, #5.0000000000e-01
fadd z31.s, p0/m, z31.s, #0.5
FADD Z31.S, P0/M, Z31.S, #0.5
fadd z31.s, p0/m, z31.s, #0.50000
fadd z31.s, p0/m, z31.s, #5.0000000000e-01
fadd z0.s, p2/m, z0.s, #0.5
FADD Z0.S, P2/M, Z0.S, #0.5
fadd z0.s, p2/m, z0.s, #0.50000
fadd z0.s, p2/m, z0.s, #5.0000000000e-01
fadd z0.s, p7/m, z0.s, #0.5
FADD Z0.S, P7/M, Z0.S, #0.5
fadd z0.s, p7/m, z0.s, #0.50000
fadd z0.s, p7/m, z0.s, #5.0000000000e-01
fadd z3.s, p0/m, z3.s, #0.5
FADD Z3.S, P0/M, Z3.S, #0.5
fadd z3.s, p0/m, z3.s, #0.50000
fadd z3.s, p0/m, z3.s, #5.0000000000e-01
fadd z0.s, p0/m, z0.s, #1.0
FADD Z0.S, P0/M, Z0.S, #1.0
fadd z0.s, p0/m, z0.s, #1.00000
fadd z0.s, p0/m, z0.s, #1.0000000000e+00
fadd z0.d, p0/m, z0.d, #0.5
FADD Z0.D, P0/M, Z0.D, #0.5
fadd z0.d, p0/m, z0.d, #0.50000
fadd z0.d, p0/m, z0.d, #5.0000000000e-01
fadd z1.d, p0/m, z1.d, #0.5
FADD Z1.D, P0/M, Z1.D, #0.5
fadd z1.d, p0/m, z1.d, #0.50000
fadd z1.d, p0/m, z1.d, #5.0000000000e-01
fadd z31.d, p0/m, z31.d, #0.5
FADD Z31.D, P0/M, Z31.D, #0.5
fadd z31.d, p0/m, z31.d, #0.50000
fadd z31.d, p0/m, z31.d, #5.0000000000e-01
fadd z0.d, p2/m, z0.d, #0.5
FADD Z0.D, P2/M, Z0.D, #0.5
fadd z0.d, p2/m, z0.d, #0.50000
fadd z0.d, p2/m, z0.d, #5.0000000000e-01
fadd z0.d, p7/m, z0.d, #0.5
FADD Z0.D, P7/M, Z0.D, #0.5
fadd z0.d, p7/m, z0.d, #0.50000
fadd z0.d, p7/m, z0.d, #5.0000000000e-01
fadd z3.d, p0/m, z3.d, #0.5
FADD Z3.D, P0/M, Z3.D, #0.5
fadd z3.d, p0/m, z3.d, #0.50000
fadd z3.d, p0/m, z3.d, #5.0000000000e-01
fadd z0.d, p0/m, z0.d, #1.0
FADD Z0.D, P0/M, Z0.D, #1.0
fadd z0.d, p0/m, z0.d, #1.00000
fadd z0.d, p0/m, z0.d, #1.0000000000e+00
fadda h0, p0, h0, z0.h
FADDA H0, P0, H0, Z0.H
fadda h1, p0, h1, z0.h
FADDA H1, P0, H1, Z0.H
fadda h31, p0, h31, z0.h
FADDA H31, P0, H31, Z0.H
fadda h0, p2, h0, z0.h
FADDA H0, P2, H0, Z0.H
fadda h0, p7, h0, z0.h
FADDA H0, P7, H0, Z0.H
fadda h3, p0, h3, z0.h
FADDA H3, P0, H3, Z0.H
fadda h0, p0, h0, z4.h
FADDA H0, P0, H0, Z4.H
fadda h0, p0, h0, z31.h
FADDA H0, P0, H0, Z31.H
fadda s0, p0, s0, z0.s
FADDA S0, P0, S0, Z0.S
fadda s1, p0, s1, z0.s
FADDA S1, P0, S1, Z0.S
fadda s31, p0, s31, z0.s
FADDA S31, P0, S31, Z0.S
fadda s0, p2, s0, z0.s
FADDA S0, P2, S0, Z0.S
fadda s0, p7, s0, z0.s
FADDA S0, P7, S0, Z0.S
fadda s3, p0, s3, z0.s
FADDA S3, P0, S3, Z0.S
fadda s0, p0, s0, z4.s
FADDA S0, P0, S0, Z4.S
fadda s0, p0, s0, z31.s
FADDA S0, P0, S0, Z31.S
fadda d0, p0, d0, z0.d
FADDA D0, P0, D0, Z0.D
fadda d1, p0, d1, z0.d
FADDA D1, P0, D1, Z0.D
fadda d31, p0, d31, z0.d
FADDA D31, P0, D31, Z0.D
fadda d0, p2, d0, z0.d
FADDA D0, P2, D0, Z0.D
fadda d0, p7, d0, z0.d
FADDA D0, P7, D0, Z0.D
fadda d3, p0, d3, z0.d
FADDA D3, P0, D3, Z0.D
fadda d0, p0, d0, z4.d
FADDA D0, P0, D0, Z4.D
fadda d0, p0, d0, z31.d
FADDA D0, P0, D0, Z31.D
faddv h0, p0, z0.h
FADDV H0, P0, Z0.H
faddv h1, p0, z0.h
FADDV H1, P0, Z0.H
faddv h31, p0, z0.h
FADDV H31, P0, Z0.H
faddv h0, p2, z0.h
FADDV H0, P2, Z0.H
faddv h0, p7, z0.h
FADDV H0, P7, Z0.H
faddv h0, p0, z3.h
FADDV H0, P0, Z3.H
faddv h0, p0, z31.h
FADDV H0, P0, Z31.H
faddv s0, p0, z0.s
FADDV S0, P0, Z0.S
faddv s1, p0, z0.s
FADDV S1, P0, Z0.S
faddv s31, p0, z0.s
FADDV S31, P0, Z0.S
faddv s0, p2, z0.s
FADDV S0, P2, Z0.S
faddv s0, p7, z0.s
FADDV S0, P7, Z0.S
faddv s0, p0, z3.s
FADDV S0, P0, Z3.S
faddv s0, p0, z31.s
FADDV S0, P0, Z31.S
faddv d0, p0, z0.d
FADDV D0, P0, Z0.D
faddv d1, p0, z0.d
FADDV D1, P0, Z0.D
faddv d31, p0, z0.d
FADDV D31, P0, Z0.D
faddv d0, p2, z0.d
FADDV D0, P2, Z0.D
faddv d0, p7, z0.d
FADDV D0, P7, Z0.D
faddv d0, p0, z3.d
FADDV D0, P0, Z3.D
faddv d0, p0, z31.d
FADDV D0, P0, Z31.D
fcadd z0.h, p0/m, z0.h, z0.h, #90
FCADD Z0.H, P0/M, Z0.H, Z0.H, #90
fcadd z1.h, p0/m, z1.h, z0.h, #90
FCADD Z1.H, P0/M, Z1.H, Z0.H, #90
fcadd z31.h, p0/m, z31.h, z0.h, #90
FCADD Z31.H, P0/M, Z31.H, Z0.H, #90
fcadd z0.h, p2/m, z0.h, z0.h, #90
FCADD Z0.H, P2/M, Z0.H, Z0.H, #90
fcadd z0.h, p7/m, z0.h, z0.h, #90
FCADD Z0.H, P7/M, Z0.H, Z0.H, #90
fcadd z3.h, p0/m, z3.h, z0.h, #90
FCADD Z3.H, P0/M, Z3.H, Z0.H, #90
fcadd z0.h, p0/m, z0.h, z4.h, #90
FCADD Z0.H, P0/M, Z0.H, Z4.H, #90
fcadd z0.h, p0/m, z0.h, z31.h, #90
FCADD Z0.H, P0/M, Z0.H, Z31.H, #90
fcadd z0.h, p0/m, z0.h, z0.h, #270
FCADD Z0.H, P0/M, Z0.H, Z0.H, #270
fcadd z0.s, p0/m, z0.s, z0.s, #90
FCADD Z0.S, P0/M, Z0.S, Z0.S, #90
fcadd z1.s, p0/m, z1.s, z0.s, #90
FCADD Z1.S, P0/M, Z1.S, Z0.S, #90
fcadd z31.s, p0/m, z31.s, z0.s, #90
FCADD Z31.S, P0/M, Z31.S, Z0.S, #90
fcadd z0.s, p2/m, z0.s, z0.s, #90
FCADD Z0.S, P2/M, Z0.S, Z0.S, #90
fcadd z0.s, p7/m, z0.s, z0.s, #90
FCADD Z0.S, P7/M, Z0.S, Z0.S, #90
fcadd z3.s, p0/m, z3.s, z0.s, #90
FCADD Z3.S, P0/M, Z3.S, Z0.S, #90
fcadd z0.s, p0/m, z0.s, z4.s, #90
FCADD Z0.S, P0/M, Z0.S, Z4.S, #90
fcadd z0.s, p0/m, z0.s, z31.s, #90
FCADD Z0.S, P0/M, Z0.S, Z31.S, #90
fcadd z0.s, p0/m, z0.s, z0.s, #270
FCADD Z0.S, P0/M, Z0.S, Z0.S, #270
fcadd z0.d, p0/m, z0.d, z0.d, #90
FCADD Z0.D, P0/M, Z0.D, Z0.D, #90
fcadd z1.d, p0/m, z1.d, z0.d, #90
FCADD Z1.D, P0/M, Z1.D, Z0.D, #90
fcadd z31.d, p0/m, z31.d, z0.d, #90
FCADD Z31.D, P0/M, Z31.D, Z0.D, #90
fcadd z0.d, p2/m, z0.d, z0.d, #90
FCADD Z0.D, P2/M, Z0.D, Z0.D, #90
fcadd z0.d, p7/m, z0.d, z0.d, #90
FCADD Z0.D, P7/M, Z0.D, Z0.D, #90
fcadd z3.d, p0/m, z3.d, z0.d, #90
FCADD Z3.D, P0/M, Z3.D, Z0.D, #90
fcadd z0.d, p0/m, z0.d, z4.d, #90
FCADD Z0.D, P0/M, Z0.D, Z4.D, #90
fcadd z0.d, p0/m, z0.d, z31.d, #90
FCADD Z0.D, P0/M, Z0.D, Z31.D, #90
fcadd z0.d, p0/m, z0.d, z0.d, #270
FCADD Z0.D, P0/M, Z0.D, Z0.D, #270
fcmla z0.h, p0/m, z0.h, z0.h, #0
FCMLA Z0.H, P0/M, Z0.H, Z0.H, #0
fcmla z1.h, p0/m, z0.h, z0.h, #0
FCMLA Z1.H, P0/M, Z0.H, Z0.H, #0
fcmla z31.h, p0/m, z0.h, z0.h, #0
FCMLA Z31.H, P0/M, Z0.H, Z0.H, #0
fcmla z0.h, p2/m, z0.h, z0.h, #0
FCMLA Z0.H, P2/M, Z0.H, Z0.H, #0
fcmla z0.h, p7/m, z0.h, z0.h, #0
FCMLA Z0.H, P7/M, Z0.H, Z0.H, #0
fcmla z0.h, p0/m, z3.h, z0.h, #0
FCMLA Z0.H, P0/M, Z3.H, Z0.H, #0
fcmla z0.h, p0/m, z31.h, z0.h, #0
FCMLA Z0.H, P0/M, Z31.H, Z0.H, #0
fcmla z0.h, p0/m, z0.h, z4.h, #0
FCMLA Z0.H, P0/M, Z0.H, Z4.H, #0
fcmla z0.h, p0/m, z0.h, z31.h, #0
FCMLA Z0.H, P0/M, Z0.H, Z31.H, #0
fcmla z0.h, p0/m, z0.h, z0.h, #90
FCMLA Z0.H, P0/M, Z0.H, Z0.H, #90
fcmla z0.h, p0/m, z0.h, z0.h, #180
FCMLA Z0.H, P0/M, Z0.H, Z0.H, #180
fcmla z0.h, p0/m, z0.h, z0.h, #270
FCMLA Z0.H, P0/M, Z0.H, Z0.H, #270
fcmla z0.s, p0/m, z0.s, z0.s, #0
FCMLA Z0.S, P0/M, Z0.S, Z0.S, #0
fcmla z1.s, p0/m, z0.s, z0.s, #0
FCMLA Z1.S, P0/M, Z0.S, Z0.S, #0
fcmla z31.s, p0/m, z0.s, z0.s, #0
FCMLA Z31.S, P0/M, Z0.S, Z0.S, #0
fcmla z0.s, p2/m, z0.s, z0.s, #0
FCMLA Z0.S, P2/M, Z0.S, Z0.S, #0
fcmla z0.s, p7/m, z0.s, z0.s, #0
FCMLA Z0.S, P7/M, Z0.S, Z0.S, #0
fcmla z0.s, p0/m, z3.s, z0.s, #0
FCMLA Z0.S, P0/M, Z3.S, Z0.S, #0
fcmla z0.s, p0/m, z31.s, z0.s, #0
FCMLA Z0.S, P0/M, Z31.S, Z0.S, #0
fcmla z0.s, p0/m, z0.s, z4.s, #0
FCMLA Z0.S, P0/M, Z0.S, Z4.S, #0
fcmla z0.s, p0/m, z0.s, z31.s, #0
FCMLA Z0.S, P0/M, Z0.S, Z31.S, #0
fcmla z0.s, p0/m, z0.s, z0.s, #90
FCMLA Z0.S, P0/M, Z0.S, Z0.S, #90
fcmla z0.s, p0/m, z0.s, z0.s, #180
FCMLA Z0.S, P0/M, Z0.S, Z0.S, #180
fcmla z0.s, p0/m, z0.s, z0.s, #270
FCMLA Z0.S, P0/M, Z0.S, Z0.S, #270
fcmla z0.d, p0/m, z0.d, z0.d, #0
FCMLA Z0.D, P0/M, Z0.D, Z0.D, #0
fcmla z1.d, p0/m, z0.d, z0.d, #0
FCMLA Z1.D, P0/M, Z0.D, Z0.D, #0
fcmla z31.d, p0/m, z0.d, z0.d, #0
FCMLA Z31.D, P0/M, Z0.D, Z0.D, #0
fcmla z0.d, p2/m, z0.d, z0.d, #0
FCMLA Z0.D, P2/M, Z0.D, Z0.D, #0
fcmla z0.d, p7/m, z0.d, z0.d, #0
FCMLA Z0.D, P7/M, Z0.D, Z0.D, #0
fcmla z0.d, p0/m, z3.d, z0.d, #0
FCMLA Z0.D, P0/M, Z3.D, Z0.D, #0
fcmla z0.d, p0/m, z31.d, z0.d, #0
FCMLA Z0.D, P0/M, Z31.D, Z0.D, #0
fcmla z0.d, p0/m, z0.d, z4.d, #0
FCMLA Z0.D, P0/M, Z0.D, Z4.D, #0
fcmla z0.d, p0/m, z0.d, z31.d, #0
FCMLA Z0.D, P0/M, Z0.D, Z31.D, #0
fcmla z0.d, p0/m, z0.d, z0.d, #90
FCMLA Z0.D, P0/M, Z0.D, Z0.D, #90
fcmla z0.d, p0/m, z0.d, z0.d, #180
FCMLA Z0.D, P0/M, Z0.D, Z0.D, #180
fcmla z0.d, p0/m, z0.d, z0.d, #270
FCMLA Z0.D, P0/M, Z0.D, Z0.D, #270
fcmla z0.h, z0.h, z0.h[0], #0
FCMLA Z0.H, Z0.H, Z0.H[0], #0
fcmla z1.h, z0.h, z0.h[0], #0
FCMLA Z1.H, Z0.H, Z0.H[0], #0
fcmla z31.h, z0.h, z0.h[0], #0
FCMLA Z31.H, Z0.H, Z0.H[0], #0
fcmla z0.h, z2.h, z0.h[0], #0
FCMLA Z0.H, Z2.H, Z0.H[0], #0
fcmla z0.h, z31.h, z0.h[0], #0
FCMLA Z0.H, Z31.H, Z0.H[0], #0
fcmla z0.h, z0.h, z3.h[0], #0
FCMLA Z0.H, Z0.H, Z3.H[0], #0
fcmla z0.h, z0.h, z7.h[0], #0
FCMLA Z0.H, Z0.H, Z7.H[0], #0
fcmla z0.h, z0.h, z0.h[1], #0
FCMLA Z0.H, Z0.H, Z0.H[1], #0
fcmla z0.h, z0.h, z5.h[1], #0
FCMLA Z0.H, Z0.H, Z5.H[1], #0
fcmla z0.h, z0.h, z0.h[2], #0
FCMLA Z0.H, Z0.H, Z0.H[2], #0
fcmla z0.h, z0.h, z3.h[2], #0
FCMLA Z0.H, Z0.H, Z3.H[2], #0
fcmla z0.h, z0.h, z0.h[3], #0
FCMLA Z0.H, Z0.H, Z0.H[3], #0
fcmla z0.h, z0.h, z6.h[3], #0
FCMLA Z0.H, Z0.H, Z6.H[3], #0
fcmla z0.h, z0.h, z0.h[0], #90
FCMLA Z0.H, Z0.H, Z0.H[0], #90
fcmla z0.h, z0.h, z0.h[0], #180
FCMLA Z0.H, Z0.H, Z0.H[0], #180
fcmla z0.h, z0.h, z0.h[0], #270
FCMLA Z0.H, Z0.H, Z0.H[0], #270
fcmla z0.s, z0.s, z0.s[0], #0
FCMLA Z0.S, Z0.S, Z0.S[0], #0
fcmla z1.s, z0.s, z0.s[0], #0
FCMLA Z1.S, Z0.S, Z0.S[0], #0
fcmla z31.s, z0.s, z0.s[0], #0
FCMLA Z31.S, Z0.S, Z0.S[0], #0
fcmla z0.s, z2.s, z0.s[0], #0
FCMLA Z0.S, Z2.S, Z0.S[0], #0
fcmla z0.s, z31.s, z0.s[0], #0
FCMLA Z0.S, Z31.S, Z0.S[0], #0
fcmla z0.s, z0.s, z3.s[0], #0
FCMLA Z0.S, Z0.S, Z3.S[0], #0
fcmla z0.s, z0.s, z15.s[0], #0
FCMLA Z0.S, Z0.S, Z15.S[0], #0
fcmla z0.s, z0.s, z0.s[1], #0
FCMLA Z0.S, Z0.S, Z0.S[1], #0
fcmla z0.s, z0.s, z11.s[1], #0
FCMLA Z0.S, Z0.S, Z11.S[1], #0
fcmla z0.s, z0.s, z0.s[0], #90
FCMLA Z0.S, Z0.S, Z0.S[0], #90
fcmla z0.s, z0.s, z0.s[0], #180
FCMLA Z0.S, Z0.S, Z0.S[0], #180
fcmla z0.s, z0.s, z0.s[0], #270
FCMLA Z0.S, Z0.S, Z0.S[0], #270
fcmeq p0.h, p0/z, z0.h, #0.0
FCMEQ P0.H, P0/Z, Z0.H, #0.0
fcmeq p1.h, p0/z, z0.h, #0.0
FCMEQ P1.H, P0/Z, Z0.H, #0.0
fcmeq p15.h, p0/z, z0.h, #0.0
FCMEQ P15.H, P0/Z, Z0.H, #0.0
fcmeq p0.h, p2/z, z0.h, #0.0
FCMEQ P0.H, P2/Z, Z0.H, #0.0
fcmeq p0.h, p7/z, z0.h, #0.0
FCMEQ P0.H, P7/Z, Z0.H, #0.0
fcmeq p0.h, p0/z, z3.h, #0.0
FCMEQ P0.H, P0/Z, Z3.H, #0.0
fcmeq p0.h, p0/z, z31.h, #0.0
FCMEQ P0.H, P0/Z, Z31.H, #0.0
fcmeq p0.s, p0/z, z0.s, #0.0
FCMEQ P0.S, P0/Z, Z0.S, #0.0
fcmeq p1.s, p0/z, z0.s, #0.0
FCMEQ P1.S, P0/Z, Z0.S, #0.0
fcmeq p15.s, p0/z, z0.s, #0.0
FCMEQ P15.S, P0/Z, Z0.S, #0.0
fcmeq p0.s, p2/z, z0.s, #0.0
FCMEQ P0.S, P2/Z, Z0.S, #0.0
fcmeq p0.s, p7/z, z0.s, #0.0
FCMEQ P0.S, P7/Z, Z0.S, #0.0
fcmeq p0.s, p0/z, z3.s, #0.0
FCMEQ P0.S, P0/Z, Z3.S, #0.0
fcmeq p0.s, p0/z, z31.s, #0.0
FCMEQ P0.S, P0/Z, Z31.S, #0.0
fcmeq p0.d, p0/z, z0.d, #0.0
FCMEQ P0.D, P0/Z, Z0.D, #0.0
fcmeq p1.d, p0/z, z0.d, #0.0
FCMEQ P1.D, P0/Z, Z0.D, #0.0
fcmeq p15.d, p0/z, z0.d, #0.0
FCMEQ P15.D, P0/Z, Z0.D, #0.0
fcmeq p0.d, p2/z, z0.d, #0.0
FCMEQ P0.D, P2/Z, Z0.D, #0.0
fcmeq p0.d, p7/z, z0.d, #0.0
FCMEQ P0.D, P7/Z, Z0.D, #0.0
fcmeq p0.d, p0/z, z3.d, #0.0
FCMEQ P0.D, P0/Z, Z3.D, #0.0
fcmeq p0.d, p0/z, z31.d, #0.0
FCMEQ P0.D, P0/Z, Z31.D, #0.0
fcmeq p0.h, p0/z, z0.h, z0.h
FCMEQ P0.H, P0/Z, Z0.H, Z0.H
fcmeq p1.h, p0/z, z0.h, z0.h
FCMEQ P1.H, P0/Z, Z0.H, Z0.H
fcmeq p15.h, p0/z, z0.h, z0.h
FCMEQ P15.H, P0/Z, Z0.H, Z0.H
fcmeq p0.h, p2/z, z0.h, z0.h
FCMEQ P0.H, P2/Z, Z0.H, Z0.H
fcmeq p0.h, p7/z, z0.h, z0.h
FCMEQ P0.H, P7/Z, Z0.H, Z0.H
fcmeq p0.h, p0/z, z3.h, z0.h
FCMEQ P0.H, P0/Z, Z3.H, Z0.H
fcmeq p0.h, p0/z, z31.h, z0.h
FCMEQ P0.H, P0/Z, Z31.H, Z0.H
fcmeq p0.h, p0/z, z0.h, z4.h
FCMEQ P0.H, P0/Z, Z0.H, Z4.H
fcmeq p0.h, p0/z, z0.h, z31.h
FCMEQ P0.H, P0/Z, Z0.H, Z31.H
fcmeq p0.s, p0/z, z0.s, z0.s
FCMEQ P0.S, P0/Z, Z0.S, Z0.S
fcmeq p1.s, p0/z, z0.s, z0.s
FCMEQ P1.S, P0/Z, Z0.S, Z0.S
fcmeq p15.s, p0/z, z0.s, z0.s
FCMEQ P15.S, P0/Z, Z0.S, Z0.S
fcmeq p0.s, p2/z, z0.s, z0.s
FCMEQ P0.S, P2/Z, Z0.S, Z0.S
fcmeq p0.s, p7/z, z0.s, z0.s
FCMEQ P0.S, P7/Z, Z0.S, Z0.S
fcmeq p0.s, p0/z, z3.s, z0.s
FCMEQ P0.S, P0/Z, Z3.S, Z0.S
fcmeq p0.s, p0/z, z31.s, z0.s
FCMEQ P0.S, P0/Z, Z31.S, Z0.S
fcmeq p0.s, p0/z, z0.s, z4.s
FCMEQ P0.S, P0/Z, Z0.S, Z4.S
fcmeq p0.s, p0/z, z0.s, z31.s
FCMEQ P0.S, P0/Z, Z0.S, Z31.S
fcmeq p0.d, p0/z, z0.d, z0.d
FCMEQ P0.D, P0/Z, Z0.D, Z0.D
fcmeq p1.d, p0/z, z0.d, z0.d
FCMEQ P1.D, P0/Z, Z0.D, Z0.D
fcmeq p15.d, p0/z, z0.d, z0.d
FCMEQ P15.D, P0/Z, Z0.D, Z0.D
fcmeq p0.d, p2/z, z0.d, z0.d
FCMEQ P0.D, P2/Z, Z0.D, Z0.D
fcmeq p0.d, p7/z, z0.d, z0.d
FCMEQ P0.D, P7/Z, Z0.D, Z0.D
fcmeq p0.d, p0/z, z3.d, z0.d
FCMEQ P0.D, P0/Z, Z3.D, Z0.D
fcmeq p0.d, p0/z, z31.d, z0.d
FCMEQ P0.D, P0/Z, Z31.D, Z0.D
fcmeq p0.d, p0/z, z0.d, z4.d
FCMEQ P0.D, P0/Z, Z0.D, Z4.D
fcmeq p0.d, p0/z, z0.d, z31.d
FCMEQ P0.D, P0/Z, Z0.D, Z31.D
fcmge p0.h, p0/z, z0.h, #0.0
FCMGE P0.H, P0/Z, Z0.H, #0.0
fcmge p1.h, p0/z, z0.h, #0.0
FCMGE P1.H, P0/Z, Z0.H, #0.0
fcmge p15.h, p0/z, z0.h, #0.0
FCMGE P15.H, P0/Z, Z0.H, #0.0
fcmge p0.h, p2/z, z0.h, #0.0
FCMGE P0.H, P2/Z, Z0.H, #0.0
fcmge p0.h, p7/z, z0.h, #0.0
FCMGE P0.H, P7/Z, Z0.H, #0.0
fcmge p0.h, p0/z, z3.h, #0.0
FCMGE P0.H, P0/Z, Z3.H, #0.0
fcmge p0.h, p0/z, z31.h, #0.0
FCMGE P0.H, P0/Z, Z31.H, #0.0
fcmge p0.s, p0/z, z0.s, #0.0
FCMGE P0.S, P0/Z, Z0.S, #0.0
fcmge p1.s, p0/z, z0.s, #0.0
FCMGE P1.S, P0/Z, Z0.S, #0.0
fcmge p15.s, p0/z, z0.s, #0.0
FCMGE P15.S, P0/Z, Z0.S, #0.0
fcmge p0.s, p2/z, z0.s, #0.0
FCMGE P0.S, P2/Z, Z0.S, #0.0
fcmge p0.s, p7/z, z0.s, #0.0
FCMGE P0.S, P7/Z, Z0.S, #0.0
fcmge p0.s, p0/z, z3.s, #0.0
FCMGE P0.S, P0/Z, Z3.S, #0.0
fcmge p0.s, p0/z, z31.s, #0.0
FCMGE P0.S, P0/Z, Z31.S, #0.0
fcmge p0.d, p0/z, z0.d, #0.0
FCMGE P0.D, P0/Z, Z0.D, #0.0
fcmge p1.d, p0/z, z0.d, #0.0
FCMGE P1.D, P0/Z, Z0.D, #0.0
fcmge p15.d, p0/z, z0.d, #0.0
FCMGE P15.D, P0/Z, Z0.D, #0.0
fcmge p0.d, p2/z, z0.d, #0.0
FCMGE P0.D, P2/Z, Z0.D, #0.0
fcmge p0.d, p7/z, z0.d, #0.0
FCMGE P0.D, P7/Z, Z0.D, #0.0
fcmge p0.d, p0/z, z3.d, #0.0
FCMGE P0.D, P0/Z, Z3.D, #0.0
fcmge p0.d, p0/z, z31.d, #0.0
FCMGE P0.D, P0/Z, Z31.D, #0.0
fcmge p0.h, p0/z, z0.h, z0.h
FCMGE P0.H, P0/Z, Z0.H, Z0.H
fcmge p1.h, p0/z, z0.h, z0.h
FCMGE P1.H, P0/Z, Z0.H, Z0.H
fcmge p15.h, p0/z, z0.h, z0.h
FCMGE P15.H, P0/Z, Z0.H, Z0.H
fcmge p0.h, p2/z, z0.h, z0.h
FCMGE P0.H, P2/Z, Z0.H, Z0.H
fcmge p0.h, p7/z, z0.h, z0.h
FCMGE P0.H, P7/Z, Z0.H, Z0.H
fcmge p0.h, p0/z, z3.h, z0.h
FCMGE P0.H, P0/Z, Z3.H, Z0.H
fcmge p0.h, p0/z, z31.h, z0.h
FCMGE P0.H, P0/Z, Z31.H, Z0.H
fcmge p0.h, p0/z, z0.h, z4.h
FCMGE P0.H, P0/Z, Z0.H, Z4.H
fcmge p0.h, p0/z, z0.h, z31.h
FCMGE P0.H, P0/Z, Z0.H, Z31.H
fcmge p0.s, p0/z, z0.s, z0.s
FCMGE P0.S, P0/Z, Z0.S, Z0.S
fcmge p1.s, p0/z, z0.s, z0.s
FCMGE P1.S, P0/Z, Z0.S, Z0.S
fcmge p15.s, p0/z, z0.s, z0.s
FCMGE P15.S, P0/Z, Z0.S, Z0.S
fcmge p0.s, p2/z, z0.s, z0.s
FCMGE P0.S, P2/Z, Z0.S, Z0.S
fcmge p0.s, p7/z, z0.s, z0.s
FCMGE P0.S, P7/Z, Z0.S, Z0.S
fcmge p0.s, p0/z, z3.s, z0.s
FCMGE P0.S, P0/Z, Z3.S, Z0.S
fcmge p0.s, p0/z, z31.s, z0.s
FCMGE P0.S, P0/Z, Z31.S, Z0.S
fcmge p0.s, p0/z, z0.s, z4.s
FCMGE P0.S, P0/Z, Z0.S, Z4.S
fcmge p0.s, p0/z, z0.s, z31.s
FCMGE P0.S, P0/Z, Z0.S, Z31.S
fcmge p0.d, p0/z, z0.d, z0.d
FCMGE P0.D, P0/Z, Z0.D, Z0.D
fcmge p1.d, p0/z, z0.d, z0.d
FCMGE P1.D, P0/Z, Z0.D, Z0.D
fcmge p15.d, p0/z, z0.d, z0.d
FCMGE P15.D, P0/Z, Z0.D, Z0.D
fcmge p0.d, p2/z, z0.d, z0.d
FCMGE P0.D, P2/Z, Z0.D, Z0.D
fcmge p0.d, p7/z, z0.d, z0.d
FCMGE P0.D, P7/Z, Z0.D, Z0.D
fcmge p0.d, p0/z, z3.d, z0.d
FCMGE P0.D, P0/Z, Z3.D, Z0.D
fcmge p0.d, p0/z, z31.d, z0.d
FCMGE P0.D, P0/Z, Z31.D, Z0.D
fcmge p0.d, p0/z, z0.d, z4.d
FCMGE P0.D, P0/Z, Z0.D, Z4.D
fcmge p0.d, p0/z, z0.d, z31.d
FCMGE P0.D, P0/Z, Z0.D, Z31.D
fcmgt p0.h, p0/z, z0.h, #0.0
FCMGT P0.H, P0/Z, Z0.H, #0.0
fcmgt p1.h, p0/z, z0.h, #0.0
FCMGT P1.H, P0/Z, Z0.H, #0.0
fcmgt p15.h, p0/z, z0.h, #0.0
FCMGT P15.H, P0/Z, Z0.H, #0.0
fcmgt p0.h, p2/z, z0.h, #0.0
FCMGT P0.H, P2/Z, Z0.H, #0.0
fcmgt p0.h, p7/z, z0.h, #0.0
FCMGT P0.H, P7/Z, Z0.H, #0.0
fcmgt p0.h, p0/z, z3.h, #0.0
FCMGT P0.H, P0/Z, Z3.H, #0.0
fcmgt p0.h, p0/z, z31.h, #0.0
FCMGT P0.H, P0/Z, Z31.H, #0.0
fcmgt p0.s, p0/z, z0.s, #0.0
FCMGT P0.S, P0/Z, Z0.S, #0.0
fcmgt p1.s, p0/z, z0.s, #0.0
FCMGT P1.S, P0/Z, Z0.S, #0.0
fcmgt p15.s, p0/z, z0.s, #0.0
FCMGT P15.S, P0/Z, Z0.S, #0.0
fcmgt p0.s, p2/z, z0.s, #0.0
FCMGT P0.S, P2/Z, Z0.S, #0.0
fcmgt p0.s, p7/z, z0.s, #0.0
FCMGT P0.S, P7/Z, Z0.S, #0.0
fcmgt p0.s, p0/z, z3.s, #0.0
FCMGT P0.S, P0/Z, Z3.S, #0.0
fcmgt p0.s, p0/z, z31.s, #0.0
FCMGT P0.S, P0/Z, Z31.S, #0.0
fcmgt p0.d, p0/z, z0.d, #0.0
FCMGT P0.D, P0/Z, Z0.D, #0.0
fcmgt p1.d, p0/z, z0.d, #0.0
FCMGT P1.D, P0/Z, Z0.D, #0.0
fcmgt p15.d, p0/z, z0.d, #0.0
FCMGT P15.D, P0/Z, Z0.D, #0.0
fcmgt p0.d, p2/z, z0.d, #0.0
FCMGT P0.D, P2/Z, Z0.D, #0.0
fcmgt p0.d, p7/z, z0.d, #0.0
FCMGT P0.D, P7/Z, Z0.D, #0.0
fcmgt p0.d, p0/z, z3.d, #0.0
FCMGT P0.D, P0/Z, Z3.D, #0.0
fcmgt p0.d, p0/z, z31.d, #0.0
FCMGT P0.D, P0/Z, Z31.D, #0.0
fcmgt p0.h, p0/z, z0.h, z0.h
FCMGT P0.H, P0/Z, Z0.H, Z0.H
fcmgt p1.h, p0/z, z0.h, z0.h
FCMGT P1.H, P0/Z, Z0.H, Z0.H
fcmgt p15.h, p0/z, z0.h, z0.h
FCMGT P15.H, P0/Z, Z0.H, Z0.H
fcmgt p0.h, p2/z, z0.h, z0.h
FCMGT P0.H, P2/Z, Z0.H, Z0.H
fcmgt p0.h, p7/z, z0.h, z0.h
FCMGT P0.H, P7/Z, Z0.H, Z0.H
fcmgt p0.h, p0/z, z3.h, z0.h
FCMGT P0.H, P0/Z, Z3.H, Z0.H
fcmgt p0.h, p0/z, z31.h, z0.h
FCMGT P0.H, P0/Z, Z31.H, Z0.H
fcmgt p0.h, p0/z, z0.h, z4.h
FCMGT P0.H, P0/Z, Z0.H, Z4.H
fcmgt p0.h, p0/z, z0.h, z31.h
FCMGT P0.H, P0/Z, Z0.H, Z31.H
fcmgt p0.s, p0/z, z0.s, z0.s
FCMGT P0.S, P0/Z, Z0.S, Z0.S
fcmgt p1.s, p0/z, z0.s, z0.s
FCMGT P1.S, P0/Z, Z0.S, Z0.S
fcmgt p15.s, p0/z, z0.s, z0.s
FCMGT P15.S, P0/Z, Z0.S, Z0.S
fcmgt p0.s, p2/z, z0.s, z0.s
FCMGT P0.S, P2/Z, Z0.S, Z0.S
fcmgt p0.s, p7/z, z0.s, z0.s
FCMGT P0.S, P7/Z, Z0.S, Z0.S
fcmgt p0.s, p0/z, z3.s, z0.s
FCMGT P0.S, P0/Z, Z3.S, Z0.S
fcmgt p0.s, p0/z, z31.s, z0.s
FCMGT P0.S, P0/Z, Z31.S, Z0.S
fcmgt p0.s, p0/z, z0.s, z4.s
FCMGT P0.S, P0/Z, Z0.S, Z4.S
fcmgt p0.s, p0/z, z0.s, z31.s
FCMGT P0.S, P0/Z, Z0.S, Z31.S
fcmgt p0.d, p0/z, z0.d, z0.d
FCMGT P0.D, P0/Z, Z0.D, Z0.D
fcmgt p1.d, p0/z, z0.d, z0.d
FCMGT P1.D, P0/Z, Z0.D, Z0.D
fcmgt p15.d, p0/z, z0.d, z0.d
FCMGT P15.D, P0/Z, Z0.D, Z0.D
fcmgt p0.d, p2/z, z0.d, z0.d
FCMGT P0.D, P2/Z, Z0.D, Z0.D
fcmgt p0.d, p7/z, z0.d, z0.d
FCMGT P0.D, P7/Z, Z0.D, Z0.D
fcmgt p0.d, p0/z, z3.d, z0.d
FCMGT P0.D, P0/Z, Z3.D, Z0.D
fcmgt p0.d, p0/z, z31.d, z0.d
FCMGT P0.D, P0/Z, Z31.D, Z0.D
fcmgt p0.d, p0/z, z0.d, z4.d
FCMGT P0.D, P0/Z, Z0.D, Z4.D
fcmgt p0.d, p0/z, z0.d, z31.d
FCMGT P0.D, P0/Z, Z0.D, Z31.D
fcmle p0.h, p0/z, z0.h, #0.0
FCMLE P0.H, P0/Z, Z0.H, #0.0
fcmle p1.h, p0/z, z0.h, #0.0
FCMLE P1.H, P0/Z, Z0.H, #0.0
fcmle p15.h, p0/z, z0.h, #0.0
FCMLE P15.H, P0/Z, Z0.H, #0.0
fcmle p0.h, p2/z, z0.h, #0.0
FCMLE P0.H, P2/Z, Z0.H, #0.0
fcmle p0.h, p7/z, z0.h, #0.0
FCMLE P0.H, P7/Z, Z0.H, #0.0
fcmle p0.h, p0/z, z3.h, #0.0
FCMLE P0.H, P0/Z, Z3.H, #0.0
fcmle p0.h, p0/z, z31.h, #0.0
FCMLE P0.H, P0/Z, Z31.H, #0.0
fcmle p0.s, p0/z, z0.s, #0.0
FCMLE P0.S, P0/Z, Z0.S, #0.0
fcmle p1.s, p0/z, z0.s, #0.0
FCMLE P1.S, P0/Z, Z0.S, #0.0
fcmle p15.s, p0/z, z0.s, #0.0
FCMLE P15.S, P0/Z, Z0.S, #0.0
fcmle p0.s, p2/z, z0.s, #0.0
FCMLE P0.S, P2/Z, Z0.S, #0.0
fcmle p0.s, p7/z, z0.s, #0.0
FCMLE P0.S, P7/Z, Z0.S, #0.0
fcmle p0.s, p0/z, z3.s, #0.0
FCMLE P0.S, P0/Z, Z3.S, #0.0
fcmle p0.s, p0/z, z31.s, #0.0
FCMLE P0.S, P0/Z, Z31.S, #0.0
fcmle p0.d, p0/z, z0.d, #0.0
FCMLE P0.D, P0/Z, Z0.D, #0.0
fcmle p1.d, p0/z, z0.d, #0.0
FCMLE P1.D, P0/Z, Z0.D, #0.0
fcmle p15.d, p0/z, z0.d, #0.0
FCMLE P15.D, P0/Z, Z0.D, #0.0
fcmle p0.d, p2/z, z0.d, #0.0
FCMLE P0.D, P2/Z, Z0.D, #0.0
fcmle p0.d, p7/z, z0.d, #0.0
FCMLE P0.D, P7/Z, Z0.D, #0.0
fcmle p0.d, p0/z, z3.d, #0.0
FCMLE P0.D, P0/Z, Z3.D, #0.0
fcmle p0.d, p0/z, z31.d, #0.0
FCMLE P0.D, P0/Z, Z31.D, #0.0
fcmlt p0.h, p0/z, z0.h, #0.0
FCMLT P0.H, P0/Z, Z0.H, #0.0
fcmlt p1.h, p0/z, z0.h, #0.0
FCMLT P1.H, P0/Z, Z0.H, #0.0
fcmlt p15.h, p0/z, z0.h, #0.0
FCMLT P15.H, P0/Z, Z0.H, #0.0
fcmlt p0.h, p2/z, z0.h, #0.0
FCMLT P0.H, P2/Z, Z0.H, #0.0
fcmlt p0.h, p7/z, z0.h, #0.0
FCMLT P0.H, P7/Z, Z0.H, #0.0
fcmlt p0.h, p0/z, z3.h, #0.0
FCMLT P0.H, P0/Z, Z3.H, #0.0
fcmlt p0.h, p0/z, z31.h, #0.0
FCMLT P0.H, P0/Z, Z31.H, #0.0
fcmlt p0.s, p0/z, z0.s, #0.0
FCMLT P0.S, P0/Z, Z0.S, #0.0
fcmlt p1.s, p0/z, z0.s, #0.0
FCMLT P1.S, P0/Z, Z0.S, #0.0
fcmlt p15.s, p0/z, z0.s, #0.0
FCMLT P15.S, P0/Z, Z0.S, #0.0
fcmlt p0.s, p2/z, z0.s, #0.0
FCMLT P0.S, P2/Z, Z0.S, #0.0
fcmlt p0.s, p7/z, z0.s, #0.0
FCMLT P0.S, P7/Z, Z0.S, #0.0
fcmlt p0.s, p0/z, z3.s, #0.0
FCMLT P0.S, P0/Z, Z3.S, #0.0
fcmlt p0.s, p0/z, z31.s, #0.0
FCMLT P0.S, P0/Z, Z31.S, #0.0
fcmlt p0.d, p0/z, z0.d, #0.0
FCMLT P0.D, P0/Z, Z0.D, #0.0
fcmlt p1.d, p0/z, z0.d, #0.0
FCMLT P1.D, P0/Z, Z0.D, #0.0
fcmlt p15.d, p0/z, z0.d, #0.0
FCMLT P15.D, P0/Z, Z0.D, #0.0
fcmlt p0.d, p2/z, z0.d, #0.0
FCMLT P0.D, P2/Z, Z0.D, #0.0
fcmlt p0.d, p7/z, z0.d, #0.0
FCMLT P0.D, P7/Z, Z0.D, #0.0
fcmlt p0.d, p0/z, z3.d, #0.0
FCMLT P0.D, P0/Z, Z3.D, #0.0
fcmlt p0.d, p0/z, z31.d, #0.0
FCMLT P0.D, P0/Z, Z31.D, #0.0
fcmne p0.h, p0/z, z0.h, #0.0
FCMNE P0.H, P0/Z, Z0.H, #0.0
fcmne p1.h, p0/z, z0.h, #0.0
FCMNE P1.H, P0/Z, Z0.H, #0.0
fcmne p15.h, p0/z, z0.h, #0.0
FCMNE P15.H, P0/Z, Z0.H, #0.0
fcmne p0.h, p2/z, z0.h, #0.0
FCMNE P0.H, P2/Z, Z0.H, #0.0
fcmne p0.h, p7/z, z0.h, #0.0
FCMNE P0.H, P7/Z, Z0.H, #0.0
fcmne p0.h, p0/z, z3.h, #0.0
FCMNE P0.H, P0/Z, Z3.H, #0.0
fcmne p0.h, p0/z, z31.h, #0.0
FCMNE P0.H, P0/Z, Z31.H, #0.0
fcmne p0.s, p0/z, z0.s, #0.0
FCMNE P0.S, P0/Z, Z0.S, #0.0
fcmne p1.s, p0/z, z0.s, #0.0
FCMNE P1.S, P0/Z, Z0.S, #0.0
fcmne p15.s, p0/z, z0.s, #0.0
FCMNE P15.S, P0/Z, Z0.S, #0.0
fcmne p0.s, p2/z, z0.s, #0.0
FCMNE P0.S, P2/Z, Z0.S, #0.0
fcmne p0.s, p7/z, z0.s, #0.0
FCMNE P0.S, P7/Z, Z0.S, #0.0
fcmne p0.s, p0/z, z3.s, #0.0
FCMNE P0.S, P0/Z, Z3.S, #0.0
fcmne p0.s, p0/z, z31.s, #0.0
FCMNE P0.S, P0/Z, Z31.S, #0.0
fcmne p0.d, p0/z, z0.d, #0.0
FCMNE P0.D, P0/Z, Z0.D, #0.0
fcmne p1.d, p0/z, z0.d, #0.0
FCMNE P1.D, P0/Z, Z0.D, #0.0
fcmne p15.d, p0/z, z0.d, #0.0
FCMNE P15.D, P0/Z, Z0.D, #0.0
fcmne p0.d, p2/z, z0.d, #0.0
FCMNE P0.D, P2/Z, Z0.D, #0.0
fcmne p0.d, p7/z, z0.d, #0.0
FCMNE P0.D, P7/Z, Z0.D, #0.0
fcmne p0.d, p0/z, z3.d, #0.0
FCMNE P0.D, P0/Z, Z3.D, #0.0
fcmne p0.d, p0/z, z31.d, #0.0
FCMNE P0.D, P0/Z, Z31.D, #0.0
fcmne p0.h, p0/z, z0.h, z0.h
FCMNE P0.H, P0/Z, Z0.H, Z0.H
fcmne p1.h, p0/z, z0.h, z0.h
FCMNE P1.H, P0/Z, Z0.H, Z0.H
fcmne p15.h, p0/z, z0.h, z0.h
FCMNE P15.H, P0/Z, Z0.H, Z0.H
fcmne p0.h, p2/z, z0.h, z0.h
FCMNE P0.H, P2/Z, Z0.H, Z0.H
fcmne p0.h, p7/z, z0.h, z0.h
FCMNE P0.H, P7/Z, Z0.H, Z0.H
fcmne p0.h, p0/z, z3.h, z0.h
FCMNE P0.H, P0/Z, Z3.H, Z0.H
fcmne p0.h, p0/z, z31.h, z0.h
FCMNE P0.H, P0/Z, Z31.H, Z0.H
fcmne p0.h, p0/z, z0.h, z4.h
FCMNE P0.H, P0/Z, Z0.H, Z4.H
fcmne p0.h, p0/z, z0.h, z31.h
FCMNE P0.H, P0/Z, Z0.H, Z31.H
fcmne p0.s, p0/z, z0.s, z0.s
FCMNE P0.S, P0/Z, Z0.S, Z0.S
fcmne p1.s, p0/z, z0.s, z0.s
FCMNE P1.S, P0/Z, Z0.S, Z0.S
fcmne p15.s, p0/z, z0.s, z0.s
FCMNE P15.S, P0/Z, Z0.S, Z0.S
fcmne p0.s, p2/z, z0.s, z0.s
FCMNE P0.S, P2/Z, Z0.S, Z0.S
fcmne p0.s, p7/z, z0.s, z0.s
FCMNE P0.S, P7/Z, Z0.S, Z0.S
fcmne p0.s, p0/z, z3.s, z0.s
FCMNE P0.S, P0/Z, Z3.S, Z0.S
fcmne p0.s, p0/z, z31.s, z0.s
FCMNE P0.S, P0/Z, Z31.S, Z0.S
fcmne p0.s, p0/z, z0.s, z4.s
FCMNE P0.S, P0/Z, Z0.S, Z4.S
fcmne p0.s, p0/z, z0.s, z31.s
FCMNE P0.S, P0/Z, Z0.S, Z31.S
fcmne p0.d, p0/z, z0.d, z0.d
FCMNE P0.D, P0/Z, Z0.D, Z0.D
fcmne p1.d, p0/z, z0.d, z0.d
FCMNE P1.D, P0/Z, Z0.D, Z0.D
fcmne p15.d, p0/z, z0.d, z0.d
FCMNE P15.D, P0/Z, Z0.D, Z0.D
fcmne p0.d, p2/z, z0.d, z0.d
FCMNE P0.D, P2/Z, Z0.D, Z0.D
fcmne p0.d, p7/z, z0.d, z0.d
FCMNE P0.D, P7/Z, Z0.D, Z0.D
fcmne p0.d, p0/z, z3.d, z0.d
FCMNE P0.D, P0/Z, Z3.D, Z0.D
fcmne p0.d, p0/z, z31.d, z0.d
FCMNE P0.D, P0/Z, Z31.D, Z0.D
fcmne p0.d, p0/z, z0.d, z4.d
FCMNE P0.D, P0/Z, Z0.D, Z4.D
fcmne p0.d, p0/z, z0.d, z31.d
FCMNE P0.D, P0/Z, Z0.D, Z31.D
fcmuo p0.h, p0/z, z0.h, z0.h
FCMUO P0.H, P0/Z, Z0.H, Z0.H
fcmuo p1.h, p0/z, z0.h, z0.h
FCMUO P1.H, P0/Z, Z0.H, Z0.H
fcmuo p15.h, p0/z, z0.h, z0.h
FCMUO P15.H, P0/Z, Z0.H, Z0.H
fcmuo p0.h, p2/z, z0.h, z0.h
FCMUO P0.H, P2/Z, Z0.H, Z0.H
fcmuo p0.h, p7/z, z0.h, z0.h
FCMUO P0.H, P7/Z, Z0.H, Z0.H
fcmuo p0.h, p0/z, z3.h, z0.h
FCMUO P0.H, P0/Z, Z3.H, Z0.H
fcmuo p0.h, p0/z, z31.h, z0.h
FCMUO P0.H, P0/Z, Z31.H, Z0.H
fcmuo p0.h, p0/z, z0.h, z4.h
FCMUO P0.H, P0/Z, Z0.H, Z4.H
fcmuo p0.h, p0/z, z0.h, z31.h
FCMUO P0.H, P0/Z, Z0.H, Z31.H
fcmuo p0.s, p0/z, z0.s, z0.s
FCMUO P0.S, P0/Z, Z0.S, Z0.S
fcmuo p1.s, p0/z, z0.s, z0.s
FCMUO P1.S, P0/Z, Z0.S, Z0.S
fcmuo p15.s, p0/z, z0.s, z0.s
FCMUO P15.S, P0/Z, Z0.S, Z0.S
fcmuo p0.s, p2/z, z0.s, z0.s
FCMUO P0.S, P2/Z, Z0.S, Z0.S
fcmuo p0.s, p7/z, z0.s, z0.s
FCMUO P0.S, P7/Z, Z0.S, Z0.S
fcmuo p0.s, p0/z, z3.s, z0.s
FCMUO P0.S, P0/Z, Z3.S, Z0.S
fcmuo p0.s, p0/z, z31.s, z0.s
FCMUO P0.S, P0/Z, Z31.S, Z0.S
fcmuo p0.s, p0/z, z0.s, z4.s
FCMUO P0.S, P0/Z, Z0.S, Z4.S
fcmuo p0.s, p0/z, z0.s, z31.s
FCMUO P0.S, P0/Z, Z0.S, Z31.S
fcmuo p0.d, p0/z, z0.d, z0.d
FCMUO P0.D, P0/Z, Z0.D, Z0.D
fcmuo p1.d, p0/z, z0.d, z0.d
FCMUO P1.D, P0/Z, Z0.D, Z0.D
fcmuo p15.d, p0/z, z0.d, z0.d
FCMUO P15.D, P0/Z, Z0.D, Z0.D
fcmuo p0.d, p2/z, z0.d, z0.d
FCMUO P0.D, P2/Z, Z0.D, Z0.D
fcmuo p0.d, p7/z, z0.d, z0.d
FCMUO P0.D, P7/Z, Z0.D, Z0.D
fcmuo p0.d, p0/z, z3.d, z0.d
FCMUO P0.D, P0/Z, Z3.D, Z0.D
fcmuo p0.d, p0/z, z31.d, z0.d
FCMUO P0.D, P0/Z, Z31.D, Z0.D
fcmuo p0.d, p0/z, z0.d, z4.d
FCMUO P0.D, P0/Z, Z0.D, Z4.D
fcmuo p0.d, p0/z, z0.d, z31.d
FCMUO P0.D, P0/Z, Z0.D, Z31.D
fcpy z0.h, p0/m, #2.0000000000
FCPY Z0.H, P0/M, #2.0000000000
fcpy z1.h, p0/m, #2.0000000000
FCPY Z1.H, P0/M, #2.0000000000
fcpy z31.h, p0/m, #2.0000000000
FCPY Z31.H, P0/M, #2.0000000000
fcpy z0.h, p2/m, #2.0000000000
FCPY Z0.H, P2/M, #2.0000000000
fcpy z0.h, p15/m, #2.0000000000
FCPY Z0.H, P15/M, #2.0000000000
fcpy z0.h, p0/m, #16.0000000000
FCPY Z0.H, P0/M, #16.0000000000
fcpy z0.h, p0/m, #0.1875000000
FCPY Z0.H, P0/M, #0.1875000000
fcpy z0.h, p0/m, #1.9375000000
FCPY Z0.H, P0/M, #1.9375000000
fcpy z0.h, p0/m, #-3.0000000000
FCPY Z0.H, P0/M, #-3.0000000000
fcpy z0.h, p0/m, #-0.1250000000
FCPY Z0.H, P0/M, #-0.1250000000
fcpy z0.h, p0/m, #-1.9375000000
FCPY Z0.H, P0/M, #-1.9375000000
fcpy z0.s, p0/m, #2.0000000000
FCPY Z0.S, P0/M, #2.0000000000
fcpy z1.s, p0/m, #2.0000000000
FCPY Z1.S, P0/M, #2.0000000000
fcpy z31.s, p0/m, #2.0000000000
FCPY Z31.S, P0/M, #2.0000000000
fcpy z0.s, p2/m, #2.0000000000
FCPY Z0.S, P2/M, #2.0000000000
fcpy z0.s, p15/m, #2.0000000000
FCPY Z0.S, P15/M, #2.0000000000
fcpy z0.s, p0/m, #16.0000000000
FCPY Z0.S, P0/M, #16.0000000000
fcpy z0.s, p0/m, #0.1875000000
FCPY Z0.S, P0/M, #0.1875000000
fcpy z0.s, p0/m, #1.9375000000
FCPY Z0.S, P0/M, #1.9375000000
fcpy z0.s, p0/m, #-3.0000000000
FCPY Z0.S, P0/M, #-3.0000000000
fcpy z0.s, p0/m, #-0.1250000000
FCPY Z0.S, P0/M, #-0.1250000000
fcpy z0.s, p0/m, #-1.9375000000
FCPY Z0.S, P0/M, #-1.9375000000
fcpy z0.d, p0/m, #2.0000000000
FCPY Z0.D, P0/M, #2.0000000000
fcpy z1.d, p0/m, #2.0000000000
FCPY Z1.D, P0/M, #2.0000000000
fcpy z31.d, p0/m, #2.0000000000
FCPY Z31.D, P0/M, #2.0000000000
fcpy z0.d, p2/m, #2.0000000000
FCPY Z0.D, P2/M, #2.0000000000
fcpy z0.d, p15/m, #2.0000000000
FCPY Z0.D, P15/M, #2.0000000000
fcpy z0.d, p0/m, #16.0000000000
FCPY Z0.D, P0/M, #16.0000000000
fcpy z0.d, p0/m, #0.1875000000
FCPY Z0.D, P0/M, #0.1875000000
fcpy z0.d, p0/m, #1.9375000000
FCPY Z0.D, P0/M, #1.9375000000
fcpy z0.d, p0/m, #-3.0000000000
FCPY Z0.D, P0/M, #-3.0000000000
fcpy z0.d, p0/m, #-0.1250000000
FCPY Z0.D, P0/M, #-0.1250000000
fcpy z0.d, p0/m, #-1.9375000000
FCPY Z0.D, P0/M, #-1.9375000000
fcvt z0.h, p0/m, z0.s
FCVT Z0.H, P0/M, Z0.S
fcvt z1.h, p0/m, z0.s
FCVT Z1.H, P0/M, Z0.S
fcvt z31.h, p0/m, z0.s
FCVT Z31.H, P0/M, Z0.S
fcvt z0.h, p2/m, z0.s
FCVT Z0.H, P2/M, Z0.S
fcvt z0.h, p7/m, z0.s
FCVT Z0.H, P7/M, Z0.S
fcvt z0.h, p0/m, z3.s
FCVT Z0.H, P0/M, Z3.S
fcvt z0.h, p0/m, z31.s
FCVT Z0.H, P0/M, Z31.S
fcvt z0.s, p0/m, z0.h
FCVT Z0.S, P0/M, Z0.H
fcvt z1.s, p0/m, z0.h
FCVT Z1.S, P0/M, Z0.H
fcvt z31.s, p0/m, z0.h
FCVT Z31.S, P0/M, Z0.H
fcvt z0.s, p2/m, z0.h
FCVT Z0.S, P2/M, Z0.H
fcvt z0.s, p7/m, z0.h
FCVT Z0.S, P7/M, Z0.H
fcvt z0.s, p0/m, z3.h
FCVT Z0.S, P0/M, Z3.H
fcvt z0.s, p0/m, z31.h
FCVT Z0.S, P0/M, Z31.H
fcvt z0.h, p0/m, z0.d
FCVT Z0.H, P0/M, Z0.D
fcvt z1.h, p0/m, z0.d
FCVT Z1.H, P0/M, Z0.D
fcvt z31.h, p0/m, z0.d
FCVT Z31.H, P0/M, Z0.D
fcvt z0.h, p2/m, z0.d
FCVT Z0.H, P2/M, Z0.D
fcvt z0.h, p7/m, z0.d
FCVT Z0.H, P7/M, Z0.D
fcvt z0.h, p0/m, z3.d
FCVT Z0.H, P0/M, Z3.D
fcvt z0.h, p0/m, z31.d
FCVT Z0.H, P0/M, Z31.D
fcvt z0.d, p0/m, z0.h
FCVT Z0.D, P0/M, Z0.H
fcvt z1.d, p0/m, z0.h
FCVT Z1.D, P0/M, Z0.H
fcvt z31.d, p0/m, z0.h
FCVT Z31.D, P0/M, Z0.H
fcvt z0.d, p2/m, z0.h
FCVT Z0.D, P2/M, Z0.H
fcvt z0.d, p7/m, z0.h
FCVT Z0.D, P7/M, Z0.H
fcvt z0.d, p0/m, z3.h
FCVT Z0.D, P0/M, Z3.H
fcvt z0.d, p0/m, z31.h
FCVT Z0.D, P0/M, Z31.H
fcvt z0.s, p0/m, z0.d
FCVT Z0.S, P0/M, Z0.D
fcvt z1.s, p0/m, z0.d
FCVT Z1.S, P0/M, Z0.D
fcvt z31.s, p0/m, z0.d
FCVT Z31.S, P0/M, Z0.D
fcvt z0.s, p2/m, z0.d
FCVT Z0.S, P2/M, Z0.D
fcvt z0.s, p7/m, z0.d
FCVT Z0.S, P7/M, Z0.D
fcvt z0.s, p0/m, z3.d
FCVT Z0.S, P0/M, Z3.D
fcvt z0.s, p0/m, z31.d
FCVT Z0.S, P0/M, Z31.D
fcvt z0.d, p0/m, z0.s
FCVT Z0.D, P0/M, Z0.S
fcvt z1.d, p0/m, z0.s
FCVT Z1.D, P0/M, Z0.S
fcvt z31.d, p0/m, z0.s
FCVT Z31.D, P0/M, Z0.S
fcvt z0.d, p2/m, z0.s
FCVT Z0.D, P2/M, Z0.S
fcvt z0.d, p7/m, z0.s
FCVT Z0.D, P7/M, Z0.S
fcvt z0.d, p0/m, z3.s
FCVT Z0.D, P0/M, Z3.S
fcvt z0.d, p0/m, z31.s
FCVT Z0.D, P0/M, Z31.S
fcvtzs z0.h, p0/m, z0.h
FCVTZS Z0.H, P0/M, Z0.H
fcvtzs z1.h, p0/m, z0.h
FCVTZS Z1.H, P0/M, Z0.H
fcvtzs z31.h, p0/m, z0.h
FCVTZS Z31.H, P0/M, Z0.H
fcvtzs z0.h, p2/m, z0.h
FCVTZS Z0.H, P2/M, Z0.H
fcvtzs z0.h, p7/m, z0.h
FCVTZS Z0.H, P7/M, Z0.H
fcvtzs z0.h, p0/m, z3.h
FCVTZS Z0.H, P0/M, Z3.H
fcvtzs z0.h, p0/m, z31.h
FCVTZS Z0.H, P0/M, Z31.H
fcvtzs z0.s, p0/m, z0.h
FCVTZS Z0.S, P0/M, Z0.H
fcvtzs z1.s, p0/m, z0.h
FCVTZS Z1.S, P0/M, Z0.H
fcvtzs z31.s, p0/m, z0.h
FCVTZS Z31.S, P0/M, Z0.H
fcvtzs z0.s, p2/m, z0.h
FCVTZS Z0.S, P2/M, Z0.H
fcvtzs z0.s, p7/m, z0.h
FCVTZS Z0.S, P7/M, Z0.H
fcvtzs z0.s, p0/m, z3.h
FCVTZS Z0.S, P0/M, Z3.H
fcvtzs z0.s, p0/m, z31.h
FCVTZS Z0.S, P0/M, Z31.H
fcvtzs z0.d, p0/m, z0.h
FCVTZS Z0.D, P0/M, Z0.H
fcvtzs z1.d, p0/m, z0.h
FCVTZS Z1.D, P0/M, Z0.H
fcvtzs z31.d, p0/m, z0.h
FCVTZS Z31.D, P0/M, Z0.H
fcvtzs z0.d, p2/m, z0.h
FCVTZS Z0.D, P2/M, Z0.H
fcvtzs z0.d, p7/m, z0.h
FCVTZS Z0.D, P7/M, Z0.H
fcvtzs z0.d, p0/m, z3.h
FCVTZS Z0.D, P0/M, Z3.H
fcvtzs z0.d, p0/m, z31.h
FCVTZS Z0.D, P0/M, Z31.H
fcvtzs z0.s, p0/m, z0.s
FCVTZS Z0.S, P0/M, Z0.S
fcvtzs z1.s, p0/m, z0.s
FCVTZS Z1.S, P0/M, Z0.S
fcvtzs z31.s, p0/m, z0.s
FCVTZS Z31.S, P0/M, Z0.S
fcvtzs z0.s, p2/m, z0.s
FCVTZS Z0.S, P2/M, Z0.S
fcvtzs z0.s, p7/m, z0.s
FCVTZS Z0.S, P7/M, Z0.S
fcvtzs z0.s, p0/m, z3.s
FCVTZS Z0.S, P0/M, Z3.S
fcvtzs z0.s, p0/m, z31.s
FCVTZS Z0.S, P0/M, Z31.S
fcvtzs z0.s, p0/m, z0.d
FCVTZS Z0.S, P0/M, Z0.D
fcvtzs z1.s, p0/m, z0.d
FCVTZS Z1.S, P0/M, Z0.D
fcvtzs z31.s, p0/m, z0.d
FCVTZS Z31.S, P0/M, Z0.D
fcvtzs z0.s, p2/m, z0.d
FCVTZS Z0.S, P2/M, Z0.D
fcvtzs z0.s, p7/m, z0.d
FCVTZS Z0.S, P7/M, Z0.D
fcvtzs z0.s, p0/m, z3.d
FCVTZS Z0.S, P0/M, Z3.D
fcvtzs z0.s, p0/m, z31.d
FCVTZS Z0.S, P0/M, Z31.D
fcvtzs z0.d, p0/m, z0.s
FCVTZS Z0.D, P0/M, Z0.S
fcvtzs z1.d, p0/m, z0.s
FCVTZS Z1.D, P0/M, Z0.S
fcvtzs z31.d, p0/m, z0.s
FCVTZS Z31.D, P0/M, Z0.S
fcvtzs z0.d, p2/m, z0.s
FCVTZS Z0.D, P2/M, Z0.S
fcvtzs z0.d, p7/m, z0.s
FCVTZS Z0.D, P7/M, Z0.S
fcvtzs z0.d, p0/m, z3.s
FCVTZS Z0.D, P0/M, Z3.S
fcvtzs z0.d, p0/m, z31.s
FCVTZS Z0.D, P0/M, Z31.S
fcvtzs z0.d, p0/m, z0.d
FCVTZS Z0.D, P0/M, Z0.D
fcvtzs z1.d, p0/m, z0.d
FCVTZS Z1.D, P0/M, Z0.D
fcvtzs z31.d, p0/m, z0.d
FCVTZS Z31.D, P0/M, Z0.D
fcvtzs z0.d, p2/m, z0.d
FCVTZS Z0.D, P2/M, Z0.D
fcvtzs z0.d, p7/m, z0.d
FCVTZS Z0.D, P7/M, Z0.D
fcvtzs z0.d, p0/m, z3.d
FCVTZS Z0.D, P0/M, Z3.D
fcvtzs z0.d, p0/m, z31.d
FCVTZS Z0.D, P0/M, Z31.D
fcvtzu z0.h, p0/m, z0.h
FCVTZU Z0.H, P0/M, Z0.H
fcvtzu z1.h, p0/m, z0.h
FCVTZU Z1.H, P0/M, Z0.H
fcvtzu z31.h, p0/m, z0.h
FCVTZU Z31.H, P0/M, Z0.H
fcvtzu z0.h, p2/m, z0.h
FCVTZU Z0.H, P2/M, Z0.H
fcvtzu z0.h, p7/m, z0.h
FCVTZU Z0.H, P7/M, Z0.H
fcvtzu z0.h, p0/m, z3.h
FCVTZU Z0.H, P0/M, Z3.H
fcvtzu z0.h, p0/m, z31.h
FCVTZU Z0.H, P0/M, Z31.H
fcvtzu z0.s, p0/m, z0.h
FCVTZU Z0.S, P0/M, Z0.H
fcvtzu z1.s, p0/m, z0.h
FCVTZU Z1.S, P0/M, Z0.H
fcvtzu z31.s, p0/m, z0.h
FCVTZU Z31.S, P0/M, Z0.H
fcvtzu z0.s, p2/m, z0.h
FCVTZU Z0.S, P2/M, Z0.H
fcvtzu z0.s, p7/m, z0.h
FCVTZU Z0.S, P7/M, Z0.H
fcvtzu z0.s, p0/m, z3.h
FCVTZU Z0.S, P0/M, Z3.H
fcvtzu z0.s, p0/m, z31.h
FCVTZU Z0.S, P0/M, Z31.H
fcvtzu z0.d, p0/m, z0.h
FCVTZU Z0.D, P0/M, Z0.H
fcvtzu z1.d, p0/m, z0.h
FCVTZU Z1.D, P0/M, Z0.H
fcvtzu z31.d, p0/m, z0.h
FCVTZU Z31.D, P0/M, Z0.H
fcvtzu z0.d, p2/m, z0.h
FCVTZU Z0.D, P2/M, Z0.H
fcvtzu z0.d, p7/m, z0.h
FCVTZU Z0.D, P7/M, Z0.H
fcvtzu z0.d, p0/m, z3.h
FCVTZU Z0.D, P0/M, Z3.H
fcvtzu z0.d, p0/m, z31.h
FCVTZU Z0.D, P0/M, Z31.H
fcvtzu z0.s, p0/m, z0.s
FCVTZU Z0.S, P0/M, Z0.S
fcvtzu z1.s, p0/m, z0.s
FCVTZU Z1.S, P0/M, Z0.S
fcvtzu z31.s, p0/m, z0.s
FCVTZU Z31.S, P0/M, Z0.S
fcvtzu z0.s, p2/m, z0.s
FCVTZU Z0.S, P2/M, Z0.S
fcvtzu z0.s, p7/m, z0.s
FCVTZU Z0.S, P7/M, Z0.S
fcvtzu z0.s, p0/m, z3.s
FCVTZU Z0.S, P0/M, Z3.S
fcvtzu z0.s, p0/m, z31.s
FCVTZU Z0.S, P0/M, Z31.S
fcvtzu z0.s, p0/m, z0.d
FCVTZU Z0.S, P0/M, Z0.D
fcvtzu z1.s, p0/m, z0.d
FCVTZU Z1.S, P0/M, Z0.D
fcvtzu z31.s, p0/m, z0.d
FCVTZU Z31.S, P0/M, Z0.D
fcvtzu z0.s, p2/m, z0.d
FCVTZU Z0.S, P2/M, Z0.D
fcvtzu z0.s, p7/m, z0.d
FCVTZU Z0.S, P7/M, Z0.D
fcvtzu z0.s, p0/m, z3.d
FCVTZU Z0.S, P0/M, Z3.D
fcvtzu z0.s, p0/m, z31.d
FCVTZU Z0.S, P0/M, Z31.D
fcvtzu z0.d, p0/m, z0.s
FCVTZU Z0.D, P0/M, Z0.S
fcvtzu z1.d, p0/m, z0.s
FCVTZU Z1.D, P0/M, Z0.S
fcvtzu z31.d, p0/m, z0.s
FCVTZU Z31.D, P0/M, Z0.S
fcvtzu z0.d, p2/m, z0.s
FCVTZU Z0.D, P2/M, Z0.S
fcvtzu z0.d, p7/m, z0.s
FCVTZU Z0.D, P7/M, Z0.S
fcvtzu z0.d, p0/m, z3.s
FCVTZU Z0.D, P0/M, Z3.S
fcvtzu z0.d, p0/m, z31.s
FCVTZU Z0.D, P0/M, Z31.S
fcvtzu z0.d, p0/m, z0.d
FCVTZU Z0.D, P0/M, Z0.D
fcvtzu z1.d, p0/m, z0.d
FCVTZU Z1.D, P0/M, Z0.D
fcvtzu z31.d, p0/m, z0.d
FCVTZU Z31.D, P0/M, Z0.D
fcvtzu z0.d, p2/m, z0.d
FCVTZU Z0.D, P2/M, Z0.D
fcvtzu z0.d, p7/m, z0.d
FCVTZU Z0.D, P7/M, Z0.D
fcvtzu z0.d, p0/m, z3.d
FCVTZU Z0.D, P0/M, Z3.D
fcvtzu z0.d, p0/m, z31.d
FCVTZU Z0.D, P0/M, Z31.D
fdiv z0.h, p0/m, z0.h, z0.h
FDIV Z0.H, P0/M, Z0.H, Z0.H
fdiv z1.h, p0/m, z1.h, z0.h
FDIV Z1.H, P0/M, Z1.H, Z0.H
fdiv z31.h, p0/m, z31.h, z0.h
FDIV Z31.H, P0/M, Z31.H, Z0.H
fdiv z0.h, p2/m, z0.h, z0.h
FDIV Z0.H, P2/M, Z0.H, Z0.H
fdiv z0.h, p7/m, z0.h, z0.h
FDIV Z0.H, P7/M, Z0.H, Z0.H
fdiv z3.h, p0/m, z3.h, z0.h
FDIV Z3.H, P0/M, Z3.H, Z0.H
fdiv z0.h, p0/m, z0.h, z4.h
FDIV Z0.H, P0/M, Z0.H, Z4.H
fdiv z0.h, p0/m, z0.h, z31.h
FDIV Z0.H, P0/M, Z0.H, Z31.H
fdiv z0.s, p0/m, z0.s, z0.s
FDIV Z0.S, P0/M, Z0.S, Z0.S
fdiv z1.s, p0/m, z1.s, z0.s
FDIV Z1.S, P0/M, Z1.S, Z0.S
fdiv z31.s, p0/m, z31.s, z0.s
FDIV Z31.S, P0/M, Z31.S, Z0.S
fdiv z0.s, p2/m, z0.s, z0.s
FDIV Z0.S, P2/M, Z0.S, Z0.S
fdiv z0.s, p7/m, z0.s, z0.s
FDIV Z0.S, P7/M, Z0.S, Z0.S
fdiv z3.s, p0/m, z3.s, z0.s
FDIV Z3.S, P0/M, Z3.S, Z0.S
fdiv z0.s, p0/m, z0.s, z4.s
FDIV Z0.S, P0/M, Z0.S, Z4.S
fdiv z0.s, p0/m, z0.s, z31.s
FDIV Z0.S, P0/M, Z0.S, Z31.S
fdiv z0.d, p0/m, z0.d, z0.d
FDIV Z0.D, P0/M, Z0.D, Z0.D
fdiv z1.d, p0/m, z1.d, z0.d
FDIV Z1.D, P0/M, Z1.D, Z0.D
fdiv z31.d, p0/m, z31.d, z0.d
FDIV Z31.D, P0/M, Z31.D, Z0.D
fdiv z0.d, p2/m, z0.d, z0.d
FDIV Z0.D, P2/M, Z0.D, Z0.D
fdiv z0.d, p7/m, z0.d, z0.d
FDIV Z0.D, P7/M, Z0.D, Z0.D
fdiv z3.d, p0/m, z3.d, z0.d
FDIV Z3.D, P0/M, Z3.D, Z0.D
fdiv z0.d, p0/m, z0.d, z4.d
FDIV Z0.D, P0/M, Z0.D, Z4.D
fdiv z0.d, p0/m, z0.d, z31.d
FDIV Z0.D, P0/M, Z0.D, Z31.D
fdivr z0.h, p0/m, z0.h, z0.h
FDIVR Z0.H, P0/M, Z0.H, Z0.H
fdivr z1.h, p0/m, z1.h, z0.h
FDIVR Z1.H, P0/M, Z1.H, Z0.H
fdivr z31.h, p0/m, z31.h, z0.h
FDIVR Z31.H, P0/M, Z31.H, Z0.H
fdivr z0.h, p2/m, z0.h, z0.h
FDIVR Z0.H, P2/M, Z0.H, Z0.H
fdivr z0.h, p7/m, z0.h, z0.h
FDIVR Z0.H, P7/M, Z0.H, Z0.H
fdivr z3.h, p0/m, z3.h, z0.h
FDIVR Z3.H, P0/M, Z3.H, Z0.H
fdivr z0.h, p0/m, z0.h, z4.h
FDIVR Z0.H, P0/M, Z0.H, Z4.H
fdivr z0.h, p0/m, z0.h, z31.h
FDIVR Z0.H, P0/M, Z0.H, Z31.H
fdivr z0.s, p0/m, z0.s, z0.s
FDIVR Z0.S, P0/M, Z0.S, Z0.S
fdivr z1.s, p0/m, z1.s, z0.s
FDIVR Z1.S, P0/M, Z1.S, Z0.S
fdivr z31.s, p0/m, z31.s, z0.s
FDIVR Z31.S, P0/M, Z31.S, Z0.S
fdivr z0.s, p2/m, z0.s, z0.s
FDIVR Z0.S, P2/M, Z0.S, Z0.S
fdivr z0.s, p7/m, z0.s, z0.s
FDIVR Z0.S, P7/M, Z0.S, Z0.S
fdivr z3.s, p0/m, z3.s, z0.s
FDIVR Z3.S, P0/M, Z3.S, Z0.S
fdivr z0.s, p0/m, z0.s, z4.s
FDIVR Z0.S, P0/M, Z0.S, Z4.S
fdivr z0.s, p0/m, z0.s, z31.s
FDIVR Z0.S, P0/M, Z0.S, Z31.S
fdivr z0.d, p0/m, z0.d, z0.d
FDIVR Z0.D, P0/M, Z0.D, Z0.D
fdivr z1.d, p0/m, z1.d, z0.d
FDIVR Z1.D, P0/M, Z1.D, Z0.D
fdivr z31.d, p0/m, z31.d, z0.d
FDIVR Z31.D, P0/M, Z31.D, Z0.D
fdivr z0.d, p2/m, z0.d, z0.d
FDIVR Z0.D, P2/M, Z0.D, Z0.D
fdivr z0.d, p7/m, z0.d, z0.d
FDIVR Z0.D, P7/M, Z0.D, Z0.D
fdivr z3.d, p0/m, z3.d, z0.d
FDIVR Z3.D, P0/M, Z3.D, Z0.D
fdivr z0.d, p0/m, z0.d, z4.d
FDIVR Z0.D, P0/M, Z0.D, Z4.D
fdivr z0.d, p0/m, z0.d, z31.d
FDIVR Z0.D, P0/M, Z0.D, Z31.D
fdup z0.h, #2.0000000000
FDUP Z0.H, #2.0000000000
fdup z1.h, #2.0000000000
FDUP Z1.H, #2.0000000000
fdup z31.h, #2.0000000000
FDUP Z31.H, #2.0000000000
fdup z0.h, #16.0000000000
FDUP Z0.H, #16.0000000000
fdup z0.h, #0.1875000000
FDUP Z0.H, #0.1875000000
fdup z0.h, #1.9375000000
FDUP Z0.H, #1.9375000000
fdup z0.h, #-3.0000000000
FDUP Z0.H, #-3.0000000000
fdup z0.h, #-0.1250000000
FDUP Z0.H, #-0.1250000000
fdup z0.h, #-1.9375000000
FDUP Z0.H, #-1.9375000000
fdup z0.s, #2.0000000000
FDUP Z0.S, #2.0000000000
fdup z1.s, #2.0000000000
FDUP Z1.S, #2.0000000000
fdup z31.s, #2.0000000000
FDUP Z31.S, #2.0000000000
fdup z0.s, #16.0000000000
FDUP Z0.S, #16.0000000000
fdup z0.s, #0.1875000000
FDUP Z0.S, #0.1875000000
fdup z0.s, #1.9375000000
FDUP Z0.S, #1.9375000000
fdup z0.s, #-3.0000000000
FDUP Z0.S, #-3.0000000000
fdup z0.s, #-0.1250000000
FDUP Z0.S, #-0.1250000000
fdup z0.s, #-1.9375000000
FDUP Z0.S, #-1.9375000000
fdup z0.d, #2.0000000000
FDUP Z0.D, #2.0000000000
fdup z1.d, #2.0000000000
FDUP Z1.D, #2.0000000000
fdup z31.d, #2.0000000000
FDUP Z31.D, #2.0000000000
fdup z0.d, #16.0000000000
FDUP Z0.D, #16.0000000000
fdup z0.d, #0.1875000000
FDUP Z0.D, #0.1875000000
fdup z0.d, #1.9375000000
FDUP Z0.D, #1.9375000000
fdup z0.d, #-3.0000000000
FDUP Z0.D, #-3.0000000000
fdup z0.d, #-0.1250000000
FDUP Z0.D, #-0.1250000000
fdup z0.d, #-1.9375000000
FDUP Z0.D, #-1.9375000000
fexpa z0.h, z0.h
FEXPA Z0.H, Z0.H
fexpa z1.h, z0.h
FEXPA Z1.H, Z0.H
fexpa z31.h, z0.h
FEXPA Z31.H, Z0.H
fexpa z0.h, z2.h
FEXPA Z0.H, Z2.H
fexpa z0.h, z31.h
FEXPA Z0.H, Z31.H
fexpa z0.s, z0.s
FEXPA Z0.S, Z0.S
fexpa z1.s, z0.s
FEXPA Z1.S, Z0.S
fexpa z31.s, z0.s
FEXPA Z31.S, Z0.S
fexpa z0.s, z2.s
FEXPA Z0.S, Z2.S
fexpa z0.s, z31.s
FEXPA Z0.S, Z31.S
fexpa z0.d, z0.d
FEXPA Z0.D, Z0.D
fexpa z1.d, z0.d
FEXPA Z1.D, Z0.D
fexpa z31.d, z0.d
FEXPA Z31.D, Z0.D
fexpa z0.d, z2.d
FEXPA Z0.D, Z2.D
fexpa z0.d, z31.d
FEXPA Z0.D, Z31.D
fmad z0.h, p0/m, z0.h, z0.h
FMAD Z0.H, P0/M, Z0.H, Z0.H
fmad z1.h, p0/m, z0.h, z0.h
FMAD Z1.H, P0/M, Z0.H, Z0.H
fmad z31.h, p0/m, z0.h, z0.h
FMAD Z31.H, P0/M, Z0.H, Z0.H
fmad z0.h, p2/m, z0.h, z0.h
FMAD Z0.H, P2/M, Z0.H, Z0.H
fmad z0.h, p7/m, z0.h, z0.h
FMAD Z0.H, P7/M, Z0.H, Z0.H
fmad z0.h, p0/m, z3.h, z0.h
FMAD Z0.H, P0/M, Z3.H, Z0.H
fmad z0.h, p0/m, z31.h, z0.h
FMAD Z0.H, P0/M, Z31.H, Z0.H
fmad z0.h, p0/m, z0.h, z4.h
FMAD Z0.H, P0/M, Z0.H, Z4.H
fmad z0.h, p0/m, z0.h, z31.h
FMAD Z0.H, P0/M, Z0.H, Z31.H
fmad z0.s, p0/m, z0.s, z0.s
FMAD Z0.S, P0/M, Z0.S, Z0.S
fmad z1.s, p0/m, z0.s, z0.s
FMAD Z1.S, P0/M, Z0.S, Z0.S
fmad z31.s, p0/m, z0.s, z0.s
FMAD Z31.S, P0/M, Z0.S, Z0.S
fmad z0.s, p2/m, z0.s, z0.s
FMAD Z0.S, P2/M, Z0.S, Z0.S
fmad z0.s, p7/m, z0.s, z0.s
FMAD Z0.S, P7/M, Z0.S, Z0.S
fmad z0.s, p0/m, z3.s, z0.s
FMAD Z0.S, P0/M, Z3.S, Z0.S
fmad z0.s, p0/m, z31.s, z0.s
FMAD Z0.S, P0/M, Z31.S, Z0.S
fmad z0.s, p0/m, z0.s, z4.s
FMAD Z0.S, P0/M, Z0.S, Z4.S
fmad z0.s, p0/m, z0.s, z31.s
FMAD Z0.S, P0/M, Z0.S, Z31.S
fmad z0.d, p0/m, z0.d, z0.d
FMAD Z0.D, P0/M, Z0.D, Z0.D
fmad z1.d, p0/m, z0.d, z0.d
FMAD Z1.D, P0/M, Z0.D, Z0.D
fmad z31.d, p0/m, z0.d, z0.d
FMAD Z31.D, P0/M, Z0.D, Z0.D
fmad z0.d, p2/m, z0.d, z0.d
FMAD Z0.D, P2/M, Z0.D, Z0.D
fmad z0.d, p7/m, z0.d, z0.d
FMAD Z0.D, P7/M, Z0.D, Z0.D
fmad z0.d, p0/m, z3.d, z0.d
FMAD Z0.D, P0/M, Z3.D, Z0.D
fmad z0.d, p0/m, z31.d, z0.d
FMAD Z0.D, P0/M, Z31.D, Z0.D
fmad z0.d, p0/m, z0.d, z4.d
FMAD Z0.D, P0/M, Z0.D, Z4.D
fmad z0.d, p0/m, z0.d, z31.d
FMAD Z0.D, P0/M, Z0.D, Z31.D
fmax z0.h, p0/m, z0.h, z0.h
FMAX Z0.H, P0/M, Z0.H, Z0.H
fmax z1.h, p0/m, z1.h, z0.h
FMAX Z1.H, P0/M, Z1.H, Z0.H
fmax z31.h, p0/m, z31.h, z0.h
FMAX Z31.H, P0/M, Z31.H, Z0.H
fmax z0.h, p2/m, z0.h, z0.h
FMAX Z0.H, P2/M, Z0.H, Z0.H
fmax z0.h, p7/m, z0.h, z0.h
FMAX Z0.H, P7/M, Z0.H, Z0.H
fmax z3.h, p0/m, z3.h, z0.h
FMAX Z3.H, P0/M, Z3.H, Z0.H
fmax z0.h, p0/m, z0.h, z4.h
FMAX Z0.H, P0/M, Z0.H, Z4.H
fmax z0.h, p0/m, z0.h, z31.h
FMAX Z0.H, P0/M, Z0.H, Z31.H
fmax z0.s, p0/m, z0.s, z0.s
FMAX Z0.S, P0/M, Z0.S, Z0.S
fmax z1.s, p0/m, z1.s, z0.s
FMAX Z1.S, P0/M, Z1.S, Z0.S
fmax z31.s, p0/m, z31.s, z0.s
FMAX Z31.S, P0/M, Z31.S, Z0.S
fmax z0.s, p2/m, z0.s, z0.s
FMAX Z0.S, P2/M, Z0.S, Z0.S
fmax z0.s, p7/m, z0.s, z0.s
FMAX Z0.S, P7/M, Z0.S, Z0.S
fmax z3.s, p0/m, z3.s, z0.s
FMAX Z3.S, P0/M, Z3.S, Z0.S
fmax z0.s, p0/m, z0.s, z4.s
FMAX Z0.S, P0/M, Z0.S, Z4.S
fmax z0.s, p0/m, z0.s, z31.s
FMAX Z0.S, P0/M, Z0.S, Z31.S
fmax z0.d, p0/m, z0.d, z0.d
FMAX Z0.D, P0/M, Z0.D, Z0.D
fmax z1.d, p0/m, z1.d, z0.d
FMAX Z1.D, P0/M, Z1.D, Z0.D
fmax z31.d, p0/m, z31.d, z0.d
FMAX Z31.D, P0/M, Z31.D, Z0.D
fmax z0.d, p2/m, z0.d, z0.d
FMAX Z0.D, P2/M, Z0.D, Z0.D
fmax z0.d, p7/m, z0.d, z0.d
FMAX Z0.D, P7/M, Z0.D, Z0.D
fmax z3.d, p0/m, z3.d, z0.d
FMAX Z3.D, P0/M, Z3.D, Z0.D
fmax z0.d, p0/m, z0.d, z4.d
FMAX Z0.D, P0/M, Z0.D, Z4.D
fmax z0.d, p0/m, z0.d, z31.d
FMAX Z0.D, P0/M, Z0.D, Z31.D
fmax z0.h, p0/m, z0.h, #0.0
FMAX Z0.H, P0/M, Z0.H, #0.0
fmax z0.h, p0/m, z0.h, #0.00000
fmax z0.h, p0/m, z0.h, #0.0000000000e+00
fmax z1.h, p0/m, z1.h, #0.0
FMAX Z1.H, P0/M, Z1.H, #0.0
fmax z1.h, p0/m, z1.h, #0.00000
fmax z1.h, p0/m, z1.h, #0.0000000000e+00
fmax z31.h, p0/m, z31.h, #0.0
FMAX Z31.H, P0/M, Z31.H, #0.0
fmax z31.h, p0/m, z31.h, #0.00000
fmax z31.h, p0/m, z31.h, #0.0000000000e+00
fmax z0.h, p2/m, z0.h, #0.0
FMAX Z0.H, P2/M, Z0.H, #0.0
fmax z0.h, p2/m, z0.h, #0.00000
fmax z0.h, p2/m, z0.h, #0.0000000000e+00
fmax z0.h, p7/m, z0.h, #0.0
FMAX Z0.H, P7/M, Z0.H, #0.0
fmax z0.h, p7/m, z0.h, #0.00000
fmax z0.h, p7/m, z0.h, #0.0000000000e+00
fmax z3.h, p0/m, z3.h, #0.0
FMAX Z3.H, P0/M, Z3.H, #0.0
fmax z3.h, p0/m, z3.h, #0.00000
fmax z3.h, p0/m, z3.h, #0.0000000000e+00
fmax z0.h, p0/m, z0.h, #1.0
FMAX Z0.H, P0/M, Z0.H, #1.0
fmax z0.h, p0/m, z0.h, #1.00000
fmax z0.h, p0/m, z0.h, #1.0000000000e+00
fmax z0.s, p0/m, z0.s, #0.0
FMAX Z0.S, P0/M, Z0.S, #0.0
fmax z0.s, p0/m, z0.s, #0.00000
fmax z0.s, p0/m, z0.s, #0.0000000000e+00
fmax z1.s, p0/m, z1.s, #0.0
FMAX Z1.S, P0/M, Z1.S, #0.0
fmax z1.s, p0/m, z1.s, #0.00000
fmax z1.s, p0/m, z1.s, #0.0000000000e+00
fmax z31.s, p0/m, z31.s, #0.0
FMAX Z31.S, P0/M, Z31.S, #0.0
fmax z31.s, p0/m, z31.s, #0.00000
fmax z31.s, p0/m, z31.s, #0.0000000000e+00
fmax z0.s, p2/m, z0.s, #0.0
FMAX Z0.S, P2/M, Z0.S, #0.0
fmax z0.s, p2/m, z0.s, #0.00000
fmax z0.s, p2/m, z0.s, #0.0000000000e+00
fmax z0.s, p7/m, z0.s, #0.0
FMAX Z0.S, P7/M, Z0.S, #0.0
fmax z0.s, p7/m, z0.s, #0.00000
fmax z0.s, p7/m, z0.s, #0.0000000000e+00
fmax z3.s, p0/m, z3.s, #0.0
FMAX Z3.S, P0/M, Z3.S, #0.0
fmax z3.s, p0/m, z3.s, #0.00000
fmax z3.s, p0/m, z3.s, #0.0000000000e+00
fmax z0.s, p0/m, z0.s, #1.0
FMAX Z0.S, P0/M, Z0.S, #1.0
fmax z0.s, p0/m, z0.s, #1.00000
fmax z0.s, p0/m, z0.s, #1.0000000000e+00
fmax z0.d, p0/m, z0.d, #0.0
FMAX Z0.D, P0/M, Z0.D, #0.0
fmax z0.d, p0/m, z0.d, #0.00000
fmax z0.d, p0/m, z0.d, #0.0000000000e+00
fmax z1.d, p0/m, z1.d, #0.0
FMAX Z1.D, P0/M, Z1.D, #0.0
fmax z1.d, p0/m, z1.d, #0.00000
fmax z1.d, p0/m, z1.d, #0.0000000000e+00
fmax z31.d, p0/m, z31.d, #0.0
FMAX Z31.D, P0/M, Z31.D, #0.0
fmax z31.d, p0/m, z31.d, #0.00000
fmax z31.d, p0/m, z31.d, #0.0000000000e+00
fmax z0.d, p2/m, z0.d, #0.0
FMAX Z0.D, P2/M, Z0.D, #0.0
fmax z0.d, p2/m, z0.d, #0.00000
fmax z0.d, p2/m, z0.d, #0.0000000000e+00
fmax z0.d, p7/m, z0.d, #0.0
FMAX Z0.D, P7/M, Z0.D, #0.0
fmax z0.d, p7/m, z0.d, #0.00000
fmax z0.d, p7/m, z0.d, #0.0000000000e+00
fmax z3.d, p0/m, z3.d, #0.0
FMAX Z3.D, P0/M, Z3.D, #0.0
fmax z3.d, p0/m, z3.d, #0.00000
fmax z3.d, p0/m, z3.d, #0.0000000000e+00
fmax z0.d, p0/m, z0.d, #1.0
FMAX Z0.D, P0/M, Z0.D, #1.0
fmax z0.d, p0/m, z0.d, #1.00000
fmax z0.d, p0/m, z0.d, #1.0000000000e+00
fmaxnm z0.h, p0/m, z0.h, z0.h
FMAXNM Z0.H, P0/M, Z0.H, Z0.H
fmaxnm z1.h, p0/m, z1.h, z0.h
FMAXNM Z1.H, P0/M, Z1.H, Z0.H
fmaxnm z31.h, p0/m, z31.h, z0.h
FMAXNM Z31.H, P0/M, Z31.H, Z0.H
fmaxnm z0.h, p2/m, z0.h, z0.h
FMAXNM Z0.H, P2/M, Z0.H, Z0.H
fmaxnm z0.h, p7/m, z0.h, z0.h
FMAXNM Z0.H, P7/M, Z0.H, Z0.H
fmaxnm z3.h, p0/m, z3.h, z0.h
FMAXNM Z3.H, P0/M, Z3.H, Z0.H
fmaxnm z0.h, p0/m, z0.h, z4.h
FMAXNM Z0.H, P0/M, Z0.H, Z4.H
fmaxnm z0.h, p0/m, z0.h, z31.h
FMAXNM Z0.H, P0/M, Z0.H, Z31.H
fmaxnm z0.s, p0/m, z0.s, z0.s
FMAXNM Z0.S, P0/M, Z0.S, Z0.S
fmaxnm z1.s, p0/m, z1.s, z0.s
FMAXNM Z1.S, P0/M, Z1.S, Z0.S
fmaxnm z31.s, p0/m, z31.s, z0.s
FMAXNM Z31.S, P0/M, Z31.S, Z0.S
fmaxnm z0.s, p2/m, z0.s, z0.s
FMAXNM Z0.S, P2/M, Z0.S, Z0.S
fmaxnm z0.s, p7/m, z0.s, z0.s
FMAXNM Z0.S, P7/M, Z0.S, Z0.S
fmaxnm z3.s, p0/m, z3.s, z0.s
FMAXNM Z3.S, P0/M, Z3.S, Z0.S
fmaxnm z0.s, p0/m, z0.s, z4.s
FMAXNM Z0.S, P0/M, Z0.S, Z4.S
fmaxnm z0.s, p0/m, z0.s, z31.s
FMAXNM Z0.S, P0/M, Z0.S, Z31.S
fmaxnm z0.d, p0/m, z0.d, z0.d
FMAXNM Z0.D, P0/M, Z0.D, Z0.D
fmaxnm z1.d, p0/m, z1.d, z0.d
FMAXNM Z1.D, P0/M, Z1.D, Z0.D
fmaxnm z31.d, p0/m, z31.d, z0.d
FMAXNM Z31.D, P0/M, Z31.D, Z0.D
fmaxnm z0.d, p2/m, z0.d, z0.d
FMAXNM Z0.D, P2/M, Z0.D, Z0.D
fmaxnm z0.d, p7/m, z0.d, z0.d
FMAXNM Z0.D, P7/M, Z0.D, Z0.D
fmaxnm z3.d, p0/m, z3.d, z0.d
FMAXNM Z3.D, P0/M, Z3.D, Z0.D
fmaxnm z0.d, p0/m, z0.d, z4.d
FMAXNM Z0.D, P0/M, Z0.D, Z4.D
fmaxnm z0.d, p0/m, z0.d, z31.d
FMAXNM Z0.D, P0/M, Z0.D, Z31.D
fmaxnm z0.h, p0/m, z0.h, #0.0
FMAXNM Z0.H, P0/M, Z0.H, #0.0
fmaxnm z0.h, p0/m, z0.h, #0.00000
fmaxnm z0.h, p0/m, z0.h, #0.0000000000e+00
fmaxnm z1.h, p0/m, z1.h, #0.0
FMAXNM Z1.H, P0/M, Z1.H, #0.0
fmaxnm z1.h, p0/m, z1.h, #0.00000
fmaxnm z1.h, p0/m, z1.h, #0.0000000000e+00
fmaxnm z31.h, p0/m, z31.h, #0.0
FMAXNM Z31.H, P0/M, Z31.H, #0.0
fmaxnm z31.h, p0/m, z31.h, #0.00000
fmaxnm z31.h, p0/m, z31.h, #0.0000000000e+00
fmaxnm z0.h, p2/m, z0.h, #0.0
FMAXNM Z0.H, P2/M, Z0.H, #0.0
fmaxnm z0.h, p2/m, z0.h, #0.00000
fmaxnm z0.h, p2/m, z0.h, #0.0000000000e+00
fmaxnm z0.h, p7/m, z0.h, #0.0
FMAXNM Z0.H, P7/M, Z0.H, #0.0
fmaxnm z0.h, p7/m, z0.h, #0.00000
fmaxnm z0.h, p7/m, z0.h, #0.0000000000e+00
fmaxnm z3.h, p0/m, z3.h, #0.0
FMAXNM Z3.H, P0/M, Z3.H, #0.0
fmaxnm z3.h, p0/m, z3.h, #0.00000
fmaxnm z3.h, p0/m, z3.h, #0.0000000000e+00
fmaxnm z0.h, p0/m, z0.h, #1.0
FMAXNM Z0.H, P0/M, Z0.H, #1.0
fmaxnm z0.h, p0/m, z0.h, #1.00000
fmaxnm z0.h, p0/m, z0.h, #1.0000000000e+00
fmaxnm z0.s, p0/m, z0.s, #0.0
FMAXNM Z0.S, P0/M, Z0.S, #0.0
fmaxnm z0.s, p0/m, z0.s, #0.00000
fmaxnm z0.s, p0/m, z0.s, #0.0000000000e+00
fmaxnm z1.s, p0/m, z1.s, #0.0
FMAXNM Z1.S, P0/M, Z1.S, #0.0
fmaxnm z1.s, p0/m, z1.s, #0.00000
fmaxnm z1.s, p0/m, z1.s, #0.0000000000e+00
fmaxnm z31.s, p0/m, z31.s, #0.0
FMAXNM Z31.S, P0/M, Z31.S, #0.0
fmaxnm z31.s, p0/m, z31.s, #0.00000
fmaxnm z31.s, p0/m, z31.s, #0.0000000000e+00
fmaxnm z0.s, p2/m, z0.s, #0.0
FMAXNM Z0.S, P2/M, Z0.S, #0.0
fmaxnm z0.s, p2/m, z0.s, #0.00000
fmaxnm z0.s, p2/m, z0.s, #0.0000000000e+00
fmaxnm z0.s, p7/m, z0.s, #0.0
FMAXNM Z0.S, P7/M, Z0.S, #0.0
fmaxnm z0.s, p7/m, z0.s, #0.00000
fmaxnm z0.s, p7/m, z0.s, #0.0000000000e+00
fmaxnm z3.s, p0/m, z3.s, #0.0
FMAXNM Z3.S, P0/M, Z3.S, #0.0
fmaxnm z3.s, p0/m, z3.s, #0.00000
fmaxnm z3.s, p0/m, z3.s, #0.0000000000e+00
fmaxnm z0.s, p0/m, z0.s, #1.0
FMAXNM Z0.S, P0/M, Z0.S, #1.0
fmaxnm z0.s, p0/m, z0.s, #1.00000
fmaxnm z0.s, p0/m, z0.s, #1.0000000000e+00
fmaxnm z0.d, p0/m, z0.d, #0.0
FMAXNM Z0.D, P0/M, Z0.D, #0.0
fmaxnm z0.d, p0/m, z0.d, #0.00000
fmaxnm z0.d, p0/m, z0.d, #0.0000000000e+00
fmaxnm z1.d, p0/m, z1.d, #0.0
FMAXNM Z1.D, P0/M, Z1.D, #0.0
fmaxnm z1.d, p0/m, z1.d, #0.00000
fmaxnm z1.d, p0/m, z1.d, #0.0000000000e+00
fmaxnm z31.d, p0/m, z31.d, #0.0
FMAXNM Z31.D, P0/M, Z31.D, #0.0
fmaxnm z31.d, p0/m, z31.d, #0.00000
fmaxnm z31.d, p0/m, z31.d, #0.0000000000e+00
fmaxnm z0.d, p2/m, z0.d, #0.0
FMAXNM Z0.D, P2/M, Z0.D, #0.0
fmaxnm z0.d, p2/m, z0.d, #0.00000
fmaxnm z0.d, p2/m, z0.d, #0.0000000000e+00
fmaxnm z0.d, p7/m, z0.d, #0.0
FMAXNM Z0.D, P7/M, Z0.D, #0.0
fmaxnm z0.d, p7/m, z0.d, #0.00000
fmaxnm z0.d, p7/m, z0.d, #0.0000000000e+00
fmaxnm z3.d, p0/m, z3.d, #0.0
FMAXNM Z3.D, P0/M, Z3.D, #0.0
fmaxnm z3.d, p0/m, z3.d, #0.00000
fmaxnm z3.d, p0/m, z3.d, #0.0000000000e+00
fmaxnm z0.d, p0/m, z0.d, #1.0
FMAXNM Z0.D, P0/M, Z0.D, #1.0
fmaxnm z0.d, p0/m, z0.d, #1.00000
fmaxnm z0.d, p0/m, z0.d, #1.0000000000e+00
fmaxnmv h0, p0, z0.h
FMAXNMV H0, P0, Z0.H
fmaxnmv h1, p0, z0.h
FMAXNMV H1, P0, Z0.H
fmaxnmv h31, p0, z0.h
FMAXNMV H31, P0, Z0.H
fmaxnmv h0, p2, z0.h
FMAXNMV H0, P2, Z0.H
fmaxnmv h0, p7, z0.h
FMAXNMV H0, P7, Z0.H
fmaxnmv h0, p0, z3.h
FMAXNMV H0, P0, Z3.H
fmaxnmv h0, p0, z31.h
FMAXNMV H0, P0, Z31.H
fmaxnmv s0, p0, z0.s
FMAXNMV S0, P0, Z0.S
fmaxnmv s1, p0, z0.s
FMAXNMV S1, P0, Z0.S
fmaxnmv s31, p0, z0.s
FMAXNMV S31, P0, Z0.S
fmaxnmv s0, p2, z0.s
FMAXNMV S0, P2, Z0.S
fmaxnmv s0, p7, z0.s
FMAXNMV S0, P7, Z0.S
fmaxnmv s0, p0, z3.s
FMAXNMV S0, P0, Z3.S
fmaxnmv s0, p0, z31.s
FMAXNMV S0, P0, Z31.S
fmaxnmv d0, p0, z0.d
FMAXNMV D0, P0, Z0.D
fmaxnmv d1, p0, z0.d
FMAXNMV D1, P0, Z0.D
fmaxnmv d31, p0, z0.d
FMAXNMV D31, P0, Z0.D
fmaxnmv d0, p2, z0.d
FMAXNMV D0, P2, Z0.D
fmaxnmv d0, p7, z0.d
FMAXNMV D0, P7, Z0.D
fmaxnmv d0, p0, z3.d
FMAXNMV D0, P0, Z3.D
fmaxnmv d0, p0, z31.d
FMAXNMV D0, P0, Z31.D
fmaxv h0, p0, z0.h
FMAXV H0, P0, Z0.H
fmaxv h1, p0, z0.h
FMAXV H1, P0, Z0.H
fmaxv h31, p0, z0.h
FMAXV H31, P0, Z0.H
fmaxv h0, p2, z0.h
FMAXV H0, P2, Z0.H
fmaxv h0, p7, z0.h
FMAXV H0, P7, Z0.H
fmaxv h0, p0, z3.h
FMAXV H0, P0, Z3.H
fmaxv h0, p0, z31.h
FMAXV H0, P0, Z31.H
fmaxv s0, p0, z0.s
FMAXV S0, P0, Z0.S
fmaxv s1, p0, z0.s
FMAXV S1, P0, Z0.S
fmaxv s31, p0, z0.s
FMAXV S31, P0, Z0.S
fmaxv s0, p2, z0.s
FMAXV S0, P2, Z0.S
fmaxv s0, p7, z0.s
FMAXV S0, P7, Z0.S
fmaxv s0, p0, z3.s
FMAXV S0, P0, Z3.S
fmaxv s0, p0, z31.s
FMAXV S0, P0, Z31.S
fmaxv d0, p0, z0.d
FMAXV D0, P0, Z0.D
fmaxv d1, p0, z0.d
FMAXV D1, P0, Z0.D
fmaxv d31, p0, z0.d
FMAXV D31, P0, Z0.D
fmaxv d0, p2, z0.d
FMAXV D0, P2, Z0.D
fmaxv d0, p7, z0.d
FMAXV D0, P7, Z0.D
fmaxv d0, p0, z3.d
FMAXV D0, P0, Z3.D
fmaxv d0, p0, z31.d
FMAXV D0, P0, Z31.D
fmin z0.h, p0/m, z0.h, z0.h
FMIN Z0.H, P0/M, Z0.H, Z0.H
fmin z1.h, p0/m, z1.h, z0.h
FMIN Z1.H, P0/M, Z1.H, Z0.H
fmin z31.h, p0/m, z31.h, z0.h
FMIN Z31.H, P0/M, Z31.H, Z0.H
fmin z0.h, p2/m, z0.h, z0.h
FMIN Z0.H, P2/M, Z0.H, Z0.H
fmin z0.h, p7/m, z0.h, z0.h
FMIN Z0.H, P7/M, Z0.H, Z0.H
fmin z3.h, p0/m, z3.h, z0.h
FMIN Z3.H, P0/M, Z3.H, Z0.H
fmin z0.h, p0/m, z0.h, z4.h
FMIN Z0.H, P0/M, Z0.H, Z4.H
fmin z0.h, p0/m, z0.h, z31.h
FMIN Z0.H, P0/M, Z0.H, Z31.H
fmin z0.s, p0/m, z0.s, z0.s
FMIN Z0.S, P0/M, Z0.S, Z0.S
fmin z1.s, p0/m, z1.s, z0.s
FMIN Z1.S, P0/M, Z1.S, Z0.S
fmin z31.s, p0/m, z31.s, z0.s
FMIN Z31.S, P0/M, Z31.S, Z0.S
fmin z0.s, p2/m, z0.s, z0.s
FMIN Z0.S, P2/M, Z0.S, Z0.S
fmin z0.s, p7/m, z0.s, z0.s
FMIN Z0.S, P7/M, Z0.S, Z0.S
fmin z3.s, p0/m, z3.s, z0.s
FMIN Z3.S, P0/M, Z3.S, Z0.S
fmin z0.s, p0/m, z0.s, z4.s
FMIN Z0.S, P0/M, Z0.S, Z4.S
fmin z0.s, p0/m, z0.s, z31.s
FMIN Z0.S, P0/M, Z0.S, Z31.S
fmin z0.d, p0/m, z0.d, z0.d
FMIN Z0.D, P0/M, Z0.D, Z0.D
fmin z1.d, p0/m, z1.d, z0.d
FMIN Z1.D, P0/M, Z1.D, Z0.D
fmin z31.d, p0/m, z31.d, z0.d
FMIN Z31.D, P0/M, Z31.D, Z0.D
fmin z0.d, p2/m, z0.d, z0.d
FMIN Z0.D, P2/M, Z0.D, Z0.D
fmin z0.d, p7/m, z0.d, z0.d
FMIN Z0.D, P7/M, Z0.D, Z0.D
fmin z3.d, p0/m, z3.d, z0.d
FMIN Z3.D, P0/M, Z3.D, Z0.D
fmin z0.d, p0/m, z0.d, z4.d
FMIN Z0.D, P0/M, Z0.D, Z4.D
fmin z0.d, p0/m, z0.d, z31.d
FMIN Z0.D, P0/M, Z0.D, Z31.D
fmin z0.h, p0/m, z0.h, #0.0
FMIN Z0.H, P0/M, Z0.H, #0.0
fmin z0.h, p0/m, z0.h, #0.00000
fmin z0.h, p0/m, z0.h, #0.0000000000e+00
fmin z1.h, p0/m, z1.h, #0.0
FMIN Z1.H, P0/M, Z1.H, #0.0
fmin z1.h, p0/m, z1.h, #0.00000
fmin z1.h, p0/m, z1.h, #0.0000000000e+00
fmin z31.h, p0/m, z31.h, #0.0
FMIN Z31.H, P0/M, Z31.H, #0.0
fmin z31.h, p0/m, z31.h, #0.00000
fmin z31.h, p0/m, z31.h, #0.0000000000e+00
fmin z0.h, p2/m, z0.h, #0.0
FMIN Z0.H, P2/M, Z0.H, #0.0
fmin z0.h, p2/m, z0.h, #0.00000
fmin z0.h, p2/m, z0.h, #0.0000000000e+00
fmin z0.h, p7/m, z0.h, #0.0
FMIN Z0.H, P7/M, Z0.H, #0.0
fmin z0.h, p7/m, z0.h, #0.00000
fmin z0.h, p7/m, z0.h, #0.0000000000e+00
fmin z3.h, p0/m, z3.h, #0.0
FMIN Z3.H, P0/M, Z3.H, #0.0
fmin z3.h, p0/m, z3.h, #0.00000
fmin z3.h, p0/m, z3.h, #0.0000000000e+00
fmin z0.h, p0/m, z0.h, #1.0
FMIN Z0.H, P0/M, Z0.H, #1.0
fmin z0.h, p0/m, z0.h, #1.00000
fmin z0.h, p0/m, z0.h, #1.0000000000e+00
fmin z0.s, p0/m, z0.s, #0.0
FMIN Z0.S, P0/M, Z0.S, #0.0
fmin z0.s, p0/m, z0.s, #0.00000
fmin z0.s, p0/m, z0.s, #0.0000000000e+00
fmin z1.s, p0/m, z1.s, #0.0
FMIN Z1.S, P0/M, Z1.S, #0.0
fmin z1.s, p0/m, z1.s, #0.00000
fmin z1.s, p0/m, z1.s, #0.0000000000e+00
fmin z31.s, p0/m, z31.s, #0.0
FMIN Z31.S, P0/M, Z31.S, #0.0
fmin z31.s, p0/m, z31.s, #0.00000
fmin z31.s, p0/m, z31.s, #0.0000000000e+00
fmin z0.s, p2/m, z0.s, #0.0
FMIN Z0.S, P2/M, Z0.S, #0.0
fmin z0.s, p2/m, z0.s, #0.00000
fmin z0.s, p2/m, z0.s, #0.0000000000e+00
fmin z0.s, p7/m, z0.s, #0.0
FMIN Z0.S, P7/M, Z0.S, #0.0
fmin z0.s, p7/m, z0.s, #0.00000
fmin z0.s, p7/m, z0.s, #0.0000000000e+00
fmin z3.s, p0/m, z3.s, #0.0
FMIN Z3.S, P0/M, Z3.S, #0.0
fmin z3.s, p0/m, z3.s, #0.00000
fmin z3.s, p0/m, z3.s, #0.0000000000e+00
fmin z0.s, p0/m, z0.s, #1.0
FMIN Z0.S, P0/M, Z0.S, #1.0
fmin z0.s, p0/m, z0.s, #1.00000
fmin z0.s, p0/m, z0.s, #1.0000000000e+00
fmin z0.d, p0/m, z0.d, #0.0
FMIN Z0.D, P0/M, Z0.D, #0.0
fmin z0.d, p0/m, z0.d, #0.00000
fmin z0.d, p0/m, z0.d, #0.0000000000e+00
fmin z1.d, p0/m, z1.d, #0.0
FMIN Z1.D, P0/M, Z1.D, #0.0
fmin z1.d, p0/m, z1.d, #0.00000
fmin z1.d, p0/m, z1.d, #0.0000000000e+00
fmin z31.d, p0/m, z31.d, #0.0
FMIN Z31.D, P0/M, Z31.D, #0.0
fmin z31.d, p0/m, z31.d, #0.00000
fmin z31.d, p0/m, z31.d, #0.0000000000e+00
fmin z0.d, p2/m, z0.d, #0.0
FMIN Z0.D, P2/M, Z0.D, #0.0
fmin z0.d, p2/m, z0.d, #0.00000
fmin z0.d, p2/m, z0.d, #0.0000000000e+00
fmin z0.d, p7/m, z0.d, #0.0
FMIN Z0.D, P7/M, Z0.D, #0.0
fmin z0.d, p7/m, z0.d, #0.00000
fmin z0.d, p7/m, z0.d, #0.0000000000e+00
fmin z3.d, p0/m, z3.d, #0.0
FMIN Z3.D, P0/M, Z3.D, #0.0
fmin z3.d, p0/m, z3.d, #0.00000
fmin z3.d, p0/m, z3.d, #0.0000000000e+00
fmin z0.d, p0/m, z0.d, #1.0
FMIN Z0.D, P0/M, Z0.D, #1.0
fmin z0.d, p0/m, z0.d, #1.00000
fmin z0.d, p0/m, z0.d, #1.0000000000e+00
fminnm z0.h, p0/m, z0.h, z0.h
FMINNM Z0.H, P0/M, Z0.H, Z0.H
fminnm z1.h, p0/m, z1.h, z0.h
FMINNM Z1.H, P0/M, Z1.H, Z0.H
fminnm z31.h, p0/m, z31.h, z0.h
FMINNM Z31.H, P0/M, Z31.H, Z0.H
fminnm z0.h, p2/m, z0.h, z0.h
FMINNM Z0.H, P2/M, Z0.H, Z0.H
fminnm z0.h, p7/m, z0.h, z0.h
FMINNM Z0.H, P7/M, Z0.H, Z0.H
fminnm z3.h, p0/m, z3.h, z0.h
FMINNM Z3.H, P0/M, Z3.H, Z0.H
fminnm z0.h, p0/m, z0.h, z4.h
FMINNM Z0.H, P0/M, Z0.H, Z4.H
fminnm z0.h, p0/m, z0.h, z31.h
FMINNM Z0.H, P0/M, Z0.H, Z31.H
fminnm z0.s, p0/m, z0.s, z0.s
FMINNM Z0.S, P0/M, Z0.S, Z0.S
fminnm z1.s, p0/m, z1.s, z0.s
FMINNM Z1.S, P0/M, Z1.S, Z0.S
fminnm z31.s, p0/m, z31.s, z0.s
FMINNM Z31.S, P0/M, Z31.S, Z0.S
fminnm z0.s, p2/m, z0.s, z0.s
FMINNM Z0.S, P2/M, Z0.S, Z0.S
fminnm z0.s, p7/m, z0.s, z0.s
FMINNM Z0.S, P7/M, Z0.S, Z0.S
fminnm z3.s, p0/m, z3.s, z0.s
FMINNM Z3.S, P0/M, Z3.S, Z0.S
fminnm z0.s, p0/m, z0.s, z4.s
FMINNM Z0.S, P0/M, Z0.S, Z4.S
fminnm z0.s, p0/m, z0.s, z31.s
FMINNM Z0.S, P0/M, Z0.S, Z31.S
fminnm z0.d, p0/m, z0.d, z0.d
FMINNM Z0.D, P0/M, Z0.D, Z0.D
fminnm z1.d, p0/m, z1.d, z0.d
FMINNM Z1.D, P0/M, Z1.D, Z0.D
fminnm z31.d, p0/m, z31.d, z0.d
FMINNM Z31.D, P0/M, Z31.D, Z0.D
fminnm z0.d, p2/m, z0.d, z0.d
FMINNM Z0.D, P2/M, Z0.D, Z0.D
fminnm z0.d, p7/m, z0.d, z0.d
FMINNM Z0.D, P7/M, Z0.D, Z0.D
fminnm z3.d, p0/m, z3.d, z0.d
FMINNM Z3.D, P0/M, Z3.D, Z0.D
fminnm z0.d, p0/m, z0.d, z4.d
FMINNM Z0.D, P0/M, Z0.D, Z4.D
fminnm z0.d, p0/m, z0.d, z31.d
FMINNM Z0.D, P0/M, Z0.D, Z31.D
fminnm z0.h, p0/m, z0.h, #0.0
FMINNM Z0.H, P0/M, Z0.H, #0.0
fminnm z0.h, p0/m, z0.h, #0.00000
fminnm z0.h, p0/m, z0.h, #0.0000000000e+00
fminnm z1.h, p0/m, z1.h, #0.0
FMINNM Z1.H, P0/M, Z1.H, #0.0
fminnm z1.h, p0/m, z1.h, #0.00000
fminnm z1.h, p0/m, z1.h, #0.0000000000e+00
fminnm z31.h, p0/m, z31.h, #0.0
FMINNM Z31.H, P0/M, Z31.H, #0.0
fminnm z31.h, p0/m, z31.h, #0.00000
fminnm z31.h, p0/m, z31.h, #0.0000000000e+00
fminnm z0.h, p2/m, z0.h, #0.0
FMINNM Z0.H, P2/M, Z0.H, #0.0
fminnm z0.h, p2/m, z0.h, #0.00000
fminnm z0.h, p2/m, z0.h, #0.0000000000e+00
fminnm z0.h, p7/m, z0.h, #0.0
FMINNM Z0.H, P7/M, Z0.H, #0.0
fminnm z0.h, p7/m, z0.h, #0.00000
fminnm z0.h, p7/m, z0.h, #0.0000000000e+00
fminnm z3.h, p0/m, z3.h, #0.0
FMINNM Z3.H, P0/M, Z3.H, #0.0
fminnm z3.h, p0/m, z3.h, #0.00000
fminnm z3.h, p0/m, z3.h, #0.0000000000e+00
fminnm z0.h, p0/m, z0.h, #1.0
FMINNM Z0.H, P0/M, Z0.H, #1.0
fminnm z0.h, p0/m, z0.h, #1.00000
fminnm z0.h, p0/m, z0.h, #1.0000000000e+00
fminnm z0.s, p0/m, z0.s, #0.0
FMINNM Z0.S, P0/M, Z0.S, #0.0
fminnm z0.s, p0/m, z0.s, #0.00000
fminnm z0.s, p0/m, z0.s, #0.0000000000e+00
fminnm z1.s, p0/m, z1.s, #0.0
FMINNM Z1.S, P0/M, Z1.S, #0.0
fminnm z1.s, p0/m, z1.s, #0.00000
fminnm z1.s, p0/m, z1.s, #0.0000000000e+00
fminnm z31.s, p0/m, z31.s, #0.0
FMINNM Z31.S, P0/M, Z31.S, #0.0
fminnm z31.s, p0/m, z31.s, #0.00000
fminnm z31.s, p0/m, z31.s, #0.0000000000e+00
fminnm z0.s, p2/m, z0.s, #0.0
FMINNM Z0.S, P2/M, Z0.S, #0.0
fminnm z0.s, p2/m, z0.s, #0.00000
fminnm z0.s, p2/m, z0.s, #0.0000000000e+00
fminnm z0.s, p7/m, z0.s, #0.0
FMINNM Z0.S, P7/M, Z0.S, #0.0
fminnm z0.s, p7/m, z0.s, #0.00000
fminnm z0.s, p7/m, z0.s, #0.0000000000e+00
fminnm z3.s, p0/m, z3.s, #0.0
FMINNM Z3.S, P0/M, Z3.S, #0.0
fminnm z3.s, p0/m, z3.s, #0.00000
fminnm z3.s, p0/m, z3.s, #0.0000000000e+00
fminnm z0.s, p0/m, z0.s, #1.0
FMINNM Z0.S, P0/M, Z0.S, #1.0
fminnm z0.s, p0/m, z0.s, #1.00000
fminnm z0.s, p0/m, z0.s, #1.0000000000e+00
fminnm z0.d, p0/m, z0.d, #0.0
FMINNM Z0.D, P0/M, Z0.D, #0.0
fminnm z0.d, p0/m, z0.d, #0.00000
fminnm z0.d, p0/m, z0.d, #0.0000000000e+00
fminnm z1.d, p0/m, z1.d, #0.0
FMINNM Z1.D, P0/M, Z1.D, #0.0
fminnm z1.d, p0/m, z1.d, #0.00000
fminnm z1.d, p0/m, z1.d, #0.0000000000e+00
fminnm z31.d, p0/m, z31.d, #0.0
FMINNM Z31.D, P0/M, Z31.D, #0.0
fminnm z31.d, p0/m, z31.d, #0.00000
fminnm z31.d, p0/m, z31.d, #0.0000000000e+00
fminnm z0.d, p2/m, z0.d, #0.0
FMINNM Z0.D, P2/M, Z0.D, #0.0
fminnm z0.d, p2/m, z0.d, #0.00000
fminnm z0.d, p2/m, z0.d, #0.0000000000e+00
fminnm z0.d, p7/m, z0.d, #0.0
FMINNM Z0.D, P7/M, Z0.D, #0.0
fminnm z0.d, p7/m, z0.d, #0.00000
fminnm z0.d, p7/m, z0.d, #0.0000000000e+00
fminnm z3.d, p0/m, z3.d, #0.0
FMINNM Z3.D, P0/M, Z3.D, #0.0
fminnm z3.d, p0/m, z3.d, #0.00000
fminnm z3.d, p0/m, z3.d, #0.0000000000e+00
fminnm z0.d, p0/m, z0.d, #1.0
FMINNM Z0.D, P0/M, Z0.D, #1.0
fminnm z0.d, p0/m, z0.d, #1.00000
fminnm z0.d, p0/m, z0.d, #1.0000000000e+00
fminnmv h0, p0, z0.h
FMINNMV h0, P0, Z0.H
fminnmv h1, p0, z0.h
FMINNMV h1, P0, Z0.H
fminnmv h31, p0, z0.h
FMINNMV h31, P0, Z0.H
fminnmv h0, p2, z0.h
FMINNMV h0, P2, Z0.H
fminnmv h0, p7, z0.h
FMINNMV h0, P7, Z0.H
fminnmv h0, p0, z3.h
FMINNMV h0, P0, Z3.H
fminnmv h0, p0, z31.h
FMINNMV h0, P0, Z31.H
fminnmv s0, p0, z0.s
FMINNMV S0, P0, Z0.S
fminnmv s1, p0, z0.s
FMINNMV S1, P0, Z0.S
fminnmv s31, p0, z0.s
FMINNMV S31, P0, Z0.S
fminnmv s0, p2, z0.s
FMINNMV S0, P2, Z0.S
fminnmv s0, p7, z0.s
FMINNMV S0, P7, Z0.S
fminnmv s0, p0, z3.s
FMINNMV S0, P0, Z3.S
fminnmv s0, p0, z31.s
FMINNMV S0, P0, Z31.S
fminnmv d0, p0, z0.d
FMINNMV D0, P0, Z0.D
fminnmv d1, p0, z0.d
FMINNMV D1, P0, Z0.D
fminnmv d31, p0, z0.d
FMINNMV D31, P0, Z0.D
fminnmv d0, p2, z0.d
FMINNMV D0, P2, Z0.D
fminnmv d0, p7, z0.d
FMINNMV D0, P7, Z0.D
fminnmv d0, p0, z3.d
FMINNMV D0, P0, Z3.D
fminnmv d0, p0, z31.d
FMINNMV D0, P0, Z31.D
fminv h0, p0, z0.h
FMINV H0, P0, Z0.H
fminv h1, p0, z0.h
FMINV H1, P0, Z0.H
fminv h31, p0, z0.h
FMINV H31, P0, Z0.H
fminv h0, p2, z0.h
FMINV H0, P2, Z0.H
fminv h0, p7, z0.h
FMINV H0, P7, Z0.H
fminv h0, p0, z3.h
FMINV H0, P0, Z3.H
fminv h0, p0, z31.h
FMINV H0, P0, Z31.H
fminv s0, p0, z0.s
FMINV S0, P0, Z0.S
fminv s1, p0, z0.s
FMINV S1, P0, Z0.S
fminv s31, p0, z0.s
FMINV S31, P0, Z0.S
fminv s0, p2, z0.s
FMINV S0, P2, Z0.S
fminv s0, p7, z0.s
FMINV S0, P7, Z0.S
fminv s0, p0, z3.s
FMINV S0, P0, Z3.S
fminv s0, p0, z31.s
FMINV S0, P0, Z31.S
fminv d0, p0, z0.d
FMINV D0, P0, Z0.D
fminv d1, p0, z0.d
FMINV D1, P0, Z0.D
fminv d31, p0, z0.d
FMINV D31, P0, Z0.D
fminv d0, p2, z0.d
FMINV D0, P2, Z0.D
fminv d0, p7, z0.d
FMINV D0, P7, Z0.D
fminv d0, p0, z3.d
FMINV D0, P0, Z3.D
fminv d0, p0, z31.d
FMINV D0, P0, Z31.D
fmla z0.h, p0/m, z0.h, z0.h
FMLA Z0.H, P0/M, Z0.H, Z0.H
fmla z1.h, p0/m, z0.h, z0.h
FMLA Z1.H, P0/M, Z0.H, Z0.H
fmla z31.h, p0/m, z0.h, z0.h
FMLA Z31.H, P0/M, Z0.H, Z0.H
fmla z0.h, p2/m, z0.h, z0.h
FMLA Z0.H, P2/M, Z0.H, Z0.H
fmla z0.h, p7/m, z0.h, z0.h
FMLA Z0.H, P7/M, Z0.H, Z0.H
fmla z0.h, p0/m, z3.h, z0.h
FMLA Z0.H, P0/M, Z3.H, Z0.H
fmla z0.h, p0/m, z31.h, z0.h
FMLA Z0.H, P0/M, Z31.H, Z0.H
fmla z0.h, p0/m, z0.h, z4.h
FMLA Z0.H, P0/M, Z0.H, Z4.H
fmla z0.h, p0/m, z0.h, z31.h
FMLA Z0.H, P0/M, Z0.H, Z31.H
fmla z0.s, p0/m, z0.s, z0.s
FMLA Z0.S, P0/M, Z0.S, Z0.S
fmla z1.s, p0/m, z0.s, z0.s
FMLA Z1.S, P0/M, Z0.S, Z0.S
fmla z31.s, p0/m, z0.s, z0.s
FMLA Z31.S, P0/M, Z0.S, Z0.S
fmla z0.s, p2/m, z0.s, z0.s
FMLA Z0.S, P2/M, Z0.S, Z0.S
fmla z0.s, p7/m, z0.s, z0.s
FMLA Z0.S, P7/M, Z0.S, Z0.S
fmla z0.s, p0/m, z3.s, z0.s
FMLA Z0.S, P0/M, Z3.S, Z0.S
fmla z0.s, p0/m, z31.s, z0.s
FMLA Z0.S, P0/M, Z31.S, Z0.S
fmla z0.s, p0/m, z0.s, z4.s
FMLA Z0.S, P0/M, Z0.S, Z4.S
fmla z0.s, p0/m, z0.s, z31.s
FMLA Z0.S, P0/M, Z0.S, Z31.S
fmla z0.d, p0/m, z0.d, z0.d
FMLA Z0.D, P0/M, Z0.D, Z0.D
fmla z1.d, p0/m, z0.d, z0.d
FMLA Z1.D, P0/M, Z0.D, Z0.D
fmla z31.d, p0/m, z0.d, z0.d
FMLA Z31.D, P0/M, Z0.D, Z0.D
fmla z0.d, p2/m, z0.d, z0.d
FMLA Z0.D, P2/M, Z0.D, Z0.D
fmla z0.d, p7/m, z0.d, z0.d
FMLA Z0.D, P7/M, Z0.D, Z0.D
fmla z0.d, p0/m, z3.d, z0.d
FMLA Z0.D, P0/M, Z3.D, Z0.D
fmla z0.d, p0/m, z31.d, z0.d
FMLA Z0.D, P0/M, Z31.D, Z0.D
fmla z0.d, p0/m, z0.d, z4.d
FMLA Z0.D, P0/M, Z0.D, Z4.D
fmla z0.d, p0/m, z0.d, z31.d
FMLA Z0.D, P0/M, Z0.D, Z31.D
fmla z0.h, z0.h, z0.h[0]
FMLA Z0.H, Z0.H, Z0.H[0]
fmla z1.h, z0.h, z0.h[0]
FMLA Z1.H, Z0.H, Z0.H[0]
fmla z31.h, z0.h, z0.h[0]
FMLA Z31.H, Z0.H, Z0.H[0]
fmla z0.h, z2.h, z0.h[0]
FMLA Z0.H, Z2.H, Z0.H[0]
fmla z0.h, z31.h, z0.h[0]
FMLA Z0.H, Z31.H, Z0.H[0]
fmla z0.h, z0.h, z3.h[0]
FMLA Z0.H, Z0.H, Z3.H[0]
fmla z0.h, z0.h, z7.h[0]
FMLA Z0.H, Z0.H, Z7.H[0]
fmla z0.h, z0.h, z0.h[1]
FMLA Z0.H, Z0.H, Z0.H[1]
fmla z0.h, z0.h, z4.h[1]
FMLA Z0.H, Z0.H, Z4.H[1]
fmla z0.h, z0.h, z3.h[4]
FMLA Z0.H, Z0.H, Z3.H[4]
fmla z0.h, z0.h, z0.h[7]
FMLA Z0.H, Z0.H, Z0.H[7]
fmla z0.h, z0.h, z5.h[7]
FMLA Z0.H, Z0.H, Z5.H[7]
fmla z0.s, z0.s, z0.s[0]
FMLA Z0.S, Z0.S, Z0.S[0]
fmla z1.s, z0.s, z0.s[0]
FMLA Z1.S, Z0.S, Z0.S[0]
fmla z31.s, z0.s, z0.s[0]
FMLA Z31.S, Z0.S, Z0.S[0]
fmla z0.s, z2.s, z0.s[0]
FMLA Z0.S, Z2.S, Z0.S[0]
fmla z0.s, z31.s, z0.s[0]
FMLA Z0.S, Z31.S, Z0.S[0]
fmla z0.s, z0.s, z3.s[0]
FMLA Z0.S, Z0.S, Z3.S[0]
fmla z0.s, z0.s, z7.s[0]
FMLA Z0.S, Z0.S, Z7.S[0]
fmla z0.s, z0.s, z0.s[1]
FMLA Z0.S, Z0.S, Z0.S[1]
fmla z0.s, z0.s, z4.s[1]
FMLA Z0.S, Z0.S, Z4.S[1]
fmla z0.s, z0.s, z3.s[2]
FMLA Z0.S, Z0.S, Z3.S[2]
fmla z0.s, z0.s, z0.s[3]
FMLA Z0.S, Z0.S, Z0.S[3]
fmla z0.s, z0.s, z5.s[3]
FMLA Z0.S, Z0.S, Z5.S[3]
fmla z0.d, z0.d, z0.d[0]
FMLA Z0.D, Z0.D, Z0.D[0]
fmla z1.d, z0.d, z0.d[0]
FMLA Z1.D, Z0.D, Z0.D[0]
fmla z31.d, z0.d, z0.d[0]
FMLA Z31.D, Z0.D, Z0.D[0]
fmla z0.d, z2.d, z0.d[0]
FMLA Z0.D, Z2.D, Z0.D[0]
fmla z0.d, z31.d, z0.d[0]
FMLA Z0.D, Z31.D, Z0.D[0]
fmla z0.d, z0.d, z3.d[0]
FMLA Z0.D, Z0.D, Z3.D[0]
fmla z0.d, z0.d, z15.d[0]
FMLA Z0.D, Z0.D, Z15.D[0]
fmla z0.d, z0.d, z0.d[1]
FMLA Z0.D, Z0.D, Z0.D[1]
fmla z0.d, z0.d, z11.d[1]
FMLA Z0.D, Z0.D, Z11.D[1]
fmls z0.h, p0/m, z0.h, z0.h
FMLS Z0.H, P0/M, Z0.H, Z0.H
fmls z1.h, p0/m, z0.h, z0.h
FMLS Z1.H, P0/M, Z0.H, Z0.H
fmls z31.h, p0/m, z0.h, z0.h
FMLS Z31.H, P0/M, Z0.H, Z0.H
fmls z0.h, p2/m, z0.h, z0.h
FMLS Z0.H, P2/M, Z0.H, Z0.H
fmls z0.h, p7/m, z0.h, z0.h
FMLS Z0.H, P7/M, Z0.H, Z0.H
fmls z0.h, p0/m, z3.h, z0.h
FMLS Z0.H, P0/M, Z3.H, Z0.H
fmls z0.h, p0/m, z31.h, z0.h
FMLS Z0.H, P0/M, Z31.H, Z0.H
fmls z0.h, p0/m, z0.h, z4.h
FMLS Z0.H, P0/M, Z0.H, Z4.H
fmls z0.h, p0/m, z0.h, z31.h
FMLS Z0.H, P0/M, Z0.H, Z31.H
fmls z0.s, p0/m, z0.s, z0.s
FMLS Z0.S, P0/M, Z0.S, Z0.S
fmls z1.s, p0/m, z0.s, z0.s
FMLS Z1.S, P0/M, Z0.S, Z0.S
fmls z31.s, p0/m, z0.s, z0.s
FMLS Z31.S, P0/M, Z0.S, Z0.S
fmls z0.s, p2/m, z0.s, z0.s
FMLS Z0.S, P2/M, Z0.S, Z0.S
fmls z0.s, p7/m, z0.s, z0.s
FMLS Z0.S, P7/M, Z0.S, Z0.S
fmls z0.s, p0/m, z3.s, z0.s
FMLS Z0.S, P0/M, Z3.S, Z0.S
fmls z0.s, p0/m, z31.s, z0.s
FMLS Z0.S, P0/M, Z31.S, Z0.S
fmls z0.s, p0/m, z0.s, z4.s
FMLS Z0.S, P0/M, Z0.S, Z4.S
fmls z0.s, p0/m, z0.s, z31.s
FMLS Z0.S, P0/M, Z0.S, Z31.S
fmls z0.d, p0/m, z0.d, z0.d
FMLS Z0.D, P0/M, Z0.D, Z0.D
fmls z1.d, p0/m, z0.d, z0.d
FMLS Z1.D, P0/M, Z0.D, Z0.D
fmls z31.d, p0/m, z0.d, z0.d
FMLS Z31.D, P0/M, Z0.D, Z0.D
fmls z0.d, p2/m, z0.d, z0.d
FMLS Z0.D, P2/M, Z0.D, Z0.D
fmls z0.d, p7/m, z0.d, z0.d
FMLS Z0.D, P7/M, Z0.D, Z0.D
fmls z0.d, p0/m, z3.d, z0.d
FMLS Z0.D, P0/M, Z3.D, Z0.D
fmls z0.d, p0/m, z31.d, z0.d
FMLS Z0.D, P0/M, Z31.D, Z0.D
fmls z0.d, p0/m, z0.d, z4.d
FMLS Z0.D, P0/M, Z0.D, Z4.D
fmls z0.d, p0/m, z0.d, z31.d
FMLS Z0.D, P0/M, Z0.D, Z31.D
fmls z0.h, z0.h, z0.h[0]
FMLS Z0.H, Z0.H, Z0.H[0]
fmls z1.h, z0.h, z0.h[0]
FMLS Z1.H, Z0.H, Z0.H[0]
fmls z31.h, z0.h, z0.h[0]
FMLS Z31.H, Z0.H, Z0.H[0]
fmls z0.h, z2.h, z0.h[0]
FMLS Z0.H, Z2.H, Z0.H[0]
fmls z0.h, z31.h, z0.h[0]
FMLS Z0.H, Z31.H, Z0.H[0]
fmls z0.h, z0.h, z3.h[0]
FMLS Z0.H, Z0.H, Z3.H[0]
fmls z0.h, z0.h, z7.h[0]
FMLS Z0.H, Z0.H, Z7.H[0]
fmls z0.h, z0.h, z0.h[1]
FMLS Z0.H, Z0.H, Z0.H[1]
fmls z0.h, z0.h, z4.h[1]
FMLS Z0.H, Z0.H, Z4.H[1]
fmls z0.h, z0.h, z3.h[4]
FMLS Z0.H, Z0.H, Z3.H[4]
fmls z0.h, z0.h, z0.h[7]
FMLS Z0.H, Z0.H, Z0.H[7]
fmls z0.h, z0.h, z5.h[7]
FMLS Z0.H, Z0.H, Z5.H[7]
fmls z0.s, z0.s, z0.s[0]
FMLS Z0.S, Z0.S, Z0.S[0]
fmls z1.s, z0.s, z0.s[0]
FMLS Z1.S, Z0.S, Z0.S[0]
fmls z31.s, z0.s, z0.s[0]
FMLS Z31.S, Z0.S, Z0.S[0]
fmls z0.s, z2.s, z0.s[0]
FMLS Z0.S, Z2.S, Z0.S[0]
fmls z0.s, z31.s, z0.s[0]
FMLS Z0.S, Z31.S, Z0.S[0]
fmls z0.s, z0.s, z3.s[0]
FMLS Z0.S, Z0.S, Z3.S[0]
fmls z0.s, z0.s, z7.s[0]
FMLS Z0.S, Z0.S, Z7.S[0]
fmls z0.s, z0.s, z0.s[1]
FMLS Z0.S, Z0.S, Z0.S[1]
fmls z0.s, z0.s, z4.s[1]
FMLS Z0.S, Z0.S, Z4.S[1]
fmls z0.s, z0.s, z3.s[2]
FMLS Z0.S, Z0.S, Z3.S[2]
fmls z0.s, z0.s, z0.s[3]
FMLS Z0.S, Z0.S, Z0.S[3]
fmls z0.s, z0.s, z5.s[3]
FMLS Z0.S, Z0.S, Z5.S[3]
fmls z0.d, z0.d, z0.d[0]
FMLS Z0.D, Z0.D, Z0.D[0]
fmls z1.d, z0.d, z0.d[0]
FMLS Z1.D, Z0.D, Z0.D[0]
fmls z31.d, z0.d, z0.d[0]
FMLS Z31.D, Z0.D, Z0.D[0]
fmls z0.d, z2.d, z0.d[0]
FMLS Z0.D, Z2.D, Z0.D[0]
fmls z0.d, z31.d, z0.d[0]
FMLS Z0.D, Z31.D, Z0.D[0]
fmls z0.d, z0.d, z3.d[0]
FMLS Z0.D, Z0.D, Z3.D[0]
fmls z0.d, z0.d, z15.d[0]
FMLS Z0.D, Z0.D, Z15.D[0]
fmls z0.d, z0.d, z0.d[1]
FMLS Z0.D, Z0.D, Z0.D[1]
fmls z0.d, z0.d, z11.d[1]
FMLS Z0.D, Z0.D, Z11.D[1]
fmsb z0.h, p0/m, z0.h, z0.h
FMSB Z0.H, P0/M, Z0.H, Z0.H
fmsb z1.h, p0/m, z0.h, z0.h
FMSB Z1.H, P0/M, Z0.H, Z0.H
fmsb z31.h, p0/m, z0.h, z0.h
FMSB Z31.H, P0/M, Z0.H, Z0.H
fmsb z0.h, p2/m, z0.h, z0.h
FMSB Z0.H, P2/M, Z0.H, Z0.H
fmsb z0.h, p7/m, z0.h, z0.h
FMSB Z0.H, P7/M, Z0.H, Z0.H
fmsb z0.h, p0/m, z3.h, z0.h
FMSB Z0.H, P0/M, Z3.H, Z0.H
fmsb z0.h, p0/m, z31.h, z0.h
FMSB Z0.H, P0/M, Z31.H, Z0.H
fmsb z0.h, p0/m, z0.h, z4.h
FMSB Z0.H, P0/M, Z0.H, Z4.H
fmsb z0.h, p0/m, z0.h, z31.h
FMSB Z0.H, P0/M, Z0.H, Z31.H
fmsb z0.s, p0/m, z0.s, z0.s
FMSB Z0.S, P0/M, Z0.S, Z0.S
fmsb z1.s, p0/m, z0.s, z0.s
FMSB Z1.S, P0/M, Z0.S, Z0.S
fmsb z31.s, p0/m, z0.s, z0.s
FMSB Z31.S, P0/M, Z0.S, Z0.S
fmsb z0.s, p2/m, z0.s, z0.s
FMSB Z0.S, P2/M, Z0.S, Z0.S
fmsb z0.s, p7/m, z0.s, z0.s
FMSB Z0.S, P7/M, Z0.S, Z0.S
fmsb z0.s, p0/m, z3.s, z0.s
FMSB Z0.S, P0/M, Z3.S, Z0.S
fmsb z0.s, p0/m, z31.s, z0.s
FMSB Z0.S, P0/M, Z31.S, Z0.S
fmsb z0.s, p0/m, z0.s, z4.s
FMSB Z0.S, P0/M, Z0.S, Z4.S
fmsb z0.s, p0/m, z0.s, z31.s
FMSB Z0.S, P0/M, Z0.S, Z31.S
fmsb z0.d, p0/m, z0.d, z0.d
FMSB Z0.D, P0/M, Z0.D, Z0.D
fmsb z1.d, p0/m, z0.d, z0.d
FMSB Z1.D, P0/M, Z0.D, Z0.D
fmsb z31.d, p0/m, z0.d, z0.d
FMSB Z31.D, P0/M, Z0.D, Z0.D
fmsb z0.d, p2/m, z0.d, z0.d
FMSB Z0.D, P2/M, Z0.D, Z0.D
fmsb z0.d, p7/m, z0.d, z0.d
FMSB Z0.D, P7/M, Z0.D, Z0.D
fmsb z0.d, p0/m, z3.d, z0.d
FMSB Z0.D, P0/M, Z3.D, Z0.D
fmsb z0.d, p0/m, z31.d, z0.d
FMSB Z0.D, P0/M, Z31.D, Z0.D
fmsb z0.d, p0/m, z0.d, z4.d
FMSB Z0.D, P0/M, Z0.D, Z4.D
fmsb z0.d, p0/m, z0.d, z31.d
FMSB Z0.D, P0/M, Z0.D, Z31.D
fmul z0.h, z0.h, z0.h
FMUL Z0.H, Z0.H, Z0.H
fmul z1.h, z0.h, z0.h
FMUL Z1.H, Z0.H, Z0.H
fmul z31.h, z0.h, z0.h
FMUL Z31.H, Z0.H, Z0.H
fmul z0.h, z2.h, z0.h
FMUL Z0.H, Z2.H, Z0.H
fmul z0.h, z31.h, z0.h
FMUL Z0.H, Z31.H, Z0.H
fmul z0.h, z0.h, z3.h
FMUL Z0.H, Z0.H, Z3.H
fmul z0.h, z0.h, z31.h
FMUL Z0.H, Z0.H, Z31.H
fmul z0.s, z0.s, z0.s
FMUL Z0.S, Z0.S, Z0.S
fmul z1.s, z0.s, z0.s
FMUL Z1.S, Z0.S, Z0.S
fmul z31.s, z0.s, z0.s
FMUL Z31.S, Z0.S, Z0.S
fmul z0.s, z2.s, z0.s
FMUL Z0.S, Z2.S, Z0.S
fmul z0.s, z31.s, z0.s
FMUL Z0.S, Z31.S, Z0.S
fmul z0.s, z0.s, z3.s
FMUL Z0.S, Z0.S, Z3.S
fmul z0.s, z0.s, z31.s
FMUL Z0.S, Z0.S, Z31.S
fmul z0.d, z0.d, z0.d
FMUL Z0.D, Z0.D, Z0.D
fmul z1.d, z0.d, z0.d
FMUL Z1.D, Z0.D, Z0.D
fmul z31.d, z0.d, z0.d
FMUL Z31.D, Z0.D, Z0.D
fmul z0.d, z2.d, z0.d
FMUL Z0.D, Z2.D, Z0.D
fmul z0.d, z31.d, z0.d
FMUL Z0.D, Z31.D, Z0.D
fmul z0.d, z0.d, z3.d
FMUL Z0.D, Z0.D, Z3.D
fmul z0.d, z0.d, z31.d
FMUL Z0.D, Z0.D, Z31.D
fmul z0.h, p0/m, z0.h, z0.h
FMUL Z0.H, P0/M, Z0.H, Z0.H
fmul z1.h, p0/m, z1.h, z0.h
FMUL Z1.H, P0/M, Z1.H, Z0.H
fmul z31.h, p0/m, z31.h, z0.h
FMUL Z31.H, P0/M, Z31.H, Z0.H
fmul z0.h, p2/m, z0.h, z0.h
FMUL Z0.H, P2/M, Z0.H, Z0.H
fmul z0.h, p7/m, z0.h, z0.h
FMUL Z0.H, P7/M, Z0.H, Z0.H
fmul z3.h, p0/m, z3.h, z0.h
FMUL Z3.H, P0/M, Z3.H, Z0.H
fmul z0.h, p0/m, z0.h, z4.h
FMUL Z0.H, P0/M, Z0.H, Z4.H
fmul z0.h, p0/m, z0.h, z31.h
FMUL Z0.H, P0/M, Z0.H, Z31.H
fmul z0.s, p0/m, z0.s, z0.s
FMUL Z0.S, P0/M, Z0.S, Z0.S
fmul z1.s, p0/m, z1.s, z0.s
FMUL Z1.S, P0/M, Z1.S, Z0.S
fmul z31.s, p0/m, z31.s, z0.s
FMUL Z31.S, P0/M, Z31.S, Z0.S
fmul z0.s, p2/m, z0.s, z0.s
FMUL Z0.S, P2/M, Z0.S, Z0.S
fmul z0.s, p7/m, z0.s, z0.s
FMUL Z0.S, P7/M, Z0.S, Z0.S
fmul z3.s, p0/m, z3.s, z0.s
FMUL Z3.S, P0/M, Z3.S, Z0.S
fmul z0.s, p0/m, z0.s, z4.s
FMUL Z0.S, P0/M, Z0.S, Z4.S
fmul z0.s, p0/m, z0.s, z31.s
FMUL Z0.S, P0/M, Z0.S, Z31.S
fmul z0.d, p0/m, z0.d, z0.d
FMUL Z0.D, P0/M, Z0.D, Z0.D
fmul z1.d, p0/m, z1.d, z0.d
FMUL Z1.D, P0/M, Z1.D, Z0.D
fmul z31.d, p0/m, z31.d, z0.d
FMUL Z31.D, P0/M, Z31.D, Z0.D
fmul z0.d, p2/m, z0.d, z0.d
FMUL Z0.D, P2/M, Z0.D, Z0.D
fmul z0.d, p7/m, z0.d, z0.d
FMUL Z0.D, P7/M, Z0.D, Z0.D
fmul z3.d, p0/m, z3.d, z0.d
FMUL Z3.D, P0/M, Z3.D, Z0.D
fmul z0.d, p0/m, z0.d, z4.d
FMUL Z0.D, P0/M, Z0.D, Z4.D
fmul z0.d, p0/m, z0.d, z31.d
FMUL Z0.D, P0/M, Z0.D, Z31.D
fmul z0.h, p0/m, z0.h, #0.5
FMUL Z0.H, P0/M, Z0.H, #0.5
fmul z0.h, p0/m, z0.h, #0.50000
fmul z0.h, p0/m, z0.h, #5.0000000000e-01
fmul z1.h, p0/m, z1.h, #0.5
FMUL Z1.H, P0/M, Z1.H, #0.5
fmul z1.h, p0/m, z1.h, #0.50000
fmul z1.h, p0/m, z1.h, #5.0000000000e-01
fmul z31.h, p0/m, z31.h, #0.5
FMUL Z31.H, P0/M, Z31.H, #0.5
fmul z31.h, p0/m, z31.h, #0.50000
fmul z31.h, p0/m, z31.h, #5.0000000000e-01
fmul z0.h, p2/m, z0.h, #0.5
FMUL Z0.H, P2/M, Z0.H, #0.5
fmul z0.h, p2/m, z0.h, #0.50000
fmul z0.h, p2/m, z0.h, #5.0000000000e-01
fmul z0.h, p7/m, z0.h, #0.5
FMUL Z0.H, P7/M, Z0.H, #0.5
fmul z0.h, p7/m, z0.h, #0.50000
fmul z0.h, p7/m, z0.h, #5.0000000000e-01
fmul z3.h, p0/m, z3.h, #0.5
FMUL Z3.H, P0/M, Z3.H, #0.5
fmul z3.h, p0/m, z3.h, #0.50000
fmul z3.h, p0/m, z3.h, #5.0000000000e-01
fmul z0.h, p0/m, z0.h, #2.0
FMUL Z0.H, P0/M, Z0.H, #2.0
fmul z0.h, p0/m, z0.h, #2.00000
fmul z0.h, p0/m, z0.h, #2.0000000000e+00
fmul z0.s, p0/m, z0.s, #0.5
FMUL Z0.S, P0/M, Z0.S, #0.5
fmul z0.s, p0/m, z0.s, #0.50000
fmul z0.s, p0/m, z0.s, #5.0000000000e-01
fmul z1.s, p0/m, z1.s, #0.5
FMUL Z1.S, P0/M, Z1.S, #0.5
fmul z1.s, p0/m, z1.s, #0.50000
fmul z1.s, p0/m, z1.s, #5.0000000000e-01
fmul z31.s, p0/m, z31.s, #0.5
FMUL Z31.S, P0/M, Z31.S, #0.5
fmul z31.s, p0/m, z31.s, #0.50000
fmul z31.s, p0/m, z31.s, #5.0000000000e-01
fmul z0.s, p2/m, z0.s, #0.5
FMUL Z0.S, P2/M, Z0.S, #0.5
fmul z0.s, p2/m, z0.s, #0.50000
fmul z0.s, p2/m, z0.s, #5.0000000000e-01
fmul z0.s, p7/m, z0.s, #0.5
FMUL Z0.S, P7/M, Z0.S, #0.5
fmul z0.s, p7/m, z0.s, #0.50000
fmul z0.s, p7/m, z0.s, #5.0000000000e-01
fmul z3.s, p0/m, z3.s, #0.5
FMUL Z3.S, P0/M, Z3.S, #0.5
fmul z3.s, p0/m, z3.s, #0.50000
fmul z3.s, p0/m, z3.s, #5.0000000000e-01
fmul z0.s, p0/m, z0.s, #2.0
FMUL Z0.S, P0/M, Z0.S, #2.0
fmul z0.s, p0/m, z0.s, #2.00000
fmul z0.s, p0/m, z0.s, #2.0000000000e+00
fmul z0.d, p0/m, z0.d, #0.5
FMUL Z0.D, P0/M, Z0.D, #0.5
fmul z0.d, p0/m, z0.d, #0.50000
fmul z0.d, p0/m, z0.d, #5.0000000000e-01
fmul z1.d, p0/m, z1.d, #0.5
FMUL Z1.D, P0/M, Z1.D, #0.5
fmul z1.d, p0/m, z1.d, #0.50000
fmul z1.d, p0/m, z1.d, #5.0000000000e-01
fmul z31.d, p0/m, z31.d, #0.5
FMUL Z31.D, P0/M, Z31.D, #0.5
fmul z31.d, p0/m, z31.d, #0.50000
fmul z31.d, p0/m, z31.d, #5.0000000000e-01
fmul z0.d, p2/m, z0.d, #0.5
FMUL Z0.D, P2/M, Z0.D, #0.5
fmul z0.d, p2/m, z0.d, #0.50000
fmul z0.d, p2/m, z0.d, #5.0000000000e-01
fmul z0.d, p7/m, z0.d, #0.5
FMUL Z0.D, P7/M, Z0.D, #0.5
fmul z0.d, p7/m, z0.d, #0.50000
fmul z0.d, p7/m, z0.d, #5.0000000000e-01
fmul z3.d, p0/m, z3.d, #0.5
FMUL Z3.D, P0/M, Z3.D, #0.5
fmul z3.d, p0/m, z3.d, #0.50000
fmul z3.d, p0/m, z3.d, #5.0000000000e-01
fmul z0.d, p0/m, z0.d, #2.0
FMUL Z0.D, P0/M, Z0.D, #2.0
fmul z0.d, p0/m, z0.d, #2.00000
fmul z0.d, p0/m, z0.d, #2.0000000000e+00
fmul z0.h, z0.h, z0.h[0]
FMUL Z0.H, Z0.H, Z0.H[0]
fmul z1.h, z0.h, z0.h[0]
FMUL Z1.H, Z0.H, Z0.H[0]
fmul z31.h, z0.h, z0.h[0]
FMUL Z31.H, Z0.H, Z0.H[0]
fmul z0.h, z2.h, z0.h[0]
FMUL Z0.H, Z2.H, Z0.H[0]
fmul z0.h, z31.h, z0.h[0]
FMUL Z0.H, Z31.H, Z0.H[0]
fmul z0.h, z0.h, z3.h[0]
FMUL Z0.H, Z0.H, Z3.H[0]
fmul z0.h, z0.h, z7.h[0]
FMUL Z0.H, Z0.H, Z7.H[0]
fmul z0.h, z0.h, z0.h[1]
FMUL Z0.H, Z0.H, Z0.H[1]
fmul z0.h, z0.h, z4.h[1]
FMUL Z0.H, Z0.H, Z4.H[1]
fmul z0.h, z0.h, z3.h[4]
FMUL Z0.H, Z0.H, Z3.H[4]
fmul z0.h, z0.h, z0.h[7]
FMUL Z0.H, Z0.H, Z0.H[7]
fmul z0.h, z0.h, z5.h[7]
FMUL Z0.H, Z0.H, Z5.H[7]
fmul z0.s, z0.s, z0.s[0]
FMUL Z0.S, Z0.S, Z0.S[0]
fmul z1.s, z0.s, z0.s[0]
FMUL Z1.S, Z0.S, Z0.S[0]
fmul z31.s, z0.s, z0.s[0]
FMUL Z31.S, Z0.S, Z0.S[0]
fmul z0.s, z2.s, z0.s[0]
FMUL Z0.S, Z2.S, Z0.S[0]
fmul z0.s, z31.s, z0.s[0]
FMUL Z0.S, Z31.S, Z0.S[0]
fmul z0.s, z0.s, z3.s[0]
FMUL Z0.S, Z0.S, Z3.S[0]
fmul z0.s, z0.s, z7.s[0]
FMUL Z0.S, Z0.S, Z7.S[0]
fmul z0.s, z0.s, z0.s[1]
FMUL Z0.S, Z0.S, Z0.S[1]
fmul z0.s, z0.s, z4.s[1]
FMUL Z0.S, Z0.S, Z4.S[1]
fmul z0.s, z0.s, z3.s[2]
FMUL Z0.S, Z0.S, Z3.S[2]
fmul z0.s, z0.s, z0.s[3]
FMUL Z0.S, Z0.S, Z0.S[3]
fmul z0.s, z0.s, z5.s[3]
FMUL Z0.S, Z0.S, Z5.S[3]
fmul z0.d, z0.d, z0.d[0]
FMUL Z0.D, Z0.D, Z0.D[0]
fmul z1.d, z0.d, z0.d[0]
FMUL Z1.D, Z0.D, Z0.D[0]
fmul z31.d, z0.d, z0.d[0]
FMUL Z31.D, Z0.D, Z0.D[0]
fmul z0.d, z2.d, z0.d[0]
FMUL Z0.D, Z2.D, Z0.D[0]
fmul z0.d, z31.d, z0.d[0]
FMUL Z0.D, Z31.D, Z0.D[0]
fmul z0.d, z0.d, z3.d[0]
FMUL Z0.D, Z0.D, Z3.D[0]
fmul z0.d, z0.d, z15.d[0]
FMUL Z0.D, Z0.D, Z15.D[0]
fmul z0.d, z0.d, z0.d[1]
FMUL Z0.D, Z0.D, Z0.D[1]
fmul z0.d, z0.d, z11.d[1]
FMUL Z0.D, Z0.D, Z11.D[1]
fmulx z0.h, p0/m, z0.h, z0.h
FMULX Z0.H, P0/M, Z0.H, Z0.H
fmulx z1.h, p0/m, z1.h, z0.h
FMULX Z1.H, P0/M, Z1.H, Z0.H
fmulx z31.h, p0/m, z31.h, z0.h
FMULX Z31.H, P0/M, Z31.H, Z0.H
fmulx z0.h, p2/m, z0.h, z0.h
FMULX Z0.H, P2/M, Z0.H, Z0.H
fmulx z0.h, p7/m, z0.h, z0.h
FMULX Z0.H, P7/M, Z0.H, Z0.H
fmulx z3.h, p0/m, z3.h, z0.h
FMULX Z3.H, P0/M, Z3.H, Z0.H
fmulx z0.h, p0/m, z0.h, z4.h
FMULX Z0.H, P0/M, Z0.H, Z4.H
fmulx z0.h, p0/m, z0.h, z31.h
FMULX Z0.H, P0/M, Z0.H, Z31.H
fmulx z0.s, p0/m, z0.s, z0.s
FMULX Z0.S, P0/M, Z0.S, Z0.S
fmulx z1.s, p0/m, z1.s, z0.s
FMULX Z1.S, P0/M, Z1.S, Z0.S
fmulx z31.s, p0/m, z31.s, z0.s
FMULX Z31.S, P0/M, Z31.S, Z0.S
fmulx z0.s, p2/m, z0.s, z0.s
FMULX Z0.S, P2/M, Z0.S, Z0.S
fmulx z0.s, p7/m, z0.s, z0.s
FMULX Z0.S, P7/M, Z0.S, Z0.S
fmulx z3.s, p0/m, z3.s, z0.s
FMULX Z3.S, P0/M, Z3.S, Z0.S
fmulx z0.s, p0/m, z0.s, z4.s
FMULX Z0.S, P0/M, Z0.S, Z4.S
fmulx z0.s, p0/m, z0.s, z31.s
FMULX Z0.S, P0/M, Z0.S, Z31.S
fmulx z0.d, p0/m, z0.d, z0.d
FMULX Z0.D, P0/M, Z0.D, Z0.D
fmulx z1.d, p0/m, z1.d, z0.d
FMULX Z1.D, P0/M, Z1.D, Z0.D
fmulx z31.d, p0/m, z31.d, z0.d
FMULX Z31.D, P0/M, Z31.D, Z0.D
fmulx z0.d, p2/m, z0.d, z0.d
FMULX Z0.D, P2/M, Z0.D, Z0.D
fmulx z0.d, p7/m, z0.d, z0.d
FMULX Z0.D, P7/M, Z0.D, Z0.D
fmulx z3.d, p0/m, z3.d, z0.d
FMULX Z3.D, P0/M, Z3.D, Z0.D
fmulx z0.d, p0/m, z0.d, z4.d
FMULX Z0.D, P0/M, Z0.D, Z4.D
fmulx z0.d, p0/m, z0.d, z31.d
FMULX Z0.D, P0/M, Z0.D, Z31.D
fneg z0.h, p0/m, z0.h
FNEG Z0.H, P0/M, Z0.H
fneg z1.h, p0/m, z0.h
FNEG Z1.H, P0/M, Z0.H
fneg z31.h, p0/m, z0.h
FNEG Z31.H, P0/M, Z0.H
fneg z0.h, p2/m, z0.h
FNEG Z0.H, P2/M, Z0.H
fneg z0.h, p7/m, z0.h
FNEG Z0.H, P7/M, Z0.H
fneg z0.h, p0/m, z3.h
FNEG Z0.H, P0/M, Z3.H
fneg z0.h, p0/m, z31.h
FNEG Z0.H, P0/M, Z31.H
fneg z0.s, p0/m, z0.s
FNEG Z0.S, P0/M, Z0.S
fneg z1.s, p0/m, z0.s
FNEG Z1.S, P0/M, Z0.S
fneg z31.s, p0/m, z0.s
FNEG Z31.S, P0/M, Z0.S
fneg z0.s, p2/m, z0.s
FNEG Z0.S, P2/M, Z0.S
fneg z0.s, p7/m, z0.s
FNEG Z0.S, P7/M, Z0.S
fneg z0.s, p0/m, z3.s
FNEG Z0.S, P0/M, Z3.S
fneg z0.s, p0/m, z31.s
FNEG Z0.S, P0/M, Z31.S
fneg z0.d, p0/m, z0.d
FNEG Z0.D, P0/M, Z0.D
fneg z1.d, p0/m, z0.d
FNEG Z1.D, P0/M, Z0.D
fneg z31.d, p0/m, z0.d
FNEG Z31.D, P0/M, Z0.D
fneg z0.d, p2/m, z0.d
FNEG Z0.D, P2/M, Z0.D
fneg z0.d, p7/m, z0.d
FNEG Z0.D, P7/M, Z0.D
fneg z0.d, p0/m, z3.d
FNEG Z0.D, P0/M, Z3.D
fneg z0.d, p0/m, z31.d
FNEG Z0.D, P0/M, Z31.D
fnmad z0.h, p0/m, z0.h, z0.h
FNMAD Z0.H, P0/M, Z0.H, Z0.H
fnmad z1.h, p0/m, z0.h, z0.h
FNMAD Z1.H, P0/M, Z0.H, Z0.H
fnmad z31.h, p0/m, z0.h, z0.h
FNMAD Z31.H, P0/M, Z0.H, Z0.H
fnmad z0.h, p2/m, z0.h, z0.h
FNMAD Z0.H, P2/M, Z0.H, Z0.H
fnmad z0.h, p7/m, z0.h, z0.h
FNMAD Z0.H, P7/M, Z0.H, Z0.H
fnmad z0.h, p0/m, z3.h, z0.h
FNMAD Z0.H, P0/M, Z3.H, Z0.H
fnmad z0.h, p0/m, z31.h, z0.h
FNMAD Z0.H, P0/M, Z31.H, Z0.H
fnmad z0.h, p0/m, z0.h, z4.h
FNMAD Z0.H, P0/M, Z0.H, Z4.H
fnmad z0.h, p0/m, z0.h, z31.h
FNMAD Z0.H, P0/M, Z0.H, Z31.H
fnmad z0.s, p0/m, z0.s, z0.s
FNMAD Z0.S, P0/M, Z0.S, Z0.S
fnmad z1.s, p0/m, z0.s, z0.s
FNMAD Z1.S, P0/M, Z0.S, Z0.S
fnmad z31.s, p0/m, z0.s, z0.s
FNMAD Z31.S, P0/M, Z0.S, Z0.S
fnmad z0.s, p2/m, z0.s, z0.s
FNMAD Z0.S, P2/M, Z0.S, Z0.S
fnmad z0.s, p7/m, z0.s, z0.s
FNMAD Z0.S, P7/M, Z0.S, Z0.S
fnmad z0.s, p0/m, z3.s, z0.s
FNMAD Z0.S, P0/M, Z3.S, Z0.S
fnmad z0.s, p0/m, z31.s, z0.s
FNMAD Z0.S, P0/M, Z31.S, Z0.S
fnmad z0.s, p0/m, z0.s, z4.s
FNMAD Z0.S, P0/M, Z0.S, Z4.S
fnmad z0.s, p0/m, z0.s, z31.s
FNMAD Z0.S, P0/M, Z0.S, Z31.S
fnmad z0.d, p0/m, z0.d, z0.d
FNMAD Z0.D, P0/M, Z0.D, Z0.D
fnmad z1.d, p0/m, z0.d, z0.d
FNMAD Z1.D, P0/M, Z0.D, Z0.D
fnmad z31.d, p0/m, z0.d, z0.d
FNMAD Z31.D, P0/M, Z0.D, Z0.D
fnmad z0.d, p2/m, z0.d, z0.d
FNMAD Z0.D, P2/M, Z0.D, Z0.D
fnmad z0.d, p7/m, z0.d, z0.d
FNMAD Z0.D, P7/M, Z0.D, Z0.D
fnmad z0.d, p0/m, z3.d, z0.d
FNMAD Z0.D, P0/M, Z3.D, Z0.D
fnmad z0.d, p0/m, z31.d, z0.d
FNMAD Z0.D, P0/M, Z31.D, Z0.D
fnmad z0.d, p0/m, z0.d, z4.d
FNMAD Z0.D, P0/M, Z0.D, Z4.D
fnmad z0.d, p0/m, z0.d, z31.d
FNMAD Z0.D, P0/M, Z0.D, Z31.D
fnmla z0.h, p0/m, z0.h, z0.h
FNMLA Z0.H, P0/M, Z0.H, Z0.H
fnmla z1.h, p0/m, z0.h, z0.h
FNMLA Z1.H, P0/M, Z0.H, Z0.H
fnmla z31.h, p0/m, z0.h, z0.h
FNMLA Z31.H, P0/M, Z0.H, Z0.H
fnmla z0.h, p2/m, z0.h, z0.h
FNMLA Z0.H, P2/M, Z0.H, Z0.H
fnmla z0.h, p7/m, z0.h, z0.h
FNMLA Z0.H, P7/M, Z0.H, Z0.H
fnmla z0.h, p0/m, z3.h, z0.h
FNMLA Z0.H, P0/M, Z3.H, Z0.H
fnmla z0.h, p0/m, z31.h, z0.h
FNMLA Z0.H, P0/M, Z31.H, Z0.H
fnmla z0.h, p0/m, z0.h, z4.h
FNMLA Z0.H, P0/M, Z0.H, Z4.H
fnmla z0.h, p0/m, z0.h, z31.h
FNMLA Z0.H, P0/M, Z0.H, Z31.H
fnmla z0.s, p0/m, z0.s, z0.s
FNMLA Z0.S, P0/M, Z0.S, Z0.S
fnmla z1.s, p0/m, z0.s, z0.s
FNMLA Z1.S, P0/M, Z0.S, Z0.S
fnmla z31.s, p0/m, z0.s, z0.s
FNMLA Z31.S, P0/M, Z0.S, Z0.S
fnmla z0.s, p2/m, z0.s, z0.s
FNMLA Z0.S, P2/M, Z0.S, Z0.S
fnmla z0.s, p7/m, z0.s, z0.s
FNMLA Z0.S, P7/M, Z0.S, Z0.S
fnmla z0.s, p0/m, z3.s, z0.s
FNMLA Z0.S, P0/M, Z3.S, Z0.S
fnmla z0.s, p0/m, z31.s, z0.s
FNMLA Z0.S, P0/M, Z31.S, Z0.S
fnmla z0.s, p0/m, z0.s, z4.s
FNMLA Z0.S, P0/M, Z0.S, Z4.S
fnmla z0.s, p0/m, z0.s, z31.s
FNMLA Z0.S, P0/M, Z0.S, Z31.S
fnmla z0.d, p0/m, z0.d, z0.d
FNMLA Z0.D, P0/M, Z0.D, Z0.D
fnmla z1.d, p0/m, z0.d, z0.d
FNMLA Z1.D, P0/M, Z0.D, Z0.D
fnmla z31.d, p0/m, z0.d, z0.d
FNMLA Z31.D, P0/M, Z0.D, Z0.D
fnmla z0.d, p2/m, z0.d, z0.d
FNMLA Z0.D, P2/M, Z0.D, Z0.D
fnmla z0.d, p7/m, z0.d, z0.d
FNMLA Z0.D, P7/M, Z0.D, Z0.D
fnmla z0.d, p0/m, z3.d, z0.d
FNMLA Z0.D, P0/M, Z3.D, Z0.D
fnmla z0.d, p0/m, z31.d, z0.d
FNMLA Z0.D, P0/M, Z31.D, Z0.D
fnmla z0.d, p0/m, z0.d, z4.d
FNMLA Z0.D, P0/M, Z0.D, Z4.D
fnmla z0.d, p0/m, z0.d, z31.d
FNMLA Z0.D, P0/M, Z0.D, Z31.D
fnmls z0.h, p0/m, z0.h, z0.h
FNMLS Z0.H, P0/M, Z0.H, Z0.H
fnmls z1.h, p0/m, z0.h, z0.h
FNMLS Z1.H, P0/M, Z0.H, Z0.H
fnmls z31.h, p0/m, z0.h, z0.h
FNMLS Z31.H, P0/M, Z0.H, Z0.H
fnmls z0.h, p2/m, z0.h, z0.h
FNMLS Z0.H, P2/M, Z0.H, Z0.H
fnmls z0.h, p7/m, z0.h, z0.h
FNMLS Z0.H, P7/M, Z0.H, Z0.H
fnmls z0.h, p0/m, z3.h, z0.h
FNMLS Z0.H, P0/M, Z3.H, Z0.H
fnmls z0.h, p0/m, z31.h, z0.h
FNMLS Z0.H, P0/M, Z31.H, Z0.H
fnmls z0.h, p0/m, z0.h, z4.h
FNMLS Z0.H, P0/M, Z0.H, Z4.H
fnmls z0.h, p0/m, z0.h, z31.h
FNMLS Z0.H, P0/M, Z0.H, Z31.H
fnmls z0.s, p0/m, z0.s, z0.s
FNMLS Z0.S, P0/M, Z0.S, Z0.S
fnmls z1.s, p0/m, z0.s, z0.s
FNMLS Z1.S, P0/M, Z0.S, Z0.S
fnmls z31.s, p0/m, z0.s, z0.s
FNMLS Z31.S, P0/M, Z0.S, Z0.S
fnmls z0.s, p2/m, z0.s, z0.s
FNMLS Z0.S, P2/M, Z0.S, Z0.S
fnmls z0.s, p7/m, z0.s, z0.s
FNMLS Z0.S, P7/M, Z0.S, Z0.S
fnmls z0.s, p0/m, z3.s, z0.s
FNMLS Z0.S, P0/M, Z3.S, Z0.S
fnmls z0.s, p0/m, z31.s, z0.s
FNMLS Z0.S, P0/M, Z31.S, Z0.S
fnmls z0.s, p0/m, z0.s, z4.s
FNMLS Z0.S, P0/M, Z0.S, Z4.S
fnmls z0.s, p0/m, z0.s, z31.s
FNMLS Z0.S, P0/M, Z0.S, Z31.S
fnmls z0.d, p0/m, z0.d, z0.d
FNMLS Z0.D, P0/M, Z0.D, Z0.D
fnmls z1.d, p0/m, z0.d, z0.d
FNMLS Z1.D, P0/M, Z0.D, Z0.D
fnmls z31.d, p0/m, z0.d, z0.d
FNMLS Z31.D, P0/M, Z0.D, Z0.D
fnmls z0.d, p2/m, z0.d, z0.d
FNMLS Z0.D, P2/M, Z0.D, Z0.D
fnmls z0.d, p7/m, z0.d, z0.d
FNMLS Z0.D, P7/M, Z0.D, Z0.D
fnmls z0.d, p0/m, z3.d, z0.d
FNMLS Z0.D, P0/M, Z3.D, Z0.D
fnmls z0.d, p0/m, z31.d, z0.d
FNMLS Z0.D, P0/M, Z31.D, Z0.D
fnmls z0.d, p0/m, z0.d, z4.d
FNMLS Z0.D, P0/M, Z0.D, Z4.D
fnmls z0.d, p0/m, z0.d, z31.d
FNMLS Z0.D, P0/M, Z0.D, Z31.D
fnmsb z0.h, p0/m, z0.h, z0.h
FNMSB Z0.H, P0/M, Z0.H, Z0.H
fnmsb z1.h, p0/m, z0.h, z0.h
FNMSB Z1.H, P0/M, Z0.H, Z0.H
fnmsb z31.h, p0/m, z0.h, z0.h
FNMSB Z31.H, P0/M, Z0.H, Z0.H
fnmsb z0.h, p2/m, z0.h, z0.h
FNMSB Z0.H, P2/M, Z0.H, Z0.H
fnmsb z0.h, p7/m, z0.h, z0.h
FNMSB Z0.H, P7/M, Z0.H, Z0.H
fnmsb z0.h, p0/m, z3.h, z0.h
FNMSB Z0.H, P0/M, Z3.H, Z0.H
fnmsb z0.h, p0/m, z31.h, z0.h
FNMSB Z0.H, P0/M, Z31.H, Z0.H
fnmsb z0.h, p0/m, z0.h, z4.h
FNMSB Z0.H, P0/M, Z0.H, Z4.H
fnmsb z0.h, p0/m, z0.h, z31.h
FNMSB Z0.H, P0/M, Z0.H, Z31.H
fnmsb z0.s, p0/m, z0.s, z0.s
FNMSB Z0.S, P0/M, Z0.S, Z0.S
fnmsb z1.s, p0/m, z0.s, z0.s
FNMSB Z1.S, P0/M, Z0.S, Z0.S
fnmsb z31.s, p0/m, z0.s, z0.s
FNMSB Z31.S, P0/M, Z0.S, Z0.S
fnmsb z0.s, p2/m, z0.s, z0.s
FNMSB Z0.S, P2/M, Z0.S, Z0.S
fnmsb z0.s, p7/m, z0.s, z0.s
FNMSB Z0.S, P7/M, Z0.S, Z0.S
fnmsb z0.s, p0/m, z3.s, z0.s
FNMSB Z0.S, P0/M, Z3.S, Z0.S
fnmsb z0.s, p0/m, z31.s, z0.s
FNMSB Z0.S, P0/M, Z31.S, Z0.S
fnmsb z0.s, p0/m, z0.s, z4.s
FNMSB Z0.S, P0/M, Z0.S, Z4.S
fnmsb z0.s, p0/m, z0.s, z31.s
FNMSB Z0.S, P0/M, Z0.S, Z31.S
fnmsb z0.d, p0/m, z0.d, z0.d
FNMSB Z0.D, P0/M, Z0.D, Z0.D
fnmsb z1.d, p0/m, z0.d, z0.d
FNMSB Z1.D, P0/M, Z0.D, Z0.D
fnmsb z31.d, p0/m, z0.d, z0.d
FNMSB Z31.D, P0/M, Z0.D, Z0.D
fnmsb z0.d, p2/m, z0.d, z0.d
FNMSB Z0.D, P2/M, Z0.D, Z0.D
fnmsb z0.d, p7/m, z0.d, z0.d
FNMSB Z0.D, P7/M, Z0.D, Z0.D
fnmsb z0.d, p0/m, z3.d, z0.d
FNMSB Z0.D, P0/M, Z3.D, Z0.D
fnmsb z0.d, p0/m, z31.d, z0.d
FNMSB Z0.D, P0/M, Z31.D, Z0.D
fnmsb z0.d, p0/m, z0.d, z4.d
FNMSB Z0.D, P0/M, Z0.D, Z4.D
fnmsb z0.d, p0/m, z0.d, z31.d
FNMSB Z0.D, P0/M, Z0.D, Z31.D
frecpe z0.h, z0.h
FRECPE Z0.H, Z0.H
frecpe z1.h, z0.h
FRECPE Z1.H, Z0.H
frecpe z31.h, z0.h
FRECPE Z31.H, Z0.H
frecpe z0.h, z2.h
FRECPE Z0.H, Z2.H
frecpe z0.h, z31.h
FRECPE Z0.H, Z31.H
frecpe z0.s, z0.s
FRECPE Z0.S, Z0.S
frecpe z1.s, z0.s
FRECPE Z1.S, Z0.S
frecpe z31.s, z0.s
FRECPE Z31.S, Z0.S
frecpe z0.s, z2.s
FRECPE Z0.S, Z2.S
frecpe z0.s, z31.s
FRECPE Z0.S, Z31.S
frecpe z0.d, z0.d
FRECPE Z0.D, Z0.D
frecpe z1.d, z0.d
FRECPE Z1.D, Z0.D
frecpe z31.d, z0.d
FRECPE Z31.D, Z0.D
frecpe z0.d, z2.d
FRECPE Z0.D, Z2.D
frecpe z0.d, z31.d
FRECPE Z0.D, Z31.D
frecps z0.h, z0.h, z0.h
FRECPS Z0.H, Z0.H, Z0.H
frecps z1.h, z0.h, z0.h
FRECPS Z1.H, Z0.H, Z0.H
frecps z31.h, z0.h, z0.h
FRECPS Z31.H, Z0.H, Z0.H
frecps z0.h, z2.h, z0.h
FRECPS Z0.H, Z2.H, Z0.H
frecps z0.h, z31.h, z0.h
FRECPS Z0.H, Z31.H, Z0.H
frecps z0.h, z0.h, z3.h
FRECPS Z0.H, Z0.H, Z3.H
frecps z0.h, z0.h, z31.h
FRECPS Z0.H, Z0.H, Z31.H
frecps z0.s, z0.s, z0.s
FRECPS Z0.S, Z0.S, Z0.S
frecps z1.s, z0.s, z0.s
FRECPS Z1.S, Z0.S, Z0.S
frecps z31.s, z0.s, z0.s
FRECPS Z31.S, Z0.S, Z0.S
frecps z0.s, z2.s, z0.s
FRECPS Z0.S, Z2.S, Z0.S
frecps z0.s, z31.s, z0.s
FRECPS Z0.S, Z31.S, Z0.S
frecps z0.s, z0.s, z3.s
FRECPS Z0.S, Z0.S, Z3.S
frecps z0.s, z0.s, z31.s
FRECPS Z0.S, Z0.S, Z31.S
frecps z0.d, z0.d, z0.d
FRECPS Z0.D, Z0.D, Z0.D
frecps z1.d, z0.d, z0.d
FRECPS Z1.D, Z0.D, Z0.D
frecps z31.d, z0.d, z0.d
FRECPS Z31.D, Z0.D, Z0.D
frecps z0.d, z2.d, z0.d
FRECPS Z0.D, Z2.D, Z0.D
frecps z0.d, z31.d, z0.d
FRECPS Z0.D, Z31.D, Z0.D
frecps z0.d, z0.d, z3.d
FRECPS Z0.D, Z0.D, Z3.D
frecps z0.d, z0.d, z31.d
FRECPS Z0.D, Z0.D, Z31.D
frecpx z0.h, p0/m, z0.h
FRECPX Z0.H, P0/M, Z0.H
frecpx z1.h, p0/m, z0.h
FRECPX Z1.H, P0/M, Z0.H
frecpx z31.h, p0/m, z0.h
FRECPX Z31.H, P0/M, Z0.H
frecpx z0.h, p2/m, z0.h
FRECPX Z0.H, P2/M, Z0.H
frecpx z0.h, p7/m, z0.h
FRECPX Z0.H, P7/M, Z0.H
frecpx z0.h, p0/m, z3.h
FRECPX Z0.H, P0/M, Z3.H
frecpx z0.h, p0/m, z31.h
FRECPX Z0.H, P0/M, Z31.H
frecpx z0.s, p0/m, z0.s
FRECPX Z0.S, P0/M, Z0.S
frecpx z1.s, p0/m, z0.s
FRECPX Z1.S, P0/M, Z0.S
frecpx z31.s, p0/m, z0.s
FRECPX Z31.S, P0/M, Z0.S
frecpx z0.s, p2/m, z0.s
FRECPX Z0.S, P2/M, Z0.S
frecpx z0.s, p7/m, z0.s
FRECPX Z0.S, P7/M, Z0.S
frecpx z0.s, p0/m, z3.s
FRECPX Z0.S, P0/M, Z3.S
frecpx z0.s, p0/m, z31.s
FRECPX Z0.S, P0/M, Z31.S
frecpx z0.d, p0/m, z0.d
FRECPX Z0.D, P0/M, Z0.D
frecpx z1.d, p0/m, z0.d
FRECPX Z1.D, P0/M, Z0.D
frecpx z31.d, p0/m, z0.d
FRECPX Z31.D, P0/M, Z0.D
frecpx z0.d, p2/m, z0.d
FRECPX Z0.D, P2/M, Z0.D
frecpx z0.d, p7/m, z0.d
FRECPX Z0.D, P7/M, Z0.D
frecpx z0.d, p0/m, z3.d
FRECPX Z0.D, P0/M, Z3.D
frecpx z0.d, p0/m, z31.d
FRECPX Z0.D, P0/M, Z31.D
frinta z0.h, p0/m, z0.h
FRINTA Z0.H, P0/M, Z0.H
frinta z1.h, p0/m, z0.h
FRINTA Z1.H, P0/M, Z0.H
frinta z31.h, p0/m, z0.h
FRINTA Z31.H, P0/M, Z0.H
frinta z0.h, p2/m, z0.h
FRINTA Z0.H, P2/M, Z0.H
frinta z0.h, p7/m, z0.h
FRINTA Z0.H, P7/M, Z0.H
frinta z0.h, p0/m, z3.h
FRINTA Z0.H, P0/M, Z3.H
frinta z0.h, p0/m, z31.h
FRINTA Z0.H, P0/M, Z31.H
frinta z0.s, p0/m, z0.s
FRINTA Z0.S, P0/M, Z0.S
frinta z1.s, p0/m, z0.s
FRINTA Z1.S, P0/M, Z0.S
frinta z31.s, p0/m, z0.s
FRINTA Z31.S, P0/M, Z0.S
frinta z0.s, p2/m, z0.s
FRINTA Z0.S, P2/M, Z0.S
frinta z0.s, p7/m, z0.s
FRINTA Z0.S, P7/M, Z0.S
frinta z0.s, p0/m, z3.s
FRINTA Z0.S, P0/M, Z3.S
frinta z0.s, p0/m, z31.s
FRINTA Z0.S, P0/M, Z31.S
frinta z0.d, p0/m, z0.d
FRINTA Z0.D, P0/M, Z0.D
frinta z1.d, p0/m, z0.d
FRINTA Z1.D, P0/M, Z0.D
frinta z31.d, p0/m, z0.d
FRINTA Z31.D, P0/M, Z0.D
frinta z0.d, p2/m, z0.d
FRINTA Z0.D, P2/M, Z0.D
frinta z0.d, p7/m, z0.d
FRINTA Z0.D, P7/M, Z0.D
frinta z0.d, p0/m, z3.d
FRINTA Z0.D, P0/M, Z3.D
frinta z0.d, p0/m, z31.d
FRINTA Z0.D, P0/M, Z31.D
frinti z0.h, p0/m, z0.h
FRINTI Z0.H, P0/M, Z0.H
frinti z1.h, p0/m, z0.h
FRINTI Z1.H, P0/M, Z0.H
frinti z31.h, p0/m, z0.h
FRINTI Z31.H, P0/M, Z0.H
frinti z0.h, p2/m, z0.h
FRINTI Z0.H, P2/M, Z0.H
frinti z0.h, p7/m, z0.h
FRINTI Z0.H, P7/M, Z0.H
frinti z0.h, p0/m, z3.h
FRINTI Z0.H, P0/M, Z3.H
frinti z0.h, p0/m, z31.h
FRINTI Z0.H, P0/M, Z31.H
frinti z0.s, p0/m, z0.s
FRINTI Z0.S, P0/M, Z0.S
frinti z1.s, p0/m, z0.s
FRINTI Z1.S, P0/M, Z0.S
frinti z31.s, p0/m, z0.s
FRINTI Z31.S, P0/M, Z0.S
frinti z0.s, p2/m, z0.s
FRINTI Z0.S, P2/M, Z0.S
frinti z0.s, p7/m, z0.s
FRINTI Z0.S, P7/M, Z0.S
frinti z0.s, p0/m, z3.s
FRINTI Z0.S, P0/M, Z3.S
frinti z0.s, p0/m, z31.s
FRINTI Z0.S, P0/M, Z31.S
frinti z0.d, p0/m, z0.d
FRINTI Z0.D, P0/M, Z0.D
frinti z1.d, p0/m, z0.d
FRINTI Z1.D, P0/M, Z0.D
frinti z31.d, p0/m, z0.d
FRINTI Z31.D, P0/M, Z0.D
frinti z0.d, p2/m, z0.d
FRINTI Z0.D, P2/M, Z0.D
frinti z0.d, p7/m, z0.d
FRINTI Z0.D, P7/M, Z0.D
frinti z0.d, p0/m, z3.d
FRINTI Z0.D, P0/M, Z3.D
frinti z0.d, p0/m, z31.d
FRINTI Z0.D, P0/M, Z31.D
frintm z0.h, p0/m, z0.h
FRINTM Z0.H, P0/M, Z0.H
frintm z1.h, p0/m, z0.h
FRINTM Z1.H, P0/M, Z0.H
frintm z31.h, p0/m, z0.h
FRINTM Z31.H, P0/M, Z0.H
frintm z0.h, p2/m, z0.h
FRINTM Z0.H, P2/M, Z0.H
frintm z0.h, p7/m, z0.h
FRINTM Z0.H, P7/M, Z0.H
frintm z0.h, p0/m, z3.h
FRINTM Z0.H, P0/M, Z3.H
frintm z0.h, p0/m, z31.h
FRINTM Z0.H, P0/M, Z31.H
frintm z0.s, p0/m, z0.s
FRINTM Z0.S, P0/M, Z0.S
frintm z1.s, p0/m, z0.s
FRINTM Z1.S, P0/M, Z0.S
frintm z31.s, p0/m, z0.s
FRINTM Z31.S, P0/M, Z0.S
frintm z0.s, p2/m, z0.s
FRINTM Z0.S, P2/M, Z0.S
frintm z0.s, p7/m, z0.s
FRINTM Z0.S, P7/M, Z0.S
frintm z0.s, p0/m, z3.s
FRINTM Z0.S, P0/M, Z3.S
frintm z0.s, p0/m, z31.s
FRINTM Z0.S, P0/M, Z31.S
frintm z0.d, p0/m, z0.d
FRINTM Z0.D, P0/M, Z0.D
frintm z1.d, p0/m, z0.d
FRINTM Z1.D, P0/M, Z0.D
frintm z31.d, p0/m, z0.d
FRINTM Z31.D, P0/M, Z0.D
frintm z0.d, p2/m, z0.d
FRINTM Z0.D, P2/M, Z0.D
frintm z0.d, p7/m, z0.d
FRINTM Z0.D, P7/M, Z0.D
frintm z0.d, p0/m, z3.d
FRINTM Z0.D, P0/M, Z3.D
frintm z0.d, p0/m, z31.d
FRINTM Z0.D, P0/M, Z31.D
frintn z0.h, p0/m, z0.h
FRINTN Z0.H, P0/M, Z0.H
frintn z1.h, p0/m, z0.h
FRINTN Z1.H, P0/M, Z0.H
frintn z31.h, p0/m, z0.h
FRINTN Z31.H, P0/M, Z0.H
frintn z0.h, p2/m, z0.h
FRINTN Z0.H, P2/M, Z0.H
frintn z0.h, p7/m, z0.h
FRINTN Z0.H, P7/M, Z0.H
frintn z0.h, p0/m, z3.h
FRINTN Z0.H, P0/M, Z3.H
frintn z0.h, p0/m, z31.h
FRINTN Z0.H, P0/M, Z31.H
frintn z0.s, p0/m, z0.s
FRINTN Z0.S, P0/M, Z0.S
frintn z1.s, p0/m, z0.s
FRINTN Z1.S, P0/M, Z0.S
frintn z31.s, p0/m, z0.s
FRINTN Z31.S, P0/M, Z0.S
frintn z0.s, p2/m, z0.s
FRINTN Z0.S, P2/M, Z0.S
frintn z0.s, p7/m, z0.s
FRINTN Z0.S, P7/M, Z0.S
frintn z0.s, p0/m, z3.s
FRINTN Z0.S, P0/M, Z3.S
frintn z0.s, p0/m, z31.s
FRINTN Z0.S, P0/M, Z31.S
frintn z0.d, p0/m, z0.d
FRINTN Z0.D, P0/M, Z0.D
frintn z1.d, p0/m, z0.d
FRINTN Z1.D, P0/M, Z0.D
frintn z31.d, p0/m, z0.d
FRINTN Z31.D, P0/M, Z0.D
frintn z0.d, p2/m, z0.d
FRINTN Z0.D, P2/M, Z0.D
frintn z0.d, p7/m, z0.d
FRINTN Z0.D, P7/M, Z0.D
frintn z0.d, p0/m, z3.d
FRINTN Z0.D, P0/M, Z3.D
frintn z0.d, p0/m, z31.d
FRINTN Z0.D, P0/M, Z31.D
frintp z0.h, p0/m, z0.h
FRINTP Z0.H, P0/M, Z0.H
frintp z1.h, p0/m, z0.h
FRINTP Z1.H, P0/M, Z0.H
frintp z31.h, p0/m, z0.h
FRINTP Z31.H, P0/M, Z0.H
frintp z0.h, p2/m, z0.h
FRINTP Z0.H, P2/M, Z0.H
frintp z0.h, p7/m, z0.h
FRINTP Z0.H, P7/M, Z0.H
frintp z0.h, p0/m, z3.h
FRINTP Z0.H, P0/M, Z3.H
frintp z0.h, p0/m, z31.h
FRINTP Z0.H, P0/M, Z31.H
frintp z0.s, p0/m, z0.s
FRINTP Z0.S, P0/M, Z0.S
frintp z1.s, p0/m, z0.s
FRINTP Z1.S, P0/M, Z0.S
frintp z31.s, p0/m, z0.s
FRINTP Z31.S, P0/M, Z0.S
frintp z0.s, p2/m, z0.s
FRINTP Z0.S, P2/M, Z0.S
frintp z0.s, p7/m, z0.s
FRINTP Z0.S, P7/M, Z0.S
frintp z0.s, p0/m, z3.s
FRINTP Z0.S, P0/M, Z3.S
frintp z0.s, p0/m, z31.s
FRINTP Z0.S, P0/M, Z31.S
frintp z0.d, p0/m, z0.d
FRINTP Z0.D, P0/M, Z0.D
frintp z1.d, p0/m, z0.d
FRINTP Z1.D, P0/M, Z0.D
frintp z31.d, p0/m, z0.d
FRINTP Z31.D, P0/M, Z0.D
frintp z0.d, p2/m, z0.d
FRINTP Z0.D, P2/M, Z0.D
frintp z0.d, p7/m, z0.d
FRINTP Z0.D, P7/M, Z0.D
frintp z0.d, p0/m, z3.d
FRINTP Z0.D, P0/M, Z3.D
frintp z0.d, p0/m, z31.d
FRINTP Z0.D, P0/M, Z31.D
frintx z0.h, p0/m, z0.h
FRINTX Z0.H, P0/M, Z0.H
frintx z1.h, p0/m, z0.h
FRINTX Z1.H, P0/M, Z0.H
frintx z31.h, p0/m, z0.h
FRINTX Z31.H, P0/M, Z0.H
frintx z0.h, p2/m, z0.h
FRINTX Z0.H, P2/M, Z0.H
frintx z0.h, p7/m, z0.h
FRINTX Z0.H, P7/M, Z0.H
frintx z0.h, p0/m, z3.h
FRINTX Z0.H, P0/M, Z3.H
frintx z0.h, p0/m, z31.h
FRINTX Z0.H, P0/M, Z31.H
frintx z0.s, p0/m, z0.s
FRINTX Z0.S, P0/M, Z0.S
frintx z1.s, p0/m, z0.s
FRINTX Z1.S, P0/M, Z0.S
frintx z31.s, p0/m, z0.s
FRINTX Z31.S, P0/M, Z0.S
frintx z0.s, p2/m, z0.s
FRINTX Z0.S, P2/M, Z0.S
frintx z0.s, p7/m, z0.s
FRINTX Z0.S, P7/M, Z0.S
frintx z0.s, p0/m, z3.s
FRINTX Z0.S, P0/M, Z3.S
frintx z0.s, p0/m, z31.s
FRINTX Z0.S, P0/M, Z31.S
frintx z0.d, p0/m, z0.d
FRINTX Z0.D, P0/M, Z0.D
frintx z1.d, p0/m, z0.d
FRINTX Z1.D, P0/M, Z0.D
frintx z31.d, p0/m, z0.d
FRINTX Z31.D, P0/M, Z0.D
frintx z0.d, p2/m, z0.d
FRINTX Z0.D, P2/M, Z0.D
frintx z0.d, p7/m, z0.d
FRINTX Z0.D, P7/M, Z0.D
frintx z0.d, p0/m, z3.d
FRINTX Z0.D, P0/M, Z3.D
frintx z0.d, p0/m, z31.d
FRINTX Z0.D, P0/M, Z31.D
frintz z0.h, p0/m, z0.h
FRINTZ Z0.H, P0/M, Z0.H
frintz z1.h, p0/m, z0.h
FRINTZ Z1.H, P0/M, Z0.H
frintz z31.h, p0/m, z0.h
FRINTZ Z31.H, P0/M, Z0.H
frintz z0.h, p2/m, z0.h
FRINTZ Z0.H, P2/M, Z0.H
frintz z0.h, p7/m, z0.h
FRINTZ Z0.H, P7/M, Z0.H
frintz z0.h, p0/m, z3.h
FRINTZ Z0.H, P0/M, Z3.H
frintz z0.h, p0/m, z31.h
FRINTZ Z0.H, P0/M, Z31.H
frintz z0.s, p0/m, z0.s
FRINTZ Z0.S, P0/M, Z0.S
frintz z1.s, p0/m, z0.s
FRINTZ Z1.S, P0/M, Z0.S
frintz z31.s, p0/m, z0.s
FRINTZ Z31.S, P0/M, Z0.S
frintz z0.s, p2/m, z0.s
FRINTZ Z0.S, P2/M, Z0.S
frintz z0.s, p7/m, z0.s
FRINTZ Z0.S, P7/M, Z0.S
frintz z0.s, p0/m, z3.s
FRINTZ Z0.S, P0/M, Z3.S
frintz z0.s, p0/m, z31.s
FRINTZ Z0.S, P0/M, Z31.S
frintz z0.d, p0/m, z0.d
FRINTZ Z0.D, P0/M, Z0.D
frintz z1.d, p0/m, z0.d
FRINTZ Z1.D, P0/M, Z0.D
frintz z31.d, p0/m, z0.d
FRINTZ Z31.D, P0/M, Z0.D
frintz z0.d, p2/m, z0.d
FRINTZ Z0.D, P2/M, Z0.D
frintz z0.d, p7/m, z0.d
FRINTZ Z0.D, P7/M, Z0.D
frintz z0.d, p0/m, z3.d
FRINTZ Z0.D, P0/M, Z3.D
frintz z0.d, p0/m, z31.d
FRINTZ Z0.D, P0/M, Z31.D
frsqrte z0.h, z0.h
FRSQRTE Z0.H, Z0.H
frsqrte z1.h, z0.h
FRSQRTE Z1.H, Z0.H
frsqrte z31.h, z0.h
FRSQRTE Z31.H, Z0.H
frsqrte z0.h, z2.h
FRSQRTE Z0.H, Z2.H
frsqrte z0.h, z31.h
FRSQRTE Z0.H, Z31.H
frsqrte z0.s, z0.s
FRSQRTE Z0.S, Z0.S
frsqrte z1.s, z0.s
FRSQRTE Z1.S, Z0.S
frsqrte z31.s, z0.s
FRSQRTE Z31.S, Z0.S
frsqrte z0.s, z2.s
FRSQRTE Z0.S, Z2.S
frsqrte z0.s, z31.s
FRSQRTE Z0.S, Z31.S
frsqrte z0.d, z0.d
FRSQRTE Z0.D, Z0.D
frsqrte z1.d, z0.d
FRSQRTE Z1.D, Z0.D
frsqrte z31.d, z0.d
FRSQRTE Z31.D, Z0.D
frsqrte z0.d, z2.d
FRSQRTE Z0.D, Z2.D
frsqrte z0.d, z31.d
FRSQRTE Z0.D, Z31.D
frsqrts z0.h, z0.h, z0.h
FRSQRTS Z0.H, Z0.H, Z0.H
frsqrts z1.h, z0.h, z0.h
FRSQRTS Z1.H, Z0.H, Z0.H
frsqrts z31.h, z0.h, z0.h
FRSQRTS Z31.H, Z0.H, Z0.H
frsqrts z0.h, z2.h, z0.h
FRSQRTS Z0.H, Z2.H, Z0.H
frsqrts z0.h, z31.h, z0.h
FRSQRTS Z0.H, Z31.H, Z0.H
frsqrts z0.h, z0.h, z3.h
FRSQRTS Z0.H, Z0.H, Z3.H
frsqrts z0.h, z0.h, z31.h
FRSQRTS Z0.H, Z0.H, Z31.H
frsqrts z0.s, z0.s, z0.s
FRSQRTS Z0.S, Z0.S, Z0.S
frsqrts z1.s, z0.s, z0.s
FRSQRTS Z1.S, Z0.S, Z0.S
frsqrts z31.s, z0.s, z0.s
FRSQRTS Z31.S, Z0.S, Z0.S
frsqrts z0.s, z2.s, z0.s
FRSQRTS Z0.S, Z2.S, Z0.S
frsqrts z0.s, z31.s, z0.s
FRSQRTS Z0.S, Z31.S, Z0.S
frsqrts z0.s, z0.s, z3.s
FRSQRTS Z0.S, Z0.S, Z3.S
frsqrts z0.s, z0.s, z31.s
FRSQRTS Z0.S, Z0.S, Z31.S
frsqrts z0.d, z0.d, z0.d
FRSQRTS Z0.D, Z0.D, Z0.D
frsqrts z1.d, z0.d, z0.d
FRSQRTS Z1.D, Z0.D, Z0.D
frsqrts z31.d, z0.d, z0.d
FRSQRTS Z31.D, Z0.D, Z0.D
frsqrts z0.d, z2.d, z0.d
FRSQRTS Z0.D, Z2.D, Z0.D
frsqrts z0.d, z31.d, z0.d
FRSQRTS Z0.D, Z31.D, Z0.D
frsqrts z0.d, z0.d, z3.d
FRSQRTS Z0.D, Z0.D, Z3.D
frsqrts z0.d, z0.d, z31.d
FRSQRTS Z0.D, Z0.D, Z31.D
fscale z0.h, p0/m, z0.h, z0.h
FSCALE Z0.H, P0/M, Z0.H, Z0.H
fscale z1.h, p0/m, z1.h, z0.h
FSCALE Z1.H, P0/M, Z1.H, Z0.H
fscale z31.h, p0/m, z31.h, z0.h
FSCALE Z31.H, P0/M, Z31.H, Z0.H
fscale z0.h, p2/m, z0.h, z0.h
FSCALE Z0.H, P2/M, Z0.H, Z0.H
fscale z0.h, p7/m, z0.h, z0.h
FSCALE Z0.H, P7/M, Z0.H, Z0.H
fscale z3.h, p0/m, z3.h, z0.h
FSCALE Z3.H, P0/M, Z3.H, Z0.H
fscale z0.h, p0/m, z0.h, z4.h
FSCALE Z0.H, P0/M, Z0.H, Z4.H
fscale z0.h, p0/m, z0.h, z31.h
FSCALE Z0.H, P0/M, Z0.H, Z31.H
fscale z0.s, p0/m, z0.s, z0.s
FSCALE Z0.S, P0/M, Z0.S, Z0.S
fscale z1.s, p0/m, z1.s, z0.s
FSCALE Z1.S, P0/M, Z1.S, Z0.S
fscale z31.s, p0/m, z31.s, z0.s
FSCALE Z31.S, P0/M, Z31.S, Z0.S
fscale z0.s, p2/m, z0.s, z0.s
FSCALE Z0.S, P2/M, Z0.S, Z0.S
fscale z0.s, p7/m, z0.s, z0.s
FSCALE Z0.S, P7/M, Z0.S, Z0.S
fscale z3.s, p0/m, z3.s, z0.s
FSCALE Z3.S, P0/M, Z3.S, Z0.S
fscale z0.s, p0/m, z0.s, z4.s
FSCALE Z0.S, P0/M, Z0.S, Z4.S
fscale z0.s, p0/m, z0.s, z31.s
FSCALE Z0.S, P0/M, Z0.S, Z31.S
fscale z0.d, p0/m, z0.d, z0.d
FSCALE Z0.D, P0/M, Z0.D, Z0.D
fscale z1.d, p0/m, z1.d, z0.d
FSCALE Z1.D, P0/M, Z1.D, Z0.D
fscale z31.d, p0/m, z31.d, z0.d
FSCALE Z31.D, P0/M, Z31.D, Z0.D
fscale z0.d, p2/m, z0.d, z0.d
FSCALE Z0.D, P2/M, Z0.D, Z0.D
fscale z0.d, p7/m, z0.d, z0.d
FSCALE Z0.D, P7/M, Z0.D, Z0.D
fscale z3.d, p0/m, z3.d, z0.d
FSCALE Z3.D, P0/M, Z3.D, Z0.D
fscale z0.d, p0/m, z0.d, z4.d
FSCALE Z0.D, P0/M, Z0.D, Z4.D
fscale z0.d, p0/m, z0.d, z31.d
FSCALE Z0.D, P0/M, Z0.D, Z31.D
fsqrt z0.h, p0/m, z0.h
FSQRT Z0.H, P0/M, Z0.H
fsqrt z1.h, p0/m, z0.h
FSQRT Z1.H, P0/M, Z0.H
fsqrt z31.h, p0/m, z0.h
FSQRT Z31.H, P0/M, Z0.H
fsqrt z0.h, p2/m, z0.h
FSQRT Z0.H, P2/M, Z0.H
fsqrt z0.h, p7/m, z0.h
FSQRT Z0.H, P7/M, Z0.H
fsqrt z0.h, p0/m, z3.h
FSQRT Z0.H, P0/M, Z3.H
fsqrt z0.h, p0/m, z31.h
FSQRT Z0.H, P0/M, Z31.H
fsqrt z0.s, p0/m, z0.s
FSQRT Z0.S, P0/M, Z0.S
fsqrt z1.s, p0/m, z0.s
FSQRT Z1.S, P0/M, Z0.S
fsqrt z31.s, p0/m, z0.s
FSQRT Z31.S, P0/M, Z0.S
fsqrt z0.s, p2/m, z0.s
FSQRT Z0.S, P2/M, Z0.S
fsqrt z0.s, p7/m, z0.s
FSQRT Z0.S, P7/M, Z0.S
fsqrt z0.s, p0/m, z3.s
FSQRT Z0.S, P0/M, Z3.S
fsqrt z0.s, p0/m, z31.s
FSQRT Z0.S, P0/M, Z31.S
fsqrt z0.d, p0/m, z0.d
FSQRT Z0.D, P0/M, Z0.D
fsqrt z1.d, p0/m, z0.d
FSQRT Z1.D, P0/M, Z0.D
fsqrt z31.d, p0/m, z0.d
FSQRT Z31.D, P0/M, Z0.D
fsqrt z0.d, p2/m, z0.d
FSQRT Z0.D, P2/M, Z0.D
fsqrt z0.d, p7/m, z0.d
FSQRT Z0.D, P7/M, Z0.D
fsqrt z0.d, p0/m, z3.d
FSQRT Z0.D, P0/M, Z3.D
fsqrt z0.d, p0/m, z31.d
FSQRT Z0.D, P0/M, Z31.D
fsub z0.h, z0.h, z0.h
FSUB Z0.H, Z0.H, Z0.H
fsub z1.h, z0.h, z0.h
FSUB Z1.H, Z0.H, Z0.H
fsub z31.h, z0.h, z0.h
FSUB Z31.H, Z0.H, Z0.H
fsub z0.h, z2.h, z0.h
FSUB Z0.H, Z2.H, Z0.H
fsub z0.h, z31.h, z0.h
FSUB Z0.H, Z31.H, Z0.H
fsub z0.h, z0.h, z3.h
FSUB Z0.H, Z0.H, Z3.H
fsub z0.h, z0.h, z31.h
FSUB Z0.H, Z0.H, Z31.H
fsub z0.s, z0.s, z0.s
FSUB Z0.S, Z0.S, Z0.S
fsub z1.s, z0.s, z0.s
FSUB Z1.S, Z0.S, Z0.S
fsub z31.s, z0.s, z0.s
FSUB Z31.S, Z0.S, Z0.S
fsub z0.s, z2.s, z0.s
FSUB Z0.S, Z2.S, Z0.S
fsub z0.s, z31.s, z0.s
FSUB Z0.S, Z31.S, Z0.S
fsub z0.s, z0.s, z3.s
FSUB Z0.S, Z0.S, Z3.S
fsub z0.s, z0.s, z31.s
FSUB Z0.S, Z0.S, Z31.S
fsub z0.d, z0.d, z0.d
FSUB Z0.D, Z0.D, Z0.D
fsub z1.d, z0.d, z0.d
FSUB Z1.D, Z0.D, Z0.D
fsub z31.d, z0.d, z0.d
FSUB Z31.D, Z0.D, Z0.D
fsub z0.d, z2.d, z0.d
FSUB Z0.D, Z2.D, Z0.D
fsub z0.d, z31.d, z0.d
FSUB Z0.D, Z31.D, Z0.D
fsub z0.d, z0.d, z3.d
FSUB Z0.D, Z0.D, Z3.D
fsub z0.d, z0.d, z31.d
FSUB Z0.D, Z0.D, Z31.D
fsub z0.h, p0/m, z0.h, z0.h
FSUB Z0.H, P0/M, Z0.H, Z0.H
fsub z1.h, p0/m, z1.h, z0.h
FSUB Z1.H, P0/M, Z1.H, Z0.H
fsub z31.h, p0/m, z31.h, z0.h
FSUB Z31.H, P0/M, Z31.H, Z0.H
fsub z0.h, p2/m, z0.h, z0.h
FSUB Z0.H, P2/M, Z0.H, Z0.H
fsub z0.h, p7/m, z0.h, z0.h
FSUB Z0.H, P7/M, Z0.H, Z0.H
fsub z3.h, p0/m, z3.h, z0.h
FSUB Z3.H, P0/M, Z3.H, Z0.H
fsub z0.h, p0/m, z0.h, z4.h
FSUB Z0.H, P0/M, Z0.H, Z4.H
fsub z0.h, p0/m, z0.h, z31.h
FSUB Z0.H, P0/M, Z0.H, Z31.H
fsub z0.s, p0/m, z0.s, z0.s
FSUB Z0.S, P0/M, Z0.S, Z0.S
fsub z1.s, p0/m, z1.s, z0.s
FSUB Z1.S, P0/M, Z1.S, Z0.S
fsub z31.s, p0/m, z31.s, z0.s
FSUB Z31.S, P0/M, Z31.S, Z0.S
fsub z0.s, p2/m, z0.s, z0.s
FSUB Z0.S, P2/M, Z0.S, Z0.S
fsub z0.s, p7/m, z0.s, z0.s
FSUB Z0.S, P7/M, Z0.S, Z0.S
fsub z3.s, p0/m, z3.s, z0.s
FSUB Z3.S, P0/M, Z3.S, Z0.S
fsub z0.s, p0/m, z0.s, z4.s
FSUB Z0.S, P0/M, Z0.S, Z4.S
fsub z0.s, p0/m, z0.s, z31.s
FSUB Z0.S, P0/M, Z0.S, Z31.S
fsub z0.d, p0/m, z0.d, z0.d
FSUB Z0.D, P0/M, Z0.D, Z0.D
fsub z1.d, p0/m, z1.d, z0.d
FSUB Z1.D, P0/M, Z1.D, Z0.D
fsub z31.d, p0/m, z31.d, z0.d
FSUB Z31.D, P0/M, Z31.D, Z0.D
fsub z0.d, p2/m, z0.d, z0.d
FSUB Z0.D, P2/M, Z0.D, Z0.D
fsub z0.d, p7/m, z0.d, z0.d
FSUB Z0.D, P7/M, Z0.D, Z0.D
fsub z3.d, p0/m, z3.d, z0.d
FSUB Z3.D, P0/M, Z3.D, Z0.D
fsub z0.d, p0/m, z0.d, z4.d
FSUB Z0.D, P0/M, Z0.D, Z4.D
fsub z0.d, p0/m, z0.d, z31.d
FSUB Z0.D, P0/M, Z0.D, Z31.D
fsub z0.h, p0/m, z0.h, #0.5
FSUB Z0.H, P0/M, Z0.H, #0.5
fsub z0.h, p0/m, z0.h, #0.50000
fsub z0.h, p0/m, z0.h, #5.0000000000e-01
fsub z1.h, p0/m, z1.h, #0.5
FSUB Z1.H, P0/M, Z1.H, #0.5
fsub z1.h, p0/m, z1.h, #0.50000
fsub z1.h, p0/m, z1.h, #5.0000000000e-01
fsub z31.h, p0/m, z31.h, #0.5
FSUB Z31.H, P0/M, Z31.H, #0.5
fsub z31.h, p0/m, z31.h, #0.50000
fsub z31.h, p0/m, z31.h, #5.0000000000e-01
fsub z0.h, p2/m, z0.h, #0.5
FSUB Z0.H, P2/M, Z0.H, #0.5
fsub z0.h, p2/m, z0.h, #0.50000
fsub z0.h, p2/m, z0.h, #5.0000000000e-01
fsub z0.h, p7/m, z0.h, #0.5
FSUB Z0.H, P7/M, Z0.H, #0.5
fsub z0.h, p7/m, z0.h, #0.50000
fsub z0.h, p7/m, z0.h, #5.0000000000e-01
fsub z3.h, p0/m, z3.h, #0.5
FSUB Z3.H, P0/M, Z3.H, #0.5
fsub z3.h, p0/m, z3.h, #0.50000
fsub z3.h, p0/m, z3.h, #5.0000000000e-01
fsub z0.h, p0/m, z0.h, #1.0
FSUB Z0.H, P0/M, Z0.H, #1.0
fsub z0.h, p0/m, z0.h, #1.00000
fsub z0.h, p0/m, z0.h, #1.0000000000e+00
fsub z0.s, p0/m, z0.s, #0.5
FSUB Z0.S, P0/M, Z0.S, #0.5
fsub z0.s, p0/m, z0.s, #0.50000
fsub z0.s, p0/m, z0.s, #5.0000000000e-01
fsub z1.s, p0/m, z1.s, #0.5
FSUB Z1.S, P0/M, Z1.S, #0.5
fsub z1.s, p0/m, z1.s, #0.50000
fsub z1.s, p0/m, z1.s, #5.0000000000e-01
fsub z31.s, p0/m, z31.s, #0.5
FSUB Z31.S, P0/M, Z31.S, #0.5
fsub z31.s, p0/m, z31.s, #0.50000
fsub z31.s, p0/m, z31.s, #5.0000000000e-01
fsub z0.s, p2/m, z0.s, #0.5
FSUB Z0.S, P2/M, Z0.S, #0.5
fsub z0.s, p2/m, z0.s, #0.50000
fsub z0.s, p2/m, z0.s, #5.0000000000e-01
fsub z0.s, p7/m, z0.s, #0.5
FSUB Z0.S, P7/M, Z0.S, #0.5
fsub z0.s, p7/m, z0.s, #0.50000
fsub z0.s, p7/m, z0.s, #5.0000000000e-01
fsub z3.s, p0/m, z3.s, #0.5
FSUB Z3.S, P0/M, Z3.S, #0.5
fsub z3.s, p0/m, z3.s, #0.50000
fsub z3.s, p0/m, z3.s, #5.0000000000e-01
fsub z0.s, p0/m, z0.s, #1.0
FSUB Z0.S, P0/M, Z0.S, #1.0
fsub z0.s, p0/m, z0.s, #1.00000
fsub z0.s, p0/m, z0.s, #1.0000000000e+00
fsub z0.d, p0/m, z0.d, #0.5
FSUB Z0.D, P0/M, Z0.D, #0.5
fsub z0.d, p0/m, z0.d, #0.50000
fsub z0.d, p0/m, z0.d, #5.0000000000e-01
fsub z1.d, p0/m, z1.d, #0.5
FSUB Z1.D, P0/M, Z1.D, #0.5
fsub z1.d, p0/m, z1.d, #0.50000
fsub z1.d, p0/m, z1.d, #5.0000000000e-01
fsub z31.d, p0/m, z31.d, #0.5
FSUB Z31.D, P0/M, Z31.D, #0.5
fsub z31.d, p0/m, z31.d, #0.50000
fsub z31.d, p0/m, z31.d, #5.0000000000e-01
fsub z0.d, p2/m, z0.d, #0.5
FSUB Z0.D, P2/M, Z0.D, #0.5
fsub z0.d, p2/m, z0.d, #0.50000
fsub z0.d, p2/m, z0.d, #5.0000000000e-01
fsub z0.d, p7/m, z0.d, #0.5
FSUB Z0.D, P7/M, Z0.D, #0.5
fsub z0.d, p7/m, z0.d, #0.50000
fsub z0.d, p7/m, z0.d, #5.0000000000e-01
fsub z3.d, p0/m, z3.d, #0.5
FSUB Z3.D, P0/M, Z3.D, #0.5
fsub z3.d, p0/m, z3.d, #0.50000
fsub z3.d, p0/m, z3.d, #5.0000000000e-01
fsub z0.d, p0/m, z0.d, #1.0
FSUB Z0.D, P0/M, Z0.D, #1.0
fsub z0.d, p0/m, z0.d, #1.00000
fsub z0.d, p0/m, z0.d, #1.0000000000e+00
fsubr z0.h, p0/m, z0.h, z0.h
FSUBR Z0.H, P0/M, Z0.H, Z0.H
fsubr z1.h, p0/m, z1.h, z0.h
FSUBR Z1.H, P0/M, Z1.H, Z0.H
fsubr z31.h, p0/m, z31.h, z0.h
FSUBR Z31.H, P0/M, Z31.H, Z0.H
fsubr z0.h, p2/m, z0.h, z0.h
FSUBR Z0.H, P2/M, Z0.H, Z0.H
fsubr z0.h, p7/m, z0.h, z0.h
FSUBR Z0.H, P7/M, Z0.H, Z0.H
fsubr z3.h, p0/m, z3.h, z0.h
FSUBR Z3.H, P0/M, Z3.H, Z0.H
fsubr z0.h, p0/m, z0.h, z4.h
FSUBR Z0.H, P0/M, Z0.H, Z4.H
fsubr z0.h, p0/m, z0.h, z31.h
FSUBR Z0.H, P0/M, Z0.H, Z31.H
fsubr z0.s, p0/m, z0.s, z0.s
FSUBR Z0.S, P0/M, Z0.S, Z0.S
fsubr z1.s, p0/m, z1.s, z0.s
FSUBR Z1.S, P0/M, Z1.S, Z0.S
fsubr z31.s, p0/m, z31.s, z0.s
FSUBR Z31.S, P0/M, Z31.S, Z0.S
fsubr z0.s, p2/m, z0.s, z0.s
FSUBR Z0.S, P2/M, Z0.S, Z0.S
fsubr z0.s, p7/m, z0.s, z0.s
FSUBR Z0.S, P7/M, Z0.S, Z0.S
fsubr z3.s, p0/m, z3.s, z0.s
FSUBR Z3.S, P0/M, Z3.S, Z0.S
fsubr z0.s, p0/m, z0.s, z4.s
FSUBR Z0.S, P0/M, Z0.S, Z4.S
fsubr z0.s, p0/m, z0.s, z31.s
FSUBR Z0.S, P0/M, Z0.S, Z31.S
fsubr z0.d, p0/m, z0.d, z0.d
FSUBR Z0.D, P0/M, Z0.D, Z0.D
fsubr z1.d, p0/m, z1.d, z0.d
FSUBR Z1.D, P0/M, Z1.D, Z0.D
fsubr z31.d, p0/m, z31.d, z0.d
FSUBR Z31.D, P0/M, Z31.D, Z0.D
fsubr z0.d, p2/m, z0.d, z0.d
FSUBR Z0.D, P2/M, Z0.D, Z0.D
fsubr z0.d, p7/m, z0.d, z0.d
FSUBR Z0.D, P7/M, Z0.D, Z0.D
fsubr z3.d, p0/m, z3.d, z0.d
FSUBR Z3.D, P0/M, Z3.D, Z0.D
fsubr z0.d, p0/m, z0.d, z4.d
FSUBR Z0.D, P0/M, Z0.D, Z4.D
fsubr z0.d, p0/m, z0.d, z31.d
FSUBR Z0.D, P0/M, Z0.D, Z31.D
fsubr z0.h, p0/m, z0.h, #0.5
FSUBR Z0.H, P0/M, Z0.H, #0.5
fsubr z0.h, p0/m, z0.h, #0.50000
fsubr z0.h, p0/m, z0.h, #5.0000000000e-01
fsubr z1.h, p0/m, z1.h, #0.5
FSUBR Z1.H, P0/M, Z1.H, #0.5
fsubr z1.h, p0/m, z1.h, #0.50000
fsubr z1.h, p0/m, z1.h, #5.0000000000e-01
fsubr z31.h, p0/m, z31.h, #0.5
FSUBR Z31.H, P0/M, Z31.H, #0.5
fsubr z31.h, p0/m, z31.h, #0.50000
fsubr z31.h, p0/m, z31.h, #5.0000000000e-01
fsubr z0.h, p2/m, z0.h, #0.5
FSUBR Z0.H, P2/M, Z0.H, #0.5
fsubr z0.h, p2/m, z0.h, #0.50000
fsubr z0.h, p2/m, z0.h, #5.0000000000e-01
fsubr z0.h, p7/m, z0.h, #0.5
FSUBR Z0.H, P7/M, Z0.H, #0.5
fsubr z0.h, p7/m, z0.h, #0.50000
fsubr z0.h, p7/m, z0.h, #5.0000000000e-01
fsubr z3.h, p0/m, z3.h, #0.5
FSUBR Z3.H, P0/M, Z3.H, #0.5
fsubr z3.h, p0/m, z3.h, #0.50000
fsubr z3.h, p0/m, z3.h, #5.0000000000e-01
fsubr z0.h, p0/m, z0.h, #1.0
FSUBR Z0.H, P0/M, Z0.H, #1.0
fsubr z0.h, p0/m, z0.h, #1.00000
fsubr z0.h, p0/m, z0.h, #1.0000000000e+00
fsubr z0.s, p0/m, z0.s, #0.5
FSUBR Z0.S, P0/M, Z0.S, #0.5
fsubr z0.s, p0/m, z0.s, #0.50000
fsubr z0.s, p0/m, z0.s, #5.0000000000e-01
fsubr z1.s, p0/m, z1.s, #0.5
FSUBR Z1.S, P0/M, Z1.S, #0.5
fsubr z1.s, p0/m, z1.s, #0.50000
fsubr z1.s, p0/m, z1.s, #5.0000000000e-01
fsubr z31.s, p0/m, z31.s, #0.5
FSUBR Z31.S, P0/M, Z31.S, #0.5
fsubr z31.s, p0/m, z31.s, #0.50000
fsubr z31.s, p0/m, z31.s, #5.0000000000e-01
fsubr z0.s, p2/m, z0.s, #0.5
FSUBR Z0.S, P2/M, Z0.S, #0.5
fsubr z0.s, p2/m, z0.s, #0.50000
fsubr z0.s, p2/m, z0.s, #5.0000000000e-01
fsubr z0.s, p7/m, z0.s, #0.5
FSUBR Z0.S, P7/M, Z0.S, #0.5
fsubr z0.s, p7/m, z0.s, #0.50000
fsubr z0.s, p7/m, z0.s, #5.0000000000e-01
fsubr z3.s, p0/m, z3.s, #0.5
FSUBR Z3.S, P0/M, Z3.S, #0.5
fsubr z3.s, p0/m, z3.s, #0.50000
fsubr z3.s, p0/m, z3.s, #5.0000000000e-01
fsubr z0.s, p0/m, z0.s, #1.0
FSUBR Z0.S, P0/M, Z0.S, #1.0
fsubr z0.s, p0/m, z0.s, #1.00000
fsubr z0.s, p0/m, z0.s, #1.0000000000e+00
fsubr z0.d, p0/m, z0.d, #0.5
FSUBR Z0.D, P0/M, Z0.D, #0.5
fsubr z0.d, p0/m, z0.d, #0.50000
fsubr z0.d, p0/m, z0.d, #5.0000000000e-01
fsubr z1.d, p0/m, z1.d, #0.5
FSUBR Z1.D, P0/M, Z1.D, #0.5
fsubr z1.d, p0/m, z1.d, #0.50000
fsubr z1.d, p0/m, z1.d, #5.0000000000e-01
fsubr z31.d, p0/m, z31.d, #0.5
FSUBR Z31.D, P0/M, Z31.D, #0.5
fsubr z31.d, p0/m, z31.d, #0.50000
fsubr z31.d, p0/m, z31.d, #5.0000000000e-01
fsubr z0.d, p2/m, z0.d, #0.5
FSUBR Z0.D, P2/M, Z0.D, #0.5
fsubr z0.d, p2/m, z0.d, #0.50000
fsubr z0.d, p2/m, z0.d, #5.0000000000e-01
fsubr z0.d, p7/m, z0.d, #0.5
FSUBR Z0.D, P7/M, Z0.D, #0.5
fsubr z0.d, p7/m, z0.d, #0.50000
fsubr z0.d, p7/m, z0.d, #5.0000000000e-01
fsubr z3.d, p0/m, z3.d, #0.5
FSUBR Z3.D, P0/M, Z3.D, #0.5
fsubr z3.d, p0/m, z3.d, #0.50000
fsubr z3.d, p0/m, z3.d, #5.0000000000e-01
fsubr z0.d, p0/m, z0.d, #1.0
FSUBR Z0.D, P0/M, Z0.D, #1.0
fsubr z0.d, p0/m, z0.d, #1.00000
fsubr z0.d, p0/m, z0.d, #1.0000000000e+00
ftmad z0.h, z0.h, z0.h, #0
FTMAD Z0.H, Z0.H, Z0.H, #0
ftmad z1.h, z1.h, z0.h, #0
FTMAD Z1.H, Z1.H, Z0.H, #0
ftmad z31.h, z31.h, z0.h, #0
FTMAD Z31.H, Z31.H, Z0.H, #0
ftmad z2.h, z2.h, z0.h, #0
FTMAD Z2.H, Z2.H, Z0.H, #0
ftmad z0.h, z0.h, z3.h, #0
FTMAD Z0.H, Z0.H, Z3.H, #0
ftmad z0.h, z0.h, z31.h, #0
FTMAD Z0.H, Z0.H, Z31.H, #0
ftmad z0.h, z0.h, z0.h, #3
FTMAD Z0.H, Z0.H, Z0.H, #3
ftmad z0.h, z0.h, z0.h, #4
FTMAD Z0.H, Z0.H, Z0.H, #4
ftmad z0.h, z0.h, z0.h, #5
FTMAD Z0.H, Z0.H, Z0.H, #5
ftmad z0.h, z0.h, z0.h, #7
FTMAD Z0.H, Z0.H, Z0.H, #7
ftmad z0.s, z0.s, z0.s, #0
FTMAD Z0.S, Z0.S, Z0.S, #0
ftmad z1.s, z1.s, z0.s, #0
FTMAD Z1.S, Z1.S, Z0.S, #0
ftmad z31.s, z31.s, z0.s, #0
FTMAD Z31.S, Z31.S, Z0.S, #0
ftmad z2.s, z2.s, z0.s, #0
FTMAD Z2.S, Z2.S, Z0.S, #0
ftmad z0.s, z0.s, z3.s, #0
FTMAD Z0.S, Z0.S, Z3.S, #0
ftmad z0.s, z0.s, z31.s, #0
FTMAD Z0.S, Z0.S, Z31.S, #0
ftmad z0.s, z0.s, z0.s, #3
FTMAD Z0.S, Z0.S, Z0.S, #3
ftmad z0.s, z0.s, z0.s, #4
FTMAD Z0.S, Z0.S, Z0.S, #4
ftmad z0.s, z0.s, z0.s, #5
FTMAD Z0.S, Z0.S, Z0.S, #5
ftmad z0.s, z0.s, z0.s, #7
FTMAD Z0.S, Z0.S, Z0.S, #7
ftmad z0.d, z0.d, z0.d, #0
FTMAD Z0.D, Z0.D, Z0.D, #0
ftmad z1.d, z1.d, z0.d, #0
FTMAD Z1.D, Z1.D, Z0.D, #0
ftmad z31.d, z31.d, z0.d, #0
FTMAD Z31.D, Z31.D, Z0.D, #0
ftmad z2.d, z2.d, z0.d, #0
FTMAD Z2.D, Z2.D, Z0.D, #0
ftmad z0.d, z0.d, z3.d, #0
FTMAD Z0.D, Z0.D, Z3.D, #0
ftmad z0.d, z0.d, z31.d, #0
FTMAD Z0.D, Z0.D, Z31.D, #0
ftmad z0.d, z0.d, z0.d, #3
FTMAD Z0.D, Z0.D, Z0.D, #3
ftmad z0.d, z0.d, z0.d, #4
FTMAD Z0.D, Z0.D, Z0.D, #4
ftmad z0.d, z0.d, z0.d, #5
FTMAD Z0.D, Z0.D, Z0.D, #5
ftmad z0.d, z0.d, z0.d, #7
FTMAD Z0.D, Z0.D, Z0.D, #7
ftsmul z0.h, z0.h, z0.h
FTSMUL Z0.H, Z0.H, Z0.H
ftsmul z1.h, z0.h, z0.h
FTSMUL Z1.H, Z0.H, Z0.H
ftsmul z31.h, z0.h, z0.h
FTSMUL Z31.H, Z0.H, Z0.H
ftsmul z0.h, z2.h, z0.h
FTSMUL Z0.H, Z2.H, Z0.H
ftsmul z0.h, z31.h, z0.h
FTSMUL Z0.H, Z31.H, Z0.H
ftsmul z0.h, z0.h, z3.h
FTSMUL Z0.H, Z0.H, Z3.H
ftsmul z0.h, z0.h, z31.h
FTSMUL Z0.H, Z0.H, Z31.H
ftsmul z0.s, z0.s, z0.s
FTSMUL Z0.S, Z0.S, Z0.S
ftsmul z1.s, z0.s, z0.s
FTSMUL Z1.S, Z0.S, Z0.S
ftsmul z31.s, z0.s, z0.s
FTSMUL Z31.S, Z0.S, Z0.S
ftsmul z0.s, z2.s, z0.s
FTSMUL Z0.S, Z2.S, Z0.S
ftsmul z0.s, z31.s, z0.s
FTSMUL Z0.S, Z31.S, Z0.S
ftsmul z0.s, z0.s, z3.s
FTSMUL Z0.S, Z0.S, Z3.S
ftsmul z0.s, z0.s, z31.s
FTSMUL Z0.S, Z0.S, Z31.S
ftsmul z0.d, z0.d, z0.d
FTSMUL Z0.D, Z0.D, Z0.D
ftsmul z1.d, z0.d, z0.d
FTSMUL Z1.D, Z0.D, Z0.D
ftsmul z31.d, z0.d, z0.d
FTSMUL Z31.D, Z0.D, Z0.D
ftsmul z0.d, z2.d, z0.d
FTSMUL Z0.D, Z2.D, Z0.D
ftsmul z0.d, z31.d, z0.d
FTSMUL Z0.D, Z31.D, Z0.D
ftsmul z0.d, z0.d, z3.d
FTSMUL Z0.D, Z0.D, Z3.D
ftsmul z0.d, z0.d, z31.d
FTSMUL Z0.D, Z0.D, Z31.D
ftssel z0.h, z0.h, z0.h
FTSSEL Z0.H, Z0.H, Z0.H
ftssel z1.h, z0.h, z0.h
FTSSEL Z1.H, Z0.H, Z0.H
ftssel z31.h, z0.h, z0.h
FTSSEL Z31.H, Z0.H, Z0.H
ftssel z0.h, z2.h, z0.h
FTSSEL Z0.H, Z2.H, Z0.H
ftssel z0.h, z31.h, z0.h
FTSSEL Z0.H, Z31.H, Z0.H
ftssel z0.h, z0.h, z3.h
FTSSEL Z0.H, Z0.H, Z3.H
ftssel z0.h, z0.h, z31.h
FTSSEL Z0.H, Z0.H, Z31.H
ftssel z0.s, z0.s, z0.s
FTSSEL Z0.S, Z0.S, Z0.S
ftssel z1.s, z0.s, z0.s
FTSSEL Z1.S, Z0.S, Z0.S
ftssel z31.s, z0.s, z0.s
FTSSEL Z31.S, Z0.S, Z0.S
ftssel z0.s, z2.s, z0.s
FTSSEL Z0.S, Z2.S, Z0.S
ftssel z0.s, z31.s, z0.s
FTSSEL Z0.S, Z31.S, Z0.S
ftssel z0.s, z0.s, z3.s
FTSSEL Z0.S, Z0.S, Z3.S
ftssel z0.s, z0.s, z31.s
FTSSEL Z0.S, Z0.S, Z31.S
ftssel z0.d, z0.d, z0.d
FTSSEL Z0.D, Z0.D, Z0.D
ftssel z1.d, z0.d, z0.d
FTSSEL Z1.D, Z0.D, Z0.D
ftssel z31.d, z0.d, z0.d
FTSSEL Z31.D, Z0.D, Z0.D
ftssel z0.d, z2.d, z0.d
FTSSEL Z0.D, Z2.D, Z0.D
ftssel z0.d, z31.d, z0.d
FTSSEL Z0.D, Z31.D, Z0.D
ftssel z0.d, z0.d, z3.d
FTSSEL Z0.D, Z0.D, Z3.D
ftssel z0.d, z0.d, z31.d
FTSSEL Z0.D, Z0.D, Z31.D
incb x0, pow2
INCB X0, POW2
incb x0, pow2, mul #1
incb x1, pow2
INCB X1, POW2
incb x1, pow2, mul #1
incb xzr, pow2
INCB XZR, POW2
incb xzr, pow2, mul #1
incb x0, vl1
INCB X0, VL1
incb x0, vl1, mul #1
incb x0, vl2
INCB X0, VL2
incb x0, vl2, mul #1
incb x0, vl3
INCB X0, VL3
incb x0, vl3, mul #1
incb x0, vl4
INCB X0, VL4
incb x0, vl4, mul #1
incb x0, vl5
INCB X0, VL5
incb x0, vl5, mul #1
incb x0, vl6
INCB X0, VL6
incb x0, vl6, mul #1
incb x0, vl7
INCB X0, VL7
incb x0, vl7, mul #1
incb x0, vl8
INCB X0, VL8
incb x0, vl8, mul #1
incb x0, vl16
INCB X0, VL16
incb x0, vl16, mul #1
incb x0, vl32
INCB X0, VL32
incb x0, vl32, mul #1
incb x0, vl64
INCB X0, VL64
incb x0, vl64, mul #1
incb x0, vl128
INCB X0, VL128
incb x0, vl128, mul #1
incb x0, vl256
INCB X0, VL256
incb x0, vl256, mul #1
incb x0, #14
INCB X0, #14
incb x0, #14, mul #1
incb x0, #15
INCB X0, #15
incb x0, #15, mul #1
incb x0, #16
INCB X0, #16
incb x0, #16, mul #1
incb x0, #17
INCB X0, #17
incb x0, #17, mul #1
incb x0, #18
INCB X0, #18
incb x0, #18, mul #1
incb x0, #19
INCB X0, #19
incb x0, #19, mul #1
incb x0, #20
INCB X0, #20
incb x0, #20, mul #1
incb x0, #21
INCB X0, #21
incb x0, #21, mul #1
incb x0, #22
INCB X0, #22
incb x0, #22, mul #1
incb x0, #23
INCB X0, #23
incb x0, #23, mul #1
incb x0, #24
INCB X0, #24
incb x0, #24, mul #1
incb x0, #25
INCB X0, #25
incb x0, #25, mul #1
incb x0, #26
INCB X0, #26
incb x0, #26, mul #1
incb x0, #27
INCB X0, #27
incb x0, #27, mul #1
incb x0, #28
INCB X0, #28
incb x0, #28, mul #1
incb x0, mul4
INCB X0, MUL4
incb x0, mul4, mul #1
incb x0, mul3
INCB X0, MUL3
incb x0, mul3, mul #1
incb x0
INCB X0
incb x0, all
incb x0, all, mul #1
incb x0, pow2, mul #8
INCB X0, POW2, MUL #8
incb x0, pow2, mul #9
INCB X0, POW2, MUL #9
incb x0, pow2, mul #10
INCB X0, POW2, MUL #10
incb x0, pow2, mul #16
INCB X0, POW2, MUL #16
incd z0.d, pow2
INCD Z0.D, POW2
incd z0.d, pow2, mul #1
incd z1.d, pow2
INCD Z1.D, POW2
incd z1.d, pow2, mul #1
incd z31.d, pow2
INCD Z31.D, POW2
incd z31.d, pow2, mul #1
incd z0.d, vl1
INCD Z0.D, VL1
incd z0.d, vl1, mul #1
incd z0.d, vl2
INCD Z0.D, VL2
incd z0.d, vl2, mul #1
incd z0.d, vl3
INCD Z0.D, VL3
incd z0.d, vl3, mul #1
incd z0.d, vl4
INCD Z0.D, VL4
incd z0.d, vl4, mul #1
incd z0.d, vl5
INCD Z0.D, VL5
incd z0.d, vl5, mul #1
incd z0.d, vl6
INCD Z0.D, VL6
incd z0.d, vl6, mul #1
incd z0.d, vl7
INCD Z0.D, VL7
incd z0.d, vl7, mul #1
incd z0.d, vl8
INCD Z0.D, VL8
incd z0.d, vl8, mul #1
incd z0.d, vl16
INCD Z0.D, VL16
incd z0.d, vl16, mul #1
incd z0.d, vl32
INCD Z0.D, VL32
incd z0.d, vl32, mul #1
incd z0.d, vl64
INCD Z0.D, VL64
incd z0.d, vl64, mul #1
incd z0.d, vl128
INCD Z0.D, VL128
incd z0.d, vl128, mul #1
incd z0.d, vl256
INCD Z0.D, VL256
incd z0.d, vl256, mul #1
incd z0.d, #14
INCD Z0.D, #14
incd z0.d, #14, mul #1
incd z0.d, #15
INCD Z0.D, #15
incd z0.d, #15, mul #1
incd z0.d, #16
INCD Z0.D, #16
incd z0.d, #16, mul #1
incd z0.d, #17
INCD Z0.D, #17
incd z0.d, #17, mul #1
incd z0.d, #18
INCD Z0.D, #18
incd z0.d, #18, mul #1
incd z0.d, #19
INCD Z0.D, #19
incd z0.d, #19, mul #1
incd z0.d, #20
INCD Z0.D, #20
incd z0.d, #20, mul #1
incd z0.d, #21
INCD Z0.D, #21
incd z0.d, #21, mul #1
incd z0.d, #22
INCD Z0.D, #22
incd z0.d, #22, mul #1
incd z0.d, #23
INCD Z0.D, #23
incd z0.d, #23, mul #1
incd z0.d, #24
INCD Z0.D, #24
incd z0.d, #24, mul #1
incd z0.d, #25
INCD Z0.D, #25
incd z0.d, #25, mul #1
incd z0.d, #26
INCD Z0.D, #26
incd z0.d, #26, mul #1
incd z0.d, #27
INCD Z0.D, #27
incd z0.d, #27, mul #1
incd z0.d, #28
INCD Z0.D, #28
incd z0.d, #28, mul #1
incd z0.d, mul4
INCD Z0.D, MUL4
incd z0.d, mul4, mul #1
incd z0.d, mul3
INCD Z0.D, MUL3
incd z0.d, mul3, mul #1
incd z0.d
INCD Z0.D
incd z0.d, all
incd z0.d, all, mul #1
incd z0.d, pow2, mul #8
INCD Z0.D, POW2, MUL #8
incd z0.d, pow2, mul #9
INCD Z0.D, POW2, MUL #9
incd z0.d, pow2, mul #10
INCD Z0.D, POW2, MUL #10
incd z0.d, pow2, mul #16
INCD Z0.D, POW2, MUL #16
incd x0, pow2
INCD X0, POW2
incd x0, pow2, mul #1
incd x1, pow2
INCD X1, POW2
incd x1, pow2, mul #1
incd xzr, pow2
INCD XZR, POW2
incd xzr, pow2, mul #1
incd x0, vl1
INCD X0, VL1
incd x0, vl1, mul #1
incd x0, vl2
INCD X0, VL2
incd x0, vl2, mul #1
incd x0, vl3
INCD X0, VL3
incd x0, vl3, mul #1
incd x0, vl4
INCD X0, VL4
incd x0, vl4, mul #1
incd x0, vl5
INCD X0, VL5
incd x0, vl5, mul #1
incd x0, vl6
INCD X0, VL6
incd x0, vl6, mul #1
incd x0, vl7
INCD X0, VL7
incd x0, vl7, mul #1
incd x0, vl8
INCD X0, VL8
incd x0, vl8, mul #1
incd x0, vl16
INCD X0, VL16
incd x0, vl16, mul #1
incd x0, vl32
INCD X0, VL32
incd x0, vl32, mul #1
incd x0, vl64
INCD X0, VL64
incd x0, vl64, mul #1
incd x0, vl128
INCD X0, VL128
incd x0, vl128, mul #1
incd x0, vl256
INCD X0, VL256
incd x0, vl256, mul #1
incd x0, #14
INCD X0, #14
incd x0, #14, mul #1
incd x0, #15
INCD X0, #15
incd x0, #15, mul #1
incd x0, #16
INCD X0, #16
incd x0, #16, mul #1
incd x0, #17
INCD X0, #17
incd x0, #17, mul #1
incd x0, #18
INCD X0, #18
incd x0, #18, mul #1
incd x0, #19
INCD X0, #19
incd x0, #19, mul #1
incd x0, #20
INCD X0, #20
incd x0, #20, mul #1
incd x0, #21
INCD X0, #21
incd x0, #21, mul #1
incd x0, #22
INCD X0, #22
incd x0, #22, mul #1
incd x0, #23
INCD X0, #23
incd x0, #23, mul #1
incd x0, #24
INCD X0, #24
incd x0, #24, mul #1
incd x0, #25
INCD X0, #25
incd x0, #25, mul #1
incd x0, #26
INCD X0, #26
incd x0, #26, mul #1
incd x0, #27
INCD X0, #27
incd x0, #27, mul #1
incd x0, #28
INCD X0, #28
incd x0, #28, mul #1
incd x0, mul4
INCD X0, MUL4
incd x0, mul4, mul #1
incd x0, mul3
INCD X0, MUL3
incd x0, mul3, mul #1
incd x0
INCD X0
incd x0, all
incd x0, all, mul #1
incd x0, pow2, mul #8
INCD X0, POW2, MUL #8
incd x0, pow2, mul #9
INCD X0, POW2, MUL #9
incd x0, pow2, mul #10
INCD X0, POW2, MUL #10
incd x0, pow2, mul #16
INCD X0, POW2, MUL #16
inch z0.h, pow2
INCH Z0.H, POW2
inch z0.h, pow2, mul #1
inch z1.h, pow2
INCH Z1.H, POW2
inch z1.h, pow2, mul #1
inch z31.h, pow2
INCH Z31.H, POW2
inch z31.h, pow2, mul #1
inch z0.h, vl1
INCH Z0.H, VL1
inch z0.h, vl1, mul #1
inch z0.h, vl2
INCH Z0.H, VL2
inch z0.h, vl2, mul #1
inch z0.h, vl3
INCH Z0.H, VL3
inch z0.h, vl3, mul #1
inch z0.h, vl4
INCH Z0.H, VL4
inch z0.h, vl4, mul #1
inch z0.h, vl5
INCH Z0.H, VL5
inch z0.h, vl5, mul #1
inch z0.h, vl6
INCH Z0.H, VL6
inch z0.h, vl6, mul #1
inch z0.h, vl7
INCH Z0.H, VL7
inch z0.h, vl7, mul #1
inch z0.h, vl8
INCH Z0.H, VL8
inch z0.h, vl8, mul #1
inch z0.h, vl16
INCH Z0.H, VL16
inch z0.h, vl16, mul #1
inch z0.h, vl32
INCH Z0.H, VL32
inch z0.h, vl32, mul #1
inch z0.h, vl64
INCH Z0.H, VL64
inch z0.h, vl64, mul #1
inch z0.h, vl128
INCH Z0.H, VL128
inch z0.h, vl128, mul #1
inch z0.h, vl256
INCH Z0.H, VL256
inch z0.h, vl256, mul #1
inch z0.h, #14
INCH Z0.H, #14
inch z0.h, #14, mul #1
inch z0.h, #15
INCH Z0.H, #15
inch z0.h, #15, mul #1
inch z0.h, #16
INCH Z0.H, #16
inch z0.h, #16, mul #1
inch z0.h, #17
INCH Z0.H, #17
inch z0.h, #17, mul #1
inch z0.h, #18
INCH Z0.H, #18
inch z0.h, #18, mul #1
inch z0.h, #19
INCH Z0.H, #19
inch z0.h, #19, mul #1
inch z0.h, #20
INCH Z0.H, #20
inch z0.h, #20, mul #1
inch z0.h, #21
INCH Z0.H, #21
inch z0.h, #21, mul #1
inch z0.h, #22
INCH Z0.H, #22
inch z0.h, #22, mul #1
inch z0.h, #23
INCH Z0.H, #23
inch z0.h, #23, mul #1
inch z0.h, #24
INCH Z0.H, #24
inch z0.h, #24, mul #1
inch z0.h, #25
INCH Z0.H, #25
inch z0.h, #25, mul #1
inch z0.h, #26
INCH Z0.H, #26
inch z0.h, #26, mul #1
inch z0.h, #27
INCH Z0.H, #27
inch z0.h, #27, mul #1
inch z0.h, #28
INCH Z0.H, #28
inch z0.h, #28, mul #1
inch z0.h, mul4
INCH Z0.H, MUL4
inch z0.h, mul4, mul #1
inch z0.h, mul3
INCH Z0.H, MUL3
inch z0.h, mul3, mul #1
inch z0.h
INCH Z0.H
inch z0.h, all
inch z0.h, all, mul #1
inch z0.h, pow2, mul #8
INCH Z0.H, POW2, MUL #8
inch z0.h, pow2, mul #9
INCH Z0.H, POW2, MUL #9
inch z0.h, pow2, mul #10
INCH Z0.H, POW2, MUL #10
inch z0.h, pow2, mul #16
INCH Z0.H, POW2, MUL #16
inch x0, pow2
INCH X0, POW2
inch x0, pow2, mul #1
inch x1, pow2
INCH X1, POW2
inch x1, pow2, mul #1
inch xzr, pow2
INCH XZR, POW2
inch xzr, pow2, mul #1
inch x0, vl1
INCH X0, VL1
inch x0, vl1, mul #1
inch x0, vl2
INCH X0, VL2
inch x0, vl2, mul #1
inch x0, vl3
INCH X0, VL3
inch x0, vl3, mul #1
inch x0, vl4
INCH X0, VL4
inch x0, vl4, mul #1
inch x0, vl5
INCH X0, VL5
inch x0, vl5, mul #1
inch x0, vl6
INCH X0, VL6
inch x0, vl6, mul #1
inch x0, vl7
INCH X0, VL7
inch x0, vl7, mul #1
inch x0, vl8
INCH X0, VL8
inch x0, vl8, mul #1
inch x0, vl16
INCH X0, VL16
inch x0, vl16, mul #1
inch x0, vl32
INCH X0, VL32
inch x0, vl32, mul #1
inch x0, vl64
INCH X0, VL64
inch x0, vl64, mul #1
inch x0, vl128
INCH X0, VL128
inch x0, vl128, mul #1
inch x0, vl256
INCH X0, VL256
inch x0, vl256, mul #1
inch x0, #14
INCH X0, #14
inch x0, #14, mul #1
inch x0, #15
INCH X0, #15
inch x0, #15, mul #1
inch x0, #16
INCH X0, #16
inch x0, #16, mul #1
inch x0, #17
INCH X0, #17
inch x0, #17, mul #1
inch x0, #18
INCH X0, #18
inch x0, #18, mul #1
inch x0, #19
INCH X0, #19
inch x0, #19, mul #1
inch x0, #20
INCH X0, #20
inch x0, #20, mul #1
inch x0, #21
INCH X0, #21
inch x0, #21, mul #1
inch x0, #22
INCH X0, #22
inch x0, #22, mul #1
inch x0, #23
INCH X0, #23
inch x0, #23, mul #1
inch x0, #24
INCH X0, #24
inch x0, #24, mul #1
inch x0, #25
INCH X0, #25
inch x0, #25, mul #1
inch x0, #26
INCH X0, #26
inch x0, #26, mul #1
inch x0, #27
INCH X0, #27
inch x0, #27, mul #1
inch x0, #28
INCH X0, #28
inch x0, #28, mul #1
inch x0, mul4
INCH X0, MUL4
inch x0, mul4, mul #1
inch x0, mul3
INCH X0, MUL3
inch x0, mul3, mul #1
inch x0
INCH X0
inch x0, all
inch x0, all, mul #1
inch x0, pow2, mul #8
INCH X0, POW2, MUL #8
inch x0, pow2, mul #9
INCH X0, POW2, MUL #9
inch x0, pow2, mul #10
INCH X0, POW2, MUL #10
inch x0, pow2, mul #16
INCH X0, POW2, MUL #16
incp z0.h, p0
INCP Z0.H, P0
incp z1.h, p0
INCP Z1.H, P0
incp z31.h, p0
INCP Z31.H, P0
incp z0.h, p2
INCP Z0.H, P2
incp z0.h, p15
INCP Z0.H, P15
incp z0.s, p0
INCP Z0.S, P0
incp z1.s, p0
INCP Z1.S, P0
incp z31.s, p0
INCP Z31.S, P0
incp z0.s, p2
INCP Z0.S, P2
incp z0.s, p15
INCP Z0.S, P15
incp z0.d, p0
INCP Z0.D, P0
incp z1.d, p0
INCP Z1.D, P0
incp z31.d, p0
INCP Z31.D, P0
incp z0.d, p2
INCP Z0.D, P2
incp z0.d, p15
INCP Z0.D, P15
incp x0, p0.b
INCP X0, P0.B
incp x1, p0.b
INCP X1, P0.B
incp xzr, p0.b
INCP XZR, P0.B
incp x0, p2.b
INCP X0, P2.B
incp x0, p15.b
INCP X0, P15.B
incp x0, p0.h
INCP X0, P0.H
incp x1, p0.h
INCP X1, P0.H
incp xzr, p0.h
INCP XZR, P0.H
incp x0, p2.h
INCP X0, P2.H
incp x0, p15.h
INCP X0, P15.H
incp x0, p0.s
INCP X0, P0.S
incp x1, p0.s
INCP X1, P0.S
incp xzr, p0.s
INCP XZR, P0.S
incp x0, p2.s
INCP X0, P2.S
incp x0, p15.s
INCP X0, P15.S
incp x0, p0.d
INCP X0, P0.D
incp x1, p0.d
INCP X1, P0.D
incp xzr, p0.d
INCP XZR, P0.D
incp x0, p2.d
INCP X0, P2.D
incp x0, p15.d
INCP X0, P15.D
incw z0.s, pow2
INCW Z0.S, POW2
incw z0.s, pow2, mul #1
incw z1.s, pow2
INCW Z1.S, POW2
incw z1.s, pow2, mul #1
incw z31.s, pow2
INCW Z31.S, POW2
incw z31.s, pow2, mul #1
incw z0.s, vl1
INCW Z0.S, VL1
incw z0.s, vl1, mul #1
incw z0.s, vl2
INCW Z0.S, VL2
incw z0.s, vl2, mul #1
incw z0.s, vl3
INCW Z0.S, VL3
incw z0.s, vl3, mul #1
incw z0.s, vl4
INCW Z0.S, VL4
incw z0.s, vl4, mul #1
incw z0.s, vl5
INCW Z0.S, VL5
incw z0.s, vl5, mul #1
incw z0.s, vl6
INCW Z0.S, VL6
incw z0.s, vl6, mul #1
incw z0.s, vl7
INCW Z0.S, VL7
incw z0.s, vl7, mul #1
incw z0.s, vl8
INCW Z0.S, VL8
incw z0.s, vl8, mul #1
incw z0.s, vl16
INCW Z0.S, VL16
incw z0.s, vl16, mul #1
incw z0.s, vl32
INCW Z0.S, VL32
incw z0.s, vl32, mul #1
incw z0.s, vl64
INCW Z0.S, VL64
incw z0.s, vl64, mul #1
incw z0.s, vl128
INCW Z0.S, VL128
incw z0.s, vl128, mul #1
incw z0.s, vl256
INCW Z0.S, VL256
incw z0.s, vl256, mul #1
incw z0.s, #14
INCW Z0.S, #14
incw z0.s, #14, mul #1
incw z0.s, #15
INCW Z0.S, #15
incw z0.s, #15, mul #1
incw z0.s, #16
INCW Z0.S, #16
incw z0.s, #16, mul #1
incw z0.s, #17
INCW Z0.S, #17
incw z0.s, #17, mul #1
incw z0.s, #18
INCW Z0.S, #18
incw z0.s, #18, mul #1
incw z0.s, #19
INCW Z0.S, #19
incw z0.s, #19, mul #1
incw z0.s, #20
INCW Z0.S, #20
incw z0.s, #20, mul #1
incw z0.s, #21
INCW Z0.S, #21
incw z0.s, #21, mul #1
incw z0.s, #22
INCW Z0.S, #22
incw z0.s, #22, mul #1
incw z0.s, #23
INCW Z0.S, #23
incw z0.s, #23, mul #1
incw z0.s, #24
INCW Z0.S, #24
incw z0.s, #24, mul #1
incw z0.s, #25
INCW Z0.S, #25
incw z0.s, #25, mul #1
incw z0.s, #26
INCW Z0.S, #26
incw z0.s, #26, mul #1
incw z0.s, #27
INCW Z0.S, #27
incw z0.s, #27, mul #1
incw z0.s, #28
INCW Z0.S, #28
incw z0.s, #28, mul #1
incw z0.s, mul4
INCW Z0.S, MUL4
incw z0.s, mul4, mul #1
incw z0.s, mul3
INCW Z0.S, MUL3
incw z0.s, mul3, mul #1
incw z0.s
INCW Z0.S
incw z0.s, all
incw z0.s, all, mul #1
incw z0.s, pow2, mul #8
INCW Z0.S, POW2, MUL #8
incw z0.s, pow2, mul #9
INCW Z0.S, POW2, MUL #9
incw z0.s, pow2, mul #10
INCW Z0.S, POW2, MUL #10
incw z0.s, pow2, mul #16
INCW Z0.S, POW2, MUL #16
incw x0, pow2
INCW X0, POW2
incw x0, pow2, mul #1
incw x1, pow2
INCW X1, POW2
incw x1, pow2, mul #1
incw xzr, pow2
INCW XZR, POW2
incw xzr, pow2, mul #1
incw x0, vl1
INCW X0, VL1
incw x0, vl1, mul #1
incw x0, vl2
INCW X0, VL2
incw x0, vl2, mul #1
incw x0, vl3
INCW X0, VL3
incw x0, vl3, mul #1
incw x0, vl4
INCW X0, VL4
incw x0, vl4, mul #1
incw x0, vl5
INCW X0, VL5
incw x0, vl5, mul #1
incw x0, vl6
INCW X0, VL6
incw x0, vl6, mul #1
incw x0, vl7
INCW X0, VL7
incw x0, vl7, mul #1
incw x0, vl8
INCW X0, VL8
incw x0, vl8, mul #1
incw x0, vl16
INCW X0, VL16
incw x0, vl16, mul #1
incw x0, vl32
INCW X0, VL32
incw x0, vl32, mul #1
incw x0, vl64
INCW X0, VL64
incw x0, vl64, mul #1
incw x0, vl128
INCW X0, VL128
incw x0, vl128, mul #1
incw x0, vl256
INCW X0, VL256
incw x0, vl256, mul #1
incw x0, #14
INCW X0, #14
incw x0, #14, mul #1
incw x0, #15
INCW X0, #15
incw x0, #15, mul #1
incw x0, #16
INCW X0, #16
incw x0, #16, mul #1
incw x0, #17
INCW X0, #17
incw x0, #17, mul #1
incw x0, #18
INCW X0, #18
incw x0, #18, mul #1
incw x0, #19
INCW X0, #19
incw x0, #19, mul #1
incw x0, #20
INCW X0, #20
incw x0, #20, mul #1
incw x0, #21
INCW X0, #21
incw x0, #21, mul #1
incw x0, #22
INCW X0, #22
incw x0, #22, mul #1
incw x0, #23
INCW X0, #23
incw x0, #23, mul #1
incw x0, #24
INCW X0, #24
incw x0, #24, mul #1
incw x0, #25
INCW X0, #25
incw x0, #25, mul #1
incw x0, #26
INCW X0, #26
incw x0, #26, mul #1
incw x0, #27
INCW X0, #27
incw x0, #27, mul #1
incw x0, #28
INCW X0, #28
incw x0, #28, mul #1
incw x0, mul4
INCW X0, MUL4
incw x0, mul4, mul #1
incw x0, mul3
INCW X0, MUL3
incw x0, mul3, mul #1
incw x0
INCW X0
incw x0, all
incw x0, all, mul #1
incw x0, pow2, mul #8
INCW X0, POW2, MUL #8
incw x0, pow2, mul #9
INCW X0, POW2, MUL #9
incw x0, pow2, mul #10
INCW X0, POW2, MUL #10
incw x0, pow2, mul #16
INCW X0, POW2, MUL #16
index z0.b, w0, w0
INDEX Z0.B, W0, W0
index z1.b, w0, w0
INDEX Z1.B, W0, W0
index z31.b, w0, w0
INDEX Z31.B, W0, W0
index z0.b, w2, w0
INDEX Z0.B, W2, W0
index z0.b, wzr, w0
INDEX Z0.B, WZR, W0
index z0.b, w0, w3
INDEX Z0.B, W0, W3
index z0.b, w0, wzr
INDEX Z0.B, W0, WZR
index z0.h, w0, w0
INDEX Z0.H, W0, W0
index z1.h, w0, w0
INDEX Z1.H, W0, W0
index z31.h, w0, w0
INDEX Z31.H, W0, W0
index z0.h, w2, w0
INDEX Z0.H, W2, W0
index z0.h, wzr, w0
INDEX Z0.H, WZR, W0
index z0.h, w0, w3
INDEX Z0.H, W0, W3
index z0.h, w0, wzr
INDEX Z0.H, W0, WZR
index z0.s, w0, w0
INDEX Z0.S, W0, W0
index z1.s, w0, w0
INDEX Z1.S, W0, W0
index z31.s, w0, w0
INDEX Z31.S, W0, W0
index z0.s, w2, w0
INDEX Z0.S, W2, W0
index z0.s, wzr, w0
INDEX Z0.S, WZR, W0
index z0.s, w0, w3
INDEX Z0.S, W0, W3
index z0.s, w0, wzr
INDEX Z0.S, W0, WZR
index z0.d, x0, x0
INDEX Z0.D, X0, X0
index z1.d, x0, x0
INDEX Z1.D, X0, X0
index z31.d, x0, x0
INDEX Z31.D, X0, X0
index z0.d, x2, x0
INDEX Z0.D, X2, X0
index z0.d, xzr, x0
INDEX Z0.D, XZR, X0
index z0.d, x0, x3
INDEX Z0.D, X0, X3
index z0.d, x0, xzr
INDEX Z0.D, X0, XZR
index z0.b, #0, #0
INDEX Z0.B, #0, #0
index z1.b, #0, #0
INDEX Z1.B, #0, #0
index z31.b, #0, #0
INDEX Z31.B, #0, #0
index z0.b, #15, #0
INDEX Z0.B, #15, #0
index z0.b, #-16, #0
INDEX Z0.B, #-16, #0
index z0.b, #-15, #0
INDEX Z0.B, #-15, #0
index z0.b, #-1, #0
INDEX Z0.B, #-1, #0
index z0.b, #0, #15
INDEX Z0.B, #0, #15
index z0.b, #0, #-16
INDEX Z0.B, #0, #-16
index z0.b, #0, #-15
INDEX Z0.B, #0, #-15
index z0.b, #0, #-1
INDEX Z0.B, #0, #-1
index z0.h, #0, #0
INDEX Z0.H, #0, #0
index z1.h, #0, #0
INDEX Z1.H, #0, #0
index z31.h, #0, #0
INDEX Z31.H, #0, #0
index z0.h, #15, #0
INDEX Z0.H, #15, #0
index z0.h, #-16, #0
INDEX Z0.H, #-16, #0
index z0.h, #-15, #0
INDEX Z0.H, #-15, #0
index z0.h, #-1, #0
INDEX Z0.H, #-1, #0
index z0.h, #0, #15
INDEX Z0.H, #0, #15
index z0.h, #0, #-16
INDEX Z0.H, #0, #-16
index z0.h, #0, #-15
INDEX Z0.H, #0, #-15
index z0.h, #0, #-1
INDEX Z0.H, #0, #-1
index z0.s, #0, #0
INDEX Z0.S, #0, #0
index z1.s, #0, #0
INDEX Z1.S, #0, #0
index z31.s, #0, #0
INDEX Z31.S, #0, #0
index z0.s, #15, #0
INDEX Z0.S, #15, #0
index z0.s, #-16, #0
INDEX Z0.S, #-16, #0
index z0.s, #-15, #0
INDEX Z0.S, #-15, #0
index z0.s, #-1, #0
INDEX Z0.S, #-1, #0
index z0.s, #0, #15
INDEX Z0.S, #0, #15
index z0.s, #0, #-16
INDEX Z0.S, #0, #-16
index z0.s, #0, #-15
INDEX Z0.S, #0, #-15
index z0.s, #0, #-1
INDEX Z0.S, #0, #-1
index z0.d, #0, #0
INDEX Z0.D, #0, #0
index z1.d, #0, #0
INDEX Z1.D, #0, #0
index z31.d, #0, #0
INDEX Z31.D, #0, #0
index z0.d, #15, #0
INDEX Z0.D, #15, #0
index z0.d, #-16, #0
INDEX Z0.D, #-16, #0
index z0.d, #-15, #0
INDEX Z0.D, #-15, #0
index z0.d, #-1, #0
INDEX Z0.D, #-1, #0
index z0.d, #0, #15
INDEX Z0.D, #0, #15
index z0.d, #0, #-16
INDEX Z0.D, #0, #-16
index z0.d, #0, #-15
INDEX Z0.D, #0, #-15
index z0.d, #0, #-1
INDEX Z0.D, #0, #-1
index z0.b, w0, #0
INDEX Z0.B, W0, #0
index z1.b, w0, #0
INDEX Z1.B, W0, #0
index z31.b, w0, #0
INDEX Z31.B, W0, #0
index z0.b, w2, #0
INDEX Z0.B, W2, #0
index z0.b, wzr, #0
INDEX Z0.B, WZR, #0
index z0.b, w0, #15
INDEX Z0.B, W0, #15
index z0.b, w0, #-16
INDEX Z0.B, W0, #-16
index z0.b, w0, #-15
INDEX Z0.B, W0, #-15
index z0.b, w0, #-1
INDEX Z0.B, W0, #-1
index z0.h, w0, #0
INDEX Z0.H, W0, #0
index z1.h, w0, #0
INDEX Z1.H, W0, #0
index z31.h, w0, #0
INDEX Z31.H, W0, #0
index z0.h, w2, #0
INDEX Z0.H, W2, #0
index z0.h, wzr, #0
INDEX Z0.H, WZR, #0
index z0.h, w0, #15
INDEX Z0.H, W0, #15
index z0.h, w0, #-16
INDEX Z0.H, W0, #-16
index z0.h, w0, #-15
INDEX Z0.H, W0, #-15
index z0.h, w0, #-1
INDEX Z0.H, W0, #-1
index z0.s, w0, #0
INDEX Z0.S, W0, #0
index z1.s, w0, #0
INDEX Z1.S, W0, #0
index z31.s, w0, #0
INDEX Z31.S, W0, #0
index z0.s, w2, #0
INDEX Z0.S, W2, #0
index z0.s, wzr, #0
INDEX Z0.S, WZR, #0
index z0.s, w0, #15
INDEX Z0.S, W0, #15
index z0.s, w0, #-16
INDEX Z0.S, W0, #-16
index z0.s, w0, #-15
INDEX Z0.S, W0, #-15
index z0.s, w0, #-1
INDEX Z0.S, W0, #-1
index z0.d, x0, #0
INDEX Z0.D, X0, #0
index z1.d, x0, #0
INDEX Z1.D, X0, #0
index z31.d, x0, #0
INDEX Z31.D, X0, #0
index z0.d, x2, #0
INDEX Z0.D, X2, #0
index z0.d, xzr, #0
INDEX Z0.D, XZR, #0
index z0.d, x0, #15
INDEX Z0.D, X0, #15
index z0.d, x0, #-16
INDEX Z0.D, X0, #-16
index z0.d, x0, #-15
INDEX Z0.D, X0, #-15
index z0.d, x0, #-1
INDEX Z0.D, X0, #-1
index z0.b, #0, w0
INDEX Z0.B, #0, W0
index z1.b, #0, w0
INDEX Z1.B, #0, W0
index z31.b, #0, w0
INDEX Z31.B, #0, W0
index z0.b, #15, w0
INDEX Z0.B, #15, W0
index z0.b, #-16, w0
INDEX Z0.B, #-16, W0
index z0.b, #-15, w0
INDEX Z0.B, #-15, W0
index z0.b, #-1, w0
INDEX Z0.B, #-1, W0
index z0.b, #0, w3
INDEX Z0.B, #0, W3
index z0.b, #0, wzr
INDEX Z0.B, #0, WZR
index z0.h, #0, w0
INDEX Z0.H, #0, W0
index z1.h, #0, w0
INDEX Z1.H, #0, W0
index z31.h, #0, w0
INDEX Z31.H, #0, W0
index z0.h, #15, w0
INDEX Z0.H, #15, W0
index z0.h, #-16, w0
INDEX Z0.H, #-16, W0
index z0.h, #-15, w0
INDEX Z0.H, #-15, W0
index z0.h, #-1, w0
INDEX Z0.H, #-1, W0
index z0.h, #0, w3
INDEX Z0.H, #0, W3
index z0.h, #0, wzr
INDEX Z0.H, #0, WZR
index z0.s, #0, w0
INDEX Z0.S, #0, W0
index z1.s, #0, w0
INDEX Z1.S, #0, W0
index z31.s, #0, w0
INDEX Z31.S, #0, W0
index z0.s, #15, w0
INDEX Z0.S, #15, W0
index z0.s, #-16, w0
INDEX Z0.S, #-16, W0
index z0.s, #-15, w0
INDEX Z0.S, #-15, W0
index z0.s, #-1, w0
INDEX Z0.S, #-1, W0
index z0.s, #0, w3
INDEX Z0.S, #0, W3
index z0.s, #0, wzr
INDEX Z0.S, #0, WZR
index z0.d, #0, x0
INDEX Z0.D, #0, X0
index z1.d, #0, x0
INDEX Z1.D, #0, X0
index z31.d, #0, x0
INDEX Z31.D, #0, X0
index z0.d, #15, x0
INDEX Z0.D, #15, X0
index z0.d, #-16, x0
INDEX Z0.D, #-16, X0
index z0.d, #-15, x0
INDEX Z0.D, #-15, X0
index z0.d, #-1, x0
INDEX Z0.D, #-1, X0
index z0.d, #0, x3
INDEX Z0.D, #0, X3
index z0.d, #0, xzr
INDEX Z0.D, #0, XZR
insr z0.b, w0
INSR Z0.B, W0
insr z1.b, w0
INSR Z1.B, W0
insr z31.b, w0
INSR Z31.B, W0
insr z0.b, w2
INSR Z0.B, W2
insr z0.b, wzr
INSR Z0.B, WZR
insr z0.h, w0
INSR Z0.H, W0
insr z1.h, w0
INSR Z1.H, W0
insr z31.h, w0
INSR Z31.H, W0
insr z0.h, w2
INSR Z0.H, W2
insr z0.h, wzr
INSR Z0.H, WZR
insr z0.s, w0
INSR Z0.S, W0
insr z1.s, w0
INSR Z1.S, W0
insr z31.s, w0
INSR Z31.S, W0
insr z0.s, w2
INSR Z0.S, W2
insr z0.s, wzr
INSR Z0.S, WZR
insr z0.d, x0
INSR Z0.D, X0
insr z1.d, x0
INSR Z1.D, X0
insr z31.d, x0
INSR Z31.D, X0
insr z0.d, x2
INSR Z0.D, X2
insr z0.d, xzr
INSR Z0.D, XZR
insr z0.b, b0
INSR Z0.B, B0
insr z1.b, b0
INSR Z1.B, B0
insr z31.b, b0
INSR Z31.B, B0
insr z0.b, b2
INSR Z0.B, B2
insr z0.b, b31
INSR Z0.B, B31
insr z0.h, h0
INSR Z0.H, H0
insr z1.h, h0
INSR Z1.H, H0
insr z31.h, h0
INSR Z31.H, H0
insr z0.h, h2
INSR Z0.H, H2
insr z0.h, h31
INSR Z0.H, H31
insr z0.s, s0
INSR Z0.S, S0
insr z1.s, s0
INSR Z1.S, S0
insr z31.s, s0
INSR Z31.S, S0
insr z0.s, s2
INSR Z0.S, S2
insr z0.s, s31
INSR Z0.S, S31
insr z0.d, d0
INSR Z0.D, D0
insr z1.d, d0
INSR Z1.D, D0
insr z31.d, d0
INSR Z31.D, D0
insr z0.d, d2
INSR Z0.D, D2
insr z0.d, d31
INSR Z0.D, D31
lasta w0, p0, z0.b
LASTA W0, P0, Z0.B
lasta w1, p0, z0.b
LASTA W1, P0, Z0.B
lasta wzr, p0, z0.b
LASTA WZR, P0, Z0.B
lasta w0, p2, z0.b
LASTA W0, P2, Z0.B
lasta w0, p7, z0.b
LASTA W0, P7, Z0.B
lasta w0, p0, z3.b
LASTA W0, P0, Z3.B
lasta w0, p0, z31.b
LASTA W0, P0, Z31.B
lasta w0, p0, z0.h
LASTA W0, P0, Z0.H
lasta w1, p0, z0.h
LASTA W1, P0, Z0.H
lasta wzr, p0, z0.h
LASTA WZR, P0, Z0.H
lasta w0, p2, z0.h
LASTA W0, P2, Z0.H
lasta w0, p7, z0.h
LASTA W0, P7, Z0.H
lasta w0, p0, z3.h
LASTA W0, P0, Z3.H
lasta w0, p0, z31.h
LASTA W0, P0, Z31.H
lasta w0, p0, z0.s
LASTA W0, P0, Z0.S
lasta w1, p0, z0.s
LASTA W1, P0, Z0.S
lasta wzr, p0, z0.s
LASTA WZR, P0, Z0.S
lasta w0, p2, z0.s
LASTA W0, P2, Z0.S
lasta w0, p7, z0.s
LASTA W0, P7, Z0.S
lasta w0, p0, z3.s
LASTA W0, P0, Z3.S
lasta w0, p0, z31.s
LASTA W0, P0, Z31.S
lasta x0, p0, z0.d
LASTA X0, P0, Z0.D
lasta x1, p0, z0.d
LASTA X1, P0, Z0.D
lasta xzr, p0, z0.d
LASTA XZR, P0, Z0.D
lasta x0, p2, z0.d
LASTA X0, P2, Z0.D
lasta x0, p7, z0.d
LASTA X0, P7, Z0.D
lasta x0, p0, z3.d
LASTA X0, P0, Z3.D
lasta x0, p0, z31.d
LASTA X0, P0, Z31.D
lasta b0, p0, z0.b
LASTA B0, P0, Z0.B
lasta b1, p0, z0.b
LASTA B1, P0, Z0.B
lasta b31, p0, z0.b
LASTA B31, P0, Z0.B
lasta b0, p2, z0.b
LASTA B0, P2, Z0.B
lasta b0, p7, z0.b
LASTA B0, P7, Z0.B
lasta b0, p0, z3.b
LASTA B0, P0, Z3.B
lasta b0, p0, z31.b
LASTA B0, P0, Z31.B
lasta h0, p0, z0.h
LASTA H0, P0, Z0.H
lasta h1, p0, z0.h
LASTA H1, P0, Z0.H
lasta h31, p0, z0.h
LASTA H31, P0, Z0.H
lasta h0, p2, z0.h
LASTA H0, P2, Z0.H
lasta h0, p7, z0.h
LASTA H0, P7, Z0.H
lasta h0, p0, z3.h
LASTA H0, P0, Z3.H
lasta h0, p0, z31.h
LASTA H0, P0, Z31.H
lasta s0, p0, z0.s
LASTA S0, P0, Z0.S
lasta s1, p0, z0.s
LASTA S1, P0, Z0.S
lasta s31, p0, z0.s
LASTA S31, P0, Z0.S
lasta s0, p2, z0.s
LASTA S0, P2, Z0.S
lasta s0, p7, z0.s
LASTA S0, P7, Z0.S
lasta s0, p0, z3.s
LASTA S0, P0, Z3.S
lasta s0, p0, z31.s
LASTA S0, P0, Z31.S
lasta d0, p0, z0.d
LASTA D0, P0, Z0.D
lasta d1, p0, z0.d
LASTA D1, P0, Z0.D
lasta d31, p0, z0.d
LASTA D31, P0, Z0.D
lasta d0, p2, z0.d
LASTA D0, P2, Z0.D
lasta d0, p7, z0.d
LASTA D0, P7, Z0.D
lasta d0, p0, z3.d
LASTA D0, P0, Z3.D
lasta d0, p0, z31.d
LASTA D0, P0, Z31.D
lastb w0, p0, z0.b
LASTB W0, P0, Z0.B
lastb w1, p0, z0.b
LASTB W1, P0, Z0.B
lastb wzr, p0, z0.b
LASTB WZR, P0, Z0.B
lastb w0, p2, z0.b
LASTB W0, P2, Z0.B
lastb w0, p7, z0.b
LASTB W0, P7, Z0.B
lastb w0, p0, z3.b
LASTB W0, P0, Z3.B
lastb w0, p0, z31.b
LASTB W0, P0, Z31.B
lastb w0, p0, z0.h
LASTB W0, P0, Z0.H
lastb w1, p0, z0.h
LASTB W1, P0, Z0.H
lastb wzr, p0, z0.h
LASTB WZR, P0, Z0.H
lastb w0, p2, z0.h
LASTB W0, P2, Z0.H
lastb w0, p7, z0.h
LASTB W0, P7, Z0.H
lastb w0, p0, z3.h
LASTB W0, P0, Z3.H
lastb w0, p0, z31.h
LASTB W0, P0, Z31.H
lastb w0, p0, z0.s
LASTB W0, P0, Z0.S
lastb w1, p0, z0.s
LASTB W1, P0, Z0.S
lastb wzr, p0, z0.s
LASTB WZR, P0, Z0.S
lastb w0, p2, z0.s
LASTB W0, P2, Z0.S
lastb w0, p7, z0.s
LASTB W0, P7, Z0.S
lastb w0, p0, z3.s
LASTB W0, P0, Z3.S
lastb w0, p0, z31.s
LASTB W0, P0, Z31.S
lastb x0, p0, z0.d
LASTB X0, P0, Z0.D
lastb x1, p0, z0.d
LASTB X1, P0, Z0.D
lastb xzr, p0, z0.d
LASTB XZR, P0, Z0.D
lastb x0, p2, z0.d
LASTB X0, P2, Z0.D
lastb x0, p7, z0.d
LASTB X0, P7, Z0.D
lastb x0, p0, z3.d
LASTB X0, P0, Z3.D
lastb x0, p0, z31.d
LASTB X0, P0, Z31.D
lastb b0, p0, z0.b
LASTB B0, P0, Z0.B
lastb b1, p0, z0.b
LASTB B1, P0, Z0.B
lastb b31, p0, z0.b
LASTB B31, P0, Z0.B
lastb b0, p2, z0.b
LASTB B0, P2, Z0.B
lastb b0, p7, z0.b
LASTB B0, P7, Z0.B
lastb b0, p0, z3.b
LASTB B0, P0, Z3.B
lastb b0, p0, z31.b
LASTB B0, P0, Z31.B
lastb h0, p0, z0.h
LASTB H0, P0, Z0.H
lastb h1, p0, z0.h
LASTB H1, P0, Z0.H
lastb h31, p0, z0.h
LASTB H31, P0, Z0.H
lastb h0, p2, z0.h
LASTB H0, P2, Z0.H
lastb h0, p7, z0.h
LASTB H0, P7, Z0.H
lastb h0, p0, z3.h
LASTB H0, P0, Z3.H
lastb h0, p0, z31.h
LASTB H0, P0, Z31.H
lastb s0, p0, z0.s
LASTB S0, P0, Z0.S
lastb s1, p0, z0.s
LASTB S1, P0, Z0.S
lastb s31, p0, z0.s
LASTB S31, P0, Z0.S
lastb s0, p2, z0.s
LASTB S0, P2, Z0.S
lastb s0, p7, z0.s
LASTB S0, P7, Z0.S
lastb s0, p0, z3.s
LASTB S0, P0, Z3.S
lastb s0, p0, z31.s
LASTB S0, P0, Z31.S
lastb d0, p0, z0.d
LASTB D0, P0, Z0.D
lastb d1, p0, z0.d
LASTB D1, P0, Z0.D
lastb d31, p0, z0.d
LASTB D31, P0, Z0.D
lastb d0, p2, z0.d
LASTB D0, P2, Z0.D
lastb d0, p7, z0.d
LASTB D0, P7, Z0.D
lastb d0, p0, z3.d
LASTB D0, P0, Z3.D
lastb d0, p0, z31.d
LASTB D0, P0, Z31.D
ld1b z0.s, p0/z, [x0,z0.s,uxtw]
ld1b {z0.s}, p0/z, [x0,z0.s,uxtw]
LD1B {Z0.S}, P0/Z, [X0,Z0.S,UXTW]
ld1b {z0.s}, p0/z, [x0,z0.s,uxtw #0]
ld1b z1.s, p0/z, [x0,z0.s,uxtw]
ld1b {z1.s}, p0/z, [x0,z0.s,uxtw]
LD1B {Z1.S}, P0/Z, [X0,Z0.S,UXTW]
ld1b {z1.s}, p0/z, [x0,z0.s,uxtw #0]
ld1b z31.s, p0/z, [x0,z0.s,uxtw]
ld1b {z31.s}, p0/z, [x0,z0.s,uxtw]
LD1B {Z31.S}, P0/Z, [X0,Z0.S,UXTW]
ld1b {z31.s}, p0/z, [x0,z0.s,uxtw #0]
ld1b {z0.s}, p2/z, [x0,z0.s,uxtw]
LD1B {Z0.S}, P2/Z, [X0,Z0.S,UXTW]
ld1b {z0.s}, p2/z, [x0,z0.s,uxtw #0]
ld1b {z0.s}, p7/z, [x0,z0.s,uxtw]
LD1B {Z0.S}, P7/Z, [X0,Z0.S,UXTW]
ld1b {z0.s}, p7/z, [x0,z0.s,uxtw #0]
ld1b {z0.s}, p0/z, [x3,z0.s,uxtw]
LD1B {Z0.S}, P0/Z, [X3,Z0.S,UXTW]
ld1b {z0.s}, p0/z, [x3,z0.s,uxtw #0]
ld1b {z0.s}, p0/z, [sp,z0.s,uxtw]
LD1B {Z0.S}, P0/Z, [SP,Z0.S,UXTW]
ld1b {z0.s}, p0/z, [sp,z0.s,uxtw #0]
ld1b {z0.s}, p0/z, [x0,z4.s,uxtw]
LD1B {Z0.S}, P0/Z, [X0,Z4.S,UXTW]
ld1b {z0.s}, p0/z, [x0,z4.s,uxtw #0]
ld1b {z0.s}, p0/z, [x0,z31.s,uxtw]
LD1B {Z0.S}, P0/Z, [X0,Z31.S,UXTW]
ld1b {z0.s}, p0/z, [x0,z31.s,uxtw #0]
ld1b z0.s, p0/z, [x0,z0.s,sxtw]
ld1b {z0.s}, p0/z, [x0,z0.s,sxtw]
LD1B {Z0.S}, P0/Z, [X0,Z0.S,SXTW]
ld1b {z0.s}, p0/z, [x0,z0.s,sxtw #0]
ld1b z1.s, p0/z, [x0,z0.s,sxtw]
ld1b {z1.s}, p0/z, [x0,z0.s,sxtw]
LD1B {Z1.S}, P0/Z, [X0,Z0.S,SXTW]
ld1b {z1.s}, p0/z, [x0,z0.s,sxtw #0]
ld1b z31.s, p0/z, [x0,z0.s,sxtw]
ld1b {z31.s}, p0/z, [x0,z0.s,sxtw]
LD1B {Z31.S}, P0/Z, [X0,Z0.S,SXTW]
ld1b {z31.s}, p0/z, [x0,z0.s,sxtw #0]
ld1b {z0.s}, p2/z, [x0,z0.s,sxtw]
LD1B {Z0.S}, P2/Z, [X0,Z0.S,SXTW]
ld1b {z0.s}, p2/z, [x0,z0.s,sxtw #0]
ld1b {z0.s}, p7/z, [x0,z0.s,sxtw]
LD1B {Z0.S}, P7/Z, [X0,Z0.S,SXTW]
ld1b {z0.s}, p7/z, [x0,z0.s,sxtw #0]
ld1b {z0.s}, p0/z, [x3,z0.s,sxtw]
LD1B {Z0.S}, P0/Z, [X3,Z0.S,SXTW]
ld1b {z0.s}, p0/z, [x3,z0.s,sxtw #0]
ld1b {z0.s}, p0/z, [sp,z0.s,sxtw]
LD1B {Z0.S}, P0/Z, [SP,Z0.S,SXTW]
ld1b {z0.s}, p0/z, [sp,z0.s,sxtw #0]
ld1b {z0.s}, p0/z, [x0,z4.s,sxtw]
LD1B {Z0.S}, P0/Z, [X0,Z4.S,SXTW]
ld1b {z0.s}, p0/z, [x0,z4.s,sxtw #0]
ld1b {z0.s}, p0/z, [x0,z31.s,sxtw]
LD1B {Z0.S}, P0/Z, [X0,Z31.S,SXTW]
ld1b {z0.s}, p0/z, [x0,z31.s,sxtw #0]
ld1b z0.b, p0/z, [x0,x0]
ld1b {z0.b}, p0/z, [x0,x0]
LD1B {Z0.B}, P0/Z, [X0,X0]
ld1b {z0.b}, p0/z, [x0,x0,lsl #0]
ld1b z1.b, p0/z, [x0,x0]
ld1b {z1.b}, p0/z, [x0,x0]
LD1B {Z1.B}, P0/Z, [X0,X0]
ld1b {z1.b}, p0/z, [x0,x0,lsl #0]
ld1b z31.b, p0/z, [x0,x0]
ld1b {z31.b}, p0/z, [x0,x0]
LD1B {Z31.B}, P0/Z, [X0,X0]
ld1b {z31.b}, p0/z, [x0,x0,lsl #0]
ld1b {z0.b}, p2/z, [x0,x0]
LD1B {Z0.B}, P2/Z, [X0,X0]
ld1b {z0.b}, p2/z, [x0,x0,lsl #0]
ld1b {z0.b}, p7/z, [x0,x0]
LD1B {Z0.B}, P7/Z, [X0,X0]
ld1b {z0.b}, p7/z, [x0,x0,lsl #0]
ld1b {z0.b}, p0/z, [x3,x0]
LD1B {Z0.B}, P0/Z, [X3,X0]
ld1b {z0.b}, p0/z, [x3,x0,lsl #0]
ld1b {z0.b}, p0/z, [sp,x0]
LD1B {Z0.B}, P0/Z, [SP,X0]
ld1b {z0.b}, p0/z, [sp,x0,lsl #0]
ld1b {z0.b}, p0/z, [x0,x4]
LD1B {Z0.B}, P0/Z, [X0,X4]
ld1b {z0.b}, p0/z, [x0,x4,lsl #0]
ld1b {z0.b}, p0/z, [x0,x30]
LD1B {Z0.B}, P0/Z, [X0,X30]
ld1b {z0.b}, p0/z, [x0,x30,lsl #0]
ld1b z0.h, p0/z, [x0,x0]
ld1b {z0.h}, p0/z, [x0,x0]
LD1B {Z0.H}, P0/Z, [X0,X0]
ld1b {z0.h}, p0/z, [x0,x0,lsl #0]
ld1b z1.h, p0/z, [x0,x0]
ld1b {z1.h}, p0/z, [x0,x0]
LD1B {Z1.H}, P0/Z, [X0,X0]
ld1b {z1.h}, p0/z, [x0,x0,lsl #0]
ld1b z31.h, p0/z, [x0,x0]
ld1b {z31.h}, p0/z, [x0,x0]
LD1B {Z31.H}, P0/Z, [X0,X0]
ld1b {z31.h}, p0/z, [x0,x0,lsl #0]
ld1b {z0.h}, p2/z, [x0,x0]
LD1B {Z0.H}, P2/Z, [X0,X0]
ld1b {z0.h}, p2/z, [x0,x0,lsl #0]
ld1b {z0.h}, p7/z, [x0,x0]
LD1B {Z0.H}, P7/Z, [X0,X0]
ld1b {z0.h}, p7/z, [x0,x0,lsl #0]
ld1b {z0.h}, p0/z, [x3,x0]
LD1B {Z0.H}, P0/Z, [X3,X0]
ld1b {z0.h}, p0/z, [x3,x0,lsl #0]
ld1b {z0.h}, p0/z, [sp,x0]
LD1B {Z0.H}, P0/Z, [SP,X0]
ld1b {z0.h}, p0/z, [sp,x0,lsl #0]
ld1b {z0.h}, p0/z, [x0,x4]
LD1B {Z0.H}, P0/Z, [X0,X4]
ld1b {z0.h}, p0/z, [x0,x4,lsl #0]
ld1b {z0.h}, p0/z, [x0,x30]
LD1B {Z0.H}, P0/Z, [X0,X30]
ld1b {z0.h}, p0/z, [x0,x30,lsl #0]
ld1b z0.s, p0/z, [x0,x0]
ld1b {z0.s}, p0/z, [x0,x0]
LD1B {Z0.S}, P0/Z, [X0,X0]
ld1b {z0.s}, p0/z, [x0,x0,lsl #0]
ld1b z1.s, p0/z, [x0,x0]
ld1b {z1.s}, p0/z, [x0,x0]
LD1B {Z1.S}, P0/Z, [X0,X0]
ld1b {z1.s}, p0/z, [x0,x0,lsl #0]
ld1b z31.s, p0/z, [x0,x0]
ld1b {z31.s}, p0/z, [x0,x0]
LD1B {Z31.S}, P0/Z, [X0,X0]
ld1b {z31.s}, p0/z, [x0,x0,lsl #0]
ld1b {z0.s}, p2/z, [x0,x0]
LD1B {Z0.S}, P2/Z, [X0,X0]
ld1b {z0.s}, p2/z, [x0,x0,lsl #0]
ld1b {z0.s}, p7/z, [x0,x0]
LD1B {Z0.S}, P7/Z, [X0,X0]
ld1b {z0.s}, p7/z, [x0,x0,lsl #0]
ld1b {z0.s}, p0/z, [x3,x0]
LD1B {Z0.S}, P0/Z, [X3,X0]
ld1b {z0.s}, p0/z, [x3,x0,lsl #0]
ld1b {z0.s}, p0/z, [sp,x0]
LD1B {Z0.S}, P0/Z, [SP,X0]
ld1b {z0.s}, p0/z, [sp,x0,lsl #0]
ld1b {z0.s}, p0/z, [x0,x4]
LD1B {Z0.S}, P0/Z, [X0,X4]
ld1b {z0.s}, p0/z, [x0,x4,lsl #0]
ld1b {z0.s}, p0/z, [x0,x30]
LD1B {Z0.S}, P0/Z, [X0,X30]
ld1b {z0.s}, p0/z, [x0,x30,lsl #0]
ld1b z0.d, p0/z, [x0,x0]
ld1b {z0.d}, p0/z, [x0,x0]
LD1B {Z0.D}, P0/Z, [X0,X0]
ld1b {z0.d}, p0/z, [x0,x0,lsl #0]
ld1b z1.d, p0/z, [x0,x0]
ld1b {z1.d}, p0/z, [x0,x0]
LD1B {Z1.D}, P0/Z, [X0,X0]
ld1b {z1.d}, p0/z, [x0,x0,lsl #0]
ld1b z31.d, p0/z, [x0,x0]
ld1b {z31.d}, p0/z, [x0,x0]
LD1B {Z31.D}, P0/Z, [X0,X0]
ld1b {z31.d}, p0/z, [x0,x0,lsl #0]
ld1b {z0.d}, p2/z, [x0,x0]
LD1B {Z0.D}, P2/Z, [X0,X0]
ld1b {z0.d}, p2/z, [x0,x0,lsl #0]
ld1b {z0.d}, p7/z, [x0,x0]
LD1B {Z0.D}, P7/Z, [X0,X0]
ld1b {z0.d}, p7/z, [x0,x0,lsl #0]
ld1b {z0.d}, p0/z, [x3,x0]
LD1B {Z0.D}, P0/Z, [X3,X0]
ld1b {z0.d}, p0/z, [x3,x0,lsl #0]
ld1b {z0.d}, p0/z, [sp,x0]
LD1B {Z0.D}, P0/Z, [SP,X0]
ld1b {z0.d}, p0/z, [sp,x0,lsl #0]
ld1b {z0.d}, p0/z, [x0,x4]
LD1B {Z0.D}, P0/Z, [X0,X4]
ld1b {z0.d}, p0/z, [x0,x4,lsl #0]
ld1b {z0.d}, p0/z, [x0,x30]
LD1B {Z0.D}, P0/Z, [X0,X30]
ld1b {z0.d}, p0/z, [x0,x30,lsl #0]
ld1b z0.d, p0/z, [x0,z0.d,uxtw]
ld1b {z0.d}, p0/z, [x0,z0.d,uxtw]
LD1B {Z0.D}, P0/Z, [X0,Z0.D,UXTW]
ld1b {z0.d}, p0/z, [x0,z0.d,uxtw #0]
ld1b z1.d, p0/z, [x0,z0.d,uxtw]
ld1b {z1.d}, p0/z, [x0,z0.d,uxtw]
LD1B {Z1.D}, P0/Z, [X0,Z0.D,UXTW]
ld1b {z1.d}, p0/z, [x0,z0.d,uxtw #0]
ld1b z31.d, p0/z, [x0,z0.d,uxtw]
ld1b {z31.d}, p0/z, [x0,z0.d,uxtw]
LD1B {Z31.D}, P0/Z, [X0,Z0.D,UXTW]
ld1b {z31.d}, p0/z, [x0,z0.d,uxtw #0]
ld1b {z0.d}, p2/z, [x0,z0.d,uxtw]
LD1B {Z0.D}, P2/Z, [X0,Z0.D,UXTW]
ld1b {z0.d}, p2/z, [x0,z0.d,uxtw #0]
ld1b {z0.d}, p7/z, [x0,z0.d,uxtw]
LD1B {Z0.D}, P7/Z, [X0,Z0.D,UXTW]
ld1b {z0.d}, p7/z, [x0,z0.d,uxtw #0]
ld1b {z0.d}, p0/z, [x3,z0.d,uxtw]
LD1B {Z0.D}, P0/Z, [X3,Z0.D,UXTW]
ld1b {z0.d}, p0/z, [x3,z0.d,uxtw #0]
ld1b {z0.d}, p0/z, [sp,z0.d,uxtw]
LD1B {Z0.D}, P0/Z, [SP,Z0.D,UXTW]
ld1b {z0.d}, p0/z, [sp,z0.d,uxtw #0]
ld1b {z0.d}, p0/z, [x0,z4.d,uxtw]
LD1B {Z0.D}, P0/Z, [X0,Z4.D,UXTW]
ld1b {z0.d}, p0/z, [x0,z4.d,uxtw #0]
ld1b {z0.d}, p0/z, [x0,z31.d,uxtw]
LD1B {Z0.D}, P0/Z, [X0,Z31.D,UXTW]
ld1b {z0.d}, p0/z, [x0,z31.d,uxtw #0]
ld1b z0.d, p0/z, [x0,z0.d,sxtw]
ld1b {z0.d}, p0/z, [x0,z0.d,sxtw]
LD1B {Z0.D}, P0/Z, [X0,Z0.D,SXTW]
ld1b {z0.d}, p0/z, [x0,z0.d,sxtw #0]
ld1b z1.d, p0/z, [x0,z0.d,sxtw]
ld1b {z1.d}, p0/z, [x0,z0.d,sxtw]
LD1B {Z1.D}, P0/Z, [X0,Z0.D,SXTW]
ld1b {z1.d}, p0/z, [x0,z0.d,sxtw #0]
ld1b z31.d, p0/z, [x0,z0.d,sxtw]
ld1b {z31.d}, p0/z, [x0,z0.d,sxtw]
LD1B {Z31.D}, P0/Z, [X0,Z0.D,SXTW]
ld1b {z31.d}, p0/z, [x0,z0.d,sxtw #0]
ld1b {z0.d}, p2/z, [x0,z0.d,sxtw]
LD1B {Z0.D}, P2/Z, [X0,Z0.D,SXTW]
ld1b {z0.d}, p2/z, [x0,z0.d,sxtw #0]
ld1b {z0.d}, p7/z, [x0,z0.d,sxtw]
LD1B {Z0.D}, P7/Z, [X0,Z0.D,SXTW]
ld1b {z0.d}, p7/z, [x0,z0.d,sxtw #0]
ld1b {z0.d}, p0/z, [x3,z0.d,sxtw]
LD1B {Z0.D}, P0/Z, [X3,Z0.D,SXTW]
ld1b {z0.d}, p0/z, [x3,z0.d,sxtw #0]
ld1b {z0.d}, p0/z, [sp,z0.d,sxtw]
LD1B {Z0.D}, P0/Z, [SP,Z0.D,SXTW]
ld1b {z0.d}, p0/z, [sp,z0.d,sxtw #0]
ld1b {z0.d}, p0/z, [x0,z4.d,sxtw]
LD1B {Z0.D}, P0/Z, [X0,Z4.D,SXTW]
ld1b {z0.d}, p0/z, [x0,z4.d,sxtw #0]
ld1b {z0.d}, p0/z, [x0,z31.d,sxtw]
LD1B {Z0.D}, P0/Z, [X0,Z31.D,SXTW]
ld1b {z0.d}, p0/z, [x0,z31.d,sxtw #0]
ld1b z0.d, p0/z, [x0,z0.d]
ld1b {z0.d}, p0/z, [x0,z0.d]
LD1B {Z0.D}, P0/Z, [X0,Z0.D]
ld1b {z0.d}, p0/z, [x0,z0.d,lsl #0]
ld1b z1.d, p0/z, [x0,z0.d]
ld1b {z1.d}, p0/z, [x0,z0.d]
LD1B {Z1.D}, P0/Z, [X0,Z0.D]
ld1b {z1.d}, p0/z, [x0,z0.d,lsl #0]
ld1b z31.d, p0/z, [x0,z0.d]
ld1b {z31.d}, p0/z, [x0,z0.d]
LD1B {Z31.D}, P0/Z, [X0,Z0.D]
ld1b {z31.d}, p0/z, [x0,z0.d,lsl #0]
ld1b {z0.d}, p2/z, [x0,z0.d]
LD1B {Z0.D}, P2/Z, [X0,Z0.D]
ld1b {z0.d}, p2/z, [x0,z0.d,lsl #0]
ld1b {z0.d}, p7/z, [x0,z0.d]
LD1B {Z0.D}, P7/Z, [X0,Z0.D]
ld1b {z0.d}, p7/z, [x0,z0.d,lsl #0]
ld1b {z0.d}, p0/z, [x3,z0.d]
LD1B {Z0.D}, P0/Z, [X3,Z0.D]
ld1b {z0.d}, p0/z, [x3,z0.d,lsl #0]
ld1b {z0.d}, p0/z, [sp,z0.d]
LD1B {Z0.D}, P0/Z, [SP,Z0.D]
ld1b {z0.d}, p0/z, [sp,z0.d,lsl #0]
ld1b {z0.d}, p0/z, [x0,z4.d]
LD1B {Z0.D}, P0/Z, [X0,Z4.D]
ld1b {z0.d}, p0/z, [x0,z4.d,lsl #0]
ld1b {z0.d}, p0/z, [x0,z31.d]
LD1B {Z0.D}, P0/Z, [X0,Z31.D]
ld1b {z0.d}, p0/z, [x0,z31.d,lsl #0]
ld1b z0.s, p0/z, [z0.s,#0]
ld1b {z0.s}, p0/z, [z0.s,#0]
LD1B {Z0.S}, P0/Z, [Z0.S,#0]
ld1b {z0.s}, p0/z, [z0.s]
ld1b z1.s, p0/z, [z0.s,#0]
ld1b {z1.s}, p0/z, [z0.s,#0]
LD1B {Z1.S}, P0/Z, [Z0.S,#0]
ld1b {z1.s}, p0/z, [z0.s]
ld1b z31.s, p0/z, [z0.s,#0]
ld1b {z31.s}, p0/z, [z0.s,#0]
LD1B {Z31.S}, P0/Z, [Z0.S,#0]
ld1b {z31.s}, p0/z, [z0.s]
ld1b {z0.s}, p2/z, [z0.s,#0]
LD1B {Z0.S}, P2/Z, [Z0.S,#0]
ld1b {z0.s}, p2/z, [z0.s]
ld1b {z0.s}, p7/z, [z0.s,#0]
LD1B {Z0.S}, P7/Z, [Z0.S,#0]
ld1b {z0.s}, p7/z, [z0.s]
ld1b {z0.s}, p0/z, [z3.s,#0]
LD1B {Z0.S}, P0/Z, [Z3.S,#0]
ld1b {z0.s}, p0/z, [z3.s]
ld1b {z0.s}, p0/z, [z31.s,#0]
LD1B {Z0.S}, P0/Z, [Z31.S,#0]
ld1b {z0.s}, p0/z, [z31.s]
ld1b {z0.s}, p0/z, [z0.s,#15]
LD1B {Z0.S}, P0/Z, [Z0.S,#15]
ld1b {z0.s}, p0/z, [z0.s,#16]
LD1B {Z0.S}, P0/Z, [Z0.S,#16]
ld1b {z0.s}, p0/z, [z0.s,#17]
LD1B {Z0.S}, P0/Z, [Z0.S,#17]
ld1b {z0.s}, p0/z, [z0.s,#31]
LD1B {Z0.S}, P0/Z, [Z0.S,#31]
ld1b z0.b, p0/z, [x0,#0]
ld1b {z0.b}, p0/z, [x0,#0]
LD1B {Z0.B}, P0/Z, [X0,#0]
ld1b {z0.b}, p0/z, [x0,#0,mul vl]
ld1b {z0.b}, p0/z, [x0]
ld1b z1.b, p0/z, [x0,#0]
ld1b {z1.b}, p0/z, [x0,#0]
LD1B {Z1.B}, P0/Z, [X0,#0]
ld1b {z1.b}, p0/z, [x0,#0,mul vl]
ld1b {z1.b}, p0/z, [x0]
ld1b z31.b, p0/z, [x0,#0]
ld1b {z31.b}, p0/z, [x0,#0]
LD1B {Z31.B}, P0/Z, [X0,#0]
ld1b {z31.b}, p0/z, [x0,#0,mul vl]
ld1b {z31.b}, p0/z, [x0]
ld1b {z0.b}, p2/z, [x0,#0]
LD1B {Z0.B}, P2/Z, [X0,#0]
ld1b {z0.b}, p2/z, [x0,#0,mul vl]
ld1b {z0.b}, p2/z, [x0]
ld1b {z0.b}, p7/z, [x0,#0]
LD1B {Z0.B}, P7/Z, [X0,#0]
ld1b {z0.b}, p7/z, [x0,#0,mul vl]
ld1b {z0.b}, p7/z, [x0]
ld1b {z0.b}, p0/z, [x3,#0]
LD1B {Z0.B}, P0/Z, [X3,#0]
ld1b {z0.b}, p0/z, [x3,#0,mul vl]
ld1b {z0.b}, p0/z, [x3]
ld1b {z0.b}, p0/z, [sp,#0]
LD1B {Z0.B}, P0/Z, [SP,#0]
ld1b {z0.b}, p0/z, [sp,#0,mul vl]
ld1b {z0.b}, p0/z, [sp]
ld1b {z0.b}, p0/z, [x0,#7,mul vl]
LD1B {Z0.B}, P0/Z, [X0,#7,MUL VL]
ld1b {z0.b}, p0/z, [x0,#-8,mul vl]
LD1B {Z0.B}, P0/Z, [X0,#-8,MUL VL]
ld1b {z0.b}, p0/z, [x0,#-7,mul vl]
LD1B {Z0.B}, P0/Z, [X0,#-7,MUL VL]
ld1b {z0.b}, p0/z, [x0,#-1,mul vl]
LD1B {Z0.B}, P0/Z, [X0,#-1,MUL VL]
ld1b z0.h, p0/z, [x0,#0]
ld1b {z0.h}, p0/z, [x0,#0]
LD1B {Z0.H}, P0/Z, [X0,#0]
ld1b {z0.h}, p0/z, [x0,#0,mul vl]
ld1b {z0.h}, p0/z, [x0]
ld1b z1.h, p0/z, [x0,#0]
ld1b {z1.h}, p0/z, [x0,#0]
LD1B {Z1.H}, P0/Z, [X0,#0]
ld1b {z1.h}, p0/z, [x0,#0,mul vl]
ld1b {z1.h}, p0/z, [x0]
ld1b z31.h, p0/z, [x0,#0]
ld1b {z31.h}, p0/z, [x0,#0]
LD1B {Z31.H}, P0/Z, [X0,#0]
ld1b {z31.h}, p0/z, [x0,#0,mul vl]
ld1b {z31.h}, p0/z, [x0]
ld1b {z0.h}, p2/z, [x0,#0]
LD1B {Z0.H}, P2/Z, [X0,#0]
ld1b {z0.h}, p2/z, [x0,#0,mul vl]
ld1b {z0.h}, p2/z, [x0]
ld1b {z0.h}, p7/z, [x0,#0]
LD1B {Z0.H}, P7/Z, [X0,#0]
ld1b {z0.h}, p7/z, [x0,#0,mul vl]
ld1b {z0.h}, p7/z, [x0]
ld1b {z0.h}, p0/z, [x3,#0]
LD1B {Z0.H}, P0/Z, [X3,#0]
ld1b {z0.h}, p0/z, [x3,#0,mul vl]
ld1b {z0.h}, p0/z, [x3]
ld1b {z0.h}, p0/z, [sp,#0]
LD1B {Z0.H}, P0/Z, [SP,#0]
ld1b {z0.h}, p0/z, [sp,#0,mul vl]
ld1b {z0.h}, p0/z, [sp]
ld1b {z0.h}, p0/z, [x0,#7,mul vl]
LD1B {Z0.H}, P0/Z, [X0,#7,MUL VL]
ld1b {z0.h}, p0/z, [x0,#-8,mul vl]
LD1B {Z0.H}, P0/Z, [X0,#-8,MUL VL]
ld1b {z0.h}, p0/z, [x0,#-7,mul vl]
LD1B {Z0.H}, P0/Z, [X0,#-7,MUL VL]
ld1b {z0.h}, p0/z, [x0,#-1,mul vl]
LD1B {Z0.H}, P0/Z, [X0,#-1,MUL VL]
ld1b z0.s, p0/z, [x0,#0]
ld1b {z0.s}, p0/z, [x0,#0]
LD1B {Z0.S}, P0/Z, [X0,#0]
ld1b {z0.s}, p0/z, [x0,#0,mul vl]
ld1b {z0.s}, p0/z, [x0]
ld1b z1.s, p0/z, [x0,#0]
ld1b {z1.s}, p0/z, [x0,#0]
LD1B {Z1.S}, P0/Z, [X0,#0]
ld1b {z1.s}, p0/z, [x0,#0,mul vl]
ld1b {z1.s}, p0/z, [x0]
ld1b z31.s, p0/z, [x0,#0]
ld1b {z31.s}, p0/z, [x0,#0]
LD1B {Z31.S}, P0/Z, [X0,#0]
ld1b {z31.s}, p0/z, [x0,#0,mul vl]
ld1b {z31.s}, p0/z, [x0]
ld1b {z0.s}, p2/z, [x0,#0]
LD1B {Z0.S}, P2/Z, [X0,#0]
ld1b {z0.s}, p2/z, [x0,#0,mul vl]
ld1b {z0.s}, p2/z, [x0]
ld1b {z0.s}, p7/z, [x0,#0]
LD1B {Z0.S}, P7/Z, [X0,#0]
ld1b {z0.s}, p7/z, [x0,#0,mul vl]
ld1b {z0.s}, p7/z, [x0]
ld1b {z0.s}, p0/z, [x3,#0]
LD1B {Z0.S}, P0/Z, [X3,#0]
ld1b {z0.s}, p0/z, [x3,#0,mul vl]
ld1b {z0.s}, p0/z, [x3]
ld1b {z0.s}, p0/z, [sp,#0]
LD1B {Z0.S}, P0/Z, [SP,#0]
ld1b {z0.s}, p0/z, [sp,#0,mul vl]
ld1b {z0.s}, p0/z, [sp]
ld1b {z0.s}, p0/z, [x0,#7,mul vl]
LD1B {Z0.S}, P0/Z, [X0,#7,MUL VL]
ld1b {z0.s}, p0/z, [x0,#-8,mul vl]
LD1B {Z0.S}, P0/Z, [X0,#-8,MUL VL]
ld1b {z0.s}, p0/z, [x0,#-7,mul vl]
LD1B {Z0.S}, P0/Z, [X0,#-7,MUL VL]
ld1b {z0.s}, p0/z, [x0,#-1,mul vl]
LD1B {Z0.S}, P0/Z, [X0,#-1,MUL VL]
ld1b z0.d, p0/z, [x0,#0]
ld1b {z0.d}, p0/z, [x0,#0]
LD1B {Z0.D}, P0/Z, [X0,#0]
ld1b {z0.d}, p0/z, [x0,#0,mul vl]
ld1b {z0.d}, p0/z, [x0]
ld1b z1.d, p0/z, [x0,#0]
ld1b {z1.d}, p0/z, [x0,#0]
LD1B {Z1.D}, P0/Z, [X0,#0]
ld1b {z1.d}, p0/z, [x0,#0,mul vl]
ld1b {z1.d}, p0/z, [x0]
ld1b z31.d, p0/z, [x0,#0]
ld1b {z31.d}, p0/z, [x0,#0]
LD1B {Z31.D}, P0/Z, [X0,#0]
ld1b {z31.d}, p0/z, [x0,#0,mul vl]
ld1b {z31.d}, p0/z, [x0]
ld1b {z0.d}, p2/z, [x0,#0]
LD1B {Z0.D}, P2/Z, [X0,#0]
ld1b {z0.d}, p2/z, [x0,#0,mul vl]
ld1b {z0.d}, p2/z, [x0]
ld1b {z0.d}, p7/z, [x0,#0]
LD1B {Z0.D}, P7/Z, [X0,#0]
ld1b {z0.d}, p7/z, [x0,#0,mul vl]
ld1b {z0.d}, p7/z, [x0]
ld1b {z0.d}, p0/z, [x3,#0]
LD1B {Z0.D}, P0/Z, [X3,#0]
ld1b {z0.d}, p0/z, [x3,#0,mul vl]
ld1b {z0.d}, p0/z, [x3]
ld1b {z0.d}, p0/z, [sp,#0]
LD1B {Z0.D}, P0/Z, [SP,#0]
ld1b {z0.d}, p0/z, [sp,#0,mul vl]
ld1b {z0.d}, p0/z, [sp]
ld1b {z0.d}, p0/z, [x0,#7,mul vl]
LD1B {Z0.D}, P0/Z, [X0,#7,MUL VL]
ld1b {z0.d}, p0/z, [x0,#-8,mul vl]
LD1B {Z0.D}, P0/Z, [X0,#-8,MUL VL]
ld1b {z0.d}, p0/z, [x0,#-7,mul vl]
LD1B {Z0.D}, P0/Z, [X0,#-7,MUL VL]
ld1b {z0.d}, p0/z, [x0,#-1,mul vl]
LD1B {Z0.D}, P0/Z, [X0,#-1,MUL VL]
ld1b z0.d, p0/z, [z0.d,#0]
ld1b {z0.d}, p0/z, [z0.d,#0]
LD1B {Z0.D}, P0/Z, [Z0.D,#0]
ld1b {z0.d}, p0/z, [z0.d]
ld1b z1.d, p0/z, [z0.d,#0]
ld1b {z1.d}, p0/z, [z0.d,#0]
LD1B {Z1.D}, P0/Z, [Z0.D,#0]
ld1b {z1.d}, p0/z, [z0.d]
ld1b z31.d, p0/z, [z0.d,#0]
ld1b {z31.d}, p0/z, [z0.d,#0]
LD1B {Z31.D}, P0/Z, [Z0.D,#0]
ld1b {z31.d}, p0/z, [z0.d]
ld1b {z0.d}, p2/z, [z0.d,#0]
LD1B {Z0.D}, P2/Z, [Z0.D,#0]
ld1b {z0.d}, p2/z, [z0.d]
ld1b {z0.d}, p7/z, [z0.d,#0]
LD1B {Z0.D}, P7/Z, [Z0.D,#0]
ld1b {z0.d}, p7/z, [z0.d]
ld1b {z0.d}, p0/z, [z3.d,#0]
LD1B {Z0.D}, P0/Z, [Z3.D,#0]
ld1b {z0.d}, p0/z, [z3.d]
ld1b {z0.d}, p0/z, [z31.d,#0]
LD1B {Z0.D}, P0/Z, [Z31.D,#0]
ld1b {z0.d}, p0/z, [z31.d]
ld1b {z0.d}, p0/z, [z0.d,#15]
LD1B {Z0.D}, P0/Z, [Z0.D,#15]
ld1b {z0.d}, p0/z, [z0.d,#16]
LD1B {Z0.D}, P0/Z, [Z0.D,#16]
ld1b {z0.d}, p0/z, [z0.d,#17]
LD1B {Z0.D}, P0/Z, [Z0.D,#17]
ld1b {z0.d}, p0/z, [z0.d,#31]
LD1B {Z0.D}, P0/Z, [Z0.D,#31]
ld1d z0.d, p0/z, [x0,x0,lsl #3]
ld1d {z0.d}, p0/z, [x0,x0,lsl #3]
LD1D {Z0.D}, P0/Z, [X0,X0,LSL #3]
ld1d z1.d, p0/z, [x0,x0,lsl #3]
ld1d {z1.d}, p0/z, [x0,x0,lsl #3]
LD1D {Z1.D}, P0/Z, [X0,X0,LSL #3]
ld1d z31.d, p0/z, [x0,x0,lsl #3]
ld1d {z31.d}, p0/z, [x0,x0,lsl #3]
LD1D {Z31.D}, P0/Z, [X0,X0,LSL #3]
ld1d {z0.d}, p2/z, [x0,x0,lsl #3]
LD1D {Z0.D}, P2/Z, [X0,X0,LSL #3]
ld1d {z0.d}, p7/z, [x0,x0,lsl #3]
LD1D {Z0.D}, P7/Z, [X0,X0,LSL #3]
ld1d {z0.d}, p0/z, [x3,x0,lsl #3]
LD1D {Z0.D}, P0/Z, [X3,X0,LSL #3]
ld1d {z0.d}, p0/z, [sp,x0,lsl #3]
LD1D {Z0.D}, P0/Z, [SP,X0,LSL #3]
ld1d {z0.d}, p0/z, [x0,x4,lsl #3]
LD1D {Z0.D}, P0/Z, [X0,X4,LSL #3]
ld1d {z0.d}, p0/z, [x0,x30,lsl #3]
LD1D {Z0.D}, P0/Z, [X0,X30,LSL #3]
ld1d z0.d, p0/z, [x0,z0.d,uxtw]
ld1d {z0.d}, p0/z, [x0,z0.d,uxtw]
LD1D {Z0.D}, P0/Z, [X0,Z0.D,UXTW]
ld1d {z0.d}, p0/z, [x0,z0.d,uxtw #0]
ld1d z1.d, p0/z, [x0,z0.d,uxtw]
ld1d {z1.d}, p0/z, [x0,z0.d,uxtw]
LD1D {Z1.D}, P0/Z, [X0,Z0.D,UXTW]
ld1d {z1.d}, p0/z, [x0,z0.d,uxtw #0]
ld1d z31.d, p0/z, [x0,z0.d,uxtw]
ld1d {z31.d}, p0/z, [x0,z0.d,uxtw]
LD1D {Z31.D}, P0/Z, [X0,Z0.D,UXTW]
ld1d {z31.d}, p0/z, [x0,z0.d,uxtw #0]
ld1d {z0.d}, p2/z, [x0,z0.d,uxtw]
LD1D {Z0.D}, P2/Z, [X0,Z0.D,UXTW]
ld1d {z0.d}, p2/z, [x0,z0.d,uxtw #0]
ld1d {z0.d}, p7/z, [x0,z0.d,uxtw]
LD1D {Z0.D}, P7/Z, [X0,Z0.D,UXTW]
ld1d {z0.d}, p7/z, [x0,z0.d,uxtw #0]
ld1d {z0.d}, p0/z, [x3,z0.d,uxtw]
LD1D {Z0.D}, P0/Z, [X3,Z0.D,UXTW]
ld1d {z0.d}, p0/z, [x3,z0.d,uxtw #0]
ld1d {z0.d}, p0/z, [sp,z0.d,uxtw]
LD1D {Z0.D}, P0/Z, [SP,Z0.D,UXTW]
ld1d {z0.d}, p0/z, [sp,z0.d,uxtw #0]
ld1d {z0.d}, p0/z, [x0,z4.d,uxtw]
LD1D {Z0.D}, P0/Z, [X0,Z4.D,UXTW]
ld1d {z0.d}, p0/z, [x0,z4.d,uxtw #0]
ld1d {z0.d}, p0/z, [x0,z31.d,uxtw]
LD1D {Z0.D}, P0/Z, [X0,Z31.D,UXTW]
ld1d {z0.d}, p0/z, [x0,z31.d,uxtw #0]
ld1d z0.d, p0/z, [x0,z0.d,sxtw]
ld1d {z0.d}, p0/z, [x0,z0.d,sxtw]
LD1D {Z0.D}, P0/Z, [X0,Z0.D,SXTW]
ld1d {z0.d}, p0/z, [x0,z0.d,sxtw #0]
ld1d z1.d, p0/z, [x0,z0.d,sxtw]
ld1d {z1.d}, p0/z, [x0,z0.d,sxtw]
LD1D {Z1.D}, P0/Z, [X0,Z0.D,SXTW]
ld1d {z1.d}, p0/z, [x0,z0.d,sxtw #0]
ld1d z31.d, p0/z, [x0,z0.d,sxtw]
ld1d {z31.d}, p0/z, [x0,z0.d,sxtw]
LD1D {Z31.D}, P0/Z, [X0,Z0.D,SXTW]
ld1d {z31.d}, p0/z, [x0,z0.d,sxtw #0]
ld1d {z0.d}, p2/z, [x0,z0.d,sxtw]
LD1D {Z0.D}, P2/Z, [X0,Z0.D,SXTW]
ld1d {z0.d}, p2/z, [x0,z0.d,sxtw #0]
ld1d {z0.d}, p7/z, [x0,z0.d,sxtw]
LD1D {Z0.D}, P7/Z, [X0,Z0.D,SXTW]
ld1d {z0.d}, p7/z, [x0,z0.d,sxtw #0]
ld1d {z0.d}, p0/z, [x3,z0.d,sxtw]
LD1D {Z0.D}, P0/Z, [X3,Z0.D,SXTW]
ld1d {z0.d}, p0/z, [x3,z0.d,sxtw #0]
ld1d {z0.d}, p0/z, [sp,z0.d,sxtw]
LD1D {Z0.D}, P0/Z, [SP,Z0.D,SXTW]
ld1d {z0.d}, p0/z, [sp,z0.d,sxtw #0]
ld1d {z0.d}, p0/z, [x0,z4.d,sxtw]
LD1D {Z0.D}, P0/Z, [X0,Z4.D,SXTW]
ld1d {z0.d}, p0/z, [x0,z4.d,sxtw #0]
ld1d {z0.d}, p0/z, [x0,z31.d,sxtw]
LD1D {Z0.D}, P0/Z, [X0,Z31.D,SXTW]
ld1d {z0.d}, p0/z, [x0,z31.d,sxtw #0]
ld1d z0.d, p0/z, [x0,z0.d,uxtw #3]
ld1d {z0.d}, p0/z, [x0,z0.d,uxtw #3]
LD1D {Z0.D}, P0/Z, [X0,Z0.D,UXTW #3]
ld1d z1.d, p0/z, [x0,z0.d,uxtw #3]
ld1d {z1.d}, p0/z, [x0,z0.d,uxtw #3]
LD1D {Z1.D}, P0/Z, [X0,Z0.D,UXTW #3]
ld1d z31.d, p0/z, [x0,z0.d,uxtw #3]
ld1d {z31.d}, p0/z, [x0,z0.d,uxtw #3]
LD1D {Z31.D}, P0/Z, [X0,Z0.D,UXTW #3]
ld1d {z0.d}, p2/z, [x0,z0.d,uxtw #3]
LD1D {Z0.D}, P2/Z, [X0,Z0.D,UXTW #3]
ld1d {z0.d}, p7/z, [x0,z0.d,uxtw #3]
LD1D {Z0.D}, P7/Z, [X0,Z0.D,UXTW #3]
ld1d {z0.d}, p0/z, [x3,z0.d,uxtw #3]
LD1D {Z0.D}, P0/Z, [X3,Z0.D,UXTW #3]
ld1d {z0.d}, p0/z, [sp,z0.d,uxtw #3]
LD1D {Z0.D}, P0/Z, [SP,Z0.D,UXTW #3]
ld1d {z0.d}, p0/z, [x0,z4.d,uxtw #3]
LD1D {Z0.D}, P0/Z, [X0,Z4.D,UXTW #3]
ld1d {z0.d}, p0/z, [x0,z31.d,uxtw #3]
LD1D {Z0.D}, P0/Z, [X0,Z31.D,UXTW #3]
ld1d z0.d, p0/z, [x0,z0.d,sxtw #3]
ld1d {z0.d}, p0/z, [x0,z0.d,sxtw #3]
LD1D {Z0.D}, P0/Z, [X0,Z0.D,SXTW #3]
ld1d z1.d, p0/z, [x0,z0.d,sxtw #3]
ld1d {z1.d}, p0/z, [x0,z0.d,sxtw #3]
LD1D {Z1.D}, P0/Z, [X0,Z0.D,SXTW #3]
ld1d z31.d, p0/z, [x0,z0.d,sxtw #3]
ld1d {z31.d}, p0/z, [x0,z0.d,sxtw #3]
LD1D {Z31.D}, P0/Z, [X0,Z0.D,SXTW #3]
ld1d {z0.d}, p2/z, [x0,z0.d,sxtw #3]
LD1D {Z0.D}, P2/Z, [X0,Z0.D,SXTW #3]
ld1d {z0.d}, p7/z, [x0,z0.d,sxtw #3]
LD1D {Z0.D}, P7/Z, [X0,Z0.D,SXTW #3]
ld1d {z0.d}, p0/z, [x3,z0.d,sxtw #3]
LD1D {Z0.D}, P0/Z, [X3,Z0.D,SXTW #3]
ld1d {z0.d}, p0/z, [sp,z0.d,sxtw #3]
LD1D {Z0.D}, P0/Z, [SP,Z0.D,SXTW #3]
ld1d {z0.d}, p0/z, [x0,z4.d,sxtw #3]
LD1D {Z0.D}, P0/Z, [X0,Z4.D,SXTW #3]
ld1d {z0.d}, p0/z, [x0,z31.d,sxtw #3]
LD1D {Z0.D}, P0/Z, [X0,Z31.D,SXTW #3]
ld1d z0.d, p0/z, [x0,z0.d]
ld1d {z0.d}, p0/z, [x0,z0.d]
LD1D {Z0.D}, P0/Z, [X0,Z0.D]
ld1d {z0.d}, p0/z, [x0,z0.d,lsl #0]
ld1d z1.d, p0/z, [x0,z0.d]
ld1d {z1.d}, p0/z, [x0,z0.d]
LD1D {Z1.D}, P0/Z, [X0,Z0.D]
ld1d {z1.d}, p0/z, [x0,z0.d,lsl #0]
ld1d z31.d, p0/z, [x0,z0.d]
ld1d {z31.d}, p0/z, [x0,z0.d]
LD1D {Z31.D}, P0/Z, [X0,Z0.D]
ld1d {z31.d}, p0/z, [x0,z0.d,lsl #0]
ld1d {z0.d}, p2/z, [x0,z0.d]
LD1D {Z0.D}, P2/Z, [X0,Z0.D]
ld1d {z0.d}, p2/z, [x0,z0.d,lsl #0]
ld1d {z0.d}, p7/z, [x0,z0.d]
LD1D {Z0.D}, P7/Z, [X0,Z0.D]
ld1d {z0.d}, p7/z, [x0,z0.d,lsl #0]
ld1d {z0.d}, p0/z, [x3,z0.d]
LD1D {Z0.D}, P0/Z, [X3,Z0.D]
ld1d {z0.d}, p0/z, [x3,z0.d,lsl #0]
ld1d {z0.d}, p0/z, [sp,z0.d]
LD1D {Z0.D}, P0/Z, [SP,Z0.D]
ld1d {z0.d}, p0/z, [sp,z0.d,lsl #0]
ld1d {z0.d}, p0/z, [x0,z4.d]
LD1D {Z0.D}, P0/Z, [X0,Z4.D]
ld1d {z0.d}, p0/z, [x0,z4.d,lsl #0]
ld1d {z0.d}, p0/z, [x0,z31.d]
LD1D {Z0.D}, P0/Z, [X0,Z31.D]
ld1d {z0.d}, p0/z, [x0,z31.d,lsl #0]
ld1d z0.d, p0/z, [x0,z0.d,lsl #3]
ld1d {z0.d}, p0/z, [x0,z0.d,lsl #3]
LD1D {Z0.D}, P0/Z, [X0,Z0.D,LSL #3]
ld1d z1.d, p0/z, [x0,z0.d,lsl #3]
ld1d {z1.d}, p0/z, [x0,z0.d,lsl #3]
LD1D {Z1.D}, P0/Z, [X0,Z0.D,LSL #3]
ld1d z31.d, p0/z, [x0,z0.d,lsl #3]
ld1d {z31.d}, p0/z, [x0,z0.d,lsl #3]
LD1D {Z31.D}, P0/Z, [X0,Z0.D,LSL #3]
ld1d {z0.d}, p2/z, [x0,z0.d,lsl #3]
LD1D {Z0.D}, P2/Z, [X0,Z0.D,LSL #3]
ld1d {z0.d}, p7/z, [x0,z0.d,lsl #3]
LD1D {Z0.D}, P7/Z, [X0,Z0.D,LSL #3]
ld1d {z0.d}, p0/z, [x3,z0.d,lsl #3]
LD1D {Z0.D}, P0/Z, [X3,Z0.D,LSL #3]
ld1d {z0.d}, p0/z, [sp,z0.d,lsl #3]
LD1D {Z0.D}, P0/Z, [SP,Z0.D,LSL #3]
ld1d {z0.d}, p0/z, [x0,z4.d,lsl #3]
LD1D {Z0.D}, P0/Z, [X0,Z4.D,LSL #3]
ld1d {z0.d}, p0/z, [x0,z31.d,lsl #3]
LD1D {Z0.D}, P0/Z, [X0,Z31.D,LSL #3]
ld1d z0.d, p0/z, [x0,#0]
ld1d {z0.d}, p0/z, [x0,#0]
LD1D {Z0.D}, P0/Z, [X0,#0]
ld1d {z0.d}, p0/z, [x0,#0,mul vl]
ld1d {z0.d}, p0/z, [x0]
ld1d z1.d, p0/z, [x0,#0]
ld1d {z1.d}, p0/z, [x0,#0]
LD1D {Z1.D}, P0/Z, [X0,#0]
ld1d {z1.d}, p0/z, [x0,#0,mul vl]
ld1d {z1.d}, p0/z, [x0]
ld1d z31.d, p0/z, [x0,#0]
ld1d {z31.d}, p0/z, [x0,#0]
LD1D {Z31.D}, P0/Z, [X0,#0]
ld1d {z31.d}, p0/z, [x0,#0,mul vl]
ld1d {z31.d}, p0/z, [x0]
ld1d {z0.d}, p2/z, [x0,#0]
LD1D {Z0.D}, P2/Z, [X0,#0]
ld1d {z0.d}, p2/z, [x0,#0,mul vl]
ld1d {z0.d}, p2/z, [x0]
ld1d {z0.d}, p7/z, [x0,#0]
LD1D {Z0.D}, P7/Z, [X0,#0]
ld1d {z0.d}, p7/z, [x0,#0,mul vl]
ld1d {z0.d}, p7/z, [x0]
ld1d {z0.d}, p0/z, [x3,#0]
LD1D {Z0.D}, P0/Z, [X3,#0]
ld1d {z0.d}, p0/z, [x3,#0,mul vl]
ld1d {z0.d}, p0/z, [x3]
ld1d {z0.d}, p0/z, [sp,#0]
LD1D {Z0.D}, P0/Z, [SP,#0]
ld1d {z0.d}, p0/z, [sp,#0,mul vl]
ld1d {z0.d}, p0/z, [sp]
ld1d {z0.d}, p0/z, [x0,#7,mul vl]
LD1D {Z0.D}, P0/Z, [X0,#7,MUL VL]
ld1d {z0.d}, p0/z, [x0,#-8,mul vl]
LD1D {Z0.D}, P0/Z, [X0,#-8,MUL VL]
ld1d {z0.d}, p0/z, [x0,#-7,mul vl]
LD1D {Z0.D}, P0/Z, [X0,#-7,MUL VL]
ld1d {z0.d}, p0/z, [x0,#-1,mul vl]
LD1D {Z0.D}, P0/Z, [X0,#-1,MUL VL]
ld1d z0.d, p0/z, [z0.d,#0]
ld1d {z0.d}, p0/z, [z0.d,#0]
LD1D {Z0.D}, P0/Z, [Z0.D,#0]
ld1d {z0.d}, p0/z, [z0.d]
ld1d z1.d, p0/z, [z0.d,#0]
ld1d {z1.d}, p0/z, [z0.d,#0]
LD1D {Z1.D}, P0/Z, [Z0.D,#0]
ld1d {z1.d}, p0/z, [z0.d]
ld1d z31.d, p0/z, [z0.d,#0]
ld1d {z31.d}, p0/z, [z0.d,#0]
LD1D {Z31.D}, P0/Z, [Z0.D,#0]
ld1d {z31.d}, p0/z, [z0.d]
ld1d {z0.d}, p2/z, [z0.d,#0]
LD1D {Z0.D}, P2/Z, [Z0.D,#0]
ld1d {z0.d}, p2/z, [z0.d]
ld1d {z0.d}, p7/z, [z0.d,#0]
LD1D {Z0.D}, P7/Z, [Z0.D,#0]
ld1d {z0.d}, p7/z, [z0.d]
ld1d {z0.d}, p0/z, [z3.d,#0]
LD1D {Z0.D}, P0/Z, [Z3.D,#0]
ld1d {z0.d}, p0/z, [z3.d]
ld1d {z0.d}, p0/z, [z31.d,#0]
LD1D {Z0.D}, P0/Z, [Z31.D,#0]
ld1d {z0.d}, p0/z, [z31.d]
ld1d {z0.d}, p0/z, [z0.d,#120]
LD1D {Z0.D}, P0/Z, [Z0.D,#120]
ld1d {z0.d}, p0/z, [z0.d,#128]
LD1D {Z0.D}, P0/Z, [Z0.D,#128]
ld1d {z0.d}, p0/z, [z0.d,#136]
LD1D {Z0.D}, P0/Z, [Z0.D,#136]
ld1d {z0.d}, p0/z, [z0.d,#248]
LD1D {Z0.D}, P0/Z, [Z0.D,#248]
ld1h z0.s, p0/z, [x0,z0.s,uxtw]
ld1h {z0.s}, p0/z, [x0,z0.s,uxtw]
LD1H {Z0.S}, P0/Z, [X0,Z0.S,UXTW]
ld1h {z0.s}, p0/z, [x0,z0.s,uxtw #0]
ld1h z1.s, p0/z, [x0,z0.s,uxtw]
ld1h {z1.s}, p0/z, [x0,z0.s,uxtw]
LD1H {Z1.S}, P0/Z, [X0,Z0.S,UXTW]
ld1h {z1.s}, p0/z, [x0,z0.s,uxtw #0]
ld1h z31.s, p0/z, [x0,z0.s,uxtw]
ld1h {z31.s}, p0/z, [x0,z0.s,uxtw]
LD1H {Z31.S}, P0/Z, [X0,Z0.S,UXTW]
ld1h {z31.s}, p0/z, [x0,z0.s,uxtw #0]
ld1h {z0.s}, p2/z, [x0,z0.s,uxtw]
LD1H {Z0.S}, P2/Z, [X0,Z0.S,UXTW]
ld1h {z0.s}, p2/z, [x0,z0.s,uxtw #0]
ld1h {z0.s}, p7/z, [x0,z0.s,uxtw]
LD1H {Z0.S}, P7/Z, [X0,Z0.S,UXTW]
ld1h {z0.s}, p7/z, [x0,z0.s,uxtw #0]
ld1h {z0.s}, p0/z, [x3,z0.s,uxtw]
LD1H {Z0.S}, P0/Z, [X3,Z0.S,UXTW]
ld1h {z0.s}, p0/z, [x3,z0.s,uxtw #0]
ld1h {z0.s}, p0/z, [sp,z0.s,uxtw]
LD1H {Z0.S}, P0/Z, [SP,Z0.S,UXTW]
ld1h {z0.s}, p0/z, [sp,z0.s,uxtw #0]
ld1h {z0.s}, p0/z, [x0,z4.s,uxtw]
LD1H {Z0.S}, P0/Z, [X0,Z4.S,UXTW]
ld1h {z0.s}, p0/z, [x0,z4.s,uxtw #0]
ld1h {z0.s}, p0/z, [x0,z31.s,uxtw]
LD1H {Z0.S}, P0/Z, [X0,Z31.S,UXTW]
ld1h {z0.s}, p0/z, [x0,z31.s,uxtw #0]
ld1h z0.s, p0/z, [x0,z0.s,sxtw]
ld1h {z0.s}, p0/z, [x0,z0.s,sxtw]
LD1H {Z0.S}, P0/Z, [X0,Z0.S,SXTW]
ld1h {z0.s}, p0/z, [x0,z0.s,sxtw #0]
ld1h z1.s, p0/z, [x0,z0.s,sxtw]
ld1h {z1.s}, p0/z, [x0,z0.s,sxtw]
LD1H {Z1.S}, P0/Z, [X0,Z0.S,SXTW]
ld1h {z1.s}, p0/z, [x0,z0.s,sxtw #0]
ld1h z31.s, p0/z, [x0,z0.s,sxtw]
ld1h {z31.s}, p0/z, [x0,z0.s,sxtw]
LD1H {Z31.S}, P0/Z, [X0,Z0.S,SXTW]
ld1h {z31.s}, p0/z, [x0,z0.s,sxtw #0]
ld1h {z0.s}, p2/z, [x0,z0.s,sxtw]
LD1H {Z0.S}, P2/Z, [X0,Z0.S,SXTW]
ld1h {z0.s}, p2/z, [x0,z0.s,sxtw #0]
ld1h {z0.s}, p7/z, [x0,z0.s,sxtw]
LD1H {Z0.S}, P7/Z, [X0,Z0.S,SXTW]
ld1h {z0.s}, p7/z, [x0,z0.s,sxtw #0]
ld1h {z0.s}, p0/z, [x3,z0.s,sxtw]
LD1H {Z0.S}, P0/Z, [X3,Z0.S,SXTW]
ld1h {z0.s}, p0/z, [x3,z0.s,sxtw #0]
ld1h {z0.s}, p0/z, [sp,z0.s,sxtw]
LD1H {Z0.S}, P0/Z, [SP,Z0.S,SXTW]
ld1h {z0.s}, p0/z, [sp,z0.s,sxtw #0]
ld1h {z0.s}, p0/z, [x0,z4.s,sxtw]
LD1H {Z0.S}, P0/Z, [X0,Z4.S,SXTW]
ld1h {z0.s}, p0/z, [x0,z4.s,sxtw #0]
ld1h {z0.s}, p0/z, [x0,z31.s,sxtw]
LD1H {Z0.S}, P0/Z, [X0,Z31.S,SXTW]
ld1h {z0.s}, p0/z, [x0,z31.s,sxtw #0]
ld1h z0.s, p0/z, [x0,z0.s,uxtw #1]
ld1h {z0.s}, p0/z, [x0,z0.s,uxtw #1]
LD1H {Z0.S}, P0/Z, [X0,Z0.S,UXTW #1]
ld1h z1.s, p0/z, [x0,z0.s,uxtw #1]
ld1h {z1.s}, p0/z, [x0,z0.s,uxtw #1]
LD1H {Z1.S}, P0/Z, [X0,Z0.S,UXTW #1]
ld1h z31.s, p0/z, [x0,z0.s,uxtw #1]
ld1h {z31.s}, p0/z, [x0,z0.s,uxtw #1]
LD1H {Z31.S}, P0/Z, [X0,Z0.S,UXTW #1]
ld1h {z0.s}, p2/z, [x0,z0.s,uxtw #1]
LD1H {Z0.S}, P2/Z, [X0,Z0.S,UXTW #1]
ld1h {z0.s}, p7/z, [x0,z0.s,uxtw #1]
LD1H {Z0.S}, P7/Z, [X0,Z0.S,UXTW #1]
ld1h {z0.s}, p0/z, [x3,z0.s,uxtw #1]
LD1H {Z0.S}, P0/Z, [X3,Z0.S,UXTW #1]
ld1h {z0.s}, p0/z, [sp,z0.s,uxtw #1]
LD1H {Z0.S}, P0/Z, [SP,Z0.S,UXTW #1]
ld1h {z0.s}, p0/z, [x0,z4.s,uxtw #1]
LD1H {Z0.S}, P0/Z, [X0,Z4.S,UXTW #1]
ld1h {z0.s}, p0/z, [x0,z31.s,uxtw #1]
LD1H {Z0.S}, P0/Z, [X0,Z31.S,UXTW #1]
ld1h z0.s, p0/z, [x0,z0.s,sxtw #1]
ld1h {z0.s}, p0/z, [x0,z0.s,sxtw #1]
LD1H {Z0.S}, P0/Z, [X0,Z0.S,SXTW #1]
ld1h z1.s, p0/z, [x0,z0.s,sxtw #1]
ld1h {z1.s}, p0/z, [x0,z0.s,sxtw #1]
LD1H {Z1.S}, P0/Z, [X0,Z0.S,SXTW #1]
ld1h z31.s, p0/z, [x0,z0.s,sxtw #1]
ld1h {z31.s}, p0/z, [x0,z0.s,sxtw #1]
LD1H {Z31.S}, P0/Z, [X0,Z0.S,SXTW #1]
ld1h {z0.s}, p2/z, [x0,z0.s,sxtw #1]
LD1H {Z0.S}, P2/Z, [X0,Z0.S,SXTW #1]
ld1h {z0.s}, p7/z, [x0,z0.s,sxtw #1]
LD1H {Z0.S}, P7/Z, [X0,Z0.S,SXTW #1]
ld1h {z0.s}, p0/z, [x3,z0.s,sxtw #1]
LD1H {Z0.S}, P0/Z, [X3,Z0.S,SXTW #1]
ld1h {z0.s}, p0/z, [sp,z0.s,sxtw #1]
LD1H {Z0.S}, P0/Z, [SP,Z0.S,SXTW #1]
ld1h {z0.s}, p0/z, [x0,z4.s,sxtw #1]
LD1H {Z0.S}, P0/Z, [X0,Z4.S,SXTW #1]
ld1h {z0.s}, p0/z, [x0,z31.s,sxtw #1]
LD1H {Z0.S}, P0/Z, [X0,Z31.S,SXTW #1]
ld1h z0.h, p0/z, [x0,x0,lsl #1]
ld1h {z0.h}, p0/z, [x0,x0,lsl #1]
LD1H {Z0.H}, P0/Z, [X0,X0,LSL #1]
ld1h z1.h, p0/z, [x0,x0,lsl #1]
ld1h {z1.h}, p0/z, [x0,x0,lsl #1]
LD1H {Z1.H}, P0/Z, [X0,X0,LSL #1]
ld1h z31.h, p0/z, [x0,x0,lsl #1]
ld1h {z31.h}, p0/z, [x0,x0,lsl #1]
LD1H {Z31.H}, P0/Z, [X0,X0,LSL #1]
ld1h {z0.h}, p2/z, [x0,x0,lsl #1]
LD1H {Z0.H}, P2/Z, [X0,X0,LSL #1]
ld1h {z0.h}, p7/z, [x0,x0,lsl #1]
LD1H {Z0.H}, P7/Z, [X0,X0,LSL #1]
ld1h {z0.h}, p0/z, [x3,x0,lsl #1]
LD1H {Z0.H}, P0/Z, [X3,X0,LSL #1]
ld1h {z0.h}, p0/z, [sp,x0,lsl #1]
LD1H {Z0.H}, P0/Z, [SP,X0,LSL #1]
ld1h {z0.h}, p0/z, [x0,x4,lsl #1]
LD1H {Z0.H}, P0/Z, [X0,X4,LSL #1]
ld1h {z0.h}, p0/z, [x0,x30,lsl #1]
LD1H {Z0.H}, P0/Z, [X0,X30,LSL #1]
ld1h z0.s, p0/z, [x0,x0,lsl #1]
ld1h {z0.s}, p0/z, [x0,x0,lsl #1]
LD1H {Z0.S}, P0/Z, [X0,X0,LSL #1]
ld1h z1.s, p0/z, [x0,x0,lsl #1]
ld1h {z1.s}, p0/z, [x0,x0,lsl #1]
LD1H {Z1.S}, P0/Z, [X0,X0,LSL #1]
ld1h z31.s, p0/z, [x0,x0,lsl #1]
ld1h {z31.s}, p0/z, [x0,x0,lsl #1]
LD1H {Z31.S}, P0/Z, [X0,X0,LSL #1]
ld1h {z0.s}, p2/z, [x0,x0,lsl #1]
LD1H {Z0.S}, P2/Z, [X0,X0,LSL #1]
ld1h {z0.s}, p7/z, [x0,x0,lsl #1]
LD1H {Z0.S}, P7/Z, [X0,X0,LSL #1]
ld1h {z0.s}, p0/z, [x3,x0,lsl #1]
LD1H {Z0.S}, P0/Z, [X3,X0,LSL #1]
ld1h {z0.s}, p0/z, [sp,x0,lsl #1]
LD1H {Z0.S}, P0/Z, [SP,X0,LSL #1]
ld1h {z0.s}, p0/z, [x0,x4,lsl #1]
LD1H {Z0.S}, P0/Z, [X0,X4,LSL #1]
ld1h {z0.s}, p0/z, [x0,x30,lsl #1]
LD1H {Z0.S}, P0/Z, [X0,X30,LSL #1]
ld1h z0.d, p0/z, [x0,x0,lsl #1]
ld1h {z0.d}, p0/z, [x0,x0,lsl #1]
LD1H {Z0.D}, P0/Z, [X0,X0,LSL #1]
ld1h z1.d, p0/z, [x0,x0,lsl #1]
ld1h {z1.d}, p0/z, [x0,x0,lsl #1]
LD1H {Z1.D}, P0/Z, [X0,X0,LSL #1]
ld1h z31.d, p0/z, [x0,x0,lsl #1]
ld1h {z31.d}, p0/z, [x0,x0,lsl #1]
LD1H {Z31.D}, P0/Z, [X0,X0,LSL #1]
ld1h {z0.d}, p2/z, [x0,x0,lsl #1]
LD1H {Z0.D}, P2/Z, [X0,X0,LSL #1]
ld1h {z0.d}, p7/z, [x0,x0,lsl #1]
LD1H {Z0.D}, P7/Z, [X0,X0,LSL #1]
ld1h {z0.d}, p0/z, [x3,x0,lsl #1]
LD1H {Z0.D}, P0/Z, [X3,X0,LSL #1]
ld1h {z0.d}, p0/z, [sp,x0,lsl #1]
LD1H {Z0.D}, P0/Z, [SP,X0,LSL #1]
ld1h {z0.d}, p0/z, [x0,x4,lsl #1]
LD1H {Z0.D}, P0/Z, [X0,X4,LSL #1]
ld1h {z0.d}, p0/z, [x0,x30,lsl #1]
LD1H {Z0.D}, P0/Z, [X0,X30,LSL #1]
ld1h z0.d, p0/z, [x0,z0.d,uxtw]
ld1h {z0.d}, p0/z, [x0,z0.d,uxtw]
LD1H {Z0.D}, P0/Z, [X0,Z0.D,UXTW]
ld1h {z0.d}, p0/z, [x0,z0.d,uxtw #0]
ld1h z1.d, p0/z, [x0,z0.d,uxtw]
ld1h {z1.d}, p0/z, [x0,z0.d,uxtw]
LD1H {Z1.D}, P0/Z, [X0,Z0.D,UXTW]
ld1h {z1.d}, p0/z, [x0,z0.d,uxtw #0]
ld1h z31.d, p0/z, [x0,z0.d,uxtw]
ld1h {z31.d}, p0/z, [x0,z0.d,uxtw]
LD1H {Z31.D}, P0/Z, [X0,Z0.D,UXTW]
ld1h {z31.d}, p0/z, [x0,z0.d,uxtw #0]
ld1h {z0.d}, p2/z, [x0,z0.d,uxtw]
LD1H {Z0.D}, P2/Z, [X0,Z0.D,UXTW]
ld1h {z0.d}, p2/z, [x0,z0.d,uxtw #0]
ld1h {z0.d}, p7/z, [x0,z0.d,uxtw]
LD1H {Z0.D}, P7/Z, [X0,Z0.D,UXTW]
ld1h {z0.d}, p7/z, [x0,z0.d,uxtw #0]
ld1h {z0.d}, p0/z, [x3,z0.d,uxtw]
LD1H {Z0.D}, P0/Z, [X3,Z0.D,UXTW]
ld1h {z0.d}, p0/z, [x3,z0.d,uxtw #0]
ld1h {z0.d}, p0/z, [sp,z0.d,uxtw]
LD1H {Z0.D}, P0/Z, [SP,Z0.D,UXTW]
ld1h {z0.d}, p0/z, [sp,z0.d,uxtw #0]
ld1h {z0.d}, p0/z, [x0,z4.d,uxtw]
LD1H {Z0.D}, P0/Z, [X0,Z4.D,UXTW]
ld1h {z0.d}, p0/z, [x0,z4.d,uxtw #0]
ld1h {z0.d}, p0/z, [x0,z31.d,uxtw]
LD1H {Z0.D}, P0/Z, [X0,Z31.D,UXTW]
ld1h {z0.d}, p0/z, [x0,z31.d,uxtw #0]
ld1h z0.d, p0/z, [x0,z0.d,sxtw]
ld1h {z0.d}, p0/z, [x0,z0.d,sxtw]
LD1H {Z0.D}, P0/Z, [X0,Z0.D,SXTW]
ld1h {z0.d}, p0/z, [x0,z0.d,sxtw #0]
ld1h z1.d, p0/z, [x0,z0.d,sxtw]
ld1h {z1.d}, p0/z, [x0,z0.d,sxtw]
LD1H {Z1.D}, P0/Z, [X0,Z0.D,SXTW]
ld1h {z1.d}, p0/z, [x0,z0.d,sxtw #0]
ld1h z31.d, p0/z, [x0,z0.d,sxtw]
ld1h {z31.d}, p0/z, [x0,z0.d,sxtw]
LD1H {Z31.D}, P0/Z, [X0,Z0.D,SXTW]
ld1h {z31.d}, p0/z, [x0,z0.d,sxtw #0]
ld1h {z0.d}, p2/z, [x0,z0.d,sxtw]
LD1H {Z0.D}, P2/Z, [X0,Z0.D,SXTW]
ld1h {z0.d}, p2/z, [x0,z0.d,sxtw #0]
ld1h {z0.d}, p7/z, [x0,z0.d,sxtw]
LD1H {Z0.D}, P7/Z, [X0,Z0.D,SXTW]
ld1h {z0.d}, p7/z, [x0,z0.d,sxtw #0]
ld1h {z0.d}, p0/z, [x3,z0.d,sxtw]
LD1H {Z0.D}, P0/Z, [X3,Z0.D,SXTW]
ld1h {z0.d}, p0/z, [x3,z0.d,sxtw #0]
ld1h {z0.d}, p0/z, [sp,z0.d,sxtw]
LD1H {Z0.D}, P0/Z, [SP,Z0.D,SXTW]
ld1h {z0.d}, p0/z, [sp,z0.d,sxtw #0]
ld1h {z0.d}, p0/z, [x0,z4.d,sxtw]
LD1H {Z0.D}, P0/Z, [X0,Z4.D,SXTW]
ld1h {z0.d}, p0/z, [x0,z4.d,sxtw #0]
ld1h {z0.d}, p0/z, [x0,z31.d,sxtw]
LD1H {Z0.D}, P0/Z, [X0,Z31.D,SXTW]
ld1h {z0.d}, p0/z, [x0,z31.d,sxtw #0]
ld1h z0.d, p0/z, [x0,z0.d,uxtw #1]
ld1h {z0.d}, p0/z, [x0,z0.d,uxtw #1]
LD1H {Z0.D}, P0/Z, [X0,Z0.D,UXTW #1]
ld1h z1.d, p0/z, [x0,z0.d,uxtw #1]
ld1h {z1.d}, p0/z, [x0,z0.d,uxtw #1]
LD1H {Z1.D}, P0/Z, [X0,Z0.D,UXTW #1]
ld1h z31.d, p0/z, [x0,z0.d,uxtw #1]
ld1h {z31.d}, p0/z, [x0,z0.d,uxtw #1]
LD1H {Z31.D}, P0/Z, [X0,Z0.D,UXTW #1]
ld1h {z0.d}, p2/z, [x0,z0.d,uxtw #1]
LD1H {Z0.D}, P2/Z, [X0,Z0.D,UXTW #1]
ld1h {z0.d}, p7/z, [x0,z0.d,uxtw #1]
LD1H {Z0.D}, P7/Z, [X0,Z0.D,UXTW #1]
ld1h {z0.d}, p0/z, [x3,z0.d,uxtw #1]
LD1H {Z0.D}, P0/Z, [X3,Z0.D,UXTW #1]
ld1h {z0.d}, p0/z, [sp,z0.d,uxtw #1]
LD1H {Z0.D}, P0/Z, [SP,Z0.D,UXTW #1]
ld1h {z0.d}, p0/z, [x0,z4.d,uxtw #1]
LD1H {Z0.D}, P0/Z, [X0,Z4.D,UXTW #1]
ld1h {z0.d}, p0/z, [x0,z31.d,uxtw #1]
LD1H {Z0.D}, P0/Z, [X0,Z31.D,UXTW #1]
ld1h z0.d, p0/z, [x0,z0.d,sxtw #1]
ld1h {z0.d}, p0/z, [x0,z0.d,sxtw #1]
LD1H {Z0.D}, P0/Z, [X0,Z0.D,SXTW #1]
ld1h z1.d, p0/z, [x0,z0.d,sxtw #1]
ld1h {z1.d}, p0/z, [x0,z0.d,sxtw #1]
LD1H {Z1.D}, P0/Z, [X0,Z0.D,SXTW #1]
ld1h z31.d, p0/z, [x0,z0.d,sxtw #1]
ld1h {z31.d}, p0/z, [x0,z0.d,sxtw #1]
LD1H {Z31.D}, P0/Z, [X0,Z0.D,SXTW #1]
ld1h {z0.d}, p2/z, [x0,z0.d,sxtw #1]
LD1H {Z0.D}, P2/Z, [X0,Z0.D,SXTW #1]
ld1h {z0.d}, p7/z, [x0,z0.d,sxtw #1]
LD1H {Z0.D}, P7/Z, [X0,Z0.D,SXTW #1]
ld1h {z0.d}, p0/z, [x3,z0.d,sxtw #1]
LD1H {Z0.D}, P0/Z, [X3,Z0.D,SXTW #1]
ld1h {z0.d}, p0/z, [sp,z0.d,sxtw #1]
LD1H {Z0.D}, P0/Z, [SP,Z0.D,SXTW #1]
ld1h {z0.d}, p0/z, [x0,z4.d,sxtw #1]
LD1H {Z0.D}, P0/Z, [X0,Z4.D,SXTW #1]
ld1h {z0.d}, p0/z, [x0,z31.d,sxtw #1]
LD1H {Z0.D}, P0/Z, [X0,Z31.D,SXTW #1]
ld1h z0.d, p0/z, [x0,z0.d]
ld1h {z0.d}, p0/z, [x0,z0.d]
LD1H {Z0.D}, P0/Z, [X0,Z0.D]
ld1h {z0.d}, p0/z, [x0,z0.d,lsl #0]
ld1h z1.d, p0/z, [x0,z0.d]
ld1h {z1.d}, p0/z, [x0,z0.d]
LD1H {Z1.D}, P0/Z, [X0,Z0.D]
ld1h {z1.d}, p0/z, [x0,z0.d,lsl #0]
ld1h z31.d, p0/z, [x0,z0.d]
ld1h {z31.d}, p0/z, [x0,z0.d]
LD1H {Z31.D}, P0/Z, [X0,Z0.D]
ld1h {z31.d}, p0/z, [x0,z0.d,lsl #0]
ld1h {z0.d}, p2/z, [x0,z0.d]
LD1H {Z0.D}, P2/Z, [X0,Z0.D]
ld1h {z0.d}, p2/z, [x0,z0.d,lsl #0]
ld1h {z0.d}, p7/z, [x0,z0.d]
LD1H {Z0.D}, P7/Z, [X0,Z0.D]
ld1h {z0.d}, p7/z, [x0,z0.d,lsl #0]
ld1h {z0.d}, p0/z, [x3,z0.d]
LD1H {Z0.D}, P0/Z, [X3,Z0.D]
ld1h {z0.d}, p0/z, [x3,z0.d,lsl #0]
ld1h {z0.d}, p0/z, [sp,z0.d]
LD1H {Z0.D}, P0/Z, [SP,Z0.D]
ld1h {z0.d}, p0/z, [sp,z0.d,lsl #0]
ld1h {z0.d}, p0/z, [x0,z4.d]
LD1H {Z0.D}, P0/Z, [X0,Z4.D]
ld1h {z0.d}, p0/z, [x0,z4.d,lsl #0]
ld1h {z0.d}, p0/z, [x0,z31.d]
LD1H {Z0.D}, P0/Z, [X0,Z31.D]
ld1h {z0.d}, p0/z, [x0,z31.d,lsl #0]
ld1h z0.d, p0/z, [x0,z0.d,lsl #1]
ld1h {z0.d}, p0/z, [x0,z0.d,lsl #1]
LD1H {Z0.D}, P0/Z, [X0,Z0.D,LSL #1]
ld1h z1.d, p0/z, [x0,z0.d,lsl #1]
ld1h {z1.d}, p0/z, [x0,z0.d,lsl #1]
LD1H {Z1.D}, P0/Z, [X0,Z0.D,LSL #1]
ld1h z31.d, p0/z, [x0,z0.d,lsl #1]
ld1h {z31.d}, p0/z, [x0,z0.d,lsl #1]
LD1H {Z31.D}, P0/Z, [X0,Z0.D,LSL #1]
ld1h {z0.d}, p2/z, [x0,z0.d,lsl #1]
LD1H {Z0.D}, P2/Z, [X0,Z0.D,LSL #1]
ld1h {z0.d}, p7/z, [x0,z0.d,lsl #1]
LD1H {Z0.D}, P7/Z, [X0,Z0.D,LSL #1]
ld1h {z0.d}, p0/z, [x3,z0.d,lsl #1]
LD1H {Z0.D}, P0/Z, [X3,Z0.D,LSL #1]
ld1h {z0.d}, p0/z, [sp,z0.d,lsl #1]
LD1H {Z0.D}, P0/Z, [SP,Z0.D,LSL #1]
ld1h {z0.d}, p0/z, [x0,z4.d,lsl #1]
LD1H {Z0.D}, P0/Z, [X0,Z4.D,LSL #1]
ld1h {z0.d}, p0/z, [x0,z31.d,lsl #1]
LD1H {Z0.D}, P0/Z, [X0,Z31.D,LSL #1]
ld1h z0.s, p0/z, [z0.s,#0]
ld1h {z0.s}, p0/z, [z0.s,#0]
LD1H {Z0.S}, P0/Z, [Z0.S,#0]
ld1h {z0.s}, p0/z, [z0.s]
ld1h z1.s, p0/z, [z0.s,#0]
ld1h {z1.s}, p0/z, [z0.s,#0]
LD1H {Z1.S}, P0/Z, [Z0.S,#0]
ld1h {z1.s}, p0/z, [z0.s]
ld1h z31.s, p0/z, [z0.s,#0]
ld1h {z31.s}, p0/z, [z0.s,#0]
LD1H {Z31.S}, P0/Z, [Z0.S,#0]
ld1h {z31.s}, p0/z, [z0.s]
ld1h {z0.s}, p2/z, [z0.s,#0]
LD1H {Z0.S}, P2/Z, [Z0.S,#0]
ld1h {z0.s}, p2/z, [z0.s]
ld1h {z0.s}, p7/z, [z0.s,#0]
LD1H {Z0.S}, P7/Z, [Z0.S,#0]
ld1h {z0.s}, p7/z, [z0.s]
ld1h {z0.s}, p0/z, [z3.s,#0]
LD1H {Z0.S}, P0/Z, [Z3.S,#0]
ld1h {z0.s}, p0/z, [z3.s]
ld1h {z0.s}, p0/z, [z31.s,#0]
LD1H {Z0.S}, P0/Z, [Z31.S,#0]
ld1h {z0.s}, p0/z, [z31.s]
ld1h {z0.s}, p0/z, [z0.s,#30]
LD1H {Z0.S}, P0/Z, [Z0.S,#30]
ld1h {z0.s}, p0/z, [z0.s,#32]
LD1H {Z0.S}, P0/Z, [Z0.S,#32]
ld1h {z0.s}, p0/z, [z0.s,#34]
LD1H {Z0.S}, P0/Z, [Z0.S,#34]
ld1h {z0.s}, p0/z, [z0.s,#62]
LD1H {Z0.S}, P0/Z, [Z0.S,#62]
ld1h z0.h, p0/z, [x0,#0]
ld1h {z0.h}, p0/z, [x0,#0]
LD1H {Z0.H}, P0/Z, [X0,#0]
ld1h {z0.h}, p0/z, [x0,#0,mul vl]
ld1h {z0.h}, p0/z, [x0]
ld1h z1.h, p0/z, [x0,#0]
ld1h {z1.h}, p0/z, [x0,#0]
LD1H {Z1.H}, P0/Z, [X0,#0]
ld1h {z1.h}, p0/z, [x0,#0,mul vl]
ld1h {z1.h}, p0/z, [x0]
ld1h z31.h, p0/z, [x0,#0]
ld1h {z31.h}, p0/z, [x0,#0]
LD1H {Z31.H}, P0/Z, [X0,#0]
ld1h {z31.h}, p0/z, [x0,#0,mul vl]
ld1h {z31.h}, p0/z, [x0]
ld1h {z0.h}, p2/z, [x0,#0]
LD1H {Z0.H}, P2/Z, [X0,#0]
ld1h {z0.h}, p2/z, [x0,#0,mul vl]
ld1h {z0.h}, p2/z, [x0]
ld1h {z0.h}, p7/z, [x0,#0]
LD1H {Z0.H}, P7/Z, [X0,#0]
ld1h {z0.h}, p7/z, [x0,#0,mul vl]
ld1h {z0.h}, p7/z, [x0]
ld1h {z0.h}, p0/z, [x3,#0]
LD1H {Z0.H}, P0/Z, [X3,#0]
ld1h {z0.h}, p0/z, [x3,#0,mul vl]
ld1h {z0.h}, p0/z, [x3]
ld1h {z0.h}, p0/z, [sp,#0]
LD1H {Z0.H}, P0/Z, [SP,#0]
ld1h {z0.h}, p0/z, [sp,#0,mul vl]
ld1h {z0.h}, p0/z, [sp]
ld1h {z0.h}, p0/z, [x0,#7,mul vl]
LD1H {Z0.H}, P0/Z, [X0,#7,MUL VL]
ld1h {z0.h}, p0/z, [x0,#-8,mul vl]
LD1H {Z0.H}, P0/Z, [X0,#-8,MUL VL]
ld1h {z0.h}, p0/z, [x0,#-7,mul vl]
LD1H {Z0.H}, P0/Z, [X0,#-7,MUL VL]
ld1h {z0.h}, p0/z, [x0,#-1,mul vl]
LD1H {Z0.H}, P0/Z, [X0,#-1,MUL VL]
ld1h z0.s, p0/z, [x0,#0]
ld1h {z0.s}, p0/z, [x0,#0]
LD1H {Z0.S}, P0/Z, [X0,#0]
ld1h {z0.s}, p0/z, [x0,#0,mul vl]
ld1h {z0.s}, p0/z, [x0]
ld1h z1.s, p0/z, [x0,#0]
ld1h {z1.s}, p0/z, [x0,#0]
LD1H {Z1.S}, P0/Z, [X0,#0]
ld1h {z1.s}, p0/z, [x0,#0,mul vl]
ld1h {z1.s}, p0/z, [x0]
ld1h z31.s, p0/z, [x0,#0]
ld1h {z31.s}, p0/z, [x0,#0]
LD1H {Z31.S}, P0/Z, [X0,#0]
ld1h {z31.s}, p0/z, [x0,#0,mul vl]
ld1h {z31.s}, p0/z, [x0]
ld1h {z0.s}, p2/z, [x0,#0]
LD1H {Z0.S}, P2/Z, [X0,#0]
ld1h {z0.s}, p2/z, [x0,#0,mul vl]
ld1h {z0.s}, p2/z, [x0]
ld1h {z0.s}, p7/z, [x0,#0]
LD1H {Z0.S}, P7/Z, [X0,#0]
ld1h {z0.s}, p7/z, [x0,#0,mul vl]
ld1h {z0.s}, p7/z, [x0]
ld1h {z0.s}, p0/z, [x3,#0]
LD1H {Z0.S}, P0/Z, [X3,#0]
ld1h {z0.s}, p0/z, [x3,#0,mul vl]
ld1h {z0.s}, p0/z, [x3]
ld1h {z0.s}, p0/z, [sp,#0]
LD1H {Z0.S}, P0/Z, [SP,#0]
ld1h {z0.s}, p0/z, [sp,#0,mul vl]
ld1h {z0.s}, p0/z, [sp]
ld1h {z0.s}, p0/z, [x0,#7,mul vl]
LD1H {Z0.S}, P0/Z, [X0,#7,MUL VL]
ld1h {z0.s}, p0/z, [x0,#-8,mul vl]
LD1H {Z0.S}, P0/Z, [X0,#-8,MUL VL]
ld1h {z0.s}, p0/z, [x0,#-7,mul vl]
LD1H {Z0.S}, P0/Z, [X0,#-7,MUL VL]
ld1h {z0.s}, p0/z, [x0,#-1,mul vl]
LD1H {Z0.S}, P0/Z, [X0,#-1,MUL VL]
ld1h z0.d, p0/z, [x0,#0]
ld1h {z0.d}, p0/z, [x0,#0]
LD1H {Z0.D}, P0/Z, [X0,#0]
ld1h {z0.d}, p0/z, [x0,#0,mul vl]
ld1h {z0.d}, p0/z, [x0]
ld1h z1.d, p0/z, [x0,#0]
ld1h {z1.d}, p0/z, [x0,#0]
LD1H {Z1.D}, P0/Z, [X0,#0]
ld1h {z1.d}, p0/z, [x0,#0,mul vl]
ld1h {z1.d}, p0/z, [x0]
ld1h z31.d, p0/z, [x0,#0]
ld1h {z31.d}, p0/z, [x0,#0]
LD1H {Z31.D}, P0/Z, [X0,#0]
ld1h {z31.d}, p0/z, [x0,#0,mul vl]
ld1h {z31.d}, p0/z, [x0]
ld1h {z0.d}, p2/z, [x0,#0]
LD1H {Z0.D}, P2/Z, [X0,#0]
ld1h {z0.d}, p2/z, [x0,#0,mul vl]
ld1h {z0.d}, p2/z, [x0]
ld1h {z0.d}, p7/z, [x0,#0]
LD1H {Z0.D}, P7/Z, [X0,#0]
ld1h {z0.d}, p7/z, [x0,#0,mul vl]
ld1h {z0.d}, p7/z, [x0]
ld1h {z0.d}, p0/z, [x3,#0]
LD1H {Z0.D}, P0/Z, [X3,#0]
ld1h {z0.d}, p0/z, [x3,#0,mul vl]
ld1h {z0.d}, p0/z, [x3]
ld1h {z0.d}, p0/z, [sp,#0]
LD1H {Z0.D}, P0/Z, [SP,#0]
ld1h {z0.d}, p0/z, [sp,#0,mul vl]
ld1h {z0.d}, p0/z, [sp]
ld1h {z0.d}, p0/z, [x0,#7,mul vl]
LD1H {Z0.D}, P0/Z, [X0,#7,MUL VL]
ld1h {z0.d}, p0/z, [x0,#-8,mul vl]
LD1H {Z0.D}, P0/Z, [X0,#-8,MUL VL]
ld1h {z0.d}, p0/z, [x0,#-7,mul vl]
LD1H {Z0.D}, P0/Z, [X0,#-7,MUL VL]
ld1h {z0.d}, p0/z, [x0,#-1,mul vl]
LD1H {Z0.D}, P0/Z, [X0,#-1,MUL VL]
ld1h z0.d, p0/z, [z0.d,#0]
ld1h {z0.d}, p0/z, [z0.d,#0]
LD1H {Z0.D}, P0/Z, [Z0.D,#0]
ld1h {z0.d}, p0/z, [z0.d]
ld1h z1.d, p0/z, [z0.d,#0]
ld1h {z1.d}, p0/z, [z0.d,#0]
LD1H {Z1.D}, P0/Z, [Z0.D,#0]
ld1h {z1.d}, p0/z, [z0.d]
ld1h z31.d, p0/z, [z0.d,#0]
ld1h {z31.d}, p0/z, [z0.d,#0]
LD1H {Z31.D}, P0/Z, [Z0.D,#0]
ld1h {z31.d}, p0/z, [z0.d]
ld1h {z0.d}, p2/z, [z0.d,#0]
LD1H {Z0.D}, P2/Z, [Z0.D,#0]
ld1h {z0.d}, p2/z, [z0.d]
ld1h {z0.d}, p7/z, [z0.d,#0]
LD1H {Z0.D}, P7/Z, [Z0.D,#0]
ld1h {z0.d}, p7/z, [z0.d]
ld1h {z0.d}, p0/z, [z3.d,#0]
LD1H {Z0.D}, P0/Z, [Z3.D,#0]
ld1h {z0.d}, p0/z, [z3.d]
ld1h {z0.d}, p0/z, [z31.d,#0]
LD1H {Z0.D}, P0/Z, [Z31.D,#0]
ld1h {z0.d}, p0/z, [z31.d]
ld1h {z0.d}, p0/z, [z0.d,#30]
LD1H {Z0.D}, P0/Z, [Z0.D,#30]
ld1h {z0.d}, p0/z, [z0.d,#32]
LD1H {Z0.D}, P0/Z, [Z0.D,#32]
ld1h {z0.d}, p0/z, [z0.d,#34]
LD1H {Z0.D}, P0/Z, [Z0.D,#34]
ld1h {z0.d}, p0/z, [z0.d,#62]
LD1H {Z0.D}, P0/Z, [Z0.D,#62]
ld1rb z0.b, p0/z, [x0,#0]
ld1rb {z0.b}, p0/z, [x0,#0]
LD1RB {Z0.B}, P0/Z, [X0,#0]
ld1rb {z0.b}, p0/z, [x0]
ld1rb z1.b, p0/z, [x0,#0]
ld1rb {z1.b}, p0/z, [x0,#0]
LD1RB {Z1.B}, P0/Z, [X0,#0]
ld1rb {z1.b}, p0/z, [x0]
ld1rb z31.b, p0/z, [x0,#0]
ld1rb {z31.b}, p0/z, [x0,#0]
LD1RB {Z31.B}, P0/Z, [X0,#0]
ld1rb {z31.b}, p0/z, [x0]
ld1rb {z0.b}, p2/z, [x0,#0]
LD1RB {Z0.B}, P2/Z, [X0,#0]
ld1rb {z0.b}, p2/z, [x0]
ld1rb {z0.b}, p7/z, [x0,#0]
LD1RB {Z0.B}, P7/Z, [X0,#0]
ld1rb {z0.b}, p7/z, [x0]
ld1rb {z0.b}, p0/z, [x3,#0]
LD1RB {Z0.B}, P0/Z, [X3,#0]
ld1rb {z0.b}, p0/z, [x3]
ld1rb {z0.b}, p0/z, [sp,#0]
LD1RB {Z0.B}, P0/Z, [SP,#0]
ld1rb {z0.b}, p0/z, [sp]
ld1rb {z0.b}, p0/z, [x0,#31]
LD1RB {Z0.B}, P0/Z, [X0,#31]
ld1rb {z0.b}, p0/z, [x0,#32]
LD1RB {Z0.B}, P0/Z, [X0,#32]
ld1rb {z0.b}, p0/z, [x0,#33]
LD1RB {Z0.B}, P0/Z, [X0,#33]
ld1rb {z0.b}, p0/z, [x0,#63]
LD1RB {Z0.B}, P0/Z, [X0,#63]
ld1rb z0.h, p0/z, [x0,#0]
ld1rb {z0.h}, p0/z, [x0,#0]
LD1RB {Z0.H}, P0/Z, [X0,#0]
ld1rb {z0.h}, p0/z, [x0]
ld1rb z1.h, p0/z, [x0,#0]
ld1rb {z1.h}, p0/z, [x0,#0]
LD1RB {Z1.H}, P0/Z, [X0,#0]
ld1rb {z1.h}, p0/z, [x0]
ld1rb z31.h, p0/z, [x0,#0]
ld1rb {z31.h}, p0/z, [x0,#0]
LD1RB {Z31.H}, P0/Z, [X0,#0]
ld1rb {z31.h}, p0/z, [x0]
ld1rb {z0.h}, p2/z, [x0,#0]
LD1RB {Z0.H}, P2/Z, [X0,#0]
ld1rb {z0.h}, p2/z, [x0]
ld1rb {z0.h}, p7/z, [x0,#0]
LD1RB {Z0.H}, P7/Z, [X0,#0]
ld1rb {z0.h}, p7/z, [x0]
ld1rb {z0.h}, p0/z, [x3,#0]
LD1RB {Z0.H}, P0/Z, [X3,#0]
ld1rb {z0.h}, p0/z, [x3]
ld1rb {z0.h}, p0/z, [sp,#0]
LD1RB {Z0.H}, P0/Z, [SP,#0]
ld1rb {z0.h}, p0/z, [sp]
ld1rb {z0.h}, p0/z, [x0,#31]
LD1RB {Z0.H}, P0/Z, [X0,#31]
ld1rb {z0.h}, p0/z, [x0,#32]
LD1RB {Z0.H}, P0/Z, [X0,#32]
ld1rb {z0.h}, p0/z, [x0,#33]
LD1RB {Z0.H}, P0/Z, [X0,#33]
ld1rb {z0.h}, p0/z, [x0,#63]
LD1RB {Z0.H}, P0/Z, [X0,#63]
ld1rb z0.s, p0/z, [x0,#0]
ld1rb {z0.s}, p0/z, [x0,#0]
LD1RB {Z0.S}, P0/Z, [X0,#0]
ld1rb {z0.s}, p0/z, [x0]
ld1rb z1.s, p0/z, [x0,#0]
ld1rb {z1.s}, p0/z, [x0,#0]
LD1RB {Z1.S}, P0/Z, [X0,#0]
ld1rb {z1.s}, p0/z, [x0]
ld1rb z31.s, p0/z, [x0,#0]
ld1rb {z31.s}, p0/z, [x0,#0]
LD1RB {Z31.S}, P0/Z, [X0,#0]
ld1rb {z31.s}, p0/z, [x0]
ld1rb {z0.s}, p2/z, [x0,#0]
LD1RB {Z0.S}, P2/Z, [X0,#0]
ld1rb {z0.s}, p2/z, [x0]
ld1rb {z0.s}, p7/z, [x0,#0]
LD1RB {Z0.S}, P7/Z, [X0,#0]
ld1rb {z0.s}, p7/z, [x0]
ld1rb {z0.s}, p0/z, [x3,#0]
LD1RB {Z0.S}, P0/Z, [X3,#0]
ld1rb {z0.s}, p0/z, [x3]
ld1rb {z0.s}, p0/z, [sp,#0]
LD1RB {Z0.S}, P0/Z, [SP,#0]
ld1rb {z0.s}, p0/z, [sp]
ld1rb {z0.s}, p0/z, [x0,#31]
LD1RB {Z0.S}, P0/Z, [X0,#31]
ld1rb {z0.s}, p0/z, [x0,#32]
LD1RB {Z0.S}, P0/Z, [X0,#32]
ld1rb {z0.s}, p0/z, [x0,#33]
LD1RB {Z0.S}, P0/Z, [X0,#33]
ld1rb {z0.s}, p0/z, [x0,#63]
LD1RB {Z0.S}, P0/Z, [X0,#63]
ld1rb z0.d, p0/z, [x0,#0]
ld1rb {z0.d}, p0/z, [x0,#0]
LD1RB {Z0.D}, P0/Z, [X0,#0]
ld1rb {z0.d}, p0/z, [x0]
ld1rb z1.d, p0/z, [x0,#0]
ld1rb {z1.d}, p0/z, [x0,#0]
LD1RB {Z1.D}, P0/Z, [X0,#0]
ld1rb {z1.d}, p0/z, [x0]
ld1rb z31.d, p0/z, [x0,#0]
ld1rb {z31.d}, p0/z, [x0,#0]
LD1RB {Z31.D}, P0/Z, [X0,#0]
ld1rb {z31.d}, p0/z, [x0]
ld1rb {z0.d}, p2/z, [x0,#0]
LD1RB {Z0.D}, P2/Z, [X0,#0]
ld1rb {z0.d}, p2/z, [x0]
ld1rb {z0.d}, p7/z, [x0,#0]
LD1RB {Z0.D}, P7/Z, [X0,#0]
ld1rb {z0.d}, p7/z, [x0]
ld1rb {z0.d}, p0/z, [x3,#0]
LD1RB {Z0.D}, P0/Z, [X3,#0]
ld1rb {z0.d}, p0/z, [x3]
ld1rb {z0.d}, p0/z, [sp,#0]
LD1RB {Z0.D}, P0/Z, [SP,#0]
ld1rb {z0.d}, p0/z, [sp]
ld1rb {z0.d}, p0/z, [x0,#31]
LD1RB {Z0.D}, P0/Z, [X0,#31]
ld1rb {z0.d}, p0/z, [x0,#32]
LD1RB {Z0.D}, P0/Z, [X0,#32]
ld1rb {z0.d}, p0/z, [x0,#33]
LD1RB {Z0.D}, P0/Z, [X0,#33]
ld1rb {z0.d}, p0/z, [x0,#63]
LD1RB {Z0.D}, P0/Z, [X0,#63]
ld1rd z0.d, p0/z, [x0,#0]
ld1rd {z0.d}, p0/z, [x0,#0]
LD1RD {Z0.D}, P0/Z, [X0,#0]
ld1rd {z0.d}, p0/z, [x0]
ld1rd z1.d, p0/z, [x0,#0]
ld1rd {z1.d}, p0/z, [x0,#0]
LD1RD {Z1.D}, P0/Z, [X0,#0]
ld1rd {z1.d}, p0/z, [x0]
ld1rd z31.d, p0/z, [x0,#0]
ld1rd {z31.d}, p0/z, [x0,#0]
LD1RD {Z31.D}, P0/Z, [X0,#0]
ld1rd {z31.d}, p0/z, [x0]
ld1rd {z0.d}, p2/z, [x0,#0]
LD1RD {Z0.D}, P2/Z, [X0,#0]
ld1rd {z0.d}, p2/z, [x0]
ld1rd {z0.d}, p7/z, [x0,#0]
LD1RD {Z0.D}, P7/Z, [X0,#0]
ld1rd {z0.d}, p7/z, [x0]
ld1rd {z0.d}, p0/z, [x3,#0]
LD1RD {Z0.D}, P0/Z, [X3,#0]
ld1rd {z0.d}, p0/z, [x3]
ld1rd {z0.d}, p0/z, [sp,#0]
LD1RD {Z0.D}, P0/Z, [SP,#0]
ld1rd {z0.d}, p0/z, [sp]
ld1rd {z0.d}, p0/z, [x0,#248]
LD1RD {Z0.D}, P0/Z, [X0,#248]
ld1rd {z0.d}, p0/z, [x0,#256]
LD1RD {Z0.D}, P0/Z, [X0,#256]
ld1rd {z0.d}, p0/z, [x0,#264]
LD1RD {Z0.D}, P0/Z, [X0,#264]
ld1rd {z0.d}, p0/z, [x0,#504]
LD1RD {Z0.D}, P0/Z, [X0,#504]
ld1rh z0.h, p0/z, [x0,#0]
ld1rh {z0.h}, p0/z, [x0,#0]
LD1RH {Z0.H}, P0/Z, [X0,#0]
ld1rh {z0.h}, p0/z, [x0]
ld1rh z1.h, p0/z, [x0,#0]
ld1rh {z1.h}, p0/z, [x0,#0]
LD1RH {Z1.H}, P0/Z, [X0,#0]
ld1rh {z1.h}, p0/z, [x0]
ld1rh z31.h, p0/z, [x0,#0]
ld1rh {z31.h}, p0/z, [x0,#0]
LD1RH {Z31.H}, P0/Z, [X0,#0]
ld1rh {z31.h}, p0/z, [x0]
ld1rh {z0.h}, p2/z, [x0,#0]
LD1RH {Z0.H}, P2/Z, [X0,#0]
ld1rh {z0.h}, p2/z, [x0]
ld1rh {z0.h}, p7/z, [x0,#0]
LD1RH {Z0.H}, P7/Z, [X0,#0]
ld1rh {z0.h}, p7/z, [x0]
ld1rh {z0.h}, p0/z, [x3,#0]
LD1RH {Z0.H}, P0/Z, [X3,#0]
ld1rh {z0.h}, p0/z, [x3]
ld1rh {z0.h}, p0/z, [sp,#0]
LD1RH {Z0.H}, P0/Z, [SP,#0]
ld1rh {z0.h}, p0/z, [sp]
ld1rh {z0.h}, p0/z, [x0,#62]
LD1RH {Z0.H}, P0/Z, [X0,#62]
ld1rh {z0.h}, p0/z, [x0,#64]
LD1RH {Z0.H}, P0/Z, [X0,#64]
ld1rh {z0.h}, p0/z, [x0,#66]
LD1RH {Z0.H}, P0/Z, [X0,#66]
ld1rh {z0.h}, p0/z, [x0,#126]
LD1RH {Z0.H}, P0/Z, [X0,#126]
ld1rh z0.s, p0/z, [x0,#0]
ld1rh {z0.s}, p0/z, [x0,#0]
LD1RH {Z0.S}, P0/Z, [X0,#0]
ld1rh {z0.s}, p0/z, [x0]
ld1rh z1.s, p0/z, [x0,#0]
ld1rh {z1.s}, p0/z, [x0,#0]
LD1RH {Z1.S}, P0/Z, [X0,#0]
ld1rh {z1.s}, p0/z, [x0]
ld1rh z31.s, p0/z, [x0,#0]
ld1rh {z31.s}, p0/z, [x0,#0]
LD1RH {Z31.S}, P0/Z, [X0,#0]
ld1rh {z31.s}, p0/z, [x0]
ld1rh {z0.s}, p2/z, [x0,#0]
LD1RH {Z0.S}, P2/Z, [X0,#0]
ld1rh {z0.s}, p2/z, [x0]
ld1rh {z0.s}, p7/z, [x0,#0]
LD1RH {Z0.S}, P7/Z, [X0,#0]
ld1rh {z0.s}, p7/z, [x0]
ld1rh {z0.s}, p0/z, [x3,#0]
LD1RH {Z0.S}, P0/Z, [X3,#0]
ld1rh {z0.s}, p0/z, [x3]
ld1rh {z0.s}, p0/z, [sp,#0]
LD1RH {Z0.S}, P0/Z, [SP,#0]
ld1rh {z0.s}, p0/z, [sp]
ld1rh {z0.s}, p0/z, [x0,#62]
LD1RH {Z0.S}, P0/Z, [X0,#62]
ld1rh {z0.s}, p0/z, [x0,#64]
LD1RH {Z0.S}, P0/Z, [X0,#64]
ld1rh {z0.s}, p0/z, [x0,#66]
LD1RH {Z0.S}, P0/Z, [X0,#66]
ld1rh {z0.s}, p0/z, [x0,#126]
LD1RH {Z0.S}, P0/Z, [X0,#126]
ld1rh z0.d, p0/z, [x0,#0]
ld1rh {z0.d}, p0/z, [x0,#0]
LD1RH {Z0.D}, P0/Z, [X0,#0]
ld1rh {z0.d}, p0/z, [x0]
ld1rh z1.d, p0/z, [x0,#0]
ld1rh {z1.d}, p0/z, [x0,#0]
LD1RH {Z1.D}, P0/Z, [X0,#0]
ld1rh {z1.d}, p0/z, [x0]
ld1rh z31.d, p0/z, [x0,#0]
ld1rh {z31.d}, p0/z, [x0,#0]
LD1RH {Z31.D}, P0/Z, [X0,#0]
ld1rh {z31.d}, p0/z, [x0]
ld1rh {z0.d}, p2/z, [x0,#0]
LD1RH {Z0.D}, P2/Z, [X0,#0]
ld1rh {z0.d}, p2/z, [x0]
ld1rh {z0.d}, p7/z, [x0,#0]
LD1RH {Z0.D}, P7/Z, [X0,#0]
ld1rh {z0.d}, p7/z, [x0]
ld1rh {z0.d}, p0/z, [x3,#0]
LD1RH {Z0.D}, P0/Z, [X3,#0]
ld1rh {z0.d}, p0/z, [x3]
ld1rh {z0.d}, p0/z, [sp,#0]
LD1RH {Z0.D}, P0/Z, [SP,#0]
ld1rh {z0.d}, p0/z, [sp]
ld1rh {z0.d}, p0/z, [x0,#62]
LD1RH {Z0.D}, P0/Z, [X0,#62]
ld1rh {z0.d}, p0/z, [x0,#64]
LD1RH {Z0.D}, P0/Z, [X0,#64]
ld1rh {z0.d}, p0/z, [x0,#66]
LD1RH {Z0.D}, P0/Z, [X0,#66]
ld1rh {z0.d}, p0/z, [x0,#126]
LD1RH {Z0.D}, P0/Z, [X0,#126]
ld1rsb z0.d, p0/z, [x0,#0]
ld1rsb {z0.d}, p0/z, [x0,#0]
LD1RSB {Z0.D}, P0/Z, [X0,#0]
ld1rsb {z0.d}, p0/z, [x0]
ld1rsb z1.d, p0/z, [x0,#0]
ld1rsb {z1.d}, p0/z, [x0,#0]
LD1RSB {Z1.D}, P0/Z, [X0,#0]
ld1rsb {z1.d}, p0/z, [x0]
ld1rsb z31.d, p0/z, [x0,#0]
ld1rsb {z31.d}, p0/z, [x0,#0]
LD1RSB {Z31.D}, P0/Z, [X0,#0]
ld1rsb {z31.d}, p0/z, [x0]
ld1rsb {z0.d}, p2/z, [x0,#0]
LD1RSB {Z0.D}, P2/Z, [X0,#0]
ld1rsb {z0.d}, p2/z, [x0]
ld1rsb {z0.d}, p7/z, [x0,#0]
LD1RSB {Z0.D}, P7/Z, [X0,#0]
ld1rsb {z0.d}, p7/z, [x0]
ld1rsb {z0.d}, p0/z, [x3,#0]
LD1RSB {Z0.D}, P0/Z, [X3,#0]
ld1rsb {z0.d}, p0/z, [x3]
ld1rsb {z0.d}, p0/z, [sp,#0]
LD1RSB {Z0.D}, P0/Z, [SP,#0]
ld1rsb {z0.d}, p0/z, [sp]
ld1rsb {z0.d}, p0/z, [x0,#31]
LD1RSB {Z0.D}, P0/Z, [X0,#31]
ld1rsb {z0.d}, p0/z, [x0,#32]
LD1RSB {Z0.D}, P0/Z, [X0,#32]
ld1rsb {z0.d}, p0/z, [x0,#33]
LD1RSB {Z0.D}, P0/Z, [X0,#33]
ld1rsb {z0.d}, p0/z, [x0,#63]
LD1RSB {Z0.D}, P0/Z, [X0,#63]
ld1rsb z0.s, p0/z, [x0,#0]
ld1rsb {z0.s}, p0/z, [x0,#0]
LD1RSB {Z0.S}, P0/Z, [X0,#0]
ld1rsb {z0.s}, p0/z, [x0]
ld1rsb z1.s, p0/z, [x0,#0]
ld1rsb {z1.s}, p0/z, [x0,#0]
LD1RSB {Z1.S}, P0/Z, [X0,#0]
ld1rsb {z1.s}, p0/z, [x0]
ld1rsb z31.s, p0/z, [x0,#0]
ld1rsb {z31.s}, p0/z, [x0,#0]
LD1RSB {Z31.S}, P0/Z, [X0,#0]
ld1rsb {z31.s}, p0/z, [x0]
ld1rsb {z0.s}, p2/z, [x0,#0]
LD1RSB {Z0.S}, P2/Z, [X0,#0]
ld1rsb {z0.s}, p2/z, [x0]
ld1rsb {z0.s}, p7/z, [x0,#0]
LD1RSB {Z0.S}, P7/Z, [X0,#0]
ld1rsb {z0.s}, p7/z, [x0]
ld1rsb {z0.s}, p0/z, [x3,#0]
LD1RSB {Z0.S}, P0/Z, [X3,#0]
ld1rsb {z0.s}, p0/z, [x3]
ld1rsb {z0.s}, p0/z, [sp,#0]
LD1RSB {Z0.S}, P0/Z, [SP,#0]
ld1rsb {z0.s}, p0/z, [sp]
ld1rsb {z0.s}, p0/z, [x0,#31]
LD1RSB {Z0.S}, P0/Z, [X0,#31]
ld1rsb {z0.s}, p0/z, [x0,#32]
LD1RSB {Z0.S}, P0/Z, [X0,#32]
ld1rsb {z0.s}, p0/z, [x0,#33]
LD1RSB {Z0.S}, P0/Z, [X0,#33]
ld1rsb {z0.s}, p0/z, [x0,#63]
LD1RSB {Z0.S}, P0/Z, [X0,#63]
ld1rsb z0.h, p0/z, [x0,#0]
ld1rsb {z0.h}, p0/z, [x0,#0]
LD1RSB {Z0.H}, P0/Z, [X0,#0]
ld1rsb {z0.h}, p0/z, [x0]
ld1rsb z1.h, p0/z, [x0,#0]
ld1rsb {z1.h}, p0/z, [x0,#0]
LD1RSB {Z1.H}, P0/Z, [X0,#0]
ld1rsb {z1.h}, p0/z, [x0]
ld1rsb z31.h, p0/z, [x0,#0]
ld1rsb {z31.h}, p0/z, [x0,#0]
LD1RSB {Z31.H}, P0/Z, [X0,#0]
ld1rsb {z31.h}, p0/z, [x0]
ld1rsb {z0.h}, p2/z, [x0,#0]
LD1RSB {Z0.H}, P2/Z, [X0,#0]
ld1rsb {z0.h}, p2/z, [x0]
ld1rsb {z0.h}, p7/z, [x0,#0]
LD1RSB {Z0.H}, P7/Z, [X0,#0]
ld1rsb {z0.h}, p7/z, [x0]
ld1rsb {z0.h}, p0/z, [x3,#0]
LD1RSB {Z0.H}, P0/Z, [X3,#0]
ld1rsb {z0.h}, p0/z, [x3]
ld1rsb {z0.h}, p0/z, [sp,#0]
LD1RSB {Z0.H}, P0/Z, [SP,#0]
ld1rsb {z0.h}, p0/z, [sp]
ld1rsb {z0.h}, p0/z, [x0,#31]
LD1RSB {Z0.H}, P0/Z, [X0,#31]
ld1rsb {z0.h}, p0/z, [x0,#32]
LD1RSB {Z0.H}, P0/Z, [X0,#32]
ld1rsb {z0.h}, p0/z, [x0,#33]
LD1RSB {Z0.H}, P0/Z, [X0,#33]
ld1rsb {z0.h}, p0/z, [x0,#63]
LD1RSB {Z0.H}, P0/Z, [X0,#63]
ld1rsh z0.d, p0/z, [x0,#0]
ld1rsh {z0.d}, p0/z, [x0,#0]
LD1RSH {Z0.D}, P0/Z, [X0,#0]
ld1rsh {z0.d}, p0/z, [x0]
ld1rsh z1.d, p0/z, [x0,#0]
ld1rsh {z1.d}, p0/z, [x0,#0]
LD1RSH {Z1.D}, P0/Z, [X0,#0]
ld1rsh {z1.d}, p0/z, [x0]
ld1rsh z31.d, p0/z, [x0,#0]
ld1rsh {z31.d}, p0/z, [x0,#0]
LD1RSH {Z31.D}, P0/Z, [X0,#0]
ld1rsh {z31.d}, p0/z, [x0]
ld1rsh {z0.d}, p2/z, [x0,#0]
LD1RSH {Z0.D}, P2/Z, [X0,#0]
ld1rsh {z0.d}, p2/z, [x0]
ld1rsh {z0.d}, p7/z, [x0,#0]
LD1RSH {Z0.D}, P7/Z, [X0,#0]
ld1rsh {z0.d}, p7/z, [x0]
ld1rsh {z0.d}, p0/z, [x3,#0]
LD1RSH {Z0.D}, P0/Z, [X3,#0]
ld1rsh {z0.d}, p0/z, [x3]
ld1rsh {z0.d}, p0/z, [sp,#0]
LD1RSH {Z0.D}, P0/Z, [SP,#0]
ld1rsh {z0.d}, p0/z, [sp]
ld1rsh {z0.d}, p0/z, [x0,#62]
LD1RSH {Z0.D}, P0/Z, [X0,#62]
ld1rsh {z0.d}, p0/z, [x0,#64]
LD1RSH {Z0.D}, P0/Z, [X0,#64]
ld1rsh {z0.d}, p0/z, [x0,#66]
LD1RSH {Z0.D}, P0/Z, [X0,#66]
ld1rsh {z0.d}, p0/z, [x0,#126]
LD1RSH {Z0.D}, P0/Z, [X0,#126]
ld1rsh z0.s, p0/z, [x0,#0]
ld1rsh {z0.s}, p0/z, [x0,#0]
LD1RSH {Z0.S}, P0/Z, [X0,#0]
ld1rsh {z0.s}, p0/z, [x0]
ld1rsh z1.s, p0/z, [x0,#0]
ld1rsh {z1.s}, p0/z, [x0,#0]
LD1RSH {Z1.S}, P0/Z, [X0,#0]
ld1rsh {z1.s}, p0/z, [x0]
ld1rsh z31.s, p0/z, [x0,#0]
ld1rsh {z31.s}, p0/z, [x0,#0]
LD1RSH {Z31.S}, P0/Z, [X0,#0]
ld1rsh {z31.s}, p0/z, [x0]
ld1rsh {z0.s}, p2/z, [x0,#0]
LD1RSH {Z0.S}, P2/Z, [X0,#0]
ld1rsh {z0.s}, p2/z, [x0]
ld1rsh {z0.s}, p7/z, [x0,#0]
LD1RSH {Z0.S}, P7/Z, [X0,#0]
ld1rsh {z0.s}, p7/z, [x0]
ld1rsh {z0.s}, p0/z, [x3,#0]
LD1RSH {Z0.S}, P0/Z, [X3,#0]
ld1rsh {z0.s}, p0/z, [x3]
ld1rsh {z0.s}, p0/z, [sp,#0]
LD1RSH {Z0.S}, P0/Z, [SP,#0]
ld1rsh {z0.s}, p0/z, [sp]
ld1rsh {z0.s}, p0/z, [x0,#62]
LD1RSH {Z0.S}, P0/Z, [X0,#62]
ld1rsh {z0.s}, p0/z, [x0,#64]
LD1RSH {Z0.S}, P0/Z, [X0,#64]
ld1rsh {z0.s}, p0/z, [x0,#66]
LD1RSH {Z0.S}, P0/Z, [X0,#66]
ld1rsh {z0.s}, p0/z, [x0,#126]
LD1RSH {Z0.S}, P0/Z, [X0,#126]
ld1rsw z0.d, p0/z, [x0,#0]
ld1rsw {z0.d}, p0/z, [x0,#0]
LD1RSW {Z0.D}, P0/Z, [X0,#0]
ld1rsw {z0.d}, p0/z, [x0]
ld1rsw z1.d, p0/z, [x0,#0]
ld1rsw {z1.d}, p0/z, [x0,#0]
LD1RSW {Z1.D}, P0/Z, [X0,#0]
ld1rsw {z1.d}, p0/z, [x0]
ld1rsw z31.d, p0/z, [x0,#0]
ld1rsw {z31.d}, p0/z, [x0,#0]
LD1RSW {Z31.D}, P0/Z, [X0,#0]
ld1rsw {z31.d}, p0/z, [x0]
ld1rsw {z0.d}, p2/z, [x0,#0]
LD1RSW {Z0.D}, P2/Z, [X0,#0]
ld1rsw {z0.d}, p2/z, [x0]
ld1rsw {z0.d}, p7/z, [x0,#0]
LD1RSW {Z0.D}, P7/Z, [X0,#0]
ld1rsw {z0.d}, p7/z, [x0]
ld1rsw {z0.d}, p0/z, [x3,#0]
LD1RSW {Z0.D}, P0/Z, [X3,#0]
ld1rsw {z0.d}, p0/z, [x3]
ld1rsw {z0.d}, p0/z, [sp,#0]
LD1RSW {Z0.D}, P0/Z, [SP,#0]
ld1rsw {z0.d}, p0/z, [sp]
ld1rsw {z0.d}, p0/z, [x0,#124]
LD1RSW {Z0.D}, P0/Z, [X0,#124]
ld1rsw {z0.d}, p0/z, [x0,#128]
LD1RSW {Z0.D}, P0/Z, [X0,#128]
ld1rsw {z0.d}, p0/z, [x0,#132]
LD1RSW {Z0.D}, P0/Z, [X0,#132]
ld1rsw {z0.d}, p0/z, [x0,#252]
LD1RSW {Z0.D}, P0/Z, [X0,#252]
ld1rqb z0.b, p0/z, [x0,#0]
ld1rqb {z0.b}, p0/z, [x0,#0]
LD1RQB {Z0.B}, P0/Z, [X0,#0]
ld1rqb {z0.b}, p0/z, [x0]
ld1rqb z1.b, p0/z, [x0,#0]
ld1rqb {z1.b}, p0/z, [x0,#0]
LD1RQB {Z1.B}, P0/Z, [X0,#0]
ld1rqb {z1.b}, p0/z, [x0]
ld1rqb z31.b, p0/z, [x0,#0]
ld1rqb {z31.b}, p0/z, [x0,#0]
LD1RQB {Z31.B}, P0/Z, [X0,#0]
ld1rqb {z31.b}, p0/z, [x0]
ld1rqb {z0.b}, p2/z, [x0,#0]
LD1RQB {Z0.B}, P2/Z, [X0,#0]
ld1rqb {z0.b}, p2/z, [x0]
ld1rqb {z0.b}, p7/z, [x0,#0]
LD1RQB {Z0.B}, P7/Z, [X0,#0]
ld1rqb {z0.b}, p7/z, [x0]
ld1rqb {z0.b}, p0/z, [x3,#0]
LD1RQB {Z0.B}, P0/Z, [X3,#0]
ld1rqb {z0.b}, p0/z, [x3]
ld1rqb {z0.b}, p0/z, [sp,#0]
LD1RQB {Z0.B}, P0/Z, [SP,#0]
ld1rqb {z0.b}, p0/z, [sp]
ld1rqb {z0.b}, p0/z, [x0,#-128]
LD1RQB {Z0.B}, P0/Z, [X0,#-128]
ld1rqb {z0.b}, p0/z, [x0,#-16]
LD1RQB {Z0.B}, P0/Z, [X0,#-16]
ld1rqb {z0.b}, p0/z, [x0,#16]
LD1RQB {Z0.B}, P0/Z, [X0,#16]
ld1rqb {z0.b}, p0/z, [x0,#112]
LD1RQB {Z0.B}, P0/Z, [X0,#112]
ld1rqb z0.b, p0/z, [x0,x0]
ld1rqb {z0.b}, p0/z, [x0,x0]
LD1RQB {Z0.B}, P0/Z, [X0,X0]
ld1rqb {z0.b}, p0/z, [x0,x0,lsl #0]
ld1rqb z1.b, p0/z, [x0,x0]
ld1rqb {z1.b}, p0/z, [x0,x0]
LD1RQB {Z1.B}, P0/Z, [X0,X0]
ld1rqb {z1.b}, p0/z, [x0,x0,lsl #0]
ld1rqb z31.b, p0/z, [x0,x0]
ld1rqb {z31.b}, p0/z, [x0,x0]
LD1RQB {Z31.B}, P0/Z, [X0,X0]
ld1rqb {z31.b}, p0/z, [x0,x0,lsl #0]
ld1rqb {z0.b}, p2/z, [x0,x0]
LD1RQB {Z0.B}, P2/Z, [X0,X0]
ld1rqb {z0.b}, p2/z, [x0,x0,lsl #0]
ld1rqb {z0.b}, p7/z, [x0,x0]
LD1RQB {Z0.B}, P7/Z, [X0,X0]
ld1rqb {z0.b}, p7/z, [x0,x0,lsl #0]
ld1rqb {z0.b}, p0/z, [x3,x0]
LD1RQB {Z0.B}, P0/Z, [X3,X0]
ld1rqb {z0.b}, p0/z, [x3,x0,lsl #0]
ld1rqb {z0.b}, p0/z, [sp,x0]
LD1RQB {Z0.B}, P0/Z, [SP,X0]
ld1rqb {z0.b}, p0/z, [sp,x0,lsl #0]
ld1rqb {z0.b}, p0/z, [x0,x4]
LD1RQB {Z0.B}, P0/Z, [X0,X4]
ld1rqb {z0.b}, p0/z, [x0,x4,lsl #0]
ld1rqb {z0.b}, p0/z, [x0,x30]
LD1RQB {Z0.B}, P0/Z, [X0,X30]
ld1rqb {z0.b}, p0/z, [x0,x30,lsl #0]
ld1rqd z0.d, p0/z, [x0,#0]
ld1rqd {z0.d}, p0/z, [x0,#0]
LD1RQD {Z0.D}, P0/Z, [X0,#0]
ld1rqd {z0.d}, p0/z, [x0]
ld1rqd z1.d, p0/z, [x0,#0]
ld1rqd {z1.d}, p0/z, [x0,#0]
LD1RQD {Z1.D}, P0/Z, [X0,#0]
ld1rqd {z1.d}, p0/z, [x0]
ld1rqd z31.d, p0/z, [x0,#0]
ld1rqd {z31.d}, p0/z, [x0,#0]
LD1RQD {Z31.D}, P0/Z, [X0,#0]
ld1rqd {z31.d}, p0/z, [x0]
ld1rqd {z0.d}, p2/z, [x0,#0]
LD1RQD {Z0.D}, P2/Z, [X0,#0]
ld1rqd {z0.d}, p2/z, [x0]
ld1rqd {z0.d}, p7/z, [x0,#0]
LD1RQD {Z0.D}, P7/Z, [X0,#0]
ld1rqd {z0.d}, p7/z, [x0]
ld1rqd {z0.d}, p0/z, [x3,#0]
LD1RQD {Z0.D}, P0/Z, [X3,#0]
ld1rqd {z0.d}, p0/z, [x3]
ld1rqd {z0.d}, p0/z, [sp,#0]
LD1RQD {Z0.D}, P0/Z, [SP,#0]
ld1rqd {z0.d}, p0/z, [sp]
ld1rqd {z0.d}, p0/z, [x0,#-128]
LD1RQD {Z0.D}, P0/Z, [X0,#-128]
ld1rqd {z0.d}, p0/z, [x0,#-16]
LD1RQD {Z0.D}, P0/Z, [X0,#-16]
ld1rqd {z0.d}, p0/z, [x0,#16]
LD1RQD {Z0.D}, P0/Z, [X0,#16]
ld1rqd {z0.d}, p0/z, [x0,#112]
LD1RQD {Z0.D}, P0/Z, [X0,#112]
ld1rqd z0.d, p0/z, [x0,x0,lsl #3]
ld1rqd {z0.d}, p0/z, [x0,x0,lsl #3]
LD1RQD {Z0.D}, P0/Z, [X0,X0,LSL #3]
ld1rqd z1.d, p0/z, [x0,x0,lsl #3]
ld1rqd {z1.d}, p0/z, [x0,x0,lsl #3]
LD1RQD {Z1.D}, P0/Z, [X0,X0,LSL #3]
ld1rqd z31.d, p0/z, [x0,x0,lsl #3]
ld1rqd {z31.d}, p0/z, [x0,x0,lsl #3]
LD1RQD {Z31.D}, P0/Z, [X0,X0,LSL #3]
ld1rqd {z0.d}, p2/z, [x0,x0,lsl #3]
LD1RQD {Z0.D}, P2/Z, [X0,X0,LSL #3]
ld1rqd {z0.d}, p7/z, [x0,x0,lsl #3]
LD1RQD {Z0.D}, P7/Z, [X0,X0,LSL #3]
ld1rqd {z0.d}, p0/z, [x3,x0,lsl #3]
LD1RQD {Z0.D}, P0/Z, [X3,X0,LSL #3]
ld1rqd {z0.d}, p0/z, [sp,x0,lsl #3]
LD1RQD {Z0.D}, P0/Z, [SP,X0,LSL #3]
ld1rqd {z0.d}, p0/z, [x0,x4,lsl #3]
LD1RQD {Z0.D}, P0/Z, [X0,X4,LSL #3]
ld1rqd {z0.d}, p0/z, [x0,x30,lsl #3]
LD1RQD {Z0.D}, P0/Z, [X0,X30,LSL #3]
ld1rqh z0.h, p0/z, [x0,#0]
ld1rqh {z0.h}, p0/z, [x0,#0]
LD1RQH {Z0.H}, P0/Z, [X0,#0]
ld1rqh {z0.h}, p0/z, [x0]
ld1rqh z1.h, p0/z, [x0,#0]
ld1rqh {z1.h}, p0/z, [x0,#0]
LD1RQH {Z1.H}, P0/Z, [X0,#0]
ld1rqh {z1.h}, p0/z, [x0]
ld1rqh z31.h, p0/z, [x0,#0]
ld1rqh {z31.h}, p0/z, [x0,#0]
LD1RQH {Z31.H}, P0/Z, [X0,#0]
ld1rqh {z31.h}, p0/z, [x0]
ld1rqh {z0.h}, p2/z, [x0,#0]
LD1RQH {Z0.H}, P2/Z, [X0,#0]
ld1rqh {z0.h}, p2/z, [x0]
ld1rqh {z0.h}, p7/z, [x0,#0]
LD1RQH {Z0.H}, P7/Z, [X0,#0]
ld1rqh {z0.h}, p7/z, [x0]
ld1rqh {z0.h}, p0/z, [x3,#0]
LD1RQH {Z0.H}, P0/Z, [X3,#0]
ld1rqh {z0.h}, p0/z, [x3]
ld1rqh {z0.h}, p0/z, [sp,#0]
LD1RQH {Z0.H}, P0/Z, [SP,#0]
ld1rqh {z0.h}, p0/z, [sp]
ld1rqh {z0.h}, p0/z, [x0,#-128]
LD1RQH {Z0.H}, P0/Z, [X0,#-128]
ld1rqh {z0.h}, p0/z, [x0,#-16]
LD1RQH {Z0.H}, P0/Z, [X0,#-16]
ld1rqh {z0.h}, p0/z, [x0,#16]
LD1RQH {Z0.H}, P0/Z, [X0,#16]
ld1rqh {z0.h}, p0/z, [x0,#112]
LD1RQH {Z0.H}, P0/Z, [X0,#112]
ld1rqh z0.h, p0/z, [x0,x0,lsl #1]
ld1rqh {z0.h}, p0/z, [x0,x0,lsl #1]
LD1RQH {Z0.H}, P0/Z, [X0,X0,LSL #1]
ld1rqh z1.h, p0/z, [x0,x0,lsl #1]
ld1rqh {z1.h}, p0/z, [x0,x0,lsl #1]
LD1RQH {Z1.H}, P0/Z, [X0,X0,LSL #1]
ld1rqh z31.h, p0/z, [x0,x0,lsl #1]
ld1rqh {z31.h}, p0/z, [x0,x0,lsl #1]
LD1RQH {Z31.H}, P0/Z, [X0,X0,LSL #1]
ld1rqh {z0.h}, p2/z, [x0,x0,lsl #1]
LD1RQH {Z0.H}, P2/Z, [X0,X0,LSL #1]
ld1rqh {z0.h}, p7/z, [x0,x0,lsl #1]
LD1RQH {Z0.H}, P7/Z, [X0,X0,LSL #1]
ld1rqh {z0.h}, p0/z, [x3,x0,lsl #1]
LD1RQH {Z0.H}, P0/Z, [X3,X0,LSL #1]
ld1rqh {z0.h}, p0/z, [sp,x0,lsl #1]
LD1RQH {Z0.H}, P0/Z, [SP,X0,LSL #1]
ld1rqh {z0.h}, p0/z, [x0,x4,lsl #1]
LD1RQH {Z0.H}, P0/Z, [X0,X4,LSL #1]
ld1rqh {z0.h}, p0/z, [x0,x30,lsl #1]
LD1RQH {Z0.H}, P0/Z, [X0,X30,LSL #1]
ld1rqw z0.s, p0/z, [x0,#0]
ld1rqw {z0.s}, p0/z, [x0,#0]
LD1RQW {Z0.S}, P0/Z, [X0,#0]
ld1rqw {z0.s}, p0/z, [x0]
ld1rqw z1.s, p0/z, [x0,#0]
ld1rqw {z1.s}, p0/z, [x0,#0]
LD1RQW {Z1.S}, P0/Z, [X0,#0]
ld1rqw {z1.s}, p0/z, [x0]
ld1rqw z31.s, p0/z, [x0,#0]
ld1rqw {z31.s}, p0/z, [x0,#0]
LD1RQW {Z31.S}, P0/Z, [X0,#0]
ld1rqw {z31.s}, p0/z, [x0]
ld1rqw {z0.s}, p2/z, [x0,#0]
LD1RQW {Z0.S}, P2/Z, [X0,#0]
ld1rqw {z0.s}, p2/z, [x0]
ld1rqw {z0.s}, p7/z, [x0,#0]
LD1RQW {Z0.S}, P7/Z, [X0,#0]
ld1rqw {z0.s}, p7/z, [x0]
ld1rqw {z0.s}, p0/z, [x3,#0]
LD1RQW {Z0.S}, P0/Z, [X3,#0]
ld1rqw {z0.s}, p0/z, [x3]
ld1rqw {z0.s}, p0/z, [sp,#0]
LD1RQW {Z0.S}, P0/Z, [SP,#0]
ld1rqw {z0.s}, p0/z, [sp]
ld1rqw {z0.s}, p0/z, [x0,#-128]
LD1RQW {Z0.S}, P0/Z, [X0,#-128]
ld1rqw {z0.s}, p0/z, [x0,#-16]
LD1RQW {Z0.S}, P0/Z, [X0,#-16]
ld1rqw {z0.s}, p0/z, [x0,#16]
LD1RQW {Z0.S}, P0/Z, [X0,#16]
ld1rqw {z0.s}, p0/z, [x0,#112]
LD1RQW {Z0.S}, P0/Z, [X0,#112]
ld1rqw z0.s, p0/z, [x0,x0,lsl #2]
ld1rqw {z0.s}, p0/z, [x0,x0,lsl #2]
LD1RQW {Z0.S}, P0/Z, [X0,X0,LSL #2]
ld1rqw z1.s, p0/z, [x0,x0,lsl #2]
ld1rqw {z1.s}, p0/z, [x0,x0,lsl #2]
LD1RQW {Z1.S}, P0/Z, [X0,X0,LSL #2]
ld1rqw z31.s, p0/z, [x0,x0,lsl #2]
ld1rqw {z31.s}, p0/z, [x0,x0,lsl #2]
LD1RQW {Z31.S}, P0/Z, [X0,X0,LSL #2]
ld1rqw {z0.s}, p2/z, [x0,x0,lsl #2]
LD1RQW {Z0.S}, P2/Z, [X0,X0,LSL #2]
ld1rqw {z0.s}, p7/z, [x0,x0,lsl #2]
LD1RQW {Z0.S}, P7/Z, [X0,X0,LSL #2]
ld1rqw {z0.s}, p0/z, [x3,x0,lsl #2]
LD1RQW {Z0.S}, P0/Z, [X3,X0,LSL #2]
ld1rqw {z0.s}, p0/z, [sp,x0,lsl #2]
LD1RQW {Z0.S}, P0/Z, [SP,X0,LSL #2]
ld1rqw {z0.s}, p0/z, [x0,x4,lsl #2]
LD1RQW {Z0.S}, P0/Z, [X0,X4,LSL #2]
ld1rqw {z0.s}, p0/z, [x0,x30,lsl #2]
LD1RQW {Z0.S}, P0/Z, [X0,X30,LSL #2]
ld1rw z0.s, p0/z, [x0,#0]
ld1rw {z0.s}, p0/z, [x0,#0]
LD1RW {Z0.S}, P0/Z, [X0,#0]
ld1rw {z0.s}, p0/z, [x0]
ld1rw z1.s, p0/z, [x0,#0]
ld1rw {z1.s}, p0/z, [x0,#0]
LD1RW {Z1.S}, P0/Z, [X0,#0]
ld1rw {z1.s}, p0/z, [x0]
ld1rw z31.s, p0/z, [x0,#0]
ld1rw {z31.s}, p0/z, [x0,#0]
LD1RW {Z31.S}, P0/Z, [X0,#0]
ld1rw {z31.s}, p0/z, [x0]
ld1rw {z0.s}, p2/z, [x0,#0]
LD1RW {Z0.S}, P2/Z, [X0,#0]
ld1rw {z0.s}, p2/z, [x0]
ld1rw {z0.s}, p7/z, [x0,#0]
LD1RW {Z0.S}, P7/Z, [X0,#0]
ld1rw {z0.s}, p7/z, [x0]
ld1rw {z0.s}, p0/z, [x3,#0]
LD1RW {Z0.S}, P0/Z, [X3,#0]
ld1rw {z0.s}, p0/z, [x3]
ld1rw {z0.s}, p0/z, [sp,#0]
LD1RW {Z0.S}, P0/Z, [SP,#0]
ld1rw {z0.s}, p0/z, [sp]
ld1rw {z0.s}, p0/z, [x0,#124]
LD1RW {Z0.S}, P0/Z, [X0,#124]
ld1rw {z0.s}, p0/z, [x0,#128]
LD1RW {Z0.S}, P0/Z, [X0,#128]
ld1rw {z0.s}, p0/z, [x0,#132]
LD1RW {Z0.S}, P0/Z, [X0,#132]
ld1rw {z0.s}, p0/z, [x0,#252]
LD1RW {Z0.S}, P0/Z, [X0,#252]
ld1rw z0.d, p0/z, [x0,#0]
ld1rw {z0.d}, p0/z, [x0,#0]
LD1RW {Z0.D}, P0/Z, [X0,#0]
ld1rw {z0.d}, p0/z, [x0]
ld1rw z1.d, p0/z, [x0,#0]
ld1rw {z1.d}, p0/z, [x0,#0]
LD1RW {Z1.D}, P0/Z, [X0,#0]
ld1rw {z1.d}, p0/z, [x0]
ld1rw z31.d, p0/z, [x0,#0]
ld1rw {z31.d}, p0/z, [x0,#0]
LD1RW {Z31.D}, P0/Z, [X0,#0]
ld1rw {z31.d}, p0/z, [x0]
ld1rw {z0.d}, p2/z, [x0,#0]
LD1RW {Z0.D}, P2/Z, [X0,#0]
ld1rw {z0.d}, p2/z, [x0]
ld1rw {z0.d}, p7/z, [x0,#0]
LD1RW {Z0.D}, P7/Z, [X0,#0]
ld1rw {z0.d}, p7/z, [x0]
ld1rw {z0.d}, p0/z, [x3,#0]
LD1RW {Z0.D}, P0/Z, [X3,#0]
ld1rw {z0.d}, p0/z, [x3]
ld1rw {z0.d}, p0/z, [sp,#0]
LD1RW {Z0.D}, P0/Z, [SP,#0]
ld1rw {z0.d}, p0/z, [sp]
ld1rw {z0.d}, p0/z, [x0,#124]
LD1RW {Z0.D}, P0/Z, [X0,#124]
ld1rw {z0.d}, p0/z, [x0,#128]
LD1RW {Z0.D}, P0/Z, [X0,#128]
ld1rw {z0.d}, p0/z, [x0,#132]
LD1RW {Z0.D}, P0/Z, [X0,#132]
ld1rw {z0.d}, p0/z, [x0,#252]
LD1RW {Z0.D}, P0/Z, [X0,#252]
ld1sb z0.s, p0/z, [x0,z0.s,uxtw]
ld1sb {z0.s}, p0/z, [x0,z0.s,uxtw]
LD1SB {Z0.S}, P0/Z, [X0,Z0.S,UXTW]
ld1sb {z0.s}, p0/z, [x0,z0.s,uxtw #0]
ld1sb z1.s, p0/z, [x0,z0.s,uxtw]
ld1sb {z1.s}, p0/z, [x0,z0.s,uxtw]
LD1SB {Z1.S}, P0/Z, [X0,Z0.S,UXTW]
ld1sb {z1.s}, p0/z, [x0,z0.s,uxtw #0]
ld1sb z31.s, p0/z, [x0,z0.s,uxtw]
ld1sb {z31.s}, p0/z, [x0,z0.s,uxtw]
LD1SB {Z31.S}, P0/Z, [X0,Z0.S,UXTW]
ld1sb {z31.s}, p0/z, [x0,z0.s,uxtw #0]
ld1sb {z0.s}, p2/z, [x0,z0.s,uxtw]
LD1SB {Z0.S}, P2/Z, [X0,Z0.S,UXTW]
ld1sb {z0.s}, p2/z, [x0,z0.s,uxtw #0]
ld1sb {z0.s}, p7/z, [x0,z0.s,uxtw]
LD1SB {Z0.S}, P7/Z, [X0,Z0.S,UXTW]
ld1sb {z0.s}, p7/z, [x0,z0.s,uxtw #0]
ld1sb {z0.s}, p0/z, [x3,z0.s,uxtw]
LD1SB {Z0.S}, P0/Z, [X3,Z0.S,UXTW]
ld1sb {z0.s}, p0/z, [x3,z0.s,uxtw #0]
ld1sb {z0.s}, p0/z, [sp,z0.s,uxtw]
LD1SB {Z0.S}, P0/Z, [SP,Z0.S,UXTW]
ld1sb {z0.s}, p0/z, [sp,z0.s,uxtw #0]
ld1sb {z0.s}, p0/z, [x0,z4.s,uxtw]
LD1SB {Z0.S}, P0/Z, [X0,Z4.S,UXTW]
ld1sb {z0.s}, p0/z, [x0,z4.s,uxtw #0]
ld1sb {z0.s}, p0/z, [x0,z31.s,uxtw]
LD1SB {Z0.S}, P0/Z, [X0,Z31.S,UXTW]
ld1sb {z0.s}, p0/z, [x0,z31.s,uxtw #0]
ld1sb z0.s, p0/z, [x0,z0.s,sxtw]
ld1sb {z0.s}, p0/z, [x0,z0.s,sxtw]
LD1SB {Z0.S}, P0/Z, [X0,Z0.S,SXTW]
ld1sb {z0.s}, p0/z, [x0,z0.s,sxtw #0]
ld1sb z1.s, p0/z, [x0,z0.s,sxtw]
ld1sb {z1.s}, p0/z, [x0,z0.s,sxtw]
LD1SB {Z1.S}, P0/Z, [X0,Z0.S,SXTW]
ld1sb {z1.s}, p0/z, [x0,z0.s,sxtw #0]
ld1sb z31.s, p0/z, [x0,z0.s,sxtw]
ld1sb {z31.s}, p0/z, [x0,z0.s,sxtw]
LD1SB {Z31.S}, P0/Z, [X0,Z0.S,SXTW]
ld1sb {z31.s}, p0/z, [x0,z0.s,sxtw #0]
ld1sb {z0.s}, p2/z, [x0,z0.s,sxtw]
LD1SB {Z0.S}, P2/Z, [X0,Z0.S,SXTW]
ld1sb {z0.s}, p2/z, [x0,z0.s,sxtw #0]
ld1sb {z0.s}, p7/z, [x0,z0.s,sxtw]
LD1SB {Z0.S}, P7/Z, [X0,Z0.S,SXTW]
ld1sb {z0.s}, p7/z, [x0,z0.s,sxtw #0]
ld1sb {z0.s}, p0/z, [x3,z0.s,sxtw]
LD1SB {Z0.S}, P0/Z, [X3,Z0.S,SXTW]
ld1sb {z0.s}, p0/z, [x3,z0.s,sxtw #0]
ld1sb {z0.s}, p0/z, [sp,z0.s,sxtw]
LD1SB {Z0.S}, P0/Z, [SP,Z0.S,SXTW]
ld1sb {z0.s}, p0/z, [sp,z0.s,sxtw #0]
ld1sb {z0.s}, p0/z, [x0,z4.s,sxtw]
LD1SB {Z0.S}, P0/Z, [X0,Z4.S,SXTW]
ld1sb {z0.s}, p0/z, [x0,z4.s,sxtw #0]
ld1sb {z0.s}, p0/z, [x0,z31.s,sxtw]
LD1SB {Z0.S}, P0/Z, [X0,Z31.S,SXTW]
ld1sb {z0.s}, p0/z, [x0,z31.s,sxtw #0]
ld1sb z0.d, p0/z, [x0,x0]
ld1sb {z0.d}, p0/z, [x0,x0]
LD1SB {Z0.D}, P0/Z, [X0,X0]
ld1sb {z0.d}, p0/z, [x0,x0,lsl #0]
ld1sb z1.d, p0/z, [x0,x0]
ld1sb {z1.d}, p0/z, [x0,x0]
LD1SB {Z1.D}, P0/Z, [X0,X0]
ld1sb {z1.d}, p0/z, [x0,x0,lsl #0]
ld1sb z31.d, p0/z, [x0,x0]
ld1sb {z31.d}, p0/z, [x0,x0]
LD1SB {Z31.D}, P0/Z, [X0,X0]
ld1sb {z31.d}, p0/z, [x0,x0,lsl #0]
ld1sb {z0.d}, p2/z, [x0,x0]
LD1SB {Z0.D}, P2/Z, [X0,X0]
ld1sb {z0.d}, p2/z, [x0,x0,lsl #0]
ld1sb {z0.d}, p7/z, [x0,x0]
LD1SB {Z0.D}, P7/Z, [X0,X0]
ld1sb {z0.d}, p7/z, [x0,x0,lsl #0]
ld1sb {z0.d}, p0/z, [x3,x0]
LD1SB {Z0.D}, P0/Z, [X3,X0]
ld1sb {z0.d}, p0/z, [x3,x0,lsl #0]
ld1sb {z0.d}, p0/z, [sp,x0]
LD1SB {Z0.D}, P0/Z, [SP,X0]
ld1sb {z0.d}, p0/z, [sp,x0,lsl #0]
ld1sb {z0.d}, p0/z, [x0,x4]
LD1SB {Z0.D}, P0/Z, [X0,X4]
ld1sb {z0.d}, p0/z, [x0,x4,lsl #0]
ld1sb {z0.d}, p0/z, [x0,x30]
LD1SB {Z0.D}, P0/Z, [X0,X30]
ld1sb {z0.d}, p0/z, [x0,x30,lsl #0]
ld1sb z0.s, p0/z, [x0,x0]
ld1sb {z0.s}, p0/z, [x0,x0]
LD1SB {Z0.S}, P0/Z, [X0,X0]
ld1sb {z0.s}, p0/z, [x0,x0,lsl #0]
ld1sb z1.s, p0/z, [x0,x0]
ld1sb {z1.s}, p0/z, [x0,x0]
LD1SB {Z1.S}, P0/Z, [X0,X0]
ld1sb {z1.s}, p0/z, [x0,x0,lsl #0]
ld1sb z31.s, p0/z, [x0,x0]
ld1sb {z31.s}, p0/z, [x0,x0]
LD1SB {Z31.S}, P0/Z, [X0,X0]
ld1sb {z31.s}, p0/z, [x0,x0,lsl #0]
ld1sb {z0.s}, p2/z, [x0,x0]
LD1SB {Z0.S}, P2/Z, [X0,X0]
ld1sb {z0.s}, p2/z, [x0,x0,lsl #0]
ld1sb {z0.s}, p7/z, [x0,x0]
LD1SB {Z0.S}, P7/Z, [X0,X0]
ld1sb {z0.s}, p7/z, [x0,x0,lsl #0]
ld1sb {z0.s}, p0/z, [x3,x0]
LD1SB {Z0.S}, P0/Z, [X3,X0]
ld1sb {z0.s}, p0/z, [x3,x0,lsl #0]
ld1sb {z0.s}, p0/z, [sp,x0]
LD1SB {Z0.S}, P0/Z, [SP,X0]
ld1sb {z0.s}, p0/z, [sp,x0,lsl #0]
ld1sb {z0.s}, p0/z, [x0,x4]
LD1SB {Z0.S}, P0/Z, [X0,X4]
ld1sb {z0.s}, p0/z, [x0,x4,lsl #0]
ld1sb {z0.s}, p0/z, [x0,x30]
LD1SB {Z0.S}, P0/Z, [X0,X30]
ld1sb {z0.s}, p0/z, [x0,x30,lsl #0]
ld1sb z0.h, p0/z, [x0,x0]
ld1sb {z0.h}, p0/z, [x0,x0]
LD1SB {Z0.H}, P0/Z, [X0,X0]
ld1sb {z0.h}, p0/z, [x0,x0,lsl #0]
ld1sb z1.h, p0/z, [x0,x0]
ld1sb {z1.h}, p0/z, [x0,x0]
LD1SB {Z1.H}, P0/Z, [X0,X0]
ld1sb {z1.h}, p0/z, [x0,x0,lsl #0]
ld1sb z31.h, p0/z, [x0,x0]
ld1sb {z31.h}, p0/z, [x0,x0]
LD1SB {Z31.H}, P0/Z, [X0,X0]
ld1sb {z31.h}, p0/z, [x0,x0,lsl #0]
ld1sb {z0.h}, p2/z, [x0,x0]
LD1SB {Z0.H}, P2/Z, [X0,X0]
ld1sb {z0.h}, p2/z, [x0,x0,lsl #0]
ld1sb {z0.h}, p7/z, [x0,x0]
LD1SB {Z0.H}, P7/Z, [X0,X0]
ld1sb {z0.h}, p7/z, [x0,x0,lsl #0]
ld1sb {z0.h}, p0/z, [x3,x0]
LD1SB {Z0.H}, P0/Z, [X3,X0]
ld1sb {z0.h}, p0/z, [x3,x0,lsl #0]
ld1sb {z0.h}, p0/z, [sp,x0]
LD1SB {Z0.H}, P0/Z, [SP,X0]
ld1sb {z0.h}, p0/z, [sp,x0,lsl #0]
ld1sb {z0.h}, p0/z, [x0,x4]
LD1SB {Z0.H}, P0/Z, [X0,X4]
ld1sb {z0.h}, p0/z, [x0,x4,lsl #0]
ld1sb {z0.h}, p0/z, [x0,x30]
LD1SB {Z0.H}, P0/Z, [X0,X30]
ld1sb {z0.h}, p0/z, [x0,x30,lsl #0]
ld1sb z0.d, p0/z, [x0,z0.d,uxtw]
ld1sb {z0.d}, p0/z, [x0,z0.d,uxtw]
LD1SB {Z0.D}, P0/Z, [X0,Z0.D,UXTW]
ld1sb {z0.d}, p0/z, [x0,z0.d,uxtw #0]
ld1sb z1.d, p0/z, [x0,z0.d,uxtw]
ld1sb {z1.d}, p0/z, [x0,z0.d,uxtw]
LD1SB {Z1.D}, P0/Z, [X0,Z0.D,UXTW]
ld1sb {z1.d}, p0/z, [x0,z0.d,uxtw #0]
ld1sb z31.d, p0/z, [x0,z0.d,uxtw]
ld1sb {z31.d}, p0/z, [x0,z0.d,uxtw]
LD1SB {Z31.D}, P0/Z, [X0,Z0.D,UXTW]
ld1sb {z31.d}, p0/z, [x0,z0.d,uxtw #0]
ld1sb {z0.d}, p2/z, [x0,z0.d,uxtw]
LD1SB {Z0.D}, P2/Z, [X0,Z0.D,UXTW]
ld1sb {z0.d}, p2/z, [x0,z0.d,uxtw #0]
ld1sb {z0.d}, p7/z, [x0,z0.d,uxtw]
LD1SB {Z0.D}, P7/Z, [X0,Z0.D,UXTW]
ld1sb {z0.d}, p7/z, [x0,z0.d,uxtw #0]
ld1sb {z0.d}, p0/z, [x3,z0.d,uxtw]
LD1SB {Z0.D}, P0/Z, [X3,Z0.D,UXTW]
ld1sb {z0.d}, p0/z, [x3,z0.d,uxtw #0]
ld1sb {z0.d}, p0/z, [sp,z0.d,uxtw]
LD1SB {Z0.D}, P0/Z, [SP,Z0.D,UXTW]
ld1sb {z0.d}, p0/z, [sp,z0.d,uxtw #0]
ld1sb {z0.d}, p0/z, [x0,z4.d,uxtw]
LD1SB {Z0.D}, P0/Z, [X0,Z4.D,UXTW]
ld1sb {z0.d}, p0/z, [x0,z4.d,uxtw #0]
ld1sb {z0.d}, p0/z, [x0,z31.d,uxtw]
LD1SB {Z0.D}, P0/Z, [X0,Z31.D,UXTW]
ld1sb {z0.d}, p0/z, [x0,z31.d,uxtw #0]
ld1sb z0.d, p0/z, [x0,z0.d,sxtw]
ld1sb {z0.d}, p0/z, [x0,z0.d,sxtw]
LD1SB {Z0.D}, P0/Z, [X0,Z0.D,SXTW]
ld1sb {z0.d}, p0/z, [x0,z0.d,sxtw #0]
ld1sb z1.d, p0/z, [x0,z0.d,sxtw]
ld1sb {z1.d}, p0/z, [x0,z0.d,sxtw]
LD1SB {Z1.D}, P0/Z, [X0,Z0.D,SXTW]
ld1sb {z1.d}, p0/z, [x0,z0.d,sxtw #0]
ld1sb z31.d, p0/z, [x0,z0.d,sxtw]
ld1sb {z31.d}, p0/z, [x0,z0.d,sxtw]
LD1SB {Z31.D}, P0/Z, [X0,Z0.D,SXTW]
ld1sb {z31.d}, p0/z, [x0,z0.d,sxtw #0]
ld1sb {z0.d}, p2/z, [x0,z0.d,sxtw]
LD1SB {Z0.D}, P2/Z, [X0,Z0.D,SXTW]
ld1sb {z0.d}, p2/z, [x0,z0.d,sxtw #0]
ld1sb {z0.d}, p7/z, [x0,z0.d,sxtw]
LD1SB {Z0.D}, P7/Z, [X0,Z0.D,SXTW]
ld1sb {z0.d}, p7/z, [x0,z0.d,sxtw #0]
ld1sb {z0.d}, p0/z, [x3,z0.d,sxtw]
LD1SB {Z0.D}, P0/Z, [X3,Z0.D,SXTW]
ld1sb {z0.d}, p0/z, [x3,z0.d,sxtw #0]
ld1sb {z0.d}, p0/z, [sp,z0.d,sxtw]
LD1SB {Z0.D}, P0/Z, [SP,Z0.D,SXTW]
ld1sb {z0.d}, p0/z, [sp,z0.d,sxtw #0]
ld1sb {z0.d}, p0/z, [x0,z4.d,sxtw]
LD1SB {Z0.D}, P0/Z, [X0,Z4.D,SXTW]
ld1sb {z0.d}, p0/z, [x0,z4.d,sxtw #0]
ld1sb {z0.d}, p0/z, [x0,z31.d,sxtw]
LD1SB {Z0.D}, P0/Z, [X0,Z31.D,SXTW]
ld1sb {z0.d}, p0/z, [x0,z31.d,sxtw #0]
ld1sb z0.d, p0/z, [x0,z0.d]
ld1sb {z0.d}, p0/z, [x0,z0.d]
LD1SB {Z0.D}, P0/Z, [X0,Z0.D]
ld1sb {z0.d}, p0/z, [x0,z0.d,lsl #0]
ld1sb z1.d, p0/z, [x0,z0.d]
ld1sb {z1.d}, p0/z, [x0,z0.d]
LD1SB {Z1.D}, P0/Z, [X0,Z0.D]
ld1sb {z1.d}, p0/z, [x0,z0.d,lsl #0]
ld1sb z31.d, p0/z, [x0,z0.d]
ld1sb {z31.d}, p0/z, [x0,z0.d]
LD1SB {Z31.D}, P0/Z, [X0,Z0.D]
ld1sb {z31.d}, p0/z, [x0,z0.d,lsl #0]
ld1sb {z0.d}, p2/z, [x0,z0.d]
LD1SB {Z0.D}, P2/Z, [X0,Z0.D]
ld1sb {z0.d}, p2/z, [x0,z0.d,lsl #0]
ld1sb {z0.d}, p7/z, [x0,z0.d]
LD1SB {Z0.D}, P7/Z, [X0,Z0.D]
ld1sb {z0.d}, p7/z, [x0,z0.d,lsl #0]
ld1sb {z0.d}, p0/z, [x3,z0.d]
LD1SB {Z0.D}, P0/Z, [X3,Z0.D]
ld1sb {z0.d}, p0/z, [x3,z0.d,lsl #0]
ld1sb {z0.d}, p0/z, [sp,z0.d]
LD1SB {Z0.D}, P0/Z, [SP,Z0.D]
ld1sb {z0.d}, p0/z, [sp,z0.d,lsl #0]
ld1sb {z0.d}, p0/z, [x0,z4.d]
LD1SB {Z0.D}, P0/Z, [X0,Z4.D]
ld1sb {z0.d}, p0/z, [x0,z4.d,lsl #0]
ld1sb {z0.d}, p0/z, [x0,z31.d]
LD1SB {Z0.D}, P0/Z, [X0,Z31.D]
ld1sb {z0.d}, p0/z, [x0,z31.d,lsl #0]
ld1sb z0.s, p0/z, [z0.s,#0]
ld1sb {z0.s}, p0/z, [z0.s,#0]
LD1SB {Z0.S}, P0/Z, [Z0.S,#0]
ld1sb {z0.s}, p0/z, [z0.s]
ld1sb z1.s, p0/z, [z0.s,#0]
ld1sb {z1.s}, p0/z, [z0.s,#0]
LD1SB {Z1.S}, P0/Z, [Z0.S,#0]
ld1sb {z1.s}, p0/z, [z0.s]
ld1sb z31.s, p0/z, [z0.s,#0]
ld1sb {z31.s}, p0/z, [z0.s,#0]
LD1SB {Z31.S}, P0/Z, [Z0.S,#0]
ld1sb {z31.s}, p0/z, [z0.s]
ld1sb {z0.s}, p2/z, [z0.s,#0]
LD1SB {Z0.S}, P2/Z, [Z0.S,#0]
ld1sb {z0.s}, p2/z, [z0.s]
ld1sb {z0.s}, p7/z, [z0.s,#0]
LD1SB {Z0.S}, P7/Z, [Z0.S,#0]
ld1sb {z0.s}, p7/z, [z0.s]
ld1sb {z0.s}, p0/z, [z3.s,#0]
LD1SB {Z0.S}, P0/Z, [Z3.S,#0]
ld1sb {z0.s}, p0/z, [z3.s]
ld1sb {z0.s}, p0/z, [z31.s,#0]
LD1SB {Z0.S}, P0/Z, [Z31.S,#0]
ld1sb {z0.s}, p0/z, [z31.s]
ld1sb {z0.s}, p0/z, [z0.s,#15]
LD1SB {Z0.S}, P0/Z, [Z0.S,#15]
ld1sb {z0.s}, p0/z, [z0.s,#16]
LD1SB {Z0.S}, P0/Z, [Z0.S,#16]
ld1sb {z0.s}, p0/z, [z0.s,#17]
LD1SB {Z0.S}, P0/Z, [Z0.S,#17]
ld1sb {z0.s}, p0/z, [z0.s,#31]
LD1SB {Z0.S}, P0/Z, [Z0.S,#31]
ld1sb z0.d, p0/z, [x0,#0]
ld1sb {z0.d}, p0/z, [x0,#0]
LD1SB {Z0.D}, P0/Z, [X0,#0]
ld1sb {z0.d}, p0/z, [x0,#0,mul vl]
ld1sb {z0.d}, p0/z, [x0]
ld1sb z1.d, p0/z, [x0,#0]
ld1sb {z1.d}, p0/z, [x0,#0]
LD1SB {Z1.D}, P0/Z, [X0,#0]
ld1sb {z1.d}, p0/z, [x0,#0,mul vl]
ld1sb {z1.d}, p0/z, [x0]
ld1sb z31.d, p0/z, [x0,#0]
ld1sb {z31.d}, p0/z, [x0,#0]
LD1SB {Z31.D}, P0/Z, [X0,#0]
ld1sb {z31.d}, p0/z, [x0,#0,mul vl]
ld1sb {z31.d}, p0/z, [x0]
ld1sb {z0.d}, p2/z, [x0,#0]
LD1SB {Z0.D}, P2/Z, [X0,#0]
ld1sb {z0.d}, p2/z, [x0,#0,mul vl]
ld1sb {z0.d}, p2/z, [x0]
ld1sb {z0.d}, p7/z, [x0,#0]
LD1SB {Z0.D}, P7/Z, [X0,#0]
ld1sb {z0.d}, p7/z, [x0,#0,mul vl]
ld1sb {z0.d}, p7/z, [x0]
ld1sb {z0.d}, p0/z, [x3,#0]
LD1SB {Z0.D}, P0/Z, [X3,#0]
ld1sb {z0.d}, p0/z, [x3,#0,mul vl]
ld1sb {z0.d}, p0/z, [x3]
ld1sb {z0.d}, p0/z, [sp,#0]
LD1SB {Z0.D}, P0/Z, [SP,#0]
ld1sb {z0.d}, p0/z, [sp,#0,mul vl]
ld1sb {z0.d}, p0/z, [sp]
ld1sb {z0.d}, p0/z, [x0,#7,mul vl]
LD1SB {Z0.D}, P0/Z, [X0,#7,MUL VL]
ld1sb {z0.d}, p0/z, [x0,#-8,mul vl]
LD1SB {Z0.D}, P0/Z, [X0,#-8,MUL VL]
ld1sb {z0.d}, p0/z, [x0,#-7,mul vl]
LD1SB {Z0.D}, P0/Z, [X0,#-7,MUL VL]
ld1sb {z0.d}, p0/z, [x0,#-1,mul vl]
LD1SB {Z0.D}, P0/Z, [X0,#-1,MUL VL]
ld1sb z0.s, p0/z, [x0,#0]
ld1sb {z0.s}, p0/z, [x0,#0]
LD1SB {Z0.S}, P0/Z, [X0,#0]
ld1sb {z0.s}, p0/z, [x0,#0,mul vl]
ld1sb {z0.s}, p0/z, [x0]
ld1sb z1.s, p0/z, [x0,#0]
ld1sb {z1.s}, p0/z, [x0,#0]
LD1SB {Z1.S}, P0/Z, [X0,#0]
ld1sb {z1.s}, p0/z, [x0,#0,mul vl]
ld1sb {z1.s}, p0/z, [x0]
ld1sb z31.s, p0/z, [x0,#0]
ld1sb {z31.s}, p0/z, [x0,#0]
LD1SB {Z31.S}, P0/Z, [X0,#0]
ld1sb {z31.s}, p0/z, [x0,#0,mul vl]
ld1sb {z31.s}, p0/z, [x0]
ld1sb {z0.s}, p2/z, [x0,#0]
LD1SB {Z0.S}, P2/Z, [X0,#0]
ld1sb {z0.s}, p2/z, [x0,#0,mul vl]
ld1sb {z0.s}, p2/z, [x0]
ld1sb {z0.s}, p7/z, [x0,#0]
LD1SB {Z0.S}, P7/Z, [X0,#0]
ld1sb {z0.s}, p7/z, [x0,#0,mul vl]
ld1sb {z0.s}, p7/z, [x0]
ld1sb {z0.s}, p0/z, [x3,#0]
LD1SB {Z0.S}, P0/Z, [X3,#0]
ld1sb {z0.s}, p0/z, [x3,#0,mul vl]
ld1sb {z0.s}, p0/z, [x3]
ld1sb {z0.s}, p0/z, [sp,#0]
LD1SB {Z0.S}, P0/Z, [SP,#0]
ld1sb {z0.s}, p0/z, [sp,#0,mul vl]
ld1sb {z0.s}, p0/z, [sp]
ld1sb {z0.s}, p0/z, [x0,#7,mul vl]
LD1SB {Z0.S}, P0/Z, [X0,#7,MUL VL]
ld1sb {z0.s}, p0/z, [x0,#-8,mul vl]
LD1SB {Z0.S}, P0/Z, [X0,#-8,MUL VL]
ld1sb {z0.s}, p0/z, [x0,#-7,mul vl]
LD1SB {Z0.S}, P0/Z, [X0,#-7,MUL VL]
ld1sb {z0.s}, p0/z, [x0,#-1,mul vl]
LD1SB {Z0.S}, P0/Z, [X0,#-1,MUL VL]
ld1sb z0.h, p0/z, [x0,#0]
ld1sb {z0.h}, p0/z, [x0,#0]
LD1SB {Z0.H}, P0/Z, [X0,#0]
ld1sb {z0.h}, p0/z, [x0,#0,mul vl]
ld1sb {z0.h}, p0/z, [x0]
ld1sb z1.h, p0/z, [x0,#0]
ld1sb {z1.h}, p0/z, [x0,#0]
LD1SB {Z1.H}, P0/Z, [X0,#0]
ld1sb {z1.h}, p0/z, [x0,#0,mul vl]
ld1sb {z1.h}, p0/z, [x0]
ld1sb z31.h, p0/z, [x0,#0]
ld1sb {z31.h}, p0/z, [x0,#0]
LD1SB {Z31.H}, P0/Z, [X0,#0]
ld1sb {z31.h}, p0/z, [x0,#0,mul vl]
ld1sb {z31.h}, p0/z, [x0]
ld1sb {z0.h}, p2/z, [x0,#0]
LD1SB {Z0.H}, P2/Z, [X0,#0]
ld1sb {z0.h}, p2/z, [x0,#0,mul vl]
ld1sb {z0.h}, p2/z, [x0]
ld1sb {z0.h}, p7/z, [x0,#0]
LD1SB {Z0.H}, P7/Z, [X0,#0]
ld1sb {z0.h}, p7/z, [x0,#0,mul vl]
ld1sb {z0.h}, p7/z, [x0]
ld1sb {z0.h}, p0/z, [x3,#0]
LD1SB {Z0.H}, P0/Z, [X3,#0]
ld1sb {z0.h}, p0/z, [x3,#0,mul vl]
ld1sb {z0.h}, p0/z, [x3]
ld1sb {z0.h}, p0/z, [sp,#0]
LD1SB {Z0.H}, P0/Z, [SP,#0]
ld1sb {z0.h}, p0/z, [sp,#0,mul vl]
ld1sb {z0.h}, p0/z, [sp]
ld1sb {z0.h}, p0/z, [x0,#7,mul vl]
LD1SB {Z0.H}, P0/Z, [X0,#7,MUL VL]
ld1sb {z0.h}, p0/z, [x0,#-8,mul vl]
LD1SB {Z0.H}, P0/Z, [X0,#-8,MUL VL]
ld1sb {z0.h}, p0/z, [x0,#-7,mul vl]
LD1SB {Z0.H}, P0/Z, [X0,#-7,MUL VL]
ld1sb {z0.h}, p0/z, [x0,#-1,mul vl]
LD1SB {Z0.H}, P0/Z, [X0,#-1,MUL VL]
ld1sb z0.d, p0/z, [z0.d,#0]
ld1sb {z0.d}, p0/z, [z0.d,#0]
LD1SB {Z0.D}, P0/Z, [Z0.D,#0]
ld1sb {z0.d}, p0/z, [z0.d]
ld1sb z1.d, p0/z, [z0.d,#0]
ld1sb {z1.d}, p0/z, [z0.d,#0]
LD1SB {Z1.D}, P0/Z, [Z0.D,#0]
ld1sb {z1.d}, p0/z, [z0.d]
ld1sb z31.d, p0/z, [z0.d,#0]
ld1sb {z31.d}, p0/z, [z0.d,#0]
LD1SB {Z31.D}, P0/Z, [Z0.D,#0]
ld1sb {z31.d}, p0/z, [z0.d]
ld1sb {z0.d}, p2/z, [z0.d,#0]
LD1SB {Z0.D}, P2/Z, [Z0.D,#0]
ld1sb {z0.d}, p2/z, [z0.d]
ld1sb {z0.d}, p7/z, [z0.d,#0]
LD1SB {Z0.D}, P7/Z, [Z0.D,#0]
ld1sb {z0.d}, p7/z, [z0.d]
ld1sb {z0.d}, p0/z, [z3.d,#0]
LD1SB {Z0.D}, P0/Z, [Z3.D,#0]
ld1sb {z0.d}, p0/z, [z3.d]
ld1sb {z0.d}, p0/z, [z31.d,#0]
LD1SB {Z0.D}, P0/Z, [Z31.D,#0]
ld1sb {z0.d}, p0/z, [z31.d]
ld1sb {z0.d}, p0/z, [z0.d,#15]
LD1SB {Z0.D}, P0/Z, [Z0.D,#15]
ld1sb {z0.d}, p0/z, [z0.d,#16]
LD1SB {Z0.D}, P0/Z, [Z0.D,#16]
ld1sb {z0.d}, p0/z, [z0.d,#17]
LD1SB {Z0.D}, P0/Z, [Z0.D,#17]
ld1sb {z0.d}, p0/z, [z0.d,#31]
LD1SB {Z0.D}, P0/Z, [Z0.D,#31]
ld1sh z0.s, p0/z, [x0,z0.s,uxtw]
ld1sh {z0.s}, p0/z, [x0,z0.s,uxtw]
LD1SH {Z0.S}, P0/Z, [X0,Z0.S,UXTW]
ld1sh {z0.s}, p0/z, [x0,z0.s,uxtw #0]
ld1sh z1.s, p0/z, [x0,z0.s,uxtw]
ld1sh {z1.s}, p0/z, [x0,z0.s,uxtw]
LD1SH {Z1.S}, P0/Z, [X0,Z0.S,UXTW]
ld1sh {z1.s}, p0/z, [x0,z0.s,uxtw #0]
ld1sh z31.s, p0/z, [x0,z0.s,uxtw]
ld1sh {z31.s}, p0/z, [x0,z0.s,uxtw]
LD1SH {Z31.S}, P0/Z, [X0,Z0.S,UXTW]
ld1sh {z31.s}, p0/z, [x0,z0.s,uxtw #0]
ld1sh {z0.s}, p2/z, [x0,z0.s,uxtw]
LD1SH {Z0.S}, P2/Z, [X0,Z0.S,UXTW]
ld1sh {z0.s}, p2/z, [x0,z0.s,uxtw #0]
ld1sh {z0.s}, p7/z, [x0,z0.s,uxtw]
LD1SH {Z0.S}, P7/Z, [X0,Z0.S,UXTW]
ld1sh {z0.s}, p7/z, [x0,z0.s,uxtw #0]
ld1sh {z0.s}, p0/z, [x3,z0.s,uxtw]
LD1SH {Z0.S}, P0/Z, [X3,Z0.S,UXTW]
ld1sh {z0.s}, p0/z, [x3,z0.s,uxtw #0]
ld1sh {z0.s}, p0/z, [sp,z0.s,uxtw]
LD1SH {Z0.S}, P0/Z, [SP,Z0.S,UXTW]
ld1sh {z0.s}, p0/z, [sp,z0.s,uxtw #0]
ld1sh {z0.s}, p0/z, [x0,z4.s,uxtw]
LD1SH {Z0.S}, P0/Z, [X0,Z4.S,UXTW]
ld1sh {z0.s}, p0/z, [x0,z4.s,uxtw #0]
ld1sh {z0.s}, p0/z, [x0,z31.s,uxtw]
LD1SH {Z0.S}, P0/Z, [X0,Z31.S,UXTW]
ld1sh {z0.s}, p0/z, [x0,z31.s,uxtw #0]
ld1sh z0.s, p0/z, [x0,z0.s,sxtw]
ld1sh {z0.s}, p0/z, [x0,z0.s,sxtw]
LD1SH {Z0.S}, P0/Z, [X0,Z0.S,SXTW]
ld1sh {z0.s}, p0/z, [x0,z0.s,sxtw #0]
ld1sh z1.s, p0/z, [x0,z0.s,sxtw]
ld1sh {z1.s}, p0/z, [x0,z0.s,sxtw]
LD1SH {Z1.S}, P0/Z, [X0,Z0.S,SXTW]
ld1sh {z1.s}, p0/z, [x0,z0.s,sxtw #0]
ld1sh z31.s, p0/z, [x0,z0.s,sxtw]
ld1sh {z31.s}, p0/z, [x0,z0.s,sxtw]
LD1SH {Z31.S}, P0/Z, [X0,Z0.S,SXTW]
ld1sh {z31.s}, p0/z, [x0,z0.s,sxtw #0]
ld1sh {z0.s}, p2/z, [x0,z0.s,sxtw]
LD1SH {Z0.S}, P2/Z, [X0,Z0.S,SXTW]
ld1sh {z0.s}, p2/z, [x0,z0.s,sxtw #0]
ld1sh {z0.s}, p7/z, [x0,z0.s,sxtw]
LD1SH {Z0.S}, P7/Z, [X0,Z0.S,SXTW]
ld1sh {z0.s}, p7/z, [x0,z0.s,sxtw #0]
ld1sh {z0.s}, p0/z, [x3,z0.s,sxtw]
LD1SH {Z0.S}, P0/Z, [X3,Z0.S,SXTW]
ld1sh {z0.s}, p0/z, [x3,z0.s,sxtw #0]
ld1sh {z0.s}, p0/z, [sp,z0.s,sxtw]
LD1SH {Z0.S}, P0/Z, [SP,Z0.S,SXTW]
ld1sh {z0.s}, p0/z, [sp,z0.s,sxtw #0]
ld1sh {z0.s}, p0/z, [x0,z4.s,sxtw]
LD1SH {Z0.S}, P0/Z, [X0,Z4.S,SXTW]
ld1sh {z0.s}, p0/z, [x0,z4.s,sxtw #0]
ld1sh {z0.s}, p0/z, [x0,z31.s,sxtw]
LD1SH {Z0.S}, P0/Z, [X0,Z31.S,SXTW]
ld1sh {z0.s}, p0/z, [x0,z31.s,sxtw #0]
ld1sh z0.s, p0/z, [x0,z0.s,uxtw #1]
ld1sh {z0.s}, p0/z, [x0,z0.s,uxtw #1]
LD1SH {Z0.S}, P0/Z, [X0,Z0.S,UXTW #1]
ld1sh z1.s, p0/z, [x0,z0.s,uxtw #1]
ld1sh {z1.s}, p0/z, [x0,z0.s,uxtw #1]
LD1SH {Z1.S}, P0/Z, [X0,Z0.S,UXTW #1]
ld1sh z31.s, p0/z, [x0,z0.s,uxtw #1]
ld1sh {z31.s}, p0/z, [x0,z0.s,uxtw #1]
LD1SH {Z31.S}, P0/Z, [X0,Z0.S,UXTW #1]
ld1sh {z0.s}, p2/z, [x0,z0.s,uxtw #1]
LD1SH {Z0.S}, P2/Z, [X0,Z0.S,UXTW #1]
ld1sh {z0.s}, p7/z, [x0,z0.s,uxtw #1]
LD1SH {Z0.S}, P7/Z, [X0,Z0.S,UXTW #1]
ld1sh {z0.s}, p0/z, [x3,z0.s,uxtw #1]
LD1SH {Z0.S}, P0/Z, [X3,Z0.S,UXTW #1]
ld1sh {z0.s}, p0/z, [sp,z0.s,uxtw #1]
LD1SH {Z0.S}, P0/Z, [SP,Z0.S,UXTW #1]
ld1sh {z0.s}, p0/z, [x0,z4.s,uxtw #1]
LD1SH {Z0.S}, P0/Z, [X0,Z4.S,UXTW #1]
ld1sh {z0.s}, p0/z, [x0,z31.s,uxtw #1]
LD1SH {Z0.S}, P0/Z, [X0,Z31.S,UXTW #1]
ld1sh z0.s, p0/z, [x0,z0.s,sxtw #1]
ld1sh {z0.s}, p0/z, [x0,z0.s,sxtw #1]
LD1SH {Z0.S}, P0/Z, [X0,Z0.S,SXTW #1]
ld1sh z1.s, p0/z, [x0,z0.s,sxtw #1]
ld1sh {z1.s}, p0/z, [x0,z0.s,sxtw #1]
LD1SH {Z1.S}, P0/Z, [X0,Z0.S,SXTW #1]
ld1sh z31.s, p0/z, [x0,z0.s,sxtw #1]
ld1sh {z31.s}, p0/z, [x0,z0.s,sxtw #1]
LD1SH {Z31.S}, P0/Z, [X0,Z0.S,SXTW #1]
ld1sh {z0.s}, p2/z, [x0,z0.s,sxtw #1]
LD1SH {Z0.S}, P2/Z, [X0,Z0.S,SXTW #1]
ld1sh {z0.s}, p7/z, [x0,z0.s,sxtw #1]
LD1SH {Z0.S}, P7/Z, [X0,Z0.S,SXTW #1]
ld1sh {z0.s}, p0/z, [x3,z0.s,sxtw #1]
LD1SH {Z0.S}, P0/Z, [X3,Z0.S,SXTW #1]
ld1sh {z0.s}, p0/z, [sp,z0.s,sxtw #1]
LD1SH {Z0.S}, P0/Z, [SP,Z0.S,SXTW #1]
ld1sh {z0.s}, p0/z, [x0,z4.s,sxtw #1]
LD1SH {Z0.S}, P0/Z, [X0,Z4.S,SXTW #1]
ld1sh {z0.s}, p0/z, [x0,z31.s,sxtw #1]
LD1SH {Z0.S}, P0/Z, [X0,Z31.S,SXTW #1]
ld1sh z0.d, p0/z, [x0,x0,lsl #1]
ld1sh {z0.d}, p0/z, [x0,x0,lsl #1]
LD1SH {Z0.D}, P0/Z, [X0,X0,LSL #1]
ld1sh z1.d, p0/z, [x0,x0,lsl #1]
ld1sh {z1.d}, p0/z, [x0,x0,lsl #1]
LD1SH {Z1.D}, P0/Z, [X0,X0,LSL #1]
ld1sh z31.d, p0/z, [x0,x0,lsl #1]
ld1sh {z31.d}, p0/z, [x0,x0,lsl #1]
LD1SH {Z31.D}, P0/Z, [X0,X0,LSL #1]
ld1sh {z0.d}, p2/z, [x0,x0,lsl #1]
LD1SH {Z0.D}, P2/Z, [X0,X0,LSL #1]
ld1sh {z0.d}, p7/z, [x0,x0,lsl #1]
LD1SH {Z0.D}, P7/Z, [X0,X0,LSL #1]
ld1sh {z0.d}, p0/z, [x3,x0,lsl #1]
LD1SH {Z0.D}, P0/Z, [X3,X0,LSL #1]
ld1sh {z0.d}, p0/z, [sp,x0,lsl #1]
LD1SH {Z0.D}, P0/Z, [SP,X0,LSL #1]
ld1sh {z0.d}, p0/z, [x0,x4,lsl #1]
LD1SH {Z0.D}, P0/Z, [X0,X4,LSL #1]
ld1sh {z0.d}, p0/z, [x0,x30,lsl #1]
LD1SH {Z0.D}, P0/Z, [X0,X30,LSL #1]
ld1sh z0.s, p0/z, [x0,x0,lsl #1]
ld1sh {z0.s}, p0/z, [x0,x0,lsl #1]
LD1SH {Z0.S}, P0/Z, [X0,X0,LSL #1]
ld1sh z1.s, p0/z, [x0,x0,lsl #1]
ld1sh {z1.s}, p0/z, [x0,x0,lsl #1]
LD1SH {Z1.S}, P0/Z, [X0,X0,LSL #1]
ld1sh z31.s, p0/z, [x0,x0,lsl #1]
ld1sh {z31.s}, p0/z, [x0,x0,lsl #1]
LD1SH {Z31.S}, P0/Z, [X0,X0,LSL #1]
ld1sh {z0.s}, p2/z, [x0,x0,lsl #1]
LD1SH {Z0.S}, P2/Z, [X0,X0,LSL #1]
ld1sh {z0.s}, p7/z, [x0,x0,lsl #1]
LD1SH {Z0.S}, P7/Z, [X0,X0,LSL #1]
ld1sh {z0.s}, p0/z, [x3,x0,lsl #1]
LD1SH {Z0.S}, P0/Z, [X3,X0,LSL #1]
ld1sh {z0.s}, p0/z, [sp,x0,lsl #1]
LD1SH {Z0.S}, P0/Z, [SP,X0,LSL #1]
ld1sh {z0.s}, p0/z, [x0,x4,lsl #1]
LD1SH {Z0.S}, P0/Z, [X0,X4,LSL #1]
ld1sh {z0.s}, p0/z, [x0,x30,lsl #1]
LD1SH {Z0.S}, P0/Z, [X0,X30,LSL #1]
ld1sh z0.d, p0/z, [x0,z0.d,uxtw]
ld1sh {z0.d}, p0/z, [x0,z0.d,uxtw]
LD1SH {Z0.D}, P0/Z, [X0,Z0.D,UXTW]
ld1sh {z0.d}, p0/z, [x0,z0.d,uxtw #0]
ld1sh z1.d, p0/z, [x0,z0.d,uxtw]
ld1sh {z1.d}, p0/z, [x0,z0.d,uxtw]
LD1SH {Z1.D}, P0/Z, [X0,Z0.D,UXTW]
ld1sh {z1.d}, p0/z, [x0,z0.d,uxtw #0]
ld1sh z31.d, p0/z, [x0,z0.d,uxtw]
ld1sh {z31.d}, p0/z, [x0,z0.d,uxtw]
LD1SH {Z31.D}, P0/Z, [X0,Z0.D,UXTW]
ld1sh {z31.d}, p0/z, [x0,z0.d,uxtw #0]
ld1sh {z0.d}, p2/z, [x0,z0.d,uxtw]
LD1SH {Z0.D}, P2/Z, [X0,Z0.D,UXTW]
ld1sh {z0.d}, p2/z, [x0,z0.d,uxtw #0]
ld1sh {z0.d}, p7/z, [x0,z0.d,uxtw]
LD1SH {Z0.D}, P7/Z, [X0,Z0.D,UXTW]
ld1sh {z0.d}, p7/z, [x0,z0.d,uxtw #0]
ld1sh {z0.d}, p0/z, [x3,z0.d,uxtw]
LD1SH {Z0.D}, P0/Z, [X3,Z0.D,UXTW]
ld1sh {z0.d}, p0/z, [x3,z0.d,uxtw #0]
ld1sh {z0.d}, p0/z, [sp,z0.d,uxtw]
LD1SH {Z0.D}, P0/Z, [SP,Z0.D,UXTW]
ld1sh {z0.d}, p0/z, [sp,z0.d,uxtw #0]
ld1sh {z0.d}, p0/z, [x0,z4.d,uxtw]
LD1SH {Z0.D}, P0/Z, [X0,Z4.D,UXTW]
ld1sh {z0.d}, p0/z, [x0,z4.d,uxtw #0]
ld1sh {z0.d}, p0/z, [x0,z31.d,uxtw]
LD1SH {Z0.D}, P0/Z, [X0,Z31.D,UXTW]
ld1sh {z0.d}, p0/z, [x0,z31.d,uxtw #0]
ld1sh z0.d, p0/z, [x0,z0.d,sxtw]
ld1sh {z0.d}, p0/z, [x0,z0.d,sxtw]
LD1SH {Z0.D}, P0/Z, [X0,Z0.D,SXTW]
ld1sh {z0.d}, p0/z, [x0,z0.d,sxtw #0]
ld1sh z1.d, p0/z, [x0,z0.d,sxtw]
ld1sh {z1.d}, p0/z, [x0,z0.d,sxtw]
LD1SH {Z1.D}, P0/Z, [X0,Z0.D,SXTW]
ld1sh {z1.d}, p0/z, [x0,z0.d,sxtw #0]
ld1sh z31.d, p0/z, [x0,z0.d,sxtw]
ld1sh {z31.d}, p0/z, [x0,z0.d,sxtw]
LD1SH {Z31.D}, P0/Z, [X0,Z0.D,SXTW]
ld1sh {z31.d}, p0/z, [x0,z0.d,sxtw #0]
ld1sh {z0.d}, p2/z, [x0,z0.d,sxtw]
LD1SH {Z0.D}, P2/Z, [X0,Z0.D,SXTW]
ld1sh {z0.d}, p2/z, [x0,z0.d,sxtw #0]
ld1sh {z0.d}, p7/z, [x0,z0.d,sxtw]
LD1SH {Z0.D}, P7/Z, [X0,Z0.D,SXTW]
ld1sh {z0.d}, p7/z, [x0,z0.d,sxtw #0]
ld1sh {z0.d}, p0/z, [x3,z0.d,sxtw]
LD1SH {Z0.D}, P0/Z, [X3,Z0.D,SXTW]
ld1sh {z0.d}, p0/z, [x3,z0.d,sxtw #0]
ld1sh {z0.d}, p0/z, [sp,z0.d,sxtw]
LD1SH {Z0.D}, P0/Z, [SP,Z0.D,SXTW]
ld1sh {z0.d}, p0/z, [sp,z0.d,sxtw #0]
ld1sh {z0.d}, p0/z, [x0,z4.d,sxtw]
LD1SH {Z0.D}, P0/Z, [X0,Z4.D,SXTW]
ld1sh {z0.d}, p0/z, [x0,z4.d,sxtw #0]
ld1sh {z0.d}, p0/z, [x0,z31.d,sxtw]
LD1SH {Z0.D}, P0/Z, [X0,Z31.D,SXTW]
ld1sh {z0.d}, p0/z, [x0,z31.d,sxtw #0]
ld1sh z0.d, p0/z, [x0,z0.d,uxtw #1]
ld1sh {z0.d}, p0/z, [x0,z0.d,uxtw #1]
LD1SH {Z0.D}, P0/Z, [X0,Z0.D,UXTW #1]
ld1sh z1.d, p0/z, [x0,z0.d,uxtw #1]
ld1sh {z1.d}, p0/z, [x0,z0.d,uxtw #1]
LD1SH {Z1.D}, P0/Z, [X0,Z0.D,UXTW #1]
ld1sh z31.d, p0/z, [x0,z0.d,uxtw #1]
ld1sh {z31.d}, p0/z, [x0,z0.d,uxtw #1]
LD1SH {Z31.D}, P0/Z, [X0,Z0.D,UXTW #1]
ld1sh {z0.d}, p2/z, [x0,z0.d,uxtw #1]
LD1SH {Z0.D}, P2/Z, [X0,Z0.D,UXTW #1]
ld1sh {z0.d}, p7/z, [x0,z0.d,uxtw #1]
LD1SH {Z0.D}, P7/Z, [X0,Z0.D,UXTW #1]
ld1sh {z0.d}, p0/z, [x3,z0.d,uxtw #1]
LD1SH {Z0.D}, P0/Z, [X3,Z0.D,UXTW #1]
ld1sh {z0.d}, p0/z, [sp,z0.d,uxtw #1]
LD1SH {Z0.D}, P0/Z, [SP,Z0.D,UXTW #1]
ld1sh {z0.d}, p0/z, [x0,z4.d,uxtw #1]
LD1SH {Z0.D}, P0/Z, [X0,Z4.D,UXTW #1]
ld1sh {z0.d}, p0/z, [x0,z31.d,uxtw #1]
LD1SH {Z0.D}, P0/Z, [X0,Z31.D,UXTW #1]
ld1sh z0.d, p0/z, [x0,z0.d,sxtw #1]
ld1sh {z0.d}, p0/z, [x0,z0.d,sxtw #1]
LD1SH {Z0.D}, P0/Z, [X0,Z0.D,SXTW #1]
ld1sh z1.d, p0/z, [x0,z0.d,sxtw #1]
ld1sh {z1.d}, p0/z, [x0,z0.d,sxtw #1]
LD1SH {Z1.D}, P0/Z, [X0,Z0.D,SXTW #1]
ld1sh z31.d, p0/z, [x0,z0.d,sxtw #1]
ld1sh {z31.d}, p0/z, [x0,z0.d,sxtw #1]
LD1SH {Z31.D}, P0/Z, [X0,Z0.D,SXTW #1]
ld1sh {z0.d}, p2/z, [x0,z0.d,sxtw #1]
LD1SH {Z0.D}, P2/Z, [X0,Z0.D,SXTW #1]
ld1sh {z0.d}, p7/z, [x0,z0.d,sxtw #1]
LD1SH {Z0.D}, P7/Z, [X0,Z0.D,SXTW #1]
ld1sh {z0.d}, p0/z, [x3,z0.d,sxtw #1]
LD1SH {Z0.D}, P0/Z, [X3,Z0.D,SXTW #1]
ld1sh {z0.d}, p0/z, [sp,z0.d,sxtw #1]
LD1SH {Z0.D}, P0/Z, [SP,Z0.D,SXTW #1]
ld1sh {z0.d}, p0/z, [x0,z4.d,sxtw #1]
LD1SH {Z0.D}, P0/Z, [X0,Z4.D,SXTW #1]
ld1sh {z0.d}, p0/z, [x0,z31.d,sxtw #1]
LD1SH {Z0.D}, P0/Z, [X0,Z31.D,SXTW #1]
ld1sh z0.d, p0/z, [x0,z0.d]
ld1sh {z0.d}, p0/z, [x0,z0.d]
LD1SH {Z0.D}, P0/Z, [X0,Z0.D]
ld1sh {z0.d}, p0/z, [x0,z0.d,lsl #0]
ld1sh z1.d, p0/z, [x0,z0.d]
ld1sh {z1.d}, p0/z, [x0,z0.d]
LD1SH {Z1.D}, P0/Z, [X0,Z0.D]
ld1sh {z1.d}, p0/z, [x0,z0.d,lsl #0]
ld1sh z31.d, p0/z, [x0,z0.d]
ld1sh {z31.d}, p0/z, [x0,z0.d]
LD1SH {Z31.D}, P0/Z, [X0,Z0.D]
ld1sh {z31.d}, p0/z, [x0,z0.d,lsl #0]
ld1sh {z0.d}, p2/z, [x0,z0.d]
LD1SH {Z0.D}, P2/Z, [X0,Z0.D]
ld1sh {z0.d}, p2/z, [x0,z0.d,lsl #0]
ld1sh {z0.d}, p7/z, [x0,z0.d]
LD1SH {Z0.D}, P7/Z, [X0,Z0.D]
ld1sh {z0.d}, p7/z, [x0,z0.d,lsl #0]
ld1sh {z0.d}, p0/z, [x3,z0.d]
LD1SH {Z0.D}, P0/Z, [X3,Z0.D]
ld1sh {z0.d}, p0/z, [x3,z0.d,lsl #0]
ld1sh {z0.d}, p0/z, [sp,z0.d]
LD1SH {Z0.D}, P0/Z, [SP,Z0.D]
ld1sh {z0.d}, p0/z, [sp,z0.d,lsl #0]
ld1sh {z0.d}, p0/z, [x0,z4.d]
LD1SH {Z0.D}, P0/Z, [X0,Z4.D]
ld1sh {z0.d}, p0/z, [x0,z4.d,lsl #0]
ld1sh {z0.d}, p0/z, [x0,z31.d]
LD1SH {Z0.D}, P0/Z, [X0,Z31.D]
ld1sh {z0.d}, p0/z, [x0,z31.d,lsl #0]
ld1sh z0.d, p0/z, [x0,z0.d,lsl #1]
ld1sh {z0.d}, p0/z, [x0,z0.d,lsl #1]
LD1SH {Z0.D}, P0/Z, [X0,Z0.D,LSL #1]
ld1sh z1.d, p0/z, [x0,z0.d,lsl #1]
ld1sh {z1.d}, p0/z, [x0,z0.d,lsl #1]
LD1SH {Z1.D}, P0/Z, [X0,Z0.D,LSL #1]
ld1sh z31.d, p0/z, [x0,z0.d,lsl #1]
ld1sh {z31.d}, p0/z, [x0,z0.d,lsl #1]
LD1SH {Z31.D}, P0/Z, [X0,Z0.D,LSL #1]
ld1sh {z0.d}, p2/z, [x0,z0.d,lsl #1]
LD1SH {Z0.D}, P2/Z, [X0,Z0.D,LSL #1]
ld1sh {z0.d}, p7/z, [x0,z0.d,lsl #1]
LD1SH {Z0.D}, P7/Z, [X0,Z0.D,LSL #1]
ld1sh {z0.d}, p0/z, [x3,z0.d,lsl #1]
LD1SH {Z0.D}, P0/Z, [X3,Z0.D,LSL #1]
ld1sh {z0.d}, p0/z, [sp,z0.d,lsl #1]
LD1SH {Z0.D}, P0/Z, [SP,Z0.D,LSL #1]
ld1sh {z0.d}, p0/z, [x0,z4.d,lsl #1]
LD1SH {Z0.D}, P0/Z, [X0,Z4.D,LSL #1]
ld1sh {z0.d}, p0/z, [x0,z31.d,lsl #1]
LD1SH {Z0.D}, P0/Z, [X0,Z31.D,LSL #1]
ld1sh z0.s, p0/z, [z0.s,#0]
ld1sh {z0.s}, p0/z, [z0.s,#0]
LD1SH {Z0.S}, P0/Z, [Z0.S,#0]
ld1sh {z0.s}, p0/z, [z0.s]
ld1sh z1.s, p0/z, [z0.s,#0]
ld1sh {z1.s}, p0/z, [z0.s,#0]
LD1SH {Z1.S}, P0/Z, [Z0.S,#0]
ld1sh {z1.s}, p0/z, [z0.s]
ld1sh z31.s, p0/z, [z0.s,#0]
ld1sh {z31.s}, p0/z, [z0.s,#0]
LD1SH {Z31.S}, P0/Z, [Z0.S,#0]
ld1sh {z31.s}, p0/z, [z0.s]
ld1sh {z0.s}, p2/z, [z0.s,#0]
LD1SH {Z0.S}, P2/Z, [Z0.S,#0]
ld1sh {z0.s}, p2/z, [z0.s]
ld1sh {z0.s}, p7/z, [z0.s,#0]
LD1SH {Z0.S}, P7/Z, [Z0.S,#0]
ld1sh {z0.s}, p7/z, [z0.s]
ld1sh {z0.s}, p0/z, [z3.s,#0]
LD1SH {Z0.S}, P0/Z, [Z3.S,#0]
ld1sh {z0.s}, p0/z, [z3.s]
ld1sh {z0.s}, p0/z, [z31.s,#0]
LD1SH {Z0.S}, P0/Z, [Z31.S,#0]
ld1sh {z0.s}, p0/z, [z31.s]
ld1sh {z0.s}, p0/z, [z0.s,#30]
LD1SH {Z0.S}, P0/Z, [Z0.S,#30]
ld1sh {z0.s}, p0/z, [z0.s,#32]
LD1SH {Z0.S}, P0/Z, [Z0.S,#32]
ld1sh {z0.s}, p0/z, [z0.s,#34]
LD1SH {Z0.S}, P0/Z, [Z0.S,#34]
ld1sh {z0.s}, p0/z, [z0.s,#62]
LD1SH {Z0.S}, P0/Z, [Z0.S,#62]
ld1sh z0.d, p0/z, [x0,#0]
ld1sh {z0.d}, p0/z, [x0,#0]
LD1SH {Z0.D}, P0/Z, [X0,#0]
ld1sh {z0.d}, p0/z, [x0,#0,mul vl]
ld1sh {z0.d}, p0/z, [x0]
ld1sh z1.d, p0/z, [x0,#0]
ld1sh {z1.d}, p0/z, [x0,#0]
LD1SH {Z1.D}, P0/Z, [X0,#0]
ld1sh {z1.d}, p0/z, [x0,#0,mul vl]
ld1sh {z1.d}, p0/z, [x0]
ld1sh z31.d, p0/z, [x0,#0]
ld1sh {z31.d}, p0/z, [x0,#0]
LD1SH {Z31.D}, P0/Z, [X0,#0]
ld1sh {z31.d}, p0/z, [x0,#0,mul vl]
ld1sh {z31.d}, p0/z, [x0]
ld1sh {z0.d}, p2/z, [x0,#0]
LD1SH {Z0.D}, P2/Z, [X0,#0]
ld1sh {z0.d}, p2/z, [x0,#0,mul vl]
ld1sh {z0.d}, p2/z, [x0]
ld1sh {z0.d}, p7/z, [x0,#0]
LD1SH {Z0.D}, P7/Z, [X0,#0]
ld1sh {z0.d}, p7/z, [x0,#0,mul vl]
ld1sh {z0.d}, p7/z, [x0]
ld1sh {z0.d}, p0/z, [x3,#0]
LD1SH {Z0.D}, P0/Z, [X3,#0]
ld1sh {z0.d}, p0/z, [x3,#0,mul vl]
ld1sh {z0.d}, p0/z, [x3]
ld1sh {z0.d}, p0/z, [sp,#0]
LD1SH {Z0.D}, P0/Z, [SP,#0]
ld1sh {z0.d}, p0/z, [sp,#0,mul vl]
ld1sh {z0.d}, p0/z, [sp]
ld1sh {z0.d}, p0/z, [x0,#7,mul vl]
LD1SH {Z0.D}, P0/Z, [X0,#7,MUL VL]
ld1sh {z0.d}, p0/z, [x0,#-8,mul vl]
LD1SH {Z0.D}, P0/Z, [X0,#-8,MUL VL]
ld1sh {z0.d}, p0/z, [x0,#-7,mul vl]
LD1SH {Z0.D}, P0/Z, [X0,#-7,MUL VL]
ld1sh {z0.d}, p0/z, [x0,#-1,mul vl]
LD1SH {Z0.D}, P0/Z, [X0,#-1,MUL VL]
ld1sh z0.s, p0/z, [x0,#0]
ld1sh {z0.s}, p0/z, [x0,#0]
LD1SH {Z0.S}, P0/Z, [X0,#0]
ld1sh {z0.s}, p0/z, [x0,#0,mul vl]
ld1sh {z0.s}, p0/z, [x0]
ld1sh z1.s, p0/z, [x0,#0]
ld1sh {z1.s}, p0/z, [x0,#0]
LD1SH {Z1.S}, P0/Z, [X0,#0]
ld1sh {z1.s}, p0/z, [x0,#0,mul vl]
ld1sh {z1.s}, p0/z, [x0]
ld1sh z31.s, p0/z, [x0,#0]
ld1sh {z31.s}, p0/z, [x0,#0]
LD1SH {Z31.S}, P0/Z, [X0,#0]
ld1sh {z31.s}, p0/z, [x0,#0,mul vl]
ld1sh {z31.s}, p0/z, [x0]
ld1sh {z0.s}, p2/z, [x0,#0]
LD1SH {Z0.S}, P2/Z, [X0,#0]
ld1sh {z0.s}, p2/z, [x0,#0,mul vl]
ld1sh {z0.s}, p2/z, [x0]
ld1sh {z0.s}, p7/z, [x0,#0]
LD1SH {Z0.S}, P7/Z, [X0,#0]
ld1sh {z0.s}, p7/z, [x0,#0,mul vl]
ld1sh {z0.s}, p7/z, [x0]
ld1sh {z0.s}, p0/z, [x3,#0]
LD1SH {Z0.S}, P0/Z, [X3,#0]
ld1sh {z0.s}, p0/z, [x3,#0,mul vl]
ld1sh {z0.s}, p0/z, [x3]
ld1sh {z0.s}, p0/z, [sp,#0]
LD1SH {Z0.S}, P0/Z, [SP,#0]
ld1sh {z0.s}, p0/z, [sp,#0,mul vl]
ld1sh {z0.s}, p0/z, [sp]
ld1sh {z0.s}, p0/z, [x0,#7,mul vl]
LD1SH {Z0.S}, P0/Z, [X0,#7,MUL VL]
ld1sh {z0.s}, p0/z, [x0,#-8,mul vl]
LD1SH {Z0.S}, P0/Z, [X0,#-8,MUL VL]
ld1sh {z0.s}, p0/z, [x0,#-7,mul vl]
LD1SH {Z0.S}, P0/Z, [X0,#-7,MUL VL]
ld1sh {z0.s}, p0/z, [x0,#-1,mul vl]
LD1SH {Z0.S}, P0/Z, [X0,#-1,MUL VL]
ld1sh z0.d, p0/z, [z0.d,#0]
ld1sh {z0.d}, p0/z, [z0.d,#0]
LD1SH {Z0.D}, P0/Z, [Z0.D,#0]
ld1sh {z0.d}, p0/z, [z0.d]
ld1sh z1.d, p0/z, [z0.d,#0]
ld1sh {z1.d}, p0/z, [z0.d,#0]
LD1SH {Z1.D}, P0/Z, [Z0.D,#0]
ld1sh {z1.d}, p0/z, [z0.d]
ld1sh z31.d, p0/z, [z0.d,#0]
ld1sh {z31.d}, p0/z, [z0.d,#0]
LD1SH {Z31.D}, P0/Z, [Z0.D,#0]
ld1sh {z31.d}, p0/z, [z0.d]
ld1sh {z0.d}, p2/z, [z0.d,#0]
LD1SH {Z0.D}, P2/Z, [Z0.D,#0]
ld1sh {z0.d}, p2/z, [z0.d]
ld1sh {z0.d}, p7/z, [z0.d,#0]
LD1SH {Z0.D}, P7/Z, [Z0.D,#0]
ld1sh {z0.d}, p7/z, [z0.d]
ld1sh {z0.d}, p0/z, [z3.d,#0]
LD1SH {Z0.D}, P0/Z, [Z3.D,#0]
ld1sh {z0.d}, p0/z, [z3.d]
ld1sh {z0.d}, p0/z, [z31.d,#0]
LD1SH {Z0.D}, P0/Z, [Z31.D,#0]
ld1sh {z0.d}, p0/z, [z31.d]
ld1sh {z0.d}, p0/z, [z0.d,#30]
LD1SH {Z0.D}, P0/Z, [Z0.D,#30]
ld1sh {z0.d}, p0/z, [z0.d,#32]
LD1SH {Z0.D}, P0/Z, [Z0.D,#32]
ld1sh {z0.d}, p0/z, [z0.d,#34]
LD1SH {Z0.D}, P0/Z, [Z0.D,#34]
ld1sh {z0.d}, p0/z, [z0.d,#62]
LD1SH {Z0.D}, P0/Z, [Z0.D,#62]
ld1sw z0.d, p0/z, [x0,x0,lsl #2]
ld1sw {z0.d}, p0/z, [x0,x0,lsl #2]
LD1SW {Z0.D}, P0/Z, [X0,X0,LSL #2]
ld1sw z1.d, p0/z, [x0,x0,lsl #2]
ld1sw {z1.d}, p0/z, [x0,x0,lsl #2]
LD1SW {Z1.D}, P0/Z, [X0,X0,LSL #2]
ld1sw z31.d, p0/z, [x0,x0,lsl #2]
ld1sw {z31.d}, p0/z, [x0,x0,lsl #2]
LD1SW {Z31.D}, P0/Z, [X0,X0,LSL #2]
ld1sw {z0.d}, p2/z, [x0,x0,lsl #2]
LD1SW {Z0.D}, P2/Z, [X0,X0,LSL #2]
ld1sw {z0.d}, p7/z, [x0,x0,lsl #2]
LD1SW {Z0.D}, P7/Z, [X0,X0,LSL #2]
ld1sw {z0.d}, p0/z, [x3,x0,lsl #2]
LD1SW {Z0.D}, P0/Z, [X3,X0,LSL #2]
ld1sw {z0.d}, p0/z, [sp,x0,lsl #2]
LD1SW {Z0.D}, P0/Z, [SP,X0,LSL #2]
ld1sw {z0.d}, p0/z, [x0,x4,lsl #2]
LD1SW {Z0.D}, P0/Z, [X0,X4,LSL #2]
ld1sw {z0.d}, p0/z, [x0,x30,lsl #2]
LD1SW {Z0.D}, P0/Z, [X0,X30,LSL #2]
ld1sw z0.d, p0/z, [x0,z0.d,uxtw]
ld1sw {z0.d}, p0/z, [x0,z0.d,uxtw]
LD1SW {Z0.D}, P0/Z, [X0,Z0.D,UXTW]
ld1sw {z0.d}, p0/z, [x0,z0.d,uxtw #0]
ld1sw z1.d, p0/z, [x0,z0.d,uxtw]
ld1sw {z1.d}, p0/z, [x0,z0.d,uxtw]
LD1SW {Z1.D}, P0/Z, [X0,Z0.D,UXTW]
ld1sw {z1.d}, p0/z, [x0,z0.d,uxtw #0]
ld1sw z31.d, p0/z, [x0,z0.d,uxtw]
ld1sw {z31.d}, p0/z, [x0,z0.d,uxtw]
LD1SW {Z31.D}, P0/Z, [X0,Z0.D,UXTW]
ld1sw {z31.d}, p0/z, [x0,z0.d,uxtw #0]
ld1sw {z0.d}, p2/z, [x0,z0.d,uxtw]
LD1SW {Z0.D}, P2/Z, [X0,Z0.D,UXTW]
ld1sw {z0.d}, p2/z, [x0,z0.d,uxtw #0]
ld1sw {z0.d}, p7/z, [x0,z0.d,uxtw]
LD1SW {Z0.D}, P7/Z, [X0,Z0.D,UXTW]
ld1sw {z0.d}, p7/z, [x0,z0.d,uxtw #0]
ld1sw {z0.d}, p0/z, [x3,z0.d,uxtw]
LD1SW {Z0.D}, P0/Z, [X3,Z0.D,UXTW]
ld1sw {z0.d}, p0/z, [x3,z0.d,uxtw #0]
ld1sw {z0.d}, p0/z, [sp,z0.d,uxtw]
LD1SW {Z0.D}, P0/Z, [SP,Z0.D,UXTW]
ld1sw {z0.d}, p0/z, [sp,z0.d,uxtw #0]
ld1sw {z0.d}, p0/z, [x0,z4.d,uxtw]
LD1SW {Z0.D}, P0/Z, [X0,Z4.D,UXTW]
ld1sw {z0.d}, p0/z, [x0,z4.d,uxtw #0]
ld1sw {z0.d}, p0/z, [x0,z31.d,uxtw]
LD1SW {Z0.D}, P0/Z, [X0,Z31.D,UXTW]
ld1sw {z0.d}, p0/z, [x0,z31.d,uxtw #0]
ld1sw z0.d, p0/z, [x0,z0.d,sxtw]
ld1sw {z0.d}, p0/z, [x0,z0.d,sxtw]
LD1SW {Z0.D}, P0/Z, [X0,Z0.D,SXTW]
ld1sw {z0.d}, p0/z, [x0,z0.d,sxtw #0]
ld1sw z1.d, p0/z, [x0,z0.d,sxtw]
ld1sw {z1.d}, p0/z, [x0,z0.d,sxtw]
LD1SW {Z1.D}, P0/Z, [X0,Z0.D,SXTW]
ld1sw {z1.d}, p0/z, [x0,z0.d,sxtw #0]
ld1sw z31.d, p0/z, [x0,z0.d,sxtw]
ld1sw {z31.d}, p0/z, [x0,z0.d,sxtw]
LD1SW {Z31.D}, P0/Z, [X0,Z0.D,SXTW]
ld1sw {z31.d}, p0/z, [x0,z0.d,sxtw #0]
ld1sw {z0.d}, p2/z, [x0,z0.d,sxtw]
LD1SW {Z0.D}, P2/Z, [X0,Z0.D,SXTW]
ld1sw {z0.d}, p2/z, [x0,z0.d,sxtw #0]
ld1sw {z0.d}, p7/z, [x0,z0.d,sxtw]
LD1SW {Z0.D}, P7/Z, [X0,Z0.D,SXTW]
ld1sw {z0.d}, p7/z, [x0,z0.d,sxtw #0]
ld1sw {z0.d}, p0/z, [x3,z0.d,sxtw]
LD1SW {Z0.D}, P0/Z, [X3,Z0.D,SXTW]
ld1sw {z0.d}, p0/z, [x3,z0.d,sxtw #0]
ld1sw {z0.d}, p0/z, [sp,z0.d,sxtw]
LD1SW {Z0.D}, P0/Z, [SP,Z0.D,SXTW]
ld1sw {z0.d}, p0/z, [sp,z0.d,sxtw #0]
ld1sw {z0.d}, p0/z, [x0,z4.d,sxtw]
LD1SW {Z0.D}, P0/Z, [X0,Z4.D,SXTW]
ld1sw {z0.d}, p0/z, [x0,z4.d,sxtw #0]
ld1sw {z0.d}, p0/z, [x0,z31.d,sxtw]
LD1SW {Z0.D}, P0/Z, [X0,Z31.D,SXTW]
ld1sw {z0.d}, p0/z, [x0,z31.d,sxtw #0]
ld1sw z0.d, p0/z, [x0,z0.d,uxtw #2]
ld1sw {z0.d}, p0/z, [x0,z0.d,uxtw #2]
LD1SW {Z0.D}, P0/Z, [X0,Z0.D,UXTW #2]
ld1sw z1.d, p0/z, [x0,z0.d,uxtw #2]
ld1sw {z1.d}, p0/z, [x0,z0.d,uxtw #2]
LD1SW {Z1.D}, P0/Z, [X0,Z0.D,UXTW #2]
ld1sw z31.d, p0/z, [x0,z0.d,uxtw #2]
ld1sw {z31.d}, p0/z, [x0,z0.d,uxtw #2]
LD1SW {Z31.D}, P0/Z, [X0,Z0.D,UXTW #2]
ld1sw {z0.d}, p2/z, [x0,z0.d,uxtw #2]
LD1SW {Z0.D}, P2/Z, [X0,Z0.D,UXTW #2]
ld1sw {z0.d}, p7/z, [x0,z0.d,uxtw #2]
LD1SW {Z0.D}, P7/Z, [X0,Z0.D,UXTW #2]
ld1sw {z0.d}, p0/z, [x3,z0.d,uxtw #2]
LD1SW {Z0.D}, P0/Z, [X3,Z0.D,UXTW #2]
ld1sw {z0.d}, p0/z, [sp,z0.d,uxtw #2]
LD1SW {Z0.D}, P0/Z, [SP,Z0.D,UXTW #2]
ld1sw {z0.d}, p0/z, [x0,z4.d,uxtw #2]
LD1SW {Z0.D}, P0/Z, [X0,Z4.D,UXTW #2]
ld1sw {z0.d}, p0/z, [x0,z31.d,uxtw #2]
LD1SW {Z0.D}, P0/Z, [X0,Z31.D,UXTW #2]
ld1sw z0.d, p0/z, [x0,z0.d,sxtw #2]
ld1sw {z0.d}, p0/z, [x0,z0.d,sxtw #2]
LD1SW {Z0.D}, P0/Z, [X0,Z0.D,SXTW #2]
ld1sw z1.d, p0/z, [x0,z0.d,sxtw #2]
ld1sw {z1.d}, p0/z, [x0,z0.d,sxtw #2]
LD1SW {Z1.D}, P0/Z, [X0,Z0.D,SXTW #2]
ld1sw z31.d, p0/z, [x0,z0.d,sxtw #2]
ld1sw {z31.d}, p0/z, [x0,z0.d,sxtw #2]
LD1SW {Z31.D}, P0/Z, [X0,Z0.D,SXTW #2]
ld1sw {z0.d}, p2/z, [x0,z0.d,sxtw #2]
LD1SW {Z0.D}, P2/Z, [X0,Z0.D,SXTW #2]
ld1sw {z0.d}, p7/z, [x0,z0.d,sxtw #2]
LD1SW {Z0.D}, P7/Z, [X0,Z0.D,SXTW #2]
ld1sw {z0.d}, p0/z, [x3,z0.d,sxtw #2]
LD1SW {Z0.D}, P0/Z, [X3,Z0.D,SXTW #2]
ld1sw {z0.d}, p0/z, [sp,z0.d,sxtw #2]
LD1SW {Z0.D}, P0/Z, [SP,Z0.D,SXTW #2]
ld1sw {z0.d}, p0/z, [x0,z4.d,sxtw #2]
LD1SW {Z0.D}, P0/Z, [X0,Z4.D,SXTW #2]
ld1sw {z0.d}, p0/z, [x0,z31.d,sxtw #2]
LD1SW {Z0.D}, P0/Z, [X0,Z31.D,SXTW #2]
ld1sw z0.d, p0/z, [x0,z0.d]
ld1sw {z0.d}, p0/z, [x0,z0.d]
LD1SW {Z0.D}, P0/Z, [X0,Z0.D]
ld1sw {z0.d}, p0/z, [x0,z0.d,lsl #0]
ld1sw z1.d, p0/z, [x0,z0.d]
ld1sw {z1.d}, p0/z, [x0,z0.d]
LD1SW {Z1.D}, P0/Z, [X0,Z0.D]
ld1sw {z1.d}, p0/z, [x0,z0.d,lsl #0]
ld1sw z31.d, p0/z, [x0,z0.d]
ld1sw {z31.d}, p0/z, [x0,z0.d]
LD1SW {Z31.D}, P0/Z, [X0,Z0.D]
ld1sw {z31.d}, p0/z, [x0,z0.d,lsl #0]
ld1sw {z0.d}, p2/z, [x0,z0.d]
LD1SW {Z0.D}, P2/Z, [X0,Z0.D]
ld1sw {z0.d}, p2/z, [x0,z0.d,lsl #0]
ld1sw {z0.d}, p7/z, [x0,z0.d]
LD1SW {Z0.D}, P7/Z, [X0,Z0.D]
ld1sw {z0.d}, p7/z, [x0,z0.d,lsl #0]
ld1sw {z0.d}, p0/z, [x3,z0.d]
LD1SW {Z0.D}, P0/Z, [X3,Z0.D]
ld1sw {z0.d}, p0/z, [x3,z0.d,lsl #0]
ld1sw {z0.d}, p0/z, [sp,z0.d]
LD1SW {Z0.D}, P0/Z, [SP,Z0.D]
ld1sw {z0.d}, p0/z, [sp,z0.d,lsl #0]
ld1sw {z0.d}, p0/z, [x0,z4.d]
LD1SW {Z0.D}, P0/Z, [X0,Z4.D]
ld1sw {z0.d}, p0/z, [x0,z4.d,lsl #0]
ld1sw {z0.d}, p0/z, [x0,z31.d]
LD1SW {Z0.D}, P0/Z, [X0,Z31.D]
ld1sw {z0.d}, p0/z, [x0,z31.d,lsl #0]
ld1sw z0.d, p0/z, [x0,z0.d,lsl #2]
ld1sw {z0.d}, p0/z, [x0,z0.d,lsl #2]
LD1SW {Z0.D}, P0/Z, [X0,Z0.D,LSL #2]
ld1sw z1.d, p0/z, [x0,z0.d,lsl #2]
ld1sw {z1.d}, p0/z, [x0,z0.d,lsl #2]
LD1SW {Z1.D}, P0/Z, [X0,Z0.D,LSL #2]
ld1sw z31.d, p0/z, [x0,z0.d,lsl #2]
ld1sw {z31.d}, p0/z, [x0,z0.d,lsl #2]
LD1SW {Z31.D}, P0/Z, [X0,Z0.D,LSL #2]
ld1sw {z0.d}, p2/z, [x0,z0.d,lsl #2]
LD1SW {Z0.D}, P2/Z, [X0,Z0.D,LSL #2]
ld1sw {z0.d}, p7/z, [x0,z0.d,lsl #2]
LD1SW {Z0.D}, P7/Z, [X0,Z0.D,LSL #2]
ld1sw {z0.d}, p0/z, [x3,z0.d,lsl #2]
LD1SW {Z0.D}, P0/Z, [X3,Z0.D,LSL #2]
ld1sw {z0.d}, p0/z, [sp,z0.d,lsl #2]
LD1SW {Z0.D}, P0/Z, [SP,Z0.D,LSL #2]
ld1sw {z0.d}, p0/z, [x0,z4.d,lsl #2]
LD1SW {Z0.D}, P0/Z, [X0,Z4.D,LSL #2]
ld1sw {z0.d}, p0/z, [x0,z31.d,lsl #2]
LD1SW {Z0.D}, P0/Z, [X0,Z31.D,LSL #2]
ld1sw z0.d, p0/z, [x0,#0]
ld1sw {z0.d}, p0/z, [x0,#0]
LD1SW {Z0.D}, P0/Z, [X0,#0]
ld1sw {z0.d}, p0/z, [x0,#0,mul vl]
ld1sw {z0.d}, p0/z, [x0]
ld1sw z1.d, p0/z, [x0,#0]
ld1sw {z1.d}, p0/z, [x0,#0]
LD1SW {Z1.D}, P0/Z, [X0,#0]
ld1sw {z1.d}, p0/z, [x0,#0,mul vl]
ld1sw {z1.d}, p0/z, [x0]
ld1sw z31.d, p0/z, [x0,#0]
ld1sw {z31.d}, p0/z, [x0,#0]
LD1SW {Z31.D}, P0/Z, [X0,#0]
ld1sw {z31.d}, p0/z, [x0,#0,mul vl]
ld1sw {z31.d}, p0/z, [x0]
ld1sw {z0.d}, p2/z, [x0,#0]
LD1SW {Z0.D}, P2/Z, [X0,#0]
ld1sw {z0.d}, p2/z, [x0,#0,mul vl]
ld1sw {z0.d}, p2/z, [x0]
ld1sw {z0.d}, p7/z, [x0,#0]
LD1SW {Z0.D}, P7/Z, [X0,#0]
ld1sw {z0.d}, p7/z, [x0,#0,mul vl]
ld1sw {z0.d}, p7/z, [x0]
ld1sw {z0.d}, p0/z, [x3,#0]
LD1SW {Z0.D}, P0/Z, [X3,#0]
ld1sw {z0.d}, p0/z, [x3,#0,mul vl]
ld1sw {z0.d}, p0/z, [x3]
ld1sw {z0.d}, p0/z, [sp,#0]
LD1SW {Z0.D}, P0/Z, [SP,#0]
ld1sw {z0.d}, p0/z, [sp,#0,mul vl]
ld1sw {z0.d}, p0/z, [sp]
ld1sw {z0.d}, p0/z, [x0,#7,mul vl]
LD1SW {Z0.D}, P0/Z, [X0,#7,MUL VL]
ld1sw {z0.d}, p0/z, [x0,#-8,mul vl]
LD1SW {Z0.D}, P0/Z, [X0,#-8,MUL VL]
ld1sw {z0.d}, p0/z, [x0,#-7,mul vl]
LD1SW {Z0.D}, P0/Z, [X0,#-7,MUL VL]
ld1sw {z0.d}, p0/z, [x0,#-1,mul vl]
LD1SW {Z0.D}, P0/Z, [X0,#-1,MUL VL]
ld1sw z0.d, p0/z, [z0.d,#0]
ld1sw {z0.d}, p0/z, [z0.d,#0]
LD1SW {Z0.D}, P0/Z, [Z0.D,#0]
ld1sw {z0.d}, p0/z, [z0.d]
ld1sw z1.d, p0/z, [z0.d,#0]
ld1sw {z1.d}, p0/z, [z0.d,#0]
LD1SW {Z1.D}, P0/Z, [Z0.D,#0]
ld1sw {z1.d}, p0/z, [z0.d]
ld1sw z31.d, p0/z, [z0.d,#0]
ld1sw {z31.d}, p0/z, [z0.d,#0]
LD1SW {Z31.D}, P0/Z, [Z0.D,#0]
ld1sw {z31.d}, p0/z, [z0.d]
ld1sw {z0.d}, p2/z, [z0.d,#0]
LD1SW {Z0.D}, P2/Z, [Z0.D,#0]
ld1sw {z0.d}, p2/z, [z0.d]
ld1sw {z0.d}, p7/z, [z0.d,#0]
LD1SW {Z0.D}, P7/Z, [Z0.D,#0]
ld1sw {z0.d}, p7/z, [z0.d]
ld1sw {z0.d}, p0/z, [z3.d,#0]
LD1SW {Z0.D}, P0/Z, [Z3.D,#0]
ld1sw {z0.d}, p0/z, [z3.d]
ld1sw {z0.d}, p0/z, [z31.d,#0]
LD1SW {Z0.D}, P0/Z, [Z31.D,#0]
ld1sw {z0.d}, p0/z, [z31.d]
ld1sw {z0.d}, p0/z, [z0.d,#60]
LD1SW {Z0.D}, P0/Z, [Z0.D,#60]
ld1sw {z0.d}, p0/z, [z0.d,#64]
LD1SW {Z0.D}, P0/Z, [Z0.D,#64]
ld1sw {z0.d}, p0/z, [z0.d,#68]
LD1SW {Z0.D}, P0/Z, [Z0.D,#68]
ld1sw {z0.d}, p0/z, [z0.d,#124]
LD1SW {Z0.D}, P0/Z, [Z0.D,#124]
ld1w z0.s, p0/z, [x0,z0.s,uxtw]
ld1w {z0.s}, p0/z, [x0,z0.s,uxtw]
LD1W {Z0.S}, P0/Z, [X0,Z0.S,UXTW]
ld1w {z0.s}, p0/z, [x0,z0.s,uxtw #0]
ld1w z1.s, p0/z, [x0,z0.s,uxtw]
ld1w {z1.s}, p0/z, [x0,z0.s,uxtw]
LD1W {Z1.S}, P0/Z, [X0,Z0.S,UXTW]
ld1w {z1.s}, p0/z, [x0,z0.s,uxtw #0]
ld1w z31.s, p0/z, [x0,z0.s,uxtw]
ld1w {z31.s}, p0/z, [x0,z0.s,uxtw]
LD1W {Z31.S}, P0/Z, [X0,Z0.S,UXTW]
ld1w {z31.s}, p0/z, [x0,z0.s,uxtw #0]
ld1w {z0.s}, p2/z, [x0,z0.s,uxtw]
LD1W {Z0.S}, P2/Z, [X0,Z0.S,UXTW]
ld1w {z0.s}, p2/z, [x0,z0.s,uxtw #0]
ld1w {z0.s}, p7/z, [x0,z0.s,uxtw]
LD1W {Z0.S}, P7/Z, [X0,Z0.S,UXTW]
ld1w {z0.s}, p7/z, [x0,z0.s,uxtw #0]
ld1w {z0.s}, p0/z, [x3,z0.s,uxtw]
LD1W {Z0.S}, P0/Z, [X3,Z0.S,UXTW]
ld1w {z0.s}, p0/z, [x3,z0.s,uxtw #0]
ld1w {z0.s}, p0/z, [sp,z0.s,uxtw]
LD1W {Z0.S}, P0/Z, [SP,Z0.S,UXTW]
ld1w {z0.s}, p0/z, [sp,z0.s,uxtw #0]
ld1w {z0.s}, p0/z, [x0,z4.s,uxtw]
LD1W {Z0.S}, P0/Z, [X0,Z4.S,UXTW]
ld1w {z0.s}, p0/z, [x0,z4.s,uxtw #0]
ld1w {z0.s}, p0/z, [x0,z31.s,uxtw]
LD1W {Z0.S}, P0/Z, [X0,Z31.S,UXTW]
ld1w {z0.s}, p0/z, [x0,z31.s,uxtw #0]
ld1w z0.s, p0/z, [x0,z0.s,sxtw]
ld1w {z0.s}, p0/z, [x0,z0.s,sxtw]
LD1W {Z0.S}, P0/Z, [X0,Z0.S,SXTW]
ld1w {z0.s}, p0/z, [x0,z0.s,sxtw #0]
ld1w z1.s, p0/z, [x0,z0.s,sxtw]
ld1w {z1.s}, p0/z, [x0,z0.s,sxtw]
LD1W {Z1.S}, P0/Z, [X0,Z0.S,SXTW]
ld1w {z1.s}, p0/z, [x0,z0.s,sxtw #0]
ld1w z31.s, p0/z, [x0,z0.s,sxtw]
ld1w {z31.s}, p0/z, [x0,z0.s,sxtw]
LD1W {Z31.S}, P0/Z, [X0,Z0.S,SXTW]
ld1w {z31.s}, p0/z, [x0,z0.s,sxtw #0]
ld1w {z0.s}, p2/z, [x0,z0.s,sxtw]
LD1W {Z0.S}, P2/Z, [X0,Z0.S,SXTW]
ld1w {z0.s}, p2/z, [x0,z0.s,sxtw #0]
ld1w {z0.s}, p7/z, [x0,z0.s,sxtw]
LD1W {Z0.S}, P7/Z, [X0,Z0.S,SXTW]
ld1w {z0.s}, p7/z, [x0,z0.s,sxtw #0]
ld1w {z0.s}, p0/z, [x3,z0.s,sxtw]
LD1W {Z0.S}, P0/Z, [X3,Z0.S,SXTW]
ld1w {z0.s}, p0/z, [x3,z0.s,sxtw #0]
ld1w {z0.s}, p0/z, [sp,z0.s,sxtw]
LD1W {Z0.S}, P0/Z, [SP,Z0.S,SXTW]
ld1w {z0.s}, p0/z, [sp,z0.s,sxtw #0]
ld1w {z0.s}, p0/z, [x0,z4.s,sxtw]
LD1W {Z0.S}, P0/Z, [X0,Z4.S,SXTW]
ld1w {z0.s}, p0/z, [x0,z4.s,sxtw #0]
ld1w {z0.s}, p0/z, [x0,z31.s,sxtw]
LD1W {Z0.S}, P0/Z, [X0,Z31.S,SXTW]
ld1w {z0.s}, p0/z, [x0,z31.s,sxtw #0]
ld1w z0.s, p0/z, [x0,z0.s,uxtw #2]
ld1w {z0.s}, p0/z, [x0,z0.s,uxtw #2]
LD1W {Z0.S}, P0/Z, [X0,Z0.S,UXTW #2]
ld1w z1.s, p0/z, [x0,z0.s,uxtw #2]
ld1w {z1.s}, p0/z, [x0,z0.s,uxtw #2]
LD1W {Z1.S}, P0/Z, [X0,Z0.S,UXTW #2]
ld1w z31.s, p0/z, [x0,z0.s,uxtw #2]
ld1w {z31.s}, p0/z, [x0,z0.s,uxtw #2]
LD1W {Z31.S}, P0/Z, [X0,Z0.S,UXTW #2]
ld1w {z0.s}, p2/z, [x0,z0.s,uxtw #2]
LD1W {Z0.S}, P2/Z, [X0,Z0.S,UXTW #2]
ld1w {z0.s}, p7/z, [x0,z0.s,uxtw #2]
LD1W {Z0.S}, P7/Z, [X0,Z0.S,UXTW #2]
ld1w {z0.s}, p0/z, [x3,z0.s,uxtw #2]
LD1W {Z0.S}, P0/Z, [X3,Z0.S,UXTW #2]
ld1w {z0.s}, p0/z, [sp,z0.s,uxtw #2]
LD1W {Z0.S}, P0/Z, [SP,Z0.S,UXTW #2]
ld1w {z0.s}, p0/z, [x0,z4.s,uxtw #2]
LD1W {Z0.S}, P0/Z, [X0,Z4.S,UXTW #2]
ld1w {z0.s}, p0/z, [x0,z31.s,uxtw #2]
LD1W {Z0.S}, P0/Z, [X0,Z31.S,UXTW #2]
ld1w z0.s, p0/z, [x0,z0.s,sxtw #2]
ld1w {z0.s}, p0/z, [x0,z0.s,sxtw #2]
LD1W {Z0.S}, P0/Z, [X0,Z0.S,SXTW #2]
ld1w z1.s, p0/z, [x0,z0.s,sxtw #2]
ld1w {z1.s}, p0/z, [x0,z0.s,sxtw #2]
LD1W {Z1.S}, P0/Z, [X0,Z0.S,SXTW #2]
ld1w z31.s, p0/z, [x0,z0.s,sxtw #2]
ld1w {z31.s}, p0/z, [x0,z0.s,sxtw #2]
LD1W {Z31.S}, P0/Z, [X0,Z0.S,SXTW #2]
ld1w {z0.s}, p2/z, [x0,z0.s,sxtw #2]
LD1W {Z0.S}, P2/Z, [X0,Z0.S,SXTW #2]
ld1w {z0.s}, p7/z, [x0,z0.s,sxtw #2]
LD1W {Z0.S}, P7/Z, [X0,Z0.S,SXTW #2]
ld1w {z0.s}, p0/z, [x3,z0.s,sxtw #2]
LD1W {Z0.S}, P0/Z, [X3,Z0.S,SXTW #2]
ld1w {z0.s}, p0/z, [sp,z0.s,sxtw #2]
LD1W {Z0.S}, P0/Z, [SP,Z0.S,SXTW #2]
ld1w {z0.s}, p0/z, [x0,z4.s,sxtw #2]
LD1W {Z0.S}, P0/Z, [X0,Z4.S,SXTW #2]
ld1w {z0.s}, p0/z, [x0,z31.s,sxtw #2]
LD1W {Z0.S}, P0/Z, [X0,Z31.S,SXTW #2]
ld1w z0.s, p0/z, [x0,x0,lsl #2]
ld1w {z0.s}, p0/z, [x0,x0,lsl #2]
LD1W {Z0.S}, P0/Z, [X0,X0,LSL #2]
ld1w z1.s, p0/z, [x0,x0,lsl #2]
ld1w {z1.s}, p0/z, [x0,x0,lsl #2]
LD1W {Z1.S}, P0/Z, [X0,X0,LSL #2]
ld1w z31.s, p0/z, [x0,x0,lsl #2]
ld1w {z31.s}, p0/z, [x0,x0,lsl #2]
LD1W {Z31.S}, P0/Z, [X0,X0,LSL #2]
ld1w {z0.s}, p2/z, [x0,x0,lsl #2]
LD1W {Z0.S}, P2/Z, [X0,X0,LSL #2]
ld1w {z0.s}, p7/z, [x0,x0,lsl #2]
LD1W {Z0.S}, P7/Z, [X0,X0,LSL #2]
ld1w {z0.s}, p0/z, [x3,x0,lsl #2]
LD1W {Z0.S}, P0/Z, [X3,X0,LSL #2]
ld1w {z0.s}, p0/z, [sp,x0,lsl #2]
LD1W {Z0.S}, P0/Z, [SP,X0,LSL #2]
ld1w {z0.s}, p0/z, [x0,x4,lsl #2]
LD1W {Z0.S}, P0/Z, [X0,X4,LSL #2]
ld1w {z0.s}, p0/z, [x0,x30,lsl #2]
LD1W {Z0.S}, P0/Z, [X0,X30,LSL #2]
ld1w z0.d, p0/z, [x0,x0,lsl #2]
ld1w {z0.d}, p0/z, [x0,x0,lsl #2]
LD1W {Z0.D}, P0/Z, [X0,X0,LSL #2]
ld1w z1.d, p0/z, [x0,x0,lsl #2]
ld1w {z1.d}, p0/z, [x0,x0,lsl #2]
LD1W {Z1.D}, P0/Z, [X0,X0,LSL #2]
ld1w z31.d, p0/z, [x0,x0,lsl #2]
ld1w {z31.d}, p0/z, [x0,x0,lsl #2]
LD1W {Z31.D}, P0/Z, [X0,X0,LSL #2]
ld1w {z0.d}, p2/z, [x0,x0,lsl #2]
LD1W {Z0.D}, P2/Z, [X0,X0,LSL #2]
ld1w {z0.d}, p7/z, [x0,x0,lsl #2]
LD1W {Z0.D}, P7/Z, [X0,X0,LSL #2]
ld1w {z0.d}, p0/z, [x3,x0,lsl #2]
LD1W {Z0.D}, P0/Z, [X3,X0,LSL #2]
ld1w {z0.d}, p0/z, [sp,x0,lsl #2]
LD1W {Z0.D}, P0/Z, [SP,X0,LSL #2]
ld1w {z0.d}, p0/z, [x0,x4,lsl #2]
LD1W {Z0.D}, P0/Z, [X0,X4,LSL #2]
ld1w {z0.d}, p0/z, [x0,x30,lsl #2]
LD1W {Z0.D}, P0/Z, [X0,X30,LSL #2]
ld1w z0.d, p0/z, [x0,z0.d,uxtw]
ld1w {z0.d}, p0/z, [x0,z0.d,uxtw]
LD1W {Z0.D}, P0/Z, [X0,Z0.D,UXTW]
ld1w {z0.d}, p0/z, [x0,z0.d,uxtw #0]
ld1w z1.d, p0/z, [x0,z0.d,uxtw]
ld1w {z1.d}, p0/z, [x0,z0.d,uxtw]
LD1W {Z1.D}, P0/Z, [X0,Z0.D,UXTW]
ld1w {z1.d}, p0/z, [x0,z0.d,uxtw #0]
ld1w z31.d, p0/z, [x0,z0.d,uxtw]
ld1w {z31.d}, p0/z, [x0,z0.d,uxtw]
LD1W {Z31.D}, P0/Z, [X0,Z0.D,UXTW]
ld1w {z31.d}, p0/z, [x0,z0.d,uxtw #0]
ld1w {z0.d}, p2/z, [x0,z0.d,uxtw]
LD1W {Z0.D}, P2/Z, [X0,Z0.D,UXTW]
ld1w {z0.d}, p2/z, [x0,z0.d,uxtw #0]
ld1w {z0.d}, p7/z, [x0,z0.d,uxtw]
LD1W {Z0.D}, P7/Z, [X0,Z0.D,UXTW]
ld1w {z0.d}, p7/z, [x0,z0.d,uxtw #0]
ld1w {z0.d}, p0/z, [x3,z0.d,uxtw]
LD1W {Z0.D}, P0/Z, [X3,Z0.D,UXTW]
ld1w {z0.d}, p0/z, [x3,z0.d,uxtw #0]
ld1w {z0.d}, p0/z, [sp,z0.d,uxtw]
LD1W {Z0.D}, P0/Z, [SP,Z0.D,UXTW]
ld1w {z0.d}, p0/z, [sp,z0.d,uxtw #0]
ld1w {z0.d}, p0/z, [x0,z4.d,uxtw]
LD1W {Z0.D}, P0/Z, [X0,Z4.D,UXTW]
ld1w {z0.d}, p0/z, [x0,z4.d,uxtw #0]
ld1w {z0.d}, p0/z, [x0,z31.d,uxtw]
LD1W {Z0.D}, P0/Z, [X0,Z31.D,UXTW]
ld1w {z0.d}, p0/z, [x0,z31.d,uxtw #0]
ld1w z0.d, p0/z, [x0,z0.d,sxtw]
ld1w {z0.d}, p0/z, [x0,z0.d,sxtw]
LD1W {Z0.D}, P0/Z, [X0,Z0.D,SXTW]
ld1w {z0.d}, p0/z, [x0,z0.d,sxtw #0]
ld1w z1.d, p0/z, [x0,z0.d,sxtw]
ld1w {z1.d}, p0/z, [x0,z0.d,sxtw]
LD1W {Z1.D}, P0/Z, [X0,Z0.D,SXTW]
ld1w {z1.d}, p0/z, [x0,z0.d,sxtw #0]
ld1w z31.d, p0/z, [x0,z0.d,sxtw]
ld1w {z31.d}, p0/z, [x0,z0.d,sxtw]
LD1W {Z31.D}, P0/Z, [X0,Z0.D,SXTW]
ld1w {z31.d}, p0/z, [x0,z0.d,sxtw #0]
ld1w {z0.d}, p2/z, [x0,z0.d,sxtw]
LD1W {Z0.D}, P2/Z, [X0,Z0.D,SXTW]
ld1w {z0.d}, p2/z, [x0,z0.d,sxtw #0]
ld1w {z0.d}, p7/z, [x0,z0.d,sxtw]
LD1W {Z0.D}, P7/Z, [X0,Z0.D,SXTW]
ld1w {z0.d}, p7/z, [x0,z0.d,sxtw #0]
ld1w {z0.d}, p0/z, [x3,z0.d,sxtw]
LD1W {Z0.D}, P0/Z, [X3,Z0.D,SXTW]
ld1w {z0.d}, p0/z, [x3,z0.d,sxtw #0]
ld1w {z0.d}, p0/z, [sp,z0.d,sxtw]
LD1W {Z0.D}, P0/Z, [SP,Z0.D,SXTW]
ld1w {z0.d}, p0/z, [sp,z0.d,sxtw #0]
ld1w {z0.d}, p0/z, [x0,z4.d,sxtw]
LD1W {Z0.D}, P0/Z, [X0,Z4.D,SXTW]
ld1w {z0.d}, p0/z, [x0,z4.d,sxtw #0]
ld1w {z0.d}, p0/z, [x0,z31.d,sxtw]
LD1W {Z0.D}, P0/Z, [X0,Z31.D,SXTW]
ld1w {z0.d}, p0/z, [x0,z31.d,sxtw #0]
ld1w z0.d, p0/z, [x0,z0.d,uxtw #2]
ld1w {z0.d}, p0/z, [x0,z0.d,uxtw #2]
LD1W {Z0.D}, P0/Z, [X0,Z0.D,UXTW #2]
ld1w z1.d, p0/z, [x0,z0.d,uxtw #2]
ld1w {z1.d}, p0/z, [x0,z0.d,uxtw #2]
LD1W {Z1.D}, P0/Z, [X0,Z0.D,UXTW #2]
ld1w z31.d, p0/z, [x0,z0.d,uxtw #2]
ld1w {z31.d}, p0/z, [x0,z0.d,uxtw #2]
LD1W {Z31.D}, P0/Z, [X0,Z0.D,UXTW #2]
ld1w {z0.d}, p2/z, [x0,z0.d,uxtw #2]
LD1W {Z0.D}, P2/Z, [X0,Z0.D,UXTW #2]
ld1w {z0.d}, p7/z, [x0,z0.d,uxtw #2]
LD1W {Z0.D}, P7/Z, [X0,Z0.D,UXTW #2]
ld1w {z0.d}, p0/z, [x3,z0.d,uxtw #2]
LD1W {Z0.D}, P0/Z, [X3,Z0.D,UXTW #2]
ld1w {z0.d}, p0/z, [sp,z0.d,uxtw #2]
LD1W {Z0.D}, P0/Z, [SP,Z0.D,UXTW #2]
ld1w {z0.d}, p0/z, [x0,z4.d,uxtw #2]
LD1W {Z0.D}, P0/Z, [X0,Z4.D,UXTW #2]
ld1w {z0.d}, p0/z, [x0,z31.d,uxtw #2]
LD1W {Z0.D}, P0/Z, [X0,Z31.D,UXTW #2]
ld1w z0.d, p0/z, [x0,z0.d,sxtw #2]
ld1w {z0.d}, p0/z, [x0,z0.d,sxtw #2]
LD1W {Z0.D}, P0/Z, [X0,Z0.D,SXTW #2]
ld1w z1.d, p0/z, [x0,z0.d,sxtw #2]
ld1w {z1.d}, p0/z, [x0,z0.d,sxtw #2]
LD1W {Z1.D}, P0/Z, [X0,Z0.D,SXTW #2]
ld1w z31.d, p0/z, [x0,z0.d,sxtw #2]
ld1w {z31.d}, p0/z, [x0,z0.d,sxtw #2]
LD1W {Z31.D}, P0/Z, [X0,Z0.D,SXTW #2]
ld1w {z0.d}, p2/z, [x0,z0.d,sxtw #2]
LD1W {Z0.D}, P2/Z, [X0,Z0.D,SXTW #2]
ld1w {z0.d}, p7/z, [x0,z0.d,sxtw #2]
LD1W {Z0.D}, P7/Z, [X0,Z0.D,SXTW #2]
ld1w {z0.d}, p0/z, [x3,z0.d,sxtw #2]
LD1W {Z0.D}, P0/Z, [X3,Z0.D,SXTW #2]
ld1w {z0.d}, p0/z, [sp,z0.d,sxtw #2]
LD1W {Z0.D}, P0/Z, [SP,Z0.D,SXTW #2]
ld1w {z0.d}, p0/z, [x0,z4.d,sxtw #2]
LD1W {Z0.D}, P0/Z, [X0,Z4.D,SXTW #2]
ld1w {z0.d}, p0/z, [x0,z31.d,sxtw #2]
LD1W {Z0.D}, P0/Z, [X0,Z31.D,SXTW #2]
ld1w z0.d, p0/z, [x0,z0.d]
ld1w {z0.d}, p0/z, [x0,z0.d]
LD1W {Z0.D}, P0/Z, [X0,Z0.D]
ld1w {z0.d}, p0/z, [x0,z0.d,lsl #0]
ld1w z1.d, p0/z, [x0,z0.d]
ld1w {z1.d}, p0/z, [x0,z0.d]
LD1W {Z1.D}, P0/Z, [X0,Z0.D]
ld1w {z1.d}, p0/z, [x0,z0.d,lsl #0]
ld1w z31.d, p0/z, [x0,z0.d]
ld1w {z31.d}, p0/z, [x0,z0.d]
LD1W {Z31.D}, P0/Z, [X0,Z0.D]
ld1w {z31.d}, p0/z, [x0,z0.d,lsl #0]
ld1w {z0.d}, p2/z, [x0,z0.d]
LD1W {Z0.D}, P2/Z, [X0,Z0.D]
ld1w {z0.d}, p2/z, [x0,z0.d,lsl #0]
ld1w {z0.d}, p7/z, [x0,z0.d]
LD1W {Z0.D}, P7/Z, [X0,Z0.D]
ld1w {z0.d}, p7/z, [x0,z0.d,lsl #0]
ld1w {z0.d}, p0/z, [x3,z0.d]
LD1W {Z0.D}, P0/Z, [X3,Z0.D]
ld1w {z0.d}, p0/z, [x3,z0.d,lsl #0]
ld1w {z0.d}, p0/z, [sp,z0.d]
LD1W {Z0.D}, P0/Z, [SP,Z0.D]
ld1w {z0.d}, p0/z, [sp,z0.d,lsl #0]
ld1w {z0.d}, p0/z, [x0,z4.d]
LD1W {Z0.D}, P0/Z, [X0,Z4.D]
ld1w {z0.d}, p0/z, [x0,z4.d,lsl #0]
ld1w {z0.d}, p0/z, [x0,z31.d]
LD1W {Z0.D}, P0/Z, [X0,Z31.D]
ld1w {z0.d}, p0/z, [x0,z31.d,lsl #0]
ld1w z0.d, p0/z, [x0,z0.d,lsl #2]
ld1w {z0.d}, p0/z, [x0,z0.d,lsl #2]
LD1W {Z0.D}, P0/Z, [X0,Z0.D,LSL #2]
ld1w z1.d, p0/z, [x0,z0.d,lsl #2]
ld1w {z1.d}, p0/z, [x0,z0.d,lsl #2]
LD1W {Z1.D}, P0/Z, [X0,Z0.D,LSL #2]
ld1w z31.d, p0/z, [x0,z0.d,lsl #2]
ld1w {z31.d}, p0/z, [x0,z0.d,lsl #2]
LD1W {Z31.D}, P0/Z, [X0,Z0.D,LSL #2]
ld1w {z0.d}, p2/z, [x0,z0.d,lsl #2]
LD1W {Z0.D}, P2/Z, [X0,Z0.D,LSL #2]
ld1w {z0.d}, p7/z, [x0,z0.d,lsl #2]
LD1W {Z0.D}, P7/Z, [X0,Z0.D,LSL #2]
ld1w {z0.d}, p0/z, [x3,z0.d,lsl #2]
LD1W {Z0.D}, P0/Z, [X3,Z0.D,LSL #2]
ld1w {z0.d}, p0/z, [sp,z0.d,lsl #2]
LD1W {Z0.D}, P0/Z, [SP,Z0.D,LSL #2]
ld1w {z0.d}, p0/z, [x0,z4.d,lsl #2]
LD1W {Z0.D}, P0/Z, [X0,Z4.D,LSL #2]
ld1w {z0.d}, p0/z, [x0,z31.d,lsl #2]
LD1W {Z0.D}, P0/Z, [X0,Z31.D,LSL #2]
ld1w z0.s, p0/z, [z0.s,#0]
ld1w {z0.s}, p0/z, [z0.s,#0]
LD1W {Z0.S}, P0/Z, [Z0.S,#0]
ld1w {z0.s}, p0/z, [z0.s]
ld1w z1.s, p0/z, [z0.s,#0]
ld1w {z1.s}, p0/z, [z0.s,#0]
LD1W {Z1.S}, P0/Z, [Z0.S,#0]
ld1w {z1.s}, p0/z, [z0.s]
ld1w z31.s, p0/z, [z0.s,#0]
ld1w {z31.s}, p0/z, [z0.s,#0]
LD1W {Z31.S}, P0/Z, [Z0.S,#0]
ld1w {z31.s}, p0/z, [z0.s]
ld1w {z0.s}, p2/z, [z0.s,#0]
LD1W {Z0.S}, P2/Z, [Z0.S,#0]
ld1w {z0.s}, p2/z, [z0.s]
ld1w {z0.s}, p7/z, [z0.s,#0]
LD1W {Z0.S}, P7/Z, [Z0.S,#0]
ld1w {z0.s}, p7/z, [z0.s]
ld1w {z0.s}, p0/z, [z3.s,#0]
LD1W {Z0.S}, P0/Z, [Z3.S,#0]
ld1w {z0.s}, p0/z, [z3.s]
ld1w {z0.s}, p0/z, [z31.s,#0]
LD1W {Z0.S}, P0/Z, [Z31.S,#0]
ld1w {z0.s}, p0/z, [z31.s]
ld1w {z0.s}, p0/z, [z0.s,#60]
LD1W {Z0.S}, P0/Z, [Z0.S,#60]
ld1w {z0.s}, p0/z, [z0.s,#64]
LD1W {Z0.S}, P0/Z, [Z0.S,#64]
ld1w {z0.s}, p0/z, [z0.s,#68]
LD1W {Z0.S}, P0/Z, [Z0.S,#68]
ld1w {z0.s}, p0/z, [z0.s,#124]
LD1W {Z0.S}, P0/Z, [Z0.S,#124]
ld1w z0.s, p0/z, [x0,#0]
ld1w {z0.s}, p0/z, [x0,#0]
LD1W {Z0.S}, P0/Z, [X0,#0]
ld1w {z0.s}, p0/z, [x0,#0,mul vl]
ld1w {z0.s}, p0/z, [x0]
ld1w z1.s, p0/z, [x0,#0]
ld1w {z1.s}, p0/z, [x0,#0]
LD1W {Z1.S}, P0/Z, [X0,#0]
ld1w {z1.s}, p0/z, [x0,#0,mul vl]
ld1w {z1.s}, p0/z, [x0]
ld1w z31.s, p0/z, [x0,#0]
ld1w {z31.s}, p0/z, [x0,#0]
LD1W {Z31.S}, P0/Z, [X0,#0]
ld1w {z31.s}, p0/z, [x0,#0,mul vl]
ld1w {z31.s}, p0/z, [x0]
ld1w {z0.s}, p2/z, [x0,#0]
LD1W {Z0.S}, P2/Z, [X0,#0]
ld1w {z0.s}, p2/z, [x0,#0,mul vl]
ld1w {z0.s}, p2/z, [x0]
ld1w {z0.s}, p7/z, [x0,#0]
LD1W {Z0.S}, P7/Z, [X0,#0]
ld1w {z0.s}, p7/z, [x0,#0,mul vl]
ld1w {z0.s}, p7/z, [x0]
ld1w {z0.s}, p0/z, [x3,#0]
LD1W {Z0.S}, P0/Z, [X3,#0]
ld1w {z0.s}, p0/z, [x3,#0,mul vl]
ld1w {z0.s}, p0/z, [x3]
ld1w {z0.s}, p0/z, [sp,#0]
LD1W {Z0.S}, P0/Z, [SP,#0]
ld1w {z0.s}, p0/z, [sp,#0,mul vl]
ld1w {z0.s}, p0/z, [sp]
ld1w {z0.s}, p0/z, [x0,#7,mul vl]
LD1W {Z0.S}, P0/Z, [X0,#7,MUL VL]
ld1w {z0.s}, p0/z, [x0,#-8,mul vl]
LD1W {Z0.S}, P0/Z, [X0,#-8,MUL VL]
ld1w {z0.s}, p0/z, [x0,#-7,mul vl]
LD1W {Z0.S}, P0/Z, [X0,#-7,MUL VL]
ld1w {z0.s}, p0/z, [x0,#-1,mul vl]
LD1W {Z0.S}, P0/Z, [X0,#-1,MUL VL]
ld1w z0.d, p0/z, [x0,#0]
ld1w {z0.d}, p0/z, [x0,#0]
LD1W {Z0.D}, P0/Z, [X0,#0]
ld1w {z0.d}, p0/z, [x0,#0,mul vl]
ld1w {z0.d}, p0/z, [x0]
ld1w z1.d, p0/z, [x0,#0]
ld1w {z1.d}, p0/z, [x0,#0]
LD1W {Z1.D}, P0/Z, [X0,#0]
ld1w {z1.d}, p0/z, [x0,#0,mul vl]
ld1w {z1.d}, p0/z, [x0]
ld1w z31.d, p0/z, [x0,#0]
ld1w {z31.d}, p0/z, [x0,#0]
LD1W {Z31.D}, P0/Z, [X0,#0]
ld1w {z31.d}, p0/z, [x0,#0,mul vl]
ld1w {z31.d}, p0/z, [x0]
ld1w {z0.d}, p2/z, [x0,#0]
LD1W {Z0.D}, P2/Z, [X0,#0]
ld1w {z0.d}, p2/z, [x0,#0,mul vl]
ld1w {z0.d}, p2/z, [x0]
ld1w {z0.d}, p7/z, [x0,#0]
LD1W {Z0.D}, P7/Z, [X0,#0]
ld1w {z0.d}, p7/z, [x0,#0,mul vl]
ld1w {z0.d}, p7/z, [x0]
ld1w {z0.d}, p0/z, [x3,#0]
LD1W {Z0.D}, P0/Z, [X3,#0]
ld1w {z0.d}, p0/z, [x3,#0,mul vl]
ld1w {z0.d}, p0/z, [x3]
ld1w {z0.d}, p0/z, [sp,#0]
LD1W {Z0.D}, P0/Z, [SP,#0]
ld1w {z0.d}, p0/z, [sp,#0,mul vl]
ld1w {z0.d}, p0/z, [sp]
ld1w {z0.d}, p0/z, [x0,#7,mul vl]
LD1W {Z0.D}, P0/Z, [X0,#7,MUL VL]
ld1w {z0.d}, p0/z, [x0,#-8,mul vl]
LD1W {Z0.D}, P0/Z, [X0,#-8,MUL VL]
ld1w {z0.d}, p0/z, [x0,#-7,mul vl]
LD1W {Z0.D}, P0/Z, [X0,#-7,MUL VL]
ld1w {z0.d}, p0/z, [x0,#-1,mul vl]
LD1W {Z0.D}, P0/Z, [X0,#-1,MUL VL]
ld1w z0.d, p0/z, [z0.d,#0]
ld1w {z0.d}, p0/z, [z0.d,#0]
LD1W {Z0.D}, P0/Z, [Z0.D,#0]
ld1w {z0.d}, p0/z, [z0.d]
ld1w z1.d, p0/z, [z0.d,#0]
ld1w {z1.d}, p0/z, [z0.d,#0]
LD1W {Z1.D}, P0/Z, [Z0.D,#0]
ld1w {z1.d}, p0/z, [z0.d]
ld1w z31.d, p0/z, [z0.d,#0]
ld1w {z31.d}, p0/z, [z0.d,#0]
LD1W {Z31.D}, P0/Z, [Z0.D,#0]
ld1w {z31.d}, p0/z, [z0.d]
ld1w {z0.d}, p2/z, [z0.d,#0]
LD1W {Z0.D}, P2/Z, [Z0.D,#0]
ld1w {z0.d}, p2/z, [z0.d]
ld1w {z0.d}, p7/z, [z0.d,#0]
LD1W {Z0.D}, P7/Z, [Z0.D,#0]
ld1w {z0.d}, p7/z, [z0.d]
ld1w {z0.d}, p0/z, [z3.d,#0]
LD1W {Z0.D}, P0/Z, [Z3.D,#0]
ld1w {z0.d}, p0/z, [z3.d]
ld1w {z0.d}, p0/z, [z31.d,#0]
LD1W {Z0.D}, P0/Z, [Z31.D,#0]
ld1w {z0.d}, p0/z, [z31.d]
ld1w {z0.d}, p0/z, [z0.d,#60]
LD1W {Z0.D}, P0/Z, [Z0.D,#60]
ld1w {z0.d}, p0/z, [z0.d,#64]
LD1W {Z0.D}, P0/Z, [Z0.D,#64]
ld1w {z0.d}, p0/z, [z0.d,#68]
LD1W {Z0.D}, P0/Z, [Z0.D,#68]
ld1w {z0.d}, p0/z, [z0.d,#124]
LD1W {Z0.D}, P0/Z, [Z0.D,#124]
ld2b {z0.b, z1.b}, p0/z, [x0,x0]
LD2B {Z0.B, Z1.B}, P0/Z, [X0,X0]
ld2b {z0.b, z1.b}, p0/z, [x0,x0,lsl #0]
ld2b {z0.b-z1.b}, p0/z, [x0,x0]
ld2b {z0.b-z1.b}, p0/z, [x0,x0,lsl #0]
ld2b {z1.b, z2.b}, p0/z, [x0,x0]
LD2B {Z1.B, Z2.B}, P0/Z, [X0,X0]
ld2b {z1.b, z2.b}, p0/z, [x0,x0,lsl #0]
ld2b {z1.b-z2.b}, p0/z, [x0,x0]
ld2b {z1.b-z2.b}, p0/z, [x0,x0,lsl #0]
ld2b {z31.b, z0.b}, p0/z, [x0,x0]
LD2B {Z31.B, Z0.B}, P0/Z, [X0,X0]
ld2b {z31.b, z0.b}, p0/z, [x0,x0,lsl #0]
ld2b {z0.b, z1.b}, p2/z, [x0,x0]
LD2B {Z0.B, Z1.B}, P2/Z, [X0,X0]
ld2b {z0.b, z1.b}, p2/z, [x0,x0,lsl #0]
ld2b {z0.b-z1.b}, p2/z, [x0,x0]
ld2b {z0.b-z1.b}, p2/z, [x0,x0,lsl #0]
ld2b {z0.b, z1.b}, p7/z, [x0,x0]
LD2B {Z0.B, Z1.B}, P7/Z, [X0,X0]
ld2b {z0.b, z1.b}, p7/z, [x0,x0,lsl #0]
ld2b {z0.b-z1.b}, p7/z, [x0,x0]
ld2b {z0.b-z1.b}, p7/z, [x0,x0,lsl #0]
ld2b {z0.b, z1.b}, p0/z, [x3,x0]
LD2B {Z0.B, Z1.B}, P0/Z, [X3,X0]
ld2b {z0.b, z1.b}, p0/z, [x3,x0,lsl #0]
ld2b {z0.b-z1.b}, p0/z, [x3,x0]
ld2b {z0.b-z1.b}, p0/z, [x3,x0,lsl #0]
ld2b {z0.b, z1.b}, p0/z, [sp,x0]
LD2B {Z0.B, Z1.B}, P0/Z, [SP,X0]
ld2b {z0.b, z1.b}, p0/z, [sp,x0,lsl #0]
ld2b {z0.b-z1.b}, p0/z, [sp,x0]
ld2b {z0.b-z1.b}, p0/z, [sp,x0,lsl #0]
ld2b {z0.b, z1.b}, p0/z, [x0,x4]
LD2B {Z0.B, Z1.B}, P0/Z, [X0,X4]
ld2b {z0.b, z1.b}, p0/z, [x0,x4,lsl #0]
ld2b {z0.b-z1.b}, p0/z, [x0,x4]
ld2b {z0.b-z1.b}, p0/z, [x0,x4,lsl #0]
ld2b {z0.b, z1.b}, p0/z, [x0,x30]
LD2B {Z0.B, Z1.B}, P0/Z, [X0,X30]
ld2b {z0.b, z1.b}, p0/z, [x0,x30,lsl #0]
ld2b {z0.b-z1.b}, p0/z, [x0,x30]
ld2b {z0.b-z1.b}, p0/z, [x0,x30,lsl #0]
ld2b {z0.b, z1.b}, p0/z, [x0,#0]
LD2B {Z0.B, Z1.B}, P0/Z, [X0,#0]
ld2b {z0.b, z1.b}, p0/z, [x0,#0,mul vl]
ld2b {z0.b, z1.b}, p0/z, [x0]
ld2b {z0.b-z1.b}, p0/z, [x0,#0]
ld2b {z0.b-z1.b}, p0/z, [x0,#0,mul vl]
ld2b {z0.b-z1.b}, p0/z, [x0]
ld2b {z1.b, z2.b}, p0/z, [x0,#0]
LD2B {Z1.B, Z2.B}, P0/Z, [X0,#0]
ld2b {z1.b, z2.b}, p0/z, [x0,#0,mul vl]
ld2b {z1.b, z2.b}, p0/z, [x0]
ld2b {z1.b-z2.b}, p0/z, [x0,#0]
ld2b {z1.b-z2.b}, p0/z, [x0,#0,mul vl]
ld2b {z1.b-z2.b}, p0/z, [x0]
ld2b {z31.b, z0.b}, p0/z, [x0,#0]
LD2B {Z31.B, Z0.B}, P0/Z, [X0,#0]
ld2b {z31.b, z0.b}, p0/z, [x0,#0,mul vl]
ld2b {z31.b, z0.b}, p0/z, [x0]
ld2b {z0.b, z1.b}, p2/z, [x0,#0]
LD2B {Z0.B, Z1.B}, P2/Z, [X0,#0]
ld2b {z0.b, z1.b}, p2/z, [x0,#0,mul vl]
ld2b {z0.b, z1.b}, p2/z, [x0]
ld2b {z0.b-z1.b}, p2/z, [x0,#0]
ld2b {z0.b-z1.b}, p2/z, [x0,#0,mul vl]
ld2b {z0.b-z1.b}, p2/z, [x0]
ld2b {z0.b, z1.b}, p7/z, [x0,#0]
LD2B {Z0.B, Z1.B}, P7/Z, [X0,#0]
ld2b {z0.b, z1.b}, p7/z, [x0,#0,mul vl]
ld2b {z0.b, z1.b}, p7/z, [x0]
ld2b {z0.b-z1.b}, p7/z, [x0,#0]
ld2b {z0.b-z1.b}, p7/z, [x0,#0,mul vl]
ld2b {z0.b-z1.b}, p7/z, [x0]
ld2b {z0.b, z1.b}, p0/z, [x3,#0]
LD2B {Z0.B, Z1.B}, P0/Z, [X3,#0]
ld2b {z0.b, z1.b}, p0/z, [x3,#0,mul vl]
ld2b {z0.b, z1.b}, p0/z, [x3]
ld2b {z0.b-z1.b}, p0/z, [x3,#0]
ld2b {z0.b-z1.b}, p0/z, [x3,#0,mul vl]
ld2b {z0.b-z1.b}, p0/z, [x3]
ld2b {z0.b, z1.b}, p0/z, [sp,#0]
LD2B {Z0.B, Z1.B}, P0/Z, [SP,#0]
ld2b {z0.b, z1.b}, p0/z, [sp,#0,mul vl]
ld2b {z0.b, z1.b}, p0/z, [sp]
ld2b {z0.b-z1.b}, p0/z, [sp,#0]
ld2b {z0.b-z1.b}, p0/z, [sp,#0,mul vl]
ld2b {z0.b-z1.b}, p0/z, [sp]
ld2b {z0.b, z1.b}, p0/z, [x0,#14,mul vl]
LD2B {Z0.B, Z1.B}, P0/Z, [X0,#14,MUL VL]
ld2b {z0.b-z1.b}, p0/z, [x0,#14,mul vl]
ld2b {z0.b, z1.b}, p0/z, [x0,#-16,mul vl]
LD2B {Z0.B, Z1.B}, P0/Z, [X0,#-16,MUL VL]
ld2b {z0.b-z1.b}, p0/z, [x0,#-16,mul vl]
ld2b {z0.b, z1.b}, p0/z, [x0,#-14,mul vl]
LD2B {Z0.B, Z1.B}, P0/Z, [X0,#-14,MUL VL]
ld2b {z0.b-z1.b}, p0/z, [x0,#-14,mul vl]
ld2b {z0.b, z1.b}, p0/z, [x0,#-2,mul vl]
LD2B {Z0.B, Z1.B}, P0/Z, [X0,#-2,MUL VL]
ld2b {z0.b-z1.b}, p0/z, [x0,#-2,mul vl]
ld2d {z0.d, z1.d}, p0/z, [x0,x0,lsl #3]
LD2D {Z0.D, Z1.D}, P0/Z, [X0,X0,LSL #3]
ld2d {z0.d-z1.d}, p0/z, [x0,x0,lsl #3]
ld2d {z1.d, z2.d}, p0/z, [x0,x0,lsl #3]
LD2D {Z1.D, Z2.D}, P0/Z, [X0,X0,LSL #3]
ld2d {z1.d-z2.d}, p0/z, [x0,x0,lsl #3]
ld2d {z31.d, z0.d}, p0/z, [x0,x0,lsl #3]
LD2D {Z31.D, Z0.D}, P0/Z, [X0,X0,LSL #3]
ld2d {z0.d, z1.d}, p2/z, [x0,x0,lsl #3]
LD2D {Z0.D, Z1.D}, P2/Z, [X0,X0,LSL #3]
ld2d {z0.d-z1.d}, p2/z, [x0,x0,lsl #3]
ld2d {z0.d, z1.d}, p7/z, [x0,x0,lsl #3]
LD2D {Z0.D, Z1.D}, P7/Z, [X0,X0,LSL #3]
ld2d {z0.d-z1.d}, p7/z, [x0,x0,lsl #3]
ld2d {z0.d, z1.d}, p0/z, [x3,x0,lsl #3]
LD2D {Z0.D, Z1.D}, P0/Z, [X3,X0,LSL #3]
ld2d {z0.d-z1.d}, p0/z, [x3,x0,lsl #3]
ld2d {z0.d, z1.d}, p0/z, [sp,x0,lsl #3]
LD2D {Z0.D, Z1.D}, P0/Z, [SP,X0,LSL #3]
ld2d {z0.d-z1.d}, p0/z, [sp,x0,lsl #3]
ld2d {z0.d, z1.d}, p0/z, [x0,x4,lsl #3]
LD2D {Z0.D, Z1.D}, P0/Z, [X0,X4,LSL #3]
ld2d {z0.d-z1.d}, p0/z, [x0,x4,lsl #3]
ld2d {z0.d, z1.d}, p0/z, [x0,x30,lsl #3]
LD2D {Z0.D, Z1.D}, P0/Z, [X0,X30,LSL #3]
ld2d {z0.d-z1.d}, p0/z, [x0,x30,lsl #3]
ld2d {z0.d, z1.d}, p0/z, [x0,#0]
LD2D {Z0.D, Z1.D}, P0/Z, [X0,#0]
ld2d {z0.d, z1.d}, p0/z, [x0,#0,mul vl]
ld2d {z0.d, z1.d}, p0/z, [x0]
ld2d {z0.d-z1.d}, p0/z, [x0,#0]
ld2d {z0.d-z1.d}, p0/z, [x0,#0,mul vl]
ld2d {z0.d-z1.d}, p0/z, [x0]
ld2d {z1.d, z2.d}, p0/z, [x0,#0]
LD2D {Z1.D, Z2.D}, P0/Z, [X0,#0]
ld2d {z1.d, z2.d}, p0/z, [x0,#0,mul vl]
ld2d {z1.d, z2.d}, p0/z, [x0]
ld2d {z1.d-z2.d}, p0/z, [x0,#0]
ld2d {z1.d-z2.d}, p0/z, [x0,#0,mul vl]
ld2d {z1.d-z2.d}, p0/z, [x0]
ld2d {z31.d, z0.d}, p0/z, [x0,#0]
LD2D {Z31.D, Z0.D}, P0/Z, [X0,#0]
ld2d {z31.d, z0.d}, p0/z, [x0,#0,mul vl]
ld2d {z31.d, z0.d}, p0/z, [x0]
ld2d {z0.d, z1.d}, p2/z, [x0,#0]
LD2D {Z0.D, Z1.D}, P2/Z, [X0,#0]
ld2d {z0.d, z1.d}, p2/z, [x0,#0,mul vl]
ld2d {z0.d, z1.d}, p2/z, [x0]
ld2d {z0.d-z1.d}, p2/z, [x0,#0]
ld2d {z0.d-z1.d}, p2/z, [x0,#0,mul vl]
ld2d {z0.d-z1.d}, p2/z, [x0]
ld2d {z0.d, z1.d}, p7/z, [x0,#0]
LD2D {Z0.D, Z1.D}, P7/Z, [X0,#0]
ld2d {z0.d, z1.d}, p7/z, [x0,#0,mul vl]
ld2d {z0.d, z1.d}, p7/z, [x0]
ld2d {z0.d-z1.d}, p7/z, [x0,#0]
ld2d {z0.d-z1.d}, p7/z, [x0,#0,mul vl]
ld2d {z0.d-z1.d}, p7/z, [x0]
ld2d {z0.d, z1.d}, p0/z, [x3,#0]
LD2D {Z0.D, Z1.D}, P0/Z, [X3,#0]
ld2d {z0.d, z1.d}, p0/z, [x3,#0,mul vl]
ld2d {z0.d, z1.d}, p0/z, [x3]
ld2d {z0.d-z1.d}, p0/z, [x3,#0]
ld2d {z0.d-z1.d}, p0/z, [x3,#0,mul vl]
ld2d {z0.d-z1.d}, p0/z, [x3]
ld2d {z0.d, z1.d}, p0/z, [sp,#0]
LD2D {Z0.D, Z1.D}, P0/Z, [SP,#0]
ld2d {z0.d, z1.d}, p0/z, [sp,#0,mul vl]
ld2d {z0.d, z1.d}, p0/z, [sp]
ld2d {z0.d-z1.d}, p0/z, [sp,#0]
ld2d {z0.d-z1.d}, p0/z, [sp,#0,mul vl]
ld2d {z0.d-z1.d}, p0/z, [sp]
ld2d {z0.d, z1.d}, p0/z, [x0,#14,mul vl]
LD2D {Z0.D, Z1.D}, P0/Z, [X0,#14,MUL VL]
ld2d {z0.d-z1.d}, p0/z, [x0,#14,mul vl]
ld2d {z0.d, z1.d}, p0/z, [x0,#-16,mul vl]
LD2D {Z0.D, Z1.D}, P0/Z, [X0,#-16,MUL VL]
ld2d {z0.d-z1.d}, p0/z, [x0,#-16,mul vl]
ld2d {z0.d, z1.d}, p0/z, [x0,#-14,mul vl]
LD2D {Z0.D, Z1.D}, P0/Z, [X0,#-14,MUL VL]
ld2d {z0.d-z1.d}, p0/z, [x0,#-14,mul vl]
ld2d {z0.d, z1.d}, p0/z, [x0,#-2,mul vl]
LD2D {Z0.D, Z1.D}, P0/Z, [X0,#-2,MUL VL]
ld2d {z0.d-z1.d}, p0/z, [x0,#-2,mul vl]
ld2h {z0.h, z1.h}, p0/z, [x0,x0,lsl #1]
LD2H {Z0.H, Z1.H}, P0/Z, [X0,X0,LSL #1]
ld2h {z0.h-z1.h}, p0/z, [x0,x0,lsl #1]
ld2h {z1.h, z2.h}, p0/z, [x0,x0,lsl #1]
LD2H {Z1.H, Z2.H}, P0/Z, [X0,X0,LSL #1]
ld2h {z1.h-z2.h}, p0/z, [x0,x0,lsl #1]
ld2h {z31.h, z0.h}, p0/z, [x0,x0,lsl #1]
LD2H {Z31.H, Z0.H}, P0/Z, [X0,X0,LSL #1]
ld2h {z0.h, z1.h}, p2/z, [x0,x0,lsl #1]
LD2H {Z0.H, Z1.H}, P2/Z, [X0,X0,LSL #1]
ld2h {z0.h-z1.h}, p2/z, [x0,x0,lsl #1]
ld2h {z0.h, z1.h}, p7/z, [x0,x0,lsl #1]
LD2H {Z0.H, Z1.H}, P7/Z, [X0,X0,LSL #1]
ld2h {z0.h-z1.h}, p7/z, [x0,x0,lsl #1]
ld2h {z0.h, z1.h}, p0/z, [x3,x0,lsl #1]
LD2H {Z0.H, Z1.H}, P0/Z, [X3,X0,LSL #1]
ld2h {z0.h-z1.h}, p0/z, [x3,x0,lsl #1]
ld2h {z0.h, z1.h}, p0/z, [sp,x0,lsl #1]
LD2H {Z0.H, Z1.H}, P0/Z, [SP,X0,LSL #1]
ld2h {z0.h-z1.h}, p0/z, [sp,x0,lsl #1]
ld2h {z0.h, z1.h}, p0/z, [x0,x4,lsl #1]
LD2H {Z0.H, Z1.H}, P0/Z, [X0,X4,LSL #1]
ld2h {z0.h-z1.h}, p0/z, [x0,x4,lsl #1]
ld2h {z0.h, z1.h}, p0/z, [x0,x30,lsl #1]
LD2H {Z0.H, Z1.H}, P0/Z, [X0,X30,LSL #1]
ld2h {z0.h-z1.h}, p0/z, [x0,x30,lsl #1]
ld2h {z0.h, z1.h}, p0/z, [x0,#0]
LD2H {Z0.H, Z1.H}, P0/Z, [X0,#0]
ld2h {z0.h, z1.h}, p0/z, [x0,#0,mul vl]
ld2h {z0.h, z1.h}, p0/z, [x0]
ld2h {z0.h-z1.h}, p0/z, [x0,#0]
ld2h {z0.h-z1.h}, p0/z, [x0,#0,mul vl]
ld2h {z0.h-z1.h}, p0/z, [x0]
ld2h {z1.h, z2.h}, p0/z, [x0,#0]
LD2H {Z1.H, Z2.H}, P0/Z, [X0,#0]
ld2h {z1.h, z2.h}, p0/z, [x0,#0,mul vl]
ld2h {z1.h, z2.h}, p0/z, [x0]
ld2h {z1.h-z2.h}, p0/z, [x0,#0]
ld2h {z1.h-z2.h}, p0/z, [x0,#0,mul vl]
ld2h {z1.h-z2.h}, p0/z, [x0]
ld2h {z31.h, z0.h}, p0/z, [x0,#0]
LD2H {Z31.H, Z0.H}, P0/Z, [X0,#0]
ld2h {z31.h, z0.h}, p0/z, [x0,#0,mul vl]
ld2h {z31.h, z0.h}, p0/z, [x0]
ld2h {z0.h, z1.h}, p2/z, [x0,#0]
LD2H {Z0.H, Z1.H}, P2/Z, [X0,#0]
ld2h {z0.h, z1.h}, p2/z, [x0,#0,mul vl]
ld2h {z0.h, z1.h}, p2/z, [x0]
ld2h {z0.h-z1.h}, p2/z, [x0,#0]
ld2h {z0.h-z1.h}, p2/z, [x0,#0,mul vl]
ld2h {z0.h-z1.h}, p2/z, [x0]
ld2h {z0.h, z1.h}, p7/z, [x0,#0]
LD2H {Z0.H, Z1.H}, P7/Z, [X0,#0]
ld2h {z0.h, z1.h}, p7/z, [x0,#0,mul vl]
ld2h {z0.h, z1.h}, p7/z, [x0]
ld2h {z0.h-z1.h}, p7/z, [x0,#0]
ld2h {z0.h-z1.h}, p7/z, [x0,#0,mul vl]
ld2h {z0.h-z1.h}, p7/z, [x0]
ld2h {z0.h, z1.h}, p0/z, [x3,#0]
LD2H {Z0.H, Z1.H}, P0/Z, [X3,#0]
ld2h {z0.h, z1.h}, p0/z, [x3,#0,mul vl]
ld2h {z0.h, z1.h}, p0/z, [x3]
ld2h {z0.h-z1.h}, p0/z, [x3,#0]
ld2h {z0.h-z1.h}, p0/z, [x3,#0,mul vl]
ld2h {z0.h-z1.h}, p0/z, [x3]
ld2h {z0.h, z1.h}, p0/z, [sp,#0]
LD2H {Z0.H, Z1.H}, P0/Z, [SP,#0]
ld2h {z0.h, z1.h}, p0/z, [sp,#0,mul vl]
ld2h {z0.h, z1.h}, p0/z, [sp]
ld2h {z0.h-z1.h}, p0/z, [sp,#0]
ld2h {z0.h-z1.h}, p0/z, [sp,#0,mul vl]
ld2h {z0.h-z1.h}, p0/z, [sp]
ld2h {z0.h, z1.h}, p0/z, [x0,#14,mul vl]
LD2H {Z0.H, Z1.H}, P0/Z, [X0,#14,MUL VL]
ld2h {z0.h-z1.h}, p0/z, [x0,#14,mul vl]
ld2h {z0.h, z1.h}, p0/z, [x0,#-16,mul vl]
LD2H {Z0.H, Z1.H}, P0/Z, [X0,#-16,MUL VL]
ld2h {z0.h-z1.h}, p0/z, [x0,#-16,mul vl]
ld2h {z0.h, z1.h}, p0/z, [x0,#-14,mul vl]
LD2H {Z0.H, Z1.H}, P0/Z, [X0,#-14,MUL VL]
ld2h {z0.h-z1.h}, p0/z, [x0,#-14,mul vl]
ld2h {z0.h, z1.h}, p0/z, [x0,#-2,mul vl]
LD2H {Z0.H, Z1.H}, P0/Z, [X0,#-2,MUL VL]
ld2h {z0.h-z1.h}, p0/z, [x0,#-2,mul vl]
ld2w {z0.s, z1.s}, p0/z, [x0,x0,lsl #2]
LD2W {Z0.S, Z1.S}, P0/Z, [X0,X0,LSL #2]
ld2w {z0.s-z1.s}, p0/z, [x0,x0,lsl #2]
ld2w {z1.s, z2.s}, p0/z, [x0,x0,lsl #2]
LD2W {Z1.S, Z2.S}, P0/Z, [X0,X0,LSL #2]
ld2w {z1.s-z2.s}, p0/z, [x0,x0,lsl #2]
ld2w {z31.s, z0.s}, p0/z, [x0,x0,lsl #2]
LD2W {Z31.S, Z0.S}, P0/Z, [X0,X0,LSL #2]
ld2w {z0.s, z1.s}, p2/z, [x0,x0,lsl #2]
LD2W {Z0.S, Z1.S}, P2/Z, [X0,X0,LSL #2]
ld2w {z0.s-z1.s}, p2/z, [x0,x0,lsl #2]
ld2w {z0.s, z1.s}, p7/z, [x0,x0,lsl #2]
LD2W {Z0.S, Z1.S}, P7/Z, [X0,X0,LSL #2]
ld2w {z0.s-z1.s}, p7/z, [x0,x0,lsl #2]
ld2w {z0.s, z1.s}, p0/z, [x3,x0,lsl #2]
LD2W {Z0.S, Z1.S}, P0/Z, [X3,X0,LSL #2]
ld2w {z0.s-z1.s}, p0/z, [x3,x0,lsl #2]
ld2w {z0.s, z1.s}, p0/z, [sp,x0,lsl #2]
LD2W {Z0.S, Z1.S}, P0/Z, [SP,X0,LSL #2]
ld2w {z0.s-z1.s}, p0/z, [sp,x0,lsl #2]
ld2w {z0.s, z1.s}, p0/z, [x0,x4,lsl #2]
LD2W {Z0.S, Z1.S}, P0/Z, [X0,X4,LSL #2]
ld2w {z0.s-z1.s}, p0/z, [x0,x4,lsl #2]
ld2w {z0.s, z1.s}, p0/z, [x0,x30,lsl #2]
LD2W {Z0.S, Z1.S}, P0/Z, [X0,X30,LSL #2]
ld2w {z0.s-z1.s}, p0/z, [x0,x30,lsl #2]
ld2w {z0.s, z1.s}, p0/z, [x0,#0]
LD2W {Z0.S, Z1.S}, P0/Z, [X0,#0]
ld2w {z0.s, z1.s}, p0/z, [x0,#0,mul vl]
ld2w {z0.s, z1.s}, p0/z, [x0]
ld2w {z0.s-z1.s}, p0/z, [x0,#0]
ld2w {z0.s-z1.s}, p0/z, [x0,#0,mul vl]
ld2w {z0.s-z1.s}, p0/z, [x0]
ld2w {z1.s, z2.s}, p0/z, [x0,#0]
LD2W {Z1.S, Z2.S}, P0/Z, [X0,#0]
ld2w {z1.s, z2.s}, p0/z, [x0,#0,mul vl]
ld2w {z1.s, z2.s}, p0/z, [x0]
ld2w {z1.s-z2.s}, p0/z, [x0,#0]
ld2w {z1.s-z2.s}, p0/z, [x0,#0,mul vl]
ld2w {z1.s-z2.s}, p0/z, [x0]
ld2w {z31.s, z0.s}, p0/z, [x0,#0]
LD2W {Z31.S, Z0.S}, P0/Z, [X0,#0]
ld2w {z31.s, z0.s}, p0/z, [x0,#0,mul vl]
ld2w {z31.s, z0.s}, p0/z, [x0]
ld2w {z0.s, z1.s}, p2/z, [x0,#0]
LD2W {Z0.S, Z1.S}, P2/Z, [X0,#0]
ld2w {z0.s, z1.s}, p2/z, [x0,#0,mul vl]
ld2w {z0.s, z1.s}, p2/z, [x0]
ld2w {z0.s-z1.s}, p2/z, [x0,#0]
ld2w {z0.s-z1.s}, p2/z, [x0,#0,mul vl]
ld2w {z0.s-z1.s}, p2/z, [x0]
ld2w {z0.s, z1.s}, p7/z, [x0,#0]
LD2W {Z0.S, Z1.S}, P7/Z, [X0,#0]
ld2w {z0.s, z1.s}, p7/z, [x0,#0,mul vl]
ld2w {z0.s, z1.s}, p7/z, [x0]
ld2w {z0.s-z1.s}, p7/z, [x0,#0]
ld2w {z0.s-z1.s}, p7/z, [x0,#0,mul vl]
ld2w {z0.s-z1.s}, p7/z, [x0]
ld2w {z0.s, z1.s}, p0/z, [x3,#0]
LD2W {Z0.S, Z1.S}, P0/Z, [X3,#0]
ld2w {z0.s, z1.s}, p0/z, [x3,#0,mul vl]
ld2w {z0.s, z1.s}, p0/z, [x3]
ld2w {z0.s-z1.s}, p0/z, [x3,#0]
ld2w {z0.s-z1.s}, p0/z, [x3,#0,mul vl]
ld2w {z0.s-z1.s}, p0/z, [x3]
ld2w {z0.s, z1.s}, p0/z, [sp,#0]
LD2W {Z0.S, Z1.S}, P0/Z, [SP,#0]
ld2w {z0.s, z1.s}, p0/z, [sp,#0,mul vl]
ld2w {z0.s, z1.s}, p0/z, [sp]
ld2w {z0.s-z1.s}, p0/z, [sp,#0]
ld2w {z0.s-z1.s}, p0/z, [sp,#0,mul vl]
ld2w {z0.s-z1.s}, p0/z, [sp]
ld2w {z0.s, z1.s}, p0/z, [x0,#14,mul vl]
LD2W {Z0.S, Z1.S}, P0/Z, [X0,#14,MUL VL]
ld2w {z0.s-z1.s}, p0/z, [x0,#14,mul vl]
ld2w {z0.s, z1.s}, p0/z, [x0,#-16,mul vl]
LD2W {Z0.S, Z1.S}, P0/Z, [X0,#-16,MUL VL]
ld2w {z0.s-z1.s}, p0/z, [x0,#-16,mul vl]
ld2w {z0.s, z1.s}, p0/z, [x0,#-14,mul vl]
LD2W {Z0.S, Z1.S}, P0/Z, [X0,#-14,MUL VL]
ld2w {z0.s-z1.s}, p0/z, [x0,#-14,mul vl]
ld2w {z0.s, z1.s}, p0/z, [x0,#-2,mul vl]
LD2W {Z0.S, Z1.S}, P0/Z, [X0,#-2,MUL VL]
ld2w {z0.s-z1.s}, p0/z, [x0,#-2,mul vl]
ld3b {z0.b-z2.b}, p0/z, [x0,x0]
LD3B {Z0.B-Z2.B}, P0/Z, [X0,X0]
ld3b {z0.b-z2.b}, p0/z, [x0,x0,lsl #0]
ld3b {z0.b, z1.b, z2.b}, p0/z, [x0,x0]
ld3b {z0.b, z1.b, z2.b}, p0/z, [x0,x0,lsl #0]
ld3b {z1.b-z3.b}, p0/z, [x0,x0]
LD3B {Z1.B-Z3.B}, P0/Z, [X0,X0]
ld3b {z1.b-z3.b}, p0/z, [x0,x0,lsl #0]
ld3b {z1.b, z2.b, z3.b}, p0/z, [x0,x0]
ld3b {z1.b, z2.b, z3.b}, p0/z, [x0,x0,lsl #0]
ld3b {z31.b, z0.b, z1.b}, p0/z, [x0,x0]
LD3B {Z31.B, Z0.B, Z1.B}, P0/Z, [X0,X0]
ld3b {z31.b, z0.b, z1.b}, p0/z, [x0,x0,lsl #0]
ld3b {z0.b-z2.b}, p2/z, [x0,x0]
LD3B {Z0.B-Z2.B}, P2/Z, [X0,X0]
ld3b {z0.b-z2.b}, p2/z, [x0,x0,lsl #0]
ld3b {z0.b, z1.b, z2.b}, p2/z, [x0,x0]
ld3b {z0.b, z1.b, z2.b}, p2/z, [x0,x0,lsl #0]
ld3b {z0.b-z2.b}, p7/z, [x0,x0]
LD3B {Z0.B-Z2.B}, P7/Z, [X0,X0]
ld3b {z0.b-z2.b}, p7/z, [x0,x0,lsl #0]
ld3b {z0.b, z1.b, z2.b}, p7/z, [x0,x0]
ld3b {z0.b, z1.b, z2.b}, p7/z, [x0,x0,lsl #0]
ld3b {z0.b-z2.b}, p0/z, [x3,x0]
LD3B {Z0.B-Z2.B}, P0/Z, [X3,X0]
ld3b {z0.b-z2.b}, p0/z, [x3,x0,lsl #0]
ld3b {z0.b, z1.b, z2.b}, p0/z, [x3,x0]
ld3b {z0.b, z1.b, z2.b}, p0/z, [x3,x0,lsl #0]
ld3b {z0.b-z2.b}, p0/z, [sp,x0]
LD3B {Z0.B-Z2.B}, P0/Z, [SP,X0]
ld3b {z0.b-z2.b}, p0/z, [sp,x0,lsl #0]
ld3b {z0.b, z1.b, z2.b}, p0/z, [sp,x0]
ld3b {z0.b, z1.b, z2.b}, p0/z, [sp,x0,lsl #0]
ld3b {z0.b-z2.b}, p0/z, [x0,x4]
LD3B {Z0.B-Z2.B}, P0/Z, [X0,X4]
ld3b {z0.b-z2.b}, p0/z, [x0,x4,lsl #0]
ld3b {z0.b, z1.b, z2.b}, p0/z, [x0,x4]
ld3b {z0.b, z1.b, z2.b}, p0/z, [x0,x4,lsl #0]
ld3b {z0.b-z2.b}, p0/z, [x0,x30]
LD3B {Z0.B-Z2.B}, P0/Z, [X0,X30]
ld3b {z0.b-z2.b}, p0/z, [x0,x30,lsl #0]
ld3b {z0.b, z1.b, z2.b}, p0/z, [x0,x30]
ld3b {z0.b, z1.b, z2.b}, p0/z, [x0,x30,lsl #0]
ld3b {z0.b-z2.b}, p0/z, [x0,#0]
LD3B {Z0.B-Z2.B}, P0/Z, [X0,#0]
ld3b {z0.b-z2.b}, p0/z, [x0,#0,mul vl]
ld3b {z0.b-z2.b}, p0/z, [x0]
ld3b {z0.b, z1.b, z2.b}, p0/z, [x0,#0]
ld3b {z0.b, z1.b, z2.b}, p0/z, [x0,#0,mul vl]
ld3b {z0.b, z1.b, z2.b}, p0/z, [x0]
ld3b {z1.b-z3.b}, p0/z, [x0,#0]
LD3B {Z1.B-Z3.B}, P0/Z, [X0,#0]
ld3b {z1.b-z3.b}, p0/z, [x0,#0,mul vl]
ld3b {z1.b-z3.b}, p0/z, [x0]
ld3b {z1.b, z2.b, z3.b}, p0/z, [x0,#0]
ld3b {z1.b, z2.b, z3.b}, p0/z, [x0,#0,mul vl]
ld3b {z1.b, z2.b, z3.b}, p0/z, [x0]
ld3b {z31.b, z0.b, z1.b}, p0/z, [x0,#0]
LD3B {Z31.B, Z0.B, Z1.B}, P0/Z, [X0,#0]
ld3b {z31.b, z0.b, z1.b}, p0/z, [x0,#0,mul vl]
ld3b {z31.b, z0.b, z1.b}, p0/z, [x0]
ld3b {z0.b-z2.b}, p2/z, [x0,#0]
LD3B {Z0.B-Z2.B}, P2/Z, [X0,#0]
ld3b {z0.b-z2.b}, p2/z, [x0,#0,mul vl]
ld3b {z0.b-z2.b}, p2/z, [x0]
ld3b {z0.b, z1.b, z2.b}, p2/z, [x0,#0]
ld3b {z0.b, z1.b, z2.b}, p2/z, [x0,#0,mul vl]
ld3b {z0.b, z1.b, z2.b}, p2/z, [x0]
ld3b {z0.b-z2.b}, p7/z, [x0,#0]
LD3B {Z0.B-Z2.B}, P7/Z, [X0,#0]
ld3b {z0.b-z2.b}, p7/z, [x0,#0,mul vl]
ld3b {z0.b-z2.b}, p7/z, [x0]
ld3b {z0.b, z1.b, z2.b}, p7/z, [x0,#0]
ld3b {z0.b, z1.b, z2.b}, p7/z, [x0,#0,mul vl]
ld3b {z0.b, z1.b, z2.b}, p7/z, [x0]
ld3b {z0.b-z2.b}, p0/z, [x3,#0]
LD3B {Z0.B-Z2.B}, P0/Z, [X3,#0]
ld3b {z0.b-z2.b}, p0/z, [x3,#0,mul vl]
ld3b {z0.b-z2.b}, p0/z, [x3]
ld3b {z0.b, z1.b, z2.b}, p0/z, [x3,#0]
ld3b {z0.b, z1.b, z2.b}, p0/z, [x3,#0,mul vl]
ld3b {z0.b, z1.b, z2.b}, p0/z, [x3]
ld3b {z0.b-z2.b}, p0/z, [sp,#0]
LD3B {Z0.B-Z2.B}, P0/Z, [SP,#0]
ld3b {z0.b-z2.b}, p0/z, [sp,#0,mul vl]
ld3b {z0.b-z2.b}, p0/z, [sp]
ld3b {z0.b, z1.b, z2.b}, p0/z, [sp,#0]
ld3b {z0.b, z1.b, z2.b}, p0/z, [sp,#0,mul vl]
ld3b {z0.b, z1.b, z2.b}, p0/z, [sp]
ld3b {z0.b-z2.b}, p0/z, [x0,#21,mul vl]
LD3B {Z0.B-Z2.B}, P0/Z, [X0,#21,MUL VL]
ld3b {z0.b, z1.b, z2.b}, p0/z, [x0,#21,mul vl]
ld3b {z0.b-z2.b}, p0/z, [x0,#-24,mul vl]
LD3B {Z0.B-Z2.B}, P0/Z, [X0,#-24,MUL VL]
ld3b {z0.b, z1.b, z2.b}, p0/z, [x0,#-24,mul vl]
ld3b {z0.b-z2.b}, p0/z, [x0,#-21,mul vl]
LD3B {Z0.B-Z2.B}, P0/Z, [X0,#-21,MUL VL]
ld3b {z0.b, z1.b, z2.b}, p0/z, [x0,#-21,mul vl]
ld3b {z0.b-z2.b}, p0/z, [x0,#-3,mul vl]
LD3B {Z0.B-Z2.B}, P0/Z, [X0,#-3,MUL VL]
ld3b {z0.b, z1.b, z2.b}, p0/z, [x0,#-3,mul vl]
ld3d {z0.d-z2.d}, p0/z, [x0,x0,lsl #3]
LD3D {Z0.D-Z2.D}, P0/Z, [X0,X0,LSL #3]
ld3d {z0.d, z1.d, z2.d}, p0/z, [x0,x0,lsl #3]
ld3d {z1.d-z3.d}, p0/z, [x0,x0,lsl #3]
LD3D {Z1.D-Z3.D}, P0/Z, [X0,X0,LSL #3]
ld3d {z1.d, z2.d, z3.d}, p0/z, [x0,x0,lsl #3]
ld3d {z31.d, z0.d, z1.d}, p0/z, [x0,x0,lsl #3]
LD3D {Z31.D, Z0.D, Z1.D}, P0/Z, [X0,X0,LSL #3]
ld3d {z0.d-z2.d}, p2/z, [x0,x0,lsl #3]
LD3D {Z0.D-Z2.D}, P2/Z, [X0,X0,LSL #3]
ld3d {z0.d, z1.d, z2.d}, p2/z, [x0,x0,lsl #3]
ld3d {z0.d-z2.d}, p7/z, [x0,x0,lsl #3]
LD3D {Z0.D-Z2.D}, P7/Z, [X0,X0,LSL #3]
ld3d {z0.d, z1.d, z2.d}, p7/z, [x0,x0,lsl #3]
ld3d {z0.d-z2.d}, p0/z, [x3,x0,lsl #3]
LD3D {Z0.D-Z2.D}, P0/Z, [X3,X0,LSL #3]
ld3d {z0.d, z1.d, z2.d}, p0/z, [x3,x0,lsl #3]
ld3d {z0.d-z2.d}, p0/z, [sp,x0,lsl #3]
LD3D {Z0.D-Z2.D}, P0/Z, [SP,X0,LSL #3]
ld3d {z0.d, z1.d, z2.d}, p0/z, [sp,x0,lsl #3]
ld3d {z0.d-z2.d}, p0/z, [x0,x4,lsl #3]
LD3D {Z0.D-Z2.D}, P0/Z, [X0,X4,LSL #3]
ld3d {z0.d, z1.d, z2.d}, p0/z, [x0,x4,lsl #3]
ld3d {z0.d-z2.d}, p0/z, [x0,x30,lsl #3]
LD3D {Z0.D-Z2.D}, P0/Z, [X0,X30,LSL #3]
ld3d {z0.d, z1.d, z2.d}, p0/z, [x0,x30,lsl #3]
ld3d {z0.d-z2.d}, p0/z, [x0,#0]
LD3D {Z0.D-Z2.D}, P0/Z, [X0,#0]
ld3d {z0.d-z2.d}, p0/z, [x0,#0,mul vl]
ld3d {z0.d-z2.d}, p0/z, [x0]
ld3d {z0.d, z1.d, z2.d}, p0/z, [x0,#0]
ld3d {z0.d, z1.d, z2.d}, p0/z, [x0,#0,mul vl]
ld3d {z0.d, z1.d, z2.d}, p0/z, [x0]
ld3d {z1.d-z3.d}, p0/z, [x0,#0]
LD3D {Z1.D-Z3.D}, P0/Z, [X0,#0]
ld3d {z1.d-z3.d}, p0/z, [x0,#0,mul vl]
ld3d {z1.d-z3.d}, p0/z, [x0]
ld3d {z1.d, z2.d, z3.d}, p0/z, [x0,#0]
ld3d {z1.d, z2.d, z3.d}, p0/z, [x0,#0,mul vl]
ld3d {z1.d, z2.d, z3.d}, p0/z, [x0]
ld3d {z31.d, z0.d, z1.d}, p0/z, [x0,#0]
LD3D {Z31.D, Z0.D, Z1.D}, P0/Z, [X0,#0]
ld3d {z31.d, z0.d, z1.d}, p0/z, [x0,#0,mul vl]
ld3d {z31.d, z0.d, z1.d}, p0/z, [x0]
ld3d {z0.d-z2.d}, p2/z, [x0,#0]
LD3D {Z0.D-Z2.D}, P2/Z, [X0,#0]
ld3d {z0.d-z2.d}, p2/z, [x0,#0,mul vl]
ld3d {z0.d-z2.d}, p2/z, [x0]
ld3d {z0.d, z1.d, z2.d}, p2/z, [x0,#0]
ld3d {z0.d, z1.d, z2.d}, p2/z, [x0,#0,mul vl]
ld3d {z0.d, z1.d, z2.d}, p2/z, [x0]
ld3d {z0.d-z2.d}, p7/z, [x0,#0]
LD3D {Z0.D-Z2.D}, P7/Z, [X0,#0]
ld3d {z0.d-z2.d}, p7/z, [x0,#0,mul vl]
ld3d {z0.d-z2.d}, p7/z, [x0]
ld3d {z0.d, z1.d, z2.d}, p7/z, [x0,#0]
ld3d {z0.d, z1.d, z2.d}, p7/z, [x0,#0,mul vl]
ld3d {z0.d, z1.d, z2.d}, p7/z, [x0]
ld3d {z0.d-z2.d}, p0/z, [x3,#0]
LD3D {Z0.D-Z2.D}, P0/Z, [X3,#0]
ld3d {z0.d-z2.d}, p0/z, [x3,#0,mul vl]
ld3d {z0.d-z2.d}, p0/z, [x3]
ld3d {z0.d, z1.d, z2.d}, p0/z, [x3,#0]
ld3d {z0.d, z1.d, z2.d}, p0/z, [x3,#0,mul vl]
ld3d {z0.d, z1.d, z2.d}, p0/z, [x3]
ld3d {z0.d-z2.d}, p0/z, [sp,#0]
LD3D {Z0.D-Z2.D}, P0/Z, [SP,#0]
ld3d {z0.d-z2.d}, p0/z, [sp,#0,mul vl]
ld3d {z0.d-z2.d}, p0/z, [sp]
ld3d {z0.d, z1.d, z2.d}, p0/z, [sp,#0]
ld3d {z0.d, z1.d, z2.d}, p0/z, [sp,#0,mul vl]
ld3d {z0.d, z1.d, z2.d}, p0/z, [sp]
ld3d {z0.d-z2.d}, p0/z, [x0,#21,mul vl]
LD3D {Z0.D-Z2.D}, P0/Z, [X0,#21,MUL VL]
ld3d {z0.d, z1.d, z2.d}, p0/z, [x0,#21,mul vl]
ld3d {z0.d-z2.d}, p0/z, [x0,#-24,mul vl]
LD3D {Z0.D-Z2.D}, P0/Z, [X0,#-24,MUL VL]
ld3d {z0.d, z1.d, z2.d}, p0/z, [x0,#-24,mul vl]
ld3d {z0.d-z2.d}, p0/z, [x0,#-21,mul vl]
LD3D {Z0.D-Z2.D}, P0/Z, [X0,#-21,MUL VL]
ld3d {z0.d, z1.d, z2.d}, p0/z, [x0,#-21,mul vl]
ld3d {z0.d-z2.d}, p0/z, [x0,#-3,mul vl]
LD3D {Z0.D-Z2.D}, P0/Z, [X0,#-3,MUL VL]
ld3d {z0.d, z1.d, z2.d}, p0/z, [x0,#-3,mul vl]
ld3h {z0.h-z2.h}, p0/z, [x0,x0,lsl #1]
LD3H {Z0.H-Z2.H}, P0/Z, [X0,X0,LSL #1]
ld3h {z0.h, z1.h, z2.h}, p0/z, [x0,x0,lsl #1]
ld3h {z1.h-z3.h}, p0/z, [x0,x0,lsl #1]
LD3H {Z1.H-Z3.H}, P0/Z, [X0,X0,LSL #1]
ld3h {z1.h, z2.h, z3.h}, p0/z, [x0,x0,lsl #1]
ld3h {z31.h, z0.h, z1.h}, p0/z, [x0,x0,lsl #1]
LD3H {Z31.H, Z0.H, Z1.H}, P0/Z, [X0,X0,LSL #1]
ld3h {z0.h-z2.h}, p2/z, [x0,x0,lsl #1]
LD3H {Z0.H-Z2.H}, P2/Z, [X0,X0,LSL #1]
ld3h {z0.h, z1.h, z2.h}, p2/z, [x0,x0,lsl #1]
ld3h {z0.h-z2.h}, p7/z, [x0,x0,lsl #1]
LD3H {Z0.H-Z2.H}, P7/Z, [X0,X0,LSL #1]
ld3h {z0.h, z1.h, z2.h}, p7/z, [x0,x0,lsl #1]
ld3h {z0.h-z2.h}, p0/z, [x3,x0,lsl #1]
LD3H {Z0.H-Z2.H}, P0/Z, [X3,X0,LSL #1]
ld3h {z0.h, z1.h, z2.h}, p0/z, [x3,x0,lsl #1]
ld3h {z0.h-z2.h}, p0/z, [sp,x0,lsl #1]
LD3H {Z0.H-Z2.H}, P0/Z, [SP,X0,LSL #1]
ld3h {z0.h, z1.h, z2.h}, p0/z, [sp,x0,lsl #1]
ld3h {z0.h-z2.h}, p0/z, [x0,x4,lsl #1]
LD3H {Z0.H-Z2.H}, P0/Z, [X0,X4,LSL #1]
ld3h {z0.h, z1.h, z2.h}, p0/z, [x0,x4,lsl #1]
ld3h {z0.h-z2.h}, p0/z, [x0,x30,lsl #1]
LD3H {Z0.H-Z2.H}, P0/Z, [X0,X30,LSL #1]
ld3h {z0.h, z1.h, z2.h}, p0/z, [x0,x30,lsl #1]
ld3h {z0.h-z2.h}, p0/z, [x0,#0]
LD3H {Z0.H-Z2.H}, P0/Z, [X0,#0]
ld3h {z0.h-z2.h}, p0/z, [x0,#0,mul vl]
ld3h {z0.h-z2.h}, p0/z, [x0]
ld3h {z0.h, z1.h, z2.h}, p0/z, [x0,#0]
ld3h {z0.h, z1.h, z2.h}, p0/z, [x0,#0,mul vl]
ld3h {z0.h, z1.h, z2.h}, p0/z, [x0]
ld3h {z1.h-z3.h}, p0/z, [x0,#0]
LD3H {Z1.H-Z3.H}, P0/Z, [X0,#0]
ld3h {z1.h-z3.h}, p0/z, [x0,#0,mul vl]
ld3h {z1.h-z3.h}, p0/z, [x0]
ld3h {z1.h, z2.h, z3.h}, p0/z, [x0,#0]
ld3h {z1.h, z2.h, z3.h}, p0/z, [x0,#0,mul vl]
ld3h {z1.h, z2.h, z3.h}, p0/z, [x0]
ld3h {z31.h, z0.h, z1.h}, p0/z, [x0,#0]
LD3H {Z31.H, Z0.H, Z1.H}, P0/Z, [X0,#0]
ld3h {z31.h, z0.h, z1.h}, p0/z, [x0,#0,mul vl]
ld3h {z31.h, z0.h, z1.h}, p0/z, [x0]
ld3h {z0.h-z2.h}, p2/z, [x0,#0]
LD3H {Z0.H-Z2.H}, P2/Z, [X0,#0]
ld3h {z0.h-z2.h}, p2/z, [x0,#0,mul vl]
ld3h {z0.h-z2.h}, p2/z, [x0]
ld3h {z0.h, z1.h, z2.h}, p2/z, [x0,#0]
ld3h {z0.h, z1.h, z2.h}, p2/z, [x0,#0,mul vl]
ld3h {z0.h, z1.h, z2.h}, p2/z, [x0]
ld3h {z0.h-z2.h}, p7/z, [x0,#0]
LD3H {Z0.H-Z2.H}, P7/Z, [X0,#0]
ld3h {z0.h-z2.h}, p7/z, [x0,#0,mul vl]
ld3h {z0.h-z2.h}, p7/z, [x0]
ld3h {z0.h, z1.h, z2.h}, p7/z, [x0,#0]
ld3h {z0.h, z1.h, z2.h}, p7/z, [x0,#0,mul vl]
ld3h {z0.h, z1.h, z2.h}, p7/z, [x0]
ld3h {z0.h-z2.h}, p0/z, [x3,#0]
LD3H {Z0.H-Z2.H}, P0/Z, [X3,#0]
ld3h {z0.h-z2.h}, p0/z, [x3,#0,mul vl]
ld3h {z0.h-z2.h}, p0/z, [x3]
ld3h {z0.h, z1.h, z2.h}, p0/z, [x3,#0]
ld3h {z0.h, z1.h, z2.h}, p0/z, [x3,#0,mul vl]
ld3h {z0.h, z1.h, z2.h}, p0/z, [x3]
ld3h {z0.h-z2.h}, p0/z, [sp,#0]
LD3H {Z0.H-Z2.H}, P0/Z, [SP,#0]
ld3h {z0.h-z2.h}, p0/z, [sp,#0,mul vl]
ld3h {z0.h-z2.h}, p0/z, [sp]
ld3h {z0.h, z1.h, z2.h}, p0/z, [sp,#0]
ld3h {z0.h, z1.h, z2.h}, p0/z, [sp,#0,mul vl]
ld3h {z0.h, z1.h, z2.h}, p0/z, [sp]
ld3h {z0.h-z2.h}, p0/z, [x0,#21,mul vl]
LD3H {Z0.H-Z2.H}, P0/Z, [X0,#21,MUL VL]
ld3h {z0.h, z1.h, z2.h}, p0/z, [x0,#21,mul vl]
ld3h {z0.h-z2.h}, p0/z, [x0,#-24,mul vl]
LD3H {Z0.H-Z2.H}, P0/Z, [X0,#-24,MUL VL]
ld3h {z0.h, z1.h, z2.h}, p0/z, [x0,#-24,mul vl]
ld3h {z0.h-z2.h}, p0/z, [x0,#-21,mul vl]
LD3H {Z0.H-Z2.H}, P0/Z, [X0,#-21,MUL VL]
ld3h {z0.h, z1.h, z2.h}, p0/z, [x0,#-21,mul vl]
ld3h {z0.h-z2.h}, p0/z, [x0,#-3,mul vl]
LD3H {Z0.H-Z2.H}, P0/Z, [X0,#-3,MUL VL]
ld3h {z0.h, z1.h, z2.h}, p0/z, [x0,#-3,mul vl]
ld3w {z0.s-z2.s}, p0/z, [x0,x0,lsl #2]
LD3W {Z0.S-Z2.S}, P0/Z, [X0,X0,LSL #2]
ld3w {z0.s, z1.s, z2.s}, p0/z, [x0,x0,lsl #2]
ld3w {z1.s-z3.s}, p0/z, [x0,x0,lsl #2]
LD3W {Z1.S-Z3.S}, P0/Z, [X0,X0,LSL #2]
ld3w {z1.s, z2.s, z3.s}, p0/z, [x0,x0,lsl #2]
ld3w {z31.s, z0.s, z1.s}, p0/z, [x0,x0,lsl #2]
LD3W {Z31.S, Z0.S, Z1.S}, P0/Z, [X0,X0,LSL #2]
ld3w {z0.s-z2.s}, p2/z, [x0,x0,lsl #2]
LD3W {Z0.S-Z2.S}, P2/Z, [X0,X0,LSL #2]
ld3w {z0.s, z1.s, z2.s}, p2/z, [x0,x0,lsl #2]
ld3w {z0.s-z2.s}, p7/z, [x0,x0,lsl #2]
LD3W {Z0.S-Z2.S}, P7/Z, [X0,X0,LSL #2]
ld3w {z0.s, z1.s, z2.s}, p7/z, [x0,x0,lsl #2]
ld3w {z0.s-z2.s}, p0/z, [x3,x0,lsl #2]
LD3W {Z0.S-Z2.S}, P0/Z, [X3,X0,LSL #2]
ld3w {z0.s, z1.s, z2.s}, p0/z, [x3,x0,lsl #2]
ld3w {z0.s-z2.s}, p0/z, [sp,x0,lsl #2]
LD3W {Z0.S-Z2.S}, P0/Z, [SP,X0,LSL #2]
ld3w {z0.s, z1.s, z2.s}, p0/z, [sp,x0,lsl #2]
ld3w {z0.s-z2.s}, p0/z, [x0,x4,lsl #2]
LD3W {Z0.S-Z2.S}, P0/Z, [X0,X4,LSL #2]
ld3w {z0.s, z1.s, z2.s}, p0/z, [x0,x4,lsl #2]
ld3w {z0.s-z2.s}, p0/z, [x0,x30,lsl #2]
LD3W {Z0.S-Z2.S}, P0/Z, [X0,X30,LSL #2]
ld3w {z0.s, z1.s, z2.s}, p0/z, [x0,x30,lsl #2]
ld3w {z0.s-z2.s}, p0/z, [x0,#0]
LD3W {Z0.S-Z2.S}, P0/Z, [X0,#0]
ld3w {z0.s-z2.s}, p0/z, [x0,#0,mul vl]
ld3w {z0.s-z2.s}, p0/z, [x0]
ld3w {z0.s, z1.s, z2.s}, p0/z, [x0,#0]
ld3w {z0.s, z1.s, z2.s}, p0/z, [x0,#0,mul vl]
ld3w {z0.s, z1.s, z2.s}, p0/z, [x0]
ld3w {z1.s-z3.s}, p0/z, [x0,#0]
LD3W {Z1.S-Z3.S}, P0/Z, [X0,#0]
ld3w {z1.s-z3.s}, p0/z, [x0,#0,mul vl]
ld3w {z1.s-z3.s}, p0/z, [x0]
ld3w {z1.s, z2.s, z3.s}, p0/z, [x0,#0]
ld3w {z1.s, z2.s, z3.s}, p0/z, [x0,#0,mul vl]
ld3w {z1.s, z2.s, z3.s}, p0/z, [x0]
ld3w {z31.s, z0.s, z1.s}, p0/z, [x0,#0]
LD3W {Z31.S, Z0.S, Z1.S}, P0/Z, [X0,#0]
ld3w {z31.s, z0.s, z1.s}, p0/z, [x0,#0,mul vl]
ld3w {z31.s, z0.s, z1.s}, p0/z, [x0]
ld3w {z0.s-z2.s}, p2/z, [x0,#0]
LD3W {Z0.S-Z2.S}, P2/Z, [X0,#0]
ld3w {z0.s-z2.s}, p2/z, [x0,#0,mul vl]
ld3w {z0.s-z2.s}, p2/z, [x0]
ld3w {z0.s, z1.s, z2.s}, p2/z, [x0,#0]
ld3w {z0.s, z1.s, z2.s}, p2/z, [x0,#0,mul vl]
ld3w {z0.s, z1.s, z2.s}, p2/z, [x0]
ld3w {z0.s-z2.s}, p7/z, [x0,#0]
LD3W {Z0.S-Z2.S}, P7/Z, [X0,#0]
ld3w {z0.s-z2.s}, p7/z, [x0,#0,mul vl]
ld3w {z0.s-z2.s}, p7/z, [x0]
ld3w {z0.s, z1.s, z2.s}, p7/z, [x0,#0]
ld3w {z0.s, z1.s, z2.s}, p7/z, [x0,#0,mul vl]
ld3w {z0.s, z1.s, z2.s}, p7/z, [x0]
ld3w {z0.s-z2.s}, p0/z, [x3,#0]
LD3W {Z0.S-Z2.S}, P0/Z, [X3,#0]
ld3w {z0.s-z2.s}, p0/z, [x3,#0,mul vl]
ld3w {z0.s-z2.s}, p0/z, [x3]
ld3w {z0.s, z1.s, z2.s}, p0/z, [x3,#0]
ld3w {z0.s, z1.s, z2.s}, p0/z, [x3,#0,mul vl]
ld3w {z0.s, z1.s, z2.s}, p0/z, [x3]
ld3w {z0.s-z2.s}, p0/z, [sp,#0]
LD3W {Z0.S-Z2.S}, P0/Z, [SP,#0]
ld3w {z0.s-z2.s}, p0/z, [sp,#0,mul vl]
ld3w {z0.s-z2.s}, p0/z, [sp]
ld3w {z0.s, z1.s, z2.s}, p0/z, [sp,#0]
ld3w {z0.s, z1.s, z2.s}, p0/z, [sp,#0,mul vl]
ld3w {z0.s, z1.s, z2.s}, p0/z, [sp]
ld3w {z0.s-z2.s}, p0/z, [x0,#21,mul vl]
LD3W {Z0.S-Z2.S}, P0/Z, [X0,#21,MUL VL]
ld3w {z0.s, z1.s, z2.s}, p0/z, [x0,#21,mul vl]
ld3w {z0.s-z2.s}, p0/z, [x0,#-24,mul vl]
LD3W {Z0.S-Z2.S}, P0/Z, [X0,#-24,MUL VL]
ld3w {z0.s, z1.s, z2.s}, p0/z, [x0,#-24,mul vl]
ld3w {z0.s-z2.s}, p0/z, [x0,#-21,mul vl]
LD3W {Z0.S-Z2.S}, P0/Z, [X0,#-21,MUL VL]
ld3w {z0.s, z1.s, z2.s}, p0/z, [x0,#-21,mul vl]
ld3w {z0.s-z2.s}, p0/z, [x0,#-3,mul vl]
LD3W {Z0.S-Z2.S}, P0/Z, [X0,#-3,MUL VL]
ld3w {z0.s, z1.s, z2.s}, p0/z, [x0,#-3,mul vl]
ld4b {z0.b-z3.b}, p0/z, [x0,x0]
LD4B {Z0.B-Z3.B}, P0/Z, [X0,X0]
ld4b {z0.b-z3.b}, p0/z, [x0,x0,lsl #0]
ld4b {z0.b, z1.b, z2.b, z3.b}, p0/z, [x0,x0]
ld4b {z0.b, z1.b, z2.b, z3.b}, p0/z, [x0,x0,lsl #0]
ld4b {z1.b-z4.b}, p0/z, [x0,x0]
LD4B {Z1.B-Z4.B}, P0/Z, [X0,X0]
ld4b {z1.b-z4.b}, p0/z, [x0,x0,lsl #0]
ld4b {z1.b, z2.b, z3.b, z4.b}, p0/z, [x0,x0]
ld4b {z1.b, z2.b, z3.b, z4.b}, p0/z, [x0,x0,lsl #0]
ld4b {z31.b, z0.b, z1.b, z2.b}, p0/z, [x0,x0]
LD4B {Z31.B, Z0.B, Z1.B, Z2.B}, P0/Z, [X0,X0]
ld4b {z31.b, z0.b, z1.b, z2.b}, p0/z, [x0,x0,lsl #0]
ld4b {z0.b-z3.b}, p2/z, [x0,x0]
LD4B {Z0.B-Z3.B}, P2/Z, [X0,X0]
ld4b {z0.b-z3.b}, p2/z, [x0,x0,lsl #0]
ld4b {z0.b, z1.b, z2.b, z3.b}, p2/z, [x0,x0]
ld4b {z0.b, z1.b, z2.b, z3.b}, p2/z, [x0,x0,lsl #0]
ld4b {z0.b-z3.b}, p7/z, [x0,x0]
LD4B {Z0.B-Z3.B}, P7/Z, [X0,X0]
ld4b {z0.b-z3.b}, p7/z, [x0,x0,lsl #0]
ld4b {z0.b, z1.b, z2.b, z3.b}, p7/z, [x0,x0]
ld4b {z0.b, z1.b, z2.b, z3.b}, p7/z, [x0,x0,lsl #0]
ld4b {z0.b-z3.b}, p0/z, [x3,x0]
LD4B {Z0.B-Z3.B}, P0/Z, [X3,X0]
ld4b {z0.b-z3.b}, p0/z, [x3,x0,lsl #0]
ld4b {z0.b, z1.b, z2.b, z3.b}, p0/z, [x3,x0]
ld4b {z0.b, z1.b, z2.b, z3.b}, p0/z, [x3,x0,lsl #0]
ld4b {z0.b-z3.b}, p0/z, [sp,x0]
LD4B {Z0.B-Z3.B}, P0/Z, [SP,X0]
ld4b {z0.b-z3.b}, p0/z, [sp,x0,lsl #0]
ld4b {z0.b, z1.b, z2.b, z3.b}, p0/z, [sp,x0]
ld4b {z0.b, z1.b, z2.b, z3.b}, p0/z, [sp,x0,lsl #0]
ld4b {z0.b-z3.b}, p0/z, [x0,x4]
LD4B {Z0.B-Z3.B}, P0/Z, [X0,X4]
ld4b {z0.b-z3.b}, p0/z, [x0,x4,lsl #0]
ld4b {z0.b, z1.b, z2.b, z3.b}, p0/z, [x0,x4]
ld4b {z0.b, z1.b, z2.b, z3.b}, p0/z, [x0,x4,lsl #0]
ld4b {z0.b-z3.b}, p0/z, [x0,x30]
LD4B {Z0.B-Z3.B}, P0/Z, [X0,X30]
ld4b {z0.b-z3.b}, p0/z, [x0,x30,lsl #0]
ld4b {z0.b, z1.b, z2.b, z3.b}, p0/z, [x0,x30]
ld4b {z0.b, z1.b, z2.b, z3.b}, p0/z, [x0,x30,lsl #0]
ld4b {z0.b-z3.b}, p0/z, [x0,#0]
LD4B {Z0.B-Z3.B}, P0/Z, [X0,#0]
ld4b {z0.b-z3.b}, p0/z, [x0,#0,mul vl]
ld4b {z0.b-z3.b}, p0/z, [x0]
ld4b {z0.b, z1.b, z2.b, z3.b}, p0/z, [x0,#0]
ld4b {z0.b, z1.b, z2.b, z3.b}, p0/z, [x0,#0,mul vl]
ld4b {z0.b, z1.b, z2.b, z3.b}, p0/z, [x0]
ld4b {z1.b-z4.b}, p0/z, [x0,#0]
LD4B {Z1.B-Z4.B}, P0/Z, [X0,#0]
ld4b {z1.b-z4.b}, p0/z, [x0,#0,mul vl]
ld4b {z1.b-z4.b}, p0/z, [x0]
ld4b {z1.b, z2.b, z3.b, z4.b}, p0/z, [x0,#0]
ld4b {z1.b, z2.b, z3.b, z4.b}, p0/z, [x0,#0,mul vl]
ld4b {z1.b, z2.b, z3.b, z4.b}, p0/z, [x0]
ld4b {z31.b, z0.b, z1.b, z2.b}, p0/z, [x0,#0]
LD4B {Z31.B, Z0.B, Z1.B, Z2.B}, P0/Z, [X0,#0]
ld4b {z31.b, z0.b, z1.b, z2.b}, p0/z, [x0,#0,mul vl]
ld4b {z31.b, z0.b, z1.b, z2.b}, p0/z, [x0]
ld4b {z0.b-z3.b}, p2/z, [x0,#0]
LD4B {Z0.B-Z3.B}, P2/Z, [X0,#0]
ld4b {z0.b-z3.b}, p2/z, [x0,#0,mul vl]
ld4b {z0.b-z3.b}, p2/z, [x0]
ld4b {z0.b, z1.b, z2.b, z3.b}, p2/z, [x0,#0]
ld4b {z0.b, z1.b, z2.b, z3.b}, p2/z, [x0,#0,mul vl]
ld4b {z0.b, z1.b, z2.b, z3.b}, p2/z, [x0]
ld4b {z0.b-z3.b}, p7/z, [x0,#0]
LD4B {Z0.B-Z3.B}, P7/Z, [X0,#0]
ld4b {z0.b-z3.b}, p7/z, [x0,#0,mul vl]
ld4b {z0.b-z3.b}, p7/z, [x0]
ld4b {z0.b, z1.b, z2.b, z3.b}, p7/z, [x0,#0]
ld4b {z0.b, z1.b, z2.b, z3.b}, p7/z, [x0,#0,mul vl]
ld4b {z0.b, z1.b, z2.b, z3.b}, p7/z, [x0]
ld4b {z0.b-z3.b}, p0/z, [x3,#0]
LD4B {Z0.B-Z3.B}, P0/Z, [X3,#0]
ld4b {z0.b-z3.b}, p0/z, [x3,#0,mul vl]
ld4b {z0.b-z3.b}, p0/z, [x3]
ld4b {z0.b, z1.b, z2.b, z3.b}, p0/z, [x3,#0]
ld4b {z0.b, z1.b, z2.b, z3.b}, p0/z, [x3,#0,mul vl]
ld4b {z0.b, z1.b, z2.b, z3.b}, p0/z, [x3]
ld4b {z0.b-z3.b}, p0/z, [sp,#0]
LD4B {Z0.B-Z3.B}, P0/Z, [SP,#0]
ld4b {z0.b-z3.b}, p0/z, [sp,#0,mul vl]
ld4b {z0.b-z3.b}, p0/z, [sp]
ld4b {z0.b, z1.b, z2.b, z3.b}, p0/z, [sp,#0]
ld4b {z0.b, z1.b, z2.b, z3.b}, p0/z, [sp,#0,mul vl]
ld4b {z0.b, z1.b, z2.b, z3.b}, p0/z, [sp]
ld4b {z0.b-z3.b}, p0/z, [x0,#28,mul vl]
LD4B {Z0.B-Z3.B}, P0/Z, [X0,#28,MUL VL]
ld4b {z0.b, z1.b, z2.b, z3.b}, p0/z, [x0,#28,mul vl]
ld4b {z0.b-z3.b}, p0/z, [x0,#-32,mul vl]
LD4B {Z0.B-Z3.B}, P0/Z, [X0,#-32,MUL VL]
ld4b {z0.b, z1.b, z2.b, z3.b}, p0/z, [x0,#-32,mul vl]
ld4b {z0.b-z3.b}, p0/z, [x0,#-28,mul vl]
LD4B {Z0.B-Z3.B}, P0/Z, [X0,#-28,MUL VL]
ld4b {z0.b, z1.b, z2.b, z3.b}, p0/z, [x0,#-28,mul vl]
ld4b {z0.b-z3.b}, p0/z, [x0,#-4,mul vl]
LD4B {Z0.B-Z3.B}, P0/Z, [X0,#-4,MUL VL]
ld4b {z0.b, z1.b, z2.b, z3.b}, p0/z, [x0,#-4,mul vl]
ld4d {z0.d-z3.d}, p0/z, [x0,x0,lsl #3]
LD4D {Z0.D-Z3.D}, P0/Z, [X0,X0,LSL #3]
ld4d {z0.d, z1.d, z2.d, z3.d}, p0/z, [x0,x0,lsl #3]
ld4d {z1.d-z4.d}, p0/z, [x0,x0,lsl #3]
LD4D {Z1.D-Z4.D}, P0/Z, [X0,X0,LSL #3]
ld4d {z1.d, z2.d, z3.d, z4.d}, p0/z, [x0,x0,lsl #3]
ld4d {z31.d, z0.d, z1.d, z2.d}, p0/z, [x0,x0,lsl #3]
LD4D {Z31.D, Z0.D, Z1.D, Z2.D}, P0/Z, [X0,X0,LSL #3]
ld4d {z0.d-z3.d}, p2/z, [x0,x0,lsl #3]
LD4D {Z0.D-Z3.D}, P2/Z, [X0,X0,LSL #3]
ld4d {z0.d, z1.d, z2.d, z3.d}, p2/z, [x0,x0,lsl #3]
ld4d {z0.d-z3.d}, p7/z, [x0,x0,lsl #3]
LD4D {Z0.D-Z3.D}, P7/Z, [X0,X0,LSL #3]
ld4d {z0.d, z1.d, z2.d, z3.d}, p7/z, [x0,x0,lsl #3]
ld4d {z0.d-z3.d}, p0/z, [x3,x0,lsl #3]
LD4D {Z0.D-Z3.D}, P0/Z, [X3,X0,LSL #3]
ld4d {z0.d, z1.d, z2.d, z3.d}, p0/z, [x3,x0,lsl #3]
ld4d {z0.d-z3.d}, p0/z, [sp,x0,lsl #3]
LD4D {Z0.D-Z3.D}, P0/Z, [SP,X0,LSL #3]
ld4d {z0.d, z1.d, z2.d, z3.d}, p0/z, [sp,x0,lsl #3]
ld4d {z0.d-z3.d}, p0/z, [x0,x4,lsl #3]
LD4D {Z0.D-Z3.D}, P0/Z, [X0,X4,LSL #3]
ld4d {z0.d, z1.d, z2.d, z3.d}, p0/z, [x0,x4,lsl #3]
ld4d {z0.d-z3.d}, p0/z, [x0,x30,lsl #3]
LD4D {Z0.D-Z3.D}, P0/Z, [X0,X30,LSL #3]
ld4d {z0.d, z1.d, z2.d, z3.d}, p0/z, [x0,x30,lsl #3]
ld4d {z0.d-z3.d}, p0/z, [x0,#0]
LD4D {Z0.D-Z3.D}, P0/Z, [X0,#0]
ld4d {z0.d-z3.d}, p0/z, [x0,#0,mul vl]
ld4d {z0.d-z3.d}, p0/z, [x0]
ld4d {z0.d, z1.d, z2.d, z3.d}, p0/z, [x0,#0]
ld4d {z0.d, z1.d, z2.d, z3.d}, p0/z, [x0,#0,mul vl]
ld4d {z0.d, z1.d, z2.d, z3.d}, p0/z, [x0]
ld4d {z1.d-z4.d}, p0/z, [x0,#0]
LD4D {Z1.D-Z4.D}, P0/Z, [X0,#0]
ld4d {z1.d-z4.d}, p0/z, [x0,#0,mul vl]
ld4d {z1.d-z4.d}, p0/z, [x0]
ld4d {z1.d, z2.d, z3.d, z4.d}, p0/z, [x0,#0]
ld4d {z1.d, z2.d, z3.d, z4.d}, p0/z, [x0,#0,mul vl]
ld4d {z1.d, z2.d, z3.d, z4.d}, p0/z, [x0]
ld4d {z31.d, z0.d, z1.d, z2.d}, p0/z, [x0,#0]
LD4D {Z31.D, Z0.D, Z1.D, Z2.D}, P0/Z, [X0,#0]
ld4d {z31.d, z0.d, z1.d, z2.d}, p0/z, [x0,#0,mul vl]
ld4d {z31.d, z0.d, z1.d, z2.d}, p0/z, [x0]
ld4d {z0.d-z3.d}, p2/z, [x0,#0]
LD4D {Z0.D-Z3.D}, P2/Z, [X0,#0]
ld4d {z0.d-z3.d}, p2/z, [x0,#0,mul vl]
ld4d {z0.d-z3.d}, p2/z, [x0]
ld4d {z0.d, z1.d, z2.d, z3.d}, p2/z, [x0,#0]
ld4d {z0.d, z1.d, z2.d, z3.d}, p2/z, [x0,#0,mul vl]
ld4d {z0.d, z1.d, z2.d, z3.d}, p2/z, [x0]
ld4d {z0.d-z3.d}, p7/z, [x0,#0]
LD4D {Z0.D-Z3.D}, P7/Z, [X0,#0]
ld4d {z0.d-z3.d}, p7/z, [x0,#0,mul vl]
ld4d {z0.d-z3.d}, p7/z, [x0]
ld4d {z0.d, z1.d, z2.d, z3.d}, p7/z, [x0,#0]
ld4d {z0.d, z1.d, z2.d, z3.d}, p7/z, [x0,#0,mul vl]
ld4d {z0.d, z1.d, z2.d, z3.d}, p7/z, [x0]
ld4d {z0.d-z3.d}, p0/z, [x3,#0]
LD4D {Z0.D-Z3.D}, P0/Z, [X3,#0]
ld4d {z0.d-z3.d}, p0/z, [x3,#0,mul vl]
ld4d {z0.d-z3.d}, p0/z, [x3]
ld4d {z0.d, z1.d, z2.d, z3.d}, p0/z, [x3,#0]
ld4d {z0.d, z1.d, z2.d, z3.d}, p0/z, [x3,#0,mul vl]
ld4d {z0.d, z1.d, z2.d, z3.d}, p0/z, [x3]
ld4d {z0.d-z3.d}, p0/z, [sp,#0]
LD4D {Z0.D-Z3.D}, P0/Z, [SP,#0]
ld4d {z0.d-z3.d}, p0/z, [sp,#0,mul vl]
ld4d {z0.d-z3.d}, p0/z, [sp]
ld4d {z0.d, z1.d, z2.d, z3.d}, p0/z, [sp,#0]
ld4d {z0.d, z1.d, z2.d, z3.d}, p0/z, [sp,#0,mul vl]
ld4d {z0.d, z1.d, z2.d, z3.d}, p0/z, [sp]
ld4d {z0.d-z3.d}, p0/z, [x0,#28,mul vl]
LD4D {Z0.D-Z3.D}, P0/Z, [X0,#28,MUL VL]
ld4d {z0.d, z1.d, z2.d, z3.d}, p0/z, [x0,#28,mul vl]
ld4d {z0.d-z3.d}, p0/z, [x0,#-32,mul vl]
LD4D {Z0.D-Z3.D}, P0/Z, [X0,#-32,MUL VL]
ld4d {z0.d, z1.d, z2.d, z3.d}, p0/z, [x0,#-32,mul vl]
ld4d {z0.d-z3.d}, p0/z, [x0,#-28,mul vl]
LD4D {Z0.D-Z3.D}, P0/Z, [X0,#-28,MUL VL]
ld4d {z0.d, z1.d, z2.d, z3.d}, p0/z, [x0,#-28,mul vl]
ld4d {z0.d-z3.d}, p0/z, [x0,#-4,mul vl]
LD4D {Z0.D-Z3.D}, P0/Z, [X0,#-4,MUL VL]
ld4d {z0.d, z1.d, z2.d, z3.d}, p0/z, [x0,#-4,mul vl]
ld4h {z0.h-z3.h}, p0/z, [x0,x0,lsl #1]
LD4H {Z0.H-Z3.H}, P0/Z, [X0,X0,LSL #1]
ld4h {z0.h, z1.h, z2.h, z3.h}, p0/z, [x0,x0,lsl #1]
ld4h {z1.h-z4.h}, p0/z, [x0,x0,lsl #1]
LD4H {Z1.H-Z4.H}, P0/Z, [X0,X0,LSL #1]
ld4h {z1.h, z2.h, z3.h, z4.h}, p0/z, [x0,x0,lsl #1]
ld4h {z31.h, z0.h, z1.h, z2.h}, p0/z, [x0,x0,lsl #1]
LD4H {Z31.H, Z0.H, Z1.H, Z2.H}, P0/Z, [X0,X0,LSL #1]
ld4h {z0.h-z3.h}, p2/z, [x0,x0,lsl #1]
LD4H {Z0.H-Z3.H}, P2/Z, [X0,X0,LSL #1]
ld4h {z0.h, z1.h, z2.h, z3.h}, p2/z, [x0,x0,lsl #1]
ld4h {z0.h-z3.h}, p7/z, [x0,x0,lsl #1]
LD4H {Z0.H-Z3.H}, P7/Z, [X0,X0,LSL #1]
ld4h {z0.h, z1.h, z2.h, z3.h}, p7/z, [x0,x0,lsl #1]
ld4h {z0.h-z3.h}, p0/z, [x3,x0,lsl #1]
LD4H {Z0.H-Z3.H}, P0/Z, [X3,X0,LSL #1]
ld4h {z0.h, z1.h, z2.h, z3.h}, p0/z, [x3,x0,lsl #1]
ld4h {z0.h-z3.h}, p0/z, [sp,x0,lsl #1]
LD4H {Z0.H-Z3.H}, P0/Z, [SP,X0,LSL #1]
ld4h {z0.h, z1.h, z2.h, z3.h}, p0/z, [sp,x0,lsl #1]
ld4h {z0.h-z3.h}, p0/z, [x0,x4,lsl #1]
LD4H {Z0.H-Z3.H}, P0/Z, [X0,X4,LSL #1]
ld4h {z0.h, z1.h, z2.h, z3.h}, p0/z, [x0,x4,lsl #1]
ld4h {z0.h-z3.h}, p0/z, [x0,x30,lsl #1]
LD4H {Z0.H-Z3.H}, P0/Z, [X0,X30,LSL #1]
ld4h {z0.h, z1.h, z2.h, z3.h}, p0/z, [x0,x30,lsl #1]
ld4h {z0.h-z3.h}, p0/z, [x0,#0]
LD4H {Z0.H-Z3.H}, P0/Z, [X0,#0]
ld4h {z0.h-z3.h}, p0/z, [x0,#0,mul vl]
ld4h {z0.h-z3.h}, p0/z, [x0]
ld4h {z0.h, z1.h, z2.h, z3.h}, p0/z, [x0,#0]
ld4h {z0.h, z1.h, z2.h, z3.h}, p0/z, [x0,#0,mul vl]
ld4h {z0.h, z1.h, z2.h, z3.h}, p0/z, [x0]
ld4h {z1.h-z4.h}, p0/z, [x0,#0]
LD4H {Z1.H-Z4.H}, P0/Z, [X0,#0]
ld4h {z1.h-z4.h}, p0/z, [x0,#0,mul vl]
ld4h {z1.h-z4.h}, p0/z, [x0]
ld4h {z1.h, z2.h, z3.h, z4.h}, p0/z, [x0,#0]
ld4h {z1.h, z2.h, z3.h, z4.h}, p0/z, [x0,#0,mul vl]
ld4h {z1.h, z2.h, z3.h, z4.h}, p0/z, [x0]
ld4h {z31.h, z0.h, z1.h, z2.h}, p0/z, [x0,#0]
LD4H {Z31.H, Z0.H, Z1.H, Z2.H}, P0/Z, [X0,#0]
ld4h {z31.h, z0.h, z1.h, z2.h}, p0/z, [x0,#0,mul vl]
ld4h {z31.h, z0.h, z1.h, z2.h}, p0/z, [x0]
ld4h {z0.h-z3.h}, p2/z, [x0,#0]
LD4H {Z0.H-Z3.H}, P2/Z, [X0,#0]
ld4h {z0.h-z3.h}, p2/z, [x0,#0,mul vl]
ld4h {z0.h-z3.h}, p2/z, [x0]
ld4h {z0.h, z1.h, z2.h, z3.h}, p2/z, [x0,#0]
ld4h {z0.h, z1.h, z2.h, z3.h}, p2/z, [x0,#0,mul vl]
ld4h {z0.h, z1.h, z2.h, z3.h}, p2/z, [x0]
ld4h {z0.h-z3.h}, p7/z, [x0,#0]
LD4H {Z0.H-Z3.H}, P7/Z, [X0,#0]
ld4h {z0.h-z3.h}, p7/z, [x0,#0,mul vl]
ld4h {z0.h-z3.h}, p7/z, [x0]
ld4h {z0.h, z1.h, z2.h, z3.h}, p7/z, [x0,#0]
ld4h {z0.h, z1.h, z2.h, z3.h}, p7/z, [x0,#0,mul vl]
ld4h {z0.h, z1.h, z2.h, z3.h}, p7/z, [x0]
ld4h {z0.h-z3.h}, p0/z, [x3,#0]
LD4H {Z0.H-Z3.H}, P0/Z, [X3,#0]
ld4h {z0.h-z3.h}, p0/z, [x3,#0,mul vl]
ld4h {z0.h-z3.h}, p0/z, [x3]
ld4h {z0.h, z1.h, z2.h, z3.h}, p0/z, [x3,#0]
ld4h {z0.h, z1.h, z2.h, z3.h}, p0/z, [x3,#0,mul vl]
ld4h {z0.h, z1.h, z2.h, z3.h}, p0/z, [x3]
ld4h {z0.h-z3.h}, p0/z, [sp,#0]
LD4H {Z0.H-Z3.H}, P0/Z, [SP,#0]
ld4h {z0.h-z3.h}, p0/z, [sp,#0,mul vl]
ld4h {z0.h-z3.h}, p0/z, [sp]
ld4h {z0.h, z1.h, z2.h, z3.h}, p0/z, [sp,#0]
ld4h {z0.h, z1.h, z2.h, z3.h}, p0/z, [sp,#0,mul vl]
ld4h {z0.h, z1.h, z2.h, z3.h}, p0/z, [sp]
ld4h {z0.h-z3.h}, p0/z, [x0,#28,mul vl]
LD4H {Z0.H-Z3.H}, P0/Z, [X0,#28,MUL VL]
ld4h {z0.h, z1.h, z2.h, z3.h}, p0/z, [x0,#28,mul vl]
ld4h {z0.h-z3.h}, p0/z, [x0,#-32,mul vl]
LD4H {Z0.H-Z3.H}, P0/Z, [X0,#-32,MUL VL]
ld4h {z0.h, z1.h, z2.h, z3.h}, p0/z, [x0,#-32,mul vl]
ld4h {z0.h-z3.h}, p0/z, [x0,#-28,mul vl]
LD4H {Z0.H-Z3.H}, P0/Z, [X0,#-28,MUL VL]
ld4h {z0.h, z1.h, z2.h, z3.h}, p0/z, [x0,#-28,mul vl]
ld4h {z0.h-z3.h}, p0/z, [x0,#-4,mul vl]
LD4H {Z0.H-Z3.H}, P0/Z, [X0,#-4,MUL VL]
ld4h {z0.h, z1.h, z2.h, z3.h}, p0/z, [x0,#-4,mul vl]
ld4w {z0.s-z3.s}, p0/z, [x0,x0,lsl #2]
LD4W {Z0.S-Z3.S}, P0/Z, [X0,X0,LSL #2]
ld4w {z0.s, z1.s, z2.s, z3.s}, p0/z, [x0,x0,lsl #2]
ld4w {z1.s-z4.s}, p0/z, [x0,x0,lsl #2]
LD4W {Z1.S-Z4.S}, P0/Z, [X0,X0,LSL #2]
ld4w {z1.s, z2.s, z3.s, z4.s}, p0/z, [x0,x0,lsl #2]
ld4w {z31.s, z0.s, z1.s, z2.s}, p0/z, [x0,x0,lsl #2]
LD4W {Z31.S, Z0.S, Z1.S, Z2.S}, P0/Z, [X0,X0,LSL #2]
ld4w {z0.s-z3.s}, p2/z, [x0,x0,lsl #2]
LD4W {Z0.S-Z3.S}, P2/Z, [X0,X0,LSL #2]
ld4w {z0.s, z1.s, z2.s, z3.s}, p2/z, [x0,x0,lsl #2]
ld4w {z0.s-z3.s}, p7/z, [x0,x0,lsl #2]
LD4W {Z0.S-Z3.S}, P7/Z, [X0,X0,LSL #2]
ld4w {z0.s, z1.s, z2.s, z3.s}, p7/z, [x0,x0,lsl #2]
ld4w {z0.s-z3.s}, p0/z, [x3,x0,lsl #2]
LD4W {Z0.S-Z3.S}, P0/Z, [X3,X0,LSL #2]
ld4w {z0.s, z1.s, z2.s, z3.s}, p0/z, [x3,x0,lsl #2]
ld4w {z0.s-z3.s}, p0/z, [sp,x0,lsl #2]
LD4W {Z0.S-Z3.S}, P0/Z, [SP,X0,LSL #2]
ld4w {z0.s, z1.s, z2.s, z3.s}, p0/z, [sp,x0,lsl #2]
ld4w {z0.s-z3.s}, p0/z, [x0,x4,lsl #2]
LD4W {Z0.S-Z3.S}, P0/Z, [X0,X4,LSL #2]
ld4w {z0.s, z1.s, z2.s, z3.s}, p0/z, [x0,x4,lsl #2]
ld4w {z0.s-z3.s}, p0/z, [x0,x30,lsl #2]
LD4W {Z0.S-Z3.S}, P0/Z, [X0,X30,LSL #2]
ld4w {z0.s, z1.s, z2.s, z3.s}, p0/z, [x0,x30,lsl #2]
ld4w {z0.s-z3.s}, p0/z, [x0,#0]
LD4W {Z0.S-Z3.S}, P0/Z, [X0,#0]
ld4w {z0.s-z3.s}, p0/z, [x0,#0,mul vl]
ld4w {z0.s-z3.s}, p0/z, [x0]
ld4w {z0.s, z1.s, z2.s, z3.s}, p0/z, [x0,#0]
ld4w {z0.s, z1.s, z2.s, z3.s}, p0/z, [x0,#0,mul vl]
ld4w {z0.s, z1.s, z2.s, z3.s}, p0/z, [x0]
ld4w {z1.s-z4.s}, p0/z, [x0,#0]
LD4W {Z1.S-Z4.S}, P0/Z, [X0,#0]
ld4w {z1.s-z4.s}, p0/z, [x0,#0,mul vl]
ld4w {z1.s-z4.s}, p0/z, [x0]
ld4w {z1.s, z2.s, z3.s, z4.s}, p0/z, [x0,#0]
ld4w {z1.s, z2.s, z3.s, z4.s}, p0/z, [x0,#0,mul vl]
ld4w {z1.s, z2.s, z3.s, z4.s}, p0/z, [x0]
ld4w {z31.s, z0.s, z1.s, z2.s}, p0/z, [x0,#0]
LD4W {Z31.S, Z0.S, Z1.S, Z2.S}, P0/Z, [X0,#0]
ld4w {z31.s, z0.s, z1.s, z2.s}, p0/z, [x0,#0,mul vl]
ld4w {z31.s, z0.s, z1.s, z2.s}, p0/z, [x0]
ld4w {z0.s-z3.s}, p2/z, [x0,#0]
LD4W {Z0.S-Z3.S}, P2/Z, [X0,#0]
ld4w {z0.s-z3.s}, p2/z, [x0,#0,mul vl]
ld4w {z0.s-z3.s}, p2/z, [x0]
ld4w {z0.s, z1.s, z2.s, z3.s}, p2/z, [x0,#0]
ld4w {z0.s, z1.s, z2.s, z3.s}, p2/z, [x0,#0,mul vl]
ld4w {z0.s, z1.s, z2.s, z3.s}, p2/z, [x0]
ld4w {z0.s-z3.s}, p7/z, [x0,#0]
LD4W {Z0.S-Z3.S}, P7/Z, [X0,#0]
ld4w {z0.s-z3.s}, p7/z, [x0,#0,mul vl]
ld4w {z0.s-z3.s}, p7/z, [x0]
ld4w {z0.s, z1.s, z2.s, z3.s}, p7/z, [x0,#0]
ld4w {z0.s, z1.s, z2.s, z3.s}, p7/z, [x0,#0,mul vl]
ld4w {z0.s, z1.s, z2.s, z3.s}, p7/z, [x0]
ld4w {z0.s-z3.s}, p0/z, [x3,#0]
LD4W {Z0.S-Z3.S}, P0/Z, [X3,#0]
ld4w {z0.s-z3.s}, p0/z, [x3,#0,mul vl]
ld4w {z0.s-z3.s}, p0/z, [x3]
ld4w {z0.s, z1.s, z2.s, z3.s}, p0/z, [x3,#0]
ld4w {z0.s, z1.s, z2.s, z3.s}, p0/z, [x3,#0,mul vl]
ld4w {z0.s, z1.s, z2.s, z3.s}, p0/z, [x3]
ld4w {z0.s-z3.s}, p0/z, [sp,#0]
LD4W {Z0.S-Z3.S}, P0/Z, [SP,#0]
ld4w {z0.s-z3.s}, p0/z, [sp,#0,mul vl]
ld4w {z0.s-z3.s}, p0/z, [sp]
ld4w {z0.s, z1.s, z2.s, z3.s}, p0/z, [sp,#0]
ld4w {z0.s, z1.s, z2.s, z3.s}, p0/z, [sp,#0,mul vl]
ld4w {z0.s, z1.s, z2.s, z3.s}, p0/z, [sp]
ld4w {z0.s-z3.s}, p0/z, [x0,#28,mul vl]
LD4W {Z0.S-Z3.S}, P0/Z, [X0,#28,MUL VL]
ld4w {z0.s, z1.s, z2.s, z3.s}, p0/z, [x0,#28,mul vl]
ld4w {z0.s-z3.s}, p0/z, [x0,#-32,mul vl]
LD4W {Z0.S-Z3.S}, P0/Z, [X0,#-32,MUL VL]
ld4w {z0.s, z1.s, z2.s, z3.s}, p0/z, [x0,#-32,mul vl]
ld4w {z0.s-z3.s}, p0/z, [x0,#-28,mul vl]
LD4W {Z0.S-Z3.S}, P0/Z, [X0,#-28,MUL VL]
ld4w {z0.s, z1.s, z2.s, z3.s}, p0/z, [x0,#-28,mul vl]
ld4w {z0.s-z3.s}, p0/z, [x0,#-4,mul vl]
LD4W {Z0.S-Z3.S}, P0/Z, [X0,#-4,MUL VL]
ld4w {z0.s, z1.s, z2.s, z3.s}, p0/z, [x0,#-4,mul vl]
ldff1b z0.s, p0/z, [x0,z0.s,uxtw]
ldff1b {z0.s}, p0/z, [x0,z0.s,uxtw]
LDFF1B {Z0.S}, P0/Z, [X0,Z0.S,UXTW]
ldff1b {z0.s}, p0/z, [x0,z0.s,uxtw #0]
ldff1b z1.s, p0/z, [x0,z0.s,uxtw]
ldff1b {z1.s}, p0/z, [x0,z0.s,uxtw]
LDFF1B {Z1.S}, P0/Z, [X0,Z0.S,UXTW]
ldff1b {z1.s}, p0/z, [x0,z0.s,uxtw #0]
ldff1b z31.s, p0/z, [x0,z0.s,uxtw]
ldff1b {z31.s}, p0/z, [x0,z0.s,uxtw]
LDFF1B {Z31.S}, P0/Z, [X0,Z0.S,UXTW]
ldff1b {z31.s}, p0/z, [x0,z0.s,uxtw #0]
ldff1b {z0.s}, p2/z, [x0,z0.s,uxtw]
LDFF1B {Z0.S}, P2/Z, [X0,Z0.S,UXTW]
ldff1b {z0.s}, p2/z, [x0,z0.s,uxtw #0]
ldff1b {z0.s}, p7/z, [x0,z0.s,uxtw]
LDFF1B {Z0.S}, P7/Z, [X0,Z0.S,UXTW]
ldff1b {z0.s}, p7/z, [x0,z0.s,uxtw #0]
ldff1b {z0.s}, p0/z, [x3,z0.s,uxtw]
LDFF1B {Z0.S}, P0/Z, [X3,Z0.S,UXTW]
ldff1b {z0.s}, p0/z, [x3,z0.s,uxtw #0]
ldff1b {z0.s}, p0/z, [sp,z0.s,uxtw]
LDFF1B {Z0.S}, P0/Z, [SP,Z0.S,UXTW]
ldff1b {z0.s}, p0/z, [sp,z0.s,uxtw #0]
ldff1b {z0.s}, p0/z, [x0,z4.s,uxtw]
LDFF1B {Z0.S}, P0/Z, [X0,Z4.S,UXTW]
ldff1b {z0.s}, p0/z, [x0,z4.s,uxtw #0]
ldff1b {z0.s}, p0/z, [x0,z31.s,uxtw]
LDFF1B {Z0.S}, P0/Z, [X0,Z31.S,UXTW]
ldff1b {z0.s}, p0/z, [x0,z31.s,uxtw #0]
ldff1b z0.s, p0/z, [x0,z0.s,sxtw]
ldff1b {z0.s}, p0/z, [x0,z0.s,sxtw]
LDFF1B {Z0.S}, P0/Z, [X0,Z0.S,SXTW]
ldff1b {z0.s}, p0/z, [x0,z0.s,sxtw #0]
ldff1b z1.s, p0/z, [x0,z0.s,sxtw]
ldff1b {z1.s}, p0/z, [x0,z0.s,sxtw]
LDFF1B {Z1.S}, P0/Z, [X0,Z0.S,SXTW]
ldff1b {z1.s}, p0/z, [x0,z0.s,sxtw #0]
ldff1b z31.s, p0/z, [x0,z0.s,sxtw]
ldff1b {z31.s}, p0/z, [x0,z0.s,sxtw]
LDFF1B {Z31.S}, P0/Z, [X0,Z0.S,SXTW]
ldff1b {z31.s}, p0/z, [x0,z0.s,sxtw #0]
ldff1b {z0.s}, p2/z, [x0,z0.s,sxtw]
LDFF1B {Z0.S}, P2/Z, [X0,Z0.S,SXTW]
ldff1b {z0.s}, p2/z, [x0,z0.s,sxtw #0]
ldff1b {z0.s}, p7/z, [x0,z0.s,sxtw]
LDFF1B {Z0.S}, P7/Z, [X0,Z0.S,SXTW]
ldff1b {z0.s}, p7/z, [x0,z0.s,sxtw #0]
ldff1b {z0.s}, p0/z, [x3,z0.s,sxtw]
LDFF1B {Z0.S}, P0/Z, [X3,Z0.S,SXTW]
ldff1b {z0.s}, p0/z, [x3,z0.s,sxtw #0]
ldff1b {z0.s}, p0/z, [sp,z0.s,sxtw]
LDFF1B {Z0.S}, P0/Z, [SP,Z0.S,SXTW]
ldff1b {z0.s}, p0/z, [sp,z0.s,sxtw #0]
ldff1b {z0.s}, p0/z, [x0,z4.s,sxtw]
LDFF1B {Z0.S}, P0/Z, [X0,Z4.S,SXTW]
ldff1b {z0.s}, p0/z, [x0,z4.s,sxtw #0]
ldff1b {z0.s}, p0/z, [x0,z31.s,sxtw]
LDFF1B {Z0.S}, P0/Z, [X0,Z31.S,SXTW]
ldff1b {z0.s}, p0/z, [x0,z31.s,sxtw #0]
ldff1b z0.b, p0/z, [x0,x0]
ldff1b {z0.b}, p0/z, [x0,x0]
LDFF1B {Z0.B}, P0/Z, [X0,X0]
ldff1b {z0.b}, p0/z, [x0,x0,lsl #0]
ldff1b z1.b, p0/z, [x0,x0]
ldff1b {z1.b}, p0/z, [x0,x0]
LDFF1B {Z1.B}, P0/Z, [X0,X0]
ldff1b {z1.b}, p0/z, [x0,x0,lsl #0]
ldff1b z31.b, p0/z, [x0,x0]
ldff1b {z31.b}, p0/z, [x0,x0]
LDFF1B {Z31.B}, P0/Z, [X0,X0]
ldff1b {z31.b}, p0/z, [x0,x0,lsl #0]
ldff1b {z0.b}, p2/z, [x0,x0]
LDFF1B {Z0.B}, P2/Z, [X0,X0]
ldff1b {z0.b}, p2/z, [x0,x0,lsl #0]
ldff1b {z0.b}, p7/z, [x0,x0]
LDFF1B {Z0.B}, P7/Z, [X0,X0]
ldff1b {z0.b}, p7/z, [x0,x0,lsl #0]
ldff1b {z0.b}, p0/z, [x3,x0]
LDFF1B {Z0.B}, P0/Z, [X3,X0]
ldff1b {z0.b}, p0/z, [x3,x0,lsl #0]
ldff1b {z0.b}, p0/z, [sp,x0]
LDFF1B {Z0.B}, P0/Z, [SP,X0]
ldff1b {z0.b}, p0/z, [sp,x0,lsl #0]
ldff1b {z0.b}, p0/z, [x0,x4]
LDFF1B {Z0.B}, P0/Z, [X0,X4]
ldff1b {z0.b}, p0/z, [x0,x4,lsl #0]
ldff1b {z0.b}, p0/z, [x0,xzr]
LDFF1B {Z0.B}, P0/Z, [X0,XZR]
ldff1b {z0.b}, p0/z, [x0,xzr,lsl #0]
ldff1b z0.h, p0/z, [x0,x0]
ldff1b {z0.h}, p0/z, [x0,x0]
LDFF1B {Z0.H}, P0/Z, [X0,X0]
ldff1b {z0.h}, p0/z, [x0,x0,lsl #0]
ldff1b z1.h, p0/z, [x0,x0]
ldff1b {z1.h}, p0/z, [x0,x0]
LDFF1B {Z1.H}, P0/Z, [X0,X0]
ldff1b {z1.h}, p0/z, [x0,x0,lsl #0]
ldff1b z31.h, p0/z, [x0,x0]
ldff1b {z31.h}, p0/z, [x0,x0]
LDFF1B {Z31.H}, P0/Z, [X0,X0]
ldff1b {z31.h}, p0/z, [x0,x0,lsl #0]
ldff1b {z0.h}, p2/z, [x0,x0]
LDFF1B {Z0.H}, P2/Z, [X0,X0]
ldff1b {z0.h}, p2/z, [x0,x0,lsl #0]
ldff1b {z0.h}, p7/z, [x0,x0]
LDFF1B {Z0.H}, P7/Z, [X0,X0]
ldff1b {z0.h}, p7/z, [x0,x0,lsl #0]
ldff1b {z0.h}, p0/z, [x3,x0]
LDFF1B {Z0.H}, P0/Z, [X3,X0]
ldff1b {z0.h}, p0/z, [x3,x0,lsl #0]
ldff1b {z0.h}, p0/z, [sp,x0]
LDFF1B {Z0.H}, P0/Z, [SP,X0]
ldff1b {z0.h}, p0/z, [sp,x0,lsl #0]
ldff1b {z0.h}, p0/z, [x0,x4]
LDFF1B {Z0.H}, P0/Z, [X0,X4]
ldff1b {z0.h}, p0/z, [x0,x4,lsl #0]
ldff1b {z0.h}, p0/z, [x0,xzr]
LDFF1B {Z0.H}, P0/Z, [X0,XZR]
ldff1b {z0.h}, p0/z, [x0,xzr,lsl #0]
ldff1b z0.s, p0/z, [x0,x0]
ldff1b {z0.s}, p0/z, [x0,x0]
LDFF1B {Z0.S}, P0/Z, [X0,X0]
ldff1b {z0.s}, p0/z, [x0,x0,lsl #0]
ldff1b z1.s, p0/z, [x0,x0]
ldff1b {z1.s}, p0/z, [x0,x0]
LDFF1B {Z1.S}, P0/Z, [X0,X0]
ldff1b {z1.s}, p0/z, [x0,x0,lsl #0]
ldff1b z31.s, p0/z, [x0,x0]
ldff1b {z31.s}, p0/z, [x0,x0]
LDFF1B {Z31.S}, P0/Z, [X0,X0]
ldff1b {z31.s}, p0/z, [x0,x0,lsl #0]
ldff1b {z0.s}, p2/z, [x0,x0]
LDFF1B {Z0.S}, P2/Z, [X0,X0]
ldff1b {z0.s}, p2/z, [x0,x0,lsl #0]
ldff1b {z0.s}, p7/z, [x0,x0]
LDFF1B {Z0.S}, P7/Z, [X0,X0]
ldff1b {z0.s}, p7/z, [x0,x0,lsl #0]
ldff1b {z0.s}, p0/z, [x3,x0]
LDFF1B {Z0.S}, P0/Z, [X3,X0]
ldff1b {z0.s}, p0/z, [x3,x0,lsl #0]
ldff1b {z0.s}, p0/z, [sp,x0]
LDFF1B {Z0.S}, P0/Z, [SP,X0]
ldff1b {z0.s}, p0/z, [sp,x0,lsl #0]
ldff1b {z0.s}, p0/z, [x0,x4]
LDFF1B {Z0.S}, P0/Z, [X0,X4]
ldff1b {z0.s}, p0/z, [x0,x4,lsl #0]
ldff1b {z0.s}, p0/z, [x0,xzr]
LDFF1B {Z0.S}, P0/Z, [X0,XZR]
ldff1b {z0.s}, p0/z, [x0,xzr,lsl #0]
ldff1b z0.d, p0/z, [x0,x0]
ldff1b {z0.d}, p0/z, [x0,x0]
LDFF1B {Z0.D}, P0/Z, [X0,X0]
ldff1b {z0.d}, p0/z, [x0,x0,lsl #0]
ldff1b z1.d, p0/z, [x0,x0]
ldff1b {z1.d}, p0/z, [x0,x0]
LDFF1B {Z1.D}, P0/Z, [X0,X0]
ldff1b {z1.d}, p0/z, [x0,x0,lsl #0]
ldff1b z31.d, p0/z, [x0,x0]
ldff1b {z31.d}, p0/z, [x0,x0]
LDFF1B {Z31.D}, P0/Z, [X0,X0]
ldff1b {z31.d}, p0/z, [x0,x0,lsl #0]
ldff1b {z0.d}, p2/z, [x0,x0]
LDFF1B {Z0.D}, P2/Z, [X0,X0]
ldff1b {z0.d}, p2/z, [x0,x0,lsl #0]
ldff1b {z0.d}, p7/z, [x0,x0]
LDFF1B {Z0.D}, P7/Z, [X0,X0]
ldff1b {z0.d}, p7/z, [x0,x0,lsl #0]
ldff1b {z0.d}, p0/z, [x3,x0]
LDFF1B {Z0.D}, P0/Z, [X3,X0]
ldff1b {z0.d}, p0/z, [x3,x0,lsl #0]
ldff1b {z0.d}, p0/z, [sp,x0]
LDFF1B {Z0.D}, P0/Z, [SP,X0]
ldff1b {z0.d}, p0/z, [sp,x0,lsl #0]
ldff1b {z0.d}, p0/z, [x0,x4]
LDFF1B {Z0.D}, P0/Z, [X0,X4]
ldff1b {z0.d}, p0/z, [x0,x4,lsl #0]
ldff1b {z0.d}, p0/z, [x0,xzr]
LDFF1B {Z0.D}, P0/Z, [X0,XZR]
ldff1b {z0.d}, p0/z, [x0,xzr,lsl #0]
ldff1b z0.d, p0/z, [x0,z0.d,uxtw]
ldff1b {z0.d}, p0/z, [x0,z0.d,uxtw]
LDFF1B {Z0.D}, P0/Z, [X0,Z0.D,UXTW]
ldff1b {z0.d}, p0/z, [x0,z0.d,uxtw #0]
ldff1b z1.d, p0/z, [x0,z0.d,uxtw]
ldff1b {z1.d}, p0/z, [x0,z0.d,uxtw]
LDFF1B {Z1.D}, P0/Z, [X0,Z0.D,UXTW]
ldff1b {z1.d}, p0/z, [x0,z0.d,uxtw #0]
ldff1b z31.d, p0/z, [x0,z0.d,uxtw]
ldff1b {z31.d}, p0/z, [x0,z0.d,uxtw]
LDFF1B {Z31.D}, P0/Z, [X0,Z0.D,UXTW]
ldff1b {z31.d}, p0/z, [x0,z0.d,uxtw #0]
ldff1b {z0.d}, p2/z, [x0,z0.d,uxtw]
LDFF1B {Z0.D}, P2/Z, [X0,Z0.D,UXTW]
ldff1b {z0.d}, p2/z, [x0,z0.d,uxtw #0]
ldff1b {z0.d}, p7/z, [x0,z0.d,uxtw]
LDFF1B {Z0.D}, P7/Z, [X0,Z0.D,UXTW]
ldff1b {z0.d}, p7/z, [x0,z0.d,uxtw #0]
ldff1b {z0.d}, p0/z, [x3,z0.d,uxtw]
LDFF1B {Z0.D}, P0/Z, [X3,Z0.D,UXTW]
ldff1b {z0.d}, p0/z, [x3,z0.d,uxtw #0]
ldff1b {z0.d}, p0/z, [sp,z0.d,uxtw]
LDFF1B {Z0.D}, P0/Z, [SP,Z0.D,UXTW]
ldff1b {z0.d}, p0/z, [sp,z0.d,uxtw #0]
ldff1b {z0.d}, p0/z, [x0,z4.d,uxtw]
LDFF1B {Z0.D}, P0/Z, [X0,Z4.D,UXTW]
ldff1b {z0.d}, p0/z, [x0,z4.d,uxtw #0]
ldff1b {z0.d}, p0/z, [x0,z31.d,uxtw]
LDFF1B {Z0.D}, P0/Z, [X0,Z31.D,UXTW]
ldff1b {z0.d}, p0/z, [x0,z31.d,uxtw #0]
ldff1b z0.d, p0/z, [x0,z0.d,sxtw]
ldff1b {z0.d}, p0/z, [x0,z0.d,sxtw]
LDFF1B {Z0.D}, P0/Z, [X0,Z0.D,SXTW]
ldff1b {z0.d}, p0/z, [x0,z0.d,sxtw #0]
ldff1b z1.d, p0/z, [x0,z0.d,sxtw]
ldff1b {z1.d}, p0/z, [x0,z0.d,sxtw]
LDFF1B {Z1.D}, P0/Z, [X0,Z0.D,SXTW]
ldff1b {z1.d}, p0/z, [x0,z0.d,sxtw #0]
ldff1b z31.d, p0/z, [x0,z0.d,sxtw]
ldff1b {z31.d}, p0/z, [x0,z0.d,sxtw]
LDFF1B {Z31.D}, P0/Z, [X0,Z0.D,SXTW]
ldff1b {z31.d}, p0/z, [x0,z0.d,sxtw #0]
ldff1b {z0.d}, p2/z, [x0,z0.d,sxtw]
LDFF1B {Z0.D}, P2/Z, [X0,Z0.D,SXTW]
ldff1b {z0.d}, p2/z, [x0,z0.d,sxtw #0]
ldff1b {z0.d}, p7/z, [x0,z0.d,sxtw]
LDFF1B {Z0.D}, P7/Z, [X0,Z0.D,SXTW]
ldff1b {z0.d}, p7/z, [x0,z0.d,sxtw #0]
ldff1b {z0.d}, p0/z, [x3,z0.d,sxtw]
LDFF1B {Z0.D}, P0/Z, [X3,Z0.D,SXTW]
ldff1b {z0.d}, p0/z, [x3,z0.d,sxtw #0]
ldff1b {z0.d}, p0/z, [sp,z0.d,sxtw]
LDFF1B {Z0.D}, P0/Z, [SP,Z0.D,SXTW]
ldff1b {z0.d}, p0/z, [sp,z0.d,sxtw #0]
ldff1b {z0.d}, p0/z, [x0,z4.d,sxtw]
LDFF1B {Z0.D}, P0/Z, [X0,Z4.D,SXTW]
ldff1b {z0.d}, p0/z, [x0,z4.d,sxtw #0]
ldff1b {z0.d}, p0/z, [x0,z31.d,sxtw]
LDFF1B {Z0.D}, P0/Z, [X0,Z31.D,SXTW]
ldff1b {z0.d}, p0/z, [x0,z31.d,sxtw #0]
ldff1b z0.d, p0/z, [x0,z0.d]
ldff1b {z0.d}, p0/z, [x0,z0.d]
LDFF1B {Z0.D}, P0/Z, [X0,Z0.D]
ldff1b {z0.d}, p0/z, [x0,z0.d,lsl #0]
ldff1b z1.d, p0/z, [x0,z0.d]
ldff1b {z1.d}, p0/z, [x0,z0.d]
LDFF1B {Z1.D}, P0/Z, [X0,Z0.D]
ldff1b {z1.d}, p0/z, [x0,z0.d,lsl #0]
ldff1b z31.d, p0/z, [x0,z0.d]
ldff1b {z31.d}, p0/z, [x0,z0.d]
LDFF1B {Z31.D}, P0/Z, [X0,Z0.D]
ldff1b {z31.d}, p0/z, [x0,z0.d,lsl #0]
ldff1b {z0.d}, p2/z, [x0,z0.d]
LDFF1B {Z0.D}, P2/Z, [X0,Z0.D]
ldff1b {z0.d}, p2/z, [x0,z0.d,lsl #0]
ldff1b {z0.d}, p7/z, [x0,z0.d]
LDFF1B {Z0.D}, P7/Z, [X0,Z0.D]
ldff1b {z0.d}, p7/z, [x0,z0.d,lsl #0]
ldff1b {z0.d}, p0/z, [x3,z0.d]
LDFF1B {Z0.D}, P0/Z, [X3,Z0.D]
ldff1b {z0.d}, p0/z, [x3,z0.d,lsl #0]
ldff1b {z0.d}, p0/z, [sp,z0.d]
LDFF1B {Z0.D}, P0/Z, [SP,Z0.D]
ldff1b {z0.d}, p0/z, [sp,z0.d,lsl #0]
ldff1b {z0.d}, p0/z, [x0,z4.d]
LDFF1B {Z0.D}, P0/Z, [X0,Z4.D]
ldff1b {z0.d}, p0/z, [x0,z4.d,lsl #0]
ldff1b {z0.d}, p0/z, [x0,z31.d]
LDFF1B {Z0.D}, P0/Z, [X0,Z31.D]
ldff1b {z0.d}, p0/z, [x0,z31.d,lsl #0]
ldff1b z0.s, p0/z, [z0.s,#0]
ldff1b {z0.s}, p0/z, [z0.s,#0]
LDFF1B {Z0.S}, P0/Z, [Z0.S,#0]
ldff1b {z0.s}, p0/z, [z0.s]
ldff1b z1.s, p0/z, [z0.s,#0]
ldff1b {z1.s}, p0/z, [z0.s,#0]
LDFF1B {Z1.S}, P0/Z, [Z0.S,#0]
ldff1b {z1.s}, p0/z, [z0.s]
ldff1b z31.s, p0/z, [z0.s,#0]
ldff1b {z31.s}, p0/z, [z0.s,#0]
LDFF1B {Z31.S}, P0/Z, [Z0.S,#0]
ldff1b {z31.s}, p0/z, [z0.s]
ldff1b {z0.s}, p2/z, [z0.s,#0]
LDFF1B {Z0.S}, P2/Z, [Z0.S,#0]
ldff1b {z0.s}, p2/z, [z0.s]
ldff1b {z0.s}, p7/z, [z0.s,#0]
LDFF1B {Z0.S}, P7/Z, [Z0.S,#0]
ldff1b {z0.s}, p7/z, [z0.s]
ldff1b {z0.s}, p0/z, [z3.s,#0]
LDFF1B {Z0.S}, P0/Z, [Z3.S,#0]
ldff1b {z0.s}, p0/z, [z3.s]
ldff1b {z0.s}, p0/z, [z31.s,#0]
LDFF1B {Z0.S}, P0/Z, [Z31.S,#0]
ldff1b {z0.s}, p0/z, [z31.s]
ldff1b {z0.s}, p0/z, [z0.s,#15]
LDFF1B {Z0.S}, P0/Z, [Z0.S,#15]
ldff1b {z0.s}, p0/z, [z0.s,#16]
LDFF1B {Z0.S}, P0/Z, [Z0.S,#16]
ldff1b {z0.s}, p0/z, [z0.s,#17]
LDFF1B {Z0.S}, P0/Z, [Z0.S,#17]
ldff1b {z0.s}, p0/z, [z0.s,#31]
LDFF1B {Z0.S}, P0/Z, [Z0.S,#31]
ldff1b z0.d, p0/z, [z0.d,#0]
ldff1b {z0.d}, p0/z, [z0.d,#0]
LDFF1B {Z0.D}, P0/Z, [Z0.D,#0]
ldff1b {z0.d}, p0/z, [z0.d]
ldff1b z1.d, p0/z, [z0.d,#0]
ldff1b {z1.d}, p0/z, [z0.d,#0]
LDFF1B {Z1.D}, P0/Z, [Z0.D,#0]
ldff1b {z1.d}, p0/z, [z0.d]
ldff1b z31.d, p0/z, [z0.d,#0]
ldff1b {z31.d}, p0/z, [z0.d,#0]
LDFF1B {Z31.D}, P0/Z, [Z0.D,#0]
ldff1b {z31.d}, p0/z, [z0.d]
ldff1b {z0.d}, p2/z, [z0.d,#0]
LDFF1B {Z0.D}, P2/Z, [Z0.D,#0]
ldff1b {z0.d}, p2/z, [z0.d]
ldff1b {z0.d}, p7/z, [z0.d,#0]
LDFF1B {Z0.D}, P7/Z, [Z0.D,#0]
ldff1b {z0.d}, p7/z, [z0.d]
ldff1b {z0.d}, p0/z, [z3.d,#0]
LDFF1B {Z0.D}, P0/Z, [Z3.D,#0]
ldff1b {z0.d}, p0/z, [z3.d]
ldff1b {z0.d}, p0/z, [z31.d,#0]
LDFF1B {Z0.D}, P0/Z, [Z31.D,#0]
ldff1b {z0.d}, p0/z, [z31.d]
ldff1b {z0.d}, p0/z, [z0.d,#15]
LDFF1B {Z0.D}, P0/Z, [Z0.D,#15]
ldff1b {z0.d}, p0/z, [z0.d,#16]
LDFF1B {Z0.D}, P0/Z, [Z0.D,#16]
ldff1b {z0.d}, p0/z, [z0.d,#17]
LDFF1B {Z0.D}, P0/Z, [Z0.D,#17]
ldff1b {z0.d}, p0/z, [z0.d,#31]
LDFF1B {Z0.D}, P0/Z, [Z0.D,#31]
ldff1d z0.d, p0/z, [x0,x0,lsl #3]
ldff1d {z0.d}, p0/z, [x0,x0,lsl #3]
LDFF1D {Z0.D}, P0/Z, [X0,X0,LSL #3]
ldff1d z1.d, p0/z, [x0,x0,lsl #3]
ldff1d {z1.d}, p0/z, [x0,x0,lsl #3]
LDFF1D {Z1.D}, P0/Z, [X0,X0,LSL #3]
ldff1d z31.d, p0/z, [x0,x0,lsl #3]
ldff1d {z31.d}, p0/z, [x0,x0,lsl #3]
LDFF1D {Z31.D}, P0/Z, [X0,X0,LSL #3]
ldff1d {z0.d}, p2/z, [x0,x0,lsl #3]
LDFF1D {Z0.D}, P2/Z, [X0,X0,LSL #3]
ldff1d {z0.d}, p7/z, [x0,x0,lsl #3]
LDFF1D {Z0.D}, P7/Z, [X0,X0,LSL #3]
ldff1d {z0.d}, p0/z, [x3,x0,lsl #3]
LDFF1D {Z0.D}, P0/Z, [X3,X0,LSL #3]
ldff1d {z0.d}, p0/z, [sp,x0,lsl #3]
LDFF1D {Z0.D}, P0/Z, [SP,X0,LSL #3]
ldff1d {z0.d}, p0/z, [x0,x4,lsl #3]
LDFF1D {Z0.D}, P0/Z, [X0,X4,LSL #3]
ldff1d {z0.d}, p0/z, [x0,xzr,lsl #3]
LDFF1D {Z0.D}, P0/Z, [X0,XZR,LSL #3]
ldff1d z0.d, p0/z, [x0,z0.d,uxtw]
ldff1d {z0.d}, p0/z, [x0,z0.d,uxtw]
LDFF1D {Z0.D}, P0/Z, [X0,Z0.D,UXTW]
ldff1d {z0.d}, p0/z, [x0,z0.d,uxtw #0]
ldff1d z1.d, p0/z, [x0,z0.d,uxtw]
ldff1d {z1.d}, p0/z, [x0,z0.d,uxtw]
LDFF1D {Z1.D}, P0/Z, [X0,Z0.D,UXTW]
ldff1d {z1.d}, p0/z, [x0,z0.d,uxtw #0]
ldff1d z31.d, p0/z, [x0,z0.d,uxtw]
ldff1d {z31.d}, p0/z, [x0,z0.d,uxtw]
LDFF1D {Z31.D}, P0/Z, [X0,Z0.D,UXTW]
ldff1d {z31.d}, p0/z, [x0,z0.d,uxtw #0]
ldff1d {z0.d}, p2/z, [x0,z0.d,uxtw]
LDFF1D {Z0.D}, P2/Z, [X0,Z0.D,UXTW]
ldff1d {z0.d}, p2/z, [x0,z0.d,uxtw #0]
ldff1d {z0.d}, p7/z, [x0,z0.d,uxtw]
LDFF1D {Z0.D}, P7/Z, [X0,Z0.D,UXTW]
ldff1d {z0.d}, p7/z, [x0,z0.d,uxtw #0]
ldff1d {z0.d}, p0/z, [x3,z0.d,uxtw]
LDFF1D {Z0.D}, P0/Z, [X3,Z0.D,UXTW]
ldff1d {z0.d}, p0/z, [x3,z0.d,uxtw #0]
ldff1d {z0.d}, p0/z, [sp,z0.d,uxtw]
LDFF1D {Z0.D}, P0/Z, [SP,Z0.D,UXTW]
ldff1d {z0.d}, p0/z, [sp,z0.d,uxtw #0]
ldff1d {z0.d}, p0/z, [x0,z4.d,uxtw]
LDFF1D {Z0.D}, P0/Z, [X0,Z4.D,UXTW]
ldff1d {z0.d}, p0/z, [x0,z4.d,uxtw #0]
ldff1d {z0.d}, p0/z, [x0,z31.d,uxtw]
LDFF1D {Z0.D}, P0/Z, [X0,Z31.D,UXTW]
ldff1d {z0.d}, p0/z, [x0,z31.d,uxtw #0]
ldff1d z0.d, p0/z, [x0,z0.d,sxtw]
ldff1d {z0.d}, p0/z, [x0,z0.d,sxtw]
LDFF1D {Z0.D}, P0/Z, [X0,Z0.D,SXTW]
ldff1d {z0.d}, p0/z, [x0,z0.d,sxtw #0]
ldff1d z1.d, p0/z, [x0,z0.d,sxtw]
ldff1d {z1.d}, p0/z, [x0,z0.d,sxtw]
LDFF1D {Z1.D}, P0/Z, [X0,Z0.D,SXTW]
ldff1d {z1.d}, p0/z, [x0,z0.d,sxtw #0]
ldff1d z31.d, p0/z, [x0,z0.d,sxtw]
ldff1d {z31.d}, p0/z, [x0,z0.d,sxtw]
LDFF1D {Z31.D}, P0/Z, [X0,Z0.D,SXTW]
ldff1d {z31.d}, p0/z, [x0,z0.d,sxtw #0]
ldff1d {z0.d}, p2/z, [x0,z0.d,sxtw]
LDFF1D {Z0.D}, P2/Z, [X0,Z0.D,SXTW]
ldff1d {z0.d}, p2/z, [x0,z0.d,sxtw #0]
ldff1d {z0.d}, p7/z, [x0,z0.d,sxtw]
LDFF1D {Z0.D}, P7/Z, [X0,Z0.D,SXTW]
ldff1d {z0.d}, p7/z, [x0,z0.d,sxtw #0]
ldff1d {z0.d}, p0/z, [x3,z0.d,sxtw]
LDFF1D {Z0.D}, P0/Z, [X3,Z0.D,SXTW]
ldff1d {z0.d}, p0/z, [x3,z0.d,sxtw #0]
ldff1d {z0.d}, p0/z, [sp,z0.d,sxtw]
LDFF1D {Z0.D}, P0/Z, [SP,Z0.D,SXTW]
ldff1d {z0.d}, p0/z, [sp,z0.d,sxtw #0]
ldff1d {z0.d}, p0/z, [x0,z4.d,sxtw]
LDFF1D {Z0.D}, P0/Z, [X0,Z4.D,SXTW]
ldff1d {z0.d}, p0/z, [x0,z4.d,sxtw #0]
ldff1d {z0.d}, p0/z, [x0,z31.d,sxtw]
LDFF1D {Z0.D}, P0/Z, [X0,Z31.D,SXTW]
ldff1d {z0.d}, p0/z, [x0,z31.d,sxtw #0]
ldff1d z0.d, p0/z, [x0,z0.d,uxtw #3]
ldff1d {z0.d}, p0/z, [x0,z0.d,uxtw #3]
LDFF1D {Z0.D}, P0/Z, [X0,Z0.D,UXTW #3]
ldff1d z1.d, p0/z, [x0,z0.d,uxtw #3]
ldff1d {z1.d}, p0/z, [x0,z0.d,uxtw #3]
LDFF1D {Z1.D}, P0/Z, [X0,Z0.D,UXTW #3]
ldff1d z31.d, p0/z, [x0,z0.d,uxtw #3]
ldff1d {z31.d}, p0/z, [x0,z0.d,uxtw #3]
LDFF1D {Z31.D}, P0/Z, [X0,Z0.D,UXTW #3]
ldff1d {z0.d}, p2/z, [x0,z0.d,uxtw #3]
LDFF1D {Z0.D}, P2/Z, [X0,Z0.D,UXTW #3]
ldff1d {z0.d}, p7/z, [x0,z0.d,uxtw #3]
LDFF1D {Z0.D}, P7/Z, [X0,Z0.D,UXTW #3]
ldff1d {z0.d}, p0/z, [x3,z0.d,uxtw #3]
LDFF1D {Z0.D}, P0/Z, [X3,Z0.D,UXTW #3]
ldff1d {z0.d}, p0/z, [sp,z0.d,uxtw #3]
LDFF1D {Z0.D}, P0/Z, [SP,Z0.D,UXTW #3]
ldff1d {z0.d}, p0/z, [x0,z4.d,uxtw #3]
LDFF1D {Z0.D}, P0/Z, [X0,Z4.D,UXTW #3]
ldff1d {z0.d}, p0/z, [x0,z31.d,uxtw #3]
LDFF1D {Z0.D}, P0/Z, [X0,Z31.D,UXTW #3]
ldff1d z0.d, p0/z, [x0,z0.d,sxtw #3]
ldff1d {z0.d}, p0/z, [x0,z0.d,sxtw #3]
LDFF1D {Z0.D}, P0/Z, [X0,Z0.D,SXTW #3]
ldff1d z1.d, p0/z, [x0,z0.d,sxtw #3]
ldff1d {z1.d}, p0/z, [x0,z0.d,sxtw #3]
LDFF1D {Z1.D}, P0/Z, [X0,Z0.D,SXTW #3]
ldff1d z31.d, p0/z, [x0,z0.d,sxtw #3]
ldff1d {z31.d}, p0/z, [x0,z0.d,sxtw #3]
LDFF1D {Z31.D}, P0/Z, [X0,Z0.D,SXTW #3]
ldff1d {z0.d}, p2/z, [x0,z0.d,sxtw #3]
LDFF1D {Z0.D}, P2/Z, [X0,Z0.D,SXTW #3]
ldff1d {z0.d}, p7/z, [x0,z0.d,sxtw #3]
LDFF1D {Z0.D}, P7/Z, [X0,Z0.D,SXTW #3]
ldff1d {z0.d}, p0/z, [x3,z0.d,sxtw #3]
LDFF1D {Z0.D}, P0/Z, [X3,Z0.D,SXTW #3]
ldff1d {z0.d}, p0/z, [sp,z0.d,sxtw #3]
LDFF1D {Z0.D}, P0/Z, [SP,Z0.D,SXTW #3]
ldff1d {z0.d}, p0/z, [x0,z4.d,sxtw #3]
LDFF1D {Z0.D}, P0/Z, [X0,Z4.D,SXTW #3]
ldff1d {z0.d}, p0/z, [x0,z31.d,sxtw #3]
LDFF1D {Z0.D}, P0/Z, [X0,Z31.D,SXTW #3]
ldff1d z0.d, p0/z, [x0,z0.d]
ldff1d {z0.d}, p0/z, [x0,z0.d]
LDFF1D {Z0.D}, P0/Z, [X0,Z0.D]
ldff1d {z0.d}, p0/z, [x0,z0.d,lsl #0]
ldff1d z1.d, p0/z, [x0,z0.d]
ldff1d {z1.d}, p0/z, [x0,z0.d]
LDFF1D {Z1.D}, P0/Z, [X0,Z0.D]
ldff1d {z1.d}, p0/z, [x0,z0.d,lsl #0]
ldff1d z31.d, p0/z, [x0,z0.d]
ldff1d {z31.d}, p0/z, [x0,z0.d]
LDFF1D {Z31.D}, P0/Z, [X0,Z0.D]
ldff1d {z31.d}, p0/z, [x0,z0.d,lsl #0]
ldff1d {z0.d}, p2/z, [x0,z0.d]
LDFF1D {Z0.D}, P2/Z, [X0,Z0.D]
ldff1d {z0.d}, p2/z, [x0,z0.d,lsl #0]
ldff1d {z0.d}, p7/z, [x0,z0.d]
LDFF1D {Z0.D}, P7/Z, [X0,Z0.D]
ldff1d {z0.d}, p7/z, [x0,z0.d,lsl #0]
ldff1d {z0.d}, p0/z, [x3,z0.d]
LDFF1D {Z0.D}, P0/Z, [X3,Z0.D]
ldff1d {z0.d}, p0/z, [x3,z0.d,lsl #0]
ldff1d {z0.d}, p0/z, [sp,z0.d]
LDFF1D {Z0.D}, P0/Z, [SP,Z0.D]
ldff1d {z0.d}, p0/z, [sp,z0.d,lsl #0]
ldff1d {z0.d}, p0/z, [x0,z4.d]
LDFF1D {Z0.D}, P0/Z, [X0,Z4.D]
ldff1d {z0.d}, p0/z, [x0,z4.d,lsl #0]
ldff1d {z0.d}, p0/z, [x0,z31.d]
LDFF1D {Z0.D}, P0/Z, [X0,Z31.D]
ldff1d {z0.d}, p0/z, [x0,z31.d,lsl #0]
ldff1d z0.d, p0/z, [x0,z0.d,lsl #3]
ldff1d {z0.d}, p0/z, [x0,z0.d,lsl #3]
LDFF1D {Z0.D}, P0/Z, [X0,Z0.D,LSL #3]
ldff1d z1.d, p0/z, [x0,z0.d,lsl #3]
ldff1d {z1.d}, p0/z, [x0,z0.d,lsl #3]
LDFF1D {Z1.D}, P0/Z, [X0,Z0.D,LSL #3]
ldff1d z31.d, p0/z, [x0,z0.d,lsl #3]
ldff1d {z31.d}, p0/z, [x0,z0.d,lsl #3]
LDFF1D {Z31.D}, P0/Z, [X0,Z0.D,LSL #3]
ldff1d {z0.d}, p2/z, [x0,z0.d,lsl #3]
LDFF1D {Z0.D}, P2/Z, [X0,Z0.D,LSL #3]
ldff1d {z0.d}, p7/z, [x0,z0.d,lsl #3]
LDFF1D {Z0.D}, P7/Z, [X0,Z0.D,LSL #3]
ldff1d {z0.d}, p0/z, [x3,z0.d,lsl #3]
LDFF1D {Z0.D}, P0/Z, [X3,Z0.D,LSL #3]
ldff1d {z0.d}, p0/z, [sp,z0.d,lsl #3]
LDFF1D {Z0.D}, P0/Z, [SP,Z0.D,LSL #3]
ldff1d {z0.d}, p0/z, [x0,z4.d,lsl #3]
LDFF1D {Z0.D}, P0/Z, [X0,Z4.D,LSL #3]
ldff1d {z0.d}, p0/z, [x0,z31.d,lsl #3]
LDFF1D {Z0.D}, P0/Z, [X0,Z31.D,LSL #3]
ldff1d z0.d, p0/z, [z0.d,#0]
ldff1d {z0.d}, p0/z, [z0.d,#0]
LDFF1D {Z0.D}, P0/Z, [Z0.D,#0]
ldff1d {z0.d}, p0/z, [z0.d]
ldff1d z1.d, p0/z, [z0.d,#0]
ldff1d {z1.d}, p0/z, [z0.d,#0]
LDFF1D {Z1.D}, P0/Z, [Z0.D,#0]
ldff1d {z1.d}, p0/z, [z0.d]
ldff1d z31.d, p0/z, [z0.d,#0]
ldff1d {z31.d}, p0/z, [z0.d,#0]
LDFF1D {Z31.D}, P0/Z, [Z0.D,#0]
ldff1d {z31.d}, p0/z, [z0.d]
ldff1d {z0.d}, p2/z, [z0.d,#0]
LDFF1D {Z0.D}, P2/Z, [Z0.D,#0]
ldff1d {z0.d}, p2/z, [z0.d]
ldff1d {z0.d}, p7/z, [z0.d,#0]
LDFF1D {Z0.D}, P7/Z, [Z0.D,#0]
ldff1d {z0.d}, p7/z, [z0.d]
ldff1d {z0.d}, p0/z, [z3.d,#0]
LDFF1D {Z0.D}, P0/Z, [Z3.D,#0]
ldff1d {z0.d}, p0/z, [z3.d]
ldff1d {z0.d}, p0/z, [z31.d,#0]
LDFF1D {Z0.D}, P0/Z, [Z31.D,#0]
ldff1d {z0.d}, p0/z, [z31.d]
ldff1d {z0.d}, p0/z, [z0.d,#120]
LDFF1D {Z0.D}, P0/Z, [Z0.D,#120]
ldff1d {z0.d}, p0/z, [z0.d,#128]
LDFF1D {Z0.D}, P0/Z, [Z0.D,#128]
ldff1d {z0.d}, p0/z, [z0.d,#136]
LDFF1D {Z0.D}, P0/Z, [Z0.D,#136]
ldff1d {z0.d}, p0/z, [z0.d,#248]
LDFF1D {Z0.D}, P0/Z, [Z0.D,#248]
ldff1h z0.s, p0/z, [x0,z0.s,uxtw]
ldff1h {z0.s}, p0/z, [x0,z0.s,uxtw]
LDFF1H {Z0.S}, P0/Z, [X0,Z0.S,UXTW]
ldff1h {z0.s}, p0/z, [x0,z0.s,uxtw #0]
ldff1h z1.s, p0/z, [x0,z0.s,uxtw]
ldff1h {z1.s}, p0/z, [x0,z0.s,uxtw]
LDFF1H {Z1.S}, P0/Z, [X0,Z0.S,UXTW]
ldff1h {z1.s}, p0/z, [x0,z0.s,uxtw #0]
ldff1h z31.s, p0/z, [x0,z0.s,uxtw]
ldff1h {z31.s}, p0/z, [x0,z0.s,uxtw]
LDFF1H {Z31.S}, P0/Z, [X0,Z0.S,UXTW]
ldff1h {z31.s}, p0/z, [x0,z0.s,uxtw #0]
ldff1h {z0.s}, p2/z, [x0,z0.s,uxtw]
LDFF1H {Z0.S}, P2/Z, [X0,Z0.S,UXTW]
ldff1h {z0.s}, p2/z, [x0,z0.s,uxtw #0]
ldff1h {z0.s}, p7/z, [x0,z0.s,uxtw]
LDFF1H {Z0.S}, P7/Z, [X0,Z0.S,UXTW]
ldff1h {z0.s}, p7/z, [x0,z0.s,uxtw #0]
ldff1h {z0.s}, p0/z, [x3,z0.s,uxtw]
LDFF1H {Z0.S}, P0/Z, [X3,Z0.S,UXTW]
ldff1h {z0.s}, p0/z, [x3,z0.s,uxtw #0]
ldff1h {z0.s}, p0/z, [sp,z0.s,uxtw]
LDFF1H {Z0.S}, P0/Z, [SP,Z0.S,UXTW]
ldff1h {z0.s}, p0/z, [sp,z0.s,uxtw #0]
ldff1h {z0.s}, p0/z, [x0,z4.s,uxtw]
LDFF1H {Z0.S}, P0/Z, [X0,Z4.S,UXTW]
ldff1h {z0.s}, p0/z, [x0,z4.s,uxtw #0]
ldff1h {z0.s}, p0/z, [x0,z31.s,uxtw]
LDFF1H {Z0.S}, P0/Z, [X0,Z31.S,UXTW]
ldff1h {z0.s}, p0/z, [x0,z31.s,uxtw #0]
ldff1h z0.s, p0/z, [x0,z0.s,sxtw]
ldff1h {z0.s}, p0/z, [x0,z0.s,sxtw]
LDFF1H {Z0.S}, P0/Z, [X0,Z0.S,SXTW]
ldff1h {z0.s}, p0/z, [x0,z0.s,sxtw #0]
ldff1h z1.s, p0/z, [x0,z0.s,sxtw]
ldff1h {z1.s}, p0/z, [x0,z0.s,sxtw]
LDFF1H {Z1.S}, P0/Z, [X0,Z0.S,SXTW]
ldff1h {z1.s}, p0/z, [x0,z0.s,sxtw #0]
ldff1h z31.s, p0/z, [x0,z0.s,sxtw]
ldff1h {z31.s}, p0/z, [x0,z0.s,sxtw]
LDFF1H {Z31.S}, P0/Z, [X0,Z0.S,SXTW]
ldff1h {z31.s}, p0/z, [x0,z0.s,sxtw #0]
ldff1h {z0.s}, p2/z, [x0,z0.s,sxtw]
LDFF1H {Z0.S}, P2/Z, [X0,Z0.S,SXTW]
ldff1h {z0.s}, p2/z, [x0,z0.s,sxtw #0]
ldff1h {z0.s}, p7/z, [x0,z0.s,sxtw]
LDFF1H {Z0.S}, P7/Z, [X0,Z0.S,SXTW]
ldff1h {z0.s}, p7/z, [x0,z0.s,sxtw #0]
ldff1h {z0.s}, p0/z, [x3,z0.s,sxtw]
LDFF1H {Z0.S}, P0/Z, [X3,Z0.S,SXTW]
ldff1h {z0.s}, p0/z, [x3,z0.s,sxtw #0]
ldff1h {z0.s}, p0/z, [sp,z0.s,sxtw]
LDFF1H {Z0.S}, P0/Z, [SP,Z0.S,SXTW]
ldff1h {z0.s}, p0/z, [sp,z0.s,sxtw #0]
ldff1h {z0.s}, p0/z, [x0,z4.s,sxtw]
LDFF1H {Z0.S}, P0/Z, [X0,Z4.S,SXTW]
ldff1h {z0.s}, p0/z, [x0,z4.s,sxtw #0]
ldff1h {z0.s}, p0/z, [x0,z31.s,sxtw]
LDFF1H {Z0.S}, P0/Z, [X0,Z31.S,SXTW]
ldff1h {z0.s}, p0/z, [x0,z31.s,sxtw #0]
ldff1h z0.s, p0/z, [x0,z0.s,uxtw #1]
ldff1h {z0.s}, p0/z, [x0,z0.s,uxtw #1]
LDFF1H {Z0.S}, P0/Z, [X0,Z0.S,UXTW #1]
ldff1h z1.s, p0/z, [x0,z0.s,uxtw #1]
ldff1h {z1.s}, p0/z, [x0,z0.s,uxtw #1]
LDFF1H {Z1.S}, P0/Z, [X0,Z0.S,UXTW #1]
ldff1h z31.s, p0/z, [x0,z0.s,uxtw #1]
ldff1h {z31.s}, p0/z, [x0,z0.s,uxtw #1]
LDFF1H {Z31.S}, P0/Z, [X0,Z0.S,UXTW #1]
ldff1h {z0.s}, p2/z, [x0,z0.s,uxtw #1]
LDFF1H {Z0.S}, P2/Z, [X0,Z0.S,UXTW #1]
ldff1h {z0.s}, p7/z, [x0,z0.s,uxtw #1]
LDFF1H {Z0.S}, P7/Z, [X0,Z0.S,UXTW #1]
ldff1h {z0.s}, p0/z, [x3,z0.s,uxtw #1]
LDFF1H {Z0.S}, P0/Z, [X3,Z0.S,UXTW #1]
ldff1h {z0.s}, p0/z, [sp,z0.s,uxtw #1]
LDFF1H {Z0.S}, P0/Z, [SP,Z0.S,UXTW #1]
ldff1h {z0.s}, p0/z, [x0,z4.s,uxtw #1]
LDFF1H {Z0.S}, P0/Z, [X0,Z4.S,UXTW #1]
ldff1h {z0.s}, p0/z, [x0,z31.s,uxtw #1]
LDFF1H {Z0.S}, P0/Z, [X0,Z31.S,UXTW #1]
ldff1h z0.s, p0/z, [x0,z0.s,sxtw #1]
ldff1h {z0.s}, p0/z, [x0,z0.s,sxtw #1]
LDFF1H {Z0.S}, P0/Z, [X0,Z0.S,SXTW #1]
ldff1h z1.s, p0/z, [x0,z0.s,sxtw #1]
ldff1h {z1.s}, p0/z, [x0,z0.s,sxtw #1]
LDFF1H {Z1.S}, P0/Z, [X0,Z0.S,SXTW #1]
ldff1h z31.s, p0/z, [x0,z0.s,sxtw #1]
ldff1h {z31.s}, p0/z, [x0,z0.s,sxtw #1]
LDFF1H {Z31.S}, P0/Z, [X0,Z0.S,SXTW #1]
ldff1h {z0.s}, p2/z, [x0,z0.s,sxtw #1]
LDFF1H {Z0.S}, P2/Z, [X0,Z0.S,SXTW #1]
ldff1h {z0.s}, p7/z, [x0,z0.s,sxtw #1]
LDFF1H {Z0.S}, P7/Z, [X0,Z0.S,SXTW #1]
ldff1h {z0.s}, p0/z, [x3,z0.s,sxtw #1]
LDFF1H {Z0.S}, P0/Z, [X3,Z0.S,SXTW #1]
ldff1h {z0.s}, p0/z, [sp,z0.s,sxtw #1]
LDFF1H {Z0.S}, P0/Z, [SP,Z0.S,SXTW #1]
ldff1h {z0.s}, p0/z, [x0,z4.s,sxtw #1]
LDFF1H {Z0.S}, P0/Z, [X0,Z4.S,SXTW #1]
ldff1h {z0.s}, p0/z, [x0,z31.s,sxtw #1]
LDFF1H {Z0.S}, P0/Z, [X0,Z31.S,SXTW #1]
ldff1h z0.h, p0/z, [x0,x0,lsl #1]
ldff1h {z0.h}, p0/z, [x0,x0,lsl #1]
LDFF1H {Z0.H}, P0/Z, [X0,X0,LSL #1]
ldff1h z1.h, p0/z, [x0,x0,lsl #1]
ldff1h {z1.h}, p0/z, [x0,x0,lsl #1]
LDFF1H {Z1.H}, P0/Z, [X0,X0,LSL #1]
ldff1h z31.h, p0/z, [x0,x0,lsl #1]
ldff1h {z31.h}, p0/z, [x0,x0,lsl #1]
LDFF1H {Z31.H}, P0/Z, [X0,X0,LSL #1]
ldff1h {z0.h}, p2/z, [x0,x0,lsl #1]
LDFF1H {Z0.H}, P2/Z, [X0,X0,LSL #1]
ldff1h {z0.h}, p7/z, [x0,x0,lsl #1]
LDFF1H {Z0.H}, P7/Z, [X0,X0,LSL #1]
ldff1h {z0.h}, p0/z, [x3,x0,lsl #1]
LDFF1H {Z0.H}, P0/Z, [X3,X0,LSL #1]
ldff1h {z0.h}, p0/z, [sp,x0,lsl #1]
LDFF1H {Z0.H}, P0/Z, [SP,X0,LSL #1]
ldff1h {z0.h}, p0/z, [x0,x4,lsl #1]
LDFF1H {Z0.H}, P0/Z, [X0,X4,LSL #1]
ldff1h {z0.h}, p0/z, [x0,xzr,lsl #1]
LDFF1H {Z0.H}, P0/Z, [X0,XZR,LSL #1]
ldff1h z0.s, p0/z, [x0,x0,lsl #1]
ldff1h {z0.s}, p0/z, [x0,x0,lsl #1]
LDFF1H {Z0.S}, P0/Z, [X0,X0,LSL #1]
ldff1h z1.s, p0/z, [x0,x0,lsl #1]
ldff1h {z1.s}, p0/z, [x0,x0,lsl #1]
LDFF1H {Z1.S}, P0/Z, [X0,X0,LSL #1]
ldff1h z31.s, p0/z, [x0,x0,lsl #1]
ldff1h {z31.s}, p0/z, [x0,x0,lsl #1]
LDFF1H {Z31.S}, P0/Z, [X0,X0,LSL #1]
ldff1h {z0.s}, p2/z, [x0,x0,lsl #1]
LDFF1H {Z0.S}, P2/Z, [X0,X0,LSL #1]
ldff1h {z0.s}, p7/z, [x0,x0,lsl #1]
LDFF1H {Z0.S}, P7/Z, [X0,X0,LSL #1]
ldff1h {z0.s}, p0/z, [x3,x0,lsl #1]
LDFF1H {Z0.S}, P0/Z, [X3,X0,LSL #1]
ldff1h {z0.s}, p0/z, [sp,x0,lsl #1]
LDFF1H {Z0.S}, P0/Z, [SP,X0,LSL #1]
ldff1h {z0.s}, p0/z, [x0,x4,lsl #1]
LDFF1H {Z0.S}, P0/Z, [X0,X4,LSL #1]
ldff1h {z0.s}, p0/z, [x0,xzr,lsl #1]
LDFF1H {Z0.S}, P0/Z, [X0,XZR,LSL #1]
ldff1h z0.d, p0/z, [x0,x0,lsl #1]
ldff1h {z0.d}, p0/z, [x0,x0,lsl #1]
LDFF1H {Z0.D}, P0/Z, [X0,X0,LSL #1]
ldff1h z1.d, p0/z, [x0,x0,lsl #1]
ldff1h {z1.d}, p0/z, [x0,x0,lsl #1]
LDFF1H {Z1.D}, P0/Z, [X0,X0,LSL #1]
ldff1h z31.d, p0/z, [x0,x0,lsl #1]
ldff1h {z31.d}, p0/z, [x0,x0,lsl #1]
LDFF1H {Z31.D}, P0/Z, [X0,X0,LSL #1]
ldff1h {z0.d}, p2/z, [x0,x0,lsl #1]
LDFF1H {Z0.D}, P2/Z, [X0,X0,LSL #1]
ldff1h {z0.d}, p7/z, [x0,x0,lsl #1]
LDFF1H {Z0.D}, P7/Z, [X0,X0,LSL #1]
ldff1h {z0.d}, p0/z, [x3,x0,lsl #1]
LDFF1H {Z0.D}, P0/Z, [X3,X0,LSL #1]
ldff1h {z0.d}, p0/z, [sp,x0,lsl #1]
LDFF1H {Z0.D}, P0/Z, [SP,X0,LSL #1]
ldff1h {z0.d}, p0/z, [x0,x4,lsl #1]
LDFF1H {Z0.D}, P0/Z, [X0,X4,LSL #1]
ldff1h {z0.d}, p0/z, [x0,xzr,lsl #1]
LDFF1H {Z0.D}, P0/Z, [X0,XZR,LSL #1]
ldff1h z0.d, p0/z, [x0,z0.d,uxtw]
ldff1h {z0.d}, p0/z, [x0,z0.d,uxtw]
LDFF1H {Z0.D}, P0/Z, [X0,Z0.D,UXTW]
ldff1h {z0.d}, p0/z, [x0,z0.d,uxtw #0]
ldff1h z1.d, p0/z, [x0,z0.d,uxtw]
ldff1h {z1.d}, p0/z, [x0,z0.d,uxtw]
LDFF1H {Z1.D}, P0/Z, [X0,Z0.D,UXTW]
ldff1h {z1.d}, p0/z, [x0,z0.d,uxtw #0]
ldff1h z31.d, p0/z, [x0,z0.d,uxtw]
ldff1h {z31.d}, p0/z, [x0,z0.d,uxtw]
LDFF1H {Z31.D}, P0/Z, [X0,Z0.D,UXTW]
ldff1h {z31.d}, p0/z, [x0,z0.d,uxtw #0]
ldff1h {z0.d}, p2/z, [x0,z0.d,uxtw]
LDFF1H {Z0.D}, P2/Z, [X0,Z0.D,UXTW]
ldff1h {z0.d}, p2/z, [x0,z0.d,uxtw #0]
ldff1h {z0.d}, p7/z, [x0,z0.d,uxtw]
LDFF1H {Z0.D}, P7/Z, [X0,Z0.D,UXTW]
ldff1h {z0.d}, p7/z, [x0,z0.d,uxtw #0]
ldff1h {z0.d}, p0/z, [x3,z0.d,uxtw]
LDFF1H {Z0.D}, P0/Z, [X3,Z0.D,UXTW]
ldff1h {z0.d}, p0/z, [x3,z0.d,uxtw #0]
ldff1h {z0.d}, p0/z, [sp,z0.d,uxtw]
LDFF1H {Z0.D}, P0/Z, [SP,Z0.D,UXTW]
ldff1h {z0.d}, p0/z, [sp,z0.d,uxtw #0]
ldff1h {z0.d}, p0/z, [x0,z4.d,uxtw]
LDFF1H {Z0.D}, P0/Z, [X0,Z4.D,UXTW]
ldff1h {z0.d}, p0/z, [x0,z4.d,uxtw #0]
ldff1h {z0.d}, p0/z, [x0,z31.d,uxtw]
LDFF1H {Z0.D}, P0/Z, [X0,Z31.D,UXTW]
ldff1h {z0.d}, p0/z, [x0,z31.d,uxtw #0]
ldff1h z0.d, p0/z, [x0,z0.d,sxtw]
ldff1h {z0.d}, p0/z, [x0,z0.d,sxtw]
LDFF1H {Z0.D}, P0/Z, [X0,Z0.D,SXTW]
ldff1h {z0.d}, p0/z, [x0,z0.d,sxtw #0]
ldff1h z1.d, p0/z, [x0,z0.d,sxtw]
ldff1h {z1.d}, p0/z, [x0,z0.d,sxtw]
LDFF1H {Z1.D}, P0/Z, [X0,Z0.D,SXTW]
ldff1h {z1.d}, p0/z, [x0,z0.d,sxtw #0]
ldff1h z31.d, p0/z, [x0,z0.d,sxtw]
ldff1h {z31.d}, p0/z, [x0,z0.d,sxtw]
LDFF1H {Z31.D}, P0/Z, [X0,Z0.D,SXTW]
ldff1h {z31.d}, p0/z, [x0,z0.d,sxtw #0]
ldff1h {z0.d}, p2/z, [x0,z0.d,sxtw]
LDFF1H {Z0.D}, P2/Z, [X0,Z0.D,SXTW]
ldff1h {z0.d}, p2/z, [x0,z0.d,sxtw #0]
ldff1h {z0.d}, p7/z, [x0,z0.d,sxtw]
LDFF1H {Z0.D}, P7/Z, [X0,Z0.D,SXTW]
ldff1h {z0.d}, p7/z, [x0,z0.d,sxtw #0]
ldff1h {z0.d}, p0/z, [x3,z0.d,sxtw]
LDFF1H {Z0.D}, P0/Z, [X3,Z0.D,SXTW]
ldff1h {z0.d}, p0/z, [x3,z0.d,sxtw #0]
ldff1h {z0.d}, p0/z, [sp,z0.d,sxtw]
LDFF1H {Z0.D}, P0/Z, [SP,Z0.D,SXTW]
ldff1h {z0.d}, p0/z, [sp,z0.d,sxtw #0]
ldff1h {z0.d}, p0/z, [x0,z4.d,sxtw]
LDFF1H {Z0.D}, P0/Z, [X0,Z4.D,SXTW]
ldff1h {z0.d}, p0/z, [x0,z4.d,sxtw #0]
ldff1h {z0.d}, p0/z, [x0,z31.d,sxtw]
LDFF1H {Z0.D}, P0/Z, [X0,Z31.D,SXTW]
ldff1h {z0.d}, p0/z, [x0,z31.d,sxtw #0]
ldff1h z0.d, p0/z, [x0,z0.d,uxtw #1]
ldff1h {z0.d}, p0/z, [x0,z0.d,uxtw #1]
LDFF1H {Z0.D}, P0/Z, [X0,Z0.D,UXTW #1]
ldff1h z1.d, p0/z, [x0,z0.d,uxtw #1]
ldff1h {z1.d}, p0/z, [x0,z0.d,uxtw #1]
LDFF1H {Z1.D}, P0/Z, [X0,Z0.D,UXTW #1]
ldff1h z31.d, p0/z, [x0,z0.d,uxtw #1]
ldff1h {z31.d}, p0/z, [x0,z0.d,uxtw #1]
LDFF1H {Z31.D}, P0/Z, [X0,Z0.D,UXTW #1]
ldff1h {z0.d}, p2/z, [x0,z0.d,uxtw #1]
LDFF1H {Z0.D}, P2/Z, [X0,Z0.D,UXTW #1]
ldff1h {z0.d}, p7/z, [x0,z0.d,uxtw #1]
LDFF1H {Z0.D}, P7/Z, [X0,Z0.D,UXTW #1]
ldff1h {z0.d}, p0/z, [x3,z0.d,uxtw #1]
LDFF1H {Z0.D}, P0/Z, [X3,Z0.D,UXTW #1]
ldff1h {z0.d}, p0/z, [sp,z0.d,uxtw #1]
LDFF1H {Z0.D}, P0/Z, [SP,Z0.D,UXTW #1]
ldff1h {z0.d}, p0/z, [x0,z4.d,uxtw #1]
LDFF1H {Z0.D}, P0/Z, [X0,Z4.D,UXTW #1]
ldff1h {z0.d}, p0/z, [x0,z31.d,uxtw #1]
LDFF1H {Z0.D}, P0/Z, [X0,Z31.D,UXTW #1]
ldff1h z0.d, p0/z, [x0,z0.d,sxtw #1]
ldff1h {z0.d}, p0/z, [x0,z0.d,sxtw #1]
LDFF1H {Z0.D}, P0/Z, [X0,Z0.D,SXTW #1]
ldff1h z1.d, p0/z, [x0,z0.d,sxtw #1]
ldff1h {z1.d}, p0/z, [x0,z0.d,sxtw #1]
LDFF1H {Z1.D}, P0/Z, [X0,Z0.D,SXTW #1]
ldff1h z31.d, p0/z, [x0,z0.d,sxtw #1]
ldff1h {z31.d}, p0/z, [x0,z0.d,sxtw #1]
LDFF1H {Z31.D}, P0/Z, [X0,Z0.D,SXTW #1]
ldff1h {z0.d}, p2/z, [x0,z0.d,sxtw #1]
LDFF1H {Z0.D}, P2/Z, [X0,Z0.D,SXTW #1]
ldff1h {z0.d}, p7/z, [x0,z0.d,sxtw #1]
LDFF1H {Z0.D}, P7/Z, [X0,Z0.D,SXTW #1]
ldff1h {z0.d}, p0/z, [x3,z0.d,sxtw #1]
LDFF1H {Z0.D}, P0/Z, [X3,Z0.D,SXTW #1]
ldff1h {z0.d}, p0/z, [sp,z0.d,sxtw #1]
LDFF1H {Z0.D}, P0/Z, [SP,Z0.D,SXTW #1]
ldff1h {z0.d}, p0/z, [x0,z4.d,sxtw #1]
LDFF1H {Z0.D}, P0/Z, [X0,Z4.D,SXTW #1]
ldff1h {z0.d}, p0/z, [x0,z31.d,sxtw #1]
LDFF1H {Z0.D}, P0/Z, [X0,Z31.D,SXTW #1]
ldff1h z0.d, p0/z, [x0,z0.d]
ldff1h {z0.d}, p0/z, [x0,z0.d]
LDFF1H {Z0.D}, P0/Z, [X0,Z0.D]
ldff1h {z0.d}, p0/z, [x0,z0.d,lsl #0]
ldff1h z1.d, p0/z, [x0,z0.d]
ldff1h {z1.d}, p0/z, [x0,z0.d]
LDFF1H {Z1.D}, P0/Z, [X0,Z0.D]
ldff1h {z1.d}, p0/z, [x0,z0.d,lsl #0]
ldff1h z31.d, p0/z, [x0,z0.d]
ldff1h {z31.d}, p0/z, [x0,z0.d]
LDFF1H {Z31.D}, P0/Z, [X0,Z0.D]
ldff1h {z31.d}, p0/z, [x0,z0.d,lsl #0]
ldff1h {z0.d}, p2/z, [x0,z0.d]
LDFF1H {Z0.D}, P2/Z, [X0,Z0.D]
ldff1h {z0.d}, p2/z, [x0,z0.d,lsl #0]
ldff1h {z0.d}, p7/z, [x0,z0.d]
LDFF1H {Z0.D}, P7/Z, [X0,Z0.D]
ldff1h {z0.d}, p7/z, [x0,z0.d,lsl #0]
ldff1h {z0.d}, p0/z, [x3,z0.d]
LDFF1H {Z0.D}, P0/Z, [X3,Z0.D]
ldff1h {z0.d}, p0/z, [x3,z0.d,lsl #0]
ldff1h {z0.d}, p0/z, [sp,z0.d]
LDFF1H {Z0.D}, P0/Z, [SP,Z0.D]
ldff1h {z0.d}, p0/z, [sp,z0.d,lsl #0]
ldff1h {z0.d}, p0/z, [x0,z4.d]
LDFF1H {Z0.D}, P0/Z, [X0,Z4.D]
ldff1h {z0.d}, p0/z, [x0,z4.d,lsl #0]
ldff1h {z0.d}, p0/z, [x0,z31.d]
LDFF1H {Z0.D}, P0/Z, [X0,Z31.D]
ldff1h {z0.d}, p0/z, [x0,z31.d,lsl #0]
ldff1h z0.d, p0/z, [x0,z0.d,lsl #1]
ldff1h {z0.d}, p0/z, [x0,z0.d,lsl #1]
LDFF1H {Z0.D}, P0/Z, [X0,Z0.D,LSL #1]
ldff1h z1.d, p0/z, [x0,z0.d,lsl #1]
ldff1h {z1.d}, p0/z, [x0,z0.d,lsl #1]
LDFF1H {Z1.D}, P0/Z, [X0,Z0.D,LSL #1]
ldff1h z31.d, p0/z, [x0,z0.d,lsl #1]
ldff1h {z31.d}, p0/z, [x0,z0.d,lsl #1]
LDFF1H {Z31.D}, P0/Z, [X0,Z0.D,LSL #1]
ldff1h {z0.d}, p2/z, [x0,z0.d,lsl #1]
LDFF1H {Z0.D}, P2/Z, [X0,Z0.D,LSL #1]
ldff1h {z0.d}, p7/z, [x0,z0.d,lsl #1]
LDFF1H {Z0.D}, P7/Z, [X0,Z0.D,LSL #1]
ldff1h {z0.d}, p0/z, [x3,z0.d,lsl #1]
LDFF1H {Z0.D}, P0/Z, [X3,Z0.D,LSL #1]
ldff1h {z0.d}, p0/z, [sp,z0.d,lsl #1]
LDFF1H {Z0.D}, P0/Z, [SP,Z0.D,LSL #1]
ldff1h {z0.d}, p0/z, [x0,z4.d,lsl #1]
LDFF1H {Z0.D}, P0/Z, [X0,Z4.D,LSL #1]
ldff1h {z0.d}, p0/z, [x0,z31.d,lsl #1]
LDFF1H {Z0.D}, P0/Z, [X0,Z31.D,LSL #1]
ldff1h z0.s, p0/z, [z0.s,#0]
ldff1h {z0.s}, p0/z, [z0.s,#0]
LDFF1H {Z0.S}, P0/Z, [Z0.S,#0]
ldff1h {z0.s}, p0/z, [z0.s]
ldff1h z1.s, p0/z, [z0.s,#0]
ldff1h {z1.s}, p0/z, [z0.s,#0]
LDFF1H {Z1.S}, P0/Z, [Z0.S,#0]
ldff1h {z1.s}, p0/z, [z0.s]
ldff1h z31.s, p0/z, [z0.s,#0]
ldff1h {z31.s}, p0/z, [z0.s,#0]
LDFF1H {Z31.S}, P0/Z, [Z0.S,#0]
ldff1h {z31.s}, p0/z, [z0.s]
ldff1h {z0.s}, p2/z, [z0.s,#0]
LDFF1H {Z0.S}, P2/Z, [Z0.S,#0]
ldff1h {z0.s}, p2/z, [z0.s]
ldff1h {z0.s}, p7/z, [z0.s,#0]
LDFF1H {Z0.S}, P7/Z, [Z0.S,#0]
ldff1h {z0.s}, p7/z, [z0.s]
ldff1h {z0.s}, p0/z, [z3.s,#0]
LDFF1H {Z0.S}, P0/Z, [Z3.S,#0]
ldff1h {z0.s}, p0/z, [z3.s]
ldff1h {z0.s}, p0/z, [z31.s,#0]
LDFF1H {Z0.S}, P0/Z, [Z31.S,#0]
ldff1h {z0.s}, p0/z, [z31.s]
ldff1h {z0.s}, p0/z, [z0.s,#30]
LDFF1H {Z0.S}, P0/Z, [Z0.S,#30]
ldff1h {z0.s}, p0/z, [z0.s,#32]
LDFF1H {Z0.S}, P0/Z, [Z0.S,#32]
ldff1h {z0.s}, p0/z, [z0.s,#34]
LDFF1H {Z0.S}, P0/Z, [Z0.S,#34]
ldff1h {z0.s}, p0/z, [z0.s,#62]
LDFF1H {Z0.S}, P0/Z, [Z0.S,#62]
ldff1h z0.d, p0/z, [z0.d,#0]
ldff1h {z0.d}, p0/z, [z0.d,#0]
LDFF1H {Z0.D}, P0/Z, [Z0.D,#0]
ldff1h {z0.d}, p0/z, [z0.d]
ldff1h z1.d, p0/z, [z0.d,#0]
ldff1h {z1.d}, p0/z, [z0.d,#0]
LDFF1H {Z1.D}, P0/Z, [Z0.D,#0]
ldff1h {z1.d}, p0/z, [z0.d]
ldff1h z31.d, p0/z, [z0.d,#0]
ldff1h {z31.d}, p0/z, [z0.d,#0]
LDFF1H {Z31.D}, P0/Z, [Z0.D,#0]
ldff1h {z31.d}, p0/z, [z0.d]
ldff1h {z0.d}, p2/z, [z0.d,#0]
LDFF1H {Z0.D}, P2/Z, [Z0.D,#0]
ldff1h {z0.d}, p2/z, [z0.d]
ldff1h {z0.d}, p7/z, [z0.d,#0]
LDFF1H {Z0.D}, P7/Z, [Z0.D,#0]
ldff1h {z0.d}, p7/z, [z0.d]
ldff1h {z0.d}, p0/z, [z3.d,#0]
LDFF1H {Z0.D}, P0/Z, [Z3.D,#0]
ldff1h {z0.d}, p0/z, [z3.d]
ldff1h {z0.d}, p0/z, [z31.d,#0]
LDFF1H {Z0.D}, P0/Z, [Z31.D,#0]
ldff1h {z0.d}, p0/z, [z31.d]
ldff1h {z0.d}, p0/z, [z0.d,#30]
LDFF1H {Z0.D}, P0/Z, [Z0.D,#30]
ldff1h {z0.d}, p0/z, [z0.d,#32]
LDFF1H {Z0.D}, P0/Z, [Z0.D,#32]
ldff1h {z0.d}, p0/z, [z0.d,#34]
LDFF1H {Z0.D}, P0/Z, [Z0.D,#34]
ldff1h {z0.d}, p0/z, [z0.d,#62]
LDFF1H {Z0.D}, P0/Z, [Z0.D,#62]
ldff1sb z0.s, p0/z, [x0,z0.s,uxtw]
ldff1sb {z0.s}, p0/z, [x0,z0.s,uxtw]
LDFF1SB {Z0.S}, P0/Z, [X0,Z0.S,UXTW]
ldff1sb {z0.s}, p0/z, [x0,z0.s,uxtw #0]
ldff1sb z1.s, p0/z, [x0,z0.s,uxtw]
ldff1sb {z1.s}, p0/z, [x0,z0.s,uxtw]
LDFF1SB {Z1.S}, P0/Z, [X0,Z0.S,UXTW]
ldff1sb {z1.s}, p0/z, [x0,z0.s,uxtw #0]
ldff1sb z31.s, p0/z, [x0,z0.s,uxtw]
ldff1sb {z31.s}, p0/z, [x0,z0.s,uxtw]
LDFF1SB {Z31.S}, P0/Z, [X0,Z0.S,UXTW]
ldff1sb {z31.s}, p0/z, [x0,z0.s,uxtw #0]
ldff1sb {z0.s}, p2/z, [x0,z0.s,uxtw]
LDFF1SB {Z0.S}, P2/Z, [X0,Z0.S,UXTW]
ldff1sb {z0.s}, p2/z, [x0,z0.s,uxtw #0]
ldff1sb {z0.s}, p7/z, [x0,z0.s,uxtw]
LDFF1SB {Z0.S}, P7/Z, [X0,Z0.S,UXTW]
ldff1sb {z0.s}, p7/z, [x0,z0.s,uxtw #0]
ldff1sb {z0.s}, p0/z, [x3,z0.s,uxtw]
LDFF1SB {Z0.S}, P0/Z, [X3,Z0.S,UXTW]
ldff1sb {z0.s}, p0/z, [x3,z0.s,uxtw #0]
ldff1sb {z0.s}, p0/z, [sp,z0.s,uxtw]
LDFF1SB {Z0.S}, P0/Z, [SP,Z0.S,UXTW]
ldff1sb {z0.s}, p0/z, [sp,z0.s,uxtw #0]
ldff1sb {z0.s}, p0/z, [x0,z4.s,uxtw]
LDFF1SB {Z0.S}, P0/Z, [X0,Z4.S,UXTW]
ldff1sb {z0.s}, p0/z, [x0,z4.s,uxtw #0]
ldff1sb {z0.s}, p0/z, [x0,z31.s,uxtw]
LDFF1SB {Z0.S}, P0/Z, [X0,Z31.S,UXTW]
ldff1sb {z0.s}, p0/z, [x0,z31.s,uxtw #0]
ldff1sb z0.s, p0/z, [x0,z0.s,sxtw]
ldff1sb {z0.s}, p0/z, [x0,z0.s,sxtw]
LDFF1SB {Z0.S}, P0/Z, [X0,Z0.S,SXTW]
ldff1sb {z0.s}, p0/z, [x0,z0.s,sxtw #0]
ldff1sb z1.s, p0/z, [x0,z0.s,sxtw]
ldff1sb {z1.s}, p0/z, [x0,z0.s,sxtw]
LDFF1SB {Z1.S}, P0/Z, [X0,Z0.S,SXTW]
ldff1sb {z1.s}, p0/z, [x0,z0.s,sxtw #0]
ldff1sb z31.s, p0/z, [x0,z0.s,sxtw]
ldff1sb {z31.s}, p0/z, [x0,z0.s,sxtw]
LDFF1SB {Z31.S}, P0/Z, [X0,Z0.S,SXTW]
ldff1sb {z31.s}, p0/z, [x0,z0.s,sxtw #0]
ldff1sb {z0.s}, p2/z, [x0,z0.s,sxtw]
LDFF1SB {Z0.S}, P2/Z, [X0,Z0.S,SXTW]
ldff1sb {z0.s}, p2/z, [x0,z0.s,sxtw #0]
ldff1sb {z0.s}, p7/z, [x0,z0.s,sxtw]
LDFF1SB {Z0.S}, P7/Z, [X0,Z0.S,SXTW]
ldff1sb {z0.s}, p7/z, [x0,z0.s,sxtw #0]
ldff1sb {z0.s}, p0/z, [x3,z0.s,sxtw]
LDFF1SB {Z0.S}, P0/Z, [X3,Z0.S,SXTW]
ldff1sb {z0.s}, p0/z, [x3,z0.s,sxtw #0]
ldff1sb {z0.s}, p0/z, [sp,z0.s,sxtw]
LDFF1SB {Z0.S}, P0/Z, [SP,Z0.S,SXTW]
ldff1sb {z0.s}, p0/z, [sp,z0.s,sxtw #0]
ldff1sb {z0.s}, p0/z, [x0,z4.s,sxtw]
LDFF1SB {Z0.S}, P0/Z, [X0,Z4.S,SXTW]
ldff1sb {z0.s}, p0/z, [x0,z4.s,sxtw #0]
ldff1sb {z0.s}, p0/z, [x0,z31.s,sxtw]
LDFF1SB {Z0.S}, P0/Z, [X0,Z31.S,SXTW]
ldff1sb {z0.s}, p0/z, [x0,z31.s,sxtw #0]
ldff1sb z0.d, p0/z, [x0,x0]
ldff1sb {z0.d}, p0/z, [x0,x0]
LDFF1SB {Z0.D}, P0/Z, [X0,X0]
ldff1sb {z0.d}, p0/z, [x0,x0,lsl #0]
ldff1sb z1.d, p0/z, [x0,x0]
ldff1sb {z1.d}, p0/z, [x0,x0]
LDFF1SB {Z1.D}, P0/Z, [X0,X0]
ldff1sb {z1.d}, p0/z, [x0,x0,lsl #0]
ldff1sb z31.d, p0/z, [x0,x0]
ldff1sb {z31.d}, p0/z, [x0,x0]
LDFF1SB {Z31.D}, P0/Z, [X0,X0]
ldff1sb {z31.d}, p0/z, [x0,x0,lsl #0]
ldff1sb {z0.d}, p2/z, [x0,x0]
LDFF1SB {Z0.D}, P2/Z, [X0,X0]
ldff1sb {z0.d}, p2/z, [x0,x0,lsl #0]
ldff1sb {z0.d}, p7/z, [x0,x0]
LDFF1SB {Z0.D}, P7/Z, [X0,X0]
ldff1sb {z0.d}, p7/z, [x0,x0,lsl #0]
ldff1sb {z0.d}, p0/z, [x3,x0]
LDFF1SB {Z0.D}, P0/Z, [X3,X0]
ldff1sb {z0.d}, p0/z, [x3,x0,lsl #0]
ldff1sb {z0.d}, p0/z, [sp,x0]
LDFF1SB {Z0.D}, P0/Z, [SP,X0]
ldff1sb {z0.d}, p0/z, [sp,x0,lsl #0]
ldff1sb {z0.d}, p0/z, [x0,x4]
LDFF1SB {Z0.D}, P0/Z, [X0,X4]
ldff1sb {z0.d}, p0/z, [x0,x4,lsl #0]
ldff1sb {z0.d}, p0/z, [x0,xzr]
LDFF1SB {Z0.D}, P0/Z, [X0,XZR]
ldff1sb {z0.d}, p0/z, [x0,xzr,lsl #0]
ldff1sb z0.s, p0/z, [x0,x0]
ldff1sb {z0.s}, p0/z, [x0,x0]
LDFF1SB {Z0.S}, P0/Z, [X0,X0]
ldff1sb {z0.s}, p0/z, [x0,x0,lsl #0]
ldff1sb z1.s, p0/z, [x0,x0]
ldff1sb {z1.s}, p0/z, [x0,x0]
LDFF1SB {Z1.S}, P0/Z, [X0,X0]
ldff1sb {z1.s}, p0/z, [x0,x0,lsl #0]
ldff1sb z31.s, p0/z, [x0,x0]
ldff1sb {z31.s}, p0/z, [x0,x0]
LDFF1SB {Z31.S}, P0/Z, [X0,X0]
ldff1sb {z31.s}, p0/z, [x0,x0,lsl #0]
ldff1sb {z0.s}, p2/z, [x0,x0]
LDFF1SB {Z0.S}, P2/Z, [X0,X0]
ldff1sb {z0.s}, p2/z, [x0,x0,lsl #0]
ldff1sb {z0.s}, p7/z, [x0,x0]
LDFF1SB {Z0.S}, P7/Z, [X0,X0]
ldff1sb {z0.s}, p7/z, [x0,x0,lsl #0]
ldff1sb {z0.s}, p0/z, [x3,x0]
LDFF1SB {Z0.S}, P0/Z, [X3,X0]
ldff1sb {z0.s}, p0/z, [x3,x0,lsl #0]
ldff1sb {z0.s}, p0/z, [sp,x0]
LDFF1SB {Z0.S}, P0/Z, [SP,X0]
ldff1sb {z0.s}, p0/z, [sp,x0,lsl #0]
ldff1sb {z0.s}, p0/z, [x0,x4]
LDFF1SB {Z0.S}, P0/Z, [X0,X4]
ldff1sb {z0.s}, p0/z, [x0,x4,lsl #0]
ldff1sb {z0.s}, p0/z, [x0,xzr]
LDFF1SB {Z0.S}, P0/Z, [X0,XZR]
ldff1sb {z0.s}, p0/z, [x0,xzr,lsl #0]
ldff1sb z0.h, p0/z, [x0,x0]
ldff1sb {z0.h}, p0/z, [x0,x0]
LDFF1SB {Z0.H}, P0/Z, [X0,X0]
ldff1sb {z0.h}, p0/z, [x0,x0,lsl #0]
ldff1sb z1.h, p0/z, [x0,x0]
ldff1sb {z1.h}, p0/z, [x0,x0]
LDFF1SB {Z1.H}, P0/Z, [X0,X0]
ldff1sb {z1.h}, p0/z, [x0,x0,lsl #0]
ldff1sb z31.h, p0/z, [x0,x0]
ldff1sb {z31.h}, p0/z, [x0,x0]
LDFF1SB {Z31.H}, P0/Z, [X0,X0]
ldff1sb {z31.h}, p0/z, [x0,x0,lsl #0]
ldff1sb {z0.h}, p2/z, [x0,x0]
LDFF1SB {Z0.H}, P2/Z, [X0,X0]
ldff1sb {z0.h}, p2/z, [x0,x0,lsl #0]
ldff1sb {z0.h}, p7/z, [x0,x0]
LDFF1SB {Z0.H}, P7/Z, [X0,X0]
ldff1sb {z0.h}, p7/z, [x0,x0,lsl #0]
ldff1sb {z0.h}, p0/z, [x3,x0]
LDFF1SB {Z0.H}, P0/Z, [X3,X0]
ldff1sb {z0.h}, p0/z, [x3,x0,lsl #0]
ldff1sb {z0.h}, p0/z, [sp,x0]
LDFF1SB {Z0.H}, P0/Z, [SP,X0]
ldff1sb {z0.h}, p0/z, [sp,x0,lsl #0]
ldff1sb {z0.h}, p0/z, [x0,x4]
LDFF1SB {Z0.H}, P0/Z, [X0,X4]
ldff1sb {z0.h}, p0/z, [x0,x4,lsl #0]
ldff1sb {z0.h}, p0/z, [x0,xzr]
LDFF1SB {Z0.H}, P0/Z, [X0,XZR]
ldff1sb {z0.h}, p0/z, [x0,xzr,lsl #0]
ldff1sb z0.d, p0/z, [x0,z0.d,uxtw]
ldff1sb {z0.d}, p0/z, [x0,z0.d,uxtw]
LDFF1SB {Z0.D}, P0/Z, [X0,Z0.D,UXTW]
ldff1sb {z0.d}, p0/z, [x0,z0.d,uxtw #0]
ldff1sb z1.d, p0/z, [x0,z0.d,uxtw]
ldff1sb {z1.d}, p0/z, [x0,z0.d,uxtw]
LDFF1SB {Z1.D}, P0/Z, [X0,Z0.D,UXTW]
ldff1sb {z1.d}, p0/z, [x0,z0.d,uxtw #0]
ldff1sb z31.d, p0/z, [x0,z0.d,uxtw]
ldff1sb {z31.d}, p0/z, [x0,z0.d,uxtw]
LDFF1SB {Z31.D}, P0/Z, [X0,Z0.D,UXTW]
ldff1sb {z31.d}, p0/z, [x0,z0.d,uxtw #0]
ldff1sb {z0.d}, p2/z, [x0,z0.d,uxtw]
LDFF1SB {Z0.D}, P2/Z, [X0,Z0.D,UXTW]
ldff1sb {z0.d}, p2/z, [x0,z0.d,uxtw #0]
ldff1sb {z0.d}, p7/z, [x0,z0.d,uxtw]
LDFF1SB {Z0.D}, P7/Z, [X0,Z0.D,UXTW]
ldff1sb {z0.d}, p7/z, [x0,z0.d,uxtw #0]
ldff1sb {z0.d}, p0/z, [x3,z0.d,uxtw]
LDFF1SB {Z0.D}, P0/Z, [X3,Z0.D,UXTW]
ldff1sb {z0.d}, p0/z, [x3,z0.d,uxtw #0]
ldff1sb {z0.d}, p0/z, [sp,z0.d,uxtw]
LDFF1SB {Z0.D}, P0/Z, [SP,Z0.D,UXTW]
ldff1sb {z0.d}, p0/z, [sp,z0.d,uxtw #0]
ldff1sb {z0.d}, p0/z, [x0,z4.d,uxtw]
LDFF1SB {Z0.D}, P0/Z, [X0,Z4.D,UXTW]
ldff1sb {z0.d}, p0/z, [x0,z4.d,uxtw #0]
ldff1sb {z0.d}, p0/z, [x0,z31.d,uxtw]
LDFF1SB {Z0.D}, P0/Z, [X0,Z31.D,UXTW]
ldff1sb {z0.d}, p0/z, [x0,z31.d,uxtw #0]
ldff1sb z0.d, p0/z, [x0,z0.d,sxtw]
ldff1sb {z0.d}, p0/z, [x0,z0.d,sxtw]
LDFF1SB {Z0.D}, P0/Z, [X0,Z0.D,SXTW]
ldff1sb {z0.d}, p0/z, [x0,z0.d,sxtw #0]
ldff1sb z1.d, p0/z, [x0,z0.d,sxtw]
ldff1sb {z1.d}, p0/z, [x0,z0.d,sxtw]
LDFF1SB {Z1.D}, P0/Z, [X0,Z0.D,SXTW]
ldff1sb {z1.d}, p0/z, [x0,z0.d,sxtw #0]
ldff1sb z31.d, p0/z, [x0,z0.d,sxtw]
ldff1sb {z31.d}, p0/z, [x0,z0.d,sxtw]
LDFF1SB {Z31.D}, P0/Z, [X0,Z0.D,SXTW]
ldff1sb {z31.d}, p0/z, [x0,z0.d,sxtw #0]
ldff1sb {z0.d}, p2/z, [x0,z0.d,sxtw]
LDFF1SB {Z0.D}, P2/Z, [X0,Z0.D,SXTW]
ldff1sb {z0.d}, p2/z, [x0,z0.d,sxtw #0]
ldff1sb {z0.d}, p7/z, [x0,z0.d,sxtw]
LDFF1SB {Z0.D}, P7/Z, [X0,Z0.D,SXTW]
ldff1sb {z0.d}, p7/z, [x0,z0.d,sxtw #0]
ldff1sb {z0.d}, p0/z, [x3,z0.d,sxtw]
LDFF1SB {Z0.D}, P0/Z, [X3,Z0.D,SXTW]
ldff1sb {z0.d}, p0/z, [x3,z0.d,sxtw #0]
ldff1sb {z0.d}, p0/z, [sp,z0.d,sxtw]
LDFF1SB {Z0.D}, P0/Z, [SP,Z0.D,SXTW]
ldff1sb {z0.d}, p0/z, [sp,z0.d,sxtw #0]
ldff1sb {z0.d}, p0/z, [x0,z4.d,sxtw]
LDFF1SB {Z0.D}, P0/Z, [X0,Z4.D,SXTW]
ldff1sb {z0.d}, p0/z, [x0,z4.d,sxtw #0]
ldff1sb {z0.d}, p0/z, [x0,z31.d,sxtw]
LDFF1SB {Z0.D}, P0/Z, [X0,Z31.D,SXTW]
ldff1sb {z0.d}, p0/z, [x0,z31.d,sxtw #0]
ldff1sb z0.d, p0/z, [x0,z0.d]
ldff1sb {z0.d}, p0/z, [x0,z0.d]
LDFF1SB {Z0.D}, P0/Z, [X0,Z0.D]
ldff1sb {z0.d}, p0/z, [x0,z0.d,lsl #0]
ldff1sb z1.d, p0/z, [x0,z0.d]
ldff1sb {z1.d}, p0/z, [x0,z0.d]
LDFF1SB {Z1.D}, P0/Z, [X0,Z0.D]
ldff1sb {z1.d}, p0/z, [x0,z0.d,lsl #0]
ldff1sb z31.d, p0/z, [x0,z0.d]
ldff1sb {z31.d}, p0/z, [x0,z0.d]
LDFF1SB {Z31.D}, P0/Z, [X0,Z0.D]
ldff1sb {z31.d}, p0/z, [x0,z0.d,lsl #0]
ldff1sb {z0.d}, p2/z, [x0,z0.d]
LDFF1SB {Z0.D}, P2/Z, [X0,Z0.D]
ldff1sb {z0.d}, p2/z, [x0,z0.d,lsl #0]
ldff1sb {z0.d}, p7/z, [x0,z0.d]
LDFF1SB {Z0.D}, P7/Z, [X0,Z0.D]
ldff1sb {z0.d}, p7/z, [x0,z0.d,lsl #0]
ldff1sb {z0.d}, p0/z, [x3,z0.d]
LDFF1SB {Z0.D}, P0/Z, [X3,Z0.D]
ldff1sb {z0.d}, p0/z, [x3,z0.d,lsl #0]
ldff1sb {z0.d}, p0/z, [sp,z0.d]
LDFF1SB {Z0.D}, P0/Z, [SP,Z0.D]
ldff1sb {z0.d}, p0/z, [sp,z0.d,lsl #0]
ldff1sb {z0.d}, p0/z, [x0,z4.d]
LDFF1SB {Z0.D}, P0/Z, [X0,Z4.D]
ldff1sb {z0.d}, p0/z, [x0,z4.d,lsl #0]
ldff1sb {z0.d}, p0/z, [x0,z31.d]
LDFF1SB {Z0.D}, P0/Z, [X0,Z31.D]
ldff1sb {z0.d}, p0/z, [x0,z31.d,lsl #0]
ldff1sb z0.s, p0/z, [z0.s,#0]
ldff1sb {z0.s}, p0/z, [z0.s,#0]
LDFF1SB {Z0.S}, P0/Z, [Z0.S,#0]
ldff1sb {z0.s}, p0/z, [z0.s]
ldff1sb z1.s, p0/z, [z0.s,#0]
ldff1sb {z1.s}, p0/z, [z0.s,#0]
LDFF1SB {Z1.S}, P0/Z, [Z0.S,#0]
ldff1sb {z1.s}, p0/z, [z0.s]
ldff1sb z31.s, p0/z, [z0.s,#0]
ldff1sb {z31.s}, p0/z, [z0.s,#0]
LDFF1SB {Z31.S}, P0/Z, [Z0.S,#0]
ldff1sb {z31.s}, p0/z, [z0.s]
ldff1sb {z0.s}, p2/z, [z0.s,#0]
LDFF1SB {Z0.S}, P2/Z, [Z0.S,#0]
ldff1sb {z0.s}, p2/z, [z0.s]
ldff1sb {z0.s}, p7/z, [z0.s,#0]
LDFF1SB {Z0.S}, P7/Z, [Z0.S,#0]
ldff1sb {z0.s}, p7/z, [z0.s]
ldff1sb {z0.s}, p0/z, [z3.s,#0]
LDFF1SB {Z0.S}, P0/Z, [Z3.S,#0]
ldff1sb {z0.s}, p0/z, [z3.s]
ldff1sb {z0.s}, p0/z, [z31.s,#0]
LDFF1SB {Z0.S}, P0/Z, [Z31.S,#0]
ldff1sb {z0.s}, p0/z, [z31.s]
ldff1sb {z0.s}, p0/z, [z0.s,#15]
LDFF1SB {Z0.S}, P0/Z, [Z0.S,#15]
ldff1sb {z0.s}, p0/z, [z0.s,#16]
LDFF1SB {Z0.S}, P0/Z, [Z0.S,#16]
ldff1sb {z0.s}, p0/z, [z0.s,#17]
LDFF1SB {Z0.S}, P0/Z, [Z0.S,#17]
ldff1sb {z0.s}, p0/z, [z0.s,#31]
LDFF1SB {Z0.S}, P0/Z, [Z0.S,#31]
ldff1sb z0.d, p0/z, [z0.d,#0]
ldff1sb {z0.d}, p0/z, [z0.d,#0]
LDFF1SB {Z0.D}, P0/Z, [Z0.D,#0]
ldff1sb {z0.d}, p0/z, [z0.d]
ldff1sb z1.d, p0/z, [z0.d,#0]
ldff1sb {z1.d}, p0/z, [z0.d,#0]
LDFF1SB {Z1.D}, P0/Z, [Z0.D,#0]
ldff1sb {z1.d}, p0/z, [z0.d]
ldff1sb z31.d, p0/z, [z0.d,#0]
ldff1sb {z31.d}, p0/z, [z0.d,#0]
LDFF1SB {Z31.D}, P0/Z, [Z0.D,#0]
ldff1sb {z31.d}, p0/z, [z0.d]
ldff1sb {z0.d}, p2/z, [z0.d,#0]
LDFF1SB {Z0.D}, P2/Z, [Z0.D,#0]
ldff1sb {z0.d}, p2/z, [z0.d]
ldff1sb {z0.d}, p7/z, [z0.d,#0]
LDFF1SB {Z0.D}, P7/Z, [Z0.D,#0]
ldff1sb {z0.d}, p7/z, [z0.d]
ldff1sb {z0.d}, p0/z, [z3.d,#0]
LDFF1SB {Z0.D}, P0/Z, [Z3.D,#0]
ldff1sb {z0.d}, p0/z, [z3.d]
ldff1sb {z0.d}, p0/z, [z31.d,#0]
LDFF1SB {Z0.D}, P0/Z, [Z31.D,#0]
ldff1sb {z0.d}, p0/z, [z31.d]
ldff1sb {z0.d}, p0/z, [z0.d,#15]
LDFF1SB {Z0.D}, P0/Z, [Z0.D,#15]
ldff1sb {z0.d}, p0/z, [z0.d,#16]
LDFF1SB {Z0.D}, P0/Z, [Z0.D,#16]
ldff1sb {z0.d}, p0/z, [z0.d,#17]
LDFF1SB {Z0.D}, P0/Z, [Z0.D,#17]
ldff1sb {z0.d}, p0/z, [z0.d,#31]
LDFF1SB {Z0.D}, P0/Z, [Z0.D,#31]
ldff1sh z0.s, p0/z, [x0,z0.s,uxtw]
ldff1sh {z0.s}, p0/z, [x0,z0.s,uxtw]
LDFF1SH {Z0.S}, P0/Z, [X0,Z0.S,UXTW]
ldff1sh {z0.s}, p0/z, [x0,z0.s,uxtw #0]
ldff1sh z1.s, p0/z, [x0,z0.s,uxtw]
ldff1sh {z1.s}, p0/z, [x0,z0.s,uxtw]
LDFF1SH {Z1.S}, P0/Z, [X0,Z0.S,UXTW]
ldff1sh {z1.s}, p0/z, [x0,z0.s,uxtw #0]
ldff1sh z31.s, p0/z, [x0,z0.s,uxtw]
ldff1sh {z31.s}, p0/z, [x0,z0.s,uxtw]
LDFF1SH {Z31.S}, P0/Z, [X0,Z0.S,UXTW]
ldff1sh {z31.s}, p0/z, [x0,z0.s,uxtw #0]
ldff1sh {z0.s}, p2/z, [x0,z0.s,uxtw]
LDFF1SH {Z0.S}, P2/Z, [X0,Z0.S,UXTW]
ldff1sh {z0.s}, p2/z, [x0,z0.s,uxtw #0]
ldff1sh {z0.s}, p7/z, [x0,z0.s,uxtw]
LDFF1SH {Z0.S}, P7/Z, [X0,Z0.S,UXTW]
ldff1sh {z0.s}, p7/z, [x0,z0.s,uxtw #0]
ldff1sh {z0.s}, p0/z, [x3,z0.s,uxtw]
LDFF1SH {Z0.S}, P0/Z, [X3,Z0.S,UXTW]
ldff1sh {z0.s}, p0/z, [x3,z0.s,uxtw #0]
ldff1sh {z0.s}, p0/z, [sp,z0.s,uxtw]
LDFF1SH {Z0.S}, P0/Z, [SP,Z0.S,UXTW]
ldff1sh {z0.s}, p0/z, [sp,z0.s,uxtw #0]
ldff1sh {z0.s}, p0/z, [x0,z4.s,uxtw]
LDFF1SH {Z0.S}, P0/Z, [X0,Z4.S,UXTW]
ldff1sh {z0.s}, p0/z, [x0,z4.s,uxtw #0]
ldff1sh {z0.s}, p0/z, [x0,z31.s,uxtw]
LDFF1SH {Z0.S}, P0/Z, [X0,Z31.S,UXTW]
ldff1sh {z0.s}, p0/z, [x0,z31.s,uxtw #0]
ldff1sh z0.s, p0/z, [x0,z0.s,sxtw]
ldff1sh {z0.s}, p0/z, [x0,z0.s,sxtw]
LDFF1SH {Z0.S}, P0/Z, [X0,Z0.S,SXTW]
ldff1sh {z0.s}, p0/z, [x0,z0.s,sxtw #0]
ldff1sh z1.s, p0/z, [x0,z0.s,sxtw]
ldff1sh {z1.s}, p0/z, [x0,z0.s,sxtw]
LDFF1SH {Z1.S}, P0/Z, [X0,Z0.S,SXTW]
ldff1sh {z1.s}, p0/z, [x0,z0.s,sxtw #0]
ldff1sh z31.s, p0/z, [x0,z0.s,sxtw]
ldff1sh {z31.s}, p0/z, [x0,z0.s,sxtw]
LDFF1SH {Z31.S}, P0/Z, [X0,Z0.S,SXTW]
ldff1sh {z31.s}, p0/z, [x0,z0.s,sxtw #0]
ldff1sh {z0.s}, p2/z, [x0,z0.s,sxtw]
LDFF1SH {Z0.S}, P2/Z, [X0,Z0.S,SXTW]
ldff1sh {z0.s}, p2/z, [x0,z0.s,sxtw #0]
ldff1sh {z0.s}, p7/z, [x0,z0.s,sxtw]
LDFF1SH {Z0.S}, P7/Z, [X0,Z0.S,SXTW]
ldff1sh {z0.s}, p7/z, [x0,z0.s,sxtw #0]
ldff1sh {z0.s}, p0/z, [x3,z0.s,sxtw]
LDFF1SH {Z0.S}, P0/Z, [X3,Z0.S,SXTW]
ldff1sh {z0.s}, p0/z, [x3,z0.s,sxtw #0]
ldff1sh {z0.s}, p0/z, [sp,z0.s,sxtw]
LDFF1SH {Z0.S}, P0/Z, [SP,Z0.S,SXTW]
ldff1sh {z0.s}, p0/z, [sp,z0.s,sxtw #0]
ldff1sh {z0.s}, p0/z, [x0,z4.s,sxtw]
LDFF1SH {Z0.S}, P0/Z, [X0,Z4.S,SXTW]
ldff1sh {z0.s}, p0/z, [x0,z4.s,sxtw #0]
ldff1sh {z0.s}, p0/z, [x0,z31.s,sxtw]
LDFF1SH {Z0.S}, P0/Z, [X0,Z31.S,SXTW]
ldff1sh {z0.s}, p0/z, [x0,z31.s,sxtw #0]
ldff1sh z0.s, p0/z, [x0,z0.s,uxtw #1]
ldff1sh {z0.s}, p0/z, [x0,z0.s,uxtw #1]
LDFF1SH {Z0.S}, P0/Z, [X0,Z0.S,UXTW #1]
ldff1sh z1.s, p0/z, [x0,z0.s,uxtw #1]
ldff1sh {z1.s}, p0/z, [x0,z0.s,uxtw #1]
LDFF1SH {Z1.S}, P0/Z, [X0,Z0.S,UXTW #1]
ldff1sh z31.s, p0/z, [x0,z0.s,uxtw #1]
ldff1sh {z31.s}, p0/z, [x0,z0.s,uxtw #1]
LDFF1SH {Z31.S}, P0/Z, [X0,Z0.S,UXTW #1]
ldff1sh {z0.s}, p2/z, [x0,z0.s,uxtw #1]
LDFF1SH {Z0.S}, P2/Z, [X0,Z0.S,UXTW #1]
ldff1sh {z0.s}, p7/z, [x0,z0.s,uxtw #1]
LDFF1SH {Z0.S}, P7/Z, [X0,Z0.S,UXTW #1]
ldff1sh {z0.s}, p0/z, [x3,z0.s,uxtw #1]
LDFF1SH {Z0.S}, P0/Z, [X3,Z0.S,UXTW #1]
ldff1sh {z0.s}, p0/z, [sp,z0.s,uxtw #1]
LDFF1SH {Z0.S}, P0/Z, [SP,Z0.S,UXTW #1]
ldff1sh {z0.s}, p0/z, [x0,z4.s,uxtw #1]
LDFF1SH {Z0.S}, P0/Z, [X0,Z4.S,UXTW #1]
ldff1sh {z0.s}, p0/z, [x0,z31.s,uxtw #1]
LDFF1SH {Z0.S}, P0/Z, [X0,Z31.S,UXTW #1]
ldff1sh z0.s, p0/z, [x0,z0.s,sxtw #1]
ldff1sh {z0.s}, p0/z, [x0,z0.s,sxtw #1]
LDFF1SH {Z0.S}, P0/Z, [X0,Z0.S,SXTW #1]
ldff1sh z1.s, p0/z, [x0,z0.s,sxtw #1]
ldff1sh {z1.s}, p0/z, [x0,z0.s,sxtw #1]
LDFF1SH {Z1.S}, P0/Z, [X0,Z0.S,SXTW #1]
ldff1sh z31.s, p0/z, [x0,z0.s,sxtw #1]
ldff1sh {z31.s}, p0/z, [x0,z0.s,sxtw #1]
LDFF1SH {Z31.S}, P0/Z, [X0,Z0.S,SXTW #1]
ldff1sh {z0.s}, p2/z, [x0,z0.s,sxtw #1]
LDFF1SH {Z0.S}, P2/Z, [X0,Z0.S,SXTW #1]
ldff1sh {z0.s}, p7/z, [x0,z0.s,sxtw #1]
LDFF1SH {Z0.S}, P7/Z, [X0,Z0.S,SXTW #1]
ldff1sh {z0.s}, p0/z, [x3,z0.s,sxtw #1]
LDFF1SH {Z0.S}, P0/Z, [X3,Z0.S,SXTW #1]
ldff1sh {z0.s}, p0/z, [sp,z0.s,sxtw #1]
LDFF1SH {Z0.S}, P0/Z, [SP,Z0.S,SXTW #1]
ldff1sh {z0.s}, p0/z, [x0,z4.s,sxtw #1]
LDFF1SH {Z0.S}, P0/Z, [X0,Z4.S,SXTW #1]
ldff1sh {z0.s}, p0/z, [x0,z31.s,sxtw #1]
LDFF1SH {Z0.S}, P0/Z, [X0,Z31.S,SXTW #1]
ldff1sh z0.d, p0/z, [x0,x0,lsl #1]
ldff1sh {z0.d}, p0/z, [x0,x0,lsl #1]
LDFF1SH {Z0.D}, P0/Z, [X0,X0,LSL #1]
ldff1sh z1.d, p0/z, [x0,x0,lsl #1]
ldff1sh {z1.d}, p0/z, [x0,x0,lsl #1]
LDFF1SH {Z1.D}, P0/Z, [X0,X0,LSL #1]
ldff1sh z31.d, p0/z, [x0,x0,lsl #1]
ldff1sh {z31.d}, p0/z, [x0,x0,lsl #1]
LDFF1SH {Z31.D}, P0/Z, [X0,X0,LSL #1]
ldff1sh {z0.d}, p2/z, [x0,x0,lsl #1]
LDFF1SH {Z0.D}, P2/Z, [X0,X0,LSL #1]
ldff1sh {z0.d}, p7/z, [x0,x0,lsl #1]
LDFF1SH {Z0.D}, P7/Z, [X0,X0,LSL #1]
ldff1sh {z0.d}, p0/z, [x3,x0,lsl #1]
LDFF1SH {Z0.D}, P0/Z, [X3,X0,LSL #1]
ldff1sh {z0.d}, p0/z, [sp,x0,lsl #1]
LDFF1SH {Z0.D}, P0/Z, [SP,X0,LSL #1]
ldff1sh {z0.d}, p0/z, [x0,x4,lsl #1]
LDFF1SH {Z0.D}, P0/Z, [X0,X4,LSL #1]
ldff1sh {z0.d}, p0/z, [x0,xzr,lsl #1]
LDFF1SH {Z0.D}, P0/Z, [X0,XZR,LSL #1]
ldff1sh z0.s, p0/z, [x0,x0,lsl #1]
ldff1sh {z0.s}, p0/z, [x0,x0,lsl #1]
LDFF1SH {Z0.S}, P0/Z, [X0,X0,LSL #1]
ldff1sh z1.s, p0/z, [x0,x0,lsl #1]
ldff1sh {z1.s}, p0/z, [x0,x0,lsl #1]
LDFF1SH {Z1.S}, P0/Z, [X0,X0,LSL #1]
ldff1sh z31.s, p0/z, [x0,x0,lsl #1]
ldff1sh {z31.s}, p0/z, [x0,x0,lsl #1]
LDFF1SH {Z31.S}, P0/Z, [X0,X0,LSL #1]
ldff1sh {z0.s}, p2/z, [x0,x0,lsl #1]
LDFF1SH {Z0.S}, P2/Z, [X0,X0,LSL #1]
ldff1sh {z0.s}, p7/z, [x0,x0,lsl #1]
LDFF1SH {Z0.S}, P7/Z, [X0,X0,LSL #1]
ldff1sh {z0.s}, p0/z, [x3,x0,lsl #1]
LDFF1SH {Z0.S}, P0/Z, [X3,X0,LSL #1]
ldff1sh {z0.s}, p0/z, [sp,x0,lsl #1]
LDFF1SH {Z0.S}, P0/Z, [SP,X0,LSL #1]
ldff1sh {z0.s}, p0/z, [x0,x4,lsl #1]
LDFF1SH {Z0.S}, P0/Z, [X0,X4,LSL #1]
ldff1sh {z0.s}, p0/z, [x0,xzr,lsl #1]
LDFF1SH {Z0.S}, P0/Z, [X0,XZR,LSL #1]
ldff1sh z0.d, p0/z, [x0,z0.d,uxtw]
ldff1sh {z0.d}, p0/z, [x0,z0.d,uxtw]
LDFF1SH {Z0.D}, P0/Z, [X0,Z0.D,UXTW]
ldff1sh {z0.d}, p0/z, [x0,z0.d,uxtw #0]
ldff1sh z1.d, p0/z, [x0,z0.d,uxtw]
ldff1sh {z1.d}, p0/z, [x0,z0.d,uxtw]
LDFF1SH {Z1.D}, P0/Z, [X0,Z0.D,UXTW]
ldff1sh {z1.d}, p0/z, [x0,z0.d,uxtw #0]
ldff1sh z31.d, p0/z, [x0,z0.d,uxtw]
ldff1sh {z31.d}, p0/z, [x0,z0.d,uxtw]
LDFF1SH {Z31.D}, P0/Z, [X0,Z0.D,UXTW]
ldff1sh {z31.d}, p0/z, [x0,z0.d,uxtw #0]
ldff1sh {z0.d}, p2/z, [x0,z0.d,uxtw]
LDFF1SH {Z0.D}, P2/Z, [X0,Z0.D,UXTW]
ldff1sh {z0.d}, p2/z, [x0,z0.d,uxtw #0]
ldff1sh {z0.d}, p7/z, [x0,z0.d,uxtw]
LDFF1SH {Z0.D}, P7/Z, [X0,Z0.D,UXTW]
ldff1sh {z0.d}, p7/z, [x0,z0.d,uxtw #0]
ldff1sh {z0.d}, p0/z, [x3,z0.d,uxtw]
LDFF1SH {Z0.D}, P0/Z, [X3,Z0.D,UXTW]
ldff1sh {z0.d}, p0/z, [x3,z0.d,uxtw #0]
ldff1sh {z0.d}, p0/z, [sp,z0.d,uxtw]
LDFF1SH {Z0.D}, P0/Z, [SP,Z0.D,UXTW]
ldff1sh {z0.d}, p0/z, [sp,z0.d,uxtw #0]
ldff1sh {z0.d}, p0/z, [x0,z4.d,uxtw]
LDFF1SH {Z0.D}, P0/Z, [X0,Z4.D,UXTW]
ldff1sh {z0.d}, p0/z, [x0,z4.d,uxtw #0]
ldff1sh {z0.d}, p0/z, [x0,z31.d,uxtw]
LDFF1SH {Z0.D}, P0/Z, [X0,Z31.D,UXTW]
ldff1sh {z0.d}, p0/z, [x0,z31.d,uxtw #0]
ldff1sh z0.d, p0/z, [x0,z0.d,sxtw]
ldff1sh {z0.d}, p0/z, [x0,z0.d,sxtw]
LDFF1SH {Z0.D}, P0/Z, [X0,Z0.D,SXTW]
ldff1sh {z0.d}, p0/z, [x0,z0.d,sxtw #0]
ldff1sh z1.d, p0/z, [x0,z0.d,sxtw]
ldff1sh {z1.d}, p0/z, [x0,z0.d,sxtw]
LDFF1SH {Z1.D}, P0/Z, [X0,Z0.D,SXTW]
ldff1sh {z1.d}, p0/z, [x0,z0.d,sxtw #0]
ldff1sh z31.d, p0/z, [x0,z0.d,sxtw]
ldff1sh {z31.d}, p0/z, [x0,z0.d,sxtw]
LDFF1SH {Z31.D}, P0/Z, [X0,Z0.D,SXTW]
ldff1sh {z31.d}, p0/z, [x0,z0.d,sxtw #0]
ldff1sh {z0.d}, p2/z, [x0,z0.d,sxtw]
LDFF1SH {Z0.D}, P2/Z, [X0,Z0.D,SXTW]
ldff1sh {z0.d}, p2/z, [x0,z0.d,sxtw #0]
ldff1sh {z0.d}, p7/z, [x0,z0.d,sxtw]
LDFF1SH {Z0.D}, P7/Z, [X0,Z0.D,SXTW]
ldff1sh {z0.d}, p7/z, [x0,z0.d,sxtw #0]
ldff1sh {z0.d}, p0/z, [x3,z0.d,sxtw]
LDFF1SH {Z0.D}, P0/Z, [X3,Z0.D,SXTW]
ldff1sh {z0.d}, p0/z, [x3,z0.d,sxtw #0]
ldff1sh {z0.d}, p0/z, [sp,z0.d,sxtw]
LDFF1SH {Z0.D}, P0/Z, [SP,Z0.D,SXTW]
ldff1sh {z0.d}, p0/z, [sp,z0.d,sxtw #0]
ldff1sh {z0.d}, p0/z, [x0,z4.d,sxtw]
LDFF1SH {Z0.D}, P0/Z, [X0,Z4.D,SXTW]
ldff1sh {z0.d}, p0/z, [x0,z4.d,sxtw #0]
ldff1sh {z0.d}, p0/z, [x0,z31.d,sxtw]
LDFF1SH {Z0.D}, P0/Z, [X0,Z31.D,SXTW]
ldff1sh {z0.d}, p0/z, [x0,z31.d,sxtw #0]
ldff1sh z0.d, p0/z, [x0,z0.d,uxtw #1]
ldff1sh {z0.d}, p0/z, [x0,z0.d,uxtw #1]
LDFF1SH {Z0.D}, P0/Z, [X0,Z0.D,UXTW #1]
ldff1sh z1.d, p0/z, [x0,z0.d,uxtw #1]
ldff1sh {z1.d}, p0/z, [x0,z0.d,uxtw #1]
LDFF1SH {Z1.D}, P0/Z, [X0,Z0.D,UXTW #1]
ldff1sh z31.d, p0/z, [x0,z0.d,uxtw #1]
ldff1sh {z31.d}, p0/z, [x0,z0.d,uxtw #1]
LDFF1SH {Z31.D}, P0/Z, [X0,Z0.D,UXTW #1]
ldff1sh {z0.d}, p2/z, [x0,z0.d,uxtw #1]
LDFF1SH {Z0.D}, P2/Z, [X0,Z0.D,UXTW #1]
ldff1sh {z0.d}, p7/z, [x0,z0.d,uxtw #1]
LDFF1SH {Z0.D}, P7/Z, [X0,Z0.D,UXTW #1]
ldff1sh {z0.d}, p0/z, [x3,z0.d,uxtw #1]
LDFF1SH {Z0.D}, P0/Z, [X3,Z0.D,UXTW #1]
ldff1sh {z0.d}, p0/z, [sp,z0.d,uxtw #1]
LDFF1SH {Z0.D}, P0/Z, [SP,Z0.D,UXTW #1]
ldff1sh {z0.d}, p0/z, [x0,z4.d,uxtw #1]
LDFF1SH {Z0.D}, P0/Z, [X0,Z4.D,UXTW #1]
ldff1sh {z0.d}, p0/z, [x0,z31.d,uxtw #1]
LDFF1SH {Z0.D}, P0/Z, [X0,Z31.D,UXTW #1]
ldff1sh z0.d, p0/z, [x0,z0.d,sxtw #1]
ldff1sh {z0.d}, p0/z, [x0,z0.d,sxtw #1]
LDFF1SH {Z0.D}, P0/Z, [X0,Z0.D,SXTW #1]
ldff1sh z1.d, p0/z, [x0,z0.d,sxtw #1]
ldff1sh {z1.d}, p0/z, [x0,z0.d,sxtw #1]
LDFF1SH {Z1.D}, P0/Z, [X0,Z0.D,SXTW #1]
ldff1sh z31.d, p0/z, [x0,z0.d,sxtw #1]
ldff1sh {z31.d}, p0/z, [x0,z0.d,sxtw #1]
LDFF1SH {Z31.D}, P0/Z, [X0,Z0.D,SXTW #1]
ldff1sh {z0.d}, p2/z, [x0,z0.d,sxtw #1]
LDFF1SH {Z0.D}, P2/Z, [X0,Z0.D,SXTW #1]
ldff1sh {z0.d}, p7/z, [x0,z0.d,sxtw #1]
LDFF1SH {Z0.D}, P7/Z, [X0,Z0.D,SXTW #1]
ldff1sh {z0.d}, p0/z, [x3,z0.d,sxtw #1]
LDFF1SH {Z0.D}, P0/Z, [X3,Z0.D,SXTW #1]
ldff1sh {z0.d}, p0/z, [sp,z0.d,sxtw #1]
LDFF1SH {Z0.D}, P0/Z, [SP,Z0.D,SXTW #1]
ldff1sh {z0.d}, p0/z, [x0,z4.d,sxtw #1]
LDFF1SH {Z0.D}, P0/Z, [X0,Z4.D,SXTW #1]
ldff1sh {z0.d}, p0/z, [x0,z31.d,sxtw #1]
LDFF1SH {Z0.D}, P0/Z, [X0,Z31.D,SXTW #1]
ldff1sh z0.d, p0/z, [x0,z0.d]
ldff1sh {z0.d}, p0/z, [x0,z0.d]
LDFF1SH {Z0.D}, P0/Z, [X0,Z0.D]
ldff1sh {z0.d}, p0/z, [x0,z0.d,lsl #0]
ldff1sh z1.d, p0/z, [x0,z0.d]
ldff1sh {z1.d}, p0/z, [x0,z0.d]
LDFF1SH {Z1.D}, P0/Z, [X0,Z0.D]
ldff1sh {z1.d}, p0/z, [x0,z0.d,lsl #0]
ldff1sh z31.d, p0/z, [x0,z0.d]
ldff1sh {z31.d}, p0/z, [x0,z0.d]
LDFF1SH {Z31.D}, P0/Z, [X0,Z0.D]
ldff1sh {z31.d}, p0/z, [x0,z0.d,lsl #0]
ldff1sh {z0.d}, p2/z, [x0,z0.d]
LDFF1SH {Z0.D}, P2/Z, [X0,Z0.D]
ldff1sh {z0.d}, p2/z, [x0,z0.d,lsl #0]
ldff1sh {z0.d}, p7/z, [x0,z0.d]
LDFF1SH {Z0.D}, P7/Z, [X0,Z0.D]
ldff1sh {z0.d}, p7/z, [x0,z0.d,lsl #0]
ldff1sh {z0.d}, p0/z, [x3,z0.d]
LDFF1SH {Z0.D}, P0/Z, [X3,Z0.D]
ldff1sh {z0.d}, p0/z, [x3,z0.d,lsl #0]
ldff1sh {z0.d}, p0/z, [sp,z0.d]
LDFF1SH {Z0.D}, P0/Z, [SP,Z0.D]
ldff1sh {z0.d}, p0/z, [sp,z0.d,lsl #0]
ldff1sh {z0.d}, p0/z, [x0,z4.d]
LDFF1SH {Z0.D}, P0/Z, [X0,Z4.D]
ldff1sh {z0.d}, p0/z, [x0,z4.d,lsl #0]
ldff1sh {z0.d}, p0/z, [x0,z31.d]
LDFF1SH {Z0.D}, P0/Z, [X0,Z31.D]
ldff1sh {z0.d}, p0/z, [x0,z31.d,lsl #0]
ldff1sh z0.d, p0/z, [x0,z0.d,lsl #1]
ldff1sh {z0.d}, p0/z, [x0,z0.d,lsl #1]
LDFF1SH {Z0.D}, P0/Z, [X0,Z0.D,LSL #1]
ldff1sh z1.d, p0/z, [x0,z0.d,lsl #1]
ldff1sh {z1.d}, p0/z, [x0,z0.d,lsl #1]
LDFF1SH {Z1.D}, P0/Z, [X0,Z0.D,LSL #1]
ldff1sh z31.d, p0/z, [x0,z0.d,lsl #1]
ldff1sh {z31.d}, p0/z, [x0,z0.d,lsl #1]
LDFF1SH {Z31.D}, P0/Z, [X0,Z0.D,LSL #1]
ldff1sh {z0.d}, p2/z, [x0,z0.d,lsl #1]
LDFF1SH {Z0.D}, P2/Z, [X0,Z0.D,LSL #1]
ldff1sh {z0.d}, p7/z, [x0,z0.d,lsl #1]
LDFF1SH {Z0.D}, P7/Z, [X0,Z0.D,LSL #1]
ldff1sh {z0.d}, p0/z, [x3,z0.d,lsl #1]
LDFF1SH {Z0.D}, P0/Z, [X3,Z0.D,LSL #1]
ldff1sh {z0.d}, p0/z, [sp,z0.d,lsl #1]
LDFF1SH {Z0.D}, P0/Z, [SP,Z0.D,LSL #1]
ldff1sh {z0.d}, p0/z, [x0,z4.d,lsl #1]
LDFF1SH {Z0.D}, P0/Z, [X0,Z4.D,LSL #1]
ldff1sh {z0.d}, p0/z, [x0,z31.d,lsl #1]
LDFF1SH {Z0.D}, P0/Z, [X0,Z31.D,LSL #1]
ldff1sh z0.s, p0/z, [z0.s,#0]
ldff1sh {z0.s}, p0/z, [z0.s,#0]
LDFF1SH {Z0.S}, P0/Z, [Z0.S,#0]
ldff1sh {z0.s}, p0/z, [z0.s]
ldff1sh z1.s, p0/z, [z0.s,#0]
ldff1sh {z1.s}, p0/z, [z0.s,#0]
LDFF1SH {Z1.S}, P0/Z, [Z0.S,#0]
ldff1sh {z1.s}, p0/z, [z0.s]
ldff1sh z31.s, p0/z, [z0.s,#0]
ldff1sh {z31.s}, p0/z, [z0.s,#0]
LDFF1SH {Z31.S}, P0/Z, [Z0.S,#0]
ldff1sh {z31.s}, p0/z, [z0.s]
ldff1sh {z0.s}, p2/z, [z0.s,#0]
LDFF1SH {Z0.S}, P2/Z, [Z0.S,#0]
ldff1sh {z0.s}, p2/z, [z0.s]
ldff1sh {z0.s}, p7/z, [z0.s,#0]
LDFF1SH {Z0.S}, P7/Z, [Z0.S,#0]
ldff1sh {z0.s}, p7/z, [z0.s]
ldff1sh {z0.s}, p0/z, [z3.s,#0]
LDFF1SH {Z0.S}, P0/Z, [Z3.S,#0]
ldff1sh {z0.s}, p0/z, [z3.s]
ldff1sh {z0.s}, p0/z, [z31.s,#0]
LDFF1SH {Z0.S}, P0/Z, [Z31.S,#0]
ldff1sh {z0.s}, p0/z, [z31.s]
ldff1sh {z0.s}, p0/z, [z0.s,#30]
LDFF1SH {Z0.S}, P0/Z, [Z0.S,#30]
ldff1sh {z0.s}, p0/z, [z0.s,#32]
LDFF1SH {Z0.S}, P0/Z, [Z0.S,#32]
ldff1sh {z0.s}, p0/z, [z0.s,#34]
LDFF1SH {Z0.S}, P0/Z, [Z0.S,#34]
ldff1sh {z0.s}, p0/z, [z0.s,#62]
LDFF1SH {Z0.S}, P0/Z, [Z0.S,#62]
ldff1sh z0.d, p0/z, [z0.d,#0]
ldff1sh {z0.d}, p0/z, [z0.d,#0]
LDFF1SH {Z0.D}, P0/Z, [Z0.D,#0]
ldff1sh {z0.d}, p0/z, [z0.d]
ldff1sh z1.d, p0/z, [z0.d,#0]
ldff1sh {z1.d}, p0/z, [z0.d,#0]
LDFF1SH {Z1.D}, P0/Z, [Z0.D,#0]
ldff1sh {z1.d}, p0/z, [z0.d]
ldff1sh z31.d, p0/z, [z0.d,#0]
ldff1sh {z31.d}, p0/z, [z0.d,#0]
LDFF1SH {Z31.D}, P0/Z, [Z0.D,#0]
ldff1sh {z31.d}, p0/z, [z0.d]
ldff1sh {z0.d}, p2/z, [z0.d,#0]
LDFF1SH {Z0.D}, P2/Z, [Z0.D,#0]
ldff1sh {z0.d}, p2/z, [z0.d]
ldff1sh {z0.d}, p7/z, [z0.d,#0]
LDFF1SH {Z0.D}, P7/Z, [Z0.D,#0]
ldff1sh {z0.d}, p7/z, [z0.d]
ldff1sh {z0.d}, p0/z, [z3.d,#0]
LDFF1SH {Z0.D}, P0/Z, [Z3.D,#0]
ldff1sh {z0.d}, p0/z, [z3.d]
ldff1sh {z0.d}, p0/z, [z31.d,#0]
LDFF1SH {Z0.D}, P0/Z, [Z31.D,#0]
ldff1sh {z0.d}, p0/z, [z31.d]
ldff1sh {z0.d}, p0/z, [z0.d,#30]
LDFF1SH {Z0.D}, P0/Z, [Z0.D,#30]
ldff1sh {z0.d}, p0/z, [z0.d,#32]
LDFF1SH {Z0.D}, P0/Z, [Z0.D,#32]
ldff1sh {z0.d}, p0/z, [z0.d,#34]
LDFF1SH {Z0.D}, P0/Z, [Z0.D,#34]
ldff1sh {z0.d}, p0/z, [z0.d,#62]
LDFF1SH {Z0.D}, P0/Z, [Z0.D,#62]
ldff1sw z0.d, p0/z, [x0,x0,lsl #2]
ldff1sw {z0.d}, p0/z, [x0,x0,lsl #2]
LDFF1SW {Z0.D}, P0/Z, [X0,X0,LSL #2]
ldff1sw z1.d, p0/z, [x0,x0,lsl #2]
ldff1sw {z1.d}, p0/z, [x0,x0,lsl #2]
LDFF1SW {Z1.D}, P0/Z, [X0,X0,LSL #2]
ldff1sw z31.d, p0/z, [x0,x0,lsl #2]
ldff1sw {z31.d}, p0/z, [x0,x0,lsl #2]
LDFF1SW {Z31.D}, P0/Z, [X0,X0,LSL #2]
ldff1sw {z0.d}, p2/z, [x0,x0,lsl #2]
LDFF1SW {Z0.D}, P2/Z, [X0,X0,LSL #2]
ldff1sw {z0.d}, p7/z, [x0,x0,lsl #2]
LDFF1SW {Z0.D}, P7/Z, [X0,X0,LSL #2]
ldff1sw {z0.d}, p0/z, [x3,x0,lsl #2]
LDFF1SW {Z0.D}, P0/Z, [X3,X0,LSL #2]
ldff1sw {z0.d}, p0/z, [sp,x0,lsl #2]
LDFF1SW {Z0.D}, P0/Z, [SP,X0,LSL #2]
ldff1sw {z0.d}, p0/z, [x0,x4,lsl #2]
LDFF1SW {Z0.D}, P0/Z, [X0,X4,LSL #2]
ldff1sw {z0.d}, p0/z, [x0,xzr,lsl #2]
LDFF1SW {Z0.D}, P0/Z, [X0,XZR,LSL #2]
ldff1sw z0.d, p0/z, [x0,z0.d,uxtw]
ldff1sw {z0.d}, p0/z, [x0,z0.d,uxtw]
LDFF1SW {Z0.D}, P0/Z, [X0,Z0.D,UXTW]
ldff1sw {z0.d}, p0/z, [x0,z0.d,uxtw #0]
ldff1sw z1.d, p0/z, [x0,z0.d,uxtw]
ldff1sw {z1.d}, p0/z, [x0,z0.d,uxtw]
LDFF1SW {Z1.D}, P0/Z, [X0,Z0.D,UXTW]
ldff1sw {z1.d}, p0/z, [x0,z0.d,uxtw #0]
ldff1sw z31.d, p0/z, [x0,z0.d,uxtw]
ldff1sw {z31.d}, p0/z, [x0,z0.d,uxtw]
LDFF1SW {Z31.D}, P0/Z, [X0,Z0.D,UXTW]
ldff1sw {z31.d}, p0/z, [x0,z0.d,uxtw #0]
ldff1sw {z0.d}, p2/z, [x0,z0.d,uxtw]
LDFF1SW {Z0.D}, P2/Z, [X0,Z0.D,UXTW]
ldff1sw {z0.d}, p2/z, [x0,z0.d,uxtw #0]
ldff1sw {z0.d}, p7/z, [x0,z0.d,uxtw]
LDFF1SW {Z0.D}, P7/Z, [X0,Z0.D,UXTW]
ldff1sw {z0.d}, p7/z, [x0,z0.d,uxtw #0]
ldff1sw {z0.d}, p0/z, [x3,z0.d,uxtw]
LDFF1SW {Z0.D}, P0/Z, [X3,Z0.D,UXTW]
ldff1sw {z0.d}, p0/z, [x3,z0.d,uxtw #0]
ldff1sw {z0.d}, p0/z, [sp,z0.d,uxtw]
LDFF1SW {Z0.D}, P0/Z, [SP,Z0.D,UXTW]
ldff1sw {z0.d}, p0/z, [sp,z0.d,uxtw #0]
ldff1sw {z0.d}, p0/z, [x0,z4.d,uxtw]
LDFF1SW {Z0.D}, P0/Z, [X0,Z4.D,UXTW]
ldff1sw {z0.d}, p0/z, [x0,z4.d,uxtw #0]
ldff1sw {z0.d}, p0/z, [x0,z31.d,uxtw]
LDFF1SW {Z0.D}, P0/Z, [X0,Z31.D,UXTW]
ldff1sw {z0.d}, p0/z, [x0,z31.d,uxtw #0]
ldff1sw z0.d, p0/z, [x0,z0.d,sxtw]
ldff1sw {z0.d}, p0/z, [x0,z0.d,sxtw]
LDFF1SW {Z0.D}, P0/Z, [X0,Z0.D,SXTW]
ldff1sw {z0.d}, p0/z, [x0,z0.d,sxtw #0]
ldff1sw z1.d, p0/z, [x0,z0.d,sxtw]
ldff1sw {z1.d}, p0/z, [x0,z0.d,sxtw]
LDFF1SW {Z1.D}, P0/Z, [X0,Z0.D,SXTW]
ldff1sw {z1.d}, p0/z, [x0,z0.d,sxtw #0]
ldff1sw z31.d, p0/z, [x0,z0.d,sxtw]
ldff1sw {z31.d}, p0/z, [x0,z0.d,sxtw]
LDFF1SW {Z31.D}, P0/Z, [X0,Z0.D,SXTW]
ldff1sw {z31.d}, p0/z, [x0,z0.d,sxtw #0]
ldff1sw {z0.d}, p2/z, [x0,z0.d,sxtw]
LDFF1SW {Z0.D}, P2/Z, [X0,Z0.D,SXTW]
ldff1sw {z0.d}, p2/z, [x0,z0.d,sxtw #0]
ldff1sw {z0.d}, p7/z, [x0,z0.d,sxtw]
LDFF1SW {Z0.D}, P7/Z, [X0,Z0.D,SXTW]
ldff1sw {z0.d}, p7/z, [x0,z0.d,sxtw #0]
ldff1sw {z0.d}, p0/z, [x3,z0.d,sxtw]
LDFF1SW {Z0.D}, P0/Z, [X3,Z0.D,SXTW]
ldff1sw {z0.d}, p0/z, [x3,z0.d,sxtw #0]
ldff1sw {z0.d}, p0/z, [sp,z0.d,sxtw]
LDFF1SW {Z0.D}, P0/Z, [SP,Z0.D,SXTW]
ldff1sw {z0.d}, p0/z, [sp,z0.d,sxtw #0]
ldff1sw {z0.d}, p0/z, [x0,z4.d,sxtw]
LDFF1SW {Z0.D}, P0/Z, [X0,Z4.D,SXTW]
ldff1sw {z0.d}, p0/z, [x0,z4.d,sxtw #0]
ldff1sw {z0.d}, p0/z, [x0,z31.d,sxtw]
LDFF1SW {Z0.D}, P0/Z, [X0,Z31.D,SXTW]
ldff1sw {z0.d}, p0/z, [x0,z31.d,sxtw #0]
ldff1sw z0.d, p0/z, [x0,z0.d,uxtw #2]
ldff1sw {z0.d}, p0/z, [x0,z0.d,uxtw #2]
LDFF1SW {Z0.D}, P0/Z, [X0,Z0.D,UXTW #2]
ldff1sw z1.d, p0/z, [x0,z0.d,uxtw #2]
ldff1sw {z1.d}, p0/z, [x0,z0.d,uxtw #2]
LDFF1SW {Z1.D}, P0/Z, [X0,Z0.D,UXTW #2]
ldff1sw z31.d, p0/z, [x0,z0.d,uxtw #2]
ldff1sw {z31.d}, p0/z, [x0,z0.d,uxtw #2]
LDFF1SW {Z31.D}, P0/Z, [X0,Z0.D,UXTW #2]
ldff1sw {z0.d}, p2/z, [x0,z0.d,uxtw #2]
LDFF1SW {Z0.D}, P2/Z, [X0,Z0.D,UXTW #2]
ldff1sw {z0.d}, p7/z, [x0,z0.d,uxtw #2]
LDFF1SW {Z0.D}, P7/Z, [X0,Z0.D,UXTW #2]
ldff1sw {z0.d}, p0/z, [x3,z0.d,uxtw #2]
LDFF1SW {Z0.D}, P0/Z, [X3,Z0.D,UXTW #2]
ldff1sw {z0.d}, p0/z, [sp,z0.d,uxtw #2]
LDFF1SW {Z0.D}, P0/Z, [SP,Z0.D,UXTW #2]
ldff1sw {z0.d}, p0/z, [x0,z4.d,uxtw #2]
LDFF1SW {Z0.D}, P0/Z, [X0,Z4.D,UXTW #2]
ldff1sw {z0.d}, p0/z, [x0,z31.d,uxtw #2]
LDFF1SW {Z0.D}, P0/Z, [X0,Z31.D,UXTW #2]
ldff1sw z0.d, p0/z, [x0,z0.d,sxtw #2]
ldff1sw {z0.d}, p0/z, [x0,z0.d,sxtw #2]
LDFF1SW {Z0.D}, P0/Z, [X0,Z0.D,SXTW #2]
ldff1sw z1.d, p0/z, [x0,z0.d,sxtw #2]
ldff1sw {z1.d}, p0/z, [x0,z0.d,sxtw #2]
LDFF1SW {Z1.D}, P0/Z, [X0,Z0.D,SXTW #2]
ldff1sw z31.d, p0/z, [x0,z0.d,sxtw #2]
ldff1sw {z31.d}, p0/z, [x0,z0.d,sxtw #2]
LDFF1SW {Z31.D}, P0/Z, [X0,Z0.D,SXTW #2]
ldff1sw {z0.d}, p2/z, [x0,z0.d,sxtw #2]
LDFF1SW {Z0.D}, P2/Z, [X0,Z0.D,SXTW #2]
ldff1sw {z0.d}, p7/z, [x0,z0.d,sxtw #2]
LDFF1SW {Z0.D}, P7/Z, [X0,Z0.D,SXTW #2]
ldff1sw {z0.d}, p0/z, [x3,z0.d,sxtw #2]
LDFF1SW {Z0.D}, P0/Z, [X3,Z0.D,SXTW #2]
ldff1sw {z0.d}, p0/z, [sp,z0.d,sxtw #2]
LDFF1SW {Z0.D}, P0/Z, [SP,Z0.D,SXTW #2]
ldff1sw {z0.d}, p0/z, [x0,z4.d,sxtw #2]
LDFF1SW {Z0.D}, P0/Z, [X0,Z4.D,SXTW #2]
ldff1sw {z0.d}, p0/z, [x0,z31.d,sxtw #2]
LDFF1SW {Z0.D}, P0/Z, [X0,Z31.D,SXTW #2]
ldff1sw z0.d, p0/z, [x0,z0.d]
ldff1sw {z0.d}, p0/z, [x0,z0.d]
LDFF1SW {Z0.D}, P0/Z, [X0,Z0.D]
ldff1sw {z0.d}, p0/z, [x0,z0.d,lsl #0]
ldff1sw z1.d, p0/z, [x0,z0.d]
ldff1sw {z1.d}, p0/z, [x0,z0.d]
LDFF1SW {Z1.D}, P0/Z, [X0,Z0.D]
ldff1sw {z1.d}, p0/z, [x0,z0.d,lsl #0]
ldff1sw z31.d, p0/z, [x0,z0.d]
ldff1sw {z31.d}, p0/z, [x0,z0.d]
LDFF1SW {Z31.D}, P0/Z, [X0,Z0.D]
ldff1sw {z31.d}, p0/z, [x0,z0.d,lsl #0]
ldff1sw {z0.d}, p2/z, [x0,z0.d]
LDFF1SW {Z0.D}, P2/Z, [X0,Z0.D]
ldff1sw {z0.d}, p2/z, [x0,z0.d,lsl #0]
ldff1sw {z0.d}, p7/z, [x0,z0.d]
LDFF1SW {Z0.D}, P7/Z, [X0,Z0.D]
ldff1sw {z0.d}, p7/z, [x0,z0.d,lsl #0]
ldff1sw {z0.d}, p0/z, [x3,z0.d]
LDFF1SW {Z0.D}, P0/Z, [X3,Z0.D]
ldff1sw {z0.d}, p0/z, [x3,z0.d,lsl #0]
ldff1sw {z0.d}, p0/z, [sp,z0.d]
LDFF1SW {Z0.D}, P0/Z, [SP,Z0.D]
ldff1sw {z0.d}, p0/z, [sp,z0.d,lsl #0]
ldff1sw {z0.d}, p0/z, [x0,z4.d]
LDFF1SW {Z0.D}, P0/Z, [X0,Z4.D]
ldff1sw {z0.d}, p0/z, [x0,z4.d,lsl #0]
ldff1sw {z0.d}, p0/z, [x0,z31.d]
LDFF1SW {Z0.D}, P0/Z, [X0,Z31.D]
ldff1sw {z0.d}, p0/z, [x0,z31.d,lsl #0]
ldff1sw z0.d, p0/z, [x0,z0.d,lsl #2]
ldff1sw {z0.d}, p0/z, [x0,z0.d,lsl #2]
LDFF1SW {Z0.D}, P0/Z, [X0,Z0.D,LSL #2]
ldff1sw z1.d, p0/z, [x0,z0.d,lsl #2]
ldff1sw {z1.d}, p0/z, [x0,z0.d,lsl #2]
LDFF1SW {Z1.D}, P0/Z, [X0,Z0.D,LSL #2]
ldff1sw z31.d, p0/z, [x0,z0.d,lsl #2]
ldff1sw {z31.d}, p0/z, [x0,z0.d,lsl #2]
LDFF1SW {Z31.D}, P0/Z, [X0,Z0.D,LSL #2]
ldff1sw {z0.d}, p2/z, [x0,z0.d,lsl #2]
LDFF1SW {Z0.D}, P2/Z, [X0,Z0.D,LSL #2]
ldff1sw {z0.d}, p7/z, [x0,z0.d,lsl #2]
LDFF1SW {Z0.D}, P7/Z, [X0,Z0.D,LSL #2]
ldff1sw {z0.d}, p0/z, [x3,z0.d,lsl #2]
LDFF1SW {Z0.D}, P0/Z, [X3,Z0.D,LSL #2]
ldff1sw {z0.d}, p0/z, [sp,z0.d,lsl #2]
LDFF1SW {Z0.D}, P0/Z, [SP,Z0.D,LSL #2]
ldff1sw {z0.d}, p0/z, [x0,z4.d,lsl #2]
LDFF1SW {Z0.D}, P0/Z, [X0,Z4.D,LSL #2]
ldff1sw {z0.d}, p0/z, [x0,z31.d,lsl #2]
LDFF1SW {Z0.D}, P0/Z, [X0,Z31.D,LSL #2]
ldff1sw z0.d, p0/z, [z0.d,#0]
ldff1sw {z0.d}, p0/z, [z0.d,#0]
LDFF1SW {Z0.D}, P0/Z, [Z0.D,#0]
ldff1sw {z0.d}, p0/z, [z0.d]
ldff1sw z1.d, p0/z, [z0.d,#0]
ldff1sw {z1.d}, p0/z, [z0.d,#0]
LDFF1SW {Z1.D}, P0/Z, [Z0.D,#0]
ldff1sw {z1.d}, p0/z, [z0.d]
ldff1sw z31.d, p0/z, [z0.d,#0]
ldff1sw {z31.d}, p0/z, [z0.d,#0]
LDFF1SW {Z31.D}, P0/Z, [Z0.D,#0]
ldff1sw {z31.d}, p0/z, [z0.d]
ldff1sw {z0.d}, p2/z, [z0.d,#0]
LDFF1SW {Z0.D}, P2/Z, [Z0.D,#0]
ldff1sw {z0.d}, p2/z, [z0.d]
ldff1sw {z0.d}, p7/z, [z0.d,#0]
LDFF1SW {Z0.D}, P7/Z, [Z0.D,#0]
ldff1sw {z0.d}, p7/z, [z0.d]
ldff1sw {z0.d}, p0/z, [z3.d,#0]
LDFF1SW {Z0.D}, P0/Z, [Z3.D,#0]
ldff1sw {z0.d}, p0/z, [z3.d]
ldff1sw {z0.d}, p0/z, [z31.d,#0]
LDFF1SW {Z0.D}, P0/Z, [Z31.D,#0]
ldff1sw {z0.d}, p0/z, [z31.d]
ldff1sw {z0.d}, p0/z, [z0.d,#60]
LDFF1SW {Z0.D}, P0/Z, [Z0.D,#60]
ldff1sw {z0.d}, p0/z, [z0.d,#64]
LDFF1SW {Z0.D}, P0/Z, [Z0.D,#64]
ldff1sw {z0.d}, p0/z, [z0.d,#68]
LDFF1SW {Z0.D}, P0/Z, [Z0.D,#68]
ldff1sw {z0.d}, p0/z, [z0.d,#124]
LDFF1SW {Z0.D}, P0/Z, [Z0.D,#124]
ldff1w z0.s, p0/z, [x0,z0.s,uxtw]
ldff1w {z0.s}, p0/z, [x0,z0.s,uxtw]
LDFF1W {Z0.S}, P0/Z, [X0,Z0.S,UXTW]
ldff1w {z0.s}, p0/z, [x0,z0.s,uxtw #0]
ldff1w z1.s, p0/z, [x0,z0.s,uxtw]
ldff1w {z1.s}, p0/z, [x0,z0.s,uxtw]
LDFF1W {Z1.S}, P0/Z, [X0,Z0.S,UXTW]
ldff1w {z1.s}, p0/z, [x0,z0.s,uxtw #0]
ldff1w z31.s, p0/z, [x0,z0.s,uxtw]
ldff1w {z31.s}, p0/z, [x0,z0.s,uxtw]
LDFF1W {Z31.S}, P0/Z, [X0,Z0.S,UXTW]
ldff1w {z31.s}, p0/z, [x0,z0.s,uxtw #0]
ldff1w {z0.s}, p2/z, [x0,z0.s,uxtw]
LDFF1W {Z0.S}, P2/Z, [X0,Z0.S,UXTW]
ldff1w {z0.s}, p2/z, [x0,z0.s,uxtw #0]
ldff1w {z0.s}, p7/z, [x0,z0.s,uxtw]
LDFF1W {Z0.S}, P7/Z, [X0,Z0.S,UXTW]
ldff1w {z0.s}, p7/z, [x0,z0.s,uxtw #0]
ldff1w {z0.s}, p0/z, [x3,z0.s,uxtw]
LDFF1W {Z0.S}, P0/Z, [X3,Z0.S,UXTW]
ldff1w {z0.s}, p0/z, [x3,z0.s,uxtw #0]
ldff1w {z0.s}, p0/z, [sp,z0.s,uxtw]
LDFF1W {Z0.S}, P0/Z, [SP,Z0.S,UXTW]
ldff1w {z0.s}, p0/z, [sp,z0.s,uxtw #0]
ldff1w {z0.s}, p0/z, [x0,z4.s,uxtw]
LDFF1W {Z0.S}, P0/Z, [X0,Z4.S,UXTW]
ldff1w {z0.s}, p0/z, [x0,z4.s,uxtw #0]
ldff1w {z0.s}, p0/z, [x0,z31.s,uxtw]
LDFF1W {Z0.S}, P0/Z, [X0,Z31.S,UXTW]
ldff1w {z0.s}, p0/z, [x0,z31.s,uxtw #0]
ldff1w z0.s, p0/z, [x0,z0.s,sxtw]
ldff1w {z0.s}, p0/z, [x0,z0.s,sxtw]
LDFF1W {Z0.S}, P0/Z, [X0,Z0.S,SXTW]
ldff1w {z0.s}, p0/z, [x0,z0.s,sxtw #0]
ldff1w z1.s, p0/z, [x0,z0.s,sxtw]
ldff1w {z1.s}, p0/z, [x0,z0.s,sxtw]
LDFF1W {Z1.S}, P0/Z, [X0,Z0.S,SXTW]
ldff1w {z1.s}, p0/z, [x0,z0.s,sxtw #0]
ldff1w z31.s, p0/z, [x0,z0.s,sxtw]
ldff1w {z31.s}, p0/z, [x0,z0.s,sxtw]
LDFF1W {Z31.S}, P0/Z, [X0,Z0.S,SXTW]
ldff1w {z31.s}, p0/z, [x0,z0.s,sxtw #0]
ldff1w {z0.s}, p2/z, [x0,z0.s,sxtw]
LDFF1W {Z0.S}, P2/Z, [X0,Z0.S,SXTW]
ldff1w {z0.s}, p2/z, [x0,z0.s,sxtw #0]
ldff1w {z0.s}, p7/z, [x0,z0.s,sxtw]
LDFF1W {Z0.S}, P7/Z, [X0,Z0.S,SXTW]
ldff1w {z0.s}, p7/z, [x0,z0.s,sxtw #0]
ldff1w {z0.s}, p0/z, [x3,z0.s,sxtw]
LDFF1W {Z0.S}, P0/Z, [X3,Z0.S,SXTW]
ldff1w {z0.s}, p0/z, [x3,z0.s,sxtw #0]
ldff1w {z0.s}, p0/z, [sp,z0.s,sxtw]
LDFF1W {Z0.S}, P0/Z, [SP,Z0.S,SXTW]
ldff1w {z0.s}, p0/z, [sp,z0.s,sxtw #0]
ldff1w {z0.s}, p0/z, [x0,z4.s,sxtw]
LDFF1W {Z0.S}, P0/Z, [X0,Z4.S,SXTW]
ldff1w {z0.s}, p0/z, [x0,z4.s,sxtw #0]
ldff1w {z0.s}, p0/z, [x0,z31.s,sxtw]
LDFF1W {Z0.S}, P0/Z, [X0,Z31.S,SXTW]
ldff1w {z0.s}, p0/z, [x0,z31.s,sxtw #0]
ldff1w z0.s, p0/z, [x0,z0.s,uxtw #2]
ldff1w {z0.s}, p0/z, [x0,z0.s,uxtw #2]
LDFF1W {Z0.S}, P0/Z, [X0,Z0.S,UXTW #2]
ldff1w z1.s, p0/z, [x0,z0.s,uxtw #2]
ldff1w {z1.s}, p0/z, [x0,z0.s,uxtw #2]
LDFF1W {Z1.S}, P0/Z, [X0,Z0.S,UXTW #2]
ldff1w z31.s, p0/z, [x0,z0.s,uxtw #2]
ldff1w {z31.s}, p0/z, [x0,z0.s,uxtw #2]
LDFF1W {Z31.S}, P0/Z, [X0,Z0.S,UXTW #2]
ldff1w {z0.s}, p2/z, [x0,z0.s,uxtw #2]
LDFF1W {Z0.S}, P2/Z, [X0,Z0.S,UXTW #2]
ldff1w {z0.s}, p7/z, [x0,z0.s,uxtw #2]
LDFF1W {Z0.S}, P7/Z, [X0,Z0.S,UXTW #2]
ldff1w {z0.s}, p0/z, [x3,z0.s,uxtw #2]
LDFF1W {Z0.S}, P0/Z, [X3,Z0.S,UXTW #2]
ldff1w {z0.s}, p0/z, [sp,z0.s,uxtw #2]
LDFF1W {Z0.S}, P0/Z, [SP,Z0.S,UXTW #2]
ldff1w {z0.s}, p0/z, [x0,z4.s,uxtw #2]
LDFF1W {Z0.S}, P0/Z, [X0,Z4.S,UXTW #2]
ldff1w {z0.s}, p0/z, [x0,z31.s,uxtw #2]
LDFF1W {Z0.S}, P0/Z, [X0,Z31.S,UXTW #2]
ldff1w z0.s, p0/z, [x0,z0.s,sxtw #2]
ldff1w {z0.s}, p0/z, [x0,z0.s,sxtw #2]
LDFF1W {Z0.S}, P0/Z, [X0,Z0.S,SXTW #2]
ldff1w z1.s, p0/z, [x0,z0.s,sxtw #2]
ldff1w {z1.s}, p0/z, [x0,z0.s,sxtw #2]
LDFF1W {Z1.S}, P0/Z, [X0,Z0.S,SXTW #2]
ldff1w z31.s, p0/z, [x0,z0.s,sxtw #2]
ldff1w {z31.s}, p0/z, [x0,z0.s,sxtw #2]
LDFF1W {Z31.S}, P0/Z, [X0,Z0.S,SXTW #2]
ldff1w {z0.s}, p2/z, [x0,z0.s,sxtw #2]
LDFF1W {Z0.S}, P2/Z, [X0,Z0.S,SXTW #2]
ldff1w {z0.s}, p7/z, [x0,z0.s,sxtw #2]
LDFF1W {Z0.S}, P7/Z, [X0,Z0.S,SXTW #2]
ldff1w {z0.s}, p0/z, [x3,z0.s,sxtw #2]
LDFF1W {Z0.S}, P0/Z, [X3,Z0.S,SXTW #2]
ldff1w {z0.s}, p0/z, [sp,z0.s,sxtw #2]
LDFF1W {Z0.S}, P0/Z, [SP,Z0.S,SXTW #2]
ldff1w {z0.s}, p0/z, [x0,z4.s,sxtw #2]
LDFF1W {Z0.S}, P0/Z, [X0,Z4.S,SXTW #2]
ldff1w {z0.s}, p0/z, [x0,z31.s,sxtw #2]
LDFF1W {Z0.S}, P0/Z, [X0,Z31.S,SXTW #2]
ldff1w z0.s, p0/z, [x0,x0,lsl #2]
ldff1w {z0.s}, p0/z, [x0,x0,lsl #2]
LDFF1W {Z0.S}, P0/Z, [X0,X0,LSL #2]
ldff1w z1.s, p0/z, [x0,x0,lsl #2]
ldff1w {z1.s}, p0/z, [x0,x0,lsl #2]
LDFF1W {Z1.S}, P0/Z, [X0,X0,LSL #2]
ldff1w z31.s, p0/z, [x0,x0,lsl #2]
ldff1w {z31.s}, p0/z, [x0,x0,lsl #2]
LDFF1W {Z31.S}, P0/Z, [X0,X0,LSL #2]
ldff1w {z0.s}, p2/z, [x0,x0,lsl #2]
LDFF1W {Z0.S}, P2/Z, [X0,X0,LSL #2]
ldff1w {z0.s}, p7/z, [x0,x0,lsl #2]
LDFF1W {Z0.S}, P7/Z, [X0,X0,LSL #2]
ldff1w {z0.s}, p0/z, [x3,x0,lsl #2]
LDFF1W {Z0.S}, P0/Z, [X3,X0,LSL #2]
ldff1w {z0.s}, p0/z, [sp,x0,lsl #2]
LDFF1W {Z0.S}, P0/Z, [SP,X0,LSL #2]
ldff1w {z0.s}, p0/z, [x0,x4,lsl #2]
LDFF1W {Z0.S}, P0/Z, [X0,X4,LSL #2]
ldff1w {z0.s}, p0/z, [x0,xzr,lsl #2]
LDFF1W {Z0.S}, P0/Z, [X0,XZR,LSL #2]
ldff1w z0.d, p0/z, [x0,x0,lsl #2]
ldff1w {z0.d}, p0/z, [x0,x0,lsl #2]
LDFF1W {Z0.D}, P0/Z, [X0,X0,LSL #2]
ldff1w z1.d, p0/z, [x0,x0,lsl #2]
ldff1w {z1.d}, p0/z, [x0,x0,lsl #2]
LDFF1W {Z1.D}, P0/Z, [X0,X0,LSL #2]
ldff1w z31.d, p0/z, [x0,x0,lsl #2]
ldff1w {z31.d}, p0/z, [x0,x0,lsl #2]
LDFF1W {Z31.D}, P0/Z, [X0,X0,LSL #2]
ldff1w {z0.d}, p2/z, [x0,x0,lsl #2]
LDFF1W {Z0.D}, P2/Z, [X0,X0,LSL #2]
ldff1w {z0.d}, p7/z, [x0,x0,lsl #2]
LDFF1W {Z0.D}, P7/Z, [X0,X0,LSL #2]
ldff1w {z0.d}, p0/z, [x3,x0,lsl #2]
LDFF1W {Z0.D}, P0/Z, [X3,X0,LSL #2]
ldff1w {z0.d}, p0/z, [sp,x0,lsl #2]
LDFF1W {Z0.D}, P0/Z, [SP,X0,LSL #2]
ldff1w {z0.d}, p0/z, [x0,x4,lsl #2]
LDFF1W {Z0.D}, P0/Z, [X0,X4,LSL #2]
ldff1w {z0.d}, p0/z, [x0,xzr,lsl #2]
LDFF1W {Z0.D}, P0/Z, [X0,XZR,LSL #2]
ldff1w z0.d, p0/z, [x0,z0.d,uxtw]
ldff1w {z0.d}, p0/z, [x0,z0.d,uxtw]
LDFF1W {Z0.D}, P0/Z, [X0,Z0.D,UXTW]
ldff1w {z0.d}, p0/z, [x0,z0.d,uxtw #0]
ldff1w z1.d, p0/z, [x0,z0.d,uxtw]
ldff1w {z1.d}, p0/z, [x0,z0.d,uxtw]
LDFF1W {Z1.D}, P0/Z, [X0,Z0.D,UXTW]
ldff1w {z1.d}, p0/z, [x0,z0.d,uxtw #0]
ldff1w z31.d, p0/z, [x0,z0.d,uxtw]
ldff1w {z31.d}, p0/z, [x0,z0.d,uxtw]
LDFF1W {Z31.D}, P0/Z, [X0,Z0.D,UXTW]
ldff1w {z31.d}, p0/z, [x0,z0.d,uxtw #0]
ldff1w {z0.d}, p2/z, [x0,z0.d,uxtw]
LDFF1W {Z0.D}, P2/Z, [X0,Z0.D,UXTW]
ldff1w {z0.d}, p2/z, [x0,z0.d,uxtw #0]
ldff1w {z0.d}, p7/z, [x0,z0.d,uxtw]
LDFF1W {Z0.D}, P7/Z, [X0,Z0.D,UXTW]
ldff1w {z0.d}, p7/z, [x0,z0.d,uxtw #0]
ldff1w {z0.d}, p0/z, [x3,z0.d,uxtw]
LDFF1W {Z0.D}, P0/Z, [X3,Z0.D,UXTW]
ldff1w {z0.d}, p0/z, [x3,z0.d,uxtw #0]
ldff1w {z0.d}, p0/z, [sp,z0.d,uxtw]
LDFF1W {Z0.D}, P0/Z, [SP,Z0.D,UXTW]
ldff1w {z0.d}, p0/z, [sp,z0.d,uxtw #0]
ldff1w {z0.d}, p0/z, [x0,z4.d,uxtw]
LDFF1W {Z0.D}, P0/Z, [X0,Z4.D,UXTW]
ldff1w {z0.d}, p0/z, [x0,z4.d,uxtw #0]
ldff1w {z0.d}, p0/z, [x0,z31.d,uxtw]
LDFF1W {Z0.D}, P0/Z, [X0,Z31.D,UXTW]
ldff1w {z0.d}, p0/z, [x0,z31.d,uxtw #0]
ldff1w z0.d, p0/z, [x0,z0.d,sxtw]
ldff1w {z0.d}, p0/z, [x0,z0.d,sxtw]
LDFF1W {Z0.D}, P0/Z, [X0,Z0.D,SXTW]
ldff1w {z0.d}, p0/z, [x0,z0.d,sxtw #0]
ldff1w z1.d, p0/z, [x0,z0.d,sxtw]
ldff1w {z1.d}, p0/z, [x0,z0.d,sxtw]
LDFF1W {Z1.D}, P0/Z, [X0,Z0.D,SXTW]
ldff1w {z1.d}, p0/z, [x0,z0.d,sxtw #0]
ldff1w z31.d, p0/z, [x0,z0.d,sxtw]
ldff1w {z31.d}, p0/z, [x0,z0.d,sxtw]
LDFF1W {Z31.D}, P0/Z, [X0,Z0.D,SXTW]
ldff1w {z31.d}, p0/z, [x0,z0.d,sxtw #0]
ldff1w {z0.d}, p2/z, [x0,z0.d,sxtw]
LDFF1W {Z0.D}, P2/Z, [X0,Z0.D,SXTW]
ldff1w {z0.d}, p2/z, [x0,z0.d,sxtw #0]
ldff1w {z0.d}, p7/z, [x0,z0.d,sxtw]
LDFF1W {Z0.D}, P7/Z, [X0,Z0.D,SXTW]
ldff1w {z0.d}, p7/z, [x0,z0.d,sxtw #0]
ldff1w {z0.d}, p0/z, [x3,z0.d,sxtw]
LDFF1W {Z0.D}, P0/Z, [X3,Z0.D,SXTW]
ldff1w {z0.d}, p0/z, [x3,z0.d,sxtw #0]
ldff1w {z0.d}, p0/z, [sp,z0.d,sxtw]
LDFF1W {Z0.D}, P0/Z, [SP,Z0.D,SXTW]
ldff1w {z0.d}, p0/z, [sp,z0.d,sxtw #0]
ldff1w {z0.d}, p0/z, [x0,z4.d,sxtw]
LDFF1W {Z0.D}, P0/Z, [X0,Z4.D,SXTW]
ldff1w {z0.d}, p0/z, [x0,z4.d,sxtw #0]
ldff1w {z0.d}, p0/z, [x0,z31.d,sxtw]
LDFF1W {Z0.D}, P0/Z, [X0,Z31.D,SXTW]
ldff1w {z0.d}, p0/z, [x0,z31.d,sxtw #0]
ldff1w z0.d, p0/z, [x0,z0.d,uxtw #2]
ldff1w {z0.d}, p0/z, [x0,z0.d,uxtw #2]
LDFF1W {Z0.D}, P0/Z, [X0,Z0.D,UXTW #2]
ldff1w z1.d, p0/z, [x0,z0.d,uxtw #2]
ldff1w {z1.d}, p0/z, [x0,z0.d,uxtw #2]
LDFF1W {Z1.D}, P0/Z, [X0,Z0.D,UXTW #2]
ldff1w z31.d, p0/z, [x0,z0.d,uxtw #2]
ldff1w {z31.d}, p0/z, [x0,z0.d,uxtw #2]
LDFF1W {Z31.D}, P0/Z, [X0,Z0.D,UXTW #2]
ldff1w {z0.d}, p2/z, [x0,z0.d,uxtw #2]
LDFF1W {Z0.D}, P2/Z, [X0,Z0.D,UXTW #2]
ldff1w {z0.d}, p7/z, [x0,z0.d,uxtw #2]
LDFF1W {Z0.D}, P7/Z, [X0,Z0.D,UXTW #2]
ldff1w {z0.d}, p0/z, [x3,z0.d,uxtw #2]
LDFF1W {Z0.D}, P0/Z, [X3,Z0.D,UXTW #2]
ldff1w {z0.d}, p0/z, [sp,z0.d,uxtw #2]
LDFF1W {Z0.D}, P0/Z, [SP,Z0.D,UXTW #2]
ldff1w {z0.d}, p0/z, [x0,z4.d,uxtw #2]
LDFF1W {Z0.D}, P0/Z, [X0,Z4.D,UXTW #2]
ldff1w {z0.d}, p0/z, [x0,z31.d,uxtw #2]
LDFF1W {Z0.D}, P0/Z, [X0,Z31.D,UXTW #2]
ldff1w z0.d, p0/z, [x0,z0.d,sxtw #2]
ldff1w {z0.d}, p0/z, [x0,z0.d,sxtw #2]
LDFF1W {Z0.D}, P0/Z, [X0,Z0.D,SXTW #2]
ldff1w z1.d, p0/z, [x0,z0.d,sxtw #2]
ldff1w {z1.d}, p0/z, [x0,z0.d,sxtw #2]
LDFF1W {Z1.D}, P0/Z, [X0,Z0.D,SXTW #2]
ldff1w z31.d, p0/z, [x0,z0.d,sxtw #2]
ldff1w {z31.d}, p0/z, [x0,z0.d,sxtw #2]
LDFF1W {Z31.D}, P0/Z, [X0,Z0.D,SXTW #2]
ldff1w {z0.d}, p2/z, [x0,z0.d,sxtw #2]
LDFF1W {Z0.D}, P2/Z, [X0,Z0.D,SXTW #2]
ldff1w {z0.d}, p7/z, [x0,z0.d,sxtw #2]
LDFF1W {Z0.D}, P7/Z, [X0,Z0.D,SXTW #2]
ldff1w {z0.d}, p0/z, [x3,z0.d,sxtw #2]
LDFF1W {Z0.D}, P0/Z, [X3,Z0.D,SXTW #2]
ldff1w {z0.d}, p0/z, [sp,z0.d,sxtw #2]
LDFF1W {Z0.D}, P0/Z, [SP,Z0.D,SXTW #2]
ldff1w {z0.d}, p0/z, [x0,z4.d,sxtw #2]
LDFF1W {Z0.D}, P0/Z, [X0,Z4.D,SXTW #2]
ldff1w {z0.d}, p0/z, [x0,z31.d,sxtw #2]
LDFF1W {Z0.D}, P0/Z, [X0,Z31.D,SXTW #2]
ldff1w z0.d, p0/z, [x0,z0.d]
ldff1w {z0.d}, p0/z, [x0,z0.d]
LDFF1W {Z0.D}, P0/Z, [X0,Z0.D]
ldff1w {z0.d}, p0/z, [x0,z0.d,lsl #0]
ldff1w z1.d, p0/z, [x0,z0.d]
ldff1w {z1.d}, p0/z, [x0,z0.d]
LDFF1W {Z1.D}, P0/Z, [X0,Z0.D]
ldff1w {z1.d}, p0/z, [x0,z0.d,lsl #0]
ldff1w z31.d, p0/z, [x0,z0.d]
ldff1w {z31.d}, p0/z, [x0,z0.d]
LDFF1W {Z31.D}, P0/Z, [X0,Z0.D]
ldff1w {z31.d}, p0/z, [x0,z0.d,lsl #0]
ldff1w {z0.d}, p2/z, [x0,z0.d]
LDFF1W {Z0.D}, P2/Z, [X0,Z0.D]
ldff1w {z0.d}, p2/z, [x0,z0.d,lsl #0]
ldff1w {z0.d}, p7/z, [x0,z0.d]
LDFF1W {Z0.D}, P7/Z, [X0,Z0.D]
ldff1w {z0.d}, p7/z, [x0,z0.d,lsl #0]
ldff1w {z0.d}, p0/z, [x3,z0.d]
LDFF1W {Z0.D}, P0/Z, [X3,Z0.D]
ldff1w {z0.d}, p0/z, [x3,z0.d,lsl #0]
ldff1w {z0.d}, p0/z, [sp,z0.d]
LDFF1W {Z0.D}, P0/Z, [SP,Z0.D]
ldff1w {z0.d}, p0/z, [sp,z0.d,lsl #0]
ldff1w {z0.d}, p0/z, [x0,z4.d]
LDFF1W {Z0.D}, P0/Z, [X0,Z4.D]
ldff1w {z0.d}, p0/z, [x0,z4.d,lsl #0]
ldff1w {z0.d}, p0/z, [x0,z31.d]
LDFF1W {Z0.D}, P0/Z, [X0,Z31.D]
ldff1w {z0.d}, p0/z, [x0,z31.d,lsl #0]
ldff1w z0.d, p0/z, [x0,z0.d,lsl #2]
ldff1w {z0.d}, p0/z, [x0,z0.d,lsl #2]
LDFF1W {Z0.D}, P0/Z, [X0,Z0.D,LSL #2]
ldff1w z1.d, p0/z, [x0,z0.d,lsl #2]
ldff1w {z1.d}, p0/z, [x0,z0.d,lsl #2]
LDFF1W {Z1.D}, P0/Z, [X0,Z0.D,LSL #2]
ldff1w z31.d, p0/z, [x0,z0.d,lsl #2]
ldff1w {z31.d}, p0/z, [x0,z0.d,lsl #2]
LDFF1W {Z31.D}, P0/Z, [X0,Z0.D,LSL #2]
ldff1w {z0.d}, p2/z, [x0,z0.d,lsl #2]
LDFF1W {Z0.D}, P2/Z, [X0,Z0.D,LSL #2]
ldff1w {z0.d}, p7/z, [x0,z0.d,lsl #2]
LDFF1W {Z0.D}, P7/Z, [X0,Z0.D,LSL #2]
ldff1w {z0.d}, p0/z, [x3,z0.d,lsl #2]
LDFF1W {Z0.D}, P0/Z, [X3,Z0.D,LSL #2]
ldff1w {z0.d}, p0/z, [sp,z0.d,lsl #2]
LDFF1W {Z0.D}, P0/Z, [SP,Z0.D,LSL #2]
ldff1w {z0.d}, p0/z, [x0,z4.d,lsl #2]
LDFF1W {Z0.D}, P0/Z, [X0,Z4.D,LSL #2]
ldff1w {z0.d}, p0/z, [x0,z31.d,lsl #2]
LDFF1W {Z0.D}, P0/Z, [X0,Z31.D,LSL #2]
ldff1w z0.s, p0/z, [z0.s,#0]
ldff1w {z0.s}, p0/z, [z0.s,#0]
LDFF1W {Z0.S}, P0/Z, [Z0.S,#0]
ldff1w {z0.s}, p0/z, [z0.s]
ldff1w z1.s, p0/z, [z0.s,#0]
ldff1w {z1.s}, p0/z, [z0.s,#0]
LDFF1W {Z1.S}, P0/Z, [Z0.S,#0]
ldff1w {z1.s}, p0/z, [z0.s]
ldff1w z31.s, p0/z, [z0.s,#0]
ldff1w {z31.s}, p0/z, [z0.s,#0]
LDFF1W {Z31.S}, P0/Z, [Z0.S,#0]
ldff1w {z31.s}, p0/z, [z0.s]
ldff1w {z0.s}, p2/z, [z0.s,#0]
LDFF1W {Z0.S}, P2/Z, [Z0.S,#0]
ldff1w {z0.s}, p2/z, [z0.s]
ldff1w {z0.s}, p7/z, [z0.s,#0]
LDFF1W {Z0.S}, P7/Z, [Z0.S,#0]
ldff1w {z0.s}, p7/z, [z0.s]
ldff1w {z0.s}, p0/z, [z3.s,#0]
LDFF1W {Z0.S}, P0/Z, [Z3.S,#0]
ldff1w {z0.s}, p0/z, [z3.s]
ldff1w {z0.s}, p0/z, [z31.s,#0]
LDFF1W {Z0.S}, P0/Z, [Z31.S,#0]
ldff1w {z0.s}, p0/z, [z31.s]
ldff1w {z0.s}, p0/z, [z0.s,#60]
LDFF1W {Z0.S}, P0/Z, [Z0.S,#60]
ldff1w {z0.s}, p0/z, [z0.s,#64]
LDFF1W {Z0.S}, P0/Z, [Z0.S,#64]
ldff1w {z0.s}, p0/z, [z0.s,#68]
LDFF1W {Z0.S}, P0/Z, [Z0.S,#68]
ldff1w {z0.s}, p0/z, [z0.s,#124]
LDFF1W {Z0.S}, P0/Z, [Z0.S,#124]
ldff1w z0.d, p0/z, [z0.d,#0]
ldff1w {z0.d}, p0/z, [z0.d,#0]
LDFF1W {Z0.D}, P0/Z, [Z0.D,#0]
ldff1w {z0.d}, p0/z, [z0.d]
ldff1w z1.d, p0/z, [z0.d,#0]
ldff1w {z1.d}, p0/z, [z0.d,#0]
LDFF1W {Z1.D}, P0/Z, [Z0.D,#0]
ldff1w {z1.d}, p0/z, [z0.d]
ldff1w z31.d, p0/z, [z0.d,#0]
ldff1w {z31.d}, p0/z, [z0.d,#0]
LDFF1W {Z31.D}, P0/Z, [Z0.D,#0]
ldff1w {z31.d}, p0/z, [z0.d]
ldff1w {z0.d}, p2/z, [z0.d,#0]
LDFF1W {Z0.D}, P2/Z, [Z0.D,#0]
ldff1w {z0.d}, p2/z, [z0.d]
ldff1w {z0.d}, p7/z, [z0.d,#0]
LDFF1W {Z0.D}, P7/Z, [Z0.D,#0]
ldff1w {z0.d}, p7/z, [z0.d]
ldff1w {z0.d}, p0/z, [z3.d,#0]
LDFF1W {Z0.D}, P0/Z, [Z3.D,#0]
ldff1w {z0.d}, p0/z, [z3.d]
ldff1w {z0.d}, p0/z, [z31.d,#0]
LDFF1W {Z0.D}, P0/Z, [Z31.D,#0]
ldff1w {z0.d}, p0/z, [z31.d]
ldff1w {z0.d}, p0/z, [z0.d,#60]
LDFF1W {Z0.D}, P0/Z, [Z0.D,#60]
ldff1w {z0.d}, p0/z, [z0.d,#64]
LDFF1W {Z0.D}, P0/Z, [Z0.D,#64]
ldff1w {z0.d}, p0/z, [z0.d,#68]
LDFF1W {Z0.D}, P0/Z, [Z0.D,#68]
ldff1w {z0.d}, p0/z, [z0.d,#124]
LDFF1W {Z0.D}, P0/Z, [Z0.D,#124]
ldnf1b z0.b, p0/z, [x0,#0]
ldnf1b {z0.b}, p0/z, [x0,#0]
LDNF1B {Z0.B}, P0/Z, [X0,#0]
ldnf1b {z0.b}, p0/z, [x0,#0,mul vl]
ldnf1b {z0.b}, p0/z, [x0]
ldnf1b z1.b, p0/z, [x0,#0]
ldnf1b {z1.b}, p0/z, [x0,#0]
LDNF1B {Z1.B}, P0/Z, [X0,#0]
ldnf1b {z1.b}, p0/z, [x0,#0,mul vl]
ldnf1b {z1.b}, p0/z, [x0]
ldnf1b z31.b, p0/z, [x0,#0]
ldnf1b {z31.b}, p0/z, [x0,#0]
LDNF1B {Z31.B}, P0/Z, [X0,#0]
ldnf1b {z31.b}, p0/z, [x0,#0,mul vl]
ldnf1b {z31.b}, p0/z, [x0]
ldnf1b {z0.b}, p2/z, [x0,#0]
LDNF1B {Z0.B}, P2/Z, [X0,#0]
ldnf1b {z0.b}, p2/z, [x0,#0,mul vl]
ldnf1b {z0.b}, p2/z, [x0]
ldnf1b {z0.b}, p7/z, [x0,#0]
LDNF1B {Z0.B}, P7/Z, [X0,#0]
ldnf1b {z0.b}, p7/z, [x0,#0,mul vl]
ldnf1b {z0.b}, p7/z, [x0]
ldnf1b {z0.b}, p0/z, [x3,#0]
LDNF1B {Z0.B}, P0/Z, [X3,#0]
ldnf1b {z0.b}, p0/z, [x3,#0,mul vl]
ldnf1b {z0.b}, p0/z, [x3]
ldnf1b {z0.b}, p0/z, [sp,#0]
LDNF1B {Z0.B}, P0/Z, [SP,#0]
ldnf1b {z0.b}, p0/z, [sp,#0,mul vl]
ldnf1b {z0.b}, p0/z, [sp]
ldnf1b {z0.b}, p0/z, [x0,#7,mul vl]
LDNF1B {Z0.B}, P0/Z, [X0,#7,MUL VL]
ldnf1b {z0.b}, p0/z, [x0,#-8,mul vl]
LDNF1B {Z0.B}, P0/Z, [X0,#-8,MUL VL]
ldnf1b {z0.b}, p0/z, [x0,#-7,mul vl]
LDNF1B {Z0.B}, P0/Z, [X0,#-7,MUL VL]
ldnf1b {z0.b}, p0/z, [x0,#-1,mul vl]
LDNF1B {Z0.B}, P0/Z, [X0,#-1,MUL VL]
ldnf1b z0.h, p0/z, [x0,#0]
ldnf1b {z0.h}, p0/z, [x0,#0]
LDNF1B {Z0.H}, P0/Z, [X0,#0]
ldnf1b {z0.h}, p0/z, [x0,#0,mul vl]
ldnf1b {z0.h}, p0/z, [x0]
ldnf1b z1.h, p0/z, [x0,#0]
ldnf1b {z1.h}, p0/z, [x0,#0]
LDNF1B {Z1.H}, P0/Z, [X0,#0]
ldnf1b {z1.h}, p0/z, [x0,#0,mul vl]
ldnf1b {z1.h}, p0/z, [x0]
ldnf1b z31.h, p0/z, [x0,#0]
ldnf1b {z31.h}, p0/z, [x0,#0]
LDNF1B {Z31.H}, P0/Z, [X0,#0]
ldnf1b {z31.h}, p0/z, [x0,#0,mul vl]
ldnf1b {z31.h}, p0/z, [x0]
ldnf1b {z0.h}, p2/z, [x0,#0]
LDNF1B {Z0.H}, P2/Z, [X0,#0]
ldnf1b {z0.h}, p2/z, [x0,#0,mul vl]
ldnf1b {z0.h}, p2/z, [x0]
ldnf1b {z0.h}, p7/z, [x0,#0]
LDNF1B {Z0.H}, P7/Z, [X0,#0]
ldnf1b {z0.h}, p7/z, [x0,#0,mul vl]
ldnf1b {z0.h}, p7/z, [x0]
ldnf1b {z0.h}, p0/z, [x3,#0]
LDNF1B {Z0.H}, P0/Z, [X3,#0]
ldnf1b {z0.h}, p0/z, [x3,#0,mul vl]
ldnf1b {z0.h}, p0/z, [x3]
ldnf1b {z0.h}, p0/z, [sp,#0]
LDNF1B {Z0.H}, P0/Z, [SP,#0]
ldnf1b {z0.h}, p0/z, [sp,#0,mul vl]
ldnf1b {z0.h}, p0/z, [sp]
ldnf1b {z0.h}, p0/z, [x0,#7,mul vl]
LDNF1B {Z0.H}, P0/Z, [X0,#7,MUL VL]
ldnf1b {z0.h}, p0/z, [x0,#-8,mul vl]
LDNF1B {Z0.H}, P0/Z, [X0,#-8,MUL VL]
ldnf1b {z0.h}, p0/z, [x0,#-7,mul vl]
LDNF1B {Z0.H}, P0/Z, [X0,#-7,MUL VL]
ldnf1b {z0.h}, p0/z, [x0,#-1,mul vl]
LDNF1B {Z0.H}, P0/Z, [X0,#-1,MUL VL]
ldnf1b z0.s, p0/z, [x0,#0]
ldnf1b {z0.s}, p0/z, [x0,#0]
LDNF1B {Z0.S}, P0/Z, [X0,#0]
ldnf1b {z0.s}, p0/z, [x0,#0,mul vl]
ldnf1b {z0.s}, p0/z, [x0]
ldnf1b z1.s, p0/z, [x0,#0]
ldnf1b {z1.s}, p0/z, [x0,#0]
LDNF1B {Z1.S}, P0/Z, [X0,#0]
ldnf1b {z1.s}, p0/z, [x0,#0,mul vl]
ldnf1b {z1.s}, p0/z, [x0]
ldnf1b z31.s, p0/z, [x0,#0]
ldnf1b {z31.s}, p0/z, [x0,#0]
LDNF1B {Z31.S}, P0/Z, [X0,#0]
ldnf1b {z31.s}, p0/z, [x0,#0,mul vl]
ldnf1b {z31.s}, p0/z, [x0]
ldnf1b {z0.s}, p2/z, [x0,#0]
LDNF1B {Z0.S}, P2/Z, [X0,#0]
ldnf1b {z0.s}, p2/z, [x0,#0,mul vl]
ldnf1b {z0.s}, p2/z, [x0]
ldnf1b {z0.s}, p7/z, [x0,#0]
LDNF1B {Z0.S}, P7/Z, [X0,#0]
ldnf1b {z0.s}, p7/z, [x0,#0,mul vl]
ldnf1b {z0.s}, p7/z, [x0]
ldnf1b {z0.s}, p0/z, [x3,#0]
LDNF1B {Z0.S}, P0/Z, [X3,#0]
ldnf1b {z0.s}, p0/z, [x3,#0,mul vl]
ldnf1b {z0.s}, p0/z, [x3]
ldnf1b {z0.s}, p0/z, [sp,#0]
LDNF1B {Z0.S}, P0/Z, [SP,#0]
ldnf1b {z0.s}, p0/z, [sp,#0,mul vl]
ldnf1b {z0.s}, p0/z, [sp]
ldnf1b {z0.s}, p0/z, [x0,#7,mul vl]
LDNF1B {Z0.S}, P0/Z, [X0,#7,MUL VL]
ldnf1b {z0.s}, p0/z, [x0,#-8,mul vl]
LDNF1B {Z0.S}, P0/Z, [X0,#-8,MUL VL]
ldnf1b {z0.s}, p0/z, [x0,#-7,mul vl]
LDNF1B {Z0.S}, P0/Z, [X0,#-7,MUL VL]
ldnf1b {z0.s}, p0/z, [x0,#-1,mul vl]
LDNF1B {Z0.S}, P0/Z, [X0,#-1,MUL VL]
ldnf1b z0.d, p0/z, [x0,#0]
ldnf1b {z0.d}, p0/z, [x0,#0]
LDNF1B {Z0.D}, P0/Z, [X0,#0]
ldnf1b {z0.d}, p0/z, [x0,#0,mul vl]
ldnf1b {z0.d}, p0/z, [x0]
ldnf1b z1.d, p0/z, [x0,#0]
ldnf1b {z1.d}, p0/z, [x0,#0]
LDNF1B {Z1.D}, P0/Z, [X0,#0]
ldnf1b {z1.d}, p0/z, [x0,#0,mul vl]
ldnf1b {z1.d}, p0/z, [x0]
ldnf1b z31.d, p0/z, [x0,#0]
ldnf1b {z31.d}, p0/z, [x0,#0]
LDNF1B {Z31.D}, P0/Z, [X0,#0]
ldnf1b {z31.d}, p0/z, [x0,#0,mul vl]
ldnf1b {z31.d}, p0/z, [x0]
ldnf1b {z0.d}, p2/z, [x0,#0]
LDNF1B {Z0.D}, P2/Z, [X0,#0]
ldnf1b {z0.d}, p2/z, [x0,#0,mul vl]
ldnf1b {z0.d}, p2/z, [x0]
ldnf1b {z0.d}, p7/z, [x0,#0]
LDNF1B {Z0.D}, P7/Z, [X0,#0]
ldnf1b {z0.d}, p7/z, [x0,#0,mul vl]
ldnf1b {z0.d}, p7/z, [x0]
ldnf1b {z0.d}, p0/z, [x3,#0]
LDNF1B {Z0.D}, P0/Z, [X3,#0]
ldnf1b {z0.d}, p0/z, [x3,#0,mul vl]
ldnf1b {z0.d}, p0/z, [x3]
ldnf1b {z0.d}, p0/z, [sp,#0]
LDNF1B {Z0.D}, P0/Z, [SP,#0]
ldnf1b {z0.d}, p0/z, [sp,#0,mul vl]
ldnf1b {z0.d}, p0/z, [sp]
ldnf1b {z0.d}, p0/z, [x0,#7,mul vl]
LDNF1B {Z0.D}, P0/Z, [X0,#7,MUL VL]
ldnf1b {z0.d}, p0/z, [x0,#-8,mul vl]
LDNF1B {Z0.D}, P0/Z, [X0,#-8,MUL VL]
ldnf1b {z0.d}, p0/z, [x0,#-7,mul vl]
LDNF1B {Z0.D}, P0/Z, [X0,#-7,MUL VL]
ldnf1b {z0.d}, p0/z, [x0,#-1,mul vl]
LDNF1B {Z0.D}, P0/Z, [X0,#-1,MUL VL]
ldnf1d z0.d, p0/z, [x0,#0]
ldnf1d {z0.d}, p0/z, [x0,#0]
LDNF1D {Z0.D}, P0/Z, [X0,#0]
ldnf1d {z0.d}, p0/z, [x0,#0,mul vl]
ldnf1d {z0.d}, p0/z, [x0]
ldnf1d z1.d, p0/z, [x0,#0]
ldnf1d {z1.d}, p0/z, [x0,#0]
LDNF1D {Z1.D}, P0/Z, [X0,#0]
ldnf1d {z1.d}, p0/z, [x0,#0,mul vl]
ldnf1d {z1.d}, p0/z, [x0]
ldnf1d z31.d, p0/z, [x0,#0]
ldnf1d {z31.d}, p0/z, [x0,#0]
LDNF1D {Z31.D}, P0/Z, [X0,#0]
ldnf1d {z31.d}, p0/z, [x0,#0,mul vl]
ldnf1d {z31.d}, p0/z, [x0]
ldnf1d {z0.d}, p2/z, [x0,#0]
LDNF1D {Z0.D}, P2/Z, [X0,#0]
ldnf1d {z0.d}, p2/z, [x0,#0,mul vl]
ldnf1d {z0.d}, p2/z, [x0]
ldnf1d {z0.d}, p7/z, [x0,#0]
LDNF1D {Z0.D}, P7/Z, [X0,#0]
ldnf1d {z0.d}, p7/z, [x0,#0,mul vl]
ldnf1d {z0.d}, p7/z, [x0]
ldnf1d {z0.d}, p0/z, [x3,#0]
LDNF1D {Z0.D}, P0/Z, [X3,#0]
ldnf1d {z0.d}, p0/z, [x3,#0,mul vl]
ldnf1d {z0.d}, p0/z, [x3]
ldnf1d {z0.d}, p0/z, [sp,#0]
LDNF1D {Z0.D}, P0/Z, [SP,#0]
ldnf1d {z0.d}, p0/z, [sp,#0,mul vl]
ldnf1d {z0.d}, p0/z, [sp]
ldnf1d {z0.d}, p0/z, [x0,#7,mul vl]
LDNF1D {Z0.D}, P0/Z, [X0,#7,MUL VL]
ldnf1d {z0.d}, p0/z, [x0,#-8,mul vl]
LDNF1D {Z0.D}, P0/Z, [X0,#-8,MUL VL]
ldnf1d {z0.d}, p0/z, [x0,#-7,mul vl]
LDNF1D {Z0.D}, P0/Z, [X0,#-7,MUL VL]
ldnf1d {z0.d}, p0/z, [x0,#-1,mul vl]
LDNF1D {Z0.D}, P0/Z, [X0,#-1,MUL VL]
ldnf1h z0.h, p0/z, [x0,#0]
ldnf1h {z0.h}, p0/z, [x0,#0]
LDNF1H {Z0.H}, P0/Z, [X0,#0]
ldnf1h {z0.h}, p0/z, [x0,#0,mul vl]
ldnf1h {z0.h}, p0/z, [x0]
ldnf1h z1.h, p0/z, [x0,#0]
ldnf1h {z1.h}, p0/z, [x0,#0]
LDNF1H {Z1.H}, P0/Z, [X0,#0]
ldnf1h {z1.h}, p0/z, [x0,#0,mul vl]
ldnf1h {z1.h}, p0/z, [x0]
ldnf1h z31.h, p0/z, [x0,#0]
ldnf1h {z31.h}, p0/z, [x0,#0]
LDNF1H {Z31.H}, P0/Z, [X0,#0]
ldnf1h {z31.h}, p0/z, [x0,#0,mul vl]
ldnf1h {z31.h}, p0/z, [x0]
ldnf1h {z0.h}, p2/z, [x0,#0]
LDNF1H {Z0.H}, P2/Z, [X0,#0]
ldnf1h {z0.h}, p2/z, [x0,#0,mul vl]
ldnf1h {z0.h}, p2/z, [x0]
ldnf1h {z0.h}, p7/z, [x0,#0]
LDNF1H {Z0.H}, P7/Z, [X0,#0]
ldnf1h {z0.h}, p7/z, [x0,#0,mul vl]
ldnf1h {z0.h}, p7/z, [x0]
ldnf1h {z0.h}, p0/z, [x3,#0]
LDNF1H {Z0.H}, P0/Z, [X3,#0]
ldnf1h {z0.h}, p0/z, [x3,#0,mul vl]
ldnf1h {z0.h}, p0/z, [x3]
ldnf1h {z0.h}, p0/z, [sp,#0]
LDNF1H {Z0.H}, P0/Z, [SP,#0]
ldnf1h {z0.h}, p0/z, [sp,#0,mul vl]
ldnf1h {z0.h}, p0/z, [sp]
ldnf1h {z0.h}, p0/z, [x0,#7,mul vl]
LDNF1H {Z0.H}, P0/Z, [X0,#7,MUL VL]
ldnf1h {z0.h}, p0/z, [x0,#-8,mul vl]
LDNF1H {Z0.H}, P0/Z, [X0,#-8,MUL VL]
ldnf1h {z0.h}, p0/z, [x0,#-7,mul vl]
LDNF1H {Z0.H}, P0/Z, [X0,#-7,MUL VL]
ldnf1h {z0.h}, p0/z, [x0,#-1,mul vl]
LDNF1H {Z0.H}, P0/Z, [X0,#-1,MUL VL]
ldnf1h z0.s, p0/z, [x0,#0]
ldnf1h {z0.s}, p0/z, [x0,#0]
LDNF1H {Z0.S}, P0/Z, [X0,#0]
ldnf1h {z0.s}, p0/z, [x0,#0,mul vl]
ldnf1h {z0.s}, p0/z, [x0]
ldnf1h z1.s, p0/z, [x0,#0]
ldnf1h {z1.s}, p0/z, [x0,#0]
LDNF1H {Z1.S}, P0/Z, [X0,#0]
ldnf1h {z1.s}, p0/z, [x0,#0,mul vl]
ldnf1h {z1.s}, p0/z, [x0]
ldnf1h z31.s, p0/z, [x0,#0]
ldnf1h {z31.s}, p0/z, [x0,#0]
LDNF1H {Z31.S}, P0/Z, [X0,#0]
ldnf1h {z31.s}, p0/z, [x0,#0,mul vl]
ldnf1h {z31.s}, p0/z, [x0]
ldnf1h {z0.s}, p2/z, [x0,#0]
LDNF1H {Z0.S}, P2/Z, [X0,#0]
ldnf1h {z0.s}, p2/z, [x0,#0,mul vl]
ldnf1h {z0.s}, p2/z, [x0]
ldnf1h {z0.s}, p7/z, [x0,#0]
LDNF1H {Z0.S}, P7/Z, [X0,#0]
ldnf1h {z0.s}, p7/z, [x0,#0,mul vl]
ldnf1h {z0.s}, p7/z, [x0]
ldnf1h {z0.s}, p0/z, [x3,#0]
LDNF1H {Z0.S}, P0/Z, [X3,#0]
ldnf1h {z0.s}, p0/z, [x3,#0,mul vl]
ldnf1h {z0.s}, p0/z, [x3]
ldnf1h {z0.s}, p0/z, [sp,#0]
LDNF1H {Z0.S}, P0/Z, [SP,#0]
ldnf1h {z0.s}, p0/z, [sp,#0,mul vl]
ldnf1h {z0.s}, p0/z, [sp]
ldnf1h {z0.s}, p0/z, [x0,#7,mul vl]
LDNF1H {Z0.S}, P0/Z, [X0,#7,MUL VL]
ldnf1h {z0.s}, p0/z, [x0,#-8,mul vl]
LDNF1H {Z0.S}, P0/Z, [X0,#-8,MUL VL]
ldnf1h {z0.s}, p0/z, [x0,#-7,mul vl]
LDNF1H {Z0.S}, P0/Z, [X0,#-7,MUL VL]
ldnf1h {z0.s}, p0/z, [x0,#-1,mul vl]
LDNF1H {Z0.S}, P0/Z, [X0,#-1,MUL VL]
ldnf1h z0.d, p0/z, [x0,#0]
ldnf1h {z0.d}, p0/z, [x0,#0]
LDNF1H {Z0.D}, P0/Z, [X0,#0]
ldnf1h {z0.d}, p0/z, [x0,#0,mul vl]
ldnf1h {z0.d}, p0/z, [x0]
ldnf1h z1.d, p0/z, [x0,#0]
ldnf1h {z1.d}, p0/z, [x0,#0]
LDNF1H {Z1.D}, P0/Z, [X0,#0]
ldnf1h {z1.d}, p0/z, [x0,#0,mul vl]
ldnf1h {z1.d}, p0/z, [x0]
ldnf1h z31.d, p0/z, [x0,#0]
ldnf1h {z31.d}, p0/z, [x0,#0]
LDNF1H {Z31.D}, P0/Z, [X0,#0]
ldnf1h {z31.d}, p0/z, [x0,#0,mul vl]
ldnf1h {z31.d}, p0/z, [x0]
ldnf1h {z0.d}, p2/z, [x0,#0]
LDNF1H {Z0.D}, P2/Z, [X0,#0]
ldnf1h {z0.d}, p2/z, [x0,#0,mul vl]
ldnf1h {z0.d}, p2/z, [x0]
ldnf1h {z0.d}, p7/z, [x0,#0]
LDNF1H {Z0.D}, P7/Z, [X0,#0]
ldnf1h {z0.d}, p7/z, [x0,#0,mul vl]
ldnf1h {z0.d}, p7/z, [x0]
ldnf1h {z0.d}, p0/z, [x3,#0]
LDNF1H {Z0.D}, P0/Z, [X3,#0]
ldnf1h {z0.d}, p0/z, [x3,#0,mul vl]
ldnf1h {z0.d}, p0/z, [x3]
ldnf1h {z0.d}, p0/z, [sp,#0]
LDNF1H {Z0.D}, P0/Z, [SP,#0]
ldnf1h {z0.d}, p0/z, [sp,#0,mul vl]
ldnf1h {z0.d}, p0/z, [sp]
ldnf1h {z0.d}, p0/z, [x0,#7,mul vl]
LDNF1H {Z0.D}, P0/Z, [X0,#7,MUL VL]
ldnf1h {z0.d}, p0/z, [x0,#-8,mul vl]
LDNF1H {Z0.D}, P0/Z, [X0,#-8,MUL VL]
ldnf1h {z0.d}, p0/z, [x0,#-7,mul vl]
LDNF1H {Z0.D}, P0/Z, [X0,#-7,MUL VL]
ldnf1h {z0.d}, p0/z, [x0,#-1,mul vl]
LDNF1H {Z0.D}, P0/Z, [X0,#-1,MUL VL]
ldnf1sb z0.d, p0/z, [x0,#0]
ldnf1sb {z0.d}, p0/z, [x0,#0]
LDNF1SB {Z0.D}, P0/Z, [X0,#0]
ldnf1sb {z0.d}, p0/z, [x0,#0,mul vl]
ldnf1sb {z0.d}, p0/z, [x0]
ldnf1sb z1.d, p0/z, [x0,#0]
ldnf1sb {z1.d}, p0/z, [x0,#0]
LDNF1SB {Z1.D}, P0/Z, [X0,#0]
ldnf1sb {z1.d}, p0/z, [x0,#0,mul vl]
ldnf1sb {z1.d}, p0/z, [x0]
ldnf1sb z31.d, p0/z, [x0,#0]
ldnf1sb {z31.d}, p0/z, [x0,#0]
LDNF1SB {Z31.D}, P0/Z, [X0,#0]
ldnf1sb {z31.d}, p0/z, [x0,#0,mul vl]
ldnf1sb {z31.d}, p0/z, [x0]
ldnf1sb {z0.d}, p2/z, [x0,#0]
LDNF1SB {Z0.D}, P2/Z, [X0,#0]
ldnf1sb {z0.d}, p2/z, [x0,#0,mul vl]
ldnf1sb {z0.d}, p2/z, [x0]
ldnf1sb {z0.d}, p7/z, [x0,#0]
LDNF1SB {Z0.D}, P7/Z, [X0,#0]
ldnf1sb {z0.d}, p7/z, [x0,#0,mul vl]
ldnf1sb {z0.d}, p7/z, [x0]
ldnf1sb {z0.d}, p0/z, [x3,#0]
LDNF1SB {Z0.D}, P0/Z, [X3,#0]
ldnf1sb {z0.d}, p0/z, [x3,#0,mul vl]
ldnf1sb {z0.d}, p0/z, [x3]
ldnf1sb {z0.d}, p0/z, [sp,#0]
LDNF1SB {Z0.D}, P0/Z, [SP,#0]
ldnf1sb {z0.d}, p0/z, [sp,#0,mul vl]
ldnf1sb {z0.d}, p0/z, [sp]
ldnf1sb {z0.d}, p0/z, [x0,#7,mul vl]
LDNF1SB {Z0.D}, P0/Z, [X0,#7,MUL VL]
ldnf1sb {z0.d}, p0/z, [x0,#-8,mul vl]
LDNF1SB {Z0.D}, P0/Z, [X0,#-8,MUL VL]
ldnf1sb {z0.d}, p0/z, [x0,#-7,mul vl]
LDNF1SB {Z0.D}, P0/Z, [X0,#-7,MUL VL]
ldnf1sb {z0.d}, p0/z, [x0,#-1,mul vl]
LDNF1SB {Z0.D}, P0/Z, [X0,#-1,MUL VL]
ldnf1sb z0.s, p0/z, [x0,#0]
ldnf1sb {z0.s}, p0/z, [x0,#0]
LDNF1SB {Z0.S}, P0/Z, [X0,#0]
ldnf1sb {z0.s}, p0/z, [x0,#0,mul vl]
ldnf1sb {z0.s}, p0/z, [x0]
ldnf1sb z1.s, p0/z, [x0,#0]
ldnf1sb {z1.s}, p0/z, [x0,#0]
LDNF1SB {Z1.S}, P0/Z, [X0,#0]
ldnf1sb {z1.s}, p0/z, [x0,#0,mul vl]
ldnf1sb {z1.s}, p0/z, [x0]
ldnf1sb z31.s, p0/z, [x0,#0]
ldnf1sb {z31.s}, p0/z, [x0,#0]
LDNF1SB {Z31.S}, P0/Z, [X0,#0]
ldnf1sb {z31.s}, p0/z, [x0,#0,mul vl]
ldnf1sb {z31.s}, p0/z, [x0]
ldnf1sb {z0.s}, p2/z, [x0,#0]
LDNF1SB {Z0.S}, P2/Z, [X0,#0]
ldnf1sb {z0.s}, p2/z, [x0,#0,mul vl]
ldnf1sb {z0.s}, p2/z, [x0]
ldnf1sb {z0.s}, p7/z, [x0,#0]
LDNF1SB {Z0.S}, P7/Z, [X0,#0]
ldnf1sb {z0.s}, p7/z, [x0,#0,mul vl]
ldnf1sb {z0.s}, p7/z, [x0]
ldnf1sb {z0.s}, p0/z, [x3,#0]
LDNF1SB {Z0.S}, P0/Z, [X3,#0]
ldnf1sb {z0.s}, p0/z, [x3,#0,mul vl]
ldnf1sb {z0.s}, p0/z, [x3]
ldnf1sb {z0.s}, p0/z, [sp,#0]
LDNF1SB {Z0.S}, P0/Z, [SP,#0]
ldnf1sb {z0.s}, p0/z, [sp,#0,mul vl]
ldnf1sb {z0.s}, p0/z, [sp]
ldnf1sb {z0.s}, p0/z, [x0,#7,mul vl]
LDNF1SB {Z0.S}, P0/Z, [X0,#7,MUL VL]
ldnf1sb {z0.s}, p0/z, [x0,#-8,mul vl]
LDNF1SB {Z0.S}, P0/Z, [X0,#-8,MUL VL]
ldnf1sb {z0.s}, p0/z, [x0,#-7,mul vl]
LDNF1SB {Z0.S}, P0/Z, [X0,#-7,MUL VL]
ldnf1sb {z0.s}, p0/z, [x0,#-1,mul vl]
LDNF1SB {Z0.S}, P0/Z, [X0,#-1,MUL VL]
ldnf1sb z0.h, p0/z, [x0,#0]
ldnf1sb {z0.h}, p0/z, [x0,#0]
LDNF1SB {Z0.H}, P0/Z, [X0,#0]
ldnf1sb {z0.h}, p0/z, [x0,#0,mul vl]
ldnf1sb {z0.h}, p0/z, [x0]
ldnf1sb z1.h, p0/z, [x0,#0]
ldnf1sb {z1.h}, p0/z, [x0,#0]
LDNF1SB {Z1.H}, P0/Z, [X0,#0]
ldnf1sb {z1.h}, p0/z, [x0,#0,mul vl]
ldnf1sb {z1.h}, p0/z, [x0]
ldnf1sb z31.h, p0/z, [x0,#0]
ldnf1sb {z31.h}, p0/z, [x0,#0]
LDNF1SB {Z31.H}, P0/Z, [X0,#0]
ldnf1sb {z31.h}, p0/z, [x0,#0,mul vl]
ldnf1sb {z31.h}, p0/z, [x0]
ldnf1sb {z0.h}, p2/z, [x0,#0]
LDNF1SB {Z0.H}, P2/Z, [X0,#0]
ldnf1sb {z0.h}, p2/z, [x0,#0,mul vl]
ldnf1sb {z0.h}, p2/z, [x0]
ldnf1sb {z0.h}, p7/z, [x0,#0]
LDNF1SB {Z0.H}, P7/Z, [X0,#0]
ldnf1sb {z0.h}, p7/z, [x0,#0,mul vl]
ldnf1sb {z0.h}, p7/z, [x0]
ldnf1sb {z0.h}, p0/z, [x3,#0]
LDNF1SB {Z0.H}, P0/Z, [X3,#0]
ldnf1sb {z0.h}, p0/z, [x3,#0,mul vl]
ldnf1sb {z0.h}, p0/z, [x3]
ldnf1sb {z0.h}, p0/z, [sp,#0]
LDNF1SB {Z0.H}, P0/Z, [SP,#0]
ldnf1sb {z0.h}, p0/z, [sp,#0,mul vl]
ldnf1sb {z0.h}, p0/z, [sp]
ldnf1sb {z0.h}, p0/z, [x0,#7,mul vl]
LDNF1SB {Z0.H}, P0/Z, [X0,#7,MUL VL]
ldnf1sb {z0.h}, p0/z, [x0,#-8,mul vl]
LDNF1SB {Z0.H}, P0/Z, [X0,#-8,MUL VL]
ldnf1sb {z0.h}, p0/z, [x0,#-7,mul vl]
LDNF1SB {Z0.H}, P0/Z, [X0,#-7,MUL VL]
ldnf1sb {z0.h}, p0/z, [x0,#-1,mul vl]
LDNF1SB {Z0.H}, P0/Z, [X0,#-1,MUL VL]
ldnf1sh z0.d, p0/z, [x0,#0]
ldnf1sh {z0.d}, p0/z, [x0,#0]
LDNF1SH {Z0.D}, P0/Z, [X0,#0]
ldnf1sh {z0.d}, p0/z, [x0,#0,mul vl]
ldnf1sh {z0.d}, p0/z, [x0]
ldnf1sh z1.d, p0/z, [x0,#0]
ldnf1sh {z1.d}, p0/z, [x0,#0]
LDNF1SH {Z1.D}, P0/Z, [X0,#0]
ldnf1sh {z1.d}, p0/z, [x0,#0,mul vl]
ldnf1sh {z1.d}, p0/z, [x0]
ldnf1sh z31.d, p0/z, [x0,#0]
ldnf1sh {z31.d}, p0/z, [x0,#0]
LDNF1SH {Z31.D}, P0/Z, [X0,#0]
ldnf1sh {z31.d}, p0/z, [x0,#0,mul vl]
ldnf1sh {z31.d}, p0/z, [x0]
ldnf1sh {z0.d}, p2/z, [x0,#0]
LDNF1SH {Z0.D}, P2/Z, [X0,#0]
ldnf1sh {z0.d}, p2/z, [x0,#0,mul vl]
ldnf1sh {z0.d}, p2/z, [x0]
ldnf1sh {z0.d}, p7/z, [x0,#0]
LDNF1SH {Z0.D}, P7/Z, [X0,#0]
ldnf1sh {z0.d}, p7/z, [x0,#0,mul vl]
ldnf1sh {z0.d}, p7/z, [x0]
ldnf1sh {z0.d}, p0/z, [x3,#0]
LDNF1SH {Z0.D}, P0/Z, [X3,#0]
ldnf1sh {z0.d}, p0/z, [x3,#0,mul vl]
ldnf1sh {z0.d}, p0/z, [x3]
ldnf1sh {z0.d}, p0/z, [sp,#0]
LDNF1SH {Z0.D}, P0/Z, [SP,#0]
ldnf1sh {z0.d}, p0/z, [sp,#0,mul vl]
ldnf1sh {z0.d}, p0/z, [sp]
ldnf1sh {z0.d}, p0/z, [x0,#7,mul vl]
LDNF1SH {Z0.D}, P0/Z, [X0,#7,MUL VL]
ldnf1sh {z0.d}, p0/z, [x0,#-8,mul vl]
LDNF1SH {Z0.D}, P0/Z, [X0,#-8,MUL VL]
ldnf1sh {z0.d}, p0/z, [x0,#-7,mul vl]
LDNF1SH {Z0.D}, P0/Z, [X0,#-7,MUL VL]
ldnf1sh {z0.d}, p0/z, [x0,#-1,mul vl]
LDNF1SH {Z0.D}, P0/Z, [X0,#-1,MUL VL]
ldnf1sh z0.s, p0/z, [x0,#0]
ldnf1sh {z0.s}, p0/z, [x0,#0]
LDNF1SH {Z0.S}, P0/Z, [X0,#0]
ldnf1sh {z0.s}, p0/z, [x0,#0,mul vl]
ldnf1sh {z0.s}, p0/z, [x0]
ldnf1sh z1.s, p0/z, [x0,#0]
ldnf1sh {z1.s}, p0/z, [x0,#0]
LDNF1SH {Z1.S}, P0/Z, [X0,#0]
ldnf1sh {z1.s}, p0/z, [x0,#0,mul vl]
ldnf1sh {z1.s}, p0/z, [x0]
ldnf1sh z31.s, p0/z, [x0,#0]
ldnf1sh {z31.s}, p0/z, [x0,#0]
LDNF1SH {Z31.S}, P0/Z, [X0,#0]
ldnf1sh {z31.s}, p0/z, [x0,#0,mul vl]
ldnf1sh {z31.s}, p0/z, [x0]
ldnf1sh {z0.s}, p2/z, [x0,#0]
LDNF1SH {Z0.S}, P2/Z, [X0,#0]
ldnf1sh {z0.s}, p2/z, [x0,#0,mul vl]
ldnf1sh {z0.s}, p2/z, [x0]
ldnf1sh {z0.s}, p7/z, [x0,#0]
LDNF1SH {Z0.S}, P7/Z, [X0,#0]
ldnf1sh {z0.s}, p7/z, [x0,#0,mul vl]
ldnf1sh {z0.s}, p7/z, [x0]
ldnf1sh {z0.s}, p0/z, [x3,#0]
LDNF1SH {Z0.S}, P0/Z, [X3,#0]
ldnf1sh {z0.s}, p0/z, [x3,#0,mul vl]
ldnf1sh {z0.s}, p0/z, [x3]
ldnf1sh {z0.s}, p0/z, [sp,#0]
LDNF1SH {Z0.S}, P0/Z, [SP,#0]
ldnf1sh {z0.s}, p0/z, [sp,#0,mul vl]
ldnf1sh {z0.s}, p0/z, [sp]
ldnf1sh {z0.s}, p0/z, [x0,#7,mul vl]
LDNF1SH {Z0.S}, P0/Z, [X0,#7,MUL VL]
ldnf1sh {z0.s}, p0/z, [x0,#-8,mul vl]
LDNF1SH {Z0.S}, P0/Z, [X0,#-8,MUL VL]
ldnf1sh {z0.s}, p0/z, [x0,#-7,mul vl]
LDNF1SH {Z0.S}, P0/Z, [X0,#-7,MUL VL]
ldnf1sh {z0.s}, p0/z, [x0,#-1,mul vl]
LDNF1SH {Z0.S}, P0/Z, [X0,#-1,MUL VL]
ldnf1sw z0.d, p0/z, [x0,#0]
ldnf1sw {z0.d}, p0/z, [x0,#0]
LDNF1SW {Z0.D}, P0/Z, [X0,#0]
ldnf1sw {z0.d}, p0/z, [x0,#0,mul vl]
ldnf1sw {z0.d}, p0/z, [x0]
ldnf1sw z1.d, p0/z, [x0,#0]
ldnf1sw {z1.d}, p0/z, [x0,#0]
LDNF1SW {Z1.D}, P0/Z, [X0,#0]
ldnf1sw {z1.d}, p0/z, [x0,#0,mul vl]
ldnf1sw {z1.d}, p0/z, [x0]
ldnf1sw z31.d, p0/z, [x0,#0]
ldnf1sw {z31.d}, p0/z, [x0,#0]
LDNF1SW {Z31.D}, P0/Z, [X0,#0]
ldnf1sw {z31.d}, p0/z, [x0,#0,mul vl]
ldnf1sw {z31.d}, p0/z, [x0]
ldnf1sw {z0.d}, p2/z, [x0,#0]
LDNF1SW {Z0.D}, P2/Z, [X0,#0]
ldnf1sw {z0.d}, p2/z, [x0,#0,mul vl]
ldnf1sw {z0.d}, p2/z, [x0]
ldnf1sw {z0.d}, p7/z, [x0,#0]
LDNF1SW {Z0.D}, P7/Z, [X0,#0]
ldnf1sw {z0.d}, p7/z, [x0,#0,mul vl]
ldnf1sw {z0.d}, p7/z, [x0]
ldnf1sw {z0.d}, p0/z, [x3,#0]
LDNF1SW {Z0.D}, P0/Z, [X3,#0]
ldnf1sw {z0.d}, p0/z, [x3,#0,mul vl]
ldnf1sw {z0.d}, p0/z, [x3]
ldnf1sw {z0.d}, p0/z, [sp,#0]
LDNF1SW {Z0.D}, P0/Z, [SP,#0]
ldnf1sw {z0.d}, p0/z, [sp,#0,mul vl]
ldnf1sw {z0.d}, p0/z, [sp]
ldnf1sw {z0.d}, p0/z, [x0,#7,mul vl]
LDNF1SW {Z0.D}, P0/Z, [X0,#7,MUL VL]
ldnf1sw {z0.d}, p0/z, [x0,#-8,mul vl]
LDNF1SW {Z0.D}, P0/Z, [X0,#-8,MUL VL]
ldnf1sw {z0.d}, p0/z, [x0,#-7,mul vl]
LDNF1SW {Z0.D}, P0/Z, [X0,#-7,MUL VL]
ldnf1sw {z0.d}, p0/z, [x0,#-1,mul vl]
LDNF1SW {Z0.D}, P0/Z, [X0,#-1,MUL VL]
ldnf1w z0.s, p0/z, [x0,#0]
ldnf1w {z0.s}, p0/z, [x0,#0]
LDNF1W {Z0.S}, P0/Z, [X0,#0]
ldnf1w {z0.s}, p0/z, [x0,#0,mul vl]
ldnf1w {z0.s}, p0/z, [x0]
ldnf1w z1.s, p0/z, [x0,#0]
ldnf1w {z1.s}, p0/z, [x0,#0]
LDNF1W {Z1.S}, P0/Z, [X0,#0]
ldnf1w {z1.s}, p0/z, [x0,#0,mul vl]
ldnf1w {z1.s}, p0/z, [x0]
ldnf1w z31.s, p0/z, [x0,#0]
ldnf1w {z31.s}, p0/z, [x0,#0]
LDNF1W {Z31.S}, P0/Z, [X0,#0]
ldnf1w {z31.s}, p0/z, [x0,#0,mul vl]
ldnf1w {z31.s}, p0/z, [x0]
ldnf1w {z0.s}, p2/z, [x0,#0]
LDNF1W {Z0.S}, P2/Z, [X0,#0]
ldnf1w {z0.s}, p2/z, [x0,#0,mul vl]
ldnf1w {z0.s}, p2/z, [x0]
ldnf1w {z0.s}, p7/z, [x0,#0]
LDNF1W {Z0.S}, P7/Z, [X0,#0]
ldnf1w {z0.s}, p7/z, [x0,#0,mul vl]
ldnf1w {z0.s}, p7/z, [x0]
ldnf1w {z0.s}, p0/z, [x3,#0]
LDNF1W {Z0.S}, P0/Z, [X3,#0]
ldnf1w {z0.s}, p0/z, [x3,#0,mul vl]
ldnf1w {z0.s}, p0/z, [x3]
ldnf1w {z0.s}, p0/z, [sp,#0]
LDNF1W {Z0.S}, P0/Z, [SP,#0]
ldnf1w {z0.s}, p0/z, [sp,#0,mul vl]
ldnf1w {z0.s}, p0/z, [sp]
ldnf1w {z0.s}, p0/z, [x0,#7,mul vl]
LDNF1W {Z0.S}, P0/Z, [X0,#7,MUL VL]
ldnf1w {z0.s}, p0/z, [x0,#-8,mul vl]
LDNF1W {Z0.S}, P0/Z, [X0,#-8,MUL VL]
ldnf1w {z0.s}, p0/z, [x0,#-7,mul vl]
LDNF1W {Z0.S}, P0/Z, [X0,#-7,MUL VL]
ldnf1w {z0.s}, p0/z, [x0,#-1,mul vl]
LDNF1W {Z0.S}, P0/Z, [X0,#-1,MUL VL]
ldnf1w z0.d, p0/z, [x0,#0]
ldnf1w {z0.d}, p0/z, [x0,#0]
LDNF1W {Z0.D}, P0/Z, [X0,#0]
ldnf1w {z0.d}, p0/z, [x0,#0,mul vl]
ldnf1w {z0.d}, p0/z, [x0]
ldnf1w z1.d, p0/z, [x0,#0]
ldnf1w {z1.d}, p0/z, [x0,#0]
LDNF1W {Z1.D}, P0/Z, [X0,#0]
ldnf1w {z1.d}, p0/z, [x0,#0,mul vl]
ldnf1w {z1.d}, p0/z, [x0]
ldnf1w z31.d, p0/z, [x0,#0]
ldnf1w {z31.d}, p0/z, [x0,#0]
LDNF1W {Z31.D}, P0/Z, [X0,#0]
ldnf1w {z31.d}, p0/z, [x0,#0,mul vl]
ldnf1w {z31.d}, p0/z, [x0]
ldnf1w {z0.d}, p2/z, [x0,#0]
LDNF1W {Z0.D}, P2/Z, [X0,#0]
ldnf1w {z0.d}, p2/z, [x0,#0,mul vl]
ldnf1w {z0.d}, p2/z, [x0]
ldnf1w {z0.d}, p7/z, [x0,#0]
LDNF1W {Z0.D}, P7/Z, [X0,#0]
ldnf1w {z0.d}, p7/z, [x0,#0,mul vl]
ldnf1w {z0.d}, p7/z, [x0]
ldnf1w {z0.d}, p0/z, [x3,#0]
LDNF1W {Z0.D}, P0/Z, [X3,#0]
ldnf1w {z0.d}, p0/z, [x3,#0,mul vl]
ldnf1w {z0.d}, p0/z, [x3]
ldnf1w {z0.d}, p0/z, [sp,#0]
LDNF1W {Z0.D}, P0/Z, [SP,#0]
ldnf1w {z0.d}, p0/z, [sp,#0,mul vl]
ldnf1w {z0.d}, p0/z, [sp]
ldnf1w {z0.d}, p0/z, [x0,#7,mul vl]
LDNF1W {Z0.D}, P0/Z, [X0,#7,MUL VL]
ldnf1w {z0.d}, p0/z, [x0,#-8,mul vl]
LDNF1W {Z0.D}, P0/Z, [X0,#-8,MUL VL]
ldnf1w {z0.d}, p0/z, [x0,#-7,mul vl]
LDNF1W {Z0.D}, P0/Z, [X0,#-7,MUL VL]
ldnf1w {z0.d}, p0/z, [x0,#-1,mul vl]
LDNF1W {Z0.D}, P0/Z, [X0,#-1,MUL VL]
ldnt1b z0.b, p0/z, [x0,x0]
ldnt1b {z0.b}, p0/z, [x0,x0]
LDNT1B {Z0.B}, P0/Z, [X0,X0]
ldnt1b {z0.b}, p0/z, [x0,x0,lsl #0]
ldnt1b z1.b, p0/z, [x0,x0]
ldnt1b {z1.b}, p0/z, [x0,x0]
LDNT1B {Z1.B}, P0/Z, [X0,X0]
ldnt1b {z1.b}, p0/z, [x0,x0,lsl #0]
ldnt1b z31.b, p0/z, [x0,x0]
ldnt1b {z31.b}, p0/z, [x0,x0]
LDNT1B {Z31.B}, P0/Z, [X0,X0]
ldnt1b {z31.b}, p0/z, [x0,x0,lsl #0]
ldnt1b {z0.b}, p2/z, [x0,x0]
LDNT1B {Z0.B}, P2/Z, [X0,X0]
ldnt1b {z0.b}, p2/z, [x0,x0,lsl #0]
ldnt1b {z0.b}, p7/z, [x0,x0]
LDNT1B {Z0.B}, P7/Z, [X0,X0]
ldnt1b {z0.b}, p7/z, [x0,x0,lsl #0]
ldnt1b {z0.b}, p0/z, [x3,x0]
LDNT1B {Z0.B}, P0/Z, [X3,X0]
ldnt1b {z0.b}, p0/z, [x3,x0,lsl #0]
ldnt1b {z0.b}, p0/z, [sp,x0]
LDNT1B {Z0.B}, P0/Z, [SP,X0]
ldnt1b {z0.b}, p0/z, [sp,x0,lsl #0]
ldnt1b {z0.b}, p0/z, [x0,x4]
LDNT1B {Z0.B}, P0/Z, [X0,X4]
ldnt1b {z0.b}, p0/z, [x0,x4,lsl #0]
ldnt1b {z0.b}, p0/z, [x0,x30]
LDNT1B {Z0.B}, P0/Z, [X0,X30]
ldnt1b {z0.b}, p0/z, [x0,x30,lsl #0]
ldnt1b z0.b, p0/z, [x0,#0]
ldnt1b {z0.b}, p0/z, [x0,#0]
LDNT1B {Z0.B}, P0/Z, [X0,#0]
ldnt1b {z0.b}, p0/z, [x0,#0,mul vl]
ldnt1b {z0.b}, p0/z, [x0]
ldnt1b z1.b, p0/z, [x0,#0]
ldnt1b {z1.b}, p0/z, [x0,#0]
LDNT1B {Z1.B}, P0/Z, [X0,#0]
ldnt1b {z1.b}, p0/z, [x0,#0,mul vl]
ldnt1b {z1.b}, p0/z, [x0]
ldnt1b z31.b, p0/z, [x0,#0]
ldnt1b {z31.b}, p0/z, [x0,#0]
LDNT1B {Z31.B}, P0/Z, [X0,#0]
ldnt1b {z31.b}, p0/z, [x0,#0,mul vl]
ldnt1b {z31.b}, p0/z, [x0]
ldnt1b {z0.b}, p2/z, [x0,#0]
LDNT1B {Z0.B}, P2/Z, [X0,#0]
ldnt1b {z0.b}, p2/z, [x0,#0,mul vl]
ldnt1b {z0.b}, p2/z, [x0]
ldnt1b {z0.b}, p7/z, [x0,#0]
LDNT1B {Z0.B}, P7/Z, [X0,#0]
ldnt1b {z0.b}, p7/z, [x0,#0,mul vl]
ldnt1b {z0.b}, p7/z, [x0]
ldnt1b {z0.b}, p0/z, [x3,#0]
LDNT1B {Z0.B}, P0/Z, [X3,#0]
ldnt1b {z0.b}, p0/z, [x3,#0,mul vl]
ldnt1b {z0.b}, p0/z, [x3]
ldnt1b {z0.b}, p0/z, [sp,#0]
LDNT1B {Z0.B}, P0/Z, [SP,#0]
ldnt1b {z0.b}, p0/z, [sp,#0,mul vl]
ldnt1b {z0.b}, p0/z, [sp]
ldnt1b {z0.b}, p0/z, [x0,#7,mul vl]
LDNT1B {Z0.B}, P0/Z, [X0,#7,MUL VL]
ldnt1b {z0.b}, p0/z, [x0,#-8,mul vl]
LDNT1B {Z0.B}, P0/Z, [X0,#-8,MUL VL]
ldnt1b {z0.b}, p0/z, [x0,#-7,mul vl]
LDNT1B {Z0.B}, P0/Z, [X0,#-7,MUL VL]
ldnt1b {z0.b}, p0/z, [x0,#-1,mul vl]
LDNT1B {Z0.B}, P0/Z, [X0,#-1,MUL VL]
ldnt1d z0.d, p0/z, [x0,x0,lsl #3]
ldnt1d {z0.d}, p0/z, [x0,x0,lsl #3]
LDNT1D {Z0.D}, P0/Z, [X0,X0,LSL #3]
ldnt1d z1.d, p0/z, [x0,x0,lsl #3]
ldnt1d {z1.d}, p0/z, [x0,x0,lsl #3]
LDNT1D {Z1.D}, P0/Z, [X0,X0,LSL #3]
ldnt1d z31.d, p0/z, [x0,x0,lsl #3]
ldnt1d {z31.d}, p0/z, [x0,x0,lsl #3]
LDNT1D {Z31.D}, P0/Z, [X0,X0,LSL #3]
ldnt1d {z0.d}, p2/z, [x0,x0,lsl #3]
LDNT1D {Z0.D}, P2/Z, [X0,X0,LSL #3]
ldnt1d {z0.d}, p7/z, [x0,x0,lsl #3]
LDNT1D {Z0.D}, P7/Z, [X0,X0,LSL #3]
ldnt1d {z0.d}, p0/z, [x3,x0,lsl #3]
LDNT1D {Z0.D}, P0/Z, [X3,X0,LSL #3]
ldnt1d {z0.d}, p0/z, [sp,x0,lsl #3]
LDNT1D {Z0.D}, P0/Z, [SP,X0,LSL #3]
ldnt1d {z0.d}, p0/z, [x0,x4,lsl #3]
LDNT1D {Z0.D}, P0/Z, [X0,X4,LSL #3]
ldnt1d {z0.d}, p0/z, [x0,x30,lsl #3]
LDNT1D {Z0.D}, P0/Z, [X0,X30,LSL #3]
ldnt1d z0.d, p0/z, [x0,#0]
ldnt1d {z0.d}, p0/z, [x0,#0]
LDNT1D {Z0.D}, P0/Z, [X0,#0]
ldnt1d {z0.d}, p0/z, [x0,#0,mul vl]
ldnt1d {z0.d}, p0/z, [x0]
ldnt1d z1.d, p0/z, [x0,#0]
ldnt1d {z1.d}, p0/z, [x0,#0]
LDNT1D {Z1.D}, P0/Z, [X0,#0]
ldnt1d {z1.d}, p0/z, [x0,#0,mul vl]
ldnt1d {z1.d}, p0/z, [x0]
ldnt1d z31.d, p0/z, [x0,#0]
ldnt1d {z31.d}, p0/z, [x0,#0]
LDNT1D {Z31.D}, P0/Z, [X0,#0]
ldnt1d {z31.d}, p0/z, [x0,#0,mul vl]
ldnt1d {z31.d}, p0/z, [x0]
ldnt1d {z0.d}, p2/z, [x0,#0]
LDNT1D {Z0.D}, P2/Z, [X0,#0]
ldnt1d {z0.d}, p2/z, [x0,#0,mul vl]
ldnt1d {z0.d}, p2/z, [x0]
ldnt1d {z0.d}, p7/z, [x0,#0]
LDNT1D {Z0.D}, P7/Z, [X0,#0]
ldnt1d {z0.d}, p7/z, [x0,#0,mul vl]
ldnt1d {z0.d}, p7/z, [x0]
ldnt1d {z0.d}, p0/z, [x3,#0]
LDNT1D {Z0.D}, P0/Z, [X3,#0]
ldnt1d {z0.d}, p0/z, [x3,#0,mul vl]
ldnt1d {z0.d}, p0/z, [x3]
ldnt1d {z0.d}, p0/z, [sp,#0]
LDNT1D {Z0.D}, P0/Z, [SP,#0]
ldnt1d {z0.d}, p0/z, [sp,#0,mul vl]
ldnt1d {z0.d}, p0/z, [sp]
ldnt1d {z0.d}, p0/z, [x0,#7,mul vl]
LDNT1D {Z0.D}, P0/Z, [X0,#7,MUL VL]
ldnt1d {z0.d}, p0/z, [x0,#-8,mul vl]
LDNT1D {Z0.D}, P0/Z, [X0,#-8,MUL VL]
ldnt1d {z0.d}, p0/z, [x0,#-7,mul vl]
LDNT1D {Z0.D}, P0/Z, [X0,#-7,MUL VL]
ldnt1d {z0.d}, p0/z, [x0,#-1,mul vl]
LDNT1D {Z0.D}, P0/Z, [X0,#-1,MUL VL]
ldnt1h z0.h, p0/z, [x0,x0,lsl #1]
ldnt1h {z0.h}, p0/z, [x0,x0,lsl #1]
LDNT1H {Z0.H}, P0/Z, [X0,X0,LSL #1]
ldnt1h z1.h, p0/z, [x0,x0,lsl #1]
ldnt1h {z1.h}, p0/z, [x0,x0,lsl #1]
LDNT1H {Z1.H}, P0/Z, [X0,X0,LSL #1]
ldnt1h z31.h, p0/z, [x0,x0,lsl #1]
ldnt1h {z31.h}, p0/z, [x0,x0,lsl #1]
LDNT1H {Z31.H}, P0/Z, [X0,X0,LSL #1]
ldnt1h {z0.h}, p2/z, [x0,x0,lsl #1]
LDNT1H {Z0.H}, P2/Z, [X0,X0,LSL #1]
ldnt1h {z0.h}, p7/z, [x0,x0,lsl #1]
LDNT1H {Z0.H}, P7/Z, [X0,X0,LSL #1]
ldnt1h {z0.h}, p0/z, [x3,x0,lsl #1]
LDNT1H {Z0.H}, P0/Z, [X3,X0,LSL #1]
ldnt1h {z0.h}, p0/z, [sp,x0,lsl #1]
LDNT1H {Z0.H}, P0/Z, [SP,X0,LSL #1]
ldnt1h {z0.h}, p0/z, [x0,x4,lsl #1]
LDNT1H {Z0.H}, P0/Z, [X0,X4,LSL #1]
ldnt1h {z0.h}, p0/z, [x0,x30,lsl #1]
LDNT1H {Z0.H}, P0/Z, [X0,X30,LSL #1]
ldnt1h z0.h, p0/z, [x0,#0]
ldnt1h {z0.h}, p0/z, [x0,#0]
LDNT1H {Z0.H}, P0/Z, [X0,#0]
ldnt1h {z0.h}, p0/z, [x0,#0,mul vl]
ldnt1h {z0.h}, p0/z, [x0]
ldnt1h z1.h, p0/z, [x0,#0]
ldnt1h {z1.h}, p0/z, [x0,#0]
LDNT1H {Z1.H}, P0/Z, [X0,#0]
ldnt1h {z1.h}, p0/z, [x0,#0,mul vl]
ldnt1h {z1.h}, p0/z, [x0]
ldnt1h z31.h, p0/z, [x0,#0]
ldnt1h {z31.h}, p0/z, [x0,#0]
LDNT1H {Z31.H}, P0/Z, [X0,#0]
ldnt1h {z31.h}, p0/z, [x0,#0,mul vl]
ldnt1h {z31.h}, p0/z, [x0]
ldnt1h {z0.h}, p2/z, [x0,#0]
LDNT1H {Z0.H}, P2/Z, [X0,#0]
ldnt1h {z0.h}, p2/z, [x0,#0,mul vl]
ldnt1h {z0.h}, p2/z, [x0]
ldnt1h {z0.h}, p7/z, [x0,#0]
LDNT1H {Z0.H}, P7/Z, [X0,#0]
ldnt1h {z0.h}, p7/z, [x0,#0,mul vl]
ldnt1h {z0.h}, p7/z, [x0]
ldnt1h {z0.h}, p0/z, [x3,#0]
LDNT1H {Z0.H}, P0/Z, [X3,#0]
ldnt1h {z0.h}, p0/z, [x3,#0,mul vl]
ldnt1h {z0.h}, p0/z, [x3]
ldnt1h {z0.h}, p0/z, [sp,#0]
LDNT1H {Z0.H}, P0/Z, [SP,#0]
ldnt1h {z0.h}, p0/z, [sp,#0,mul vl]
ldnt1h {z0.h}, p0/z, [sp]
ldnt1h {z0.h}, p0/z, [x0,#7,mul vl]
LDNT1H {Z0.H}, P0/Z, [X0,#7,MUL VL]
ldnt1h {z0.h}, p0/z, [x0,#-8,mul vl]
LDNT1H {Z0.H}, P0/Z, [X0,#-8,MUL VL]
ldnt1h {z0.h}, p0/z, [x0,#-7,mul vl]
LDNT1H {Z0.H}, P0/Z, [X0,#-7,MUL VL]
ldnt1h {z0.h}, p0/z, [x0,#-1,mul vl]
LDNT1H {Z0.H}, P0/Z, [X0,#-1,MUL VL]
ldnt1w z0.s, p0/z, [x0,x0,lsl #2]
ldnt1w {z0.s}, p0/z, [x0,x0,lsl #2]
LDNT1W {Z0.S}, P0/Z, [X0,X0,LSL #2]
ldnt1w z1.s, p0/z, [x0,x0,lsl #2]
ldnt1w {z1.s}, p0/z, [x0,x0,lsl #2]
LDNT1W {Z1.S}, P0/Z, [X0,X0,LSL #2]
ldnt1w z31.s, p0/z, [x0,x0,lsl #2]
ldnt1w {z31.s}, p0/z, [x0,x0,lsl #2]
LDNT1W {Z31.S}, P0/Z, [X0,X0,LSL #2]
ldnt1w {z0.s}, p2/z, [x0,x0,lsl #2]
LDNT1W {Z0.S}, P2/Z, [X0,X0,LSL #2]
ldnt1w {z0.s}, p7/z, [x0,x0,lsl #2]
LDNT1W {Z0.S}, P7/Z, [X0,X0,LSL #2]
ldnt1w {z0.s}, p0/z, [x3,x0,lsl #2]
LDNT1W {Z0.S}, P0/Z, [X3,X0,LSL #2]
ldnt1w {z0.s}, p0/z, [sp,x0,lsl #2]
LDNT1W {Z0.S}, P0/Z, [SP,X0,LSL #2]
ldnt1w {z0.s}, p0/z, [x0,x4,lsl #2]
LDNT1W {Z0.S}, P0/Z, [X0,X4,LSL #2]
ldnt1w {z0.s}, p0/z, [x0,x30,lsl #2]
LDNT1W {Z0.S}, P0/Z, [X0,X30,LSL #2]
ldnt1w z0.s, p0/z, [x0,#0]
ldnt1w {z0.s}, p0/z, [x0,#0]
LDNT1W {Z0.S}, P0/Z, [X0,#0]
ldnt1w {z0.s}, p0/z, [x0,#0,mul vl]
ldnt1w {z0.s}, p0/z, [x0]
ldnt1w z1.s, p0/z, [x0,#0]
ldnt1w {z1.s}, p0/z, [x0,#0]
LDNT1W {Z1.S}, P0/Z, [X0,#0]
ldnt1w {z1.s}, p0/z, [x0,#0,mul vl]
ldnt1w {z1.s}, p0/z, [x0]
ldnt1w z31.s, p0/z, [x0,#0]
ldnt1w {z31.s}, p0/z, [x0,#0]
LDNT1W {Z31.S}, P0/Z, [X0,#0]
ldnt1w {z31.s}, p0/z, [x0,#0,mul vl]
ldnt1w {z31.s}, p0/z, [x0]
ldnt1w {z0.s}, p2/z, [x0,#0]
LDNT1W {Z0.S}, P2/Z, [X0,#0]
ldnt1w {z0.s}, p2/z, [x0,#0,mul vl]
ldnt1w {z0.s}, p2/z, [x0]
ldnt1w {z0.s}, p7/z, [x0,#0]
LDNT1W {Z0.S}, P7/Z, [X0,#0]
ldnt1w {z0.s}, p7/z, [x0,#0,mul vl]
ldnt1w {z0.s}, p7/z, [x0]
ldnt1w {z0.s}, p0/z, [x3,#0]
LDNT1W {Z0.S}, P0/Z, [X3,#0]
ldnt1w {z0.s}, p0/z, [x3,#0,mul vl]
ldnt1w {z0.s}, p0/z, [x3]
ldnt1w {z0.s}, p0/z, [sp,#0]
LDNT1W {Z0.S}, P0/Z, [SP,#0]
ldnt1w {z0.s}, p0/z, [sp,#0,mul vl]
ldnt1w {z0.s}, p0/z, [sp]
ldnt1w {z0.s}, p0/z, [x0,#7,mul vl]
LDNT1W {Z0.S}, P0/Z, [X0,#7,MUL VL]
ldnt1w {z0.s}, p0/z, [x0,#-8,mul vl]
LDNT1W {Z0.S}, P0/Z, [X0,#-8,MUL VL]
ldnt1w {z0.s}, p0/z, [x0,#-7,mul vl]
LDNT1W {Z0.S}, P0/Z, [X0,#-7,MUL VL]
ldnt1w {z0.s}, p0/z, [x0,#-1,mul vl]
LDNT1W {Z0.S}, P0/Z, [X0,#-1,MUL VL]
ldr p0, [x0,#0]
LDR P0, [X0,#0]
ldr p0, [x0,#0,mul vl]
ldr p0, [x0]
ldr p1, [x0,#0]
LDR P1, [X0,#0]
ldr p1, [x0,#0,mul vl]
ldr p1, [x0]
ldr p15, [x0,#0]
LDR P15, [X0,#0]
ldr p15, [x0,#0,mul vl]
ldr p15, [x0]
ldr p0, [x2,#0]
LDR P0, [X2,#0]
ldr p0, [x2,#0,mul vl]
ldr p0, [x2]
ldr p0, [sp,#0]
LDR P0, [SP,#0]
ldr p0, [sp,#0,mul vl]
ldr p0, [sp]
ldr p0, [x0,#255,mul vl]
LDR P0, [X0,#255,MUL VL]
ldr p0, [x0,#-256,mul vl]
LDR P0, [X0,#-256,MUL VL]
ldr p0, [x0,#-255,mul vl]
LDR P0, [X0,#-255,MUL VL]
ldr p0, [x0,#-1,mul vl]
LDR P0, [X0,#-1,MUL VL]
ldr z0, [x0,#0]
LDR Z0, [X0,#0]
ldr z0, [x0,#0,mul vl]
ldr z0, [x0]
ldr z1, [x0,#0]
LDR Z1, [X0,#0]
ldr z1, [x0,#0,mul vl]
ldr z1, [x0]
ldr z31, [x0,#0]
LDR Z31, [X0,#0]
ldr z31, [x0,#0,mul vl]
ldr z31, [x0]
ldr z0, [x2,#0]
LDR Z0, [X2,#0]
ldr z0, [x2,#0,mul vl]
ldr z0, [x2]
ldr z0, [sp,#0]
LDR Z0, [SP,#0]
ldr z0, [sp,#0,mul vl]
ldr z0, [sp]
ldr z0, [x0,#255,mul vl]
LDR Z0, [X0,#255,MUL VL]
ldr z0, [x0,#-256,mul vl]
LDR Z0, [X0,#-256,MUL VL]
ldr z0, [x0,#-255,mul vl]
LDR Z0, [X0,#-255,MUL VL]
ldr z0, [x0,#-1,mul vl]
LDR Z0, [X0,#-1,MUL VL]
lsl z0.b, z0.b, z0.d
LSL Z0.B, Z0.B, Z0.D
lsl z1.b, z0.b, z0.d
LSL Z1.B, Z0.B, Z0.D
lsl z31.b, z0.b, z0.d
LSL Z31.B, Z0.B, Z0.D
lsl z0.b, z2.b, z0.d
LSL Z0.B, Z2.B, Z0.D
lsl z0.b, z31.b, z0.d
LSL Z0.B, Z31.B, Z0.D
lsl z0.b, z0.b, z3.d
LSL Z0.B, Z0.B, Z3.D
lsl z0.b, z0.b, z31.d
LSL Z0.B, Z0.B, Z31.D
lsl z0.h, z0.h, z0.d
LSL Z0.H, Z0.H, Z0.D
lsl z1.h, z0.h, z0.d
LSL Z1.H, Z0.H, Z0.D
lsl z31.h, z0.h, z0.d
LSL Z31.H, Z0.H, Z0.D
lsl z0.h, z2.h, z0.d
LSL Z0.H, Z2.H, Z0.D
lsl z0.h, z31.h, z0.d
LSL Z0.H, Z31.H, Z0.D
lsl z0.h, z0.h, z3.d
LSL Z0.H, Z0.H, Z3.D
lsl z0.h, z0.h, z31.d
LSL Z0.H, Z0.H, Z31.D
lsl z0.s, z0.s, z0.d
LSL Z0.S, Z0.S, Z0.D
lsl z1.s, z0.s, z0.d
LSL Z1.S, Z0.S, Z0.D
lsl z31.s, z0.s, z0.d
LSL Z31.S, Z0.S, Z0.D
lsl z0.s, z2.s, z0.d
LSL Z0.S, Z2.S, Z0.D
lsl z0.s, z31.s, z0.d
LSL Z0.S, Z31.S, Z0.D
lsl z0.s, z0.s, z3.d
LSL Z0.S, Z0.S, Z3.D
lsl z0.s, z0.s, z31.d
LSL Z0.S, Z0.S, Z31.D
lsl z0.b, z0.b, #0
LSL Z0.B, Z0.B, #0
lsl z1.b, z0.b, #0
LSL Z1.B, Z0.B, #0
lsl z31.b, z0.b, #0
LSL Z31.B, Z0.B, #0
lsl z0.b, z2.b, #0
LSL Z0.B, Z2.B, #0
lsl z0.b, z31.b, #0
LSL Z0.B, Z31.B, #0
lsl z0.b, z0.b, #1
LSL Z0.B, Z0.B, #1
lsl z0.b, z0.b, #6
LSL Z0.B, Z0.B, #6
lsl z0.b, z0.b, #7
LSL Z0.B, Z0.B, #7
lsl z0.h, z0.h, #0
LSL Z0.H, Z0.H, #0
lsl z1.h, z0.h, #0
LSL Z1.H, Z0.H, #0
lsl z31.h, z0.h, #0
LSL Z31.H, Z0.H, #0
lsl z0.h, z2.h, #0
LSL Z0.H, Z2.H, #0
lsl z0.h, z31.h, #0
LSL Z0.H, Z31.H, #0
lsl z0.h, z0.h, #1
LSL Z0.H, Z0.H, #1
lsl z0.h, z0.h, #14
LSL Z0.H, Z0.H, #14
lsl z0.h, z0.h, #15
LSL Z0.H, Z0.H, #15
lsl z0.h, z0.h, #8
LSL Z0.H, Z0.H, #8
lsl z1.h, z0.h, #8
LSL Z1.H, Z0.H, #8
lsl z31.h, z0.h, #8
LSL Z31.H, Z0.H, #8
lsl z0.h, z2.h, #8
LSL Z0.H, Z2.H, #8
lsl z0.h, z31.h, #8
LSL Z0.H, Z31.H, #8
lsl z0.h, z0.h, #9
LSL Z0.H, Z0.H, #9
lsl z0.s, z0.s, #14
LSL Z0.S, Z0.S, #14
lsl z0.s, z0.s, #15
LSL Z0.S, Z0.S, #15
lsl z0.s, z0.s, #0
LSL Z0.S, Z0.S, #0
lsl z1.s, z0.s, #0
LSL Z1.S, Z0.S, #0
lsl z31.s, z0.s, #0
LSL Z31.S, Z0.S, #0
lsl z0.s, z2.s, #0
LSL Z0.S, Z2.S, #0
lsl z0.s, z31.s, #0
LSL Z0.S, Z31.S, #0
lsl z0.s, z0.s, #1
LSL Z0.S, Z0.S, #1
lsl z0.s, z0.s, #30
LSL Z0.S, Z0.S, #30
lsl z0.s, z0.s, #31
LSL Z0.S, Z0.S, #31
lsl z0.s, z0.s, #8
LSL Z0.S, Z0.S, #8
lsl z1.s, z0.s, #8
LSL Z1.S, Z0.S, #8
lsl z31.s, z0.s, #8
LSL Z31.S, Z0.S, #8
lsl z0.s, z2.s, #8
LSL Z0.S, Z2.S, #8
lsl z0.s, z31.s, #8
LSL Z0.S, Z31.S, #8
lsl z0.s, z0.s, #9
LSL Z0.S, Z0.S, #9
lsl z0.d, z0.d, #14
LSL Z0.D, Z0.D, #14
lsl z0.d, z0.d, #15
LSL Z0.D, Z0.D, #15
lsl z0.s, z0.s, #16
LSL Z0.S, Z0.S, #16
lsl z1.s, z0.s, #16
LSL Z1.S, Z0.S, #16
lsl z31.s, z0.s, #16
LSL Z31.S, Z0.S, #16
lsl z0.s, z2.s, #16
LSL Z0.S, Z2.S, #16
lsl z0.s, z31.s, #16
LSL Z0.S, Z31.S, #16
lsl z0.s, z0.s, #17
LSL Z0.S, Z0.S, #17
lsl z0.d, z0.d, #30
LSL Z0.D, Z0.D, #30
lsl z0.d, z0.d, #31
LSL Z0.D, Z0.D, #31
lsl z0.s, z0.s, #24
LSL Z0.S, Z0.S, #24
lsl z1.s, z0.s, #24
LSL Z1.S, Z0.S, #24
lsl z31.s, z0.s, #24
LSL Z31.S, Z0.S, #24
lsl z0.s, z2.s, #24
LSL Z0.S, Z2.S, #24
lsl z0.s, z31.s, #24
LSL Z0.S, Z31.S, #24
lsl z0.s, z0.s, #25
LSL Z0.S, Z0.S, #25
lsl z0.d, z0.d, #46
LSL Z0.D, Z0.D, #46
lsl z0.d, z0.d, #47
LSL Z0.D, Z0.D, #47
lsl z0.d, z0.d, #0
LSL Z0.D, Z0.D, #0
lsl z1.d, z0.d, #0
LSL Z1.D, Z0.D, #0
lsl z31.d, z0.d, #0
LSL Z31.D, Z0.D, #0
lsl z0.d, z2.d, #0
LSL Z0.D, Z2.D, #0
lsl z0.d, z31.d, #0
LSL Z0.D, Z31.D, #0
lsl z0.d, z0.d, #1
LSL Z0.D, Z0.D, #1
lsl z0.d, z0.d, #62
LSL Z0.D, Z0.D, #62
lsl z0.d, z0.d, #63
LSL Z0.D, Z0.D, #63
lsl z0.d, z0.d, #8
LSL Z0.D, Z0.D, #8
lsl z1.d, z0.d, #8
LSL Z1.D, Z0.D, #8
lsl z31.d, z0.d, #8
LSL Z31.D, Z0.D, #8
lsl z0.d, z2.d, #8
LSL Z0.D, Z2.D, #8
lsl z0.d, z31.d, #8
LSL Z0.D, Z31.D, #8
lsl z0.d, z0.d, #9
LSL Z0.D, Z0.D, #9
lsl z0.d, z0.d, #16
LSL Z0.D, Z0.D, #16
lsl z1.d, z0.d, #16
LSL Z1.D, Z0.D, #16
lsl z31.d, z0.d, #16
LSL Z31.D, Z0.D, #16
lsl z0.d, z2.d, #16
LSL Z0.D, Z2.D, #16
lsl z0.d, z31.d, #16
LSL Z0.D, Z31.D, #16
lsl z0.d, z0.d, #17
LSL Z0.D, Z0.D, #17
lsl z0.d, z0.d, #24
LSL Z0.D, Z0.D, #24
lsl z1.d, z0.d, #24
LSL Z1.D, Z0.D, #24
lsl z31.d, z0.d, #24
LSL Z31.D, Z0.D, #24
lsl z0.d, z2.d, #24
LSL Z0.D, Z2.D, #24
lsl z0.d, z31.d, #24
LSL Z0.D, Z31.D, #24
lsl z0.d, z0.d, #25
LSL Z0.D, Z0.D, #25
lsl z0.d, z0.d, #32
LSL Z0.D, Z0.D, #32
lsl z1.d, z0.d, #32
LSL Z1.D, Z0.D, #32
lsl z31.d, z0.d, #32
LSL Z31.D, Z0.D, #32
lsl z0.d, z2.d, #32
LSL Z0.D, Z2.D, #32
lsl z0.d, z31.d, #32
LSL Z0.D, Z31.D, #32
lsl z0.d, z0.d, #33
LSL Z0.D, Z0.D, #33
lsl z0.d, z0.d, #40
LSL Z0.D, Z0.D, #40
lsl z1.d, z0.d, #40
LSL Z1.D, Z0.D, #40
lsl z31.d, z0.d, #40
LSL Z31.D, Z0.D, #40
lsl z0.d, z2.d, #40
LSL Z0.D, Z2.D, #40
lsl z0.d, z31.d, #40
LSL Z0.D, Z31.D, #40
lsl z0.d, z0.d, #41
LSL Z0.D, Z0.D, #41
lsl z0.d, z0.d, #48
LSL Z0.D, Z0.D, #48
lsl z1.d, z0.d, #48
LSL Z1.D, Z0.D, #48
lsl z31.d, z0.d, #48
LSL Z31.D, Z0.D, #48
lsl z0.d, z2.d, #48
LSL Z0.D, Z2.D, #48
lsl z0.d, z31.d, #48
LSL Z0.D, Z31.D, #48
lsl z0.d, z0.d, #49
LSL Z0.D, Z0.D, #49
lsl z0.d, z0.d, #56
LSL Z0.D, Z0.D, #56
lsl z1.d, z0.d, #56
LSL Z1.D, Z0.D, #56
lsl z31.d, z0.d, #56
LSL Z31.D, Z0.D, #56
lsl z0.d, z2.d, #56
LSL Z0.D, Z2.D, #56
lsl z0.d, z31.d, #56
LSL Z0.D, Z31.D, #56
lsl z0.d, z0.d, #57
LSL Z0.D, Z0.D, #57
lsl z0.b, p0/m, z0.b, z0.b
LSL Z0.B, P0/M, Z0.B, Z0.B
lsl z1.b, p0/m, z1.b, z0.b
LSL Z1.B, P0/M, Z1.B, Z0.B
lsl z31.b, p0/m, z31.b, z0.b
LSL Z31.B, P0/M, Z31.B, Z0.B
lsl z0.b, p2/m, z0.b, z0.b
LSL Z0.B, P2/M, Z0.B, Z0.B
lsl z0.b, p7/m, z0.b, z0.b
LSL Z0.B, P7/M, Z0.B, Z0.B
lsl z3.b, p0/m, z3.b, z0.b
LSL Z3.B, P0/M, Z3.B, Z0.B
lsl z0.b, p0/m, z0.b, z4.b
LSL Z0.B, P0/M, Z0.B, Z4.B
lsl z0.b, p0/m, z0.b, z31.b
LSL Z0.B, P0/M, Z0.B, Z31.B
lsl z0.h, p0/m, z0.h, z0.h
LSL Z0.H, P0/M, Z0.H, Z0.H
lsl z1.h, p0/m, z1.h, z0.h
LSL Z1.H, P0/M, Z1.H, Z0.H
lsl z31.h, p0/m, z31.h, z0.h
LSL Z31.H, P0/M, Z31.H, Z0.H
lsl z0.h, p2/m, z0.h, z0.h
LSL Z0.H, P2/M, Z0.H, Z0.H
lsl z0.h, p7/m, z0.h, z0.h
LSL Z0.H, P7/M, Z0.H, Z0.H
lsl z3.h, p0/m, z3.h, z0.h
LSL Z3.H, P0/M, Z3.H, Z0.H
lsl z0.h, p0/m, z0.h, z4.h
LSL Z0.H, P0/M, Z0.H, Z4.H
lsl z0.h, p0/m, z0.h, z31.h
LSL Z0.H, P0/M, Z0.H, Z31.H
lsl z0.s, p0/m, z0.s, z0.s
LSL Z0.S, P0/M, Z0.S, Z0.S
lsl z1.s, p0/m, z1.s, z0.s
LSL Z1.S, P0/M, Z1.S, Z0.S
lsl z31.s, p0/m, z31.s, z0.s
LSL Z31.S, P0/M, Z31.S, Z0.S
lsl z0.s, p2/m, z0.s, z0.s
LSL Z0.S, P2/M, Z0.S, Z0.S
lsl z0.s, p7/m, z0.s, z0.s
LSL Z0.S, P7/M, Z0.S, Z0.S
lsl z3.s, p0/m, z3.s, z0.s
LSL Z3.S, P0/M, Z3.S, Z0.S
lsl z0.s, p0/m, z0.s, z4.s
LSL Z0.S, P0/M, Z0.S, Z4.S
lsl z0.s, p0/m, z0.s, z31.s
LSL Z0.S, P0/M, Z0.S, Z31.S
lsl z0.d, p0/m, z0.d, z0.d
LSL Z0.D, P0/M, Z0.D, Z0.D
lsl z1.d, p0/m, z1.d, z0.d
LSL Z1.D, P0/M, Z1.D, Z0.D
lsl z31.d, p0/m, z31.d, z0.d
LSL Z31.D, P0/M, Z31.D, Z0.D
lsl z0.d, p2/m, z0.d, z0.d
LSL Z0.D, P2/M, Z0.D, Z0.D
lsl z0.d, p7/m, z0.d, z0.d
LSL Z0.D, P7/M, Z0.D, Z0.D
lsl z3.d, p0/m, z3.d, z0.d
LSL Z3.D, P0/M, Z3.D, Z0.D
lsl z0.d, p0/m, z0.d, z4.d
LSL Z0.D, P0/M, Z0.D, Z4.D
lsl z0.d, p0/m, z0.d, z31.d
LSL Z0.D, P0/M, Z0.D, Z31.D
lsl z0.b, p0/m, z0.b, z0.d
LSL Z0.B, P0/M, Z0.B, Z0.D
lsl z1.b, p0/m, z1.b, z0.d
LSL Z1.B, P0/M, Z1.B, Z0.D
lsl z31.b, p0/m, z31.b, z0.d
LSL Z31.B, P0/M, Z31.B, Z0.D
lsl z0.b, p2/m, z0.b, z0.d
LSL Z0.B, P2/M, Z0.B, Z0.D
lsl z0.b, p7/m, z0.b, z0.d
LSL Z0.B, P7/M, Z0.B, Z0.D
lsl z3.b, p0/m, z3.b, z0.d
LSL Z3.B, P0/M, Z3.B, Z0.D
lsl z0.b, p0/m, z0.b, z4.d
LSL Z0.B, P0/M, Z0.B, Z4.D
lsl z0.b, p0/m, z0.b, z31.d
LSL Z0.B, P0/M, Z0.B, Z31.D
lsl z0.h, p0/m, z0.h, z0.d
LSL Z0.H, P0/M, Z0.H, Z0.D
lsl z1.h, p0/m, z1.h, z0.d
LSL Z1.H, P0/M, Z1.H, Z0.D
lsl z31.h, p0/m, z31.h, z0.d
LSL Z31.H, P0/M, Z31.H, Z0.D
lsl z0.h, p2/m, z0.h, z0.d
LSL Z0.H, P2/M, Z0.H, Z0.D
lsl z0.h, p7/m, z0.h, z0.d
LSL Z0.H, P7/M, Z0.H, Z0.D
lsl z3.h, p0/m, z3.h, z0.d
LSL Z3.H, P0/M, Z3.H, Z0.D
lsl z0.h, p0/m, z0.h, z4.d
LSL Z0.H, P0/M, Z0.H, Z4.D
lsl z0.h, p0/m, z0.h, z31.d
LSL Z0.H, P0/M, Z0.H, Z31.D
lsl z0.s, p0/m, z0.s, z0.d
LSL Z0.S, P0/M, Z0.S, Z0.D
lsl z1.s, p0/m, z1.s, z0.d
LSL Z1.S, P0/M, Z1.S, Z0.D
lsl z31.s, p0/m, z31.s, z0.d
LSL Z31.S, P0/M, Z31.S, Z0.D
lsl z0.s, p2/m, z0.s, z0.d
LSL Z0.S, P2/M, Z0.S, Z0.D
lsl z0.s, p7/m, z0.s, z0.d
LSL Z0.S, P7/M, Z0.S, Z0.D
lsl z3.s, p0/m, z3.s, z0.d
LSL Z3.S, P0/M, Z3.S, Z0.D
lsl z0.s, p0/m, z0.s, z4.d
LSL Z0.S, P0/M, Z0.S, Z4.D
lsl z0.s, p0/m, z0.s, z31.d
LSL Z0.S, P0/M, Z0.S, Z31.D
lsl z0.b, p0/m, z0.b, #0
LSL Z0.B, P0/M, Z0.B, #0
lsl z1.b, p0/m, z1.b, #0
LSL Z1.B, P0/M, Z1.B, #0
lsl z31.b, p0/m, z31.b, #0
LSL Z31.B, P0/M, Z31.B, #0
lsl z0.b, p2/m, z0.b, #0
LSL Z0.B, P2/M, Z0.B, #0
lsl z0.b, p7/m, z0.b, #0
LSL Z0.B, P7/M, Z0.B, #0
lsl z3.b, p0/m, z3.b, #0
LSL Z3.B, P0/M, Z3.B, #0
lsl z0.b, p0/m, z0.b, #1
LSL Z0.B, P0/M, Z0.B, #1
lsl z0.b, p0/m, z0.b, #6
LSL Z0.B, P0/M, Z0.B, #6
lsl z0.b, p0/m, z0.b, #7
LSL Z0.B, P0/M, Z0.B, #7
lsl z0.h, p0/m, z0.h, #0
LSL Z0.H, P0/M, Z0.H, #0
lsl z1.h, p0/m, z1.h, #0
LSL Z1.H, P0/M, Z1.H, #0
lsl z31.h, p0/m, z31.h, #0
LSL Z31.H, P0/M, Z31.H, #0
lsl z0.h, p2/m, z0.h, #0
LSL Z0.H, P2/M, Z0.H, #0
lsl z0.h, p7/m, z0.h, #0
LSL Z0.H, P7/M, Z0.H, #0
lsl z3.h, p0/m, z3.h, #0
LSL Z3.H, P0/M, Z3.H, #0
lsl z0.h, p0/m, z0.h, #1
LSL Z0.H, P0/M, Z0.H, #1
lsl z0.h, p0/m, z0.h, #14
LSL Z0.H, P0/M, Z0.H, #14
lsl z0.h, p0/m, z0.h, #15
LSL Z0.H, P0/M, Z0.H, #15
lsl z0.h, p0/m, z0.h, #8
LSL Z0.H, P0/M, Z0.H, #8
lsl z1.h, p0/m, z1.h, #8
LSL Z1.H, P0/M, Z1.H, #8
lsl z31.h, p0/m, z31.h, #8
LSL Z31.H, P0/M, Z31.H, #8
lsl z0.h, p2/m, z0.h, #8
LSL Z0.H, P2/M, Z0.H, #8
lsl z0.h, p7/m, z0.h, #8
LSL Z0.H, P7/M, Z0.H, #8
lsl z3.h, p0/m, z3.h, #8
LSL Z3.H, P0/M, Z3.H, #8
lsl z0.h, p0/m, z0.h, #9
LSL Z0.H, P0/M, Z0.H, #9
lsl z0.s, p0/m, z0.s, #14
LSL Z0.S, P0/M, Z0.S, #14
lsl z0.s, p0/m, z0.s, #15
LSL Z0.S, P0/M, Z0.S, #15
lsl z0.s, p0/m, z0.s, #0
LSL Z0.S, P0/M, Z0.S, #0
lsl z1.s, p0/m, z1.s, #0
LSL Z1.S, P0/M, Z1.S, #0
lsl z31.s, p0/m, z31.s, #0
LSL Z31.S, P0/M, Z31.S, #0
lsl z0.s, p2/m, z0.s, #0
LSL Z0.S, P2/M, Z0.S, #0
lsl z0.s, p7/m, z0.s, #0
LSL Z0.S, P7/M, Z0.S, #0
lsl z3.s, p0/m, z3.s, #0
LSL Z3.S, P0/M, Z3.S, #0
lsl z0.s, p0/m, z0.s, #1
LSL Z0.S, P0/M, Z0.S, #1
lsl z0.s, p0/m, z0.s, #30
LSL Z0.S, P0/M, Z0.S, #30
lsl z0.s, p0/m, z0.s, #31
LSL Z0.S, P0/M, Z0.S, #31
lsl z0.s, p0/m, z0.s, #8
LSL Z0.S, P0/M, Z0.S, #8
lsl z1.s, p0/m, z1.s, #8
LSL Z1.S, P0/M, Z1.S, #8
lsl z31.s, p0/m, z31.s, #8
LSL Z31.S, P0/M, Z31.S, #8
lsl z0.s, p2/m, z0.s, #8
LSL Z0.S, P2/M, Z0.S, #8
lsl z0.s, p7/m, z0.s, #8
LSL Z0.S, P7/M, Z0.S, #8
lsl z3.s, p0/m, z3.s, #8
LSL Z3.S, P0/M, Z3.S, #8
lsl z0.s, p0/m, z0.s, #9
LSL Z0.S, P0/M, Z0.S, #9
lsl z0.d, p0/m, z0.d, #14
LSL Z0.D, P0/M, Z0.D, #14
lsl z0.d, p0/m, z0.d, #15
LSL Z0.D, P0/M, Z0.D, #15
lsl z0.s, p0/m, z0.s, #16
LSL Z0.S, P0/M, Z0.S, #16
lsl z1.s, p0/m, z1.s, #16
LSL Z1.S, P0/M, Z1.S, #16
lsl z31.s, p0/m, z31.s, #16
LSL Z31.S, P0/M, Z31.S, #16
lsl z0.s, p2/m, z0.s, #16
LSL Z0.S, P2/M, Z0.S, #16
lsl z0.s, p7/m, z0.s, #16
LSL Z0.S, P7/M, Z0.S, #16
lsl z3.s, p0/m, z3.s, #16
LSL Z3.S, P0/M, Z3.S, #16
lsl z0.s, p0/m, z0.s, #17
LSL Z0.S, P0/M, Z0.S, #17
lsl z0.d, p0/m, z0.d, #30
LSL Z0.D, P0/M, Z0.D, #30
lsl z0.d, p0/m, z0.d, #31
LSL Z0.D, P0/M, Z0.D, #31
lsl z0.s, p0/m, z0.s, #24
LSL Z0.S, P0/M, Z0.S, #24
lsl z1.s, p0/m, z1.s, #24
LSL Z1.S, P0/M, Z1.S, #24
lsl z31.s, p0/m, z31.s, #24
LSL Z31.S, P0/M, Z31.S, #24
lsl z0.s, p2/m, z0.s, #24
LSL Z0.S, P2/M, Z0.S, #24
lsl z0.s, p7/m, z0.s, #24
LSL Z0.S, P7/M, Z0.S, #24
lsl z3.s, p0/m, z3.s, #24
LSL Z3.S, P0/M, Z3.S, #24
lsl z0.s, p0/m, z0.s, #25
LSL Z0.S, P0/M, Z0.S, #25
lsl z0.d, p0/m, z0.d, #46
LSL Z0.D, P0/M, Z0.D, #46
lsl z0.d, p0/m, z0.d, #47
LSL Z0.D, P0/M, Z0.D, #47
lsl z0.d, p0/m, z0.d, #0
LSL Z0.D, P0/M, Z0.D, #0
lsl z1.d, p0/m, z1.d, #0
LSL Z1.D, P0/M, Z1.D, #0
lsl z31.d, p0/m, z31.d, #0
LSL Z31.D, P0/M, Z31.D, #0
lsl z0.d, p2/m, z0.d, #0
LSL Z0.D, P2/M, Z0.D, #0
lsl z0.d, p7/m, z0.d, #0
LSL Z0.D, P7/M, Z0.D, #0
lsl z3.d, p0/m, z3.d, #0
LSL Z3.D, P0/M, Z3.D, #0
lsl z0.d, p0/m, z0.d, #1
LSL Z0.D, P0/M, Z0.D, #1
lsl z0.d, p0/m, z0.d, #62
LSL Z0.D, P0/M, Z0.D, #62
lsl z0.d, p0/m, z0.d, #63
LSL Z0.D, P0/M, Z0.D, #63
lsl z0.d, p0/m, z0.d, #8
LSL Z0.D, P0/M, Z0.D, #8
lsl z1.d, p0/m, z1.d, #8
LSL Z1.D, P0/M, Z1.D, #8
lsl z31.d, p0/m, z31.d, #8
LSL Z31.D, P0/M, Z31.D, #8
lsl z0.d, p2/m, z0.d, #8
LSL Z0.D, P2/M, Z0.D, #8
lsl z0.d, p7/m, z0.d, #8
LSL Z0.D, P7/M, Z0.D, #8
lsl z3.d, p0/m, z3.d, #8
LSL Z3.D, P0/M, Z3.D, #8
lsl z0.d, p0/m, z0.d, #9
LSL Z0.D, P0/M, Z0.D, #9
lsl z0.d, p0/m, z0.d, #16
LSL Z0.D, P0/M, Z0.D, #16
lsl z1.d, p0/m, z1.d, #16
LSL Z1.D, P0/M, Z1.D, #16
lsl z31.d, p0/m, z31.d, #16
LSL Z31.D, P0/M, Z31.D, #16
lsl z0.d, p2/m, z0.d, #16
LSL Z0.D, P2/M, Z0.D, #16
lsl z0.d, p7/m, z0.d, #16
LSL Z0.D, P7/M, Z0.D, #16
lsl z3.d, p0/m, z3.d, #16
LSL Z3.D, P0/M, Z3.D, #16
lsl z0.d, p0/m, z0.d, #17
LSL Z0.D, P0/M, Z0.D, #17
lsl z0.d, p0/m, z0.d, #24
LSL Z0.D, P0/M, Z0.D, #24
lsl z1.d, p0/m, z1.d, #24
LSL Z1.D, P0/M, Z1.D, #24
lsl z31.d, p0/m, z31.d, #24
LSL Z31.D, P0/M, Z31.D, #24
lsl z0.d, p2/m, z0.d, #24
LSL Z0.D, P2/M, Z0.D, #24
lsl z0.d, p7/m, z0.d, #24
LSL Z0.D, P7/M, Z0.D, #24
lsl z3.d, p0/m, z3.d, #24
LSL Z3.D, P0/M, Z3.D, #24
lsl z0.d, p0/m, z0.d, #25
LSL Z0.D, P0/M, Z0.D, #25
lsl z0.d, p0/m, z0.d, #32
LSL Z0.D, P0/M, Z0.D, #32
lsl z1.d, p0/m, z1.d, #32
LSL Z1.D, P0/M, Z1.D, #32
lsl z31.d, p0/m, z31.d, #32
LSL Z31.D, P0/M, Z31.D, #32
lsl z0.d, p2/m, z0.d, #32
LSL Z0.D, P2/M, Z0.D, #32
lsl z0.d, p7/m, z0.d, #32
LSL Z0.D, P7/M, Z0.D, #32
lsl z3.d, p0/m, z3.d, #32
LSL Z3.D, P0/M, Z3.D, #32
lsl z0.d, p0/m, z0.d, #33
LSL Z0.D, P0/M, Z0.D, #33
lsl z0.d, p0/m, z0.d, #40
LSL Z0.D, P0/M, Z0.D, #40
lsl z1.d, p0/m, z1.d, #40
LSL Z1.D, P0/M, Z1.D, #40
lsl z31.d, p0/m, z31.d, #40
LSL Z31.D, P0/M, Z31.D, #40
lsl z0.d, p2/m, z0.d, #40
LSL Z0.D, P2/M, Z0.D, #40
lsl z0.d, p7/m, z0.d, #40
LSL Z0.D, P7/M, Z0.D, #40
lsl z3.d, p0/m, z3.d, #40
LSL Z3.D, P0/M, Z3.D, #40
lsl z0.d, p0/m, z0.d, #41
LSL Z0.D, P0/M, Z0.D, #41
lsl z0.d, p0/m, z0.d, #48
LSL Z0.D, P0/M, Z0.D, #48
lsl z1.d, p0/m, z1.d, #48
LSL Z1.D, P0/M, Z1.D, #48
lsl z31.d, p0/m, z31.d, #48
LSL Z31.D, P0/M, Z31.D, #48
lsl z0.d, p2/m, z0.d, #48
LSL Z0.D, P2/M, Z0.D, #48
lsl z0.d, p7/m, z0.d, #48
LSL Z0.D, P7/M, Z0.D, #48
lsl z3.d, p0/m, z3.d, #48
LSL Z3.D, P0/M, Z3.D, #48
lsl z0.d, p0/m, z0.d, #49
LSL Z0.D, P0/M, Z0.D, #49
lsl z0.d, p0/m, z0.d, #56
LSL Z0.D, P0/M, Z0.D, #56
lsl z1.d, p0/m, z1.d, #56
LSL Z1.D, P0/M, Z1.D, #56
lsl z31.d, p0/m, z31.d, #56
LSL Z31.D, P0/M, Z31.D, #56
lsl z0.d, p2/m, z0.d, #56
LSL Z0.D, P2/M, Z0.D, #56
lsl z0.d, p7/m, z0.d, #56
LSL Z0.D, P7/M, Z0.D, #56
lsl z3.d, p0/m, z3.d, #56
LSL Z3.D, P0/M, Z3.D, #56
lsl z0.d, p0/m, z0.d, #57
LSL Z0.D, P0/M, Z0.D, #57
lslr z0.b, p0/m, z0.b, z0.b
LSLR Z0.B, P0/M, Z0.B, Z0.B
lslr z1.b, p0/m, z1.b, z0.b
LSLR Z1.B, P0/M, Z1.B, Z0.B
lslr z31.b, p0/m, z31.b, z0.b
LSLR Z31.B, P0/M, Z31.B, Z0.B
lslr z0.b, p2/m, z0.b, z0.b
LSLR Z0.B, P2/M, Z0.B, Z0.B
lslr z0.b, p7/m, z0.b, z0.b
LSLR Z0.B, P7/M, Z0.B, Z0.B
lslr z3.b, p0/m, z3.b, z0.b
LSLR Z3.B, P0/M, Z3.B, Z0.B
lslr z0.b, p0/m, z0.b, z4.b
LSLR Z0.B, P0/M, Z0.B, Z4.B
lslr z0.b, p0/m, z0.b, z31.b
LSLR Z0.B, P0/M, Z0.B, Z31.B
lslr z0.h, p0/m, z0.h, z0.h
LSLR Z0.H, P0/M, Z0.H, Z0.H
lslr z1.h, p0/m, z1.h, z0.h
LSLR Z1.H, P0/M, Z1.H, Z0.H
lslr z31.h, p0/m, z31.h, z0.h
LSLR Z31.H, P0/M, Z31.H, Z0.H
lslr z0.h, p2/m, z0.h, z0.h
LSLR Z0.H, P2/M, Z0.H, Z0.H
lslr z0.h, p7/m, z0.h, z0.h
LSLR Z0.H, P7/M, Z0.H, Z0.H
lslr z3.h, p0/m, z3.h, z0.h
LSLR Z3.H, P0/M, Z3.H, Z0.H
lslr z0.h, p0/m, z0.h, z4.h
LSLR Z0.H, P0/M, Z0.H, Z4.H
lslr z0.h, p0/m, z0.h, z31.h
LSLR Z0.H, P0/M, Z0.H, Z31.H
lslr z0.s, p0/m, z0.s, z0.s
LSLR Z0.S, P0/M, Z0.S, Z0.S
lslr z1.s, p0/m, z1.s, z0.s
LSLR Z1.S, P0/M, Z1.S, Z0.S
lslr z31.s, p0/m, z31.s, z0.s
LSLR Z31.S, P0/M, Z31.S, Z0.S
lslr z0.s, p2/m, z0.s, z0.s
LSLR Z0.S, P2/M, Z0.S, Z0.S
lslr z0.s, p7/m, z0.s, z0.s
LSLR Z0.S, P7/M, Z0.S, Z0.S
lslr z3.s, p0/m, z3.s, z0.s
LSLR Z3.S, P0/M, Z3.S, Z0.S
lslr z0.s, p0/m, z0.s, z4.s
LSLR Z0.S, P0/M, Z0.S, Z4.S
lslr z0.s, p0/m, z0.s, z31.s
LSLR Z0.S, P0/M, Z0.S, Z31.S
lslr z0.d, p0/m, z0.d, z0.d
LSLR Z0.D, P0/M, Z0.D, Z0.D
lslr z1.d, p0/m, z1.d, z0.d
LSLR Z1.D, P0/M, Z1.D, Z0.D
lslr z31.d, p0/m, z31.d, z0.d
LSLR Z31.D, P0/M, Z31.D, Z0.D
lslr z0.d, p2/m, z0.d, z0.d
LSLR Z0.D, P2/M, Z0.D, Z0.D
lslr z0.d, p7/m, z0.d, z0.d
LSLR Z0.D, P7/M, Z0.D, Z0.D
lslr z3.d, p0/m, z3.d, z0.d
LSLR Z3.D, P0/M, Z3.D, Z0.D
lslr z0.d, p0/m, z0.d, z4.d
LSLR Z0.D, P0/M, Z0.D, Z4.D
lslr z0.d, p0/m, z0.d, z31.d
LSLR Z0.D, P0/M, Z0.D, Z31.D
lsr z0.b, z0.b, z0.d
LSR Z0.B, Z0.B, Z0.D
lsr z1.b, z0.b, z0.d
LSR Z1.B, Z0.B, Z0.D
lsr z31.b, z0.b, z0.d
LSR Z31.B, Z0.B, Z0.D
lsr z0.b, z2.b, z0.d
LSR Z0.B, Z2.B, Z0.D
lsr z0.b, z31.b, z0.d
LSR Z0.B, Z31.B, Z0.D
lsr z0.b, z0.b, z3.d
LSR Z0.B, Z0.B, Z3.D
lsr z0.b, z0.b, z31.d
LSR Z0.B, Z0.B, Z31.D
lsr z0.h, z0.h, z0.d
LSR Z0.H, Z0.H, Z0.D
lsr z1.h, z0.h, z0.d
LSR Z1.H, Z0.H, Z0.D
lsr z31.h, z0.h, z0.d
LSR Z31.H, Z0.H, Z0.D
lsr z0.h, z2.h, z0.d
LSR Z0.H, Z2.H, Z0.D
lsr z0.h, z31.h, z0.d
LSR Z0.H, Z31.H, Z0.D
lsr z0.h, z0.h, z3.d
LSR Z0.H, Z0.H, Z3.D
lsr z0.h, z0.h, z31.d
LSR Z0.H, Z0.H, Z31.D
lsr z0.s, z0.s, z0.d
LSR Z0.S, Z0.S, Z0.D
lsr z1.s, z0.s, z0.d
LSR Z1.S, Z0.S, Z0.D
lsr z31.s, z0.s, z0.d
LSR Z31.S, Z0.S, Z0.D
lsr z0.s, z2.s, z0.d
LSR Z0.S, Z2.S, Z0.D
lsr z0.s, z31.s, z0.d
LSR Z0.S, Z31.S, Z0.D
lsr z0.s, z0.s, z3.d
LSR Z0.S, Z0.S, Z3.D
lsr z0.s, z0.s, z31.d
LSR Z0.S, Z0.S, Z31.D
lsr z0.b, z0.b, #8
LSR Z0.B, Z0.B, #8
lsr z1.b, z0.b, #8
LSR Z1.B, Z0.B, #8
lsr z31.b, z0.b, #8
LSR Z31.B, Z0.B, #8
lsr z0.b, z2.b, #8
LSR Z0.B, Z2.B, #8
lsr z0.b, z31.b, #8
LSR Z0.B, Z31.B, #8
lsr z0.b, z0.b, #7
LSR Z0.B, Z0.B, #7
lsr z0.b, z0.b, #2
LSR Z0.B, Z0.B, #2
lsr z0.b, z0.b, #1
LSR Z0.B, Z0.B, #1
lsr z0.h, z0.h, #16
LSR Z0.H, Z0.H, #16
lsr z1.h, z0.h, #16
LSR Z1.H, Z0.H, #16
lsr z31.h, z0.h, #16
LSR Z31.H, Z0.H, #16
lsr z0.h, z2.h, #16
LSR Z0.H, Z2.H, #16
lsr z0.h, z31.h, #16
LSR Z0.H, Z31.H, #16
lsr z0.h, z0.h, #15
LSR Z0.H, Z0.H, #15
lsr z0.h, z0.h, #2
LSR Z0.H, Z0.H, #2
lsr z0.h, z0.h, #1
LSR Z0.H, Z0.H, #1
lsr z0.h, z0.h, #8
LSR Z0.H, Z0.H, #8
lsr z1.h, z0.h, #8
LSR Z1.H, Z0.H, #8
lsr z31.h, z0.h, #8
LSR Z31.H, Z0.H, #8
lsr z0.h, z2.h, #8
LSR Z0.H, Z2.H, #8
lsr z0.h, z31.h, #8
LSR Z0.H, Z31.H, #8
lsr z0.h, z0.h, #7
LSR Z0.H, Z0.H, #7
lsr z0.s, z0.s, #18
LSR Z0.S, Z0.S, #18
lsr z0.s, z0.s, #17
LSR Z0.S, Z0.S, #17
lsr z0.s, z0.s, #32
LSR Z0.S, Z0.S, #32
lsr z1.s, z0.s, #32
LSR Z1.S, Z0.S, #32
lsr z31.s, z0.s, #32
LSR Z31.S, Z0.S, #32
lsr z0.s, z2.s, #32
LSR Z0.S, Z2.S, #32
lsr z0.s, z31.s, #32
LSR Z0.S, Z31.S, #32
lsr z0.s, z0.s, #31
LSR Z0.S, Z0.S, #31
lsr z0.s, z0.s, #2
LSR Z0.S, Z0.S, #2
lsr z0.s, z0.s, #1
LSR Z0.S, Z0.S, #1
lsr z0.s, z0.s, #24
LSR Z0.S, Z0.S, #24
lsr z1.s, z0.s, #24
LSR Z1.S, Z0.S, #24
lsr z31.s, z0.s, #24
LSR Z31.S, Z0.S, #24
lsr z0.s, z2.s, #24
LSR Z0.S, Z2.S, #24
lsr z0.s, z31.s, #24
LSR Z0.S, Z31.S, #24
lsr z0.s, z0.s, #23
LSR Z0.S, Z0.S, #23
lsr z0.d, z0.d, #50
LSR Z0.D, Z0.D, #50
lsr z0.d, z0.d, #49
LSR Z0.D, Z0.D, #49
lsr z0.s, z0.s, #16
LSR Z0.S, Z0.S, #16
lsr z1.s, z0.s, #16
LSR Z1.S, Z0.S, #16
lsr z31.s, z0.s, #16
LSR Z31.S, Z0.S, #16
lsr z0.s, z2.s, #16
LSR Z0.S, Z2.S, #16
lsr z0.s, z31.s, #16
LSR Z0.S, Z31.S, #16
lsr z0.s, z0.s, #15
LSR Z0.S, Z0.S, #15
lsr z0.d, z0.d, #34
LSR Z0.D, Z0.D, #34
lsr z0.d, z0.d, #33
LSR Z0.D, Z0.D, #33
lsr z0.s, z0.s, #8
LSR Z0.S, Z0.S, #8
lsr z1.s, z0.s, #8
LSR Z1.S, Z0.S, #8
lsr z31.s, z0.s, #8
LSR Z31.S, Z0.S, #8
lsr z0.s, z2.s, #8
LSR Z0.S, Z2.S, #8
lsr z0.s, z31.s, #8
LSR Z0.S, Z31.S, #8
lsr z0.s, z0.s, #7
LSR Z0.S, Z0.S, #7
lsr z0.d, z0.d, #18
LSR Z0.D, Z0.D, #18
lsr z0.d, z0.d, #17
LSR Z0.D, Z0.D, #17
lsr z0.d, z0.d, #64
LSR Z0.D, Z0.D, #64
lsr z1.d, z0.d, #64
LSR Z1.D, Z0.D, #64
lsr z31.d, z0.d, #64
LSR Z31.D, Z0.D, #64
lsr z0.d, z2.d, #64
LSR Z0.D, Z2.D, #64
lsr z0.d, z31.d, #64
LSR Z0.D, Z31.D, #64
lsr z0.d, z0.d, #63
LSR Z0.D, Z0.D, #63
lsr z0.d, z0.d, #2
LSR Z0.D, Z0.D, #2
lsr z0.d, z0.d, #1
LSR Z0.D, Z0.D, #1
lsr z0.d, z0.d, #56
LSR Z0.D, Z0.D, #56
lsr z1.d, z0.d, #56
LSR Z1.D, Z0.D, #56
lsr z31.d, z0.d, #56
LSR Z31.D, Z0.D, #56
lsr z0.d, z2.d, #56
LSR Z0.D, Z2.D, #56
lsr z0.d, z31.d, #56
LSR Z0.D, Z31.D, #56
lsr z0.d, z0.d, #55
LSR Z0.D, Z0.D, #55
lsr z0.d, z0.d, #48
LSR Z0.D, Z0.D, #48
lsr z1.d, z0.d, #48
LSR Z1.D, Z0.D, #48
lsr z31.d, z0.d, #48
LSR Z31.D, Z0.D, #48
lsr z0.d, z2.d, #48
LSR Z0.D, Z2.D, #48
lsr z0.d, z31.d, #48
LSR Z0.D, Z31.D, #48
lsr z0.d, z0.d, #47
LSR Z0.D, Z0.D, #47
lsr z0.d, z0.d, #40
LSR Z0.D, Z0.D, #40
lsr z1.d, z0.d, #40
LSR Z1.D, Z0.D, #40
lsr z31.d, z0.d, #40
LSR Z31.D, Z0.D, #40
lsr z0.d, z2.d, #40
LSR Z0.D, Z2.D, #40
lsr z0.d, z31.d, #40
LSR Z0.D, Z31.D, #40
lsr z0.d, z0.d, #39
LSR Z0.D, Z0.D, #39
lsr z0.d, z0.d, #32
LSR Z0.D, Z0.D, #32
lsr z1.d, z0.d, #32
LSR Z1.D, Z0.D, #32
lsr z31.d, z0.d, #32
LSR Z31.D, Z0.D, #32
lsr z0.d, z2.d, #32
LSR Z0.D, Z2.D, #32
lsr z0.d, z31.d, #32
LSR Z0.D, Z31.D, #32
lsr z0.d, z0.d, #31
LSR Z0.D, Z0.D, #31
lsr z0.d, z0.d, #24
LSR Z0.D, Z0.D, #24
lsr z1.d, z0.d, #24
LSR Z1.D, Z0.D, #24
lsr z31.d, z0.d, #24
LSR Z31.D, Z0.D, #24
lsr z0.d, z2.d, #24
LSR Z0.D, Z2.D, #24
lsr z0.d, z31.d, #24
LSR Z0.D, Z31.D, #24
lsr z0.d, z0.d, #23
LSR Z0.D, Z0.D, #23
lsr z0.d, z0.d, #16
LSR Z0.D, Z0.D, #16
lsr z1.d, z0.d, #16
LSR Z1.D, Z0.D, #16
lsr z31.d, z0.d, #16
LSR Z31.D, Z0.D, #16
lsr z0.d, z2.d, #16
LSR Z0.D, Z2.D, #16
lsr z0.d, z31.d, #16
LSR Z0.D, Z31.D, #16
lsr z0.d, z0.d, #15
LSR Z0.D, Z0.D, #15
lsr z0.d, z0.d, #8
LSR Z0.D, Z0.D, #8
lsr z1.d, z0.d, #8
LSR Z1.D, Z0.D, #8
lsr z31.d, z0.d, #8
LSR Z31.D, Z0.D, #8
lsr z0.d, z2.d, #8
LSR Z0.D, Z2.D, #8
lsr z0.d, z31.d, #8
LSR Z0.D, Z31.D, #8
lsr z0.d, z0.d, #7
LSR Z0.D, Z0.D, #7
lsr z0.b, p0/m, z0.b, z0.b
LSR Z0.B, P0/M, Z0.B, Z0.B
lsr z1.b, p0/m, z1.b, z0.b
LSR Z1.B, P0/M, Z1.B, Z0.B
lsr z31.b, p0/m, z31.b, z0.b
LSR Z31.B, P0/M, Z31.B, Z0.B
lsr z0.b, p2/m, z0.b, z0.b
LSR Z0.B, P2/M, Z0.B, Z0.B
lsr z0.b, p7/m, z0.b, z0.b
LSR Z0.B, P7/M, Z0.B, Z0.B
lsr z3.b, p0/m, z3.b, z0.b
LSR Z3.B, P0/M, Z3.B, Z0.B
lsr z0.b, p0/m, z0.b, z4.b
LSR Z0.B, P0/M, Z0.B, Z4.B
lsr z0.b, p0/m, z0.b, z31.b
LSR Z0.B, P0/M, Z0.B, Z31.B
lsr z0.h, p0/m, z0.h, z0.h
LSR Z0.H, P0/M, Z0.H, Z0.H
lsr z1.h, p0/m, z1.h, z0.h
LSR Z1.H, P0/M, Z1.H, Z0.H
lsr z31.h, p0/m, z31.h, z0.h
LSR Z31.H, P0/M, Z31.H, Z0.H
lsr z0.h, p2/m, z0.h, z0.h
LSR Z0.H, P2/M, Z0.H, Z0.H
lsr z0.h, p7/m, z0.h, z0.h
LSR Z0.H, P7/M, Z0.H, Z0.H
lsr z3.h, p0/m, z3.h, z0.h
LSR Z3.H, P0/M, Z3.H, Z0.H
lsr z0.h, p0/m, z0.h, z4.h
LSR Z0.H, P0/M, Z0.H, Z4.H
lsr z0.h, p0/m, z0.h, z31.h
LSR Z0.H, P0/M, Z0.H, Z31.H
lsr z0.s, p0/m, z0.s, z0.s
LSR Z0.S, P0/M, Z0.S, Z0.S
lsr z1.s, p0/m, z1.s, z0.s
LSR Z1.S, P0/M, Z1.S, Z0.S
lsr z31.s, p0/m, z31.s, z0.s
LSR Z31.S, P0/M, Z31.S, Z0.S
lsr z0.s, p2/m, z0.s, z0.s
LSR Z0.S, P2/M, Z0.S, Z0.S
lsr z0.s, p7/m, z0.s, z0.s
LSR Z0.S, P7/M, Z0.S, Z0.S
lsr z3.s, p0/m, z3.s, z0.s
LSR Z3.S, P0/M, Z3.S, Z0.S
lsr z0.s, p0/m, z0.s, z4.s
LSR Z0.S, P0/M, Z0.S, Z4.S
lsr z0.s, p0/m, z0.s, z31.s
LSR Z0.S, P0/M, Z0.S, Z31.S
lsr z0.d, p0/m, z0.d, z0.d
LSR Z0.D, P0/M, Z0.D, Z0.D
lsr z1.d, p0/m, z1.d, z0.d
LSR Z1.D, P0/M, Z1.D, Z0.D
lsr z31.d, p0/m, z31.d, z0.d
LSR Z31.D, P0/M, Z31.D, Z0.D
lsr z0.d, p2/m, z0.d, z0.d
LSR Z0.D, P2/M, Z0.D, Z0.D
lsr z0.d, p7/m, z0.d, z0.d
LSR Z0.D, P7/M, Z0.D, Z0.D
lsr z3.d, p0/m, z3.d, z0.d
LSR Z3.D, P0/M, Z3.D, Z0.D
lsr z0.d, p0/m, z0.d, z4.d
LSR Z0.D, P0/M, Z0.D, Z4.D
lsr z0.d, p0/m, z0.d, z31.d
LSR Z0.D, P0/M, Z0.D, Z31.D
lsr z0.b, p0/m, z0.b, z0.d
LSR Z0.B, P0/M, Z0.B, Z0.D
lsr z1.b, p0/m, z1.b, z0.d
LSR Z1.B, P0/M, Z1.B, Z0.D
lsr z31.b, p0/m, z31.b, z0.d
LSR Z31.B, P0/M, Z31.B, Z0.D
lsr z0.b, p2/m, z0.b, z0.d
LSR Z0.B, P2/M, Z0.B, Z0.D
lsr z0.b, p7/m, z0.b, z0.d
LSR Z0.B, P7/M, Z0.B, Z0.D
lsr z3.b, p0/m, z3.b, z0.d
LSR Z3.B, P0/M, Z3.B, Z0.D
lsr z0.b, p0/m, z0.b, z4.d
LSR Z0.B, P0/M, Z0.B, Z4.D
lsr z0.b, p0/m, z0.b, z31.d
LSR Z0.B, P0/M, Z0.B, Z31.D
lsr z0.h, p0/m, z0.h, z0.d
LSR Z0.H, P0/M, Z0.H, Z0.D
lsr z1.h, p0/m, z1.h, z0.d
LSR Z1.H, P0/M, Z1.H, Z0.D
lsr z31.h, p0/m, z31.h, z0.d
LSR Z31.H, P0/M, Z31.H, Z0.D
lsr z0.h, p2/m, z0.h, z0.d
LSR Z0.H, P2/M, Z0.H, Z0.D
lsr z0.h, p7/m, z0.h, z0.d
LSR Z0.H, P7/M, Z0.H, Z0.D
lsr z3.h, p0/m, z3.h, z0.d
LSR Z3.H, P0/M, Z3.H, Z0.D
lsr z0.h, p0/m, z0.h, z4.d
LSR Z0.H, P0/M, Z0.H, Z4.D
lsr z0.h, p0/m, z0.h, z31.d
LSR Z0.H, P0/M, Z0.H, Z31.D
lsr z0.s, p0/m, z0.s, z0.d
LSR Z0.S, P0/M, Z0.S, Z0.D
lsr z1.s, p0/m, z1.s, z0.d
LSR Z1.S, P0/M, Z1.S, Z0.D
lsr z31.s, p0/m, z31.s, z0.d
LSR Z31.S, P0/M, Z31.S, Z0.D
lsr z0.s, p2/m, z0.s, z0.d
LSR Z0.S, P2/M, Z0.S, Z0.D
lsr z0.s, p7/m, z0.s, z0.d
LSR Z0.S, P7/M, Z0.S, Z0.D
lsr z3.s, p0/m, z3.s, z0.d
LSR Z3.S, P0/M, Z3.S, Z0.D
lsr z0.s, p0/m, z0.s, z4.d
LSR Z0.S, P0/M, Z0.S, Z4.D
lsr z0.s, p0/m, z0.s, z31.d
LSR Z0.S, P0/M, Z0.S, Z31.D
lsr z0.b, p0/m, z0.b, #8
LSR Z0.B, P0/M, Z0.B, #8
lsr z1.b, p0/m, z1.b, #8
LSR Z1.B, P0/M, Z1.B, #8
lsr z31.b, p0/m, z31.b, #8
LSR Z31.B, P0/M, Z31.B, #8
lsr z0.b, p2/m, z0.b, #8
LSR Z0.B, P2/M, Z0.B, #8
lsr z0.b, p7/m, z0.b, #8
LSR Z0.B, P7/M, Z0.B, #8
lsr z3.b, p0/m, z3.b, #8
LSR Z3.B, P0/M, Z3.B, #8
lsr z0.b, p0/m, z0.b, #7
LSR Z0.B, P0/M, Z0.B, #7
lsr z0.b, p0/m, z0.b, #2
LSR Z0.B, P0/M, Z0.B, #2
lsr z0.b, p0/m, z0.b, #1
LSR Z0.B, P0/M, Z0.B, #1
lsr z0.h, p0/m, z0.h, #16
LSR Z0.H, P0/M, Z0.H, #16
lsr z1.h, p0/m, z1.h, #16
LSR Z1.H, P0/M, Z1.H, #16
lsr z31.h, p0/m, z31.h, #16
LSR Z31.H, P0/M, Z31.H, #16
lsr z0.h, p2/m, z0.h, #16
LSR Z0.H, P2/M, Z0.H, #16
lsr z0.h, p7/m, z0.h, #16
LSR Z0.H, P7/M, Z0.H, #16
lsr z3.h, p0/m, z3.h, #16
LSR Z3.H, P0/M, Z3.H, #16
lsr z0.h, p0/m, z0.h, #15
LSR Z0.H, P0/M, Z0.H, #15
lsr z0.h, p0/m, z0.h, #2
LSR Z0.H, P0/M, Z0.H, #2
lsr z0.h, p0/m, z0.h, #1
LSR Z0.H, P0/M, Z0.H, #1
lsr z0.h, p0/m, z0.h, #8
LSR Z0.H, P0/M, Z0.H, #8
lsr z1.h, p0/m, z1.h, #8
LSR Z1.H, P0/M, Z1.H, #8
lsr z31.h, p0/m, z31.h, #8
LSR Z31.H, P0/M, Z31.H, #8
lsr z0.h, p2/m, z0.h, #8
LSR Z0.H, P2/M, Z0.H, #8
lsr z0.h, p7/m, z0.h, #8
LSR Z0.H, P7/M, Z0.H, #8
lsr z3.h, p0/m, z3.h, #8
LSR Z3.H, P0/M, Z3.H, #8
lsr z0.h, p0/m, z0.h, #7
LSR Z0.H, P0/M, Z0.H, #7
lsr z0.s, p0/m, z0.s, #18
LSR Z0.S, P0/M, Z0.S, #18
lsr z0.s, p0/m, z0.s, #17
LSR Z0.S, P0/M, Z0.S, #17
lsr z0.s, p0/m, z0.s, #32
LSR Z0.S, P0/M, Z0.S, #32
lsr z1.s, p0/m, z1.s, #32
LSR Z1.S, P0/M, Z1.S, #32
lsr z31.s, p0/m, z31.s, #32
LSR Z31.S, P0/M, Z31.S, #32
lsr z0.s, p2/m, z0.s, #32
LSR Z0.S, P2/M, Z0.S, #32
lsr z0.s, p7/m, z0.s, #32
LSR Z0.S, P7/M, Z0.S, #32
lsr z3.s, p0/m, z3.s, #32
LSR Z3.S, P0/M, Z3.S, #32
lsr z0.s, p0/m, z0.s, #31
LSR Z0.S, P0/M, Z0.S, #31
lsr z0.s, p0/m, z0.s, #2
LSR Z0.S, P0/M, Z0.S, #2
lsr z0.s, p0/m, z0.s, #1
LSR Z0.S, P0/M, Z0.S, #1
lsr z0.s, p0/m, z0.s, #24
LSR Z0.S, P0/M, Z0.S, #24
lsr z1.s, p0/m, z1.s, #24
LSR Z1.S, P0/M, Z1.S, #24
lsr z31.s, p0/m, z31.s, #24
LSR Z31.S, P0/M, Z31.S, #24
lsr z0.s, p2/m, z0.s, #24
LSR Z0.S, P2/M, Z0.S, #24
lsr z0.s, p7/m, z0.s, #24
LSR Z0.S, P7/M, Z0.S, #24
lsr z3.s, p0/m, z3.s, #24
LSR Z3.S, P0/M, Z3.S, #24
lsr z0.s, p0/m, z0.s, #23
LSR Z0.S, P0/M, Z0.S, #23
lsr z0.d, p0/m, z0.d, #50
LSR Z0.D, P0/M, Z0.D, #50
lsr z0.d, p0/m, z0.d, #49
LSR Z0.D, P0/M, Z0.D, #49
lsr z0.s, p0/m, z0.s, #16
LSR Z0.S, P0/M, Z0.S, #16
lsr z1.s, p0/m, z1.s, #16
LSR Z1.S, P0/M, Z1.S, #16
lsr z31.s, p0/m, z31.s, #16
LSR Z31.S, P0/M, Z31.S, #16
lsr z0.s, p2/m, z0.s, #16
LSR Z0.S, P2/M, Z0.S, #16
lsr z0.s, p7/m, z0.s, #16
LSR Z0.S, P7/M, Z0.S, #16
lsr z3.s, p0/m, z3.s, #16
LSR Z3.S, P0/M, Z3.S, #16
lsr z0.s, p0/m, z0.s, #15
LSR Z0.S, P0/M, Z0.S, #15
lsr z0.d, p0/m, z0.d, #34
LSR Z0.D, P0/M, Z0.D, #34
lsr z0.d, p0/m, z0.d, #33
LSR Z0.D, P0/M, Z0.D, #33
lsr z0.s, p0/m, z0.s, #8
LSR Z0.S, P0/M, Z0.S, #8
lsr z1.s, p0/m, z1.s, #8
LSR Z1.S, P0/M, Z1.S, #8
lsr z31.s, p0/m, z31.s, #8
LSR Z31.S, P0/M, Z31.S, #8
lsr z0.s, p2/m, z0.s, #8
LSR Z0.S, P2/M, Z0.S, #8
lsr z0.s, p7/m, z0.s, #8
LSR Z0.S, P7/M, Z0.S, #8
lsr z3.s, p0/m, z3.s, #8
LSR Z3.S, P0/M, Z3.S, #8
lsr z0.s, p0/m, z0.s, #7
LSR Z0.S, P0/M, Z0.S, #7
lsr z0.d, p0/m, z0.d, #18
LSR Z0.D, P0/M, Z0.D, #18
lsr z0.d, p0/m, z0.d, #17
LSR Z0.D, P0/M, Z0.D, #17
lsr z0.d, p0/m, z0.d, #64
LSR Z0.D, P0/M, Z0.D, #64
lsr z1.d, p0/m, z1.d, #64
LSR Z1.D, P0/M, Z1.D, #64
lsr z31.d, p0/m, z31.d, #64
LSR Z31.D, P0/M, Z31.D, #64
lsr z0.d, p2/m, z0.d, #64
LSR Z0.D, P2/M, Z0.D, #64
lsr z0.d, p7/m, z0.d, #64
LSR Z0.D, P7/M, Z0.D, #64
lsr z3.d, p0/m, z3.d, #64
LSR Z3.D, P0/M, Z3.D, #64
lsr z0.d, p0/m, z0.d, #63
LSR Z0.D, P0/M, Z0.D, #63
lsr z0.d, p0/m, z0.d, #2
LSR Z0.D, P0/M, Z0.D, #2
lsr z0.d, p0/m, z0.d, #1
LSR Z0.D, P0/M, Z0.D, #1
lsr z0.d, p0/m, z0.d, #56
LSR Z0.D, P0/M, Z0.D, #56
lsr z1.d, p0/m, z1.d, #56
LSR Z1.D, P0/M, Z1.D, #56
lsr z31.d, p0/m, z31.d, #56
LSR Z31.D, P0/M, Z31.D, #56
lsr z0.d, p2/m, z0.d, #56
LSR Z0.D, P2/M, Z0.D, #56
lsr z0.d, p7/m, z0.d, #56
LSR Z0.D, P7/M, Z0.D, #56
lsr z3.d, p0/m, z3.d, #56
LSR Z3.D, P0/M, Z3.D, #56
lsr z0.d, p0/m, z0.d, #55
LSR Z0.D, P0/M, Z0.D, #55
lsr z0.d, p0/m, z0.d, #48
LSR Z0.D, P0/M, Z0.D, #48
lsr z1.d, p0/m, z1.d, #48
LSR Z1.D, P0/M, Z1.D, #48
lsr z31.d, p0/m, z31.d, #48
LSR Z31.D, P0/M, Z31.D, #48
lsr z0.d, p2/m, z0.d, #48
LSR Z0.D, P2/M, Z0.D, #48
lsr z0.d, p7/m, z0.d, #48
LSR Z0.D, P7/M, Z0.D, #48
lsr z3.d, p0/m, z3.d, #48
LSR Z3.D, P0/M, Z3.D, #48
lsr z0.d, p0/m, z0.d, #47
LSR Z0.D, P0/M, Z0.D, #47
lsr z0.d, p0/m, z0.d, #40
LSR Z0.D, P0/M, Z0.D, #40
lsr z1.d, p0/m, z1.d, #40
LSR Z1.D, P0/M, Z1.D, #40
lsr z31.d, p0/m, z31.d, #40
LSR Z31.D, P0/M, Z31.D, #40
lsr z0.d, p2/m, z0.d, #40
LSR Z0.D, P2/M, Z0.D, #40
lsr z0.d, p7/m, z0.d, #40
LSR Z0.D, P7/M, Z0.D, #40
lsr z3.d, p0/m, z3.d, #40
LSR Z3.D, P0/M, Z3.D, #40
lsr z0.d, p0/m, z0.d, #39
LSR Z0.D, P0/M, Z0.D, #39
lsr z0.d, p0/m, z0.d, #32
LSR Z0.D, P0/M, Z0.D, #32
lsr z1.d, p0/m, z1.d, #32
LSR Z1.D, P0/M, Z1.D, #32
lsr z31.d, p0/m, z31.d, #32
LSR Z31.D, P0/M, Z31.D, #32
lsr z0.d, p2/m, z0.d, #32
LSR Z0.D, P2/M, Z0.D, #32
lsr z0.d, p7/m, z0.d, #32
LSR Z0.D, P7/M, Z0.D, #32
lsr z3.d, p0/m, z3.d, #32
LSR Z3.D, P0/M, Z3.D, #32
lsr z0.d, p0/m, z0.d, #31
LSR Z0.D, P0/M, Z0.D, #31
lsr z0.d, p0/m, z0.d, #24
LSR Z0.D, P0/M, Z0.D, #24
lsr z1.d, p0/m, z1.d, #24
LSR Z1.D, P0/M, Z1.D, #24
lsr z31.d, p0/m, z31.d, #24
LSR Z31.D, P0/M, Z31.D, #24
lsr z0.d, p2/m, z0.d, #24
LSR Z0.D, P2/M, Z0.D, #24
lsr z0.d, p7/m, z0.d, #24
LSR Z0.D, P7/M, Z0.D, #24
lsr z3.d, p0/m, z3.d, #24
LSR Z3.D, P0/M, Z3.D, #24
lsr z0.d, p0/m, z0.d, #23
LSR Z0.D, P0/M, Z0.D, #23
lsr z0.d, p0/m, z0.d, #16
LSR Z0.D, P0/M, Z0.D, #16
lsr z1.d, p0/m, z1.d, #16
LSR Z1.D, P0/M, Z1.D, #16
lsr z31.d, p0/m, z31.d, #16
LSR Z31.D, P0/M, Z31.D, #16
lsr z0.d, p2/m, z0.d, #16
LSR Z0.D, P2/M, Z0.D, #16
lsr z0.d, p7/m, z0.d, #16
LSR Z0.D, P7/M, Z0.D, #16
lsr z3.d, p0/m, z3.d, #16
LSR Z3.D, P0/M, Z3.D, #16
lsr z0.d, p0/m, z0.d, #15
LSR Z0.D, P0/M, Z0.D, #15
lsr z0.d, p0/m, z0.d, #8
LSR Z0.D, P0/M, Z0.D, #8
lsr z1.d, p0/m, z1.d, #8
LSR Z1.D, P0/M, Z1.D, #8
lsr z31.d, p0/m, z31.d, #8
LSR Z31.D, P0/M, Z31.D, #8
lsr z0.d, p2/m, z0.d, #8
LSR Z0.D, P2/M, Z0.D, #8
lsr z0.d, p7/m, z0.d, #8
LSR Z0.D, P7/M, Z0.D, #8
lsr z3.d, p0/m, z3.d, #8
LSR Z3.D, P0/M, Z3.D, #8
lsr z0.d, p0/m, z0.d, #7
LSR Z0.D, P0/M, Z0.D, #7
lsrr z0.b, p0/m, z0.b, z0.b
LSRR Z0.B, P0/M, Z0.B, Z0.B
lsrr z1.b, p0/m, z1.b, z0.b
LSRR Z1.B, P0/M, Z1.B, Z0.B
lsrr z31.b, p0/m, z31.b, z0.b
LSRR Z31.B, P0/M, Z31.B, Z0.B
lsrr z0.b, p2/m, z0.b, z0.b
LSRR Z0.B, P2/M, Z0.B, Z0.B
lsrr z0.b, p7/m, z0.b, z0.b
LSRR Z0.B, P7/M, Z0.B, Z0.B
lsrr z3.b, p0/m, z3.b, z0.b
LSRR Z3.B, P0/M, Z3.B, Z0.B
lsrr z0.b, p0/m, z0.b, z4.b
LSRR Z0.B, P0/M, Z0.B, Z4.B
lsrr z0.b, p0/m, z0.b, z31.b
LSRR Z0.B, P0/M, Z0.B, Z31.B
lsrr z0.h, p0/m, z0.h, z0.h
LSRR Z0.H, P0/M, Z0.H, Z0.H
lsrr z1.h, p0/m, z1.h, z0.h
LSRR Z1.H, P0/M, Z1.H, Z0.H
lsrr z31.h, p0/m, z31.h, z0.h
LSRR Z31.H, P0/M, Z31.H, Z0.H
lsrr z0.h, p2/m, z0.h, z0.h
LSRR Z0.H, P2/M, Z0.H, Z0.H
lsrr z0.h, p7/m, z0.h, z0.h
LSRR Z0.H, P7/M, Z0.H, Z0.H
lsrr z3.h, p0/m, z3.h, z0.h
LSRR Z3.H, P0/M, Z3.H, Z0.H
lsrr z0.h, p0/m, z0.h, z4.h
LSRR Z0.H, P0/M, Z0.H, Z4.H
lsrr z0.h, p0/m, z0.h, z31.h
LSRR Z0.H, P0/M, Z0.H, Z31.H
lsrr z0.s, p0/m, z0.s, z0.s
LSRR Z0.S, P0/M, Z0.S, Z0.S
lsrr z1.s, p0/m, z1.s, z0.s
LSRR Z1.S, P0/M, Z1.S, Z0.S
lsrr z31.s, p0/m, z31.s, z0.s
LSRR Z31.S, P0/M, Z31.S, Z0.S
lsrr z0.s, p2/m, z0.s, z0.s
LSRR Z0.S, P2/M, Z0.S, Z0.S
lsrr z0.s, p7/m, z0.s, z0.s
LSRR Z0.S, P7/M, Z0.S, Z0.S
lsrr z3.s, p0/m, z3.s, z0.s
LSRR Z3.S, P0/M, Z3.S, Z0.S
lsrr z0.s, p0/m, z0.s, z4.s
LSRR Z0.S, P0/M, Z0.S, Z4.S
lsrr z0.s, p0/m, z0.s, z31.s
LSRR Z0.S, P0/M, Z0.S, Z31.S
lsrr z0.d, p0/m, z0.d, z0.d
LSRR Z0.D, P0/M, Z0.D, Z0.D
lsrr z1.d, p0/m, z1.d, z0.d
LSRR Z1.D, P0/M, Z1.D, Z0.D
lsrr z31.d, p0/m, z31.d, z0.d
LSRR Z31.D, P0/M, Z31.D, Z0.D
lsrr z0.d, p2/m, z0.d, z0.d
LSRR Z0.D, P2/M, Z0.D, Z0.D
lsrr z0.d, p7/m, z0.d, z0.d
LSRR Z0.D, P7/M, Z0.D, Z0.D
lsrr z3.d, p0/m, z3.d, z0.d
LSRR Z3.D, P0/M, Z3.D, Z0.D
lsrr z0.d, p0/m, z0.d, z4.d
LSRR Z0.D, P0/M, Z0.D, Z4.D
lsrr z0.d, p0/m, z0.d, z31.d
LSRR Z0.D, P0/M, Z0.D, Z31.D
mad z0.b, p0/m, z0.b, z0.b
MAD Z0.B, P0/M, Z0.B, Z0.B
mad z1.b, p0/m, z0.b, z0.b
MAD Z1.B, P0/M, Z0.B, Z0.B
mad z31.b, p0/m, z0.b, z0.b
MAD Z31.B, P0/M, Z0.B, Z0.B
mad z0.b, p2/m, z0.b, z0.b
MAD Z0.B, P2/M, Z0.B, Z0.B
mad z0.b, p7/m, z0.b, z0.b
MAD Z0.B, P7/M, Z0.B, Z0.B
mad z0.b, p0/m, z3.b, z0.b
MAD Z0.B, P0/M, Z3.B, Z0.B
mad z0.b, p0/m, z31.b, z0.b
MAD Z0.B, P0/M, Z31.B, Z0.B
mad z0.b, p0/m, z0.b, z4.b
MAD Z0.B, P0/M, Z0.B, Z4.B
mad z0.b, p0/m, z0.b, z31.b
MAD Z0.B, P0/M, Z0.B, Z31.B
mad z0.h, p0/m, z0.h, z0.h
MAD Z0.H, P0/M, Z0.H, Z0.H
mad z1.h, p0/m, z0.h, z0.h
MAD Z1.H, P0/M, Z0.H, Z0.H
mad z31.h, p0/m, z0.h, z0.h
MAD Z31.H, P0/M, Z0.H, Z0.H
mad z0.h, p2/m, z0.h, z0.h
MAD Z0.H, P2/M, Z0.H, Z0.H
mad z0.h, p7/m, z0.h, z0.h
MAD Z0.H, P7/M, Z0.H, Z0.H
mad z0.h, p0/m, z3.h, z0.h
MAD Z0.H, P0/M, Z3.H, Z0.H
mad z0.h, p0/m, z31.h, z0.h
MAD Z0.H, P0/M, Z31.H, Z0.H
mad z0.h, p0/m, z0.h, z4.h
MAD Z0.H, P0/M, Z0.H, Z4.H
mad z0.h, p0/m, z0.h, z31.h
MAD Z0.H, P0/M, Z0.H, Z31.H
mad z0.s, p0/m, z0.s, z0.s
MAD Z0.S, P0/M, Z0.S, Z0.S
mad z1.s, p0/m, z0.s, z0.s
MAD Z1.S, P0/M, Z0.S, Z0.S
mad z31.s, p0/m, z0.s, z0.s
MAD Z31.S, P0/M, Z0.S, Z0.S
mad z0.s, p2/m, z0.s, z0.s
MAD Z0.S, P2/M, Z0.S, Z0.S
mad z0.s, p7/m, z0.s, z0.s
MAD Z0.S, P7/M, Z0.S, Z0.S
mad z0.s, p0/m, z3.s, z0.s
MAD Z0.S, P0/M, Z3.S, Z0.S
mad z0.s, p0/m, z31.s, z0.s
MAD Z0.S, P0/M, Z31.S, Z0.S
mad z0.s, p0/m, z0.s, z4.s
MAD Z0.S, P0/M, Z0.S, Z4.S
mad z0.s, p0/m, z0.s, z31.s
MAD Z0.S, P0/M, Z0.S, Z31.S
mad z0.d, p0/m, z0.d, z0.d
MAD Z0.D, P0/M, Z0.D, Z0.D
mad z1.d, p0/m, z0.d, z0.d
MAD Z1.D, P0/M, Z0.D, Z0.D
mad z31.d, p0/m, z0.d, z0.d
MAD Z31.D, P0/M, Z0.D, Z0.D
mad z0.d, p2/m, z0.d, z0.d
MAD Z0.D, P2/M, Z0.D, Z0.D
mad z0.d, p7/m, z0.d, z0.d
MAD Z0.D, P7/M, Z0.D, Z0.D
mad z0.d, p0/m, z3.d, z0.d
MAD Z0.D, P0/M, Z3.D, Z0.D
mad z0.d, p0/m, z31.d, z0.d
MAD Z0.D, P0/M, Z31.D, Z0.D
mad z0.d, p0/m, z0.d, z4.d
MAD Z0.D, P0/M, Z0.D, Z4.D
mad z0.d, p0/m, z0.d, z31.d
MAD Z0.D, P0/M, Z0.D, Z31.D
mla z0.b, p0/m, z0.b, z0.b
MLA Z0.B, P0/M, Z0.B, Z0.B
mla z1.b, p0/m, z0.b, z0.b
MLA Z1.B, P0/M, Z0.B, Z0.B
mla z31.b, p0/m, z0.b, z0.b
MLA Z31.B, P0/M, Z0.B, Z0.B
mla z0.b, p2/m, z0.b, z0.b
MLA Z0.B, P2/M, Z0.B, Z0.B
mla z0.b, p7/m, z0.b, z0.b
MLA Z0.B, P7/M, Z0.B, Z0.B
mla z0.b, p0/m, z3.b, z0.b
MLA Z0.B, P0/M, Z3.B, Z0.B
mla z0.b, p0/m, z31.b, z0.b
MLA Z0.B, P0/M, Z31.B, Z0.B
mla z0.b, p0/m, z0.b, z4.b
MLA Z0.B, P0/M, Z0.B, Z4.B
mla z0.b, p0/m, z0.b, z31.b
MLA Z0.B, P0/M, Z0.B, Z31.B
mla z0.h, p0/m, z0.h, z0.h
MLA Z0.H, P0/M, Z0.H, Z0.H
mla z1.h, p0/m, z0.h, z0.h
MLA Z1.H, P0/M, Z0.H, Z0.H
mla z31.h, p0/m, z0.h, z0.h
MLA Z31.H, P0/M, Z0.H, Z0.H
mla z0.h, p2/m, z0.h, z0.h
MLA Z0.H, P2/M, Z0.H, Z0.H
mla z0.h, p7/m, z0.h, z0.h
MLA Z0.H, P7/M, Z0.H, Z0.H
mla z0.h, p0/m, z3.h, z0.h
MLA Z0.H, P0/M, Z3.H, Z0.H
mla z0.h, p0/m, z31.h, z0.h
MLA Z0.H, P0/M, Z31.H, Z0.H
mla z0.h, p0/m, z0.h, z4.h
MLA Z0.H, P0/M, Z0.H, Z4.H
mla z0.h, p0/m, z0.h, z31.h
MLA Z0.H, P0/M, Z0.H, Z31.H
mla z0.s, p0/m, z0.s, z0.s
MLA Z0.S, P0/M, Z0.S, Z0.S
mla z1.s, p0/m, z0.s, z0.s
MLA Z1.S, P0/M, Z0.S, Z0.S
mla z31.s, p0/m, z0.s, z0.s
MLA Z31.S, P0/M, Z0.S, Z0.S
mla z0.s, p2/m, z0.s, z0.s
MLA Z0.S, P2/M, Z0.S, Z0.S
mla z0.s, p7/m, z0.s, z0.s
MLA Z0.S, P7/M, Z0.S, Z0.S
mla z0.s, p0/m, z3.s, z0.s
MLA Z0.S, P0/M, Z3.S, Z0.S
mla z0.s, p0/m, z31.s, z0.s
MLA Z0.S, P0/M, Z31.S, Z0.S
mla z0.s, p0/m, z0.s, z4.s
MLA Z0.S, P0/M, Z0.S, Z4.S
mla z0.s, p0/m, z0.s, z31.s
MLA Z0.S, P0/M, Z0.S, Z31.S
mla z0.d, p0/m, z0.d, z0.d
MLA Z0.D, P0/M, Z0.D, Z0.D
mla z1.d, p0/m, z0.d, z0.d
MLA Z1.D, P0/M, Z0.D, Z0.D
mla z31.d, p0/m, z0.d, z0.d
MLA Z31.D, P0/M, Z0.D, Z0.D
mla z0.d, p2/m, z0.d, z0.d
MLA Z0.D, P2/M, Z0.D, Z0.D
mla z0.d, p7/m, z0.d, z0.d
MLA Z0.D, P7/M, Z0.D, Z0.D
mla z0.d, p0/m, z3.d, z0.d
MLA Z0.D, P0/M, Z3.D, Z0.D
mla z0.d, p0/m, z31.d, z0.d
MLA Z0.D, P0/M, Z31.D, Z0.D
mla z0.d, p0/m, z0.d, z4.d
MLA Z0.D, P0/M, Z0.D, Z4.D
mla z0.d, p0/m, z0.d, z31.d
MLA Z0.D, P0/M, Z0.D, Z31.D
mls z0.b, p0/m, z0.b, z0.b
MLS Z0.B, P0/M, Z0.B, Z0.B
mls z1.b, p0/m, z0.b, z0.b
MLS Z1.B, P0/M, Z0.B, Z0.B
mls z31.b, p0/m, z0.b, z0.b
MLS Z31.B, P0/M, Z0.B, Z0.B
mls z0.b, p2/m, z0.b, z0.b
MLS Z0.B, P2/M, Z0.B, Z0.B
mls z0.b, p7/m, z0.b, z0.b
MLS Z0.B, P7/M, Z0.B, Z0.B
mls z0.b, p0/m, z3.b, z0.b
MLS Z0.B, P0/M, Z3.B, Z0.B
mls z0.b, p0/m, z31.b, z0.b
MLS Z0.B, P0/M, Z31.B, Z0.B
mls z0.b, p0/m, z0.b, z4.b
MLS Z0.B, P0/M, Z0.B, Z4.B
mls z0.b, p0/m, z0.b, z31.b
MLS Z0.B, P0/M, Z0.B, Z31.B
mls z0.h, p0/m, z0.h, z0.h
MLS Z0.H, P0/M, Z0.H, Z0.H
mls z1.h, p0/m, z0.h, z0.h
MLS Z1.H, P0/M, Z0.H, Z0.H
mls z31.h, p0/m, z0.h, z0.h
MLS Z31.H, P0/M, Z0.H, Z0.H
mls z0.h, p2/m, z0.h, z0.h
MLS Z0.H, P2/M, Z0.H, Z0.H
mls z0.h, p7/m, z0.h, z0.h
MLS Z0.H, P7/M, Z0.H, Z0.H
mls z0.h, p0/m, z3.h, z0.h
MLS Z0.H, P0/M, Z3.H, Z0.H
mls z0.h, p0/m, z31.h, z0.h
MLS Z0.H, P0/M, Z31.H, Z0.H
mls z0.h, p0/m, z0.h, z4.h
MLS Z0.H, P0/M, Z0.H, Z4.H
mls z0.h, p0/m, z0.h, z31.h
MLS Z0.H, P0/M, Z0.H, Z31.H
mls z0.s, p0/m, z0.s, z0.s
MLS Z0.S, P0/M, Z0.S, Z0.S
mls z1.s, p0/m, z0.s, z0.s
MLS Z1.S, P0/M, Z0.S, Z0.S
mls z31.s, p0/m, z0.s, z0.s
MLS Z31.S, P0/M, Z0.S, Z0.S
mls z0.s, p2/m, z0.s, z0.s
MLS Z0.S, P2/M, Z0.S, Z0.S
mls z0.s, p7/m, z0.s, z0.s
MLS Z0.S, P7/M, Z0.S, Z0.S
mls z0.s, p0/m, z3.s, z0.s
MLS Z0.S, P0/M, Z3.S, Z0.S
mls z0.s, p0/m, z31.s, z0.s
MLS Z0.S, P0/M, Z31.S, Z0.S
mls z0.s, p0/m, z0.s, z4.s
MLS Z0.S, P0/M, Z0.S, Z4.S
mls z0.s, p0/m, z0.s, z31.s
MLS Z0.S, P0/M, Z0.S, Z31.S
mls z0.d, p0/m, z0.d, z0.d
MLS Z0.D, P0/M, Z0.D, Z0.D
mls z1.d, p0/m, z0.d, z0.d
MLS Z1.D, P0/M, Z0.D, Z0.D
mls z31.d, p0/m, z0.d, z0.d
MLS Z31.D, P0/M, Z0.D, Z0.D
mls z0.d, p2/m, z0.d, z0.d
MLS Z0.D, P2/M, Z0.D, Z0.D
mls z0.d, p7/m, z0.d, z0.d
MLS Z0.D, P7/M, Z0.D, Z0.D
mls z0.d, p0/m, z3.d, z0.d
MLS Z0.D, P0/M, Z3.D, Z0.D
mls z0.d, p0/m, z31.d, z0.d
MLS Z0.D, P0/M, Z31.D, Z0.D
mls z0.d, p0/m, z0.d, z4.d
MLS Z0.D, P0/M, Z0.D, Z4.D
mls z0.d, p0/m, z0.d, z31.d
MLS Z0.D, P0/M, Z0.D, Z31.D
msb z0.b, p0/m, z0.b, z0.b
MSB Z0.B, P0/M, Z0.B, Z0.B
msb z1.b, p0/m, z0.b, z0.b
MSB Z1.B, P0/M, Z0.B, Z0.B
msb z31.b, p0/m, z0.b, z0.b
MSB Z31.B, P0/M, Z0.B, Z0.B
msb z0.b, p2/m, z0.b, z0.b
MSB Z0.B, P2/M, Z0.B, Z0.B
msb z0.b, p7/m, z0.b, z0.b
MSB Z0.B, P7/M, Z0.B, Z0.B
msb z0.b, p0/m, z3.b, z0.b
MSB Z0.B, P0/M, Z3.B, Z0.B
msb z0.b, p0/m, z31.b, z0.b
MSB Z0.B, P0/M, Z31.B, Z0.B
msb z0.b, p0/m, z0.b, z4.b
MSB Z0.B, P0/M, Z0.B, Z4.B
msb z0.b, p0/m, z0.b, z31.b
MSB Z0.B, P0/M, Z0.B, Z31.B
msb z0.h, p0/m, z0.h, z0.h
MSB Z0.H, P0/M, Z0.H, Z0.H
msb z1.h, p0/m, z0.h, z0.h
MSB Z1.H, P0/M, Z0.H, Z0.H
msb z31.h, p0/m, z0.h, z0.h
MSB Z31.H, P0/M, Z0.H, Z0.H
msb z0.h, p2/m, z0.h, z0.h
MSB Z0.H, P2/M, Z0.H, Z0.H
msb z0.h, p7/m, z0.h, z0.h
MSB Z0.H, P7/M, Z0.H, Z0.H
msb z0.h, p0/m, z3.h, z0.h
MSB Z0.H, P0/M, Z3.H, Z0.H
msb z0.h, p0/m, z31.h, z0.h
MSB Z0.H, P0/M, Z31.H, Z0.H
msb z0.h, p0/m, z0.h, z4.h
MSB Z0.H, P0/M, Z0.H, Z4.H
msb z0.h, p0/m, z0.h, z31.h
MSB Z0.H, P0/M, Z0.H, Z31.H
msb z0.s, p0/m, z0.s, z0.s
MSB Z0.S, P0/M, Z0.S, Z0.S
msb z1.s, p0/m, z0.s, z0.s
MSB Z1.S, P0/M, Z0.S, Z0.S
msb z31.s, p0/m, z0.s, z0.s
MSB Z31.S, P0/M, Z0.S, Z0.S
msb z0.s, p2/m, z0.s, z0.s
MSB Z0.S, P2/M, Z0.S, Z0.S
msb z0.s, p7/m, z0.s, z0.s
MSB Z0.S, P7/M, Z0.S, Z0.S
msb z0.s, p0/m, z3.s, z0.s
MSB Z0.S, P0/M, Z3.S, Z0.S
msb z0.s, p0/m, z31.s, z0.s
MSB Z0.S, P0/M, Z31.S, Z0.S
msb z0.s, p0/m, z0.s, z4.s
MSB Z0.S, P0/M, Z0.S, Z4.S
msb z0.s, p0/m, z0.s, z31.s
MSB Z0.S, P0/M, Z0.S, Z31.S
msb z0.d, p0/m, z0.d, z0.d
MSB Z0.D, P0/M, Z0.D, Z0.D
msb z1.d, p0/m, z0.d, z0.d
MSB Z1.D, P0/M, Z0.D, Z0.D
msb z31.d, p0/m, z0.d, z0.d
MSB Z31.D, P0/M, Z0.D, Z0.D
msb z0.d, p2/m, z0.d, z0.d
MSB Z0.D, P2/M, Z0.D, Z0.D
msb z0.d, p7/m, z0.d, z0.d
MSB Z0.D, P7/M, Z0.D, Z0.D
msb z0.d, p0/m, z3.d, z0.d
MSB Z0.D, P0/M, Z3.D, Z0.D
msb z0.d, p0/m, z31.d, z0.d
MSB Z0.D, P0/M, Z31.D, Z0.D
msb z0.d, p0/m, z0.d, z4.d
MSB Z0.D, P0/M, Z0.D, Z4.D
msb z0.d, p0/m, z0.d, z31.d
MSB Z0.D, P0/M, Z0.D, Z31.D
mul z0.b, z0.b, #0
MUL Z0.B, Z0.B, #0
mul z1.b, z1.b, #0
MUL Z1.B, Z1.B, #0
mul z31.b, z31.b, #0
MUL Z31.B, Z31.B, #0
mul z2.b, z2.b, #0
MUL Z2.B, Z2.B, #0
mul z0.b, z0.b, #127
MUL Z0.B, Z0.B, #127
mul z0.b, z0.b, #-128
MUL Z0.B, Z0.B, #-128
mul z0.b, z0.b, #-127
MUL Z0.B, Z0.B, #-127
mul z0.b, z0.b, #-1
MUL Z0.B, Z0.B, #-1
mul z0.h, z0.h, #0
MUL Z0.H, Z0.H, #0
mul z1.h, z1.h, #0
MUL Z1.H, Z1.H, #0
mul z31.h, z31.h, #0
MUL Z31.H, Z31.H, #0
mul z2.h, z2.h, #0
MUL Z2.H, Z2.H, #0
mul z0.h, z0.h, #127
MUL Z0.H, Z0.H, #127
mul z0.h, z0.h, #-128
MUL Z0.H, Z0.H, #-128
mul z0.h, z0.h, #-127
MUL Z0.H, Z0.H, #-127
mul z0.h, z0.h, #-1
MUL Z0.H, Z0.H, #-1
mul z0.s, z0.s, #0
MUL Z0.S, Z0.S, #0
mul z1.s, z1.s, #0
MUL Z1.S, Z1.S, #0
mul z31.s, z31.s, #0
MUL Z31.S, Z31.S, #0
mul z2.s, z2.s, #0
MUL Z2.S, Z2.S, #0
mul z0.s, z0.s, #127
MUL Z0.S, Z0.S, #127
mul z0.s, z0.s, #-128
MUL Z0.S, Z0.S, #-128
mul z0.s, z0.s, #-127
MUL Z0.S, Z0.S, #-127
mul z0.s, z0.s, #-1
MUL Z0.S, Z0.S, #-1
mul z0.d, z0.d, #0
MUL Z0.D, Z0.D, #0
mul z1.d, z1.d, #0
MUL Z1.D, Z1.D, #0
mul z31.d, z31.d, #0
MUL Z31.D, Z31.D, #0
mul z2.d, z2.d, #0
MUL Z2.D, Z2.D, #0
mul z0.d, z0.d, #127
MUL Z0.D, Z0.D, #127
mul z0.d, z0.d, #-128
MUL Z0.D, Z0.D, #-128
mul z0.d, z0.d, #-127
MUL Z0.D, Z0.D, #-127
mul z0.d, z0.d, #-1
MUL Z0.D, Z0.D, #-1
mul z0.b, p0/m, z0.b, z0.b
MUL Z0.B, P0/M, Z0.B, Z0.B
mul z1.b, p0/m, z1.b, z0.b
MUL Z1.B, P0/M, Z1.B, Z0.B
mul z31.b, p0/m, z31.b, z0.b
MUL Z31.B, P0/M, Z31.B, Z0.B
mul z0.b, p2/m, z0.b, z0.b
MUL Z0.B, P2/M, Z0.B, Z0.B
mul z0.b, p7/m, z0.b, z0.b
MUL Z0.B, P7/M, Z0.B, Z0.B
mul z3.b, p0/m, z3.b, z0.b
MUL Z3.B, P0/M, Z3.B, Z0.B
mul z0.b, p0/m, z0.b, z4.b
MUL Z0.B, P0/M, Z0.B, Z4.B
mul z0.b, p0/m, z0.b, z31.b
MUL Z0.B, P0/M, Z0.B, Z31.B
mul z0.h, p0/m, z0.h, z0.h
MUL Z0.H, P0/M, Z0.H, Z0.H
mul z1.h, p0/m, z1.h, z0.h
MUL Z1.H, P0/M, Z1.H, Z0.H
mul z31.h, p0/m, z31.h, z0.h
MUL Z31.H, P0/M, Z31.H, Z0.H
mul z0.h, p2/m, z0.h, z0.h
MUL Z0.H, P2/M, Z0.H, Z0.H
mul z0.h, p7/m, z0.h, z0.h
MUL Z0.H, P7/M, Z0.H, Z0.H
mul z3.h, p0/m, z3.h, z0.h
MUL Z3.H, P0/M, Z3.H, Z0.H
mul z0.h, p0/m, z0.h, z4.h
MUL Z0.H, P0/M, Z0.H, Z4.H
mul z0.h, p0/m, z0.h, z31.h
MUL Z0.H, P0/M, Z0.H, Z31.H
mul z0.s, p0/m, z0.s, z0.s
MUL Z0.S, P0/M, Z0.S, Z0.S
mul z1.s, p0/m, z1.s, z0.s
MUL Z1.S, P0/M, Z1.S, Z0.S
mul z31.s, p0/m, z31.s, z0.s
MUL Z31.S, P0/M, Z31.S, Z0.S
mul z0.s, p2/m, z0.s, z0.s
MUL Z0.S, P2/M, Z0.S, Z0.S
mul z0.s, p7/m, z0.s, z0.s
MUL Z0.S, P7/M, Z0.S, Z0.S
mul z3.s, p0/m, z3.s, z0.s
MUL Z3.S, P0/M, Z3.S, Z0.S
mul z0.s, p0/m, z0.s, z4.s
MUL Z0.S, P0/M, Z0.S, Z4.S
mul z0.s, p0/m, z0.s, z31.s
MUL Z0.S, P0/M, Z0.S, Z31.S
mul z0.d, p0/m, z0.d, z0.d
MUL Z0.D, P0/M, Z0.D, Z0.D
mul z1.d, p0/m, z1.d, z0.d
MUL Z1.D, P0/M, Z1.D, Z0.D
mul z31.d, p0/m, z31.d, z0.d
MUL Z31.D, P0/M, Z31.D, Z0.D
mul z0.d, p2/m, z0.d, z0.d
MUL Z0.D, P2/M, Z0.D, Z0.D
mul z0.d, p7/m, z0.d, z0.d
MUL Z0.D, P7/M, Z0.D, Z0.D
mul z3.d, p0/m, z3.d, z0.d
MUL Z3.D, P0/M, Z3.D, Z0.D
mul z0.d, p0/m, z0.d, z4.d
MUL Z0.D, P0/M, Z0.D, Z4.D
mul z0.d, p0/m, z0.d, z31.d
MUL Z0.D, P0/M, Z0.D, Z31.D
nand p0.b, p0/z, p0.b, p0.b
NAND P0.B, P0/Z, P0.B, P0.B
nand p1.b, p0/z, p0.b, p0.b
NAND P1.B, P0/Z, P0.B, P0.B
nand p15.b, p0/z, p0.b, p0.b
NAND P15.B, P0/Z, P0.B, P0.B
nand p0.b, p2/z, p0.b, p0.b
NAND P0.B, P2/Z, P0.B, P0.B
nand p0.b, p15/z, p0.b, p0.b
NAND P0.B, P15/Z, P0.B, P0.B
nand p0.b, p0/z, p3.b, p0.b
NAND P0.B, P0/Z, P3.B, P0.B
nand p0.b, p0/z, p15.b, p0.b
NAND P0.B, P0/Z, P15.B, P0.B
nand p0.b, p0/z, p0.b, p4.b
NAND P0.B, P0/Z, P0.B, P4.B
nand p0.b, p0/z, p0.b, p15.b
NAND P0.B, P0/Z, P0.B, P15.B
nands p0.b, p0/z, p0.b, p0.b
NANDS P0.B, P0/Z, P0.B, P0.B
nands p1.b, p0/z, p0.b, p0.b
NANDS P1.B, P0/Z, P0.B, P0.B
nands p15.b, p0/z, p0.b, p0.b
NANDS P15.B, P0/Z, P0.B, P0.B
nands p0.b, p2/z, p0.b, p0.b
NANDS P0.B, P2/Z, P0.B, P0.B
nands p0.b, p15/z, p0.b, p0.b
NANDS P0.B, P15/Z, P0.B, P0.B
nands p0.b, p0/z, p3.b, p0.b
NANDS P0.B, P0/Z, P3.B, P0.B
nands p0.b, p0/z, p15.b, p0.b
NANDS P0.B, P0/Z, P15.B, P0.B
nands p0.b, p0/z, p0.b, p4.b
NANDS P0.B, P0/Z, P0.B, P4.B
nands p0.b, p0/z, p0.b, p15.b
NANDS P0.B, P0/Z, P0.B, P15.B
neg z0.b, p0/m, z0.b
NEG Z0.B, P0/M, Z0.B
neg z1.b, p0/m, z0.b
NEG Z1.B, P0/M, Z0.B
neg z31.b, p0/m, z0.b
NEG Z31.B, P0/M, Z0.B
neg z0.b, p2/m, z0.b
NEG Z0.B, P2/M, Z0.B
neg z0.b, p7/m, z0.b
NEG Z0.B, P7/M, Z0.B
neg z0.b, p0/m, z3.b
NEG Z0.B, P0/M, Z3.B
neg z0.b, p0/m, z31.b
NEG Z0.B, P0/M, Z31.B
neg z0.h, p0/m, z0.h
NEG Z0.H, P0/M, Z0.H
neg z1.h, p0/m, z0.h
NEG Z1.H, P0/M, Z0.H
neg z31.h, p0/m, z0.h
NEG Z31.H, P0/M, Z0.H
neg z0.h, p2/m, z0.h
NEG Z0.H, P2/M, Z0.H
neg z0.h, p7/m, z0.h
NEG Z0.H, P7/M, Z0.H
neg z0.h, p0/m, z3.h
NEG Z0.H, P0/M, Z3.H
neg z0.h, p0/m, z31.h
NEG Z0.H, P0/M, Z31.H
neg z0.s, p0/m, z0.s
NEG Z0.S, P0/M, Z0.S
neg z1.s, p0/m, z0.s
NEG Z1.S, P0/M, Z0.S
neg z31.s, p0/m, z0.s
NEG Z31.S, P0/M, Z0.S
neg z0.s, p2/m, z0.s
NEG Z0.S, P2/M, Z0.S
neg z0.s, p7/m, z0.s
NEG Z0.S, P7/M, Z0.S
neg z0.s, p0/m, z3.s
NEG Z0.S, P0/M, Z3.S
neg z0.s, p0/m, z31.s
NEG Z0.S, P0/M, Z31.S
neg z0.d, p0/m, z0.d
NEG Z0.D, P0/M, Z0.D
neg z1.d, p0/m, z0.d
NEG Z1.D, P0/M, Z0.D
neg z31.d, p0/m, z0.d
NEG Z31.D, P0/M, Z0.D
neg z0.d, p2/m, z0.d
NEG Z0.D, P2/M, Z0.D
neg z0.d, p7/m, z0.d
NEG Z0.D, P7/M, Z0.D
neg z0.d, p0/m, z3.d
NEG Z0.D, P0/M, Z3.D
neg z0.d, p0/m, z31.d
NEG Z0.D, P0/M, Z31.D
nor p0.b, p0/z, p0.b, p0.b
NOR P0.B, P0/Z, P0.B, P0.B
nor p1.b, p0/z, p0.b, p0.b
NOR P1.B, P0/Z, P0.B, P0.B
nor p15.b, p0/z, p0.b, p0.b
NOR P15.B, P0/Z, P0.B, P0.B
nor p0.b, p2/z, p0.b, p0.b
NOR P0.B, P2/Z, P0.B, P0.B
nor p0.b, p15/z, p0.b, p0.b
NOR P0.B, P15/Z, P0.B, P0.B
nor p0.b, p0/z, p3.b, p0.b
NOR P0.B, P0/Z, P3.B, P0.B
nor p0.b, p0/z, p15.b, p0.b
NOR P0.B, P0/Z, P15.B, P0.B
nor p0.b, p0/z, p0.b, p4.b
NOR P0.B, P0/Z, P0.B, P4.B
nor p0.b, p0/z, p0.b, p15.b
NOR P0.B, P0/Z, P0.B, P15.B
nors p0.b, p0/z, p0.b, p0.b
NORS P0.B, P0/Z, P0.B, P0.B
nors p1.b, p0/z, p0.b, p0.b
NORS P1.B, P0/Z, P0.B, P0.B
nors p15.b, p0/z, p0.b, p0.b
NORS P15.B, P0/Z, P0.B, P0.B
nors p0.b, p2/z, p0.b, p0.b
NORS P0.B, P2/Z, P0.B, P0.B
nors p0.b, p15/z, p0.b, p0.b
NORS P0.B, P15/Z, P0.B, P0.B
nors p0.b, p0/z, p3.b, p0.b
NORS P0.B, P0/Z, P3.B, P0.B
nors p0.b, p0/z, p15.b, p0.b
NORS P0.B, P0/Z, P15.B, P0.B
nors p0.b, p0/z, p0.b, p4.b
NORS P0.B, P0/Z, P0.B, P4.B
nors p0.b, p0/z, p0.b, p15.b
NORS P0.B, P0/Z, P0.B, P15.B
not z0.b, p0/m, z0.b
NOT Z0.B, P0/M, Z0.B
not z1.b, p0/m, z0.b
NOT Z1.B, P0/M, Z0.B
not z31.b, p0/m, z0.b
NOT Z31.B, P0/M, Z0.B
not z0.b, p2/m, z0.b
NOT Z0.B, P2/M, Z0.B
not z0.b, p7/m, z0.b
NOT Z0.B, P7/M, Z0.B
not z0.b, p0/m, z3.b
NOT Z0.B, P0/M, Z3.B
not z0.b, p0/m, z31.b
NOT Z0.B, P0/M, Z31.B
not z0.h, p0/m, z0.h
NOT Z0.H, P0/M, Z0.H
not z1.h, p0/m, z0.h
NOT Z1.H, P0/M, Z0.H
not z31.h, p0/m, z0.h
NOT Z31.H, P0/M, Z0.H
not z0.h, p2/m, z0.h
NOT Z0.H, P2/M, Z0.H
not z0.h, p7/m, z0.h
NOT Z0.H, P7/M, Z0.H
not z0.h, p0/m, z3.h
NOT Z0.H, P0/M, Z3.H
not z0.h, p0/m, z31.h
NOT Z0.H, P0/M, Z31.H
not z0.s, p0/m, z0.s
NOT Z0.S, P0/M, Z0.S
not z1.s, p0/m, z0.s
NOT Z1.S, P0/M, Z0.S
not z31.s, p0/m, z0.s
NOT Z31.S, P0/M, Z0.S
not z0.s, p2/m, z0.s
NOT Z0.S, P2/M, Z0.S
not z0.s, p7/m, z0.s
NOT Z0.S, P7/M, Z0.S
not z0.s, p0/m, z3.s
NOT Z0.S, P0/M, Z3.S
not z0.s, p0/m, z31.s
NOT Z0.S, P0/M, Z31.S
not z0.d, p0/m, z0.d
NOT Z0.D, P0/M, Z0.D
not z1.d, p0/m, z0.d
NOT Z1.D, P0/M, Z0.D
not z31.d, p0/m, z0.d
NOT Z31.D, P0/M, Z0.D
not z0.d, p2/m, z0.d
NOT Z0.D, P2/M, Z0.D
not z0.d, p7/m, z0.d
NOT Z0.D, P7/M, Z0.D
not z0.d, p0/m, z3.d
NOT Z0.D, P0/M, Z3.D
not z0.d, p0/m, z31.d
NOT Z0.D, P0/M, Z31.D
orn p0.b, p0/z, p0.b, p0.b
ORN P0.B, P0/Z, P0.B, P0.B
orn p1.b, p0/z, p0.b, p0.b
ORN P1.B, P0/Z, P0.B, P0.B
orn p15.b, p0/z, p0.b, p0.b
ORN P15.B, P0/Z, P0.B, P0.B
orn p0.b, p2/z, p0.b, p0.b
ORN P0.B, P2/Z, P0.B, P0.B
orn p0.b, p15/z, p0.b, p0.b
ORN P0.B, P15/Z, P0.B, P0.B
orn p0.b, p0/z, p3.b, p0.b
ORN P0.B, P0/Z, P3.B, P0.B
orn p0.b, p0/z, p15.b, p0.b
ORN P0.B, P0/Z, P15.B, P0.B
orn p0.b, p0/z, p0.b, p4.b
ORN P0.B, P0/Z, P0.B, P4.B
orn p0.b, p0/z, p0.b, p15.b
ORN P0.B, P0/Z, P0.B, P15.B
orns p0.b, p0/z, p0.b, p0.b
ORNS P0.B, P0/Z, P0.B, P0.B
orns p1.b, p0/z, p0.b, p0.b
ORNS P1.B, P0/Z, P0.B, P0.B
orns p15.b, p0/z, p0.b, p0.b
ORNS P15.B, P0/Z, P0.B, P0.B
orns p0.b, p2/z, p0.b, p0.b
ORNS P0.B, P2/Z, P0.B, P0.B
orns p0.b, p15/z, p0.b, p0.b
ORNS P0.B, P15/Z, P0.B, P0.B
orns p0.b, p0/z, p3.b, p0.b
ORNS P0.B, P0/Z, P3.B, P0.B
orns p0.b, p0/z, p15.b, p0.b
ORNS P0.B, P0/Z, P15.B, P0.B
orns p0.b, p0/z, p0.b, p4.b
ORNS P0.B, P0/Z, P0.B, P4.B
orns p0.b, p0/z, p0.b, p15.b
ORNS P0.B, P0/Z, P0.B, P15.B
orr z0.d, z0.d, z0.d
ORR Z0.D, Z0.D, Z0.D
orr z1.d, z0.d, z0.d
ORR Z1.D, Z0.D, Z0.D
orr z31.d, z0.d, z0.d
ORR Z31.D, Z0.D, Z0.D
orr z0.d, z2.d, z0.d
ORR Z0.D, Z2.D, Z0.D
orr z0.d, z31.d, z0.d
ORR Z0.D, Z31.D, Z0.D
orr z0.d, z0.d, z3.d
ORR Z0.D, Z0.D, Z3.D
orr z0.d, z0.d, z31.d
ORR Z0.D, Z0.D, Z31.D
orr z0.s, z0.s, #0x1
ORR Z0.S, Z0.S, #0X1
orr z0.d, z0.d, #0x100000001
orr z1.s, z1.s, #0x1
ORR Z1.S, Z1.S, #0X1
orr z1.d, z1.d, #0x100000001
orr z31.s, z31.s, #0x1
ORR Z31.S, Z31.S, #0X1
orr z31.d, z31.d, #0x100000001
orr z2.s, z2.s, #0x1
ORR Z2.S, Z2.S, #0X1
orr z2.d, z2.d, #0x100000001
orr z0.s, z0.s, #0x7f
ORR Z0.S, Z0.S, #0X7F
orr z0.d, z0.d, #0x7f0000007f
orr z0.s, z0.s, #0x7fffffff
ORR Z0.S, Z0.S, #0X7FFFFFFF
orr z0.d, z0.d, #0x7fffffff7fffffff
orr z0.h, z0.h, #0x1
ORR Z0.H, Z0.H, #0X1
orr z0.s, z0.s, #0x10001
orr z0.d, z0.d, #0x1000100010001
orr z0.h, z0.h, #0x7fff
ORR Z0.H, Z0.H, #0X7FFF
orr z0.s, z0.s, #0x7fff7fff
orr z0.d, z0.d, #0x7fff7fff7fff7fff
orr z0.b, z0.b, #0x1
ORR Z0.B, Z0.B, #0X1
orr z0.h, z0.h, #0x101
orr z0.s, z0.s, #0x1010101
orr z0.d, z0.d, #0x101010101010101
orr z0.b, z0.b, #0x55
ORR Z0.B, Z0.B, #0X55
orr z0.h, z0.h, #0x5555
orr z0.s, z0.s, #0x55555555
orr z0.d, z0.d, #0x5555555555555555
orr z0.s, z0.s, #0x80000000
ORR Z0.S, Z0.S, #0X80000000
orr z0.d, z0.d, #0x8000000080000000
orr z0.s, z0.s, #0xbfffffff
ORR Z0.S, Z0.S, #0XBFFFFFFF
orr z0.d, z0.d, #0xbfffffffbfffffff
orr z0.h, z0.h, #0x8000
ORR Z0.H, Z0.H, #0X8000
orr z0.s, z0.s, #0x80008000
orr z0.d, z0.d, #0x8000800080008000
orr z0.b, z0.b, #0xbf
ORR Z0.B, Z0.B, #0XBF
orr z0.h, z0.h, #0xbfbf
orr z0.s, z0.s, #0xbfbfbfbf
orr z0.d, z0.d, #0xbfbfbfbfbfbfbfbf
orr z0.b, z0.b, #0xe3
ORR Z0.B, Z0.B, #0XE3
orr z0.h, z0.h, #0xe3e3
orr z0.s, z0.s, #0xe3e3e3e3
orr z0.d, z0.d, #0xe3e3e3e3e3e3e3e3
orr z0.s, z0.s, #0xfffffeff
ORR Z0.S, Z0.S, #0XFFFFFEFF
orr z0.d, z0.d, #0xfffffefffffffeff
orr z0.d, z0.d, #0xfffffffffffffffe
ORR Z0.D, Z0.D, #0XFFFFFFFFFFFFFFFE
orr z0.b, p0/m, z0.b, z0.b
ORR Z0.B, P0/M, Z0.B, Z0.B
orr z1.b, p0/m, z1.b, z0.b
ORR Z1.B, P0/M, Z1.B, Z0.B
orr z31.b, p0/m, z31.b, z0.b
ORR Z31.B, P0/M, Z31.B, Z0.B
orr z0.b, p2/m, z0.b, z0.b
ORR Z0.B, P2/M, Z0.B, Z0.B
orr z0.b, p7/m, z0.b, z0.b
ORR Z0.B, P7/M, Z0.B, Z0.B
orr z3.b, p0/m, z3.b, z0.b
ORR Z3.B, P0/M, Z3.B, Z0.B
orr z0.b, p0/m, z0.b, z4.b
ORR Z0.B, P0/M, Z0.B, Z4.B
orr z0.b, p0/m, z0.b, z31.b
ORR Z0.B, P0/M, Z0.B, Z31.B
orr z0.h, p0/m, z0.h, z0.h
ORR Z0.H, P0/M, Z0.H, Z0.H
orr z1.h, p0/m, z1.h, z0.h
ORR Z1.H, P0/M, Z1.H, Z0.H
orr z31.h, p0/m, z31.h, z0.h
ORR Z31.H, P0/M, Z31.H, Z0.H
orr z0.h, p2/m, z0.h, z0.h
ORR Z0.H, P2/M, Z0.H, Z0.H
orr z0.h, p7/m, z0.h, z0.h
ORR Z0.H, P7/M, Z0.H, Z0.H
orr z3.h, p0/m, z3.h, z0.h
ORR Z3.H, P0/M, Z3.H, Z0.H
orr z0.h, p0/m, z0.h, z4.h
ORR Z0.H, P0/M, Z0.H, Z4.H
orr z0.h, p0/m, z0.h, z31.h
ORR Z0.H, P0/M, Z0.H, Z31.H
orr z0.s, p0/m, z0.s, z0.s
ORR Z0.S, P0/M, Z0.S, Z0.S
orr z1.s, p0/m, z1.s, z0.s
ORR Z1.S, P0/M, Z1.S, Z0.S
orr z31.s, p0/m, z31.s, z0.s
ORR Z31.S, P0/M, Z31.S, Z0.S
orr z0.s, p2/m, z0.s, z0.s
ORR Z0.S, P2/M, Z0.S, Z0.S
orr z0.s, p7/m, z0.s, z0.s
ORR Z0.S, P7/M, Z0.S, Z0.S
orr z3.s, p0/m, z3.s, z0.s
ORR Z3.S, P0/M, Z3.S, Z0.S
orr z0.s, p0/m, z0.s, z4.s
ORR Z0.S, P0/M, Z0.S, Z4.S
orr z0.s, p0/m, z0.s, z31.s
ORR Z0.S, P0/M, Z0.S, Z31.S
orr z0.d, p0/m, z0.d, z0.d
ORR Z0.D, P0/M, Z0.D, Z0.D
orr z1.d, p0/m, z1.d, z0.d
ORR Z1.D, P0/M, Z1.D, Z0.D
orr z31.d, p0/m, z31.d, z0.d
ORR Z31.D, P0/M, Z31.D, Z0.D
orr z0.d, p2/m, z0.d, z0.d
ORR Z0.D, P2/M, Z0.D, Z0.D
orr z0.d, p7/m, z0.d, z0.d
ORR Z0.D, P7/M, Z0.D, Z0.D
orr z3.d, p0/m, z3.d, z0.d
ORR Z3.D, P0/M, Z3.D, Z0.D
orr z0.d, p0/m, z0.d, z4.d
ORR Z0.D, P0/M, Z0.D, Z4.D
orr z0.d, p0/m, z0.d, z31.d
ORR Z0.D, P0/M, Z0.D, Z31.D
orr p0.b, p0/z, p0.b, p0.b
ORR P0.B, P0/Z, P0.B, P0.B
orr p1.b, p0/z, p0.b, p0.b
ORR P1.B, P0/Z, P0.B, P0.B
orr p15.b, p0/z, p0.b, p0.b
ORR P15.B, P0/Z, P0.B, P0.B
orr p0.b, p2/z, p0.b, p0.b
ORR P0.B, P2/Z, P0.B, P0.B
orr p0.b, p15/z, p0.b, p0.b
ORR P0.B, P15/Z, P0.B, P0.B
orr p0.b, p0/z, p3.b, p0.b
ORR P0.B, P0/Z, P3.B, P0.B
orr p0.b, p0/z, p15.b, p0.b
ORR P0.B, P0/Z, P15.B, P0.B
orr p0.b, p0/z, p0.b, p4.b
ORR P0.B, P0/Z, P0.B, P4.B
orr p0.b, p0/z, p0.b, p15.b
ORR P0.B, P0/Z, P0.B, P15.B
orrs p0.b, p0/z, p0.b, p0.b
ORRS P0.B, P0/Z, P0.B, P0.B
orrs p1.b, p0/z, p0.b, p0.b
ORRS P1.B, P0/Z, P0.B, P0.B
orrs p15.b, p0/z, p0.b, p0.b
ORRS P15.B, P0/Z, P0.B, P0.B
orrs p0.b, p2/z, p0.b, p0.b
ORRS P0.B, P2/Z, P0.B, P0.B
orrs p0.b, p15/z, p0.b, p0.b
ORRS P0.B, P15/Z, P0.B, P0.B
orrs p0.b, p0/z, p3.b, p0.b
ORRS P0.B, P0/Z, P3.B, P0.B
orrs p0.b, p0/z, p15.b, p0.b
ORRS P0.B, P0/Z, P15.B, P0.B
orrs p0.b, p0/z, p0.b, p4.b
ORRS P0.B, P0/Z, P0.B, P4.B
orrs p0.b, p0/z, p0.b, p15.b
ORRS P0.B, P0/Z, P0.B, P15.B
orv b0, p0, z0.b
ORV B0, P0, Z0.B
orv b1, p0, z0.b
ORV B1, P0, Z0.B
orv b31, p0, z0.b
ORV B31, P0, Z0.B
orv b0, p2, z0.b
ORV B0, P2, Z0.B
orv b0, p7, z0.b
ORV B0, P7, Z0.B
orv b0, p0, z3.b
ORV B0, P0, Z3.B
orv b0, p0, z31.b
ORV B0, P0, Z31.B
orv h0, p0, z0.h
ORV H0, P0, Z0.H
orv h1, p0, z0.h
ORV H1, P0, Z0.H
orv h31, p0, z0.h
ORV H31, P0, Z0.H
orv h0, p2, z0.h
ORV H0, P2, Z0.H
orv h0, p7, z0.h
ORV H0, P7, Z0.H
orv h0, p0, z3.h
ORV H0, P0, Z3.H
orv h0, p0, z31.h
ORV H0, P0, Z31.H
orv s0, p0, z0.s
ORV S0, P0, Z0.S
orv s1, p0, z0.s
ORV S1, P0, Z0.S
orv s31, p0, z0.s
ORV S31, P0, Z0.S
orv s0, p2, z0.s
ORV S0, P2, Z0.S
orv s0, p7, z0.s
ORV S0, P7, Z0.S
orv s0, p0, z3.s
ORV S0, P0, Z3.S
orv s0, p0, z31.s
ORV S0, P0, Z31.S
orv d0, p0, z0.d
ORV D0, P0, Z0.D
orv d1, p0, z0.d
ORV D1, P0, Z0.D
orv d31, p0, z0.d
ORV D31, P0, Z0.D
orv d0, p2, z0.d
ORV D0, P2, Z0.D
orv d0, p7, z0.d
ORV D0, P7, Z0.D
orv d0, p0, z3.d
ORV D0, P0, Z3.D
orv d0, p0, z31.d
ORV D0, P0, Z31.D
pfalse p0.b
PFALSE P0.B
pfalse p1.b
PFALSE P1.B
pfalse p15.b
PFALSE P15.B
pfirst p0.b, p0, p0.b
PFIRST P0.B, P0, P0.B
pfirst p1.b, p0, p1.b
PFIRST P1.B, P0, P1.B
pfirst p15.b, p0, p15.b
PFIRST P15.B, P0, P15.B
pfirst p0.b, p2, p0.b
PFIRST P0.B, P2, P0.B
pfirst p0.b, p15, p0.b
PFIRST P0.B, P15, P0.B
pfirst p3.b, p0, p3.b
PFIRST P3.B, P0, P3.B
pnext p0.b, p0, p0.b
PNEXT P0.B, P0, P0.B
pnext p1.b, p0, p1.b
PNEXT P1.B, P0, P1.B
pnext p15.b, p0, p15.b
PNEXT P15.B, P0, P15.B
pnext p0.b, p2, p0.b
PNEXT P0.B, P2, P0.B
pnext p0.b, p15, p0.b
PNEXT P0.B, P15, P0.B
pnext p3.b, p0, p3.b
PNEXT P3.B, P0, P3.B
pnext p0.h, p0, p0.h
PNEXT P0.H, P0, P0.H
pnext p1.h, p0, p1.h
PNEXT P1.H, P0, P1.H
pnext p15.h, p0, p15.h
PNEXT P15.H, P0, P15.H
pnext p0.h, p2, p0.h
PNEXT P0.H, P2, P0.H
pnext p0.h, p15, p0.h
PNEXT P0.H, P15, P0.H
pnext p3.h, p0, p3.h
PNEXT P3.H, P0, P3.H
pnext p0.s, p0, p0.s
PNEXT P0.S, P0, P0.S
pnext p1.s, p0, p1.s
PNEXT P1.S, P0, P1.S
pnext p15.s, p0, p15.s
PNEXT P15.S, P0, P15.S
pnext p0.s, p2, p0.s
PNEXT P0.S, P2, P0.S
pnext p0.s, p15, p0.s
PNEXT P0.S, P15, P0.S
pnext p3.s, p0, p3.s
PNEXT P3.S, P0, P3.S
pnext p0.d, p0, p0.d
PNEXT P0.D, P0, P0.D
pnext p1.d, p0, p1.d
PNEXT P1.D, P0, P1.D
pnext p15.d, p0, p15.d
PNEXT P15.D, P0, P15.D
pnext p0.d, p2, p0.d
PNEXT P0.D, P2, P0.D
pnext p0.d, p15, p0.d
PNEXT P0.D, P15, P0.D
pnext p3.d, p0, p3.d
PNEXT P3.D, P0, P3.D
prfb pldl1keep, p0, [x0,x0]
PRFB PLDL1KEEP, P0, [X0,X0]
prfb pldl1keep, p0, [x0,x0,lsl #0]
prfb pldl1strm, p0, [x0,x0]
PRFB PLDL1STRM, P0, [X0,X0]
prfb pldl1strm, p0, [x0,x0,lsl #0]
prfb pldl2keep, p0, [x0,x0]
PRFB PLDL2KEEP, P0, [X0,X0]
prfb pldl2keep, p0, [x0,x0,lsl #0]
prfb pldl2strm, p0, [x0,x0]
PRFB PLDL2STRM, P0, [X0,X0]
prfb pldl2strm, p0, [x0,x0,lsl #0]
prfb pldl3keep, p0, [x0,x0]
PRFB PLDL3KEEP, P0, [X0,X0]
prfb pldl3keep, p0, [x0,x0,lsl #0]
prfb pldl3strm, p0, [x0,x0]
PRFB PLDL3STRM, P0, [X0,X0]
prfb pldl3strm, p0, [x0,x0,lsl #0]
prfb #6, p0, [x0,x0]
PRFB #6, P0, [X0,X0]
prfb #6, p0, [x0,x0,lsl #0]
prfb #7, p0, [x0,x0]
PRFB #7, P0, [X0,X0]
prfb #7, p0, [x0,x0,lsl #0]
prfb pstl1keep, p0, [x0,x0]
PRFB PSTL1KEEP, P0, [X0,X0]
prfb pstl1keep, p0, [x0,x0,lsl #0]
prfb pstl1strm, p0, [x0,x0]
PRFB PSTL1STRM, P0, [X0,X0]
prfb pstl1strm, p0, [x0,x0,lsl #0]
prfb pstl2keep, p0, [x0,x0]
PRFB PSTL2KEEP, P0, [X0,X0]
prfb pstl2keep, p0, [x0,x0,lsl #0]
prfb pstl2strm, p0, [x0,x0]
PRFB PSTL2STRM, P0, [X0,X0]
prfb pstl2strm, p0, [x0,x0,lsl #0]
prfb pstl3keep, p0, [x0,x0]
PRFB PSTL3KEEP, P0, [X0,X0]
prfb pstl3keep, p0, [x0,x0,lsl #0]
prfb pstl3strm, p0, [x0,x0]
PRFB PSTL3STRM, P0, [X0,X0]
prfb pstl3strm, p0, [x0,x0,lsl #0]
prfb #14, p0, [x0,x0]
PRFB #14, P0, [X0,X0]
prfb #14, p0, [x0,x0,lsl #0]
prfb #15, p0, [x0,x0]
PRFB #15, P0, [X0,X0]
prfb #15, p0, [x0,x0,lsl #0]
prfb pldl1keep, p2, [x0,x0]
PRFB PLDL1KEEP, P2, [X0,X0]
prfb pldl1keep, p2, [x0,x0,lsl #0]
prfb pldl1keep, p7, [x0,x0]
PRFB PLDL1KEEP, P7, [X0,X0]
prfb pldl1keep, p7, [x0,x0,lsl #0]
prfb pldl1keep, p0, [x3,x0]
PRFB PLDL1KEEP, P0, [X3,X0]
prfb pldl1keep, p0, [x3,x0,lsl #0]
prfb pldl1keep, p0, [sp,x0]
PRFB PLDL1KEEP, P0, [SP,X0]
prfb pldl1keep, p0, [sp,x0,lsl #0]
prfb pldl1keep, p0, [x0,x4]
PRFB PLDL1KEEP, P0, [X0,X4]
prfb pldl1keep, p0, [x0,x4,lsl #0]
prfb pldl1keep, p0, [x0,x30]
PRFB PLDL1KEEP, P0, [X0,X30]
prfb pldl1keep, p0, [x0,x30,lsl #0]
prfb pldl1keep, p0, [x0,z0.s,uxtw]
PRFB PLDL1KEEP, P0, [X0,Z0.S,UXTW]
prfb pldl1keep, p0, [x0,z0.s,uxtw #0]
prfb pldl1strm, p0, [x0,z0.s,uxtw]
PRFB PLDL1STRM, P0, [X0,Z0.S,UXTW]
prfb pldl1strm, p0, [x0,z0.s,uxtw #0]
prfb pldl2keep, p0, [x0,z0.s,uxtw]
PRFB PLDL2KEEP, P0, [X0,Z0.S,UXTW]
prfb pldl2keep, p0, [x0,z0.s,uxtw #0]
prfb pldl2strm, p0, [x0,z0.s,uxtw]
PRFB PLDL2STRM, P0, [X0,Z0.S,UXTW]
prfb pldl2strm, p0, [x0,z0.s,uxtw #0]
prfb pldl3keep, p0, [x0,z0.s,uxtw]
PRFB PLDL3KEEP, P0, [X0,Z0.S,UXTW]
prfb pldl3keep, p0, [x0,z0.s,uxtw #0]
prfb pldl3strm, p0, [x0,z0.s,uxtw]
PRFB PLDL3STRM, P0, [X0,Z0.S,UXTW]
prfb pldl3strm, p0, [x0,z0.s,uxtw #0]
prfb #6, p0, [x0,z0.s,uxtw]
PRFB #6, P0, [X0,Z0.S,UXTW]
prfb #6, p0, [x0,z0.s,uxtw #0]
prfb #7, p0, [x0,z0.s,uxtw]
PRFB #7, P0, [X0,Z0.S,UXTW]
prfb #7, p0, [x0,z0.s,uxtw #0]
prfb pstl1keep, p0, [x0,z0.s,uxtw]
PRFB PSTL1KEEP, P0, [X0,Z0.S,UXTW]
prfb pstl1keep, p0, [x0,z0.s,uxtw #0]
prfb pstl1strm, p0, [x0,z0.s,uxtw]
PRFB PSTL1STRM, P0, [X0,Z0.S,UXTW]
prfb pstl1strm, p0, [x0,z0.s,uxtw #0]
prfb pstl2keep, p0, [x0,z0.s,uxtw]
PRFB PSTL2KEEP, P0, [X0,Z0.S,UXTW]
prfb pstl2keep, p0, [x0,z0.s,uxtw #0]
prfb pstl2strm, p0, [x0,z0.s,uxtw]
PRFB PSTL2STRM, P0, [X0,Z0.S,UXTW]
prfb pstl2strm, p0, [x0,z0.s,uxtw #0]
prfb pstl3keep, p0, [x0,z0.s,uxtw]
PRFB PSTL3KEEP, P0, [X0,Z0.S,UXTW]
prfb pstl3keep, p0, [x0,z0.s,uxtw #0]
prfb pstl3strm, p0, [x0,z0.s,uxtw]
PRFB PSTL3STRM, P0, [X0,Z0.S,UXTW]
prfb pstl3strm, p0, [x0,z0.s,uxtw #0]
prfb #14, p0, [x0,z0.s,uxtw]
PRFB #14, P0, [X0,Z0.S,UXTW]
prfb #14, p0, [x0,z0.s,uxtw #0]
prfb #15, p0, [x0,z0.s,uxtw]
PRFB #15, P0, [X0,Z0.S,UXTW]
prfb #15, p0, [x0,z0.s,uxtw #0]
prfb pldl1keep, p2, [x0,z0.s,uxtw]
PRFB PLDL1KEEP, P2, [X0,Z0.S,UXTW]
prfb pldl1keep, p2, [x0,z0.s,uxtw #0]
prfb pldl1keep, p7, [x0,z0.s,uxtw]
PRFB PLDL1KEEP, P7, [X0,Z0.S,UXTW]
prfb pldl1keep, p7, [x0,z0.s,uxtw #0]
prfb pldl1keep, p0, [x3,z0.s,uxtw]
PRFB PLDL1KEEP, P0, [X3,Z0.S,UXTW]
prfb pldl1keep, p0, [x3,z0.s,uxtw #0]
prfb pldl1keep, p0, [sp,z0.s,uxtw]
PRFB PLDL1KEEP, P0, [SP,Z0.S,UXTW]
prfb pldl1keep, p0, [sp,z0.s,uxtw #0]
prfb pldl1keep, p0, [x0,z4.s,uxtw]
PRFB PLDL1KEEP, P0, [X0,Z4.S,UXTW]
prfb pldl1keep, p0, [x0,z4.s,uxtw #0]
prfb pldl1keep, p0, [x0,z31.s,uxtw]
PRFB PLDL1KEEP, P0, [X0,Z31.S,UXTW]
prfb pldl1keep, p0, [x0,z31.s,uxtw #0]
prfb pldl1keep, p0, [x0,z0.s,sxtw]
PRFB PLDL1KEEP, P0, [X0,Z0.S,SXTW]
prfb pldl1keep, p0, [x0,z0.s,sxtw #0]
prfb pldl1strm, p0, [x0,z0.s,sxtw]
PRFB PLDL1STRM, P0, [X0,Z0.S,SXTW]
prfb pldl1strm, p0, [x0,z0.s,sxtw #0]
prfb pldl2keep, p0, [x0,z0.s,sxtw]
PRFB PLDL2KEEP, P0, [X0,Z0.S,SXTW]
prfb pldl2keep, p0, [x0,z0.s,sxtw #0]
prfb pldl2strm, p0, [x0,z0.s,sxtw]
PRFB PLDL2STRM, P0, [X0,Z0.S,SXTW]
prfb pldl2strm, p0, [x0,z0.s,sxtw #0]
prfb pldl3keep, p0, [x0,z0.s,sxtw]
PRFB PLDL3KEEP, P0, [X0,Z0.S,SXTW]
prfb pldl3keep, p0, [x0,z0.s,sxtw #0]
prfb pldl3strm, p0, [x0,z0.s,sxtw]
PRFB PLDL3STRM, P0, [X0,Z0.S,SXTW]
prfb pldl3strm, p0, [x0,z0.s,sxtw #0]
prfb #6, p0, [x0,z0.s,sxtw]
PRFB #6, P0, [X0,Z0.S,SXTW]
prfb #6, p0, [x0,z0.s,sxtw #0]
prfb #7, p0, [x0,z0.s,sxtw]
PRFB #7, P0, [X0,Z0.S,SXTW]
prfb #7, p0, [x0,z0.s,sxtw #0]
prfb pstl1keep, p0, [x0,z0.s,sxtw]
PRFB PSTL1KEEP, P0, [X0,Z0.S,SXTW]
prfb pstl1keep, p0, [x0,z0.s,sxtw #0]
prfb pstl1strm, p0, [x0,z0.s,sxtw]
PRFB PSTL1STRM, P0, [X0,Z0.S,SXTW]
prfb pstl1strm, p0, [x0,z0.s,sxtw #0]
prfb pstl2keep, p0, [x0,z0.s,sxtw]
PRFB PSTL2KEEP, P0, [X0,Z0.S,SXTW]
prfb pstl2keep, p0, [x0,z0.s,sxtw #0]
prfb pstl2strm, p0, [x0,z0.s,sxtw]
PRFB PSTL2STRM, P0, [X0,Z0.S,SXTW]
prfb pstl2strm, p0, [x0,z0.s,sxtw #0]
prfb pstl3keep, p0, [x0,z0.s,sxtw]
PRFB PSTL3KEEP, P0, [X0,Z0.S,SXTW]
prfb pstl3keep, p0, [x0,z0.s,sxtw #0]
prfb pstl3strm, p0, [x0,z0.s,sxtw]
PRFB PSTL3STRM, P0, [X0,Z0.S,SXTW]
prfb pstl3strm, p0, [x0,z0.s,sxtw #0]
prfb #14, p0, [x0,z0.s,sxtw]
PRFB #14, P0, [X0,Z0.S,SXTW]
prfb #14, p0, [x0,z0.s,sxtw #0]
prfb #15, p0, [x0,z0.s,sxtw]
PRFB #15, P0, [X0,Z0.S,SXTW]
prfb #15, p0, [x0,z0.s,sxtw #0]
prfb pldl1keep, p2, [x0,z0.s,sxtw]
PRFB PLDL1KEEP, P2, [X0,Z0.S,SXTW]
prfb pldl1keep, p2, [x0,z0.s,sxtw #0]
prfb pldl1keep, p7, [x0,z0.s,sxtw]
PRFB PLDL1KEEP, P7, [X0,Z0.S,SXTW]
prfb pldl1keep, p7, [x0,z0.s,sxtw #0]
prfb pldl1keep, p0, [x3,z0.s,sxtw]
PRFB PLDL1KEEP, P0, [X3,Z0.S,SXTW]
prfb pldl1keep, p0, [x3,z0.s,sxtw #0]
prfb pldl1keep, p0, [sp,z0.s,sxtw]
PRFB PLDL1KEEP, P0, [SP,Z0.S,SXTW]
prfb pldl1keep, p0, [sp,z0.s,sxtw #0]
prfb pldl1keep, p0, [x0,z4.s,sxtw]
PRFB PLDL1KEEP, P0, [X0,Z4.S,SXTW]
prfb pldl1keep, p0, [x0,z4.s,sxtw #0]
prfb pldl1keep, p0, [x0,z31.s,sxtw]
PRFB PLDL1KEEP, P0, [X0,Z31.S,SXTW]
prfb pldl1keep, p0, [x0,z31.s,sxtw #0]
prfb pldl1keep, p0, [x0,z0.d,uxtw]
PRFB PLDL1KEEP, P0, [X0,Z0.D,UXTW]
prfb pldl1keep, p0, [x0,z0.d,uxtw #0]
prfb pldl1strm, p0, [x0,z0.d,uxtw]
PRFB PLDL1STRM, P0, [X0,Z0.D,UXTW]
prfb pldl1strm, p0, [x0,z0.d,uxtw #0]
prfb pldl2keep, p0, [x0,z0.d,uxtw]
PRFB PLDL2KEEP, P0, [X0,Z0.D,UXTW]
prfb pldl2keep, p0, [x0,z0.d,uxtw #0]
prfb pldl2strm, p0, [x0,z0.d,uxtw]
PRFB PLDL2STRM, P0, [X0,Z0.D,UXTW]
prfb pldl2strm, p0, [x0,z0.d,uxtw #0]
prfb pldl3keep, p0, [x0,z0.d,uxtw]
PRFB PLDL3KEEP, P0, [X0,Z0.D,UXTW]
prfb pldl3keep, p0, [x0,z0.d,uxtw #0]
prfb pldl3strm, p0, [x0,z0.d,uxtw]
PRFB PLDL3STRM, P0, [X0,Z0.D,UXTW]
prfb pldl3strm, p0, [x0,z0.d,uxtw #0]
prfb #6, p0, [x0,z0.d,uxtw]
PRFB #6, P0, [X0,Z0.D,UXTW]
prfb #6, p0, [x0,z0.d,uxtw #0]
prfb #7, p0, [x0,z0.d,uxtw]
PRFB #7, P0, [X0,Z0.D,UXTW]
prfb #7, p0, [x0,z0.d,uxtw #0]
prfb pstl1keep, p0, [x0,z0.d,uxtw]
PRFB PSTL1KEEP, P0, [X0,Z0.D,UXTW]
prfb pstl1keep, p0, [x0,z0.d,uxtw #0]
prfb pstl1strm, p0, [x0,z0.d,uxtw]
PRFB PSTL1STRM, P0, [X0,Z0.D,UXTW]
prfb pstl1strm, p0, [x0,z0.d,uxtw #0]
prfb pstl2keep, p0, [x0,z0.d,uxtw]
PRFB PSTL2KEEP, P0, [X0,Z0.D,UXTW]
prfb pstl2keep, p0, [x0,z0.d,uxtw #0]
prfb pstl2strm, p0, [x0,z0.d,uxtw]
PRFB PSTL2STRM, P0, [X0,Z0.D,UXTW]
prfb pstl2strm, p0, [x0,z0.d,uxtw #0]
prfb pstl3keep, p0, [x0,z0.d,uxtw]
PRFB PSTL3KEEP, P0, [X0,Z0.D,UXTW]
prfb pstl3keep, p0, [x0,z0.d,uxtw #0]
prfb pstl3strm, p0, [x0,z0.d,uxtw]
PRFB PSTL3STRM, P0, [X0,Z0.D,UXTW]
prfb pstl3strm, p0, [x0,z0.d,uxtw #0]
prfb #14, p0, [x0,z0.d,uxtw]
PRFB #14, P0, [X0,Z0.D,UXTW]
prfb #14, p0, [x0,z0.d,uxtw #0]
prfb #15, p0, [x0,z0.d,uxtw]
PRFB #15, P0, [X0,Z0.D,UXTW]
prfb #15, p0, [x0,z0.d,uxtw #0]
prfb pldl1keep, p2, [x0,z0.d,uxtw]
PRFB PLDL1KEEP, P2, [X0,Z0.D,UXTW]
prfb pldl1keep, p2, [x0,z0.d,uxtw #0]
prfb pldl1keep, p7, [x0,z0.d,uxtw]
PRFB PLDL1KEEP, P7, [X0,Z0.D,UXTW]
prfb pldl1keep, p7, [x0,z0.d,uxtw #0]
prfb pldl1keep, p0, [x3,z0.d,uxtw]
PRFB PLDL1KEEP, P0, [X3,Z0.D,UXTW]
prfb pldl1keep, p0, [x3,z0.d,uxtw #0]
prfb pldl1keep, p0, [sp,z0.d,uxtw]
PRFB PLDL1KEEP, P0, [SP,Z0.D,UXTW]
prfb pldl1keep, p0, [sp,z0.d,uxtw #0]
prfb pldl1keep, p0, [x0,z4.d,uxtw]
PRFB PLDL1KEEP, P0, [X0,Z4.D,UXTW]
prfb pldl1keep, p0, [x0,z4.d,uxtw #0]
prfb pldl1keep, p0, [x0,z31.d,uxtw]
PRFB PLDL1KEEP, P0, [X0,Z31.D,UXTW]
prfb pldl1keep, p0, [x0,z31.d,uxtw #0]
prfb pldl1keep, p0, [x0,z0.d,sxtw]
PRFB PLDL1KEEP, P0, [X0,Z0.D,SXTW]
prfb pldl1keep, p0, [x0,z0.d,sxtw #0]
prfb pldl1strm, p0, [x0,z0.d,sxtw]
PRFB PLDL1STRM, P0, [X0,Z0.D,SXTW]
prfb pldl1strm, p0, [x0,z0.d,sxtw #0]
prfb pldl2keep, p0, [x0,z0.d,sxtw]
PRFB PLDL2KEEP, P0, [X0,Z0.D,SXTW]
prfb pldl2keep, p0, [x0,z0.d,sxtw #0]
prfb pldl2strm, p0, [x0,z0.d,sxtw]
PRFB PLDL2STRM, P0, [X0,Z0.D,SXTW]
prfb pldl2strm, p0, [x0,z0.d,sxtw #0]
prfb pldl3keep, p0, [x0,z0.d,sxtw]
PRFB PLDL3KEEP, P0, [X0,Z0.D,SXTW]
prfb pldl3keep, p0, [x0,z0.d,sxtw #0]
prfb pldl3strm, p0, [x0,z0.d,sxtw]
PRFB PLDL3STRM, P0, [X0,Z0.D,SXTW]
prfb pldl3strm, p0, [x0,z0.d,sxtw #0]
prfb #6, p0, [x0,z0.d,sxtw]
PRFB #6, P0, [X0,Z0.D,SXTW]
prfb #6, p0, [x0,z0.d,sxtw #0]
prfb #7, p0, [x0,z0.d,sxtw]
PRFB #7, P0, [X0,Z0.D,SXTW]
prfb #7, p0, [x0,z0.d,sxtw #0]
prfb pstl1keep, p0, [x0,z0.d,sxtw]
PRFB PSTL1KEEP, P0, [X0,Z0.D,SXTW]
prfb pstl1keep, p0, [x0,z0.d,sxtw #0]
prfb pstl1strm, p0, [x0,z0.d,sxtw]
PRFB PSTL1STRM, P0, [X0,Z0.D,SXTW]
prfb pstl1strm, p0, [x0,z0.d,sxtw #0]
prfb pstl2keep, p0, [x0,z0.d,sxtw]
PRFB PSTL2KEEP, P0, [X0,Z0.D,SXTW]
prfb pstl2keep, p0, [x0,z0.d,sxtw #0]
prfb pstl2strm, p0, [x0,z0.d,sxtw]
PRFB PSTL2STRM, P0, [X0,Z0.D,SXTW]
prfb pstl2strm, p0, [x0,z0.d,sxtw #0]
prfb pstl3keep, p0, [x0,z0.d,sxtw]
PRFB PSTL3KEEP, P0, [X0,Z0.D,SXTW]
prfb pstl3keep, p0, [x0,z0.d,sxtw #0]
prfb pstl3strm, p0, [x0,z0.d,sxtw]
PRFB PSTL3STRM, P0, [X0,Z0.D,SXTW]
prfb pstl3strm, p0, [x0,z0.d,sxtw #0]
prfb #14, p0, [x0,z0.d,sxtw]
PRFB #14, P0, [X0,Z0.D,SXTW]
prfb #14, p0, [x0,z0.d,sxtw #0]
prfb #15, p0, [x0,z0.d,sxtw]
PRFB #15, P0, [X0,Z0.D,SXTW]
prfb #15, p0, [x0,z0.d,sxtw #0]
prfb pldl1keep, p2, [x0,z0.d,sxtw]
PRFB PLDL1KEEP, P2, [X0,Z0.D,SXTW]
prfb pldl1keep, p2, [x0,z0.d,sxtw #0]
prfb pldl1keep, p7, [x0,z0.d,sxtw]
PRFB PLDL1KEEP, P7, [X0,Z0.D,SXTW]
prfb pldl1keep, p7, [x0,z0.d,sxtw #0]
prfb pldl1keep, p0, [x3,z0.d,sxtw]
PRFB PLDL1KEEP, P0, [X3,Z0.D,SXTW]
prfb pldl1keep, p0, [x3,z0.d,sxtw #0]
prfb pldl1keep, p0, [sp,z0.d,sxtw]
PRFB PLDL1KEEP, P0, [SP,Z0.D,SXTW]
prfb pldl1keep, p0, [sp,z0.d,sxtw #0]
prfb pldl1keep, p0, [x0,z4.d,sxtw]
PRFB PLDL1KEEP, P0, [X0,Z4.D,SXTW]
prfb pldl1keep, p0, [x0,z4.d,sxtw #0]
prfb pldl1keep, p0, [x0,z31.d,sxtw]
PRFB PLDL1KEEP, P0, [X0,Z31.D,SXTW]
prfb pldl1keep, p0, [x0,z31.d,sxtw #0]
prfb pldl1keep, p0, [x0,z0.d]
PRFB PLDL1KEEP, P0, [X0,Z0.D]
prfb pldl1keep, p0, [x0,z0.d,lsl #0]
prfb pldl1strm, p0, [x0,z0.d]
PRFB PLDL1STRM, P0, [X0,Z0.D]
prfb pldl1strm, p0, [x0,z0.d,lsl #0]
prfb pldl2keep, p0, [x0,z0.d]
PRFB PLDL2KEEP, P0, [X0,Z0.D]
prfb pldl2keep, p0, [x0,z0.d,lsl #0]
prfb pldl2strm, p0, [x0,z0.d]
PRFB PLDL2STRM, P0, [X0,Z0.D]
prfb pldl2strm, p0, [x0,z0.d,lsl #0]
prfb pldl3keep, p0, [x0,z0.d]
PRFB PLDL3KEEP, P0, [X0,Z0.D]
prfb pldl3keep, p0, [x0,z0.d,lsl #0]
prfb pldl3strm, p0, [x0,z0.d]
PRFB PLDL3STRM, P0, [X0,Z0.D]
prfb pldl3strm, p0, [x0,z0.d,lsl #0]
prfb #6, p0, [x0,z0.d]
PRFB #6, P0, [X0,Z0.D]
prfb #6, p0, [x0,z0.d,lsl #0]
prfb #7, p0, [x0,z0.d]
PRFB #7, P0, [X0,Z0.D]
prfb #7, p0, [x0,z0.d,lsl #0]
prfb pstl1keep, p0, [x0,z0.d]
PRFB PSTL1KEEP, P0, [X0,Z0.D]
prfb pstl1keep, p0, [x0,z0.d,lsl #0]
prfb pstl1strm, p0, [x0,z0.d]
PRFB PSTL1STRM, P0, [X0,Z0.D]
prfb pstl1strm, p0, [x0,z0.d,lsl #0]
prfb pstl2keep, p0, [x0,z0.d]
PRFB PSTL2KEEP, P0, [X0,Z0.D]
prfb pstl2keep, p0, [x0,z0.d,lsl #0]
prfb pstl2strm, p0, [x0,z0.d]
PRFB PSTL2STRM, P0, [X0,Z0.D]
prfb pstl2strm, p0, [x0,z0.d,lsl #0]
prfb pstl3keep, p0, [x0,z0.d]
PRFB PSTL3KEEP, P0, [X0,Z0.D]
prfb pstl3keep, p0, [x0,z0.d,lsl #0]
prfb pstl3strm, p0, [x0,z0.d]
PRFB PSTL3STRM, P0, [X0,Z0.D]
prfb pstl3strm, p0, [x0,z0.d,lsl #0]
prfb #14, p0, [x0,z0.d]
PRFB #14, P0, [X0,Z0.D]
prfb #14, p0, [x0,z0.d,lsl #0]
prfb #15, p0, [x0,z0.d]
PRFB #15, P0, [X0,Z0.D]
prfb #15, p0, [x0,z0.d,lsl #0]
prfb pldl1keep, p2, [x0,z0.d]
PRFB PLDL1KEEP, P2, [X0,Z0.D]
prfb pldl1keep, p2, [x0,z0.d,lsl #0]
prfb pldl1keep, p7, [x0,z0.d]
PRFB PLDL1KEEP, P7, [X0,Z0.D]
prfb pldl1keep, p7, [x0,z0.d,lsl #0]
prfb pldl1keep, p0, [x3,z0.d]
PRFB PLDL1KEEP, P0, [X3,Z0.D]
prfb pldl1keep, p0, [x3,z0.d,lsl #0]
prfb pldl1keep, p0, [sp,z0.d]
PRFB PLDL1KEEP, P0, [SP,Z0.D]
prfb pldl1keep, p0, [sp,z0.d,lsl #0]
prfb pldl1keep, p0, [x0,z4.d]
PRFB PLDL1KEEP, P0, [X0,Z4.D]
prfb pldl1keep, p0, [x0,z4.d,lsl #0]
prfb pldl1keep, p0, [x0,z31.d]
PRFB PLDL1KEEP, P0, [X0,Z31.D]
prfb pldl1keep, p0, [x0,z31.d,lsl #0]
prfb pldl1keep, p0, [z0.s,#0]
PRFB PLDL1KEEP, P0, [Z0.S,#0]
prfb pldl1keep, p0, [z0.s]
prfb pldl1strm, p0, [z0.s,#0]
PRFB PLDL1STRM, P0, [Z0.S,#0]
prfb pldl1strm, p0, [z0.s]
prfb pldl2keep, p0, [z0.s,#0]
PRFB PLDL2KEEP, P0, [Z0.S,#0]
prfb pldl2keep, p0, [z0.s]
prfb pldl2strm, p0, [z0.s,#0]
PRFB PLDL2STRM, P0, [Z0.S,#0]
prfb pldl2strm, p0, [z0.s]
prfb pldl3keep, p0, [z0.s,#0]
PRFB PLDL3KEEP, P0, [Z0.S,#0]
prfb pldl3keep, p0, [z0.s]
prfb pldl3strm, p0, [z0.s,#0]
PRFB PLDL3STRM, P0, [Z0.S,#0]
prfb pldl3strm, p0, [z0.s]
prfb #6, p0, [z0.s,#0]
PRFB #6, P0, [Z0.S,#0]
prfb #6, p0, [z0.s]
prfb #7, p0, [z0.s,#0]
PRFB #7, P0, [Z0.S,#0]
prfb #7, p0, [z0.s]
prfb pstl1keep, p0, [z0.s,#0]
PRFB PSTL1KEEP, P0, [Z0.S,#0]
prfb pstl1keep, p0, [z0.s]
prfb pstl1strm, p0, [z0.s,#0]
PRFB PSTL1STRM, P0, [Z0.S,#0]
prfb pstl1strm, p0, [z0.s]
prfb pstl2keep, p0, [z0.s,#0]
PRFB PSTL2KEEP, P0, [Z0.S,#0]
prfb pstl2keep, p0, [z0.s]
prfb pstl2strm, p0, [z0.s,#0]
PRFB PSTL2STRM, P0, [Z0.S,#0]
prfb pstl2strm, p0, [z0.s]
prfb pstl3keep, p0, [z0.s,#0]
PRFB PSTL3KEEP, P0, [Z0.S,#0]
prfb pstl3keep, p0, [z0.s]
prfb pstl3strm, p0, [z0.s,#0]
PRFB PSTL3STRM, P0, [Z0.S,#0]
prfb pstl3strm, p0, [z0.s]
prfb #14, p0, [z0.s,#0]
PRFB #14, P0, [Z0.S,#0]
prfb #14, p0, [z0.s]
prfb #15, p0, [z0.s,#0]
PRFB #15, P0, [Z0.S,#0]
prfb #15, p0, [z0.s]
prfb pldl1keep, p2, [z0.s,#0]
PRFB PLDL1KEEP, P2, [Z0.S,#0]
prfb pldl1keep, p2, [z0.s]
prfb pldl1keep, p7, [z0.s,#0]
PRFB PLDL1KEEP, P7, [Z0.S,#0]
prfb pldl1keep, p7, [z0.s]
prfb pldl1keep, p0, [z3.s,#0]
PRFB PLDL1KEEP, P0, [Z3.S,#0]
prfb pldl1keep, p0, [z3.s]
prfb pldl1keep, p0, [z31.s,#0]
PRFB PLDL1KEEP, P0, [Z31.S,#0]
prfb pldl1keep, p0, [z31.s]
prfb pldl1keep, p0, [z0.s,#15]
PRFB PLDL1KEEP, P0, [Z0.S,#15]
prfb pldl1keep, p0, [z0.s,#16]
PRFB PLDL1KEEP, P0, [Z0.S,#16]
prfb pldl1keep, p0, [z0.s,#17]
PRFB PLDL1KEEP, P0, [Z0.S,#17]
prfb pldl1keep, p0, [z0.s,#31]
PRFB PLDL1KEEP, P0, [Z0.S,#31]
prfb pldl1keep, p0, [x0,#0]
PRFB PLDL1KEEP, P0, [X0,#0]
prfb pldl1keep, p0, [x0,#0,mul vl]
prfb pldl1keep, p0, [x0]
prfb pldl1strm, p0, [x0,#0]
PRFB PLDL1STRM, P0, [X0,#0]
prfb pldl1strm, p0, [x0,#0,mul vl]
prfb pldl1strm, p0, [x0]
prfb pldl2keep, p0, [x0,#0]
PRFB PLDL2KEEP, P0, [X0,#0]
prfb pldl2keep, p0, [x0,#0,mul vl]
prfb pldl2keep, p0, [x0]
prfb pldl2strm, p0, [x0,#0]
PRFB PLDL2STRM, P0, [X0,#0]
prfb pldl2strm, p0, [x0,#0,mul vl]
prfb pldl2strm, p0, [x0]
prfb pldl3keep, p0, [x0,#0]
PRFB PLDL3KEEP, P0, [X0,#0]
prfb pldl3keep, p0, [x0,#0,mul vl]
prfb pldl3keep, p0, [x0]
prfb pldl3strm, p0, [x0,#0]
PRFB PLDL3STRM, P0, [X0,#0]
prfb pldl3strm, p0, [x0,#0,mul vl]
prfb pldl3strm, p0, [x0]
prfb #6, p0, [x0,#0]
PRFB #6, P0, [X0,#0]
prfb #6, p0, [x0,#0,mul vl]
prfb #6, p0, [x0]
prfb #7, p0, [x0,#0]
PRFB #7, P0, [X0,#0]
prfb #7, p0, [x0,#0,mul vl]
prfb #7, p0, [x0]
prfb pstl1keep, p0, [x0,#0]
PRFB PSTL1KEEP, P0, [X0,#0]
prfb pstl1keep, p0, [x0,#0,mul vl]
prfb pstl1keep, p0, [x0]
prfb pstl1strm, p0, [x0,#0]
PRFB PSTL1STRM, P0, [X0,#0]
prfb pstl1strm, p0, [x0,#0,mul vl]
prfb pstl1strm, p0, [x0]
prfb pstl2keep, p0, [x0,#0]
PRFB PSTL2KEEP, P0, [X0,#0]
prfb pstl2keep, p0, [x0,#0,mul vl]
prfb pstl2keep, p0, [x0]
prfb pstl2strm, p0, [x0,#0]
PRFB PSTL2STRM, P0, [X0,#0]
prfb pstl2strm, p0, [x0,#0,mul vl]
prfb pstl2strm, p0, [x0]
prfb pstl3keep, p0, [x0,#0]
PRFB PSTL3KEEP, P0, [X0,#0]
prfb pstl3keep, p0, [x0,#0,mul vl]
prfb pstl3keep, p0, [x0]
prfb pstl3strm, p0, [x0,#0]
PRFB PSTL3STRM, P0, [X0,#0]
prfb pstl3strm, p0, [x0,#0,mul vl]
prfb pstl3strm, p0, [x0]
prfb #14, p0, [x0,#0]
PRFB #14, P0, [X0,#0]
prfb #14, p0, [x0,#0,mul vl]
prfb #14, p0, [x0]
prfb #15, p0, [x0,#0]
PRFB #15, P0, [X0,#0]
prfb #15, p0, [x0,#0,mul vl]
prfb #15, p0, [x0]
prfb pldl1keep, p2, [x0,#0]
PRFB PLDL1KEEP, P2, [X0,#0]
prfb pldl1keep, p2, [x0,#0,mul vl]
prfb pldl1keep, p2, [x0]
prfb pldl1keep, p7, [x0,#0]
PRFB PLDL1KEEP, P7, [X0,#0]
prfb pldl1keep, p7, [x0,#0,mul vl]
prfb pldl1keep, p7, [x0]
prfb pldl1keep, p0, [x3,#0]
PRFB PLDL1KEEP, P0, [X3,#0]
prfb pldl1keep, p0, [x3,#0,mul vl]
prfb pldl1keep, p0, [x3]
prfb pldl1keep, p0, [sp,#0]
PRFB PLDL1KEEP, P0, [SP,#0]
prfb pldl1keep, p0, [sp,#0,mul vl]
prfb pldl1keep, p0, [sp]
prfb pldl1keep, p0, [x0,#31,mul vl]
PRFB PLDL1KEEP, P0, [X0,#31,MUL VL]
prfb pldl1keep, p0, [x0,#-32,mul vl]
PRFB PLDL1KEEP, P0, [X0,#-32,MUL VL]
prfb pldl1keep, p0, [x0,#-31,mul vl]
PRFB PLDL1KEEP, P0, [X0,#-31,MUL VL]
prfb pldl1keep, p0, [x0,#-1,mul vl]
PRFB PLDL1KEEP, P0, [X0,#-1,MUL VL]
prfb pldl1keep, p0, [z0.d,#0]
PRFB PLDL1KEEP, P0, [Z0.D,#0]
prfb pldl1keep, p0, [z0.d]
prfb pldl1strm, p0, [z0.d,#0]
PRFB PLDL1STRM, P0, [Z0.D,#0]
prfb pldl1strm, p0, [z0.d]
prfb pldl2keep, p0, [z0.d,#0]
PRFB PLDL2KEEP, P0, [Z0.D,#0]
prfb pldl2keep, p0, [z0.d]
prfb pldl2strm, p0, [z0.d,#0]
PRFB PLDL2STRM, P0, [Z0.D,#0]
prfb pldl2strm, p0, [z0.d]
prfb pldl3keep, p0, [z0.d,#0]
PRFB PLDL3KEEP, P0, [Z0.D,#0]
prfb pldl3keep, p0, [z0.d]
prfb pldl3strm, p0, [z0.d,#0]
PRFB PLDL3STRM, P0, [Z0.D,#0]
prfb pldl3strm, p0, [z0.d]
prfb #6, p0, [z0.d,#0]
PRFB #6, P0, [Z0.D,#0]
prfb #6, p0, [z0.d]
prfb #7, p0, [z0.d,#0]
PRFB #7, P0, [Z0.D,#0]
prfb #7, p0, [z0.d]
prfb pstl1keep, p0, [z0.d,#0]
PRFB PSTL1KEEP, P0, [Z0.D,#0]
prfb pstl1keep, p0, [z0.d]
prfb pstl1strm, p0, [z0.d,#0]
PRFB PSTL1STRM, P0, [Z0.D,#0]
prfb pstl1strm, p0, [z0.d]
prfb pstl2keep, p0, [z0.d,#0]
PRFB PSTL2KEEP, P0, [Z0.D,#0]
prfb pstl2keep, p0, [z0.d]
prfb pstl2strm, p0, [z0.d,#0]
PRFB PSTL2STRM, P0, [Z0.D,#0]
prfb pstl2strm, p0, [z0.d]
prfb pstl3keep, p0, [z0.d,#0]
PRFB PSTL3KEEP, P0, [Z0.D,#0]
prfb pstl3keep, p0, [z0.d]
prfb pstl3strm, p0, [z0.d,#0]
PRFB PSTL3STRM, P0, [Z0.D,#0]
prfb pstl3strm, p0, [z0.d]
prfb #14, p0, [z0.d,#0]
PRFB #14, P0, [Z0.D,#0]
prfb #14, p0, [z0.d]
prfb #15, p0, [z0.d,#0]
PRFB #15, P0, [Z0.D,#0]
prfb #15, p0, [z0.d]
prfb pldl1keep, p2, [z0.d,#0]
PRFB PLDL1KEEP, P2, [Z0.D,#0]
prfb pldl1keep, p2, [z0.d]
prfb pldl1keep, p7, [z0.d,#0]
PRFB PLDL1KEEP, P7, [Z0.D,#0]
prfb pldl1keep, p7, [z0.d]
prfb pldl1keep, p0, [z3.d,#0]
PRFB PLDL1KEEP, P0, [Z3.D,#0]
prfb pldl1keep, p0, [z3.d]
prfb pldl1keep, p0, [z31.d,#0]
PRFB PLDL1KEEP, P0, [Z31.D,#0]
prfb pldl1keep, p0, [z31.d]
prfb pldl1keep, p0, [z0.d,#15]
PRFB PLDL1KEEP, P0, [Z0.D,#15]
prfb pldl1keep, p0, [z0.d,#16]
PRFB PLDL1KEEP, P0, [Z0.D,#16]
prfb pldl1keep, p0, [z0.d,#17]
PRFB PLDL1KEEP, P0, [Z0.D,#17]
prfb pldl1keep, p0, [z0.d,#31]
PRFB PLDL1KEEP, P0, [Z0.D,#31]
prfd pldl1keep, p0, [x0,z0.s,uxtw #3]
PRFD PLDL1KEEP, P0, [X0,Z0.S,UXTW #3]
prfd pldl1strm, p0, [x0,z0.s,uxtw #3]
PRFD PLDL1STRM, P0, [X0,Z0.S,UXTW #3]
prfd pldl2keep, p0, [x0,z0.s,uxtw #3]
PRFD PLDL2KEEP, P0, [X0,Z0.S,UXTW #3]
prfd pldl2strm, p0, [x0,z0.s,uxtw #3]
PRFD PLDL2STRM, P0, [X0,Z0.S,UXTW #3]
prfd pldl3keep, p0, [x0,z0.s,uxtw #3]
PRFD PLDL3KEEP, P0, [X0,Z0.S,UXTW #3]
prfd pldl3strm, p0, [x0,z0.s,uxtw #3]
PRFD PLDL3STRM, P0, [X0,Z0.S,UXTW #3]
prfd #6, p0, [x0,z0.s,uxtw #3]
PRFD #6, P0, [X0,Z0.S,UXTW #3]
prfd #7, p0, [x0,z0.s,uxtw #3]
PRFD #7, P0, [X0,Z0.S,UXTW #3]
prfd pstl1keep, p0, [x0,z0.s,uxtw #3]
PRFD PSTL1KEEP, P0, [X0,Z0.S,UXTW #3]
prfd pstl1strm, p0, [x0,z0.s,uxtw #3]
PRFD PSTL1STRM, P0, [X0,Z0.S,UXTW #3]
prfd pstl2keep, p0, [x0,z0.s,uxtw #3]
PRFD PSTL2KEEP, P0, [X0,Z0.S,UXTW #3]
prfd pstl2strm, p0, [x0,z0.s,uxtw #3]
PRFD PSTL2STRM, P0, [X0,Z0.S,UXTW #3]
prfd pstl3keep, p0, [x0,z0.s,uxtw #3]
PRFD PSTL3KEEP, P0, [X0,Z0.S,UXTW #3]
prfd pstl3strm, p0, [x0,z0.s,uxtw #3]
PRFD PSTL3STRM, P0, [X0,Z0.S,UXTW #3]
prfd #14, p0, [x0,z0.s,uxtw #3]
PRFD #14, P0, [X0,Z0.S,UXTW #3]
prfd #15, p0, [x0,z0.s,uxtw #3]
PRFD #15, P0, [X0,Z0.S,UXTW #3]
prfd pldl1keep, p2, [x0,z0.s,uxtw #3]
PRFD PLDL1KEEP, P2, [X0,Z0.S,UXTW #3]
prfd pldl1keep, p7, [x0,z0.s,uxtw #3]
PRFD PLDL1KEEP, P7, [X0,Z0.S,UXTW #3]
prfd pldl1keep, p0, [x3,z0.s,uxtw #3]
PRFD PLDL1KEEP, P0, [X3,Z0.S,UXTW #3]
prfd pldl1keep, p0, [sp,z0.s,uxtw #3]
PRFD PLDL1KEEP, P0, [SP,Z0.S,UXTW #3]
prfd pldl1keep, p0, [x0,z4.s,uxtw #3]
PRFD PLDL1KEEP, P0, [X0,Z4.S,UXTW #3]
prfd pldl1keep, p0, [x0,z31.s,uxtw #3]
PRFD PLDL1KEEP, P0, [X0,Z31.S,UXTW #3]
prfd pldl1keep, p0, [x0,z0.s,sxtw #3]
PRFD PLDL1KEEP, P0, [X0,Z0.S,SXTW #3]
prfd pldl1strm, p0, [x0,z0.s,sxtw #3]
PRFD PLDL1STRM, P0, [X0,Z0.S,SXTW #3]
prfd pldl2keep, p0, [x0,z0.s,sxtw #3]
PRFD PLDL2KEEP, P0, [X0,Z0.S,SXTW #3]
prfd pldl2strm, p0, [x0,z0.s,sxtw #3]
PRFD PLDL2STRM, P0, [X0,Z0.S,SXTW #3]
prfd pldl3keep, p0, [x0,z0.s,sxtw #3]
PRFD PLDL3KEEP, P0, [X0,Z0.S,SXTW #3]
prfd pldl3strm, p0, [x0,z0.s,sxtw #3]
PRFD PLDL3STRM, P0, [X0,Z0.S,SXTW #3]
prfd #6, p0, [x0,z0.s,sxtw #3]
PRFD #6, P0, [X0,Z0.S,SXTW #3]
prfd #7, p0, [x0,z0.s,sxtw #3]
PRFD #7, P0, [X0,Z0.S,SXTW #3]
prfd pstl1keep, p0, [x0,z0.s,sxtw #3]
PRFD PSTL1KEEP, P0, [X0,Z0.S,SXTW #3]
prfd pstl1strm, p0, [x0,z0.s,sxtw #3]
PRFD PSTL1STRM, P0, [X0,Z0.S,SXTW #3]
prfd pstl2keep, p0, [x0,z0.s,sxtw #3]
PRFD PSTL2KEEP, P0, [X0,Z0.S,SXTW #3]
prfd pstl2strm, p0, [x0,z0.s,sxtw #3]
PRFD PSTL2STRM, P0, [X0,Z0.S,SXTW #3]
prfd pstl3keep, p0, [x0,z0.s,sxtw #3]
PRFD PSTL3KEEP, P0, [X0,Z0.S,SXTW #3]
prfd pstl3strm, p0, [x0,z0.s,sxtw #3]
PRFD PSTL3STRM, P0, [X0,Z0.S,SXTW #3]
prfd #14, p0, [x0,z0.s,sxtw #3]
PRFD #14, P0, [X0,Z0.S,SXTW #3]
prfd #15, p0, [x0,z0.s,sxtw #3]
PRFD #15, P0, [X0,Z0.S,SXTW #3]
prfd pldl1keep, p2, [x0,z0.s,sxtw #3]
PRFD PLDL1KEEP, P2, [X0,Z0.S,SXTW #3]
prfd pldl1keep, p7, [x0,z0.s,sxtw #3]
PRFD PLDL1KEEP, P7, [X0,Z0.S,SXTW #3]
prfd pldl1keep, p0, [x3,z0.s,sxtw #3]
PRFD PLDL1KEEP, P0, [X3,Z0.S,SXTW #3]
prfd pldl1keep, p0, [sp,z0.s,sxtw #3]
PRFD PLDL1KEEP, P0, [SP,Z0.S,SXTW #3]
prfd pldl1keep, p0, [x0,z4.s,sxtw #3]
PRFD PLDL1KEEP, P0, [X0,Z4.S,SXTW #3]
prfd pldl1keep, p0, [x0,z31.s,sxtw #3]
PRFD PLDL1KEEP, P0, [X0,Z31.S,SXTW #3]
prfd pldl1keep, p0, [x0,x0,lsl #3]
PRFD PLDL1KEEP, P0, [X0,X0,LSL #3]
prfd pldl1strm, p0, [x0,x0,lsl #3]
PRFD PLDL1STRM, P0, [X0,X0,LSL #3]
prfd pldl2keep, p0, [x0,x0,lsl #3]
PRFD PLDL2KEEP, P0, [X0,X0,LSL #3]
prfd pldl2strm, p0, [x0,x0,lsl #3]
PRFD PLDL2STRM, P0, [X0,X0,LSL #3]
prfd pldl3keep, p0, [x0,x0,lsl #3]
PRFD PLDL3KEEP, P0, [X0,X0,LSL #3]
prfd pldl3strm, p0, [x0,x0,lsl #3]
PRFD PLDL3STRM, P0, [X0,X0,LSL #3]
prfd #6, p0, [x0,x0,lsl #3]
PRFD #6, P0, [X0,X0,LSL #3]
prfd #7, p0, [x0,x0,lsl #3]
PRFD #7, P0, [X0,X0,LSL #3]
prfd pstl1keep, p0, [x0,x0,lsl #3]
PRFD PSTL1KEEP, P0, [X0,X0,LSL #3]
prfd pstl1strm, p0, [x0,x0,lsl #3]
PRFD PSTL1STRM, P0, [X0,X0,LSL #3]
prfd pstl2keep, p0, [x0,x0,lsl #3]
PRFD PSTL2KEEP, P0, [X0,X0,LSL #3]
prfd pstl2strm, p0, [x0,x0,lsl #3]
PRFD PSTL2STRM, P0, [X0,X0,LSL #3]
prfd pstl3keep, p0, [x0,x0,lsl #3]
PRFD PSTL3KEEP, P0, [X0,X0,LSL #3]
prfd pstl3strm, p0, [x0,x0,lsl #3]
PRFD PSTL3STRM, P0, [X0,X0,LSL #3]
prfd #14, p0, [x0,x0,lsl #3]
PRFD #14, P0, [X0,X0,LSL #3]
prfd #15, p0, [x0,x0,lsl #3]
PRFD #15, P0, [X0,X0,LSL #3]
prfd pldl1keep, p2, [x0,x0,lsl #3]
PRFD PLDL1KEEP, P2, [X0,X0,LSL #3]
prfd pldl1keep, p7, [x0,x0,lsl #3]
PRFD PLDL1KEEP, P7, [X0,X0,LSL #3]
prfd pldl1keep, p0, [x3,x0,lsl #3]
PRFD PLDL1KEEP, P0, [X3,X0,LSL #3]
prfd pldl1keep, p0, [sp,x0,lsl #3]
PRFD PLDL1KEEP, P0, [SP,X0,LSL #3]
prfd pldl1keep, p0, [x0,x4,lsl #3]
PRFD PLDL1KEEP, P0, [X0,X4,LSL #3]
prfd pldl1keep, p0, [x0,x30,lsl #3]
PRFD PLDL1KEEP, P0, [X0,X30,LSL #3]
prfd pldl1keep, p0, [x0,z0.d,uxtw #3]
PRFD PLDL1KEEP, P0, [X0,Z0.D,UXTW #3]
prfd pldl1strm, p0, [x0,z0.d,uxtw #3]
PRFD PLDL1STRM, P0, [X0,Z0.D,UXTW #3]
prfd pldl2keep, p0, [x0,z0.d,uxtw #3]
PRFD PLDL2KEEP, P0, [X0,Z0.D,UXTW #3]
prfd pldl2strm, p0, [x0,z0.d,uxtw #3]
PRFD PLDL2STRM, P0, [X0,Z0.D,UXTW #3]
prfd pldl3keep, p0, [x0,z0.d,uxtw #3]
PRFD PLDL3KEEP, P0, [X0,Z0.D,UXTW #3]
prfd pldl3strm, p0, [x0,z0.d,uxtw #3]
PRFD PLDL3STRM, P0, [X0,Z0.D,UXTW #3]
prfd #6, p0, [x0,z0.d,uxtw #3]
PRFD #6, P0, [X0,Z0.D,UXTW #3]
prfd #7, p0, [x0,z0.d,uxtw #3]
PRFD #7, P0, [X0,Z0.D,UXTW #3]
prfd pstl1keep, p0, [x0,z0.d,uxtw #3]
PRFD PSTL1KEEP, P0, [X0,Z0.D,UXTW #3]
prfd pstl1strm, p0, [x0,z0.d,uxtw #3]
PRFD PSTL1STRM, P0, [X0,Z0.D,UXTW #3]
prfd pstl2keep, p0, [x0,z0.d,uxtw #3]
PRFD PSTL2KEEP, P0, [X0,Z0.D,UXTW #3]
prfd pstl2strm, p0, [x0,z0.d,uxtw #3]
PRFD PSTL2STRM, P0, [X0,Z0.D,UXTW #3]
prfd pstl3keep, p0, [x0,z0.d,uxtw #3]
PRFD PSTL3KEEP, P0, [X0,Z0.D,UXTW #3]
prfd pstl3strm, p0, [x0,z0.d,uxtw #3]
PRFD PSTL3STRM, P0, [X0,Z0.D,UXTW #3]
prfd #14, p0, [x0,z0.d,uxtw #3]
PRFD #14, P0, [X0,Z0.D,UXTW #3]
prfd #15, p0, [x0,z0.d,uxtw #3]
PRFD #15, P0, [X0,Z0.D,UXTW #3]
prfd pldl1keep, p2, [x0,z0.d,uxtw #3]
PRFD PLDL1KEEP, P2, [X0,Z0.D,UXTW #3]
prfd pldl1keep, p7, [x0,z0.d,uxtw #3]
PRFD PLDL1KEEP, P7, [X0,Z0.D,UXTW #3]
prfd pldl1keep, p0, [x3,z0.d,uxtw #3]
PRFD PLDL1KEEP, P0, [X3,Z0.D,UXTW #3]
prfd pldl1keep, p0, [sp,z0.d,uxtw #3]
PRFD PLDL1KEEP, P0, [SP,Z0.D,UXTW #3]
prfd pldl1keep, p0, [x0,z4.d,uxtw #3]
PRFD PLDL1KEEP, P0, [X0,Z4.D,UXTW #3]
prfd pldl1keep, p0, [x0,z31.d,uxtw #3]
PRFD PLDL1KEEP, P0, [X0,Z31.D,UXTW #3]
prfd pldl1keep, p0, [x0,z0.d,sxtw #3]
PRFD PLDL1KEEP, P0, [X0,Z0.D,SXTW #3]
prfd pldl1strm, p0, [x0,z0.d,sxtw #3]
PRFD PLDL1STRM, P0, [X0,Z0.D,SXTW #3]
prfd pldl2keep, p0, [x0,z0.d,sxtw #3]
PRFD PLDL2KEEP, P0, [X0,Z0.D,SXTW #3]
prfd pldl2strm, p0, [x0,z0.d,sxtw #3]
PRFD PLDL2STRM, P0, [X0,Z0.D,SXTW #3]
prfd pldl3keep, p0, [x0,z0.d,sxtw #3]
PRFD PLDL3KEEP, P0, [X0,Z0.D,SXTW #3]
prfd pldl3strm, p0, [x0,z0.d,sxtw #3]
PRFD PLDL3STRM, P0, [X0,Z0.D,SXTW #3]
prfd #6, p0, [x0,z0.d,sxtw #3]
PRFD #6, P0, [X0,Z0.D,SXTW #3]
prfd #7, p0, [x0,z0.d,sxtw #3]
PRFD #7, P0, [X0,Z0.D,SXTW #3]
prfd pstl1keep, p0, [x0,z0.d,sxtw #3]
PRFD PSTL1KEEP, P0, [X0,Z0.D,SXTW #3]
prfd pstl1strm, p0, [x0,z0.d,sxtw #3]
PRFD PSTL1STRM, P0, [X0,Z0.D,SXTW #3]
prfd pstl2keep, p0, [x0,z0.d,sxtw #3]
PRFD PSTL2KEEP, P0, [X0,Z0.D,SXTW #3]
prfd pstl2strm, p0, [x0,z0.d,sxtw #3]
PRFD PSTL2STRM, P0, [X0,Z0.D,SXTW #3]
prfd pstl3keep, p0, [x0,z0.d,sxtw #3]
PRFD PSTL3KEEP, P0, [X0,Z0.D,SXTW #3]
prfd pstl3strm, p0, [x0,z0.d,sxtw #3]
PRFD PSTL3STRM, P0, [X0,Z0.D,SXTW #3]
prfd #14, p0, [x0,z0.d,sxtw #3]
PRFD #14, P0, [X0,Z0.D,SXTW #3]
prfd #15, p0, [x0,z0.d,sxtw #3]
PRFD #15, P0, [X0,Z0.D,SXTW #3]
prfd pldl1keep, p2, [x0,z0.d,sxtw #3]
PRFD PLDL1KEEP, P2, [X0,Z0.D,SXTW #3]
prfd pldl1keep, p7, [x0,z0.d,sxtw #3]
PRFD PLDL1KEEP, P7, [X0,Z0.D,SXTW #3]
prfd pldl1keep, p0, [x3,z0.d,sxtw #3]
PRFD PLDL1KEEP, P0, [X3,Z0.D,SXTW #3]
prfd pldl1keep, p0, [sp,z0.d,sxtw #3]
PRFD PLDL1KEEP, P0, [SP,Z0.D,SXTW #3]
prfd pldl1keep, p0, [x0,z4.d,sxtw #3]
PRFD PLDL1KEEP, P0, [X0,Z4.D,SXTW #3]
prfd pldl1keep, p0, [x0,z31.d,sxtw #3]
PRFD PLDL1KEEP, P0, [X0,Z31.D,SXTW #3]
prfd pldl1keep, p0, [x0,z0.d,lsl #3]
PRFD PLDL1KEEP, P0, [X0,Z0.D,LSL #3]
prfd pldl1strm, p0, [x0,z0.d,lsl #3]
PRFD PLDL1STRM, P0, [X0,Z0.D,LSL #3]
prfd pldl2keep, p0, [x0,z0.d,lsl #3]
PRFD PLDL2KEEP, P0, [X0,Z0.D,LSL #3]
prfd pldl2strm, p0, [x0,z0.d,lsl #3]
PRFD PLDL2STRM, P0, [X0,Z0.D,LSL #3]
prfd pldl3keep, p0, [x0,z0.d,lsl #3]
PRFD PLDL3KEEP, P0, [X0,Z0.D,LSL #3]
prfd pldl3strm, p0, [x0,z0.d,lsl #3]
PRFD PLDL3STRM, P0, [X0,Z0.D,LSL #3]
prfd #6, p0, [x0,z0.d,lsl #3]
PRFD #6, P0, [X0,Z0.D,LSL #3]
prfd #7, p0, [x0,z0.d,lsl #3]
PRFD #7, P0, [X0,Z0.D,LSL #3]
prfd pstl1keep, p0, [x0,z0.d,lsl #3]
PRFD PSTL1KEEP, P0, [X0,Z0.D,LSL #3]
prfd pstl1strm, p0, [x0,z0.d,lsl #3]
PRFD PSTL1STRM, P0, [X0,Z0.D,LSL #3]
prfd pstl2keep, p0, [x0,z0.d,lsl #3]
PRFD PSTL2KEEP, P0, [X0,Z0.D,LSL #3]
prfd pstl2strm, p0, [x0,z0.d,lsl #3]
PRFD PSTL2STRM, P0, [X0,Z0.D,LSL #3]
prfd pstl3keep, p0, [x0,z0.d,lsl #3]
PRFD PSTL3KEEP, P0, [X0,Z0.D,LSL #3]
prfd pstl3strm, p0, [x0,z0.d,lsl #3]
PRFD PSTL3STRM, P0, [X0,Z0.D,LSL #3]
prfd #14, p0, [x0,z0.d,lsl #3]
PRFD #14, P0, [X0,Z0.D,LSL #3]
prfd #15, p0, [x0,z0.d,lsl #3]
PRFD #15, P0, [X0,Z0.D,LSL #3]
prfd pldl1keep, p2, [x0,z0.d,lsl #3]
PRFD PLDL1KEEP, P2, [X0,Z0.D,LSL #3]
prfd pldl1keep, p7, [x0,z0.d,lsl #3]
PRFD PLDL1KEEP, P7, [X0,Z0.D,LSL #3]
prfd pldl1keep, p0, [x3,z0.d,lsl #3]
PRFD PLDL1KEEP, P0, [X3,Z0.D,LSL #3]
prfd pldl1keep, p0, [sp,z0.d,lsl #3]
PRFD PLDL1KEEP, P0, [SP,Z0.D,LSL #3]
prfd pldl1keep, p0, [x0,z4.d,lsl #3]
PRFD PLDL1KEEP, P0, [X0,Z4.D,LSL #3]
prfd pldl1keep, p0, [x0,z31.d,lsl #3]
PRFD PLDL1KEEP, P0, [X0,Z31.D,LSL #3]
prfd pldl1keep, p0, [z0.s,#0]
PRFD PLDL1KEEP, P0, [Z0.S,#0]
prfd pldl1keep, p0, [z0.s]
prfd pldl1strm, p0, [z0.s,#0]
PRFD PLDL1STRM, P0, [Z0.S,#0]
prfd pldl1strm, p0, [z0.s]
prfd pldl2keep, p0, [z0.s,#0]
PRFD PLDL2KEEP, P0, [Z0.S,#0]
prfd pldl2keep, p0, [z0.s]
prfd pldl2strm, p0, [z0.s,#0]
PRFD PLDL2STRM, P0, [Z0.S,#0]
prfd pldl2strm, p0, [z0.s]
prfd pldl3keep, p0, [z0.s,#0]
PRFD PLDL3KEEP, P0, [Z0.S,#0]
prfd pldl3keep, p0, [z0.s]
prfd pldl3strm, p0, [z0.s,#0]
PRFD PLDL3STRM, P0, [Z0.S,#0]
prfd pldl3strm, p0, [z0.s]
prfd #6, p0, [z0.s,#0]
PRFD #6, P0, [Z0.S,#0]
prfd #6, p0, [z0.s]
prfd #7, p0, [z0.s,#0]
PRFD #7, P0, [Z0.S,#0]
prfd #7, p0, [z0.s]
prfd pstl1keep, p0, [z0.s,#0]
PRFD PSTL1KEEP, P0, [Z0.S,#0]
prfd pstl1keep, p0, [z0.s]
prfd pstl1strm, p0, [z0.s,#0]
PRFD PSTL1STRM, P0, [Z0.S,#0]
prfd pstl1strm, p0, [z0.s]
prfd pstl2keep, p0, [z0.s,#0]
PRFD PSTL2KEEP, P0, [Z0.S,#0]
prfd pstl2keep, p0, [z0.s]
prfd pstl2strm, p0, [z0.s,#0]
PRFD PSTL2STRM, P0, [Z0.S,#0]
prfd pstl2strm, p0, [z0.s]
prfd pstl3keep, p0, [z0.s,#0]
PRFD PSTL3KEEP, P0, [Z0.S,#0]
prfd pstl3keep, p0, [z0.s]
prfd pstl3strm, p0, [z0.s,#0]
PRFD PSTL3STRM, P0, [Z0.S,#0]
prfd pstl3strm, p0, [z0.s]
prfd #14, p0, [z0.s,#0]
PRFD #14, P0, [Z0.S,#0]
prfd #14, p0, [z0.s]
prfd #15, p0, [z0.s,#0]
PRFD #15, P0, [Z0.S,#0]
prfd #15, p0, [z0.s]
prfd pldl1keep, p2, [z0.s,#0]
PRFD PLDL1KEEP, P2, [Z0.S,#0]
prfd pldl1keep, p2, [z0.s]
prfd pldl1keep, p7, [z0.s,#0]
PRFD PLDL1KEEP, P7, [Z0.S,#0]
prfd pldl1keep, p7, [z0.s]
prfd pldl1keep, p0, [z3.s,#0]
PRFD PLDL1KEEP, P0, [Z3.S,#0]
prfd pldl1keep, p0, [z3.s]
prfd pldl1keep, p0, [z31.s,#0]
PRFD PLDL1KEEP, P0, [Z31.S,#0]
prfd pldl1keep, p0, [z31.s]
prfd pldl1keep, p0, [z0.s,#120]
PRFD PLDL1KEEP, P0, [Z0.S,#120]
prfd pldl1keep, p0, [z0.s,#128]
PRFD PLDL1KEEP, P0, [Z0.S,#128]
prfd pldl1keep, p0, [z0.s,#136]
PRFD PLDL1KEEP, P0, [Z0.S,#136]
prfd pldl1keep, p0, [z0.s,#248]
PRFD PLDL1KEEP, P0, [Z0.S,#248]
prfd pldl1keep, p0, [x0,#0]
PRFD PLDL1KEEP, P0, [X0,#0]
prfd pldl1keep, p0, [x0,#0,mul vl]
prfd pldl1keep, p0, [x0]
prfd pldl1strm, p0, [x0,#0]
PRFD PLDL1STRM, P0, [X0,#0]
prfd pldl1strm, p0, [x0,#0,mul vl]
prfd pldl1strm, p0, [x0]
prfd pldl2keep, p0, [x0,#0]
PRFD PLDL2KEEP, P0, [X0,#0]
prfd pldl2keep, p0, [x0,#0,mul vl]
prfd pldl2keep, p0, [x0]
prfd pldl2strm, p0, [x0,#0]
PRFD PLDL2STRM, P0, [X0,#0]
prfd pldl2strm, p0, [x0,#0,mul vl]
prfd pldl2strm, p0, [x0]
prfd pldl3keep, p0, [x0,#0]
PRFD PLDL3KEEP, P0, [X0,#0]
prfd pldl3keep, p0, [x0,#0,mul vl]
prfd pldl3keep, p0, [x0]
prfd pldl3strm, p0, [x0,#0]
PRFD PLDL3STRM, P0, [X0,#0]
prfd pldl3strm, p0, [x0,#0,mul vl]
prfd pldl3strm, p0, [x0]
prfd #6, p0, [x0,#0]
PRFD #6, P0, [X0,#0]
prfd #6, p0, [x0,#0,mul vl]
prfd #6, p0, [x0]
prfd #7, p0, [x0,#0]
PRFD #7, P0, [X0,#0]
prfd #7, p0, [x0,#0,mul vl]
prfd #7, p0, [x0]
prfd pstl1keep, p0, [x0,#0]
PRFD PSTL1KEEP, P0, [X0,#0]
prfd pstl1keep, p0, [x0,#0,mul vl]
prfd pstl1keep, p0, [x0]
prfd pstl1strm, p0, [x0,#0]
PRFD PSTL1STRM, P0, [X0,#0]
prfd pstl1strm, p0, [x0,#0,mul vl]
prfd pstl1strm, p0, [x0]
prfd pstl2keep, p0, [x0,#0]
PRFD PSTL2KEEP, P0, [X0,#0]
prfd pstl2keep, p0, [x0,#0,mul vl]
prfd pstl2keep, p0, [x0]
prfd pstl2strm, p0, [x0,#0]
PRFD PSTL2STRM, P0, [X0,#0]
prfd pstl2strm, p0, [x0,#0,mul vl]
prfd pstl2strm, p0, [x0]
prfd pstl3keep, p0, [x0,#0]
PRFD PSTL3KEEP, P0, [X0,#0]
prfd pstl3keep, p0, [x0,#0,mul vl]
prfd pstl3keep, p0, [x0]
prfd pstl3strm, p0, [x0,#0]
PRFD PSTL3STRM, P0, [X0,#0]
prfd pstl3strm, p0, [x0,#0,mul vl]
prfd pstl3strm, p0, [x0]
prfd #14, p0, [x0,#0]
PRFD #14, P0, [X0,#0]
prfd #14, p0, [x0,#0,mul vl]
prfd #14, p0, [x0]
prfd #15, p0, [x0,#0]
PRFD #15, P0, [X0,#0]
prfd #15, p0, [x0,#0,mul vl]
prfd #15, p0, [x0]
prfd pldl1keep, p2, [x0,#0]
PRFD PLDL1KEEP, P2, [X0,#0]
prfd pldl1keep, p2, [x0,#0,mul vl]
prfd pldl1keep, p2, [x0]
prfd pldl1keep, p7, [x0,#0]
PRFD PLDL1KEEP, P7, [X0,#0]
prfd pldl1keep, p7, [x0,#0,mul vl]
prfd pldl1keep, p7, [x0]
prfd pldl1keep, p0, [x3,#0]
PRFD PLDL1KEEP, P0, [X3,#0]
prfd pldl1keep, p0, [x3,#0,mul vl]
prfd pldl1keep, p0, [x3]
prfd pldl1keep, p0, [sp,#0]
PRFD PLDL1KEEP, P0, [SP,#0]
prfd pldl1keep, p0, [sp,#0,mul vl]
prfd pldl1keep, p0, [sp]
prfd pldl1keep, p0, [x0,#31,mul vl]
PRFD PLDL1KEEP, P0, [X0,#31,MUL VL]
prfd pldl1keep, p0, [x0,#-32,mul vl]
PRFD PLDL1KEEP, P0, [X0,#-32,MUL VL]
prfd pldl1keep, p0, [x0,#-31,mul vl]
PRFD PLDL1KEEP, P0, [X0,#-31,MUL VL]
prfd pldl1keep, p0, [x0,#-1,mul vl]
PRFD PLDL1KEEP, P0, [X0,#-1,MUL VL]
prfd pldl1keep, p0, [z0.d,#0]
PRFD PLDL1KEEP, P0, [Z0.D,#0]
prfd pldl1keep, p0, [z0.d]
prfd pldl1strm, p0, [z0.d,#0]
PRFD PLDL1STRM, P0, [Z0.D,#0]
prfd pldl1strm, p0, [z0.d]
prfd pldl2keep, p0, [z0.d,#0]
PRFD PLDL2KEEP, P0, [Z0.D,#0]
prfd pldl2keep, p0, [z0.d]
prfd pldl2strm, p0, [z0.d,#0]
PRFD PLDL2STRM, P0, [Z0.D,#0]
prfd pldl2strm, p0, [z0.d]
prfd pldl3keep, p0, [z0.d,#0]
PRFD PLDL3KEEP, P0, [Z0.D,#0]
prfd pldl3keep, p0, [z0.d]
prfd pldl3strm, p0, [z0.d,#0]
PRFD PLDL3STRM, P0, [Z0.D,#0]
prfd pldl3strm, p0, [z0.d]
prfd #6, p0, [z0.d,#0]
PRFD #6, P0, [Z0.D,#0]
prfd #6, p0, [z0.d]
prfd #7, p0, [z0.d,#0]
PRFD #7, P0, [Z0.D,#0]
prfd #7, p0, [z0.d]
prfd pstl1keep, p0, [z0.d,#0]
PRFD PSTL1KEEP, P0, [Z0.D,#0]
prfd pstl1keep, p0, [z0.d]
prfd pstl1strm, p0, [z0.d,#0]
PRFD PSTL1STRM, P0, [Z0.D,#0]
prfd pstl1strm, p0, [z0.d]
prfd pstl2keep, p0, [z0.d,#0]
PRFD PSTL2KEEP, P0, [Z0.D,#0]
prfd pstl2keep, p0, [z0.d]
prfd pstl2strm, p0, [z0.d,#0]
PRFD PSTL2STRM, P0, [Z0.D,#0]
prfd pstl2strm, p0, [z0.d]
prfd pstl3keep, p0, [z0.d,#0]
PRFD PSTL3KEEP, P0, [Z0.D,#0]
prfd pstl3keep, p0, [z0.d]
prfd pstl3strm, p0, [z0.d,#0]
PRFD PSTL3STRM, P0, [Z0.D,#0]
prfd pstl3strm, p0, [z0.d]
prfd #14, p0, [z0.d,#0]
PRFD #14, P0, [Z0.D,#0]
prfd #14, p0, [z0.d]
prfd #15, p0, [z0.d,#0]
PRFD #15, P0, [Z0.D,#0]
prfd #15, p0, [z0.d]
prfd pldl1keep, p2, [z0.d,#0]
PRFD PLDL1KEEP, P2, [Z0.D,#0]
prfd pldl1keep, p2, [z0.d]
prfd pldl1keep, p7, [z0.d,#0]
PRFD PLDL1KEEP, P7, [Z0.D,#0]
prfd pldl1keep, p7, [z0.d]
prfd pldl1keep, p0, [z3.d,#0]
PRFD PLDL1KEEP, P0, [Z3.D,#0]
prfd pldl1keep, p0, [z3.d]
prfd pldl1keep, p0, [z31.d,#0]
PRFD PLDL1KEEP, P0, [Z31.D,#0]
prfd pldl1keep, p0, [z31.d]
prfd pldl1keep, p0, [z0.d,#120]
PRFD PLDL1KEEP, P0, [Z0.D,#120]
prfd pldl1keep, p0, [z0.d,#128]
PRFD PLDL1KEEP, P0, [Z0.D,#128]
prfd pldl1keep, p0, [z0.d,#136]
PRFD PLDL1KEEP, P0, [Z0.D,#136]
prfd pldl1keep, p0, [z0.d,#248]
PRFD PLDL1KEEP, P0, [Z0.D,#248]
prfh pldl1keep, p0, [x0,z0.s,uxtw #1]
PRFH PLDL1KEEP, P0, [X0,Z0.S,UXTW #1]
prfh pldl1strm, p0, [x0,z0.s,uxtw #1]
PRFH PLDL1STRM, P0, [X0,Z0.S,UXTW #1]
prfh pldl2keep, p0, [x0,z0.s,uxtw #1]
PRFH PLDL2KEEP, P0, [X0,Z0.S,UXTW #1]
prfh pldl2strm, p0, [x0,z0.s,uxtw #1]
PRFH PLDL2STRM, P0, [X0,Z0.S,UXTW #1]
prfh pldl3keep, p0, [x0,z0.s,uxtw #1]
PRFH PLDL3KEEP, P0, [X0,Z0.S,UXTW #1]
prfh pldl3strm, p0, [x0,z0.s,uxtw #1]
PRFH PLDL3STRM, P0, [X0,Z0.S,UXTW #1]
prfh #6, p0, [x0,z0.s,uxtw #1]
PRFH #6, P0, [X0,Z0.S,UXTW #1]
prfh #7, p0, [x0,z0.s,uxtw #1]
PRFH #7, P0, [X0,Z0.S,UXTW #1]
prfh pstl1keep, p0, [x0,z0.s,uxtw #1]
PRFH PSTL1KEEP, P0, [X0,Z0.S,UXTW #1]
prfh pstl1strm, p0, [x0,z0.s,uxtw #1]
PRFH PSTL1STRM, P0, [X0,Z0.S,UXTW #1]
prfh pstl2keep, p0, [x0,z0.s,uxtw #1]
PRFH PSTL2KEEP, P0, [X0,Z0.S,UXTW #1]
prfh pstl2strm, p0, [x0,z0.s,uxtw #1]
PRFH PSTL2STRM, P0, [X0,Z0.S,UXTW #1]
prfh pstl3keep, p0, [x0,z0.s,uxtw #1]
PRFH PSTL3KEEP, P0, [X0,Z0.S,UXTW #1]
prfh pstl3strm, p0, [x0,z0.s,uxtw #1]
PRFH PSTL3STRM, P0, [X0,Z0.S,UXTW #1]
prfh #14, p0, [x0,z0.s,uxtw #1]
PRFH #14, P0, [X0,Z0.S,UXTW #1]
prfh #15, p0, [x0,z0.s,uxtw #1]
PRFH #15, P0, [X0,Z0.S,UXTW #1]
prfh pldl1keep, p2, [x0,z0.s,uxtw #1]
PRFH PLDL1KEEP, P2, [X0,Z0.S,UXTW #1]
prfh pldl1keep, p7, [x0,z0.s,uxtw #1]
PRFH PLDL1KEEP, P7, [X0,Z0.S,UXTW #1]
prfh pldl1keep, p0, [x3,z0.s,uxtw #1]
PRFH PLDL1KEEP, P0, [X3,Z0.S,UXTW #1]
prfh pldl1keep, p0, [sp,z0.s,uxtw #1]
PRFH PLDL1KEEP, P0, [SP,Z0.S,UXTW #1]
prfh pldl1keep, p0, [x0,z4.s,uxtw #1]
PRFH PLDL1KEEP, P0, [X0,Z4.S,UXTW #1]
prfh pldl1keep, p0, [x0,z31.s,uxtw #1]
PRFH PLDL1KEEP, P0, [X0,Z31.S,UXTW #1]
prfh pldl1keep, p0, [x0,z0.s,sxtw #1]
PRFH PLDL1KEEP, P0, [X0,Z0.S,SXTW #1]
prfh pldl1strm, p0, [x0,z0.s,sxtw #1]
PRFH PLDL1STRM, P0, [X0,Z0.S,SXTW #1]
prfh pldl2keep, p0, [x0,z0.s,sxtw #1]
PRFH PLDL2KEEP, P0, [X0,Z0.S,SXTW #1]
prfh pldl2strm, p0, [x0,z0.s,sxtw #1]
PRFH PLDL2STRM, P0, [X0,Z0.S,SXTW #1]
prfh pldl3keep, p0, [x0,z0.s,sxtw #1]
PRFH PLDL3KEEP, P0, [X0,Z0.S,SXTW #1]
prfh pldl3strm, p0, [x0,z0.s,sxtw #1]
PRFH PLDL3STRM, P0, [X0,Z0.S,SXTW #1]
prfh #6, p0, [x0,z0.s,sxtw #1]
PRFH #6, P0, [X0,Z0.S,SXTW #1]
prfh #7, p0, [x0,z0.s,sxtw #1]
PRFH #7, P0, [X0,Z0.S,SXTW #1]
prfh pstl1keep, p0, [x0,z0.s,sxtw #1]
PRFH PSTL1KEEP, P0, [X0,Z0.S,SXTW #1]
prfh pstl1strm, p0, [x0,z0.s,sxtw #1]
PRFH PSTL1STRM, P0, [X0,Z0.S,SXTW #1]
prfh pstl2keep, p0, [x0,z0.s,sxtw #1]
PRFH PSTL2KEEP, P0, [X0,Z0.S,SXTW #1]
prfh pstl2strm, p0, [x0,z0.s,sxtw #1]
PRFH PSTL2STRM, P0, [X0,Z0.S,SXTW #1]
prfh pstl3keep, p0, [x0,z0.s,sxtw #1]
PRFH PSTL3KEEP, P0, [X0,Z0.S,SXTW #1]
prfh pstl3strm, p0, [x0,z0.s,sxtw #1]
PRFH PSTL3STRM, P0, [X0,Z0.S,SXTW #1]
prfh #14, p0, [x0,z0.s,sxtw #1]
PRFH #14, P0, [X0,Z0.S,SXTW #1]
prfh #15, p0, [x0,z0.s,sxtw #1]
PRFH #15, P0, [X0,Z0.S,SXTW #1]
prfh pldl1keep, p2, [x0,z0.s,sxtw #1]
PRFH PLDL1KEEP, P2, [X0,Z0.S,SXTW #1]
prfh pldl1keep, p7, [x0,z0.s,sxtw #1]
PRFH PLDL1KEEP, P7, [X0,Z0.S,SXTW #1]
prfh pldl1keep, p0, [x3,z0.s,sxtw #1]
PRFH PLDL1KEEP, P0, [X3,Z0.S,SXTW #1]
prfh pldl1keep, p0, [sp,z0.s,sxtw #1]
PRFH PLDL1KEEP, P0, [SP,Z0.S,SXTW #1]
prfh pldl1keep, p0, [x0,z4.s,sxtw #1]
PRFH PLDL1KEEP, P0, [X0,Z4.S,SXTW #1]
prfh pldl1keep, p0, [x0,z31.s,sxtw #1]
PRFH PLDL1KEEP, P0, [X0,Z31.S,SXTW #1]
prfh pldl1keep, p0, [x0,x0,lsl #1]
PRFH PLDL1KEEP, P0, [X0,X0,LSL #1]
prfh pldl1strm, p0, [x0,x0,lsl #1]
PRFH PLDL1STRM, P0, [X0,X0,LSL #1]
prfh pldl2keep, p0, [x0,x0,lsl #1]
PRFH PLDL2KEEP, P0, [X0,X0,LSL #1]
prfh pldl2strm, p0, [x0,x0,lsl #1]
PRFH PLDL2STRM, P0, [X0,X0,LSL #1]
prfh pldl3keep, p0, [x0,x0,lsl #1]
PRFH PLDL3KEEP, P0, [X0,X0,LSL #1]
prfh pldl3strm, p0, [x0,x0,lsl #1]
PRFH PLDL3STRM, P0, [X0,X0,LSL #1]
prfh #6, p0, [x0,x0,lsl #1]
PRFH #6, P0, [X0,X0,LSL #1]
prfh #7, p0, [x0,x0,lsl #1]
PRFH #7, P0, [X0,X0,LSL #1]
prfh pstl1keep, p0, [x0,x0,lsl #1]
PRFH PSTL1KEEP, P0, [X0,X0,LSL #1]
prfh pstl1strm, p0, [x0,x0,lsl #1]
PRFH PSTL1STRM, P0, [X0,X0,LSL #1]
prfh pstl2keep, p0, [x0,x0,lsl #1]
PRFH PSTL2KEEP, P0, [X0,X0,LSL #1]
prfh pstl2strm, p0, [x0,x0,lsl #1]
PRFH PSTL2STRM, P0, [X0,X0,LSL #1]
prfh pstl3keep, p0, [x0,x0,lsl #1]
PRFH PSTL3KEEP, P0, [X0,X0,LSL #1]
prfh pstl3strm, p0, [x0,x0,lsl #1]
PRFH PSTL3STRM, P0, [X0,X0,LSL #1]
prfh #14, p0, [x0,x0,lsl #1]
PRFH #14, P0, [X0,X0,LSL #1]
prfh #15, p0, [x0,x0,lsl #1]
PRFH #15, P0, [X0,X0,LSL #1]
prfh pldl1keep, p2, [x0,x0,lsl #1]
PRFH PLDL1KEEP, P2, [X0,X0,LSL #1]
prfh pldl1keep, p7, [x0,x0,lsl #1]
PRFH PLDL1KEEP, P7, [X0,X0,LSL #1]
prfh pldl1keep, p0, [x3,x0,lsl #1]
PRFH PLDL1KEEP, P0, [X3,X0,LSL #1]
prfh pldl1keep, p0, [sp,x0,lsl #1]
PRFH PLDL1KEEP, P0, [SP,X0,LSL #1]
prfh pldl1keep, p0, [x0,x4,lsl #1]
PRFH PLDL1KEEP, P0, [X0,X4,LSL #1]
prfh pldl1keep, p0, [x0,x30,lsl #1]
PRFH PLDL1KEEP, P0, [X0,X30,LSL #1]
prfh pldl1keep, p0, [x0,z0.d,uxtw #1]
PRFH PLDL1KEEP, P0, [X0,Z0.D,UXTW #1]
prfh pldl1strm, p0, [x0,z0.d,uxtw #1]
PRFH PLDL1STRM, P0, [X0,Z0.D,UXTW #1]
prfh pldl2keep, p0, [x0,z0.d,uxtw #1]
PRFH PLDL2KEEP, P0, [X0,Z0.D,UXTW #1]
prfh pldl2strm, p0, [x0,z0.d,uxtw #1]
PRFH PLDL2STRM, P0, [X0,Z0.D,UXTW #1]
prfh pldl3keep, p0, [x0,z0.d,uxtw #1]
PRFH PLDL3KEEP, P0, [X0,Z0.D,UXTW #1]
prfh pldl3strm, p0, [x0,z0.d,uxtw #1]
PRFH PLDL3STRM, P0, [X0,Z0.D,UXTW #1]
prfh #6, p0, [x0,z0.d,uxtw #1]
PRFH #6, P0, [X0,Z0.D,UXTW #1]
prfh #7, p0, [x0,z0.d,uxtw #1]
PRFH #7, P0, [X0,Z0.D,UXTW #1]
prfh pstl1keep, p0, [x0,z0.d,uxtw #1]
PRFH PSTL1KEEP, P0, [X0,Z0.D,UXTW #1]
prfh pstl1strm, p0, [x0,z0.d,uxtw #1]
PRFH PSTL1STRM, P0, [X0,Z0.D,UXTW #1]
prfh pstl2keep, p0, [x0,z0.d,uxtw #1]
PRFH PSTL2KEEP, P0, [X0,Z0.D,UXTW #1]
prfh pstl2strm, p0, [x0,z0.d,uxtw #1]
PRFH PSTL2STRM, P0, [X0,Z0.D,UXTW #1]
prfh pstl3keep, p0, [x0,z0.d,uxtw #1]
PRFH PSTL3KEEP, P0, [X0,Z0.D,UXTW #1]
prfh pstl3strm, p0, [x0,z0.d,uxtw #1]
PRFH PSTL3STRM, P0, [X0,Z0.D,UXTW #1]
prfh #14, p0, [x0,z0.d,uxtw #1]
PRFH #14, P0, [X0,Z0.D,UXTW #1]
prfh #15, p0, [x0,z0.d,uxtw #1]
PRFH #15, P0, [X0,Z0.D,UXTW #1]
prfh pldl1keep, p2, [x0,z0.d,uxtw #1]
PRFH PLDL1KEEP, P2, [X0,Z0.D,UXTW #1]
prfh pldl1keep, p7, [x0,z0.d,uxtw #1]
PRFH PLDL1KEEP, P7, [X0,Z0.D,UXTW #1]
prfh pldl1keep, p0, [x3,z0.d,uxtw #1]
PRFH PLDL1KEEP, P0, [X3,Z0.D,UXTW #1]
prfh pldl1keep, p0, [sp,z0.d,uxtw #1]
PRFH PLDL1KEEP, P0, [SP,Z0.D,UXTW #1]
prfh pldl1keep, p0, [x0,z4.d,uxtw #1]
PRFH PLDL1KEEP, P0, [X0,Z4.D,UXTW #1]
prfh pldl1keep, p0, [x0,z31.d,uxtw #1]
PRFH PLDL1KEEP, P0, [X0,Z31.D,UXTW #1]
prfh pldl1keep, p0, [x0,z0.d,sxtw #1]
PRFH PLDL1KEEP, P0, [X0,Z0.D,SXTW #1]
prfh pldl1strm, p0, [x0,z0.d,sxtw #1]
PRFH PLDL1STRM, P0, [X0,Z0.D,SXTW #1]
prfh pldl2keep, p0, [x0,z0.d,sxtw #1]
PRFH PLDL2KEEP, P0, [X0,Z0.D,SXTW #1]
prfh pldl2strm, p0, [x0,z0.d,sxtw #1]
PRFH PLDL2STRM, P0, [X0,Z0.D,SXTW #1]
prfh pldl3keep, p0, [x0,z0.d,sxtw #1]
PRFH PLDL3KEEP, P0, [X0,Z0.D,SXTW #1]
prfh pldl3strm, p0, [x0,z0.d,sxtw #1]
PRFH PLDL3STRM, P0, [X0,Z0.D,SXTW #1]
prfh #6, p0, [x0,z0.d,sxtw #1]
PRFH #6, P0, [X0,Z0.D,SXTW #1]
prfh #7, p0, [x0,z0.d,sxtw #1]
PRFH #7, P0, [X0,Z0.D,SXTW #1]
prfh pstl1keep, p0, [x0,z0.d,sxtw #1]
PRFH PSTL1KEEP, P0, [X0,Z0.D,SXTW #1]
prfh pstl1strm, p0, [x0,z0.d,sxtw #1]
PRFH PSTL1STRM, P0, [X0,Z0.D,SXTW #1]
prfh pstl2keep, p0, [x0,z0.d,sxtw #1]
PRFH PSTL2KEEP, P0, [X0,Z0.D,SXTW #1]
prfh pstl2strm, p0, [x0,z0.d,sxtw #1]
PRFH PSTL2STRM, P0, [X0,Z0.D,SXTW #1]
prfh pstl3keep, p0, [x0,z0.d,sxtw #1]
PRFH PSTL3KEEP, P0, [X0,Z0.D,SXTW #1]
prfh pstl3strm, p0, [x0,z0.d,sxtw #1]
PRFH PSTL3STRM, P0, [X0,Z0.D,SXTW #1]
prfh #14, p0, [x0,z0.d,sxtw #1]
PRFH #14, P0, [X0,Z0.D,SXTW #1]
prfh #15, p0, [x0,z0.d,sxtw #1]
PRFH #15, P0, [X0,Z0.D,SXTW #1]
prfh pldl1keep, p2, [x0,z0.d,sxtw #1]
PRFH PLDL1KEEP, P2, [X0,Z0.D,SXTW #1]
prfh pldl1keep, p7, [x0,z0.d,sxtw #1]
PRFH PLDL1KEEP, P7, [X0,Z0.D,SXTW #1]
prfh pldl1keep, p0, [x3,z0.d,sxtw #1]
PRFH PLDL1KEEP, P0, [X3,Z0.D,SXTW #1]
prfh pldl1keep, p0, [sp,z0.d,sxtw #1]
PRFH PLDL1KEEP, P0, [SP,Z0.D,SXTW #1]
prfh pldl1keep, p0, [x0,z4.d,sxtw #1]
PRFH PLDL1KEEP, P0, [X0,Z4.D,SXTW #1]
prfh pldl1keep, p0, [x0,z31.d,sxtw #1]
PRFH PLDL1KEEP, P0, [X0,Z31.D,SXTW #1]
prfh pldl1keep, p0, [x0,z0.d,lsl #1]
PRFH PLDL1KEEP, P0, [X0,Z0.D,LSL #1]
prfh pldl1strm, p0, [x0,z0.d,lsl #1]
PRFH PLDL1STRM, P0, [X0,Z0.D,LSL #1]
prfh pldl2keep, p0, [x0,z0.d,lsl #1]
PRFH PLDL2KEEP, P0, [X0,Z0.D,LSL #1]
prfh pldl2strm, p0, [x0,z0.d,lsl #1]
PRFH PLDL2STRM, P0, [X0,Z0.D,LSL #1]
prfh pldl3keep, p0, [x0,z0.d,lsl #1]
PRFH PLDL3KEEP, P0, [X0,Z0.D,LSL #1]
prfh pldl3strm, p0, [x0,z0.d,lsl #1]
PRFH PLDL3STRM, P0, [X0,Z0.D,LSL #1]
prfh #6, p0, [x0,z0.d,lsl #1]
PRFH #6, P0, [X0,Z0.D,LSL #1]
prfh #7, p0, [x0,z0.d,lsl #1]
PRFH #7, P0, [X0,Z0.D,LSL #1]
prfh pstl1keep, p0, [x0,z0.d,lsl #1]
PRFH PSTL1KEEP, P0, [X0,Z0.D,LSL #1]
prfh pstl1strm, p0, [x0,z0.d,lsl #1]
PRFH PSTL1STRM, P0, [X0,Z0.D,LSL #1]
prfh pstl2keep, p0, [x0,z0.d,lsl #1]
PRFH PSTL2KEEP, P0, [X0,Z0.D,LSL #1]
prfh pstl2strm, p0, [x0,z0.d,lsl #1]
PRFH PSTL2STRM, P0, [X0,Z0.D,LSL #1]
prfh pstl3keep, p0, [x0,z0.d,lsl #1]
PRFH PSTL3KEEP, P0, [X0,Z0.D,LSL #1]
prfh pstl3strm, p0, [x0,z0.d,lsl #1]
PRFH PSTL3STRM, P0, [X0,Z0.D,LSL #1]
prfh #14, p0, [x0,z0.d,lsl #1]
PRFH #14, P0, [X0,Z0.D,LSL #1]
prfh #15, p0, [x0,z0.d,lsl #1]
PRFH #15, P0, [X0,Z0.D,LSL #1]
prfh pldl1keep, p2, [x0,z0.d,lsl #1]
PRFH PLDL1KEEP, P2, [X0,Z0.D,LSL #1]
prfh pldl1keep, p7, [x0,z0.d,lsl #1]
PRFH PLDL1KEEP, P7, [X0,Z0.D,LSL #1]
prfh pldl1keep, p0, [x3,z0.d,lsl #1]
PRFH PLDL1KEEP, P0, [X3,Z0.D,LSL #1]
prfh pldl1keep, p0, [sp,z0.d,lsl #1]
PRFH PLDL1KEEP, P0, [SP,Z0.D,LSL #1]
prfh pldl1keep, p0, [x0,z4.d,lsl #1]
PRFH PLDL1KEEP, P0, [X0,Z4.D,LSL #1]
prfh pldl1keep, p0, [x0,z31.d,lsl #1]
PRFH PLDL1KEEP, P0, [X0,Z31.D,LSL #1]
prfh pldl1keep, p0, [z0.s,#0]
PRFH PLDL1KEEP, P0, [Z0.S,#0]
prfh pldl1keep, p0, [z0.s]
prfh pldl1strm, p0, [z0.s,#0]
PRFH PLDL1STRM, P0, [Z0.S,#0]
prfh pldl1strm, p0, [z0.s]
prfh pldl2keep, p0, [z0.s,#0]
PRFH PLDL2KEEP, P0, [Z0.S,#0]
prfh pldl2keep, p0, [z0.s]
prfh pldl2strm, p0, [z0.s,#0]
PRFH PLDL2STRM, P0, [Z0.S,#0]
prfh pldl2strm, p0, [z0.s]
prfh pldl3keep, p0, [z0.s,#0]
PRFH PLDL3KEEP, P0, [Z0.S,#0]
prfh pldl3keep, p0, [z0.s]
prfh pldl3strm, p0, [z0.s,#0]
PRFH PLDL3STRM, P0, [Z0.S,#0]
prfh pldl3strm, p0, [z0.s]
prfh #6, p0, [z0.s,#0]
PRFH #6, P0, [Z0.S,#0]
prfh #6, p0, [z0.s]
prfh #7, p0, [z0.s,#0]
PRFH #7, P0, [Z0.S,#0]
prfh #7, p0, [z0.s]
prfh pstl1keep, p0, [z0.s,#0]
PRFH PSTL1KEEP, P0, [Z0.S,#0]
prfh pstl1keep, p0, [z0.s]
prfh pstl1strm, p0, [z0.s,#0]
PRFH PSTL1STRM, P0, [Z0.S,#0]
prfh pstl1strm, p0, [z0.s]
prfh pstl2keep, p0, [z0.s,#0]
PRFH PSTL2KEEP, P0, [Z0.S,#0]
prfh pstl2keep, p0, [z0.s]
prfh pstl2strm, p0, [z0.s,#0]
PRFH PSTL2STRM, P0, [Z0.S,#0]
prfh pstl2strm, p0, [z0.s]
prfh pstl3keep, p0, [z0.s,#0]
PRFH PSTL3KEEP, P0, [Z0.S,#0]
prfh pstl3keep, p0, [z0.s]
prfh pstl3strm, p0, [z0.s,#0]
PRFH PSTL3STRM, P0, [Z0.S,#0]
prfh pstl3strm, p0, [z0.s]
prfh #14, p0, [z0.s,#0]
PRFH #14, P0, [Z0.S,#0]
prfh #14, p0, [z0.s]
prfh #15, p0, [z0.s,#0]
PRFH #15, P0, [Z0.S,#0]
prfh #15, p0, [z0.s]
prfh pldl1keep, p2, [z0.s,#0]
PRFH PLDL1KEEP, P2, [Z0.S,#0]
prfh pldl1keep, p2, [z0.s]
prfh pldl1keep, p7, [z0.s,#0]
PRFH PLDL1KEEP, P7, [Z0.S,#0]
prfh pldl1keep, p7, [z0.s]
prfh pldl1keep, p0, [z3.s,#0]
PRFH PLDL1KEEP, P0, [Z3.S,#0]
prfh pldl1keep, p0, [z3.s]
prfh pldl1keep, p0, [z31.s,#0]
PRFH PLDL1KEEP, P0, [Z31.S,#0]
prfh pldl1keep, p0, [z31.s]
prfh pldl1keep, p0, [z0.s,#30]
PRFH PLDL1KEEP, P0, [Z0.S,#30]
prfh pldl1keep, p0, [z0.s,#32]
PRFH PLDL1KEEP, P0, [Z0.S,#32]
prfh pldl1keep, p0, [z0.s,#34]
PRFH PLDL1KEEP, P0, [Z0.S,#34]
prfh pldl1keep, p0, [z0.s,#62]
PRFH PLDL1KEEP, P0, [Z0.S,#62]
prfh pldl1keep, p0, [x0,#0]
PRFH PLDL1KEEP, P0, [X0,#0]
prfh pldl1keep, p0, [x0,#0,mul vl]
prfh pldl1keep, p0, [x0]
prfh pldl1strm, p0, [x0,#0]
PRFH PLDL1STRM, P0, [X0,#0]
prfh pldl1strm, p0, [x0,#0,mul vl]
prfh pldl1strm, p0, [x0]
prfh pldl2keep, p0, [x0,#0]
PRFH PLDL2KEEP, P0, [X0,#0]
prfh pldl2keep, p0, [x0,#0,mul vl]
prfh pldl2keep, p0, [x0]
prfh pldl2strm, p0, [x0,#0]
PRFH PLDL2STRM, P0, [X0,#0]
prfh pldl2strm, p0, [x0,#0,mul vl]
prfh pldl2strm, p0, [x0]
prfh pldl3keep, p0, [x0,#0]
PRFH PLDL3KEEP, P0, [X0,#0]
prfh pldl3keep, p0, [x0,#0,mul vl]
prfh pldl3keep, p0, [x0]
prfh pldl3strm, p0, [x0,#0]
PRFH PLDL3STRM, P0, [X0,#0]
prfh pldl3strm, p0, [x0,#0,mul vl]
prfh pldl3strm, p0, [x0]
prfh #6, p0, [x0,#0]
PRFH #6, P0, [X0,#0]
prfh #6, p0, [x0,#0,mul vl]
prfh #6, p0, [x0]
prfh #7, p0, [x0,#0]
PRFH #7, P0, [X0,#0]
prfh #7, p0, [x0,#0,mul vl]
prfh #7, p0, [x0]
prfh pstl1keep, p0, [x0,#0]
PRFH PSTL1KEEP, P0, [X0,#0]
prfh pstl1keep, p0, [x0,#0,mul vl]
prfh pstl1keep, p0, [x0]
prfh pstl1strm, p0, [x0,#0]
PRFH PSTL1STRM, P0, [X0,#0]
prfh pstl1strm, p0, [x0,#0,mul vl]
prfh pstl1strm, p0, [x0]
prfh pstl2keep, p0, [x0,#0]
PRFH PSTL2KEEP, P0, [X0,#0]
prfh pstl2keep, p0, [x0,#0,mul vl]
prfh pstl2keep, p0, [x0]
prfh pstl2strm, p0, [x0,#0]
PRFH PSTL2STRM, P0, [X0,#0]
prfh pstl2strm, p0, [x0,#0,mul vl]
prfh pstl2strm, p0, [x0]
prfh pstl3keep, p0, [x0,#0]
PRFH PSTL3KEEP, P0, [X0,#0]
prfh pstl3keep, p0, [x0,#0,mul vl]
prfh pstl3keep, p0, [x0]
prfh pstl3strm, p0, [x0,#0]
PRFH PSTL3STRM, P0, [X0,#0]
prfh pstl3strm, p0, [x0,#0,mul vl]
prfh pstl3strm, p0, [x0]
prfh #14, p0, [x0,#0]
PRFH #14, P0, [X0,#0]
prfh #14, p0, [x0,#0,mul vl]
prfh #14, p0, [x0]
prfh #15, p0, [x0,#0]
PRFH #15, P0, [X0,#0]
prfh #15, p0, [x0,#0,mul vl]
prfh #15, p0, [x0]
prfh pldl1keep, p2, [x0,#0]
PRFH PLDL1KEEP, P2, [X0,#0]
prfh pldl1keep, p2, [x0,#0,mul vl]
prfh pldl1keep, p2, [x0]
prfh pldl1keep, p7, [x0,#0]
PRFH PLDL1KEEP, P7, [X0,#0]
prfh pldl1keep, p7, [x0,#0,mul vl]
prfh pldl1keep, p7, [x0]
prfh pldl1keep, p0, [x3,#0]
PRFH PLDL1KEEP, P0, [X3,#0]
prfh pldl1keep, p0, [x3,#0,mul vl]
prfh pldl1keep, p0, [x3]
prfh pldl1keep, p0, [sp,#0]
PRFH PLDL1KEEP, P0, [SP,#0]
prfh pldl1keep, p0, [sp,#0,mul vl]
prfh pldl1keep, p0, [sp]
prfh pldl1keep, p0, [x0,#31,mul vl]
PRFH PLDL1KEEP, P0, [X0,#31,MUL VL]
prfh pldl1keep, p0, [x0,#-32,mul vl]
PRFH PLDL1KEEP, P0, [X0,#-32,MUL VL]
prfh pldl1keep, p0, [x0,#-31,mul vl]
PRFH PLDL1KEEP, P0, [X0,#-31,MUL VL]
prfh pldl1keep, p0, [x0,#-1,mul vl]
PRFH PLDL1KEEP, P0, [X0,#-1,MUL VL]
prfh pldl1keep, p0, [z0.d,#0]
PRFH PLDL1KEEP, P0, [Z0.D,#0]
prfh pldl1keep, p0, [z0.d]
prfh pldl1strm, p0, [z0.d,#0]
PRFH PLDL1STRM, P0, [Z0.D,#0]
prfh pldl1strm, p0, [z0.d]
prfh pldl2keep, p0, [z0.d,#0]
PRFH PLDL2KEEP, P0, [Z0.D,#0]
prfh pldl2keep, p0, [z0.d]
prfh pldl2strm, p0, [z0.d,#0]
PRFH PLDL2STRM, P0, [Z0.D,#0]
prfh pldl2strm, p0, [z0.d]
prfh pldl3keep, p0, [z0.d,#0]
PRFH PLDL3KEEP, P0, [Z0.D,#0]
prfh pldl3keep, p0, [z0.d]
prfh pldl3strm, p0, [z0.d,#0]
PRFH PLDL3STRM, P0, [Z0.D,#0]
prfh pldl3strm, p0, [z0.d]
prfh #6, p0, [z0.d,#0]
PRFH #6, P0, [Z0.D,#0]
prfh #6, p0, [z0.d]
prfh #7, p0, [z0.d,#0]
PRFH #7, P0, [Z0.D,#0]
prfh #7, p0, [z0.d]
prfh pstl1keep, p0, [z0.d,#0]
PRFH PSTL1KEEP, P0, [Z0.D,#0]
prfh pstl1keep, p0, [z0.d]
prfh pstl1strm, p0, [z0.d,#0]
PRFH PSTL1STRM, P0, [Z0.D,#0]
prfh pstl1strm, p0, [z0.d]
prfh pstl2keep, p0, [z0.d,#0]
PRFH PSTL2KEEP, P0, [Z0.D,#0]
prfh pstl2keep, p0, [z0.d]
prfh pstl2strm, p0, [z0.d,#0]
PRFH PSTL2STRM, P0, [Z0.D,#0]
prfh pstl2strm, p0, [z0.d]
prfh pstl3keep, p0, [z0.d,#0]
PRFH PSTL3KEEP, P0, [Z0.D,#0]
prfh pstl3keep, p0, [z0.d]
prfh pstl3strm, p0, [z0.d,#0]
PRFH PSTL3STRM, P0, [Z0.D,#0]
prfh pstl3strm, p0, [z0.d]
prfh #14, p0, [z0.d,#0]
PRFH #14, P0, [Z0.D,#0]
prfh #14, p0, [z0.d]
prfh #15, p0, [z0.d,#0]
PRFH #15, P0, [Z0.D,#0]
prfh #15, p0, [z0.d]
prfh pldl1keep, p2, [z0.d,#0]
PRFH PLDL1KEEP, P2, [Z0.D,#0]
prfh pldl1keep, p2, [z0.d]
prfh pldl1keep, p7, [z0.d,#0]
PRFH PLDL1KEEP, P7, [Z0.D,#0]
prfh pldl1keep, p7, [z0.d]
prfh pldl1keep, p0, [z3.d,#0]
PRFH PLDL1KEEP, P0, [Z3.D,#0]
prfh pldl1keep, p0, [z3.d]
prfh pldl1keep, p0, [z31.d,#0]
PRFH PLDL1KEEP, P0, [Z31.D,#0]
prfh pldl1keep, p0, [z31.d]
prfh pldl1keep, p0, [z0.d,#30]
PRFH PLDL1KEEP, P0, [Z0.D,#30]
prfh pldl1keep, p0, [z0.d,#32]
PRFH PLDL1KEEP, P0, [Z0.D,#32]
prfh pldl1keep, p0, [z0.d,#34]
PRFH PLDL1KEEP, P0, [Z0.D,#34]
prfh pldl1keep, p0, [z0.d,#62]
PRFH PLDL1KEEP, P0, [Z0.D,#62]
prfw pldl1keep, p0, [x0,z0.s,uxtw #2]
PRFW PLDL1KEEP, P0, [X0,Z0.S,UXTW #2]
prfw pldl1strm, p0, [x0,z0.s,uxtw #2]
PRFW PLDL1STRM, P0, [X0,Z0.S,UXTW #2]
prfw pldl2keep, p0, [x0,z0.s,uxtw #2]
PRFW PLDL2KEEP, P0, [X0,Z0.S,UXTW #2]
prfw pldl2strm, p0, [x0,z0.s,uxtw #2]
PRFW PLDL2STRM, P0, [X0,Z0.S,UXTW #2]
prfw pldl3keep, p0, [x0,z0.s,uxtw #2]
PRFW PLDL3KEEP, P0, [X0,Z0.S,UXTW #2]
prfw pldl3strm, p0, [x0,z0.s,uxtw #2]
PRFW PLDL3STRM, P0, [X0,Z0.S,UXTW #2]
prfw #6, p0, [x0,z0.s,uxtw #2]
PRFW #6, P0, [X0,Z0.S,UXTW #2]
prfw #7, p0, [x0,z0.s,uxtw #2]
PRFW #7, P0, [X0,Z0.S,UXTW #2]
prfw pstl1keep, p0, [x0,z0.s,uxtw #2]
PRFW PSTL1KEEP, P0, [X0,Z0.S,UXTW #2]
prfw pstl1strm, p0, [x0,z0.s,uxtw #2]
PRFW PSTL1STRM, P0, [X0,Z0.S,UXTW #2]
prfw pstl2keep, p0, [x0,z0.s,uxtw #2]
PRFW PSTL2KEEP, P0, [X0,Z0.S,UXTW #2]
prfw pstl2strm, p0, [x0,z0.s,uxtw #2]
PRFW PSTL2STRM, P0, [X0,Z0.S,UXTW #2]
prfw pstl3keep, p0, [x0,z0.s,uxtw #2]
PRFW PSTL3KEEP, P0, [X0,Z0.S,UXTW #2]
prfw pstl3strm, p0, [x0,z0.s,uxtw #2]
PRFW PSTL3STRM, P0, [X0,Z0.S,UXTW #2]
prfw #14, p0, [x0,z0.s,uxtw #2]
PRFW #14, P0, [X0,Z0.S,UXTW #2]
prfw #15, p0, [x0,z0.s,uxtw #2]
PRFW #15, P0, [X0,Z0.S,UXTW #2]
prfw pldl1keep, p2, [x0,z0.s,uxtw #2]
PRFW PLDL1KEEP, P2, [X0,Z0.S,UXTW #2]
prfw pldl1keep, p7, [x0,z0.s,uxtw #2]
PRFW PLDL1KEEP, P7, [X0,Z0.S,UXTW #2]
prfw pldl1keep, p0, [x3,z0.s,uxtw #2]
PRFW PLDL1KEEP, P0, [X3,Z0.S,UXTW #2]
prfw pldl1keep, p0, [sp,z0.s,uxtw #2]
PRFW PLDL1KEEP, P0, [SP,Z0.S,UXTW #2]
prfw pldl1keep, p0, [x0,z4.s,uxtw #2]
PRFW PLDL1KEEP, P0, [X0,Z4.S,UXTW #2]
prfw pldl1keep, p0, [x0,z31.s,uxtw #2]
PRFW PLDL1KEEP, P0, [X0,Z31.S,UXTW #2]
prfw pldl1keep, p0, [x0,z0.s,sxtw #2]
PRFW PLDL1KEEP, P0, [X0,Z0.S,SXTW #2]
prfw pldl1strm, p0, [x0,z0.s,sxtw #2]
PRFW PLDL1STRM, P0, [X0,Z0.S,SXTW #2]
prfw pldl2keep, p0, [x0,z0.s,sxtw #2]
PRFW PLDL2KEEP, P0, [X0,Z0.S,SXTW #2]
prfw pldl2strm, p0, [x0,z0.s,sxtw #2]
PRFW PLDL2STRM, P0, [X0,Z0.S,SXTW #2]
prfw pldl3keep, p0, [x0,z0.s,sxtw #2]
PRFW PLDL3KEEP, P0, [X0,Z0.S,SXTW #2]
prfw pldl3strm, p0, [x0,z0.s,sxtw #2]
PRFW PLDL3STRM, P0, [X0,Z0.S,SXTW #2]
prfw #6, p0, [x0,z0.s,sxtw #2]
PRFW #6, P0, [X0,Z0.S,SXTW #2]
prfw #7, p0, [x0,z0.s,sxtw #2]
PRFW #7, P0, [X0,Z0.S,SXTW #2]
prfw pstl1keep, p0, [x0,z0.s,sxtw #2]
PRFW PSTL1KEEP, P0, [X0,Z0.S,SXTW #2]
prfw pstl1strm, p0, [x0,z0.s,sxtw #2]
PRFW PSTL1STRM, P0, [X0,Z0.S,SXTW #2]
prfw pstl2keep, p0, [x0,z0.s,sxtw #2]
PRFW PSTL2KEEP, P0, [X0,Z0.S,SXTW #2]
prfw pstl2strm, p0, [x0,z0.s,sxtw #2]
PRFW PSTL2STRM, P0, [X0,Z0.S,SXTW #2]
prfw pstl3keep, p0, [x0,z0.s,sxtw #2]
PRFW PSTL3KEEP, P0, [X0,Z0.S,SXTW #2]
prfw pstl3strm, p0, [x0,z0.s,sxtw #2]
PRFW PSTL3STRM, P0, [X0,Z0.S,SXTW #2]
prfw #14, p0, [x0,z0.s,sxtw #2]
PRFW #14, P0, [X0,Z0.S,SXTW #2]
prfw #15, p0, [x0,z0.s,sxtw #2]
PRFW #15, P0, [X0,Z0.S,SXTW #2]
prfw pldl1keep, p2, [x0,z0.s,sxtw #2]
PRFW PLDL1KEEP, P2, [X0,Z0.S,SXTW #2]
prfw pldl1keep, p7, [x0,z0.s,sxtw #2]
PRFW PLDL1KEEP, P7, [X0,Z0.S,SXTW #2]
prfw pldl1keep, p0, [x3,z0.s,sxtw #2]
PRFW PLDL1KEEP, P0, [X3,Z0.S,SXTW #2]
prfw pldl1keep, p0, [sp,z0.s,sxtw #2]
PRFW PLDL1KEEP, P0, [SP,Z0.S,SXTW #2]
prfw pldl1keep, p0, [x0,z4.s,sxtw #2]
PRFW PLDL1KEEP, P0, [X0,Z4.S,SXTW #2]
prfw pldl1keep, p0, [x0,z31.s,sxtw #2]
PRFW PLDL1KEEP, P0, [X0,Z31.S,SXTW #2]
prfw pldl1keep, p0, [x0,x0,lsl #2]
PRFW PLDL1KEEP, P0, [X0,X0,LSL #2]
prfw pldl1strm, p0, [x0,x0,lsl #2]
PRFW PLDL1STRM, P0, [X0,X0,LSL #2]
prfw pldl2keep, p0, [x0,x0,lsl #2]
PRFW PLDL2KEEP, P0, [X0,X0,LSL #2]
prfw pldl2strm, p0, [x0,x0,lsl #2]
PRFW PLDL2STRM, P0, [X0,X0,LSL #2]
prfw pldl3keep, p0, [x0,x0,lsl #2]
PRFW PLDL3KEEP, P0, [X0,X0,LSL #2]
prfw pldl3strm, p0, [x0,x0,lsl #2]
PRFW PLDL3STRM, P0, [X0,X0,LSL #2]
prfw #6, p0, [x0,x0,lsl #2]
PRFW #6, P0, [X0,X0,LSL #2]
prfw #7, p0, [x0,x0,lsl #2]
PRFW #7, P0, [X0,X0,LSL #2]
prfw pstl1keep, p0, [x0,x0,lsl #2]
PRFW PSTL1KEEP, P0, [X0,X0,LSL #2]
prfw pstl1strm, p0, [x0,x0,lsl #2]
PRFW PSTL1STRM, P0, [X0,X0,LSL #2]
prfw pstl2keep, p0, [x0,x0,lsl #2]
PRFW PSTL2KEEP, P0, [X0,X0,LSL #2]
prfw pstl2strm, p0, [x0,x0,lsl #2]
PRFW PSTL2STRM, P0, [X0,X0,LSL #2]
prfw pstl3keep, p0, [x0,x0,lsl #2]
PRFW PSTL3KEEP, P0, [X0,X0,LSL #2]
prfw pstl3strm, p0, [x0,x0,lsl #2]
PRFW PSTL3STRM, P0, [X0,X0,LSL #2]
prfw #14, p0, [x0,x0,lsl #2]
PRFW #14, P0, [X0,X0,LSL #2]
prfw #15, p0, [x0,x0,lsl #2]
PRFW #15, P0, [X0,X0,LSL #2]
prfw pldl1keep, p2, [x0,x0,lsl #2]
PRFW PLDL1KEEP, P2, [X0,X0,LSL #2]
prfw pldl1keep, p7, [x0,x0,lsl #2]
PRFW PLDL1KEEP, P7, [X0,X0,LSL #2]
prfw pldl1keep, p0, [x3,x0,lsl #2]
PRFW PLDL1KEEP, P0, [X3,X0,LSL #2]
prfw pldl1keep, p0, [sp,x0,lsl #2]
PRFW PLDL1KEEP, P0, [SP,X0,LSL #2]
prfw pldl1keep, p0, [x0,x4,lsl #2]
PRFW PLDL1KEEP, P0, [X0,X4,LSL #2]
prfw pldl1keep, p0, [x0,x30,lsl #2]
PRFW PLDL1KEEP, P0, [X0,X30,LSL #2]
prfw pldl1keep, p0, [x0,z0.d,uxtw #2]
PRFW PLDL1KEEP, P0, [X0,Z0.D,UXTW #2]
prfw pldl1strm, p0, [x0,z0.d,uxtw #2]
PRFW PLDL1STRM, P0, [X0,Z0.D,UXTW #2]
prfw pldl2keep, p0, [x0,z0.d,uxtw #2]
PRFW PLDL2KEEP, P0, [X0,Z0.D,UXTW #2]
prfw pldl2strm, p0, [x0,z0.d,uxtw #2]
PRFW PLDL2STRM, P0, [X0,Z0.D,UXTW #2]
prfw pldl3keep, p0, [x0,z0.d,uxtw #2]
PRFW PLDL3KEEP, P0, [X0,Z0.D,UXTW #2]
prfw pldl3strm, p0, [x0,z0.d,uxtw #2]
PRFW PLDL3STRM, P0, [X0,Z0.D,UXTW #2]
prfw #6, p0, [x0,z0.d,uxtw #2]
PRFW #6, P0, [X0,Z0.D,UXTW #2]
prfw #7, p0, [x0,z0.d,uxtw #2]
PRFW #7, P0, [X0,Z0.D,UXTW #2]
prfw pstl1keep, p0, [x0,z0.d,uxtw #2]
PRFW PSTL1KEEP, P0, [X0,Z0.D,UXTW #2]
prfw pstl1strm, p0, [x0,z0.d,uxtw #2]
PRFW PSTL1STRM, P0, [X0,Z0.D,UXTW #2]
prfw pstl2keep, p0, [x0,z0.d,uxtw #2]
PRFW PSTL2KEEP, P0, [X0,Z0.D,UXTW #2]
prfw pstl2strm, p0, [x0,z0.d,uxtw #2]
PRFW PSTL2STRM, P0, [X0,Z0.D,UXTW #2]
prfw pstl3keep, p0, [x0,z0.d,uxtw #2]
PRFW PSTL3KEEP, P0, [X0,Z0.D,UXTW #2]
prfw pstl3strm, p0, [x0,z0.d,uxtw #2]
PRFW PSTL3STRM, P0, [X0,Z0.D,UXTW #2]
prfw #14, p0, [x0,z0.d,uxtw #2]
PRFW #14, P0, [X0,Z0.D,UXTW #2]
prfw #15, p0, [x0,z0.d,uxtw #2]
PRFW #15, P0, [X0,Z0.D,UXTW #2]
prfw pldl1keep, p2, [x0,z0.d,uxtw #2]
PRFW PLDL1KEEP, P2, [X0,Z0.D,UXTW #2]
prfw pldl1keep, p7, [x0,z0.d,uxtw #2]
PRFW PLDL1KEEP, P7, [X0,Z0.D,UXTW #2]
prfw pldl1keep, p0, [x3,z0.d,uxtw #2]
PRFW PLDL1KEEP, P0, [X3,Z0.D,UXTW #2]
prfw pldl1keep, p0, [sp,z0.d,uxtw #2]
PRFW PLDL1KEEP, P0, [SP,Z0.D,UXTW #2]
prfw pldl1keep, p0, [x0,z4.d,uxtw #2]
PRFW PLDL1KEEP, P0, [X0,Z4.D,UXTW #2]
prfw pldl1keep, p0, [x0,z31.d,uxtw #2]
PRFW PLDL1KEEP, P0, [X0,Z31.D,UXTW #2]
prfw pldl1keep, p0, [x0,z0.d,sxtw #2]
PRFW PLDL1KEEP, P0, [X0,Z0.D,SXTW #2]
prfw pldl1strm, p0, [x0,z0.d,sxtw #2]
PRFW PLDL1STRM, P0, [X0,Z0.D,SXTW #2]
prfw pldl2keep, p0, [x0,z0.d,sxtw #2]
PRFW PLDL2KEEP, P0, [X0,Z0.D,SXTW #2]
prfw pldl2strm, p0, [x0,z0.d,sxtw #2]
PRFW PLDL2STRM, P0, [X0,Z0.D,SXTW #2]
prfw pldl3keep, p0, [x0,z0.d,sxtw #2]
PRFW PLDL3KEEP, P0, [X0,Z0.D,SXTW #2]
prfw pldl3strm, p0, [x0,z0.d,sxtw #2]
PRFW PLDL3STRM, P0, [X0,Z0.D,SXTW #2]
prfw #6, p0, [x0,z0.d,sxtw #2]
PRFW #6, P0, [X0,Z0.D,SXTW #2]
prfw #7, p0, [x0,z0.d,sxtw #2]
PRFW #7, P0, [X0,Z0.D,SXTW #2]
prfw pstl1keep, p0, [x0,z0.d,sxtw #2]
PRFW PSTL1KEEP, P0, [X0,Z0.D,SXTW #2]
prfw pstl1strm, p0, [x0,z0.d,sxtw #2]
PRFW PSTL1STRM, P0, [X0,Z0.D,SXTW #2]
prfw pstl2keep, p0, [x0,z0.d,sxtw #2]
PRFW PSTL2KEEP, P0, [X0,Z0.D,SXTW #2]
prfw pstl2strm, p0, [x0,z0.d,sxtw #2]
PRFW PSTL2STRM, P0, [X0,Z0.D,SXTW #2]
prfw pstl3keep, p0, [x0,z0.d,sxtw #2]
PRFW PSTL3KEEP, P0, [X0,Z0.D,SXTW #2]
prfw pstl3strm, p0, [x0,z0.d,sxtw #2]
PRFW PSTL3STRM, P0, [X0,Z0.D,SXTW #2]
prfw #14, p0, [x0,z0.d,sxtw #2]
PRFW #14, P0, [X0,Z0.D,SXTW #2]
prfw #15, p0, [x0,z0.d,sxtw #2]
PRFW #15, P0, [X0,Z0.D,SXTW #2]
prfw pldl1keep, p2, [x0,z0.d,sxtw #2]
PRFW PLDL1KEEP, P2, [X0,Z0.D,SXTW #2]
prfw pldl1keep, p7, [x0,z0.d,sxtw #2]
PRFW PLDL1KEEP, P7, [X0,Z0.D,SXTW #2]
prfw pldl1keep, p0, [x3,z0.d,sxtw #2]
PRFW PLDL1KEEP, P0, [X3,Z0.D,SXTW #2]
prfw pldl1keep, p0, [sp,z0.d,sxtw #2]
PRFW PLDL1KEEP, P0, [SP,Z0.D,SXTW #2]
prfw pldl1keep, p0, [x0,z4.d,sxtw #2]
PRFW PLDL1KEEP, P0, [X0,Z4.D,SXTW #2]
prfw pldl1keep, p0, [x0,z31.d,sxtw #2]
PRFW PLDL1KEEP, P0, [X0,Z31.D,SXTW #2]
prfw pldl1keep, p0, [x0,z0.d,lsl #2]
PRFW PLDL1KEEP, P0, [X0,Z0.D,LSL #2]
prfw pldl1strm, p0, [x0,z0.d,lsl #2]
PRFW PLDL1STRM, P0, [X0,Z0.D,LSL #2]
prfw pldl2keep, p0, [x0,z0.d,lsl #2]
PRFW PLDL2KEEP, P0, [X0,Z0.D,LSL #2]
prfw pldl2strm, p0, [x0,z0.d,lsl #2]
PRFW PLDL2STRM, P0, [X0,Z0.D,LSL #2]
prfw pldl3keep, p0, [x0,z0.d,lsl #2]
PRFW PLDL3KEEP, P0, [X0,Z0.D,LSL #2]
prfw pldl3strm, p0, [x0,z0.d,lsl #2]
PRFW PLDL3STRM, P0, [X0,Z0.D,LSL #2]
prfw #6, p0, [x0,z0.d,lsl #2]
PRFW #6, P0, [X0,Z0.D,LSL #2]
prfw #7, p0, [x0,z0.d,lsl #2]
PRFW #7, P0, [X0,Z0.D,LSL #2]
prfw pstl1keep, p0, [x0,z0.d,lsl #2]
PRFW PSTL1KEEP, P0, [X0,Z0.D,LSL #2]
prfw pstl1strm, p0, [x0,z0.d,lsl #2]
PRFW PSTL1STRM, P0, [X0,Z0.D,LSL #2]
prfw pstl2keep, p0, [x0,z0.d,lsl #2]
PRFW PSTL2KEEP, P0, [X0,Z0.D,LSL #2]
prfw pstl2strm, p0, [x0,z0.d,lsl #2]
PRFW PSTL2STRM, P0, [X0,Z0.D,LSL #2]
prfw pstl3keep, p0, [x0,z0.d,lsl #2]
PRFW PSTL3KEEP, P0, [X0,Z0.D,LSL #2]
prfw pstl3strm, p0, [x0,z0.d,lsl #2]
PRFW PSTL3STRM, P0, [X0,Z0.D,LSL #2]
prfw #14, p0, [x0,z0.d,lsl #2]
PRFW #14, P0, [X0,Z0.D,LSL #2]
prfw #15, p0, [x0,z0.d,lsl #2]
PRFW #15, P0, [X0,Z0.D,LSL #2]
prfw pldl1keep, p2, [x0,z0.d,lsl #2]
PRFW PLDL1KEEP, P2, [X0,Z0.D,LSL #2]
prfw pldl1keep, p7, [x0,z0.d,lsl #2]
PRFW PLDL1KEEP, P7, [X0,Z0.D,LSL #2]
prfw pldl1keep, p0, [x3,z0.d,lsl #2]
PRFW PLDL1KEEP, P0, [X3,Z0.D,LSL #2]
prfw pldl1keep, p0, [sp,z0.d,lsl #2]
PRFW PLDL1KEEP, P0, [SP,Z0.D,LSL #2]
prfw pldl1keep, p0, [x0,z4.d,lsl #2]
PRFW PLDL1KEEP, P0, [X0,Z4.D,LSL #2]
prfw pldl1keep, p0, [x0,z31.d,lsl #2]
PRFW PLDL1KEEP, P0, [X0,Z31.D,LSL #2]
prfw pldl1keep, p0, [z0.s,#0]
PRFW PLDL1KEEP, P0, [Z0.S,#0]
prfw pldl1keep, p0, [z0.s]
prfw pldl1strm, p0, [z0.s,#0]
PRFW PLDL1STRM, P0, [Z0.S,#0]
prfw pldl1strm, p0, [z0.s]
prfw pldl2keep, p0, [z0.s,#0]
PRFW PLDL2KEEP, P0, [Z0.S,#0]
prfw pldl2keep, p0, [z0.s]
prfw pldl2strm, p0, [z0.s,#0]
PRFW PLDL2STRM, P0, [Z0.S,#0]
prfw pldl2strm, p0, [z0.s]
prfw pldl3keep, p0, [z0.s,#0]
PRFW PLDL3KEEP, P0, [Z0.S,#0]
prfw pldl3keep, p0, [z0.s]
prfw pldl3strm, p0, [z0.s,#0]
PRFW PLDL3STRM, P0, [Z0.S,#0]
prfw pldl3strm, p0, [z0.s]
prfw #6, p0, [z0.s,#0]
PRFW #6, P0, [Z0.S,#0]
prfw #6, p0, [z0.s]
prfw #7, p0, [z0.s,#0]
PRFW #7, P0, [Z0.S,#0]
prfw #7, p0, [z0.s]
prfw pstl1keep, p0, [z0.s,#0]
PRFW PSTL1KEEP, P0, [Z0.S,#0]
prfw pstl1keep, p0, [z0.s]
prfw pstl1strm, p0, [z0.s,#0]
PRFW PSTL1STRM, P0, [Z0.S,#0]
prfw pstl1strm, p0, [z0.s]
prfw pstl2keep, p0, [z0.s,#0]
PRFW PSTL2KEEP, P0, [Z0.S,#0]
prfw pstl2keep, p0, [z0.s]
prfw pstl2strm, p0, [z0.s,#0]
PRFW PSTL2STRM, P0, [Z0.S,#0]
prfw pstl2strm, p0, [z0.s]
prfw pstl3keep, p0, [z0.s,#0]
PRFW PSTL3KEEP, P0, [Z0.S,#0]
prfw pstl3keep, p0, [z0.s]
prfw pstl3strm, p0, [z0.s,#0]
PRFW PSTL3STRM, P0, [Z0.S,#0]
prfw pstl3strm, p0, [z0.s]
prfw #14, p0, [z0.s,#0]
PRFW #14, P0, [Z0.S,#0]
prfw #14, p0, [z0.s]
prfw #15, p0, [z0.s,#0]
PRFW #15, P0, [Z0.S,#0]
prfw #15, p0, [z0.s]
prfw pldl1keep, p2, [z0.s,#0]
PRFW PLDL1KEEP, P2, [Z0.S,#0]
prfw pldl1keep, p2, [z0.s]
prfw pldl1keep, p7, [z0.s,#0]
PRFW PLDL1KEEP, P7, [Z0.S,#0]
prfw pldl1keep, p7, [z0.s]
prfw pldl1keep, p0, [z3.s,#0]
PRFW PLDL1KEEP, P0, [Z3.S,#0]
prfw pldl1keep, p0, [z3.s]
prfw pldl1keep, p0, [z31.s,#0]
PRFW PLDL1KEEP, P0, [Z31.S,#0]
prfw pldl1keep, p0, [z31.s]
prfw pldl1keep, p0, [z0.s,#60]
PRFW PLDL1KEEP, P0, [Z0.S,#60]
prfw pldl1keep, p0, [z0.s,#64]
PRFW PLDL1KEEP, P0, [Z0.S,#64]
prfw pldl1keep, p0, [z0.s,#68]
PRFW PLDL1KEEP, P0, [Z0.S,#68]
prfw pldl1keep, p0, [z0.s,#124]
PRFW PLDL1KEEP, P0, [Z0.S,#124]
prfw pldl1keep, p0, [x0,#0]
PRFW PLDL1KEEP, P0, [X0,#0]
prfw pldl1keep, p0, [x0,#0,mul vl]
prfw pldl1keep, p0, [x0]
prfw pldl1strm, p0, [x0,#0]
PRFW PLDL1STRM, P0, [X0,#0]
prfw pldl1strm, p0, [x0,#0,mul vl]
prfw pldl1strm, p0, [x0]
prfw pldl2keep, p0, [x0,#0]
PRFW PLDL2KEEP, P0, [X0,#0]
prfw pldl2keep, p0, [x0,#0,mul vl]
prfw pldl2keep, p0, [x0]
prfw pldl2strm, p0, [x0,#0]
PRFW PLDL2STRM, P0, [X0,#0]
prfw pldl2strm, p0, [x0,#0,mul vl]
prfw pldl2strm, p0, [x0]
prfw pldl3keep, p0, [x0,#0]
PRFW PLDL3KEEP, P0, [X0,#0]
prfw pldl3keep, p0, [x0,#0,mul vl]
prfw pldl3keep, p0, [x0]
prfw pldl3strm, p0, [x0,#0]
PRFW PLDL3STRM, P0, [X0,#0]
prfw pldl3strm, p0, [x0,#0,mul vl]
prfw pldl3strm, p0, [x0]
prfw #6, p0, [x0,#0]
PRFW #6, P0, [X0,#0]
prfw #6, p0, [x0,#0,mul vl]
prfw #6, p0, [x0]
prfw #7, p0, [x0,#0]
PRFW #7, P0, [X0,#0]
prfw #7, p0, [x0,#0,mul vl]
prfw #7, p0, [x0]
prfw pstl1keep, p0, [x0,#0]
PRFW PSTL1KEEP, P0, [X0,#0]
prfw pstl1keep, p0, [x0,#0,mul vl]
prfw pstl1keep, p0, [x0]
prfw pstl1strm, p0, [x0,#0]
PRFW PSTL1STRM, P0, [X0,#0]
prfw pstl1strm, p0, [x0,#0,mul vl]
prfw pstl1strm, p0, [x0]
prfw pstl2keep, p0, [x0,#0]
PRFW PSTL2KEEP, P0, [X0,#0]
prfw pstl2keep, p0, [x0,#0,mul vl]
prfw pstl2keep, p0, [x0]
prfw pstl2strm, p0, [x0,#0]
PRFW PSTL2STRM, P0, [X0,#0]
prfw pstl2strm, p0, [x0,#0,mul vl]
prfw pstl2strm, p0, [x0]
prfw pstl3keep, p0, [x0,#0]
PRFW PSTL3KEEP, P0, [X0,#0]
prfw pstl3keep, p0, [x0,#0,mul vl]
prfw pstl3keep, p0, [x0]
prfw pstl3strm, p0, [x0,#0]
PRFW PSTL3STRM, P0, [X0,#0]
prfw pstl3strm, p0, [x0,#0,mul vl]
prfw pstl3strm, p0, [x0]
prfw #14, p0, [x0,#0]
PRFW #14, P0, [X0,#0]
prfw #14, p0, [x0,#0,mul vl]
prfw #14, p0, [x0]
prfw #15, p0, [x0,#0]
PRFW #15, P0, [X0,#0]
prfw #15, p0, [x0,#0,mul vl]
prfw #15, p0, [x0]
prfw pldl1keep, p2, [x0,#0]
PRFW PLDL1KEEP, P2, [X0,#0]
prfw pldl1keep, p2, [x0,#0,mul vl]
prfw pldl1keep, p2, [x0]
prfw pldl1keep, p7, [x0,#0]
PRFW PLDL1KEEP, P7, [X0,#0]
prfw pldl1keep, p7, [x0,#0,mul vl]
prfw pldl1keep, p7, [x0]
prfw pldl1keep, p0, [x3,#0]
PRFW PLDL1KEEP, P0, [X3,#0]
prfw pldl1keep, p0, [x3,#0,mul vl]
prfw pldl1keep, p0, [x3]
prfw pldl1keep, p0, [sp,#0]
PRFW PLDL1KEEP, P0, [SP,#0]
prfw pldl1keep, p0, [sp,#0,mul vl]
prfw pldl1keep, p0, [sp]
prfw pldl1keep, p0, [x0,#31,mul vl]
PRFW PLDL1KEEP, P0, [X0,#31,MUL VL]
prfw pldl1keep, p0, [x0,#-32,mul vl]
PRFW PLDL1KEEP, P0, [X0,#-32,MUL VL]
prfw pldl1keep, p0, [x0,#-31,mul vl]
PRFW PLDL1KEEP, P0, [X0,#-31,MUL VL]
prfw pldl1keep, p0, [x0,#-1,mul vl]
PRFW PLDL1KEEP, P0, [X0,#-1,MUL VL]
prfw pldl1keep, p0, [z0.d,#0]
PRFW PLDL1KEEP, P0, [Z0.D,#0]
prfw pldl1keep, p0, [z0.d]
prfw pldl1strm, p0, [z0.d,#0]
PRFW PLDL1STRM, P0, [Z0.D,#0]
prfw pldl1strm, p0, [z0.d]
prfw pldl2keep, p0, [z0.d,#0]
PRFW PLDL2KEEP, P0, [Z0.D,#0]
prfw pldl2keep, p0, [z0.d]
prfw pldl2strm, p0, [z0.d,#0]
PRFW PLDL2STRM, P0, [Z0.D,#0]
prfw pldl2strm, p0, [z0.d]
prfw pldl3keep, p0, [z0.d,#0]
PRFW PLDL3KEEP, P0, [Z0.D,#0]
prfw pldl3keep, p0, [z0.d]
prfw pldl3strm, p0, [z0.d,#0]
PRFW PLDL3STRM, P0, [Z0.D,#0]
prfw pldl3strm, p0, [z0.d]
prfw #6, p0, [z0.d,#0]
PRFW #6, P0, [Z0.D,#0]
prfw #6, p0, [z0.d]
prfw #7, p0, [z0.d,#0]
PRFW #7, P0, [Z0.D,#0]
prfw #7, p0, [z0.d]
prfw pstl1keep, p0, [z0.d,#0]
PRFW PSTL1KEEP, P0, [Z0.D,#0]
prfw pstl1keep, p0, [z0.d]
prfw pstl1strm, p0, [z0.d,#0]
PRFW PSTL1STRM, P0, [Z0.D,#0]
prfw pstl1strm, p0, [z0.d]
prfw pstl2keep, p0, [z0.d,#0]
PRFW PSTL2KEEP, P0, [Z0.D,#0]
prfw pstl2keep, p0, [z0.d]
prfw pstl2strm, p0, [z0.d,#0]
PRFW PSTL2STRM, P0, [Z0.D,#0]
prfw pstl2strm, p0, [z0.d]
prfw pstl3keep, p0, [z0.d,#0]
PRFW PSTL3KEEP, P0, [Z0.D,#0]
prfw pstl3keep, p0, [z0.d]
prfw pstl3strm, p0, [z0.d,#0]
PRFW PSTL3STRM, P0, [Z0.D,#0]
prfw pstl3strm, p0, [z0.d]
prfw #14, p0, [z0.d,#0]
PRFW #14, P0, [Z0.D,#0]
prfw #14, p0, [z0.d]
prfw #15, p0, [z0.d,#0]
PRFW #15, P0, [Z0.D,#0]
prfw #15, p0, [z0.d]
prfw pldl1keep, p2, [z0.d,#0]
PRFW PLDL1KEEP, P2, [Z0.D,#0]
prfw pldl1keep, p2, [z0.d]
prfw pldl1keep, p7, [z0.d,#0]
PRFW PLDL1KEEP, P7, [Z0.D,#0]
prfw pldl1keep, p7, [z0.d]
prfw pldl1keep, p0, [z3.d,#0]
PRFW PLDL1KEEP, P0, [Z3.D,#0]
prfw pldl1keep, p0, [z3.d]
prfw pldl1keep, p0, [z31.d,#0]
PRFW PLDL1KEEP, P0, [Z31.D,#0]
prfw pldl1keep, p0, [z31.d]
prfw pldl1keep, p0, [z0.d,#60]
PRFW PLDL1KEEP, P0, [Z0.D,#60]
prfw pldl1keep, p0, [z0.d,#64]
PRFW PLDL1KEEP, P0, [Z0.D,#64]
prfw pldl1keep, p0, [z0.d,#68]
PRFW PLDL1KEEP, P0, [Z0.D,#68]
prfw pldl1keep, p0, [z0.d,#124]
PRFW PLDL1KEEP, P0, [Z0.D,#124]
ptest p0, p0.b
PTEST P0, P0.B
ptest p1, p0.b
PTEST P1, P0.B
ptest p15, p0.b
PTEST P15, P0.B
ptest p0, p2.b
PTEST P0, P2.B
ptest p0, p15.b
PTEST P0, P15.B
ptrue p0.b, pow2
PTRUE P0.B, POW2
ptrue p1.b, pow2
PTRUE P1.B, POW2
ptrue p15.b, pow2
PTRUE P15.B, POW2
ptrue p0.b, vl1
PTRUE P0.B, VL1
ptrue p0.b, vl2
PTRUE P0.B, VL2
ptrue p0.b, vl3
PTRUE P0.B, VL3
ptrue p0.b, vl4
PTRUE P0.B, VL4
ptrue p0.b, vl5
PTRUE P0.B, VL5
ptrue p0.b, vl6
PTRUE P0.B, VL6
ptrue p0.b, vl7
PTRUE P0.B, VL7
ptrue p0.b, vl8
PTRUE P0.B, VL8
ptrue p0.b, vl16
PTRUE P0.B, VL16
ptrue p0.b, vl32
PTRUE P0.B, VL32
ptrue p0.b, vl64
PTRUE P0.B, VL64
ptrue p0.b, vl128
PTRUE P0.B, VL128
ptrue p0.b, vl256
PTRUE P0.B, VL256
ptrue p0.b, #14
PTRUE P0.B, #14
ptrue p0.b, #15
PTRUE P0.B, #15
ptrue p0.b, #16
PTRUE P0.B, #16
ptrue p0.b, #17
PTRUE P0.B, #17
ptrue p0.b, #18
PTRUE P0.B, #18
ptrue p0.b, #19
PTRUE P0.B, #19
ptrue p0.b, #20
PTRUE P0.B, #20
ptrue p0.b, #21
PTRUE P0.B, #21
ptrue p0.b, #22
PTRUE P0.B, #22
ptrue p0.b, #23
PTRUE P0.B, #23
ptrue p0.b, #24
PTRUE P0.B, #24
ptrue p0.b, #25
PTRUE P0.B, #25
ptrue p0.b, #26
PTRUE P0.B, #26
ptrue p0.b, #27
PTRUE P0.B, #27
ptrue p0.b, #28
PTRUE P0.B, #28
ptrue p0.b, mul4
PTRUE P0.B, MUL4
ptrue p0.b, mul3
PTRUE P0.B, MUL3
ptrue p0.b
PTRUE P0.B
ptrue p0.b, all
ptrue p0.h, pow2
PTRUE P0.H, POW2
ptrue p1.h, pow2
PTRUE P1.H, POW2
ptrue p15.h, pow2
PTRUE P15.H, POW2
ptrue p0.h, vl1
PTRUE P0.H, VL1
ptrue p0.h, vl2
PTRUE P0.H, VL2
ptrue p0.h, vl3
PTRUE P0.H, VL3
ptrue p0.h, vl4
PTRUE P0.H, VL4
ptrue p0.h, vl5
PTRUE P0.H, VL5
ptrue p0.h, vl6
PTRUE P0.H, VL6
ptrue p0.h, vl7
PTRUE P0.H, VL7
ptrue p0.h, vl8
PTRUE P0.H, VL8
ptrue p0.h, vl16
PTRUE P0.H, VL16
ptrue p0.h, vl32
PTRUE P0.H, VL32
ptrue p0.h, vl64
PTRUE P0.H, VL64
ptrue p0.h, vl128
PTRUE P0.H, VL128
ptrue p0.h, vl256
PTRUE P0.H, VL256
ptrue p0.h, #14
PTRUE P0.H, #14
ptrue p0.h, #15
PTRUE P0.H, #15
ptrue p0.h, #16
PTRUE P0.H, #16
ptrue p0.h, #17
PTRUE P0.H, #17
ptrue p0.h, #18
PTRUE P0.H, #18
ptrue p0.h, #19
PTRUE P0.H, #19
ptrue p0.h, #20
PTRUE P0.H, #20
ptrue p0.h, #21
PTRUE P0.H, #21
ptrue p0.h, #22
PTRUE P0.H, #22
ptrue p0.h, #23
PTRUE P0.H, #23
ptrue p0.h, #24
PTRUE P0.H, #24
ptrue p0.h, #25
PTRUE P0.H, #25
ptrue p0.h, #26
PTRUE P0.H, #26
ptrue p0.h, #27
PTRUE P0.H, #27
ptrue p0.h, #28
PTRUE P0.H, #28
ptrue p0.h, mul4
PTRUE P0.H, MUL4
ptrue p0.h, mul3
PTRUE P0.H, MUL3
ptrue p0.h
PTRUE P0.H
ptrue p0.h, all
ptrue p0.s, pow2
PTRUE P0.S, POW2
ptrue p1.s, pow2
PTRUE P1.S, POW2
ptrue p15.s, pow2
PTRUE P15.S, POW2
ptrue p0.s, vl1
PTRUE P0.S, VL1
ptrue p0.s, vl2
PTRUE P0.S, VL2
ptrue p0.s, vl3
PTRUE P0.S, VL3
ptrue p0.s, vl4
PTRUE P0.S, VL4
ptrue p0.s, vl5
PTRUE P0.S, VL5
ptrue p0.s, vl6
PTRUE P0.S, VL6
ptrue p0.s, vl7
PTRUE P0.S, VL7
ptrue p0.s, vl8
PTRUE P0.S, VL8
ptrue p0.s, vl16
PTRUE P0.S, VL16
ptrue p0.s, vl32
PTRUE P0.S, VL32
ptrue p0.s, vl64
PTRUE P0.S, VL64
ptrue p0.s, vl128
PTRUE P0.S, VL128
ptrue p0.s, vl256
PTRUE P0.S, VL256
ptrue p0.s, #14
PTRUE P0.S, #14
ptrue p0.s, #15
PTRUE P0.S, #15
ptrue p0.s, #16
PTRUE P0.S, #16
ptrue p0.s, #17
PTRUE P0.S, #17
ptrue p0.s, #18
PTRUE P0.S, #18
ptrue p0.s, #19
PTRUE P0.S, #19
ptrue p0.s, #20
PTRUE P0.S, #20
ptrue p0.s, #21
PTRUE P0.S, #21
ptrue p0.s, #22
PTRUE P0.S, #22
ptrue p0.s, #23
PTRUE P0.S, #23
ptrue p0.s, #24
PTRUE P0.S, #24
ptrue p0.s, #25
PTRUE P0.S, #25
ptrue p0.s, #26
PTRUE P0.S, #26
ptrue p0.s, #27
PTRUE P0.S, #27
ptrue p0.s, #28
PTRUE P0.S, #28
ptrue p0.s, mul4
PTRUE P0.S, MUL4
ptrue p0.s, mul3
PTRUE P0.S, MUL3
ptrue p0.s
PTRUE P0.S
ptrue p0.s, all
ptrue p0.d, pow2
PTRUE P0.D, POW2
ptrue p1.d, pow2
PTRUE P1.D, POW2
ptrue p15.d, pow2
PTRUE P15.D, POW2
ptrue p0.d, vl1
PTRUE P0.D, VL1
ptrue p0.d, vl2
PTRUE P0.D, VL2
ptrue p0.d, vl3
PTRUE P0.D, VL3
ptrue p0.d, vl4
PTRUE P0.D, VL4
ptrue p0.d, vl5
PTRUE P0.D, VL5
ptrue p0.d, vl6
PTRUE P0.D, VL6
ptrue p0.d, vl7
PTRUE P0.D, VL7
ptrue p0.d, vl8
PTRUE P0.D, VL8
ptrue p0.d, vl16
PTRUE P0.D, VL16
ptrue p0.d, vl32
PTRUE P0.D, VL32
ptrue p0.d, vl64
PTRUE P0.D, VL64
ptrue p0.d, vl128
PTRUE P0.D, VL128
ptrue p0.d, vl256
PTRUE P0.D, VL256
ptrue p0.d, #14
PTRUE P0.D, #14
ptrue p0.d, #15
PTRUE P0.D, #15
ptrue p0.d, #16
PTRUE P0.D, #16
ptrue p0.d, #17
PTRUE P0.D, #17
ptrue p0.d, #18
PTRUE P0.D, #18
ptrue p0.d, #19
PTRUE P0.D, #19
ptrue p0.d, #20
PTRUE P0.D, #20
ptrue p0.d, #21
PTRUE P0.D, #21
ptrue p0.d, #22
PTRUE P0.D, #22
ptrue p0.d, #23
PTRUE P0.D, #23
ptrue p0.d, #24
PTRUE P0.D, #24
ptrue p0.d, #25
PTRUE P0.D, #25
ptrue p0.d, #26
PTRUE P0.D, #26
ptrue p0.d, #27
PTRUE P0.D, #27
ptrue p0.d, #28
PTRUE P0.D, #28
ptrue p0.d, mul4
PTRUE P0.D, MUL4
ptrue p0.d, mul3
PTRUE P0.D, MUL3
ptrue p0.d
PTRUE P0.D
ptrue p0.d, all
ptrues p0.b, pow2
PTRUES P0.B, POW2
ptrues p1.b, pow2
PTRUES P1.B, POW2
ptrues p15.b, pow2
PTRUES P15.B, POW2
ptrues p0.b, vl1
PTRUES P0.B, VL1
ptrues p0.b, vl2
PTRUES P0.B, VL2
ptrues p0.b, vl3
PTRUES P0.B, VL3
ptrues p0.b, vl4
PTRUES P0.B, VL4
ptrues p0.b, vl5
PTRUES P0.B, VL5
ptrues p0.b, vl6
PTRUES P0.B, VL6
ptrues p0.b, vl7
PTRUES P0.B, VL7
ptrues p0.b, vl8
PTRUES P0.B, VL8
ptrues p0.b, vl16
PTRUES P0.B, VL16
ptrues p0.b, vl32
PTRUES P0.B, VL32
ptrues p0.b, vl64
PTRUES P0.B, VL64
ptrues p0.b, vl128
PTRUES P0.B, VL128
ptrues p0.b, vl256
PTRUES P0.B, VL256
ptrues p0.b, #14
PTRUES P0.B, #14
ptrues p0.b, #15
PTRUES P0.B, #15
ptrues p0.b, #16
PTRUES P0.B, #16
ptrues p0.b, #17
PTRUES P0.B, #17
ptrues p0.b, #18
PTRUES P0.B, #18
ptrues p0.b, #19
PTRUES P0.B, #19
ptrues p0.b, #20
PTRUES P0.B, #20
ptrues p0.b, #21
PTRUES P0.B, #21
ptrues p0.b, #22
PTRUES P0.B, #22
ptrues p0.b, #23
PTRUES P0.B, #23
ptrues p0.b, #24
PTRUES P0.B, #24
ptrues p0.b, #25
PTRUES P0.B, #25
ptrues p0.b, #26
PTRUES P0.B, #26
ptrues p0.b, #27
PTRUES P0.B, #27
ptrues p0.b, #28
PTRUES P0.B, #28
ptrues p0.b, mul4
PTRUES P0.B, MUL4
ptrues p0.b, mul3
PTRUES P0.B, MUL3
ptrues p0.b
PTRUES P0.B
ptrues p0.b, all
ptrues p0.h, pow2
PTRUES P0.H, POW2
ptrues p1.h, pow2
PTRUES P1.H, POW2
ptrues p15.h, pow2
PTRUES P15.H, POW2
ptrues p0.h, vl1
PTRUES P0.H, VL1
ptrues p0.h, vl2
PTRUES P0.H, VL2
ptrues p0.h, vl3
PTRUES P0.H, VL3
ptrues p0.h, vl4
PTRUES P0.H, VL4
ptrues p0.h, vl5
PTRUES P0.H, VL5
ptrues p0.h, vl6
PTRUES P0.H, VL6
ptrues p0.h, vl7
PTRUES P0.H, VL7
ptrues p0.h, vl8
PTRUES P0.H, VL8
ptrues p0.h, vl16
PTRUES P0.H, VL16
ptrues p0.h, vl32
PTRUES P0.H, VL32
ptrues p0.h, vl64
PTRUES P0.H, VL64
ptrues p0.h, vl128
PTRUES P0.H, VL128
ptrues p0.h, vl256
PTRUES P0.H, VL256
ptrues p0.h, #14
PTRUES P0.H, #14
ptrues p0.h, #15
PTRUES P0.H, #15
ptrues p0.h, #16
PTRUES P0.H, #16
ptrues p0.h, #17
PTRUES P0.H, #17
ptrues p0.h, #18
PTRUES P0.H, #18
ptrues p0.h, #19
PTRUES P0.H, #19
ptrues p0.h, #20
PTRUES P0.H, #20
ptrues p0.h, #21
PTRUES P0.H, #21
ptrues p0.h, #22
PTRUES P0.H, #22
ptrues p0.h, #23
PTRUES P0.H, #23
ptrues p0.h, #24
PTRUES P0.H, #24
ptrues p0.h, #25
PTRUES P0.H, #25
ptrues p0.h, #26
PTRUES P0.H, #26
ptrues p0.h, #27
PTRUES P0.H, #27
ptrues p0.h, #28
PTRUES P0.H, #28
ptrues p0.h, mul4
PTRUES P0.H, MUL4
ptrues p0.h, mul3
PTRUES P0.H, MUL3
ptrues p0.h
PTRUES P0.H
ptrues p0.h, all
ptrues p0.s, pow2
PTRUES P0.S, POW2
ptrues p1.s, pow2
PTRUES P1.S, POW2
ptrues p15.s, pow2
PTRUES P15.S, POW2
ptrues p0.s, vl1
PTRUES P0.S, VL1
ptrues p0.s, vl2
PTRUES P0.S, VL2
ptrues p0.s, vl3
PTRUES P0.S, VL3
ptrues p0.s, vl4
PTRUES P0.S, VL4
ptrues p0.s, vl5
PTRUES P0.S, VL5
ptrues p0.s, vl6
PTRUES P0.S, VL6
ptrues p0.s, vl7
PTRUES P0.S, VL7
ptrues p0.s, vl8
PTRUES P0.S, VL8
ptrues p0.s, vl16
PTRUES P0.S, VL16
ptrues p0.s, vl32
PTRUES P0.S, VL32
ptrues p0.s, vl64
PTRUES P0.S, VL64
ptrues p0.s, vl128
PTRUES P0.S, VL128
ptrues p0.s, vl256
PTRUES P0.S, VL256
ptrues p0.s, #14
PTRUES P0.S, #14
ptrues p0.s, #15
PTRUES P0.S, #15
ptrues p0.s, #16
PTRUES P0.S, #16
ptrues p0.s, #17
PTRUES P0.S, #17
ptrues p0.s, #18
PTRUES P0.S, #18
ptrues p0.s, #19
PTRUES P0.S, #19
ptrues p0.s, #20
PTRUES P0.S, #20
ptrues p0.s, #21
PTRUES P0.S, #21
ptrues p0.s, #22
PTRUES P0.S, #22
ptrues p0.s, #23
PTRUES P0.S, #23
ptrues p0.s, #24
PTRUES P0.S, #24
ptrues p0.s, #25
PTRUES P0.S, #25
ptrues p0.s, #26
PTRUES P0.S, #26
ptrues p0.s, #27
PTRUES P0.S, #27
ptrues p0.s, #28
PTRUES P0.S, #28
ptrues p0.s, mul4
PTRUES P0.S, MUL4
ptrues p0.s, mul3
PTRUES P0.S, MUL3
ptrues p0.s
PTRUES P0.S
ptrues p0.s, all
ptrues p0.d, pow2
PTRUES P0.D, POW2
ptrues p1.d, pow2
PTRUES P1.D, POW2
ptrues p15.d, pow2
PTRUES P15.D, POW2
ptrues p0.d, vl1
PTRUES P0.D, VL1
ptrues p0.d, vl2
PTRUES P0.D, VL2
ptrues p0.d, vl3
PTRUES P0.D, VL3
ptrues p0.d, vl4
PTRUES P0.D, VL4
ptrues p0.d, vl5
PTRUES P0.D, VL5
ptrues p0.d, vl6
PTRUES P0.D, VL6
ptrues p0.d, vl7
PTRUES P0.D, VL7
ptrues p0.d, vl8
PTRUES P0.D, VL8
ptrues p0.d, vl16
PTRUES P0.D, VL16
ptrues p0.d, vl32
PTRUES P0.D, VL32
ptrues p0.d, vl64
PTRUES P0.D, VL64
ptrues p0.d, vl128
PTRUES P0.D, VL128
ptrues p0.d, vl256
PTRUES P0.D, VL256
ptrues p0.d, #14
PTRUES P0.D, #14
ptrues p0.d, #15
PTRUES P0.D, #15
ptrues p0.d, #16
PTRUES P0.D, #16
ptrues p0.d, #17
PTRUES P0.D, #17
ptrues p0.d, #18
PTRUES P0.D, #18
ptrues p0.d, #19
PTRUES P0.D, #19
ptrues p0.d, #20
PTRUES P0.D, #20
ptrues p0.d, #21
PTRUES P0.D, #21
ptrues p0.d, #22
PTRUES P0.D, #22
ptrues p0.d, #23
PTRUES P0.D, #23
ptrues p0.d, #24
PTRUES P0.D, #24
ptrues p0.d, #25
PTRUES P0.D, #25
ptrues p0.d, #26
PTRUES P0.D, #26
ptrues p0.d, #27
PTRUES P0.D, #27
ptrues p0.d, #28
PTRUES P0.D, #28
ptrues p0.d, mul4
PTRUES P0.D, MUL4
ptrues p0.d, mul3
PTRUES P0.D, MUL3
ptrues p0.d
PTRUES P0.D
ptrues p0.d, all
punpkhi p0.h, p0.b
PUNPKHI P0.H, P0.B
punpkhi p1.h, p0.b
PUNPKHI P1.H, P0.B
punpkhi p15.h, p0.b
PUNPKHI P15.H, P0.B
punpkhi p0.h, p2.b
PUNPKHI P0.H, P2.B
punpkhi p0.h, p15.b
PUNPKHI P0.H, P15.B
punpklo p0.h, p0.b
PUNPKLO P0.H, P0.B
punpklo p1.h, p0.b
PUNPKLO P1.H, P0.B
punpklo p15.h, p0.b
PUNPKLO P15.H, P0.B
punpklo p0.h, p2.b
PUNPKLO P0.H, P2.B
punpklo p0.h, p15.b
PUNPKLO P0.H, P15.B
rbit z0.b, p0/m, z0.b
RBIT Z0.B, P0/M, Z0.B
rbit z1.b, p0/m, z0.b
RBIT Z1.B, P0/M, Z0.B
rbit z31.b, p0/m, z0.b
RBIT Z31.B, P0/M, Z0.B
rbit z0.b, p2/m, z0.b
RBIT Z0.B, P2/M, Z0.B
rbit z0.b, p7/m, z0.b
RBIT Z0.B, P7/M, Z0.B
rbit z0.b, p0/m, z3.b
RBIT Z0.B, P0/M, Z3.B
rbit z0.b, p0/m, z31.b
RBIT Z0.B, P0/M, Z31.B
rbit z0.h, p0/m, z0.h
RBIT Z0.H, P0/M, Z0.H
rbit z1.h, p0/m, z0.h
RBIT Z1.H, P0/M, Z0.H
rbit z31.h, p0/m, z0.h
RBIT Z31.H, P0/M, Z0.H
rbit z0.h, p2/m, z0.h
RBIT Z0.H, P2/M, Z0.H
rbit z0.h, p7/m, z0.h
RBIT Z0.H, P7/M, Z0.H
rbit z0.h, p0/m, z3.h
RBIT Z0.H, P0/M, Z3.H
rbit z0.h, p0/m, z31.h
RBIT Z0.H, P0/M, Z31.H
rbit z0.s, p0/m, z0.s
RBIT Z0.S, P0/M, Z0.S
rbit z1.s, p0/m, z0.s
RBIT Z1.S, P0/M, Z0.S
rbit z31.s, p0/m, z0.s
RBIT Z31.S, P0/M, Z0.S
rbit z0.s, p2/m, z0.s
RBIT Z0.S, P2/M, Z0.S
rbit z0.s, p7/m, z0.s
RBIT Z0.S, P7/M, Z0.S
rbit z0.s, p0/m, z3.s
RBIT Z0.S, P0/M, Z3.S
rbit z0.s, p0/m, z31.s
RBIT Z0.S, P0/M, Z31.S
rbit z0.d, p0/m, z0.d
RBIT Z0.D, P0/M, Z0.D
rbit z1.d, p0/m, z0.d
RBIT Z1.D, P0/M, Z0.D
rbit z31.d, p0/m, z0.d
RBIT Z31.D, P0/M, Z0.D
rbit z0.d, p2/m, z0.d
RBIT Z0.D, P2/M, Z0.D
rbit z0.d, p7/m, z0.d
RBIT Z0.D, P7/M, Z0.D
rbit z0.d, p0/m, z3.d
RBIT Z0.D, P0/M, Z3.D
rbit z0.d, p0/m, z31.d
RBIT Z0.D, P0/M, Z31.D
rdffr p0.b
RDFFR P0.B
rdffr p1.b
RDFFR P1.B
rdffr p15.b
RDFFR P15.B
rdffr p0.b, p0/z
RDFFR P0.B, P0/Z
rdffr p1.b, p0/z
RDFFR P1.B, P0/Z
rdffr p15.b, p0/z
RDFFR P15.B, P0/Z
rdffr p0.b, p2/z
RDFFR P0.B, P2/Z
rdffr p0.b, p15/z
RDFFR P0.B, P15/Z
rdffrs p0.b, p0/z
RDFFRS P0.B, P0/Z
rdffrs p1.b, p0/z
RDFFRS P1.B, P0/Z
rdffrs p15.b, p0/z
RDFFRS P15.B, P0/Z
rdffrs p0.b, p2/z
RDFFRS P0.B, P2/Z
rdffrs p0.b, p15/z
RDFFRS P0.B, P15/Z
rdvl x0, #0
RDVL X0, #0
rdvl x1, #0
RDVL X1, #0
rdvl xzr, #0
RDVL XZR, #0
rdvl x0, #31
RDVL X0, #31
rdvl x0, #-32
RDVL X0, #-32
rdvl x0, #-31
RDVL X0, #-31
rdvl x0, #-1
RDVL X0, #-1
rev p0.b, p0.b
REV P0.B, P0.B
rev p1.b, p0.b
REV P1.B, P0.B
rev p15.b, p0.b
REV P15.B, P0.B
rev p0.b, p2.b
REV P0.B, P2.B
rev p0.b, p15.b
REV P0.B, P15.B
rev p0.h, p0.h
REV P0.H, P0.H
rev p1.h, p0.h
REV P1.H, P0.H
rev p15.h, p0.h
REV P15.H, P0.H
rev p0.h, p2.h
REV P0.H, P2.H
rev p0.h, p15.h
REV P0.H, P15.H
rev p0.s, p0.s
REV P0.S, P0.S
rev p1.s, p0.s
REV P1.S, P0.S
rev p15.s, p0.s
REV P15.S, P0.S
rev p0.s, p2.s
REV P0.S, P2.S
rev p0.s, p15.s
REV P0.S, P15.S
rev p0.d, p0.d
REV P0.D, P0.D
rev p1.d, p0.d
REV P1.D, P0.D
rev p15.d, p0.d
REV P15.D, P0.D
rev p0.d, p2.d
REV P0.D, P2.D
rev p0.d, p15.d
REV P0.D, P15.D
rev z0.b, z0.b
REV Z0.B, Z0.B
rev z1.b, z0.b
REV Z1.B, Z0.B
rev z31.b, z0.b
REV Z31.B, Z0.B
rev z0.b, z2.b
REV Z0.B, Z2.B
rev z0.b, z31.b
REV Z0.B, Z31.B
rev z0.h, z0.h
REV Z0.H, Z0.H
rev z1.h, z0.h
REV Z1.H, Z0.H
rev z31.h, z0.h
REV Z31.H, Z0.H
rev z0.h, z2.h
REV Z0.H, Z2.H
rev z0.h, z31.h
REV Z0.H, Z31.H
rev z0.s, z0.s
REV Z0.S, Z0.S
rev z1.s, z0.s
REV Z1.S, Z0.S
rev z31.s, z0.s
REV Z31.S, Z0.S
rev z0.s, z2.s
REV Z0.S, Z2.S
rev z0.s, z31.s
REV Z0.S, Z31.S
rev z0.d, z0.d
REV Z0.D, Z0.D
rev z1.d, z0.d
REV Z1.D, Z0.D
rev z31.d, z0.d
REV Z31.D, Z0.D
rev z0.d, z2.d
REV Z0.D, Z2.D
rev z0.d, z31.d
REV Z0.D, Z31.D
revb z0.h, p0/m, z0.h
REVB Z0.H, P0/M, Z0.H
revb z1.h, p0/m, z0.h
REVB Z1.H, P0/M, Z0.H
revb z31.h, p0/m, z0.h
REVB Z31.H, P0/M, Z0.H
revb z0.h, p2/m, z0.h
REVB Z0.H, P2/M, Z0.H
revb z0.h, p7/m, z0.h
REVB Z0.H, P7/M, Z0.H
revb z0.h, p0/m, z3.h
REVB Z0.H, P0/M, Z3.H
revb z0.h, p0/m, z31.h
REVB Z0.H, P0/M, Z31.H
revb z0.s, p0/m, z0.s
REVB Z0.S, P0/M, Z0.S
revb z1.s, p0/m, z0.s
REVB Z1.S, P0/M, Z0.S
revb z31.s, p0/m, z0.s
REVB Z31.S, P0/M, Z0.S
revb z0.s, p2/m, z0.s
REVB Z0.S, P2/M, Z0.S
revb z0.s, p7/m, z0.s
REVB Z0.S, P7/M, Z0.S
revb z0.s, p0/m, z3.s
REVB Z0.S, P0/M, Z3.S
revb z0.s, p0/m, z31.s
REVB Z0.S, P0/M, Z31.S
revb z0.d, p0/m, z0.d
REVB Z0.D, P0/M, Z0.D
revb z1.d, p0/m, z0.d
REVB Z1.D, P0/M, Z0.D
revb z31.d, p0/m, z0.d
REVB Z31.D, P0/M, Z0.D
revb z0.d, p2/m, z0.d
REVB Z0.D, P2/M, Z0.D
revb z0.d, p7/m, z0.d
REVB Z0.D, P7/M, Z0.D
revb z0.d, p0/m, z3.d
REVB Z0.D, P0/M, Z3.D
revb z0.d, p0/m, z31.d
REVB Z0.D, P0/M, Z31.D
revh z0.s, p0/m, z0.s
REVH Z0.S, P0/M, Z0.S
revh z1.s, p0/m, z0.s
REVH Z1.S, P0/M, Z0.S
revh z31.s, p0/m, z0.s
REVH Z31.S, P0/M, Z0.S
revh z0.s, p2/m, z0.s
REVH Z0.S, P2/M, Z0.S
revh z0.s, p7/m, z0.s
REVH Z0.S, P7/M, Z0.S
revh z0.s, p0/m, z3.s
REVH Z0.S, P0/M, Z3.S
revh z0.s, p0/m, z31.s
REVH Z0.S, P0/M, Z31.S
revh z0.d, p0/m, z0.d
REVH Z0.D, P0/M, Z0.D
revh z1.d, p0/m, z0.d
REVH Z1.D, P0/M, Z0.D
revh z31.d, p0/m, z0.d
REVH Z31.D, P0/M, Z0.D
revh z0.d, p2/m, z0.d
REVH Z0.D, P2/M, Z0.D
revh z0.d, p7/m, z0.d
REVH Z0.D, P7/M, Z0.D
revh z0.d, p0/m, z3.d
REVH Z0.D, P0/M, Z3.D
revh z0.d, p0/m, z31.d
REVH Z0.D, P0/M, Z31.D
revw z0.d, p0/m, z0.d
REVW Z0.D, P0/M, Z0.D
revw z1.d, p0/m, z0.d
REVW Z1.D, P0/M, Z0.D
revw z31.d, p0/m, z0.d
REVW Z31.D, P0/M, Z0.D
revw z0.d, p2/m, z0.d
REVW Z0.D, P2/M, Z0.D
revw z0.d, p7/m, z0.d
REVW Z0.D, P7/M, Z0.D
revw z0.d, p0/m, z3.d
REVW Z0.D, P0/M, Z3.D
revw z0.d, p0/m, z31.d
REVW Z0.D, P0/M, Z31.D
sabd z0.b, p0/m, z0.b, z0.b
SABD Z0.B, P0/M, Z0.B, Z0.B
sabd z1.b, p0/m, z1.b, z0.b
SABD Z1.B, P0/M, Z1.B, Z0.B
sabd z31.b, p0/m, z31.b, z0.b
SABD Z31.B, P0/M, Z31.B, Z0.B
sabd z0.b, p2/m, z0.b, z0.b
SABD Z0.B, P2/M, Z0.B, Z0.B
sabd z0.b, p7/m, z0.b, z0.b
SABD Z0.B, P7/M, Z0.B, Z0.B
sabd z3.b, p0/m, z3.b, z0.b
SABD Z3.B, P0/M, Z3.B, Z0.B
sabd z0.b, p0/m, z0.b, z4.b
SABD Z0.B, P0/M, Z0.B, Z4.B
sabd z0.b, p0/m, z0.b, z31.b
SABD Z0.B, P0/M, Z0.B, Z31.B
sabd z0.h, p0/m, z0.h, z0.h
SABD Z0.H, P0/M, Z0.H, Z0.H
sabd z1.h, p0/m, z1.h, z0.h
SABD Z1.H, P0/M, Z1.H, Z0.H
sabd z31.h, p0/m, z31.h, z0.h
SABD Z31.H, P0/M, Z31.H, Z0.H
sabd z0.h, p2/m, z0.h, z0.h
SABD Z0.H, P2/M, Z0.H, Z0.H
sabd z0.h, p7/m, z0.h, z0.h
SABD Z0.H, P7/M, Z0.H, Z0.H
sabd z3.h, p0/m, z3.h, z0.h
SABD Z3.H, P0/M, Z3.H, Z0.H
sabd z0.h, p0/m, z0.h, z4.h
SABD Z0.H, P0/M, Z0.H, Z4.H
sabd z0.h, p0/m, z0.h, z31.h
SABD Z0.H, P0/M, Z0.H, Z31.H
sabd z0.s, p0/m, z0.s, z0.s
SABD Z0.S, P0/M, Z0.S, Z0.S
sabd z1.s, p0/m, z1.s, z0.s
SABD Z1.S, P0/M, Z1.S, Z0.S
sabd z31.s, p0/m, z31.s, z0.s
SABD Z31.S, P0/M, Z31.S, Z0.S
sabd z0.s, p2/m, z0.s, z0.s
SABD Z0.S, P2/M, Z0.S, Z0.S
sabd z0.s, p7/m, z0.s, z0.s
SABD Z0.S, P7/M, Z0.S, Z0.S
sabd z3.s, p0/m, z3.s, z0.s
SABD Z3.S, P0/M, Z3.S, Z0.S
sabd z0.s, p0/m, z0.s, z4.s
SABD Z0.S, P0/M, Z0.S, Z4.S
sabd z0.s, p0/m, z0.s, z31.s
SABD Z0.S, P0/M, Z0.S, Z31.S
sabd z0.d, p0/m, z0.d, z0.d
SABD Z0.D, P0/M, Z0.D, Z0.D
sabd z1.d, p0/m, z1.d, z0.d
SABD Z1.D, P0/M, Z1.D, Z0.D
sabd z31.d, p0/m, z31.d, z0.d
SABD Z31.D, P0/M, Z31.D, Z0.D
sabd z0.d, p2/m, z0.d, z0.d
SABD Z0.D, P2/M, Z0.D, Z0.D
sabd z0.d, p7/m, z0.d, z0.d
SABD Z0.D, P7/M, Z0.D, Z0.D
sabd z3.d, p0/m, z3.d, z0.d
SABD Z3.D, P0/M, Z3.D, Z0.D
sabd z0.d, p0/m, z0.d, z4.d
SABD Z0.D, P0/M, Z0.D, Z4.D
sabd z0.d, p0/m, z0.d, z31.d
SABD Z0.D, P0/M, Z0.D, Z31.D
saddv d0, p0, z0.b
SADDV D0, P0, Z0.B
saddv d1, p0, z0.b
SADDV D1, P0, Z0.B
saddv d31, p0, z0.b
SADDV D31, P0, Z0.B
saddv d0, p2, z0.b
SADDV D0, P2, Z0.B
saddv d0, p7, z0.b
SADDV D0, P7, Z0.B
saddv d0, p0, z3.b
SADDV D0, P0, Z3.B
saddv d0, p0, z31.b
SADDV D0, P0, Z31.B
saddv d0, p0, z0.h
SADDV D0, P0, Z0.H
saddv d1, p0, z0.h
SADDV D1, P0, Z0.H
saddv d31, p0, z0.h
SADDV D31, P0, Z0.H
saddv d0, p2, z0.h
SADDV D0, P2, Z0.H
saddv d0, p7, z0.h
SADDV D0, P7, Z0.H
saddv d0, p0, z3.h
SADDV D0, P0, Z3.H
saddv d0, p0, z31.h
SADDV D0, P0, Z31.H
saddv d0, p0, z0.s
SADDV D0, P0, Z0.S
saddv d1, p0, z0.s
SADDV D1, P0, Z0.S
saddv d31, p0, z0.s
SADDV D31, P0, Z0.S
saddv d0, p2, z0.s
SADDV D0, P2, Z0.S
saddv d0, p7, z0.s
SADDV D0, P7, Z0.S
saddv d0, p0, z3.s
SADDV D0, P0, Z3.S
saddv d0, p0, z31.s
SADDV D0, P0, Z31.S
scvtf z0.h, p0/m, z0.h
SCVTF Z0.H, P0/M, Z0.H
scvtf z1.h, p0/m, z0.h
SCVTF Z1.H, P0/M, Z0.H
scvtf z31.h, p0/m, z0.h
SCVTF Z31.H, P0/M, Z0.H
scvtf z0.h, p2/m, z0.h
SCVTF Z0.H, P2/M, Z0.H
scvtf z0.h, p7/m, z0.h
SCVTF Z0.H, P7/M, Z0.H
scvtf z0.h, p0/m, z3.h
SCVTF Z0.H, P0/M, Z3.H
scvtf z0.h, p0/m, z31.h
SCVTF Z0.H, P0/M, Z31.H
scvtf z0.h, p0/m, z0.s
SCVTF Z0.H, P0/M, Z0.S
scvtf z1.h, p0/m, z0.s
SCVTF Z1.H, P0/M, Z0.S
scvtf z31.h, p0/m, z0.s
SCVTF Z31.H, P0/M, Z0.S
scvtf z0.h, p2/m, z0.s
SCVTF Z0.H, P2/M, Z0.S
scvtf z0.h, p7/m, z0.s
SCVTF Z0.H, P7/M, Z0.S
scvtf z0.h, p0/m, z3.s
SCVTF Z0.H, P0/M, Z3.S
scvtf z0.h, p0/m, z31.s
SCVTF Z0.H, P0/M, Z31.S
scvtf z0.s, p0/m, z0.s
SCVTF Z0.S, P0/M, Z0.S
scvtf z1.s, p0/m, z0.s
SCVTF Z1.S, P0/M, Z0.S
scvtf z31.s, p0/m, z0.s
SCVTF Z31.S, P0/M, Z0.S
scvtf z0.s, p2/m, z0.s
SCVTF Z0.S, P2/M, Z0.S
scvtf z0.s, p7/m, z0.s
SCVTF Z0.S, P7/M, Z0.S
scvtf z0.s, p0/m, z3.s
SCVTF Z0.S, P0/M, Z3.S
scvtf z0.s, p0/m, z31.s
SCVTF Z0.S, P0/M, Z31.S
scvtf z0.d, p0/m, z0.s
SCVTF Z0.D, P0/M, Z0.S
scvtf z1.d, p0/m, z0.s
SCVTF Z1.D, P0/M, Z0.S
scvtf z31.d, p0/m, z0.s
SCVTF Z31.D, P0/M, Z0.S
scvtf z0.d, p2/m, z0.s
SCVTF Z0.D, P2/M, Z0.S
scvtf z0.d, p7/m, z0.s
SCVTF Z0.D, P7/M, Z0.S
scvtf z0.d, p0/m, z3.s
SCVTF Z0.D, P0/M, Z3.S
scvtf z0.d, p0/m, z31.s
SCVTF Z0.D, P0/M, Z31.S
scvtf z0.h, p0/m, z0.d
SCVTF Z0.H, P0/M, Z0.D
scvtf z1.h, p0/m, z0.d
SCVTF Z1.H, P0/M, Z0.D
scvtf z31.h, p0/m, z0.d
SCVTF Z31.H, P0/M, Z0.D
scvtf z0.h, p2/m, z0.d
SCVTF Z0.H, P2/M, Z0.D
scvtf z0.h, p7/m, z0.d
SCVTF Z0.H, P7/M, Z0.D
scvtf z0.h, p0/m, z3.d
SCVTF Z0.H, P0/M, Z3.D
scvtf z0.h, p0/m, z31.d
SCVTF Z0.H, P0/M, Z31.D
scvtf z0.s, p0/m, z0.d
SCVTF Z0.S, P0/M, Z0.D
scvtf z1.s, p0/m, z0.d
SCVTF Z1.S, P0/M, Z0.D
scvtf z31.s, p0/m, z0.d
SCVTF Z31.S, P0/M, Z0.D
scvtf z0.s, p2/m, z0.d
SCVTF Z0.S, P2/M, Z0.D
scvtf z0.s, p7/m, z0.d
SCVTF Z0.S, P7/M, Z0.D
scvtf z0.s, p0/m, z3.d
SCVTF Z0.S, P0/M, Z3.D
scvtf z0.s, p0/m, z31.d
SCVTF Z0.S, P0/M, Z31.D
scvtf z0.d, p0/m, z0.d
SCVTF Z0.D, P0/M, Z0.D
scvtf z1.d, p0/m, z0.d
SCVTF Z1.D, P0/M, Z0.D
scvtf z31.d, p0/m, z0.d
SCVTF Z31.D, P0/M, Z0.D
scvtf z0.d, p2/m, z0.d
SCVTF Z0.D, P2/M, Z0.D
scvtf z0.d, p7/m, z0.d
SCVTF Z0.D, P7/M, Z0.D
scvtf z0.d, p0/m, z3.d
SCVTF Z0.D, P0/M, Z3.D
scvtf z0.d, p0/m, z31.d
SCVTF Z0.D, P0/M, Z31.D
sdiv z0.s, p0/m, z0.s, z0.s
SDIV Z0.S, P0/M, Z0.S, Z0.S
sdiv z1.s, p0/m, z1.s, z0.s
SDIV Z1.S, P0/M, Z1.S, Z0.S
sdiv z31.s, p0/m, z31.s, z0.s
SDIV Z31.S, P0/M, Z31.S, Z0.S
sdiv z0.s, p2/m, z0.s, z0.s
SDIV Z0.S, P2/M, Z0.S, Z0.S
sdiv z0.s, p7/m, z0.s, z0.s
SDIV Z0.S, P7/M, Z0.S, Z0.S
sdiv z3.s, p0/m, z3.s, z0.s
SDIV Z3.S, P0/M, Z3.S, Z0.S
sdiv z0.s, p0/m, z0.s, z4.s
SDIV Z0.S, P0/M, Z0.S, Z4.S
sdiv z0.s, p0/m, z0.s, z31.s
SDIV Z0.S, P0/M, Z0.S, Z31.S
sdiv z0.d, p0/m, z0.d, z0.d
SDIV Z0.D, P0/M, Z0.D, Z0.D
sdiv z1.d, p0/m, z1.d, z0.d
SDIV Z1.D, P0/M, Z1.D, Z0.D
sdiv z31.d, p0/m, z31.d, z0.d
SDIV Z31.D, P0/M, Z31.D, Z0.D
sdiv z0.d, p2/m, z0.d, z0.d
SDIV Z0.D, P2/M, Z0.D, Z0.D
sdiv z0.d, p7/m, z0.d, z0.d
SDIV Z0.D, P7/M, Z0.D, Z0.D
sdiv z3.d, p0/m, z3.d, z0.d
SDIV Z3.D, P0/M, Z3.D, Z0.D
sdiv z0.d, p0/m, z0.d, z4.d
SDIV Z0.D, P0/M, Z0.D, Z4.D
sdiv z0.d, p0/m, z0.d, z31.d
SDIV Z0.D, P0/M, Z0.D, Z31.D
sdivr z0.s, p0/m, z0.s, z0.s
SDIVR Z0.S, P0/M, Z0.S, Z0.S
sdivr z1.s, p0/m, z1.s, z0.s
SDIVR Z1.S, P0/M, Z1.S, Z0.S
sdivr z31.s, p0/m, z31.s, z0.s
SDIVR Z31.S, P0/M, Z31.S, Z0.S
sdivr z0.s, p2/m, z0.s, z0.s
SDIVR Z0.S, P2/M, Z0.S, Z0.S
sdivr z0.s, p7/m, z0.s, z0.s
SDIVR Z0.S, P7/M, Z0.S, Z0.S
sdivr z3.s, p0/m, z3.s, z0.s
SDIVR Z3.S, P0/M, Z3.S, Z0.S
sdivr z0.s, p0/m, z0.s, z4.s
SDIVR Z0.S, P0/M, Z0.S, Z4.S
sdivr z0.s, p0/m, z0.s, z31.s
SDIVR Z0.S, P0/M, Z0.S, Z31.S
sdivr z0.d, p0/m, z0.d, z0.d
SDIVR Z0.D, P0/M, Z0.D, Z0.D
sdivr z1.d, p0/m, z1.d, z0.d
SDIVR Z1.D, P0/M, Z1.D, Z0.D
sdivr z31.d, p0/m, z31.d, z0.d
SDIVR Z31.D, P0/M, Z31.D, Z0.D
sdivr z0.d, p2/m, z0.d, z0.d
SDIVR Z0.D, P2/M, Z0.D, Z0.D
sdivr z0.d, p7/m, z0.d, z0.d
SDIVR Z0.D, P7/M, Z0.D, Z0.D
sdivr z3.d, p0/m, z3.d, z0.d
SDIVR Z3.D, P0/M, Z3.D, Z0.D
sdivr z0.d, p0/m, z0.d, z4.d
SDIVR Z0.D, P0/M, Z0.D, Z4.D
sdivr z0.d, p0/m, z0.d, z31.d
SDIVR Z0.D, P0/M, Z0.D, Z31.D
sdot z0.s, z0.b, z0.b
SDOT Z0.S, Z0.B, Z0.B
sdot z1.s, z0.b, z0.b
SDOT Z1.S, Z0.B, Z0.B
sdot z31.s, z0.b, z0.b
SDOT Z31.S, Z0.B, Z0.B
sdot z0.s, z2.b, z0.b
SDOT Z0.S, Z2.B, Z0.B
sdot z0.s, z31.b, z0.b
SDOT Z0.S, Z31.B, Z0.B
sdot z0.s, z0.b, z3.b
SDOT Z0.S, Z0.B, Z3.B
sdot z0.s, z0.b, z31.b
SDOT Z0.S, Z0.B, Z31.B
sdot z0.d, z0.h, z0.h
SDOT Z0.D, Z0.H, Z0.H
sdot z1.d, z0.h, z0.h
SDOT Z1.D, Z0.H, Z0.H
sdot z31.d, z0.h, z0.h
SDOT Z31.D, Z0.H, Z0.H
sdot z0.d, z2.h, z0.h
SDOT Z0.D, Z2.H, Z0.H
sdot z0.d, z31.h, z0.h
SDOT Z0.D, Z31.H, Z0.H
sdot z0.d, z0.h, z3.h
SDOT Z0.D, Z0.H, Z3.H
sdot z0.d, z0.h, z31.h
SDOT Z0.D, Z0.H, Z31.H
sdot z0.s, z0.b, z0.b[0]
SDOT Z0.S, Z0.B, Z0.B[0]
sdot z1.s, z0.b, z0.b[0]
SDOT Z1.S, Z0.B, Z0.B[0]
sdot z31.s, z0.b, z0.b[0]
SDOT Z31.S, Z0.B, Z0.B[0]
sdot z0.s, z2.b, z0.b[0]
SDOT Z0.S, Z2.B, Z0.B[0]
sdot z0.s, z31.b, z0.b[0]
SDOT Z0.S, Z31.B, Z0.B[0]
sdot z0.s, z0.b, z3.b[0]
SDOT Z0.S, Z0.B, Z3.B[0]
sdot z0.s, z0.b, z7.b[0]
SDOT Z0.S, Z0.B, Z7.B[0]
sdot z0.s, z0.b, z0.b[1]
SDOT Z0.S, Z0.B, Z0.B[1]
sdot z0.s, z0.b, z4.b[1]
SDOT Z0.S, Z0.B, Z4.B[1]
sdot z0.s, z0.b, z3.b[2]
SDOT Z0.S, Z0.B, Z3.B[2]
sdot z0.s, z0.b, z0.b[3]
SDOT Z0.S, Z0.B, Z0.B[3]
sdot z0.s, z0.b, z5.b[3]
SDOT Z0.S, Z0.B, Z5.B[3]
sdot z0.d, z0.h, z0.h[0]
SDOT Z0.D, Z0.H, Z0.H[0]
sdot z1.d, z0.h, z0.h[0]
SDOT Z1.D, Z0.H, Z0.H[0]
sdot z31.d, z0.h, z0.h[0]
SDOT Z31.D, Z0.H, Z0.H[0]
sdot z0.d, z2.h, z0.h[0]
SDOT Z0.D, Z2.H, Z0.H[0]
sdot z0.d, z31.h, z0.h[0]
SDOT Z0.D, Z31.H, Z0.H[0]
sdot z0.d, z0.h, z3.h[0]
SDOT Z0.D, Z0.H, Z3.H[0]
sdot z0.d, z0.h, z15.h[0]
SDOT Z0.D, Z0.H, Z15.H[0]
sdot z0.d, z0.h, z0.h[1]
SDOT Z0.D, Z0.H, Z0.H[1]
sdot z0.d, z0.h, z11.h[1]
SDOT Z0.D, Z0.H, Z11.H[1]
sel z0.b, p0, z0.b, z0.b
SEL Z0.B, P0, Z0.B, Z0.B
sel z1.b, p0, z0.b, z0.b
SEL Z1.B, P0, Z0.B, Z0.B
sel z31.b, p0, z0.b, z0.b
SEL Z31.B, P0, Z0.B, Z0.B
sel z0.b, p2, z0.b, z0.b
SEL Z0.B, P2, Z0.B, Z0.B
sel z0.b, p15, z0.b, z0.b
SEL Z0.B, P15, Z0.B, Z0.B
sel z0.b, p0, z3.b, z0.b
SEL Z0.B, P0, Z3.B, Z0.B
sel z0.b, p0, z31.b, z0.b
SEL Z0.B, P0, Z31.B, Z0.B
sel z0.b, p0, z0.b, z4.b
SEL Z0.B, P0, Z0.B, Z4.B
sel z0.b, p0, z0.b, z31.b
SEL Z0.B, P0, Z0.B, Z31.B
sel z0.h, p0, z0.h, z0.h
SEL Z0.H, P0, Z0.H, Z0.H
sel z1.h, p0, z0.h, z0.h
SEL Z1.H, P0, Z0.H, Z0.H
sel z31.h, p0, z0.h, z0.h
SEL Z31.H, P0, Z0.H, Z0.H
sel z0.h, p2, z0.h, z0.h
SEL Z0.H, P2, Z0.H, Z0.H
sel z0.h, p15, z0.h, z0.h
SEL Z0.H, P15, Z0.H, Z0.H
sel z0.h, p0, z3.h, z0.h
SEL Z0.H, P0, Z3.H, Z0.H
sel z0.h, p0, z31.h, z0.h
SEL Z0.H, P0, Z31.H, Z0.H
sel z0.h, p0, z0.h, z4.h
SEL Z0.H, P0, Z0.H, Z4.H
sel z0.h, p0, z0.h, z31.h
SEL Z0.H, P0, Z0.H, Z31.H
sel z0.s, p0, z0.s, z0.s
SEL Z0.S, P0, Z0.S, Z0.S
sel z1.s, p0, z0.s, z0.s
SEL Z1.S, P0, Z0.S, Z0.S
sel z31.s, p0, z0.s, z0.s
SEL Z31.S, P0, Z0.S, Z0.S
sel z0.s, p2, z0.s, z0.s
SEL Z0.S, P2, Z0.S, Z0.S
sel z0.s, p15, z0.s, z0.s
SEL Z0.S, P15, Z0.S, Z0.S
sel z0.s, p0, z3.s, z0.s
SEL Z0.S, P0, Z3.S, Z0.S
sel z0.s, p0, z31.s, z0.s
SEL Z0.S, P0, Z31.S, Z0.S
sel z0.s, p0, z0.s, z4.s
SEL Z0.S, P0, Z0.S, Z4.S
sel z0.s, p0, z0.s, z31.s
SEL Z0.S, P0, Z0.S, Z31.S
sel z0.d, p0, z0.d, z0.d
SEL Z0.D, P0, Z0.D, Z0.D
sel z1.d, p0, z0.d, z0.d
SEL Z1.D, P0, Z0.D, Z0.D
sel z31.d, p0, z0.d, z0.d
SEL Z31.D, P0, Z0.D, Z0.D
sel z0.d, p2, z0.d, z0.d
SEL Z0.D, P2, Z0.D, Z0.D
sel z0.d, p15, z0.d, z0.d
SEL Z0.D, P15, Z0.D, Z0.D
sel z0.d, p0, z3.d, z0.d
SEL Z0.D, P0, Z3.D, Z0.D
sel z0.d, p0, z31.d, z0.d
SEL Z0.D, P0, Z31.D, Z0.D
sel z0.d, p0, z0.d, z4.d
SEL Z0.D, P0, Z0.D, Z4.D
sel z0.d, p0, z0.d, z31.d
SEL Z0.D, P0, Z0.D, Z31.D
sel p0.b, p0, p0.b, p0.b
SEL P0.B, P0, P0.B, P0.B
sel p1.b, p0, p0.b, p0.b
SEL P1.B, P0, P0.B, P0.B
sel p15.b, p0, p0.b, p0.b
SEL P15.B, P0, P0.B, P0.B
sel p0.b, p2, p0.b, p0.b
SEL P0.B, P2, P0.B, P0.B
sel p0.b, p15, p0.b, p0.b
SEL P0.B, P15, P0.B, P0.B
sel p0.b, p0, p3.b, p0.b
SEL P0.B, P0, P3.B, P0.B
sel p0.b, p0, p15.b, p0.b
SEL P0.B, P0, P15.B, P0.B
sel p0.b, p0, p0.b, p4.b
SEL P0.B, P0, P0.B, P4.B
sel p0.b, p0, p0.b, p15.b
SEL P0.B, P0, P0.B, P15.B
setffr
SETFFR
smax z0.b, z0.b, #0
SMAX Z0.B, Z0.B, #0
smax z1.b, z1.b, #0
SMAX Z1.B, Z1.B, #0
smax z31.b, z31.b, #0
SMAX Z31.B, Z31.B, #0
smax z2.b, z2.b, #0
SMAX Z2.B, Z2.B, #0
smax z0.b, z0.b, #127
SMAX Z0.B, Z0.B, #127
smax z0.b, z0.b, #-128
SMAX Z0.B, Z0.B, #-128
smax z0.b, z0.b, #-127
SMAX Z0.B, Z0.B, #-127
smax z0.b, z0.b, #-1
SMAX Z0.B, Z0.B, #-1
smax z0.h, z0.h, #0
SMAX Z0.H, Z0.H, #0
smax z1.h, z1.h, #0
SMAX Z1.H, Z1.H, #0
smax z31.h, z31.h, #0
SMAX Z31.H, Z31.H, #0
smax z2.h, z2.h, #0
SMAX Z2.H, Z2.H, #0
smax z0.h, z0.h, #127
SMAX Z0.H, Z0.H, #127
smax z0.h, z0.h, #-128
SMAX Z0.H, Z0.H, #-128
smax z0.h, z0.h, #-127
SMAX Z0.H, Z0.H, #-127
smax z0.h, z0.h, #-1
SMAX Z0.H, Z0.H, #-1
smax z0.s, z0.s, #0
SMAX Z0.S, Z0.S, #0
smax z1.s, z1.s, #0
SMAX Z1.S, Z1.S, #0
smax z31.s, z31.s, #0
SMAX Z31.S, Z31.S, #0
smax z2.s, z2.s, #0
SMAX Z2.S, Z2.S, #0
smax z0.s, z0.s, #127
SMAX Z0.S, Z0.S, #127
smax z0.s, z0.s, #-128
SMAX Z0.S, Z0.S, #-128
smax z0.s, z0.s, #-127
SMAX Z0.S, Z0.S, #-127
smax z0.s, z0.s, #-1
SMAX Z0.S, Z0.S, #-1
smax z0.d, z0.d, #0
SMAX Z0.D, Z0.D, #0
smax z1.d, z1.d, #0
SMAX Z1.D, Z1.D, #0
smax z31.d, z31.d, #0
SMAX Z31.D, Z31.D, #0
smax z2.d, z2.d, #0
SMAX Z2.D, Z2.D, #0
smax z0.d, z0.d, #127
SMAX Z0.D, Z0.D, #127
smax z0.d, z0.d, #-128
SMAX Z0.D, Z0.D, #-128
smax z0.d, z0.d, #-127
SMAX Z0.D, Z0.D, #-127
smax z0.d, z0.d, #-1
SMAX Z0.D, Z0.D, #-1
smax z0.b, p0/m, z0.b, z0.b
SMAX Z0.B, P0/M, Z0.B, Z0.B
smax z1.b, p0/m, z1.b, z0.b
SMAX Z1.B, P0/M, Z1.B, Z0.B
smax z31.b, p0/m, z31.b, z0.b
SMAX Z31.B, P0/M, Z31.B, Z0.B
smax z0.b, p2/m, z0.b, z0.b
SMAX Z0.B, P2/M, Z0.B, Z0.B
smax z0.b, p7/m, z0.b, z0.b
SMAX Z0.B, P7/M, Z0.B, Z0.B
smax z3.b, p0/m, z3.b, z0.b
SMAX Z3.B, P0/M, Z3.B, Z0.B
smax z0.b, p0/m, z0.b, z4.b
SMAX Z0.B, P0/M, Z0.B, Z4.B
smax z0.b, p0/m, z0.b, z31.b
SMAX Z0.B, P0/M, Z0.B, Z31.B
smax z0.h, p0/m, z0.h, z0.h
SMAX Z0.H, P0/M, Z0.H, Z0.H
smax z1.h, p0/m, z1.h, z0.h
SMAX Z1.H, P0/M, Z1.H, Z0.H
smax z31.h, p0/m, z31.h, z0.h
SMAX Z31.H, P0/M, Z31.H, Z0.H
smax z0.h, p2/m, z0.h, z0.h
SMAX Z0.H, P2/M, Z0.H, Z0.H
smax z0.h, p7/m, z0.h, z0.h
SMAX Z0.H, P7/M, Z0.H, Z0.H
smax z3.h, p0/m, z3.h, z0.h
SMAX Z3.H, P0/M, Z3.H, Z0.H
smax z0.h, p0/m, z0.h, z4.h
SMAX Z0.H, P0/M, Z0.H, Z4.H
smax z0.h, p0/m, z0.h, z31.h
SMAX Z0.H, P0/M, Z0.H, Z31.H
smax z0.s, p0/m, z0.s, z0.s
SMAX Z0.S, P0/M, Z0.S, Z0.S
smax z1.s, p0/m, z1.s, z0.s
SMAX Z1.S, P0/M, Z1.S, Z0.S
smax z31.s, p0/m, z31.s, z0.s
SMAX Z31.S, P0/M, Z31.S, Z0.S
smax z0.s, p2/m, z0.s, z0.s
SMAX Z0.S, P2/M, Z0.S, Z0.S
smax z0.s, p7/m, z0.s, z0.s
SMAX Z0.S, P7/M, Z0.S, Z0.S
smax z3.s, p0/m, z3.s, z0.s
SMAX Z3.S, P0/M, Z3.S, Z0.S
smax z0.s, p0/m, z0.s, z4.s
SMAX Z0.S, P0/M, Z0.S, Z4.S
smax z0.s, p0/m, z0.s, z31.s
SMAX Z0.S, P0/M, Z0.S, Z31.S
smax z0.d, p0/m, z0.d, z0.d
SMAX Z0.D, P0/M, Z0.D, Z0.D
smax z1.d, p0/m, z1.d, z0.d
SMAX Z1.D, P0/M, Z1.D, Z0.D
smax z31.d, p0/m, z31.d, z0.d
SMAX Z31.D, P0/M, Z31.D, Z0.D
smax z0.d, p2/m, z0.d, z0.d
SMAX Z0.D, P2/M, Z0.D, Z0.D
smax z0.d, p7/m, z0.d, z0.d
SMAX Z0.D, P7/M, Z0.D, Z0.D
smax z3.d, p0/m, z3.d, z0.d
SMAX Z3.D, P0/M, Z3.D, Z0.D
smax z0.d, p0/m, z0.d, z4.d
SMAX Z0.D, P0/M, Z0.D, Z4.D
smax z0.d, p0/m, z0.d, z31.d
SMAX Z0.D, P0/M, Z0.D, Z31.D
smaxv b0, p0, z0.b
SMAXV B0, P0, Z0.B
smaxv b1, p0, z0.b
SMAXV B1, P0, Z0.B
smaxv b31, p0, z0.b
SMAXV B31, P0, Z0.B
smaxv b0, p2, z0.b
SMAXV B0, P2, Z0.B
smaxv b0, p7, z0.b
SMAXV B0, P7, Z0.B
smaxv b0, p0, z3.b
SMAXV B0, P0, Z3.B
smaxv b0, p0, z31.b
SMAXV B0, P0, Z31.B
smaxv h0, p0, z0.h
SMAXV H0, P0, Z0.H
smaxv h1, p0, z0.h
SMAXV H1, P0, Z0.H
smaxv h31, p0, z0.h
SMAXV H31, P0, Z0.H
smaxv h0, p2, z0.h
SMAXV H0, P2, Z0.H
smaxv h0, p7, z0.h
SMAXV H0, P7, Z0.H
smaxv h0, p0, z3.h
SMAXV H0, P0, Z3.H
smaxv h0, p0, z31.h
SMAXV H0, P0, Z31.H
smaxv s0, p0, z0.s
SMAXV S0, P0, Z0.S
smaxv s1, p0, z0.s
SMAXV S1, P0, Z0.S
smaxv s31, p0, z0.s
SMAXV S31, P0, Z0.S
smaxv s0, p2, z0.s
SMAXV S0, P2, Z0.S
smaxv s0, p7, z0.s
SMAXV S0, P7, Z0.S
smaxv s0, p0, z3.s
SMAXV S0, P0, Z3.S
smaxv s0, p0, z31.s
SMAXV S0, P0, Z31.S
smaxv d0, p0, z0.d
SMAXV D0, P0, Z0.D
smaxv d1, p0, z0.d
SMAXV D1, P0, Z0.D
smaxv d31, p0, z0.d
SMAXV D31, P0, Z0.D
smaxv d0, p2, z0.d
SMAXV D0, P2, Z0.D
smaxv d0, p7, z0.d
SMAXV D0, P7, Z0.D
smaxv d0, p0, z3.d
SMAXV D0, P0, Z3.D
smaxv d0, p0, z31.d
SMAXV D0, P0, Z31.D
smin z0.b, z0.b, #0
SMIN Z0.B, Z0.B, #0
smin z1.b, z1.b, #0
SMIN Z1.B, Z1.B, #0
smin z31.b, z31.b, #0
SMIN Z31.B, Z31.B, #0
smin z2.b, z2.b, #0
SMIN Z2.B, Z2.B, #0
smin z0.b, z0.b, #127
SMIN Z0.B, Z0.B, #127
smin z0.b, z0.b, #-128
SMIN Z0.B, Z0.B, #-128
smin z0.b, z0.b, #-127
SMIN Z0.B, Z0.B, #-127
smin z0.b, z0.b, #-1
SMIN Z0.B, Z0.B, #-1
smin z0.h, z0.h, #0
SMIN Z0.H, Z0.H, #0
smin z1.h, z1.h, #0
SMIN Z1.H, Z1.H, #0
smin z31.h, z31.h, #0
SMIN Z31.H, Z31.H, #0
smin z2.h, z2.h, #0
SMIN Z2.H, Z2.H, #0
smin z0.h, z0.h, #127
SMIN Z0.H, Z0.H, #127
smin z0.h, z0.h, #-128
SMIN Z0.H, Z0.H, #-128
smin z0.h, z0.h, #-127
SMIN Z0.H, Z0.H, #-127
smin z0.h, z0.h, #-1
SMIN Z0.H, Z0.H, #-1
smin z0.s, z0.s, #0
SMIN Z0.S, Z0.S, #0
smin z1.s, z1.s, #0
SMIN Z1.S, Z1.S, #0
smin z31.s, z31.s, #0
SMIN Z31.S, Z31.S, #0
smin z2.s, z2.s, #0
SMIN Z2.S, Z2.S, #0
smin z0.s, z0.s, #127
SMIN Z0.S, Z0.S, #127
smin z0.s, z0.s, #-128
SMIN Z0.S, Z0.S, #-128
smin z0.s, z0.s, #-127
SMIN Z0.S, Z0.S, #-127
smin z0.s, z0.s, #-1
SMIN Z0.S, Z0.S, #-1
smin z0.d, z0.d, #0
SMIN Z0.D, Z0.D, #0
smin z1.d, z1.d, #0
SMIN Z1.D, Z1.D, #0
smin z31.d, z31.d, #0
SMIN Z31.D, Z31.D, #0
smin z2.d, z2.d, #0
SMIN Z2.D, Z2.D, #0
smin z0.d, z0.d, #127
SMIN Z0.D, Z0.D, #127
smin z0.d, z0.d, #-128
SMIN Z0.D, Z0.D, #-128
smin z0.d, z0.d, #-127
SMIN Z0.D, Z0.D, #-127
smin z0.d, z0.d, #-1
SMIN Z0.D, Z0.D, #-1
smin z0.b, p0/m, z0.b, z0.b
SMIN Z0.B, P0/M, Z0.B, Z0.B
smin z1.b, p0/m, z1.b, z0.b
SMIN Z1.B, P0/M, Z1.B, Z0.B
smin z31.b, p0/m, z31.b, z0.b
SMIN Z31.B, P0/M, Z31.B, Z0.B
smin z0.b, p2/m, z0.b, z0.b
SMIN Z0.B, P2/M, Z0.B, Z0.B
smin z0.b, p7/m, z0.b, z0.b
SMIN Z0.B, P7/M, Z0.B, Z0.B
smin z3.b, p0/m, z3.b, z0.b
SMIN Z3.B, P0/M, Z3.B, Z0.B
smin z0.b, p0/m, z0.b, z4.b
SMIN Z0.B, P0/M, Z0.B, Z4.B
smin z0.b, p0/m, z0.b, z31.b
SMIN Z0.B, P0/M, Z0.B, Z31.B
smin z0.h, p0/m, z0.h, z0.h
SMIN Z0.H, P0/M, Z0.H, Z0.H
smin z1.h, p0/m, z1.h, z0.h
SMIN Z1.H, P0/M, Z1.H, Z0.H
smin z31.h, p0/m, z31.h, z0.h
SMIN Z31.H, P0/M, Z31.H, Z0.H
smin z0.h, p2/m, z0.h, z0.h
SMIN Z0.H, P2/M, Z0.H, Z0.H
smin z0.h, p7/m, z0.h, z0.h
SMIN Z0.H, P7/M, Z0.H, Z0.H
smin z3.h, p0/m, z3.h, z0.h
SMIN Z3.H, P0/M, Z3.H, Z0.H
smin z0.h, p0/m, z0.h, z4.h
SMIN Z0.H, P0/M, Z0.H, Z4.H
smin z0.h, p0/m, z0.h, z31.h
SMIN Z0.H, P0/M, Z0.H, Z31.H
smin z0.s, p0/m, z0.s, z0.s
SMIN Z0.S, P0/M, Z0.S, Z0.S
smin z1.s, p0/m, z1.s, z0.s
SMIN Z1.S, P0/M, Z1.S, Z0.S
smin z31.s, p0/m, z31.s, z0.s
SMIN Z31.S, P0/M, Z31.S, Z0.S
smin z0.s, p2/m, z0.s, z0.s
SMIN Z0.S, P2/M, Z0.S, Z0.S
smin z0.s, p7/m, z0.s, z0.s
SMIN Z0.S, P7/M, Z0.S, Z0.S
smin z3.s, p0/m, z3.s, z0.s
SMIN Z3.S, P0/M, Z3.S, Z0.S
smin z0.s, p0/m, z0.s, z4.s
SMIN Z0.S, P0/M, Z0.S, Z4.S
smin z0.s, p0/m, z0.s, z31.s
SMIN Z0.S, P0/M, Z0.S, Z31.S
smin z0.d, p0/m, z0.d, z0.d
SMIN Z0.D, P0/M, Z0.D, Z0.D
smin z1.d, p0/m, z1.d, z0.d
SMIN Z1.D, P0/M, Z1.D, Z0.D
smin z31.d, p0/m, z31.d, z0.d
SMIN Z31.D, P0/M, Z31.D, Z0.D
smin z0.d, p2/m, z0.d, z0.d
SMIN Z0.D, P2/M, Z0.D, Z0.D
smin z0.d, p7/m, z0.d, z0.d
SMIN Z0.D, P7/M, Z0.D, Z0.D
smin z3.d, p0/m, z3.d, z0.d
SMIN Z3.D, P0/M, Z3.D, Z0.D
smin z0.d, p0/m, z0.d, z4.d
SMIN Z0.D, P0/M, Z0.D, Z4.D
smin z0.d, p0/m, z0.d, z31.d
SMIN Z0.D, P0/M, Z0.D, Z31.D
sminv b0, p0, z0.b
SMINV B0, P0, Z0.B
sminv b1, p0, z0.b
SMINV B1, P0, Z0.B
sminv b31, p0, z0.b
SMINV B31, P0, Z0.B
sminv b0, p2, z0.b
SMINV B0, P2, Z0.B
sminv b0, p7, z0.b
SMINV B0, P7, Z0.B
sminv b0, p0, z3.b
SMINV B0, P0, Z3.B
sminv b0, p0, z31.b
SMINV B0, P0, Z31.B
sminv h0, p0, z0.h
SMINV H0, P0, Z0.H
sminv h1, p0, z0.h
SMINV H1, P0, Z0.H
sminv h31, p0, z0.h
SMINV H31, P0, Z0.H
sminv h0, p2, z0.h
SMINV H0, P2, Z0.H
sminv h0, p7, z0.h
SMINV H0, P7, Z0.H
sminv h0, p0, z3.h
SMINV H0, P0, Z3.H
sminv h0, p0, z31.h
SMINV H0, P0, Z31.H
sminv s0, p0, z0.s
SMINV S0, P0, Z0.S
sminv s1, p0, z0.s
SMINV S1, P0, Z0.S
sminv s31, p0, z0.s
SMINV S31, P0, Z0.S
sminv s0, p2, z0.s
SMINV S0, P2, Z0.S
sminv s0, p7, z0.s
SMINV S0, P7, Z0.S
sminv s0, p0, z3.s
SMINV S0, P0, Z3.S
sminv s0, p0, z31.s
SMINV S0, P0, Z31.S
sminv d0, p0, z0.d
SMINV D0, P0, Z0.D
sminv d1, p0, z0.d
SMINV D1, P0, Z0.D
sminv d31, p0, z0.d
SMINV D31, P0, Z0.D
sminv d0, p2, z0.d
SMINV D0, P2, Z0.D
sminv d0, p7, z0.d
SMINV D0, P7, Z0.D
sminv d0, p0, z3.d
SMINV D0, P0, Z3.D
sminv d0, p0, z31.d
SMINV D0, P0, Z31.D
smulh z0.b, p0/m, z0.b, z0.b
SMULH Z0.B, P0/M, Z0.B, Z0.B
smulh z1.b, p0/m, z1.b, z0.b
SMULH Z1.B, P0/M, Z1.B, Z0.B
smulh z31.b, p0/m, z31.b, z0.b
SMULH Z31.B, P0/M, Z31.B, Z0.B
smulh z0.b, p2/m, z0.b, z0.b
SMULH Z0.B, P2/M, Z0.B, Z0.B
smulh z0.b, p7/m, z0.b, z0.b
SMULH Z0.B, P7/M, Z0.B, Z0.B
smulh z3.b, p0/m, z3.b, z0.b
SMULH Z3.B, P0/M, Z3.B, Z0.B
smulh z0.b, p0/m, z0.b, z4.b
SMULH Z0.B, P0/M, Z0.B, Z4.B
smulh z0.b, p0/m, z0.b, z31.b
SMULH Z0.B, P0/M, Z0.B, Z31.B
smulh z0.h, p0/m, z0.h, z0.h
SMULH Z0.H, P0/M, Z0.H, Z0.H
smulh z1.h, p0/m, z1.h, z0.h
SMULH Z1.H, P0/M, Z1.H, Z0.H
smulh z31.h, p0/m, z31.h, z0.h
SMULH Z31.H, P0/M, Z31.H, Z0.H
smulh z0.h, p2/m, z0.h, z0.h
SMULH Z0.H, P2/M, Z0.H, Z0.H
smulh z0.h, p7/m, z0.h, z0.h
SMULH Z0.H, P7/M, Z0.H, Z0.H
smulh z3.h, p0/m, z3.h, z0.h
SMULH Z3.H, P0/M, Z3.H, Z0.H
smulh z0.h, p0/m, z0.h, z4.h
SMULH Z0.H, P0/M, Z0.H, Z4.H
smulh z0.h, p0/m, z0.h, z31.h
SMULH Z0.H, P0/M, Z0.H, Z31.H
smulh z0.s, p0/m, z0.s, z0.s
SMULH Z0.S, P0/M, Z0.S, Z0.S
smulh z1.s, p0/m, z1.s, z0.s
SMULH Z1.S, P0/M, Z1.S, Z0.S
smulh z31.s, p0/m, z31.s, z0.s
SMULH Z31.S, P0/M, Z31.S, Z0.S
smulh z0.s, p2/m, z0.s, z0.s
SMULH Z0.S, P2/M, Z0.S, Z0.S
smulh z0.s, p7/m, z0.s, z0.s
SMULH Z0.S, P7/M, Z0.S, Z0.S
smulh z3.s, p0/m, z3.s, z0.s
SMULH Z3.S, P0/M, Z3.S, Z0.S
smulh z0.s, p0/m, z0.s, z4.s
SMULH Z0.S, P0/M, Z0.S, Z4.S
smulh z0.s, p0/m, z0.s, z31.s
SMULH Z0.S, P0/M, Z0.S, Z31.S
smulh z0.d, p0/m, z0.d, z0.d
SMULH Z0.D, P0/M, Z0.D, Z0.D
smulh z1.d, p0/m, z1.d, z0.d
SMULH Z1.D, P0/M, Z1.D, Z0.D
smulh z31.d, p0/m, z31.d, z0.d
SMULH Z31.D, P0/M, Z31.D, Z0.D
smulh z0.d, p2/m, z0.d, z0.d
SMULH Z0.D, P2/M, Z0.D, Z0.D
smulh z0.d, p7/m, z0.d, z0.d
SMULH Z0.D, P7/M, Z0.D, Z0.D
smulh z3.d, p0/m, z3.d, z0.d
SMULH Z3.D, P0/M, Z3.D, Z0.D
smulh z0.d, p0/m, z0.d, z4.d
SMULH Z0.D, P0/M, Z0.D, Z4.D
smulh z0.d, p0/m, z0.d, z31.d
SMULH Z0.D, P0/M, Z0.D, Z31.D
splice z0.b, p0, z0.b, z0.b
SPLICE Z0.B, P0, Z0.B, Z0.B
splice z1.b, p0, z1.b, z0.b
SPLICE Z1.B, P0, Z1.B, Z0.B
splice z31.b, p0, z31.b, z0.b
SPLICE Z31.B, P0, Z31.B, Z0.B
splice z0.b, p2, z0.b, z0.b
SPLICE Z0.B, P2, Z0.B, Z0.B
splice z0.b, p7, z0.b, z0.b
SPLICE Z0.B, P7, Z0.B, Z0.B
splice z3.b, p0, z3.b, z0.b
SPLICE Z3.B, P0, Z3.B, Z0.B
splice z0.b, p0, z0.b, z4.b
SPLICE Z0.B, P0, Z0.B, Z4.B
splice z0.b, p0, z0.b, z31.b
SPLICE Z0.B, P0, Z0.B, Z31.B
splice z0.h, p0, z0.h, z0.h
SPLICE Z0.H, P0, Z0.H, Z0.H
splice z1.h, p0, z1.h, z0.h
SPLICE Z1.H, P0, Z1.H, Z0.H
splice z31.h, p0, z31.h, z0.h
SPLICE Z31.H, P0, Z31.H, Z0.H
splice z0.h, p2, z0.h, z0.h
SPLICE Z0.H, P2, Z0.H, Z0.H
splice z0.h, p7, z0.h, z0.h
SPLICE Z0.H, P7, Z0.H, Z0.H
splice z3.h, p0, z3.h, z0.h
SPLICE Z3.H, P0, Z3.H, Z0.H
splice z0.h, p0, z0.h, z4.h
SPLICE Z0.H, P0, Z0.H, Z4.H
splice z0.h, p0, z0.h, z31.h
SPLICE Z0.H, P0, Z0.H, Z31.H
splice z0.s, p0, z0.s, z0.s
SPLICE Z0.S, P0, Z0.S, Z0.S
splice z1.s, p0, z1.s, z0.s
SPLICE Z1.S, P0, Z1.S, Z0.S
splice z31.s, p0, z31.s, z0.s
SPLICE Z31.S, P0, Z31.S, Z0.S
splice z0.s, p2, z0.s, z0.s
SPLICE Z0.S, P2, Z0.S, Z0.S
splice z0.s, p7, z0.s, z0.s
SPLICE Z0.S, P7, Z0.S, Z0.S
splice z3.s, p0, z3.s, z0.s
SPLICE Z3.S, P0, Z3.S, Z0.S
splice z0.s, p0, z0.s, z4.s
SPLICE Z0.S, P0, Z0.S, Z4.S
splice z0.s, p0, z0.s, z31.s
SPLICE Z0.S, P0, Z0.S, Z31.S
splice z0.d, p0, z0.d, z0.d
SPLICE Z0.D, P0, Z0.D, Z0.D
splice z1.d, p0, z1.d, z0.d
SPLICE Z1.D, P0, Z1.D, Z0.D
splice z31.d, p0, z31.d, z0.d
SPLICE Z31.D, P0, Z31.D, Z0.D
splice z0.d, p2, z0.d, z0.d
SPLICE Z0.D, P2, Z0.D, Z0.D
splice z0.d, p7, z0.d, z0.d
SPLICE Z0.D, P7, Z0.D, Z0.D
splice z3.d, p0, z3.d, z0.d
SPLICE Z3.D, P0, Z3.D, Z0.D
splice z0.d, p0, z0.d, z4.d
SPLICE Z0.D, P0, Z0.D, Z4.D
splice z0.d, p0, z0.d, z31.d
SPLICE Z0.D, P0, Z0.D, Z31.D
sqadd z0.b, z0.b, z0.b
SQADD Z0.B, Z0.B, Z0.B
sqadd z1.b, z0.b, z0.b
SQADD Z1.B, Z0.B, Z0.B
sqadd z31.b, z0.b, z0.b
SQADD Z31.B, Z0.B, Z0.B
sqadd z0.b, z2.b, z0.b
SQADD Z0.B, Z2.B, Z0.B
sqadd z0.b, z31.b, z0.b
SQADD Z0.B, Z31.B, Z0.B
sqadd z0.b, z0.b, z3.b
SQADD Z0.B, Z0.B, Z3.B
sqadd z0.b, z0.b, z31.b
SQADD Z0.B, Z0.B, Z31.B
sqadd z0.h, z0.h, z0.h
SQADD Z0.H, Z0.H, Z0.H
sqadd z1.h, z0.h, z0.h
SQADD Z1.H, Z0.H, Z0.H
sqadd z31.h, z0.h, z0.h
SQADD Z31.H, Z0.H, Z0.H
sqadd z0.h, z2.h, z0.h
SQADD Z0.H, Z2.H, Z0.H
sqadd z0.h, z31.h, z0.h
SQADD Z0.H, Z31.H, Z0.H
sqadd z0.h, z0.h, z3.h
SQADD Z0.H, Z0.H, Z3.H
sqadd z0.h, z0.h, z31.h
SQADD Z0.H, Z0.H, Z31.H
sqadd z0.s, z0.s, z0.s
SQADD Z0.S, Z0.S, Z0.S
sqadd z1.s, z0.s, z0.s
SQADD Z1.S, Z0.S, Z0.S
sqadd z31.s, z0.s, z0.s
SQADD Z31.S, Z0.S, Z0.S
sqadd z0.s, z2.s, z0.s
SQADD Z0.S, Z2.S, Z0.S
sqadd z0.s, z31.s, z0.s
SQADD Z0.S, Z31.S, Z0.S
sqadd z0.s, z0.s, z3.s
SQADD Z0.S, Z0.S, Z3.S
sqadd z0.s, z0.s, z31.s
SQADD Z0.S, Z0.S, Z31.S
sqadd z0.d, z0.d, z0.d
SQADD Z0.D, Z0.D, Z0.D
sqadd z1.d, z0.d, z0.d
SQADD Z1.D, Z0.D, Z0.D
sqadd z31.d, z0.d, z0.d
SQADD Z31.D, Z0.D, Z0.D
sqadd z0.d, z2.d, z0.d
SQADD Z0.D, Z2.D, Z0.D
sqadd z0.d, z31.d, z0.d
SQADD Z0.D, Z31.D, Z0.D
sqadd z0.d, z0.d, z3.d
SQADD Z0.D, Z0.D, Z3.D
sqadd z0.d, z0.d, z31.d
SQADD Z0.D, Z0.D, Z31.D
sqadd z0.b, z0.b, #0
SQADD Z0.B, Z0.B, #0
sqadd z0.b, z0.b, #0, lsl #0
sqadd z1.b, z1.b, #0
SQADD Z1.B, Z1.B, #0
sqadd z1.b, z1.b, #0, lsl #0
sqadd z31.b, z31.b, #0
SQADD Z31.B, Z31.B, #0
sqadd z31.b, z31.b, #0, lsl #0
sqadd z2.b, z2.b, #0
SQADD Z2.B, Z2.B, #0
sqadd z2.b, z2.b, #0, lsl #0
sqadd z0.b, z0.b, #127
SQADD Z0.B, Z0.B, #127
sqadd z0.b, z0.b, #127, lsl #0
sqadd z0.b, z0.b, #128
SQADD Z0.B, Z0.B, #128
sqadd z0.b, z0.b, #128, lsl #0
sqadd z0.b, z0.b, #129
SQADD Z0.B, Z0.B, #129
sqadd z0.b, z0.b, #129, lsl #0
sqadd z0.b, z0.b, #255
SQADD Z0.B, Z0.B, #255
sqadd z0.b, z0.b, #255, lsl #0
sqadd z0.h, z0.h, #0
SQADD Z0.H, Z0.H, #0
sqadd z0.h, z0.h, #0, lsl #0
sqadd z1.h, z1.h, #0
SQADD Z1.H, Z1.H, #0
sqadd z1.h, z1.h, #0, lsl #0
sqadd z31.h, z31.h, #0
SQADD Z31.H, Z31.H, #0
sqadd z31.h, z31.h, #0, lsl #0
sqadd z2.h, z2.h, #0
SQADD Z2.H, Z2.H, #0
sqadd z2.h, z2.h, #0, lsl #0
sqadd z0.h, z0.h, #127
SQADD Z0.H, Z0.H, #127
sqadd z0.h, z0.h, #127, lsl #0
sqadd z0.h, z0.h, #128
SQADD Z0.H, Z0.H, #128
sqadd z0.h, z0.h, #128, lsl #0
sqadd z0.h, z0.h, #129
SQADD Z0.H, Z0.H, #129
sqadd z0.h, z0.h, #129, lsl #0
sqadd z0.h, z0.h, #255
SQADD Z0.H, Z0.H, #255
sqadd z0.h, z0.h, #255, lsl #0
sqadd z0.h, z0.h, #0, lsl #8
SQADD Z0.H, Z0.H, #0, LSL #8
sqadd z0.h, z0.h, #32512
SQADD Z0.H, Z0.H, #32512
sqadd z0.h, z0.h, #32512, lsl #0
sqadd z0.h, z0.h, #127, lsl #8
sqadd z0.h, z0.h, #32768
SQADD Z0.H, Z0.H, #32768
sqadd z0.h, z0.h, #32768, lsl #0
sqadd z0.h, z0.h, #128, lsl #8
sqadd z0.h, z0.h, #33024
SQADD Z0.H, Z0.H, #33024
sqadd z0.h, z0.h, #33024, lsl #0
sqadd z0.h, z0.h, #129, lsl #8
sqadd z0.h, z0.h, #65280
SQADD Z0.H, Z0.H, #65280
sqadd z0.h, z0.h, #65280, lsl #0
sqadd z0.h, z0.h, #255, lsl #8
sqadd z0.s, z0.s, #0
SQADD Z0.S, Z0.S, #0
sqadd z0.s, z0.s, #0, lsl #0
sqadd z1.s, z1.s, #0
SQADD Z1.S, Z1.S, #0
sqadd z1.s, z1.s, #0, lsl #0
sqadd z31.s, z31.s, #0
SQADD Z31.S, Z31.S, #0
sqadd z31.s, z31.s, #0, lsl #0
sqadd z2.s, z2.s, #0
SQADD Z2.S, Z2.S, #0
sqadd z2.s, z2.s, #0, lsl #0
sqadd z0.s, z0.s, #127
SQADD Z0.S, Z0.S, #127
sqadd z0.s, z0.s, #127, lsl #0
sqadd z0.s, z0.s, #128
SQADD Z0.S, Z0.S, #128
sqadd z0.s, z0.s, #128, lsl #0
sqadd z0.s, z0.s, #129
SQADD Z0.S, Z0.S, #129
sqadd z0.s, z0.s, #129, lsl #0
sqadd z0.s, z0.s, #255
SQADD Z0.S, Z0.S, #255
sqadd z0.s, z0.s, #255, lsl #0
sqadd z0.s, z0.s, #0, lsl #8
SQADD Z0.S, Z0.S, #0, LSL #8
sqadd z0.s, z0.s, #32512
SQADD Z0.S, Z0.S, #32512
sqadd z0.s, z0.s, #32512, lsl #0
sqadd z0.s, z0.s, #127, lsl #8
sqadd z0.s, z0.s, #32768
SQADD Z0.S, Z0.S, #32768
sqadd z0.s, z0.s, #32768, lsl #0
sqadd z0.s, z0.s, #128, lsl #8
sqadd z0.s, z0.s, #33024
SQADD Z0.S, Z0.S, #33024
sqadd z0.s, z0.s, #33024, lsl #0
sqadd z0.s, z0.s, #129, lsl #8
sqadd z0.s, z0.s, #65280
SQADD Z0.S, Z0.S, #65280
sqadd z0.s, z0.s, #65280, lsl #0
sqadd z0.s, z0.s, #255, lsl #8
sqadd z0.d, z0.d, #0
SQADD Z0.D, Z0.D, #0
sqadd z0.d, z0.d, #0, lsl #0
sqadd z1.d, z1.d, #0
SQADD Z1.D, Z1.D, #0
sqadd z1.d, z1.d, #0, lsl #0
sqadd z31.d, z31.d, #0
SQADD Z31.D, Z31.D, #0
sqadd z31.d, z31.d, #0, lsl #0
sqadd z2.d, z2.d, #0
SQADD Z2.D, Z2.D, #0
sqadd z2.d, z2.d, #0, lsl #0
sqadd z0.d, z0.d, #127
SQADD Z0.D, Z0.D, #127
sqadd z0.d, z0.d, #127, lsl #0
sqadd z0.d, z0.d, #128
SQADD Z0.D, Z0.D, #128
sqadd z0.d, z0.d, #128, lsl #0
sqadd z0.d, z0.d, #129
SQADD Z0.D, Z0.D, #129
sqadd z0.d, z0.d, #129, lsl #0
sqadd z0.d, z0.d, #255
SQADD Z0.D, Z0.D, #255
sqadd z0.d, z0.d, #255, lsl #0
sqadd z0.d, z0.d, #0, lsl #8
SQADD Z0.D, Z0.D, #0, LSL #8
sqadd z0.d, z0.d, #32512
SQADD Z0.D, Z0.D, #32512
sqadd z0.d, z0.d, #32512, lsl #0
sqadd z0.d, z0.d, #127, lsl #8
sqadd z0.d, z0.d, #32768
SQADD Z0.D, Z0.D, #32768
sqadd z0.d, z0.d, #32768, lsl #0
sqadd z0.d, z0.d, #128, lsl #8
sqadd z0.d, z0.d, #33024
SQADD Z0.D, Z0.D, #33024
sqadd z0.d, z0.d, #33024, lsl #0
sqadd z0.d, z0.d, #129, lsl #8
sqadd z0.d, z0.d, #65280
SQADD Z0.D, Z0.D, #65280
sqadd z0.d, z0.d, #65280, lsl #0
sqadd z0.d, z0.d, #255, lsl #8
sqdecb x0, pow2
SQDECB X0, POW2
sqdecb x0, pow2, mul #1
sqdecb x1, pow2
SQDECB X1, POW2
sqdecb x1, pow2, mul #1
sqdecb xzr, pow2
SQDECB XZR, POW2
sqdecb xzr, pow2, mul #1
sqdecb x0, vl1
SQDECB X0, VL1
sqdecb x0, vl1, mul #1
sqdecb x0, vl2
SQDECB X0, VL2
sqdecb x0, vl2, mul #1
sqdecb x0, vl3
SQDECB X0, VL3
sqdecb x0, vl3, mul #1
sqdecb x0, vl4
SQDECB X0, VL4
sqdecb x0, vl4, mul #1
sqdecb x0, vl5
SQDECB X0, VL5
sqdecb x0, vl5, mul #1
sqdecb x0, vl6
SQDECB X0, VL6
sqdecb x0, vl6, mul #1
sqdecb x0, vl7
SQDECB X0, VL7
sqdecb x0, vl7, mul #1
sqdecb x0, vl8
SQDECB X0, VL8
sqdecb x0, vl8, mul #1
sqdecb x0, vl16
SQDECB X0, VL16
sqdecb x0, vl16, mul #1
sqdecb x0, vl32
SQDECB X0, VL32
sqdecb x0, vl32, mul #1
sqdecb x0, vl64
SQDECB X0, VL64
sqdecb x0, vl64, mul #1
sqdecb x0, vl128
SQDECB X0, VL128
sqdecb x0, vl128, mul #1
sqdecb x0, vl256
SQDECB X0, VL256
sqdecb x0, vl256, mul #1
sqdecb x0, #14
SQDECB X0, #14
sqdecb x0, #14, mul #1
sqdecb x0, #15
SQDECB X0, #15
sqdecb x0, #15, mul #1
sqdecb x0, #16
SQDECB X0, #16
sqdecb x0, #16, mul #1
sqdecb x0, #17
SQDECB X0, #17
sqdecb x0, #17, mul #1
sqdecb x0, #18
SQDECB X0, #18
sqdecb x0, #18, mul #1
sqdecb x0, #19
SQDECB X0, #19
sqdecb x0, #19, mul #1
sqdecb x0, #20
SQDECB X0, #20
sqdecb x0, #20, mul #1
sqdecb x0, #21
SQDECB X0, #21
sqdecb x0, #21, mul #1
sqdecb x0, #22
SQDECB X0, #22
sqdecb x0, #22, mul #1
sqdecb x0, #23
SQDECB X0, #23
sqdecb x0, #23, mul #1
sqdecb x0, #24
SQDECB X0, #24
sqdecb x0, #24, mul #1
sqdecb x0, #25
SQDECB X0, #25
sqdecb x0, #25, mul #1
sqdecb x0, #26
SQDECB X0, #26
sqdecb x0, #26, mul #1
sqdecb x0, #27
SQDECB X0, #27
sqdecb x0, #27, mul #1
sqdecb x0, #28
SQDECB X0, #28
sqdecb x0, #28, mul #1
sqdecb x0, mul4
SQDECB X0, MUL4
sqdecb x0, mul4, mul #1
sqdecb x0, mul3
SQDECB X0, MUL3
sqdecb x0, mul3, mul #1
sqdecb x0
SQDECB X0
sqdecb x0, all
sqdecb x0, all, mul #1
sqdecb x0, pow2, mul #8
SQDECB X0, POW2, MUL #8
sqdecb x0, pow2, mul #9
SQDECB X0, POW2, MUL #9
sqdecb x0, pow2, mul #10
SQDECB X0, POW2, MUL #10
sqdecb x0, pow2, mul #16
SQDECB X0, POW2, MUL #16
sqdecb x0, w0, pow2
SQDECB X0, W0, POW2
sqdecb x0, w0, pow2, mul #1
sqdecb x1, w1, pow2
SQDECB X1, W1, POW2
sqdecb x1, w1, pow2, mul #1
sqdecb xzr, wzr, pow2
SQDECB XZR, WZR, POW2
sqdecb xzr, wzr, pow2, mul #1
sqdecb x2, w2, pow2
SQDECB X2, W2, POW2
sqdecb x2, w2, pow2, mul #1
sqdecb x0, w0, vl1
SQDECB X0, W0, VL1
sqdecb x0, w0, vl1, mul #1
sqdecb x0, w0, vl2
SQDECB X0, W0, VL2
sqdecb x0, w0, vl2, mul #1
sqdecb x0, w0, vl3
SQDECB X0, W0, VL3
sqdecb x0, w0, vl3, mul #1
sqdecb x0, w0, vl4
SQDECB X0, W0, VL4
sqdecb x0, w0, vl4, mul #1
sqdecb x0, w0, vl5
SQDECB X0, W0, VL5
sqdecb x0, w0, vl5, mul #1
sqdecb x0, w0, vl6
SQDECB X0, W0, VL6
sqdecb x0, w0, vl6, mul #1
sqdecb x0, w0, vl7
SQDECB X0, W0, VL7
sqdecb x0, w0, vl7, mul #1
sqdecb x0, w0, vl8
SQDECB X0, W0, VL8
sqdecb x0, w0, vl8, mul #1
sqdecb x0, w0, vl16
SQDECB X0, W0, VL16
sqdecb x0, w0, vl16, mul #1
sqdecb x0, w0, vl32
SQDECB X0, W0, VL32
sqdecb x0, w0, vl32, mul #1
sqdecb x0, w0, vl64
SQDECB X0, W0, VL64
sqdecb x0, w0, vl64, mul #1
sqdecb x0, w0, vl128
SQDECB X0, W0, VL128
sqdecb x0, w0, vl128, mul #1
sqdecb x0, w0, vl256
SQDECB X0, W0, VL256
sqdecb x0, w0, vl256, mul #1
sqdecb x0, w0, #14
SQDECB X0, W0, #14
sqdecb x0, w0, #14, mul #1
sqdecb x0, w0, #15
SQDECB X0, W0, #15
sqdecb x0, w0, #15, mul #1
sqdecb x0, w0, #16
SQDECB X0, W0, #16
sqdecb x0, w0, #16, mul #1
sqdecb x0, w0, #17
SQDECB X0, W0, #17
sqdecb x0, w0, #17, mul #1
sqdecb x0, w0, #18
SQDECB X0, W0, #18
sqdecb x0, w0, #18, mul #1
sqdecb x0, w0, #19
SQDECB X0, W0, #19
sqdecb x0, w0, #19, mul #1
sqdecb x0, w0, #20
SQDECB X0, W0, #20
sqdecb x0, w0, #20, mul #1
sqdecb x0, w0, #21
SQDECB X0, W0, #21
sqdecb x0, w0, #21, mul #1
sqdecb x0, w0, #22
SQDECB X0, W0, #22
sqdecb x0, w0, #22, mul #1
sqdecb x0, w0, #23
SQDECB X0, W0, #23
sqdecb x0, w0, #23, mul #1
sqdecb x0, w0, #24
SQDECB X0, W0, #24
sqdecb x0, w0, #24, mul #1
sqdecb x0, w0, #25
SQDECB X0, W0, #25
sqdecb x0, w0, #25, mul #1
sqdecb x0, w0, #26
SQDECB X0, W0, #26
sqdecb x0, w0, #26, mul #1
sqdecb x0, w0, #27
SQDECB X0, W0, #27
sqdecb x0, w0, #27, mul #1
sqdecb x0, w0, #28
SQDECB X0, W0, #28
sqdecb x0, w0, #28, mul #1
sqdecb x0, w0, mul4
SQDECB X0, W0, MUL4
sqdecb x0, w0, mul4, mul #1
sqdecb x0, w0, mul3
SQDECB X0, W0, MUL3
sqdecb x0, w0, mul3, mul #1
sqdecb x0, w0
SQDECB X0, W0
sqdecb x0, w0, all
sqdecb x0, w0, all, mul #1
sqdecb x0, w0, pow2, mul #8
SQDECB X0, W0, POW2, MUL #8
sqdecb x0, w0, pow2, mul #9
SQDECB X0, W0, POW2, MUL #9
sqdecb x0, w0, pow2, mul #10
SQDECB X0, W0, POW2, MUL #10
sqdecb x0, w0, pow2, mul #16
SQDECB X0, W0, POW2, MUL #16
sqdecd z0.d, pow2
SQDECD Z0.D, POW2
sqdecd z0.d, pow2, mul #1
sqdecd z1.d, pow2
SQDECD Z1.D, POW2
sqdecd z1.d, pow2, mul #1
sqdecd z31.d, pow2
SQDECD Z31.D, POW2
sqdecd z31.d, pow2, mul #1
sqdecd z0.d, vl1
SQDECD Z0.D, VL1
sqdecd z0.d, vl1, mul #1
sqdecd z0.d, vl2
SQDECD Z0.D, VL2
sqdecd z0.d, vl2, mul #1
sqdecd z0.d, vl3
SQDECD Z0.D, VL3
sqdecd z0.d, vl3, mul #1
sqdecd z0.d, vl4
SQDECD Z0.D, VL4
sqdecd z0.d, vl4, mul #1
sqdecd z0.d, vl5
SQDECD Z0.D, VL5
sqdecd z0.d, vl5, mul #1
sqdecd z0.d, vl6
SQDECD Z0.D, VL6
sqdecd z0.d, vl6, mul #1
sqdecd z0.d, vl7
SQDECD Z0.D, VL7
sqdecd z0.d, vl7, mul #1
sqdecd z0.d, vl8
SQDECD Z0.D, VL8
sqdecd z0.d, vl8, mul #1
sqdecd z0.d, vl16
SQDECD Z0.D, VL16
sqdecd z0.d, vl16, mul #1
sqdecd z0.d, vl32
SQDECD Z0.D, VL32
sqdecd z0.d, vl32, mul #1
sqdecd z0.d, vl64
SQDECD Z0.D, VL64
sqdecd z0.d, vl64, mul #1
sqdecd z0.d, vl128
SQDECD Z0.D, VL128
sqdecd z0.d, vl128, mul #1
sqdecd z0.d, vl256
SQDECD Z0.D, VL256
sqdecd z0.d, vl256, mul #1
sqdecd z0.d, #14
SQDECD Z0.D, #14
sqdecd z0.d, #14, mul #1
sqdecd z0.d, #15
SQDECD Z0.D, #15
sqdecd z0.d, #15, mul #1
sqdecd z0.d, #16
SQDECD Z0.D, #16
sqdecd z0.d, #16, mul #1
sqdecd z0.d, #17
SQDECD Z0.D, #17
sqdecd z0.d, #17, mul #1
sqdecd z0.d, #18
SQDECD Z0.D, #18
sqdecd z0.d, #18, mul #1
sqdecd z0.d, #19
SQDECD Z0.D, #19
sqdecd z0.d, #19, mul #1
sqdecd z0.d, #20
SQDECD Z0.D, #20
sqdecd z0.d, #20, mul #1
sqdecd z0.d, #21
SQDECD Z0.D, #21
sqdecd z0.d, #21, mul #1
sqdecd z0.d, #22
SQDECD Z0.D, #22
sqdecd z0.d, #22, mul #1
sqdecd z0.d, #23
SQDECD Z0.D, #23
sqdecd z0.d, #23, mul #1
sqdecd z0.d, #24
SQDECD Z0.D, #24
sqdecd z0.d, #24, mul #1
sqdecd z0.d, #25
SQDECD Z0.D, #25
sqdecd z0.d, #25, mul #1
sqdecd z0.d, #26
SQDECD Z0.D, #26
sqdecd z0.d, #26, mul #1
sqdecd z0.d, #27
SQDECD Z0.D, #27
sqdecd z0.d, #27, mul #1
sqdecd z0.d, #28
SQDECD Z0.D, #28
sqdecd z0.d, #28, mul #1
sqdecd z0.d, mul4
SQDECD Z0.D, MUL4
sqdecd z0.d, mul4, mul #1
sqdecd z0.d, mul3
SQDECD Z0.D, MUL3
sqdecd z0.d, mul3, mul #1
sqdecd z0.d
SQDECD Z0.D
sqdecd z0.d, all
sqdecd z0.d, all, mul #1
sqdecd z0.d, pow2, mul #8
SQDECD Z0.D, POW2, MUL #8
sqdecd z0.d, pow2, mul #9
SQDECD Z0.D, POW2, MUL #9
sqdecd z0.d, pow2, mul #10
SQDECD Z0.D, POW2, MUL #10
sqdecd z0.d, pow2, mul #16
SQDECD Z0.D, POW2, MUL #16
sqdecd x0, pow2
SQDECD X0, POW2
sqdecd x0, pow2, mul #1
sqdecd x1, pow2
SQDECD X1, POW2
sqdecd x1, pow2, mul #1
sqdecd xzr, pow2
SQDECD XZR, POW2
sqdecd xzr, pow2, mul #1
sqdecd x0, vl1
SQDECD X0, VL1
sqdecd x0, vl1, mul #1
sqdecd x0, vl2
SQDECD X0, VL2
sqdecd x0, vl2, mul #1
sqdecd x0, vl3
SQDECD X0, VL3
sqdecd x0, vl3, mul #1
sqdecd x0, vl4
SQDECD X0, VL4
sqdecd x0, vl4, mul #1
sqdecd x0, vl5
SQDECD X0, VL5
sqdecd x0, vl5, mul #1
sqdecd x0, vl6
SQDECD X0, VL6
sqdecd x0, vl6, mul #1
sqdecd x0, vl7
SQDECD X0, VL7
sqdecd x0, vl7, mul #1
sqdecd x0, vl8
SQDECD X0, VL8
sqdecd x0, vl8, mul #1
sqdecd x0, vl16
SQDECD X0, VL16
sqdecd x0, vl16, mul #1
sqdecd x0, vl32
SQDECD X0, VL32
sqdecd x0, vl32, mul #1
sqdecd x0, vl64
SQDECD X0, VL64
sqdecd x0, vl64, mul #1
sqdecd x0, vl128
SQDECD X0, VL128
sqdecd x0, vl128, mul #1
sqdecd x0, vl256
SQDECD X0, VL256
sqdecd x0, vl256, mul #1
sqdecd x0, #14
SQDECD X0, #14
sqdecd x0, #14, mul #1
sqdecd x0, #15
SQDECD X0, #15
sqdecd x0, #15, mul #1
sqdecd x0, #16
SQDECD X0, #16
sqdecd x0, #16, mul #1
sqdecd x0, #17
SQDECD X0, #17
sqdecd x0, #17, mul #1
sqdecd x0, #18
SQDECD X0, #18
sqdecd x0, #18, mul #1
sqdecd x0, #19
SQDECD X0, #19
sqdecd x0, #19, mul #1
sqdecd x0, #20
SQDECD X0, #20
sqdecd x0, #20, mul #1
sqdecd x0, #21
SQDECD X0, #21
sqdecd x0, #21, mul #1
sqdecd x0, #22
SQDECD X0, #22
sqdecd x0, #22, mul #1
sqdecd x0, #23
SQDECD X0, #23
sqdecd x0, #23, mul #1
sqdecd x0, #24
SQDECD X0, #24
sqdecd x0, #24, mul #1
sqdecd x0, #25
SQDECD X0, #25
sqdecd x0, #25, mul #1
sqdecd x0, #26
SQDECD X0, #26
sqdecd x0, #26, mul #1
sqdecd x0, #27
SQDECD X0, #27
sqdecd x0, #27, mul #1
sqdecd x0, #28
SQDECD X0, #28
sqdecd x0, #28, mul #1
sqdecd x0, mul4
SQDECD X0, MUL4
sqdecd x0, mul4, mul #1
sqdecd x0, mul3
SQDECD X0, MUL3
sqdecd x0, mul3, mul #1
sqdecd x0
SQDECD X0
sqdecd x0, all
sqdecd x0, all, mul #1
sqdecd x0, pow2, mul #8
SQDECD X0, POW2, MUL #8
sqdecd x0, pow2, mul #9
SQDECD X0, POW2, MUL #9
sqdecd x0, pow2, mul #10
SQDECD X0, POW2, MUL #10
sqdecd x0, pow2, mul #16
SQDECD X0, POW2, MUL #16
sqdecd x0, w0, pow2
SQDECD X0, W0, POW2
sqdecd x0, w0, pow2, mul #1
sqdecd x1, w1, pow2
SQDECD X1, W1, POW2
sqdecd x1, w1, pow2, mul #1
sqdecd xzr, wzr, pow2
SQDECD XZR, WZR, POW2
sqdecd xzr, wzr, pow2, mul #1
sqdecd x2, w2, pow2
SQDECD X2, W2, POW2
sqdecd x2, w2, pow2, mul #1
sqdecd x0, w0, vl1
SQDECD X0, W0, VL1
sqdecd x0, w0, vl1, mul #1
sqdecd x0, w0, vl2
SQDECD X0, W0, VL2
sqdecd x0, w0, vl2, mul #1
sqdecd x0, w0, vl3
SQDECD X0, W0, VL3
sqdecd x0, w0, vl3, mul #1
sqdecd x0, w0, vl4
SQDECD X0, W0, VL4
sqdecd x0, w0, vl4, mul #1
sqdecd x0, w0, vl5
SQDECD X0, W0, VL5
sqdecd x0, w0, vl5, mul #1
sqdecd x0, w0, vl6
SQDECD X0, W0, VL6
sqdecd x0, w0, vl6, mul #1
sqdecd x0, w0, vl7
SQDECD X0, W0, VL7
sqdecd x0, w0, vl7, mul #1
sqdecd x0, w0, vl8
SQDECD X0, W0, VL8
sqdecd x0, w0, vl8, mul #1
sqdecd x0, w0, vl16
SQDECD X0, W0, VL16
sqdecd x0, w0, vl16, mul #1
sqdecd x0, w0, vl32
SQDECD X0, W0, VL32
sqdecd x0, w0, vl32, mul #1
sqdecd x0, w0, vl64
SQDECD X0, W0, VL64
sqdecd x0, w0, vl64, mul #1
sqdecd x0, w0, vl128
SQDECD X0, W0, VL128
sqdecd x0, w0, vl128, mul #1
sqdecd x0, w0, vl256
SQDECD X0, W0, VL256
sqdecd x0, w0, vl256, mul #1
sqdecd x0, w0, #14
SQDECD X0, W0, #14
sqdecd x0, w0, #14, mul #1
sqdecd x0, w0, #15
SQDECD X0, W0, #15
sqdecd x0, w0, #15, mul #1
sqdecd x0, w0, #16
SQDECD X0, W0, #16
sqdecd x0, w0, #16, mul #1
sqdecd x0, w0, #17
SQDECD X0, W0, #17
sqdecd x0, w0, #17, mul #1
sqdecd x0, w0, #18
SQDECD X0, W0, #18
sqdecd x0, w0, #18, mul #1
sqdecd x0, w0, #19
SQDECD X0, W0, #19
sqdecd x0, w0, #19, mul #1
sqdecd x0, w0, #20
SQDECD X0, W0, #20
sqdecd x0, w0, #20, mul #1
sqdecd x0, w0, #21
SQDECD X0, W0, #21
sqdecd x0, w0, #21, mul #1
sqdecd x0, w0, #22
SQDECD X0, W0, #22
sqdecd x0, w0, #22, mul #1
sqdecd x0, w0, #23
SQDECD X0, W0, #23
sqdecd x0, w0, #23, mul #1
sqdecd x0, w0, #24
SQDECD X0, W0, #24
sqdecd x0, w0, #24, mul #1
sqdecd x0, w0, #25
SQDECD X0, W0, #25
sqdecd x0, w0, #25, mul #1
sqdecd x0, w0, #26
SQDECD X0, W0, #26
sqdecd x0, w0, #26, mul #1
sqdecd x0, w0, #27
SQDECD X0, W0, #27
sqdecd x0, w0, #27, mul #1
sqdecd x0, w0, #28
SQDECD X0, W0, #28
sqdecd x0, w0, #28, mul #1
sqdecd x0, w0, mul4
SQDECD X0, W0, MUL4
sqdecd x0, w0, mul4, mul #1
sqdecd x0, w0, mul3
SQDECD X0, W0, MUL3
sqdecd x0, w0, mul3, mul #1
sqdecd x0, w0
SQDECD X0, W0
sqdecd x0, w0, all
sqdecd x0, w0, all, mul #1
sqdecd x0, w0, pow2, mul #8
SQDECD X0, W0, POW2, MUL #8
sqdecd x0, w0, pow2, mul #9
SQDECD X0, W0, POW2, MUL #9
sqdecd x0, w0, pow2, mul #10
SQDECD X0, W0, POW2, MUL #10
sqdecd x0, w0, pow2, mul #16
SQDECD X0, W0, POW2, MUL #16
sqdech z0.h, pow2
SQDECH Z0.H, POW2
sqdech z0.h, pow2, mul #1
sqdech z1.h, pow2
SQDECH Z1.H, POW2
sqdech z1.h, pow2, mul #1
sqdech z31.h, pow2
SQDECH Z31.H, POW2
sqdech z31.h, pow2, mul #1
sqdech z0.h, vl1
SQDECH Z0.H, VL1
sqdech z0.h, vl1, mul #1
sqdech z0.h, vl2
SQDECH Z0.H, VL2
sqdech z0.h, vl2, mul #1
sqdech z0.h, vl3
SQDECH Z0.H, VL3
sqdech z0.h, vl3, mul #1
sqdech z0.h, vl4
SQDECH Z0.H, VL4
sqdech z0.h, vl4, mul #1
sqdech z0.h, vl5
SQDECH Z0.H, VL5
sqdech z0.h, vl5, mul #1
sqdech z0.h, vl6
SQDECH Z0.H, VL6
sqdech z0.h, vl6, mul #1
sqdech z0.h, vl7
SQDECH Z0.H, VL7
sqdech z0.h, vl7, mul #1
sqdech z0.h, vl8
SQDECH Z0.H, VL8
sqdech z0.h, vl8, mul #1
sqdech z0.h, vl16
SQDECH Z0.H, VL16
sqdech z0.h, vl16, mul #1
sqdech z0.h, vl32
SQDECH Z0.H, VL32
sqdech z0.h, vl32, mul #1
sqdech z0.h, vl64
SQDECH Z0.H, VL64
sqdech z0.h, vl64, mul #1
sqdech z0.h, vl128
SQDECH Z0.H, VL128
sqdech z0.h, vl128, mul #1
sqdech z0.h, vl256
SQDECH Z0.H, VL256
sqdech z0.h, vl256, mul #1
sqdech z0.h, #14
SQDECH Z0.H, #14
sqdech z0.h, #14, mul #1
sqdech z0.h, #15
SQDECH Z0.H, #15
sqdech z0.h, #15, mul #1
sqdech z0.h, #16
SQDECH Z0.H, #16
sqdech z0.h, #16, mul #1
sqdech z0.h, #17
SQDECH Z0.H, #17
sqdech z0.h, #17, mul #1
sqdech z0.h, #18
SQDECH Z0.H, #18
sqdech z0.h, #18, mul #1
sqdech z0.h, #19
SQDECH Z0.H, #19
sqdech z0.h, #19, mul #1
sqdech z0.h, #20
SQDECH Z0.H, #20
sqdech z0.h, #20, mul #1
sqdech z0.h, #21
SQDECH Z0.H, #21
sqdech z0.h, #21, mul #1
sqdech z0.h, #22
SQDECH Z0.H, #22
sqdech z0.h, #22, mul #1
sqdech z0.h, #23
SQDECH Z0.H, #23
sqdech z0.h, #23, mul #1
sqdech z0.h, #24
SQDECH Z0.H, #24
sqdech z0.h, #24, mul #1
sqdech z0.h, #25
SQDECH Z0.H, #25
sqdech z0.h, #25, mul #1
sqdech z0.h, #26
SQDECH Z0.H, #26
sqdech z0.h, #26, mul #1
sqdech z0.h, #27
SQDECH Z0.H, #27
sqdech z0.h, #27, mul #1
sqdech z0.h, #28
SQDECH Z0.H, #28
sqdech z0.h, #28, mul #1
sqdech z0.h, mul4
SQDECH Z0.H, MUL4
sqdech z0.h, mul4, mul #1
sqdech z0.h, mul3
SQDECH Z0.H, MUL3
sqdech z0.h, mul3, mul #1
sqdech z0.h
SQDECH Z0.H
sqdech z0.h, all
sqdech z0.h, all, mul #1
sqdech z0.h, pow2, mul #8
SQDECH Z0.H, POW2, MUL #8
sqdech z0.h, pow2, mul #9
SQDECH Z0.H, POW2, MUL #9
sqdech z0.h, pow2, mul #10
SQDECH Z0.H, POW2, MUL #10
sqdech z0.h, pow2, mul #16
SQDECH Z0.H, POW2, MUL #16
sqdech x0, pow2
SQDECH X0, POW2
sqdech x0, pow2, mul #1
sqdech x1, pow2
SQDECH X1, POW2
sqdech x1, pow2, mul #1
sqdech xzr, pow2
SQDECH XZR, POW2
sqdech xzr, pow2, mul #1
sqdech x0, vl1
SQDECH X0, VL1
sqdech x0, vl1, mul #1
sqdech x0, vl2
SQDECH X0, VL2
sqdech x0, vl2, mul #1
sqdech x0, vl3
SQDECH X0, VL3
sqdech x0, vl3, mul #1
sqdech x0, vl4
SQDECH X0, VL4
sqdech x0, vl4, mul #1
sqdech x0, vl5
SQDECH X0, VL5
sqdech x0, vl5, mul #1
sqdech x0, vl6
SQDECH X0, VL6
sqdech x0, vl6, mul #1
sqdech x0, vl7
SQDECH X0, VL7
sqdech x0, vl7, mul #1
sqdech x0, vl8
SQDECH X0, VL8
sqdech x0, vl8, mul #1
sqdech x0, vl16
SQDECH X0, VL16
sqdech x0, vl16, mul #1
sqdech x0, vl32
SQDECH X0, VL32
sqdech x0, vl32, mul #1
sqdech x0, vl64
SQDECH X0, VL64
sqdech x0, vl64, mul #1
sqdech x0, vl128
SQDECH X0, VL128
sqdech x0, vl128, mul #1
sqdech x0, vl256
SQDECH X0, VL256
sqdech x0, vl256, mul #1
sqdech x0, #14
SQDECH X0, #14
sqdech x0, #14, mul #1
sqdech x0, #15
SQDECH X0, #15
sqdech x0, #15, mul #1
sqdech x0, #16
SQDECH X0, #16
sqdech x0, #16, mul #1
sqdech x0, #17
SQDECH X0, #17
sqdech x0, #17, mul #1
sqdech x0, #18
SQDECH X0, #18
sqdech x0, #18, mul #1
sqdech x0, #19
SQDECH X0, #19
sqdech x0, #19, mul #1
sqdech x0, #20
SQDECH X0, #20
sqdech x0, #20, mul #1
sqdech x0, #21
SQDECH X0, #21
sqdech x0, #21, mul #1
sqdech x0, #22
SQDECH X0, #22
sqdech x0, #22, mul #1
sqdech x0, #23
SQDECH X0, #23
sqdech x0, #23, mul #1
sqdech x0, #24
SQDECH X0, #24
sqdech x0, #24, mul #1
sqdech x0, #25
SQDECH X0, #25
sqdech x0, #25, mul #1
sqdech x0, #26
SQDECH X0, #26
sqdech x0, #26, mul #1
sqdech x0, #27
SQDECH X0, #27
sqdech x0, #27, mul #1
sqdech x0, #28
SQDECH X0, #28
sqdech x0, #28, mul #1
sqdech x0, mul4
SQDECH X0, MUL4
sqdech x0, mul4, mul #1
sqdech x0, mul3
SQDECH X0, MUL3
sqdech x0, mul3, mul #1
sqdech x0
SQDECH X0
sqdech x0, all
sqdech x0, all, mul #1
sqdech x0, pow2, mul #8
SQDECH X0, POW2, MUL #8
sqdech x0, pow2, mul #9
SQDECH X0, POW2, MUL #9
sqdech x0, pow2, mul #10
SQDECH X0, POW2, MUL #10
sqdech x0, pow2, mul #16
SQDECH X0, POW2, MUL #16
sqdech x0, w0, pow2
SQDECH X0, W0, POW2
sqdech x0, w0, pow2, mul #1
sqdech x1, w1, pow2
SQDECH X1, W1, POW2
sqdech x1, w1, pow2, mul #1
sqdech xzr, wzr, pow2
SQDECH XZR, WZR, POW2
sqdech xzr, wzr, pow2, mul #1
sqdech x2, w2, pow2
SQDECH X2, W2, POW2
sqdech x2, w2, pow2, mul #1
sqdech x0, w0, vl1
SQDECH X0, W0, VL1
sqdech x0, w0, vl1, mul #1
sqdech x0, w0, vl2
SQDECH X0, W0, VL2
sqdech x0, w0, vl2, mul #1
sqdech x0, w0, vl3
SQDECH X0, W0, VL3
sqdech x0, w0, vl3, mul #1
sqdech x0, w0, vl4
SQDECH X0, W0, VL4
sqdech x0, w0, vl4, mul #1
sqdech x0, w0, vl5
SQDECH X0, W0, VL5
sqdech x0, w0, vl5, mul #1
sqdech x0, w0, vl6
SQDECH X0, W0, VL6
sqdech x0, w0, vl6, mul #1
sqdech x0, w0, vl7
SQDECH X0, W0, VL7
sqdech x0, w0, vl7, mul #1
sqdech x0, w0, vl8
SQDECH X0, W0, VL8
sqdech x0, w0, vl8, mul #1
sqdech x0, w0, vl16
SQDECH X0, W0, VL16
sqdech x0, w0, vl16, mul #1
sqdech x0, w0, vl32
SQDECH X0, W0, VL32
sqdech x0, w0, vl32, mul #1
sqdech x0, w0, vl64
SQDECH X0, W0, VL64
sqdech x0, w0, vl64, mul #1
sqdech x0, w0, vl128
SQDECH X0, W0, VL128
sqdech x0, w0, vl128, mul #1
sqdech x0, w0, vl256
SQDECH X0, W0, VL256
sqdech x0, w0, vl256, mul #1
sqdech x0, w0, #14
SQDECH X0, W0, #14
sqdech x0, w0, #14, mul #1
sqdech x0, w0, #15
SQDECH X0, W0, #15
sqdech x0, w0, #15, mul #1
sqdech x0, w0, #16
SQDECH X0, W0, #16
sqdech x0, w0, #16, mul #1
sqdech x0, w0, #17
SQDECH X0, W0, #17
sqdech x0, w0, #17, mul #1
sqdech x0, w0, #18
SQDECH X0, W0, #18
sqdech x0, w0, #18, mul #1
sqdech x0, w0, #19
SQDECH X0, W0, #19
sqdech x0, w0, #19, mul #1
sqdech x0, w0, #20
SQDECH X0, W0, #20
sqdech x0, w0, #20, mul #1
sqdech x0, w0, #21
SQDECH X0, W0, #21
sqdech x0, w0, #21, mul #1
sqdech x0, w0, #22
SQDECH X0, W0, #22
sqdech x0, w0, #22, mul #1
sqdech x0, w0, #23
SQDECH X0, W0, #23
sqdech x0, w0, #23, mul #1
sqdech x0, w0, #24
SQDECH X0, W0, #24
sqdech x0, w0, #24, mul #1
sqdech x0, w0, #25
SQDECH X0, W0, #25
sqdech x0, w0, #25, mul #1
sqdech x0, w0, #26
SQDECH X0, W0, #26
sqdech x0, w0, #26, mul #1
sqdech x0, w0, #27
SQDECH X0, W0, #27
sqdech x0, w0, #27, mul #1
sqdech x0, w0, #28
SQDECH X0, W0, #28
sqdech x0, w0, #28, mul #1
sqdech x0, w0, mul4
SQDECH X0, W0, MUL4
sqdech x0, w0, mul4, mul #1
sqdech x0, w0, mul3
SQDECH X0, W0, MUL3
sqdech x0, w0, mul3, mul #1
sqdech x0, w0
SQDECH X0, W0
sqdech x0, w0, all
sqdech x0, w0, all, mul #1
sqdech x0, w0, pow2, mul #8
SQDECH X0, W0, POW2, MUL #8
sqdech x0, w0, pow2, mul #9
SQDECH X0, W0, POW2, MUL #9
sqdech x0, w0, pow2, mul #10
SQDECH X0, W0, POW2, MUL #10
sqdech x0, w0, pow2, mul #16
SQDECH X0, W0, POW2, MUL #16
sqdecp z0.h, p0
SQDECP Z0.H, P0
sqdecp z1.h, p0
SQDECP Z1.H, P0
sqdecp z31.h, p0
SQDECP Z31.H, P0
sqdecp z0.h, p2
SQDECP Z0.H, P2
sqdecp z0.h, p15
SQDECP Z0.H, P15
sqdecp z0.s, p0
SQDECP Z0.S, P0
sqdecp z1.s, p0
SQDECP Z1.S, P0
sqdecp z31.s, p0
SQDECP Z31.S, P0
sqdecp z0.s, p2
SQDECP Z0.S, P2
sqdecp z0.s, p15
SQDECP Z0.S, P15
sqdecp z0.d, p0
SQDECP Z0.D, P0
sqdecp z1.d, p0
SQDECP Z1.D, P0
sqdecp z31.d, p0
SQDECP Z31.D, P0
sqdecp z0.d, p2
SQDECP Z0.D, P2
sqdecp z0.d, p15
SQDECP Z0.D, P15
sqdecp x0, p0.b
SQDECP X0, P0.B
sqdecp x1, p0.b
SQDECP X1, P0.B
sqdecp xzr, p0.b
SQDECP XZR, P0.B
sqdecp x0, p2.b
SQDECP X0, P2.B
sqdecp x0, p15.b
SQDECP X0, P15.B
sqdecp x0, p0.h
SQDECP X0, P0.H
sqdecp x1, p0.h
SQDECP X1, P0.H
sqdecp xzr, p0.h
SQDECP XZR, P0.H
sqdecp x0, p2.h
SQDECP X0, P2.H
sqdecp x0, p15.h
SQDECP X0, P15.H
sqdecp x0, p0.s
SQDECP X0, P0.S
sqdecp x1, p0.s
SQDECP X1, P0.S
sqdecp xzr, p0.s
SQDECP XZR, P0.S
sqdecp x0, p2.s
SQDECP X0, P2.S
sqdecp x0, p15.s
SQDECP X0, P15.S
sqdecp x0, p0.d
SQDECP X0, P0.D
sqdecp x1, p0.d
SQDECP X1, P0.D
sqdecp xzr, p0.d
SQDECP XZR, P0.D
sqdecp x0, p2.d
SQDECP X0, P2.D
sqdecp x0, p15.d
SQDECP X0, P15.D
sqdecp x0, p0.b, w0
SQDECP X0, P0.B, W0
sqdecp x1, p0.b, w1
SQDECP X1, P0.B, W1
sqdecp xzr, p0.b, wzr
SQDECP XZR, P0.B, WZR
sqdecp x0, p2.b, w0
SQDECP X0, P2.B, W0
sqdecp x0, p15.b, w0
SQDECP X0, P15.B, W0
sqdecp x3, p0.b, w3
SQDECP X3, P0.B, W3
sqdecp x0, p0.h, w0
SQDECP X0, P0.H, W0
sqdecp x1, p0.h, w1
SQDECP X1, P0.H, W1
sqdecp xzr, p0.h, wzr
SQDECP XZR, P0.H, WZR
sqdecp x0, p2.h, w0
SQDECP X0, P2.H, W0
sqdecp x0, p15.h, w0
SQDECP X0, P15.H, W0
sqdecp x3, p0.h, w3
SQDECP X3, P0.H, W3
sqdecp x0, p0.s, w0
SQDECP X0, P0.S, W0
sqdecp x1, p0.s, w1
SQDECP X1, P0.S, W1
sqdecp xzr, p0.s, wzr
SQDECP XZR, P0.S, WZR
sqdecp x0, p2.s, w0
SQDECP X0, P2.S, W0
sqdecp x0, p15.s, w0
SQDECP X0, P15.S, W0
sqdecp x3, p0.s, w3
SQDECP X3, P0.S, W3
sqdecp x0, p0.d, w0
SQDECP X0, P0.D, W0
sqdecp x1, p0.d, w1
SQDECP X1, P0.D, W1
sqdecp xzr, p0.d, wzr
SQDECP XZR, P0.D, WZR
sqdecp x0, p2.d, w0
SQDECP X0, P2.D, W0
sqdecp x0, p15.d, w0
SQDECP X0, P15.D, W0
sqdecp x3, p0.d, w3
SQDECP X3, P0.D, W3
sqdecw z0.s, pow2
SQDECW Z0.S, POW2
sqdecw z0.s, pow2, mul #1
sqdecw z1.s, pow2
SQDECW Z1.S, POW2
sqdecw z1.s, pow2, mul #1
sqdecw z31.s, pow2
SQDECW Z31.S, POW2
sqdecw z31.s, pow2, mul #1
sqdecw z0.s, vl1
SQDECW Z0.S, VL1
sqdecw z0.s, vl1, mul #1
sqdecw z0.s, vl2
SQDECW Z0.S, VL2
sqdecw z0.s, vl2, mul #1
sqdecw z0.s, vl3
SQDECW Z0.S, VL3
sqdecw z0.s, vl3, mul #1
sqdecw z0.s, vl4
SQDECW Z0.S, VL4
sqdecw z0.s, vl4, mul #1
sqdecw z0.s, vl5
SQDECW Z0.S, VL5
sqdecw z0.s, vl5, mul #1
sqdecw z0.s, vl6
SQDECW Z0.S, VL6
sqdecw z0.s, vl6, mul #1
sqdecw z0.s, vl7
SQDECW Z0.S, VL7
sqdecw z0.s, vl7, mul #1
sqdecw z0.s, vl8
SQDECW Z0.S, VL8
sqdecw z0.s, vl8, mul #1
sqdecw z0.s, vl16
SQDECW Z0.S, VL16
sqdecw z0.s, vl16, mul #1
sqdecw z0.s, vl32
SQDECW Z0.S, VL32
sqdecw z0.s, vl32, mul #1
sqdecw z0.s, vl64
SQDECW Z0.S, VL64
sqdecw z0.s, vl64, mul #1
sqdecw z0.s, vl128
SQDECW Z0.S, VL128
sqdecw z0.s, vl128, mul #1
sqdecw z0.s, vl256
SQDECW Z0.S, VL256
sqdecw z0.s, vl256, mul #1
sqdecw z0.s, #14
SQDECW Z0.S, #14
sqdecw z0.s, #14, mul #1
sqdecw z0.s, #15
SQDECW Z0.S, #15
sqdecw z0.s, #15, mul #1
sqdecw z0.s, #16
SQDECW Z0.S, #16
sqdecw z0.s, #16, mul #1
sqdecw z0.s, #17
SQDECW Z0.S, #17
sqdecw z0.s, #17, mul #1
sqdecw z0.s, #18
SQDECW Z0.S, #18
sqdecw z0.s, #18, mul #1
sqdecw z0.s, #19
SQDECW Z0.S, #19
sqdecw z0.s, #19, mul #1
sqdecw z0.s, #20
SQDECW Z0.S, #20
sqdecw z0.s, #20, mul #1
sqdecw z0.s, #21
SQDECW Z0.S, #21
sqdecw z0.s, #21, mul #1
sqdecw z0.s, #22
SQDECW Z0.S, #22
sqdecw z0.s, #22, mul #1
sqdecw z0.s, #23
SQDECW Z0.S, #23
sqdecw z0.s, #23, mul #1
sqdecw z0.s, #24
SQDECW Z0.S, #24
sqdecw z0.s, #24, mul #1
sqdecw z0.s, #25
SQDECW Z0.S, #25
sqdecw z0.s, #25, mul #1
sqdecw z0.s, #26
SQDECW Z0.S, #26
sqdecw z0.s, #26, mul #1
sqdecw z0.s, #27
SQDECW Z0.S, #27
sqdecw z0.s, #27, mul #1
sqdecw z0.s, #28
SQDECW Z0.S, #28
sqdecw z0.s, #28, mul #1
sqdecw z0.s, mul4
SQDECW Z0.S, MUL4
sqdecw z0.s, mul4, mul #1
sqdecw z0.s, mul3
SQDECW Z0.S, MUL3
sqdecw z0.s, mul3, mul #1
sqdecw z0.s
SQDECW Z0.S
sqdecw z0.s, all
sqdecw z0.s, all, mul #1
sqdecw z0.s, pow2, mul #8
SQDECW Z0.S, POW2, MUL #8
sqdecw z0.s, pow2, mul #9
SQDECW Z0.S, POW2, MUL #9
sqdecw z0.s, pow2, mul #10
SQDECW Z0.S, POW2, MUL #10
sqdecw z0.s, pow2, mul #16
SQDECW Z0.S, POW2, MUL #16
sqdecw x0, pow2
SQDECW X0, POW2
sqdecw x0, pow2, mul #1
sqdecw x1, pow2
SQDECW X1, POW2
sqdecw x1, pow2, mul #1
sqdecw xzr, pow2
SQDECW XZR, POW2
sqdecw xzr, pow2, mul #1
sqdecw x0, vl1
SQDECW X0, VL1
sqdecw x0, vl1, mul #1
sqdecw x0, vl2
SQDECW X0, VL2
sqdecw x0, vl2, mul #1
sqdecw x0, vl3
SQDECW X0, VL3
sqdecw x0, vl3, mul #1
sqdecw x0, vl4
SQDECW X0, VL4
sqdecw x0, vl4, mul #1
sqdecw x0, vl5
SQDECW X0, VL5
sqdecw x0, vl5, mul #1
sqdecw x0, vl6
SQDECW X0, VL6
sqdecw x0, vl6, mul #1
sqdecw x0, vl7
SQDECW X0, VL7
sqdecw x0, vl7, mul #1
sqdecw x0, vl8
SQDECW X0, VL8
sqdecw x0, vl8, mul #1
sqdecw x0, vl16
SQDECW X0, VL16
sqdecw x0, vl16, mul #1
sqdecw x0, vl32
SQDECW X0, VL32
sqdecw x0, vl32, mul #1
sqdecw x0, vl64
SQDECW X0, VL64
sqdecw x0, vl64, mul #1
sqdecw x0, vl128
SQDECW X0, VL128
sqdecw x0, vl128, mul #1
sqdecw x0, vl256
SQDECW X0, VL256
sqdecw x0, vl256, mul #1
sqdecw x0, #14
SQDECW X0, #14
sqdecw x0, #14, mul #1
sqdecw x0, #15
SQDECW X0, #15
sqdecw x0, #15, mul #1
sqdecw x0, #16
SQDECW X0, #16
sqdecw x0, #16, mul #1
sqdecw x0, #17
SQDECW X0, #17
sqdecw x0, #17, mul #1
sqdecw x0, #18
SQDECW X0, #18
sqdecw x0, #18, mul #1
sqdecw x0, #19
SQDECW X0, #19
sqdecw x0, #19, mul #1
sqdecw x0, #20
SQDECW X0, #20
sqdecw x0, #20, mul #1
sqdecw x0, #21
SQDECW X0, #21
sqdecw x0, #21, mul #1
sqdecw x0, #22
SQDECW X0, #22
sqdecw x0, #22, mul #1
sqdecw x0, #23
SQDECW X0, #23
sqdecw x0, #23, mul #1
sqdecw x0, #24
SQDECW X0, #24
sqdecw x0, #24, mul #1
sqdecw x0, #25
SQDECW X0, #25
sqdecw x0, #25, mul #1
sqdecw x0, #26
SQDECW X0, #26
sqdecw x0, #26, mul #1
sqdecw x0, #27
SQDECW X0, #27
sqdecw x0, #27, mul #1
sqdecw x0, #28
SQDECW X0, #28
sqdecw x0, #28, mul #1
sqdecw x0, mul4
SQDECW X0, MUL4
sqdecw x0, mul4, mul #1
sqdecw x0, mul3
SQDECW X0, MUL3
sqdecw x0, mul3, mul #1
sqdecw x0
SQDECW X0
sqdecw x0, all
sqdecw x0, all, mul #1
sqdecw x0, pow2, mul #8
SQDECW X0, POW2, MUL #8
sqdecw x0, pow2, mul #9
SQDECW X0, POW2, MUL #9
sqdecw x0, pow2, mul #10
SQDECW X0, POW2, MUL #10
sqdecw x0, pow2, mul #16
SQDECW X0, POW2, MUL #16
sqdecw x0, w0, pow2
SQDECW X0, W0, POW2
sqdecw x0, w0, pow2, mul #1
sqdecw x1, w1, pow2
SQDECW X1, W1, POW2
sqdecw x1, w1, pow2, mul #1
sqdecw xzr, wzr, pow2
SQDECW XZR, WZR, POW2
sqdecw xzr, wzr, pow2, mul #1
sqdecw x2, w2, pow2
SQDECW X2, W2, POW2
sqdecw x2, w2, pow2, mul #1
sqdecw x0, w0, vl1
SQDECW X0, W0, VL1
sqdecw x0, w0, vl1, mul #1
sqdecw x0, w0, vl2
SQDECW X0, W0, VL2
sqdecw x0, w0, vl2, mul #1
sqdecw x0, w0, vl3
SQDECW X0, W0, VL3
sqdecw x0, w0, vl3, mul #1
sqdecw x0, w0, vl4
SQDECW X0, W0, VL4
sqdecw x0, w0, vl4, mul #1
sqdecw x0, w0, vl5
SQDECW X0, W0, VL5
sqdecw x0, w0, vl5, mul #1
sqdecw x0, w0, vl6
SQDECW X0, W0, VL6
sqdecw x0, w0, vl6, mul #1
sqdecw x0, w0, vl7
SQDECW X0, W0, VL7
sqdecw x0, w0, vl7, mul #1
sqdecw x0, w0, vl8
SQDECW X0, W0, VL8
sqdecw x0, w0, vl8, mul #1
sqdecw x0, w0, vl16
SQDECW X0, W0, VL16
sqdecw x0, w0, vl16, mul #1
sqdecw x0, w0, vl32
SQDECW X0, W0, VL32
sqdecw x0, w0, vl32, mul #1
sqdecw x0, w0, vl64
SQDECW X0, W0, VL64
sqdecw x0, w0, vl64, mul #1
sqdecw x0, w0, vl128
SQDECW X0, W0, VL128
sqdecw x0, w0, vl128, mul #1
sqdecw x0, w0, vl256
SQDECW X0, W0, VL256
sqdecw x0, w0, vl256, mul #1
sqdecw x0, w0, #14
SQDECW X0, W0, #14
sqdecw x0, w0, #14, mul #1
sqdecw x0, w0, #15
SQDECW X0, W0, #15
sqdecw x0, w0, #15, mul #1
sqdecw x0, w0, #16
SQDECW X0, W0, #16
sqdecw x0, w0, #16, mul #1
sqdecw x0, w0, #17
SQDECW X0, W0, #17
sqdecw x0, w0, #17, mul #1
sqdecw x0, w0, #18
SQDECW X0, W0, #18
sqdecw x0, w0, #18, mul #1
sqdecw x0, w0, #19
SQDECW X0, W0, #19
sqdecw x0, w0, #19, mul #1
sqdecw x0, w0, #20
SQDECW X0, W0, #20
sqdecw x0, w0, #20, mul #1
sqdecw x0, w0, #21
SQDECW X0, W0, #21
sqdecw x0, w0, #21, mul #1
sqdecw x0, w0, #22
SQDECW X0, W0, #22
sqdecw x0, w0, #22, mul #1
sqdecw x0, w0, #23
SQDECW X0, W0, #23
sqdecw x0, w0, #23, mul #1
sqdecw x0, w0, #24
SQDECW X0, W0, #24
sqdecw x0, w0, #24, mul #1
sqdecw x0, w0, #25
SQDECW X0, W0, #25
sqdecw x0, w0, #25, mul #1
sqdecw x0, w0, #26
SQDECW X0, W0, #26
sqdecw x0, w0, #26, mul #1
sqdecw x0, w0, #27
SQDECW X0, W0, #27
sqdecw x0, w0, #27, mul #1
sqdecw x0, w0, #28
SQDECW X0, W0, #28
sqdecw x0, w0, #28, mul #1
sqdecw x0, w0, mul4
SQDECW X0, W0, MUL4
sqdecw x0, w0, mul4, mul #1
sqdecw x0, w0, mul3
SQDECW X0, W0, MUL3
sqdecw x0, w0, mul3, mul #1
sqdecw x0, w0
SQDECW X0, W0
sqdecw x0, w0, all
sqdecw x0, w0, all, mul #1
sqdecw x0, w0, pow2, mul #8
SQDECW X0, W0, POW2, MUL #8
sqdecw x0, w0, pow2, mul #9
SQDECW X0, W0, POW2, MUL #9
sqdecw x0, w0, pow2, mul #10
SQDECW X0, W0, POW2, MUL #10
sqdecw x0, w0, pow2, mul #16
SQDECW X0, W0, POW2, MUL #16
sqincb x0, pow2
SQINCB X0, POW2
sqincb x0, pow2, mul #1
sqincb x1, pow2
SQINCB X1, POW2
sqincb x1, pow2, mul #1
sqincb xzr, pow2
SQINCB XZR, POW2
sqincb xzr, pow2, mul #1
sqincb x0, vl1
SQINCB X0, VL1
sqincb x0, vl1, mul #1
sqincb x0, vl2
SQINCB X0, VL2
sqincb x0, vl2, mul #1
sqincb x0, vl3
SQINCB X0, VL3
sqincb x0, vl3, mul #1
sqincb x0, vl4
SQINCB X0, VL4
sqincb x0, vl4, mul #1
sqincb x0, vl5
SQINCB X0, VL5
sqincb x0, vl5, mul #1
sqincb x0, vl6
SQINCB X0, VL6
sqincb x0, vl6, mul #1
sqincb x0, vl7
SQINCB X0, VL7
sqincb x0, vl7, mul #1
sqincb x0, vl8
SQINCB X0, VL8
sqincb x0, vl8, mul #1
sqincb x0, vl16
SQINCB X0, VL16
sqincb x0, vl16, mul #1
sqincb x0, vl32
SQINCB X0, VL32
sqincb x0, vl32, mul #1
sqincb x0, vl64
SQINCB X0, VL64
sqincb x0, vl64, mul #1
sqincb x0, vl128
SQINCB X0, VL128
sqincb x0, vl128, mul #1
sqincb x0, vl256
SQINCB X0, VL256
sqincb x0, vl256, mul #1
sqincb x0, #14
SQINCB X0, #14
sqincb x0, #14, mul #1
sqincb x0, #15
SQINCB X0, #15
sqincb x0, #15, mul #1
sqincb x0, #16
SQINCB X0, #16
sqincb x0, #16, mul #1
sqincb x0, #17
SQINCB X0, #17
sqincb x0, #17, mul #1
sqincb x0, #18
SQINCB X0, #18
sqincb x0, #18, mul #1
sqincb x0, #19
SQINCB X0, #19
sqincb x0, #19, mul #1
sqincb x0, #20
SQINCB X0, #20
sqincb x0, #20, mul #1
sqincb x0, #21
SQINCB X0, #21
sqincb x0, #21, mul #1
sqincb x0, #22
SQINCB X0, #22
sqincb x0, #22, mul #1
sqincb x0, #23
SQINCB X0, #23
sqincb x0, #23, mul #1
sqincb x0, #24
SQINCB X0, #24
sqincb x0, #24, mul #1
sqincb x0, #25
SQINCB X0, #25
sqincb x0, #25, mul #1
sqincb x0, #26
SQINCB X0, #26
sqincb x0, #26, mul #1
sqincb x0, #27
SQINCB X0, #27
sqincb x0, #27, mul #1
sqincb x0, #28
SQINCB X0, #28
sqincb x0, #28, mul #1
sqincb x0, mul4
SQINCB X0, MUL4
sqincb x0, mul4, mul #1
sqincb x0, mul3
SQINCB X0, MUL3
sqincb x0, mul3, mul #1
sqincb x0
SQINCB X0
sqincb x0, all
sqincb x0, all, mul #1
sqincb x0, pow2, mul #8
SQINCB X0, POW2, MUL #8
sqincb x0, pow2, mul #9
SQINCB X0, POW2, MUL #9
sqincb x0, pow2, mul #10
SQINCB X0, POW2, MUL #10
sqincb x0, pow2, mul #16
SQINCB X0, POW2, MUL #16
sqincb x0, w0, pow2
SQINCB X0, W0, POW2
sqincb x0, w0, pow2, mul #1
sqincb x1, w1, pow2
SQINCB X1, W1, POW2
sqincb x1, w1, pow2, mul #1
sqincb xzr, wzr, pow2
SQINCB XZR, WZR, POW2
sqincb xzr, wzr, pow2, mul #1
sqincb x2, w2, pow2
SQINCB X2, W2, POW2
sqincb x2, w2, pow2, mul #1
sqincb x0, w0, vl1
SQINCB X0, W0, VL1
sqincb x0, w0, vl1, mul #1
sqincb x0, w0, vl2
SQINCB X0, W0, VL2
sqincb x0, w0, vl2, mul #1
sqincb x0, w0, vl3
SQINCB X0, W0, VL3
sqincb x0, w0, vl3, mul #1
sqincb x0, w0, vl4
SQINCB X0, W0, VL4
sqincb x0, w0, vl4, mul #1
sqincb x0, w0, vl5
SQINCB X0, W0, VL5
sqincb x0, w0, vl5, mul #1
sqincb x0, w0, vl6
SQINCB X0, W0, VL6
sqincb x0, w0, vl6, mul #1
sqincb x0, w0, vl7
SQINCB X0, W0, VL7
sqincb x0, w0, vl7, mul #1
sqincb x0, w0, vl8
SQINCB X0, W0, VL8
sqincb x0, w0, vl8, mul #1
sqincb x0, w0, vl16
SQINCB X0, W0, VL16
sqincb x0, w0, vl16, mul #1
sqincb x0, w0, vl32
SQINCB X0, W0, VL32
sqincb x0, w0, vl32, mul #1
sqincb x0, w0, vl64
SQINCB X0, W0, VL64
sqincb x0, w0, vl64, mul #1
sqincb x0, w0, vl128
SQINCB X0, W0, VL128
sqincb x0, w0, vl128, mul #1
sqincb x0, w0, vl256
SQINCB X0, W0, VL256
sqincb x0, w0, vl256, mul #1
sqincb x0, w0, #14
SQINCB X0, W0, #14
sqincb x0, w0, #14, mul #1
sqincb x0, w0, #15
SQINCB X0, W0, #15
sqincb x0, w0, #15, mul #1
sqincb x0, w0, #16
SQINCB X0, W0, #16
sqincb x0, w0, #16, mul #1
sqincb x0, w0, #17
SQINCB X0, W0, #17
sqincb x0, w0, #17, mul #1
sqincb x0, w0, #18
SQINCB X0, W0, #18
sqincb x0, w0, #18, mul #1
sqincb x0, w0, #19
SQINCB X0, W0, #19
sqincb x0, w0, #19, mul #1
sqincb x0, w0, #20
SQINCB X0, W0, #20
sqincb x0, w0, #20, mul #1
sqincb x0, w0, #21
SQINCB X0, W0, #21
sqincb x0, w0, #21, mul #1
sqincb x0, w0, #22
SQINCB X0, W0, #22
sqincb x0, w0, #22, mul #1
sqincb x0, w0, #23
SQINCB X0, W0, #23
sqincb x0, w0, #23, mul #1
sqincb x0, w0, #24
SQINCB X0, W0, #24
sqincb x0, w0, #24, mul #1
sqincb x0, w0, #25
SQINCB X0, W0, #25
sqincb x0, w0, #25, mul #1
sqincb x0, w0, #26
SQINCB X0, W0, #26
sqincb x0, w0, #26, mul #1
sqincb x0, w0, #27
SQINCB X0, W0, #27
sqincb x0, w0, #27, mul #1
sqincb x0, w0, #28
SQINCB X0, W0, #28
sqincb x0, w0, #28, mul #1
sqincb x0, w0, mul4
SQINCB X0, W0, MUL4
sqincb x0, w0, mul4, mul #1
sqincb x0, w0, mul3
SQINCB X0, W0, MUL3
sqincb x0, w0, mul3, mul #1
sqincb x0, w0
SQINCB X0, W0
sqincb x0, w0, all
sqincb x0, w0, all, mul #1
sqincb x0, w0, pow2, mul #8
SQINCB X0, W0, POW2, MUL #8
sqincb x0, w0, pow2, mul #9
SQINCB X0, W0, POW2, MUL #9
sqincb x0, w0, pow2, mul #10
SQINCB X0, W0, POW2, MUL #10
sqincb x0, w0, pow2, mul #16
SQINCB X0, W0, POW2, MUL #16
sqincd z0.d, pow2
SQINCD Z0.D, POW2
sqincd z0.d, pow2, mul #1
sqincd z1.d, pow2
SQINCD Z1.D, POW2
sqincd z1.d, pow2, mul #1
sqincd z31.d, pow2
SQINCD Z31.D, POW2
sqincd z31.d, pow2, mul #1
sqincd z0.d, vl1
SQINCD Z0.D, VL1
sqincd z0.d, vl1, mul #1
sqincd z0.d, vl2
SQINCD Z0.D, VL2
sqincd z0.d, vl2, mul #1
sqincd z0.d, vl3
SQINCD Z0.D, VL3
sqincd z0.d, vl3, mul #1
sqincd z0.d, vl4
SQINCD Z0.D, VL4
sqincd z0.d, vl4, mul #1
sqincd z0.d, vl5
SQINCD Z0.D, VL5
sqincd z0.d, vl5, mul #1
sqincd z0.d, vl6
SQINCD Z0.D, VL6
sqincd z0.d, vl6, mul #1
sqincd z0.d, vl7
SQINCD Z0.D, VL7
sqincd z0.d, vl7, mul #1
sqincd z0.d, vl8
SQINCD Z0.D, VL8
sqincd z0.d, vl8, mul #1
sqincd z0.d, vl16
SQINCD Z0.D, VL16
sqincd z0.d, vl16, mul #1
sqincd z0.d, vl32
SQINCD Z0.D, VL32
sqincd z0.d, vl32, mul #1
sqincd z0.d, vl64
SQINCD Z0.D, VL64
sqincd z0.d, vl64, mul #1
sqincd z0.d, vl128
SQINCD Z0.D, VL128
sqincd z0.d, vl128, mul #1
sqincd z0.d, vl256
SQINCD Z0.D, VL256
sqincd z0.d, vl256, mul #1
sqincd z0.d, #14
SQINCD Z0.D, #14
sqincd z0.d, #14, mul #1
sqincd z0.d, #15
SQINCD Z0.D, #15
sqincd z0.d, #15, mul #1
sqincd z0.d, #16
SQINCD Z0.D, #16
sqincd z0.d, #16, mul #1
sqincd z0.d, #17
SQINCD Z0.D, #17
sqincd z0.d, #17, mul #1
sqincd z0.d, #18
SQINCD Z0.D, #18
sqincd z0.d, #18, mul #1
sqincd z0.d, #19
SQINCD Z0.D, #19
sqincd z0.d, #19, mul #1
sqincd z0.d, #20
SQINCD Z0.D, #20
sqincd z0.d, #20, mul #1
sqincd z0.d, #21
SQINCD Z0.D, #21
sqincd z0.d, #21, mul #1
sqincd z0.d, #22
SQINCD Z0.D, #22
sqincd z0.d, #22, mul #1
sqincd z0.d, #23
SQINCD Z0.D, #23
sqincd z0.d, #23, mul #1
sqincd z0.d, #24
SQINCD Z0.D, #24
sqincd z0.d, #24, mul #1
sqincd z0.d, #25
SQINCD Z0.D, #25
sqincd z0.d, #25, mul #1
sqincd z0.d, #26
SQINCD Z0.D, #26
sqincd z0.d, #26, mul #1
sqincd z0.d, #27
SQINCD Z0.D, #27
sqincd z0.d, #27, mul #1
sqincd z0.d, #28
SQINCD Z0.D, #28
sqincd z0.d, #28, mul #1
sqincd z0.d, mul4
SQINCD Z0.D, MUL4
sqincd z0.d, mul4, mul #1
sqincd z0.d, mul3
SQINCD Z0.D, MUL3
sqincd z0.d, mul3, mul #1
sqincd z0.d
SQINCD Z0.D
sqincd z0.d, all
sqincd z0.d, all, mul #1
sqincd z0.d, pow2, mul #8
SQINCD Z0.D, POW2, MUL #8
sqincd z0.d, pow2, mul #9
SQINCD Z0.D, POW2, MUL #9
sqincd z0.d, pow2, mul #10
SQINCD Z0.D, POW2, MUL #10
sqincd z0.d, pow2, mul #16
SQINCD Z0.D, POW2, MUL #16
sqincd x0, pow2
SQINCD X0, POW2
sqincd x0, pow2, mul #1
sqincd x1, pow2
SQINCD X1, POW2
sqincd x1, pow2, mul #1
sqincd xzr, pow2
SQINCD XZR, POW2
sqincd xzr, pow2, mul #1
sqincd x0, vl1
SQINCD X0, VL1
sqincd x0, vl1, mul #1
sqincd x0, vl2
SQINCD X0, VL2
sqincd x0, vl2, mul #1
sqincd x0, vl3
SQINCD X0, VL3
sqincd x0, vl3, mul #1
sqincd x0, vl4
SQINCD X0, VL4
sqincd x0, vl4, mul #1
sqincd x0, vl5
SQINCD X0, VL5
sqincd x0, vl5, mul #1
sqincd x0, vl6
SQINCD X0, VL6
sqincd x0, vl6, mul #1
sqincd x0, vl7
SQINCD X0, VL7
sqincd x0, vl7, mul #1
sqincd x0, vl8
SQINCD X0, VL8
sqincd x0, vl8, mul #1
sqincd x0, vl16
SQINCD X0, VL16
sqincd x0, vl16, mul #1
sqincd x0, vl32
SQINCD X0, VL32
sqincd x0, vl32, mul #1
sqincd x0, vl64
SQINCD X0, VL64
sqincd x0, vl64, mul #1
sqincd x0, vl128
SQINCD X0, VL128
sqincd x0, vl128, mul #1
sqincd x0, vl256
SQINCD X0, VL256
sqincd x0, vl256, mul #1
sqincd x0, #14
SQINCD X0, #14
sqincd x0, #14, mul #1
sqincd x0, #15
SQINCD X0, #15
sqincd x0, #15, mul #1
sqincd x0, #16
SQINCD X0, #16
sqincd x0, #16, mul #1
sqincd x0, #17
SQINCD X0, #17
sqincd x0, #17, mul #1
sqincd x0, #18
SQINCD X0, #18
sqincd x0, #18, mul #1
sqincd x0, #19
SQINCD X0, #19
sqincd x0, #19, mul #1
sqincd x0, #20
SQINCD X0, #20
sqincd x0, #20, mul #1
sqincd x0, #21
SQINCD X0, #21
sqincd x0, #21, mul #1
sqincd x0, #22
SQINCD X0, #22
sqincd x0, #22, mul #1
sqincd x0, #23
SQINCD X0, #23
sqincd x0, #23, mul #1
sqincd x0, #24
SQINCD X0, #24
sqincd x0, #24, mul #1
sqincd x0, #25
SQINCD X0, #25
sqincd x0, #25, mul #1
sqincd x0, #26
SQINCD X0, #26
sqincd x0, #26, mul #1
sqincd x0, #27
SQINCD X0, #27
sqincd x0, #27, mul #1
sqincd x0, #28
SQINCD X0, #28
sqincd x0, #28, mul #1
sqincd x0, mul4
SQINCD X0, MUL4
sqincd x0, mul4, mul #1
sqincd x0, mul3
SQINCD X0, MUL3
sqincd x0, mul3, mul #1
sqincd x0
SQINCD X0
sqincd x0, all
sqincd x0, all, mul #1
sqincd x0, pow2, mul #8
SQINCD X0, POW2, MUL #8
sqincd x0, pow2, mul #9
SQINCD X0, POW2, MUL #9
sqincd x0, pow2, mul #10
SQINCD X0, POW2, MUL #10
sqincd x0, pow2, mul #16
SQINCD X0, POW2, MUL #16
sqincd x0, w0, pow2
SQINCD X0, W0, POW2
sqincd x0, w0, pow2, mul #1
sqincd x1, w1, pow2
SQINCD X1, W1, POW2
sqincd x1, w1, pow2, mul #1
sqincd xzr, wzr, pow2
SQINCD XZR, WZR, POW2
sqincd xzr, wzr, pow2, mul #1
sqincd x2, w2, pow2
SQINCD X2, W2, POW2
sqincd x2, w2, pow2, mul #1
sqincd x0, w0, vl1
SQINCD X0, W0, VL1
sqincd x0, w0, vl1, mul #1
sqincd x0, w0, vl2
SQINCD X0, W0, VL2
sqincd x0, w0, vl2, mul #1
sqincd x0, w0, vl3
SQINCD X0, W0, VL3
sqincd x0, w0, vl3, mul #1
sqincd x0, w0, vl4
SQINCD X0, W0, VL4
sqincd x0, w0, vl4, mul #1
sqincd x0, w0, vl5
SQINCD X0, W0, VL5
sqincd x0, w0, vl5, mul #1
sqincd x0, w0, vl6
SQINCD X0, W0, VL6
sqincd x0, w0, vl6, mul #1
sqincd x0, w0, vl7
SQINCD X0, W0, VL7
sqincd x0, w0, vl7, mul #1
sqincd x0, w0, vl8
SQINCD X0, W0, VL8
sqincd x0, w0, vl8, mul #1
sqincd x0, w0, vl16
SQINCD X0, W0, VL16
sqincd x0, w0, vl16, mul #1
sqincd x0, w0, vl32
SQINCD X0, W0, VL32
sqincd x0, w0, vl32, mul #1
sqincd x0, w0, vl64
SQINCD X0, W0, VL64
sqincd x0, w0, vl64, mul #1
sqincd x0, w0, vl128
SQINCD X0, W0, VL128
sqincd x0, w0, vl128, mul #1
sqincd x0, w0, vl256
SQINCD X0, W0, VL256
sqincd x0, w0, vl256, mul #1
sqincd x0, w0, #14
SQINCD X0, W0, #14
sqincd x0, w0, #14, mul #1
sqincd x0, w0, #15
SQINCD X0, W0, #15
sqincd x0, w0, #15, mul #1
sqincd x0, w0, #16
SQINCD X0, W0, #16
sqincd x0, w0, #16, mul #1
sqincd x0, w0, #17
SQINCD X0, W0, #17
sqincd x0, w0, #17, mul #1
sqincd x0, w0, #18
SQINCD X0, W0, #18
sqincd x0, w0, #18, mul #1
sqincd x0, w0, #19
SQINCD X0, W0, #19
sqincd x0, w0, #19, mul #1
sqincd x0, w0, #20
SQINCD X0, W0, #20
sqincd x0, w0, #20, mul #1
sqincd x0, w0, #21
SQINCD X0, W0, #21
sqincd x0, w0, #21, mul #1
sqincd x0, w0, #22
SQINCD X0, W0, #22
sqincd x0, w0, #22, mul #1
sqincd x0, w0, #23
SQINCD X0, W0, #23
sqincd x0, w0, #23, mul #1
sqincd x0, w0, #24
SQINCD X0, W0, #24
sqincd x0, w0, #24, mul #1
sqincd x0, w0, #25
SQINCD X0, W0, #25
sqincd x0, w0, #25, mul #1
sqincd x0, w0, #26
SQINCD X0, W0, #26
sqincd x0, w0, #26, mul #1
sqincd x0, w0, #27
SQINCD X0, W0, #27
sqincd x0, w0, #27, mul #1
sqincd x0, w0, #28
SQINCD X0, W0, #28
sqincd x0, w0, #28, mul #1
sqincd x0, w0, mul4
SQINCD X0, W0, MUL4
sqincd x0, w0, mul4, mul #1
sqincd x0, w0, mul3
SQINCD X0, W0, MUL3
sqincd x0, w0, mul3, mul #1
sqincd x0, w0
SQINCD X0, W0
sqincd x0, w0, all
sqincd x0, w0, all, mul #1
sqincd x0, w0, pow2, mul #8
SQINCD X0, W0, POW2, MUL #8
sqincd x0, w0, pow2, mul #9
SQINCD X0, W0, POW2, MUL #9
sqincd x0, w0, pow2, mul #10
SQINCD X0, W0, POW2, MUL #10
sqincd x0, w0, pow2, mul #16
SQINCD X0, W0, POW2, MUL #16
sqinch z0.h, pow2
SQINCH Z0.H, POW2
sqinch z0.h, pow2, mul #1
sqinch z1.h, pow2
SQINCH Z1.H, POW2
sqinch z1.h, pow2, mul #1
sqinch z31.h, pow2
SQINCH Z31.H, POW2
sqinch z31.h, pow2, mul #1
sqinch z0.h, vl1
SQINCH Z0.H, VL1
sqinch z0.h, vl1, mul #1
sqinch z0.h, vl2
SQINCH Z0.H, VL2
sqinch z0.h, vl2, mul #1
sqinch z0.h, vl3
SQINCH Z0.H, VL3
sqinch z0.h, vl3, mul #1
sqinch z0.h, vl4
SQINCH Z0.H, VL4
sqinch z0.h, vl4, mul #1
sqinch z0.h, vl5
SQINCH Z0.H, VL5
sqinch z0.h, vl5, mul #1
sqinch z0.h, vl6
SQINCH Z0.H, VL6
sqinch z0.h, vl6, mul #1
sqinch z0.h, vl7
SQINCH Z0.H, VL7
sqinch z0.h, vl7, mul #1
sqinch z0.h, vl8
SQINCH Z0.H, VL8
sqinch z0.h, vl8, mul #1
sqinch z0.h, vl16
SQINCH Z0.H, VL16
sqinch z0.h, vl16, mul #1
sqinch z0.h, vl32
SQINCH Z0.H, VL32
sqinch z0.h, vl32, mul #1
sqinch z0.h, vl64
SQINCH Z0.H, VL64
sqinch z0.h, vl64, mul #1
sqinch z0.h, vl128
SQINCH Z0.H, VL128
sqinch z0.h, vl128, mul #1
sqinch z0.h, vl256
SQINCH Z0.H, VL256
sqinch z0.h, vl256, mul #1
sqinch z0.h, #14
SQINCH Z0.H, #14
sqinch z0.h, #14, mul #1
sqinch z0.h, #15
SQINCH Z0.H, #15
sqinch z0.h, #15, mul #1
sqinch z0.h, #16
SQINCH Z0.H, #16
sqinch z0.h, #16, mul #1
sqinch z0.h, #17
SQINCH Z0.H, #17
sqinch z0.h, #17, mul #1
sqinch z0.h, #18
SQINCH Z0.H, #18
sqinch z0.h, #18, mul #1
sqinch z0.h, #19
SQINCH Z0.H, #19
sqinch z0.h, #19, mul #1
sqinch z0.h, #20
SQINCH Z0.H, #20
sqinch z0.h, #20, mul #1
sqinch z0.h, #21
SQINCH Z0.H, #21
sqinch z0.h, #21, mul #1
sqinch z0.h, #22
SQINCH Z0.H, #22
sqinch z0.h, #22, mul #1
sqinch z0.h, #23
SQINCH Z0.H, #23
sqinch z0.h, #23, mul #1
sqinch z0.h, #24
SQINCH Z0.H, #24
sqinch z0.h, #24, mul #1
sqinch z0.h, #25
SQINCH Z0.H, #25
sqinch z0.h, #25, mul #1
sqinch z0.h, #26
SQINCH Z0.H, #26
sqinch z0.h, #26, mul #1
sqinch z0.h, #27
SQINCH Z0.H, #27
sqinch z0.h, #27, mul #1
sqinch z0.h, #28
SQINCH Z0.H, #28
sqinch z0.h, #28, mul #1
sqinch z0.h, mul4
SQINCH Z0.H, MUL4
sqinch z0.h, mul4, mul #1
sqinch z0.h, mul3
SQINCH Z0.H, MUL3
sqinch z0.h, mul3, mul #1
sqinch z0.h
SQINCH Z0.H
sqinch z0.h, all
sqinch z0.h, all, mul #1
sqinch z0.h, pow2, mul #8
SQINCH Z0.H, POW2, MUL #8
sqinch z0.h, pow2, mul #9
SQINCH Z0.H, POW2, MUL #9
sqinch z0.h, pow2, mul #10
SQINCH Z0.H, POW2, MUL #10
sqinch z0.h, pow2, mul #16
SQINCH Z0.H, POW2, MUL #16
sqinch x0, pow2
SQINCH X0, POW2
sqinch x0, pow2, mul #1
sqinch x1, pow2
SQINCH X1, POW2
sqinch x1, pow2, mul #1
sqinch xzr, pow2
SQINCH XZR, POW2
sqinch xzr, pow2, mul #1
sqinch x0, vl1
SQINCH X0, VL1
sqinch x0, vl1, mul #1
sqinch x0, vl2
SQINCH X0, VL2
sqinch x0, vl2, mul #1
sqinch x0, vl3
SQINCH X0, VL3
sqinch x0, vl3, mul #1
sqinch x0, vl4
SQINCH X0, VL4
sqinch x0, vl4, mul #1
sqinch x0, vl5
SQINCH X0, VL5
sqinch x0, vl5, mul #1
sqinch x0, vl6
SQINCH X0, VL6
sqinch x0, vl6, mul #1
sqinch x0, vl7
SQINCH X0, VL7
sqinch x0, vl7, mul #1
sqinch x0, vl8
SQINCH X0, VL8
sqinch x0, vl8, mul #1
sqinch x0, vl16
SQINCH X0, VL16
sqinch x0, vl16, mul #1
sqinch x0, vl32
SQINCH X0, VL32
sqinch x0, vl32, mul #1
sqinch x0, vl64
SQINCH X0, VL64
sqinch x0, vl64, mul #1
sqinch x0, vl128
SQINCH X0, VL128
sqinch x0, vl128, mul #1
sqinch x0, vl256
SQINCH X0, VL256
sqinch x0, vl256, mul #1
sqinch x0, #14
SQINCH X0, #14
sqinch x0, #14, mul #1
sqinch x0, #15
SQINCH X0, #15
sqinch x0, #15, mul #1
sqinch x0, #16
SQINCH X0, #16
sqinch x0, #16, mul #1
sqinch x0, #17
SQINCH X0, #17
sqinch x0, #17, mul #1
sqinch x0, #18
SQINCH X0, #18
sqinch x0, #18, mul #1
sqinch x0, #19
SQINCH X0, #19
sqinch x0, #19, mul #1
sqinch x0, #20
SQINCH X0, #20
sqinch x0, #20, mul #1
sqinch x0, #21
SQINCH X0, #21
sqinch x0, #21, mul #1
sqinch x0, #22
SQINCH X0, #22
sqinch x0, #22, mul #1
sqinch x0, #23
SQINCH X0, #23
sqinch x0, #23, mul #1
sqinch x0, #24
SQINCH X0, #24
sqinch x0, #24, mul #1
sqinch x0, #25
SQINCH X0, #25
sqinch x0, #25, mul #1
sqinch x0, #26
SQINCH X0, #26
sqinch x0, #26, mul #1
sqinch x0, #27
SQINCH X0, #27
sqinch x0, #27, mul #1
sqinch x0, #28
SQINCH X0, #28
sqinch x0, #28, mul #1
sqinch x0, mul4
SQINCH X0, MUL4
sqinch x0, mul4, mul #1
sqinch x0, mul3
SQINCH X0, MUL3
sqinch x0, mul3, mul #1
sqinch x0
SQINCH X0
sqinch x0, all
sqinch x0, all, mul #1
sqinch x0, pow2, mul #8
SQINCH X0, POW2, MUL #8
sqinch x0, pow2, mul #9
SQINCH X0, POW2, MUL #9
sqinch x0, pow2, mul #10
SQINCH X0, POW2, MUL #10
sqinch x0, pow2, mul #16
SQINCH X0, POW2, MUL #16
sqinch x0, w0, pow2
SQINCH X0, W0, POW2
sqinch x0, w0, pow2, mul #1
sqinch x1, w1, pow2
SQINCH X1, W1, POW2
sqinch x1, w1, pow2, mul #1
sqinch xzr, wzr, pow2
SQINCH XZR, WZR, POW2
sqinch xzr, wzr, pow2, mul #1
sqinch x2, w2, pow2
SQINCH X2, W2, POW2
sqinch x2, w2, pow2, mul #1
sqinch x0, w0, vl1
SQINCH X0, W0, VL1
sqinch x0, w0, vl1, mul #1
sqinch x0, w0, vl2
SQINCH X0, W0, VL2
sqinch x0, w0, vl2, mul #1
sqinch x0, w0, vl3
SQINCH X0, W0, VL3
sqinch x0, w0, vl3, mul #1
sqinch x0, w0, vl4
SQINCH X0, W0, VL4
sqinch x0, w0, vl4, mul #1
sqinch x0, w0, vl5
SQINCH X0, W0, VL5
sqinch x0, w0, vl5, mul #1
sqinch x0, w0, vl6
SQINCH X0, W0, VL6
sqinch x0, w0, vl6, mul #1
sqinch x0, w0, vl7
SQINCH X0, W0, VL7
sqinch x0, w0, vl7, mul #1
sqinch x0, w0, vl8
SQINCH X0, W0, VL8
sqinch x0, w0, vl8, mul #1
sqinch x0, w0, vl16
SQINCH X0, W0, VL16
sqinch x0, w0, vl16, mul #1
sqinch x0, w0, vl32
SQINCH X0, W0, VL32
sqinch x0, w0, vl32, mul #1
sqinch x0, w0, vl64
SQINCH X0, W0, VL64
sqinch x0, w0, vl64, mul #1
sqinch x0, w0, vl128
SQINCH X0, W0, VL128
sqinch x0, w0, vl128, mul #1
sqinch x0, w0, vl256
SQINCH X0, W0, VL256
sqinch x0, w0, vl256, mul #1
sqinch x0, w0, #14
SQINCH X0, W0, #14
sqinch x0, w0, #14, mul #1
sqinch x0, w0, #15
SQINCH X0, W0, #15
sqinch x0, w0, #15, mul #1
sqinch x0, w0, #16
SQINCH X0, W0, #16
sqinch x0, w0, #16, mul #1
sqinch x0, w0, #17
SQINCH X0, W0, #17
sqinch x0, w0, #17, mul #1
sqinch x0, w0, #18
SQINCH X0, W0, #18
sqinch x0, w0, #18, mul #1
sqinch x0, w0, #19
SQINCH X0, W0, #19
sqinch x0, w0, #19, mul #1
sqinch x0, w0, #20
SQINCH X0, W0, #20
sqinch x0, w0, #20, mul #1
sqinch x0, w0, #21
SQINCH X0, W0, #21
sqinch x0, w0, #21, mul #1
sqinch x0, w0, #22
SQINCH X0, W0, #22
sqinch x0, w0, #22, mul #1
sqinch x0, w0, #23
SQINCH X0, W0, #23
sqinch x0, w0, #23, mul #1
sqinch x0, w0, #24
SQINCH X0, W0, #24
sqinch x0, w0, #24, mul #1
sqinch x0, w0, #25
SQINCH X0, W0, #25
sqinch x0, w0, #25, mul #1
sqinch x0, w0, #26
SQINCH X0, W0, #26
sqinch x0, w0, #26, mul #1
sqinch x0, w0, #27
SQINCH X0, W0, #27
sqinch x0, w0, #27, mul #1
sqinch x0, w0, #28
SQINCH X0, W0, #28
sqinch x0, w0, #28, mul #1
sqinch x0, w0, mul4
SQINCH X0, W0, MUL4
sqinch x0, w0, mul4, mul #1
sqinch x0, w0, mul3
SQINCH X0, W0, MUL3
sqinch x0, w0, mul3, mul #1
sqinch x0, w0
SQINCH X0, W0
sqinch x0, w0, all
sqinch x0, w0, all, mul #1
sqinch x0, w0, pow2, mul #8
SQINCH X0, W0, POW2, MUL #8
sqinch x0, w0, pow2, mul #9
SQINCH X0, W0, POW2, MUL #9
sqinch x0, w0, pow2, mul #10
SQINCH X0, W0, POW2, MUL #10
sqinch x0, w0, pow2, mul #16
SQINCH X0, W0, POW2, MUL #16
sqincp z0.h, p0
SQINCP Z0.H, P0
sqincp z1.h, p0
SQINCP Z1.H, P0
sqincp z31.h, p0
SQINCP Z31.H, P0
sqincp z0.h, p2
SQINCP Z0.H, P2
sqincp z0.h, p15
SQINCP Z0.H, P15
sqincp z0.s, p0
SQINCP Z0.S, P0
sqincp z1.s, p0
SQINCP Z1.S, P0
sqincp z31.s, p0
SQINCP Z31.S, P0
sqincp z0.s, p2
SQINCP Z0.S, P2
sqincp z0.s, p15
SQINCP Z0.S, P15
sqincp z0.d, p0
SQINCP Z0.D, P0
sqincp z1.d, p0
SQINCP Z1.D, P0
sqincp z31.d, p0
SQINCP Z31.D, P0
sqincp z0.d, p2
SQINCP Z0.D, P2
sqincp z0.d, p15
SQINCP Z0.D, P15
sqincp x0, p0.b
SQINCP X0, P0.B
sqincp x1, p0.b
SQINCP X1, P0.B
sqincp xzr, p0.b
SQINCP XZR, P0.B
sqincp x0, p2.b
SQINCP X0, P2.B
sqincp x0, p15.b
SQINCP X0, P15.B
sqincp x0, p0.h
SQINCP X0, P0.H
sqincp x1, p0.h
SQINCP X1, P0.H
sqincp xzr, p0.h
SQINCP XZR, P0.H
sqincp x0, p2.h
SQINCP X0, P2.H
sqincp x0, p15.h
SQINCP X0, P15.H
sqincp x0, p0.s
SQINCP X0, P0.S
sqincp x1, p0.s
SQINCP X1, P0.S
sqincp xzr, p0.s
SQINCP XZR, P0.S
sqincp x0, p2.s
SQINCP X0, P2.S
sqincp x0, p15.s
SQINCP X0, P15.S
sqincp x0, p0.d
SQINCP X0, P0.D
sqincp x1, p0.d
SQINCP X1, P0.D
sqincp xzr, p0.d
SQINCP XZR, P0.D
sqincp x0, p2.d
SQINCP X0, P2.D
sqincp x0, p15.d
SQINCP X0, P15.D
sqincp x0, p0.b, w0
SQINCP X0, P0.B, W0
sqincp x1, p0.b, w1
SQINCP X1, P0.B, W1
sqincp xzr, p0.b, wzr
SQINCP XZR, P0.B, WZR
sqincp x0, p2.b, w0
SQINCP X0, P2.B, W0
sqincp x0, p15.b, w0
SQINCP X0, P15.B, W0
sqincp x3, p0.b, w3
SQINCP X3, P0.B, W3
sqincp x0, p0.h, w0
SQINCP X0, P0.H, W0
sqincp x1, p0.h, w1
SQINCP X1, P0.H, W1
sqincp xzr, p0.h, wzr
SQINCP XZR, P0.H, WZR
sqincp x0, p2.h, w0
SQINCP X0, P2.H, W0
sqincp x0, p15.h, w0
SQINCP X0, P15.H, W0
sqincp x3, p0.h, w3
SQINCP X3, P0.H, W3
sqincp x0, p0.s, w0
SQINCP X0, P0.S, W0
sqincp x1, p0.s, w1
SQINCP X1, P0.S, W1
sqincp xzr, p0.s, wzr
SQINCP XZR, P0.S, WZR
sqincp x0, p2.s, w0
SQINCP X0, P2.S, W0
sqincp x0, p15.s, w0
SQINCP X0, P15.S, W0
sqincp x3, p0.s, w3
SQINCP X3, P0.S, W3
sqincp x0, p0.d, w0
SQINCP X0, P0.D, W0
sqincp x1, p0.d, w1
SQINCP X1, P0.D, W1
sqincp xzr, p0.d, wzr
SQINCP XZR, P0.D, WZR
sqincp x0, p2.d, w0
SQINCP X0, P2.D, W0
sqincp x0, p15.d, w0
SQINCP X0, P15.D, W0
sqincp x3, p0.d, w3
SQINCP X3, P0.D, W3
sqincw z0.s, pow2
SQINCW Z0.S, POW2
sqincw z0.s, pow2, mul #1
sqincw z1.s, pow2
SQINCW Z1.S, POW2
sqincw z1.s, pow2, mul #1
sqincw z31.s, pow2
SQINCW Z31.S, POW2
sqincw z31.s, pow2, mul #1
sqincw z0.s, vl1
SQINCW Z0.S, VL1
sqincw z0.s, vl1, mul #1
sqincw z0.s, vl2
SQINCW Z0.S, VL2
sqincw z0.s, vl2, mul #1
sqincw z0.s, vl3
SQINCW Z0.S, VL3
sqincw z0.s, vl3, mul #1
sqincw z0.s, vl4
SQINCW Z0.S, VL4
sqincw z0.s, vl4, mul #1
sqincw z0.s, vl5
SQINCW Z0.S, VL5
sqincw z0.s, vl5, mul #1
sqincw z0.s, vl6
SQINCW Z0.S, VL6
sqincw z0.s, vl6, mul #1
sqincw z0.s, vl7
SQINCW Z0.S, VL7
sqincw z0.s, vl7, mul #1
sqincw z0.s, vl8
SQINCW Z0.S, VL8
sqincw z0.s, vl8, mul #1
sqincw z0.s, vl16
SQINCW Z0.S, VL16
sqincw z0.s, vl16, mul #1
sqincw z0.s, vl32
SQINCW Z0.S, VL32
sqincw z0.s, vl32, mul #1
sqincw z0.s, vl64
SQINCW Z0.S, VL64
sqincw z0.s, vl64, mul #1
sqincw z0.s, vl128
SQINCW Z0.S, VL128
sqincw z0.s, vl128, mul #1
sqincw z0.s, vl256
SQINCW Z0.S, VL256
sqincw z0.s, vl256, mul #1
sqincw z0.s, #14
SQINCW Z0.S, #14
sqincw z0.s, #14, mul #1
sqincw z0.s, #15
SQINCW Z0.S, #15
sqincw z0.s, #15, mul #1
sqincw z0.s, #16
SQINCW Z0.S, #16
sqincw z0.s, #16, mul #1
sqincw z0.s, #17
SQINCW Z0.S, #17
sqincw z0.s, #17, mul #1
sqincw z0.s, #18
SQINCW Z0.S, #18
sqincw z0.s, #18, mul #1
sqincw z0.s, #19
SQINCW Z0.S, #19
sqincw z0.s, #19, mul #1
sqincw z0.s, #20
SQINCW Z0.S, #20
sqincw z0.s, #20, mul #1
sqincw z0.s, #21
SQINCW Z0.S, #21
sqincw z0.s, #21, mul #1
sqincw z0.s, #22
SQINCW Z0.S, #22
sqincw z0.s, #22, mul #1
sqincw z0.s, #23
SQINCW Z0.S, #23
sqincw z0.s, #23, mul #1
sqincw z0.s, #24
SQINCW Z0.S, #24
sqincw z0.s, #24, mul #1
sqincw z0.s, #25
SQINCW Z0.S, #25
sqincw z0.s, #25, mul #1
sqincw z0.s, #26
SQINCW Z0.S, #26
sqincw z0.s, #26, mul #1
sqincw z0.s, #27
SQINCW Z0.S, #27
sqincw z0.s, #27, mul #1
sqincw z0.s, #28
SQINCW Z0.S, #28
sqincw z0.s, #28, mul #1
sqincw z0.s, mul4
SQINCW Z0.S, MUL4
sqincw z0.s, mul4, mul #1
sqincw z0.s, mul3
SQINCW Z0.S, MUL3
sqincw z0.s, mul3, mul #1
sqincw z0.s
SQINCW Z0.S
sqincw z0.s, all
sqincw z0.s, all, mul #1
sqincw z0.s, pow2, mul #8
SQINCW Z0.S, POW2, MUL #8
sqincw z0.s, pow2, mul #9
SQINCW Z0.S, POW2, MUL #9
sqincw z0.s, pow2, mul #10
SQINCW Z0.S, POW2, MUL #10
sqincw z0.s, pow2, mul #16
SQINCW Z0.S, POW2, MUL #16
sqincw x0, pow2
SQINCW X0, POW2
sqincw x0, pow2, mul #1
sqincw x1, pow2
SQINCW X1, POW2
sqincw x1, pow2, mul #1
sqincw xzr, pow2
SQINCW XZR, POW2
sqincw xzr, pow2, mul #1
sqincw x0, vl1
SQINCW X0, VL1
sqincw x0, vl1, mul #1
sqincw x0, vl2
SQINCW X0, VL2
sqincw x0, vl2, mul #1
sqincw x0, vl3
SQINCW X0, VL3
sqincw x0, vl3, mul #1
sqincw x0, vl4
SQINCW X0, VL4
sqincw x0, vl4, mul #1
sqincw x0, vl5
SQINCW X0, VL5
sqincw x0, vl5, mul #1
sqincw x0, vl6
SQINCW X0, VL6
sqincw x0, vl6, mul #1
sqincw x0, vl7
SQINCW X0, VL7
sqincw x0, vl7, mul #1
sqincw x0, vl8
SQINCW X0, VL8
sqincw x0, vl8, mul #1
sqincw x0, vl16
SQINCW X0, VL16
sqincw x0, vl16, mul #1
sqincw x0, vl32
SQINCW X0, VL32
sqincw x0, vl32, mul #1
sqincw x0, vl64
SQINCW X0, VL64
sqincw x0, vl64, mul #1
sqincw x0, vl128
SQINCW X0, VL128
sqincw x0, vl128, mul #1
sqincw x0, vl256
SQINCW X0, VL256
sqincw x0, vl256, mul #1
sqincw x0, #14
SQINCW X0, #14
sqincw x0, #14, mul #1
sqincw x0, #15
SQINCW X0, #15
sqincw x0, #15, mul #1
sqincw x0, #16
SQINCW X0, #16
sqincw x0, #16, mul #1
sqincw x0, #17
SQINCW X0, #17
sqincw x0, #17, mul #1
sqincw x0, #18
SQINCW X0, #18
sqincw x0, #18, mul #1
sqincw x0, #19
SQINCW X0, #19
sqincw x0, #19, mul #1
sqincw x0, #20
SQINCW X0, #20
sqincw x0, #20, mul #1
sqincw x0, #21
SQINCW X0, #21
sqincw x0, #21, mul #1
sqincw x0, #22
SQINCW X0, #22
sqincw x0, #22, mul #1
sqincw x0, #23
SQINCW X0, #23
sqincw x0, #23, mul #1
sqincw x0, #24
SQINCW X0, #24
sqincw x0, #24, mul #1
sqincw x0, #25
SQINCW X0, #25
sqincw x0, #25, mul #1
sqincw x0, #26
SQINCW X0, #26
sqincw x0, #26, mul #1
sqincw x0, #27
SQINCW X0, #27
sqincw x0, #27, mul #1
sqincw x0, #28
SQINCW X0, #28
sqincw x0, #28, mul #1
sqincw x0, mul4
SQINCW X0, MUL4
sqincw x0, mul4, mul #1
sqincw x0, mul3
SQINCW X0, MUL3
sqincw x0, mul3, mul #1
sqincw x0
SQINCW X0
sqincw x0, all
sqincw x0, all, mul #1
sqincw x0, pow2, mul #8
SQINCW X0, POW2, MUL #8
sqincw x0, pow2, mul #9
SQINCW X0, POW2, MUL #9
sqincw x0, pow2, mul #10
SQINCW X0, POW2, MUL #10
sqincw x0, pow2, mul #16
SQINCW X0, POW2, MUL #16
sqincw x0, w0, pow2
SQINCW X0, W0, POW2
sqincw x0, w0, pow2, mul #1
sqincw x1, w1, pow2
SQINCW X1, W1, POW2
sqincw x1, w1, pow2, mul #1
sqincw xzr, wzr, pow2
SQINCW XZR, WZR, POW2
sqincw xzr, wzr, pow2, mul #1
sqincw x2, w2, pow2
SQINCW X2, W2, POW2
sqincw x2, w2, pow2, mul #1
sqincw x0, w0, vl1
SQINCW X0, W0, VL1
sqincw x0, w0, vl1, mul #1
sqincw x0, w0, vl2
SQINCW X0, W0, VL2
sqincw x0, w0, vl2, mul #1
sqincw x0, w0, vl3
SQINCW X0, W0, VL3
sqincw x0, w0, vl3, mul #1
sqincw x0, w0, vl4
SQINCW X0, W0, VL4
sqincw x0, w0, vl4, mul #1
sqincw x0, w0, vl5
SQINCW X0, W0, VL5
sqincw x0, w0, vl5, mul #1
sqincw x0, w0, vl6
SQINCW X0, W0, VL6
sqincw x0, w0, vl6, mul #1
sqincw x0, w0, vl7
SQINCW X0, W0, VL7
sqincw x0, w0, vl7, mul #1
sqincw x0, w0, vl8
SQINCW X0, W0, VL8
sqincw x0, w0, vl8, mul #1
sqincw x0, w0, vl16
SQINCW X0, W0, VL16
sqincw x0, w0, vl16, mul #1
sqincw x0, w0, vl32
SQINCW X0, W0, VL32
sqincw x0, w0, vl32, mul #1
sqincw x0, w0, vl64
SQINCW X0, W0, VL64
sqincw x0, w0, vl64, mul #1
sqincw x0, w0, vl128
SQINCW X0, W0, VL128
sqincw x0, w0, vl128, mul #1
sqincw x0, w0, vl256
SQINCW X0, W0, VL256
sqincw x0, w0, vl256, mul #1
sqincw x0, w0, #14
SQINCW X0, W0, #14
sqincw x0, w0, #14, mul #1
sqincw x0, w0, #15
SQINCW X0, W0, #15
sqincw x0, w0, #15, mul #1
sqincw x0, w0, #16
SQINCW X0, W0, #16
sqincw x0, w0, #16, mul #1
sqincw x0, w0, #17
SQINCW X0, W0, #17
sqincw x0, w0, #17, mul #1
sqincw x0, w0, #18
SQINCW X0, W0, #18
sqincw x0, w0, #18, mul #1
sqincw x0, w0, #19
SQINCW X0, W0, #19
sqincw x0, w0, #19, mul #1
sqincw x0, w0, #20
SQINCW X0, W0, #20
sqincw x0, w0, #20, mul #1
sqincw x0, w0, #21
SQINCW X0, W0, #21
sqincw x0, w0, #21, mul #1
sqincw x0, w0, #22
SQINCW X0, W0, #22
sqincw x0, w0, #22, mul #1
sqincw x0, w0, #23
SQINCW X0, W0, #23
sqincw x0, w0, #23, mul #1
sqincw x0, w0, #24
SQINCW X0, W0, #24
sqincw x0, w0, #24, mul #1
sqincw x0, w0, #25
SQINCW X0, W0, #25
sqincw x0, w0, #25, mul #1
sqincw x0, w0, #26
SQINCW X0, W0, #26
sqincw x0, w0, #26, mul #1
sqincw x0, w0, #27
SQINCW X0, W0, #27
sqincw x0, w0, #27, mul #1
sqincw x0, w0, #28
SQINCW X0, W0, #28
sqincw x0, w0, #28, mul #1
sqincw x0, w0, mul4
SQINCW X0, W0, MUL4
sqincw x0, w0, mul4, mul #1
sqincw x0, w0, mul3
SQINCW X0, W0, MUL3
sqincw x0, w0, mul3, mul #1
sqincw x0, w0
SQINCW X0, W0
sqincw x0, w0, all
sqincw x0, w0, all, mul #1
sqincw x0, w0, pow2, mul #8
SQINCW X0, W0, POW2, MUL #8
sqincw x0, w0, pow2, mul #9
SQINCW X0, W0, POW2, MUL #9
sqincw x0, w0, pow2, mul #10
SQINCW X0, W0, POW2, MUL #10
sqincw x0, w0, pow2, mul #16
SQINCW X0, W0, POW2, MUL #16
sqsub z0.b, z0.b, z0.b
SQSUB Z0.B, Z0.B, Z0.B
sqsub z1.b, z0.b, z0.b
SQSUB Z1.B, Z0.B, Z0.B
sqsub z31.b, z0.b, z0.b
SQSUB Z31.B, Z0.B, Z0.B
sqsub z0.b, z2.b, z0.b
SQSUB Z0.B, Z2.B, Z0.B
sqsub z0.b, z31.b, z0.b
SQSUB Z0.B, Z31.B, Z0.B
sqsub z0.b, z0.b, z3.b
SQSUB Z0.B, Z0.B, Z3.B
sqsub z0.b, z0.b, z31.b
SQSUB Z0.B, Z0.B, Z31.B
sqsub z0.h, z0.h, z0.h
SQSUB Z0.H, Z0.H, Z0.H
sqsub z1.h, z0.h, z0.h
SQSUB Z1.H, Z0.H, Z0.H
sqsub z31.h, z0.h, z0.h
SQSUB Z31.H, Z0.H, Z0.H
sqsub z0.h, z2.h, z0.h
SQSUB Z0.H, Z2.H, Z0.H
sqsub z0.h, z31.h, z0.h
SQSUB Z0.H, Z31.H, Z0.H
sqsub z0.h, z0.h, z3.h
SQSUB Z0.H, Z0.H, Z3.H
sqsub z0.h, z0.h, z31.h
SQSUB Z0.H, Z0.H, Z31.H
sqsub z0.s, z0.s, z0.s
SQSUB Z0.S, Z0.S, Z0.S
sqsub z1.s, z0.s, z0.s
SQSUB Z1.S, Z0.S, Z0.S
sqsub z31.s, z0.s, z0.s
SQSUB Z31.S, Z0.S, Z0.S
sqsub z0.s, z2.s, z0.s
SQSUB Z0.S, Z2.S, Z0.S
sqsub z0.s, z31.s, z0.s
SQSUB Z0.S, Z31.S, Z0.S
sqsub z0.s, z0.s, z3.s
SQSUB Z0.S, Z0.S, Z3.S
sqsub z0.s, z0.s, z31.s
SQSUB Z0.S, Z0.S, Z31.S
sqsub z0.d, z0.d, z0.d
SQSUB Z0.D, Z0.D, Z0.D
sqsub z1.d, z0.d, z0.d
SQSUB Z1.D, Z0.D, Z0.D
sqsub z31.d, z0.d, z0.d
SQSUB Z31.D, Z0.D, Z0.D
sqsub z0.d, z2.d, z0.d
SQSUB Z0.D, Z2.D, Z0.D
sqsub z0.d, z31.d, z0.d
SQSUB Z0.D, Z31.D, Z0.D
sqsub z0.d, z0.d, z3.d
SQSUB Z0.D, Z0.D, Z3.D
sqsub z0.d, z0.d, z31.d
SQSUB Z0.D, Z0.D, Z31.D
sqsub z0.b, z0.b, #0
SQSUB Z0.B, Z0.B, #0
sqsub z0.b, z0.b, #0, lsl #0
sqsub z1.b, z1.b, #0
SQSUB Z1.B, Z1.B, #0
sqsub z1.b, z1.b, #0, lsl #0
sqsub z31.b, z31.b, #0
SQSUB Z31.B, Z31.B, #0
sqsub z31.b, z31.b, #0, lsl #0
sqsub z2.b, z2.b, #0
SQSUB Z2.B, Z2.B, #0
sqsub z2.b, z2.b, #0, lsl #0
sqsub z0.b, z0.b, #127
SQSUB Z0.B, Z0.B, #127
sqsub z0.b, z0.b, #127, lsl #0
sqsub z0.b, z0.b, #128
SQSUB Z0.B, Z0.B, #128
sqsub z0.b, z0.b, #128, lsl #0
sqsub z0.b, z0.b, #129
SQSUB Z0.B, Z0.B, #129
sqsub z0.b, z0.b, #129, lsl #0
sqsub z0.b, z0.b, #255
SQSUB Z0.B, Z0.B, #255
sqsub z0.b, z0.b, #255, lsl #0
sqsub z0.h, z0.h, #0
SQSUB Z0.H, Z0.H, #0
sqsub z0.h, z0.h, #0, lsl #0
sqsub z1.h, z1.h, #0
SQSUB Z1.H, Z1.H, #0
sqsub z1.h, z1.h, #0, lsl #0
sqsub z31.h, z31.h, #0
SQSUB Z31.H, Z31.H, #0
sqsub z31.h, z31.h, #0, lsl #0
sqsub z2.h, z2.h, #0
SQSUB Z2.H, Z2.H, #0
sqsub z2.h, z2.h, #0, lsl #0
sqsub z0.h, z0.h, #127
SQSUB Z0.H, Z0.H, #127
sqsub z0.h, z0.h, #127, lsl #0
sqsub z0.h, z0.h, #128
SQSUB Z0.H, Z0.H, #128
sqsub z0.h, z0.h, #128, lsl #0
sqsub z0.h, z0.h, #129
SQSUB Z0.H, Z0.H, #129
sqsub z0.h, z0.h, #129, lsl #0
sqsub z0.h, z0.h, #255
SQSUB Z0.H, Z0.H, #255
sqsub z0.h, z0.h, #255, lsl #0
sqsub z0.h, z0.h, #0, lsl #8
SQSUB Z0.H, Z0.H, #0, LSL #8
sqsub z0.h, z0.h, #32512
SQSUB Z0.H, Z0.H, #32512
sqsub z0.h, z0.h, #32512, lsl #0
sqsub z0.h, z0.h, #127, lsl #8
sqsub z0.h, z0.h, #32768
SQSUB Z0.H, Z0.H, #32768
sqsub z0.h, z0.h, #32768, lsl #0
sqsub z0.h, z0.h, #128, lsl #8
sqsub z0.h, z0.h, #33024
SQSUB Z0.H, Z0.H, #33024
sqsub z0.h, z0.h, #33024, lsl #0
sqsub z0.h, z0.h, #129, lsl #8
sqsub z0.h, z0.h, #65280
SQSUB Z0.H, Z0.H, #65280
sqsub z0.h, z0.h, #65280, lsl #0
sqsub z0.h, z0.h, #255, lsl #8
sqsub z0.s, z0.s, #0
SQSUB Z0.S, Z0.S, #0
sqsub z0.s, z0.s, #0, lsl #0
sqsub z1.s, z1.s, #0
SQSUB Z1.S, Z1.S, #0
sqsub z1.s, z1.s, #0, lsl #0
sqsub z31.s, z31.s, #0
SQSUB Z31.S, Z31.S, #0
sqsub z31.s, z31.s, #0, lsl #0
sqsub z2.s, z2.s, #0
SQSUB Z2.S, Z2.S, #0
sqsub z2.s, z2.s, #0, lsl #0
sqsub z0.s, z0.s, #127
SQSUB Z0.S, Z0.S, #127
sqsub z0.s, z0.s, #127, lsl #0
sqsub z0.s, z0.s, #128
SQSUB Z0.S, Z0.S, #128
sqsub z0.s, z0.s, #128, lsl #0
sqsub z0.s, z0.s, #129
SQSUB Z0.S, Z0.S, #129
sqsub z0.s, z0.s, #129, lsl #0
sqsub z0.s, z0.s, #255
SQSUB Z0.S, Z0.S, #255
sqsub z0.s, z0.s, #255, lsl #0
sqsub z0.s, z0.s, #0, lsl #8
SQSUB Z0.S, Z0.S, #0, LSL #8
sqsub z0.s, z0.s, #32512
SQSUB Z0.S, Z0.S, #32512
sqsub z0.s, z0.s, #32512, lsl #0
sqsub z0.s, z0.s, #127, lsl #8
sqsub z0.s, z0.s, #32768
SQSUB Z0.S, Z0.S, #32768
sqsub z0.s, z0.s, #32768, lsl #0
sqsub z0.s, z0.s, #128, lsl #8
sqsub z0.s, z0.s, #33024
SQSUB Z0.S, Z0.S, #33024
sqsub z0.s, z0.s, #33024, lsl #0
sqsub z0.s, z0.s, #129, lsl #8
sqsub z0.s, z0.s, #65280
SQSUB Z0.S, Z0.S, #65280
sqsub z0.s, z0.s, #65280, lsl #0
sqsub z0.s, z0.s, #255, lsl #8
sqsub z0.d, z0.d, #0
SQSUB Z0.D, Z0.D, #0
sqsub z0.d, z0.d, #0, lsl #0
sqsub z1.d, z1.d, #0
SQSUB Z1.D, Z1.D, #0
sqsub z1.d, z1.d, #0, lsl #0
sqsub z31.d, z31.d, #0
SQSUB Z31.D, Z31.D, #0
sqsub z31.d, z31.d, #0, lsl #0
sqsub z2.d, z2.d, #0
SQSUB Z2.D, Z2.D, #0
sqsub z2.d, z2.d, #0, lsl #0
sqsub z0.d, z0.d, #127
SQSUB Z0.D, Z0.D, #127
sqsub z0.d, z0.d, #127, lsl #0
sqsub z0.d, z0.d, #128
SQSUB Z0.D, Z0.D, #128
sqsub z0.d, z0.d, #128, lsl #0
sqsub z0.d, z0.d, #129
SQSUB Z0.D, Z0.D, #129
sqsub z0.d, z0.d, #129, lsl #0
sqsub z0.d, z0.d, #255
SQSUB Z0.D, Z0.D, #255
sqsub z0.d, z0.d, #255, lsl #0
sqsub z0.d, z0.d, #0, lsl #8
SQSUB Z0.D, Z0.D, #0, LSL #8
sqsub z0.d, z0.d, #32512
SQSUB Z0.D, Z0.D, #32512
sqsub z0.d, z0.d, #32512, lsl #0
sqsub z0.d, z0.d, #127, lsl #8
sqsub z0.d, z0.d, #32768
SQSUB Z0.D, Z0.D, #32768
sqsub z0.d, z0.d, #32768, lsl #0
sqsub z0.d, z0.d, #128, lsl #8
sqsub z0.d, z0.d, #33024
SQSUB Z0.D, Z0.D, #33024
sqsub z0.d, z0.d, #33024, lsl #0
sqsub z0.d, z0.d, #129, lsl #8
sqsub z0.d, z0.d, #65280
SQSUB Z0.D, Z0.D, #65280
sqsub z0.d, z0.d, #65280, lsl #0
sqsub z0.d, z0.d, #255, lsl #8
st1b z0.b, p0, [x0,x0]
st1b {z0.b}, p0, [x0,x0]
ST1B {Z0.B}, P0, [X0,X0]
st1b {z0.b}, p0, [x0,x0,lsl #0]
st1b z1.b, p0, [x0,x0]
st1b {z1.b}, p0, [x0,x0]
ST1B {Z1.B}, P0, [X0,X0]
st1b {z1.b}, p0, [x0,x0,lsl #0]
st1b z31.b, p0, [x0,x0]
st1b {z31.b}, p0, [x0,x0]
ST1B {Z31.B}, P0, [X0,X0]
st1b {z31.b}, p0, [x0,x0,lsl #0]
st1b {z0.b}, p2, [x0,x0]
ST1B {Z0.B}, P2, [X0,X0]
st1b {z0.b}, p2, [x0,x0,lsl #0]
st1b {z0.b}, p7, [x0,x0]
ST1B {Z0.B}, P7, [X0,X0]
st1b {z0.b}, p7, [x0,x0,lsl #0]
st1b {z0.b}, p0, [x3,x0]
ST1B {Z0.B}, P0, [X3,X0]
st1b {z0.b}, p0, [x3,x0,lsl #0]
st1b {z0.b}, p0, [sp,x0]
ST1B {Z0.B}, P0, [SP,X0]
st1b {z0.b}, p0, [sp,x0,lsl #0]
st1b {z0.b}, p0, [x0,x4]
ST1B {Z0.B}, P0, [X0,X4]
st1b {z0.b}, p0, [x0,x4,lsl #0]
st1b {z0.b}, p0, [x0,x30]
ST1B {Z0.B}, P0, [X0,X30]
st1b {z0.b}, p0, [x0,x30,lsl #0]
st1b z0.d, p0, [x0,z0.d,uxtw]
st1b {z0.d}, p0, [x0,z0.d,uxtw]
ST1B {Z0.D}, P0, [X0,Z0.D,UXTW]
st1b {z0.d}, p0, [x0,z0.d,uxtw #0]
st1b z1.d, p0, [x0,z0.d,uxtw]
st1b {z1.d}, p0, [x0,z0.d,uxtw]
ST1B {Z1.D}, P0, [X0,Z0.D,UXTW]
st1b {z1.d}, p0, [x0,z0.d,uxtw #0]
st1b z31.d, p0, [x0,z0.d,uxtw]
st1b {z31.d}, p0, [x0,z0.d,uxtw]
ST1B {Z31.D}, P0, [X0,Z0.D,UXTW]
st1b {z31.d}, p0, [x0,z0.d,uxtw #0]
st1b {z0.d}, p2, [x0,z0.d,uxtw]
ST1B {Z0.D}, P2, [X0,Z0.D,UXTW]
st1b {z0.d}, p2, [x0,z0.d,uxtw #0]
st1b {z0.d}, p7, [x0,z0.d,uxtw]
ST1B {Z0.D}, P7, [X0,Z0.D,UXTW]
st1b {z0.d}, p7, [x0,z0.d,uxtw #0]
st1b {z0.d}, p0, [x3,z0.d,uxtw]
ST1B {Z0.D}, P0, [X3,Z0.D,UXTW]
st1b {z0.d}, p0, [x3,z0.d,uxtw #0]
st1b {z0.d}, p0, [sp,z0.d,uxtw]
ST1B {Z0.D}, P0, [SP,Z0.D,UXTW]
st1b {z0.d}, p0, [sp,z0.d,uxtw #0]
st1b {z0.d}, p0, [x0,z4.d,uxtw]
ST1B {Z0.D}, P0, [X0,Z4.D,UXTW]
st1b {z0.d}, p0, [x0,z4.d,uxtw #0]
st1b {z0.d}, p0, [x0,z31.d,uxtw]
ST1B {Z0.D}, P0, [X0,Z31.D,UXTW]
st1b {z0.d}, p0, [x0,z31.d,uxtw #0]
st1b z0.d, p0, [x0,z0.d,sxtw]
st1b {z0.d}, p0, [x0,z0.d,sxtw]
ST1B {Z0.D}, P0, [X0,Z0.D,SXTW]
st1b {z0.d}, p0, [x0,z0.d,sxtw #0]
st1b z1.d, p0, [x0,z0.d,sxtw]
st1b {z1.d}, p0, [x0,z0.d,sxtw]
ST1B {Z1.D}, P0, [X0,Z0.D,SXTW]
st1b {z1.d}, p0, [x0,z0.d,sxtw #0]
st1b z31.d, p0, [x0,z0.d,sxtw]
st1b {z31.d}, p0, [x0,z0.d,sxtw]
ST1B {Z31.D}, P0, [X0,Z0.D,SXTW]
st1b {z31.d}, p0, [x0,z0.d,sxtw #0]
st1b {z0.d}, p2, [x0,z0.d,sxtw]
ST1B {Z0.D}, P2, [X0,Z0.D,SXTW]
st1b {z0.d}, p2, [x0,z0.d,sxtw #0]
st1b {z0.d}, p7, [x0,z0.d,sxtw]
ST1B {Z0.D}, P7, [X0,Z0.D,SXTW]
st1b {z0.d}, p7, [x0,z0.d,sxtw #0]
st1b {z0.d}, p0, [x3,z0.d,sxtw]
ST1B {Z0.D}, P0, [X3,Z0.D,SXTW]
st1b {z0.d}, p0, [x3,z0.d,sxtw #0]
st1b {z0.d}, p0, [sp,z0.d,sxtw]
ST1B {Z0.D}, P0, [SP,Z0.D,SXTW]
st1b {z0.d}, p0, [sp,z0.d,sxtw #0]
st1b {z0.d}, p0, [x0,z4.d,sxtw]
ST1B {Z0.D}, P0, [X0,Z4.D,SXTW]
st1b {z0.d}, p0, [x0,z4.d,sxtw #0]
st1b {z0.d}, p0, [x0,z31.d,sxtw]
ST1B {Z0.D}, P0, [X0,Z31.D,SXTW]
st1b {z0.d}, p0, [x0,z31.d,sxtw #0]
st1b z0.d, p0, [x0,z0.d]
st1b {z0.d}, p0, [x0,z0.d]
ST1B {Z0.D}, P0, [X0,Z0.D]
st1b {z0.d}, p0, [x0,z0.d,lsl #0]
st1b z1.d, p0, [x0,z0.d]
st1b {z1.d}, p0, [x0,z0.d]
ST1B {Z1.D}, P0, [X0,Z0.D]
st1b {z1.d}, p0, [x0,z0.d,lsl #0]
st1b z31.d, p0, [x0,z0.d]
st1b {z31.d}, p0, [x0,z0.d]
ST1B {Z31.D}, P0, [X0,Z0.D]
st1b {z31.d}, p0, [x0,z0.d,lsl #0]
st1b {z0.d}, p2, [x0,z0.d]
ST1B {Z0.D}, P2, [X0,Z0.D]
st1b {z0.d}, p2, [x0,z0.d,lsl #0]
st1b {z0.d}, p7, [x0,z0.d]
ST1B {Z0.D}, P7, [X0,Z0.D]
st1b {z0.d}, p7, [x0,z0.d,lsl #0]
st1b {z0.d}, p0, [x3,z0.d]
ST1B {Z0.D}, P0, [X3,Z0.D]
st1b {z0.d}, p0, [x3,z0.d,lsl #0]
st1b {z0.d}, p0, [sp,z0.d]
ST1B {Z0.D}, P0, [SP,Z0.D]
st1b {z0.d}, p0, [sp,z0.d,lsl #0]
st1b {z0.d}, p0, [x0,z4.d]
ST1B {Z0.D}, P0, [X0,Z4.D]
st1b {z0.d}, p0, [x0,z4.d,lsl #0]
st1b {z0.d}, p0, [x0,z31.d]
ST1B {Z0.D}, P0, [X0,Z31.D]
st1b {z0.d}, p0, [x0,z31.d,lsl #0]
st1b z0.h, p0, [x0,x0]
st1b {z0.h}, p0, [x0,x0]
ST1B {Z0.H}, P0, [X0,X0]
st1b {z0.h}, p0, [x0,x0,lsl #0]
st1b z1.h, p0, [x0,x0]
st1b {z1.h}, p0, [x0,x0]
ST1B {Z1.H}, P0, [X0,X0]
st1b {z1.h}, p0, [x0,x0,lsl #0]
st1b z31.h, p0, [x0,x0]
st1b {z31.h}, p0, [x0,x0]
ST1B {Z31.H}, P0, [X0,X0]
st1b {z31.h}, p0, [x0,x0,lsl #0]
st1b {z0.h}, p2, [x0,x0]
ST1B {Z0.H}, P2, [X0,X0]
st1b {z0.h}, p2, [x0,x0,lsl #0]
st1b {z0.h}, p7, [x0,x0]
ST1B {Z0.H}, P7, [X0,X0]
st1b {z0.h}, p7, [x0,x0,lsl #0]
st1b {z0.h}, p0, [x3,x0]
ST1B {Z0.H}, P0, [X3,X0]
st1b {z0.h}, p0, [x3,x0,lsl #0]
st1b {z0.h}, p0, [sp,x0]
ST1B {Z0.H}, P0, [SP,X0]
st1b {z0.h}, p0, [sp,x0,lsl #0]
st1b {z0.h}, p0, [x0,x4]
ST1B {Z0.H}, P0, [X0,X4]
st1b {z0.h}, p0, [x0,x4,lsl #0]
st1b {z0.h}, p0, [x0,x30]
ST1B {Z0.H}, P0, [X0,X30]
st1b {z0.h}, p0, [x0,x30,lsl #0]
st1b z0.s, p0, [x0,x0]
st1b {z0.s}, p0, [x0,x0]
ST1B {Z0.S}, P0, [X0,X0]
st1b {z0.s}, p0, [x0,x0,lsl #0]
st1b z1.s, p0, [x0,x0]
st1b {z1.s}, p0, [x0,x0]
ST1B {Z1.S}, P0, [X0,X0]
st1b {z1.s}, p0, [x0,x0,lsl #0]
st1b z31.s, p0, [x0,x0]
st1b {z31.s}, p0, [x0,x0]
ST1B {Z31.S}, P0, [X0,X0]
st1b {z31.s}, p0, [x0,x0,lsl #0]
st1b {z0.s}, p2, [x0,x0]
ST1B {Z0.S}, P2, [X0,X0]
st1b {z0.s}, p2, [x0,x0,lsl #0]
st1b {z0.s}, p7, [x0,x0]
ST1B {Z0.S}, P7, [X0,X0]
st1b {z0.s}, p7, [x0,x0,lsl #0]
st1b {z0.s}, p0, [x3,x0]
ST1B {Z0.S}, P0, [X3,X0]
st1b {z0.s}, p0, [x3,x0,lsl #0]
st1b {z0.s}, p0, [sp,x0]
ST1B {Z0.S}, P0, [SP,X0]
st1b {z0.s}, p0, [sp,x0,lsl #0]
st1b {z0.s}, p0, [x0,x4]
ST1B {Z0.S}, P0, [X0,X4]
st1b {z0.s}, p0, [x0,x4,lsl #0]
st1b {z0.s}, p0, [x0,x30]
ST1B {Z0.S}, P0, [X0,X30]
st1b {z0.s}, p0, [x0,x30,lsl #0]
st1b z0.s, p0, [x0,z0.s,uxtw]
st1b {z0.s}, p0, [x0,z0.s,uxtw]
ST1B {Z0.S}, P0, [X0,Z0.S,UXTW]
st1b {z0.s}, p0, [x0,z0.s,uxtw #0]
st1b z1.s, p0, [x0,z0.s,uxtw]
st1b {z1.s}, p0, [x0,z0.s,uxtw]
ST1B {Z1.S}, P0, [X0,Z0.S,UXTW]
st1b {z1.s}, p0, [x0,z0.s,uxtw #0]
st1b z31.s, p0, [x0,z0.s,uxtw]
st1b {z31.s}, p0, [x0,z0.s,uxtw]
ST1B {Z31.S}, P0, [X0,Z0.S,UXTW]
st1b {z31.s}, p0, [x0,z0.s,uxtw #0]
st1b {z0.s}, p2, [x0,z0.s,uxtw]
ST1B {Z0.S}, P2, [X0,Z0.S,UXTW]
st1b {z0.s}, p2, [x0,z0.s,uxtw #0]
st1b {z0.s}, p7, [x0,z0.s,uxtw]
ST1B {Z0.S}, P7, [X0,Z0.S,UXTW]
st1b {z0.s}, p7, [x0,z0.s,uxtw #0]
st1b {z0.s}, p0, [x3,z0.s,uxtw]
ST1B {Z0.S}, P0, [X3,Z0.S,UXTW]
st1b {z0.s}, p0, [x3,z0.s,uxtw #0]
st1b {z0.s}, p0, [sp,z0.s,uxtw]
ST1B {Z0.S}, P0, [SP,Z0.S,UXTW]
st1b {z0.s}, p0, [sp,z0.s,uxtw #0]
st1b {z0.s}, p0, [x0,z4.s,uxtw]
ST1B {Z0.S}, P0, [X0,Z4.S,UXTW]
st1b {z0.s}, p0, [x0,z4.s,uxtw #0]
st1b {z0.s}, p0, [x0,z31.s,uxtw]
ST1B {Z0.S}, P0, [X0,Z31.S,UXTW]
st1b {z0.s}, p0, [x0,z31.s,uxtw #0]
st1b z0.s, p0, [x0,z0.s,sxtw]
st1b {z0.s}, p0, [x0,z0.s,sxtw]
ST1B {Z0.S}, P0, [X0,Z0.S,SXTW]
st1b {z0.s}, p0, [x0,z0.s,sxtw #0]
st1b z1.s, p0, [x0,z0.s,sxtw]
st1b {z1.s}, p0, [x0,z0.s,sxtw]
ST1B {Z1.S}, P0, [X0,Z0.S,SXTW]
st1b {z1.s}, p0, [x0,z0.s,sxtw #0]
st1b z31.s, p0, [x0,z0.s,sxtw]
st1b {z31.s}, p0, [x0,z0.s,sxtw]
ST1B {Z31.S}, P0, [X0,Z0.S,SXTW]
st1b {z31.s}, p0, [x0,z0.s,sxtw #0]
st1b {z0.s}, p2, [x0,z0.s,sxtw]
ST1B {Z0.S}, P2, [X0,Z0.S,SXTW]
st1b {z0.s}, p2, [x0,z0.s,sxtw #0]
st1b {z0.s}, p7, [x0,z0.s,sxtw]
ST1B {Z0.S}, P7, [X0,Z0.S,SXTW]
st1b {z0.s}, p7, [x0,z0.s,sxtw #0]
st1b {z0.s}, p0, [x3,z0.s,sxtw]
ST1B {Z0.S}, P0, [X3,Z0.S,SXTW]
st1b {z0.s}, p0, [x3,z0.s,sxtw #0]
st1b {z0.s}, p0, [sp,z0.s,sxtw]
ST1B {Z0.S}, P0, [SP,Z0.S,SXTW]
st1b {z0.s}, p0, [sp,z0.s,sxtw #0]
st1b {z0.s}, p0, [x0,z4.s,sxtw]
ST1B {Z0.S}, P0, [X0,Z4.S,SXTW]
st1b {z0.s}, p0, [x0,z4.s,sxtw #0]
st1b {z0.s}, p0, [x0,z31.s,sxtw]
ST1B {Z0.S}, P0, [X0,Z31.S,SXTW]
st1b {z0.s}, p0, [x0,z31.s,sxtw #0]
st1b z0.d, p0, [x0,x0]
st1b {z0.d}, p0, [x0,x0]
ST1B {Z0.D}, P0, [X0,X0]
st1b {z0.d}, p0, [x0,x0,lsl #0]
st1b z1.d, p0, [x0,x0]
st1b {z1.d}, p0, [x0,x0]
ST1B {Z1.D}, P0, [X0,X0]
st1b {z1.d}, p0, [x0,x0,lsl #0]
st1b z31.d, p0, [x0,x0]
st1b {z31.d}, p0, [x0,x0]
ST1B {Z31.D}, P0, [X0,X0]
st1b {z31.d}, p0, [x0,x0,lsl #0]
st1b {z0.d}, p2, [x0,x0]
ST1B {Z0.D}, P2, [X0,X0]
st1b {z0.d}, p2, [x0,x0,lsl #0]
st1b {z0.d}, p7, [x0,x0]
ST1B {Z0.D}, P7, [X0,X0]
st1b {z0.d}, p7, [x0,x0,lsl #0]
st1b {z0.d}, p0, [x3,x0]
ST1B {Z0.D}, P0, [X3,X0]
st1b {z0.d}, p0, [x3,x0,lsl #0]
st1b {z0.d}, p0, [sp,x0]
ST1B {Z0.D}, P0, [SP,X0]
st1b {z0.d}, p0, [sp,x0,lsl #0]
st1b {z0.d}, p0, [x0,x4]
ST1B {Z0.D}, P0, [X0,X4]
st1b {z0.d}, p0, [x0,x4,lsl #0]
st1b {z0.d}, p0, [x0,x30]
ST1B {Z0.D}, P0, [X0,X30]
st1b {z0.d}, p0, [x0,x30,lsl #0]
st1b z0.b, p0, [x0,#0]
st1b {z0.b}, p0, [x0,#0]
ST1B {Z0.B}, P0, [X0,#0]
st1b {z0.b}, p0, [x0,#0,mul vl]
st1b {z0.b}, p0, [x0]
st1b z1.b, p0, [x0,#0]
st1b {z1.b}, p0, [x0,#0]
ST1B {Z1.B}, P0, [X0,#0]
st1b {z1.b}, p0, [x0,#0,mul vl]
st1b {z1.b}, p0, [x0]
st1b z31.b, p0, [x0,#0]
st1b {z31.b}, p0, [x0,#0]
ST1B {Z31.B}, P0, [X0,#0]
st1b {z31.b}, p0, [x0,#0,mul vl]
st1b {z31.b}, p0, [x0]
st1b {z0.b}, p2, [x0,#0]
ST1B {Z0.B}, P2, [X0,#0]
st1b {z0.b}, p2, [x0,#0,mul vl]
st1b {z0.b}, p2, [x0]
st1b {z0.b}, p7, [x0,#0]
ST1B {Z0.B}, P7, [X0,#0]
st1b {z0.b}, p7, [x0,#0,mul vl]
st1b {z0.b}, p7, [x0]
st1b {z0.b}, p0, [x3,#0]
ST1B {Z0.B}, P0, [X3,#0]
st1b {z0.b}, p0, [x3,#0,mul vl]
st1b {z0.b}, p0, [x3]
st1b {z0.b}, p0, [sp,#0]
ST1B {Z0.B}, P0, [SP,#0]
st1b {z0.b}, p0, [sp,#0,mul vl]
st1b {z0.b}, p0, [sp]
st1b {z0.b}, p0, [x0,#7,mul vl]
ST1B {Z0.B}, P0, [X0,#7,MUL VL]
st1b {z0.b}, p0, [x0,#-8,mul vl]
ST1B {Z0.B}, P0, [X0,#-8,MUL VL]
st1b {z0.b}, p0, [x0,#-7,mul vl]
ST1B {Z0.B}, P0, [X0,#-7,MUL VL]
st1b {z0.b}, p0, [x0,#-1,mul vl]
ST1B {Z0.B}, P0, [X0,#-1,MUL VL]
st1b z0.h, p0, [x0,#0]
st1b {z0.h}, p0, [x0,#0]
ST1B {Z0.H}, P0, [X0,#0]
st1b {z0.h}, p0, [x0,#0,mul vl]
st1b {z0.h}, p0, [x0]
st1b z1.h, p0, [x0,#0]
st1b {z1.h}, p0, [x0,#0]
ST1B {Z1.H}, P0, [X0,#0]
st1b {z1.h}, p0, [x0,#0,mul vl]
st1b {z1.h}, p0, [x0]
st1b z31.h, p0, [x0,#0]
st1b {z31.h}, p0, [x0,#0]
ST1B {Z31.H}, P0, [X0,#0]
st1b {z31.h}, p0, [x0,#0,mul vl]
st1b {z31.h}, p0, [x0]
st1b {z0.h}, p2, [x0,#0]
ST1B {Z0.H}, P2, [X0,#0]
st1b {z0.h}, p2, [x0,#0,mul vl]
st1b {z0.h}, p2, [x0]
st1b {z0.h}, p7, [x0,#0]
ST1B {Z0.H}, P7, [X0,#0]
st1b {z0.h}, p7, [x0,#0,mul vl]
st1b {z0.h}, p7, [x0]
st1b {z0.h}, p0, [x3,#0]
ST1B {Z0.H}, P0, [X3,#0]
st1b {z0.h}, p0, [x3,#0,mul vl]
st1b {z0.h}, p0, [x3]
st1b {z0.h}, p0, [sp,#0]
ST1B {Z0.H}, P0, [SP,#0]
st1b {z0.h}, p0, [sp,#0,mul vl]
st1b {z0.h}, p0, [sp]
st1b {z0.h}, p0, [x0,#7,mul vl]
ST1B {Z0.H}, P0, [X0,#7,MUL VL]
st1b {z0.h}, p0, [x0,#-8,mul vl]
ST1B {Z0.H}, P0, [X0,#-8,MUL VL]
st1b {z0.h}, p0, [x0,#-7,mul vl]
ST1B {Z0.H}, P0, [X0,#-7,MUL VL]
st1b {z0.h}, p0, [x0,#-1,mul vl]
ST1B {Z0.H}, P0, [X0,#-1,MUL VL]
st1b z0.d, p0, [z0.d,#0]
st1b {z0.d}, p0, [z0.d,#0]
ST1B {Z0.D}, P0, [Z0.D,#0]
st1b {z0.d}, p0, [z0.d]
st1b z1.d, p0, [z0.d,#0]
st1b {z1.d}, p0, [z0.d,#0]
ST1B {Z1.D}, P0, [Z0.D,#0]
st1b {z1.d}, p0, [z0.d]
st1b z31.d, p0, [z0.d,#0]
st1b {z31.d}, p0, [z0.d,#0]
ST1B {Z31.D}, P0, [Z0.D,#0]
st1b {z31.d}, p0, [z0.d]
st1b {z0.d}, p2, [z0.d,#0]
ST1B {Z0.D}, P2, [Z0.D,#0]
st1b {z0.d}, p2, [z0.d]
st1b {z0.d}, p7, [z0.d,#0]
ST1B {Z0.D}, P7, [Z0.D,#0]
st1b {z0.d}, p7, [z0.d]
st1b {z0.d}, p0, [z3.d,#0]
ST1B {Z0.D}, P0, [Z3.D,#0]
st1b {z0.d}, p0, [z3.d]
st1b {z0.d}, p0, [z31.d,#0]
ST1B {Z0.D}, P0, [Z31.D,#0]
st1b {z0.d}, p0, [z31.d]
st1b {z0.d}, p0, [z0.d,#15]
ST1B {Z0.D}, P0, [Z0.D,#15]
st1b {z0.d}, p0, [z0.d,#16]
ST1B {Z0.D}, P0, [Z0.D,#16]
st1b {z0.d}, p0, [z0.d,#17]
ST1B {Z0.D}, P0, [Z0.D,#17]
st1b {z0.d}, p0, [z0.d,#31]
ST1B {Z0.D}, P0, [Z0.D,#31]
st1b z0.s, p0, [x0,#0]
st1b {z0.s}, p0, [x0,#0]
ST1B {Z0.S}, P0, [X0,#0]
st1b {z0.s}, p0, [x0,#0,mul vl]
st1b {z0.s}, p0, [x0]
st1b z1.s, p0, [x0,#0]
st1b {z1.s}, p0, [x0,#0]
ST1B {Z1.S}, P0, [X0,#0]
st1b {z1.s}, p0, [x0,#0,mul vl]
st1b {z1.s}, p0, [x0]
st1b z31.s, p0, [x0,#0]
st1b {z31.s}, p0, [x0,#0]
ST1B {Z31.S}, P0, [X0,#0]
st1b {z31.s}, p0, [x0,#0,mul vl]
st1b {z31.s}, p0, [x0]
st1b {z0.s}, p2, [x0,#0]
ST1B {Z0.S}, P2, [X0,#0]
st1b {z0.s}, p2, [x0,#0,mul vl]
st1b {z0.s}, p2, [x0]
st1b {z0.s}, p7, [x0,#0]
ST1B {Z0.S}, P7, [X0,#0]
st1b {z0.s}, p7, [x0,#0,mul vl]
st1b {z0.s}, p7, [x0]
st1b {z0.s}, p0, [x3,#0]
ST1B {Z0.S}, P0, [X3,#0]
st1b {z0.s}, p0, [x3,#0,mul vl]
st1b {z0.s}, p0, [x3]
st1b {z0.s}, p0, [sp,#0]
ST1B {Z0.S}, P0, [SP,#0]
st1b {z0.s}, p0, [sp,#0,mul vl]
st1b {z0.s}, p0, [sp]
st1b {z0.s}, p0, [x0,#7,mul vl]
ST1B {Z0.S}, P0, [X0,#7,MUL VL]
st1b {z0.s}, p0, [x0,#-8,mul vl]
ST1B {Z0.S}, P0, [X0,#-8,MUL VL]
st1b {z0.s}, p0, [x0,#-7,mul vl]
ST1B {Z0.S}, P0, [X0,#-7,MUL VL]
st1b {z0.s}, p0, [x0,#-1,mul vl]
ST1B {Z0.S}, P0, [X0,#-1,MUL VL]
st1b z0.s, p0, [z0.s,#0]
st1b {z0.s}, p0, [z0.s,#0]
ST1B {Z0.S}, P0, [Z0.S,#0]
st1b {z0.s}, p0, [z0.s]
st1b z1.s, p0, [z0.s,#0]
st1b {z1.s}, p0, [z0.s,#0]
ST1B {Z1.S}, P0, [Z0.S,#0]
st1b {z1.s}, p0, [z0.s]
st1b z31.s, p0, [z0.s,#0]
st1b {z31.s}, p0, [z0.s,#0]
ST1B {Z31.S}, P0, [Z0.S,#0]
st1b {z31.s}, p0, [z0.s]
st1b {z0.s}, p2, [z0.s,#0]
ST1B {Z0.S}, P2, [Z0.S,#0]
st1b {z0.s}, p2, [z0.s]
st1b {z0.s}, p7, [z0.s,#0]
ST1B {Z0.S}, P7, [Z0.S,#0]
st1b {z0.s}, p7, [z0.s]
st1b {z0.s}, p0, [z3.s,#0]
ST1B {Z0.S}, P0, [Z3.S,#0]
st1b {z0.s}, p0, [z3.s]
st1b {z0.s}, p0, [z31.s,#0]
ST1B {Z0.S}, P0, [Z31.S,#0]
st1b {z0.s}, p0, [z31.s]
st1b {z0.s}, p0, [z0.s,#15]
ST1B {Z0.S}, P0, [Z0.S,#15]
st1b {z0.s}, p0, [z0.s,#16]
ST1B {Z0.S}, P0, [Z0.S,#16]
st1b {z0.s}, p0, [z0.s,#17]
ST1B {Z0.S}, P0, [Z0.S,#17]
st1b {z0.s}, p0, [z0.s,#31]
ST1B {Z0.S}, P0, [Z0.S,#31]
st1b z0.d, p0, [x0,#0]
st1b {z0.d}, p0, [x0,#0]
ST1B {Z0.D}, P0, [X0,#0]
st1b {z0.d}, p0, [x0,#0,mul vl]
st1b {z0.d}, p0, [x0]
st1b z1.d, p0, [x0,#0]
st1b {z1.d}, p0, [x0,#0]
ST1B {Z1.D}, P0, [X0,#0]
st1b {z1.d}, p0, [x0,#0,mul vl]
st1b {z1.d}, p0, [x0]
st1b z31.d, p0, [x0,#0]
st1b {z31.d}, p0, [x0,#0]
ST1B {Z31.D}, P0, [X0,#0]
st1b {z31.d}, p0, [x0,#0,mul vl]
st1b {z31.d}, p0, [x0]
st1b {z0.d}, p2, [x0,#0]
ST1B {Z0.D}, P2, [X0,#0]
st1b {z0.d}, p2, [x0,#0,mul vl]
st1b {z0.d}, p2, [x0]
st1b {z0.d}, p7, [x0,#0]
ST1B {Z0.D}, P7, [X0,#0]
st1b {z0.d}, p7, [x0,#0,mul vl]
st1b {z0.d}, p7, [x0]
st1b {z0.d}, p0, [x3,#0]
ST1B {Z0.D}, P0, [X3,#0]
st1b {z0.d}, p0, [x3,#0,mul vl]
st1b {z0.d}, p0, [x3]
st1b {z0.d}, p0, [sp,#0]
ST1B {Z0.D}, P0, [SP,#0]
st1b {z0.d}, p0, [sp,#0,mul vl]
st1b {z0.d}, p0, [sp]
st1b {z0.d}, p0, [x0,#7,mul vl]
ST1B {Z0.D}, P0, [X0,#7,MUL VL]
st1b {z0.d}, p0, [x0,#-8,mul vl]
ST1B {Z0.D}, P0, [X0,#-8,MUL VL]
st1b {z0.d}, p0, [x0,#-7,mul vl]
ST1B {Z0.D}, P0, [X0,#-7,MUL VL]
st1b {z0.d}, p0, [x0,#-1,mul vl]
ST1B {Z0.D}, P0, [X0,#-1,MUL VL]
st1d z0.d, p0, [x0,z0.d,uxtw]
st1d {z0.d}, p0, [x0,z0.d,uxtw]
ST1D {Z0.D}, P0, [X0,Z0.D,UXTW]
st1d {z0.d}, p0, [x0,z0.d,uxtw #0]
st1d z1.d, p0, [x0,z0.d,uxtw]
st1d {z1.d}, p0, [x0,z0.d,uxtw]
ST1D {Z1.D}, P0, [X0,Z0.D,UXTW]
st1d {z1.d}, p0, [x0,z0.d,uxtw #0]
st1d z31.d, p0, [x0,z0.d,uxtw]
st1d {z31.d}, p0, [x0,z0.d,uxtw]
ST1D {Z31.D}, P0, [X0,Z0.D,UXTW]
st1d {z31.d}, p0, [x0,z0.d,uxtw #0]
st1d {z0.d}, p2, [x0,z0.d,uxtw]
ST1D {Z0.D}, P2, [X0,Z0.D,UXTW]
st1d {z0.d}, p2, [x0,z0.d,uxtw #0]
st1d {z0.d}, p7, [x0,z0.d,uxtw]
ST1D {Z0.D}, P7, [X0,Z0.D,UXTW]
st1d {z0.d}, p7, [x0,z0.d,uxtw #0]
st1d {z0.d}, p0, [x3,z0.d,uxtw]
ST1D {Z0.D}, P0, [X3,Z0.D,UXTW]
st1d {z0.d}, p0, [x3,z0.d,uxtw #0]
st1d {z0.d}, p0, [sp,z0.d,uxtw]
ST1D {Z0.D}, P0, [SP,Z0.D,UXTW]
st1d {z0.d}, p0, [sp,z0.d,uxtw #0]
st1d {z0.d}, p0, [x0,z4.d,uxtw]
ST1D {Z0.D}, P0, [X0,Z4.D,UXTW]
st1d {z0.d}, p0, [x0,z4.d,uxtw #0]
st1d {z0.d}, p0, [x0,z31.d,uxtw]
ST1D {Z0.D}, P0, [X0,Z31.D,UXTW]
st1d {z0.d}, p0, [x0,z31.d,uxtw #0]
st1d z0.d, p0, [x0,z0.d,sxtw]
st1d {z0.d}, p0, [x0,z0.d,sxtw]
ST1D {Z0.D}, P0, [X0,Z0.D,SXTW]
st1d {z0.d}, p0, [x0,z0.d,sxtw #0]
st1d z1.d, p0, [x0,z0.d,sxtw]
st1d {z1.d}, p0, [x0,z0.d,sxtw]
ST1D {Z1.D}, P0, [X0,Z0.D,SXTW]
st1d {z1.d}, p0, [x0,z0.d,sxtw #0]
st1d z31.d, p0, [x0,z0.d,sxtw]
st1d {z31.d}, p0, [x0,z0.d,sxtw]
ST1D {Z31.D}, P0, [X0,Z0.D,SXTW]
st1d {z31.d}, p0, [x0,z0.d,sxtw #0]
st1d {z0.d}, p2, [x0,z0.d,sxtw]
ST1D {Z0.D}, P2, [X0,Z0.D,SXTW]
st1d {z0.d}, p2, [x0,z0.d,sxtw #0]
st1d {z0.d}, p7, [x0,z0.d,sxtw]
ST1D {Z0.D}, P7, [X0,Z0.D,SXTW]
st1d {z0.d}, p7, [x0,z0.d,sxtw #0]
st1d {z0.d}, p0, [x3,z0.d,sxtw]
ST1D {Z0.D}, P0, [X3,Z0.D,SXTW]
st1d {z0.d}, p0, [x3,z0.d,sxtw #0]
st1d {z0.d}, p0, [sp,z0.d,sxtw]
ST1D {Z0.D}, P0, [SP,Z0.D,SXTW]
st1d {z0.d}, p0, [sp,z0.d,sxtw #0]
st1d {z0.d}, p0, [x0,z4.d,sxtw]
ST1D {Z0.D}, P0, [X0,Z4.D,SXTW]
st1d {z0.d}, p0, [x0,z4.d,sxtw #0]
st1d {z0.d}, p0, [x0,z31.d,sxtw]
ST1D {Z0.D}, P0, [X0,Z31.D,SXTW]
st1d {z0.d}, p0, [x0,z31.d,sxtw #0]
st1d z0.d, p0, [x0,z0.d]
st1d {z0.d}, p0, [x0,z0.d]
ST1D {Z0.D}, P0, [X0,Z0.D]
st1d {z0.d}, p0, [x0,z0.d,lsl #0]
st1d z1.d, p0, [x0,z0.d]
st1d {z1.d}, p0, [x0,z0.d]
ST1D {Z1.D}, P0, [X0,Z0.D]
st1d {z1.d}, p0, [x0,z0.d,lsl #0]
st1d z31.d, p0, [x0,z0.d]
st1d {z31.d}, p0, [x0,z0.d]
ST1D {Z31.D}, P0, [X0,Z0.D]
st1d {z31.d}, p0, [x0,z0.d,lsl #0]
st1d {z0.d}, p2, [x0,z0.d]
ST1D {Z0.D}, P2, [X0,Z0.D]
st1d {z0.d}, p2, [x0,z0.d,lsl #0]
st1d {z0.d}, p7, [x0,z0.d]
ST1D {Z0.D}, P7, [X0,Z0.D]
st1d {z0.d}, p7, [x0,z0.d,lsl #0]
st1d {z0.d}, p0, [x3,z0.d]
ST1D {Z0.D}, P0, [X3,Z0.D]
st1d {z0.d}, p0, [x3,z0.d,lsl #0]
st1d {z0.d}, p0, [sp,z0.d]
ST1D {Z0.D}, P0, [SP,Z0.D]
st1d {z0.d}, p0, [sp,z0.d,lsl #0]
st1d {z0.d}, p0, [x0,z4.d]
ST1D {Z0.D}, P0, [X0,Z4.D]
st1d {z0.d}, p0, [x0,z4.d,lsl #0]
st1d {z0.d}, p0, [x0,z31.d]
ST1D {Z0.D}, P0, [X0,Z31.D]
st1d {z0.d}, p0, [x0,z31.d,lsl #0]
st1d z0.d, p0, [x0,z0.d,uxtw #3]
st1d {z0.d}, p0, [x0,z0.d,uxtw #3]
ST1D {Z0.D}, P0, [X0,Z0.D,UXTW #3]
st1d z1.d, p0, [x0,z0.d,uxtw #3]
st1d {z1.d}, p0, [x0,z0.d,uxtw #3]
ST1D {Z1.D}, P0, [X0,Z0.D,UXTW #3]
st1d z31.d, p0, [x0,z0.d,uxtw #3]
st1d {z31.d}, p0, [x0,z0.d,uxtw #3]
ST1D {Z31.D}, P0, [X0,Z0.D,UXTW #3]
st1d {z0.d}, p2, [x0,z0.d,uxtw #3]
ST1D {Z0.D}, P2, [X0,Z0.D,UXTW #3]
st1d {z0.d}, p7, [x0,z0.d,uxtw #3]
ST1D {Z0.D}, P7, [X0,Z0.D,UXTW #3]
st1d {z0.d}, p0, [x3,z0.d,uxtw #3]
ST1D {Z0.D}, P0, [X3,Z0.D,UXTW #3]
st1d {z0.d}, p0, [sp,z0.d,uxtw #3]
ST1D {Z0.D}, P0, [SP,Z0.D,UXTW #3]
st1d {z0.d}, p0, [x0,z4.d,uxtw #3]
ST1D {Z0.D}, P0, [X0,Z4.D,UXTW #3]
st1d {z0.d}, p0, [x0,z31.d,uxtw #3]
ST1D {Z0.D}, P0, [X0,Z31.D,UXTW #3]
st1d z0.d, p0, [x0,z0.d,sxtw #3]
st1d {z0.d}, p0, [x0,z0.d,sxtw #3]
ST1D {Z0.D}, P0, [X0,Z0.D,SXTW #3]
st1d z1.d, p0, [x0,z0.d,sxtw #3]
st1d {z1.d}, p0, [x0,z0.d,sxtw #3]
ST1D {Z1.D}, P0, [X0,Z0.D,SXTW #3]
st1d z31.d, p0, [x0,z0.d,sxtw #3]
st1d {z31.d}, p0, [x0,z0.d,sxtw #3]
ST1D {Z31.D}, P0, [X0,Z0.D,SXTW #3]
st1d {z0.d}, p2, [x0,z0.d,sxtw #3]
ST1D {Z0.D}, P2, [X0,Z0.D,SXTW #3]
st1d {z0.d}, p7, [x0,z0.d,sxtw #3]
ST1D {Z0.D}, P7, [X0,Z0.D,SXTW #3]
st1d {z0.d}, p0, [x3,z0.d,sxtw #3]
ST1D {Z0.D}, P0, [X3,Z0.D,SXTW #3]
st1d {z0.d}, p0, [sp,z0.d,sxtw #3]
ST1D {Z0.D}, P0, [SP,Z0.D,SXTW #3]
st1d {z0.d}, p0, [x0,z4.d,sxtw #3]
ST1D {Z0.D}, P0, [X0,Z4.D,SXTW #3]
st1d {z0.d}, p0, [x0,z31.d,sxtw #3]
ST1D {Z0.D}, P0, [X0,Z31.D,SXTW #3]
st1d z0.d, p0, [x0,z0.d,lsl #3]
st1d {z0.d}, p0, [x0,z0.d,lsl #3]
ST1D {Z0.D}, P0, [X0,Z0.D,LSL #3]
st1d z1.d, p0, [x0,z0.d,lsl #3]
st1d {z1.d}, p0, [x0,z0.d,lsl #3]
ST1D {Z1.D}, P0, [X0,Z0.D,LSL #3]
st1d z31.d, p0, [x0,z0.d,lsl #3]
st1d {z31.d}, p0, [x0,z0.d,lsl #3]
ST1D {Z31.D}, P0, [X0,Z0.D,LSL #3]
st1d {z0.d}, p2, [x0,z0.d,lsl #3]
ST1D {Z0.D}, P2, [X0,Z0.D,LSL #3]
st1d {z0.d}, p7, [x0,z0.d,lsl #3]
ST1D {Z0.D}, P7, [X0,Z0.D,LSL #3]
st1d {z0.d}, p0, [x3,z0.d,lsl #3]
ST1D {Z0.D}, P0, [X3,Z0.D,LSL #3]
st1d {z0.d}, p0, [sp,z0.d,lsl #3]
ST1D {Z0.D}, P0, [SP,Z0.D,LSL #3]
st1d {z0.d}, p0, [x0,z4.d,lsl #3]
ST1D {Z0.D}, P0, [X0,Z4.D,LSL #3]
st1d {z0.d}, p0, [x0,z31.d,lsl #3]
ST1D {Z0.D}, P0, [X0,Z31.D,LSL #3]
st1d z0.d, p0, [x0,x0,lsl #3]
st1d {z0.d}, p0, [x0,x0,lsl #3]
ST1D {Z0.D}, P0, [X0,X0,LSL #3]
st1d z1.d, p0, [x0,x0,lsl #3]
st1d {z1.d}, p0, [x0,x0,lsl #3]
ST1D {Z1.D}, P0, [X0,X0,LSL #3]
st1d z31.d, p0, [x0,x0,lsl #3]
st1d {z31.d}, p0, [x0,x0,lsl #3]
ST1D {Z31.D}, P0, [X0,X0,LSL #3]
st1d {z0.d}, p2, [x0,x0,lsl #3]
ST1D {Z0.D}, P2, [X0,X0,LSL #3]
st1d {z0.d}, p7, [x0,x0,lsl #3]
ST1D {Z0.D}, P7, [X0,X0,LSL #3]
st1d {z0.d}, p0, [x3,x0,lsl #3]
ST1D {Z0.D}, P0, [X3,X0,LSL #3]
st1d {z0.d}, p0, [sp,x0,lsl #3]
ST1D {Z0.D}, P0, [SP,X0,LSL #3]
st1d {z0.d}, p0, [x0,x4,lsl #3]
ST1D {Z0.D}, P0, [X0,X4,LSL #3]
st1d {z0.d}, p0, [x0,x30,lsl #3]
ST1D {Z0.D}, P0, [X0,X30,LSL #3]
st1d z0.d, p0, [z0.d,#0]
st1d {z0.d}, p0, [z0.d,#0]
ST1D {Z0.D}, P0, [Z0.D,#0]
st1d {z0.d}, p0, [z0.d]
st1d z1.d, p0, [z0.d,#0]
st1d {z1.d}, p0, [z0.d,#0]
ST1D {Z1.D}, P0, [Z0.D,#0]
st1d {z1.d}, p0, [z0.d]
st1d z31.d, p0, [z0.d,#0]
st1d {z31.d}, p0, [z0.d,#0]
ST1D {Z31.D}, P0, [Z0.D,#0]
st1d {z31.d}, p0, [z0.d]
st1d {z0.d}, p2, [z0.d,#0]
ST1D {Z0.D}, P2, [Z0.D,#0]
st1d {z0.d}, p2, [z0.d]
st1d {z0.d}, p7, [z0.d,#0]
ST1D {Z0.D}, P7, [Z0.D,#0]
st1d {z0.d}, p7, [z0.d]
st1d {z0.d}, p0, [z3.d,#0]
ST1D {Z0.D}, P0, [Z3.D,#0]
st1d {z0.d}, p0, [z3.d]
st1d {z0.d}, p0, [z31.d,#0]
ST1D {Z0.D}, P0, [Z31.D,#0]
st1d {z0.d}, p0, [z31.d]
st1d {z0.d}, p0, [z0.d,#120]
ST1D {Z0.D}, P0, [Z0.D,#120]
st1d {z0.d}, p0, [z0.d,#128]
ST1D {Z0.D}, P0, [Z0.D,#128]
st1d {z0.d}, p0, [z0.d,#136]
ST1D {Z0.D}, P0, [Z0.D,#136]
st1d {z0.d}, p0, [z0.d,#248]
ST1D {Z0.D}, P0, [Z0.D,#248]
st1d z0.d, p0, [x0,#0]
st1d {z0.d}, p0, [x0,#0]
ST1D {Z0.D}, P0, [X0,#0]
st1d {z0.d}, p0, [x0,#0,mul vl]
st1d {z0.d}, p0, [x0]
st1d z1.d, p0, [x0,#0]
st1d {z1.d}, p0, [x0,#0]
ST1D {Z1.D}, P0, [X0,#0]
st1d {z1.d}, p0, [x0,#0,mul vl]
st1d {z1.d}, p0, [x0]
st1d z31.d, p0, [x0,#0]
st1d {z31.d}, p0, [x0,#0]
ST1D {Z31.D}, P0, [X0,#0]
st1d {z31.d}, p0, [x0,#0,mul vl]
st1d {z31.d}, p0, [x0]
st1d {z0.d}, p2, [x0,#0]
ST1D {Z0.D}, P2, [X0,#0]
st1d {z0.d}, p2, [x0,#0,mul vl]
st1d {z0.d}, p2, [x0]
st1d {z0.d}, p7, [x0,#0]
ST1D {Z0.D}, P7, [X0,#0]
st1d {z0.d}, p7, [x0,#0,mul vl]
st1d {z0.d}, p7, [x0]
st1d {z0.d}, p0, [x3,#0]
ST1D {Z0.D}, P0, [X3,#0]
st1d {z0.d}, p0, [x3,#0,mul vl]
st1d {z0.d}, p0, [x3]
st1d {z0.d}, p0, [sp,#0]
ST1D {Z0.D}, P0, [SP,#0]
st1d {z0.d}, p0, [sp,#0,mul vl]
st1d {z0.d}, p0, [sp]
st1d {z0.d}, p0, [x0,#7,mul vl]
ST1D {Z0.D}, P0, [X0,#7,MUL VL]
st1d {z0.d}, p0, [x0,#-8,mul vl]
ST1D {Z0.D}, P0, [X0,#-8,MUL VL]
st1d {z0.d}, p0, [x0,#-7,mul vl]
ST1D {Z0.D}, P0, [X0,#-7,MUL VL]
st1d {z0.d}, p0, [x0,#-1,mul vl]
ST1D {Z0.D}, P0, [X0,#-1,MUL VL]
st1h z0.d, p0, [x0,z0.d,uxtw]
st1h {z0.d}, p0, [x0,z0.d,uxtw]
ST1H {Z0.D}, P0, [X0,Z0.D,UXTW]
st1h {z0.d}, p0, [x0,z0.d,uxtw #0]
st1h z1.d, p0, [x0,z0.d,uxtw]
st1h {z1.d}, p0, [x0,z0.d,uxtw]
ST1H {Z1.D}, P0, [X0,Z0.D,UXTW]
st1h {z1.d}, p0, [x0,z0.d,uxtw #0]
st1h z31.d, p0, [x0,z0.d,uxtw]
st1h {z31.d}, p0, [x0,z0.d,uxtw]
ST1H {Z31.D}, P0, [X0,Z0.D,UXTW]
st1h {z31.d}, p0, [x0,z0.d,uxtw #0]
st1h {z0.d}, p2, [x0,z0.d,uxtw]
ST1H {Z0.D}, P2, [X0,Z0.D,UXTW]
st1h {z0.d}, p2, [x0,z0.d,uxtw #0]
st1h {z0.d}, p7, [x0,z0.d,uxtw]
ST1H {Z0.D}, P7, [X0,Z0.D,UXTW]
st1h {z0.d}, p7, [x0,z0.d,uxtw #0]
st1h {z0.d}, p0, [x3,z0.d,uxtw]
ST1H {Z0.D}, P0, [X3,Z0.D,UXTW]
st1h {z0.d}, p0, [x3,z0.d,uxtw #0]
st1h {z0.d}, p0, [sp,z0.d,uxtw]
ST1H {Z0.D}, P0, [SP,Z0.D,UXTW]
st1h {z0.d}, p0, [sp,z0.d,uxtw #0]
st1h {z0.d}, p0, [x0,z4.d,uxtw]
ST1H {Z0.D}, P0, [X0,Z4.D,UXTW]
st1h {z0.d}, p0, [x0,z4.d,uxtw #0]
st1h {z0.d}, p0, [x0,z31.d,uxtw]
ST1H {Z0.D}, P0, [X0,Z31.D,UXTW]
st1h {z0.d}, p0, [x0,z31.d,uxtw #0]
st1h z0.d, p0, [x0,z0.d,sxtw]
st1h {z0.d}, p0, [x0,z0.d,sxtw]
ST1H {Z0.D}, P0, [X0,Z0.D,SXTW]
st1h {z0.d}, p0, [x0,z0.d,sxtw #0]
st1h z1.d, p0, [x0,z0.d,sxtw]
st1h {z1.d}, p0, [x0,z0.d,sxtw]
ST1H {Z1.D}, P0, [X0,Z0.D,SXTW]
st1h {z1.d}, p0, [x0,z0.d,sxtw #0]
st1h z31.d, p0, [x0,z0.d,sxtw]
st1h {z31.d}, p0, [x0,z0.d,sxtw]
ST1H {Z31.D}, P0, [X0,Z0.D,SXTW]
st1h {z31.d}, p0, [x0,z0.d,sxtw #0]
st1h {z0.d}, p2, [x0,z0.d,sxtw]
ST1H {Z0.D}, P2, [X0,Z0.D,SXTW]
st1h {z0.d}, p2, [x0,z0.d,sxtw #0]
st1h {z0.d}, p7, [x0,z0.d,sxtw]
ST1H {Z0.D}, P7, [X0,Z0.D,SXTW]
st1h {z0.d}, p7, [x0,z0.d,sxtw #0]
st1h {z0.d}, p0, [x3,z0.d,sxtw]
ST1H {Z0.D}, P0, [X3,Z0.D,SXTW]
st1h {z0.d}, p0, [x3,z0.d,sxtw #0]
st1h {z0.d}, p0, [sp,z0.d,sxtw]
ST1H {Z0.D}, P0, [SP,Z0.D,SXTW]
st1h {z0.d}, p0, [sp,z0.d,sxtw #0]
st1h {z0.d}, p0, [x0,z4.d,sxtw]
ST1H {Z0.D}, P0, [X0,Z4.D,SXTW]
st1h {z0.d}, p0, [x0,z4.d,sxtw #0]
st1h {z0.d}, p0, [x0,z31.d,sxtw]
ST1H {Z0.D}, P0, [X0,Z31.D,SXTW]
st1h {z0.d}, p0, [x0,z31.d,sxtw #0]
st1h z0.d, p0, [x0,z0.d]
st1h {z0.d}, p0, [x0,z0.d]
ST1H {Z0.D}, P0, [X0,Z0.D]
st1h {z0.d}, p0, [x0,z0.d,lsl #0]
st1h z1.d, p0, [x0,z0.d]
st1h {z1.d}, p0, [x0,z0.d]
ST1H {Z1.D}, P0, [X0,Z0.D]
st1h {z1.d}, p0, [x0,z0.d,lsl #0]
st1h z31.d, p0, [x0,z0.d]
st1h {z31.d}, p0, [x0,z0.d]
ST1H {Z31.D}, P0, [X0,Z0.D]
st1h {z31.d}, p0, [x0,z0.d,lsl #0]
st1h {z0.d}, p2, [x0,z0.d]
ST1H {Z0.D}, P2, [X0,Z0.D]
st1h {z0.d}, p2, [x0,z0.d,lsl #0]
st1h {z0.d}, p7, [x0,z0.d]
ST1H {Z0.D}, P7, [X0,Z0.D]
st1h {z0.d}, p7, [x0,z0.d,lsl #0]
st1h {z0.d}, p0, [x3,z0.d]
ST1H {Z0.D}, P0, [X3,Z0.D]
st1h {z0.d}, p0, [x3,z0.d,lsl #0]
st1h {z0.d}, p0, [sp,z0.d]
ST1H {Z0.D}, P0, [SP,Z0.D]
st1h {z0.d}, p0, [sp,z0.d,lsl #0]
st1h {z0.d}, p0, [x0,z4.d]
ST1H {Z0.D}, P0, [X0,Z4.D]
st1h {z0.d}, p0, [x0,z4.d,lsl #0]
st1h {z0.d}, p0, [x0,z31.d]
ST1H {Z0.D}, P0, [X0,Z31.D]
st1h {z0.d}, p0, [x0,z31.d,lsl #0]
st1h z0.h, p0, [x0,x0,lsl #1]
st1h {z0.h}, p0, [x0,x0,lsl #1]
ST1H {Z0.H}, P0, [X0,X0,LSL #1]
st1h z1.h, p0, [x0,x0,lsl #1]
st1h {z1.h}, p0, [x0,x0,lsl #1]
ST1H {Z1.H}, P0, [X0,X0,LSL #1]
st1h z31.h, p0, [x0,x0,lsl #1]
st1h {z31.h}, p0, [x0,x0,lsl #1]
ST1H {Z31.H}, P0, [X0,X0,LSL #1]
st1h {z0.h}, p2, [x0,x0,lsl #1]
ST1H {Z0.H}, P2, [X0,X0,LSL #1]
st1h {z0.h}, p7, [x0,x0,lsl #1]
ST1H {Z0.H}, P7, [X0,X0,LSL #1]
st1h {z0.h}, p0, [x3,x0,lsl #1]
ST1H {Z0.H}, P0, [X3,X0,LSL #1]
st1h {z0.h}, p0, [sp,x0,lsl #1]
ST1H {Z0.H}, P0, [SP,X0,LSL #1]
st1h {z0.h}, p0, [x0,x4,lsl #1]
ST1H {Z0.H}, P0, [X0,X4,LSL #1]
st1h {z0.h}, p0, [x0,x30,lsl #1]
ST1H {Z0.H}, P0, [X0,X30,LSL #1]
st1h z0.d, p0, [x0,z0.d,uxtw #1]
st1h {z0.d}, p0, [x0,z0.d,uxtw #1]
ST1H {Z0.D}, P0, [X0,Z0.D,UXTW #1]
st1h z1.d, p0, [x0,z0.d,uxtw #1]
st1h {z1.d}, p0, [x0,z0.d,uxtw #1]
ST1H {Z1.D}, P0, [X0,Z0.D,UXTW #1]
st1h z31.d, p0, [x0,z0.d,uxtw #1]
st1h {z31.d}, p0, [x0,z0.d,uxtw #1]
ST1H {Z31.D}, P0, [X0,Z0.D,UXTW #1]
st1h {z0.d}, p2, [x0,z0.d,uxtw #1]
ST1H {Z0.D}, P2, [X0,Z0.D,UXTW #1]
st1h {z0.d}, p7, [x0,z0.d,uxtw #1]
ST1H {Z0.D}, P7, [X0,Z0.D,UXTW #1]
st1h {z0.d}, p0, [x3,z0.d,uxtw #1]
ST1H {Z0.D}, P0, [X3,Z0.D,UXTW #1]
st1h {z0.d}, p0, [sp,z0.d,uxtw #1]
ST1H {Z0.D}, P0, [SP,Z0.D,UXTW #1]
st1h {z0.d}, p0, [x0,z4.d,uxtw #1]
ST1H {Z0.D}, P0, [X0,Z4.D,UXTW #1]
st1h {z0.d}, p0, [x0,z31.d,uxtw #1]
ST1H {Z0.D}, P0, [X0,Z31.D,UXTW #1]
st1h z0.d, p0, [x0,z0.d,sxtw #1]
st1h {z0.d}, p0, [x0,z0.d,sxtw #1]
ST1H {Z0.D}, P0, [X0,Z0.D,SXTW #1]
st1h z1.d, p0, [x0,z0.d,sxtw #1]
st1h {z1.d}, p0, [x0,z0.d,sxtw #1]
ST1H {Z1.D}, P0, [X0,Z0.D,SXTW #1]
st1h z31.d, p0, [x0,z0.d,sxtw #1]
st1h {z31.d}, p0, [x0,z0.d,sxtw #1]
ST1H {Z31.D}, P0, [X0,Z0.D,SXTW #1]
st1h {z0.d}, p2, [x0,z0.d,sxtw #1]
ST1H {Z0.D}, P2, [X0,Z0.D,SXTW #1]
st1h {z0.d}, p7, [x0,z0.d,sxtw #1]
ST1H {Z0.D}, P7, [X0,Z0.D,SXTW #1]
st1h {z0.d}, p0, [x3,z0.d,sxtw #1]
ST1H {Z0.D}, P0, [X3,Z0.D,SXTW #1]
st1h {z0.d}, p0, [sp,z0.d,sxtw #1]
ST1H {Z0.D}, P0, [SP,Z0.D,SXTW #1]
st1h {z0.d}, p0, [x0,z4.d,sxtw #1]
ST1H {Z0.D}, P0, [X0,Z4.D,SXTW #1]
st1h {z0.d}, p0, [x0,z31.d,sxtw #1]
ST1H {Z0.D}, P0, [X0,Z31.D,SXTW #1]
st1h z0.d, p0, [x0,z0.d,lsl #1]
st1h {z0.d}, p0, [x0,z0.d,lsl #1]
ST1H {Z0.D}, P0, [X0,Z0.D,LSL #1]
st1h z1.d, p0, [x0,z0.d,lsl #1]
st1h {z1.d}, p0, [x0,z0.d,lsl #1]
ST1H {Z1.D}, P0, [X0,Z0.D,LSL #1]
st1h z31.d, p0, [x0,z0.d,lsl #1]
st1h {z31.d}, p0, [x0,z0.d,lsl #1]
ST1H {Z31.D}, P0, [X0,Z0.D,LSL #1]
st1h {z0.d}, p2, [x0,z0.d,lsl #1]
ST1H {Z0.D}, P2, [X0,Z0.D,LSL #1]
st1h {z0.d}, p7, [x0,z0.d,lsl #1]
ST1H {Z0.D}, P7, [X0,Z0.D,LSL #1]
st1h {z0.d}, p0, [x3,z0.d,lsl #1]
ST1H {Z0.D}, P0, [X3,Z0.D,LSL #1]
st1h {z0.d}, p0, [sp,z0.d,lsl #1]
ST1H {Z0.D}, P0, [SP,Z0.D,LSL #1]
st1h {z0.d}, p0, [x0,z4.d,lsl #1]
ST1H {Z0.D}, P0, [X0,Z4.D,LSL #1]
st1h {z0.d}, p0, [x0,z31.d,lsl #1]
ST1H {Z0.D}, P0, [X0,Z31.D,LSL #1]
st1h z0.s, p0, [x0,x0,lsl #1]
st1h {z0.s}, p0, [x0,x0,lsl #1]
ST1H {Z0.S}, P0, [X0,X0,LSL #1]
st1h z1.s, p0, [x0,x0,lsl #1]
st1h {z1.s}, p0, [x0,x0,lsl #1]
ST1H {Z1.S}, P0, [X0,X0,LSL #1]
st1h z31.s, p0, [x0,x0,lsl #1]
st1h {z31.s}, p0, [x0,x0,lsl #1]
ST1H {Z31.S}, P0, [X0,X0,LSL #1]
st1h {z0.s}, p2, [x0,x0,lsl #1]
ST1H {Z0.S}, P2, [X0,X0,LSL #1]
st1h {z0.s}, p7, [x0,x0,lsl #1]
ST1H {Z0.S}, P7, [X0,X0,LSL #1]
st1h {z0.s}, p0, [x3,x0,lsl #1]
ST1H {Z0.S}, P0, [X3,X0,LSL #1]
st1h {z0.s}, p0, [sp,x0,lsl #1]
ST1H {Z0.S}, P0, [SP,X0,LSL #1]
st1h {z0.s}, p0, [x0,x4,lsl #1]
ST1H {Z0.S}, P0, [X0,X4,LSL #1]
st1h {z0.s}, p0, [x0,x30,lsl #1]
ST1H {Z0.S}, P0, [X0,X30,LSL #1]
st1h z0.s, p0, [x0,z0.s,uxtw]
st1h {z0.s}, p0, [x0,z0.s,uxtw]
ST1H {Z0.S}, P0, [X0,Z0.S,UXTW]
st1h {z0.s}, p0, [x0,z0.s,uxtw #0]
st1h z1.s, p0, [x0,z0.s,uxtw]
st1h {z1.s}, p0, [x0,z0.s,uxtw]
ST1H {Z1.S}, P0, [X0,Z0.S,UXTW]
st1h {z1.s}, p0, [x0,z0.s,uxtw #0]
st1h z31.s, p0, [x0,z0.s,uxtw]
st1h {z31.s}, p0, [x0,z0.s,uxtw]
ST1H {Z31.S}, P0, [X0,Z0.S,UXTW]
st1h {z31.s}, p0, [x0,z0.s,uxtw #0]
st1h {z0.s}, p2, [x0,z0.s,uxtw]
ST1H {Z0.S}, P2, [X0,Z0.S,UXTW]
st1h {z0.s}, p2, [x0,z0.s,uxtw #0]
st1h {z0.s}, p7, [x0,z0.s,uxtw]
ST1H {Z0.S}, P7, [X0,Z0.S,UXTW]
st1h {z0.s}, p7, [x0,z0.s,uxtw #0]
st1h {z0.s}, p0, [x3,z0.s,uxtw]
ST1H {Z0.S}, P0, [X3,Z0.S,UXTW]
st1h {z0.s}, p0, [x3,z0.s,uxtw #0]
st1h {z0.s}, p0, [sp,z0.s,uxtw]
ST1H {Z0.S}, P0, [SP,Z0.S,UXTW]
st1h {z0.s}, p0, [sp,z0.s,uxtw #0]
st1h {z0.s}, p0, [x0,z4.s,uxtw]
ST1H {Z0.S}, P0, [X0,Z4.S,UXTW]
st1h {z0.s}, p0, [x0,z4.s,uxtw #0]
st1h {z0.s}, p0, [x0,z31.s,uxtw]
ST1H {Z0.S}, P0, [X0,Z31.S,UXTW]
st1h {z0.s}, p0, [x0,z31.s,uxtw #0]
st1h z0.s, p0, [x0,z0.s,sxtw]
st1h {z0.s}, p0, [x0,z0.s,sxtw]
ST1H {Z0.S}, P0, [X0,Z0.S,SXTW]
st1h {z0.s}, p0, [x0,z0.s,sxtw #0]
st1h z1.s, p0, [x0,z0.s,sxtw]
st1h {z1.s}, p0, [x0,z0.s,sxtw]
ST1H {Z1.S}, P0, [X0,Z0.S,SXTW]
st1h {z1.s}, p0, [x0,z0.s,sxtw #0]
st1h z31.s, p0, [x0,z0.s,sxtw]
st1h {z31.s}, p0, [x0,z0.s,sxtw]
ST1H {Z31.S}, P0, [X0,Z0.S,SXTW]
st1h {z31.s}, p0, [x0,z0.s,sxtw #0]
st1h {z0.s}, p2, [x0,z0.s,sxtw]
ST1H {Z0.S}, P2, [X0,Z0.S,SXTW]
st1h {z0.s}, p2, [x0,z0.s,sxtw #0]
st1h {z0.s}, p7, [x0,z0.s,sxtw]
ST1H {Z0.S}, P7, [X0,Z0.S,SXTW]
st1h {z0.s}, p7, [x0,z0.s,sxtw #0]
st1h {z0.s}, p0, [x3,z0.s,sxtw]
ST1H {Z0.S}, P0, [X3,Z0.S,SXTW]
st1h {z0.s}, p0, [x3,z0.s,sxtw #0]
st1h {z0.s}, p0, [sp,z0.s,sxtw]
ST1H {Z0.S}, P0, [SP,Z0.S,SXTW]
st1h {z0.s}, p0, [sp,z0.s,sxtw #0]
st1h {z0.s}, p0, [x0,z4.s,sxtw]
ST1H {Z0.S}, P0, [X0,Z4.S,SXTW]
st1h {z0.s}, p0, [x0,z4.s,sxtw #0]
st1h {z0.s}, p0, [x0,z31.s,sxtw]
ST1H {Z0.S}, P0, [X0,Z31.S,SXTW]
st1h {z0.s}, p0, [x0,z31.s,sxtw #0]
st1h z0.d, p0, [x0,x0,lsl #1]
st1h {z0.d}, p0, [x0,x0,lsl #1]
ST1H {Z0.D}, P0, [X0,X0,LSL #1]
st1h z1.d, p0, [x0,x0,lsl #1]
st1h {z1.d}, p0, [x0,x0,lsl #1]
ST1H {Z1.D}, P0, [X0,X0,LSL #1]
st1h z31.d, p0, [x0,x0,lsl #1]
st1h {z31.d}, p0, [x0,x0,lsl #1]
ST1H {Z31.D}, P0, [X0,X0,LSL #1]
st1h {z0.d}, p2, [x0,x0,lsl #1]
ST1H {Z0.D}, P2, [X0,X0,LSL #1]
st1h {z0.d}, p7, [x0,x0,lsl #1]
ST1H {Z0.D}, P7, [X0,X0,LSL #1]
st1h {z0.d}, p0, [x3,x0,lsl #1]
ST1H {Z0.D}, P0, [X3,X0,LSL #1]
st1h {z0.d}, p0, [sp,x0,lsl #1]
ST1H {Z0.D}, P0, [SP,X0,LSL #1]
st1h {z0.d}, p0, [x0,x4,lsl #1]
ST1H {Z0.D}, P0, [X0,X4,LSL #1]
st1h {z0.d}, p0, [x0,x30,lsl #1]
ST1H {Z0.D}, P0, [X0,X30,LSL #1]
st1h z0.s, p0, [x0,z0.s,uxtw #1]
st1h {z0.s}, p0, [x0,z0.s,uxtw #1]
ST1H {Z0.S}, P0, [X0,Z0.S,UXTW #1]
st1h z1.s, p0, [x0,z0.s,uxtw #1]
st1h {z1.s}, p0, [x0,z0.s,uxtw #1]
ST1H {Z1.S}, P0, [X0,Z0.S,UXTW #1]
st1h z31.s, p0, [x0,z0.s,uxtw #1]
st1h {z31.s}, p0, [x0,z0.s,uxtw #1]
ST1H {Z31.S}, P0, [X0,Z0.S,UXTW #1]
st1h {z0.s}, p2, [x0,z0.s,uxtw #1]
ST1H {Z0.S}, P2, [X0,Z0.S,UXTW #1]
st1h {z0.s}, p7, [x0,z0.s,uxtw #1]
ST1H {Z0.S}, P7, [X0,Z0.S,UXTW #1]
st1h {z0.s}, p0, [x3,z0.s,uxtw #1]
ST1H {Z0.S}, P0, [X3,Z0.S,UXTW #1]
st1h {z0.s}, p0, [sp,z0.s,uxtw #1]
ST1H {Z0.S}, P0, [SP,Z0.S,UXTW #1]
st1h {z0.s}, p0, [x0,z4.s,uxtw #1]
ST1H {Z0.S}, P0, [X0,Z4.S,UXTW #1]
st1h {z0.s}, p0, [x0,z31.s,uxtw #1]
ST1H {Z0.S}, P0, [X0,Z31.S,UXTW #1]
st1h z0.s, p0, [x0,z0.s,sxtw #1]
st1h {z0.s}, p0, [x0,z0.s,sxtw #1]
ST1H {Z0.S}, P0, [X0,Z0.S,SXTW #1]
st1h z1.s, p0, [x0,z0.s,sxtw #1]
st1h {z1.s}, p0, [x0,z0.s,sxtw #1]
ST1H {Z1.S}, P0, [X0,Z0.S,SXTW #1]
st1h z31.s, p0, [x0,z0.s,sxtw #1]
st1h {z31.s}, p0, [x0,z0.s,sxtw #1]
ST1H {Z31.S}, P0, [X0,Z0.S,SXTW #1]
st1h {z0.s}, p2, [x0,z0.s,sxtw #1]
ST1H {Z0.S}, P2, [X0,Z0.S,SXTW #1]
st1h {z0.s}, p7, [x0,z0.s,sxtw #1]
ST1H {Z0.S}, P7, [X0,Z0.S,SXTW #1]
st1h {z0.s}, p0, [x3,z0.s,sxtw #1]
ST1H {Z0.S}, P0, [X3,Z0.S,SXTW #1]
st1h {z0.s}, p0, [sp,z0.s,sxtw #1]
ST1H {Z0.S}, P0, [SP,Z0.S,SXTW #1]
st1h {z0.s}, p0, [x0,z4.s,sxtw #1]
ST1H {Z0.S}, P0, [X0,Z4.S,SXTW #1]
st1h {z0.s}, p0, [x0,z31.s,sxtw #1]
ST1H {Z0.S}, P0, [X0,Z31.S,SXTW #1]
st1h z0.h, p0, [x0,#0]
st1h {z0.h}, p0, [x0,#0]
ST1H {Z0.H}, P0, [X0,#0]
st1h {z0.h}, p0, [x0,#0,mul vl]
st1h {z0.h}, p0, [x0]
st1h z1.h, p0, [x0,#0]
st1h {z1.h}, p0, [x0,#0]
ST1H {Z1.H}, P0, [X0,#0]
st1h {z1.h}, p0, [x0,#0,mul vl]
st1h {z1.h}, p0, [x0]
st1h z31.h, p0, [x0,#0]
st1h {z31.h}, p0, [x0,#0]
ST1H {Z31.H}, P0, [X0,#0]
st1h {z31.h}, p0, [x0,#0,mul vl]
st1h {z31.h}, p0, [x0]
st1h {z0.h}, p2, [x0,#0]
ST1H {Z0.H}, P2, [X0,#0]
st1h {z0.h}, p2, [x0,#0,mul vl]
st1h {z0.h}, p2, [x0]
st1h {z0.h}, p7, [x0,#0]
ST1H {Z0.H}, P7, [X0,#0]
st1h {z0.h}, p7, [x0,#0,mul vl]
st1h {z0.h}, p7, [x0]
st1h {z0.h}, p0, [x3,#0]
ST1H {Z0.H}, P0, [X3,#0]
st1h {z0.h}, p0, [x3,#0,mul vl]
st1h {z0.h}, p0, [x3]
st1h {z0.h}, p0, [sp,#0]
ST1H {Z0.H}, P0, [SP,#0]
st1h {z0.h}, p0, [sp,#0,mul vl]
st1h {z0.h}, p0, [sp]
st1h {z0.h}, p0, [x0,#7,mul vl]
ST1H {Z0.H}, P0, [X0,#7,MUL VL]
st1h {z0.h}, p0, [x0,#-8,mul vl]
ST1H {Z0.H}, P0, [X0,#-8,MUL VL]
st1h {z0.h}, p0, [x0,#-7,mul vl]
ST1H {Z0.H}, P0, [X0,#-7,MUL VL]
st1h {z0.h}, p0, [x0,#-1,mul vl]
ST1H {Z0.H}, P0, [X0,#-1,MUL VL]
st1h z0.d, p0, [z0.d,#0]
st1h {z0.d}, p0, [z0.d,#0]
ST1H {Z0.D}, P0, [Z0.D,#0]
st1h {z0.d}, p0, [z0.d]
st1h z1.d, p0, [z0.d,#0]
st1h {z1.d}, p0, [z0.d,#0]
ST1H {Z1.D}, P0, [Z0.D,#0]
st1h {z1.d}, p0, [z0.d]
st1h z31.d, p0, [z0.d,#0]
st1h {z31.d}, p0, [z0.d,#0]
ST1H {Z31.D}, P0, [Z0.D,#0]
st1h {z31.d}, p0, [z0.d]
st1h {z0.d}, p2, [z0.d,#0]
ST1H {Z0.D}, P2, [Z0.D,#0]
st1h {z0.d}, p2, [z0.d]
st1h {z0.d}, p7, [z0.d,#0]
ST1H {Z0.D}, P7, [Z0.D,#0]
st1h {z0.d}, p7, [z0.d]
st1h {z0.d}, p0, [z3.d,#0]
ST1H {Z0.D}, P0, [Z3.D,#0]
st1h {z0.d}, p0, [z3.d]
st1h {z0.d}, p0, [z31.d,#0]
ST1H {Z0.D}, P0, [Z31.D,#0]
st1h {z0.d}, p0, [z31.d]
st1h {z0.d}, p0, [z0.d,#30]
ST1H {Z0.D}, P0, [Z0.D,#30]
st1h {z0.d}, p0, [z0.d,#32]
ST1H {Z0.D}, P0, [Z0.D,#32]
st1h {z0.d}, p0, [z0.d,#34]
ST1H {Z0.D}, P0, [Z0.D,#34]
st1h {z0.d}, p0, [z0.d,#62]
ST1H {Z0.D}, P0, [Z0.D,#62]
st1h z0.s, p0, [x0,#0]
st1h {z0.s}, p0, [x0,#0]
ST1H {Z0.S}, P0, [X0,#0]
st1h {z0.s}, p0, [x0,#0,mul vl]
st1h {z0.s}, p0, [x0]
st1h z1.s, p0, [x0,#0]
st1h {z1.s}, p0, [x0,#0]
ST1H {Z1.S}, P0, [X0,#0]
st1h {z1.s}, p0, [x0,#0,mul vl]
st1h {z1.s}, p0, [x0]
st1h z31.s, p0, [x0,#0]
st1h {z31.s}, p0, [x0,#0]
ST1H {Z31.S}, P0, [X0,#0]
st1h {z31.s}, p0, [x0,#0,mul vl]
st1h {z31.s}, p0, [x0]
st1h {z0.s}, p2, [x0,#0]
ST1H {Z0.S}, P2, [X0,#0]
st1h {z0.s}, p2, [x0,#0,mul vl]
st1h {z0.s}, p2, [x0]
st1h {z0.s}, p7, [x0,#0]
ST1H {Z0.S}, P7, [X0,#0]
st1h {z0.s}, p7, [x0,#0,mul vl]
st1h {z0.s}, p7, [x0]
st1h {z0.s}, p0, [x3,#0]
ST1H {Z0.S}, P0, [X3,#0]
st1h {z0.s}, p0, [x3,#0,mul vl]
st1h {z0.s}, p0, [x3]
st1h {z0.s}, p0, [sp,#0]
ST1H {Z0.S}, P0, [SP,#0]
st1h {z0.s}, p0, [sp,#0,mul vl]
st1h {z0.s}, p0, [sp]
st1h {z0.s}, p0, [x0,#7,mul vl]
ST1H {Z0.S}, P0, [X0,#7,MUL VL]
st1h {z0.s}, p0, [x0,#-8,mul vl]
ST1H {Z0.S}, P0, [X0,#-8,MUL VL]
st1h {z0.s}, p0, [x0,#-7,mul vl]
ST1H {Z0.S}, P0, [X0,#-7,MUL VL]
st1h {z0.s}, p0, [x0,#-1,mul vl]
ST1H {Z0.S}, P0, [X0,#-1,MUL VL]
st1h z0.s, p0, [z0.s,#0]
st1h {z0.s}, p0, [z0.s,#0]
ST1H {Z0.S}, P0, [Z0.S,#0]
st1h {z0.s}, p0, [z0.s]
st1h z1.s, p0, [z0.s,#0]
st1h {z1.s}, p0, [z0.s,#0]
ST1H {Z1.S}, P0, [Z0.S,#0]
st1h {z1.s}, p0, [z0.s]
st1h z31.s, p0, [z0.s,#0]
st1h {z31.s}, p0, [z0.s,#0]
ST1H {Z31.S}, P0, [Z0.S,#0]
st1h {z31.s}, p0, [z0.s]
st1h {z0.s}, p2, [z0.s,#0]
ST1H {Z0.S}, P2, [Z0.S,#0]
st1h {z0.s}, p2, [z0.s]
st1h {z0.s}, p7, [z0.s,#0]
ST1H {Z0.S}, P7, [Z0.S,#0]
st1h {z0.s}, p7, [z0.s]
st1h {z0.s}, p0, [z3.s,#0]
ST1H {Z0.S}, P0, [Z3.S,#0]
st1h {z0.s}, p0, [z3.s]
st1h {z0.s}, p0, [z31.s,#0]
ST1H {Z0.S}, P0, [Z31.S,#0]
st1h {z0.s}, p0, [z31.s]
st1h {z0.s}, p0, [z0.s,#30]
ST1H {Z0.S}, P0, [Z0.S,#30]
st1h {z0.s}, p0, [z0.s,#32]
ST1H {Z0.S}, P0, [Z0.S,#32]
st1h {z0.s}, p0, [z0.s,#34]
ST1H {Z0.S}, P0, [Z0.S,#34]
st1h {z0.s}, p0, [z0.s,#62]
ST1H {Z0.S}, P0, [Z0.S,#62]
st1h z0.d, p0, [x0,#0]
st1h {z0.d}, p0, [x0,#0]
ST1H {Z0.D}, P0, [X0,#0]
st1h {z0.d}, p0, [x0,#0,mul vl]
st1h {z0.d}, p0, [x0]
st1h z1.d, p0, [x0,#0]
st1h {z1.d}, p0, [x0,#0]
ST1H {Z1.D}, P0, [X0,#0]
st1h {z1.d}, p0, [x0,#0,mul vl]
st1h {z1.d}, p0, [x0]
st1h z31.d, p0, [x0,#0]
st1h {z31.d}, p0, [x0,#0]
ST1H {Z31.D}, P0, [X0,#0]
st1h {z31.d}, p0, [x0,#0,mul vl]
st1h {z31.d}, p0, [x0]
st1h {z0.d}, p2, [x0,#0]
ST1H {Z0.D}, P2, [X0,#0]
st1h {z0.d}, p2, [x0,#0,mul vl]
st1h {z0.d}, p2, [x0]
st1h {z0.d}, p7, [x0,#0]
ST1H {Z0.D}, P7, [X0,#0]
st1h {z0.d}, p7, [x0,#0,mul vl]
st1h {z0.d}, p7, [x0]
st1h {z0.d}, p0, [x3,#0]
ST1H {Z0.D}, P0, [X3,#0]
st1h {z0.d}, p0, [x3,#0,mul vl]
st1h {z0.d}, p0, [x3]
st1h {z0.d}, p0, [sp,#0]
ST1H {Z0.D}, P0, [SP,#0]
st1h {z0.d}, p0, [sp,#0,mul vl]
st1h {z0.d}, p0, [sp]
st1h {z0.d}, p0, [x0,#7,mul vl]
ST1H {Z0.D}, P0, [X0,#7,MUL VL]
st1h {z0.d}, p0, [x0,#-8,mul vl]
ST1H {Z0.D}, P0, [X0,#-8,MUL VL]
st1h {z0.d}, p0, [x0,#-7,mul vl]
ST1H {Z0.D}, P0, [X0,#-7,MUL VL]
st1h {z0.d}, p0, [x0,#-1,mul vl]
ST1H {Z0.D}, P0, [X0,#-1,MUL VL]
st1w z0.d, p0, [x0,z0.d,uxtw]
st1w {z0.d}, p0, [x0,z0.d,uxtw]
ST1W {Z0.D}, P0, [X0,Z0.D,UXTW]
st1w {z0.d}, p0, [x0,z0.d,uxtw #0]
st1w z1.d, p0, [x0,z0.d,uxtw]
st1w {z1.d}, p0, [x0,z0.d,uxtw]
ST1W {Z1.D}, P0, [X0,Z0.D,UXTW]
st1w {z1.d}, p0, [x0,z0.d,uxtw #0]
st1w z31.d, p0, [x0,z0.d,uxtw]
st1w {z31.d}, p0, [x0,z0.d,uxtw]
ST1W {Z31.D}, P0, [X0,Z0.D,UXTW]
st1w {z31.d}, p0, [x0,z0.d,uxtw #0]
st1w {z0.d}, p2, [x0,z0.d,uxtw]
ST1W {Z0.D}, P2, [X0,Z0.D,UXTW]
st1w {z0.d}, p2, [x0,z0.d,uxtw #0]
st1w {z0.d}, p7, [x0,z0.d,uxtw]
ST1W {Z0.D}, P7, [X0,Z0.D,UXTW]
st1w {z0.d}, p7, [x0,z0.d,uxtw #0]
st1w {z0.d}, p0, [x3,z0.d,uxtw]
ST1W {Z0.D}, P0, [X3,Z0.D,UXTW]
st1w {z0.d}, p0, [x3,z0.d,uxtw #0]
st1w {z0.d}, p0, [sp,z0.d,uxtw]
ST1W {Z0.D}, P0, [SP,Z0.D,UXTW]
st1w {z0.d}, p0, [sp,z0.d,uxtw #0]
st1w {z0.d}, p0, [x0,z4.d,uxtw]
ST1W {Z0.D}, P0, [X0,Z4.D,UXTW]
st1w {z0.d}, p0, [x0,z4.d,uxtw #0]
st1w {z0.d}, p0, [x0,z31.d,uxtw]
ST1W {Z0.D}, P0, [X0,Z31.D,UXTW]
st1w {z0.d}, p0, [x0,z31.d,uxtw #0]
st1w z0.d, p0, [x0,z0.d,sxtw]
st1w {z0.d}, p0, [x0,z0.d,sxtw]
ST1W {Z0.D}, P0, [X0,Z0.D,SXTW]
st1w {z0.d}, p0, [x0,z0.d,sxtw #0]
st1w z1.d, p0, [x0,z0.d,sxtw]
st1w {z1.d}, p0, [x0,z0.d,sxtw]
ST1W {Z1.D}, P0, [X0,Z0.D,SXTW]
st1w {z1.d}, p0, [x0,z0.d,sxtw #0]
st1w z31.d, p0, [x0,z0.d,sxtw]
st1w {z31.d}, p0, [x0,z0.d,sxtw]
ST1W {Z31.D}, P0, [X0,Z0.D,SXTW]
st1w {z31.d}, p0, [x0,z0.d,sxtw #0]
st1w {z0.d}, p2, [x0,z0.d,sxtw]
ST1W {Z0.D}, P2, [X0,Z0.D,SXTW]
st1w {z0.d}, p2, [x0,z0.d,sxtw #0]
st1w {z0.d}, p7, [x0,z0.d,sxtw]
ST1W {Z0.D}, P7, [X0,Z0.D,SXTW]
st1w {z0.d}, p7, [x0,z0.d,sxtw #0]
st1w {z0.d}, p0, [x3,z0.d,sxtw]
ST1W {Z0.D}, P0, [X3,Z0.D,SXTW]
st1w {z0.d}, p0, [x3,z0.d,sxtw #0]
st1w {z0.d}, p0, [sp,z0.d,sxtw]
ST1W {Z0.D}, P0, [SP,Z0.D,SXTW]
st1w {z0.d}, p0, [sp,z0.d,sxtw #0]
st1w {z0.d}, p0, [x0,z4.d,sxtw]
ST1W {Z0.D}, P0, [X0,Z4.D,SXTW]
st1w {z0.d}, p0, [x0,z4.d,sxtw #0]
st1w {z0.d}, p0, [x0,z31.d,sxtw]
ST1W {Z0.D}, P0, [X0,Z31.D,SXTW]
st1w {z0.d}, p0, [x0,z31.d,sxtw #0]
st1w z0.d, p0, [x0,z0.d]
st1w {z0.d}, p0, [x0,z0.d]
ST1W {Z0.D}, P0, [X0,Z0.D]
st1w {z0.d}, p0, [x0,z0.d,lsl #0]
st1w z1.d, p0, [x0,z0.d]
st1w {z1.d}, p0, [x0,z0.d]
ST1W {Z1.D}, P0, [X0,Z0.D]
st1w {z1.d}, p0, [x0,z0.d,lsl #0]
st1w z31.d, p0, [x0,z0.d]
st1w {z31.d}, p0, [x0,z0.d]
ST1W {Z31.D}, P0, [X0,Z0.D]
st1w {z31.d}, p0, [x0,z0.d,lsl #0]
st1w {z0.d}, p2, [x0,z0.d]
ST1W {Z0.D}, P2, [X0,Z0.D]
st1w {z0.d}, p2, [x0,z0.d,lsl #0]
st1w {z0.d}, p7, [x0,z0.d]
ST1W {Z0.D}, P7, [X0,Z0.D]
st1w {z0.d}, p7, [x0,z0.d,lsl #0]
st1w {z0.d}, p0, [x3,z0.d]
ST1W {Z0.D}, P0, [X3,Z0.D]
st1w {z0.d}, p0, [x3,z0.d,lsl #0]
st1w {z0.d}, p0, [sp,z0.d]
ST1W {Z0.D}, P0, [SP,Z0.D]
st1w {z0.d}, p0, [sp,z0.d,lsl #0]
st1w {z0.d}, p0, [x0,z4.d]
ST1W {Z0.D}, P0, [X0,Z4.D]
st1w {z0.d}, p0, [x0,z4.d,lsl #0]
st1w {z0.d}, p0, [x0,z31.d]
ST1W {Z0.D}, P0, [X0,Z31.D]
st1w {z0.d}, p0, [x0,z31.d,lsl #0]
st1w z0.d, p0, [x0,z0.d,uxtw #2]
st1w {z0.d}, p0, [x0,z0.d,uxtw #2]
ST1W {Z0.D}, P0, [X0,Z0.D,UXTW #2]
st1w z1.d, p0, [x0,z0.d,uxtw #2]
st1w {z1.d}, p0, [x0,z0.d,uxtw #2]
ST1W {Z1.D}, P0, [X0,Z0.D,UXTW #2]
st1w z31.d, p0, [x0,z0.d,uxtw #2]
st1w {z31.d}, p0, [x0,z0.d,uxtw #2]
ST1W {Z31.D}, P0, [X0,Z0.D,UXTW #2]
st1w {z0.d}, p2, [x0,z0.d,uxtw #2]
ST1W {Z0.D}, P2, [X0,Z0.D,UXTW #2]
st1w {z0.d}, p7, [x0,z0.d,uxtw #2]
ST1W {Z0.D}, P7, [X0,Z0.D,UXTW #2]
st1w {z0.d}, p0, [x3,z0.d,uxtw #2]
ST1W {Z0.D}, P0, [X3,Z0.D,UXTW #2]
st1w {z0.d}, p0, [sp,z0.d,uxtw #2]
ST1W {Z0.D}, P0, [SP,Z0.D,UXTW #2]
st1w {z0.d}, p0, [x0,z4.d,uxtw #2]
ST1W {Z0.D}, P0, [X0,Z4.D,UXTW #2]
st1w {z0.d}, p0, [x0,z31.d,uxtw #2]
ST1W {Z0.D}, P0, [X0,Z31.D,UXTW #2]
st1w z0.d, p0, [x0,z0.d,sxtw #2]
st1w {z0.d}, p0, [x0,z0.d,sxtw #2]
ST1W {Z0.D}, P0, [X0,Z0.D,SXTW #2]
st1w z1.d, p0, [x0,z0.d,sxtw #2]
st1w {z1.d}, p0, [x0,z0.d,sxtw #2]
ST1W {Z1.D}, P0, [X0,Z0.D,SXTW #2]
st1w z31.d, p0, [x0,z0.d,sxtw #2]
st1w {z31.d}, p0, [x0,z0.d,sxtw #2]
ST1W {Z31.D}, P0, [X0,Z0.D,SXTW #2]
st1w {z0.d}, p2, [x0,z0.d,sxtw #2]
ST1W {Z0.D}, P2, [X0,Z0.D,SXTW #2]
st1w {z0.d}, p7, [x0,z0.d,sxtw #2]
ST1W {Z0.D}, P7, [X0,Z0.D,SXTW #2]
st1w {z0.d}, p0, [x3,z0.d,sxtw #2]
ST1W {Z0.D}, P0, [X3,Z0.D,SXTW #2]
st1w {z0.d}, p0, [sp,z0.d,sxtw #2]
ST1W {Z0.D}, P0, [SP,Z0.D,SXTW #2]
st1w {z0.d}, p0, [x0,z4.d,sxtw #2]
ST1W {Z0.D}, P0, [X0,Z4.D,SXTW #2]
st1w {z0.d}, p0, [x0,z31.d,sxtw #2]
ST1W {Z0.D}, P0, [X0,Z31.D,SXTW #2]
st1w z0.d, p0, [x0,z0.d,lsl #2]
st1w {z0.d}, p0, [x0,z0.d,lsl #2]
ST1W {Z0.D}, P0, [X0,Z0.D,LSL #2]
st1w z1.d, p0, [x0,z0.d,lsl #2]
st1w {z1.d}, p0, [x0,z0.d,lsl #2]
ST1W {Z1.D}, P0, [X0,Z0.D,LSL #2]
st1w z31.d, p0, [x0,z0.d,lsl #2]
st1w {z31.d}, p0, [x0,z0.d,lsl #2]
ST1W {Z31.D}, P0, [X0,Z0.D,LSL #2]
st1w {z0.d}, p2, [x0,z0.d,lsl #2]
ST1W {Z0.D}, P2, [X0,Z0.D,LSL #2]
st1w {z0.d}, p7, [x0,z0.d,lsl #2]
ST1W {Z0.D}, P7, [X0,Z0.D,LSL #2]
st1w {z0.d}, p0, [x3,z0.d,lsl #2]
ST1W {Z0.D}, P0, [X3,Z0.D,LSL #2]
st1w {z0.d}, p0, [sp,z0.d,lsl #2]
ST1W {Z0.D}, P0, [SP,Z0.D,LSL #2]
st1w {z0.d}, p0, [x0,z4.d,lsl #2]
ST1W {Z0.D}, P0, [X0,Z4.D,LSL #2]
st1w {z0.d}, p0, [x0,z31.d,lsl #2]
ST1W {Z0.D}, P0, [X0,Z31.D,LSL #2]
st1w z0.s, p0, [x0,x0,lsl #2]
st1w {z0.s}, p0, [x0,x0,lsl #2]
ST1W {Z0.S}, P0, [X0,X0,LSL #2]
st1w z1.s, p0, [x0,x0,lsl #2]
st1w {z1.s}, p0, [x0,x0,lsl #2]
ST1W {Z1.S}, P0, [X0,X0,LSL #2]
st1w z31.s, p0, [x0,x0,lsl #2]
st1w {z31.s}, p0, [x0,x0,lsl #2]
ST1W {Z31.S}, P0, [X0,X0,LSL #2]
st1w {z0.s}, p2, [x0,x0,lsl #2]
ST1W {Z0.S}, P2, [X0,X0,LSL #2]
st1w {z0.s}, p7, [x0,x0,lsl #2]
ST1W {Z0.S}, P7, [X0,X0,LSL #2]
st1w {z0.s}, p0, [x3,x0,lsl #2]
ST1W {Z0.S}, P0, [X3,X0,LSL #2]
st1w {z0.s}, p0, [sp,x0,lsl #2]
ST1W {Z0.S}, P0, [SP,X0,LSL #2]
st1w {z0.s}, p0, [x0,x4,lsl #2]
ST1W {Z0.S}, P0, [X0,X4,LSL #2]
st1w {z0.s}, p0, [x0,x30,lsl #2]
ST1W {Z0.S}, P0, [X0,X30,LSL #2]
st1w z0.s, p0, [x0,z0.s,uxtw]
st1w {z0.s}, p0, [x0,z0.s,uxtw]
ST1W {Z0.S}, P0, [X0,Z0.S,UXTW]
st1w {z0.s}, p0, [x0,z0.s,uxtw #0]
st1w z1.s, p0, [x0,z0.s,uxtw]
st1w {z1.s}, p0, [x0,z0.s,uxtw]
ST1W {Z1.S}, P0, [X0,Z0.S,UXTW]
st1w {z1.s}, p0, [x0,z0.s,uxtw #0]
st1w z31.s, p0, [x0,z0.s,uxtw]
st1w {z31.s}, p0, [x0,z0.s,uxtw]
ST1W {Z31.S}, P0, [X0,Z0.S,UXTW]
st1w {z31.s}, p0, [x0,z0.s,uxtw #0]
st1w {z0.s}, p2, [x0,z0.s,uxtw]
ST1W {Z0.S}, P2, [X0,Z0.S,UXTW]
st1w {z0.s}, p2, [x0,z0.s,uxtw #0]
st1w {z0.s}, p7, [x0,z0.s,uxtw]
ST1W {Z0.S}, P7, [X0,Z0.S,UXTW]
st1w {z0.s}, p7, [x0,z0.s,uxtw #0]
st1w {z0.s}, p0, [x3,z0.s,uxtw]
ST1W {Z0.S}, P0, [X3,Z0.S,UXTW]
st1w {z0.s}, p0, [x3,z0.s,uxtw #0]
st1w {z0.s}, p0, [sp,z0.s,uxtw]
ST1W {Z0.S}, P0, [SP,Z0.S,UXTW]
st1w {z0.s}, p0, [sp,z0.s,uxtw #0]
st1w {z0.s}, p0, [x0,z4.s,uxtw]
ST1W {Z0.S}, P0, [X0,Z4.S,UXTW]
st1w {z0.s}, p0, [x0,z4.s,uxtw #0]
st1w {z0.s}, p0, [x0,z31.s,uxtw]
ST1W {Z0.S}, P0, [X0,Z31.S,UXTW]
st1w {z0.s}, p0, [x0,z31.s,uxtw #0]
st1w z0.s, p0, [x0,z0.s,sxtw]
st1w {z0.s}, p0, [x0,z0.s,sxtw]
ST1W {Z0.S}, P0, [X0,Z0.S,SXTW]
st1w {z0.s}, p0, [x0,z0.s,sxtw #0]
st1w z1.s, p0, [x0,z0.s,sxtw]
st1w {z1.s}, p0, [x0,z0.s,sxtw]
ST1W {Z1.S}, P0, [X0,Z0.S,SXTW]
st1w {z1.s}, p0, [x0,z0.s,sxtw #0]
st1w z31.s, p0, [x0,z0.s,sxtw]
st1w {z31.s}, p0, [x0,z0.s,sxtw]
ST1W {Z31.S}, P0, [X0,Z0.S,SXTW]
st1w {z31.s}, p0, [x0,z0.s,sxtw #0]
st1w {z0.s}, p2, [x0,z0.s,sxtw]
ST1W {Z0.S}, P2, [X0,Z0.S,SXTW]
st1w {z0.s}, p2, [x0,z0.s,sxtw #0]
st1w {z0.s}, p7, [x0,z0.s,sxtw]
ST1W {Z0.S}, P7, [X0,Z0.S,SXTW]
st1w {z0.s}, p7, [x0,z0.s,sxtw #0]
st1w {z0.s}, p0, [x3,z0.s,sxtw]
ST1W {Z0.S}, P0, [X3,Z0.S,SXTW]
st1w {z0.s}, p0, [x3,z0.s,sxtw #0]
st1w {z0.s}, p0, [sp,z0.s,sxtw]
ST1W {Z0.S}, P0, [SP,Z0.S,SXTW]
st1w {z0.s}, p0, [sp,z0.s,sxtw #0]
st1w {z0.s}, p0, [x0,z4.s,sxtw]
ST1W {Z0.S}, P0, [X0,Z4.S,SXTW]
st1w {z0.s}, p0, [x0,z4.s,sxtw #0]
st1w {z0.s}, p0, [x0,z31.s,sxtw]
ST1W {Z0.S}, P0, [X0,Z31.S,SXTW]
st1w {z0.s}, p0, [x0,z31.s,sxtw #0]
st1w z0.d, p0, [x0,x0,lsl #2]
st1w {z0.d}, p0, [x0,x0,lsl #2]
ST1W {Z0.D}, P0, [X0,X0,LSL #2]
st1w z1.d, p0, [x0,x0,lsl #2]
st1w {z1.d}, p0, [x0,x0,lsl #2]
ST1W {Z1.D}, P0, [X0,X0,LSL #2]
st1w z31.d, p0, [x0,x0,lsl #2]
st1w {z31.d}, p0, [x0,x0,lsl #2]
ST1W {Z31.D}, P0, [X0,X0,LSL #2]
st1w {z0.d}, p2, [x0,x0,lsl #2]
ST1W {Z0.D}, P2, [X0,X0,LSL #2]
st1w {z0.d}, p7, [x0,x0,lsl #2]
ST1W {Z0.D}, P7, [X0,X0,LSL #2]
st1w {z0.d}, p0, [x3,x0,lsl #2]
ST1W {Z0.D}, P0, [X3,X0,LSL #2]
st1w {z0.d}, p0, [sp,x0,lsl #2]
ST1W {Z0.D}, P0, [SP,X0,LSL #2]
st1w {z0.d}, p0, [x0,x4,lsl #2]
ST1W {Z0.D}, P0, [X0,X4,LSL #2]
st1w {z0.d}, p0, [x0,x30,lsl #2]
ST1W {Z0.D}, P0, [X0,X30,LSL #2]
st1w z0.s, p0, [x0,z0.s,uxtw #2]
st1w {z0.s}, p0, [x0,z0.s,uxtw #2]
ST1W {Z0.S}, P0, [X0,Z0.S,UXTW #2]
st1w z1.s, p0, [x0,z0.s,uxtw #2]
st1w {z1.s}, p0, [x0,z0.s,uxtw #2]
ST1W {Z1.S}, P0, [X0,Z0.S,UXTW #2]
st1w z31.s, p0, [x0,z0.s,uxtw #2]
st1w {z31.s}, p0, [x0,z0.s,uxtw #2]
ST1W {Z31.S}, P0, [X0,Z0.S,UXTW #2]
st1w {z0.s}, p2, [x0,z0.s,uxtw #2]
ST1W {Z0.S}, P2, [X0,Z0.S,UXTW #2]
st1w {z0.s}, p7, [x0,z0.s,uxtw #2]
ST1W {Z0.S}, P7, [X0,Z0.S,UXTW #2]
st1w {z0.s}, p0, [x3,z0.s,uxtw #2]
ST1W {Z0.S}, P0, [X3,Z0.S,UXTW #2]
st1w {z0.s}, p0, [sp,z0.s,uxtw #2]
ST1W {Z0.S}, P0, [SP,Z0.S,UXTW #2]
st1w {z0.s}, p0, [x0,z4.s,uxtw #2]
ST1W {Z0.S}, P0, [X0,Z4.S,UXTW #2]
st1w {z0.s}, p0, [x0,z31.s,uxtw #2]
ST1W {Z0.S}, P0, [X0,Z31.S,UXTW #2]
st1w z0.s, p0, [x0,z0.s,sxtw #2]
st1w {z0.s}, p0, [x0,z0.s,sxtw #2]
ST1W {Z0.S}, P0, [X0,Z0.S,SXTW #2]
st1w z1.s, p0, [x0,z0.s,sxtw #2]
st1w {z1.s}, p0, [x0,z0.s,sxtw #2]
ST1W {Z1.S}, P0, [X0,Z0.S,SXTW #2]
st1w z31.s, p0, [x0,z0.s,sxtw #2]
st1w {z31.s}, p0, [x0,z0.s,sxtw #2]
ST1W {Z31.S}, P0, [X0,Z0.S,SXTW #2]
st1w {z0.s}, p2, [x0,z0.s,sxtw #2]
ST1W {Z0.S}, P2, [X0,Z0.S,SXTW #2]
st1w {z0.s}, p7, [x0,z0.s,sxtw #2]
ST1W {Z0.S}, P7, [X0,Z0.S,SXTW #2]
st1w {z0.s}, p0, [x3,z0.s,sxtw #2]
ST1W {Z0.S}, P0, [X3,Z0.S,SXTW #2]
st1w {z0.s}, p0, [sp,z0.s,sxtw #2]
ST1W {Z0.S}, P0, [SP,Z0.S,SXTW #2]
st1w {z0.s}, p0, [x0,z4.s,sxtw #2]
ST1W {Z0.S}, P0, [X0,Z4.S,SXTW #2]
st1w {z0.s}, p0, [x0,z31.s,sxtw #2]
ST1W {Z0.S}, P0, [X0,Z31.S,SXTW #2]
st1w z0.d, p0, [z0.d,#0]
st1w {z0.d}, p0, [z0.d,#0]
ST1W {Z0.D}, P0, [Z0.D,#0]
st1w {z0.d}, p0, [z0.d]
st1w z1.d, p0, [z0.d,#0]
st1w {z1.d}, p0, [z0.d,#0]
ST1W {Z1.D}, P0, [Z0.D,#0]
st1w {z1.d}, p0, [z0.d]
st1w z31.d, p0, [z0.d,#0]
st1w {z31.d}, p0, [z0.d,#0]
ST1W {Z31.D}, P0, [Z0.D,#0]
st1w {z31.d}, p0, [z0.d]
st1w {z0.d}, p2, [z0.d,#0]
ST1W {Z0.D}, P2, [Z0.D,#0]
st1w {z0.d}, p2, [z0.d]
st1w {z0.d}, p7, [z0.d,#0]
ST1W {Z0.D}, P7, [Z0.D,#0]
st1w {z0.d}, p7, [z0.d]
st1w {z0.d}, p0, [z3.d,#0]
ST1W {Z0.D}, P0, [Z3.D,#0]
st1w {z0.d}, p0, [z3.d]
st1w {z0.d}, p0, [z31.d,#0]
ST1W {Z0.D}, P0, [Z31.D,#0]
st1w {z0.d}, p0, [z31.d]
st1w {z0.d}, p0, [z0.d,#60]
ST1W {Z0.D}, P0, [Z0.D,#60]
st1w {z0.d}, p0, [z0.d,#64]
ST1W {Z0.D}, P0, [Z0.D,#64]
st1w {z0.d}, p0, [z0.d,#68]
ST1W {Z0.D}, P0, [Z0.D,#68]
st1w {z0.d}, p0, [z0.d,#124]
ST1W {Z0.D}, P0, [Z0.D,#124]
st1w z0.s, p0, [x0,#0]
st1w {z0.s}, p0, [x0,#0]
ST1W {Z0.S}, P0, [X0,#0]
st1w {z0.s}, p0, [x0,#0,mul vl]
st1w {z0.s}, p0, [x0]
st1w z1.s, p0, [x0,#0]
st1w {z1.s}, p0, [x0,#0]
ST1W {Z1.S}, P0, [X0,#0]
st1w {z1.s}, p0, [x0,#0,mul vl]
st1w {z1.s}, p0, [x0]
st1w z31.s, p0, [x0,#0]
st1w {z31.s}, p0, [x0,#0]
ST1W {Z31.S}, P0, [X0,#0]
st1w {z31.s}, p0, [x0,#0,mul vl]
st1w {z31.s}, p0, [x0]
st1w {z0.s}, p2, [x0,#0]
ST1W {Z0.S}, P2, [X0,#0]
st1w {z0.s}, p2, [x0,#0,mul vl]
st1w {z0.s}, p2, [x0]
st1w {z0.s}, p7, [x0,#0]
ST1W {Z0.S}, P7, [X0,#0]
st1w {z0.s}, p7, [x0,#0,mul vl]
st1w {z0.s}, p7, [x0]
st1w {z0.s}, p0, [x3,#0]
ST1W {Z0.S}, P0, [X3,#0]
st1w {z0.s}, p0, [x3,#0,mul vl]
st1w {z0.s}, p0, [x3]
st1w {z0.s}, p0, [sp,#0]
ST1W {Z0.S}, P0, [SP,#0]
st1w {z0.s}, p0, [sp,#0,mul vl]
st1w {z0.s}, p0, [sp]
st1w {z0.s}, p0, [x0,#7,mul vl]
ST1W {Z0.S}, P0, [X0,#7,MUL VL]
st1w {z0.s}, p0, [x0,#-8,mul vl]
ST1W {Z0.S}, P0, [X0,#-8,MUL VL]
st1w {z0.s}, p0, [x0,#-7,mul vl]
ST1W {Z0.S}, P0, [X0,#-7,MUL VL]
st1w {z0.s}, p0, [x0,#-1,mul vl]
ST1W {Z0.S}, P0, [X0,#-1,MUL VL]
st1w z0.s, p0, [z0.s,#0]
st1w {z0.s}, p0, [z0.s,#0]
ST1W {Z0.S}, P0, [Z0.S,#0]
st1w {z0.s}, p0, [z0.s]
st1w z1.s, p0, [z0.s,#0]
st1w {z1.s}, p0, [z0.s,#0]
ST1W {Z1.S}, P0, [Z0.S,#0]
st1w {z1.s}, p0, [z0.s]
st1w z31.s, p0, [z0.s,#0]
st1w {z31.s}, p0, [z0.s,#0]
ST1W {Z31.S}, P0, [Z0.S,#0]
st1w {z31.s}, p0, [z0.s]
st1w {z0.s}, p2, [z0.s,#0]
ST1W {Z0.S}, P2, [Z0.S,#0]
st1w {z0.s}, p2, [z0.s]
st1w {z0.s}, p7, [z0.s,#0]
ST1W {Z0.S}, P7, [Z0.S,#0]
st1w {z0.s}, p7, [z0.s]
st1w {z0.s}, p0, [z3.s,#0]
ST1W {Z0.S}, P0, [Z3.S,#0]
st1w {z0.s}, p0, [z3.s]
st1w {z0.s}, p0, [z31.s,#0]
ST1W {Z0.S}, P0, [Z31.S,#0]
st1w {z0.s}, p0, [z31.s]
st1w {z0.s}, p0, [z0.s,#60]
ST1W {Z0.S}, P0, [Z0.S,#60]
st1w {z0.s}, p0, [z0.s,#64]
ST1W {Z0.S}, P0, [Z0.S,#64]
st1w {z0.s}, p0, [z0.s,#68]
ST1W {Z0.S}, P0, [Z0.S,#68]
st1w {z0.s}, p0, [z0.s,#124]
ST1W {Z0.S}, P0, [Z0.S,#124]
st1w z0.d, p0, [x0,#0]
st1w {z0.d}, p0, [x0,#0]
ST1W {Z0.D}, P0, [X0,#0]
st1w {z0.d}, p0, [x0,#0,mul vl]
st1w {z0.d}, p0, [x0]
st1w z1.d, p0, [x0,#0]
st1w {z1.d}, p0, [x0,#0]
ST1W {Z1.D}, P0, [X0,#0]
st1w {z1.d}, p0, [x0,#0,mul vl]
st1w {z1.d}, p0, [x0]
st1w z31.d, p0, [x0,#0]
st1w {z31.d}, p0, [x0,#0]
ST1W {Z31.D}, P0, [X0,#0]
st1w {z31.d}, p0, [x0,#0,mul vl]
st1w {z31.d}, p0, [x0]
st1w {z0.d}, p2, [x0,#0]
ST1W {Z0.D}, P2, [X0,#0]
st1w {z0.d}, p2, [x0,#0,mul vl]
st1w {z0.d}, p2, [x0]
st1w {z0.d}, p7, [x0,#0]
ST1W {Z0.D}, P7, [X0,#0]
st1w {z0.d}, p7, [x0,#0,mul vl]
st1w {z0.d}, p7, [x0]
st1w {z0.d}, p0, [x3,#0]
ST1W {Z0.D}, P0, [X3,#0]
st1w {z0.d}, p0, [x3,#0,mul vl]
st1w {z0.d}, p0, [x3]
st1w {z0.d}, p0, [sp,#0]
ST1W {Z0.D}, P0, [SP,#0]
st1w {z0.d}, p0, [sp,#0,mul vl]
st1w {z0.d}, p0, [sp]
st1w {z0.d}, p0, [x0,#7,mul vl]
ST1W {Z0.D}, P0, [X0,#7,MUL VL]
st1w {z0.d}, p0, [x0,#-8,mul vl]
ST1W {Z0.D}, P0, [X0,#-8,MUL VL]
st1w {z0.d}, p0, [x0,#-7,mul vl]
ST1W {Z0.D}, P0, [X0,#-7,MUL VL]
st1w {z0.d}, p0, [x0,#-1,mul vl]
ST1W {Z0.D}, P0, [X0,#-1,MUL VL]
st2b {z0.b, z1.b}, p0, [x0,x0]
ST2B {Z0.B, Z1.B}, P0, [X0,X0]
st2b {z0.b, z1.b}, p0, [x0,x0,lsl #0]
st2b {z0.b-z1.b}, p0, [x0,x0]
st2b {z0.b-z1.b}, p0, [x0,x0,lsl #0]
st2b {z1.b, z2.b}, p0, [x0,x0]
ST2B {Z1.B, Z2.B}, P0, [X0,X0]
st2b {z1.b, z2.b}, p0, [x0,x0,lsl #0]
st2b {z1.b-z2.b}, p0, [x0,x0]
st2b {z1.b-z2.b}, p0, [x0,x0,lsl #0]
st2b {z31.b, z0.b}, p0, [x0,x0]
ST2B {Z31.B, Z0.B}, P0, [X0,X0]
st2b {z31.b, z0.b}, p0, [x0,x0,lsl #0]
st2b {z0.b, z1.b}, p2, [x0,x0]
ST2B {Z0.B, Z1.B}, P2, [X0,X0]
st2b {z0.b, z1.b}, p2, [x0,x0,lsl #0]
st2b {z0.b-z1.b}, p2, [x0,x0]
st2b {z0.b-z1.b}, p2, [x0,x0,lsl #0]
st2b {z0.b, z1.b}, p7, [x0,x0]
ST2B {Z0.B, Z1.B}, P7, [X0,X0]
st2b {z0.b, z1.b}, p7, [x0,x0,lsl #0]
st2b {z0.b-z1.b}, p7, [x0,x0]
st2b {z0.b-z1.b}, p7, [x0,x0,lsl #0]
st2b {z0.b, z1.b}, p0, [x3,x0]
ST2B {Z0.B, Z1.B}, P0, [X3,X0]
st2b {z0.b, z1.b}, p0, [x3,x0,lsl #0]
st2b {z0.b-z1.b}, p0, [x3,x0]
st2b {z0.b-z1.b}, p0, [x3,x0,lsl #0]
st2b {z0.b, z1.b}, p0, [sp,x0]
ST2B {Z0.B, Z1.B}, P0, [SP,X0]
st2b {z0.b, z1.b}, p0, [sp,x0,lsl #0]
st2b {z0.b-z1.b}, p0, [sp,x0]
st2b {z0.b-z1.b}, p0, [sp,x0,lsl #0]
st2b {z0.b, z1.b}, p0, [x0,x4]
ST2B {Z0.B, Z1.B}, P0, [X0,X4]
st2b {z0.b, z1.b}, p0, [x0,x4,lsl #0]
st2b {z0.b-z1.b}, p0, [x0,x4]
st2b {z0.b-z1.b}, p0, [x0,x4,lsl #0]
st2b {z0.b, z1.b}, p0, [x0,x30]
ST2B {Z0.B, Z1.B}, P0, [X0,X30]
st2b {z0.b, z1.b}, p0, [x0,x30,lsl #0]
st2b {z0.b-z1.b}, p0, [x0,x30]
st2b {z0.b-z1.b}, p0, [x0,x30,lsl #0]
st2b {z0.b, z1.b}, p0, [x0,#0]
ST2B {Z0.B, Z1.B}, P0, [X0,#0]
st2b {z0.b, z1.b}, p0, [x0,#0,mul vl]
st2b {z0.b, z1.b}, p0, [x0]
st2b {z0.b-z1.b}, p0, [x0,#0]
st2b {z0.b-z1.b}, p0, [x0,#0,mul vl]
st2b {z0.b-z1.b}, p0, [x0]
st2b {z1.b, z2.b}, p0, [x0,#0]
ST2B {Z1.B, Z2.B}, P0, [X0,#0]
st2b {z1.b, z2.b}, p0, [x0,#0,mul vl]
st2b {z1.b, z2.b}, p0, [x0]
st2b {z1.b-z2.b}, p0, [x0,#0]
st2b {z1.b-z2.b}, p0, [x0,#0,mul vl]
st2b {z1.b-z2.b}, p0, [x0]
st2b {z31.b, z0.b}, p0, [x0,#0]
ST2B {Z31.B, Z0.B}, P0, [X0,#0]
st2b {z31.b, z0.b}, p0, [x0,#0,mul vl]
st2b {z31.b, z0.b}, p0, [x0]
st2b {z0.b, z1.b}, p2, [x0,#0]
ST2B {Z0.B, Z1.B}, P2, [X0,#0]
st2b {z0.b, z1.b}, p2, [x0,#0,mul vl]
st2b {z0.b, z1.b}, p2, [x0]
st2b {z0.b-z1.b}, p2, [x0,#0]
st2b {z0.b-z1.b}, p2, [x0,#0,mul vl]
st2b {z0.b-z1.b}, p2, [x0]
st2b {z0.b, z1.b}, p7, [x0,#0]
ST2B {Z0.B, Z1.B}, P7, [X0,#0]
st2b {z0.b, z1.b}, p7, [x0,#0,mul vl]
st2b {z0.b, z1.b}, p7, [x0]
st2b {z0.b-z1.b}, p7, [x0,#0]
st2b {z0.b-z1.b}, p7, [x0,#0,mul vl]
st2b {z0.b-z1.b}, p7, [x0]
st2b {z0.b, z1.b}, p0, [x3,#0]
ST2B {Z0.B, Z1.B}, P0, [X3,#0]
st2b {z0.b, z1.b}, p0, [x3,#0,mul vl]
st2b {z0.b, z1.b}, p0, [x3]
st2b {z0.b-z1.b}, p0, [x3,#0]
st2b {z0.b-z1.b}, p0, [x3,#0,mul vl]
st2b {z0.b-z1.b}, p0, [x3]
st2b {z0.b, z1.b}, p0, [sp,#0]
ST2B {Z0.B, Z1.B}, P0, [SP,#0]
st2b {z0.b, z1.b}, p0, [sp,#0,mul vl]
st2b {z0.b, z1.b}, p0, [sp]
st2b {z0.b-z1.b}, p0, [sp,#0]
st2b {z0.b-z1.b}, p0, [sp,#0,mul vl]
st2b {z0.b-z1.b}, p0, [sp]
st2b {z0.b, z1.b}, p0, [x0,#14,mul vl]
ST2B {Z0.B, Z1.B}, P0, [X0,#14,MUL VL]
st2b {z0.b-z1.b}, p0, [x0,#14,mul vl]
st2b {z0.b, z1.b}, p0, [x0,#-16,mul vl]
ST2B {Z0.B, Z1.B}, P0, [X0,#-16,MUL VL]
st2b {z0.b-z1.b}, p0, [x0,#-16,mul vl]
st2b {z0.b, z1.b}, p0, [x0,#-14,mul vl]
ST2B {Z0.B, Z1.B}, P0, [X0,#-14,MUL VL]
st2b {z0.b-z1.b}, p0, [x0,#-14,mul vl]
st2b {z0.b, z1.b}, p0, [x0,#-2,mul vl]
ST2B {Z0.B, Z1.B}, P0, [X0,#-2,MUL VL]
st2b {z0.b-z1.b}, p0, [x0,#-2,mul vl]
st2d {z0.d, z1.d}, p0, [x0,x0,lsl #3]
ST2D {Z0.D, Z1.D}, P0, [X0,X0,LSL #3]
st2d {z0.d-z1.d}, p0, [x0,x0,lsl #3]
st2d {z1.d, z2.d}, p0, [x0,x0,lsl #3]
ST2D {Z1.D, Z2.D}, P0, [X0,X0,LSL #3]
st2d {z1.d-z2.d}, p0, [x0,x0,lsl #3]
st2d {z31.d, z0.d}, p0, [x0,x0,lsl #3]
ST2D {Z31.D, Z0.D}, P0, [X0,X0,LSL #3]
st2d {z0.d, z1.d}, p2, [x0,x0,lsl #3]
ST2D {Z0.D, Z1.D}, P2, [X0,X0,LSL #3]
st2d {z0.d-z1.d}, p2, [x0,x0,lsl #3]
st2d {z0.d, z1.d}, p7, [x0,x0,lsl #3]
ST2D {Z0.D, Z1.D}, P7, [X0,X0,LSL #3]
st2d {z0.d-z1.d}, p7, [x0,x0,lsl #3]
st2d {z0.d, z1.d}, p0, [x3,x0,lsl #3]
ST2D {Z0.D, Z1.D}, P0, [X3,X0,LSL #3]
st2d {z0.d-z1.d}, p0, [x3,x0,lsl #3]
st2d {z0.d, z1.d}, p0, [sp,x0,lsl #3]
ST2D {Z0.D, Z1.D}, P0, [SP,X0,LSL #3]
st2d {z0.d-z1.d}, p0, [sp,x0,lsl #3]
st2d {z0.d, z1.d}, p0, [x0,x4,lsl #3]
ST2D {Z0.D, Z1.D}, P0, [X0,X4,LSL #3]
st2d {z0.d-z1.d}, p0, [x0,x4,lsl #3]
st2d {z0.d, z1.d}, p0, [x0,x30,lsl #3]
ST2D {Z0.D, Z1.D}, P0, [X0,X30,LSL #3]
st2d {z0.d-z1.d}, p0, [x0,x30,lsl #3]
st2d {z0.d, z1.d}, p0, [x0,#0]
ST2D {Z0.D, Z1.D}, P0, [X0,#0]
st2d {z0.d, z1.d}, p0, [x0,#0,mul vl]
st2d {z0.d, z1.d}, p0, [x0]
st2d {z0.d-z1.d}, p0, [x0,#0]
st2d {z0.d-z1.d}, p0, [x0,#0,mul vl]
st2d {z0.d-z1.d}, p0, [x0]
st2d {z1.d, z2.d}, p0, [x0,#0]
ST2D {Z1.D, Z2.D}, P0, [X0,#0]
st2d {z1.d, z2.d}, p0, [x0,#0,mul vl]
st2d {z1.d, z2.d}, p0, [x0]
st2d {z1.d-z2.d}, p0, [x0,#0]
st2d {z1.d-z2.d}, p0, [x0,#0,mul vl]
st2d {z1.d-z2.d}, p0, [x0]
st2d {z31.d, z0.d}, p0, [x0,#0]
ST2D {Z31.D, Z0.D}, P0, [X0,#0]
st2d {z31.d, z0.d}, p0, [x0,#0,mul vl]
st2d {z31.d, z0.d}, p0, [x0]
st2d {z0.d, z1.d}, p2, [x0,#0]
ST2D {Z0.D, Z1.D}, P2, [X0,#0]
st2d {z0.d, z1.d}, p2, [x0,#0,mul vl]
st2d {z0.d, z1.d}, p2, [x0]
st2d {z0.d-z1.d}, p2, [x0,#0]
st2d {z0.d-z1.d}, p2, [x0,#0,mul vl]
st2d {z0.d-z1.d}, p2, [x0]
st2d {z0.d, z1.d}, p7, [x0,#0]
ST2D {Z0.D, Z1.D}, P7, [X0,#0]
st2d {z0.d, z1.d}, p7, [x0,#0,mul vl]
st2d {z0.d, z1.d}, p7, [x0]
st2d {z0.d-z1.d}, p7, [x0,#0]
st2d {z0.d-z1.d}, p7, [x0,#0,mul vl]
st2d {z0.d-z1.d}, p7, [x0]
st2d {z0.d, z1.d}, p0, [x3,#0]
ST2D {Z0.D, Z1.D}, P0, [X3,#0]
st2d {z0.d, z1.d}, p0, [x3,#0,mul vl]
st2d {z0.d, z1.d}, p0, [x3]
st2d {z0.d-z1.d}, p0, [x3,#0]
st2d {z0.d-z1.d}, p0, [x3,#0,mul vl]
st2d {z0.d-z1.d}, p0, [x3]
st2d {z0.d, z1.d}, p0, [sp,#0]
ST2D {Z0.D, Z1.D}, P0, [SP,#0]
st2d {z0.d, z1.d}, p0, [sp,#0,mul vl]
st2d {z0.d, z1.d}, p0, [sp]
st2d {z0.d-z1.d}, p0, [sp,#0]
st2d {z0.d-z1.d}, p0, [sp,#0,mul vl]
st2d {z0.d-z1.d}, p0, [sp]
st2d {z0.d, z1.d}, p0, [x0,#14,mul vl]
ST2D {Z0.D, Z1.D}, P0, [X0,#14,MUL VL]
st2d {z0.d-z1.d}, p0, [x0,#14,mul vl]
st2d {z0.d, z1.d}, p0, [x0,#-16,mul vl]
ST2D {Z0.D, Z1.D}, P0, [X0,#-16,MUL VL]
st2d {z0.d-z1.d}, p0, [x0,#-16,mul vl]
st2d {z0.d, z1.d}, p0, [x0,#-14,mul vl]
ST2D {Z0.D, Z1.D}, P0, [X0,#-14,MUL VL]
st2d {z0.d-z1.d}, p0, [x0,#-14,mul vl]
st2d {z0.d, z1.d}, p0, [x0,#-2,mul vl]
ST2D {Z0.D, Z1.D}, P0, [X0,#-2,MUL VL]
st2d {z0.d-z1.d}, p0, [x0,#-2,mul vl]
st2h {z0.h, z1.h}, p0, [x0,x0,lsl #1]
ST2H {Z0.H, Z1.H}, P0, [X0,X0,LSL #1]
st2h {z0.h-z1.h}, p0, [x0,x0,lsl #1]
st2h {z1.h, z2.h}, p0, [x0,x0,lsl #1]
ST2H {Z1.H, Z2.H}, P0, [X0,X0,LSL #1]
st2h {z1.h-z2.h}, p0, [x0,x0,lsl #1]
st2h {z31.h, z0.h}, p0, [x0,x0,lsl #1]
ST2H {Z31.H, Z0.H}, P0, [X0,X0,LSL #1]
st2h {z0.h, z1.h}, p2, [x0,x0,lsl #1]
ST2H {Z0.H, Z1.H}, P2, [X0,X0,LSL #1]
st2h {z0.h-z1.h}, p2, [x0,x0,lsl #1]
st2h {z0.h, z1.h}, p7, [x0,x0,lsl #1]
ST2H {Z0.H, Z1.H}, P7, [X0,X0,LSL #1]
st2h {z0.h-z1.h}, p7, [x0,x0,lsl #1]
st2h {z0.h, z1.h}, p0, [x3,x0,lsl #1]
ST2H {Z0.H, Z1.H}, P0, [X3,X0,LSL #1]
st2h {z0.h-z1.h}, p0, [x3,x0,lsl #1]
st2h {z0.h, z1.h}, p0, [sp,x0,lsl #1]
ST2H {Z0.H, Z1.H}, P0, [SP,X0,LSL #1]
st2h {z0.h-z1.h}, p0, [sp,x0,lsl #1]
st2h {z0.h, z1.h}, p0, [x0,x4,lsl #1]
ST2H {Z0.H, Z1.H}, P0, [X0,X4,LSL #1]
st2h {z0.h-z1.h}, p0, [x0,x4,lsl #1]
st2h {z0.h, z1.h}, p0, [x0,x30,lsl #1]
ST2H {Z0.H, Z1.H}, P0, [X0,X30,LSL #1]
st2h {z0.h-z1.h}, p0, [x0,x30,lsl #1]
st2h {z0.h, z1.h}, p0, [x0,#0]
ST2H {Z0.H, Z1.H}, P0, [X0,#0]
st2h {z0.h, z1.h}, p0, [x0,#0,mul vl]
st2h {z0.h, z1.h}, p0, [x0]
st2h {z0.h-z1.h}, p0, [x0,#0]
st2h {z0.h-z1.h}, p0, [x0,#0,mul vl]
st2h {z0.h-z1.h}, p0, [x0]
st2h {z1.h, z2.h}, p0, [x0,#0]
ST2H {Z1.H, Z2.H}, P0, [X0,#0]
st2h {z1.h, z2.h}, p0, [x0,#0,mul vl]
st2h {z1.h, z2.h}, p0, [x0]
st2h {z1.h-z2.h}, p0, [x0,#0]
st2h {z1.h-z2.h}, p0, [x0,#0,mul vl]
st2h {z1.h-z2.h}, p0, [x0]
st2h {z31.h, z0.h}, p0, [x0,#0]
ST2H {Z31.H, Z0.H}, P0, [X0,#0]
st2h {z31.h, z0.h}, p0, [x0,#0,mul vl]
st2h {z31.h, z0.h}, p0, [x0]
st2h {z0.h, z1.h}, p2, [x0,#0]
ST2H {Z0.H, Z1.H}, P2, [X0,#0]
st2h {z0.h, z1.h}, p2, [x0,#0,mul vl]
st2h {z0.h, z1.h}, p2, [x0]
st2h {z0.h-z1.h}, p2, [x0,#0]
st2h {z0.h-z1.h}, p2, [x0,#0,mul vl]
st2h {z0.h-z1.h}, p2, [x0]
st2h {z0.h, z1.h}, p7, [x0,#0]
ST2H {Z0.H, Z1.H}, P7, [X0,#0]
st2h {z0.h, z1.h}, p7, [x0,#0,mul vl]
st2h {z0.h, z1.h}, p7, [x0]
st2h {z0.h-z1.h}, p7, [x0,#0]
st2h {z0.h-z1.h}, p7, [x0,#0,mul vl]
st2h {z0.h-z1.h}, p7, [x0]
st2h {z0.h, z1.h}, p0, [x3,#0]
ST2H {Z0.H, Z1.H}, P0, [X3,#0]
st2h {z0.h, z1.h}, p0, [x3,#0,mul vl]
st2h {z0.h, z1.h}, p0, [x3]
st2h {z0.h-z1.h}, p0, [x3,#0]
st2h {z0.h-z1.h}, p0, [x3,#0,mul vl]
st2h {z0.h-z1.h}, p0, [x3]
st2h {z0.h, z1.h}, p0, [sp,#0]
ST2H {Z0.H, Z1.H}, P0, [SP,#0]
st2h {z0.h, z1.h}, p0, [sp,#0,mul vl]
st2h {z0.h, z1.h}, p0, [sp]
st2h {z0.h-z1.h}, p0, [sp,#0]
st2h {z0.h-z1.h}, p0, [sp,#0,mul vl]
st2h {z0.h-z1.h}, p0, [sp]
st2h {z0.h, z1.h}, p0, [x0,#14,mul vl]
ST2H {Z0.H, Z1.H}, P0, [X0,#14,MUL VL]
st2h {z0.h-z1.h}, p0, [x0,#14,mul vl]
st2h {z0.h, z1.h}, p0, [x0,#-16,mul vl]
ST2H {Z0.H, Z1.H}, P0, [X0,#-16,MUL VL]
st2h {z0.h-z1.h}, p0, [x0,#-16,mul vl]
st2h {z0.h, z1.h}, p0, [x0,#-14,mul vl]
ST2H {Z0.H, Z1.H}, P0, [X0,#-14,MUL VL]
st2h {z0.h-z1.h}, p0, [x0,#-14,mul vl]
st2h {z0.h, z1.h}, p0, [x0,#-2,mul vl]
ST2H {Z0.H, Z1.H}, P0, [X0,#-2,MUL VL]
st2h {z0.h-z1.h}, p0, [x0,#-2,mul vl]
st2w {z0.s, z1.s}, p0, [x0,x0,lsl #2]
ST2W {Z0.S, Z1.S}, P0, [X0,X0,LSL #2]
st2w {z0.s-z1.s}, p0, [x0,x0,lsl #2]
st2w {z1.s, z2.s}, p0, [x0,x0,lsl #2]
ST2W {Z1.S, Z2.S}, P0, [X0,X0,LSL #2]
st2w {z1.s-z2.s}, p0, [x0,x0,lsl #2]
st2w {z31.s, z0.s}, p0, [x0,x0,lsl #2]
ST2W {Z31.S, Z0.S}, P0, [X0,X0,LSL #2]
st2w {z0.s, z1.s}, p2, [x0,x0,lsl #2]
ST2W {Z0.S, Z1.S}, P2, [X0,X0,LSL #2]
st2w {z0.s-z1.s}, p2, [x0,x0,lsl #2]
st2w {z0.s, z1.s}, p7, [x0,x0,lsl #2]
ST2W {Z0.S, Z1.S}, P7, [X0,X0,LSL #2]
st2w {z0.s-z1.s}, p7, [x0,x0,lsl #2]
st2w {z0.s, z1.s}, p0, [x3,x0,lsl #2]
ST2W {Z0.S, Z1.S}, P0, [X3,X0,LSL #2]
st2w {z0.s-z1.s}, p0, [x3,x0,lsl #2]
st2w {z0.s, z1.s}, p0, [sp,x0,lsl #2]
ST2W {Z0.S, Z1.S}, P0, [SP,X0,LSL #2]
st2w {z0.s-z1.s}, p0, [sp,x0,lsl #2]
st2w {z0.s, z1.s}, p0, [x0,x4,lsl #2]
ST2W {Z0.S, Z1.S}, P0, [X0,X4,LSL #2]
st2w {z0.s-z1.s}, p0, [x0,x4,lsl #2]
st2w {z0.s, z1.s}, p0, [x0,x30,lsl #2]
ST2W {Z0.S, Z1.S}, P0, [X0,X30,LSL #2]
st2w {z0.s-z1.s}, p0, [x0,x30,lsl #2]
st2w {z0.s, z1.s}, p0, [x0,#0]
ST2W {Z0.S, Z1.S}, P0, [X0,#0]
st2w {z0.s, z1.s}, p0, [x0,#0,mul vl]
st2w {z0.s, z1.s}, p0, [x0]
st2w {z0.s-z1.s}, p0, [x0,#0]
st2w {z0.s-z1.s}, p0, [x0,#0,mul vl]
st2w {z0.s-z1.s}, p0, [x0]
st2w {z1.s, z2.s}, p0, [x0,#0]
ST2W {Z1.S, Z2.S}, P0, [X0,#0]
st2w {z1.s, z2.s}, p0, [x0,#0,mul vl]
st2w {z1.s, z2.s}, p0, [x0]
st2w {z1.s-z2.s}, p0, [x0,#0]
st2w {z1.s-z2.s}, p0, [x0,#0,mul vl]
st2w {z1.s-z2.s}, p0, [x0]
st2w {z31.s, z0.s}, p0, [x0,#0]
ST2W {Z31.S, Z0.S}, P0, [X0,#0]
st2w {z31.s, z0.s}, p0, [x0,#0,mul vl]
st2w {z31.s, z0.s}, p0, [x0]
st2w {z0.s, z1.s}, p2, [x0,#0]
ST2W {Z0.S, Z1.S}, P2, [X0,#0]
st2w {z0.s, z1.s}, p2, [x0,#0,mul vl]
st2w {z0.s, z1.s}, p2, [x0]
st2w {z0.s-z1.s}, p2, [x0,#0]
st2w {z0.s-z1.s}, p2, [x0,#0,mul vl]
st2w {z0.s-z1.s}, p2, [x0]
st2w {z0.s, z1.s}, p7, [x0,#0]
ST2W {Z0.S, Z1.S}, P7, [X0,#0]
st2w {z0.s, z1.s}, p7, [x0,#0,mul vl]
st2w {z0.s, z1.s}, p7, [x0]
st2w {z0.s-z1.s}, p7, [x0,#0]
st2w {z0.s-z1.s}, p7, [x0,#0,mul vl]
st2w {z0.s-z1.s}, p7, [x0]
st2w {z0.s, z1.s}, p0, [x3,#0]
ST2W {Z0.S, Z1.S}, P0, [X3,#0]
st2w {z0.s, z1.s}, p0, [x3,#0,mul vl]
st2w {z0.s, z1.s}, p0, [x3]
st2w {z0.s-z1.s}, p0, [x3,#0]
st2w {z0.s-z1.s}, p0, [x3,#0,mul vl]
st2w {z0.s-z1.s}, p0, [x3]
st2w {z0.s, z1.s}, p0, [sp,#0]
ST2W {Z0.S, Z1.S}, P0, [SP,#0]
st2w {z0.s, z1.s}, p0, [sp,#0,mul vl]
st2w {z0.s, z1.s}, p0, [sp]
st2w {z0.s-z1.s}, p0, [sp,#0]
st2w {z0.s-z1.s}, p0, [sp,#0,mul vl]
st2w {z0.s-z1.s}, p0, [sp]
st2w {z0.s, z1.s}, p0, [x0,#14,mul vl]
ST2W {Z0.S, Z1.S}, P0, [X0,#14,MUL VL]
st2w {z0.s-z1.s}, p0, [x0,#14,mul vl]
st2w {z0.s, z1.s}, p0, [x0,#-16,mul vl]
ST2W {Z0.S, Z1.S}, P0, [X0,#-16,MUL VL]
st2w {z0.s-z1.s}, p0, [x0,#-16,mul vl]
st2w {z0.s, z1.s}, p0, [x0,#-14,mul vl]
ST2W {Z0.S, Z1.S}, P0, [X0,#-14,MUL VL]
st2w {z0.s-z1.s}, p0, [x0,#-14,mul vl]
st2w {z0.s, z1.s}, p0, [x0,#-2,mul vl]
ST2W {Z0.S, Z1.S}, P0, [X0,#-2,MUL VL]
st2w {z0.s-z1.s}, p0, [x0,#-2,mul vl]
st3b {z0.b-z2.b}, p0, [x0,x0]
ST3B {Z0.B-Z2.B}, P0, [X0,X0]
st3b {z0.b-z2.b}, p0, [x0,x0,lsl #0]
st3b {z0.b, z1.b, z2.b}, p0, [x0,x0]
st3b {z0.b, z1.b, z2.b}, p0, [x0,x0,lsl #0]
st3b {z1.b-z3.b}, p0, [x0,x0]
ST3B {Z1.B-Z3.B}, P0, [X0,X0]
st3b {z1.b-z3.b}, p0, [x0,x0,lsl #0]
st3b {z1.b, z2.b, z3.b}, p0, [x0,x0]
st3b {z1.b, z2.b, z3.b}, p0, [x0,x0,lsl #0]
st3b {z31.b, z0.b, z1.b}, p0, [x0,x0]
ST3B {Z31.B, Z0.B, Z1.B}, P0, [X0,X0]
st3b {z31.b, z0.b, z1.b}, p0, [x0,x0,lsl #0]
st3b {z0.b-z2.b}, p2, [x0,x0]
ST3B {Z0.B-Z2.B}, P2, [X0,X0]
st3b {z0.b-z2.b}, p2, [x0,x0,lsl #0]
st3b {z0.b, z1.b, z2.b}, p2, [x0,x0]
st3b {z0.b, z1.b, z2.b}, p2, [x0,x0,lsl #0]
st3b {z0.b-z2.b}, p7, [x0,x0]
ST3B {Z0.B-Z2.B}, P7, [X0,X0]
st3b {z0.b-z2.b}, p7, [x0,x0,lsl #0]
st3b {z0.b, z1.b, z2.b}, p7, [x0,x0]
st3b {z0.b, z1.b, z2.b}, p7, [x0,x0,lsl #0]
st3b {z0.b-z2.b}, p0, [x3,x0]
ST3B {Z0.B-Z2.B}, P0, [X3,X0]
st3b {z0.b-z2.b}, p0, [x3,x0,lsl #0]
st3b {z0.b, z1.b, z2.b}, p0, [x3,x0]
st3b {z0.b, z1.b, z2.b}, p0, [x3,x0,lsl #0]
st3b {z0.b-z2.b}, p0, [sp,x0]
ST3B {Z0.B-Z2.B}, P0, [SP,X0]
st3b {z0.b-z2.b}, p0, [sp,x0,lsl #0]
st3b {z0.b, z1.b, z2.b}, p0, [sp,x0]
st3b {z0.b, z1.b, z2.b}, p0, [sp,x0,lsl #0]
st3b {z0.b-z2.b}, p0, [x0,x4]
ST3B {Z0.B-Z2.B}, P0, [X0,X4]
st3b {z0.b-z2.b}, p0, [x0,x4,lsl #0]
st3b {z0.b, z1.b, z2.b}, p0, [x0,x4]
st3b {z0.b, z1.b, z2.b}, p0, [x0,x4,lsl #0]
st3b {z0.b-z2.b}, p0, [x0,x30]
ST3B {Z0.B-Z2.B}, P0, [X0,X30]
st3b {z0.b-z2.b}, p0, [x0,x30,lsl #0]
st3b {z0.b, z1.b, z2.b}, p0, [x0,x30]
st3b {z0.b, z1.b, z2.b}, p0, [x0,x30,lsl #0]
st3b {z0.b-z2.b}, p0, [x0,#0]
ST3B {Z0.B-Z2.B}, P0, [X0,#0]
st3b {z0.b-z2.b}, p0, [x0,#0,mul vl]
st3b {z0.b-z2.b}, p0, [x0]
st3b {z0.b, z1.b, z2.b}, p0, [x0,#0]
st3b {z0.b, z1.b, z2.b}, p0, [x0,#0,mul vl]
st3b {z0.b, z1.b, z2.b}, p0, [x0]
st3b {z1.b-z3.b}, p0, [x0,#0]
ST3B {Z1.B-Z3.B}, P0, [X0,#0]
st3b {z1.b-z3.b}, p0, [x0,#0,mul vl]
st3b {z1.b-z3.b}, p0, [x0]
st3b {z1.b, z2.b, z3.b}, p0, [x0,#0]
st3b {z1.b, z2.b, z3.b}, p0, [x0,#0,mul vl]
st3b {z1.b, z2.b, z3.b}, p0, [x0]
st3b {z31.b, z0.b, z1.b}, p0, [x0,#0]
ST3B {Z31.B, Z0.B, Z1.B}, P0, [X0,#0]
st3b {z31.b, z0.b, z1.b}, p0, [x0,#0,mul vl]
st3b {z31.b, z0.b, z1.b}, p0, [x0]
st3b {z0.b-z2.b}, p2, [x0,#0]
ST3B {Z0.B-Z2.B}, P2, [X0,#0]
st3b {z0.b-z2.b}, p2, [x0,#0,mul vl]
st3b {z0.b-z2.b}, p2, [x0]
st3b {z0.b, z1.b, z2.b}, p2, [x0,#0]
st3b {z0.b, z1.b, z2.b}, p2, [x0,#0,mul vl]
st3b {z0.b, z1.b, z2.b}, p2, [x0]
st3b {z0.b-z2.b}, p7, [x0,#0]
ST3B {Z0.B-Z2.B}, P7, [X0,#0]
st3b {z0.b-z2.b}, p7, [x0,#0,mul vl]
st3b {z0.b-z2.b}, p7, [x0]
st3b {z0.b, z1.b, z2.b}, p7, [x0,#0]
st3b {z0.b, z1.b, z2.b}, p7, [x0,#0,mul vl]
st3b {z0.b, z1.b, z2.b}, p7, [x0]
st3b {z0.b-z2.b}, p0, [x3,#0]
ST3B {Z0.B-Z2.B}, P0, [X3,#0]
st3b {z0.b-z2.b}, p0, [x3,#0,mul vl]
st3b {z0.b-z2.b}, p0, [x3]
st3b {z0.b, z1.b, z2.b}, p0, [x3,#0]
st3b {z0.b, z1.b, z2.b}, p0, [x3,#0,mul vl]
st3b {z0.b, z1.b, z2.b}, p0, [x3]
st3b {z0.b-z2.b}, p0, [sp,#0]
ST3B {Z0.B-Z2.B}, P0, [SP,#0]
st3b {z0.b-z2.b}, p0, [sp,#0,mul vl]
st3b {z0.b-z2.b}, p0, [sp]
st3b {z0.b, z1.b, z2.b}, p0, [sp,#0]
st3b {z0.b, z1.b, z2.b}, p0, [sp,#0,mul vl]
st3b {z0.b, z1.b, z2.b}, p0, [sp]
st3b {z0.b-z2.b}, p0, [x0,#21,mul vl]
ST3B {Z0.B-Z2.B}, P0, [X0,#21,MUL VL]
st3b {z0.b, z1.b, z2.b}, p0, [x0,#21,mul vl]
st3b {z0.b-z2.b}, p0, [x0,#-24,mul vl]
ST3B {Z0.B-Z2.B}, P0, [X0,#-24,MUL VL]
st3b {z0.b, z1.b, z2.b}, p0, [x0,#-24,mul vl]
st3b {z0.b-z2.b}, p0, [x0,#-21,mul vl]
ST3B {Z0.B-Z2.B}, P0, [X0,#-21,MUL VL]
st3b {z0.b, z1.b, z2.b}, p0, [x0,#-21,mul vl]
st3b {z0.b-z2.b}, p0, [x0,#-3,mul vl]
ST3B {Z0.B-Z2.B}, P0, [X0,#-3,MUL VL]
st3b {z0.b, z1.b, z2.b}, p0, [x0,#-3,mul vl]
st3d {z0.d-z2.d}, p0, [x0,x0,lsl #3]
ST3D {Z0.D-Z2.D}, P0, [X0,X0,LSL #3]
st3d {z0.d, z1.d, z2.d}, p0, [x0,x0,lsl #3]
st3d {z1.d-z3.d}, p0, [x0,x0,lsl #3]
ST3D {Z1.D-Z3.D}, P0, [X0,X0,LSL #3]
st3d {z1.d, z2.d, z3.d}, p0, [x0,x0,lsl #3]
st3d {z31.d, z0.d, z1.d}, p0, [x0,x0,lsl #3]
ST3D {Z31.D, Z0.D, Z1.D}, P0, [X0,X0,LSL #3]
st3d {z0.d-z2.d}, p2, [x0,x0,lsl #3]
ST3D {Z0.D-Z2.D}, P2, [X0,X0,LSL #3]
st3d {z0.d, z1.d, z2.d}, p2, [x0,x0,lsl #3]
st3d {z0.d-z2.d}, p7, [x0,x0,lsl #3]
ST3D {Z0.D-Z2.D}, P7, [X0,X0,LSL #3]
st3d {z0.d, z1.d, z2.d}, p7, [x0,x0,lsl #3]
st3d {z0.d-z2.d}, p0, [x3,x0,lsl #3]
ST3D {Z0.D-Z2.D}, P0, [X3,X0,LSL #3]
st3d {z0.d, z1.d, z2.d}, p0, [x3,x0,lsl #3]
st3d {z0.d-z2.d}, p0, [sp,x0,lsl #3]
ST3D {Z0.D-Z2.D}, P0, [SP,X0,LSL #3]
st3d {z0.d, z1.d, z2.d}, p0, [sp,x0,lsl #3]
st3d {z0.d-z2.d}, p0, [x0,x4,lsl #3]
ST3D {Z0.D-Z2.D}, P0, [X0,X4,LSL #3]
st3d {z0.d, z1.d, z2.d}, p0, [x0,x4,lsl #3]
st3d {z0.d-z2.d}, p0, [x0,x30,lsl #3]
ST3D {Z0.D-Z2.D}, P0, [X0,X30,LSL #3]
st3d {z0.d, z1.d, z2.d}, p0, [x0,x30,lsl #3]
st3d {z0.d-z2.d}, p0, [x0,#0]
ST3D {Z0.D-Z2.D}, P0, [X0,#0]
st3d {z0.d-z2.d}, p0, [x0,#0,mul vl]
st3d {z0.d-z2.d}, p0, [x0]
st3d {z0.d, z1.d, z2.d}, p0, [x0,#0]
st3d {z0.d, z1.d, z2.d}, p0, [x0,#0,mul vl]
st3d {z0.d, z1.d, z2.d}, p0, [x0]
st3d {z1.d-z3.d}, p0, [x0,#0]
ST3D {Z1.D-Z3.D}, P0, [X0,#0]
st3d {z1.d-z3.d}, p0, [x0,#0,mul vl]
st3d {z1.d-z3.d}, p0, [x0]
st3d {z1.d, z2.d, z3.d}, p0, [x0,#0]
st3d {z1.d, z2.d, z3.d}, p0, [x0,#0,mul vl]
st3d {z1.d, z2.d, z3.d}, p0, [x0]
st3d {z31.d, z0.d, z1.d}, p0, [x0,#0]
ST3D {Z31.D, Z0.D, Z1.D}, P0, [X0,#0]
st3d {z31.d, z0.d, z1.d}, p0, [x0,#0,mul vl]
st3d {z31.d, z0.d, z1.d}, p0, [x0]
st3d {z0.d-z2.d}, p2, [x0,#0]
ST3D {Z0.D-Z2.D}, P2, [X0,#0]
st3d {z0.d-z2.d}, p2, [x0,#0,mul vl]
st3d {z0.d-z2.d}, p2, [x0]
st3d {z0.d, z1.d, z2.d}, p2, [x0,#0]
st3d {z0.d, z1.d, z2.d}, p2, [x0,#0,mul vl]
st3d {z0.d, z1.d, z2.d}, p2, [x0]
st3d {z0.d-z2.d}, p7, [x0,#0]
ST3D {Z0.D-Z2.D}, P7, [X0,#0]
st3d {z0.d-z2.d}, p7, [x0,#0,mul vl]
st3d {z0.d-z2.d}, p7, [x0]
st3d {z0.d, z1.d, z2.d}, p7, [x0,#0]
st3d {z0.d, z1.d, z2.d}, p7, [x0,#0,mul vl]
st3d {z0.d, z1.d, z2.d}, p7, [x0]
st3d {z0.d-z2.d}, p0, [x3,#0]
ST3D {Z0.D-Z2.D}, P0, [X3,#0]
st3d {z0.d-z2.d}, p0, [x3,#0,mul vl]
st3d {z0.d-z2.d}, p0, [x3]
st3d {z0.d, z1.d, z2.d}, p0, [x3,#0]
st3d {z0.d, z1.d, z2.d}, p0, [x3,#0,mul vl]
st3d {z0.d, z1.d, z2.d}, p0, [x3]
st3d {z0.d-z2.d}, p0, [sp,#0]
ST3D {Z0.D-Z2.D}, P0, [SP,#0]
st3d {z0.d-z2.d}, p0, [sp,#0,mul vl]
st3d {z0.d-z2.d}, p0, [sp]
st3d {z0.d, z1.d, z2.d}, p0, [sp,#0]
st3d {z0.d, z1.d, z2.d}, p0, [sp,#0,mul vl]
st3d {z0.d, z1.d, z2.d}, p0, [sp]
st3d {z0.d-z2.d}, p0, [x0,#21,mul vl]
ST3D {Z0.D-Z2.D}, P0, [X0,#21,MUL VL]
st3d {z0.d, z1.d, z2.d}, p0, [x0,#21,mul vl]
st3d {z0.d-z2.d}, p0, [x0,#-24,mul vl]
ST3D {Z0.D-Z2.D}, P0, [X0,#-24,MUL VL]
st3d {z0.d, z1.d, z2.d}, p0, [x0,#-24,mul vl]
st3d {z0.d-z2.d}, p0, [x0,#-21,mul vl]
ST3D {Z0.D-Z2.D}, P0, [X0,#-21,MUL VL]
st3d {z0.d, z1.d, z2.d}, p0, [x0,#-21,mul vl]
st3d {z0.d-z2.d}, p0, [x0,#-3,mul vl]
ST3D {Z0.D-Z2.D}, P0, [X0,#-3,MUL VL]
st3d {z0.d, z1.d, z2.d}, p0, [x0,#-3,mul vl]
st3h {z0.h-z2.h}, p0, [x0,x0,lsl #1]
ST3H {Z0.H-Z2.H}, P0, [X0,X0,LSL #1]
st3h {z0.h, z1.h, z2.h}, p0, [x0,x0,lsl #1]
st3h {z1.h-z3.h}, p0, [x0,x0,lsl #1]
ST3H {Z1.H-Z3.H}, P0, [X0,X0,LSL #1]
st3h {z1.h, z2.h, z3.h}, p0, [x0,x0,lsl #1]
st3h {z31.h, z0.h, z1.h}, p0, [x0,x0,lsl #1]
ST3H {Z31.H, Z0.H, Z1.H}, P0, [X0,X0,LSL #1]
st3h {z0.h-z2.h}, p2, [x0,x0,lsl #1]
ST3H {Z0.H-Z2.H}, P2, [X0,X0,LSL #1]
st3h {z0.h, z1.h, z2.h}, p2, [x0,x0,lsl #1]
st3h {z0.h-z2.h}, p7, [x0,x0,lsl #1]
ST3H {Z0.H-Z2.H}, P7, [X0,X0,LSL #1]
st3h {z0.h, z1.h, z2.h}, p7, [x0,x0,lsl #1]
st3h {z0.h-z2.h}, p0, [x3,x0,lsl #1]
ST3H {Z0.H-Z2.H}, P0, [X3,X0,LSL #1]
st3h {z0.h, z1.h, z2.h}, p0, [x3,x0,lsl #1]
st3h {z0.h-z2.h}, p0, [sp,x0,lsl #1]
ST3H {Z0.H-Z2.H}, P0, [SP,X0,LSL #1]
st3h {z0.h, z1.h, z2.h}, p0, [sp,x0,lsl #1]
st3h {z0.h-z2.h}, p0, [x0,x4,lsl #1]
ST3H {Z0.H-Z2.H}, P0, [X0,X4,LSL #1]
st3h {z0.h, z1.h, z2.h}, p0, [x0,x4,lsl #1]
st3h {z0.h-z2.h}, p0, [x0,x30,lsl #1]
ST3H {Z0.H-Z2.H}, P0, [X0,X30,LSL #1]
st3h {z0.h, z1.h, z2.h}, p0, [x0,x30,lsl #1]
st3h {z0.h-z2.h}, p0, [x0,#0]
ST3H {Z0.H-Z2.H}, P0, [X0,#0]
st3h {z0.h-z2.h}, p0, [x0,#0,mul vl]
st3h {z0.h-z2.h}, p0, [x0]
st3h {z0.h, z1.h, z2.h}, p0, [x0,#0]
st3h {z0.h, z1.h, z2.h}, p0, [x0,#0,mul vl]
st3h {z0.h, z1.h, z2.h}, p0, [x0]
st3h {z1.h-z3.h}, p0, [x0,#0]
ST3H {Z1.H-Z3.H}, P0, [X0,#0]
st3h {z1.h-z3.h}, p0, [x0,#0,mul vl]
st3h {z1.h-z3.h}, p0, [x0]
st3h {z1.h, z2.h, z3.h}, p0, [x0,#0]
st3h {z1.h, z2.h, z3.h}, p0, [x0,#0,mul vl]
st3h {z1.h, z2.h, z3.h}, p0, [x0]
st3h {z31.h, z0.h, z1.h}, p0, [x0,#0]
ST3H {Z31.H, Z0.H, Z1.H}, P0, [X0,#0]
st3h {z31.h, z0.h, z1.h}, p0, [x0,#0,mul vl]
st3h {z31.h, z0.h, z1.h}, p0, [x0]
st3h {z0.h-z2.h}, p2, [x0,#0]
ST3H {Z0.H-Z2.H}, P2, [X0,#0]
st3h {z0.h-z2.h}, p2, [x0,#0,mul vl]
st3h {z0.h-z2.h}, p2, [x0]
st3h {z0.h, z1.h, z2.h}, p2, [x0,#0]
st3h {z0.h, z1.h, z2.h}, p2, [x0,#0,mul vl]
st3h {z0.h, z1.h, z2.h}, p2, [x0]
st3h {z0.h-z2.h}, p7, [x0,#0]
ST3H {Z0.H-Z2.H}, P7, [X0,#0]
st3h {z0.h-z2.h}, p7, [x0,#0,mul vl]
st3h {z0.h-z2.h}, p7, [x0]
st3h {z0.h, z1.h, z2.h}, p7, [x0,#0]
st3h {z0.h, z1.h, z2.h}, p7, [x0,#0,mul vl]
st3h {z0.h, z1.h, z2.h}, p7, [x0]
st3h {z0.h-z2.h}, p0, [x3,#0]
ST3H {Z0.H-Z2.H}, P0, [X3,#0]
st3h {z0.h-z2.h}, p0, [x3,#0,mul vl]
st3h {z0.h-z2.h}, p0, [x3]
st3h {z0.h, z1.h, z2.h}, p0, [x3,#0]
st3h {z0.h, z1.h, z2.h}, p0, [x3,#0,mul vl]
st3h {z0.h, z1.h, z2.h}, p0, [x3]
st3h {z0.h-z2.h}, p0, [sp,#0]
ST3H {Z0.H-Z2.H}, P0, [SP,#0]
st3h {z0.h-z2.h}, p0, [sp,#0,mul vl]
st3h {z0.h-z2.h}, p0, [sp]
st3h {z0.h, z1.h, z2.h}, p0, [sp,#0]
st3h {z0.h, z1.h, z2.h}, p0, [sp,#0,mul vl]
st3h {z0.h, z1.h, z2.h}, p0, [sp]
st3h {z0.h-z2.h}, p0, [x0,#21,mul vl]
ST3H {Z0.H-Z2.H}, P0, [X0,#21,MUL VL]
st3h {z0.h, z1.h, z2.h}, p0, [x0,#21,mul vl]
st3h {z0.h-z2.h}, p0, [x0,#-24,mul vl]
ST3H {Z0.H-Z2.H}, P0, [X0,#-24,MUL VL]
st3h {z0.h, z1.h, z2.h}, p0, [x0,#-24,mul vl]
st3h {z0.h-z2.h}, p0, [x0,#-21,mul vl]
ST3H {Z0.H-Z2.H}, P0, [X0,#-21,MUL VL]
st3h {z0.h, z1.h, z2.h}, p0, [x0,#-21,mul vl]
st3h {z0.h-z2.h}, p0, [x0,#-3,mul vl]
ST3H {Z0.H-Z2.H}, P0, [X0,#-3,MUL VL]
st3h {z0.h, z1.h, z2.h}, p0, [x0,#-3,mul vl]
st3w {z0.s-z2.s}, p0, [x0,x0,lsl #2]
ST3W {Z0.S-Z2.S}, P0, [X0,X0,LSL #2]
st3w {z0.s, z1.s, z2.s}, p0, [x0,x0,lsl #2]
st3w {z1.s-z3.s}, p0, [x0,x0,lsl #2]
ST3W {Z1.S-Z3.S}, P0, [X0,X0,LSL #2]
st3w {z1.s, z2.s, z3.s}, p0, [x0,x0,lsl #2]
st3w {z31.s, z0.s, z1.s}, p0, [x0,x0,lsl #2]
ST3W {Z31.S, Z0.S, Z1.S}, P0, [X0,X0,LSL #2]
st3w {z0.s-z2.s}, p2, [x0,x0,lsl #2]
ST3W {Z0.S-Z2.S}, P2, [X0,X0,LSL #2]
st3w {z0.s, z1.s, z2.s}, p2, [x0,x0,lsl #2]
st3w {z0.s-z2.s}, p7, [x0,x0,lsl #2]
ST3W {Z0.S-Z2.S}, P7, [X0,X0,LSL #2]
st3w {z0.s, z1.s, z2.s}, p7, [x0,x0,lsl #2]
st3w {z0.s-z2.s}, p0, [x3,x0,lsl #2]
ST3W {Z0.S-Z2.S}, P0, [X3,X0,LSL #2]
st3w {z0.s, z1.s, z2.s}, p0, [x3,x0,lsl #2]
st3w {z0.s-z2.s}, p0, [sp,x0,lsl #2]
ST3W {Z0.S-Z2.S}, P0, [SP,X0,LSL #2]
st3w {z0.s, z1.s, z2.s}, p0, [sp,x0,lsl #2]
st3w {z0.s-z2.s}, p0, [x0,x4,lsl #2]
ST3W {Z0.S-Z2.S}, P0, [X0,X4,LSL #2]
st3w {z0.s, z1.s, z2.s}, p0, [x0,x4,lsl #2]
st3w {z0.s-z2.s}, p0, [x0,x30,lsl #2]
ST3W {Z0.S-Z2.S}, P0, [X0,X30,LSL #2]
st3w {z0.s, z1.s, z2.s}, p0, [x0,x30,lsl #2]
st3w {z0.s-z2.s}, p0, [x0,#0]
ST3W {Z0.S-Z2.S}, P0, [X0,#0]
st3w {z0.s-z2.s}, p0, [x0,#0,mul vl]
st3w {z0.s-z2.s}, p0, [x0]
st3w {z0.s, z1.s, z2.s}, p0, [x0,#0]
st3w {z0.s, z1.s, z2.s}, p0, [x0,#0,mul vl]
st3w {z0.s, z1.s, z2.s}, p0, [x0]
st3w {z1.s-z3.s}, p0, [x0,#0]
ST3W {Z1.S-Z3.S}, P0, [X0,#0]
st3w {z1.s-z3.s}, p0, [x0,#0,mul vl]
st3w {z1.s-z3.s}, p0, [x0]
st3w {z1.s, z2.s, z3.s}, p0, [x0,#0]
st3w {z1.s, z2.s, z3.s}, p0, [x0,#0,mul vl]
st3w {z1.s, z2.s, z3.s}, p0, [x0]
st3w {z31.s, z0.s, z1.s}, p0, [x0,#0]
ST3W {Z31.S, Z0.S, Z1.S}, P0, [X0,#0]
st3w {z31.s, z0.s, z1.s}, p0, [x0,#0,mul vl]
st3w {z31.s, z0.s, z1.s}, p0, [x0]
st3w {z0.s-z2.s}, p2, [x0,#0]
ST3W {Z0.S-Z2.S}, P2, [X0,#0]
st3w {z0.s-z2.s}, p2, [x0,#0,mul vl]
st3w {z0.s-z2.s}, p2, [x0]
st3w {z0.s, z1.s, z2.s}, p2, [x0,#0]
st3w {z0.s, z1.s, z2.s}, p2, [x0,#0,mul vl]
st3w {z0.s, z1.s, z2.s}, p2, [x0]
st3w {z0.s-z2.s}, p7, [x0,#0]
ST3W {Z0.S-Z2.S}, P7, [X0,#0]
st3w {z0.s-z2.s}, p7, [x0,#0,mul vl]
st3w {z0.s-z2.s}, p7, [x0]
st3w {z0.s, z1.s, z2.s}, p7, [x0,#0]
st3w {z0.s, z1.s, z2.s}, p7, [x0,#0,mul vl]
st3w {z0.s, z1.s, z2.s}, p7, [x0]
st3w {z0.s-z2.s}, p0, [x3,#0]
ST3W {Z0.S-Z2.S}, P0, [X3,#0]
st3w {z0.s-z2.s}, p0, [x3,#0,mul vl]
st3w {z0.s-z2.s}, p0, [x3]
st3w {z0.s, z1.s, z2.s}, p0, [x3,#0]
st3w {z0.s, z1.s, z2.s}, p0, [x3,#0,mul vl]
st3w {z0.s, z1.s, z2.s}, p0, [x3]
st3w {z0.s-z2.s}, p0, [sp,#0]
ST3W {Z0.S-Z2.S}, P0, [SP,#0]
st3w {z0.s-z2.s}, p0, [sp,#0,mul vl]
st3w {z0.s-z2.s}, p0, [sp]
st3w {z0.s, z1.s, z2.s}, p0, [sp,#0]
st3w {z0.s, z1.s, z2.s}, p0, [sp,#0,mul vl]
st3w {z0.s, z1.s, z2.s}, p0, [sp]
st3w {z0.s-z2.s}, p0, [x0,#21,mul vl]
ST3W {Z0.S-Z2.S}, P0, [X0,#21,MUL VL]
st3w {z0.s, z1.s, z2.s}, p0, [x0,#21,mul vl]
st3w {z0.s-z2.s}, p0, [x0,#-24,mul vl]
ST3W {Z0.S-Z2.S}, P0, [X0,#-24,MUL VL]
st3w {z0.s, z1.s, z2.s}, p0, [x0,#-24,mul vl]
st3w {z0.s-z2.s}, p0, [x0,#-21,mul vl]
ST3W {Z0.S-Z2.S}, P0, [X0,#-21,MUL VL]
st3w {z0.s, z1.s, z2.s}, p0, [x0,#-21,mul vl]
st3w {z0.s-z2.s}, p0, [x0,#-3,mul vl]
ST3W {Z0.S-Z2.S}, P0, [X0,#-3,MUL VL]
st3w {z0.s, z1.s, z2.s}, p0, [x0,#-3,mul vl]
st4b {z0.b-z3.b}, p0, [x0,x0]
ST4B {Z0.B-Z3.B}, P0, [X0,X0]
st4b {z0.b-z3.b}, p0, [x0,x0,lsl #0]
st4b {z0.b, z1.b, z2.b, z3.b}, p0, [x0,x0]
st4b {z0.b, z1.b, z2.b, z3.b}, p0, [x0,x0,lsl #0]
st4b {z1.b-z4.b}, p0, [x0,x0]
ST4B {Z1.B-Z4.B}, P0, [X0,X0]
st4b {z1.b-z4.b}, p0, [x0,x0,lsl #0]
st4b {z1.b, z2.b, z3.b, z4.b}, p0, [x0,x0]
st4b {z1.b, z2.b, z3.b, z4.b}, p0, [x0,x0,lsl #0]
st4b {z31.b, z0.b, z1.b, z2.b}, p0, [x0,x0]
ST4B {Z31.B, Z0.B, Z1.B, Z2.B}, P0, [X0,X0]
st4b {z31.b, z0.b, z1.b, z2.b}, p0, [x0,x0,lsl #0]
st4b {z0.b-z3.b}, p2, [x0,x0]
ST4B {Z0.B-Z3.B}, P2, [X0,X0]
st4b {z0.b-z3.b}, p2, [x0,x0,lsl #0]
st4b {z0.b, z1.b, z2.b, z3.b}, p2, [x0,x0]
st4b {z0.b, z1.b, z2.b, z3.b}, p2, [x0,x0,lsl #0]
st4b {z0.b-z3.b}, p7, [x0,x0]
ST4B {Z0.B-Z3.B}, P7, [X0,X0]
st4b {z0.b-z3.b}, p7, [x0,x0,lsl #0]
st4b {z0.b, z1.b, z2.b, z3.b}, p7, [x0,x0]
st4b {z0.b, z1.b, z2.b, z3.b}, p7, [x0,x0,lsl #0]
st4b {z0.b-z3.b}, p0, [x3,x0]
ST4B {Z0.B-Z3.B}, P0, [X3,X0]
st4b {z0.b-z3.b}, p0, [x3,x0,lsl #0]
st4b {z0.b, z1.b, z2.b, z3.b}, p0, [x3,x0]
st4b {z0.b, z1.b, z2.b, z3.b}, p0, [x3,x0,lsl #0]
st4b {z0.b-z3.b}, p0, [sp,x0]
ST4B {Z0.B-Z3.B}, P0, [SP,X0]
st4b {z0.b-z3.b}, p0, [sp,x0,lsl #0]
st4b {z0.b, z1.b, z2.b, z3.b}, p0, [sp,x0]
st4b {z0.b, z1.b, z2.b, z3.b}, p0, [sp,x0,lsl #0]
st4b {z0.b-z3.b}, p0, [x0,x4]
ST4B {Z0.B-Z3.B}, P0, [X0,X4]
st4b {z0.b-z3.b}, p0, [x0,x4,lsl #0]
st4b {z0.b, z1.b, z2.b, z3.b}, p0, [x0,x4]
st4b {z0.b, z1.b, z2.b, z3.b}, p0, [x0,x4,lsl #0]
st4b {z0.b-z3.b}, p0, [x0,x30]
ST4B {Z0.B-Z3.B}, P0, [X0,X30]
st4b {z0.b-z3.b}, p0, [x0,x30,lsl #0]
st4b {z0.b, z1.b, z2.b, z3.b}, p0, [x0,x30]
st4b {z0.b, z1.b, z2.b, z3.b}, p0, [x0,x30,lsl #0]
st4b {z0.b-z3.b}, p0, [x0,#0]
ST4B {Z0.B-Z3.B}, P0, [X0,#0]
st4b {z0.b-z3.b}, p0, [x0,#0,mul vl]
st4b {z0.b-z3.b}, p0, [x0]
st4b {z0.b, z1.b, z2.b, z3.b}, p0, [x0,#0]
st4b {z0.b, z1.b, z2.b, z3.b}, p0, [x0,#0,mul vl]
st4b {z0.b, z1.b, z2.b, z3.b}, p0, [x0]
st4b {z1.b-z4.b}, p0, [x0,#0]
ST4B {Z1.B-Z4.B}, P0, [X0,#0]
st4b {z1.b-z4.b}, p0, [x0,#0,mul vl]
st4b {z1.b-z4.b}, p0, [x0]
st4b {z1.b, z2.b, z3.b, z4.b}, p0, [x0,#0]
st4b {z1.b, z2.b, z3.b, z4.b}, p0, [x0,#0,mul vl]
st4b {z1.b, z2.b, z3.b, z4.b}, p0, [x0]
st4b {z31.b, z0.b, z1.b, z2.b}, p0, [x0,#0]
ST4B {Z31.B, Z0.B, Z1.B, Z2.B}, P0, [X0,#0]
st4b {z31.b, z0.b, z1.b, z2.b}, p0, [x0,#0,mul vl]
st4b {z31.b, z0.b, z1.b, z2.b}, p0, [x0]
st4b {z0.b-z3.b}, p2, [x0,#0]
ST4B {Z0.B-Z3.B}, P2, [X0,#0]
st4b {z0.b-z3.b}, p2, [x0,#0,mul vl]
st4b {z0.b-z3.b}, p2, [x0]
st4b {z0.b, z1.b, z2.b, z3.b}, p2, [x0,#0]
st4b {z0.b, z1.b, z2.b, z3.b}, p2, [x0,#0,mul vl]
st4b {z0.b, z1.b, z2.b, z3.b}, p2, [x0]
st4b {z0.b-z3.b}, p7, [x0,#0]
ST4B {Z0.B-Z3.B}, P7, [X0,#0]
st4b {z0.b-z3.b}, p7, [x0,#0,mul vl]
st4b {z0.b-z3.b}, p7, [x0]
st4b {z0.b, z1.b, z2.b, z3.b}, p7, [x0,#0]
st4b {z0.b, z1.b, z2.b, z3.b}, p7, [x0,#0,mul vl]
st4b {z0.b, z1.b, z2.b, z3.b}, p7, [x0]
st4b {z0.b-z3.b}, p0, [x3,#0]
ST4B {Z0.B-Z3.B}, P0, [X3,#0]
st4b {z0.b-z3.b}, p0, [x3,#0,mul vl]
st4b {z0.b-z3.b}, p0, [x3]
st4b {z0.b, z1.b, z2.b, z3.b}, p0, [x3,#0]
st4b {z0.b, z1.b, z2.b, z3.b}, p0, [x3,#0,mul vl]
st4b {z0.b, z1.b, z2.b, z3.b}, p0, [x3]
st4b {z0.b-z3.b}, p0, [sp,#0]
ST4B {Z0.B-Z3.B}, P0, [SP,#0]
st4b {z0.b-z3.b}, p0, [sp,#0,mul vl]
st4b {z0.b-z3.b}, p0, [sp]
st4b {z0.b, z1.b, z2.b, z3.b}, p0, [sp,#0]
st4b {z0.b, z1.b, z2.b, z3.b}, p0, [sp,#0,mul vl]
st4b {z0.b, z1.b, z2.b, z3.b}, p0, [sp]
st4b {z0.b-z3.b}, p0, [x0,#28,mul vl]
ST4B {Z0.B-Z3.B}, P0, [X0,#28,MUL VL]
st4b {z0.b, z1.b, z2.b, z3.b}, p0, [x0,#28,mul vl]
st4b {z0.b-z3.b}, p0, [x0,#-32,mul vl]
ST4B {Z0.B-Z3.B}, P0, [X0,#-32,MUL VL]
st4b {z0.b, z1.b, z2.b, z3.b}, p0, [x0,#-32,mul vl]
st4b {z0.b-z3.b}, p0, [x0,#-28,mul vl]
ST4B {Z0.B-Z3.B}, P0, [X0,#-28,MUL VL]
st4b {z0.b, z1.b, z2.b, z3.b}, p0, [x0,#-28,mul vl]
st4b {z0.b-z3.b}, p0, [x0,#-4,mul vl]
ST4B {Z0.B-Z3.B}, P0, [X0,#-4,MUL VL]
st4b {z0.b, z1.b, z2.b, z3.b}, p0, [x0,#-4,mul vl]
st4d {z0.d-z3.d}, p0, [x0,x0,lsl #3]
ST4D {Z0.D-Z3.D}, P0, [X0,X0,LSL #3]
st4d {z0.d, z1.d, z2.d, z3.d}, p0, [x0,x0,lsl #3]
st4d {z1.d-z4.d}, p0, [x0,x0,lsl #3]
ST4D {Z1.D-Z4.D}, P0, [X0,X0,LSL #3]
st4d {z1.d, z2.d, z3.d, z4.d}, p0, [x0,x0,lsl #3]
st4d {z31.d, z0.d, z1.d, z2.d}, p0, [x0,x0,lsl #3]
ST4D {Z31.D, Z0.D, Z1.D, Z2.D}, P0, [X0,X0,LSL #3]
st4d {z0.d-z3.d}, p2, [x0,x0,lsl #3]
ST4D {Z0.D-Z3.D}, P2, [X0,X0,LSL #3]
st4d {z0.d, z1.d, z2.d, z3.d}, p2, [x0,x0,lsl #3]
st4d {z0.d-z3.d}, p7, [x0,x0,lsl #3]
ST4D {Z0.D-Z3.D}, P7, [X0,X0,LSL #3]
st4d {z0.d, z1.d, z2.d, z3.d}, p7, [x0,x0,lsl #3]
st4d {z0.d-z3.d}, p0, [x3,x0,lsl #3]
ST4D {Z0.D-Z3.D}, P0, [X3,X0,LSL #3]
st4d {z0.d, z1.d, z2.d, z3.d}, p0, [x3,x0,lsl #3]
st4d {z0.d-z3.d}, p0, [sp,x0,lsl #3]
ST4D {Z0.D-Z3.D}, P0, [SP,X0,LSL #3]
st4d {z0.d, z1.d, z2.d, z3.d}, p0, [sp,x0,lsl #3]
st4d {z0.d-z3.d}, p0, [x0,x4,lsl #3]
ST4D {Z0.D-Z3.D}, P0, [X0,X4,LSL #3]
st4d {z0.d, z1.d, z2.d, z3.d}, p0, [x0,x4,lsl #3]
st4d {z0.d-z3.d}, p0, [x0,x30,lsl #3]
ST4D {Z0.D-Z3.D}, P0, [X0,X30,LSL #3]
st4d {z0.d, z1.d, z2.d, z3.d}, p0, [x0,x30,lsl #3]
st4d {z0.d-z3.d}, p0, [x0,#0]
ST4D {Z0.D-Z3.D}, P0, [X0,#0]
st4d {z0.d-z3.d}, p0, [x0,#0,mul vl]
st4d {z0.d-z3.d}, p0, [x0]
st4d {z0.d, z1.d, z2.d, z3.d}, p0, [x0,#0]
st4d {z0.d, z1.d, z2.d, z3.d}, p0, [x0,#0,mul vl]
st4d {z0.d, z1.d, z2.d, z3.d}, p0, [x0]
st4d {z1.d-z4.d}, p0, [x0,#0]
ST4D {Z1.D-Z4.D}, P0, [X0,#0]
st4d {z1.d-z4.d}, p0, [x0,#0,mul vl]
st4d {z1.d-z4.d}, p0, [x0]
st4d {z1.d, z2.d, z3.d, z4.d}, p0, [x0,#0]
st4d {z1.d, z2.d, z3.d, z4.d}, p0, [x0,#0,mul vl]
st4d {z1.d, z2.d, z3.d, z4.d}, p0, [x0]
st4d {z31.d, z0.d, z1.d, z2.d}, p0, [x0,#0]
ST4D {Z31.D, Z0.D, Z1.D, Z2.D}, P0, [X0,#0]
st4d {z31.d, z0.d, z1.d, z2.d}, p0, [x0,#0,mul vl]
st4d {z31.d, z0.d, z1.d, z2.d}, p0, [x0]
st4d {z0.d-z3.d}, p2, [x0,#0]
ST4D {Z0.D-Z3.D}, P2, [X0,#0]
st4d {z0.d-z3.d}, p2, [x0,#0,mul vl]
st4d {z0.d-z3.d}, p2, [x0]
st4d {z0.d, z1.d, z2.d, z3.d}, p2, [x0,#0]
st4d {z0.d, z1.d, z2.d, z3.d}, p2, [x0,#0,mul vl]
st4d {z0.d, z1.d, z2.d, z3.d}, p2, [x0]
st4d {z0.d-z3.d}, p7, [x0,#0]
ST4D {Z0.D-Z3.D}, P7, [X0,#0]
st4d {z0.d-z3.d}, p7, [x0,#0,mul vl]
st4d {z0.d-z3.d}, p7, [x0]
st4d {z0.d, z1.d, z2.d, z3.d}, p7, [x0,#0]
st4d {z0.d, z1.d, z2.d, z3.d}, p7, [x0,#0,mul vl]
st4d {z0.d, z1.d, z2.d, z3.d}, p7, [x0]
st4d {z0.d-z3.d}, p0, [x3,#0]
ST4D {Z0.D-Z3.D}, P0, [X3,#0]
st4d {z0.d-z3.d}, p0, [x3,#0,mul vl]
st4d {z0.d-z3.d}, p0, [x3]
st4d {z0.d, z1.d, z2.d, z3.d}, p0, [x3,#0]
st4d {z0.d, z1.d, z2.d, z3.d}, p0, [x3,#0,mul vl]
st4d {z0.d, z1.d, z2.d, z3.d}, p0, [x3]
st4d {z0.d-z3.d}, p0, [sp,#0]
ST4D {Z0.D-Z3.D}, P0, [SP,#0]
st4d {z0.d-z3.d}, p0, [sp,#0,mul vl]
st4d {z0.d-z3.d}, p0, [sp]
st4d {z0.d, z1.d, z2.d, z3.d}, p0, [sp,#0]
st4d {z0.d, z1.d, z2.d, z3.d}, p0, [sp,#0,mul vl]
st4d {z0.d, z1.d, z2.d, z3.d}, p0, [sp]
st4d {z0.d-z3.d}, p0, [x0,#28,mul vl]
ST4D {Z0.D-Z3.D}, P0, [X0,#28,MUL VL]
st4d {z0.d, z1.d, z2.d, z3.d}, p0, [x0,#28,mul vl]
st4d {z0.d-z3.d}, p0, [x0,#-32,mul vl]
ST4D {Z0.D-Z3.D}, P0, [X0,#-32,MUL VL]
st4d {z0.d, z1.d, z2.d, z3.d}, p0, [x0,#-32,mul vl]
st4d {z0.d-z3.d}, p0, [x0,#-28,mul vl]
ST4D {Z0.D-Z3.D}, P0, [X0,#-28,MUL VL]
st4d {z0.d, z1.d, z2.d, z3.d}, p0, [x0,#-28,mul vl]
st4d {z0.d-z3.d}, p0, [x0,#-4,mul vl]
ST4D {Z0.D-Z3.D}, P0, [X0,#-4,MUL VL]
st4d {z0.d, z1.d, z2.d, z3.d}, p0, [x0,#-4,mul vl]
st4h {z0.h-z3.h}, p0, [x0,x0,lsl #1]
ST4H {Z0.H-Z3.H}, P0, [X0,X0,LSL #1]
st4h {z0.h, z1.h, z2.h, z3.h}, p0, [x0,x0,lsl #1]
st4h {z1.h-z4.h}, p0, [x0,x0,lsl #1]
ST4H {Z1.H-Z4.H}, P0, [X0,X0,LSL #1]
st4h {z1.h, z2.h, z3.h, z4.h}, p0, [x0,x0,lsl #1]
st4h {z31.h, z0.h, z1.h, z2.h}, p0, [x0,x0,lsl #1]
ST4H {Z31.H, Z0.H, Z1.H, Z2.H}, P0, [X0,X0,LSL #1]
st4h {z0.h-z3.h}, p2, [x0,x0,lsl #1]
ST4H {Z0.H-Z3.H}, P2, [X0,X0,LSL #1]
st4h {z0.h, z1.h, z2.h, z3.h}, p2, [x0,x0,lsl #1]
st4h {z0.h-z3.h}, p7, [x0,x0,lsl #1]
ST4H {Z0.H-Z3.H}, P7, [X0,X0,LSL #1]
st4h {z0.h, z1.h, z2.h, z3.h}, p7, [x0,x0,lsl #1]
st4h {z0.h-z3.h}, p0, [x3,x0,lsl #1]
ST4H {Z0.H-Z3.H}, P0, [X3,X0,LSL #1]
st4h {z0.h, z1.h, z2.h, z3.h}, p0, [x3,x0,lsl #1]
st4h {z0.h-z3.h}, p0, [sp,x0,lsl #1]
ST4H {Z0.H-Z3.H}, P0, [SP,X0,LSL #1]
st4h {z0.h, z1.h, z2.h, z3.h}, p0, [sp,x0,lsl #1]
st4h {z0.h-z3.h}, p0, [x0,x4,lsl #1]
ST4H {Z0.H-Z3.H}, P0, [X0,X4,LSL #1]
st4h {z0.h, z1.h, z2.h, z3.h}, p0, [x0,x4,lsl #1]
st4h {z0.h-z3.h}, p0, [x0,x30,lsl #1]
ST4H {Z0.H-Z3.H}, P0, [X0,X30,LSL #1]
st4h {z0.h, z1.h, z2.h, z3.h}, p0, [x0,x30,lsl #1]
st4h {z0.h-z3.h}, p0, [x0,#0]
ST4H {Z0.H-Z3.H}, P0, [X0,#0]
st4h {z0.h-z3.h}, p0, [x0,#0,mul vl]
st4h {z0.h-z3.h}, p0, [x0]
st4h {z0.h, z1.h, z2.h, z3.h}, p0, [x0,#0]
st4h {z0.h, z1.h, z2.h, z3.h}, p0, [x0,#0,mul vl]
st4h {z0.h, z1.h, z2.h, z3.h}, p0, [x0]
st4h {z1.h-z4.h}, p0, [x0,#0]
ST4H {Z1.H-Z4.H}, P0, [X0,#0]
st4h {z1.h-z4.h}, p0, [x0,#0,mul vl]
st4h {z1.h-z4.h}, p0, [x0]
st4h {z1.h, z2.h, z3.h, z4.h}, p0, [x0,#0]
st4h {z1.h, z2.h, z3.h, z4.h}, p0, [x0,#0,mul vl]
st4h {z1.h, z2.h, z3.h, z4.h}, p0, [x0]
st4h {z31.h, z0.h, z1.h, z2.h}, p0, [x0,#0]
ST4H {Z31.H, Z0.H, Z1.H, Z2.H}, P0, [X0,#0]
st4h {z31.h, z0.h, z1.h, z2.h}, p0, [x0,#0,mul vl]
st4h {z31.h, z0.h, z1.h, z2.h}, p0, [x0]
st4h {z0.h-z3.h}, p2, [x0,#0]
ST4H {Z0.H-Z3.H}, P2, [X0,#0]
st4h {z0.h-z3.h}, p2, [x0,#0,mul vl]
st4h {z0.h-z3.h}, p2, [x0]
st4h {z0.h, z1.h, z2.h, z3.h}, p2, [x0,#0]
st4h {z0.h, z1.h, z2.h, z3.h}, p2, [x0,#0,mul vl]
st4h {z0.h, z1.h, z2.h, z3.h}, p2, [x0]
st4h {z0.h-z3.h}, p7, [x0,#0]
ST4H {Z0.H-Z3.H}, P7, [X0,#0]
st4h {z0.h-z3.h}, p7, [x0,#0,mul vl]
st4h {z0.h-z3.h}, p7, [x0]
st4h {z0.h, z1.h, z2.h, z3.h}, p7, [x0,#0]
st4h {z0.h, z1.h, z2.h, z3.h}, p7, [x0,#0,mul vl]
st4h {z0.h, z1.h, z2.h, z3.h}, p7, [x0]
st4h {z0.h-z3.h}, p0, [x3,#0]
ST4H {Z0.H-Z3.H}, P0, [X3,#0]
st4h {z0.h-z3.h}, p0, [x3,#0,mul vl]
st4h {z0.h-z3.h}, p0, [x3]
st4h {z0.h, z1.h, z2.h, z3.h}, p0, [x3,#0]
st4h {z0.h, z1.h, z2.h, z3.h}, p0, [x3,#0,mul vl]
st4h {z0.h, z1.h, z2.h, z3.h}, p0, [x3]
st4h {z0.h-z3.h}, p0, [sp,#0]
ST4H {Z0.H-Z3.H}, P0, [SP,#0]
st4h {z0.h-z3.h}, p0, [sp,#0,mul vl]
st4h {z0.h-z3.h}, p0, [sp]
st4h {z0.h, z1.h, z2.h, z3.h}, p0, [sp,#0]
st4h {z0.h, z1.h, z2.h, z3.h}, p0, [sp,#0,mul vl]
st4h {z0.h, z1.h, z2.h, z3.h}, p0, [sp]
st4h {z0.h-z3.h}, p0, [x0,#28,mul vl]
ST4H {Z0.H-Z3.H}, P0, [X0,#28,MUL VL]
st4h {z0.h, z1.h, z2.h, z3.h}, p0, [x0,#28,mul vl]
st4h {z0.h-z3.h}, p0, [x0,#-32,mul vl]
ST4H {Z0.H-Z3.H}, P0, [X0,#-32,MUL VL]
st4h {z0.h, z1.h, z2.h, z3.h}, p0, [x0,#-32,mul vl]
st4h {z0.h-z3.h}, p0, [x0,#-28,mul vl]
ST4H {Z0.H-Z3.H}, P0, [X0,#-28,MUL VL]
st4h {z0.h, z1.h, z2.h, z3.h}, p0, [x0,#-28,mul vl]
st4h {z0.h-z3.h}, p0, [x0,#-4,mul vl]
ST4H {Z0.H-Z3.H}, P0, [X0,#-4,MUL VL]
st4h {z0.h, z1.h, z2.h, z3.h}, p0, [x0,#-4,mul vl]
st4w {z0.s-z3.s}, p0, [x0,x0,lsl #2]
ST4W {Z0.S-Z3.S}, P0, [X0,X0,LSL #2]
st4w {z0.s, z1.s, z2.s, z3.s}, p0, [x0,x0,lsl #2]
st4w {z1.s-z4.s}, p0, [x0,x0,lsl #2]
ST4W {Z1.S-Z4.S}, P0, [X0,X0,LSL #2]
st4w {z1.s, z2.s, z3.s, z4.s}, p0, [x0,x0,lsl #2]
st4w {z31.s, z0.s, z1.s, z2.s}, p0, [x0,x0,lsl #2]
ST4W {Z31.S, Z0.S, Z1.S, Z2.S}, P0, [X0,X0,LSL #2]
st4w {z0.s-z3.s}, p2, [x0,x0,lsl #2]
ST4W {Z0.S-Z3.S}, P2, [X0,X0,LSL #2]
st4w {z0.s, z1.s, z2.s, z3.s}, p2, [x0,x0,lsl #2]
st4w {z0.s-z3.s}, p7, [x0,x0,lsl #2]
ST4W {Z0.S-Z3.S}, P7, [X0,X0,LSL #2]
st4w {z0.s, z1.s, z2.s, z3.s}, p7, [x0,x0,lsl #2]
st4w {z0.s-z3.s}, p0, [x3,x0,lsl #2]
ST4W {Z0.S-Z3.S}, P0, [X3,X0,LSL #2]
st4w {z0.s, z1.s, z2.s, z3.s}, p0, [x3,x0,lsl #2]
st4w {z0.s-z3.s}, p0, [sp,x0,lsl #2]
ST4W {Z0.S-Z3.S}, P0, [SP,X0,LSL #2]
st4w {z0.s, z1.s, z2.s, z3.s}, p0, [sp,x0,lsl #2]
st4w {z0.s-z3.s}, p0, [x0,x4,lsl #2]
ST4W {Z0.S-Z3.S}, P0, [X0,X4,LSL #2]
st4w {z0.s, z1.s, z2.s, z3.s}, p0, [x0,x4,lsl #2]
st4w {z0.s-z3.s}, p0, [x0,x30,lsl #2]
ST4W {Z0.S-Z3.S}, P0, [X0,X30,LSL #2]
st4w {z0.s, z1.s, z2.s, z3.s}, p0, [x0,x30,lsl #2]
st4w {z0.s-z3.s}, p0, [x0,#0]
ST4W {Z0.S-Z3.S}, P0, [X0,#0]
st4w {z0.s-z3.s}, p0, [x0,#0,mul vl]
st4w {z0.s-z3.s}, p0, [x0]
st4w {z0.s, z1.s, z2.s, z3.s}, p0, [x0,#0]
st4w {z0.s, z1.s, z2.s, z3.s}, p0, [x0,#0,mul vl]
st4w {z0.s, z1.s, z2.s, z3.s}, p0, [x0]
st4w {z1.s-z4.s}, p0, [x0,#0]
ST4W {Z1.S-Z4.S}, P0, [X0,#0]
st4w {z1.s-z4.s}, p0, [x0,#0,mul vl]
st4w {z1.s-z4.s}, p0, [x0]
st4w {z1.s, z2.s, z3.s, z4.s}, p0, [x0,#0]
st4w {z1.s, z2.s, z3.s, z4.s}, p0, [x0,#0,mul vl]
st4w {z1.s, z2.s, z3.s, z4.s}, p0, [x0]
st4w {z31.s, z0.s, z1.s, z2.s}, p0, [x0,#0]
ST4W {Z31.S, Z0.S, Z1.S, Z2.S}, P0, [X0,#0]
st4w {z31.s, z0.s, z1.s, z2.s}, p0, [x0,#0,mul vl]
st4w {z31.s, z0.s, z1.s, z2.s}, p0, [x0]
st4w {z0.s-z3.s}, p2, [x0,#0]
ST4W {Z0.S-Z3.S}, P2, [X0,#0]
st4w {z0.s-z3.s}, p2, [x0,#0,mul vl]
st4w {z0.s-z3.s}, p2, [x0]
st4w {z0.s, z1.s, z2.s, z3.s}, p2, [x0,#0]
st4w {z0.s, z1.s, z2.s, z3.s}, p2, [x0,#0,mul vl]
st4w {z0.s, z1.s, z2.s, z3.s}, p2, [x0]
st4w {z0.s-z3.s}, p7, [x0,#0]
ST4W {Z0.S-Z3.S}, P7, [X0,#0]
st4w {z0.s-z3.s}, p7, [x0,#0,mul vl]
st4w {z0.s-z3.s}, p7, [x0]
st4w {z0.s, z1.s, z2.s, z3.s}, p7, [x0,#0]
st4w {z0.s, z1.s, z2.s, z3.s}, p7, [x0,#0,mul vl]
st4w {z0.s, z1.s, z2.s, z3.s}, p7, [x0]
st4w {z0.s-z3.s}, p0, [x3,#0]
ST4W {Z0.S-Z3.S}, P0, [X3,#0]
st4w {z0.s-z3.s}, p0, [x3,#0,mul vl]
st4w {z0.s-z3.s}, p0, [x3]
st4w {z0.s, z1.s, z2.s, z3.s}, p0, [x3,#0]
st4w {z0.s, z1.s, z2.s, z3.s}, p0, [x3,#0,mul vl]
st4w {z0.s, z1.s, z2.s, z3.s}, p0, [x3]
st4w {z0.s-z3.s}, p0, [sp,#0]
ST4W {Z0.S-Z3.S}, P0, [SP,#0]
st4w {z0.s-z3.s}, p0, [sp,#0,mul vl]
st4w {z0.s-z3.s}, p0, [sp]
st4w {z0.s, z1.s, z2.s, z3.s}, p0, [sp,#0]
st4w {z0.s, z1.s, z2.s, z3.s}, p0, [sp,#0,mul vl]
st4w {z0.s, z1.s, z2.s, z3.s}, p0, [sp]
st4w {z0.s-z3.s}, p0, [x0,#28,mul vl]
ST4W {Z0.S-Z3.S}, P0, [X0,#28,MUL VL]
st4w {z0.s, z1.s, z2.s, z3.s}, p0, [x0,#28,mul vl]
st4w {z0.s-z3.s}, p0, [x0,#-32,mul vl]
ST4W {Z0.S-Z3.S}, P0, [X0,#-32,MUL VL]
st4w {z0.s, z1.s, z2.s, z3.s}, p0, [x0,#-32,mul vl]
st4w {z0.s-z3.s}, p0, [x0,#-28,mul vl]
ST4W {Z0.S-Z3.S}, P0, [X0,#-28,MUL VL]
st4w {z0.s, z1.s, z2.s, z3.s}, p0, [x0,#-28,mul vl]
st4w {z0.s-z3.s}, p0, [x0,#-4,mul vl]
ST4W {Z0.S-Z3.S}, P0, [X0,#-4,MUL VL]
st4w {z0.s, z1.s, z2.s, z3.s}, p0, [x0,#-4,mul vl]
stnt1b z0.b, p0, [x0,x0]
stnt1b {z0.b}, p0, [x0,x0]
STNT1B {Z0.B}, P0, [X0,X0]
stnt1b {z0.b}, p0, [x0,x0,lsl #0]
stnt1b z1.b, p0, [x0,x0]
stnt1b {z1.b}, p0, [x0,x0]
STNT1B {Z1.B}, P0, [X0,X0]
stnt1b {z1.b}, p0, [x0,x0,lsl #0]
stnt1b z31.b, p0, [x0,x0]
stnt1b {z31.b}, p0, [x0,x0]
STNT1B {Z31.B}, P0, [X0,X0]
stnt1b {z31.b}, p0, [x0,x0,lsl #0]
stnt1b {z0.b}, p2, [x0,x0]
STNT1B {Z0.B}, P2, [X0,X0]
stnt1b {z0.b}, p2, [x0,x0,lsl #0]
stnt1b {z0.b}, p7, [x0,x0]
STNT1B {Z0.B}, P7, [X0,X0]
stnt1b {z0.b}, p7, [x0,x0,lsl #0]
stnt1b {z0.b}, p0, [x3,x0]
STNT1B {Z0.B}, P0, [X3,X0]
stnt1b {z0.b}, p0, [x3,x0,lsl #0]
stnt1b {z0.b}, p0, [sp,x0]
STNT1B {Z0.B}, P0, [SP,X0]
stnt1b {z0.b}, p0, [sp,x0,lsl #0]
stnt1b {z0.b}, p0, [x0,x4]
STNT1B {Z0.B}, P0, [X0,X4]
stnt1b {z0.b}, p0, [x0,x4,lsl #0]
stnt1b {z0.b}, p0, [x0,x30]
STNT1B {Z0.B}, P0, [X0,X30]
stnt1b {z0.b}, p0, [x0,x30,lsl #0]
stnt1b z0.b, p0, [x0,#0]
stnt1b {z0.b}, p0, [x0,#0]
STNT1B {Z0.B}, P0, [X0,#0]
stnt1b {z0.b}, p0, [x0,#0,mul vl]
stnt1b {z0.b}, p0, [x0]
stnt1b z1.b, p0, [x0,#0]
stnt1b {z1.b}, p0, [x0,#0]
STNT1B {Z1.B}, P0, [X0,#0]
stnt1b {z1.b}, p0, [x0,#0,mul vl]
stnt1b {z1.b}, p0, [x0]
stnt1b z31.b, p0, [x0,#0]
stnt1b {z31.b}, p0, [x0,#0]
STNT1B {Z31.B}, P0, [X0,#0]
stnt1b {z31.b}, p0, [x0,#0,mul vl]
stnt1b {z31.b}, p0, [x0]
stnt1b {z0.b}, p2, [x0,#0]
STNT1B {Z0.B}, P2, [X0,#0]
stnt1b {z0.b}, p2, [x0,#0,mul vl]
stnt1b {z0.b}, p2, [x0]
stnt1b {z0.b}, p7, [x0,#0]
STNT1B {Z0.B}, P7, [X0,#0]
stnt1b {z0.b}, p7, [x0,#0,mul vl]
stnt1b {z0.b}, p7, [x0]
stnt1b {z0.b}, p0, [x3,#0]
STNT1B {Z0.B}, P0, [X3,#0]
stnt1b {z0.b}, p0, [x3,#0,mul vl]
stnt1b {z0.b}, p0, [x3]
stnt1b {z0.b}, p0, [sp,#0]
STNT1B {Z0.B}, P0, [SP,#0]
stnt1b {z0.b}, p0, [sp,#0,mul vl]
stnt1b {z0.b}, p0, [sp]
stnt1b {z0.b}, p0, [x0,#7,mul vl]
STNT1B {Z0.B}, P0, [X0,#7,MUL VL]
stnt1b {z0.b}, p0, [x0,#-8,mul vl]
STNT1B {Z0.B}, P0, [X0,#-8,MUL VL]
stnt1b {z0.b}, p0, [x0,#-7,mul vl]
STNT1B {Z0.B}, P0, [X0,#-7,MUL VL]
stnt1b {z0.b}, p0, [x0,#-1,mul vl]
STNT1B {Z0.B}, P0, [X0,#-1,MUL VL]
stnt1d z0.d, p0, [x0,x0,lsl #3]
stnt1d {z0.d}, p0, [x0,x0,lsl #3]
STNT1D {Z0.D}, P0, [X0,X0,LSL #3]
stnt1d z1.d, p0, [x0,x0,lsl #3]
stnt1d {z1.d}, p0, [x0,x0,lsl #3]
STNT1D {Z1.D}, P0, [X0,X0,LSL #3]
stnt1d z31.d, p0, [x0,x0,lsl #3]
stnt1d {z31.d}, p0, [x0,x0,lsl #3]
STNT1D {Z31.D}, P0, [X0,X0,LSL #3]
stnt1d {z0.d}, p2, [x0,x0,lsl #3]
STNT1D {Z0.D}, P2, [X0,X0,LSL #3]
stnt1d {z0.d}, p7, [x0,x0,lsl #3]
STNT1D {Z0.D}, P7, [X0,X0,LSL #3]
stnt1d {z0.d}, p0, [x3,x0,lsl #3]
STNT1D {Z0.D}, P0, [X3,X0,LSL #3]
stnt1d {z0.d}, p0, [sp,x0,lsl #3]
STNT1D {Z0.D}, P0, [SP,X0,LSL #3]
stnt1d {z0.d}, p0, [x0,x4,lsl #3]
STNT1D {Z0.D}, P0, [X0,X4,LSL #3]
stnt1d {z0.d}, p0, [x0,x30,lsl #3]
STNT1D {Z0.D}, P0, [X0,X30,LSL #3]
stnt1d z0.d, p0, [x0,#0]
stnt1d {z0.d}, p0, [x0,#0]
STNT1D {Z0.D}, P0, [X0,#0]
stnt1d {z0.d}, p0, [x0,#0,mul vl]
stnt1d {z0.d}, p0, [x0]
stnt1d z1.d, p0, [x0,#0]
stnt1d {z1.d}, p0, [x0,#0]
STNT1D {Z1.D}, P0, [X0,#0]
stnt1d {z1.d}, p0, [x0,#0,mul vl]
stnt1d {z1.d}, p0, [x0]
stnt1d z31.d, p0, [x0,#0]
stnt1d {z31.d}, p0, [x0,#0]
STNT1D {Z31.D}, P0, [X0,#0]
stnt1d {z31.d}, p0, [x0,#0,mul vl]
stnt1d {z31.d}, p0, [x0]
stnt1d {z0.d}, p2, [x0,#0]
STNT1D {Z0.D}, P2, [X0,#0]
stnt1d {z0.d}, p2, [x0,#0,mul vl]
stnt1d {z0.d}, p2, [x0]
stnt1d {z0.d}, p7, [x0,#0]
STNT1D {Z0.D}, P7, [X0,#0]
stnt1d {z0.d}, p7, [x0,#0,mul vl]
stnt1d {z0.d}, p7, [x0]
stnt1d {z0.d}, p0, [x3,#0]
STNT1D {Z0.D}, P0, [X3,#0]
stnt1d {z0.d}, p0, [x3,#0,mul vl]
stnt1d {z0.d}, p0, [x3]
stnt1d {z0.d}, p0, [sp,#0]
STNT1D {Z0.D}, P0, [SP,#0]
stnt1d {z0.d}, p0, [sp,#0,mul vl]
stnt1d {z0.d}, p0, [sp]
stnt1d {z0.d}, p0, [x0,#7,mul vl]
STNT1D {Z0.D}, P0, [X0,#7,MUL VL]
stnt1d {z0.d}, p0, [x0,#-8,mul vl]
STNT1D {Z0.D}, P0, [X0,#-8,MUL VL]
stnt1d {z0.d}, p0, [x0,#-7,mul vl]
STNT1D {Z0.D}, P0, [X0,#-7,MUL VL]
stnt1d {z0.d}, p0, [x0,#-1,mul vl]
STNT1D {Z0.D}, P0, [X0,#-1,MUL VL]
stnt1h z0.h, p0, [x0,x0,lsl #1]
stnt1h {z0.h}, p0, [x0,x0,lsl #1]
STNT1H {Z0.H}, P0, [X0,X0,LSL #1]
stnt1h z1.h, p0, [x0,x0,lsl #1]
stnt1h {z1.h}, p0, [x0,x0,lsl #1]
STNT1H {Z1.H}, P0, [X0,X0,LSL #1]
stnt1h z31.h, p0, [x0,x0,lsl #1]
stnt1h {z31.h}, p0, [x0,x0,lsl #1]
STNT1H {Z31.H}, P0, [X0,X0,LSL #1]
stnt1h {z0.h}, p2, [x0,x0,lsl #1]
STNT1H {Z0.H}, P2, [X0,X0,LSL #1]
stnt1h {z0.h}, p7, [x0,x0,lsl #1]
STNT1H {Z0.H}, P7, [X0,X0,LSL #1]
stnt1h {z0.h}, p0, [x3,x0,lsl #1]
STNT1H {Z0.H}, P0, [X3,X0,LSL #1]
stnt1h {z0.h}, p0, [sp,x0,lsl #1]
STNT1H {Z0.H}, P0, [SP,X0,LSL #1]
stnt1h {z0.h}, p0, [x0,x4,lsl #1]
STNT1H {Z0.H}, P0, [X0,X4,LSL #1]
stnt1h {z0.h}, p0, [x0,x30,lsl #1]
STNT1H {Z0.H}, P0, [X0,X30,LSL #1]
stnt1h z0.h, p0, [x0,#0]
stnt1h {z0.h}, p0, [x0,#0]
STNT1H {Z0.H}, P0, [X0,#0]
stnt1h {z0.h}, p0, [x0,#0,mul vl]
stnt1h {z0.h}, p0, [x0]
stnt1h z1.h, p0, [x0,#0]
stnt1h {z1.h}, p0, [x0,#0]
STNT1H {Z1.H}, P0, [X0,#0]
stnt1h {z1.h}, p0, [x0,#0,mul vl]
stnt1h {z1.h}, p0, [x0]
stnt1h z31.h, p0, [x0,#0]
stnt1h {z31.h}, p0, [x0,#0]
STNT1H {Z31.H}, P0, [X0,#0]
stnt1h {z31.h}, p0, [x0,#0,mul vl]
stnt1h {z31.h}, p0, [x0]
stnt1h {z0.h}, p2, [x0,#0]
STNT1H {Z0.H}, P2, [X0,#0]
stnt1h {z0.h}, p2, [x0,#0,mul vl]
stnt1h {z0.h}, p2, [x0]
stnt1h {z0.h}, p7, [x0,#0]
STNT1H {Z0.H}, P7, [X0,#0]
stnt1h {z0.h}, p7, [x0,#0,mul vl]
stnt1h {z0.h}, p7, [x0]
stnt1h {z0.h}, p0, [x3,#0]
STNT1H {Z0.H}, P0, [X3,#0]
stnt1h {z0.h}, p0, [x3,#0,mul vl]
stnt1h {z0.h}, p0, [x3]
stnt1h {z0.h}, p0, [sp,#0]
STNT1H {Z0.H}, P0, [SP,#0]
stnt1h {z0.h}, p0, [sp,#0,mul vl]
stnt1h {z0.h}, p0, [sp]
stnt1h {z0.h}, p0, [x0,#7,mul vl]
STNT1H {Z0.H}, P0, [X0,#7,MUL VL]
stnt1h {z0.h}, p0, [x0,#-8,mul vl]
STNT1H {Z0.H}, P0, [X0,#-8,MUL VL]
stnt1h {z0.h}, p0, [x0,#-7,mul vl]
STNT1H {Z0.H}, P0, [X0,#-7,MUL VL]
stnt1h {z0.h}, p0, [x0,#-1,mul vl]
STNT1H {Z0.H}, P0, [X0,#-1,MUL VL]
stnt1w z0.s, p0, [x0,x0,lsl #2]
stnt1w {z0.s}, p0, [x0,x0,lsl #2]
STNT1W {Z0.S}, P0, [X0,X0,LSL #2]
stnt1w z1.s, p0, [x0,x0,lsl #2]
stnt1w {z1.s}, p0, [x0,x0,lsl #2]
STNT1W {Z1.S}, P0, [X0,X0,LSL #2]
stnt1w z31.s, p0, [x0,x0,lsl #2]
stnt1w {z31.s}, p0, [x0,x0,lsl #2]
STNT1W {Z31.S}, P0, [X0,X0,LSL #2]
stnt1w {z0.s}, p2, [x0,x0,lsl #2]
STNT1W {Z0.S}, P2, [X0,X0,LSL #2]
stnt1w {z0.s}, p7, [x0,x0,lsl #2]
STNT1W {Z0.S}, P7, [X0,X0,LSL #2]
stnt1w {z0.s}, p0, [x3,x0,lsl #2]
STNT1W {Z0.S}, P0, [X3,X0,LSL #2]
stnt1w {z0.s}, p0, [sp,x0,lsl #2]
STNT1W {Z0.S}, P0, [SP,X0,LSL #2]
stnt1w {z0.s}, p0, [x0,x4,lsl #2]
STNT1W {Z0.S}, P0, [X0,X4,LSL #2]
stnt1w {z0.s}, p0, [x0,x30,lsl #2]
STNT1W {Z0.S}, P0, [X0,X30,LSL #2]
stnt1w z0.s, p0, [x0,#0]
stnt1w {z0.s}, p0, [x0,#0]
STNT1W {Z0.S}, P0, [X0,#0]
stnt1w {z0.s}, p0, [x0,#0,mul vl]
stnt1w {z0.s}, p0, [x0]
stnt1w z1.s, p0, [x0,#0]
stnt1w {z1.s}, p0, [x0,#0]
STNT1W {Z1.S}, P0, [X0,#0]
stnt1w {z1.s}, p0, [x0,#0,mul vl]
stnt1w {z1.s}, p0, [x0]
stnt1w z31.s, p0, [x0,#0]
stnt1w {z31.s}, p0, [x0,#0]
STNT1W {Z31.S}, P0, [X0,#0]
stnt1w {z31.s}, p0, [x0,#0,mul vl]
stnt1w {z31.s}, p0, [x0]
stnt1w {z0.s}, p2, [x0,#0]
STNT1W {Z0.S}, P2, [X0,#0]
stnt1w {z0.s}, p2, [x0,#0,mul vl]
stnt1w {z0.s}, p2, [x0]
stnt1w {z0.s}, p7, [x0,#0]
STNT1W {Z0.S}, P7, [X0,#0]
stnt1w {z0.s}, p7, [x0,#0,mul vl]
stnt1w {z0.s}, p7, [x0]
stnt1w {z0.s}, p0, [x3,#0]
STNT1W {Z0.S}, P0, [X3,#0]
stnt1w {z0.s}, p0, [x3,#0,mul vl]
stnt1w {z0.s}, p0, [x3]
stnt1w {z0.s}, p0, [sp,#0]
STNT1W {Z0.S}, P0, [SP,#0]
stnt1w {z0.s}, p0, [sp,#0,mul vl]
stnt1w {z0.s}, p0, [sp]
stnt1w {z0.s}, p0, [x0,#7,mul vl]
STNT1W {Z0.S}, P0, [X0,#7,MUL VL]
stnt1w {z0.s}, p0, [x0,#-8,mul vl]
STNT1W {Z0.S}, P0, [X0,#-8,MUL VL]
stnt1w {z0.s}, p0, [x0,#-7,mul vl]
STNT1W {Z0.S}, P0, [X0,#-7,MUL VL]
stnt1w {z0.s}, p0, [x0,#-1,mul vl]
STNT1W {Z0.S}, P0, [X0,#-1,MUL VL]
str p0, [x0,#0]
STR P0, [X0,#0]
str p0, [x0,#0,mul vl]
str p0, [x0]
str p1, [x0,#0]
STR P1, [X0,#0]
str p1, [x0,#0,mul vl]
str p1, [x0]
str p15, [x0,#0]
STR P15, [X0,#0]
str p15, [x0,#0,mul vl]
str p15, [x0]
str p0, [x2,#0]
STR P0, [X2,#0]
str p0, [x2,#0,mul vl]
str p0, [x2]
str p0, [sp,#0]
STR P0, [SP,#0]
str p0, [sp,#0,mul vl]
str p0, [sp]
str p0, [x0,#255,mul vl]
STR P0, [X0,#255,MUL VL]
str p0, [x0,#-256,mul vl]
STR P0, [X0,#-256,MUL VL]
str p0, [x0,#-255,mul vl]
STR P0, [X0,#-255,MUL VL]
str p0, [x0,#-1,mul vl]
STR P0, [X0,#-1,MUL VL]
str z0, [x0,#0]
STR Z0, [X0,#0]
str z0, [x0,#0,mul vl]
str z0, [x0]
str z1, [x0,#0]
STR Z1, [X0,#0]
str z1, [x0,#0,mul vl]
str z1, [x0]
str z31, [x0,#0]
STR Z31, [X0,#0]
str z31, [x0,#0,mul vl]
str z31, [x0]
str z0, [x2,#0]
STR Z0, [X2,#0]
str z0, [x2,#0,mul vl]
str z0, [x2]
str z0, [sp,#0]
STR Z0, [SP,#0]
str z0, [sp,#0,mul vl]
str z0, [sp]
str z0, [x0,#255,mul vl]
STR Z0, [X0,#255,MUL VL]
str z0, [x0,#-256,mul vl]
STR Z0, [X0,#-256,MUL VL]
str z0, [x0,#-255,mul vl]
STR Z0, [X0,#-255,MUL VL]
str z0, [x0,#-1,mul vl]
STR Z0, [X0,#-1,MUL VL]
sub z0.b, z0.b, z0.b
SUB Z0.B, Z0.B, Z0.B
sub z1.b, z0.b, z0.b
SUB Z1.B, Z0.B, Z0.B
sub z31.b, z0.b, z0.b
SUB Z31.B, Z0.B, Z0.B
sub z0.b, z2.b, z0.b
SUB Z0.B, Z2.B, Z0.B
sub z0.b, z31.b, z0.b
SUB Z0.B, Z31.B, Z0.B
sub z0.b, z0.b, z3.b
SUB Z0.B, Z0.B, Z3.B
sub z0.b, z0.b, z31.b
SUB Z0.B, Z0.B, Z31.B
sub z0.h, z0.h, z0.h
SUB Z0.H, Z0.H, Z0.H
sub z1.h, z0.h, z0.h
SUB Z1.H, Z0.H, Z0.H
sub z31.h, z0.h, z0.h
SUB Z31.H, Z0.H, Z0.H
sub z0.h, z2.h, z0.h
SUB Z0.H, Z2.H, Z0.H
sub z0.h, z31.h, z0.h
SUB Z0.H, Z31.H, Z0.H
sub z0.h, z0.h, z3.h
SUB Z0.H, Z0.H, Z3.H
sub z0.h, z0.h, z31.h
SUB Z0.H, Z0.H, Z31.H
sub z0.s, z0.s, z0.s
SUB Z0.S, Z0.S, Z0.S
sub z1.s, z0.s, z0.s
SUB Z1.S, Z0.S, Z0.S
sub z31.s, z0.s, z0.s
SUB Z31.S, Z0.S, Z0.S
sub z0.s, z2.s, z0.s
SUB Z0.S, Z2.S, Z0.S
sub z0.s, z31.s, z0.s
SUB Z0.S, Z31.S, Z0.S
sub z0.s, z0.s, z3.s
SUB Z0.S, Z0.S, Z3.S
sub z0.s, z0.s, z31.s
SUB Z0.S, Z0.S, Z31.S
sub z0.d, z0.d, z0.d
SUB Z0.D, Z0.D, Z0.D
sub z1.d, z0.d, z0.d
SUB Z1.D, Z0.D, Z0.D
sub z31.d, z0.d, z0.d
SUB Z31.D, Z0.D, Z0.D
sub z0.d, z2.d, z0.d
SUB Z0.D, Z2.D, Z0.D
sub z0.d, z31.d, z0.d
SUB Z0.D, Z31.D, Z0.D
sub z0.d, z0.d, z3.d
SUB Z0.D, Z0.D, Z3.D
sub z0.d, z0.d, z31.d
SUB Z0.D, Z0.D, Z31.D
sub z0.b, z0.b, #0
SUB Z0.B, Z0.B, #0
sub z0.b, z0.b, #0, lsl #0
sub z1.b, z1.b, #0
SUB Z1.B, Z1.B, #0
sub z1.b, z1.b, #0, lsl #0
sub z31.b, z31.b, #0
SUB Z31.B, Z31.B, #0
sub z31.b, z31.b, #0, lsl #0
sub z2.b, z2.b, #0
SUB Z2.B, Z2.B, #0
sub z2.b, z2.b, #0, lsl #0
sub z0.b, z0.b, #127
SUB Z0.B, Z0.B, #127
sub z0.b, z0.b, #127, lsl #0
sub z0.b, z0.b, #128
SUB Z0.B, Z0.B, #128
sub z0.b, z0.b, #128, lsl #0
sub z0.b, z0.b, #129
SUB Z0.B, Z0.B, #129
sub z0.b, z0.b, #129, lsl #0
sub z0.b, z0.b, #255
SUB Z0.B, Z0.B, #255
sub z0.b, z0.b, #255, lsl #0
sub z0.h, z0.h, #0
SUB Z0.H, Z0.H, #0
sub z0.h, z0.h, #0, lsl #0
sub z1.h, z1.h, #0
SUB Z1.H, Z1.H, #0
sub z1.h, z1.h, #0, lsl #0
sub z31.h, z31.h, #0
SUB Z31.H, Z31.H, #0
sub z31.h, z31.h, #0, lsl #0
sub z2.h, z2.h, #0
SUB Z2.H, Z2.H, #0
sub z2.h, z2.h, #0, lsl #0
sub z0.h, z0.h, #127
SUB Z0.H, Z0.H, #127
sub z0.h, z0.h, #127, lsl #0
sub z0.h, z0.h, #128
SUB Z0.H, Z0.H, #128
sub z0.h, z0.h, #128, lsl #0
sub z0.h, z0.h, #129
SUB Z0.H, Z0.H, #129
sub z0.h, z0.h, #129, lsl #0
sub z0.h, z0.h, #255
SUB Z0.H, Z0.H, #255
sub z0.h, z0.h, #255, lsl #0
sub z0.h, z0.h, #0, lsl #8
SUB Z0.H, Z0.H, #0, LSL #8
sub z0.h, z0.h, #32512
SUB Z0.H, Z0.H, #32512
sub z0.h, z0.h, #32512, lsl #0
sub z0.h, z0.h, #127, lsl #8
sub z0.h, z0.h, #32768
SUB Z0.H, Z0.H, #32768
sub z0.h, z0.h, #32768, lsl #0
sub z0.h, z0.h, #128, lsl #8
sub z0.h, z0.h, #33024
SUB Z0.H, Z0.H, #33024
sub z0.h, z0.h, #33024, lsl #0
sub z0.h, z0.h, #129, lsl #8
sub z0.h, z0.h, #65280
SUB Z0.H, Z0.H, #65280
sub z0.h, z0.h, #65280, lsl #0
sub z0.h, z0.h, #255, lsl #8
sub z0.s, z0.s, #0
SUB Z0.S, Z0.S, #0
sub z0.s, z0.s, #0, lsl #0
sub z1.s, z1.s, #0
SUB Z1.S, Z1.S, #0
sub z1.s, z1.s, #0, lsl #0
sub z31.s, z31.s, #0
SUB Z31.S, Z31.S, #0
sub z31.s, z31.s, #0, lsl #0
sub z2.s, z2.s, #0
SUB Z2.S, Z2.S, #0
sub z2.s, z2.s, #0, lsl #0
sub z0.s, z0.s, #127
SUB Z0.S, Z0.S, #127
sub z0.s, z0.s, #127, lsl #0
sub z0.s, z0.s, #128
SUB Z0.S, Z0.S, #128
sub z0.s, z0.s, #128, lsl #0
sub z0.s, z0.s, #129
SUB Z0.S, Z0.S, #129
sub z0.s, z0.s, #129, lsl #0
sub z0.s, z0.s, #255
SUB Z0.S, Z0.S, #255
sub z0.s, z0.s, #255, lsl #0
sub z0.s, z0.s, #0, lsl #8
SUB Z0.S, Z0.S, #0, LSL #8
sub z0.s, z0.s, #32512
SUB Z0.S, Z0.S, #32512
sub z0.s, z0.s, #32512, lsl #0
sub z0.s, z0.s, #127, lsl #8
sub z0.s, z0.s, #32768
SUB Z0.S, Z0.S, #32768
sub z0.s, z0.s, #32768, lsl #0
sub z0.s, z0.s, #128, lsl #8
sub z0.s, z0.s, #33024
SUB Z0.S, Z0.S, #33024
sub z0.s, z0.s, #33024, lsl #0
sub z0.s, z0.s, #129, lsl #8
sub z0.s, z0.s, #65280
SUB Z0.S, Z0.S, #65280
sub z0.s, z0.s, #65280, lsl #0
sub z0.s, z0.s, #255, lsl #8
sub z0.d, z0.d, #0
SUB Z0.D, Z0.D, #0
sub z0.d, z0.d, #0, lsl #0
sub z1.d, z1.d, #0
SUB Z1.D, Z1.D, #0
sub z1.d, z1.d, #0, lsl #0
sub z31.d, z31.d, #0
SUB Z31.D, Z31.D, #0
sub z31.d, z31.d, #0, lsl #0
sub z2.d, z2.d, #0
SUB Z2.D, Z2.D, #0
sub z2.d, z2.d, #0, lsl #0
sub z0.d, z0.d, #127
SUB Z0.D, Z0.D, #127
sub z0.d, z0.d, #127, lsl #0
sub z0.d, z0.d, #128
SUB Z0.D, Z0.D, #128
sub z0.d, z0.d, #128, lsl #0
sub z0.d, z0.d, #129
SUB Z0.D, Z0.D, #129
sub z0.d, z0.d, #129, lsl #0
sub z0.d, z0.d, #255
SUB Z0.D, Z0.D, #255
sub z0.d, z0.d, #255, lsl #0
sub z0.d, z0.d, #0, lsl #8
SUB Z0.D, Z0.D, #0, LSL #8
sub z0.d, z0.d, #32512
SUB Z0.D, Z0.D, #32512
sub z0.d, z0.d, #32512, lsl #0
sub z0.d, z0.d, #127, lsl #8
sub z0.d, z0.d, #32768
SUB Z0.D, Z0.D, #32768
sub z0.d, z0.d, #32768, lsl #0
sub z0.d, z0.d, #128, lsl #8
sub z0.d, z0.d, #33024
SUB Z0.D, Z0.D, #33024
sub z0.d, z0.d, #33024, lsl #0
sub z0.d, z0.d, #129, lsl #8
sub z0.d, z0.d, #65280
SUB Z0.D, Z0.D, #65280
sub z0.d, z0.d, #65280, lsl #0
sub z0.d, z0.d, #255, lsl #8
sub z0.b, p0/m, z0.b, z0.b
SUB Z0.B, P0/M, Z0.B, Z0.B
sub z1.b, p0/m, z1.b, z0.b
SUB Z1.B, P0/M, Z1.B, Z0.B
sub z31.b, p0/m, z31.b, z0.b
SUB Z31.B, P0/M, Z31.B, Z0.B
sub z0.b, p2/m, z0.b, z0.b
SUB Z0.B, P2/M, Z0.B, Z0.B
sub z0.b, p7/m, z0.b, z0.b
SUB Z0.B, P7/M, Z0.B, Z0.B
sub z3.b, p0/m, z3.b, z0.b
SUB Z3.B, P0/M, Z3.B, Z0.B
sub z0.b, p0/m, z0.b, z4.b
SUB Z0.B, P0/M, Z0.B, Z4.B
sub z0.b, p0/m, z0.b, z31.b
SUB Z0.B, P0/M, Z0.B, Z31.B
sub z0.h, p0/m, z0.h, z0.h
SUB Z0.H, P0/M, Z0.H, Z0.H
sub z1.h, p0/m, z1.h, z0.h
SUB Z1.H, P0/M, Z1.H, Z0.H
sub z31.h, p0/m, z31.h, z0.h
SUB Z31.H, P0/M, Z31.H, Z0.H
sub z0.h, p2/m, z0.h, z0.h
SUB Z0.H, P2/M, Z0.H, Z0.H
sub z0.h, p7/m, z0.h, z0.h
SUB Z0.H, P7/M, Z0.H, Z0.H
sub z3.h, p0/m, z3.h, z0.h
SUB Z3.H, P0/M, Z3.H, Z0.H
sub z0.h, p0/m, z0.h, z4.h
SUB Z0.H, P0/M, Z0.H, Z4.H
sub z0.h, p0/m, z0.h, z31.h
SUB Z0.H, P0/M, Z0.H, Z31.H
sub z0.s, p0/m, z0.s, z0.s
SUB Z0.S, P0/M, Z0.S, Z0.S
sub z1.s, p0/m, z1.s, z0.s
SUB Z1.S, P0/M, Z1.S, Z0.S
sub z31.s, p0/m, z31.s, z0.s
SUB Z31.S, P0/M, Z31.S, Z0.S
sub z0.s, p2/m, z0.s, z0.s
SUB Z0.S, P2/M, Z0.S, Z0.S
sub z0.s, p7/m, z0.s, z0.s
SUB Z0.S, P7/M, Z0.S, Z0.S
sub z3.s, p0/m, z3.s, z0.s
SUB Z3.S, P0/M, Z3.S, Z0.S
sub z0.s, p0/m, z0.s, z4.s
SUB Z0.S, P0/M, Z0.S, Z4.S
sub z0.s, p0/m, z0.s, z31.s
SUB Z0.S, P0/M, Z0.S, Z31.S
sub z0.d, p0/m, z0.d, z0.d
SUB Z0.D, P0/M, Z0.D, Z0.D
sub z1.d, p0/m, z1.d, z0.d
SUB Z1.D, P0/M, Z1.D, Z0.D
sub z31.d, p0/m, z31.d, z0.d
SUB Z31.D, P0/M, Z31.D, Z0.D
sub z0.d, p2/m, z0.d, z0.d
SUB Z0.D, P2/M, Z0.D, Z0.D
sub z0.d, p7/m, z0.d, z0.d
SUB Z0.D, P7/M, Z0.D, Z0.D
sub z3.d, p0/m, z3.d, z0.d
SUB Z3.D, P0/M, Z3.D, Z0.D
sub z0.d, p0/m, z0.d, z4.d
SUB Z0.D, P0/M, Z0.D, Z4.D
sub z0.d, p0/m, z0.d, z31.d
SUB Z0.D, P0/M, Z0.D, Z31.D
subr z0.b, z0.b, #0
SUBR Z0.B, Z0.B, #0
subr z0.b, z0.b, #0, lsl #0
subr z1.b, z1.b, #0
SUBR Z1.B, Z1.B, #0
subr z1.b, z1.b, #0, lsl #0
subr z31.b, z31.b, #0
SUBR Z31.B, Z31.B, #0
subr z31.b, z31.b, #0, lsl #0
subr z2.b, z2.b, #0
SUBR Z2.B, Z2.B, #0
subr z2.b, z2.b, #0, lsl #0
subr z0.b, z0.b, #127
SUBR Z0.B, Z0.B, #127
subr z0.b, z0.b, #127, lsl #0
subr z0.b, z0.b, #128
SUBR Z0.B, Z0.B, #128
subr z0.b, z0.b, #128, lsl #0
subr z0.b, z0.b, #129
SUBR Z0.B, Z0.B, #129
subr z0.b, z0.b, #129, lsl #0
subr z0.b, z0.b, #255
SUBR Z0.B, Z0.B, #255
subr z0.b, z0.b, #255, lsl #0
subr z0.h, z0.h, #0
SUBR Z0.H, Z0.H, #0
subr z0.h, z0.h, #0, lsl #0
subr z1.h, z1.h, #0
SUBR Z1.H, Z1.H, #0
subr z1.h, z1.h, #0, lsl #0
subr z31.h, z31.h, #0
SUBR Z31.H, Z31.H, #0
subr z31.h, z31.h, #0, lsl #0
subr z2.h, z2.h, #0
SUBR Z2.H, Z2.H, #0
subr z2.h, z2.h, #0, lsl #0
subr z0.h, z0.h, #127
SUBR Z0.H, Z0.H, #127
subr z0.h, z0.h, #127, lsl #0
subr z0.h, z0.h, #128
SUBR Z0.H, Z0.H, #128
subr z0.h, z0.h, #128, lsl #0
subr z0.h, z0.h, #129
SUBR Z0.H, Z0.H, #129
subr z0.h, z0.h, #129, lsl #0
subr z0.h, z0.h, #255
SUBR Z0.H, Z0.H, #255
subr z0.h, z0.h, #255, lsl #0
subr z0.h, z0.h, #0, lsl #8
SUBR Z0.H, Z0.H, #0, LSL #8
subr z0.h, z0.h, #32512
SUBR Z0.H, Z0.H, #32512
subr z0.h, z0.h, #32512, lsl #0
subr z0.h, z0.h, #127, lsl #8
subr z0.h, z0.h, #32768
SUBR Z0.H, Z0.H, #32768
subr z0.h, z0.h, #32768, lsl #0
subr z0.h, z0.h, #128, lsl #8
subr z0.h, z0.h, #33024
SUBR Z0.H, Z0.H, #33024
subr z0.h, z0.h, #33024, lsl #0
subr z0.h, z0.h, #129, lsl #8
subr z0.h, z0.h, #65280
SUBR Z0.H, Z0.H, #65280
subr z0.h, z0.h, #65280, lsl #0
subr z0.h, z0.h, #255, lsl #8
subr z0.s, z0.s, #0
SUBR Z0.S, Z0.S, #0
subr z0.s, z0.s, #0, lsl #0
subr z1.s, z1.s, #0
SUBR Z1.S, Z1.S, #0
subr z1.s, z1.s, #0, lsl #0
subr z31.s, z31.s, #0
SUBR Z31.S, Z31.S, #0
subr z31.s, z31.s, #0, lsl #0
subr z2.s, z2.s, #0
SUBR Z2.S, Z2.S, #0
subr z2.s, z2.s, #0, lsl #0
subr z0.s, z0.s, #127
SUBR Z0.S, Z0.S, #127
subr z0.s, z0.s, #127, lsl #0
subr z0.s, z0.s, #128
SUBR Z0.S, Z0.S, #128
subr z0.s, z0.s, #128, lsl #0
subr z0.s, z0.s, #129
SUBR Z0.S, Z0.S, #129
subr z0.s, z0.s, #129, lsl #0
subr z0.s, z0.s, #255
SUBR Z0.S, Z0.S, #255
subr z0.s, z0.s, #255, lsl #0
subr z0.s, z0.s, #0, lsl #8
SUBR Z0.S, Z0.S, #0, LSL #8
subr z0.s, z0.s, #32512
SUBR Z0.S, Z0.S, #32512
subr z0.s, z0.s, #32512, lsl #0
subr z0.s, z0.s, #127, lsl #8
subr z0.s, z0.s, #32768
SUBR Z0.S, Z0.S, #32768
subr z0.s, z0.s, #32768, lsl #0
subr z0.s, z0.s, #128, lsl #8
subr z0.s, z0.s, #33024
SUBR Z0.S, Z0.S, #33024
subr z0.s, z0.s, #33024, lsl #0
subr z0.s, z0.s, #129, lsl #8
subr z0.s, z0.s, #65280
SUBR Z0.S, Z0.S, #65280
subr z0.s, z0.s, #65280, lsl #0
subr z0.s, z0.s, #255, lsl #8
subr z0.d, z0.d, #0
SUBR Z0.D, Z0.D, #0
subr z0.d, z0.d, #0, lsl #0
subr z1.d, z1.d, #0
SUBR Z1.D, Z1.D, #0
subr z1.d, z1.d, #0, lsl #0
subr z31.d, z31.d, #0
SUBR Z31.D, Z31.D, #0
subr z31.d, z31.d, #0, lsl #0
subr z2.d, z2.d, #0
SUBR Z2.D, Z2.D, #0
subr z2.d, z2.d, #0, lsl #0
subr z0.d, z0.d, #127
SUBR Z0.D, Z0.D, #127
subr z0.d, z0.d, #127, lsl #0
subr z0.d, z0.d, #128
SUBR Z0.D, Z0.D, #128
subr z0.d, z0.d, #128, lsl #0
subr z0.d, z0.d, #129
SUBR Z0.D, Z0.D, #129
subr z0.d, z0.d, #129, lsl #0
subr z0.d, z0.d, #255
SUBR Z0.D, Z0.D, #255
subr z0.d, z0.d, #255, lsl #0
subr z0.d, z0.d, #0, lsl #8
SUBR Z0.D, Z0.D, #0, LSL #8
subr z0.d, z0.d, #32512
SUBR Z0.D, Z0.D, #32512
subr z0.d, z0.d, #32512, lsl #0
subr z0.d, z0.d, #127, lsl #8
subr z0.d, z0.d, #32768
SUBR Z0.D, Z0.D, #32768
subr z0.d, z0.d, #32768, lsl #0
subr z0.d, z0.d, #128, lsl #8
subr z0.d, z0.d, #33024
SUBR Z0.D, Z0.D, #33024
subr z0.d, z0.d, #33024, lsl #0
subr z0.d, z0.d, #129, lsl #8
subr z0.d, z0.d, #65280
SUBR Z0.D, Z0.D, #65280
subr z0.d, z0.d, #65280, lsl #0
subr z0.d, z0.d, #255, lsl #8
subr z0.b, p0/m, z0.b, z0.b
SUBR Z0.B, P0/M, Z0.B, Z0.B
subr z1.b, p0/m, z1.b, z0.b
SUBR Z1.B, P0/M, Z1.B, Z0.B
subr z31.b, p0/m, z31.b, z0.b
SUBR Z31.B, P0/M, Z31.B, Z0.B
subr z0.b, p2/m, z0.b, z0.b
SUBR Z0.B, P2/M, Z0.B, Z0.B
subr z0.b, p7/m, z0.b, z0.b
SUBR Z0.B, P7/M, Z0.B, Z0.B
subr z3.b, p0/m, z3.b, z0.b
SUBR Z3.B, P0/M, Z3.B, Z0.B
subr z0.b, p0/m, z0.b, z4.b
SUBR Z0.B, P0/M, Z0.B, Z4.B
subr z0.b, p0/m, z0.b, z31.b
SUBR Z0.B, P0/M, Z0.B, Z31.B
subr z0.h, p0/m, z0.h, z0.h
SUBR Z0.H, P0/M, Z0.H, Z0.H
subr z1.h, p0/m, z1.h, z0.h
SUBR Z1.H, P0/M, Z1.H, Z0.H
subr z31.h, p0/m, z31.h, z0.h
SUBR Z31.H, P0/M, Z31.H, Z0.H
subr z0.h, p2/m, z0.h, z0.h
SUBR Z0.H, P2/M, Z0.H, Z0.H
subr z0.h, p7/m, z0.h, z0.h
SUBR Z0.H, P7/M, Z0.H, Z0.H
subr z3.h, p0/m, z3.h, z0.h
SUBR Z3.H, P0/M, Z3.H, Z0.H
subr z0.h, p0/m, z0.h, z4.h
SUBR Z0.H, P0/M, Z0.H, Z4.H
subr z0.h, p0/m, z0.h, z31.h
SUBR Z0.H, P0/M, Z0.H, Z31.H
subr z0.s, p0/m, z0.s, z0.s
SUBR Z0.S, P0/M, Z0.S, Z0.S
subr z1.s, p0/m, z1.s, z0.s
SUBR Z1.S, P0/M, Z1.S, Z0.S
subr z31.s, p0/m, z31.s, z0.s
SUBR Z31.S, P0/M, Z31.S, Z0.S
subr z0.s, p2/m, z0.s, z0.s
SUBR Z0.S, P2/M, Z0.S, Z0.S
subr z0.s, p7/m, z0.s, z0.s
SUBR Z0.S, P7/M, Z0.S, Z0.S
subr z3.s, p0/m, z3.s, z0.s
SUBR Z3.S, P0/M, Z3.S, Z0.S
subr z0.s, p0/m, z0.s, z4.s
SUBR Z0.S, P0/M, Z0.S, Z4.S
subr z0.s, p0/m, z0.s, z31.s
SUBR Z0.S, P0/M, Z0.S, Z31.S
subr z0.d, p0/m, z0.d, z0.d
SUBR Z0.D, P0/M, Z0.D, Z0.D
subr z1.d, p0/m, z1.d, z0.d
SUBR Z1.D, P0/M, Z1.D, Z0.D
subr z31.d, p0/m, z31.d, z0.d
SUBR Z31.D, P0/M, Z31.D, Z0.D
subr z0.d, p2/m, z0.d, z0.d
SUBR Z0.D, P2/M, Z0.D, Z0.D
subr z0.d, p7/m, z0.d, z0.d
SUBR Z0.D, P7/M, Z0.D, Z0.D
subr z3.d, p0/m, z3.d, z0.d
SUBR Z3.D, P0/M, Z3.D, Z0.D
subr z0.d, p0/m, z0.d, z4.d
SUBR Z0.D, P0/M, Z0.D, Z4.D
subr z0.d, p0/m, z0.d, z31.d
SUBR Z0.D, P0/M, Z0.D, Z31.D
sunpkhi z0.h, z0.b
SUNPKHI Z0.H, Z0.B
sunpkhi z1.h, z0.b
SUNPKHI Z1.H, Z0.B
sunpkhi z31.h, z0.b
SUNPKHI Z31.H, Z0.B
sunpkhi z0.h, z2.b
SUNPKHI Z0.H, Z2.B
sunpkhi z0.h, z31.b
SUNPKHI Z0.H, Z31.B
sunpkhi z0.s, z0.h
SUNPKHI Z0.S, Z0.H
sunpkhi z1.s, z0.h
SUNPKHI Z1.S, Z0.H
sunpkhi z31.s, z0.h
SUNPKHI Z31.S, Z0.H
sunpkhi z0.s, z2.h
SUNPKHI Z0.S, Z2.H
sunpkhi z0.s, z31.h
SUNPKHI Z0.S, Z31.H
sunpkhi z0.d, z0.s
SUNPKHI Z0.D, Z0.S
sunpkhi z1.d, z0.s
SUNPKHI Z1.D, Z0.S
sunpkhi z31.d, z0.s
SUNPKHI Z31.D, Z0.S
sunpkhi z0.d, z2.s
SUNPKHI Z0.D, Z2.S
sunpkhi z0.d, z31.s
SUNPKHI Z0.D, Z31.S
sunpklo z0.h, z0.b
SUNPKLO Z0.H, Z0.B
sunpklo z1.h, z0.b
SUNPKLO Z1.H, Z0.B
sunpklo z31.h, z0.b
SUNPKLO Z31.H, Z0.B
sunpklo z0.h, z2.b
SUNPKLO Z0.H, Z2.B
sunpklo z0.h, z31.b
SUNPKLO Z0.H, Z31.B
sunpklo z0.s, z0.h
SUNPKLO Z0.S, Z0.H
sunpklo z1.s, z0.h
SUNPKLO Z1.S, Z0.H
sunpklo z31.s, z0.h
SUNPKLO Z31.S, Z0.H
sunpklo z0.s, z2.h
SUNPKLO Z0.S, Z2.H
sunpklo z0.s, z31.h
SUNPKLO Z0.S, Z31.H
sunpklo z0.d, z0.s
SUNPKLO Z0.D, Z0.S
sunpklo z1.d, z0.s
SUNPKLO Z1.D, Z0.S
sunpklo z31.d, z0.s
SUNPKLO Z31.D, Z0.S
sunpklo z0.d, z2.s
SUNPKLO Z0.D, Z2.S
sunpklo z0.d, z31.s
SUNPKLO Z0.D, Z31.S
sxtb z0.h, p0/m, z0.h
SXTB Z0.H, P0/M, Z0.H
sxtb z1.h, p0/m, z0.h
SXTB Z1.H, P0/M, Z0.H
sxtb z31.h, p0/m, z0.h
SXTB Z31.H, P0/M, Z0.H
sxtb z0.h, p2/m, z0.h
SXTB Z0.H, P2/M, Z0.H
sxtb z0.h, p7/m, z0.h
SXTB Z0.H, P7/M, Z0.H
sxtb z0.h, p0/m, z3.h
SXTB Z0.H, P0/M, Z3.H
sxtb z0.h, p0/m, z31.h
SXTB Z0.H, P0/M, Z31.H
sxtb z0.s, p0/m, z0.s
SXTB Z0.S, P0/M, Z0.S
sxtb z1.s, p0/m, z0.s
SXTB Z1.S, P0/M, Z0.S
sxtb z31.s, p0/m, z0.s
SXTB Z31.S, P0/M, Z0.S
sxtb z0.s, p2/m, z0.s
SXTB Z0.S, P2/M, Z0.S
sxtb z0.s, p7/m, z0.s
SXTB Z0.S, P7/M, Z0.S
sxtb z0.s, p0/m, z3.s
SXTB Z0.S, P0/M, Z3.S
sxtb z0.s, p0/m, z31.s
SXTB Z0.S, P0/M, Z31.S
sxtb z0.d, p0/m, z0.d
SXTB Z0.D, P0/M, Z0.D
sxtb z1.d, p0/m, z0.d
SXTB Z1.D, P0/M, Z0.D
sxtb z31.d, p0/m, z0.d
SXTB Z31.D, P0/M, Z0.D
sxtb z0.d, p2/m, z0.d
SXTB Z0.D, P2/M, Z0.D
sxtb z0.d, p7/m, z0.d
SXTB Z0.D, P7/M, Z0.D
sxtb z0.d, p0/m, z3.d
SXTB Z0.D, P0/M, Z3.D
sxtb z0.d, p0/m, z31.d
SXTB Z0.D, P0/M, Z31.D
sxth z0.s, p0/m, z0.s
SXTH Z0.S, P0/M, Z0.S
sxth z1.s, p0/m, z0.s
SXTH Z1.S, P0/M, Z0.S
sxth z31.s, p0/m, z0.s
SXTH Z31.S, P0/M, Z0.S
sxth z0.s, p2/m, z0.s
SXTH Z0.S, P2/M, Z0.S
sxth z0.s, p7/m, z0.s
SXTH Z0.S, P7/M, Z0.S
sxth z0.s, p0/m, z3.s
SXTH Z0.S, P0/M, Z3.S
sxth z0.s, p0/m, z31.s
SXTH Z0.S, P0/M, Z31.S
sxth z0.d, p0/m, z0.d
SXTH Z0.D, P0/M, Z0.D
sxth z1.d, p0/m, z0.d
SXTH Z1.D, P0/M, Z0.D
sxth z31.d, p0/m, z0.d
SXTH Z31.D, P0/M, Z0.D
sxth z0.d, p2/m, z0.d
SXTH Z0.D, P2/M, Z0.D
sxth z0.d, p7/m, z0.d
SXTH Z0.D, P7/M, Z0.D
sxth z0.d, p0/m, z3.d
SXTH Z0.D, P0/M, Z3.D
sxth z0.d, p0/m, z31.d
SXTH Z0.D, P0/M, Z31.D
sxtw z0.d, p0/m, z0.d
SXTW Z0.D, P0/M, Z0.D
sxtw z1.d, p0/m, z0.d
SXTW Z1.D, P0/M, Z0.D
sxtw z31.d, p0/m, z0.d
SXTW Z31.D, P0/M, Z0.D
sxtw z0.d, p2/m, z0.d
SXTW Z0.D, P2/M, Z0.D
sxtw z0.d, p7/m, z0.d
SXTW Z0.D, P7/M, Z0.D
sxtw z0.d, p0/m, z3.d
SXTW Z0.D, P0/M, Z3.D
sxtw z0.d, p0/m, z31.d
SXTW Z0.D, P0/M, Z31.D
tbl z0.b, z0.b, z0.b
tbl z0.b, {z0.b}, z0.b
TBL Z0.B, {Z0.B}, Z0.B
tbl z1.b, {z0.b}, z0.b
TBL Z1.B, {Z0.B}, Z0.B
tbl z31.b, {z0.b}, z0.b
TBL Z31.B, {Z0.B}, Z0.B
tbl z0.b, z2.b, z0.b
tbl z0.b, {z2.b}, z0.b
TBL Z0.B, {Z2.B}, Z0.B
tbl z0.b, z31.b, z0.b
tbl z0.b, {z31.b}, z0.b
TBL Z0.B, {Z31.B}, Z0.B
tbl z0.b, {z0.b}, z3.b
TBL Z0.B, {Z0.B}, Z3.B
tbl z0.b, {z0.b}, z31.b
TBL Z0.B, {Z0.B}, Z31.B
tbl z0.h, z0.h, z0.h
tbl z0.h, {z0.h}, z0.h
TBL Z0.H, {Z0.H}, Z0.H
tbl z1.h, {z0.h}, z0.h
TBL Z1.H, {Z0.H}, Z0.H
tbl z31.h, {z0.h}, z0.h
TBL Z31.H, {Z0.H}, Z0.H
tbl z0.h, z2.h, z0.h
tbl z0.h, {z2.h}, z0.h
TBL Z0.H, {Z2.H}, Z0.H
tbl z0.h, z31.h, z0.h
tbl z0.h, {z31.h}, z0.h
TBL Z0.H, {Z31.H}, Z0.H
tbl z0.h, {z0.h}, z3.h
TBL Z0.H, {Z0.H}, Z3.H
tbl z0.h, {z0.h}, z31.h
TBL Z0.H, {Z0.H}, Z31.H
tbl z0.s, z0.s, z0.s
tbl z0.s, {z0.s}, z0.s
TBL Z0.S, {Z0.S}, Z0.S
tbl z1.s, {z0.s}, z0.s
TBL Z1.S, {Z0.S}, Z0.S
tbl z31.s, {z0.s}, z0.s
TBL Z31.S, {Z0.S}, Z0.S
tbl z0.s, z2.s, z0.s
tbl z0.s, {z2.s}, z0.s
TBL Z0.S, {Z2.S}, Z0.S
tbl z0.s, z31.s, z0.s
tbl z0.s, {z31.s}, z0.s
TBL Z0.S, {Z31.S}, Z0.S
tbl z0.s, {z0.s}, z3.s
TBL Z0.S, {Z0.S}, Z3.S
tbl z0.s, {z0.s}, z31.s
TBL Z0.S, {Z0.S}, Z31.S
tbl z0.d, z0.d, z0.d
tbl z0.d, {z0.d}, z0.d
TBL Z0.D, {Z0.D}, Z0.D
tbl z1.d, {z0.d}, z0.d
TBL Z1.D, {Z0.D}, Z0.D
tbl z31.d, {z0.d}, z0.d
TBL Z31.D, {Z0.D}, Z0.D
tbl z0.d, z2.d, z0.d
tbl z0.d, {z2.d}, z0.d
TBL Z0.D, {Z2.D}, Z0.D
tbl z0.d, z31.d, z0.d
tbl z0.d, {z31.d}, z0.d
TBL Z0.D, {Z31.D}, Z0.D
tbl z0.d, {z0.d}, z3.d
TBL Z0.D, {Z0.D}, Z3.D
tbl z0.d, {z0.d}, z31.d
TBL Z0.D, {Z0.D}, Z31.D
trn1 p0.b, p0.b, p0.b
TRN1 P0.B, P0.B, P0.B
trn1 p1.b, p0.b, p0.b
TRN1 P1.B, P0.B, P0.B
trn1 p15.b, p0.b, p0.b
TRN1 P15.B, P0.B, P0.B
trn1 p0.b, p2.b, p0.b
TRN1 P0.B, P2.B, P0.B
trn1 p0.b, p15.b, p0.b
TRN1 P0.B, P15.B, P0.B
trn1 p0.b, p0.b, p3.b
TRN1 P0.B, P0.B, P3.B
trn1 p0.b, p0.b, p15.b
TRN1 P0.B, P0.B, P15.B
trn1 p0.h, p0.h, p0.h
TRN1 P0.H, P0.H, P0.H
trn1 p1.h, p0.h, p0.h
TRN1 P1.H, P0.H, P0.H
trn1 p15.h, p0.h, p0.h
TRN1 P15.H, P0.H, P0.H
trn1 p0.h, p2.h, p0.h
TRN1 P0.H, P2.H, P0.H
trn1 p0.h, p15.h, p0.h
TRN1 P0.H, P15.H, P0.H
trn1 p0.h, p0.h, p3.h
TRN1 P0.H, P0.H, P3.H
trn1 p0.h, p0.h, p15.h
TRN1 P0.H, P0.H, P15.H
trn1 p0.s, p0.s, p0.s
TRN1 P0.S, P0.S, P0.S
trn1 p1.s, p0.s, p0.s
TRN1 P1.S, P0.S, P0.S
trn1 p15.s, p0.s, p0.s
TRN1 P15.S, P0.S, P0.S
trn1 p0.s, p2.s, p0.s
TRN1 P0.S, P2.S, P0.S
trn1 p0.s, p15.s, p0.s
TRN1 P0.S, P15.S, P0.S
trn1 p0.s, p0.s, p3.s
TRN1 P0.S, P0.S, P3.S
trn1 p0.s, p0.s, p15.s
TRN1 P0.S, P0.S, P15.S
trn1 p0.d, p0.d, p0.d
TRN1 P0.D, P0.D, P0.D
trn1 p1.d, p0.d, p0.d
TRN1 P1.D, P0.D, P0.D
trn1 p15.d, p0.d, p0.d
TRN1 P15.D, P0.D, P0.D
trn1 p0.d, p2.d, p0.d
TRN1 P0.D, P2.D, P0.D
trn1 p0.d, p15.d, p0.d
TRN1 P0.D, P15.D, P0.D
trn1 p0.d, p0.d, p3.d
TRN1 P0.D, P0.D, P3.D
trn1 p0.d, p0.d, p15.d
TRN1 P0.D, P0.D, P15.D
trn1 z0.b, z0.b, z0.b
TRN1 Z0.B, Z0.B, Z0.B
trn1 z1.b, z0.b, z0.b
TRN1 Z1.B, Z0.B, Z0.B
trn1 z31.b, z0.b, z0.b
TRN1 Z31.B, Z0.B, Z0.B
trn1 z0.b, z2.b, z0.b
TRN1 Z0.B, Z2.B, Z0.B
trn1 z0.b, z31.b, z0.b
TRN1 Z0.B, Z31.B, Z0.B
trn1 z0.b, z0.b, z3.b
TRN1 Z0.B, Z0.B, Z3.B
trn1 z0.b, z0.b, z31.b
TRN1 Z0.B, Z0.B, Z31.B
trn1 z0.h, z0.h, z0.h
TRN1 Z0.H, Z0.H, Z0.H
trn1 z1.h, z0.h, z0.h
TRN1 Z1.H, Z0.H, Z0.H
trn1 z31.h, z0.h, z0.h
TRN1 Z31.H, Z0.H, Z0.H
trn1 z0.h, z2.h, z0.h
TRN1 Z0.H, Z2.H, Z0.H
trn1 z0.h, z31.h, z0.h
TRN1 Z0.H, Z31.H, Z0.H
trn1 z0.h, z0.h, z3.h
TRN1 Z0.H, Z0.H, Z3.H
trn1 z0.h, z0.h, z31.h
TRN1 Z0.H, Z0.H, Z31.H
trn1 z0.s, z0.s, z0.s
TRN1 Z0.S, Z0.S, Z0.S
trn1 z1.s, z0.s, z0.s
TRN1 Z1.S, Z0.S, Z0.S
trn1 z31.s, z0.s, z0.s
TRN1 Z31.S, Z0.S, Z0.S
trn1 z0.s, z2.s, z0.s
TRN1 Z0.S, Z2.S, Z0.S
trn1 z0.s, z31.s, z0.s
TRN1 Z0.S, Z31.S, Z0.S
trn1 z0.s, z0.s, z3.s
TRN1 Z0.S, Z0.S, Z3.S
trn1 z0.s, z0.s, z31.s
TRN1 Z0.S, Z0.S, Z31.S
trn1 z0.d, z0.d, z0.d
TRN1 Z0.D, Z0.D, Z0.D
trn1 z1.d, z0.d, z0.d
TRN1 Z1.D, Z0.D, Z0.D
trn1 z31.d, z0.d, z0.d
TRN1 Z31.D, Z0.D, Z0.D
trn1 z0.d, z2.d, z0.d
TRN1 Z0.D, Z2.D, Z0.D
trn1 z0.d, z31.d, z0.d
TRN1 Z0.D, Z31.D, Z0.D
trn1 z0.d, z0.d, z3.d
TRN1 Z0.D, Z0.D, Z3.D
trn1 z0.d, z0.d, z31.d
TRN1 Z0.D, Z0.D, Z31.D
trn2 p0.b, p0.b, p0.b
TRN2 P0.B, P0.B, P0.B
trn2 p1.b, p0.b, p0.b
TRN2 P1.B, P0.B, P0.B
trn2 p15.b, p0.b, p0.b
TRN2 P15.B, P0.B, P0.B
trn2 p0.b, p2.b, p0.b
TRN2 P0.B, P2.B, P0.B
trn2 p0.b, p15.b, p0.b
TRN2 P0.B, P15.B, P0.B
trn2 p0.b, p0.b, p3.b
TRN2 P0.B, P0.B, P3.B
trn2 p0.b, p0.b, p15.b
TRN2 P0.B, P0.B, P15.B
trn2 p0.h, p0.h, p0.h
TRN2 P0.H, P0.H, P0.H
trn2 p1.h, p0.h, p0.h
TRN2 P1.H, P0.H, P0.H
trn2 p15.h, p0.h, p0.h
TRN2 P15.H, P0.H, P0.H
trn2 p0.h, p2.h, p0.h
TRN2 P0.H, P2.H, P0.H
trn2 p0.h, p15.h, p0.h
TRN2 P0.H, P15.H, P0.H
trn2 p0.h, p0.h, p3.h
TRN2 P0.H, P0.H, P3.H
trn2 p0.h, p0.h, p15.h
TRN2 P0.H, P0.H, P15.H
trn2 p0.s, p0.s, p0.s
TRN2 P0.S, P0.S, P0.S
trn2 p1.s, p0.s, p0.s
TRN2 P1.S, P0.S, P0.S
trn2 p15.s, p0.s, p0.s
TRN2 P15.S, P0.S, P0.S
trn2 p0.s, p2.s, p0.s
TRN2 P0.S, P2.S, P0.S
trn2 p0.s, p15.s, p0.s
TRN2 P0.S, P15.S, P0.S
trn2 p0.s, p0.s, p3.s
TRN2 P0.S, P0.S, P3.S
trn2 p0.s, p0.s, p15.s
TRN2 P0.S, P0.S, P15.S
trn2 p0.d, p0.d, p0.d
TRN2 P0.D, P0.D, P0.D
trn2 p1.d, p0.d, p0.d
TRN2 P1.D, P0.D, P0.D
trn2 p15.d, p0.d, p0.d
TRN2 P15.D, P0.D, P0.D
trn2 p0.d, p2.d, p0.d
TRN2 P0.D, P2.D, P0.D
trn2 p0.d, p15.d, p0.d
TRN2 P0.D, P15.D, P0.D
trn2 p0.d, p0.d, p3.d
TRN2 P0.D, P0.D, P3.D
trn2 p0.d, p0.d, p15.d
TRN2 P0.D, P0.D, P15.D
trn2 z0.b, z0.b, z0.b
TRN2 Z0.B, Z0.B, Z0.B
trn2 z1.b, z0.b, z0.b
TRN2 Z1.B, Z0.B, Z0.B
trn2 z31.b, z0.b, z0.b
TRN2 Z31.B, Z0.B, Z0.B
trn2 z0.b, z2.b, z0.b
TRN2 Z0.B, Z2.B, Z0.B
trn2 z0.b, z31.b, z0.b
TRN2 Z0.B, Z31.B, Z0.B
trn2 z0.b, z0.b, z3.b
TRN2 Z0.B, Z0.B, Z3.B
trn2 z0.b, z0.b, z31.b
TRN2 Z0.B, Z0.B, Z31.B
trn2 z0.h, z0.h, z0.h
TRN2 Z0.H, Z0.H, Z0.H
trn2 z1.h, z0.h, z0.h
TRN2 Z1.H, Z0.H, Z0.H
trn2 z31.h, z0.h, z0.h
TRN2 Z31.H, Z0.H, Z0.H
trn2 z0.h, z2.h, z0.h
TRN2 Z0.H, Z2.H, Z0.H
trn2 z0.h, z31.h, z0.h
TRN2 Z0.H, Z31.H, Z0.H
trn2 z0.h, z0.h, z3.h
TRN2 Z0.H, Z0.H, Z3.H
trn2 z0.h, z0.h, z31.h
TRN2 Z0.H, Z0.H, Z31.H
trn2 z0.s, z0.s, z0.s
TRN2 Z0.S, Z0.S, Z0.S
trn2 z1.s, z0.s, z0.s
TRN2 Z1.S, Z0.S, Z0.S
trn2 z31.s, z0.s, z0.s
TRN2 Z31.S, Z0.S, Z0.S
trn2 z0.s, z2.s, z0.s
TRN2 Z0.S, Z2.S, Z0.S
trn2 z0.s, z31.s, z0.s
TRN2 Z0.S, Z31.S, Z0.S
trn2 z0.s, z0.s, z3.s
TRN2 Z0.S, Z0.S, Z3.S
trn2 z0.s, z0.s, z31.s
TRN2 Z0.S, Z0.S, Z31.S
trn2 z0.d, z0.d, z0.d
TRN2 Z0.D, Z0.D, Z0.D
trn2 z1.d, z0.d, z0.d
TRN2 Z1.D, Z0.D, Z0.D
trn2 z31.d, z0.d, z0.d
TRN2 Z31.D, Z0.D, Z0.D
trn2 z0.d, z2.d, z0.d
TRN2 Z0.D, Z2.D, Z0.D
trn2 z0.d, z31.d, z0.d
TRN2 Z0.D, Z31.D, Z0.D
trn2 z0.d, z0.d, z3.d
TRN2 Z0.D, Z0.D, Z3.D
trn2 z0.d, z0.d, z31.d
TRN2 Z0.D, Z0.D, Z31.D
uabd z0.b, p0/m, z0.b, z0.b
UABD Z0.B, P0/M, Z0.B, Z0.B
uabd z1.b, p0/m, z1.b, z0.b
UABD Z1.B, P0/M, Z1.B, Z0.B
uabd z31.b, p0/m, z31.b, z0.b
UABD Z31.B, P0/M, Z31.B, Z0.B
uabd z0.b, p2/m, z0.b, z0.b
UABD Z0.B, P2/M, Z0.B, Z0.B
uabd z0.b, p7/m, z0.b, z0.b
UABD Z0.B, P7/M, Z0.B, Z0.B
uabd z3.b, p0/m, z3.b, z0.b
UABD Z3.B, P0/M, Z3.B, Z0.B
uabd z0.b, p0/m, z0.b, z4.b
UABD Z0.B, P0/M, Z0.B, Z4.B
uabd z0.b, p0/m, z0.b, z31.b
UABD Z0.B, P0/M, Z0.B, Z31.B
uabd z0.h, p0/m, z0.h, z0.h
UABD Z0.H, P0/M, Z0.H, Z0.H
uabd z1.h, p0/m, z1.h, z0.h
UABD Z1.H, P0/M, Z1.H, Z0.H
uabd z31.h, p0/m, z31.h, z0.h
UABD Z31.H, P0/M, Z31.H, Z0.H
uabd z0.h, p2/m, z0.h, z0.h
UABD Z0.H, P2/M, Z0.H, Z0.H
uabd z0.h, p7/m, z0.h, z0.h
UABD Z0.H, P7/M, Z0.H, Z0.H
uabd z3.h, p0/m, z3.h, z0.h
UABD Z3.H, P0/M, Z3.H, Z0.H
uabd z0.h, p0/m, z0.h, z4.h
UABD Z0.H, P0/M, Z0.H, Z4.H
uabd z0.h, p0/m, z0.h, z31.h
UABD Z0.H, P0/M, Z0.H, Z31.H
uabd z0.s, p0/m, z0.s, z0.s
UABD Z0.S, P0/M, Z0.S, Z0.S
uabd z1.s, p0/m, z1.s, z0.s
UABD Z1.S, P0/M, Z1.S, Z0.S
uabd z31.s, p0/m, z31.s, z0.s
UABD Z31.S, P0/M, Z31.S, Z0.S
uabd z0.s, p2/m, z0.s, z0.s
UABD Z0.S, P2/M, Z0.S, Z0.S
uabd z0.s, p7/m, z0.s, z0.s
UABD Z0.S, P7/M, Z0.S, Z0.S
uabd z3.s, p0/m, z3.s, z0.s
UABD Z3.S, P0/M, Z3.S, Z0.S
uabd z0.s, p0/m, z0.s, z4.s
UABD Z0.S, P0/M, Z0.S, Z4.S
uabd z0.s, p0/m, z0.s, z31.s
UABD Z0.S, P0/M, Z0.S, Z31.S
uabd z0.d, p0/m, z0.d, z0.d
UABD Z0.D, P0/M, Z0.D, Z0.D
uabd z1.d, p0/m, z1.d, z0.d
UABD Z1.D, P0/M, Z1.D, Z0.D
uabd z31.d, p0/m, z31.d, z0.d
UABD Z31.D, P0/M, Z31.D, Z0.D
uabd z0.d, p2/m, z0.d, z0.d
UABD Z0.D, P2/M, Z0.D, Z0.D
uabd z0.d, p7/m, z0.d, z0.d
UABD Z0.D, P7/M, Z0.D, Z0.D
uabd z3.d, p0/m, z3.d, z0.d
UABD Z3.D, P0/M, Z3.D, Z0.D
uabd z0.d, p0/m, z0.d, z4.d
UABD Z0.D, P0/M, Z0.D, Z4.D
uabd z0.d, p0/m, z0.d, z31.d
UABD Z0.D, P0/M, Z0.D, Z31.D
uaddv d0, p0, z0.b
UADDV D0, P0, Z0.B
uaddv d1, p0, z0.b
UADDV D1, P0, Z0.B
uaddv d31, p0, z0.b
UADDV D31, P0, Z0.B
uaddv d0, p2, z0.b
UADDV D0, P2, Z0.B
uaddv d0, p7, z0.b
UADDV D0, P7, Z0.B
uaddv d0, p0, z3.b
UADDV D0, P0, Z3.B
uaddv d0, p0, z31.b
UADDV D0, P0, Z31.B
uaddv d0, p0, z0.h
UADDV D0, P0, Z0.H
uaddv d1, p0, z0.h
UADDV D1, P0, Z0.H
uaddv d31, p0, z0.h
UADDV D31, P0, Z0.H
uaddv d0, p2, z0.h
UADDV D0, P2, Z0.H
uaddv d0, p7, z0.h
UADDV D0, P7, Z0.H
uaddv d0, p0, z3.h
UADDV D0, P0, Z3.H
uaddv d0, p0, z31.h
UADDV D0, P0, Z31.H
uaddv d0, p0, z0.s
UADDV D0, P0, Z0.S
uaddv d1, p0, z0.s
UADDV D1, P0, Z0.S
uaddv d31, p0, z0.s
UADDV D31, P0, Z0.S
uaddv d0, p2, z0.s
UADDV D0, P2, Z0.S
uaddv d0, p7, z0.s
UADDV D0, P7, Z0.S
uaddv d0, p0, z3.s
UADDV D0, P0, Z3.S
uaddv d0, p0, z31.s
UADDV D0, P0, Z31.S
uaddv d0, p0, z0.d
UADDV D0, P0, Z0.D
uaddv d1, p0, z0.d
UADDV D1, P0, Z0.D
uaddv d31, p0, z0.d
UADDV D31, P0, Z0.D
uaddv d0, p2, z0.d
UADDV D0, P2, Z0.D
uaddv d0, p7, z0.d
UADDV D0, P7, Z0.D
uaddv d0, p0, z3.d
UADDV D0, P0, Z3.D
uaddv d0, p0, z31.d
UADDV D0, P0, Z31.D
ucvtf z0.h, p0/m, z0.h
UCVTF Z0.H, P0/M, Z0.H
ucvtf z1.h, p0/m, z0.h
UCVTF Z1.H, P0/M, Z0.H
ucvtf z31.h, p0/m, z0.h
UCVTF Z31.H, P0/M, Z0.H
ucvtf z0.h, p2/m, z0.h
UCVTF Z0.H, P2/M, Z0.H
ucvtf z0.h, p7/m, z0.h
UCVTF Z0.H, P7/M, Z0.H
ucvtf z0.h, p0/m, z3.h
UCVTF Z0.H, P0/M, Z3.H
ucvtf z0.h, p0/m, z31.h
UCVTF Z0.H, P0/M, Z31.H
ucvtf z0.h, p0/m, z0.s
UCVTF Z0.H, P0/M, Z0.S
ucvtf z1.h, p0/m, z0.s
UCVTF Z1.H, P0/M, Z0.S
ucvtf z31.h, p0/m, z0.s
UCVTF Z31.H, P0/M, Z0.S
ucvtf z0.h, p2/m, z0.s
UCVTF Z0.H, P2/M, Z0.S
ucvtf z0.h, p7/m, z0.s
UCVTF Z0.H, P7/M, Z0.S
ucvtf z0.h, p0/m, z3.s
UCVTF Z0.H, P0/M, Z3.S
ucvtf z0.h, p0/m, z31.s
UCVTF Z0.H, P0/M, Z31.S
ucvtf z0.s, p0/m, z0.s
UCVTF Z0.S, P0/M, Z0.S
ucvtf z1.s, p0/m, z0.s
UCVTF Z1.S, P0/M, Z0.S
ucvtf z31.s, p0/m, z0.s
UCVTF Z31.S, P0/M, Z0.S
ucvtf z0.s, p2/m, z0.s
UCVTF Z0.S, P2/M, Z0.S
ucvtf z0.s, p7/m, z0.s
UCVTF Z0.S, P7/M, Z0.S
ucvtf z0.s, p0/m, z3.s
UCVTF Z0.S, P0/M, Z3.S
ucvtf z0.s, p0/m, z31.s
UCVTF Z0.S, P0/M, Z31.S
ucvtf z0.d, p0/m, z0.s
UCVTF Z0.D, P0/M, Z0.S
ucvtf z1.d, p0/m, z0.s
UCVTF Z1.D, P0/M, Z0.S
ucvtf z31.d, p0/m, z0.s
UCVTF Z31.D, P0/M, Z0.S
ucvtf z0.d, p2/m, z0.s
UCVTF Z0.D, P2/M, Z0.S
ucvtf z0.d, p7/m, z0.s
UCVTF Z0.D, P7/M, Z0.S
ucvtf z0.d, p0/m, z3.s
UCVTF Z0.D, P0/M, Z3.S
ucvtf z0.d, p0/m, z31.s
UCVTF Z0.D, P0/M, Z31.S
ucvtf z0.h, p0/m, z0.d
UCVTF Z0.H, P0/M, Z0.D
ucvtf z1.h, p0/m, z0.d
UCVTF Z1.H, P0/M, Z0.D
ucvtf z31.h, p0/m, z0.d
UCVTF Z31.H, P0/M, Z0.D
ucvtf z0.h, p2/m, z0.d
UCVTF Z0.H, P2/M, Z0.D
ucvtf z0.h, p7/m, z0.d
UCVTF Z0.H, P7/M, Z0.D
ucvtf z0.h, p0/m, z3.d
UCVTF Z0.H, P0/M, Z3.D
ucvtf z0.h, p0/m, z31.d
UCVTF Z0.H, P0/M, Z31.D
ucvtf z0.s, p0/m, z0.d
UCVTF Z0.S, P0/M, Z0.D
ucvtf z1.s, p0/m, z0.d
UCVTF Z1.S, P0/M, Z0.D
ucvtf z31.s, p0/m, z0.d
UCVTF Z31.S, P0/M, Z0.D
ucvtf z0.s, p2/m, z0.d
UCVTF Z0.S, P2/M, Z0.D
ucvtf z0.s, p7/m, z0.d
UCVTF Z0.S, P7/M, Z0.D
ucvtf z0.s, p0/m, z3.d
UCVTF Z0.S, P0/M, Z3.D
ucvtf z0.s, p0/m, z31.d
UCVTF Z0.S, P0/M, Z31.D
ucvtf z0.d, p0/m, z0.d
UCVTF Z0.D, P0/M, Z0.D
ucvtf z1.d, p0/m, z0.d
UCVTF Z1.D, P0/M, Z0.D
ucvtf z31.d, p0/m, z0.d
UCVTF Z31.D, P0/M, Z0.D
ucvtf z0.d, p2/m, z0.d
UCVTF Z0.D, P2/M, Z0.D
ucvtf z0.d, p7/m, z0.d
UCVTF Z0.D, P7/M, Z0.D
ucvtf z0.d, p0/m, z3.d
UCVTF Z0.D, P0/M, Z3.D
ucvtf z0.d, p0/m, z31.d
UCVTF Z0.D, P0/M, Z31.D
udiv z0.s, p0/m, z0.s, z0.s
UDIV Z0.S, P0/M, Z0.S, Z0.S
udiv z1.s, p0/m, z1.s, z0.s
UDIV Z1.S, P0/M, Z1.S, Z0.S
udiv z31.s, p0/m, z31.s, z0.s
UDIV Z31.S, P0/M, Z31.S, Z0.S
udiv z0.s, p2/m, z0.s, z0.s
UDIV Z0.S, P2/M, Z0.S, Z0.S
udiv z0.s, p7/m, z0.s, z0.s
UDIV Z0.S, P7/M, Z0.S, Z0.S
udiv z3.s, p0/m, z3.s, z0.s
UDIV Z3.S, P0/M, Z3.S, Z0.S
udiv z0.s, p0/m, z0.s, z4.s
UDIV Z0.S, P0/M, Z0.S, Z4.S
udiv z0.s, p0/m, z0.s, z31.s
UDIV Z0.S, P0/M, Z0.S, Z31.S
udiv z0.d, p0/m, z0.d, z0.d
UDIV Z0.D, P0/M, Z0.D, Z0.D
udiv z1.d, p0/m, z1.d, z0.d
UDIV Z1.D, P0/M, Z1.D, Z0.D
udiv z31.d, p0/m, z31.d, z0.d
UDIV Z31.D, P0/M, Z31.D, Z0.D
udiv z0.d, p2/m, z0.d, z0.d
UDIV Z0.D, P2/M, Z0.D, Z0.D
udiv z0.d, p7/m, z0.d, z0.d
UDIV Z0.D, P7/M, Z0.D, Z0.D
udiv z3.d, p0/m, z3.d, z0.d
UDIV Z3.D, P0/M, Z3.D, Z0.D
udiv z0.d, p0/m, z0.d, z4.d
UDIV Z0.D, P0/M, Z0.D, Z4.D
udiv z0.d, p0/m, z0.d, z31.d
UDIV Z0.D, P0/M, Z0.D, Z31.D
udivr z0.s, p0/m, z0.s, z0.s
UDIVR Z0.S, P0/M, Z0.S, Z0.S
udivr z1.s, p0/m, z1.s, z0.s
UDIVR Z1.S, P0/M, Z1.S, Z0.S
udivr z31.s, p0/m, z31.s, z0.s
UDIVR Z31.S, P0/M, Z31.S, Z0.S
udivr z0.s, p2/m, z0.s, z0.s
UDIVR Z0.S, P2/M, Z0.S, Z0.S
udivr z0.s, p7/m, z0.s, z0.s
UDIVR Z0.S, P7/M, Z0.S, Z0.S
udivr z3.s, p0/m, z3.s, z0.s
UDIVR Z3.S, P0/M, Z3.S, Z0.S
udivr z0.s, p0/m, z0.s, z4.s
UDIVR Z0.S, P0/M, Z0.S, Z4.S
udivr z0.s, p0/m, z0.s, z31.s
UDIVR Z0.S, P0/M, Z0.S, Z31.S
udivr z0.d, p0/m, z0.d, z0.d
UDIVR Z0.D, P0/M, Z0.D, Z0.D
udivr z1.d, p0/m, z1.d, z0.d
UDIVR Z1.D, P0/M, Z1.D, Z0.D
udivr z31.d, p0/m, z31.d, z0.d
UDIVR Z31.D, P0/M, Z31.D, Z0.D
udivr z0.d, p2/m, z0.d, z0.d
UDIVR Z0.D, P2/M, Z0.D, Z0.D
udivr z0.d, p7/m, z0.d, z0.d
UDIVR Z0.D, P7/M, Z0.D, Z0.D
udivr z3.d, p0/m, z3.d, z0.d
UDIVR Z3.D, P0/M, Z3.D, Z0.D
udivr z0.d, p0/m, z0.d, z4.d
UDIVR Z0.D, P0/M, Z0.D, Z4.D
udivr z0.d, p0/m, z0.d, z31.d
UDIVR Z0.D, P0/M, Z0.D, Z31.D
udot z0.s, z0.b, z0.b
UDOT Z0.S, Z0.B, Z0.B
udot z1.s, z0.b, z0.b
UDOT Z1.S, Z0.B, Z0.B
udot z31.s, z0.b, z0.b
UDOT Z31.S, Z0.B, Z0.B
udot z0.s, z2.b, z0.b
UDOT Z0.S, Z2.B, Z0.B
udot z0.s, z31.b, z0.b
UDOT Z0.S, Z31.B, Z0.B
udot z0.s, z0.b, z3.b
UDOT Z0.S, Z0.B, Z3.B
udot z0.s, z0.b, z31.b
UDOT Z0.S, Z0.B, Z31.B
udot z0.d, z0.h, z0.h
UDOT Z0.D, Z0.H, Z0.H
udot z1.d, z0.h, z0.h
UDOT Z1.D, Z0.H, Z0.H
udot z31.d, z0.h, z0.h
UDOT Z31.D, Z0.H, Z0.H
udot z0.d, z2.h, z0.h
UDOT Z0.D, Z2.H, Z0.H
udot z0.d, z31.h, z0.h
UDOT Z0.D, Z31.H, Z0.H
udot z0.d, z0.h, z3.h
UDOT Z0.D, Z0.H, Z3.H
udot z0.d, z0.h, z31.h
UDOT Z0.D, Z0.H, Z31.H
udot z0.s, z0.b, z0.b[0]
UDOT Z0.S, Z0.B, Z0.B[0]
udot z1.s, z0.b, z0.b[0]
UDOT Z1.S, Z0.B, Z0.B[0]
udot z31.s, z0.b, z0.b[0]
UDOT Z31.S, Z0.B, Z0.B[0]
udot z0.s, z2.b, z0.b[0]
UDOT Z0.S, Z2.B, Z0.B[0]
udot z0.s, z31.b, z0.b[0]
UDOT Z0.S, Z31.B, Z0.B[0]
udot z0.s, z0.b, z3.b[0]
UDOT Z0.S, Z0.B, Z3.B[0]
udot z0.s, z0.b, z7.b[0]
UDOT Z0.S, Z0.B, Z7.B[0]
udot z0.s, z0.b, z0.b[1]
UDOT Z0.S, Z0.B, Z0.B[1]
udot z0.s, z0.b, z4.b[1]
UDOT Z0.S, Z0.B, Z4.B[1]
udot z0.s, z0.b, z3.b[2]
UDOT Z0.S, Z0.B, Z3.B[2]
udot z0.s, z0.b, z0.b[3]
UDOT Z0.S, Z0.B, Z0.B[3]
udot z0.s, z0.b, z5.b[3]
UDOT Z0.S, Z0.B, Z5.B[3]
udot z0.d, z0.h, z0.h[0]
UDOT Z0.D, Z0.H, Z0.H[0]
udot z1.d, z0.h, z0.h[0]
UDOT Z1.D, Z0.H, Z0.H[0]
udot z31.d, z0.h, z0.h[0]
UDOT Z31.D, Z0.H, Z0.H[0]
udot z0.d, z2.h, z0.h[0]
UDOT Z0.D, Z2.H, Z0.H[0]
udot z0.d, z31.h, z0.h[0]
UDOT Z0.D, Z31.H, Z0.H[0]
udot z0.d, z0.h, z3.h[0]
UDOT Z0.D, Z0.H, Z3.H[0]
udot z0.d, z0.h, z15.h[0]
UDOT Z0.D, Z0.H, Z15.H[0]
udot z0.d, z0.h, z0.h[1]
UDOT Z0.D, Z0.H, Z0.H[1]
udot z0.d, z0.h, z11.h[1]
UDOT Z0.D, Z0.H, Z11.H[1]
umax z0.b, z0.b, #0
UMAX Z0.B, Z0.B, #0
umax z1.b, z1.b, #0
UMAX Z1.B, Z1.B, #0
umax z31.b, z31.b, #0
UMAX Z31.B, Z31.B, #0
umax z2.b, z2.b, #0
UMAX Z2.B, Z2.B, #0
umax z0.b, z0.b, #127
UMAX Z0.B, Z0.B, #127
umax z0.b, z0.b, #128
UMAX Z0.B, Z0.B, #128
umax z0.b, z0.b, #129
UMAX Z0.B, Z0.B, #129
umax z0.b, z0.b, #255
UMAX Z0.B, Z0.B, #255
umax z0.h, z0.h, #0
UMAX Z0.H, Z0.H, #0
umax z1.h, z1.h, #0
UMAX Z1.H, Z1.H, #0
umax z31.h, z31.h, #0
UMAX Z31.H, Z31.H, #0
umax z2.h, z2.h, #0
UMAX Z2.H, Z2.H, #0
umax z0.h, z0.h, #127
UMAX Z0.H, Z0.H, #127
umax z0.h, z0.h, #128
UMAX Z0.H, Z0.H, #128
umax z0.h, z0.h, #129
UMAX Z0.H, Z0.H, #129
umax z0.h, z0.h, #255
UMAX Z0.H, Z0.H, #255
umax z0.s, z0.s, #0
UMAX Z0.S, Z0.S, #0
umax z1.s, z1.s, #0
UMAX Z1.S, Z1.S, #0
umax z31.s, z31.s, #0
UMAX Z31.S, Z31.S, #0
umax z2.s, z2.s, #0
UMAX Z2.S, Z2.S, #0
umax z0.s, z0.s, #127
UMAX Z0.S, Z0.S, #127
umax z0.s, z0.s, #128
UMAX Z0.S, Z0.S, #128
umax z0.s, z0.s, #129
UMAX Z0.S, Z0.S, #129
umax z0.s, z0.s, #255
UMAX Z0.S, Z0.S, #255
umax z0.d, z0.d, #0
UMAX Z0.D, Z0.D, #0
umax z1.d, z1.d, #0
UMAX Z1.D, Z1.D, #0
umax z31.d, z31.d, #0
UMAX Z31.D, Z31.D, #0
umax z2.d, z2.d, #0
UMAX Z2.D, Z2.D, #0
umax z0.d, z0.d, #127
UMAX Z0.D, Z0.D, #127
umax z0.d, z0.d, #128
UMAX Z0.D, Z0.D, #128
umax z0.d, z0.d, #129
UMAX Z0.D, Z0.D, #129
umax z0.d, z0.d, #255
UMAX Z0.D, Z0.D, #255
umax z0.b, p0/m, z0.b, z0.b
UMAX Z0.B, P0/M, Z0.B, Z0.B
umax z1.b, p0/m, z1.b, z0.b
UMAX Z1.B, P0/M, Z1.B, Z0.B
umax z31.b, p0/m, z31.b, z0.b
UMAX Z31.B, P0/M, Z31.B, Z0.B
umax z0.b, p2/m, z0.b, z0.b
UMAX Z0.B, P2/M, Z0.B, Z0.B
umax z0.b, p7/m, z0.b, z0.b
UMAX Z0.B, P7/M, Z0.B, Z0.B
umax z3.b, p0/m, z3.b, z0.b
UMAX Z3.B, P0/M, Z3.B, Z0.B
umax z0.b, p0/m, z0.b, z4.b
UMAX Z0.B, P0/M, Z0.B, Z4.B
umax z0.b, p0/m, z0.b, z31.b
UMAX Z0.B, P0/M, Z0.B, Z31.B
umax z0.h, p0/m, z0.h, z0.h
UMAX Z0.H, P0/M, Z0.H, Z0.H
umax z1.h, p0/m, z1.h, z0.h
UMAX Z1.H, P0/M, Z1.H, Z0.H
umax z31.h, p0/m, z31.h, z0.h
UMAX Z31.H, P0/M, Z31.H, Z0.H
umax z0.h, p2/m, z0.h, z0.h
UMAX Z0.H, P2/M, Z0.H, Z0.H
umax z0.h, p7/m, z0.h, z0.h
UMAX Z0.H, P7/M, Z0.H, Z0.H
umax z3.h, p0/m, z3.h, z0.h
UMAX Z3.H, P0/M, Z3.H, Z0.H
umax z0.h, p0/m, z0.h, z4.h
UMAX Z0.H, P0/M, Z0.H, Z4.H
umax z0.h, p0/m, z0.h, z31.h
UMAX Z0.H, P0/M, Z0.H, Z31.H
umax z0.s, p0/m, z0.s, z0.s
UMAX Z0.S, P0/M, Z0.S, Z0.S
umax z1.s, p0/m, z1.s, z0.s
UMAX Z1.S, P0/M, Z1.S, Z0.S
umax z31.s, p0/m, z31.s, z0.s
UMAX Z31.S, P0/M, Z31.S, Z0.S
umax z0.s, p2/m, z0.s, z0.s
UMAX Z0.S, P2/M, Z0.S, Z0.S
umax z0.s, p7/m, z0.s, z0.s
UMAX Z0.S, P7/M, Z0.S, Z0.S
umax z3.s, p0/m, z3.s, z0.s
UMAX Z3.S, P0/M, Z3.S, Z0.S
umax z0.s, p0/m, z0.s, z4.s
UMAX Z0.S, P0/M, Z0.S, Z4.S
umax z0.s, p0/m, z0.s, z31.s
UMAX Z0.S, P0/M, Z0.S, Z31.S
umax z0.d, p0/m, z0.d, z0.d
UMAX Z0.D, P0/M, Z0.D, Z0.D
umax z1.d, p0/m, z1.d, z0.d
UMAX Z1.D, P0/M, Z1.D, Z0.D
umax z31.d, p0/m, z31.d, z0.d
UMAX Z31.D, P0/M, Z31.D, Z0.D
umax z0.d, p2/m, z0.d, z0.d
UMAX Z0.D, P2/M, Z0.D, Z0.D
umax z0.d, p7/m, z0.d, z0.d
UMAX Z0.D, P7/M, Z0.D, Z0.D
umax z3.d, p0/m, z3.d, z0.d
UMAX Z3.D, P0/M, Z3.D, Z0.D
umax z0.d, p0/m, z0.d, z4.d
UMAX Z0.D, P0/M, Z0.D, Z4.D
umax z0.d, p0/m, z0.d, z31.d
UMAX Z0.D, P0/M, Z0.D, Z31.D
umaxv b0, p0, z0.b
UMAXV B0, P0, Z0.B
umaxv b1, p0, z0.b
UMAXV B1, P0, Z0.B
umaxv b31, p0, z0.b
UMAXV B31, P0, Z0.B
umaxv b0, p2, z0.b
UMAXV B0, P2, Z0.B
umaxv b0, p7, z0.b
UMAXV B0, P7, Z0.B
umaxv b0, p0, z3.b
UMAXV B0, P0, Z3.B
umaxv b0, p0, z31.b
UMAXV B0, P0, Z31.B
umaxv h0, p0, z0.h
UMAXV H0, P0, Z0.H
umaxv h1, p0, z0.h
UMAXV H1, P0, Z0.H
umaxv h31, p0, z0.h
UMAXV H31, P0, Z0.H
umaxv h0, p2, z0.h
UMAXV H0, P2, Z0.H
umaxv h0, p7, z0.h
UMAXV H0, P7, Z0.H
umaxv h0, p0, z3.h
UMAXV H0, P0, Z3.H
umaxv h0, p0, z31.h
UMAXV H0, P0, Z31.H
umaxv s0, p0, z0.s
UMAXV S0, P0, Z0.S
umaxv s1, p0, z0.s
UMAXV S1, P0, Z0.S
umaxv s31, p0, z0.s
UMAXV S31, P0, Z0.S
umaxv s0, p2, z0.s
UMAXV S0, P2, Z0.S
umaxv s0, p7, z0.s
UMAXV S0, P7, Z0.S
umaxv s0, p0, z3.s
UMAXV S0, P0, Z3.S
umaxv s0, p0, z31.s
UMAXV S0, P0, Z31.S
umaxv d0, p0, z0.d
UMAXV D0, P0, Z0.D
umaxv d1, p0, z0.d
UMAXV D1, P0, Z0.D
umaxv d31, p0, z0.d
UMAXV D31, P0, Z0.D
umaxv d0, p2, z0.d
UMAXV D0, P2, Z0.D
umaxv d0, p7, z0.d
UMAXV D0, P7, Z0.D
umaxv d0, p0, z3.d
UMAXV D0, P0, Z3.D
umaxv d0, p0, z31.d
UMAXV D0, P0, Z31.D
umin z0.b, z0.b, #0
UMIN Z0.B, Z0.B, #0
umin z1.b, z1.b, #0
UMIN Z1.B, Z1.B, #0
umin z31.b, z31.b, #0
UMIN Z31.B, Z31.B, #0
umin z2.b, z2.b, #0
UMIN Z2.B, Z2.B, #0
umin z0.b, z0.b, #127
UMIN Z0.B, Z0.B, #127
umin z0.b, z0.b, #128
UMIN Z0.B, Z0.B, #128
umin z0.b, z0.b, #129
UMIN Z0.B, Z0.B, #129
umin z0.b, z0.b, #255
UMIN Z0.B, Z0.B, #255
umin z0.h, z0.h, #0
UMIN Z0.H, Z0.H, #0
umin z1.h, z1.h, #0
UMIN Z1.H, Z1.H, #0
umin z31.h, z31.h, #0
UMIN Z31.H, Z31.H, #0
umin z2.h, z2.h, #0
UMIN Z2.H, Z2.H, #0
umin z0.h, z0.h, #127
UMIN Z0.H, Z0.H, #127
umin z0.h, z0.h, #128
UMIN Z0.H, Z0.H, #128
umin z0.h, z0.h, #129
UMIN Z0.H, Z0.H, #129
umin z0.h, z0.h, #255
UMIN Z0.H, Z0.H, #255
umin z0.s, z0.s, #0
UMIN Z0.S, Z0.S, #0
umin z1.s, z1.s, #0
UMIN Z1.S, Z1.S, #0
umin z31.s, z31.s, #0
UMIN Z31.S, Z31.S, #0
umin z2.s, z2.s, #0
UMIN Z2.S, Z2.S, #0
umin z0.s, z0.s, #127
UMIN Z0.S, Z0.S, #127
umin z0.s, z0.s, #128
UMIN Z0.S, Z0.S, #128
umin z0.s, z0.s, #129
UMIN Z0.S, Z0.S, #129
umin z0.s, z0.s, #255
UMIN Z0.S, Z0.S, #255
umin z0.d, z0.d, #0
UMIN Z0.D, Z0.D, #0
umin z1.d, z1.d, #0
UMIN Z1.D, Z1.D, #0
umin z31.d, z31.d, #0
UMIN Z31.D, Z31.D, #0
umin z2.d, z2.d, #0
UMIN Z2.D, Z2.D, #0
umin z0.d, z0.d, #127
UMIN Z0.D, Z0.D, #127
umin z0.d, z0.d, #128
UMIN Z0.D, Z0.D, #128
umin z0.d, z0.d, #129
UMIN Z0.D, Z0.D, #129
umin z0.d, z0.d, #255
UMIN Z0.D, Z0.D, #255
umin z0.b, p0/m, z0.b, z0.b
UMIN Z0.B, P0/M, Z0.B, Z0.B
umin z1.b, p0/m, z1.b, z0.b
UMIN Z1.B, P0/M, Z1.B, Z0.B
umin z31.b, p0/m, z31.b, z0.b
UMIN Z31.B, P0/M, Z31.B, Z0.B
umin z0.b, p2/m, z0.b, z0.b
UMIN Z0.B, P2/M, Z0.B, Z0.B
umin z0.b, p7/m, z0.b, z0.b
UMIN Z0.B, P7/M, Z0.B, Z0.B
umin z3.b, p0/m, z3.b, z0.b
UMIN Z3.B, P0/M, Z3.B, Z0.B
umin z0.b, p0/m, z0.b, z4.b
UMIN Z0.B, P0/M, Z0.B, Z4.B
umin z0.b, p0/m, z0.b, z31.b
UMIN Z0.B, P0/M, Z0.B, Z31.B
umin z0.h, p0/m, z0.h, z0.h
UMIN Z0.H, P0/M, Z0.H, Z0.H
umin z1.h, p0/m, z1.h, z0.h
UMIN Z1.H, P0/M, Z1.H, Z0.H
umin z31.h, p0/m, z31.h, z0.h
UMIN Z31.H, P0/M, Z31.H, Z0.H
umin z0.h, p2/m, z0.h, z0.h
UMIN Z0.H, P2/M, Z0.H, Z0.H
umin z0.h, p7/m, z0.h, z0.h
UMIN Z0.H, P7/M, Z0.H, Z0.H
umin z3.h, p0/m, z3.h, z0.h
UMIN Z3.H, P0/M, Z3.H, Z0.H
umin z0.h, p0/m, z0.h, z4.h
UMIN Z0.H, P0/M, Z0.H, Z4.H
umin z0.h, p0/m, z0.h, z31.h
UMIN Z0.H, P0/M, Z0.H, Z31.H
umin z0.s, p0/m, z0.s, z0.s
UMIN Z0.S, P0/M, Z0.S, Z0.S
umin z1.s, p0/m, z1.s, z0.s
UMIN Z1.S, P0/M, Z1.S, Z0.S
umin z31.s, p0/m, z31.s, z0.s
UMIN Z31.S, P0/M, Z31.S, Z0.S
umin z0.s, p2/m, z0.s, z0.s
UMIN Z0.S, P2/M, Z0.S, Z0.S
umin z0.s, p7/m, z0.s, z0.s
UMIN Z0.S, P7/M, Z0.S, Z0.S
umin z3.s, p0/m, z3.s, z0.s
UMIN Z3.S, P0/M, Z3.S, Z0.S
umin z0.s, p0/m, z0.s, z4.s
UMIN Z0.S, P0/M, Z0.S, Z4.S
umin z0.s, p0/m, z0.s, z31.s
UMIN Z0.S, P0/M, Z0.S, Z31.S
umin z0.d, p0/m, z0.d, z0.d
UMIN Z0.D, P0/M, Z0.D, Z0.D
umin z1.d, p0/m, z1.d, z0.d
UMIN Z1.D, P0/M, Z1.D, Z0.D
umin z31.d, p0/m, z31.d, z0.d
UMIN Z31.D, P0/M, Z31.D, Z0.D
umin z0.d, p2/m, z0.d, z0.d
UMIN Z0.D, P2/M, Z0.D, Z0.D
umin z0.d, p7/m, z0.d, z0.d
UMIN Z0.D, P7/M, Z0.D, Z0.D
umin z3.d, p0/m, z3.d, z0.d
UMIN Z3.D, P0/M, Z3.D, Z0.D
umin z0.d, p0/m, z0.d, z4.d
UMIN Z0.D, P0/M, Z0.D, Z4.D
umin z0.d, p0/m, z0.d, z31.d
UMIN Z0.D, P0/M, Z0.D, Z31.D
uminv b0, p0, z0.b
UMINV B0, P0, Z0.B
uminv b1, p0, z0.b
UMINV B1, P0, Z0.B
uminv b31, p0, z0.b
UMINV B31, P0, Z0.B
uminv b0, p2, z0.b
UMINV B0, P2, Z0.B
uminv b0, p7, z0.b
UMINV B0, P7, Z0.B
uminv b0, p0, z3.b
UMINV B0, P0, Z3.B
uminv b0, p0, z31.b
UMINV B0, P0, Z31.B
uminv h0, p0, z0.h
UMINV H0, P0, Z0.H
uminv h1, p0, z0.h
UMINV H1, P0, Z0.H
uminv h31, p0, z0.h
UMINV H31, P0, Z0.H
uminv h0, p2, z0.h
UMINV H0, P2, Z0.H
uminv h0, p7, z0.h
UMINV H0, P7, Z0.H
uminv h0, p0, z3.h
UMINV H0, P0, Z3.H
uminv h0, p0, z31.h
UMINV H0, P0, Z31.H
uminv s0, p0, z0.s
UMINV S0, P0, Z0.S
uminv s1, p0, z0.s
UMINV S1, P0, Z0.S
uminv s31, p0, z0.s
UMINV S31, P0, Z0.S
uminv s0, p2, z0.s
UMINV S0, P2, Z0.S
uminv s0, p7, z0.s
UMINV S0, P7, Z0.S
uminv s0, p0, z3.s
UMINV S0, P0, Z3.S
uminv s0, p0, z31.s
UMINV S0, P0, Z31.S
uminv d0, p0, z0.d
UMINV D0, P0, Z0.D
uminv d1, p0, z0.d
UMINV D1, P0, Z0.D
uminv d31, p0, z0.d
UMINV D31, P0, Z0.D
uminv d0, p2, z0.d
UMINV D0, P2, Z0.D
uminv d0, p7, z0.d
UMINV D0, P7, Z0.D
uminv d0, p0, z3.d
UMINV D0, P0, Z3.D
uminv d0, p0, z31.d
UMINV D0, P0, Z31.D
umulh z0.b, p0/m, z0.b, z0.b
UMULH Z0.B, P0/M, Z0.B, Z0.B
umulh z1.b, p0/m, z1.b, z0.b
UMULH Z1.B, P0/M, Z1.B, Z0.B
umulh z31.b, p0/m, z31.b, z0.b
UMULH Z31.B, P0/M, Z31.B, Z0.B
umulh z0.b, p2/m, z0.b, z0.b
UMULH Z0.B, P2/M, Z0.B, Z0.B
umulh z0.b, p7/m, z0.b, z0.b
UMULH Z0.B, P7/M, Z0.B, Z0.B
umulh z3.b, p0/m, z3.b, z0.b
UMULH Z3.B, P0/M, Z3.B, Z0.B
umulh z0.b, p0/m, z0.b, z4.b
UMULH Z0.B, P0/M, Z0.B, Z4.B
umulh z0.b, p0/m, z0.b, z31.b
UMULH Z0.B, P0/M, Z0.B, Z31.B
umulh z0.h, p0/m, z0.h, z0.h
UMULH Z0.H, P0/M, Z0.H, Z0.H
umulh z1.h, p0/m, z1.h, z0.h
UMULH Z1.H, P0/M, Z1.H, Z0.H
umulh z31.h, p0/m, z31.h, z0.h
UMULH Z31.H, P0/M, Z31.H, Z0.H
umulh z0.h, p2/m, z0.h, z0.h
UMULH Z0.H, P2/M, Z0.H, Z0.H
umulh z0.h, p7/m, z0.h, z0.h
UMULH Z0.H, P7/M, Z0.H, Z0.H
umulh z3.h, p0/m, z3.h, z0.h
UMULH Z3.H, P0/M, Z3.H, Z0.H
umulh z0.h, p0/m, z0.h, z4.h
UMULH Z0.H, P0/M, Z0.H, Z4.H
umulh z0.h, p0/m, z0.h, z31.h
UMULH Z0.H, P0/M, Z0.H, Z31.H
umulh z0.s, p0/m, z0.s, z0.s
UMULH Z0.S, P0/M, Z0.S, Z0.S
umulh z1.s, p0/m, z1.s, z0.s
UMULH Z1.S, P0/M, Z1.S, Z0.S
umulh z31.s, p0/m, z31.s, z0.s
UMULH Z31.S, P0/M, Z31.S, Z0.S
umulh z0.s, p2/m, z0.s, z0.s
UMULH Z0.S, P2/M, Z0.S, Z0.S
umulh z0.s, p7/m, z0.s, z0.s
UMULH Z0.S, P7/M, Z0.S, Z0.S
umulh z3.s, p0/m, z3.s, z0.s
UMULH Z3.S, P0/M, Z3.S, Z0.S
umulh z0.s, p0/m, z0.s, z4.s
UMULH Z0.S, P0/M, Z0.S, Z4.S
umulh z0.s, p0/m, z0.s, z31.s
UMULH Z0.S, P0/M, Z0.S, Z31.S
umulh z0.d, p0/m, z0.d, z0.d
UMULH Z0.D, P0/M, Z0.D, Z0.D
umulh z1.d, p0/m, z1.d, z0.d
UMULH Z1.D, P0/M, Z1.D, Z0.D
umulh z31.d, p0/m, z31.d, z0.d
UMULH Z31.D, P0/M, Z31.D, Z0.D
umulh z0.d, p2/m, z0.d, z0.d
UMULH Z0.D, P2/M, Z0.D, Z0.D
umulh z0.d, p7/m, z0.d, z0.d
UMULH Z0.D, P7/M, Z0.D, Z0.D
umulh z3.d, p0/m, z3.d, z0.d
UMULH Z3.D, P0/M, Z3.D, Z0.D
umulh z0.d, p0/m, z0.d, z4.d
UMULH Z0.D, P0/M, Z0.D, Z4.D
umulh z0.d, p0/m, z0.d, z31.d
UMULH Z0.D, P0/M, Z0.D, Z31.D
uqadd z0.b, z0.b, z0.b
UQADD Z0.B, Z0.B, Z0.B
uqadd z1.b, z0.b, z0.b
UQADD Z1.B, Z0.B, Z0.B
uqadd z31.b, z0.b, z0.b
UQADD Z31.B, Z0.B, Z0.B
uqadd z0.b, z2.b, z0.b
UQADD Z0.B, Z2.B, Z0.B
uqadd z0.b, z31.b, z0.b
UQADD Z0.B, Z31.B, Z0.B
uqadd z0.b, z0.b, z3.b
UQADD Z0.B, Z0.B, Z3.B
uqadd z0.b, z0.b, z31.b
UQADD Z0.B, Z0.B, Z31.B
uqadd z0.h, z0.h, z0.h
UQADD Z0.H, Z0.H, Z0.H
uqadd z1.h, z0.h, z0.h
UQADD Z1.H, Z0.H, Z0.H
uqadd z31.h, z0.h, z0.h
UQADD Z31.H, Z0.H, Z0.H
uqadd z0.h, z2.h, z0.h
UQADD Z0.H, Z2.H, Z0.H
uqadd z0.h, z31.h, z0.h
UQADD Z0.H, Z31.H, Z0.H
uqadd z0.h, z0.h, z3.h
UQADD Z0.H, Z0.H, Z3.H
uqadd z0.h, z0.h, z31.h
UQADD Z0.H, Z0.H, Z31.H
uqadd z0.s, z0.s, z0.s
UQADD Z0.S, Z0.S, Z0.S
uqadd z1.s, z0.s, z0.s
UQADD Z1.S, Z0.S, Z0.S
uqadd z31.s, z0.s, z0.s
UQADD Z31.S, Z0.S, Z0.S
uqadd z0.s, z2.s, z0.s
UQADD Z0.S, Z2.S, Z0.S
uqadd z0.s, z31.s, z0.s
UQADD Z0.S, Z31.S, Z0.S
uqadd z0.s, z0.s, z3.s
UQADD Z0.S, Z0.S, Z3.S
uqadd z0.s, z0.s, z31.s
UQADD Z0.S, Z0.S, Z31.S
uqadd z0.d, z0.d, z0.d
UQADD Z0.D, Z0.D, Z0.D
uqadd z1.d, z0.d, z0.d
UQADD Z1.D, Z0.D, Z0.D
uqadd z31.d, z0.d, z0.d
UQADD Z31.D, Z0.D, Z0.D
uqadd z0.d, z2.d, z0.d
UQADD Z0.D, Z2.D, Z0.D
uqadd z0.d, z31.d, z0.d
UQADD Z0.D, Z31.D, Z0.D
uqadd z0.d, z0.d, z3.d
UQADD Z0.D, Z0.D, Z3.D
uqadd z0.d, z0.d, z31.d
UQADD Z0.D, Z0.D, Z31.D
uqadd z0.b, z0.b, #0
UQADD Z0.B, Z0.B, #0
uqadd z0.b, z0.b, #0, lsl #0
uqadd z1.b, z1.b, #0
UQADD Z1.B, Z1.B, #0
uqadd z1.b, z1.b, #0, lsl #0
uqadd z31.b, z31.b, #0
UQADD Z31.B, Z31.B, #0
uqadd z31.b, z31.b, #0, lsl #0
uqadd z2.b, z2.b, #0
UQADD Z2.B, Z2.B, #0
uqadd z2.b, z2.b, #0, lsl #0
uqadd z0.b, z0.b, #127
UQADD Z0.B, Z0.B, #127
uqadd z0.b, z0.b, #127, lsl #0
uqadd z0.b, z0.b, #128
UQADD Z0.B, Z0.B, #128
uqadd z0.b, z0.b, #128, lsl #0
uqadd z0.b, z0.b, #129
UQADD Z0.B, Z0.B, #129
uqadd z0.b, z0.b, #129, lsl #0
uqadd z0.b, z0.b, #255
UQADD Z0.B, Z0.B, #255
uqadd z0.b, z0.b, #255, lsl #0
uqadd z0.h, z0.h, #0
UQADD Z0.H, Z0.H, #0
uqadd z0.h, z0.h, #0, lsl #0
uqadd z1.h, z1.h, #0
UQADD Z1.H, Z1.H, #0
uqadd z1.h, z1.h, #0, lsl #0
uqadd z31.h, z31.h, #0
UQADD Z31.H, Z31.H, #0
uqadd z31.h, z31.h, #0, lsl #0
uqadd z2.h, z2.h, #0
UQADD Z2.H, Z2.H, #0
uqadd z2.h, z2.h, #0, lsl #0
uqadd z0.h, z0.h, #127
UQADD Z0.H, Z0.H, #127
uqadd z0.h, z0.h, #127, lsl #0
uqadd z0.h, z0.h, #128
UQADD Z0.H, Z0.H, #128
uqadd z0.h, z0.h, #128, lsl #0
uqadd z0.h, z0.h, #129
UQADD Z0.H, Z0.H, #129
uqadd z0.h, z0.h, #129, lsl #0
uqadd z0.h, z0.h, #255
UQADD Z0.H, Z0.H, #255
uqadd z0.h, z0.h, #255, lsl #0
uqadd z0.h, z0.h, #0, lsl #8
UQADD Z0.H, Z0.H, #0, LSL #8
uqadd z0.h, z0.h, #32512
UQADD Z0.H, Z0.H, #32512
uqadd z0.h, z0.h, #32512, lsl #0
uqadd z0.h, z0.h, #127, lsl #8
uqadd z0.h, z0.h, #32768
UQADD Z0.H, Z0.H, #32768
uqadd z0.h, z0.h, #32768, lsl #0
uqadd z0.h, z0.h, #128, lsl #8
uqadd z0.h, z0.h, #33024
UQADD Z0.H, Z0.H, #33024
uqadd z0.h, z0.h, #33024, lsl #0
uqadd z0.h, z0.h, #129, lsl #8
uqadd z0.h, z0.h, #65280
UQADD Z0.H, Z0.H, #65280
uqadd z0.h, z0.h, #65280, lsl #0
uqadd z0.h, z0.h, #255, lsl #8
uqadd z0.s, z0.s, #0
UQADD Z0.S, Z0.S, #0
uqadd z0.s, z0.s, #0, lsl #0
uqadd z1.s, z1.s, #0
UQADD Z1.S, Z1.S, #0
uqadd z1.s, z1.s, #0, lsl #0
uqadd z31.s, z31.s, #0
UQADD Z31.S, Z31.S, #0
uqadd z31.s, z31.s, #0, lsl #0
uqadd z2.s, z2.s, #0
UQADD Z2.S, Z2.S, #0
uqadd z2.s, z2.s, #0, lsl #0
uqadd z0.s, z0.s, #127
UQADD Z0.S, Z0.S, #127
uqadd z0.s, z0.s, #127, lsl #0
uqadd z0.s, z0.s, #128
UQADD Z0.S, Z0.S, #128
uqadd z0.s, z0.s, #128, lsl #0
uqadd z0.s, z0.s, #129
UQADD Z0.S, Z0.S, #129
uqadd z0.s, z0.s, #129, lsl #0
uqadd z0.s, z0.s, #255
UQADD Z0.S, Z0.S, #255
uqadd z0.s, z0.s, #255, lsl #0
uqadd z0.s, z0.s, #0, lsl #8
UQADD Z0.S, Z0.S, #0, LSL #8
uqadd z0.s, z0.s, #32512
UQADD Z0.S, Z0.S, #32512
uqadd z0.s, z0.s, #32512, lsl #0
uqadd z0.s, z0.s, #127, lsl #8
uqadd z0.s, z0.s, #32768
UQADD Z0.S, Z0.S, #32768
uqadd z0.s, z0.s, #32768, lsl #0
uqadd z0.s, z0.s, #128, lsl #8
uqadd z0.s, z0.s, #33024
UQADD Z0.S, Z0.S, #33024
uqadd z0.s, z0.s, #33024, lsl #0
uqadd z0.s, z0.s, #129, lsl #8
uqadd z0.s, z0.s, #65280
UQADD Z0.S, Z0.S, #65280
uqadd z0.s, z0.s, #65280, lsl #0
uqadd z0.s, z0.s, #255, lsl #8
uqadd z0.d, z0.d, #0
UQADD Z0.D, Z0.D, #0
uqadd z0.d, z0.d, #0, lsl #0
uqadd z1.d, z1.d, #0
UQADD Z1.D, Z1.D, #0
uqadd z1.d, z1.d, #0, lsl #0
uqadd z31.d, z31.d, #0
UQADD Z31.D, Z31.D, #0
uqadd z31.d, z31.d, #0, lsl #0
uqadd z2.d, z2.d, #0
UQADD Z2.D, Z2.D, #0
uqadd z2.d, z2.d, #0, lsl #0
uqadd z0.d, z0.d, #127
UQADD Z0.D, Z0.D, #127
uqadd z0.d, z0.d, #127, lsl #0
uqadd z0.d, z0.d, #128
UQADD Z0.D, Z0.D, #128
uqadd z0.d, z0.d, #128, lsl #0
uqadd z0.d, z0.d, #129
UQADD Z0.D, Z0.D, #129
uqadd z0.d, z0.d, #129, lsl #0
uqadd z0.d, z0.d, #255
UQADD Z0.D, Z0.D, #255
uqadd z0.d, z0.d, #255, lsl #0
uqadd z0.d, z0.d, #0, lsl #8
UQADD Z0.D, Z0.D, #0, LSL #8
uqadd z0.d, z0.d, #32512
UQADD Z0.D, Z0.D, #32512
uqadd z0.d, z0.d, #32512, lsl #0
uqadd z0.d, z0.d, #127, lsl #8
uqadd z0.d, z0.d, #32768
UQADD Z0.D, Z0.D, #32768
uqadd z0.d, z0.d, #32768, lsl #0
uqadd z0.d, z0.d, #128, lsl #8
uqadd z0.d, z0.d, #33024
UQADD Z0.D, Z0.D, #33024
uqadd z0.d, z0.d, #33024, lsl #0
uqadd z0.d, z0.d, #129, lsl #8
uqadd z0.d, z0.d, #65280
UQADD Z0.D, Z0.D, #65280
uqadd z0.d, z0.d, #65280, lsl #0
uqadd z0.d, z0.d, #255, lsl #8
uqdecb w0, pow2
UQDECB W0, POW2
uqdecb w0, pow2, mul #1
uqdecb w1, pow2
UQDECB W1, POW2
uqdecb w1, pow2, mul #1
uqdecb wzr, pow2
UQDECB WZR, POW2
uqdecb wzr, pow2, mul #1
uqdecb w0, vl1
UQDECB W0, VL1
uqdecb w0, vl1, mul #1
uqdecb w0, vl2
UQDECB W0, VL2
uqdecb w0, vl2, mul #1
uqdecb w0, vl3
UQDECB W0, VL3
uqdecb w0, vl3, mul #1
uqdecb w0, vl4
UQDECB W0, VL4
uqdecb w0, vl4, mul #1
uqdecb w0, vl5
UQDECB W0, VL5
uqdecb w0, vl5, mul #1
uqdecb w0, vl6
UQDECB W0, VL6
uqdecb w0, vl6, mul #1
uqdecb w0, vl7
UQDECB W0, VL7
uqdecb w0, vl7, mul #1
uqdecb w0, vl8
UQDECB W0, VL8
uqdecb w0, vl8, mul #1
uqdecb w0, vl16
UQDECB W0, VL16
uqdecb w0, vl16, mul #1
uqdecb w0, vl32
UQDECB W0, VL32
uqdecb w0, vl32, mul #1
uqdecb w0, vl64
UQDECB W0, VL64
uqdecb w0, vl64, mul #1
uqdecb w0, vl128
UQDECB W0, VL128
uqdecb w0, vl128, mul #1
uqdecb w0, vl256
UQDECB W0, VL256
uqdecb w0, vl256, mul #1
uqdecb w0, #14
UQDECB W0, #14
uqdecb w0, #14, mul #1
uqdecb w0, #15
UQDECB W0, #15
uqdecb w0, #15, mul #1
uqdecb w0, #16
UQDECB W0, #16
uqdecb w0, #16, mul #1
uqdecb w0, #17
UQDECB W0, #17
uqdecb w0, #17, mul #1
uqdecb w0, #18
UQDECB W0, #18
uqdecb w0, #18, mul #1
uqdecb w0, #19
UQDECB W0, #19
uqdecb w0, #19, mul #1
uqdecb w0, #20
UQDECB W0, #20
uqdecb w0, #20, mul #1
uqdecb w0, #21
UQDECB W0, #21
uqdecb w0, #21, mul #1
uqdecb w0, #22
UQDECB W0, #22
uqdecb w0, #22, mul #1
uqdecb w0, #23
UQDECB W0, #23
uqdecb w0, #23, mul #1
uqdecb w0, #24
UQDECB W0, #24
uqdecb w0, #24, mul #1
uqdecb w0, #25
UQDECB W0, #25
uqdecb w0, #25, mul #1
uqdecb w0, #26
UQDECB W0, #26
uqdecb w0, #26, mul #1
uqdecb w0, #27
UQDECB W0, #27
uqdecb w0, #27, mul #1
uqdecb w0, #28
UQDECB W0, #28
uqdecb w0, #28, mul #1
uqdecb w0, mul4
UQDECB W0, MUL4
uqdecb w0, mul4, mul #1
uqdecb w0, mul3
UQDECB W0, MUL3
uqdecb w0, mul3, mul #1
uqdecb w0
UQDECB W0
uqdecb w0, all
uqdecb w0, all, mul #1
uqdecb w0, pow2, mul #8
UQDECB W0, POW2, MUL #8
uqdecb w0, pow2, mul #9
UQDECB W0, POW2, MUL #9
uqdecb w0, pow2, mul #10
UQDECB W0, POW2, MUL #10
uqdecb w0, pow2, mul #16
UQDECB W0, POW2, MUL #16
uqdecb x0, pow2
UQDECB X0, POW2
uqdecb x0, pow2, mul #1
uqdecb x1, pow2
UQDECB X1, POW2
uqdecb x1, pow2, mul #1
uqdecb xzr, pow2
UQDECB XZR, POW2
uqdecb xzr, pow2, mul #1
uqdecb x0, vl1
UQDECB X0, VL1
uqdecb x0, vl1, mul #1
uqdecb x0, vl2
UQDECB X0, VL2
uqdecb x0, vl2, mul #1
uqdecb x0, vl3
UQDECB X0, VL3
uqdecb x0, vl3, mul #1
uqdecb x0, vl4
UQDECB X0, VL4
uqdecb x0, vl4, mul #1
uqdecb x0, vl5
UQDECB X0, VL5
uqdecb x0, vl5, mul #1
uqdecb x0, vl6
UQDECB X0, VL6
uqdecb x0, vl6, mul #1
uqdecb x0, vl7
UQDECB X0, VL7
uqdecb x0, vl7, mul #1
uqdecb x0, vl8
UQDECB X0, VL8
uqdecb x0, vl8, mul #1
uqdecb x0, vl16
UQDECB X0, VL16
uqdecb x0, vl16, mul #1
uqdecb x0, vl32
UQDECB X0, VL32
uqdecb x0, vl32, mul #1
uqdecb x0, vl64
UQDECB X0, VL64
uqdecb x0, vl64, mul #1
uqdecb x0, vl128
UQDECB X0, VL128
uqdecb x0, vl128, mul #1
uqdecb x0, vl256
UQDECB X0, VL256
uqdecb x0, vl256, mul #1
uqdecb x0, #14
UQDECB X0, #14
uqdecb x0, #14, mul #1
uqdecb x0, #15
UQDECB X0, #15
uqdecb x0, #15, mul #1
uqdecb x0, #16
UQDECB X0, #16
uqdecb x0, #16, mul #1
uqdecb x0, #17
UQDECB X0, #17
uqdecb x0, #17, mul #1
uqdecb x0, #18
UQDECB X0, #18
uqdecb x0, #18, mul #1
uqdecb x0, #19
UQDECB X0, #19
uqdecb x0, #19, mul #1
uqdecb x0, #20
UQDECB X0, #20
uqdecb x0, #20, mul #1
uqdecb x0, #21
UQDECB X0, #21
uqdecb x0, #21, mul #1
uqdecb x0, #22
UQDECB X0, #22
uqdecb x0, #22, mul #1
uqdecb x0, #23
UQDECB X0, #23
uqdecb x0, #23, mul #1
uqdecb x0, #24
UQDECB X0, #24
uqdecb x0, #24, mul #1
uqdecb x0, #25
UQDECB X0, #25
uqdecb x0, #25, mul #1
uqdecb x0, #26
UQDECB X0, #26
uqdecb x0, #26, mul #1
uqdecb x0, #27
UQDECB X0, #27
uqdecb x0, #27, mul #1
uqdecb x0, #28
UQDECB X0, #28
uqdecb x0, #28, mul #1
uqdecb x0, mul4
UQDECB X0, MUL4
uqdecb x0, mul4, mul #1
uqdecb x0, mul3
UQDECB X0, MUL3
uqdecb x0, mul3, mul #1
uqdecb x0
UQDECB X0
uqdecb x0, all
uqdecb x0, all, mul #1
uqdecb x0, pow2, mul #8
UQDECB X0, POW2, MUL #8
uqdecb x0, pow2, mul #9
UQDECB X0, POW2, MUL #9
uqdecb x0, pow2, mul #10
UQDECB X0, POW2, MUL #10
uqdecb x0, pow2, mul #16
UQDECB X0, POW2, MUL #16
uqdecd z0.d, pow2
UQDECD Z0.D, POW2
uqdecd z0.d, pow2, mul #1
uqdecd z1.d, pow2
UQDECD Z1.D, POW2
uqdecd z1.d, pow2, mul #1
uqdecd z31.d, pow2
UQDECD Z31.D, POW2
uqdecd z31.d, pow2, mul #1
uqdecd z0.d, vl1
UQDECD Z0.D, VL1
uqdecd z0.d, vl1, mul #1
uqdecd z0.d, vl2
UQDECD Z0.D, VL2
uqdecd z0.d, vl2, mul #1
uqdecd z0.d, vl3
UQDECD Z0.D, VL3
uqdecd z0.d, vl3, mul #1
uqdecd z0.d, vl4
UQDECD Z0.D, VL4
uqdecd z0.d, vl4, mul #1
uqdecd z0.d, vl5
UQDECD Z0.D, VL5
uqdecd z0.d, vl5, mul #1
uqdecd z0.d, vl6
UQDECD Z0.D, VL6
uqdecd z0.d, vl6, mul #1
uqdecd z0.d, vl7
UQDECD Z0.D, VL7
uqdecd z0.d, vl7, mul #1
uqdecd z0.d, vl8
UQDECD Z0.D, VL8
uqdecd z0.d, vl8, mul #1
uqdecd z0.d, vl16
UQDECD Z0.D, VL16
uqdecd z0.d, vl16, mul #1
uqdecd z0.d, vl32
UQDECD Z0.D, VL32
uqdecd z0.d, vl32, mul #1
uqdecd z0.d, vl64
UQDECD Z0.D, VL64
uqdecd z0.d, vl64, mul #1
uqdecd z0.d, vl128
UQDECD Z0.D, VL128
uqdecd z0.d, vl128, mul #1
uqdecd z0.d, vl256
UQDECD Z0.D, VL256
uqdecd z0.d, vl256, mul #1
uqdecd z0.d, #14
UQDECD Z0.D, #14
uqdecd z0.d, #14, mul #1
uqdecd z0.d, #15
UQDECD Z0.D, #15
uqdecd z0.d, #15, mul #1
uqdecd z0.d, #16
UQDECD Z0.D, #16
uqdecd z0.d, #16, mul #1
uqdecd z0.d, #17
UQDECD Z0.D, #17
uqdecd z0.d, #17, mul #1
uqdecd z0.d, #18
UQDECD Z0.D, #18
uqdecd z0.d, #18, mul #1
uqdecd z0.d, #19
UQDECD Z0.D, #19
uqdecd z0.d, #19, mul #1
uqdecd z0.d, #20
UQDECD Z0.D, #20
uqdecd z0.d, #20, mul #1
uqdecd z0.d, #21
UQDECD Z0.D, #21
uqdecd z0.d, #21, mul #1
uqdecd z0.d, #22
UQDECD Z0.D, #22
uqdecd z0.d, #22, mul #1
uqdecd z0.d, #23
UQDECD Z0.D, #23
uqdecd z0.d, #23, mul #1
uqdecd z0.d, #24
UQDECD Z0.D, #24
uqdecd z0.d, #24, mul #1
uqdecd z0.d, #25
UQDECD Z0.D, #25
uqdecd z0.d, #25, mul #1
uqdecd z0.d, #26
UQDECD Z0.D, #26
uqdecd z0.d, #26, mul #1
uqdecd z0.d, #27
UQDECD Z0.D, #27
uqdecd z0.d, #27, mul #1
uqdecd z0.d, #28
UQDECD Z0.D, #28
uqdecd z0.d, #28, mul #1
uqdecd z0.d, mul4
UQDECD Z0.D, MUL4
uqdecd z0.d, mul4, mul #1
uqdecd z0.d, mul3
UQDECD Z0.D, MUL3
uqdecd z0.d, mul3, mul #1
uqdecd z0.d
UQDECD Z0.D
uqdecd z0.d, all
uqdecd z0.d, all, mul #1
uqdecd z0.d, pow2, mul #8
UQDECD Z0.D, POW2, MUL #8
uqdecd z0.d, pow2, mul #9
UQDECD Z0.D, POW2, MUL #9
uqdecd z0.d, pow2, mul #10
UQDECD Z0.D, POW2, MUL #10
uqdecd z0.d, pow2, mul #16
UQDECD Z0.D, POW2, MUL #16
uqdecd w0, pow2
UQDECD W0, POW2
uqdecd w0, pow2, mul #1
uqdecd w1, pow2
UQDECD W1, POW2
uqdecd w1, pow2, mul #1
uqdecd wzr, pow2
UQDECD WZR, POW2
uqdecd wzr, pow2, mul #1
uqdecd w0, vl1
UQDECD W0, VL1
uqdecd w0, vl1, mul #1
uqdecd w0, vl2
UQDECD W0, VL2
uqdecd w0, vl2, mul #1
uqdecd w0, vl3
UQDECD W0, VL3
uqdecd w0, vl3, mul #1
uqdecd w0, vl4
UQDECD W0, VL4
uqdecd w0, vl4, mul #1
uqdecd w0, vl5
UQDECD W0, VL5
uqdecd w0, vl5, mul #1
uqdecd w0, vl6
UQDECD W0, VL6
uqdecd w0, vl6, mul #1
uqdecd w0, vl7
UQDECD W0, VL7
uqdecd w0, vl7, mul #1
uqdecd w0, vl8
UQDECD W0, VL8
uqdecd w0, vl8, mul #1
uqdecd w0, vl16
UQDECD W0, VL16
uqdecd w0, vl16, mul #1
uqdecd w0, vl32
UQDECD W0, VL32
uqdecd w0, vl32, mul #1
uqdecd w0, vl64
UQDECD W0, VL64
uqdecd w0, vl64, mul #1
uqdecd w0, vl128
UQDECD W0, VL128
uqdecd w0, vl128, mul #1
uqdecd w0, vl256
UQDECD W0, VL256
uqdecd w0, vl256, mul #1
uqdecd w0, #14
UQDECD W0, #14
uqdecd w0, #14, mul #1
uqdecd w0, #15
UQDECD W0, #15
uqdecd w0, #15, mul #1
uqdecd w0, #16
UQDECD W0, #16
uqdecd w0, #16, mul #1
uqdecd w0, #17
UQDECD W0, #17
uqdecd w0, #17, mul #1
uqdecd w0, #18
UQDECD W0, #18
uqdecd w0, #18, mul #1
uqdecd w0, #19
UQDECD W0, #19
uqdecd w0, #19, mul #1
uqdecd w0, #20
UQDECD W0, #20
uqdecd w0, #20, mul #1
uqdecd w0, #21
UQDECD W0, #21
uqdecd w0, #21, mul #1
uqdecd w0, #22
UQDECD W0, #22
uqdecd w0, #22, mul #1
uqdecd w0, #23
UQDECD W0, #23
uqdecd w0, #23, mul #1
uqdecd w0, #24
UQDECD W0, #24
uqdecd w0, #24, mul #1
uqdecd w0, #25
UQDECD W0, #25
uqdecd w0, #25, mul #1
uqdecd w0, #26
UQDECD W0, #26
uqdecd w0, #26, mul #1
uqdecd w0, #27
UQDECD W0, #27
uqdecd w0, #27, mul #1
uqdecd w0, #28
UQDECD W0, #28
uqdecd w0, #28, mul #1
uqdecd w0, mul4
UQDECD W0, MUL4
uqdecd w0, mul4, mul #1
uqdecd w0, mul3
UQDECD W0, MUL3
uqdecd w0, mul3, mul #1
uqdecd w0
UQDECD W0
uqdecd w0, all
uqdecd w0, all, mul #1
uqdecd w0, pow2, mul #8
UQDECD W0, POW2, MUL #8
uqdecd w0, pow2, mul #9
UQDECD W0, POW2, MUL #9
uqdecd w0, pow2, mul #10
UQDECD W0, POW2, MUL #10
uqdecd w0, pow2, mul #16
UQDECD W0, POW2, MUL #16
uqdecd x0, pow2
UQDECD X0, POW2
uqdecd x0, pow2, mul #1
uqdecd x1, pow2
UQDECD X1, POW2
uqdecd x1, pow2, mul #1
uqdecd xzr, pow2
UQDECD XZR, POW2
uqdecd xzr, pow2, mul #1
uqdecd x0, vl1
UQDECD X0, VL1
uqdecd x0, vl1, mul #1
uqdecd x0, vl2
UQDECD X0, VL2
uqdecd x0, vl2, mul #1
uqdecd x0, vl3
UQDECD X0, VL3
uqdecd x0, vl3, mul #1
uqdecd x0, vl4
UQDECD X0, VL4
uqdecd x0, vl4, mul #1
uqdecd x0, vl5
UQDECD X0, VL5
uqdecd x0, vl5, mul #1
uqdecd x0, vl6
UQDECD X0, VL6
uqdecd x0, vl6, mul #1
uqdecd x0, vl7
UQDECD X0, VL7
uqdecd x0, vl7, mul #1
uqdecd x0, vl8
UQDECD X0, VL8
uqdecd x0, vl8, mul #1
uqdecd x0, vl16
UQDECD X0, VL16
uqdecd x0, vl16, mul #1
uqdecd x0, vl32
UQDECD X0, VL32
uqdecd x0, vl32, mul #1
uqdecd x0, vl64
UQDECD X0, VL64
uqdecd x0, vl64, mul #1
uqdecd x0, vl128
UQDECD X0, VL128
uqdecd x0, vl128, mul #1
uqdecd x0, vl256
UQDECD X0, VL256
uqdecd x0, vl256, mul #1
uqdecd x0, #14
UQDECD X0, #14
uqdecd x0, #14, mul #1
uqdecd x0, #15
UQDECD X0, #15
uqdecd x0, #15, mul #1
uqdecd x0, #16
UQDECD X0, #16
uqdecd x0, #16, mul #1
uqdecd x0, #17
UQDECD X0, #17
uqdecd x0, #17, mul #1
uqdecd x0, #18
UQDECD X0, #18
uqdecd x0, #18, mul #1
uqdecd x0, #19
UQDECD X0, #19
uqdecd x0, #19, mul #1
uqdecd x0, #20
UQDECD X0, #20
uqdecd x0, #20, mul #1
uqdecd x0, #21
UQDECD X0, #21
uqdecd x0, #21, mul #1
uqdecd x0, #22
UQDECD X0, #22
uqdecd x0, #22, mul #1
uqdecd x0, #23
UQDECD X0, #23
uqdecd x0, #23, mul #1
uqdecd x0, #24
UQDECD X0, #24
uqdecd x0, #24, mul #1
uqdecd x0, #25
UQDECD X0, #25
uqdecd x0, #25, mul #1
uqdecd x0, #26
UQDECD X0, #26
uqdecd x0, #26, mul #1
uqdecd x0, #27
UQDECD X0, #27
uqdecd x0, #27, mul #1
uqdecd x0, #28
UQDECD X0, #28
uqdecd x0, #28, mul #1
uqdecd x0, mul4
UQDECD X0, MUL4
uqdecd x0, mul4, mul #1
uqdecd x0, mul3
UQDECD X0, MUL3
uqdecd x0, mul3, mul #1
uqdecd x0
UQDECD X0
uqdecd x0, all
uqdecd x0, all, mul #1
uqdecd x0, pow2, mul #8
UQDECD X0, POW2, MUL #8
uqdecd x0, pow2, mul #9
UQDECD X0, POW2, MUL #9
uqdecd x0, pow2, mul #10
UQDECD X0, POW2, MUL #10
uqdecd x0, pow2, mul #16
UQDECD X0, POW2, MUL #16
uqdech z0.h, pow2
UQDECH Z0.H, POW2
uqdech z0.h, pow2, mul #1
uqdech z1.h, pow2
UQDECH Z1.H, POW2
uqdech z1.h, pow2, mul #1
uqdech z31.h, pow2
UQDECH Z31.H, POW2
uqdech z31.h, pow2, mul #1
uqdech z0.h, vl1
UQDECH Z0.H, VL1
uqdech z0.h, vl1, mul #1
uqdech z0.h, vl2
UQDECH Z0.H, VL2
uqdech z0.h, vl2, mul #1
uqdech z0.h, vl3
UQDECH Z0.H, VL3
uqdech z0.h, vl3, mul #1
uqdech z0.h, vl4
UQDECH Z0.H, VL4
uqdech z0.h, vl4, mul #1
uqdech z0.h, vl5
UQDECH Z0.H, VL5
uqdech z0.h, vl5, mul #1
uqdech z0.h, vl6
UQDECH Z0.H, VL6
uqdech z0.h, vl6, mul #1
uqdech z0.h, vl7
UQDECH Z0.H, VL7
uqdech z0.h, vl7, mul #1
uqdech z0.h, vl8
UQDECH Z0.H, VL8
uqdech z0.h, vl8, mul #1
uqdech z0.h, vl16
UQDECH Z0.H, VL16
uqdech z0.h, vl16, mul #1
uqdech z0.h, vl32
UQDECH Z0.H, VL32
uqdech z0.h, vl32, mul #1
uqdech z0.h, vl64
UQDECH Z0.H, VL64
uqdech z0.h, vl64, mul #1
uqdech z0.h, vl128
UQDECH Z0.H, VL128
uqdech z0.h, vl128, mul #1
uqdech z0.h, vl256
UQDECH Z0.H, VL256
uqdech z0.h, vl256, mul #1
uqdech z0.h, #14
UQDECH Z0.H, #14
uqdech z0.h, #14, mul #1
uqdech z0.h, #15
UQDECH Z0.H, #15
uqdech z0.h, #15, mul #1
uqdech z0.h, #16
UQDECH Z0.H, #16
uqdech z0.h, #16, mul #1
uqdech z0.h, #17
UQDECH Z0.H, #17
uqdech z0.h, #17, mul #1
uqdech z0.h, #18
UQDECH Z0.H, #18
uqdech z0.h, #18, mul #1
uqdech z0.h, #19
UQDECH Z0.H, #19
uqdech z0.h, #19, mul #1
uqdech z0.h, #20
UQDECH Z0.H, #20
uqdech z0.h, #20, mul #1
uqdech z0.h, #21
UQDECH Z0.H, #21
uqdech z0.h, #21, mul #1
uqdech z0.h, #22
UQDECH Z0.H, #22
uqdech z0.h, #22, mul #1
uqdech z0.h, #23
UQDECH Z0.H, #23
uqdech z0.h, #23, mul #1
uqdech z0.h, #24
UQDECH Z0.H, #24
uqdech z0.h, #24, mul #1
uqdech z0.h, #25
UQDECH Z0.H, #25
uqdech z0.h, #25, mul #1
uqdech z0.h, #26
UQDECH Z0.H, #26
uqdech z0.h, #26, mul #1
uqdech z0.h, #27
UQDECH Z0.H, #27
uqdech z0.h, #27, mul #1
uqdech z0.h, #28
UQDECH Z0.H, #28
uqdech z0.h, #28, mul #1
uqdech z0.h, mul4
UQDECH Z0.H, MUL4
uqdech z0.h, mul4, mul #1
uqdech z0.h, mul3
UQDECH Z0.H, MUL3
uqdech z0.h, mul3, mul #1
uqdech z0.h
UQDECH Z0.H
uqdech z0.h, all
uqdech z0.h, all, mul #1
uqdech z0.h, pow2, mul #8
UQDECH Z0.H, POW2, MUL #8
uqdech z0.h, pow2, mul #9
UQDECH Z0.H, POW2, MUL #9
uqdech z0.h, pow2, mul #10
UQDECH Z0.H, POW2, MUL #10
uqdech z0.h, pow2, mul #16
UQDECH Z0.H, POW2, MUL #16
uqdech w0, pow2
UQDECH W0, POW2
uqdech w0, pow2, mul #1
uqdech w1, pow2
UQDECH W1, POW2
uqdech w1, pow2, mul #1
uqdech wzr, pow2
UQDECH WZR, POW2
uqdech wzr, pow2, mul #1
uqdech w0, vl1
UQDECH W0, VL1
uqdech w0, vl1, mul #1
uqdech w0, vl2
UQDECH W0, VL2
uqdech w0, vl2, mul #1
uqdech w0, vl3
UQDECH W0, VL3
uqdech w0, vl3, mul #1
uqdech w0, vl4
UQDECH W0, VL4
uqdech w0, vl4, mul #1
uqdech w0, vl5
UQDECH W0, VL5
uqdech w0, vl5, mul #1
uqdech w0, vl6
UQDECH W0, VL6
uqdech w0, vl6, mul #1
uqdech w0, vl7
UQDECH W0, VL7
uqdech w0, vl7, mul #1
uqdech w0, vl8
UQDECH W0, VL8
uqdech w0, vl8, mul #1
uqdech w0, vl16
UQDECH W0, VL16
uqdech w0, vl16, mul #1
uqdech w0, vl32
UQDECH W0, VL32
uqdech w0, vl32, mul #1
uqdech w0, vl64
UQDECH W0, VL64
uqdech w0, vl64, mul #1
uqdech w0, vl128
UQDECH W0, VL128
uqdech w0, vl128, mul #1
uqdech w0, vl256
UQDECH W0, VL256
uqdech w0, vl256, mul #1
uqdech w0, #14
UQDECH W0, #14
uqdech w0, #14, mul #1
uqdech w0, #15
UQDECH W0, #15
uqdech w0, #15, mul #1
uqdech w0, #16
UQDECH W0, #16
uqdech w0, #16, mul #1
uqdech w0, #17
UQDECH W0, #17
uqdech w0, #17, mul #1
uqdech w0, #18
UQDECH W0, #18
uqdech w0, #18, mul #1
uqdech w0, #19
UQDECH W0, #19
uqdech w0, #19, mul #1
uqdech w0, #20
UQDECH W0, #20
uqdech w0, #20, mul #1
uqdech w0, #21
UQDECH W0, #21
uqdech w0, #21, mul #1
uqdech w0, #22
UQDECH W0, #22
uqdech w0, #22, mul #1
uqdech w0, #23
UQDECH W0, #23
uqdech w0, #23, mul #1
uqdech w0, #24
UQDECH W0, #24
uqdech w0, #24, mul #1
uqdech w0, #25
UQDECH W0, #25
uqdech w0, #25, mul #1
uqdech w0, #26
UQDECH W0, #26
uqdech w0, #26, mul #1
uqdech w0, #27
UQDECH W0, #27
uqdech w0, #27, mul #1
uqdech w0, #28
UQDECH W0, #28
uqdech w0, #28, mul #1
uqdech w0, mul4
UQDECH W0, MUL4
uqdech w0, mul4, mul #1
uqdech w0, mul3
UQDECH W0, MUL3
uqdech w0, mul3, mul #1
uqdech w0
UQDECH W0
uqdech w0, all
uqdech w0, all, mul #1
uqdech w0, pow2, mul #8
UQDECH W0, POW2, MUL #8
uqdech w0, pow2, mul #9
UQDECH W0, POW2, MUL #9
uqdech w0, pow2, mul #10
UQDECH W0, POW2, MUL #10
uqdech w0, pow2, mul #16
UQDECH W0, POW2, MUL #16
uqdech x0, pow2
UQDECH X0, POW2
uqdech x0, pow2, mul #1
uqdech x1, pow2
UQDECH X1, POW2
uqdech x1, pow2, mul #1
uqdech xzr, pow2
UQDECH XZR, POW2
uqdech xzr, pow2, mul #1
uqdech x0, vl1
UQDECH X0, VL1
uqdech x0, vl1, mul #1
uqdech x0, vl2
UQDECH X0, VL2
uqdech x0, vl2, mul #1
uqdech x0, vl3
UQDECH X0, VL3
uqdech x0, vl3, mul #1
uqdech x0, vl4
UQDECH X0, VL4
uqdech x0, vl4, mul #1
uqdech x0, vl5
UQDECH X0, VL5
uqdech x0, vl5, mul #1
uqdech x0, vl6
UQDECH X0, VL6
uqdech x0, vl6, mul #1
uqdech x0, vl7
UQDECH X0, VL7
uqdech x0, vl7, mul #1
uqdech x0, vl8
UQDECH X0, VL8
uqdech x0, vl8, mul #1
uqdech x0, vl16
UQDECH X0, VL16
uqdech x0, vl16, mul #1
uqdech x0, vl32
UQDECH X0, VL32
uqdech x0, vl32, mul #1
uqdech x0, vl64
UQDECH X0, VL64
uqdech x0, vl64, mul #1
uqdech x0, vl128
UQDECH X0, VL128
uqdech x0, vl128, mul #1
uqdech x0, vl256
UQDECH X0, VL256
uqdech x0, vl256, mul #1
uqdech x0, #14
UQDECH X0, #14
uqdech x0, #14, mul #1
uqdech x0, #15
UQDECH X0, #15
uqdech x0, #15, mul #1
uqdech x0, #16
UQDECH X0, #16
uqdech x0, #16, mul #1
uqdech x0, #17
UQDECH X0, #17
uqdech x0, #17, mul #1
uqdech x0, #18
UQDECH X0, #18
uqdech x0, #18, mul #1
uqdech x0, #19
UQDECH X0, #19
uqdech x0, #19, mul #1
uqdech x0, #20
UQDECH X0, #20
uqdech x0, #20, mul #1
uqdech x0, #21
UQDECH X0, #21
uqdech x0, #21, mul #1
uqdech x0, #22
UQDECH X0, #22
uqdech x0, #22, mul #1
uqdech x0, #23
UQDECH X0, #23
uqdech x0, #23, mul #1
uqdech x0, #24
UQDECH X0, #24
uqdech x0, #24, mul #1
uqdech x0, #25
UQDECH X0, #25
uqdech x0, #25, mul #1
uqdech x0, #26
UQDECH X0, #26
uqdech x0, #26, mul #1
uqdech x0, #27
UQDECH X0, #27
uqdech x0, #27, mul #1
uqdech x0, #28
UQDECH X0, #28
uqdech x0, #28, mul #1
uqdech x0, mul4
UQDECH X0, MUL4
uqdech x0, mul4, mul #1
uqdech x0, mul3
UQDECH X0, MUL3
uqdech x0, mul3, mul #1
uqdech x0
UQDECH X0
uqdech x0, all
uqdech x0, all, mul #1
uqdech x0, pow2, mul #8
UQDECH X0, POW2, MUL #8
uqdech x0, pow2, mul #9
UQDECH X0, POW2, MUL #9
uqdech x0, pow2, mul #10
UQDECH X0, POW2, MUL #10
uqdech x0, pow2, mul #16
UQDECH X0, POW2, MUL #16
uqdecp z0.h, p0
UQDECP Z0.H, P0
uqdecp z1.h, p0
UQDECP Z1.H, P0
uqdecp z31.h, p0
UQDECP Z31.H, P0
uqdecp z0.h, p2
UQDECP Z0.H, P2
uqdecp z0.h, p15
UQDECP Z0.H, P15
uqdecp z0.s, p0
UQDECP Z0.S, P0
uqdecp z1.s, p0
UQDECP Z1.S, P0
uqdecp z31.s, p0
UQDECP Z31.S, P0
uqdecp z0.s, p2
UQDECP Z0.S, P2
uqdecp z0.s, p15
UQDECP Z0.S, P15
uqdecp z0.d, p0
UQDECP Z0.D, P0
uqdecp z1.d, p0
UQDECP Z1.D, P0
uqdecp z31.d, p0
UQDECP Z31.D, P0
uqdecp z0.d, p2
UQDECP Z0.D, P2
uqdecp z0.d, p15
UQDECP Z0.D, P15
uqdecp w0, p0.b
UQDECP W0, P0.B
uqdecp w1, p0.b
UQDECP W1, P0.B
uqdecp wzr, p0.b
UQDECP WZR, P0.B
uqdecp w0, p2.b
UQDECP W0, P2.B
uqdecp w0, p15.b
UQDECP W0, P15.B
uqdecp w0, p0.h
UQDECP W0, P0.H
uqdecp w1, p0.h
UQDECP W1, P0.H
uqdecp wzr, p0.h
UQDECP WZR, P0.H
uqdecp w0, p2.h
UQDECP W0, P2.H
uqdecp w0, p15.h
UQDECP W0, P15.H
uqdecp w0, p0.s
UQDECP W0, P0.S
uqdecp w1, p0.s
UQDECP W1, P0.S
uqdecp wzr, p0.s
UQDECP WZR, P0.S
uqdecp w0, p2.s
UQDECP W0, P2.S
uqdecp w0, p15.s
UQDECP W0, P15.S
uqdecp w0, p0.d
UQDECP W0, P0.D
uqdecp w1, p0.d
UQDECP W1, P0.D
uqdecp wzr, p0.d
UQDECP WZR, P0.D
uqdecp w0, p2.d
UQDECP W0, P2.D
uqdecp w0, p15.d
UQDECP W0, P15.D
uqdecp x0, p0.b
UQDECP X0, P0.B
uqdecp x1, p0.b
UQDECP X1, P0.B
uqdecp xzr, p0.b
UQDECP XZR, P0.B
uqdecp x0, p2.b
UQDECP X0, P2.B
uqdecp x0, p15.b
UQDECP X0, P15.B
uqdecp x0, p0.h
UQDECP X0, P0.H
uqdecp x1, p0.h
UQDECP X1, P0.H
uqdecp xzr, p0.h
UQDECP XZR, P0.H
uqdecp x0, p2.h
UQDECP X0, P2.H
uqdecp x0, p15.h
UQDECP X0, P15.H
uqdecp x0, p0.s
UQDECP X0, P0.S
uqdecp x1, p0.s
UQDECP X1, P0.S
uqdecp xzr, p0.s
UQDECP XZR, P0.S
uqdecp x0, p2.s
UQDECP X0, P2.S
uqdecp x0, p15.s
UQDECP X0, P15.S
uqdecp x0, p0.d
UQDECP X0, P0.D
uqdecp x1, p0.d
UQDECP X1, P0.D
uqdecp xzr, p0.d
UQDECP XZR, P0.D
uqdecp x0, p2.d
UQDECP X0, P2.D
uqdecp x0, p15.d
UQDECP X0, P15.D
uqdecw z0.s, pow2
UQDECW Z0.S, POW2
uqdecw z0.s, pow2, mul #1
uqdecw z1.s, pow2
UQDECW Z1.S, POW2
uqdecw z1.s, pow2, mul #1
uqdecw z31.s, pow2
UQDECW Z31.S, POW2
uqdecw z31.s, pow2, mul #1
uqdecw z0.s, vl1
UQDECW Z0.S, VL1
uqdecw z0.s, vl1, mul #1
uqdecw z0.s, vl2
UQDECW Z0.S, VL2
uqdecw z0.s, vl2, mul #1
uqdecw z0.s, vl3
UQDECW Z0.S, VL3
uqdecw z0.s, vl3, mul #1
uqdecw z0.s, vl4
UQDECW Z0.S, VL4
uqdecw z0.s, vl4, mul #1
uqdecw z0.s, vl5
UQDECW Z0.S, VL5
uqdecw z0.s, vl5, mul #1
uqdecw z0.s, vl6
UQDECW Z0.S, VL6
uqdecw z0.s, vl6, mul #1
uqdecw z0.s, vl7
UQDECW Z0.S, VL7
uqdecw z0.s, vl7, mul #1
uqdecw z0.s, vl8
UQDECW Z0.S, VL8
uqdecw z0.s, vl8, mul #1
uqdecw z0.s, vl16
UQDECW Z0.S, VL16
uqdecw z0.s, vl16, mul #1
uqdecw z0.s, vl32
UQDECW Z0.S, VL32
uqdecw z0.s, vl32, mul #1
uqdecw z0.s, vl64
UQDECW Z0.S, VL64
uqdecw z0.s, vl64, mul #1
uqdecw z0.s, vl128
UQDECW Z0.S, VL128
uqdecw z0.s, vl128, mul #1
uqdecw z0.s, vl256
UQDECW Z0.S, VL256
uqdecw z0.s, vl256, mul #1
uqdecw z0.s, #14
UQDECW Z0.S, #14
uqdecw z0.s, #14, mul #1
uqdecw z0.s, #15
UQDECW Z0.S, #15
uqdecw z0.s, #15, mul #1
uqdecw z0.s, #16
UQDECW Z0.S, #16
uqdecw z0.s, #16, mul #1
uqdecw z0.s, #17
UQDECW Z0.S, #17
uqdecw z0.s, #17, mul #1
uqdecw z0.s, #18
UQDECW Z0.S, #18
uqdecw z0.s, #18, mul #1
uqdecw z0.s, #19
UQDECW Z0.S, #19
uqdecw z0.s, #19, mul #1
uqdecw z0.s, #20
UQDECW Z0.S, #20
uqdecw z0.s, #20, mul #1
uqdecw z0.s, #21
UQDECW Z0.S, #21
uqdecw z0.s, #21, mul #1
uqdecw z0.s, #22
UQDECW Z0.S, #22
uqdecw z0.s, #22, mul #1
uqdecw z0.s, #23
UQDECW Z0.S, #23
uqdecw z0.s, #23, mul #1
uqdecw z0.s, #24
UQDECW Z0.S, #24
uqdecw z0.s, #24, mul #1
uqdecw z0.s, #25
UQDECW Z0.S, #25
uqdecw z0.s, #25, mul #1
uqdecw z0.s, #26
UQDECW Z0.S, #26
uqdecw z0.s, #26, mul #1
uqdecw z0.s, #27
UQDECW Z0.S, #27
uqdecw z0.s, #27, mul #1
uqdecw z0.s, #28
UQDECW Z0.S, #28
uqdecw z0.s, #28, mul #1
uqdecw z0.s, mul4
UQDECW Z0.S, MUL4
uqdecw z0.s, mul4, mul #1
uqdecw z0.s, mul3
UQDECW Z0.S, MUL3
uqdecw z0.s, mul3, mul #1
uqdecw z0.s
UQDECW Z0.S
uqdecw z0.s, all
uqdecw z0.s, all, mul #1
uqdecw z0.s, pow2, mul #8
UQDECW Z0.S, POW2, MUL #8
uqdecw z0.s, pow2, mul #9
UQDECW Z0.S, POW2, MUL #9
uqdecw z0.s, pow2, mul #10
UQDECW Z0.S, POW2, MUL #10
uqdecw z0.s, pow2, mul #16
UQDECW Z0.S, POW2, MUL #16
uqdecw w0, pow2
UQDECW W0, POW2
uqdecw w0, pow2, mul #1
uqdecw w1, pow2
UQDECW W1, POW2
uqdecw w1, pow2, mul #1
uqdecw wzr, pow2
UQDECW WZR, POW2
uqdecw wzr, pow2, mul #1
uqdecw w0, vl1
UQDECW W0, VL1
uqdecw w0, vl1, mul #1
uqdecw w0, vl2
UQDECW W0, VL2
uqdecw w0, vl2, mul #1
uqdecw w0, vl3
UQDECW W0, VL3
uqdecw w0, vl3, mul #1
uqdecw w0, vl4
UQDECW W0, VL4
uqdecw w0, vl4, mul #1
uqdecw w0, vl5
UQDECW W0, VL5
uqdecw w0, vl5, mul #1
uqdecw w0, vl6
UQDECW W0, VL6
uqdecw w0, vl6, mul #1
uqdecw w0, vl7
UQDECW W0, VL7
uqdecw w0, vl7, mul #1
uqdecw w0, vl8
UQDECW W0, VL8
uqdecw w0, vl8, mul #1
uqdecw w0, vl16
UQDECW W0, VL16
uqdecw w0, vl16, mul #1
uqdecw w0, vl32
UQDECW W0, VL32
uqdecw w0, vl32, mul #1
uqdecw w0, vl64
UQDECW W0, VL64
uqdecw w0, vl64, mul #1
uqdecw w0, vl128
UQDECW W0, VL128
uqdecw w0, vl128, mul #1
uqdecw w0, vl256
UQDECW W0, VL256
uqdecw w0, vl256, mul #1
uqdecw w0, #14
UQDECW W0, #14
uqdecw w0, #14, mul #1
uqdecw w0, #15
UQDECW W0, #15
uqdecw w0, #15, mul #1
uqdecw w0, #16
UQDECW W0, #16
uqdecw w0, #16, mul #1
uqdecw w0, #17
UQDECW W0, #17
uqdecw w0, #17, mul #1
uqdecw w0, #18
UQDECW W0, #18
uqdecw w0, #18, mul #1
uqdecw w0, #19
UQDECW W0, #19
uqdecw w0, #19, mul #1
uqdecw w0, #20
UQDECW W0, #20
uqdecw w0, #20, mul #1
uqdecw w0, #21
UQDECW W0, #21
uqdecw w0, #21, mul #1
uqdecw w0, #22
UQDECW W0, #22
uqdecw w0, #22, mul #1
uqdecw w0, #23
UQDECW W0, #23
uqdecw w0, #23, mul #1
uqdecw w0, #24
UQDECW W0, #24
uqdecw w0, #24, mul #1
uqdecw w0, #25
UQDECW W0, #25
uqdecw w0, #25, mul #1
uqdecw w0, #26
UQDECW W0, #26
uqdecw w0, #26, mul #1
uqdecw w0, #27
UQDECW W0, #27
uqdecw w0, #27, mul #1
uqdecw w0, #28
UQDECW W0, #28
uqdecw w0, #28, mul #1
uqdecw w0, mul4
UQDECW W0, MUL4
uqdecw w0, mul4, mul #1
uqdecw w0, mul3
UQDECW W0, MUL3
uqdecw w0, mul3, mul #1
uqdecw w0
UQDECW W0
uqdecw w0, all
uqdecw w0, all, mul #1
uqdecw w0, pow2, mul #8
UQDECW W0, POW2, MUL #8
uqdecw w0, pow2, mul #9
UQDECW W0, POW2, MUL #9
uqdecw w0, pow2, mul #10
UQDECW W0, POW2, MUL #10
uqdecw w0, pow2, mul #16
UQDECW W0, POW2, MUL #16
uqdecw x0, pow2
UQDECW X0, POW2
uqdecw x0, pow2, mul #1
uqdecw x1, pow2
UQDECW X1, POW2
uqdecw x1, pow2, mul #1
uqdecw xzr, pow2
UQDECW XZR, POW2
uqdecw xzr, pow2, mul #1
uqdecw x0, vl1
UQDECW X0, VL1
uqdecw x0, vl1, mul #1
uqdecw x0, vl2
UQDECW X0, VL2
uqdecw x0, vl2, mul #1
uqdecw x0, vl3
UQDECW X0, VL3
uqdecw x0, vl3, mul #1
uqdecw x0, vl4
UQDECW X0, VL4
uqdecw x0, vl4, mul #1
uqdecw x0, vl5
UQDECW X0, VL5
uqdecw x0, vl5, mul #1
uqdecw x0, vl6
UQDECW X0, VL6
uqdecw x0, vl6, mul #1
uqdecw x0, vl7
UQDECW X0, VL7
uqdecw x0, vl7, mul #1
uqdecw x0, vl8
UQDECW X0, VL8
uqdecw x0, vl8, mul #1
uqdecw x0, vl16
UQDECW X0, VL16
uqdecw x0, vl16, mul #1
uqdecw x0, vl32
UQDECW X0, VL32
uqdecw x0, vl32, mul #1
uqdecw x0, vl64
UQDECW X0, VL64
uqdecw x0, vl64, mul #1
uqdecw x0, vl128
UQDECW X0, VL128
uqdecw x0, vl128, mul #1
uqdecw x0, vl256
UQDECW X0, VL256
uqdecw x0, vl256, mul #1
uqdecw x0, #14
UQDECW X0, #14
uqdecw x0, #14, mul #1
uqdecw x0, #15
UQDECW X0, #15
uqdecw x0, #15, mul #1
uqdecw x0, #16
UQDECW X0, #16
uqdecw x0, #16, mul #1
uqdecw x0, #17
UQDECW X0, #17
uqdecw x0, #17, mul #1
uqdecw x0, #18
UQDECW X0, #18
uqdecw x0, #18, mul #1
uqdecw x0, #19
UQDECW X0, #19
uqdecw x0, #19, mul #1
uqdecw x0, #20
UQDECW X0, #20
uqdecw x0, #20, mul #1
uqdecw x0, #21
UQDECW X0, #21
uqdecw x0, #21, mul #1
uqdecw x0, #22
UQDECW X0, #22
uqdecw x0, #22, mul #1
uqdecw x0, #23
UQDECW X0, #23
uqdecw x0, #23, mul #1
uqdecw x0, #24
UQDECW X0, #24
uqdecw x0, #24, mul #1
uqdecw x0, #25
UQDECW X0, #25
uqdecw x0, #25, mul #1
uqdecw x0, #26
UQDECW X0, #26
uqdecw x0, #26, mul #1
uqdecw x0, #27
UQDECW X0, #27
uqdecw x0, #27, mul #1
uqdecw x0, #28
UQDECW X0, #28
uqdecw x0, #28, mul #1
uqdecw x0, mul4
UQDECW X0, MUL4
uqdecw x0, mul4, mul #1
uqdecw x0, mul3
UQDECW X0, MUL3
uqdecw x0, mul3, mul #1
uqdecw x0
UQDECW X0
uqdecw x0, all
uqdecw x0, all, mul #1
uqdecw x0, pow2, mul #8
UQDECW X0, POW2, MUL #8
uqdecw x0, pow2, mul #9
UQDECW X0, POW2, MUL #9
uqdecw x0, pow2, mul #10
UQDECW X0, POW2, MUL #10
uqdecw x0, pow2, mul #16
UQDECW X0, POW2, MUL #16
uqincb w0, pow2
UQINCB W0, POW2
uqincb w0, pow2, mul #1
uqincb w1, pow2
UQINCB W1, POW2
uqincb w1, pow2, mul #1
uqincb wzr, pow2
UQINCB WZR, POW2
uqincb wzr, pow2, mul #1
uqincb w0, vl1
UQINCB W0, VL1
uqincb w0, vl1, mul #1
uqincb w0, vl2
UQINCB W0, VL2
uqincb w0, vl2, mul #1
uqincb w0, vl3
UQINCB W0, VL3
uqincb w0, vl3, mul #1
uqincb w0, vl4
UQINCB W0, VL4
uqincb w0, vl4, mul #1
uqincb w0, vl5
UQINCB W0, VL5
uqincb w0, vl5, mul #1
uqincb w0, vl6
UQINCB W0, VL6
uqincb w0, vl6, mul #1
uqincb w0, vl7
UQINCB W0, VL7
uqincb w0, vl7, mul #1
uqincb w0, vl8
UQINCB W0, VL8
uqincb w0, vl8, mul #1
uqincb w0, vl16
UQINCB W0, VL16
uqincb w0, vl16, mul #1
uqincb w0, vl32
UQINCB W0, VL32
uqincb w0, vl32, mul #1
uqincb w0, vl64
UQINCB W0, VL64
uqincb w0, vl64, mul #1
uqincb w0, vl128
UQINCB W0, VL128
uqincb w0, vl128, mul #1
uqincb w0, vl256
UQINCB W0, VL256
uqincb w0, vl256, mul #1
uqincb w0, #14
UQINCB W0, #14
uqincb w0, #14, mul #1
uqincb w0, #15
UQINCB W0, #15
uqincb w0, #15, mul #1
uqincb w0, #16
UQINCB W0, #16
uqincb w0, #16, mul #1
uqincb w0, #17
UQINCB W0, #17
uqincb w0, #17, mul #1
uqincb w0, #18
UQINCB W0, #18
uqincb w0, #18, mul #1
uqincb w0, #19
UQINCB W0, #19
uqincb w0, #19, mul #1
uqincb w0, #20
UQINCB W0, #20
uqincb w0, #20, mul #1
uqincb w0, #21
UQINCB W0, #21
uqincb w0, #21, mul #1
uqincb w0, #22
UQINCB W0, #22
uqincb w0, #22, mul #1
uqincb w0, #23
UQINCB W0, #23
uqincb w0, #23, mul #1
uqincb w0, #24
UQINCB W0, #24
uqincb w0, #24, mul #1
uqincb w0, #25
UQINCB W0, #25
uqincb w0, #25, mul #1
uqincb w0, #26
UQINCB W0, #26
uqincb w0, #26, mul #1
uqincb w0, #27
UQINCB W0, #27
uqincb w0, #27, mul #1
uqincb w0, #28
UQINCB W0, #28
uqincb w0, #28, mul #1
uqincb w0, mul4
UQINCB W0, MUL4
uqincb w0, mul4, mul #1
uqincb w0, mul3
UQINCB W0, MUL3
uqincb w0, mul3, mul #1
uqincb w0
UQINCB W0
uqincb w0, all
uqincb w0, all, mul #1
uqincb w0, pow2, mul #8
UQINCB W0, POW2, MUL #8
uqincb w0, pow2, mul #9
UQINCB W0, POW2, MUL #9
uqincb w0, pow2, mul #10
UQINCB W0, POW2, MUL #10
uqincb w0, pow2, mul #16
UQINCB W0, POW2, MUL #16
uqincb x0, pow2
UQINCB X0, POW2
uqincb x0, pow2, mul #1
uqincb x1, pow2
UQINCB X1, POW2
uqincb x1, pow2, mul #1
uqincb xzr, pow2
UQINCB XZR, POW2
uqincb xzr, pow2, mul #1
uqincb x0, vl1
UQINCB X0, VL1
uqincb x0, vl1, mul #1
uqincb x0, vl2
UQINCB X0, VL2
uqincb x0, vl2, mul #1
uqincb x0, vl3
UQINCB X0, VL3
uqincb x0, vl3, mul #1
uqincb x0, vl4
UQINCB X0, VL4
uqincb x0, vl4, mul #1
uqincb x0, vl5
UQINCB X0, VL5
uqincb x0, vl5, mul #1
uqincb x0, vl6
UQINCB X0, VL6
uqincb x0, vl6, mul #1
uqincb x0, vl7
UQINCB X0, VL7
uqincb x0, vl7, mul #1
uqincb x0, vl8
UQINCB X0, VL8
uqincb x0, vl8, mul #1
uqincb x0, vl16
UQINCB X0, VL16
uqincb x0, vl16, mul #1
uqincb x0, vl32
UQINCB X0, VL32
uqincb x0, vl32, mul #1
uqincb x0, vl64
UQINCB X0, VL64
uqincb x0, vl64, mul #1
uqincb x0, vl128
UQINCB X0, VL128
uqincb x0, vl128, mul #1
uqincb x0, vl256
UQINCB X0, VL256
uqincb x0, vl256, mul #1
uqincb x0, #14
UQINCB X0, #14
uqincb x0, #14, mul #1
uqincb x0, #15
UQINCB X0, #15
uqincb x0, #15, mul #1
uqincb x0, #16
UQINCB X0, #16
uqincb x0, #16, mul #1
uqincb x0, #17
UQINCB X0, #17
uqincb x0, #17, mul #1
uqincb x0, #18
UQINCB X0, #18
uqincb x0, #18, mul #1
uqincb x0, #19
UQINCB X0, #19
uqincb x0, #19, mul #1
uqincb x0, #20
UQINCB X0, #20
uqincb x0, #20, mul #1
uqincb x0, #21
UQINCB X0, #21
uqincb x0, #21, mul #1
uqincb x0, #22
UQINCB X0, #22
uqincb x0, #22, mul #1
uqincb x0, #23
UQINCB X0, #23
uqincb x0, #23, mul #1
uqincb x0, #24
UQINCB X0, #24
uqincb x0, #24, mul #1
uqincb x0, #25
UQINCB X0, #25
uqincb x0, #25, mul #1
uqincb x0, #26
UQINCB X0, #26
uqincb x0, #26, mul #1
uqincb x0, #27
UQINCB X0, #27
uqincb x0, #27, mul #1
uqincb x0, #28
UQINCB X0, #28
uqincb x0, #28, mul #1
uqincb x0, mul4
UQINCB X0, MUL4
uqincb x0, mul4, mul #1
uqincb x0, mul3
UQINCB X0, MUL3
uqincb x0, mul3, mul #1
uqincb x0
UQINCB X0
uqincb x0, all
uqincb x0, all, mul #1
uqincb x0, pow2, mul #8
UQINCB X0, POW2, MUL #8
uqincb x0, pow2, mul #9
UQINCB X0, POW2, MUL #9
uqincb x0, pow2, mul #10
UQINCB X0, POW2, MUL #10
uqincb x0, pow2, mul #16
UQINCB X0, POW2, MUL #16
uqincd z0.d, pow2
UQINCD Z0.D, POW2
uqincd z0.d, pow2, mul #1
uqincd z1.d, pow2
UQINCD Z1.D, POW2
uqincd z1.d, pow2, mul #1
uqincd z31.d, pow2
UQINCD Z31.D, POW2
uqincd z31.d, pow2, mul #1
uqincd z0.d, vl1
UQINCD Z0.D, VL1
uqincd z0.d, vl1, mul #1
uqincd z0.d, vl2
UQINCD Z0.D, VL2
uqincd z0.d, vl2, mul #1
uqincd z0.d, vl3
UQINCD Z0.D, VL3
uqincd z0.d, vl3, mul #1
uqincd z0.d, vl4
UQINCD Z0.D, VL4
uqincd z0.d, vl4, mul #1
uqincd z0.d, vl5
UQINCD Z0.D, VL5
uqincd z0.d, vl5, mul #1
uqincd z0.d, vl6
UQINCD Z0.D, VL6
uqincd z0.d, vl6, mul #1
uqincd z0.d, vl7
UQINCD Z0.D, VL7
uqincd z0.d, vl7, mul #1
uqincd z0.d, vl8
UQINCD Z0.D, VL8
uqincd z0.d, vl8, mul #1
uqincd z0.d, vl16
UQINCD Z0.D, VL16
uqincd z0.d, vl16, mul #1
uqincd z0.d, vl32
UQINCD Z0.D, VL32
uqincd z0.d, vl32, mul #1
uqincd z0.d, vl64
UQINCD Z0.D, VL64
uqincd z0.d, vl64, mul #1
uqincd z0.d, vl128
UQINCD Z0.D, VL128
uqincd z0.d, vl128, mul #1
uqincd z0.d, vl256
UQINCD Z0.D, VL256
uqincd z0.d, vl256, mul #1
uqincd z0.d, #14
UQINCD Z0.D, #14
uqincd z0.d, #14, mul #1
uqincd z0.d, #15
UQINCD Z0.D, #15
uqincd z0.d, #15, mul #1
uqincd z0.d, #16
UQINCD Z0.D, #16
uqincd z0.d, #16, mul #1
uqincd z0.d, #17
UQINCD Z0.D, #17
uqincd z0.d, #17, mul #1
uqincd z0.d, #18
UQINCD Z0.D, #18
uqincd z0.d, #18, mul #1
uqincd z0.d, #19
UQINCD Z0.D, #19
uqincd z0.d, #19, mul #1
uqincd z0.d, #20
UQINCD Z0.D, #20
uqincd z0.d, #20, mul #1
uqincd z0.d, #21
UQINCD Z0.D, #21
uqincd z0.d, #21, mul #1
uqincd z0.d, #22
UQINCD Z0.D, #22
uqincd z0.d, #22, mul #1
uqincd z0.d, #23
UQINCD Z0.D, #23
uqincd z0.d, #23, mul #1
uqincd z0.d, #24
UQINCD Z0.D, #24
uqincd z0.d, #24, mul #1
uqincd z0.d, #25
UQINCD Z0.D, #25
uqincd z0.d, #25, mul #1
uqincd z0.d, #26
UQINCD Z0.D, #26
uqincd z0.d, #26, mul #1
uqincd z0.d, #27
UQINCD Z0.D, #27
uqincd z0.d, #27, mul #1
uqincd z0.d, #28
UQINCD Z0.D, #28
uqincd z0.d, #28, mul #1
uqincd z0.d, mul4
UQINCD Z0.D, MUL4
uqincd z0.d, mul4, mul #1
uqincd z0.d, mul3
UQINCD Z0.D, MUL3
uqincd z0.d, mul3, mul #1
uqincd z0.d
UQINCD Z0.D
uqincd z0.d, all
uqincd z0.d, all, mul #1
uqincd z0.d, pow2, mul #8
UQINCD Z0.D, POW2, MUL #8
uqincd z0.d, pow2, mul #9
UQINCD Z0.D, POW2, MUL #9
uqincd z0.d, pow2, mul #10
UQINCD Z0.D, POW2, MUL #10
uqincd z0.d, pow2, mul #16
UQINCD Z0.D, POW2, MUL #16
uqincd w0, pow2
UQINCD W0, POW2
uqincd w0, pow2, mul #1
uqincd w1, pow2
UQINCD W1, POW2
uqincd w1, pow2, mul #1
uqincd wzr, pow2
UQINCD WZR, POW2
uqincd wzr, pow2, mul #1
uqincd w0, vl1
UQINCD W0, VL1
uqincd w0, vl1, mul #1
uqincd w0, vl2
UQINCD W0, VL2
uqincd w0, vl2, mul #1
uqincd w0, vl3
UQINCD W0, VL3
uqincd w0, vl3, mul #1
uqincd w0, vl4
UQINCD W0, VL4
uqincd w0, vl4, mul #1
uqincd w0, vl5
UQINCD W0, VL5
uqincd w0, vl5, mul #1
uqincd w0, vl6
UQINCD W0, VL6
uqincd w0, vl6, mul #1
uqincd w0, vl7
UQINCD W0, VL7
uqincd w0, vl7, mul #1
uqincd w0, vl8
UQINCD W0, VL8
uqincd w0, vl8, mul #1
uqincd w0, vl16
UQINCD W0, VL16
uqincd w0, vl16, mul #1
uqincd w0, vl32
UQINCD W0, VL32
uqincd w0, vl32, mul #1
uqincd w0, vl64
UQINCD W0, VL64
uqincd w0, vl64, mul #1
uqincd w0, vl128
UQINCD W0, VL128
uqincd w0, vl128, mul #1
uqincd w0, vl256
UQINCD W0, VL256
uqincd w0, vl256, mul #1
uqincd w0, #14
UQINCD W0, #14
uqincd w0, #14, mul #1
uqincd w0, #15
UQINCD W0, #15
uqincd w0, #15, mul #1
uqincd w0, #16
UQINCD W0, #16
uqincd w0, #16, mul #1
uqincd w0, #17
UQINCD W0, #17
uqincd w0, #17, mul #1
uqincd w0, #18
UQINCD W0, #18
uqincd w0, #18, mul #1
uqincd w0, #19
UQINCD W0, #19
uqincd w0, #19, mul #1
uqincd w0, #20
UQINCD W0, #20
uqincd w0, #20, mul #1
uqincd w0, #21
UQINCD W0, #21
uqincd w0, #21, mul #1
uqincd w0, #22
UQINCD W0, #22
uqincd w0, #22, mul #1
uqincd w0, #23
UQINCD W0, #23
uqincd w0, #23, mul #1
uqincd w0, #24
UQINCD W0, #24
uqincd w0, #24, mul #1
uqincd w0, #25
UQINCD W0, #25
uqincd w0, #25, mul #1
uqincd w0, #26
UQINCD W0, #26
uqincd w0, #26, mul #1
uqincd w0, #27
UQINCD W0, #27
uqincd w0, #27, mul #1
uqincd w0, #28
UQINCD W0, #28
uqincd w0, #28, mul #1
uqincd w0, mul4
UQINCD W0, MUL4
uqincd w0, mul4, mul #1
uqincd w0, mul3
UQINCD W0, MUL3
uqincd w0, mul3, mul #1
uqincd w0
UQINCD W0
uqincd w0, all
uqincd w0, all, mul #1
uqincd w0, pow2, mul #8
UQINCD W0, POW2, MUL #8
uqincd w0, pow2, mul #9
UQINCD W0, POW2, MUL #9
uqincd w0, pow2, mul #10
UQINCD W0, POW2, MUL #10
uqincd w0, pow2, mul #16
UQINCD W0, POW2, MUL #16
uqincd x0, pow2
UQINCD X0, POW2
uqincd x0, pow2, mul #1
uqincd x1, pow2
UQINCD X1, POW2
uqincd x1, pow2, mul #1
uqincd xzr, pow2
UQINCD XZR, POW2
uqincd xzr, pow2, mul #1
uqincd x0, vl1
UQINCD X0, VL1
uqincd x0, vl1, mul #1
uqincd x0, vl2
UQINCD X0, VL2
uqincd x0, vl2, mul #1
uqincd x0, vl3
UQINCD X0, VL3
uqincd x0, vl3, mul #1
uqincd x0, vl4
UQINCD X0, VL4
uqincd x0, vl4, mul #1
uqincd x0, vl5
UQINCD X0, VL5
uqincd x0, vl5, mul #1
uqincd x0, vl6
UQINCD X0, VL6
uqincd x0, vl6, mul #1
uqincd x0, vl7
UQINCD X0, VL7
uqincd x0, vl7, mul #1
uqincd x0, vl8
UQINCD X0, VL8
uqincd x0, vl8, mul #1
uqincd x0, vl16
UQINCD X0, VL16
uqincd x0, vl16, mul #1
uqincd x0, vl32
UQINCD X0, VL32
uqincd x0, vl32, mul #1
uqincd x0, vl64
UQINCD X0, VL64
uqincd x0, vl64, mul #1
uqincd x0, vl128
UQINCD X0, VL128
uqincd x0, vl128, mul #1
uqincd x0, vl256
UQINCD X0, VL256
uqincd x0, vl256, mul #1
uqincd x0, #14
UQINCD X0, #14
uqincd x0, #14, mul #1
uqincd x0, #15
UQINCD X0, #15
uqincd x0, #15, mul #1
uqincd x0, #16
UQINCD X0, #16
uqincd x0, #16, mul #1
uqincd x0, #17
UQINCD X0, #17
uqincd x0, #17, mul #1
uqincd x0, #18
UQINCD X0, #18
uqincd x0, #18, mul #1
uqincd x0, #19
UQINCD X0, #19
uqincd x0, #19, mul #1
uqincd x0, #20
UQINCD X0, #20
uqincd x0, #20, mul #1
uqincd x0, #21
UQINCD X0, #21
uqincd x0, #21, mul #1
uqincd x0, #22
UQINCD X0, #22
uqincd x0, #22, mul #1
uqincd x0, #23
UQINCD X0, #23
uqincd x0, #23, mul #1
uqincd x0, #24
UQINCD X0, #24
uqincd x0, #24, mul #1
uqincd x0, #25
UQINCD X0, #25
uqincd x0, #25, mul #1
uqincd x0, #26
UQINCD X0, #26
uqincd x0, #26, mul #1
uqincd x0, #27
UQINCD X0, #27
uqincd x0, #27, mul #1
uqincd x0, #28
UQINCD X0, #28
uqincd x0, #28, mul #1
uqincd x0, mul4
UQINCD X0, MUL4
uqincd x0, mul4, mul #1
uqincd x0, mul3
UQINCD X0, MUL3
uqincd x0, mul3, mul #1
uqincd x0
UQINCD X0
uqincd x0, all
uqincd x0, all, mul #1
uqincd x0, pow2, mul #8
UQINCD X0, POW2, MUL #8
uqincd x0, pow2, mul #9
UQINCD X0, POW2, MUL #9
uqincd x0, pow2, mul #10
UQINCD X0, POW2, MUL #10
uqincd x0, pow2, mul #16
UQINCD X0, POW2, MUL #16
uqinch z0.h, pow2
UQINCH Z0.H, POW2
uqinch z0.h, pow2, mul #1
uqinch z1.h, pow2
UQINCH Z1.H, POW2
uqinch z1.h, pow2, mul #1
uqinch z31.h, pow2
UQINCH Z31.H, POW2
uqinch z31.h, pow2, mul #1
uqinch z0.h, vl1
UQINCH Z0.H, VL1
uqinch z0.h, vl1, mul #1
uqinch z0.h, vl2
UQINCH Z0.H, VL2
uqinch z0.h, vl2, mul #1
uqinch z0.h, vl3
UQINCH Z0.H, VL3
uqinch z0.h, vl3, mul #1
uqinch z0.h, vl4
UQINCH Z0.H, VL4
uqinch z0.h, vl4, mul #1
uqinch z0.h, vl5
UQINCH Z0.H, VL5
uqinch z0.h, vl5, mul #1
uqinch z0.h, vl6
UQINCH Z0.H, VL6
uqinch z0.h, vl6, mul #1
uqinch z0.h, vl7
UQINCH Z0.H, VL7
uqinch z0.h, vl7, mul #1
uqinch z0.h, vl8
UQINCH Z0.H, VL8
uqinch z0.h, vl8, mul #1
uqinch z0.h, vl16
UQINCH Z0.H, VL16
uqinch z0.h, vl16, mul #1
uqinch z0.h, vl32
UQINCH Z0.H, VL32
uqinch z0.h, vl32, mul #1
uqinch z0.h, vl64
UQINCH Z0.H, VL64
uqinch z0.h, vl64, mul #1
uqinch z0.h, vl128
UQINCH Z0.H, VL128
uqinch z0.h, vl128, mul #1
uqinch z0.h, vl256
UQINCH Z0.H, VL256
uqinch z0.h, vl256, mul #1
uqinch z0.h, #14
UQINCH Z0.H, #14
uqinch z0.h, #14, mul #1
uqinch z0.h, #15
UQINCH Z0.H, #15
uqinch z0.h, #15, mul #1
uqinch z0.h, #16
UQINCH Z0.H, #16
uqinch z0.h, #16, mul #1
uqinch z0.h, #17
UQINCH Z0.H, #17
uqinch z0.h, #17, mul #1
uqinch z0.h, #18
UQINCH Z0.H, #18
uqinch z0.h, #18, mul #1
uqinch z0.h, #19
UQINCH Z0.H, #19
uqinch z0.h, #19, mul #1
uqinch z0.h, #20
UQINCH Z0.H, #20
uqinch z0.h, #20, mul #1
uqinch z0.h, #21
UQINCH Z0.H, #21
uqinch z0.h, #21, mul #1
uqinch z0.h, #22
UQINCH Z0.H, #22
uqinch z0.h, #22, mul #1
uqinch z0.h, #23
UQINCH Z0.H, #23
uqinch z0.h, #23, mul #1
uqinch z0.h, #24
UQINCH Z0.H, #24
uqinch z0.h, #24, mul #1
uqinch z0.h, #25
UQINCH Z0.H, #25
uqinch z0.h, #25, mul #1
uqinch z0.h, #26
UQINCH Z0.H, #26
uqinch z0.h, #26, mul #1
uqinch z0.h, #27
UQINCH Z0.H, #27
uqinch z0.h, #27, mul #1
uqinch z0.h, #28
UQINCH Z0.H, #28
uqinch z0.h, #28, mul #1
uqinch z0.h, mul4
UQINCH Z0.H, MUL4
uqinch z0.h, mul4, mul #1
uqinch z0.h, mul3
UQINCH Z0.H, MUL3
uqinch z0.h, mul3, mul #1
uqinch z0.h
UQINCH Z0.H
uqinch z0.h, all
uqinch z0.h, all, mul #1
uqinch z0.h, pow2, mul #8
UQINCH Z0.H, POW2, MUL #8
uqinch z0.h, pow2, mul #9
UQINCH Z0.H, POW2, MUL #9
uqinch z0.h, pow2, mul #10
UQINCH Z0.H, POW2, MUL #10
uqinch z0.h, pow2, mul #16
UQINCH Z0.H, POW2, MUL #16
uqinch w0, pow2
UQINCH W0, POW2
uqinch w0, pow2, mul #1
uqinch w1, pow2
UQINCH W1, POW2
uqinch w1, pow2, mul #1
uqinch wzr, pow2
UQINCH WZR, POW2
uqinch wzr, pow2, mul #1
uqinch w0, vl1
UQINCH W0, VL1
uqinch w0, vl1, mul #1
uqinch w0, vl2
UQINCH W0, VL2
uqinch w0, vl2, mul #1
uqinch w0, vl3
UQINCH W0, VL3
uqinch w0, vl3, mul #1
uqinch w0, vl4
UQINCH W0, VL4
uqinch w0, vl4, mul #1
uqinch w0, vl5
UQINCH W0, VL5
uqinch w0, vl5, mul #1
uqinch w0, vl6
UQINCH W0, VL6
uqinch w0, vl6, mul #1
uqinch w0, vl7
UQINCH W0, VL7
uqinch w0, vl7, mul #1
uqinch w0, vl8
UQINCH W0, VL8
uqinch w0, vl8, mul #1
uqinch w0, vl16
UQINCH W0, VL16
uqinch w0, vl16, mul #1
uqinch w0, vl32
UQINCH W0, VL32
uqinch w0, vl32, mul #1
uqinch w0, vl64
UQINCH W0, VL64
uqinch w0, vl64, mul #1
uqinch w0, vl128
UQINCH W0, VL128
uqinch w0, vl128, mul #1
uqinch w0, vl256
UQINCH W0, VL256
uqinch w0, vl256, mul #1
uqinch w0, #14
UQINCH W0, #14
uqinch w0, #14, mul #1
uqinch w0, #15
UQINCH W0, #15
uqinch w0, #15, mul #1
uqinch w0, #16
UQINCH W0, #16
uqinch w0, #16, mul #1
uqinch w0, #17
UQINCH W0, #17
uqinch w0, #17, mul #1
uqinch w0, #18
UQINCH W0, #18
uqinch w0, #18, mul #1
uqinch w0, #19
UQINCH W0, #19
uqinch w0, #19, mul #1
uqinch w0, #20
UQINCH W0, #20
uqinch w0, #20, mul #1
uqinch w0, #21
UQINCH W0, #21
uqinch w0, #21, mul #1
uqinch w0, #22
UQINCH W0, #22
uqinch w0, #22, mul #1
uqinch w0, #23
UQINCH W0, #23
uqinch w0, #23, mul #1
uqinch w0, #24
UQINCH W0, #24
uqinch w0, #24, mul #1
uqinch w0, #25
UQINCH W0, #25
uqinch w0, #25, mul #1
uqinch w0, #26
UQINCH W0, #26
uqinch w0, #26, mul #1
uqinch w0, #27
UQINCH W0, #27
uqinch w0, #27, mul #1
uqinch w0, #28
UQINCH W0, #28
uqinch w0, #28, mul #1
uqinch w0, mul4
UQINCH W0, MUL4
uqinch w0, mul4, mul #1
uqinch w0, mul3
UQINCH W0, MUL3
uqinch w0, mul3, mul #1
uqinch w0
UQINCH W0
uqinch w0, all
uqinch w0, all, mul #1
uqinch w0, pow2, mul #8
UQINCH W0, POW2, MUL #8
uqinch w0, pow2, mul #9
UQINCH W0, POW2, MUL #9
uqinch w0, pow2, mul #10
UQINCH W0, POW2, MUL #10
uqinch w0, pow2, mul #16
UQINCH W0, POW2, MUL #16
uqinch x0, pow2
UQINCH X0, POW2
uqinch x0, pow2, mul #1
uqinch x1, pow2
UQINCH X1, POW2
uqinch x1, pow2, mul #1
uqinch xzr, pow2
UQINCH XZR, POW2
uqinch xzr, pow2, mul #1
uqinch x0, vl1
UQINCH X0, VL1
uqinch x0, vl1, mul #1
uqinch x0, vl2
UQINCH X0, VL2
uqinch x0, vl2, mul #1
uqinch x0, vl3
UQINCH X0, VL3
uqinch x0, vl3, mul #1
uqinch x0, vl4
UQINCH X0, VL4
uqinch x0, vl4, mul #1
uqinch x0, vl5
UQINCH X0, VL5
uqinch x0, vl5, mul #1
uqinch x0, vl6
UQINCH X0, VL6
uqinch x0, vl6, mul #1
uqinch x0, vl7
UQINCH X0, VL7
uqinch x0, vl7, mul #1
uqinch x0, vl8
UQINCH X0, VL8
uqinch x0, vl8, mul #1
uqinch x0, vl16
UQINCH X0, VL16
uqinch x0, vl16, mul #1
uqinch x0, vl32
UQINCH X0, VL32
uqinch x0, vl32, mul #1
uqinch x0, vl64
UQINCH X0, VL64
uqinch x0, vl64, mul #1
uqinch x0, vl128
UQINCH X0, VL128
uqinch x0, vl128, mul #1
uqinch x0, vl256
UQINCH X0, VL256
uqinch x0, vl256, mul #1
uqinch x0, #14
UQINCH X0, #14
uqinch x0, #14, mul #1
uqinch x0, #15
UQINCH X0, #15
uqinch x0, #15, mul #1
uqinch x0, #16
UQINCH X0, #16
uqinch x0, #16, mul #1
uqinch x0, #17
UQINCH X0, #17
uqinch x0, #17, mul #1
uqinch x0, #18
UQINCH X0, #18
uqinch x0, #18, mul #1
uqinch x0, #19
UQINCH X0, #19
uqinch x0, #19, mul #1
uqinch x0, #20
UQINCH X0, #20
uqinch x0, #20, mul #1
uqinch x0, #21
UQINCH X0, #21
uqinch x0, #21, mul #1
uqinch x0, #22
UQINCH X0, #22
uqinch x0, #22, mul #1
uqinch x0, #23
UQINCH X0, #23
uqinch x0, #23, mul #1
uqinch x0, #24
UQINCH X0, #24
uqinch x0, #24, mul #1
uqinch x0, #25
UQINCH X0, #25
uqinch x0, #25, mul #1
uqinch x0, #26
UQINCH X0, #26
uqinch x0, #26, mul #1
uqinch x0, #27
UQINCH X0, #27
uqinch x0, #27, mul #1
uqinch x0, #28
UQINCH X0, #28
uqinch x0, #28, mul #1
uqinch x0, mul4
UQINCH X0, MUL4
uqinch x0, mul4, mul #1
uqinch x0, mul3
UQINCH X0, MUL3
uqinch x0, mul3, mul #1
uqinch x0
UQINCH X0
uqinch x0, all
uqinch x0, all, mul #1
uqinch x0, pow2, mul #8
UQINCH X0, POW2, MUL #8
uqinch x0, pow2, mul #9
UQINCH X0, POW2, MUL #9
uqinch x0, pow2, mul #10
UQINCH X0, POW2, MUL #10
uqinch x0, pow2, mul #16
UQINCH X0, POW2, MUL #16
uqincp z0.h, p0
UQINCP Z0.H, P0
uqincp z1.h, p0
UQINCP Z1.H, P0
uqincp z31.h, p0
UQINCP Z31.H, P0
uqincp z0.h, p2
UQINCP Z0.H, P2
uqincp z0.h, p15
UQINCP Z0.H, P15
uqincp z0.s, p0
UQINCP Z0.S, P0
uqincp z1.s, p0
UQINCP Z1.S, P0
uqincp z31.s, p0
UQINCP Z31.S, P0
uqincp z0.s, p2
UQINCP Z0.S, P2
uqincp z0.s, p15
UQINCP Z0.S, P15
uqincp z0.d, p0
UQINCP Z0.D, P0
uqincp z1.d, p0
UQINCP Z1.D, P0
uqincp z31.d, p0
UQINCP Z31.D, P0
uqincp z0.d, p2
UQINCP Z0.D, P2
uqincp z0.d, p15
UQINCP Z0.D, P15
uqincp w0, p0.b
UQINCP W0, P0.B
uqincp w1, p0.b
UQINCP W1, P0.B
uqincp wzr, p0.b
UQINCP WZR, P0.B
uqincp w0, p2.b
UQINCP W0, P2.B
uqincp w0, p15.b
UQINCP W0, P15.B
uqincp w0, p0.h
UQINCP W0, P0.H
uqincp w1, p0.h
UQINCP W1, P0.H
uqincp wzr, p0.h
UQINCP WZR, P0.H
uqincp w0, p2.h
UQINCP W0, P2.H
uqincp w0, p15.h
UQINCP W0, P15.H
uqincp w0, p0.s
UQINCP W0, P0.S
uqincp w1, p0.s
UQINCP W1, P0.S
uqincp wzr, p0.s
UQINCP WZR, P0.S
uqincp w0, p2.s
UQINCP W0, P2.S
uqincp w0, p15.s
UQINCP W0, P15.S
uqincp w0, p0.d
UQINCP W0, P0.D
uqincp w1, p0.d
UQINCP W1, P0.D
uqincp wzr, p0.d
UQINCP WZR, P0.D
uqincp w0, p2.d
UQINCP W0, P2.D
uqincp w0, p15.d
UQINCP W0, P15.D
uqincp x0, p0.b
UQINCP X0, P0.B
uqincp x1, p0.b
UQINCP X1, P0.B
uqincp xzr, p0.b
UQINCP XZR, P0.B
uqincp x0, p2.b
UQINCP X0, P2.B
uqincp x0, p15.b
UQINCP X0, P15.B
uqincp x0, p0.h
UQINCP X0, P0.H
uqincp x1, p0.h
UQINCP X1, P0.H
uqincp xzr, p0.h
UQINCP XZR, P0.H
uqincp x0, p2.h
UQINCP X0, P2.H
uqincp x0, p15.h
UQINCP X0, P15.H
uqincp x0, p0.s
UQINCP X0, P0.S
uqincp x1, p0.s
UQINCP X1, P0.S
uqincp xzr, p0.s
UQINCP XZR, P0.S
uqincp x0, p2.s
UQINCP X0, P2.S
uqincp x0, p15.s
UQINCP X0, P15.S
uqincp x0, p0.d
UQINCP X0, P0.D
uqincp x1, p0.d
UQINCP X1, P0.D
uqincp xzr, p0.d
UQINCP XZR, P0.D
uqincp x0, p2.d
UQINCP X0, P2.D
uqincp x0, p15.d
UQINCP X0, P15.D
uqincw z0.s, pow2
UQINCW Z0.S, POW2
uqincw z0.s, pow2, mul #1
uqincw z1.s, pow2
UQINCW Z1.S, POW2
uqincw z1.s, pow2, mul #1
uqincw z31.s, pow2
UQINCW Z31.S, POW2
uqincw z31.s, pow2, mul #1
uqincw z0.s, vl1
UQINCW Z0.S, VL1
uqincw z0.s, vl1, mul #1
uqincw z0.s, vl2
UQINCW Z0.S, VL2
uqincw z0.s, vl2, mul #1
uqincw z0.s, vl3
UQINCW Z0.S, VL3
uqincw z0.s, vl3, mul #1
uqincw z0.s, vl4
UQINCW Z0.S, VL4
uqincw z0.s, vl4, mul #1
uqincw z0.s, vl5
UQINCW Z0.S, VL5
uqincw z0.s, vl5, mul #1
uqincw z0.s, vl6
UQINCW Z0.S, VL6
uqincw z0.s, vl6, mul #1
uqincw z0.s, vl7
UQINCW Z0.S, VL7
uqincw z0.s, vl7, mul #1
uqincw z0.s, vl8
UQINCW Z0.S, VL8
uqincw z0.s, vl8, mul #1
uqincw z0.s, vl16
UQINCW Z0.S, VL16
uqincw z0.s, vl16, mul #1
uqincw z0.s, vl32
UQINCW Z0.S, VL32
uqincw z0.s, vl32, mul #1
uqincw z0.s, vl64
UQINCW Z0.S, VL64
uqincw z0.s, vl64, mul #1
uqincw z0.s, vl128
UQINCW Z0.S, VL128
uqincw z0.s, vl128, mul #1
uqincw z0.s, vl256
UQINCW Z0.S, VL256
uqincw z0.s, vl256, mul #1
uqincw z0.s, #14
UQINCW Z0.S, #14
uqincw z0.s, #14, mul #1
uqincw z0.s, #15
UQINCW Z0.S, #15
uqincw z0.s, #15, mul #1
uqincw z0.s, #16
UQINCW Z0.S, #16
uqincw z0.s, #16, mul #1
uqincw z0.s, #17
UQINCW Z0.S, #17
uqincw z0.s, #17, mul #1
uqincw z0.s, #18
UQINCW Z0.S, #18
uqincw z0.s, #18, mul #1
uqincw z0.s, #19
UQINCW Z0.S, #19
uqincw z0.s, #19, mul #1
uqincw z0.s, #20
UQINCW Z0.S, #20
uqincw z0.s, #20, mul #1
uqincw z0.s, #21
UQINCW Z0.S, #21
uqincw z0.s, #21, mul #1
uqincw z0.s, #22
UQINCW Z0.S, #22
uqincw z0.s, #22, mul #1
uqincw z0.s, #23
UQINCW Z0.S, #23
uqincw z0.s, #23, mul #1
uqincw z0.s, #24
UQINCW Z0.S, #24
uqincw z0.s, #24, mul #1
uqincw z0.s, #25
UQINCW Z0.S, #25
uqincw z0.s, #25, mul #1
uqincw z0.s, #26
UQINCW Z0.S, #26
uqincw z0.s, #26, mul #1
uqincw z0.s, #27
UQINCW Z0.S, #27
uqincw z0.s, #27, mul #1
uqincw z0.s, #28
UQINCW Z0.S, #28
uqincw z0.s, #28, mul #1
uqincw z0.s, mul4
UQINCW Z0.S, MUL4
uqincw z0.s, mul4, mul #1
uqincw z0.s, mul3
UQINCW Z0.S, MUL3
uqincw z0.s, mul3, mul #1
uqincw z0.s
UQINCW Z0.S
uqincw z0.s, all
uqincw z0.s, all, mul #1
uqincw z0.s, pow2, mul #8
UQINCW Z0.S, POW2, MUL #8
uqincw z0.s, pow2, mul #9
UQINCW Z0.S, POW2, MUL #9
uqincw z0.s, pow2, mul #10
UQINCW Z0.S, POW2, MUL #10
uqincw z0.s, pow2, mul #16
UQINCW Z0.S, POW2, MUL #16
uqincw w0, pow2
UQINCW W0, POW2
uqincw w0, pow2, mul #1
uqincw w1, pow2
UQINCW W1, POW2
uqincw w1, pow2, mul #1
uqincw wzr, pow2
UQINCW WZR, POW2
uqincw wzr, pow2, mul #1
uqincw w0, vl1
UQINCW W0, VL1
uqincw w0, vl1, mul #1
uqincw w0, vl2
UQINCW W0, VL2
uqincw w0, vl2, mul #1
uqincw w0, vl3
UQINCW W0, VL3
uqincw w0, vl3, mul #1
uqincw w0, vl4
UQINCW W0, VL4
uqincw w0, vl4, mul #1
uqincw w0, vl5
UQINCW W0, VL5
uqincw w0, vl5, mul #1
uqincw w0, vl6
UQINCW W0, VL6
uqincw w0, vl6, mul #1
uqincw w0, vl7
UQINCW W0, VL7
uqincw w0, vl7, mul #1
uqincw w0, vl8
UQINCW W0, VL8
uqincw w0, vl8, mul #1
uqincw w0, vl16
UQINCW W0, VL16
uqincw w0, vl16, mul #1
uqincw w0, vl32
UQINCW W0, VL32
uqincw w0, vl32, mul #1
uqincw w0, vl64
UQINCW W0, VL64
uqincw w0, vl64, mul #1
uqincw w0, vl128
UQINCW W0, VL128
uqincw w0, vl128, mul #1
uqincw w0, vl256
UQINCW W0, VL256
uqincw w0, vl256, mul #1
uqincw w0, #14
UQINCW W0, #14
uqincw w0, #14, mul #1
uqincw w0, #15
UQINCW W0, #15
uqincw w0, #15, mul #1
uqincw w0, #16
UQINCW W0, #16
uqincw w0, #16, mul #1
uqincw w0, #17
UQINCW W0, #17
uqincw w0, #17, mul #1
uqincw w0, #18
UQINCW W0, #18
uqincw w0, #18, mul #1
uqincw w0, #19
UQINCW W0, #19
uqincw w0, #19, mul #1
uqincw w0, #20
UQINCW W0, #20
uqincw w0, #20, mul #1
uqincw w0, #21
UQINCW W0, #21
uqincw w0, #21, mul #1
uqincw w0, #22
UQINCW W0, #22
uqincw w0, #22, mul #1
uqincw w0, #23
UQINCW W0, #23
uqincw w0, #23, mul #1
uqincw w0, #24
UQINCW W0, #24
uqincw w0, #24, mul #1
uqincw w0, #25
UQINCW W0, #25
uqincw w0, #25, mul #1
uqincw w0, #26
UQINCW W0, #26
uqincw w0, #26, mul #1
uqincw w0, #27
UQINCW W0, #27
uqincw w0, #27, mul #1
uqincw w0, #28
UQINCW W0, #28
uqincw w0, #28, mul #1
uqincw w0, mul4
UQINCW W0, MUL4
uqincw w0, mul4, mul #1
uqincw w0, mul3
UQINCW W0, MUL3
uqincw w0, mul3, mul #1
uqincw w0
UQINCW W0
uqincw w0, all
uqincw w0, all, mul #1
uqincw w0, pow2, mul #8
UQINCW W0, POW2, MUL #8
uqincw w0, pow2, mul #9
UQINCW W0, POW2, MUL #9
uqincw w0, pow2, mul #10
UQINCW W0, POW2, MUL #10
uqincw w0, pow2, mul #16
UQINCW W0, POW2, MUL #16
uqincw x0, pow2
UQINCW X0, POW2
uqincw x0, pow2, mul #1
uqincw x1, pow2
UQINCW X1, POW2
uqincw x1, pow2, mul #1
uqincw xzr, pow2
UQINCW XZR, POW2
uqincw xzr, pow2, mul #1
uqincw x0, vl1
UQINCW X0, VL1
uqincw x0, vl1, mul #1
uqincw x0, vl2
UQINCW X0, VL2
uqincw x0, vl2, mul #1
uqincw x0, vl3
UQINCW X0, VL3
uqincw x0, vl3, mul #1
uqincw x0, vl4
UQINCW X0, VL4
uqincw x0, vl4, mul #1
uqincw x0, vl5
UQINCW X0, VL5
uqincw x0, vl5, mul #1
uqincw x0, vl6
UQINCW X0, VL6
uqincw x0, vl6, mul #1
uqincw x0, vl7
UQINCW X0, VL7
uqincw x0, vl7, mul #1
uqincw x0, vl8
UQINCW X0, VL8
uqincw x0, vl8, mul #1
uqincw x0, vl16
UQINCW X0, VL16
uqincw x0, vl16, mul #1
uqincw x0, vl32
UQINCW X0, VL32
uqincw x0, vl32, mul #1
uqincw x0, vl64
UQINCW X0, VL64
uqincw x0, vl64, mul #1
uqincw x0, vl128
UQINCW X0, VL128
uqincw x0, vl128, mul #1
uqincw x0, vl256
UQINCW X0, VL256
uqincw x0, vl256, mul #1
uqincw x0, #14
UQINCW X0, #14
uqincw x0, #14, mul #1
uqincw x0, #15
UQINCW X0, #15
uqincw x0, #15, mul #1
uqincw x0, #16
UQINCW X0, #16
uqincw x0, #16, mul #1
uqincw x0, #17
UQINCW X0, #17
uqincw x0, #17, mul #1
uqincw x0, #18
UQINCW X0, #18
uqincw x0, #18, mul #1
uqincw x0, #19
UQINCW X0, #19
uqincw x0, #19, mul #1
uqincw x0, #20
UQINCW X0, #20
uqincw x0, #20, mul #1
uqincw x0, #21
UQINCW X0, #21
uqincw x0, #21, mul #1
uqincw x0, #22
UQINCW X0, #22
uqincw x0, #22, mul #1
uqincw x0, #23
UQINCW X0, #23
uqincw x0, #23, mul #1
uqincw x0, #24
UQINCW X0, #24
uqincw x0, #24, mul #1
uqincw x0, #25
UQINCW X0, #25
uqincw x0, #25, mul #1
uqincw x0, #26
UQINCW X0, #26
uqincw x0, #26, mul #1
uqincw x0, #27
UQINCW X0, #27
uqincw x0, #27, mul #1
uqincw x0, #28
UQINCW X0, #28
uqincw x0, #28, mul #1
uqincw x0, mul4
UQINCW X0, MUL4
uqincw x0, mul4, mul #1
uqincw x0, mul3
UQINCW X0, MUL3
uqincw x0, mul3, mul #1
uqincw x0
UQINCW X0
uqincw x0, all
uqincw x0, all, mul #1
uqincw x0, pow2, mul #8
UQINCW X0, POW2, MUL #8
uqincw x0, pow2, mul #9
UQINCW X0, POW2, MUL #9
uqincw x0, pow2, mul #10
UQINCW X0, POW2, MUL #10
uqincw x0, pow2, mul #16
UQINCW X0, POW2, MUL #16
uqsub z0.b, z0.b, z0.b
UQSUB Z0.B, Z0.B, Z0.B
uqsub z1.b, z0.b, z0.b
UQSUB Z1.B, Z0.B, Z0.B
uqsub z31.b, z0.b, z0.b
UQSUB Z31.B, Z0.B, Z0.B
uqsub z0.b, z2.b, z0.b
UQSUB Z0.B, Z2.B, Z0.B
uqsub z0.b, z31.b, z0.b
UQSUB Z0.B, Z31.B, Z0.B
uqsub z0.b, z0.b, z3.b
UQSUB Z0.B, Z0.B, Z3.B
uqsub z0.b, z0.b, z31.b
UQSUB Z0.B, Z0.B, Z31.B
uqsub z0.h, z0.h, z0.h
UQSUB Z0.H, Z0.H, Z0.H
uqsub z1.h, z0.h, z0.h
UQSUB Z1.H, Z0.H, Z0.H
uqsub z31.h, z0.h, z0.h
UQSUB Z31.H, Z0.H, Z0.H
uqsub z0.h, z2.h, z0.h
UQSUB Z0.H, Z2.H, Z0.H
uqsub z0.h, z31.h, z0.h
UQSUB Z0.H, Z31.H, Z0.H
uqsub z0.h, z0.h, z3.h
UQSUB Z0.H, Z0.H, Z3.H
uqsub z0.h, z0.h, z31.h
UQSUB Z0.H, Z0.H, Z31.H
uqsub z0.s, z0.s, z0.s
UQSUB Z0.S, Z0.S, Z0.S
uqsub z1.s, z0.s, z0.s
UQSUB Z1.S, Z0.S, Z0.S
uqsub z31.s, z0.s, z0.s
UQSUB Z31.S, Z0.S, Z0.S
uqsub z0.s, z2.s, z0.s
UQSUB Z0.S, Z2.S, Z0.S
uqsub z0.s, z31.s, z0.s
UQSUB Z0.S, Z31.S, Z0.S
uqsub z0.s, z0.s, z3.s
UQSUB Z0.S, Z0.S, Z3.S
uqsub z0.s, z0.s, z31.s
UQSUB Z0.S, Z0.S, Z31.S
uqsub z0.d, z0.d, z0.d
UQSUB Z0.D, Z0.D, Z0.D
uqsub z1.d, z0.d, z0.d
UQSUB Z1.D, Z0.D, Z0.D
uqsub z31.d, z0.d, z0.d
UQSUB Z31.D, Z0.D, Z0.D
uqsub z0.d, z2.d, z0.d
UQSUB Z0.D, Z2.D, Z0.D
uqsub z0.d, z31.d, z0.d
UQSUB Z0.D, Z31.D, Z0.D
uqsub z0.d, z0.d, z3.d
UQSUB Z0.D, Z0.D, Z3.D
uqsub z0.d, z0.d, z31.d
UQSUB Z0.D, Z0.D, Z31.D
uqsub z0.b, z0.b, #0
UQSUB Z0.B, Z0.B, #0
uqsub z0.b, z0.b, #0, lsl #0
uqsub z1.b, z1.b, #0
UQSUB Z1.B, Z1.B, #0
uqsub z1.b, z1.b, #0, lsl #0
uqsub z31.b, z31.b, #0
UQSUB Z31.B, Z31.B, #0
uqsub z31.b, z31.b, #0, lsl #0
uqsub z2.b, z2.b, #0
UQSUB Z2.B, Z2.B, #0
uqsub z2.b, z2.b, #0, lsl #0
uqsub z0.b, z0.b, #127
UQSUB Z0.B, Z0.B, #127
uqsub z0.b, z0.b, #127, lsl #0
uqsub z0.b, z0.b, #128
UQSUB Z0.B, Z0.B, #128
uqsub z0.b, z0.b, #128, lsl #0
uqsub z0.b, z0.b, #129
UQSUB Z0.B, Z0.B, #129
uqsub z0.b, z0.b, #129, lsl #0
uqsub z0.b, z0.b, #255
UQSUB Z0.B, Z0.B, #255
uqsub z0.b, z0.b, #255, lsl #0
uqsub z0.h, z0.h, #0
UQSUB Z0.H, Z0.H, #0
uqsub z0.h, z0.h, #0, lsl #0
uqsub z1.h, z1.h, #0
UQSUB Z1.H, Z1.H, #0
uqsub z1.h, z1.h, #0, lsl #0
uqsub z31.h, z31.h, #0
UQSUB Z31.H, Z31.H, #0
uqsub z31.h, z31.h, #0, lsl #0
uqsub z2.h, z2.h, #0
UQSUB Z2.H, Z2.H, #0
uqsub z2.h, z2.h, #0, lsl #0
uqsub z0.h, z0.h, #127
UQSUB Z0.H, Z0.H, #127
uqsub z0.h, z0.h, #127, lsl #0
uqsub z0.h, z0.h, #128
UQSUB Z0.H, Z0.H, #128
uqsub z0.h, z0.h, #128, lsl #0
uqsub z0.h, z0.h, #129
UQSUB Z0.H, Z0.H, #129
uqsub z0.h, z0.h, #129, lsl #0
uqsub z0.h, z0.h, #255
UQSUB Z0.H, Z0.H, #255
uqsub z0.h, z0.h, #255, lsl #0
uqsub z0.h, z0.h, #0, lsl #8
UQSUB Z0.H, Z0.H, #0, LSL #8
uqsub z0.h, z0.h, #32512
UQSUB Z0.H, Z0.H, #32512
uqsub z0.h, z0.h, #32512, lsl #0
uqsub z0.h, z0.h, #127, lsl #8
uqsub z0.h, z0.h, #32768
UQSUB Z0.H, Z0.H, #32768
uqsub z0.h, z0.h, #32768, lsl #0
uqsub z0.h, z0.h, #128, lsl #8
uqsub z0.h, z0.h, #33024
UQSUB Z0.H, Z0.H, #33024
uqsub z0.h, z0.h, #33024, lsl #0
uqsub z0.h, z0.h, #129, lsl #8
uqsub z0.h, z0.h, #65280
UQSUB Z0.H, Z0.H, #65280
uqsub z0.h, z0.h, #65280, lsl #0
uqsub z0.h, z0.h, #255, lsl #8
uqsub z0.s, z0.s, #0
UQSUB Z0.S, Z0.S, #0
uqsub z0.s, z0.s, #0, lsl #0
uqsub z1.s, z1.s, #0
UQSUB Z1.S, Z1.S, #0
uqsub z1.s, z1.s, #0, lsl #0
uqsub z31.s, z31.s, #0
UQSUB Z31.S, Z31.S, #0
uqsub z31.s, z31.s, #0, lsl #0
uqsub z2.s, z2.s, #0
UQSUB Z2.S, Z2.S, #0
uqsub z2.s, z2.s, #0, lsl #0
uqsub z0.s, z0.s, #127
UQSUB Z0.S, Z0.S, #127
uqsub z0.s, z0.s, #127, lsl #0
uqsub z0.s, z0.s, #128
UQSUB Z0.S, Z0.S, #128
uqsub z0.s, z0.s, #128, lsl #0
uqsub z0.s, z0.s, #129
UQSUB Z0.S, Z0.S, #129
uqsub z0.s, z0.s, #129, lsl #0
uqsub z0.s, z0.s, #255
UQSUB Z0.S, Z0.S, #255
uqsub z0.s, z0.s, #255, lsl #0
uqsub z0.s, z0.s, #0, lsl #8
UQSUB Z0.S, Z0.S, #0, LSL #8
uqsub z0.s, z0.s, #32512
UQSUB Z0.S, Z0.S, #32512
uqsub z0.s, z0.s, #32512, lsl #0
uqsub z0.s, z0.s, #127, lsl #8
uqsub z0.s, z0.s, #32768
UQSUB Z0.S, Z0.S, #32768
uqsub z0.s, z0.s, #32768, lsl #0
uqsub z0.s, z0.s, #128, lsl #8
uqsub z0.s, z0.s, #33024
UQSUB Z0.S, Z0.S, #33024
uqsub z0.s, z0.s, #33024, lsl #0
uqsub z0.s, z0.s, #129, lsl #8
uqsub z0.s, z0.s, #65280
UQSUB Z0.S, Z0.S, #65280
uqsub z0.s, z0.s, #65280, lsl #0
uqsub z0.s, z0.s, #255, lsl #8
uqsub z0.d, z0.d, #0
UQSUB Z0.D, Z0.D, #0
uqsub z0.d, z0.d, #0, lsl #0
uqsub z1.d, z1.d, #0
UQSUB Z1.D, Z1.D, #0
uqsub z1.d, z1.d, #0, lsl #0
uqsub z31.d, z31.d, #0
UQSUB Z31.D, Z31.D, #0
uqsub z31.d, z31.d, #0, lsl #0
uqsub z2.d, z2.d, #0
UQSUB Z2.D, Z2.D, #0
uqsub z2.d, z2.d, #0, lsl #0
uqsub z0.d, z0.d, #127
UQSUB Z0.D, Z0.D, #127
uqsub z0.d, z0.d, #127, lsl #0
uqsub z0.d, z0.d, #128
UQSUB Z0.D, Z0.D, #128
uqsub z0.d, z0.d, #128, lsl #0
uqsub z0.d, z0.d, #129
UQSUB Z0.D, Z0.D, #129
uqsub z0.d, z0.d, #129, lsl #0
uqsub z0.d, z0.d, #255
UQSUB Z0.D, Z0.D, #255
uqsub z0.d, z0.d, #255, lsl #0
uqsub z0.d, z0.d, #0, lsl #8
UQSUB Z0.D, Z0.D, #0, LSL #8
uqsub z0.d, z0.d, #32512
UQSUB Z0.D, Z0.D, #32512
uqsub z0.d, z0.d, #32512, lsl #0
uqsub z0.d, z0.d, #127, lsl #8
uqsub z0.d, z0.d, #32768
UQSUB Z0.D, Z0.D, #32768
uqsub z0.d, z0.d, #32768, lsl #0
uqsub z0.d, z0.d, #128, lsl #8
uqsub z0.d, z0.d, #33024
UQSUB Z0.D, Z0.D, #33024
uqsub z0.d, z0.d, #33024, lsl #0
uqsub z0.d, z0.d, #129, lsl #8
uqsub z0.d, z0.d, #65280
UQSUB Z0.D, Z0.D, #65280
uqsub z0.d, z0.d, #65280, lsl #0
uqsub z0.d, z0.d, #255, lsl #8
uunpkhi z0.h, z0.b
UUNPKHI Z0.H, Z0.B
uunpkhi z1.h, z0.b
UUNPKHI Z1.H, Z0.B
uunpkhi z31.h, z0.b
UUNPKHI Z31.H, Z0.B
uunpkhi z0.h, z2.b
UUNPKHI Z0.H, Z2.B
uunpkhi z0.h, z31.b
UUNPKHI Z0.H, Z31.B
uunpkhi z0.s, z0.h
UUNPKHI Z0.S, Z0.H
uunpkhi z1.s, z0.h
UUNPKHI Z1.S, Z0.H
uunpkhi z31.s, z0.h
UUNPKHI Z31.S, Z0.H
uunpkhi z0.s, z2.h
UUNPKHI Z0.S, Z2.H
uunpkhi z0.s, z31.h
UUNPKHI Z0.S, Z31.H
uunpkhi z0.d, z0.s
UUNPKHI Z0.D, Z0.S
uunpkhi z1.d, z0.s
UUNPKHI Z1.D, Z0.S
uunpkhi z31.d, z0.s
UUNPKHI Z31.D, Z0.S
uunpkhi z0.d, z2.s
UUNPKHI Z0.D, Z2.S
uunpkhi z0.d, z31.s
UUNPKHI Z0.D, Z31.S
uunpklo z0.h, z0.b
UUNPKLO Z0.H, Z0.B
uunpklo z1.h, z0.b
UUNPKLO Z1.H, Z0.B
uunpklo z31.h, z0.b
UUNPKLO Z31.H, Z0.B
uunpklo z0.h, z2.b
UUNPKLO Z0.H, Z2.B
uunpklo z0.h, z31.b
UUNPKLO Z0.H, Z31.B
uunpklo z0.s, z0.h
UUNPKLO Z0.S, Z0.H
uunpklo z1.s, z0.h
UUNPKLO Z1.S, Z0.H
uunpklo z31.s, z0.h
UUNPKLO Z31.S, Z0.H
uunpklo z0.s, z2.h
UUNPKLO Z0.S, Z2.H
uunpklo z0.s, z31.h
UUNPKLO Z0.S, Z31.H
uunpklo z0.d, z0.s
UUNPKLO Z0.D, Z0.S
uunpklo z1.d, z0.s
UUNPKLO Z1.D, Z0.S
uunpklo z31.d, z0.s
UUNPKLO Z31.D, Z0.S
uunpklo z0.d, z2.s
UUNPKLO Z0.D, Z2.S
uunpklo z0.d, z31.s
UUNPKLO Z0.D, Z31.S
uxtb z0.h, p0/m, z0.h
UXTB Z0.H, P0/M, Z0.H
uxtb z1.h, p0/m, z0.h
UXTB Z1.H, P0/M, Z0.H
uxtb z31.h, p0/m, z0.h
UXTB Z31.H, P0/M, Z0.H
uxtb z0.h, p2/m, z0.h
UXTB Z0.H, P2/M, Z0.H
uxtb z0.h, p7/m, z0.h
UXTB Z0.H, P7/M, Z0.H
uxtb z0.h, p0/m, z3.h
UXTB Z0.H, P0/M, Z3.H
uxtb z0.h, p0/m, z31.h
UXTB Z0.H, P0/M, Z31.H
uxtb z0.s, p0/m, z0.s
UXTB Z0.S, P0/M, Z0.S
uxtb z1.s, p0/m, z0.s
UXTB Z1.S, P0/M, Z0.S
uxtb z31.s, p0/m, z0.s
UXTB Z31.S, P0/M, Z0.S
uxtb z0.s, p2/m, z0.s
UXTB Z0.S, P2/M, Z0.S
uxtb z0.s, p7/m, z0.s
UXTB Z0.S, P7/M, Z0.S
uxtb z0.s, p0/m, z3.s
UXTB Z0.S, P0/M, Z3.S
uxtb z0.s, p0/m, z31.s
UXTB Z0.S, P0/M, Z31.S
uxtb z0.d, p0/m, z0.d
UXTB Z0.D, P0/M, Z0.D
uxtb z1.d, p0/m, z0.d
UXTB Z1.D, P0/M, Z0.D
uxtb z31.d, p0/m, z0.d
UXTB Z31.D, P0/M, Z0.D
uxtb z0.d, p2/m, z0.d
UXTB Z0.D, P2/M, Z0.D
uxtb z0.d, p7/m, z0.d
UXTB Z0.D, P7/M, Z0.D
uxtb z0.d, p0/m, z3.d
UXTB Z0.D, P0/M, Z3.D
uxtb z0.d, p0/m, z31.d
UXTB Z0.D, P0/M, Z31.D
uxth z0.s, p0/m, z0.s
UXTH Z0.S, P0/M, Z0.S
uxth z1.s, p0/m, z0.s
UXTH Z1.S, P0/M, Z0.S
uxth z31.s, p0/m, z0.s
UXTH Z31.S, P0/M, Z0.S
uxth z0.s, p2/m, z0.s
UXTH Z0.S, P2/M, Z0.S
uxth z0.s, p7/m, z0.s
UXTH Z0.S, P7/M, Z0.S
uxth z0.s, p0/m, z3.s
UXTH Z0.S, P0/M, Z3.S
uxth z0.s, p0/m, z31.s
UXTH Z0.S, P0/M, Z31.S
uxth z0.d, p0/m, z0.d
UXTH Z0.D, P0/M, Z0.D
uxth z1.d, p0/m, z0.d
UXTH Z1.D, P0/M, Z0.D
uxth z31.d, p0/m, z0.d
UXTH Z31.D, P0/M, Z0.D
uxth z0.d, p2/m, z0.d
UXTH Z0.D, P2/M, Z0.D
uxth z0.d, p7/m, z0.d
UXTH Z0.D, P7/M, Z0.D
uxth z0.d, p0/m, z3.d
UXTH Z0.D, P0/M, Z3.D
uxth z0.d, p0/m, z31.d
UXTH Z0.D, P0/M, Z31.D
uxtw z0.d, p0/m, z0.d
UXTW Z0.D, P0/M, Z0.D
uxtw z1.d, p0/m, z0.d
UXTW Z1.D, P0/M, Z0.D
uxtw z31.d, p0/m, z0.d
UXTW Z31.D, P0/M, Z0.D
uxtw z0.d, p2/m, z0.d
UXTW Z0.D, P2/M, Z0.D
uxtw z0.d, p7/m, z0.d
UXTW Z0.D, P7/M, Z0.D
uxtw z0.d, p0/m, z3.d
UXTW Z0.D, P0/M, Z3.D
uxtw z0.d, p0/m, z31.d
UXTW Z0.D, P0/M, Z31.D
uzp1 p0.b, p0.b, p0.b
UZP1 P0.B, P0.B, P0.B
uzp1 p1.b, p0.b, p0.b
UZP1 P1.B, P0.B, P0.B
uzp1 p15.b, p0.b, p0.b
UZP1 P15.B, P0.B, P0.B
uzp1 p0.b, p2.b, p0.b
UZP1 P0.B, P2.B, P0.B
uzp1 p0.b, p15.b, p0.b
UZP1 P0.B, P15.B, P0.B
uzp1 p0.b, p0.b, p3.b
UZP1 P0.B, P0.B, P3.B
uzp1 p0.b, p0.b, p15.b
UZP1 P0.B, P0.B, P15.B
uzp1 p0.h, p0.h, p0.h
UZP1 P0.H, P0.H, P0.H
uzp1 p1.h, p0.h, p0.h
UZP1 P1.H, P0.H, P0.H
uzp1 p15.h, p0.h, p0.h
UZP1 P15.H, P0.H, P0.H
uzp1 p0.h, p2.h, p0.h
UZP1 P0.H, P2.H, P0.H
uzp1 p0.h, p15.h, p0.h
UZP1 P0.H, P15.H, P0.H
uzp1 p0.h, p0.h, p3.h
UZP1 P0.H, P0.H, P3.H
uzp1 p0.h, p0.h, p15.h
UZP1 P0.H, P0.H, P15.H
uzp1 p0.s, p0.s, p0.s
UZP1 P0.S, P0.S, P0.S
uzp1 p1.s, p0.s, p0.s
UZP1 P1.S, P0.S, P0.S
uzp1 p15.s, p0.s, p0.s
UZP1 P15.S, P0.S, P0.S
uzp1 p0.s, p2.s, p0.s
UZP1 P0.S, P2.S, P0.S
uzp1 p0.s, p15.s, p0.s
UZP1 P0.S, P15.S, P0.S
uzp1 p0.s, p0.s, p3.s
UZP1 P0.S, P0.S, P3.S
uzp1 p0.s, p0.s, p15.s
UZP1 P0.S, P0.S, P15.S
uzp1 p0.d, p0.d, p0.d
UZP1 P0.D, P0.D, P0.D
uzp1 p1.d, p0.d, p0.d
UZP1 P1.D, P0.D, P0.D
uzp1 p15.d, p0.d, p0.d
UZP1 P15.D, P0.D, P0.D
uzp1 p0.d, p2.d, p0.d
UZP1 P0.D, P2.D, P0.D
uzp1 p0.d, p15.d, p0.d
UZP1 P0.D, P15.D, P0.D
uzp1 p0.d, p0.d, p3.d
UZP1 P0.D, P0.D, P3.D
uzp1 p0.d, p0.d, p15.d
UZP1 P0.D, P0.D, P15.D
uzp1 z0.b, z0.b, z0.b
UZP1 Z0.B, Z0.B, Z0.B
uzp1 z1.b, z0.b, z0.b
UZP1 Z1.B, Z0.B, Z0.B
uzp1 z31.b, z0.b, z0.b
UZP1 Z31.B, Z0.B, Z0.B
uzp1 z0.b, z2.b, z0.b
UZP1 Z0.B, Z2.B, Z0.B
uzp1 z0.b, z31.b, z0.b
UZP1 Z0.B, Z31.B, Z0.B
uzp1 z0.b, z0.b, z3.b
UZP1 Z0.B, Z0.B, Z3.B
uzp1 z0.b, z0.b, z31.b
UZP1 Z0.B, Z0.B, Z31.B
uzp1 z0.h, z0.h, z0.h
UZP1 Z0.H, Z0.H, Z0.H
uzp1 z1.h, z0.h, z0.h
UZP1 Z1.H, Z0.H, Z0.H
uzp1 z31.h, z0.h, z0.h
UZP1 Z31.H, Z0.H, Z0.H
uzp1 z0.h, z2.h, z0.h
UZP1 Z0.H, Z2.H, Z0.H
uzp1 z0.h, z31.h, z0.h
UZP1 Z0.H, Z31.H, Z0.H
uzp1 z0.h, z0.h, z3.h
UZP1 Z0.H, Z0.H, Z3.H
uzp1 z0.h, z0.h, z31.h
UZP1 Z0.H, Z0.H, Z31.H
uzp1 z0.s, z0.s, z0.s
UZP1 Z0.S, Z0.S, Z0.S
uzp1 z1.s, z0.s, z0.s
UZP1 Z1.S, Z0.S, Z0.S
uzp1 z31.s, z0.s, z0.s
UZP1 Z31.S, Z0.S, Z0.S
uzp1 z0.s, z2.s, z0.s
UZP1 Z0.S, Z2.S, Z0.S
uzp1 z0.s, z31.s, z0.s
UZP1 Z0.S, Z31.S, Z0.S
uzp1 z0.s, z0.s, z3.s
UZP1 Z0.S, Z0.S, Z3.S
uzp1 z0.s, z0.s, z31.s
UZP1 Z0.S, Z0.S, Z31.S
uzp1 z0.d, z0.d, z0.d
UZP1 Z0.D, Z0.D, Z0.D
uzp1 z1.d, z0.d, z0.d
UZP1 Z1.D, Z0.D, Z0.D
uzp1 z31.d, z0.d, z0.d
UZP1 Z31.D, Z0.D, Z0.D
uzp1 z0.d, z2.d, z0.d
UZP1 Z0.D, Z2.D, Z0.D
uzp1 z0.d, z31.d, z0.d
UZP1 Z0.D, Z31.D, Z0.D
uzp1 z0.d, z0.d, z3.d
UZP1 Z0.D, Z0.D, Z3.D
uzp1 z0.d, z0.d, z31.d
UZP1 Z0.D, Z0.D, Z31.D
uzp2 p0.b, p0.b, p0.b
UZP2 P0.B, P0.B, P0.B
uzp2 p1.b, p0.b, p0.b
UZP2 P1.B, P0.B, P0.B
uzp2 p15.b, p0.b, p0.b
UZP2 P15.B, P0.B, P0.B
uzp2 p0.b, p2.b, p0.b
UZP2 P0.B, P2.B, P0.B
uzp2 p0.b, p15.b, p0.b
UZP2 P0.B, P15.B, P0.B
uzp2 p0.b, p0.b, p3.b
UZP2 P0.B, P0.B, P3.B
uzp2 p0.b, p0.b, p15.b
UZP2 P0.B, P0.B, P15.B
uzp2 p0.h, p0.h, p0.h
UZP2 P0.H, P0.H, P0.H
uzp2 p1.h, p0.h, p0.h
UZP2 P1.H, P0.H, P0.H
uzp2 p15.h, p0.h, p0.h
UZP2 P15.H, P0.H, P0.H
uzp2 p0.h, p2.h, p0.h
UZP2 P0.H, P2.H, P0.H
uzp2 p0.h, p15.h, p0.h
UZP2 P0.H, P15.H, P0.H
uzp2 p0.h, p0.h, p3.h
UZP2 P0.H, P0.H, P3.H
uzp2 p0.h, p0.h, p15.h
UZP2 P0.H, P0.H, P15.H
uzp2 p0.s, p0.s, p0.s
UZP2 P0.S, P0.S, P0.S
uzp2 p1.s, p0.s, p0.s
UZP2 P1.S, P0.S, P0.S
uzp2 p15.s, p0.s, p0.s
UZP2 P15.S, P0.S, P0.S
uzp2 p0.s, p2.s, p0.s
UZP2 P0.S, P2.S, P0.S
uzp2 p0.s, p15.s, p0.s
UZP2 P0.S, P15.S, P0.S
uzp2 p0.s, p0.s, p3.s
UZP2 P0.S, P0.S, P3.S
uzp2 p0.s, p0.s, p15.s
UZP2 P0.S, P0.S, P15.S
uzp2 p0.d, p0.d, p0.d
UZP2 P0.D, P0.D, P0.D
uzp2 p1.d, p0.d, p0.d
UZP2 P1.D, P0.D, P0.D
uzp2 p15.d, p0.d, p0.d
UZP2 P15.D, P0.D, P0.D
uzp2 p0.d, p2.d, p0.d
UZP2 P0.D, P2.D, P0.D
uzp2 p0.d, p15.d, p0.d
UZP2 P0.D, P15.D, P0.D
uzp2 p0.d, p0.d, p3.d
UZP2 P0.D, P0.D, P3.D
uzp2 p0.d, p0.d, p15.d
UZP2 P0.D, P0.D, P15.D
uzp2 z0.b, z0.b, z0.b
UZP2 Z0.B, Z0.B, Z0.B
uzp2 z1.b, z0.b, z0.b
UZP2 Z1.B, Z0.B, Z0.B
uzp2 z31.b, z0.b, z0.b
UZP2 Z31.B, Z0.B, Z0.B
uzp2 z0.b, z2.b, z0.b
UZP2 Z0.B, Z2.B, Z0.B
uzp2 z0.b, z31.b, z0.b
UZP2 Z0.B, Z31.B, Z0.B
uzp2 z0.b, z0.b, z3.b
UZP2 Z0.B, Z0.B, Z3.B
uzp2 z0.b, z0.b, z31.b
UZP2 Z0.B, Z0.B, Z31.B
uzp2 z0.h, z0.h, z0.h
UZP2 Z0.H, Z0.H, Z0.H
uzp2 z1.h, z0.h, z0.h
UZP2 Z1.H, Z0.H, Z0.H
uzp2 z31.h, z0.h, z0.h
UZP2 Z31.H, Z0.H, Z0.H
uzp2 z0.h, z2.h, z0.h
UZP2 Z0.H, Z2.H, Z0.H
uzp2 z0.h, z31.h, z0.h
UZP2 Z0.H, Z31.H, Z0.H
uzp2 z0.h, z0.h, z3.h
UZP2 Z0.H, Z0.H, Z3.H
uzp2 z0.h, z0.h, z31.h
UZP2 Z0.H, Z0.H, Z31.H
uzp2 z0.s, z0.s, z0.s
UZP2 Z0.S, Z0.S, Z0.S
uzp2 z1.s, z0.s, z0.s
UZP2 Z1.S, Z0.S, Z0.S
uzp2 z31.s, z0.s, z0.s
UZP2 Z31.S, Z0.S, Z0.S
uzp2 z0.s, z2.s, z0.s
UZP2 Z0.S, Z2.S, Z0.S
uzp2 z0.s, z31.s, z0.s
UZP2 Z0.S, Z31.S, Z0.S
uzp2 z0.s, z0.s, z3.s
UZP2 Z0.S, Z0.S, Z3.S
uzp2 z0.s, z0.s, z31.s
UZP2 Z0.S, Z0.S, Z31.S
uzp2 z0.d, z0.d, z0.d
UZP2 Z0.D, Z0.D, Z0.D
uzp2 z1.d, z0.d, z0.d
UZP2 Z1.D, Z0.D, Z0.D
uzp2 z31.d, z0.d, z0.d
UZP2 Z31.D, Z0.D, Z0.D
uzp2 z0.d, z2.d, z0.d
UZP2 Z0.D, Z2.D, Z0.D
uzp2 z0.d, z31.d, z0.d
UZP2 Z0.D, Z31.D, Z0.D
uzp2 z0.d, z0.d, z3.d
UZP2 Z0.D, Z0.D, Z3.D
uzp2 z0.d, z0.d, z31.d
UZP2 Z0.D, Z0.D, Z31.D
whilele p0.b, w0, w0
WHILELE P0.B, W0, W0
whilele p1.b, w0, w0
WHILELE P1.B, W0, W0
whilele p15.b, w0, w0
WHILELE P15.B, W0, W0
whilele p0.b, w2, w0
WHILELE P0.B, W2, W0
whilele p0.b, wzr, w0
WHILELE P0.B, WZR, W0
whilele p0.b, w0, w3
WHILELE P0.B, W0, W3
whilele p0.b, w0, wzr
WHILELE P0.B, W0, WZR
whilele p0.h, w0, w0
WHILELE P0.H, W0, W0
whilele p1.h, w0, w0
WHILELE P1.H, W0, W0
whilele p15.h, w0, w0
WHILELE P15.H, W0, W0
whilele p0.h, w2, w0
WHILELE P0.H, W2, W0
whilele p0.h, wzr, w0
WHILELE P0.H, WZR, W0
whilele p0.h, w0, w3
WHILELE P0.H, W0, W3
whilele p0.h, w0, wzr
WHILELE P0.H, W0, WZR
whilele p0.s, w0, w0
WHILELE P0.S, W0, W0
whilele p1.s, w0, w0
WHILELE P1.S, W0, W0
whilele p15.s, w0, w0
WHILELE P15.S, W0, W0
whilele p0.s, w2, w0
WHILELE P0.S, W2, W0
whilele p0.s, wzr, w0
WHILELE P0.S, WZR, W0
whilele p0.s, w0, w3
WHILELE P0.S, W0, W3
whilele p0.s, w0, wzr
WHILELE P0.S, W0, WZR
whilele p0.d, w0, w0
WHILELE P0.D, W0, W0
whilele p1.d, w0, w0
WHILELE P1.D, W0, W0
whilele p15.d, w0, w0
WHILELE P15.D, W0, W0
whilele p0.d, w2, w0
WHILELE P0.D, W2, W0
whilele p0.d, wzr, w0
WHILELE P0.D, WZR, W0
whilele p0.d, w0, w3
WHILELE P0.D, W0, W3
whilele p0.d, w0, wzr
WHILELE P0.D, W0, WZR
whilele p0.b, x0, x0
WHILELE P0.B, X0, X0
whilele p1.b, x0, x0
WHILELE P1.B, X0, X0
whilele p15.b, x0, x0
WHILELE P15.B, X0, X0
whilele p0.b, x2, x0
WHILELE P0.B, X2, X0
whilele p0.b, xzr, x0
WHILELE P0.B, XZR, X0
whilele p0.b, x0, x3
WHILELE P0.B, X0, X3
whilele p0.b, x0, xzr
WHILELE P0.B, X0, XZR
whilele p0.h, x0, x0
WHILELE P0.H, X0, X0
whilele p1.h, x0, x0
WHILELE P1.H, X0, X0
whilele p15.h, x0, x0
WHILELE P15.H, X0, X0
whilele p0.h, x2, x0
WHILELE P0.H, X2, X0
whilele p0.h, xzr, x0
WHILELE P0.H, XZR, X0
whilele p0.h, x0, x3
WHILELE P0.H, X0, X3
whilele p0.h, x0, xzr
WHILELE P0.H, X0, XZR
whilele p0.s, x0, x0
WHILELE P0.S, X0, X0
whilele p1.s, x0, x0
WHILELE P1.S, X0, X0
whilele p15.s, x0, x0
WHILELE P15.S, X0, X0
whilele p0.s, x2, x0
WHILELE P0.S, X2, X0
whilele p0.s, xzr, x0
WHILELE P0.S, XZR, X0
whilele p0.s, x0, x3
WHILELE P0.S, X0, X3
whilele p0.s, x0, xzr
WHILELE P0.S, X0, XZR
whilele p0.d, x0, x0
WHILELE P0.D, X0, X0
whilele p1.d, x0, x0
WHILELE P1.D, X0, X0
whilele p15.d, x0, x0
WHILELE P15.D, X0, X0
whilele p0.d, x2, x0
WHILELE P0.D, X2, X0
whilele p0.d, xzr, x0
WHILELE P0.D, XZR, X0
whilele p0.d, x0, x3
WHILELE P0.D, X0, X3
whilele p0.d, x0, xzr
WHILELE P0.D, X0, XZR
whilelo p0.b, w0, w0
WHILELO P0.B, W0, W0
whilelo p1.b, w0, w0
WHILELO P1.B, W0, W0
whilelo p15.b, w0, w0
WHILELO P15.B, W0, W0
whilelo p0.b, w2, w0
WHILELO P0.B, W2, W0
whilelo p0.b, wzr, w0
WHILELO P0.B, WZR, W0
whilelo p0.b, w0, w3
WHILELO P0.B, W0, W3
whilelo p0.b, w0, wzr
WHILELO P0.B, W0, WZR
whilelo p0.h, w0, w0
WHILELO P0.H, W0, W0
whilelo p1.h, w0, w0
WHILELO P1.H, W0, W0
whilelo p15.h, w0, w0
WHILELO P15.H, W0, W0
whilelo p0.h, w2, w0
WHILELO P0.H, W2, W0
whilelo p0.h, wzr, w0
WHILELO P0.H, WZR, W0
whilelo p0.h, w0, w3
WHILELO P0.H, W0, W3
whilelo p0.h, w0, wzr
WHILELO P0.H, W0, WZR
whilelo p0.s, w0, w0
WHILELO P0.S, W0, W0
whilelo p1.s, w0, w0
WHILELO P1.S, W0, W0
whilelo p15.s, w0, w0
WHILELO P15.S, W0, W0
whilelo p0.s, w2, w0
WHILELO P0.S, W2, W0
whilelo p0.s, wzr, w0
WHILELO P0.S, WZR, W0
whilelo p0.s, w0, w3
WHILELO P0.S, W0, W3
whilelo p0.s, w0, wzr
WHILELO P0.S, W0, WZR
whilelo p0.d, w0, w0
WHILELO P0.D, W0, W0
whilelo p1.d, w0, w0
WHILELO P1.D, W0, W0
whilelo p15.d, w0, w0
WHILELO P15.D, W0, W0
whilelo p0.d, w2, w0
WHILELO P0.D, W2, W0
whilelo p0.d, wzr, w0
WHILELO P0.D, WZR, W0
whilelo p0.d, w0, w3
WHILELO P0.D, W0, W3
whilelo p0.d, w0, wzr
WHILELO P0.D, W0, WZR
whilelo p0.b, x0, x0
WHILELO P0.B, X0, X0
whilelo p1.b, x0, x0
WHILELO P1.B, X0, X0
whilelo p15.b, x0, x0
WHILELO P15.B, X0, X0
whilelo p0.b, x2, x0
WHILELO P0.B, X2, X0
whilelo p0.b, xzr, x0
WHILELO P0.B, XZR, X0
whilelo p0.b, x0, x3
WHILELO P0.B, X0, X3
whilelo p0.b, x0, xzr
WHILELO P0.B, X0, XZR
whilelo p0.h, x0, x0
WHILELO P0.H, X0, X0
whilelo p1.h, x0, x0
WHILELO P1.H, X0, X0
whilelo p15.h, x0, x0
WHILELO P15.H, X0, X0
whilelo p0.h, x2, x0
WHILELO P0.H, X2, X0
whilelo p0.h, xzr, x0
WHILELO P0.H, XZR, X0
whilelo p0.h, x0, x3
WHILELO P0.H, X0, X3
whilelo p0.h, x0, xzr
WHILELO P0.H, X0, XZR
whilelo p0.s, x0, x0
WHILELO P0.S, X0, X0
whilelo p1.s, x0, x0
WHILELO P1.S, X0, X0
whilelo p15.s, x0, x0
WHILELO P15.S, X0, X0
whilelo p0.s, x2, x0
WHILELO P0.S, X2, X0
whilelo p0.s, xzr, x0
WHILELO P0.S, XZR, X0
whilelo p0.s, x0, x3
WHILELO P0.S, X0, X3
whilelo p0.s, x0, xzr
WHILELO P0.S, X0, XZR
whilelo p0.d, x0, x0
WHILELO P0.D, X0, X0
whilelo p1.d, x0, x0
WHILELO P1.D, X0, X0
whilelo p15.d, x0, x0
WHILELO P15.D, X0, X0
whilelo p0.d, x2, x0
WHILELO P0.D, X2, X0
whilelo p0.d, xzr, x0
WHILELO P0.D, XZR, X0
whilelo p0.d, x0, x3
WHILELO P0.D, X0, X3
whilelo p0.d, x0, xzr
WHILELO P0.D, X0, XZR
whilels p0.b, w0, w0
WHILELS P0.B, W0, W0
whilels p1.b, w0, w0
WHILELS P1.B, W0, W0
whilels p15.b, w0, w0
WHILELS P15.B, W0, W0
whilels p0.b, w2, w0
WHILELS P0.B, W2, W0
whilels p0.b, wzr, w0
WHILELS P0.B, WZR, W0
whilels p0.b, w0, w3
WHILELS P0.B, W0, W3
whilels p0.b, w0, wzr
WHILELS P0.B, W0, WZR
whilels p0.h, w0, w0
WHILELS P0.H, W0, W0
whilels p1.h, w0, w0
WHILELS P1.H, W0, W0
whilels p15.h, w0, w0
WHILELS P15.H, W0, W0
whilels p0.h, w2, w0
WHILELS P0.H, W2, W0
whilels p0.h, wzr, w0
WHILELS P0.H, WZR, W0
whilels p0.h, w0, w3
WHILELS P0.H, W0, W3
whilels p0.h, w0, wzr
WHILELS P0.H, W0, WZR
whilels p0.s, w0, w0
WHILELS P0.S, W0, W0
whilels p1.s, w0, w0
WHILELS P1.S, W0, W0
whilels p15.s, w0, w0
WHILELS P15.S, W0, W0
whilels p0.s, w2, w0
WHILELS P0.S, W2, W0
whilels p0.s, wzr, w0
WHILELS P0.S, WZR, W0
whilels p0.s, w0, w3
WHILELS P0.S, W0, W3
whilels p0.s, w0, wzr
WHILELS P0.S, W0, WZR
whilels p0.d, w0, w0
WHILELS P0.D, W0, W0
whilels p1.d, w0, w0
WHILELS P1.D, W0, W0
whilels p15.d, w0, w0
WHILELS P15.D, W0, W0
whilels p0.d, w2, w0
WHILELS P0.D, W2, W0
whilels p0.d, wzr, w0
WHILELS P0.D, WZR, W0
whilels p0.d, w0, w3
WHILELS P0.D, W0, W3
whilels p0.d, w0, wzr
WHILELS P0.D, W0, WZR
whilels p0.b, x0, x0
WHILELS P0.B, X0, X0
whilels p1.b, x0, x0
WHILELS P1.B, X0, X0
whilels p15.b, x0, x0
WHILELS P15.B, X0, X0
whilels p0.b, x2, x0
WHILELS P0.B, X2, X0
whilels p0.b, xzr, x0
WHILELS P0.B, XZR, X0
whilels p0.b, x0, x3
WHILELS P0.B, X0, X3
whilels p0.b, x0, xzr
WHILELS P0.B, X0, XZR
whilels p0.h, x0, x0
WHILELS P0.H, X0, X0
whilels p1.h, x0, x0
WHILELS P1.H, X0, X0
whilels p15.h, x0, x0
WHILELS P15.H, X0, X0
whilels p0.h, x2, x0
WHILELS P0.H, X2, X0
whilels p0.h, xzr, x0
WHILELS P0.H, XZR, X0
whilels p0.h, x0, x3
WHILELS P0.H, X0, X3
whilels p0.h, x0, xzr
WHILELS P0.H, X0, XZR
whilels p0.s, x0, x0
WHILELS P0.S, X0, X0
whilels p1.s, x0, x0
WHILELS P1.S, X0, X0
whilels p15.s, x0, x0
WHILELS P15.S, X0, X0
whilels p0.s, x2, x0
WHILELS P0.S, X2, X0
whilels p0.s, xzr, x0
WHILELS P0.S, XZR, X0
whilels p0.s, x0, x3
WHILELS P0.S, X0, X3
whilels p0.s, x0, xzr
WHILELS P0.S, X0, XZR
whilels p0.d, x0, x0
WHILELS P0.D, X0, X0
whilels p1.d, x0, x0
WHILELS P1.D, X0, X0
whilels p15.d, x0, x0
WHILELS P15.D, X0, X0
whilels p0.d, x2, x0
WHILELS P0.D, X2, X0
whilels p0.d, xzr, x0
WHILELS P0.D, XZR, X0
whilels p0.d, x0, x3
WHILELS P0.D, X0, X3
whilels p0.d, x0, xzr
WHILELS P0.D, X0, XZR
whilelt p0.b, w0, w0
WHILELT P0.B, W0, W0
whilelt p1.b, w0, w0
WHILELT P1.B, W0, W0
whilelt p15.b, w0, w0
WHILELT P15.B, W0, W0
whilelt p0.b, w2, w0
WHILELT P0.B, W2, W0
whilelt p0.b, wzr, w0
WHILELT P0.B, WZR, W0
whilelt p0.b, w0, w3
WHILELT P0.B, W0, W3
whilelt p0.b, w0, wzr
WHILELT P0.B, W0, WZR
whilelt p0.h, w0, w0
WHILELT P0.H, W0, W0
whilelt p1.h, w0, w0
WHILELT P1.H, W0, W0
whilelt p15.h, w0, w0
WHILELT P15.H, W0, W0
whilelt p0.h, w2, w0
WHILELT P0.H, W2, W0
whilelt p0.h, wzr, w0
WHILELT P0.H, WZR, W0
whilelt p0.h, w0, w3
WHILELT P0.H, W0, W3
whilelt p0.h, w0, wzr
WHILELT P0.H, W0, WZR
whilelt p0.s, w0, w0
WHILELT P0.S, W0, W0
whilelt p1.s, w0, w0
WHILELT P1.S, W0, W0
whilelt p15.s, w0, w0
WHILELT P15.S, W0, W0
whilelt p0.s, w2, w0
WHILELT P0.S, W2, W0
whilelt p0.s, wzr, w0
WHILELT P0.S, WZR, W0
whilelt p0.s, w0, w3
WHILELT P0.S, W0, W3
whilelt p0.s, w0, wzr
WHILELT P0.S, W0, WZR
whilelt p0.d, w0, w0
WHILELT P0.D, W0, W0
whilelt p1.d, w0, w0
WHILELT P1.D, W0, W0
whilelt p15.d, w0, w0
WHILELT P15.D, W0, W0
whilelt p0.d, w2, w0
WHILELT P0.D, W2, W0
whilelt p0.d, wzr, w0
WHILELT P0.D, WZR, W0
whilelt p0.d, w0, w3
WHILELT P0.D, W0, W3
whilelt p0.d, w0, wzr
WHILELT P0.D, W0, WZR
whilelt p0.b, x0, x0
WHILELT P0.B, X0, X0
whilelt p1.b, x0, x0
WHILELT P1.B, X0, X0
whilelt p15.b, x0, x0
WHILELT P15.B, X0, X0
whilelt p0.b, x2, x0
WHILELT P0.B, X2, X0
whilelt p0.b, xzr, x0
WHILELT P0.B, XZR, X0
whilelt p0.b, x0, x3
WHILELT P0.B, X0, X3
whilelt p0.b, x0, xzr
WHILELT P0.B, X0, XZR
whilelt p0.h, x0, x0
WHILELT P0.H, X0, X0
whilelt p1.h, x0, x0
WHILELT P1.H, X0, X0
whilelt p15.h, x0, x0
WHILELT P15.H, X0, X0
whilelt p0.h, x2, x0
WHILELT P0.H, X2, X0
whilelt p0.h, xzr, x0
WHILELT P0.H, XZR, X0
whilelt p0.h, x0, x3
WHILELT P0.H, X0, X3
whilelt p0.h, x0, xzr
WHILELT P0.H, X0, XZR
whilelt p0.s, x0, x0
WHILELT P0.S, X0, X0
whilelt p1.s, x0, x0
WHILELT P1.S, X0, X0
whilelt p15.s, x0, x0
WHILELT P15.S, X0, X0
whilelt p0.s, x2, x0
WHILELT P0.S, X2, X0
whilelt p0.s, xzr, x0
WHILELT P0.S, XZR, X0
whilelt p0.s, x0, x3
WHILELT P0.S, X0, X3
whilelt p0.s, x0, xzr
WHILELT P0.S, X0, XZR
whilelt p0.d, x0, x0
WHILELT P0.D, X0, X0
whilelt p1.d, x0, x0
WHILELT P1.D, X0, X0
whilelt p15.d, x0, x0
WHILELT P15.D, X0, X0
whilelt p0.d, x2, x0
WHILELT P0.D, X2, X0
whilelt p0.d, xzr, x0
WHILELT P0.D, XZR, X0
whilelt p0.d, x0, x3
WHILELT P0.D, X0, X3
whilelt p0.d, x0, xzr
WHILELT P0.D, X0, XZR
wrffr p0.b
WRFFR P0.B
wrffr p1.b
WRFFR P1.B
wrffr p15.b
WRFFR P15.B
zip1 p0.b, p0.b, p0.b
ZIP1 P0.B, P0.B, P0.B
zip1 p1.b, p0.b, p0.b
ZIP1 P1.B, P0.B, P0.B
zip1 p15.b, p0.b, p0.b
ZIP1 P15.B, P0.B, P0.B
zip1 p0.b, p2.b, p0.b
ZIP1 P0.B, P2.B, P0.B
zip1 p0.b, p15.b, p0.b
ZIP1 P0.B, P15.B, P0.B
zip1 p0.b, p0.b, p3.b
ZIP1 P0.B, P0.B, P3.B
zip1 p0.b, p0.b, p15.b
ZIP1 P0.B, P0.B, P15.B
zip1 p0.h, p0.h, p0.h
ZIP1 P0.H, P0.H, P0.H
zip1 p1.h, p0.h, p0.h
ZIP1 P1.H, P0.H, P0.H
zip1 p15.h, p0.h, p0.h
ZIP1 P15.H, P0.H, P0.H
zip1 p0.h, p2.h, p0.h
ZIP1 P0.H, P2.H, P0.H
zip1 p0.h, p15.h, p0.h
ZIP1 P0.H, P15.H, P0.H
zip1 p0.h, p0.h, p3.h
ZIP1 P0.H, P0.H, P3.H
zip1 p0.h, p0.h, p15.h
ZIP1 P0.H, P0.H, P15.H
zip1 p0.s, p0.s, p0.s
ZIP1 P0.S, P0.S, P0.S
zip1 p1.s, p0.s, p0.s
ZIP1 P1.S, P0.S, P0.S
zip1 p15.s, p0.s, p0.s
ZIP1 P15.S, P0.S, P0.S
zip1 p0.s, p2.s, p0.s
ZIP1 P0.S, P2.S, P0.S
zip1 p0.s, p15.s, p0.s
ZIP1 P0.S, P15.S, P0.S
zip1 p0.s, p0.s, p3.s
ZIP1 P0.S, P0.S, P3.S
zip1 p0.s, p0.s, p15.s
ZIP1 P0.S, P0.S, P15.S
zip1 p0.d, p0.d, p0.d
ZIP1 P0.D, P0.D, P0.D
zip1 p1.d, p0.d, p0.d
ZIP1 P1.D, P0.D, P0.D
zip1 p15.d, p0.d, p0.d
ZIP1 P15.D, P0.D, P0.D
zip1 p0.d, p2.d, p0.d
ZIP1 P0.D, P2.D, P0.D
zip1 p0.d, p15.d, p0.d
ZIP1 P0.D, P15.D, P0.D
zip1 p0.d, p0.d, p3.d
ZIP1 P0.D, P0.D, P3.D
zip1 p0.d, p0.d, p15.d
ZIP1 P0.D, P0.D, P15.D
zip1 z0.b, z0.b, z0.b
ZIP1 Z0.B, Z0.B, Z0.B
zip1 z1.b, z0.b, z0.b
ZIP1 Z1.B, Z0.B, Z0.B
zip1 z31.b, z0.b, z0.b
ZIP1 Z31.B, Z0.B, Z0.B
zip1 z0.b, z2.b, z0.b
ZIP1 Z0.B, Z2.B, Z0.B
zip1 z0.b, z31.b, z0.b
ZIP1 Z0.B, Z31.B, Z0.B
zip1 z0.b, z0.b, z3.b
ZIP1 Z0.B, Z0.B, Z3.B
zip1 z0.b, z0.b, z31.b
ZIP1 Z0.B, Z0.B, Z31.B
zip1 z0.h, z0.h, z0.h
ZIP1 Z0.H, Z0.H, Z0.H
zip1 z1.h, z0.h, z0.h
ZIP1 Z1.H, Z0.H, Z0.H
zip1 z31.h, z0.h, z0.h
ZIP1 Z31.H, Z0.H, Z0.H
zip1 z0.h, z2.h, z0.h
ZIP1 Z0.H, Z2.H, Z0.H
zip1 z0.h, z31.h, z0.h
ZIP1 Z0.H, Z31.H, Z0.H
zip1 z0.h, z0.h, z3.h
ZIP1 Z0.H, Z0.H, Z3.H
zip1 z0.h, z0.h, z31.h
ZIP1 Z0.H, Z0.H, Z31.H
zip1 z0.s, z0.s, z0.s
ZIP1 Z0.S, Z0.S, Z0.S
zip1 z1.s, z0.s, z0.s
ZIP1 Z1.S, Z0.S, Z0.S
zip1 z31.s, z0.s, z0.s
ZIP1 Z31.S, Z0.S, Z0.S
zip1 z0.s, z2.s, z0.s
ZIP1 Z0.S, Z2.S, Z0.S
zip1 z0.s, z31.s, z0.s
ZIP1 Z0.S, Z31.S, Z0.S
zip1 z0.s, z0.s, z3.s
ZIP1 Z0.S, Z0.S, Z3.S
zip1 z0.s, z0.s, z31.s
ZIP1 Z0.S, Z0.S, Z31.S
zip1 z0.d, z0.d, z0.d
ZIP1 Z0.D, Z0.D, Z0.D
zip1 z1.d, z0.d, z0.d
ZIP1 Z1.D, Z0.D, Z0.D
zip1 z31.d, z0.d, z0.d
ZIP1 Z31.D, Z0.D, Z0.D
zip1 z0.d, z2.d, z0.d
ZIP1 Z0.D, Z2.D, Z0.D
zip1 z0.d, z31.d, z0.d
ZIP1 Z0.D, Z31.D, Z0.D
zip1 z0.d, z0.d, z3.d
ZIP1 Z0.D, Z0.D, Z3.D
zip1 z0.d, z0.d, z31.d
ZIP1 Z0.D, Z0.D, Z31.D
zip2 p0.b, p0.b, p0.b
ZIP2 P0.B, P0.B, P0.B
zip2 p1.b, p0.b, p0.b
ZIP2 P1.B, P0.B, P0.B
zip2 p15.b, p0.b, p0.b
ZIP2 P15.B, P0.B, P0.B
zip2 p0.b, p2.b, p0.b
ZIP2 P0.B, P2.B, P0.B
zip2 p0.b, p15.b, p0.b
ZIP2 P0.B, P15.B, P0.B
zip2 p0.b, p0.b, p3.b
ZIP2 P0.B, P0.B, P3.B
zip2 p0.b, p0.b, p15.b
ZIP2 P0.B, P0.B, P15.B
zip2 p0.h, p0.h, p0.h
ZIP2 P0.H, P0.H, P0.H
zip2 p1.h, p0.h, p0.h
ZIP2 P1.H, P0.H, P0.H
zip2 p15.h, p0.h, p0.h
ZIP2 P15.H, P0.H, P0.H
zip2 p0.h, p2.h, p0.h
ZIP2 P0.H, P2.H, P0.H
zip2 p0.h, p15.h, p0.h
ZIP2 P0.H, P15.H, P0.H
zip2 p0.h, p0.h, p3.h
ZIP2 P0.H, P0.H, P3.H
zip2 p0.h, p0.h, p15.h
ZIP2 P0.H, P0.H, P15.H
zip2 p0.s, p0.s, p0.s
ZIP2 P0.S, P0.S, P0.S
zip2 p1.s, p0.s, p0.s
ZIP2 P1.S, P0.S, P0.S
zip2 p15.s, p0.s, p0.s
ZIP2 P15.S, P0.S, P0.S
zip2 p0.s, p2.s, p0.s
ZIP2 P0.S, P2.S, P0.S
zip2 p0.s, p15.s, p0.s
ZIP2 P0.S, P15.S, P0.S
zip2 p0.s, p0.s, p3.s
ZIP2 P0.S, P0.S, P3.S
zip2 p0.s, p0.s, p15.s
ZIP2 P0.S, P0.S, P15.S
zip2 p0.d, p0.d, p0.d
ZIP2 P0.D, P0.D, P0.D
zip2 p1.d, p0.d, p0.d
ZIP2 P1.D, P0.D, P0.D
zip2 p15.d, p0.d, p0.d
ZIP2 P15.D, P0.D, P0.D
zip2 p0.d, p2.d, p0.d
ZIP2 P0.D, P2.D, P0.D
zip2 p0.d, p15.d, p0.d
ZIP2 P0.D, P15.D, P0.D
zip2 p0.d, p0.d, p3.d
ZIP2 P0.D, P0.D, P3.D
zip2 p0.d, p0.d, p15.d
ZIP2 P0.D, P0.D, P15.D
zip2 z0.b, z0.b, z0.b
ZIP2 Z0.B, Z0.B, Z0.B
zip2 z1.b, z0.b, z0.b
ZIP2 Z1.B, Z0.B, Z0.B
zip2 z31.b, z0.b, z0.b
ZIP2 Z31.B, Z0.B, Z0.B
zip2 z0.b, z2.b, z0.b
ZIP2 Z0.B, Z2.B, Z0.B
zip2 z0.b, z31.b, z0.b
ZIP2 Z0.B, Z31.B, Z0.B
zip2 z0.b, z0.b, z3.b
ZIP2 Z0.B, Z0.B, Z3.B
zip2 z0.b, z0.b, z31.b
ZIP2 Z0.B, Z0.B, Z31.B
zip2 z0.h, z0.h, z0.h
ZIP2 Z0.H, Z0.H, Z0.H
zip2 z1.h, z0.h, z0.h
ZIP2 Z1.H, Z0.H, Z0.H
zip2 z31.h, z0.h, z0.h
ZIP2 Z31.H, Z0.H, Z0.H
zip2 z0.h, z2.h, z0.h
ZIP2 Z0.H, Z2.H, Z0.H
zip2 z0.h, z31.h, z0.h
ZIP2 Z0.H, Z31.H, Z0.H
zip2 z0.h, z0.h, z3.h
ZIP2 Z0.H, Z0.H, Z3.H
zip2 z0.h, z0.h, z31.h
ZIP2 Z0.H, Z0.H, Z31.H
zip2 z0.s, z0.s, z0.s
ZIP2 Z0.S, Z0.S, Z0.S
zip2 z1.s, z0.s, z0.s
ZIP2 Z1.S, Z0.S, Z0.S
zip2 z31.s, z0.s, z0.s
ZIP2 Z31.S, Z0.S, Z0.S
zip2 z0.s, z2.s, z0.s
ZIP2 Z0.S, Z2.S, Z0.S
zip2 z0.s, z31.s, z0.s
ZIP2 Z0.S, Z31.S, Z0.S
zip2 z0.s, z0.s, z3.s
ZIP2 Z0.S, Z0.S, Z3.S
zip2 z0.s, z0.s, z31.s
ZIP2 Z0.S, Z0.S, Z31.S
zip2 z0.d, z0.d, z0.d
ZIP2 Z0.D, Z0.D, Z0.D
zip2 z1.d, z0.d, z0.d
ZIP2 Z1.D, Z0.D, Z0.D
zip2 z31.d, z0.d, z0.d
ZIP2 Z31.D, Z0.D, Z0.D
zip2 z0.d, z2.d, z0.d
ZIP2 Z0.D, Z2.D, Z0.D
zip2 z0.d, z31.d, z0.d
ZIP2 Z0.D, Z31.D, Z0.D
zip2 z0.d, z0.d, z3.d
ZIP2 Z0.D, Z0.D, Z3.D
zip2 z0.d, z0.d, z31.d
ZIP2 Z0.D, Z0.D, Z31.D
bic z0.s, z0.s, #0xfffffffe
BIC Z0.S, Z0.S, #0XFFFFFFFE
bic z0.d, z0.d, #0xfffffffefffffffe
bic z1.s, z1.s, #0xfffffffe
BIC Z1.S, Z1.S, #0XFFFFFFFE
bic z1.d, z1.d, #0xfffffffefffffffe
bic z31.s, z31.s, #0xfffffffe
BIC Z31.S, Z31.S, #0XFFFFFFFE
bic z31.d, z31.d, #0xfffffffefffffffe
bic z2.s, z2.s, #0xfffffffe
BIC Z2.S, Z2.S, #0XFFFFFFFE
bic z2.d, z2.d, #0xfffffffefffffffe
bic z0.s, z0.s, #0xffffff80
BIC Z0.S, Z0.S, #0XFFFFFF80
bic z0.d, z0.d, #0xffffff80ffffff80
bic z0.s, z0.s, #0x80000000
BIC Z0.S, Z0.S, #0X80000000
bic z0.d, z0.d, #0x8000000080000000
bic z0.h, z0.h, #0xfffe
BIC Z0.H, Z0.H, #0XFFFE
bic z0.s, z0.s, #0xfffefffe
bic z0.d, z0.d, #0xfffefffefffefffe
bic z0.h, z0.h, #0x8000
BIC Z0.H, Z0.H, #0X8000
bic z0.s, z0.s, #0x80008000
bic z0.d, z0.d, #0x8000800080008000
bic z0.b, z0.b, #0xfe
BIC Z0.B, Z0.B, #0XFE
bic z0.h, z0.h, #0xfefe
bic z0.s, z0.s, #0xfefefefe
bic z0.d, z0.d, #0xfefefefefefefefe
bic z0.b, z0.b, #0xaa
BIC Z0.B, Z0.B, #0XAA
bic z0.h, z0.h, #0xaaaa
bic z0.s, z0.s, #0xaaaaaaaa
bic z0.d, z0.d, #0xaaaaaaaaaaaaaaaa
bic z0.s, z0.s, #0x7fffffff
BIC Z0.S, Z0.S, #0X7FFFFFFF
bic z0.d, z0.d, #0x7fffffff7fffffff
bic z0.s, z0.s, #0x40000000
BIC Z0.S, Z0.S, #0X40000000
bic z0.d, z0.d, #0x4000000040000000
bic z0.h, z0.h, #0x7fff
BIC Z0.H, Z0.H, #0X7FFF
bic z0.s, z0.s, #0x7fff7fff
bic z0.d, z0.d, #0x7fff7fff7fff7fff
bic z0.b, z0.b, #0x40
BIC Z0.B, Z0.B, #0X40
bic z0.h, z0.h, #0x4040
bic z0.s, z0.s, #0x40404040
bic z0.d, z0.d, #0x4040404040404040
bic z0.b, z0.b, #0x1c
BIC Z0.B, Z0.B, #0X1C
bic z0.h, z0.h, #0x1c1c
bic z0.s, z0.s, #0x1c1c1c1c
bic z0.d, z0.d, #0x1c1c1c1c1c1c1c1c
bic z0.s, z0.s, #0x100
BIC Z0.S, Z0.S, #0X100
bic z0.d, z0.d, #0x10000000100
bic z0.d, z0.d, #0x1
BIC Z0.D, Z0.D, #0X1
cmple p0.b, p0/z, z0.b, z0.b
CMPLE P0.B, P0/Z, Z0.B, Z0.B
cmple p1.b, p0/z, z0.b, z0.b
CMPLE P1.B, P0/Z, Z0.B, Z0.B
cmple p15.b, p0/z, z0.b, z0.b
CMPLE P15.B, P0/Z, Z0.B, Z0.B
cmple p0.b, p2/z, z0.b, z0.b
CMPLE P0.B, P2/Z, Z0.B, Z0.B
cmple p0.b, p7/z, z0.b, z0.b
CMPLE P0.B, P7/Z, Z0.B, Z0.B
cmple p0.b, p0/z, z3.b, z0.b
CMPLE P0.B, P0/Z, Z3.B, Z0.B
cmple p0.b, p0/z, z31.b, z0.b
CMPLE P0.B, P0/Z, Z31.B, Z0.B
cmple p0.b, p0/z, z0.b, z4.b
CMPLE P0.B, P0/Z, Z0.B, Z4.B
cmple p0.b, p0/z, z0.b, z31.b
CMPLE P0.B, P0/Z, Z0.B, Z31.B
cmple p0.h, p0/z, z0.h, z0.h
CMPLE P0.H, P0/Z, Z0.H, Z0.H
cmple p1.h, p0/z, z0.h, z0.h
CMPLE P1.H, P0/Z, Z0.H, Z0.H
cmple p15.h, p0/z, z0.h, z0.h
CMPLE P15.H, P0/Z, Z0.H, Z0.H
cmple p0.h, p2/z, z0.h, z0.h
CMPLE P0.H, P2/Z, Z0.H, Z0.H
cmple p0.h, p7/z, z0.h, z0.h
CMPLE P0.H, P7/Z, Z0.H, Z0.H
cmple p0.h, p0/z, z3.h, z0.h
CMPLE P0.H, P0/Z, Z3.H, Z0.H
cmple p0.h, p0/z, z31.h, z0.h
CMPLE P0.H, P0/Z, Z31.H, Z0.H
cmple p0.h, p0/z, z0.h, z4.h
CMPLE P0.H, P0/Z, Z0.H, Z4.H
cmple p0.h, p0/z, z0.h, z31.h
CMPLE P0.H, P0/Z, Z0.H, Z31.H
cmple p0.s, p0/z, z0.s, z0.s
CMPLE P0.S, P0/Z, Z0.S, Z0.S
cmple p1.s, p0/z, z0.s, z0.s
CMPLE P1.S, P0/Z, Z0.S, Z0.S
cmple p15.s, p0/z, z0.s, z0.s
CMPLE P15.S, P0/Z, Z0.S, Z0.S
cmple p0.s, p2/z, z0.s, z0.s
CMPLE P0.S, P2/Z, Z0.S, Z0.S
cmple p0.s, p7/z, z0.s, z0.s
CMPLE P0.S, P7/Z, Z0.S, Z0.S
cmple p0.s, p0/z, z3.s, z0.s
CMPLE P0.S, P0/Z, Z3.S, Z0.S
cmple p0.s, p0/z, z31.s, z0.s
CMPLE P0.S, P0/Z, Z31.S, Z0.S
cmple p0.s, p0/z, z0.s, z4.s
CMPLE P0.S, P0/Z, Z0.S, Z4.S
cmple p0.s, p0/z, z0.s, z31.s
CMPLE P0.S, P0/Z, Z0.S, Z31.S
cmple p0.d, p0/z, z0.d, z0.d
CMPLE P0.D, P0/Z, Z0.D, Z0.D
cmple p1.d, p0/z, z0.d, z0.d
CMPLE P1.D, P0/Z, Z0.D, Z0.D
cmple p15.d, p0/z, z0.d, z0.d
CMPLE P15.D, P0/Z, Z0.D, Z0.D
cmple p0.d, p2/z, z0.d, z0.d
CMPLE P0.D, P2/Z, Z0.D, Z0.D
cmple p0.d, p7/z, z0.d, z0.d
CMPLE P0.D, P7/Z, Z0.D, Z0.D
cmple p0.d, p0/z, z3.d, z0.d
CMPLE P0.D, P0/Z, Z3.D, Z0.D
cmple p0.d, p0/z, z31.d, z0.d
CMPLE P0.D, P0/Z, Z31.D, Z0.D
cmple p0.d, p0/z, z0.d, z4.d
CMPLE P0.D, P0/Z, Z0.D, Z4.D
cmple p0.d, p0/z, z0.d, z31.d
CMPLE P0.D, P0/Z, Z0.D, Z31.D
cmplo p0.b, p0/z, z0.b, z0.b
CMPLO P0.B, P0/Z, Z0.B, Z0.B
cmplo p1.b, p0/z, z0.b, z0.b
CMPLO P1.B, P0/Z, Z0.B, Z0.B
cmplo p15.b, p0/z, z0.b, z0.b
CMPLO P15.B, P0/Z, Z0.B, Z0.B
cmplo p0.b, p2/z, z0.b, z0.b
CMPLO P0.B, P2/Z, Z0.B, Z0.B
cmplo p0.b, p7/z, z0.b, z0.b
CMPLO P0.B, P7/Z, Z0.B, Z0.B
cmplo p0.b, p0/z, z3.b, z0.b
CMPLO P0.B, P0/Z, Z3.B, Z0.B
cmplo p0.b, p0/z, z31.b, z0.b
CMPLO P0.B, P0/Z, Z31.B, Z0.B
cmplo p0.b, p0/z, z0.b, z4.b
CMPLO P0.B, P0/Z, Z0.B, Z4.B
cmplo p0.b, p0/z, z0.b, z31.b
CMPLO P0.B, P0/Z, Z0.B, Z31.B
cmplo p0.h, p0/z, z0.h, z0.h
CMPLO P0.H, P0/Z, Z0.H, Z0.H
cmplo p1.h, p0/z, z0.h, z0.h
CMPLO P1.H, P0/Z, Z0.H, Z0.H
cmplo p15.h, p0/z, z0.h, z0.h
CMPLO P15.H, P0/Z, Z0.H, Z0.H
cmplo p0.h, p2/z, z0.h, z0.h
CMPLO P0.H, P2/Z, Z0.H, Z0.H
cmplo p0.h, p7/z, z0.h, z0.h
CMPLO P0.H, P7/Z, Z0.H, Z0.H
cmplo p0.h, p0/z, z3.h, z0.h
CMPLO P0.H, P0/Z, Z3.H, Z0.H
cmplo p0.h, p0/z, z31.h, z0.h
CMPLO P0.H, P0/Z, Z31.H, Z0.H
cmplo p0.h, p0/z, z0.h, z4.h
CMPLO P0.H, P0/Z, Z0.H, Z4.H
cmplo p0.h, p0/z, z0.h, z31.h
CMPLO P0.H, P0/Z, Z0.H, Z31.H
cmplo p0.s, p0/z, z0.s, z0.s
CMPLO P0.S, P0/Z, Z0.S, Z0.S
cmplo p1.s, p0/z, z0.s, z0.s
CMPLO P1.S, P0/Z, Z0.S, Z0.S
cmplo p15.s, p0/z, z0.s, z0.s
CMPLO P15.S, P0/Z, Z0.S, Z0.S
cmplo p0.s, p2/z, z0.s, z0.s
CMPLO P0.S, P2/Z, Z0.S, Z0.S
cmplo p0.s, p7/z, z0.s, z0.s
CMPLO P0.S, P7/Z, Z0.S, Z0.S
cmplo p0.s, p0/z, z3.s, z0.s
CMPLO P0.S, P0/Z, Z3.S, Z0.S
cmplo p0.s, p0/z, z31.s, z0.s
CMPLO P0.S, P0/Z, Z31.S, Z0.S
cmplo p0.s, p0/z, z0.s, z4.s
CMPLO P0.S, P0/Z, Z0.S, Z4.S
cmplo p0.s, p0/z, z0.s, z31.s
CMPLO P0.S, P0/Z, Z0.S, Z31.S
cmplo p0.d, p0/z, z0.d, z0.d
CMPLO P0.D, P0/Z, Z0.D, Z0.D
cmplo p1.d, p0/z, z0.d, z0.d
CMPLO P1.D, P0/Z, Z0.D, Z0.D
cmplo p15.d, p0/z, z0.d, z0.d
CMPLO P15.D, P0/Z, Z0.D, Z0.D
cmplo p0.d, p2/z, z0.d, z0.d
CMPLO P0.D, P2/Z, Z0.D, Z0.D
cmplo p0.d, p7/z, z0.d, z0.d
CMPLO P0.D, P7/Z, Z0.D, Z0.D
cmplo p0.d, p0/z, z3.d, z0.d
CMPLO P0.D, P0/Z, Z3.D, Z0.D
cmplo p0.d, p0/z, z31.d, z0.d
CMPLO P0.D, P0/Z, Z31.D, Z0.D
cmplo p0.d, p0/z, z0.d, z4.d
CMPLO P0.D, P0/Z, Z0.D, Z4.D
cmplo p0.d, p0/z, z0.d, z31.d
CMPLO P0.D, P0/Z, Z0.D, Z31.D
cmpls p0.b, p0/z, z0.b, z0.b
CMPLS P0.B, P0/Z, Z0.B, Z0.B
cmpls p1.b, p0/z, z0.b, z0.b
CMPLS P1.B, P0/Z, Z0.B, Z0.B
cmpls p15.b, p0/z, z0.b, z0.b
CMPLS P15.B, P0/Z, Z0.B, Z0.B
cmpls p0.b, p2/z, z0.b, z0.b
CMPLS P0.B, P2/Z, Z0.B, Z0.B
cmpls p0.b, p7/z, z0.b, z0.b
CMPLS P0.B, P7/Z, Z0.B, Z0.B
cmpls p0.b, p0/z, z3.b, z0.b
CMPLS P0.B, P0/Z, Z3.B, Z0.B
cmpls p0.b, p0/z, z31.b, z0.b
CMPLS P0.B, P0/Z, Z31.B, Z0.B
cmpls p0.b, p0/z, z0.b, z4.b
CMPLS P0.B, P0/Z, Z0.B, Z4.B
cmpls p0.b, p0/z, z0.b, z31.b
CMPLS P0.B, P0/Z, Z0.B, Z31.B
cmpls p0.h, p0/z, z0.h, z0.h
CMPLS P0.H, P0/Z, Z0.H, Z0.H
cmpls p1.h, p0/z, z0.h, z0.h
CMPLS P1.H, P0/Z, Z0.H, Z0.H
cmpls p15.h, p0/z, z0.h, z0.h
CMPLS P15.H, P0/Z, Z0.H, Z0.H
cmpls p0.h, p2/z, z0.h, z0.h
CMPLS P0.H, P2/Z, Z0.H, Z0.H
cmpls p0.h, p7/z, z0.h, z0.h
CMPLS P0.H, P7/Z, Z0.H, Z0.H
cmpls p0.h, p0/z, z3.h, z0.h
CMPLS P0.H, P0/Z, Z3.H, Z0.H
cmpls p0.h, p0/z, z31.h, z0.h
CMPLS P0.H, P0/Z, Z31.H, Z0.H
cmpls p0.h, p0/z, z0.h, z4.h
CMPLS P0.H, P0/Z, Z0.H, Z4.H
cmpls p0.h, p0/z, z0.h, z31.h
CMPLS P0.H, P0/Z, Z0.H, Z31.H
cmpls p0.s, p0/z, z0.s, z0.s
CMPLS P0.S, P0/Z, Z0.S, Z0.S
cmpls p1.s, p0/z, z0.s, z0.s
CMPLS P1.S, P0/Z, Z0.S, Z0.S
cmpls p15.s, p0/z, z0.s, z0.s
CMPLS P15.S, P0/Z, Z0.S, Z0.S
cmpls p0.s, p2/z, z0.s, z0.s
CMPLS P0.S, P2/Z, Z0.S, Z0.S
cmpls p0.s, p7/z, z0.s, z0.s
CMPLS P0.S, P7/Z, Z0.S, Z0.S
cmpls p0.s, p0/z, z3.s, z0.s
CMPLS P0.S, P0/Z, Z3.S, Z0.S
cmpls p0.s, p0/z, z31.s, z0.s
CMPLS P0.S, P0/Z, Z31.S, Z0.S
cmpls p0.s, p0/z, z0.s, z4.s
CMPLS P0.S, P0/Z, Z0.S, Z4.S
cmpls p0.s, p0/z, z0.s, z31.s
CMPLS P0.S, P0/Z, Z0.S, Z31.S
cmpls p0.d, p0/z, z0.d, z0.d
CMPLS P0.D, P0/Z, Z0.D, Z0.D
cmpls p1.d, p0/z, z0.d, z0.d
CMPLS P1.D, P0/Z, Z0.D, Z0.D
cmpls p15.d, p0/z, z0.d, z0.d
CMPLS P15.D, P0/Z, Z0.D, Z0.D
cmpls p0.d, p2/z, z0.d, z0.d
CMPLS P0.D, P2/Z, Z0.D, Z0.D
cmpls p0.d, p7/z, z0.d, z0.d
CMPLS P0.D, P7/Z, Z0.D, Z0.D
cmpls p0.d, p0/z, z3.d, z0.d
CMPLS P0.D, P0/Z, Z3.D, Z0.D
cmpls p0.d, p0/z, z31.d, z0.d
CMPLS P0.D, P0/Z, Z31.D, Z0.D
cmpls p0.d, p0/z, z0.d, z4.d
CMPLS P0.D, P0/Z, Z0.D, Z4.D
cmpls p0.d, p0/z, z0.d, z31.d
CMPLS P0.D, P0/Z, Z0.D, Z31.D
cmplt p0.b, p0/z, z0.b, z0.b
CMPLT P0.B, P0/Z, Z0.B, Z0.B
cmplt p1.b, p0/z, z0.b, z0.b
CMPLT P1.B, P0/Z, Z0.B, Z0.B
cmplt p15.b, p0/z, z0.b, z0.b
CMPLT P15.B, P0/Z, Z0.B, Z0.B
cmplt p0.b, p2/z, z0.b, z0.b
CMPLT P0.B, P2/Z, Z0.B, Z0.B
cmplt p0.b, p7/z, z0.b, z0.b
CMPLT P0.B, P7/Z, Z0.B, Z0.B
cmplt p0.b, p0/z, z3.b, z0.b
CMPLT P0.B, P0/Z, Z3.B, Z0.B
cmplt p0.b, p0/z, z31.b, z0.b
CMPLT P0.B, P0/Z, Z31.B, Z0.B
cmplt p0.b, p0/z, z0.b, z4.b
CMPLT P0.B, P0/Z, Z0.B, Z4.B
cmplt p0.b, p0/z, z0.b, z31.b
CMPLT P0.B, P0/Z, Z0.B, Z31.B
cmplt p0.h, p0/z, z0.h, z0.h
CMPLT P0.H, P0/Z, Z0.H, Z0.H
cmplt p1.h, p0/z, z0.h, z0.h
CMPLT P1.H, P0/Z, Z0.H, Z0.H
cmplt p15.h, p0/z, z0.h, z0.h
CMPLT P15.H, P0/Z, Z0.H, Z0.H
cmplt p0.h, p2/z, z0.h, z0.h
CMPLT P0.H, P2/Z, Z0.H, Z0.H
cmplt p0.h, p7/z, z0.h, z0.h
CMPLT P0.H, P7/Z, Z0.H, Z0.H
cmplt p0.h, p0/z, z3.h, z0.h
CMPLT P0.H, P0/Z, Z3.H, Z0.H
cmplt p0.h, p0/z, z31.h, z0.h
CMPLT P0.H, P0/Z, Z31.H, Z0.H
cmplt p0.h, p0/z, z0.h, z4.h
CMPLT P0.H, P0/Z, Z0.H, Z4.H
cmplt p0.h, p0/z, z0.h, z31.h
CMPLT P0.H, P0/Z, Z0.H, Z31.H
cmplt p0.s, p0/z, z0.s, z0.s
CMPLT P0.S, P0/Z, Z0.S, Z0.S
cmplt p1.s, p0/z, z0.s, z0.s
CMPLT P1.S, P0/Z, Z0.S, Z0.S
cmplt p15.s, p0/z, z0.s, z0.s
CMPLT P15.S, P0/Z, Z0.S, Z0.S
cmplt p0.s, p2/z, z0.s, z0.s
CMPLT P0.S, P2/Z, Z0.S, Z0.S
cmplt p0.s, p7/z, z0.s, z0.s
CMPLT P0.S, P7/Z, Z0.S, Z0.S
cmplt p0.s, p0/z, z3.s, z0.s
CMPLT P0.S, P0/Z, Z3.S, Z0.S
cmplt p0.s, p0/z, z31.s, z0.s
CMPLT P0.S, P0/Z, Z31.S, Z0.S
cmplt p0.s, p0/z, z0.s, z4.s
CMPLT P0.S, P0/Z, Z0.S, Z4.S
cmplt p0.s, p0/z, z0.s, z31.s
CMPLT P0.S, P0/Z, Z0.S, Z31.S
cmplt p0.d, p0/z, z0.d, z0.d
CMPLT P0.D, P0/Z, Z0.D, Z0.D
cmplt p1.d, p0/z, z0.d, z0.d
CMPLT P1.D, P0/Z, Z0.D, Z0.D
cmplt p15.d, p0/z, z0.d, z0.d
CMPLT P15.D, P0/Z, Z0.D, Z0.D
cmplt p0.d, p2/z, z0.d, z0.d
CMPLT P0.D, P2/Z, Z0.D, Z0.D
cmplt p0.d, p7/z, z0.d, z0.d
CMPLT P0.D, P7/Z, Z0.D, Z0.D
cmplt p0.d, p0/z, z3.d, z0.d
CMPLT P0.D, P0/Z, Z3.D, Z0.D
cmplt p0.d, p0/z, z31.d, z0.d
CMPLT P0.D, P0/Z, Z31.D, Z0.D
cmplt p0.d, p0/z, z0.d, z4.d
CMPLT P0.D, P0/Z, Z0.D, Z4.D
cmplt p0.d, p0/z, z0.d, z31.d
CMPLT P0.D, P0/Z, Z0.D, Z31.D
eon z0.s, z0.s, #0xfffffffe
EON Z0.S, Z0.S, #0XFFFFFFFE
eon z0.d, z0.d, #0xfffffffefffffffe
eon z1.s, z1.s, #0xfffffffe
EON Z1.S, Z1.S, #0XFFFFFFFE
eon z1.d, z1.d, #0xfffffffefffffffe
eon z31.s, z31.s, #0xfffffffe
EON Z31.S, Z31.S, #0XFFFFFFFE
eon z31.d, z31.d, #0xfffffffefffffffe
eon z2.s, z2.s, #0xfffffffe
EON Z2.S, Z2.S, #0XFFFFFFFE
eon z2.d, z2.d, #0xfffffffefffffffe
eon z0.s, z0.s, #0xffffff80
EON Z0.S, Z0.S, #0XFFFFFF80
eon z0.d, z0.d, #0xffffff80ffffff80
eon z0.s, z0.s, #0x80000000
EON Z0.S, Z0.S, #0X80000000
eon z0.d, z0.d, #0x8000000080000000
eon z0.h, z0.h, #0xfffe
EON Z0.H, Z0.H, #0XFFFE
eon z0.s, z0.s, #0xfffefffe
eon z0.d, z0.d, #0xfffefffefffefffe
eon z0.h, z0.h, #0x8000
EON Z0.H, Z0.H, #0X8000
eon z0.s, z0.s, #0x80008000
eon z0.d, z0.d, #0x8000800080008000
eon z0.b, z0.b, #0xfe
EON Z0.B, Z0.B, #0XFE
eon z0.h, z0.h, #0xfefe
eon z0.s, z0.s, #0xfefefefe
eon z0.d, z0.d, #0xfefefefefefefefe
eon z0.b, z0.b, #0xaa
EON Z0.B, Z0.B, #0XAA
eon z0.h, z0.h, #0xaaaa
eon z0.s, z0.s, #0xaaaaaaaa
eon z0.d, z0.d, #0xaaaaaaaaaaaaaaaa
eon z0.s, z0.s, #0x7fffffff
EON Z0.S, Z0.S, #0X7FFFFFFF
eon z0.d, z0.d, #0x7fffffff7fffffff
eon z0.s, z0.s, #0x40000000
EON Z0.S, Z0.S, #0X40000000
eon z0.d, z0.d, #0x4000000040000000
eon z0.h, z0.h, #0x7fff
EON Z0.H, Z0.H, #0X7FFF
eon z0.s, z0.s, #0x7fff7fff
eon z0.d, z0.d, #0x7fff7fff7fff7fff
eon z0.b, z0.b, #0x40
EON Z0.B, Z0.B, #0X40
eon z0.h, z0.h, #0x4040
eon z0.s, z0.s, #0x40404040
eon z0.d, z0.d, #0x4040404040404040
eon z0.b, z0.b, #0x1c
EON Z0.B, Z0.B, #0X1C
eon z0.h, z0.h, #0x1c1c
eon z0.s, z0.s, #0x1c1c1c1c
eon z0.d, z0.d, #0x1c1c1c1c1c1c1c1c
eon z0.s, z0.s, #0x100
EON Z0.S, Z0.S, #0X100
eon z0.d, z0.d, #0x10000000100
eon z0.d, z0.d, #0x1
EON Z0.D, Z0.D, #0X1
facle p0.h, p0/z, z0.h, z0.h
FACLE P0.H, P0/Z, Z0.H, Z0.H
facle p1.h, p0/z, z0.h, z0.h
FACLE P1.H, P0/Z, Z0.H, Z0.H
facle p15.h, p0/z, z0.h, z0.h
FACLE P15.H, P0/Z, Z0.H, Z0.H
facle p0.h, p2/z, z0.h, z0.h
FACLE P0.H, P2/Z, Z0.H, Z0.H
facle p0.h, p7/z, z0.h, z0.h
FACLE P0.H, P7/Z, Z0.H, Z0.H
facle p0.h, p0/z, z3.h, z0.h
FACLE P0.H, P0/Z, Z3.H, Z0.H
facle p0.h, p0/z, z31.h, z0.h
FACLE P0.H, P0/Z, Z31.H, Z0.H
facle p0.h, p0/z, z0.h, z4.h
FACLE P0.H, P0/Z, Z0.H, Z4.H
facle p0.h, p0/z, z0.h, z31.h
FACLE P0.H, P0/Z, Z0.H, Z31.H
facle p0.s, p0/z, z0.s, z0.s
FACLE P0.S, P0/Z, Z0.S, Z0.S
facle p1.s, p0/z, z0.s, z0.s
FACLE P1.S, P0/Z, Z0.S, Z0.S
facle p15.s, p0/z, z0.s, z0.s
FACLE P15.S, P0/Z, Z0.S, Z0.S
facle p0.s, p2/z, z0.s, z0.s
FACLE P0.S, P2/Z, Z0.S, Z0.S
facle p0.s, p7/z, z0.s, z0.s
FACLE P0.S, P7/Z, Z0.S, Z0.S
facle p0.s, p0/z, z3.s, z0.s
FACLE P0.S, P0/Z, Z3.S, Z0.S
facle p0.s, p0/z, z31.s, z0.s
FACLE P0.S, P0/Z, Z31.S, Z0.S
facle p0.s, p0/z, z0.s, z4.s
FACLE P0.S, P0/Z, Z0.S, Z4.S
facle p0.s, p0/z, z0.s, z31.s
FACLE P0.S, P0/Z, Z0.S, Z31.S
facle p0.d, p0/z, z0.d, z0.d
FACLE P0.D, P0/Z, Z0.D, Z0.D
facle p1.d, p0/z, z0.d, z0.d
FACLE P1.D, P0/Z, Z0.D, Z0.D
facle p15.d, p0/z, z0.d, z0.d
FACLE P15.D, P0/Z, Z0.D, Z0.D
facle p0.d, p2/z, z0.d, z0.d
FACLE P0.D, P2/Z, Z0.D, Z0.D
facle p0.d, p7/z, z0.d, z0.d
FACLE P0.D, P7/Z, Z0.D, Z0.D
facle p0.d, p0/z, z3.d, z0.d
FACLE P0.D, P0/Z, Z3.D, Z0.D
facle p0.d, p0/z, z31.d, z0.d
FACLE P0.D, P0/Z, Z31.D, Z0.D
facle p0.d, p0/z, z0.d, z4.d
FACLE P0.D, P0/Z, Z0.D, Z4.D
facle p0.d, p0/z, z0.d, z31.d
FACLE P0.D, P0/Z, Z0.D, Z31.D
faclt p0.h, p0/z, z0.h, z0.h
FACLT P0.H, P0/Z, Z0.H, Z0.H
faclt p1.h, p0/z, z0.h, z0.h
FACLT P1.H, P0/Z, Z0.H, Z0.H
faclt p15.h, p0/z, z0.h, z0.h
FACLT P15.H, P0/Z, Z0.H, Z0.H
faclt p0.h, p2/z, z0.h, z0.h
FACLT P0.H, P2/Z, Z0.H, Z0.H
faclt p0.h, p7/z, z0.h, z0.h
FACLT P0.H, P7/Z, Z0.H, Z0.H
faclt p0.h, p0/z, z3.h, z0.h
FACLT P0.H, P0/Z, Z3.H, Z0.H
faclt p0.h, p0/z, z31.h, z0.h
FACLT P0.H, P0/Z, Z31.H, Z0.H
faclt p0.h, p0/z, z0.h, z4.h
FACLT P0.H, P0/Z, Z0.H, Z4.H
faclt p0.h, p0/z, z0.h, z31.h
FACLT P0.H, P0/Z, Z0.H, Z31.H
faclt p0.s, p0/z, z0.s, z0.s
FACLT P0.S, P0/Z, Z0.S, Z0.S
faclt p1.s, p0/z, z0.s, z0.s
FACLT P1.S, P0/Z, Z0.S, Z0.S
faclt p15.s, p0/z, z0.s, z0.s
FACLT P15.S, P0/Z, Z0.S, Z0.S
faclt p0.s, p2/z, z0.s, z0.s
FACLT P0.S, P2/Z, Z0.S, Z0.S
faclt p0.s, p7/z, z0.s, z0.s
FACLT P0.S, P7/Z, Z0.S, Z0.S
faclt p0.s, p0/z, z3.s, z0.s
FACLT P0.S, P0/Z, Z3.S, Z0.S
faclt p0.s, p0/z, z31.s, z0.s
FACLT P0.S, P0/Z, Z31.S, Z0.S
faclt p0.s, p0/z, z0.s, z4.s
FACLT P0.S, P0/Z, Z0.S, Z4.S
faclt p0.s, p0/z, z0.s, z31.s
FACLT P0.S, P0/Z, Z0.S, Z31.S
faclt p0.d, p0/z, z0.d, z0.d
FACLT P0.D, P0/Z, Z0.D, Z0.D
faclt p1.d, p0/z, z0.d, z0.d
FACLT P1.D, P0/Z, Z0.D, Z0.D
faclt p15.d, p0/z, z0.d, z0.d
FACLT P15.D, P0/Z, Z0.D, Z0.D
faclt p0.d, p2/z, z0.d, z0.d
FACLT P0.D, P2/Z, Z0.D, Z0.D
faclt p0.d, p7/z, z0.d, z0.d
FACLT P0.D, P7/Z, Z0.D, Z0.D
faclt p0.d, p0/z, z3.d, z0.d
FACLT P0.D, P0/Z, Z3.D, Z0.D
faclt p0.d, p0/z, z31.d, z0.d
FACLT P0.D, P0/Z, Z31.D, Z0.D
faclt p0.d, p0/z, z0.d, z4.d
FACLT P0.D, P0/Z, Z0.D, Z4.D
faclt p0.d, p0/z, z0.d, z31.d
FACLT P0.D, P0/Z, Z0.D, Z31.D
fcmle p0.h, p0/z, z0.h, z0.h
FCMLE P0.H, P0/Z, Z0.H, Z0.H
fcmle p1.h, p0/z, z0.h, z0.h
FCMLE P1.H, P0/Z, Z0.H, Z0.H
fcmle p15.h, p0/z, z0.h, z0.h
FCMLE P15.H, P0/Z, Z0.H, Z0.H
fcmle p0.h, p2/z, z0.h, z0.h
FCMLE P0.H, P2/Z, Z0.H, Z0.H
fcmle p0.h, p7/z, z0.h, z0.h
FCMLE P0.H, P7/Z, Z0.H, Z0.H
fcmle p0.h, p0/z, z3.h, z0.h
FCMLE P0.H, P0/Z, Z3.H, Z0.H
fcmle p0.h, p0/z, z31.h, z0.h
FCMLE P0.H, P0/Z, Z31.H, Z0.H
fcmle p0.h, p0/z, z0.h, z4.h
FCMLE P0.H, P0/Z, Z0.H, Z4.H
fcmle p0.h, p0/z, z0.h, z31.h
FCMLE P0.H, P0/Z, Z0.H, Z31.H
fcmle p0.s, p0/z, z0.s, z0.s
FCMLE P0.S, P0/Z, Z0.S, Z0.S
fcmle p1.s, p0/z, z0.s, z0.s
FCMLE P1.S, P0/Z, Z0.S, Z0.S
fcmle p15.s, p0/z, z0.s, z0.s
FCMLE P15.S, P0/Z, Z0.S, Z0.S
fcmle p0.s, p2/z, z0.s, z0.s
FCMLE P0.S, P2/Z, Z0.S, Z0.S
fcmle p0.s, p7/z, z0.s, z0.s
FCMLE P0.S, P7/Z, Z0.S, Z0.S
fcmle p0.s, p0/z, z3.s, z0.s
FCMLE P0.S, P0/Z, Z3.S, Z0.S
fcmle p0.s, p0/z, z31.s, z0.s
FCMLE P0.S, P0/Z, Z31.S, Z0.S
fcmle p0.s, p0/z, z0.s, z4.s
FCMLE P0.S, P0/Z, Z0.S, Z4.S
fcmle p0.s, p0/z, z0.s, z31.s
FCMLE P0.S, P0/Z, Z0.S, Z31.S
fcmle p0.d, p0/z, z0.d, z0.d
FCMLE P0.D, P0/Z, Z0.D, Z0.D
fcmle p1.d, p0/z, z0.d, z0.d
FCMLE P1.D, P0/Z, Z0.D, Z0.D
fcmle p15.d, p0/z, z0.d, z0.d
FCMLE P15.D, P0/Z, Z0.D, Z0.D
fcmle p0.d, p2/z, z0.d, z0.d
FCMLE P0.D, P2/Z, Z0.D, Z0.D
fcmle p0.d, p7/z, z0.d, z0.d
FCMLE P0.D, P7/Z, Z0.D, Z0.D
fcmle p0.d, p0/z, z3.d, z0.d
FCMLE P0.D, P0/Z, Z3.D, Z0.D
fcmle p0.d, p0/z, z31.d, z0.d
FCMLE P0.D, P0/Z, Z31.D, Z0.D
fcmle p0.d, p0/z, z0.d, z4.d
FCMLE P0.D, P0/Z, Z0.D, Z4.D
fcmle p0.d, p0/z, z0.d, z31.d
FCMLE P0.D, P0/Z, Z0.D, Z31.D
fcmlt p0.h, p0/z, z0.h, z0.h
FCMLT P0.H, P0/Z, Z0.H, Z0.H
fcmlt p1.h, p0/z, z0.h, z0.h
FCMLT P1.H, P0/Z, Z0.H, Z0.H
fcmlt p15.h, p0/z, z0.h, z0.h
FCMLT P15.H, P0/Z, Z0.H, Z0.H
fcmlt p0.h, p2/z, z0.h, z0.h
FCMLT P0.H, P2/Z, Z0.H, Z0.H
fcmlt p0.h, p7/z, z0.h, z0.h
FCMLT P0.H, P7/Z, Z0.H, Z0.H
fcmlt p0.h, p0/z, z3.h, z0.h
FCMLT P0.H, P0/Z, Z3.H, Z0.H
fcmlt p0.h, p0/z, z31.h, z0.h
FCMLT P0.H, P0/Z, Z31.H, Z0.H
fcmlt p0.h, p0/z, z0.h, z4.h
FCMLT P0.H, P0/Z, Z0.H, Z4.H
fcmlt p0.h, p0/z, z0.h, z31.h
FCMLT P0.H, P0/Z, Z0.H, Z31.H
fcmlt p0.s, p0/z, z0.s, z0.s
FCMLT P0.S, P0/Z, Z0.S, Z0.S
fcmlt p1.s, p0/z, z0.s, z0.s
FCMLT P1.S, P0/Z, Z0.S, Z0.S
fcmlt p15.s, p0/z, z0.s, z0.s
FCMLT P15.S, P0/Z, Z0.S, Z0.S
fcmlt p0.s, p2/z, z0.s, z0.s
FCMLT P0.S, P2/Z, Z0.S, Z0.S
fcmlt p0.s, p7/z, z0.s, z0.s
FCMLT P0.S, P7/Z, Z0.S, Z0.S
fcmlt p0.s, p0/z, z3.s, z0.s
FCMLT P0.S, P0/Z, Z3.S, Z0.S
fcmlt p0.s, p0/z, z31.s, z0.s
FCMLT P0.S, P0/Z, Z31.S, Z0.S
fcmlt p0.s, p0/z, z0.s, z4.s
FCMLT P0.S, P0/Z, Z0.S, Z4.S
fcmlt p0.s, p0/z, z0.s, z31.s
FCMLT P0.S, P0/Z, Z0.S, Z31.S
fcmlt p0.d, p0/z, z0.d, z0.d
FCMLT P0.D, P0/Z, Z0.D, Z0.D
fcmlt p1.d, p0/z, z0.d, z0.d
FCMLT P1.D, P0/Z, Z0.D, Z0.D
fcmlt p15.d, p0/z, z0.d, z0.d
FCMLT P15.D, P0/Z, Z0.D, Z0.D
fcmlt p0.d, p2/z, z0.d, z0.d
FCMLT P0.D, P2/Z, Z0.D, Z0.D
fcmlt p0.d, p7/z, z0.d, z0.d
FCMLT P0.D, P7/Z, Z0.D, Z0.D
fcmlt p0.d, p0/z, z3.d, z0.d
FCMLT P0.D, P0/Z, Z3.D, Z0.D
fcmlt p0.d, p0/z, z31.d, z0.d
FCMLT P0.D, P0/Z, Z31.D, Z0.D
fcmlt p0.d, p0/z, z0.d, z4.d
FCMLT P0.D, P0/Z, Z0.D, Z4.D
fcmlt p0.d, p0/z, z0.d, z31.d
FCMLT P0.D, P0/Z, Z0.D, Z31.D
fmov z0.h, #0.0
FMOV Z0.H, #0.0
fmov z1.h, #0.0
FMOV Z1.H, #0.0
fmov z31.h, #0.0
FMOV Z31.H, #0.0
fmov z0.s, #0.0
FMOV Z0.S, #0.0
fmov z1.s, #0.0
FMOV Z1.S, #0.0
fmov z31.s, #0.0
FMOV Z31.S, #0.0
fmov z0.d, #0.0
FMOV Z0.D, #0.0
fmov z1.d, #0.0
FMOV Z1.D, #0.0
fmov z31.d, #0.0
FMOV Z31.D, #0.0
fmov z0.h, p0/m, #0.0
FMOV Z0.H, P0/M, #0.0
fmov z1.h, p0/m, #0.0
FMOV Z1.H, P0/M, #0.0
fmov z31.h, p0/m, #0.0
FMOV Z31.H, P0/M, #0.0
fmov z0.h, p2/m, #0.0
FMOV Z0.H, P2/M, #0.0
fmov z0.h, p15/m, #0.0
FMOV Z0.H, P15/M, #0.0
fmov z0.s, p0/m, #0.0
FMOV Z0.S, P0/M, #0.0
fmov z1.s, p0/m, #0.0
FMOV Z1.S, P0/M, #0.0
fmov z31.s, p0/m, #0.0
FMOV Z31.S, P0/M, #0.0
fmov z0.s, p2/m, #0.0
FMOV Z0.S, P2/M, #0.0
fmov z0.s, p15/m, #0.0
FMOV Z0.S, P15/M, #0.0
fmov z0.d, p0/m, #0.0
FMOV Z0.D, P0/M, #0.0
fmov z1.d, p0/m, #0.0
FMOV Z1.D, P0/M, #0.0
fmov z31.d, p0/m, #0.0
FMOV Z31.D, P0/M, #0.0
fmov z0.d, p2/m, #0.0
FMOV Z0.D, P2/M, #0.0
fmov z0.d, p15/m, #0.0
FMOV Z0.D, P15/M, #0.0
orn z0.s, z0.s, #0xfffffffe
ORN Z0.S, Z0.S, #0XFFFFFFFE
orn z0.d, z0.d, #0xfffffffefffffffe
orn z1.s, z1.s, #0xfffffffe
ORN Z1.S, Z1.S, #0XFFFFFFFE
orn z1.d, z1.d, #0xfffffffefffffffe
orn z31.s, z31.s, #0xfffffffe
ORN Z31.S, Z31.S, #0XFFFFFFFE
orn z31.d, z31.d, #0xfffffffefffffffe
orn z2.s, z2.s, #0xfffffffe
ORN Z2.S, Z2.S, #0XFFFFFFFE
orn z2.d, z2.d, #0xfffffffefffffffe
orn z0.s, z0.s, #0xffffff80
ORN Z0.S, Z0.S, #0XFFFFFF80
orn z0.d, z0.d, #0xffffff80ffffff80
orn z0.s, z0.s, #0x80000000
ORN Z0.S, Z0.S, #0X80000000
orn z0.d, z0.d, #0x8000000080000000
orn z0.h, z0.h, #0xfffe
ORN Z0.H, Z0.H, #0XFFFE
orn z0.s, z0.s, #0xfffefffe
orn z0.d, z0.d, #0xfffefffefffefffe
orn z0.h, z0.h, #0x8000
ORN Z0.H, Z0.H, #0X8000
orn z0.s, z0.s, #0x80008000
orn z0.d, z0.d, #0x8000800080008000
orn z0.b, z0.b, #0xfe
ORN Z0.B, Z0.B, #0XFE
orn z0.h, z0.h, #0xfefe
orn z0.s, z0.s, #0xfefefefe
orn z0.d, z0.d, #0xfefefefefefefefe
orn z0.b, z0.b, #0xaa
ORN Z0.B, Z0.B, #0XAA
orn z0.h, z0.h, #0xaaaa
orn z0.s, z0.s, #0xaaaaaaaa
orn z0.d, z0.d, #0xaaaaaaaaaaaaaaaa
orn z0.s, z0.s, #0x7fffffff
ORN Z0.S, Z0.S, #0X7FFFFFFF
orn z0.d, z0.d, #0x7fffffff7fffffff
orn z0.s, z0.s, #0x40000000
ORN Z0.S, Z0.S, #0X40000000
orn z0.d, z0.d, #0x4000000040000000
orn z0.h, z0.h, #0x7fff
ORN Z0.H, Z0.H, #0X7FFF
orn z0.s, z0.s, #0x7fff7fff
orn z0.d, z0.d, #0x7fff7fff7fff7fff
orn z0.b, z0.b, #0x40
ORN Z0.B, Z0.B, #0X40
orn z0.h, z0.h, #0x4040
orn z0.s, z0.s, #0x40404040
orn z0.d, z0.d, #0x4040404040404040
orn z0.b, z0.b, #0x1c
ORN Z0.B, Z0.B, #0X1C
orn z0.h, z0.h, #0x1c1c
orn z0.s, z0.s, #0x1c1c1c1c
orn z0.d, z0.d, #0x1c1c1c1c1c1c1c1c
orn z0.s, z0.s, #0x100
ORN Z0.S, Z0.S, #0X100
orn z0.d, z0.d, #0x10000000100
orn z0.d, z0.d, #0x1
ORN Z0.D, Z0.D, #0X1
.include "advsimd-compnum.s"
# PR 22988 - check that [Rn] is equivalent to [Rn,xzr]
ldff1b z0.b, p1/z, [x0]
ldff1b z0.h, p1/z, [x1]
ldff1b z0.s, p1/z, [x2]
ldff1b z0.d, p1/z, [x3]
ldff1d z0.d, p0/z, [x0]
ldff1h z0.h, p1/z, [x9]
ldff1h z0.s, p1/z, [x10]
ldff1h z0.d, p1/z, [x11]
ldff1sb z0.s, p1/z, [x14]
ldff1sb z0.d, p1/z, [x15]
ldff1sh z0.s, p1/z, [x18]
ldff1sh z0.d, p1/z, [x19]
ldff1sw z0.d, p1/z, [x23]
ldff1w z0.d, p1/z, [x27]
|
tactcomplabs/xbgas-binutils-gdb
| 14,164
|
gas/testsuite/gas/aarch64/illegal.s
|
/* illegal.s Test file for AArch64 instructions that should be rejected
by the assembler.
Copyright (C) 2011-2022 Free Software Foundation, Inc. Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, or
(at your option) any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
.text
// For urecpe and ursqrte, only 2s and 4s are accepted qualifiers.
urecpe v0.1d, v7.1d
urecpe v0.2d, v7.2d
ursqrte v0.1d, v7.1d
ursqrte v0.2d, v7.2d
// For AdvSIMD (across) instructions, there are restraints on the register type and qualifiers.
saddlv b7, v31.8b
saddlv d7, v31.2s
saddlv q7, v31.2d
smaxv s7, v31.2s
sminv d7, v31.2d
fmaxv h7, v31.2h
fmaxv s7, v31.4h
fminv d7, v31.2d
abs b0, b31
neg b0, b31
abs h0, h31
neg h0, h31
abs s0, s31
neg s0, s31
fcvt s0, s0
bfm w0, w1, 8, 43
ubfm w0, x1, 8, 31
aese v1.8b, v2.8b
sha1h s7, d31
sha1h q7, d31
sha1su1 v7.4s, v7.2s
sha256su0 v7.2d, v7.2d
sha1c q7, q3, v7.4s
sha1p s7, q8, v9.4s
sha1m v8.4s, v7.4s, q8
sha1su0 v0.2d, v1.2d, v2.2d
sha256h q7, s2, v8.4s
pmull v7.8b, v15.8b, v31.8b
pmull v7.1q, v15.1q, v31.1d
pmull2 v7.8h, v15.8b, v31.8b
pmull2 v7.1q, v15.2d, v31.1q
ld2 {v1.4h, v0.4h}, [x1]
strb x0, [sp, x1, lsl #0]
strb w7, [x30, x0, lsl]
strb w7, [x30, x0, lsl #1]
ldtr x7, [x15, 266]
sttr x7, [x15, #1]!
stxrb x2, w1, [sp]
stxp w2, x3, w4, [x0]
ldxp w3, x4, [x30]
st2 {v4.2d, v5.2d}, [x3, #3]
st2 {v4.2d, v5.2d, v6.2d}, [x3]
st1 {v4.2d, v6.2d, v8.2d}, [x3]
st3 {v4.2d, v6.2d}, [x3]
st4 {v4.2d, v6.2d}, [x3]
st2 {v4.2d, v6.2d, v8.2d, v10.2d}, [x3]
st2 {v4.2d, v6.2d, v8.2d, v10.2d}, [x3], 48
ext v0.8b, v1.8b, v2.8b, 8
ext v0.16b, v1.16b, v2.16b, 20
tbz w0, #40, 0x17c
svc
fmov v1.D[0], x0
fmov v2.S[2], x0
fmov v2.S[1], x0
fmov v2.D[1], w0
smaddl w0, w1, w2, x3
smaddl x0, x1, w2, x3
smaddl x0, w1, x2, x3
smaddl x0, w1, w2, w3
ld1 {v1.s, v2.s}[1], [x3]
st1 {v2.s, v3.s}[1], [x4]
ld2 {v1.s, v2.s, v3.s}[1], [x3]
st2 {v2.s, v2.s, v3.s}[1], [x4]
ld3 {v1.s, v2.s, v3.s, v4.s}[1], [x3]
st3 {v2.s, v3.s, v4.s, v5.s}[1], [x4]
ld4 {v1.s}[1], [x3]
st4 {v2.s}[1], [x4]
ld2 {v1.b, v3.b}[1], [x3]
st2 {v2.b, v4.b}[1], [x4]
ld3 {v1.b, v3.b, v5.b}[1], [x3]
st3 {v2.b, v4.b, v6.b}[1], [x4]
ld4 {v1.b, v3.b, v5.b, v7.b}[1], [x3]
st4 {v2.b, v4.b, v6.b, v8.b}[1], [x4]
ld1 {v1.q}[1], [x3]
ld1r {v1.4s, v3.4s}, [x3]
ld1r {v1.4s, v2.4s, v3.4s}, [x3]
ld2r {v1.4s, v2.4s, v3.4s}, [x3]
ld3r {v1.4s, v2.4s, v3.4s, v4.4s}, [x3]
ld4r {v1.4s}, [x3]
ld1r {v1.4s, v3.4s}, [x3], x4
ld1r {v1.4s, v2.4s, v3.4s}, [x3], x4
ld2r {v1.4s, v2.4s, v3.4s}, [x3], x4
ld3r {v1.4s, v2.4s, v3.4s, v4.4s}, [x3], x4
ld4r {v1.4s}, [x3], x4
ld1r {v1.4s}, [x3], #1
ld1r {v1.4s, v2.4s}, [x3], #8
ld2r {v1.4s, v2.4s}, [x3], #4
ld3r {v1.4s, v2.4s, v3.4s}, [x3], #16
ld4r {v1.4s, v2.4s, v3.4s, v4.4s}, [x3], #32
addp s1, v2.2s
addp s1, v2.2d
addp d1, v2.2s
fmaxp s1, v2.4s
add s1, s2, s3
cmhi d1, d2, s3
shll v0.8h, v1.8b, 16
shll2 v0.2d, v1.4s, 16
dup s1, v2.d[1]
dup s1, v2.s[4]
mov s1, v2.h[1]
clrex #16
msr daif, w5
mrs w15, midr_el1
mrs x0, dummy
sshr v0.4s, v1.4s, #0
sshr v0.4s, v1.4s, #33
sshr v0.4h, v1.4h, #20
shl v0.4s, v1.4s, #32
fcvtzs v0.2h, v1.2h, #2
uqshrn v0.2s, v1.2d, 33
uqrshrn v0.2s, v1.2s, 32
sshll v8.8h, v2.8b, #8
sysl x7, #10, C15, C7, #11
sysl w7, #1, C15, C7, #1
dsb dummy
dmb #16
isb osh
prfm 0x2f, LABEL1
prfm pldl3strm, [sp, #8]!
prfm pldl3strm, [sp], #8
prfm pldl3strm, [sp, w0, sxtw #3]!
prfm pldl3strm, =0x100
sttr x0, LABEL1
sttr x0, [sp, #16]!
sttr x0, [sp], #16
sttr x0, [sp, x1]
ldur x0, LABEL1
ldur x0, [sp, #16]!
ldur x0, [sp], #16
ldur x0, [sp, x1]
ldr b0, =0x100
ldr h0, LABEL1
ic ivau
ic ivau, w0
ic ialluis, xzr
ic ialluis, x0
sys #0, c0, c0, 0, w0
msr spsel, #16
msr cptr_el2, #15
movz x1,#:abs_g2:u48, lsl #16
movz x1, 0xddee, lsl #8
movz w1,#:abs_g2:u48
movz w1,#:abs_g3:u48
movk x1,#:abs_g1_s:s12
movi v0.4s, #256
movi v0.2d, #0xabcdef
bic v0.4s, #255, msl #8
bic v0.4s, #512
bic v0.4s, #1, lsl #31
// bic v0.4h, #1, lsl #16
orr v0.4s, #255, msl #8
orr v0.4s, #512
movi v0.4s, #127, lsl #4
movi v0.4s, #127, msl #24
// movi v0.4h, #127, lsl #16
mvni v0.4s, #127, lsl #4
mvni v0.4s, #127, msl #24
// mvni v0.4h, #127, lsl #16
fmov v0.2s, #3.1415926
fmov v0.4s, #3.1415926
fmov v0.2d, #3.1415926
fmov x0, #1.0
fmov w0, w1
msr #5, #0
msr SPSel, #2
tbl v0.16b, {v1.16b, v3.16b, v5.16b}, v2.16b
tbx v0.8b, {v1.16b, v3.16b, v5.16b, v7.16b}, v2.8b
// Alternating register list forms are no longer available A64 ISA
.macro ldst2_reg_list_post_imm_reg_64 inst type postreg
\inst\()2 {v0.\type, v2.\type}, [x0], #16
\inst\()2 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], #32
.ifnb \postreg
\inst\()2 {v0.\type, v2.\type}, [x0], \postreg
\inst\()2 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], \postreg
.endif
.endm
.macro ldst2_reg_list_post_imm_reg_128 inst type postreg
\inst\()2 {v0.\type, v2.\type}, [x0], #32
\inst\()2 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], #64
.ifnb \postreg
\inst\()2 {v0.\type, v2.\type}, [x0], \postreg
\inst\()2 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], \postreg
.endif
.endm
.irp instr ld,st
.irp bits_64 8b, 4h, 2s
ldst2_reg_list_post_imm_reg_64 \instr \bits_64 x7
.endr
.endr
.irp instr ld,st
.irp bits_128 16b, 8h, 4s, 2d
ldst2_reg_list_post_imm_reg_128 \instr \bits_128 x7
.endr
.endr
.macro ldst34_reg_list_post_imm_reg_64 inst type postreg
\inst\()3 {v0.\type, v2.\type, v4.\type}, [x0], #24
\inst\()4 {v0.\type, v2.\type, v4.\type, v6.\type}, [x0], #32
\inst\()3 {v0.\type, v2.\type, v4.\type}, [x0], \postreg
\inst\()4 {v0.\type, v2.\type, v4.\type, v6.\type}, [x0], \postreg
.endm
.macro ldst34_reg_list_post_imm_reg_128 inst type postreg
\inst\()3 {v0.\type, v2.\type, v4.\type}, [x0], #48
\inst\()4 {v0.\type, v2.\type, v4.\type, v6.\type}, [x0], #64
\inst\()3 {v0.\type, v2.\type, v4.\type}, [x0], \postreg
\inst\()4 {v0.\type, v2.\type, v4.\type, v6.\type}, [x0], \postreg
.endm
.irp instr ld,st
.irp bits_64 8b, 4h, 2s
ldst34_reg_list_post_imm_reg_64 \instr \bits_64 x7
.endr
.endr
.irp instr ld,st
.irp bits_128 16b, 8h, 4s, 2d
ldst34_reg_list_post_imm_reg_128 \instr \bits_128 x7
.endr
.endr
// LD1R expects one register only.
ld1r {v0.8b, v1.8b}, [x0], #1
ld1r {v0.16b, v1.16b}, [x0], #1
ld1r {v0.4h, v1.4h}, [x0], #2
ld1r {v0.8h, v1.8h}, [x0], #2
ld1r {v0.2s, v1.2s}, [x0], #4
ld1r {v0.4s, v1.4s}, [x0], #4
ld1r {v0.1d, v1.1d}, [x0], #8
ld1r {v0.2d, v1.2d}, [x0], #8
.macro ldstn_index_rep_H_altreg_imm inst index type rep
\inst\()2\rep {v0.\type, v2.\type}\index, [x0], #4
\inst\()3\rep {v0.\type, v2.\type, v4.\type}\index, [x0], #6
\inst\()4\rep {v0.\type, v2.\type, v4.\type, v6.\type}\index, [x0], #8
.endm
.irp instr, ld, st
ldstn_index_rep_H_altreg_imm \instr index="[1]" type=h rep=""
.ifnc \instr, st
.irp types 4h, 8h
ldstn_index_rep_H_altreg_imm \instr index="" type=\types rep="r"
.endr
.endif
.endr
.macro ldstn_index_rep_S_altreg_imm inst index type rep
\inst\()2\rep {v0.\type, v2.\type}\index, [x0], #8
\inst\()3\rep {v0.\type, v2.\type, v4.\type}\index, [x0], #12
\inst\()4\rep {v0.\type, v2.\type, v4.\type, v6.\type}\index, [x0], #16
.endm
.irp instr, ld, st
ldstn_index_rep_S_altreg_imm \instr index="[1]" type=s rep=""
.ifnc \instr, st
.irp types 2s, 4s
ldstn_index_rep_S_altreg_imm \instr index="" type=\types rep="r"
.endr
.endif
.endr
.macro ldstn_index_rep_D_altreg_imm inst index type rep
\inst\()2\rep {v0.\type, v2.\type}\index, [x0], #16
\inst\()3\rep {v0.\type, v2.\type, v4.\type}\index, [x0], #24
\inst\()4\rep {v0.\type, v2.\type, v4.\type, v6.\type}\index, [x0], #32
.endm
.irp instr, ld, st
ldstn_index_rep_D_altreg_imm \instr index="[1]" type=d rep=""
.ifnc \instr, st
.irp types 1d, 2d
ldstn_index_rep_D_altreg_imm \instr index="" type=\types rep="r"
.endr
.endif
.endr
.irp type 8b, 16b, 4h, 8h, 2s, 4s, 1d, 2d
ld1r {v0.\type, v1.\type}, [x0], x7
.endr
.macro ldstn_index_rep_reg_altreg inst index type rep postreg
\inst\()2\rep {v0.\type, v2.\type}\index, [x0], \postreg
\inst\()3\rep {v0.\type, v2.\type, v4.\type}\index, [x0], \postreg
\inst\()4\rep {v0.\type, v2.\type, v4.\type, v6.\type}\index, [x0], \postreg
.endm
.irp instr, ld, st
.irp itypes b,h,s,d
ldstn_index_rep_reg_altreg \instr index="[1]" type=\itypes rep="" postreg=x7
.endr
.ifnc \instr, st
.irp types 8b, 16b, 4h, 8h, 2s, 4s, 1d, 2d
ldstn_index_rep_reg_altreg \instr index="" type=\types rep="r" postreg=x7
.endr
.endif
.endr
.macro ldnstn_reg_list type inst index rep
.ifb \index
.ifnb \rep
\inst\()1\rep {v0.\type, v1.\type}\index, [x0]
.endif
.endif
.ifnc \type, B
\inst\()2\rep {v0.\type, v2.\type}\index, [x0]
.endif
.ifnc \type, B
\inst\()3\rep {v0.\type, v2.\type, v4.\type}\index, [x0]
.endif
.ifnc \type, B
\inst\()4\rep {v0.\type, v2.\type, v4.\type, v6.\type}\index, [x0]
.endif
.endm
ldnstn_reg_list type="8B", inst="ld" index="" rep=""
ldnstn_reg_list type="8B", inst="st" index="" rep=""
ldnstn_reg_list type="16B", inst="ld" index="" rep=""
ldnstn_reg_list type="16B", inst="st" index="" rep=""
ldnstn_reg_list type="4H", inst="ld" index="" rep=""
ldnstn_reg_list type="4H", inst="st" index="" rep=""
ldnstn_reg_list type="8H", inst="ld" index="" rep=""
ldnstn_reg_list type="8H", inst="st" index="" rep=""
ldnstn_reg_list type="2S", inst="ld" index="" rep=""
ldnstn_reg_list type="2S", inst="st" index="" rep=""
ldnstn_reg_list type="4S", inst="ld" index="" rep=""
ldnstn_reg_list type="4S", inst="st" index="" rep=""
ldnstn_reg_list type="2D", inst="ld" index="" rep=""
ldnstn_reg_list type="2D", inst="st" index="" rep=""
ldnstn_reg_list type="B", inst="ld" index="[1]" rep=""
ldnstn_reg_list type="B", inst="st" index="[1]" rep=""
ldnstn_reg_list type="B", inst="ld" index="[1]" rep=""
ldnstn_reg_list type="B", inst="st" index="[1]" rep=""
ldnstn_reg_list type="H", inst="ld" index="[1]" rep=""
ldnstn_reg_list type="H", inst="st" index="[1]" rep=""
ldnstn_reg_list type="H", inst="ld" index="[1]" rep=""
ldnstn_reg_list type="H", inst="st" index="[1]" rep=""
ldnstn_reg_list type="S", inst="ld" index="[1]" rep=""
ldnstn_reg_list type="S", inst="st" index="[1]" rep=""
ldnstn_reg_list type="S", inst="ld" index="[1]" rep=""
ldnstn_reg_list type="S", inst="st" index="[1]" rep=""
ldnstn_reg_list type="D", inst="ld" index="[1]" rep=""
ldnstn_reg_list type="D", inst="st" index="[1]" rep=""
ldnstn_reg_list type="8B", inst="ld" index="" rep="r"
ldnstn_reg_list type="16B", inst="ld" index="" rep="r"
ldnstn_reg_list type="4H", inst="ld" index="" rep="r"
ldnstn_reg_list type="8H", inst="ld" index="" rep="r"
ldnstn_reg_list type="2S", inst="ld" index="" rep="r"
ldnstn_reg_list type="4S", inst="ld" index="" rep="r"
ldnstn_reg_list type="1D", inst="ld" index="" rep="r"
ldnstn_reg_list type="2D", inst="ld" index="" rep="r"
pmull v0.1q, v1.1d, v2.1d
pmull2 v0.1q, v1.2d, v2.2d
// #<fbits> out of range
.irp instr, scvtf, ucvtf
\instr d0, w1, 33
\instr s0, w0, 33
\instr d0, x1, 65
\instr s0, x1, 65
.endr
.irp instr, fcvtzs, fcvtzu
\instr w1, d0, 33
\instr w0, s0, 33
\instr x1, d0, 65
\instr x1, s0, 65
.endr
// Invalid instruction.
mockup-op
ldrh w0, [x1, x2, lsr #1]
add w0, w1, w2, ror #1
sub w0, w1, w2, asr #32
eor w0, w1, w2, ror #32
add x0, x1, #20, LSL #16
add x0, x1, #20, UXTX #12
add x0, x1, #20, LSR
add x0, x1, #20, LSL
ldnp h7, h15, [x0, #2]
ldnp b15, b31, [x0], #4
ldnp h0, h1, [x0, #6]!
uqrshrn h0, s1, #63
sqshl b7, b15, #8
bfxil w7, w15, #15, #30
bfi x3, x7, #31, #48
str x1,page_table_count
prfm PLDL3KEEP, [x9, x15, sxtx #2]
mrs x5, S1_0_C17_C8_0
msr S3_1_C13_C15_1, x7
msr S3_1_C11_C15_-1, x7
msr S3_1_11_15_1, x7
// MOVI (alias of ORR immediate) is no longer supported.
movi w1, #15
.set u48, 0xaabbccddeeff
uxtb x7, x15
uxth x7, x15
uxtw x7, x15
sxtb w15, xzr
sxth w15, xzr
sxtw w15, xzr
mov w0, v0.b[0]
mov w0, v0.h[0]
mov w0, v0.d[0]
mov x0, v0.b[0]
mov x0, v0.h[0]
mov x0, v0.s[0]
uabdl2 v20.4S, v12.8H, v29.8
movi d1, 0xffff, lsl #16
ST3 {v18.D-v20.D}[0],[x28],x
ST1 {v7.B}[2],[x4],x
ST1 {v22.1D-v25.1D},[x10],x
ldr w0, [x0]!
ldr w0, [x0], {127}
orr x0, x0, #0xff, lsl #1
orr x0. x0, #0xff, lsl #1
orr x0, x0, #0xff lsl #1
mov x0, ##5
msr daifset, x0
msr daifclr, x0
fmov s0, #0x11
fmov s0, #0xC0280000C1400000
fmov d0, #0xC02f800000000000
// No 16-byte relocation
ldr q0, =one_label
ands w0, w24, #0xffeefffffffffffd
one_label:
cinc w0, w1, al
cinc w0, w1, nv
cset w0, al
cset w0, nv
cinv w0, w1, al
cinv w0, w1, nv
csetm w0, al
csetm w0, nv
cneg w0, w1, al
cneg w0, w1, nv
mrs x5, S4_0_C12_C8_0
mrs x6, S0_8_C11_C7_5
mrs x7, S1_1_C16_C6_6
mrs x8, S2_2_C15_C16_7
mrs x9, S3_3_C14_C15_8
fmov s0, #-0.0
fmov s0, #0x40000000 // OK
fmov s0, #0x80000000
fmov s0, #0xc0000000 // OK
fmov d0, #-0.0
fmov d0, #0x4000000000000000 // OK
fmov d0, #0x8000000000000000
fmov d0, #0xc000000000000000 // OK
fcmgt v0.4s, v0.4s, #0.0 // OK
fcmgt v0.4s, v0.4s, #0 // OK
fcmgt v0.4s, v0.4s, #-0.0
fcmgt v0.2d, v0.2d, #0.0 // OK
fcmgt v0.2d, v0.2d, #0 // OK
fcmgt v0.2d, v0.2d, #-0.0
# PR 20319: FMOV instructions changing the size from 32 bits
# to 64 bits and vice versa are illegal.
fmov s9, x0
fmov d7, w1
st1 {v0.16b}[0],[x0]
st2 {v0.16b-v1.16b}[1],[x0]
st3 {v0.16b-v2.16b}[2],[x0]
st4 {v0.8b-v3.8b}[4],[x0]
// End (for errors during literal pool generation)
|
tactcomplabs/xbgas-binutils-gdb
| 2,866
|
gas/testsuite/gas/aarch64/fp_cvt_int.s
|
/* fp_cvt_ins.s Test file for AArch64 floating-point<->fixed-point
conversion and floating-point<->integer conversion instructions.
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, or
(at your option) any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
// SCVTF & UCVTF
.macro do_cvtf fbits, reg
.ifc \fbits, 0
// Floating-point<->integer conversions
SCVTF \reg\()7, W7
SCVTF \reg\()7, X7
UCVTF \reg\()7, W7
UCVTF \reg\()7, X7
.else
// Floating-point<->fixed-point conversions
.ifle \fbits-32
SCVTF \reg\()7, W7, #\fbits
.endif
SCVTF \reg\()7, X7, #\fbits
.ifle \fbits-32
UCVTF \reg\()7, W7, #\fbits
.endif
UCVTF \reg\()7, X7, #\fbits
.endif
.endm
// FMOV
.macro do_fmov type
.ifc \type, S
// 32-bit
FMOV W7, S7
FMOV S7, W7
.elseif \type == D
// 64-bit
FMOV X7, D7
FMOV D7, X7
.else
// 64-bit with V reg element
FMOV X7, V7.D[1]
FMOV V7.D[1], X7
.endif
.endm
.macro do_fcvt suffix, fbits, reg
.ifc \fbits, 0
// Floating-point<->integer conversions
FCVT\suffix W7, \reg\()7
FCVT\suffix X7, \reg\()7
.else
// Floating-point<->fixed-point conversions
.ifle \fbits-32
FCVT\suffix W7, \reg\()7, #\fbits
.endif
FCVT\suffix X7, \reg\()7, #\fbits
.endif
.endm
.macro fcvts_with_fbits fbits
.ifc \fbits, 0
// fp <-> integer
.irp reg, S, D
// single-precision and double precision
do_fcvt NS, \fbits, \reg
do_fcvt NU, \fbits, \reg
do_fcvt PS, \fbits, \reg
do_fcvt PU, \fbits, \reg
do_fcvt MS, \fbits, \reg
do_fcvt MU, \fbits, \reg
do_fcvt ZS, \fbits, \reg
do_fcvt ZU, \fbits, \reg
do_cvtf \fbits, \reg
do_fcvt AS, \fbits, \reg
do_fcvt AU, \fbits, \reg
do_fmov S
.endr
.else
// fp <-> fixed-point
// After ISA 2.06, only FCVTZ[US] and [US]CVTF are available
.irp reg, S, D
// single-precision and double precision
do_fcvt ZS, \fbits, \reg
do_fcvt ZU, \fbits, \reg
do_cvtf \fbits, \reg
.endr
.endif
.endm
.macro fcvts_with_fbits_wrapper from=0, to=64
fcvts_with_fbits \from
.if \to-\from
fcvts_with_fbits_wrapper "(\from+1)", \to
.endif
.endm
func:
// Generate fcvt instructions without fbits and
// with fbits from 1 to 64, also generate [us]cvtf
// and fmov.
fcvts_with_fbits_wrapper from=0, to=64
do_fmov V
|
tactcomplabs/xbgas-binutils-gdb
| 1,140
|
gas/testsuite/gas/aarch64/pac-feat.s
|
/* ARMv8.3 Pointer authentication instructions. */
.arch armv8-a+pauth
/* Basic instructions. */
pacia x3, x4
pacia x5, sp
pacib x3, x4
pacib x5, sp
pacda x3, x4
pacda x5, sp
pacdb x3, x4
pacdb x5, sp
autia x3, x4
autia x5, sp
autib x3, x4
autib x5, sp
autda x3, x4
autda x5, sp
autdb x3, x4
autdb x5, sp
paciza x5
pacizb x5
pacdza x5
pacdzb x5
autiza x5
autizb x5
autdza x5
autdzb x5
xpaci x5
xpacd x5
pacga x1, x2, x3
pacga x1, x2, sp
/* Combined instructions. */
braa x1, x2
braa x3, sp
brab x1, x2
brab x3, sp
blraa x1, x2
blraa x3, sp
blrab x1, x2
blrab x3, sp
braaz x5
brabz x5
blraaz x5
blrabz x5
retaa
retab
eretaa
eretab
ldraa x1, [x2]
ldraa x1, [x2,#0]
ldraa x3, [x4,#-8]
ldraa x5, [x6,#8]
ldraa x7, [x8,#4088]
ldraa x8, [x9,#-4096]
ldraa x2, [sp]
ldraa x4, [sp,#-2000]
ldrab x1, [x2]
ldrab x1, [x2,#0]
ldrab x3, [x4,#-8]
ldrab x5, [x6,#8]
ldrab x7, [x8,#4088]
ldrab x8, [x9,#-4096]
ldrab x2, [sp]
ldrab x4, [sp,#-2000]
ldraa x2, [x3, #8]!
ldraa x4, [x5, #-8]!
ldraa x6, [sp, #4088]!
ldrab x2, [x3, #8]!
ldrab x4, [x5, #-8]!
ldrab x6, [sp, #4088]!
|
tactcomplabs/xbgas-binutils-gdb
| 2,056
|
gas/testsuite/gas/aarch64/brbe-invalid.s
|
/* Write to read-only BRBE system registers. */
msr brbidr0_el1, x0
msr brbsrc0_el1, x0
msr brbsrc1_el1, x0
msr brbsrc2_el1, x0
msr brbsrc3_el1, x0
msr brbsrc4_el1, x0
msr brbsrc5_el1, x0
msr brbsrc6_el1, x0
msr brbsrc7_el1, x0
msr brbsrc8_el1, x0
msr brbsrc9_el1, x0
msr brbsrc10_el1, x0
msr brbsrc11_el1, x0
msr brbsrc12_el1, x0
msr brbsrc13_el1, x0
msr brbsrc14_el1, x0
msr brbsrc15_el1, x0
msr brbsrc16_el1, x0
msr brbsrc17_el1, x0
msr brbsrc18_el1, x0
msr brbsrc19_el1, x0
msr brbsrc20_el1, x0
msr brbsrc21_el1, x0
msr brbsrc22_el1, x0
msr brbsrc23_el1, x0
msr brbsrc24_el1, x0
msr brbsrc25_el1, x0
msr brbsrc26_el1, x0
msr brbsrc27_el1, x0
msr brbsrc28_el1, x0
msr brbsrc29_el1, x0
msr brbsrc30_el1, x0
msr brbsrc31_el1, x0
msr brbtgt0_el1, x0
msr brbtgt1_el1, x0
msr brbtgt2_el1, x0
msr brbtgt3_el1, x0
msr brbtgt4_el1, x0
msr brbtgt5_el1, x0
msr brbtgt6_el1, x0
msr brbtgt7_el1, x0
msr brbtgt8_el1, x0
msr brbtgt9_el1, x0
msr brbtgt10_el1, x0
msr brbtgt11_el1, x0
msr brbtgt12_el1, x0
msr brbtgt13_el1, x0
msr brbtgt14_el1, x0
msr brbtgt15_el1, x0
msr brbtgt16_el1, x0
msr brbtgt17_el1, x0
msr brbtgt18_el1, x0
msr brbtgt19_el1, x0
msr brbtgt20_el1, x0
msr brbtgt21_el1, x0
msr brbtgt22_el1, x0
msr brbtgt23_el1, x0
msr brbtgt24_el1, x0
msr brbtgt25_el1, x0
msr brbtgt26_el1, x0
msr brbtgt27_el1, x0
msr brbtgt28_el1, x0
msr brbtgt29_el1, x0
msr brbtgt30_el1, x0
msr brbtgt31_el1, x0
msr brbinf0_el1, x0
msr brbinf1_el1, x0
msr brbinf2_el1, x0
msr brbinf3_el1, x0
msr brbinf4_el1, x0
msr brbinf5_el1, x0
msr brbinf6_el1, x0
msr brbinf7_el1, x0
msr brbinf8_el1, x0
msr brbinf9_el1, x0
msr brbinf10_el1, x0
msr brbinf11_el1, x0
msr brbinf12_el1, x0
msr brbinf13_el1, x0
msr brbinf14_el1, x0
msr brbinf15_el1, x0
msr brbinf16_el1, x0
msr brbinf17_el1, x0
msr brbinf18_el1, x0
msr brbinf19_el1, x0
msr brbinf20_el1, x0
msr brbinf21_el1, x0
msr brbinf22_el1, x0
msr brbinf23_el1, x0
msr brbinf24_el1, x0
msr brbinf25_el1, x0
msr brbinf26_el1, x0
msr brbinf27_el1, x0
msr brbinf28_el1, x0
msr brbinf29_el1, x0
msr brbinf30_el1, x0
msr brbinf31_el1, x0
|
tactcomplabs/xbgas-binutils-gdb
| 1,678
|
gas/testsuite/gas/aarch64/sme-9.s
|
/* SVE2 instructions added to support SME. */
psel p1, p15, p3.b[w15, 0]
psel p2, p14, p5.b[w15, 0]
psel p3, p13, p7.b[w15, 7]
psel p5, p12, p9.b[w15, 15]
psel p8, p11, p15.h[w14, 0]
psel p13, p10, p1.h[w14, 0]
psel p15, p9, p0.h[w14, 3]
psel p1, p8, p6.h[w14, 7]
psel p2, p7, p15.s[w13, 0]
psel p3, p6, p15.s[w13, 0]
psel p5, p5, p15.s[w13, 1]
psel p8, p4, p15.s[w13, 3]
psel p13, p3, p1.d[w12, 0]
psel p15, p2, p1.d[w12, 0]
psel p1, p1, p1.d[w12, 1]
revd z0.q, p0/m, z0.q
revd z0.q, p7/m, z0.q
revd z0.q, p0/m, z31.q
revd z31.q, p7/m, z0.q
sclamp z0.b, z31.b, z17.b
sclamp z31.b, z0.b, z17.b
sclamp z8.b, z1.b, z31.b
sclamp z31.h, z0.h, z17.h
sclamp z8.h, z1.h, z31.h
sclamp z0.s, z31.s, z17.s
sclamp z31.s, z0.s, z17.s
sclamp z8.s, z1.s, z31.s
sclamp z0.d, z31.d, z17.d
sclamp z31.d, z0.d, z17.d
sclamp z8.d, z1.d, z31.d
uclamp z0.b, z31.b, z17.b
uclamp z31.b, z0.b, z17.b
uclamp z8.b, z1.b, z31.b
uclamp z0.h, z31.h, z17.h
uclamp z31.h, z0.h, z17.h
uclamp z8.h, z1.h, z31.h
uclamp z0.s, z31.s, z17.s
uclamp z31.s, z0.s, z17.s
uclamp z8.s, z1.s, z31.s
uclamp z0.d, z31.d, z17.d
uclamp z31.d, z0.d, z17.d
uclamp z8.d, z1.d, z31.d
/* The unpredicated MOVPRFX instruction. */
movprfx z3, z5
revd z3.q, p1/m, z5.q
movprfx z1, z4
revd z1.q, p1/m, z5.q
movprfx z1, z4
sclamp z1.b, z10.b, z11.b
movprfx z2, z4
sclamp z2.h, z10.h, z11.h
movprfx z3, z4
sclamp z3.s, z10.s, z11.s
movprfx z4, z5
sclamp z4.d, z10.d, z11.d
movprfx z1, z4
uclamp z1.b, z10.b, z11.b
movprfx z2, z4
uclamp z2.h, z10.h, z11.h
movprfx z3, z4
uclamp z3.s, z10.s, z11.s
movprfx z4, z5
uclamp z4.d, z10.d, z11.d
foo .req p1
bar .req w15
psel foo, p15, p3.b[w15, 0]
psel p2, p14, p5.b[bar, 0]
|
tactcomplabs/xbgas-binutils-gdb
| 558,492
|
gas/testsuite/gas/tilegx/t_insns.s
|
target:
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
{ fdouble_sub_flags r5, r6, r7 ; bnezt r15, target }
{ fdouble_sub_flags r5, r6, r7 ; bnez r15, target }
{ fdouble_addsub r5, r6, r7 ; bnez r15, target }
{ fdouble_pack1 r5, r6, r7 ; bnez r15, target }
{ fsingle_pack2 r5, r6, r7 ; bnez r15, target }
{ fsingle_mul2 r5, r6, r7 ; blez r15, target }
{ mula_hs_hu r5, r6, r7 ; bgtzt r15, target }
{ mula_hu_lu r5, r6, r7 ; bgtzt r15, target }
{ addli r5, r6, 0x1234 ; bgtzt r15, target }
{ fsingle_pack1 r5, r6 ; beqzt r15, target }
{ mul_hu_hu r5, r6, r7 ; beqzt r15, target }
{ mul_lu_lu r5, r6, r7 ; beqzt r15, target }
{ mula_hu_hu r5, r6, r7 ; beqz r15, target }
{ mula_lu_lu r5, r6, r7 ; beqz r15, target }
{ addli r5, r6, 0x1234 ; beqz r15, target }
{ dblalign2 r5, r6, r7 ; beqz r15, target }
{ mul_hs_hs r5, r6, r7 ; blbs r15, target }
{ mul_hu_ls r5, r6, r7 ; blbs r15, target }
{ shl1addx r5, r6, r7 ; blbst r15, target }
{ v1cmpleu r5, r6, r7 ; blbst r15, target }
{ v1ddotpu r5, r6, r7 ; blbst r15, target }
{ v1dotpusa r5, r6, r7 ; blbs r15, target }
{ v2cmpltsi r5, r6, 5 ; blbst r15, target }
{ v4packsc r5, r6, r7 ; blbst r15, target }
{ cmovnez r5, r6, r7 ; blbst r15, target }
{ shl1addx r5, r6, r7 ; bgtz r15, target }
{ v1adduc r5, r6, r7 ; bgtzt r15, target }
{ v1cmpleu r5, r6, r7 ; bgtz r15, target }
{ v1cmpne r5, r6, r7 ; bgtzt r15, target }
{ v1dotpus r5, r6, r7 ; bgtz r15, target }
{ v1sadau r5, r6, r7 ; bgtzt r15, target }
{ v2cmpeqi r5, r6, 5 ; bgtzt r15, target }
{ v2cmpltu r5, r6, r7 ; bgtz r15, target }
{ v2int_l r5, r6, r7 ; bgtzt r15, target }
{ v2packuc r5, r6, r7 ; bgtz r15, target }
{ v4addsc r5, r6, r7 ; bgtzt r15, target }
{ v4subsc r5, r6, r7 ; bgtzt r15, target }
{ cmples r5, r6, r7 ; bgtzt r15, target }
{ cmpltui r5, r6, 5 ; bgtzt r15, target }
{ fsingle_addsub2 r5, r6, r7 ; j target }
{ subxsc r5, r6, r7 ; bltzt r15, target }
{ v1cmpne r5, r6, r7 ; bltz r15, target }
{ v1int_l r5, r6, r7 ; bltz r15, target }
{ v1multu r5, r6, r7 ; bltz r15, target }
{ v1shrs r5, r6, r7 ; bltzt r15, target }
{ v2addsc r5, r6, r7 ; bltz r15, target }
{ v2dotp r5, r6, r7 ; bltzt r15, target }
{ v2maxsi r5, r6, 5 ; bltzt r15, target }
{ v2packh r5, r6, r7 ; bltz r15, target }
{ v2sadu r5, r6, r7 ; bltzt r15, target }
{ v2shrui r5, r6, 5 ; bltzt r15, target }
{ v4shlsc r5, r6, r7 ; bltz r15, target }
{ cmpeq r5, r6, r7 ; bltzt r15, target }
{ cmpltsi r5, r6, 5 ; bltz r15, target }
{ cmulaf r5, r6, r7 ; bltz r15, target }
{ moveli r5, 0x1234 ; bgez r15, target }
{ subxsc r5, r6, r7 ; bnez r15, target }
{ v1maxu r5, r6, r7 ; bnez r15, target }
{ v1mulu r5, r6, r7 ; bnez r15, target }
{ v1shrsi r5, r6, 5 ; bnez r15, target }
{ v2addi r5, r6, 5 ; bnezt r15, target }
{ v2mins r5, r6, r7 ; bnez r15, target }
{ v2sadu r5, r6, r7 ; bnez r15, target }
{ v2shru r5, r6, r7 ; bnez r15, target }
{ v4shrs r5, r6, r7 ; bnez r15, target }
{ cmpeq r5, r6, r7 ; bnez r15, target }
{ cmulf r5, r6, r7 ; bnez r15, target }
{ revbytes r5, r6 ; blbst r15, target }
{ shrs r5, r6, r7 ; blbst r15, target }
{ shruxi r5, r6, 5 ; blbs r15, target }
{ tblidxb3 r5, r6 ; blbst r15, target }
{ v1shl r5, r6, r7 ; blbs r15, target }
{ v2mnz r5, r6, r7 ; blbs r15, target }
{ v4add r5, r6, r7 ; blbs r15, target }
{ addx r5, r6, r7 ; blbs r15, target }
{ fsingle_sub1 r5, r6, r7 ; j target }
{ nor r5, r6, r7 ; blezt r15, target }
{ shl r5, r6, r7 ; blezt r15, target }
{ shrsi r5, r6, 5 ; blez r15, target }
{ tblidxb0 r5, r6 ; blbs r15, target }
{ v2mz r5, r6, r7 ; blbc r15, target }
{ and r5, r6, r7 ; bgtz r15, target }
{ mz r5, r6, r7 ; blbst r15, target }
{ shl r5, r6, r7 ; blbs r15, target }
{ bfexts r5, r6, 5, 7 ; jal target }
{ ori r5, r6, 5 ; bgtz r15, target }
{ infol 0x1234 ; bgez r15, target }
{ pcnt r5, r6 ; bnezt r15, target }
{ bfextu r5, r6, 5, 7 ; j target }
{ movei r5, 5 ; blbs r15, target }
{ v2avgs r5, r6, r7 ; jal target }
{ cmulh r5, r6, r7 ; jal target }
{ v2dotpa r5, r6, r7 ; j target }
{ rotli r5, r6, 5 ; jal target }
{ v4shrs r5, r6, r7 ; j target }
{ v2sub r5, r6, r7 ; j target }
{ and r5, r6, r7 ; j target }
{ nop ; blbst r15, target }
{ beqzt r15, target ; cmpltu r5, r6, r7 }
{ beqzt r15, target ; mul_hs_hs r5, r6, r7 }
{ beqzt r15, target ; shli r5, r6, 5 }
{ beqzt r15, target ; v1dotpusa r5, r6, r7 }
{ beqzt r15, target ; v2maxs r5, r6, r7 }
{ bgezt r15, target ; addli r5, r6, 0x1234 }
{ bgezt r15, target ; fdouble_pack2 r5, r6, r7 }
{ bgezt r15, target ; mulx r5, r6, r7 }
{ bgezt r15, target ; v1avgu r5, r6, r7 }
{ bgezt r15, target ; v1subuc r5, r6, r7 }
{ bgezt r15, target ; v2shru r5, r6, r7 }
{ bgtzt r15, target ; cmpne r5, r6, r7 }
{ bgtzt r15, target ; mul_hs_ls r5, r6, r7 }
{ bgtzt r15, target ; shlxi r5, r6, 5 }
{ bgtzt r15, target ; v1int_l r5, r6, r7 }
{ bgtzt r15, target ; v2mins r5, r6, r7 }
{ blbct r15, target ; addxi r5, r6, 5 }
{ blbct r15, target ; fdouble_unpack_max r5, r6, r7 }
{ blbct r15, target ; nop }
{ blbct r15, target ; v1cmpeqi r5, r6, 5 }
{ blbct r15, target ; v2addi r5, r6, 5 }
{ blbct r15, target ; v2sub r5, r6, r7 }
{ blbst r15, target ; cmula r5, r6, r7 }
{ blbst r15, target ; mul_hu_hu r5, r6, r7 }
{ blbst r15, target ; shrsi r5, r6, 5 }
{ blbst r15, target ; v1maxui r5, r6, 5 }
{ blbst r15, target ; v2mnz r5, r6, r7 }
{ blezt r15, target ; addxsc r5, r6, r7 }
{ blezt r15, target ; fnop }
{ blezt r15, target ; or r5, r6, r7 }
{ blezt r15, target ; v1cmpleu r5, r6, r7 }
{ blezt r15, target ; v2adiffs r5, r6, r7 }
{ blezt r15, target ; v4add r5, r6, r7 }
{ bltzt r15, target ; cmulf r5, r6, r7 }
{ bltzt r15, target ; mul_hu_lu r5, r6, r7 }
{ bltzt r15, target ; shrui r5, r6, 5 }
{ bltzt r15, target ; v1minui r5, r6, 5 }
{ bltzt r15, target ; v2muls r5, r6, r7 }
{ bnezt r15, target ; andi r5, r6, 5 }
{ bnezt r15, target ; fsingle_addsub2 r5, r6, r7 }
{ bnezt r15, target ; pcnt r5, r6 }
{ bnezt r15, target ; v1cmpltsi r5, r6, 5 }
{ bnezt r15, target ; v2cmpeq r5, r6, r7 }
{ bnezt r15, target ; v4int_h r5, r6, r7 }
{ beqz r15, target ; cmulfr r5, r6, r7 }
{ beqz r15, target ; mul_ls_ls r5, r6, r7 }
{ beqz r15, target ; shrux r5, r6, r7 }
{ beqz r15, target ; v1mnz r5, r6, r7 }
{ beqz r15, target ; v2mults r5, r6, r7 }
{ bgez r15, target ; bfexts r5, r6, 5, 7 }
{ bgez r15, target ; fsingle_mul1 r5, r6, r7 }
{ bgez r15, target ; revbits r5, r6 }
{ bgez r15, target ; v1cmpltu r5, r6, r7 }
{ bgez r15, target ; v2cmpeqi r5, r6, 5 }
{ bgez r15, target ; v4int_l r5, r6, r7 }
{ bgtz r15, target ; cmulhr r5, r6, r7 }
{ bgtz r15, target ; mul_lu_lu r5, r6, r7 }
{ bgtz r15, target ; shufflebytes r5, r6, r7 }
{ bgtz r15, target ; v1mulu r5, r6, r7 }
{ bgtz r15, target ; v2packh r5, r6, r7 }
{ blbc r15, target ; bfins r5, r6, 5, 7 }
{ blbc r15, target ; fsingle_pack1 r5, r6 }
{ blbc r15, target ; rotl r5, r6, r7 }
{ blbc r15, target ; v1cmpne r5, r6, r7 }
{ blbc r15, target ; v2cmpleu r5, r6, r7 }
{ blbc r15, target ; v4shl r5, r6, r7 }
{ blbs r15, target ; crc32_8 r5, r6, r7 }
{ blbs r15, target ; mula_hs_hu r5, r6, r7 }
{ blbs r15, target ; subx r5, r6, r7 }
{ blbs r15, target ; v1mz r5, r6, r7 }
{ blbs r15, target ; v2packuc r5, r6, r7 }
{ blez r15, target ; cmoveqz r5, r6, r7 }
{ blez r15, target ; fsingle_sub1 r5, r6, r7 }
{ blez r15, target ; shl r5, r6, r7 }
{ blez r15, target ; v1ddotpua r5, r6, r7 }
{ blez r15, target ; v2cmpltsi r5, r6, 5 }
{ blez r15, target ; v4shrs r5, r6, r7 }
{ bltz r15, target ; dblalign r5, r6, r7 }
{ bltz r15, target ; mula_hs_lu r5, r6, r7 }
{ bltz r15, target ; tblidxb0 r5, r6 }
{ bltz r15, target ; v1sadu r5, r6, r7 }
{ bltz r15, target ; v2sadau r5, r6, r7 }
{ bnez r15, target ; cmpeq r5, r6, r7 }
{ bnez r15, target ; infol 0x1234 }
{ bnez r15, target ; shl1add r5, r6, r7 }
{ bnez r15, target ; v1ddotpusa r5, r6, r7 }
{ bnez r15, target ; v2cmpltui r5, r6, 5 }
{ bnez r15, target ; v4sub r5, r6, r7 }
{ jal target ; cmples r5, r6, r7 }
{ jal target ; mnz r5, r6, r7 }
{ jal target ; shl2add r5, r6, r7 }
{ jal target ; v1dotpa r5, r6, r7 }
{ jal target ; v2dotp r5, r6, r7 }
{ jal target ; xor r5, r6, r7 }
{ j target ; dblalign6 r5, r6, r7 }
{ j target ; mula_hu_lu r5, r6, r7 }
{ j target ; tblidxb3 r5, r6 }
{ j target ; v1shrs r5, r6, r7 }
{ j target ; v2shl r5, r6, r7 }
cmpeqi r5, r6, 5
fetchand r5, r6, r7
ldna_add r5, r6, 5
mula_hu_lu r5, r6, r7
shlx r5, r6, r7
v1avgu r5, r6, r7
v1subuc r5, r6, r7
v2shru r5, r6, r7
{ add r15, r16, r17 ; addi r5, r6, 5 ; ld2s r25, r26 }
{ add r15, r16, r17 ; addxi r5, r6, 5 ; ld2u r25, r26 }
{ add r15, r16, r17 ; andi r5, r6, 5 ; ld2u r25, r26 }
{ add r15, r16, r17 ; cmoveqz r5, r6, r7 ; ld2s r25, r26 }
{ add r15, r16, r17 ; cmpeq r5, r6, r7 ; ld4s r25, r26 }
{ add r15, r16, r17 ; cmples r5, r6, r7 ; prefetch r25 }
{ add r15, r16, r17 ; cmplts r5, r6, r7 ; prefetch_l1_fault r25 }
{ add r15, r16, r17 ; cmpltu r5, r6, r7 ; prefetch_l2_fault r25 }
{ add r15, r16, r17 ; ctz r5, r6 ; ld2s r25, r26 }
{ add r15, r16, r17 ; fnop ; prefetch_l3 r25 }
{ add r15, r16, r17 ; info 19 ; prefetch_l1 r25 }
{ add r15, r16, r17 ; ld r25, r26 ; mula_hs_hs r5, r6, r7 }
{ add r15, r16, r17 ; ld1s r25, r26 ; andi r5, r6, 5 }
{ add r15, r16, r17 ; ld1s r25, r26 ; shl1addx r5, r6, r7 }
{ add r15, r16, r17 ; ld1u r25, r26 ; move r5, r6 }
{ add r15, r16, r17 ; ld1u r25, r26 }
{ add r15, r16, r17 ; ld2s r25, r26 ; revbits r5, r6 }
{ add r15, r16, r17 ; ld2u r25, r26 ; cmpne r5, r6, r7 }
{ add r15, r16, r17 ; ld2u r25, r26 ; subx r5, r6, r7 }
{ add r15, r16, r17 ; ld4s r25, r26 ; mulx r5, r6, r7 }
{ add r15, r16, r17 ; ld4u r25, r26 ; cmpeqi r5, r6, 5 }
{ add r15, r16, r17 ; ld4u r25, r26 ; shli r5, r6, 5 }
{ add r15, r16, r17 ; move r5, r6 ; prefetch r25 }
{ add r15, r16, r17 ; mul_hs_hs r5, r6, r7 ; prefetch_l1 r25 }
{ add r15, r16, r17 ; mul_ls_ls r5, r6, r7 ; ld4s r25, r26 }
{ add r15, r16, r17 ; mula_hs_hs r5, r6, r7 ; ld4u r25, r26 }
{ add r15, r16, r17 ; mula_ls_ls r5, r6, r7 ; ld2s r25, r26 }
{ add r15, r16, r17 ; mulax r5, r6, r7 ; ld2u r25, r26 }
{ add r15, r16, r17 ; mz r5, r6, r7 ; ld4u r25, r26 }
{ add r15, r16, r17 ; nor r5, r6, r7 ; prefetch_l1 r25 }
{ add r15, r16, r17 ; pcnt r5, r6 ; prefetch_l1_fault r25 }
{ add r15, r16, r17 ; prefetch r25 ; mula_ls_ls r5, r6, r7 }
{ add r15, r16, r17 ; prefetch_l1 r25 ; cmoveqz r5, r6, r7 }
{ add r15, r16, r17 ; prefetch_l1 r25 ; shl2addx r5, r6, r7 }
{ add r15, r16, r17 ; prefetch_l1_fault r25 ; mul_hs_hs r5, r6, r7 }
{ add r15, r16, r17 ; prefetch_l2 r25 ; addi r5, r6, 5 }
{ add r15, r16, r17 ; prefetch_l2 r25 ; rotl r5, r6, r7 }
{ add r15, r16, r17 ; prefetch_l2_fault r25 ; fnop }
{ add r15, r16, r17 ; prefetch_l2_fault r25 ; tblidxb1 r5, r6 }
{ add r15, r16, r17 ; prefetch_l3 r25 ; nop }
{ add r15, r16, r17 ; prefetch_l3_fault r25 ; cmpleu r5, r6, r7 }
{ add r15, r16, r17 ; prefetch_l3_fault r25 ; shrsi r5, r6, 5 }
{ add r15, r16, r17 ; revbytes r5, r6 ; prefetch_l2 r25 }
{ add r15, r16, r17 ; rotli r5, r6, 5 ; prefetch_l3 r25 }
{ add r15, r16, r17 ; shl1add r5, r6, r7 ; prefetch_l3_fault r25 }
{ add r15, r16, r17 ; shl2add r5, r6, r7 ; st1 r25, r26 }
{ add r15, r16, r17 ; shl3add r5, r6, r7 ; st4 r25, r26 }
{ add r15, r16, r17 ; shlx r5, r6, r7 }
{ add r15, r16, r17 ; shru r5, r6, r7 ; ld r25, r26 }
{ add r15, r16, r17 ; shufflebytes r5, r6, r7 }
{ add r15, r16, r17 ; st r25, r26 ; revbits r5, r6 }
{ add r15, r16, r17 ; st1 r25, r26 ; cmpne r5, r6, r7 }
{ add r15, r16, r17 ; st1 r25, r26 ; subx r5, r6, r7 }
{ add r15, r16, r17 ; st2 r25, r26 ; mulx r5, r6, r7 }
{ add r15, r16, r17 ; st4 r25, r26 ; cmpeqi r5, r6, 5 }
{ add r15, r16, r17 ; st4 r25, r26 ; shli r5, r6, 5 }
{ add r15, r16, r17 ; subx r5, r6, r7 ; prefetch_l1 r25 }
{ add r15, r16, r17 ; tblidxb1 r5, r6 ; prefetch_l1_fault r25 }
{ add r15, r16, r17 ; tblidxb3 r5, r6 ; prefetch_l2_fault r25 }
{ add r15, r16, r17 ; v1mulu r5, r6, r7 }
{ add r15, r16, r17 ; v2packh r5, r6, r7 }
{ add r15, r16, r17 ; xor r5, r6, r7 ; prefetch_l3_fault r25 }
{ add r5, r6, r7 ; addi r15, r16, 5 ; st r25, r26 }
{ add r5, r6, r7 ; addxi r15, r16, 5 ; st1 r25, r26 }
{ add r5, r6, r7 ; andi r15, r16, 5 ; st1 r25, r26 }
{ add r5, r6, r7 ; cmpeqi r15, r16, 5 ; st4 r25, r26 }
{ add r5, r6, r7 ; cmpleu r15, r16, r17 ; st4 r25, r26 }
{ add r5, r6, r7 ; cmpltu r15, r16, r17 ; ld r25, r26 }
{ add r5, r6, r7 ; dblalign4 r15, r16, r17 }
{ add r5, r6, r7 ; ill ; ld2u r25, r26 }
{ add r5, r6, r7 ; jalr r15 ; ld2s r25, r26 }
{ add r5, r6, r7 ; jr r15 ; ld4s r25, r26 }
{ add r5, r6, r7 ; ld r25, r26 ; cmpeq r15, r16, r17 }
{ add r5, r6, r7 ; ld r25, r26 }
{ add r5, r6, r7 ; ld1s r25, r26 ; shli r15, r16, 5 }
{ add r5, r6, r7 ; ld1u r25, r26 ; rotl r15, r16, r17 }
{ add r5, r6, r7 ; ld2s r25, r26 ; jrp r15 }
{ add r5, r6, r7 ; ld2u r25, r26 ; cmpltsi r15, r16, 5 }
{ add r5, r6, r7 ; ld4s r25, r26 ; addx r15, r16, r17 }
{ add r5, r6, r7 ; ld4s r25, r26 ; shrui r15, r16, 5 }
{ add r5, r6, r7 ; ld4u r25, r26 ; shl1addx r15, r16, r17 }
{ add r5, r6, r7 ; lnk r15 ; prefetch_l1 r25 }
{ add r5, r6, r7 ; move r15, r16 ; prefetch_l1 r25 }
{ add r5, r6, r7 ; mz r15, r16, r17 ; prefetch_l1 r25 }
{ add r5, r6, r7 ; nor r15, r16, r17 ; prefetch_l2 r25 }
{ add r5, r6, r7 ; prefetch r25 ; cmplts r15, r16, r17 }
{ add r5, r6, r7 ; prefetch_add_l2_fault r15, 5 }
{ add r5, r6, r7 ; prefetch_l1 r25 ; shl3add r15, r16, r17 }
{ add r5, r6, r7 ; prefetch_l1_fault r25 ; or r15, r16, r17 }
{ add r5, r6, r7 ; prefetch_l2 r25 ; jrp r15 }
{ add r5, r6, r7 ; prefetch_l2_fault r25 ; cmpltu r15, r16, r17 }
{ add r5, r6, r7 ; prefetch_l3 r25 ; and r15, r16, r17 }
{ add r5, r6, r7 ; prefetch_l3 r25 ; subx r15, r16, r17 }
{ add r5, r6, r7 ; prefetch_l3_fault r25 ; shl3add r15, r16, r17 }
{ add r5, r6, r7 ; rotli r15, r16, 5 ; prefetch_l1_fault r25 }
{ add r5, r6, r7 ; shl1add r15, r16, r17 ; prefetch_l2 r25 }
{ add r5, r6, r7 ; shl2add r15, r16, r17 ; prefetch_l3 r25 }
{ add r5, r6, r7 ; shl3add r15, r16, r17 ; st r25, r26 }
{ add r5, r6, r7 ; shli r15, r16, 5 ; st2 r25, r26 }
{ add r5, r6, r7 ; shrsi r15, r16, 5 ; st2 r25, r26 }
{ add r5, r6, r7 ; shrui r15, r16, 5 }
{ add r5, r6, r7 ; st r25, r26 ; shl3add r15, r16, r17 }
{ add r5, r6, r7 ; st1 r25, r26 ; or r15, r16, r17 }
{ add r5, r6, r7 ; st2 r25, r26 ; jr r15 }
{ add r5, r6, r7 ; st4 r25, r26 ; cmplts r15, r16, r17 }
{ add r5, r6, r7 ; stnt1 r15, r16 }
{ add r5, r6, r7 ; subx r15, r16, r17 ; st r25, r26 }
{ add r5, r6, r7 ; v2cmpleu r15, r16, r17 }
{ add r5, r6, r7 ; xor r15, r16, r17 ; ld1u r25, r26 }
{ addi r15, r16, 5 ; addi r5, r6, 5 ; ld2s r25, r26 }
{ addi r15, r16, 5 ; addxi r5, r6, 5 ; ld2u r25, r26 }
{ addi r15, r16, 5 ; andi r5, r6, 5 ; ld2u r25, r26 }
{ addi r15, r16, 5 ; cmoveqz r5, r6, r7 ; ld2s r25, r26 }
{ addi r15, r16, 5 ; cmpeq r5, r6, r7 ; ld4s r25, r26 }
{ addi r15, r16, 5 ; cmples r5, r6, r7 ; prefetch r25 }
{ addi r15, r16, 5 ; cmplts r5, r6, r7 ; prefetch_l1_fault r25 }
{ addi r15, r16, 5 ; cmpltu r5, r6, r7 ; prefetch_l2_fault r25 }
{ addi r15, r16, 5 ; ctz r5, r6 ; ld2s r25, r26 }
{ addi r15, r16, 5 ; fnop ; prefetch_l3 r25 }
{ addi r15, r16, 5 ; info 19 ; prefetch_l1 r25 }
{ addi r15, r16, 5 ; ld r25, r26 ; mula_hs_hs r5, r6, r7 }
{ addi r15, r16, 5 ; ld1s r25, r26 ; andi r5, r6, 5 }
{ addi r15, r16, 5 ; ld1s r25, r26 ; shl1addx r5, r6, r7 }
{ addi r15, r16, 5 ; ld1u r25, r26 ; move r5, r6 }
{ addi r15, r16, 5 ; ld1u r25, r26 }
{ addi r15, r16, 5 ; ld2s r25, r26 ; revbits r5, r6 }
{ addi r15, r16, 5 ; ld2u r25, r26 ; cmpne r5, r6, r7 }
{ addi r15, r16, 5 ; ld2u r25, r26 ; subx r5, r6, r7 }
{ addi r15, r16, 5 ; ld4s r25, r26 ; mulx r5, r6, r7 }
{ addi r15, r16, 5 ; ld4u r25, r26 ; cmpeqi r5, r6, 5 }
{ addi r15, r16, 5 ; ld4u r25, r26 ; shli r5, r6, 5 }
{ addi r15, r16, 5 ; move r5, r6 ; prefetch r25 }
{ addi r15, r16, 5 ; mul_hs_hs r5, r6, r7 ; prefetch_l1 r25 }
{ addi r15, r16, 5 ; mul_ls_ls r5, r6, r7 ; ld4s r25, r26 }
{ addi r15, r16, 5 ; mula_hs_hs r5, r6, r7 ; ld4u r25, r26 }
{ addi r15, r16, 5 ; mula_ls_ls r5, r6, r7 ; ld2s r25, r26 }
{ addi r15, r16, 5 ; mulax r5, r6, r7 ; ld2u r25, r26 }
{ addi r15, r16, 5 ; mz r5, r6, r7 ; ld4u r25, r26 }
{ addi r15, r16, 5 ; nor r5, r6, r7 ; prefetch_l1 r25 }
{ addi r15, r16, 5 ; pcnt r5, r6 ; prefetch_l1_fault r25 }
{ addi r15, r16, 5 ; prefetch r25 ; mula_ls_ls r5, r6, r7 }
{ addi r15, r16, 5 ; prefetch_l1 r25 ; cmoveqz r5, r6, r7 }
{ addi r15, r16, 5 ; prefetch_l1 r25 ; shl2addx r5, r6, r7 }
{ addi r15, r16, 5 ; prefetch_l1_fault r25 ; mul_hs_hs r5, r6, r7 }
{ addi r15, r16, 5 ; prefetch_l2 r25 ; addi r5, r6, 5 }
{ addi r15, r16, 5 ; prefetch_l2 r25 ; rotl r5, r6, r7 }
{ addi r15, r16, 5 ; prefetch_l2_fault r25 ; fnop }
{ addi r15, r16, 5 ; prefetch_l2_fault r25 ; tblidxb1 r5, r6 }
{ addi r15, r16, 5 ; prefetch_l3 r25 ; nop }
{ addi r15, r16, 5 ; prefetch_l3_fault r25 ; cmpleu r5, r6, r7 }
{ addi r15, r16, 5 ; prefetch_l3_fault r25 ; shrsi r5, r6, 5 }
{ addi r15, r16, 5 ; revbytes r5, r6 ; prefetch_l2 r25 }
{ addi r15, r16, 5 ; rotli r5, r6, 5 ; prefetch_l3 r25 }
{ addi r15, r16, 5 ; shl1add r5, r6, r7 ; prefetch_l3_fault r25 }
{ addi r15, r16, 5 ; shl2add r5, r6, r7 ; st1 r25, r26 }
{ addi r15, r16, 5 ; shl3add r5, r6, r7 ; st4 r25, r26 }
{ addi r15, r16, 5 ; shlx r5, r6, r7 }
{ addi r15, r16, 5 ; shru r5, r6, r7 ; ld r25, r26 }
{ addi r15, r16, 5 ; shufflebytes r5, r6, r7 }
{ addi r15, r16, 5 ; st r25, r26 ; revbits r5, r6 }
{ addi r15, r16, 5 ; st1 r25, r26 ; cmpne r5, r6, r7 }
{ addi r15, r16, 5 ; st1 r25, r26 ; subx r5, r6, r7 }
{ addi r15, r16, 5 ; st2 r25, r26 ; mulx r5, r6, r7 }
{ addi r15, r16, 5 ; st4 r25, r26 ; cmpeqi r5, r6, 5 }
{ addi r15, r16, 5 ; st4 r25, r26 ; shli r5, r6, 5 }
{ addi r15, r16, 5 ; subx r5, r6, r7 ; prefetch_l1 r25 }
{ addi r15, r16, 5 ; tblidxb1 r5, r6 ; prefetch_l1_fault r25 }
{ addi r15, r16, 5 ; tblidxb3 r5, r6 ; prefetch_l2_fault r25 }
{ addi r15, r16, 5 ; v1mulu r5, r6, r7 }
{ addi r15, r16, 5 ; v2packh r5, r6, r7 }
{ addi r15, r16, 5 ; xor r5, r6, r7 ; prefetch_l3_fault r25 }
{ addi r5, r6, 5 ; addi r15, r16, 5 ; st r25, r26 }
{ addi r5, r6, 5 ; addxi r15, r16, 5 ; st1 r25, r26 }
{ addi r5, r6, 5 ; andi r15, r16, 5 ; st1 r25, r26 }
{ addi r5, r6, 5 ; cmpeqi r15, r16, 5 ; st4 r25, r26 }
{ addi r5, r6, 5 ; cmpleu r15, r16, r17 ; st4 r25, r26 }
{ addi r5, r6, 5 ; cmpltu r15, r16, r17 ; ld r25, r26 }
{ addi r5, r6, 5 ; dblalign4 r15, r16, r17 }
{ addi r5, r6, 5 ; ill ; ld2u r25, r26 }
{ addi r5, r6, 5 ; jalr r15 ; ld2s r25, r26 }
{ addi r5, r6, 5 ; jr r15 ; ld4s r25, r26 }
{ addi r5, r6, 5 ; ld r25, r26 ; cmpeq r15, r16, r17 }
{ addi r5, r6, 5 ; ld r25, r26 }
{ addi r5, r6, 5 ; ld1s r25, r26 ; shli r15, r16, 5 }
{ addi r5, r6, 5 ; ld1u r25, r26 ; rotl r15, r16, r17 }
{ addi r5, r6, 5 ; ld2s r25, r26 ; jrp r15 }
{ addi r5, r6, 5 ; ld2u r25, r26 ; cmpltsi r15, r16, 5 }
{ addi r5, r6, 5 ; ld4s r25, r26 ; addx r15, r16, r17 }
{ addi r5, r6, 5 ; ld4s r25, r26 ; shrui r15, r16, 5 }
{ addi r5, r6, 5 ; ld4u r25, r26 ; shl1addx r15, r16, r17 }
{ addi r5, r6, 5 ; lnk r15 ; prefetch_l1 r25 }
{ addi r5, r6, 5 ; move r15, r16 ; prefetch_l1 r25 }
{ addi r5, r6, 5 ; mz r15, r16, r17 ; prefetch_l1 r25 }
{ addi r5, r6, 5 ; nor r15, r16, r17 ; prefetch_l2 r25 }
{ addi r5, r6, 5 ; prefetch r25 ; cmplts r15, r16, r17 }
{ addi r5, r6, 5 ; prefetch_add_l2_fault r15, 5 }
{ addi r5, r6, 5 ; prefetch_l1 r25 ; shl3add r15, r16, r17 }
{ addi r5, r6, 5 ; prefetch_l1_fault r25 ; or r15, r16, r17 }
{ addi r5, r6, 5 ; prefetch_l2 r25 ; jrp r15 }
{ addi r5, r6, 5 ; prefetch_l2_fault r25 ; cmpltu r15, r16, r17 }
{ addi r5, r6, 5 ; prefetch_l3 r25 ; and r15, r16, r17 }
{ addi r5, r6, 5 ; prefetch_l3 r25 ; subx r15, r16, r17 }
{ addi r5, r6, 5 ; prefetch_l3_fault r25 ; shl3add r15, r16, r17 }
{ addi r5, r6, 5 ; rotli r15, r16, 5 ; prefetch_l1_fault r25 }
{ addi r5, r6, 5 ; shl1add r15, r16, r17 ; prefetch_l2 r25 }
{ addi r5, r6, 5 ; shl2add r15, r16, r17 ; prefetch_l3 r25 }
{ addi r5, r6, 5 ; shl3add r15, r16, r17 ; st r25, r26 }
{ addi r5, r6, 5 ; shli r15, r16, 5 ; st2 r25, r26 }
{ addi r5, r6, 5 ; shrsi r15, r16, 5 ; st2 r25, r26 }
{ addi r5, r6, 5 ; shrui r15, r16, 5 }
{ addi r5, r6, 5 ; st r25, r26 ; shl3add r15, r16, r17 }
{ addi r5, r6, 5 ; st1 r25, r26 ; or r15, r16, r17 }
{ addi r5, r6, 5 ; st2 r25, r26 ; jr r15 }
{ addi r5, r6, 5 ; st4 r25, r26 ; cmplts r15, r16, r17 }
{ addi r5, r6, 5 ; stnt1 r15, r16 }
{ addi r5, r6, 5 ; subx r15, r16, r17 ; st r25, r26 }
{ addi r5, r6, 5 ; v2cmpleu r15, r16, r17 }
{ addi r5, r6, 5 ; xor r15, r16, r17 ; ld1u r25, r26 }
{ addli r15, r16, 0x1234 ; cmpltui r5, r6, 5 }
{ addli r15, r16, 0x1234 ; mul_hs_hu r5, r6, r7 }
{ addli r15, r16, 0x1234 ; shlx r5, r6, r7 }
{ addli r15, r16, 0x1234 ; v1int_h r5, r6, r7 }
{ addli r15, r16, 0x1234 ; v2maxsi r5, r6, 5 }
{ addli r5, r6, 0x1234 ; addx r15, r16, r17 }
{ addli r5, r6, 0x1234 ; iret }
{ addli r5, r6, 0x1234 ; movei r15, 5 }
{ addli r5, r6, 0x1234 ; shruxi r15, r16, 5 }
{ addli r5, r6, 0x1234 ; v1shl r15, r16, r17 }
{ addli r5, r6, 0x1234 ; v4add r15, r16, r17 }
{ addx r15, r16, r17 ; addi r5, r6, 5 ; prefetch r25 }
{ addx r15, r16, r17 ; addxi r5, r6, 5 ; prefetch_l1 r25 }
{ addx r15, r16, r17 ; andi r5, r6, 5 ; prefetch_l1 r25 }
{ addx r15, r16, r17 ; cmoveqz r5, r6, r7 ; prefetch r25 }
{ addx r15, r16, r17 ; cmpeq r5, r6, r7 ; prefetch_l1_fault r25 }
{ addx r15, r16, r17 ; cmples r5, r6, r7 ; prefetch_l2_fault r25 }
{ addx r15, r16, r17 ; cmplts r5, r6, r7 ; prefetch_l3_fault r25 }
{ addx r15, r16, r17 ; cmpltu r5, r6, r7 ; st1 r25, r26 }
{ addx r15, r16, r17 ; ctz r5, r6 ; prefetch r25 }
{ addx r15, r16, r17 ; fnop ; st2 r25, r26 }
{ addx r15, r16, r17 ; info 19 ; prefetch_l3 r25 }
{ addx r15, r16, r17 ; ld r25, r26 ; mulax r5, r6, r7 }
{ addx r15, r16, r17 ; ld1s r25, r26 ; cmpeq r5, r6, r7 }
{ addx r15, r16, r17 ; ld1s r25, r26 ; shl3addx r5, r6, r7 }
{ addx r15, r16, r17 ; ld1u r25, r26 ; mul_ls_ls r5, r6, r7 }
{ addx r15, r16, r17 ; ld2s r25, r26 ; addxi r5, r6, 5 }
{ addx r15, r16, r17 ; ld2s r25, r26 ; shl r5, r6, r7 }
{ addx r15, r16, r17 ; ld2u r25, r26 ; info 19 }
{ addx r15, r16, r17 ; ld2u r25, r26 ; tblidxb3 r5, r6 }
{ addx r15, r16, r17 ; ld4s r25, r26 ; or r5, r6, r7 }
{ addx r15, r16, r17 ; ld4u r25, r26 ; cmpltsi r5, r6, 5 }
{ addx r15, r16, r17 ; ld4u r25, r26 ; shrui r5, r6, 5 }
{ addx r15, r16, r17 ; move r5, r6 ; prefetch_l2_fault r25 }
{ addx r15, r16, r17 ; mul_hs_hs r5, r6, r7 ; prefetch_l3 r25 }
{ addx r15, r16, r17 ; mul_ls_ls r5, r6, r7 ; prefetch_l1_fault r25 }
{ addx r15, r16, r17 ; mula_hs_hs r5, r6, r7 ; prefetch_l2 r25 }
{ addx r15, r16, r17 ; mula_ls_ls r5, r6, r7 ; prefetch r25 }
{ addx r15, r16, r17 ; mulax r5, r6, r7 ; prefetch_l1 r25 }
{ addx r15, r16, r17 ; mz r5, r6, r7 ; prefetch_l2 r25 }
{ addx r15, r16, r17 ; nor r5, r6, r7 ; prefetch_l3 r25 }
{ addx r15, r16, r17 ; pcnt r5, r6 ; prefetch_l3_fault r25 }
{ addx r15, r16, r17 ; prefetch r25 ; mz r5, r6, r7 }
{ addx r15, r16, r17 ; prefetch_l1 r25 ; cmples r5, r6, r7 }
{ addx r15, r16, r17 ; prefetch_l1 r25 ; shrs r5, r6, r7 }
{ addx r15, r16, r17 ; prefetch_l1_fault r25 ; mula_hs_hs r5, r6, r7 }
{ addx r15, r16, r17 ; prefetch_l2 r25 ; andi r5, r6, 5 }
{ addx r15, r16, r17 ; prefetch_l2 r25 ; shl1addx r5, r6, r7 }
{ addx r15, r16, r17 ; prefetch_l2_fault r25 ; move r5, r6 }
{ addx r15, r16, r17 ; prefetch_l2_fault r25 }
{ addx r15, r16, r17 ; prefetch_l3 r25 ; revbits r5, r6 }
{ addx r15, r16, r17 ; prefetch_l3_fault r25 ; cmpne r5, r6, r7 }
{ addx r15, r16, r17 ; prefetch_l3_fault r25 ; subx r5, r6, r7 }
{ addx r15, r16, r17 ; revbytes r5, r6 ; st r25, r26 }
{ addx r15, r16, r17 ; rotli r5, r6, 5 ; st2 r25, r26 }
{ addx r15, r16, r17 ; shl1add r5, r6, r7 ; st4 r25, r26 }
{ addx r15, r16, r17 ; shl2addx r5, r6, r7 ; ld r25, r26 }
{ addx r15, r16, r17 ; shl3addx r5, r6, r7 ; ld1u r25, r26 }
{ addx r15, r16, r17 ; shrs r5, r6, r7 ; ld1u r25, r26 }
{ addx r15, r16, r17 ; shru r5, r6, r7 ; ld2u r25, r26 }
{ addx r15, r16, r17 ; st r25, r26 ; addxi r5, r6, 5 }
{ addx r15, r16, r17 ; st r25, r26 ; shl r5, r6, r7 }
{ addx r15, r16, r17 ; st1 r25, r26 ; info 19 }
{ addx r15, r16, r17 ; st1 r25, r26 ; tblidxb3 r5, r6 }
{ addx r15, r16, r17 ; st2 r25, r26 ; or r5, r6, r7 }
{ addx r15, r16, r17 ; st4 r25, r26 ; cmpltsi r5, r6, 5 }
{ addx r15, r16, r17 ; st4 r25, r26 ; shrui r5, r6, 5 }
{ addx r15, r16, r17 ; subx r5, r6, r7 ; prefetch_l3 r25 }
{ addx r15, r16, r17 ; tblidxb1 r5, r6 ; prefetch_l3_fault r25 }
{ addx r15, r16, r17 ; tblidxb3 r5, r6 ; st1 r25, r26 }
{ addx r15, r16, r17 ; v1sadu r5, r6, r7 }
{ addx r15, r16, r17 ; v2sadau r5, r6, r7 }
{ addx r15, r16, r17 ; xor r5, r6, r7 ; st4 r25, r26 }
{ addx r5, r6, r7 ; addi r15, r16, 5 }
{ addx r5, r6, r7 ; addxli r15, r16, 0x1234 }
{ addx r5, r6, r7 ; cmpeq r15, r16, r17 ; ld r25, r26 }
{ addx r5, r6, r7 ; cmples r15, r16, r17 ; ld r25, r26 }
{ addx r5, r6, r7 ; cmplts r15, r16, r17 ; ld1u r25, r26 }
{ addx r5, r6, r7 ; cmpltu r15, r16, r17 ; ld2u r25, r26 }
{ addx r5, r6, r7 ; exch4 r15, r16, r17 }
{ addx r5, r6, r7 ; ill ; prefetch_l1 r25 }
{ addx r5, r6, r7 ; jalr r15 ; prefetch r25 }
{ addx r5, r6, r7 ; jr r15 ; prefetch_l1_fault r25 }
{ addx r5, r6, r7 ; ld r25, r26 ; cmplts r15, r16, r17 }
{ addx r5, r6, r7 ; ld1s r25, r26 ; addx r15, r16, r17 }
{ addx r5, r6, r7 ; ld1s r25, r26 ; shrui r15, r16, 5 }
{ addx r5, r6, r7 ; ld1u r25, r26 ; shl1addx r15, r16, r17 }
{ addx r5, r6, r7 ; ld2s r25, r26 ; movei r15, 5 }
{ addx r5, r6, r7 ; ld2u r25, r26 ; ill }
{ addx r5, r6, r7 ; ld4s r25, r26 ; cmpeq r15, r16, r17 }
{ addx r5, r6, r7 ; ld4s r25, r26 }
{ addx r5, r6, r7 ; ld4u r25, r26 ; shl3addx r15, r16, r17 }
{ addx r5, r6, r7 ; lnk r15 ; prefetch_l3 r25 }
{ addx r5, r6, r7 ; move r15, r16 ; prefetch_l3 r25 }
{ addx r5, r6, r7 ; mz r15, r16, r17 ; prefetch_l3 r25 }
{ addx r5, r6, r7 ; nor r15, r16, r17 ; st r25, r26 }
{ addx r5, r6, r7 ; prefetch r25 ; fnop }
{ addx r5, r6, r7 ; prefetch_l1 r25 ; add r15, r16, r17 }
{ addx r5, r6, r7 ; prefetch_l1 r25 ; shrsi r15, r16, 5 }
{ addx r5, r6, r7 ; prefetch_l1_fault r25 ; shl1add r15, r16, r17 }
{ addx r5, r6, r7 ; prefetch_l2 r25 ; movei r15, 5 }
{ addx r5, r6, r7 ; prefetch_l2_fault r25 ; info 19 }
{ addx r5, r6, r7 ; prefetch_l3 r25 ; cmples r15, r16, r17 }
{ addx r5, r6, r7 ; prefetch_l3_fault r25 ; add r15, r16, r17 }
{ addx r5, r6, r7 ; prefetch_l3_fault r25 ; shrsi r15, r16, 5 }
{ addx r5, r6, r7 ; rotli r15, r16, 5 ; prefetch_l3_fault r25 }
{ addx r5, r6, r7 ; shl1add r15, r16, r17 ; st r25, r26 }
{ addx r5, r6, r7 ; shl2add r15, r16, r17 ; st2 r25, r26 }
{ addx r5, r6, r7 ; shl3add r15, r16, r17 }
{ addx r5, r6, r7 ; shlxi r15, r16, 5 }
{ addx r5, r6, r7 ; shru r15, r16, r17 ; ld1s r25, r26 }
{ addx r5, r6, r7 ; st r25, r26 ; add r15, r16, r17 }
{ addx r5, r6, r7 ; st r25, r26 ; shrsi r15, r16, 5 }
{ addx r5, r6, r7 ; st1 r25, r26 ; shl1add r15, r16, r17 }
{ addx r5, r6, r7 ; st2 r25, r26 ; move r15, r16 }
{ addx r5, r6, r7 ; st4 r25, r26 ; fnop }
{ addx r5, r6, r7 ; stnt4 r15, r16 }
{ addx r5, r6, r7 ; subx r15, r16, r17 }
{ addx r5, r6, r7 ; v2cmpltui r15, r16, 5 }
{ addx r5, r6, r7 ; xor r15, r16, r17 ; ld4u r25, r26 }
{ addxi r15, r16, 5 ; addi r5, r6, 5 ; prefetch r25 }
{ addxi r15, r16, 5 ; addxi r5, r6, 5 ; prefetch_l1 r25 }
{ addxi r15, r16, 5 ; andi r5, r6, 5 ; prefetch_l1 r25 }
{ addxi r15, r16, 5 ; cmoveqz r5, r6, r7 ; prefetch r25 }
{ addxi r15, r16, 5 ; cmpeq r5, r6, r7 ; prefetch_l1_fault r25 }
{ addxi r15, r16, 5 ; cmples r5, r6, r7 ; prefetch_l2_fault r25 }
{ addxi r15, r16, 5 ; cmplts r5, r6, r7 ; prefetch_l3_fault r25 }
{ addxi r15, r16, 5 ; cmpltu r5, r6, r7 ; st1 r25, r26 }
{ addxi r15, r16, 5 ; ctz r5, r6 ; prefetch r25 }
{ addxi r15, r16, 5 ; fnop ; st2 r25, r26 }
{ addxi r15, r16, 5 ; info 19 ; prefetch_l3 r25 }
{ addxi r15, r16, 5 ; ld r25, r26 ; mulax r5, r6, r7 }
{ addxi r15, r16, 5 ; ld1s r25, r26 ; cmpeq r5, r6, r7 }
{ addxi r15, r16, 5 ; ld1s r25, r26 ; shl3addx r5, r6, r7 }
{ addxi r15, r16, 5 ; ld1u r25, r26 ; mul_ls_ls r5, r6, r7 }
{ addxi r15, r16, 5 ; ld2s r25, r26 ; addxi r5, r6, 5 }
{ addxi r15, r16, 5 ; ld2s r25, r26 ; shl r5, r6, r7 }
{ addxi r15, r16, 5 ; ld2u r25, r26 ; info 19 }
{ addxi r15, r16, 5 ; ld2u r25, r26 ; tblidxb3 r5, r6 }
{ addxi r15, r16, 5 ; ld4s r25, r26 ; or r5, r6, r7 }
{ addxi r15, r16, 5 ; ld4u r25, r26 ; cmpltsi r5, r6, 5 }
{ addxi r15, r16, 5 ; ld4u r25, r26 ; shrui r5, r6, 5 }
{ addxi r15, r16, 5 ; move r5, r6 ; prefetch_l2_fault r25 }
{ addxi r15, r16, 5 ; mul_hs_hs r5, r6, r7 ; prefetch_l3 r25 }
{ addxi r15, r16, 5 ; mul_ls_ls r5, r6, r7 ; prefetch_l1_fault r25 }
{ addxi r15, r16, 5 ; mula_hs_hs r5, r6, r7 ; prefetch_l2 r25 }
{ addxi r15, r16, 5 ; mula_ls_ls r5, r6, r7 ; prefetch r25 }
{ addxi r15, r16, 5 ; mulax r5, r6, r7 ; prefetch_l1 r25 }
{ addxi r15, r16, 5 ; mz r5, r6, r7 ; prefetch_l2 r25 }
{ addxi r15, r16, 5 ; nor r5, r6, r7 ; prefetch_l3 r25 }
{ addxi r15, r16, 5 ; pcnt r5, r6 ; prefetch_l3_fault r25 }
{ addxi r15, r16, 5 ; prefetch r25 ; mz r5, r6, r7 }
{ addxi r15, r16, 5 ; prefetch_l1 r25 ; cmples r5, r6, r7 }
{ addxi r15, r16, 5 ; prefetch_l1 r25 ; shrs r5, r6, r7 }
{ addxi r15, r16, 5 ; prefetch_l1_fault r25 ; mula_hs_hs r5, r6, r7 }
{ addxi r15, r16, 5 ; prefetch_l2 r25 ; andi r5, r6, 5 }
{ addxi r15, r16, 5 ; prefetch_l2 r25 ; shl1addx r5, r6, r7 }
{ addxi r15, r16, 5 ; prefetch_l2_fault r25 ; move r5, r6 }
{ addxi r15, r16, 5 ; prefetch_l2_fault r25 }
{ addxi r15, r16, 5 ; prefetch_l3 r25 ; revbits r5, r6 }
{ addxi r15, r16, 5 ; prefetch_l3_fault r25 ; cmpne r5, r6, r7 }
{ addxi r15, r16, 5 ; prefetch_l3_fault r25 ; subx r5, r6, r7 }
{ addxi r15, r16, 5 ; revbytes r5, r6 ; st r25, r26 }
{ addxi r15, r16, 5 ; rotli r5, r6, 5 ; st2 r25, r26 }
{ addxi r15, r16, 5 ; shl1add r5, r6, r7 ; st4 r25, r26 }
{ addxi r15, r16, 5 ; shl2addx r5, r6, r7 ; ld r25, r26 }
{ addxi r15, r16, 5 ; shl3addx r5, r6, r7 ; ld1u r25, r26 }
{ addxi r15, r16, 5 ; shrs r5, r6, r7 ; ld1u r25, r26 }
{ addxi r15, r16, 5 ; shru r5, r6, r7 ; ld2u r25, r26 }
{ addxi r15, r16, 5 ; st r25, r26 ; addxi r5, r6, 5 }
{ addxi r15, r16, 5 ; st r25, r26 ; shl r5, r6, r7 }
{ addxi r15, r16, 5 ; st1 r25, r26 ; info 19 }
{ addxi r15, r16, 5 ; st1 r25, r26 ; tblidxb3 r5, r6 }
{ addxi r15, r16, 5 ; st2 r25, r26 ; or r5, r6, r7 }
{ addxi r15, r16, 5 ; st4 r25, r26 ; cmpltsi r5, r6, 5 }
{ addxi r15, r16, 5 ; st4 r25, r26 ; shrui r5, r6, 5 }
{ addxi r15, r16, 5 ; subx r5, r6, r7 ; prefetch_l3 r25 }
{ addxi r15, r16, 5 ; tblidxb1 r5, r6 ; prefetch_l3_fault r25 }
{ addxi r15, r16, 5 ; tblidxb3 r5, r6 ; st1 r25, r26 }
{ addxi r15, r16, 5 ; v1sadu r5, r6, r7 }
{ addxi r15, r16, 5 ; v2sadau r5, r6, r7 }
{ addxi r15, r16, 5 ; xor r5, r6, r7 ; st4 r25, r26 }
{ addxi r5, r6, 5 ; addi r15, r16, 5 }
{ addxi r5, r6, 5 ; addxli r15, r16, 0x1234 }
{ addxi r5, r6, 5 ; cmpeq r15, r16, r17 ; ld r25, r26 }
{ addxi r5, r6, 5 ; cmples r15, r16, r17 ; ld r25, r26 }
{ addxi r5, r6, 5 ; cmplts r15, r16, r17 ; ld1u r25, r26 }
{ addxi r5, r6, 5 ; cmpltu r15, r16, r17 ; ld2u r25, r26 }
{ addxi r5, r6, 5 ; exch4 r15, r16, r17 }
{ addxi r5, r6, 5 ; ill ; prefetch_l1 r25 }
{ addxi r5, r6, 5 ; jalr r15 ; prefetch r25 }
{ addxi r5, r6, 5 ; jr r15 ; prefetch_l1_fault r25 }
{ addxi r5, r6, 5 ; ld r25, r26 ; cmplts r15, r16, r17 }
{ addxi r5, r6, 5 ; ld1s r25, r26 ; addx r15, r16, r17 }
{ addxi r5, r6, 5 ; ld1s r25, r26 ; shrui r15, r16, 5 }
{ addxi r5, r6, 5 ; ld1u r25, r26 ; shl1addx r15, r16, r17 }
{ addxi r5, r6, 5 ; ld2s r25, r26 ; movei r15, 5 }
{ addxi r5, r6, 5 ; ld2u r25, r26 ; ill }
{ addxi r5, r6, 5 ; ld4s r25, r26 ; cmpeq r15, r16, r17 }
{ addxi r5, r6, 5 ; ld4s r25, r26 }
{ addxi r5, r6, 5 ; ld4u r25, r26 ; shl3addx r15, r16, r17 }
{ addxi r5, r6, 5 ; lnk r15 ; prefetch_l3 r25 }
{ addxi r5, r6, 5 ; move r15, r16 ; prefetch_l3 r25 }
{ addxi r5, r6, 5 ; mz r15, r16, r17 ; prefetch_l3 r25 }
{ addxi r5, r6, 5 ; nor r15, r16, r17 ; st r25, r26 }
{ addxi r5, r6, 5 ; prefetch r25 ; fnop }
{ addxi r5, r6, 5 ; prefetch_l1 r25 ; add r15, r16, r17 }
{ addxi r5, r6, 5 ; prefetch_l1 r25 ; shrsi r15, r16, 5 }
{ addxi r5, r6, 5 ; prefetch_l1_fault r25 ; shl1add r15, r16, r17 }
{ addxi r5, r6, 5 ; prefetch_l2 r25 ; movei r15, 5 }
{ addxi r5, r6, 5 ; prefetch_l2_fault r25 ; info 19 }
{ addxi r5, r6, 5 ; prefetch_l3 r25 ; cmples r15, r16, r17 }
{ addxi r5, r6, 5 ; prefetch_l3_fault r25 ; add r15, r16, r17 }
{ addxi r5, r6, 5 ; prefetch_l3_fault r25 ; shrsi r15, r16, 5 }
{ addxi r5, r6, 5 ; rotli r15, r16, 5 ; prefetch_l3_fault r25 }
{ addxi r5, r6, 5 ; shl1add r15, r16, r17 ; st r25, r26 }
{ addxi r5, r6, 5 ; shl2add r15, r16, r17 ; st2 r25, r26 }
{ addxi r5, r6, 5 ; shl3add r15, r16, r17 }
{ addxi r5, r6, 5 ; shlxi r15, r16, 5 }
{ addxi r5, r6, 5 ; shru r15, r16, r17 ; ld1s r25, r26 }
{ addxi r5, r6, 5 ; st r25, r26 ; add r15, r16, r17 }
{ addxi r5, r6, 5 ; st r25, r26 ; shrsi r15, r16, 5 }
{ addxi r5, r6, 5 ; st1 r25, r26 ; shl1add r15, r16, r17 }
{ addxi r5, r6, 5 ; st2 r25, r26 ; move r15, r16 }
{ addxi r5, r6, 5 ; st4 r25, r26 ; fnop }
{ addxi r5, r6, 5 ; stnt4 r15, r16 }
{ addxi r5, r6, 5 ; subx r15, r16, r17 }
{ addxi r5, r6, 5 ; v2cmpltui r15, r16, 5 }
{ addxi r5, r6, 5 ; xor r15, r16, r17 ; ld4u r25, r26 }
{ addxli r15, r16, 0x1234 ; cmulaf r5, r6, r7 }
{ addxli r15, r16, 0x1234 ; mul_hu_ls r5, r6, r7 }
{ addxli r15, r16, 0x1234 ; shru r5, r6, r7 }
{ addxli r15, r16, 0x1234 ; v1minu r5, r6, r7 }
{ addxli r15, r16, 0x1234 ; v2mulfsc r5, r6, r7 }
{ addxli r5, r6, 0x1234 ; and r15, r16, r17 }
{ addxli r5, r6, 0x1234 ; jrp r15 }
{ addxli r5, r6, 0x1234 ; nop }
{ addxli r5, r6, 0x1234 ; st2 r15, r16 }
{ addxli r5, r6, 0x1234 ; v1shru r15, r16, r17 }
{ addxli r5, r6, 0x1234 ; v4packsc r15, r16, r17 }
{ addxsc r15, r16, r17 ; cmulhr r5, r6, r7 }
{ addxsc r15, r16, r17 ; mul_lu_lu r5, r6, r7 }
{ addxsc r15, r16, r17 ; shufflebytes r5, r6, r7 }
{ addxsc r15, r16, r17 ; v1mulu r5, r6, r7 }
{ addxsc r15, r16, r17 ; v2packh r5, r6, r7 }
{ addxsc r5, r6, r7 ; cmpexch r15, r16, r17 }
{ addxsc r5, r6, r7 ; ld1u r15, r16 }
{ addxsc r5, r6, r7 ; prefetch r15 }
{ addxsc r5, r6, r7 ; st_add r15, r16, 5 }
{ addxsc r5, r6, r7 ; v2add r15, r16, r17 }
{ addxsc r5, r6, r7 ; v4shru r15, r16, r17 }
{ and r15, r16, r17 ; addi r5, r6, 5 ; st1 r25, r26 }
{ and r15, r16, r17 ; addxi r5, r6, 5 ; st2 r25, r26 }
{ and r15, r16, r17 ; andi r5, r6, 5 ; st2 r25, r26 }
{ and r15, r16, r17 ; cmoveqz r5, r6, r7 ; st1 r25, r26 }
{ and r15, r16, r17 ; cmpeq r5, r6, r7 ; st4 r25, r26 }
{ and r15, r16, r17 ; cmpleu r5, r6, r7 ; ld r25, r26 }
{ and r15, r16, r17 ; cmpltsi r5, r6, 5 ; ld1u r25, r26 }
{ and r15, r16, r17 ; cmpne r5, r6, r7 ; ld2s r25, r26 }
{ and r15, r16, r17 ; ctz r5, r6 ; st1 r25, r26 }
{ and r15, r16, r17 ; fsingle_pack1 r5, r6 ; ld1s r25, r26 }
{ and r15, r16, r17 ; ld r25, r26 ; add r5, r6, r7 }
{ and r15, r16, r17 ; ld r25, r26 ; revbytes r5, r6 }
{ and r15, r16, r17 ; ld1s r25, r26 ; ctz r5, r6 }
{ and r15, r16, r17 ; ld1s r25, r26 ; tblidxb0 r5, r6 }
{ and r15, r16, r17 ; ld1u r25, r26 ; mz r5, r6, r7 }
{ and r15, r16, r17 ; ld2s r25, r26 ; cmples r5, r6, r7 }
{ and r15, r16, r17 ; ld2s r25, r26 ; shrs r5, r6, r7 }
{ and r15, r16, r17 ; ld2u r25, r26 ; mula_hs_hs r5, r6, r7 }
{ and r15, r16, r17 ; ld4s r25, r26 ; andi r5, r6, 5 }
{ and r15, r16, r17 ; ld4s r25, r26 ; shl1addx r5, r6, r7 }
{ and r15, r16, r17 ; ld4u r25, r26 ; move r5, r6 }
{ and r15, r16, r17 ; ld4u r25, r26 }
{ and r15, r16, r17 ; movei r5, 5 ; ld r25, r26 }
{ and r15, r16, r17 ; mul_hs_ls r5, r6, r7 }
{ and r15, r16, r17 ; mul_ls_ls r5, r6, r7 ; st4 r25, r26 }
{ and r15, r16, r17 ; mula_hs_hs r5, r6, r7 }
{ and r15, r16, r17 ; mula_ls_ls r5, r6, r7 ; st1 r25, r26 }
{ and r15, r16, r17 ; mulax r5, r6, r7 ; st2 r25, r26 }
{ and r15, r16, r17 ; mz r5, r6, r7 }
{ and r15, r16, r17 ; or r5, r6, r7 ; ld1s r25, r26 }
{ and r15, r16, r17 ; prefetch r25 ; addx r5, r6, r7 }
{ and r15, r16, r17 ; prefetch r25 ; rotli r5, r6, 5 }
{ and r15, r16, r17 ; prefetch_l1 r25 ; fsingle_pack1 r5, r6 }
{ and r15, r16, r17 ; prefetch_l1 r25 ; tblidxb2 r5, r6 }
{ and r15, r16, r17 ; prefetch_l1_fault r25 ; nor r5, r6, r7 }
{ and r15, r16, r17 ; prefetch_l2 r25 ; cmplts r5, r6, r7 }
{ and r15, r16, r17 ; prefetch_l2 r25 ; shru r5, r6, r7 }
{ and r15, r16, r17 ; prefetch_l2_fault r25 ; mula_ls_ls r5, r6, r7 }
{ and r15, r16, r17 ; prefetch_l3 r25 ; cmoveqz r5, r6, r7 }
{ and r15, r16, r17 ; prefetch_l3 r25 ; shl2addx r5, r6, r7 }
{ and r15, r16, r17 ; prefetch_l3_fault r25 ; mul_hs_hs r5, r6, r7 }
{ and r15, r16, r17 ; revbits r5, r6 ; ld1s r25, r26 }
{ and r15, r16, r17 ; rotl r5, r6, r7 ; ld2s r25, r26 }
{ and r15, r16, r17 ; shl r5, r6, r7 ; ld4s r25, r26 }
{ and r15, r16, r17 ; shl1addx r5, r6, r7 ; ld4u r25, r26 }
{ and r15, r16, r17 ; shl2addx r5, r6, r7 ; prefetch_l1 r25 }
{ and r15, r16, r17 ; shl3addx r5, r6, r7 ; prefetch_l2 r25 }
{ and r15, r16, r17 ; shrs r5, r6, r7 ; prefetch_l2 r25 }
{ and r15, r16, r17 ; shru r5, r6, r7 ; prefetch_l3 r25 }
{ and r15, r16, r17 ; st r25, r26 ; cmples r5, r6, r7 }
{ and r15, r16, r17 ; st r25, r26 ; shrs r5, r6, r7 }
{ and r15, r16, r17 ; st1 r25, r26 ; mula_hs_hs r5, r6, r7 }
{ and r15, r16, r17 ; st2 r25, r26 ; andi r5, r6, 5 }
{ and r15, r16, r17 ; st2 r25, r26 ; shl1addx r5, r6, r7 }
{ and r15, r16, r17 ; st4 r25, r26 ; move r5, r6 }
{ and r15, r16, r17 ; st4 r25, r26 }
{ and r15, r16, r17 ; tblidxb0 r5, r6 ; ld r25, r26 }
{ and r15, r16, r17 ; tblidxb2 r5, r6 ; ld1u r25, r26 }
{ and r15, r16, r17 ; v1avgu r5, r6, r7 }
{ and r15, r16, r17 ; v1subuc r5, r6, r7 }
{ and r15, r16, r17 ; v2shru r5, r6, r7 }
{ and r5, r6, r7 ; add r15, r16, r17 ; ld4s r25, r26 }
{ and r5, r6, r7 ; addx r15, r16, r17 ; ld4u r25, r26 }
{ and r5, r6, r7 ; and r15, r16, r17 ; ld4u r25, r26 }
{ and r5, r6, r7 ; cmpeq r15, r16, r17 ; prefetch_l1 r25 }
{ and r5, r6, r7 ; cmples r15, r16, r17 ; prefetch_l1 r25 }
{ and r5, r6, r7 ; cmplts r15, r16, r17 ; prefetch_l2 r25 }
{ and r5, r6, r7 ; cmpltu r15, r16, r17 ; prefetch_l3 r25 }
{ and r5, r6, r7 ; fetchor4 r15, r16, r17 }
{ and r5, r6, r7 ; ill ; st2 r25, r26 }
{ and r5, r6, r7 ; jalr r15 ; st1 r25, r26 }
{ and r5, r6, r7 ; jr r15 ; st4 r25, r26 }
{ and r5, r6, r7 ; ld r25, r26 ; jalrp r15 }
{ and r5, r6, r7 ; ld1s r25, r26 ; cmplts r15, r16, r17 }
{ and r5, r6, r7 ; ld1u r25, r26 ; addi r15, r16, 5 }
{ and r5, r6, r7 ; ld1u r25, r26 ; shru r15, r16, r17 }
{ and r5, r6, r7 ; ld2s r25, r26 ; shl1add r15, r16, r17 }
{ and r5, r6, r7 ; ld2u r25, r26 ; move r15, r16 }
{ and r5, r6, r7 ; ld4s r25, r26 ; fnop }
{ and r5, r6, r7 ; ld4u r25, r26 ; andi r15, r16, 5 }
{ and r5, r6, r7 ; ld4u r25, r26 ; xor r15, r16, r17 }
{ and r5, r6, r7 ; mfspr r16, 0x5 }
{ and r5, r6, r7 ; movei r15, 5 ; ld1s r25, r26 }
{ and r5, r6, r7 ; nop ; ld1s r25, r26 }
{ and r5, r6, r7 ; or r15, r16, r17 ; ld2s r25, r26 }
{ and r5, r6, r7 ; prefetch r25 ; mnz r15, r16, r17 }
{ and r5, r6, r7 ; prefetch_l1 r25 ; cmples r15, r16, r17 }
{ and r5, r6, r7 ; prefetch_l1_fault r25 ; add r15, r16, r17 }
{ and r5, r6, r7 ; prefetch_l1_fault r25 ; shrsi r15, r16, 5 }
{ and r5, r6, r7 ; prefetch_l2 r25 ; shl1add r15, r16, r17 }
{ and r5, r6, r7 ; prefetch_l2_fault r25 ; movei r15, 5 }
{ and r5, r6, r7 ; prefetch_l3 r25 ; info 19 }
{ and r5, r6, r7 ; prefetch_l3_fault r25 ; cmples r15, r16, r17 }
{ and r5, r6, r7 ; rotl r15, r16, r17 ; ld r25, r26 }
{ and r5, r6, r7 ; shl r15, r16, r17 ; ld1u r25, r26 }
{ and r5, r6, r7 ; shl1addx r15, r16, r17 ; ld2s r25, r26 }
{ and r5, r6, r7 ; shl2addx r15, r16, r17 ; ld4s r25, r26 }
{ and r5, r6, r7 ; shl3addx r15, r16, r17 ; prefetch r25 }
{ and r5, r6, r7 ; shrs r15, r16, r17 ; prefetch r25 }
{ and r5, r6, r7 ; shru r15, r16, r17 ; prefetch_l1_fault r25 }
{ and r5, r6, r7 ; st r25, r26 ; cmples r15, r16, r17 }
{ and r5, r6, r7 ; st1 r25, r26 ; add r15, r16, r17 }
{ and r5, r6, r7 ; st1 r25, r26 ; shrsi r15, r16, 5 }
{ and r5, r6, r7 ; st2 r25, r26 ; shl r15, r16, r17 }
{ and r5, r6, r7 ; st4 r25, r26 ; mnz r15, r16, r17 }
{ and r5, r6, r7 ; sub r15, r16, r17 ; ld4s r25, r26 }
{ and r5, r6, r7 ; v1cmpleu r15, r16, r17 }
{ and r5, r6, r7 ; v2mnz r15, r16, r17 }
{ and r5, r6, r7 ; xor r15, r16, r17 ; st r25, r26 }
{ andi r15, r16, 5 ; addi r5, r6, 5 ; st1 r25, r26 }
{ andi r15, r16, 5 ; addxi r5, r6, 5 ; st2 r25, r26 }
{ andi r15, r16, 5 ; andi r5, r6, 5 ; st2 r25, r26 }
{ andi r15, r16, 5 ; cmoveqz r5, r6, r7 ; st1 r25, r26 }
{ andi r15, r16, 5 ; cmpeq r5, r6, r7 ; st4 r25, r26 }
{ andi r15, r16, 5 ; cmpleu r5, r6, r7 ; ld r25, r26 }
{ andi r15, r16, 5 ; cmpltsi r5, r6, 5 ; ld1u r25, r26 }
{ andi r15, r16, 5 ; cmpne r5, r6, r7 ; ld2s r25, r26 }
{ andi r15, r16, 5 ; ctz r5, r6 ; st1 r25, r26 }
{ andi r15, r16, 5 ; fsingle_pack1 r5, r6 ; ld1s r25, r26 }
{ andi r15, r16, 5 ; ld r25, r26 ; add r5, r6, r7 }
{ andi r15, r16, 5 ; ld r25, r26 ; revbytes r5, r6 }
{ andi r15, r16, 5 ; ld1s r25, r26 ; ctz r5, r6 }
{ andi r15, r16, 5 ; ld1s r25, r26 ; tblidxb0 r5, r6 }
{ andi r15, r16, 5 ; ld1u r25, r26 ; mz r5, r6, r7 }
{ andi r15, r16, 5 ; ld2s r25, r26 ; cmples r5, r6, r7 }
{ andi r15, r16, 5 ; ld2s r25, r26 ; shrs r5, r6, r7 }
{ andi r15, r16, 5 ; ld2u r25, r26 ; mula_hs_hs r5, r6, r7 }
{ andi r15, r16, 5 ; ld4s r25, r26 ; andi r5, r6, 5 }
{ andi r15, r16, 5 ; ld4s r25, r26 ; shl1addx r5, r6, r7 }
{ andi r15, r16, 5 ; ld4u r25, r26 ; move r5, r6 }
{ andi r15, r16, 5 ; ld4u r25, r26 }
{ andi r15, r16, 5 ; movei r5, 5 ; ld r25, r26 }
{ andi r15, r16, 5 ; mul_hs_ls r5, r6, r7 }
{ andi r15, r16, 5 ; mul_ls_ls r5, r6, r7 ; st4 r25, r26 }
{ andi r15, r16, 5 ; mula_hs_hs r5, r6, r7 }
{ andi r15, r16, 5 ; mula_ls_ls r5, r6, r7 ; st1 r25, r26 }
{ andi r15, r16, 5 ; mulax r5, r6, r7 ; st2 r25, r26 }
{ andi r15, r16, 5 ; mz r5, r6, r7 }
{ andi r15, r16, 5 ; or r5, r6, r7 ; ld1s r25, r26 }
{ andi r15, r16, 5 ; prefetch r25 ; addx r5, r6, r7 }
{ andi r15, r16, 5 ; prefetch r25 ; rotli r5, r6, 5 }
{ andi r15, r16, 5 ; prefetch_l1 r25 ; fsingle_pack1 r5, r6 }
{ andi r15, r16, 5 ; prefetch_l1 r25 ; tblidxb2 r5, r6 }
{ andi r15, r16, 5 ; prefetch_l1_fault r25 ; nor r5, r6, r7 }
{ andi r15, r16, 5 ; prefetch_l2 r25 ; cmplts r5, r6, r7 }
{ andi r15, r16, 5 ; prefetch_l2 r25 ; shru r5, r6, r7 }
{ andi r15, r16, 5 ; prefetch_l2_fault r25 ; mula_ls_ls r5, r6, r7 }
{ andi r15, r16, 5 ; prefetch_l3 r25 ; cmoveqz r5, r6, r7 }
{ andi r15, r16, 5 ; prefetch_l3 r25 ; shl2addx r5, r6, r7 }
{ andi r15, r16, 5 ; prefetch_l3_fault r25 ; mul_hs_hs r5, r6, r7 }
{ andi r15, r16, 5 ; revbits r5, r6 ; ld1s r25, r26 }
{ andi r15, r16, 5 ; rotl r5, r6, r7 ; ld2s r25, r26 }
{ andi r15, r16, 5 ; shl r5, r6, r7 ; ld4s r25, r26 }
{ andi r15, r16, 5 ; shl1addx r5, r6, r7 ; ld4u r25, r26 }
{ andi r15, r16, 5 ; shl2addx r5, r6, r7 ; prefetch_l1 r25 }
{ andi r15, r16, 5 ; shl3addx r5, r6, r7 ; prefetch_l2 r25 }
{ andi r15, r16, 5 ; shrs r5, r6, r7 ; prefetch_l2 r25 }
{ andi r15, r16, 5 ; shru r5, r6, r7 ; prefetch_l3 r25 }
{ andi r15, r16, 5 ; st r25, r26 ; cmples r5, r6, r7 }
{ andi r15, r16, 5 ; st r25, r26 ; shrs r5, r6, r7 }
{ andi r15, r16, 5 ; st1 r25, r26 ; mula_hs_hs r5, r6, r7 }
{ andi r15, r16, 5 ; st2 r25, r26 ; andi r5, r6, 5 }
{ andi r15, r16, 5 ; st2 r25, r26 ; shl1addx r5, r6, r7 }
{ andi r15, r16, 5 ; st4 r25, r26 ; move r5, r6 }
{ andi r15, r16, 5 ; st4 r25, r26 }
{ andi r15, r16, 5 ; tblidxb0 r5, r6 ; ld r25, r26 }
{ andi r15, r16, 5 ; tblidxb2 r5, r6 ; ld1u r25, r26 }
{ andi r15, r16, 5 ; v1avgu r5, r6, r7 }
{ andi r15, r16, 5 ; v1subuc r5, r6, r7 }
{ andi r15, r16, 5 ; v2shru r5, r6, r7 }
{ andi r5, r6, 5 ; add r15, r16, r17 ; ld4s r25, r26 }
{ andi r5, r6, 5 ; addx r15, r16, r17 ; ld4u r25, r26 }
{ andi r5, r6, 5 ; and r15, r16, r17 ; ld4u r25, r26 }
{ andi r5, r6, 5 ; cmpeq r15, r16, r17 ; prefetch_l1 r25 }
{ andi r5, r6, 5 ; cmples r15, r16, r17 ; prefetch_l1 r25 }
{ andi r5, r6, 5 ; cmplts r15, r16, r17 ; prefetch_l2 r25 }
{ andi r5, r6, 5 ; cmpltu r15, r16, r17 ; prefetch_l3 r25 }
{ andi r5, r6, 5 ; fetchor4 r15, r16, r17 }
{ andi r5, r6, 5 ; ill ; st2 r25, r26 }
{ andi r5, r6, 5 ; jalr r15 ; st1 r25, r26 }
{ andi r5, r6, 5 ; jr r15 ; st4 r25, r26 }
{ andi r5, r6, 5 ; ld r25, r26 ; jalrp r15 }
{ andi r5, r6, 5 ; ld1s r25, r26 ; cmplts r15, r16, r17 }
{ andi r5, r6, 5 ; ld1u r25, r26 ; addi r15, r16, 5 }
{ andi r5, r6, 5 ; ld1u r25, r26 ; shru r15, r16, r17 }
{ andi r5, r6, 5 ; ld2s r25, r26 ; shl1add r15, r16, r17 }
{ andi r5, r6, 5 ; ld2u r25, r26 ; move r15, r16 }
{ andi r5, r6, 5 ; ld4s r25, r26 ; fnop }
{ andi r5, r6, 5 ; ld4u r25, r26 ; andi r15, r16, 5 }
{ andi r5, r6, 5 ; ld4u r25, r26 ; xor r15, r16, r17 }
{ andi r5, r6, 5 ; mfspr r16, 0x5 }
{ andi r5, r6, 5 ; movei r15, 5 ; ld1s r25, r26 }
{ andi r5, r6, 5 ; nop ; ld1s r25, r26 }
{ andi r5, r6, 5 ; or r15, r16, r17 ; ld2s r25, r26 }
{ andi r5, r6, 5 ; prefetch r25 ; mnz r15, r16, r17 }
{ andi r5, r6, 5 ; prefetch_l1 r25 ; cmples r15, r16, r17 }
{ andi r5, r6, 5 ; prefetch_l1_fault r25 ; add r15, r16, r17 }
{ andi r5, r6, 5 ; prefetch_l1_fault r25 ; shrsi r15, r16, 5 }
{ andi r5, r6, 5 ; prefetch_l2 r25 ; shl1add r15, r16, r17 }
{ andi r5, r6, 5 ; prefetch_l2_fault r25 ; movei r15, 5 }
{ andi r5, r6, 5 ; prefetch_l3 r25 ; info 19 }
{ andi r5, r6, 5 ; prefetch_l3_fault r25 ; cmples r15, r16, r17 }
{ andi r5, r6, 5 ; rotl r15, r16, r17 ; ld r25, r26 }
{ andi r5, r6, 5 ; shl r15, r16, r17 ; ld1u r25, r26 }
{ andi r5, r6, 5 ; shl1addx r15, r16, r17 ; ld2s r25, r26 }
{ andi r5, r6, 5 ; shl2addx r15, r16, r17 ; ld4s r25, r26 }
{ andi r5, r6, 5 ; shl3addx r15, r16, r17 ; prefetch r25 }
{ andi r5, r6, 5 ; shrs r15, r16, r17 ; prefetch r25 }
{ andi r5, r6, 5 ; shru r15, r16, r17 ; prefetch_l1_fault r25 }
{ andi r5, r6, 5 ; st r25, r26 ; cmples r15, r16, r17 }
{ andi r5, r6, 5 ; st1 r25, r26 ; add r15, r16, r17 }
{ andi r5, r6, 5 ; st1 r25, r26 ; shrsi r15, r16, 5 }
{ andi r5, r6, 5 ; st2 r25, r26 ; shl r15, r16, r17 }
{ andi r5, r6, 5 ; st4 r25, r26 ; mnz r15, r16, r17 }
{ andi r5, r6, 5 ; sub r15, r16, r17 ; ld4s r25, r26 }
{ andi r5, r6, 5 ; v1cmpleu r15, r16, r17 }
{ andi r5, r6, 5 ; v2mnz r15, r16, r17 }
{ andi r5, r6, 5 ; xor r15, r16, r17 ; st r25, r26 }
{ bfexts r5, r6, 5, 7 ; finv r15 }
{ bfexts r5, r6, 5, 7 ; ldnt4s_add r15, r16, 5 }
{ bfexts r5, r6, 5, 7 ; shl3addx r15, r16, r17 }
{ bfexts r5, r6, 5, 7 ; v1cmpne r15, r16, r17 }
{ bfexts r5, r6, 5, 7 ; v2shl r15, r16, r17 }
{ bfextu r5, r6, 5, 7 ; cmpltu r15, r16, r17 }
{ bfextu r5, r6, 5, 7 ; ld4s r15, r16 }
{ bfextu r5, r6, 5, 7 ; prefetch_add_l3_fault r15, 5 }
{ bfextu r5, r6, 5, 7 ; stnt4 r15, r16 }
{ bfextu r5, r6, 5, 7 ; v2cmpleu r15, r16, r17 }
{ bfins r5, r6, 5, 7 ; add r15, r16, r17 }
{ bfins r5, r6, 5, 7 ; info 19 }
{ bfins r5, r6, 5, 7 ; mfspr r16, 0x5 }
{ bfins r5, r6, 5, 7 ; shru r15, r16, r17 }
{ bfins r5, r6, 5, 7 ; v1minui r15, r16, 5 }
{ bfins r5, r6, 5, 7 ; v2shrui r15, r16, 5 }
{ clz r5, r6 ; addi r15, r16, 5 ; ld2s r25, r26 }
{ clz r5, r6 ; addxi r15, r16, 5 ; ld2u r25, r26 }
{ clz r5, r6 ; andi r15, r16, 5 ; ld2u r25, r26 }
{ clz r5, r6 ; cmpeqi r15, r16, 5 ; ld4u r25, r26 }
{ clz r5, r6 ; cmpleu r15, r16, r17 ; ld4u r25, r26 }
{ clz r5, r6 ; cmpltsi r15, r16, 5 ; prefetch_l1 r25 }
{ clz r5, r6 ; cmpne r15, r16, r17 ; prefetch_l1_fault r25 }
{ clz r5, r6 ; fnop ; prefetch_l3_fault r25 }
{ clz r5, r6 ; info 19 ; st r25, r26 }
{ clz r5, r6 ; jalrp r15 ; prefetch_l3_fault r25 }
{ clz r5, r6 ; jrp r15 ; st1 r25, r26 }
{ clz r5, r6 ; ld r25, r26 ; shl2addx r15, r16, r17 }
{ clz r5, r6 ; ld1s r25, r26 ; nor r15, r16, r17 }
{ clz r5, r6 ; ld1u r25, r26 ; jalrp r15 }
{ clz r5, r6 ; ld2s r25, r26 ; cmpleu r15, r16, r17 }
{ clz r5, r6 ; ld2u r25, r26 ; add r15, r16, r17 }
{ clz r5, r6 ; ld2u r25, r26 ; shrsi r15, r16, 5 }
{ clz r5, r6 ; ld4s r25, r26 ; shl r15, r16, r17 }
{ clz r5, r6 ; ld4u r25, r26 ; mnz r15, r16, r17 }
{ clz r5, r6 ; ldnt4u r15, r16 }
{ clz r5, r6 ; mnz r15, r16, r17 ; st2 r25, r26 }
{ clz r5, r6 ; movei r15, 5 }
{ clz r5, r6 ; nop }
{ clz r5, r6 ; prefetch r15 }
{ clz r5, r6 ; prefetch r25 ; shrs r15, r16, r17 }
{ clz r5, r6 ; prefetch_l1 r25 ; mz r15, r16, r17 }
{ clz r5, r6 ; prefetch_l1_fault r25 ; jalr r15 }
{ clz r5, r6 ; prefetch_l2 r25 ; cmpleu r15, r16, r17 }
{ clz r5, r6 ; prefetch_l2_fault r25 ; addi r15, r16, 5 }
{ clz r5, r6 ; prefetch_l2_fault r25 ; shru r15, r16, r17 }
{ clz r5, r6 ; prefetch_l3 r25 ; shl1addx r15, r16, r17 }
{ clz r5, r6 ; prefetch_l3_fault r25 ; mz r15, r16, r17 }
{ clz r5, r6 ; rotl r15, r16, r17 ; st4 r25, r26 }
{ clz r5, r6 ; shl16insli r15, r16, 0x1234 }
{ clz r5, r6 ; shl2add r15, r16, r17 ; ld1s r25, r26 }
{ clz r5, r6 ; shl3add r15, r16, r17 ; ld2s r25, r26 }
{ clz r5, r6 ; shli r15, r16, 5 ; ld4s r25, r26 }
{ clz r5, r6 ; shrsi r15, r16, 5 ; ld4s r25, r26 }
{ clz r5, r6 ; shrui r15, r16, 5 ; prefetch r25 }
{ clz r5, r6 ; st r25, r26 ; mz r15, r16, r17 }
{ clz r5, r6 ; st1 r25, r26 ; jalr r15 }
{ clz r5, r6 ; st2 r25, r26 ; cmples r15, r16, r17 }
{ clz r5, r6 ; st4 r15, r16 }
{ clz r5, r6 ; st4 r25, r26 ; shrs r15, r16, r17 }
{ clz r5, r6 ; subx r15, r16, r17 ; ld2s r25, r26 }
{ clz r5, r6 ; v1shrsi r15, r16, 5 }
{ clz r5, r6 ; v4int_l r15, r16, r17 }
{ cmoveqz r5, r6, r7 ; add r15, r16, r17 ; prefetch_l2_fault r25 }
{ cmoveqz r5, r6, r7 ; addx r15, r16, r17 ; prefetch_l3 r25 }
{ cmoveqz r5, r6, r7 ; and r15, r16, r17 ; prefetch_l3 r25 }
{ cmoveqz r5, r6, r7 ; cmpeq r15, r16, r17 ; st r25, r26 }
{ cmoveqz r5, r6, r7 ; cmples r15, r16, r17 ; st r25, r26 }
{ cmoveqz r5, r6, r7 ; cmplts r15, r16, r17 ; st2 r25, r26 }
{ cmoveqz r5, r6, r7 ; cmpltu r15, r16, r17 }
{ cmoveqz r5, r6, r7 ; fnop ; ld1u r25, r26 }
{ cmoveqz r5, r6, r7 ; info 19 ; ld2s r25, r26 }
{ cmoveqz r5, r6, r7 ; jalrp r15 ; ld1u r25, r26 }
{ cmoveqz r5, r6, r7 ; jrp r15 ; ld2u r25, r26 }
{ cmoveqz r5, r6, r7 ; ld r25, r26 ; movei r15, 5 }
{ cmoveqz r5, r6, r7 ; ld1s r25, r26 ; info 19 }
{ cmoveqz r5, r6, r7 ; ld1u r25, r26 ; cmpeqi r15, r16, 5 }
{ cmoveqz r5, r6, r7 ; ld1u_add r15, r16, 5 }
{ cmoveqz r5, r6, r7 ; ld2s r25, r26 ; shli r15, r16, 5 }
{ cmoveqz r5, r6, r7 ; ld2u r25, r26 ; rotl r15, r16, r17 }
{ cmoveqz r5, r6, r7 ; ld4s r25, r26 ; jrp r15 }
{ cmoveqz r5, r6, r7 ; ld4u r25, r26 ; cmpltsi r15, r16, 5 }
{ cmoveqz r5, r6, r7 ; ldnt r15, r16 }
{ cmoveqz r5, r6, r7 ; mnz r15, r16, r17 ; ld4s r25, r26 }
{ cmoveqz r5, r6, r7 ; movei r15, 5 ; prefetch r25 }
{ cmoveqz r5, r6, r7 ; nop ; prefetch r25 }
{ cmoveqz r5, r6, r7 ; or r15, r16, r17 ; prefetch_l1_fault r25 }
{ cmoveqz r5, r6, r7 ; prefetch r25 ; or r15, r16, r17 }
{ cmoveqz r5, r6, r7 ; prefetch_l1 r25 ; fnop }
{ cmoveqz r5, r6, r7 ; prefetch_l1_fault r25 ; cmpeq r15, r16, r17 }
{ cmoveqz r5, r6, r7 ; prefetch_l1_fault r25 }
{ cmoveqz r5, r6, r7 ; prefetch_l2 r25 ; shli r15, r16, 5 }
{ cmoveqz r5, r6, r7 ; prefetch_l2_fault r25 ; rotli r15, r16, 5 }
{ cmoveqz r5, r6, r7 ; prefetch_l3 r25 ; mnz r15, r16, r17 }
{ cmoveqz r5, r6, r7 ; prefetch_l3_fault r25 ; fnop }
{ cmoveqz r5, r6, r7 ; rotl r15, r16, r17 ; ld4u r25, r26 }
{ cmoveqz r5, r6, r7 ; shl r15, r16, r17 ; prefetch_l1 r25 }
{ cmoveqz r5, r6, r7 ; shl1addx r15, r16, r17 ; prefetch_l1_fault r25 }
{ cmoveqz r5, r6, r7 ; shl2addx r15, r16, r17 ; prefetch_l2_fault r25 }
{ cmoveqz r5, r6, r7 ; shl3addx r15, r16, r17 ; prefetch_l3_fault r25 }
{ cmoveqz r5, r6, r7 ; shrs r15, r16, r17 ; prefetch_l3_fault r25 }
{ cmoveqz r5, r6, r7 ; shru r15, r16, r17 ; st1 r25, r26 }
{ cmoveqz r5, r6, r7 ; st r25, r26 ; fnop }
{ cmoveqz r5, r6, r7 ; st1 r25, r26 ; cmpeq r15, r16, r17 }
{ cmoveqz r5, r6, r7 ; st1 r25, r26 }
{ cmoveqz r5, r6, r7 ; st2 r25, r26 ; shl3addx r15, r16, r17 }
{ cmoveqz r5, r6, r7 ; st4 r25, r26 ; or r15, r16, r17 }
{ cmoveqz r5, r6, r7 ; sub r15, r16, r17 ; prefetch_l2_fault r25 }
{ cmoveqz r5, r6, r7 ; v1int_h r15, r16, r17 }
{ cmoveqz r5, r6, r7 ; v2shli r15, r16, 5 }
{ cmovnez r5, r6, r7 ; add r15, r16, r17 ; ld r25, r26 }
{ cmovnez r5, r6, r7 ; addx r15, r16, r17 ; ld1s r25, r26 }
{ cmovnez r5, r6, r7 ; and r15, r16, r17 ; ld1s r25, r26 }
{ cmovnez r5, r6, r7 ; cmpeq r15, r16, r17 ; ld2s r25, r26 }
{ cmovnez r5, r6, r7 ; cmples r15, r16, r17 ; ld2s r25, r26 }
{ cmovnez r5, r6, r7 ; cmplts r15, r16, r17 ; ld4s r25, r26 }
{ cmovnez r5, r6, r7 ; cmpltu r15, r16, r17 ; prefetch r25 }
{ cmovnez r5, r6, r7 ; fetchaddgez r15, r16, r17 }
{ cmovnez r5, r6, r7 ; ill ; prefetch_l2_fault r25 }
{ cmovnez r5, r6, r7 ; jalr r15 ; prefetch_l2 r25 }
{ cmovnez r5, r6, r7 ; jr r15 ; prefetch_l3 r25 }
{ cmovnez r5, r6, r7 ; ld r25, r26 ; cmpne r15, r16, r17 }
{ cmovnez r5, r6, r7 ; ld1s r25, r26 ; andi r15, r16, 5 }
{ cmovnez r5, r6, r7 ; ld1s r25, r26 ; xor r15, r16, r17 }
{ cmovnez r5, r6, r7 ; ld1u r25, r26 ; shl3add r15, r16, r17 }
{ cmovnez r5, r6, r7 ; ld2s r25, r26 ; nor r15, r16, r17 }
{ cmovnez r5, r6, r7 ; ld2u r25, r26 ; jalrp r15 }
{ cmovnez r5, r6, r7 ; ld4s r25, r26 ; cmpleu r15, r16, r17 }
{ cmovnez r5, r6, r7 ; ld4u r25, r26 ; add r15, r16, r17 }
{ cmovnez r5, r6, r7 ; ld4u r25, r26 ; shrsi r15, r16, 5 }
{ cmovnez r5, r6, r7 ; lnk r15 ; st1 r25, r26 }
{ cmovnez r5, r6, r7 ; move r15, r16 ; st1 r25, r26 }
{ cmovnez r5, r6, r7 ; mz r15, r16, r17 ; st1 r25, r26 }
{ cmovnez r5, r6, r7 ; nor r15, r16, r17 ; st4 r25, r26 }
{ cmovnez r5, r6, r7 ; prefetch r25 ; jalr r15 }
{ cmovnez r5, r6, r7 ; prefetch_l1 r25 ; addxi r15, r16, 5 }
{ cmovnez r5, r6, r7 ; prefetch_l1 r25 ; sub r15, r16, r17 }
{ cmovnez r5, r6, r7 ; prefetch_l1_fault r25 ; shl2addx r15, r16, r17 }
{ cmovnez r5, r6, r7 ; prefetch_l2 r25 ; nor r15, r16, r17 }
{ cmovnez r5, r6, r7 ; prefetch_l2_fault r25 ; jr r15 }
{ cmovnez r5, r6, r7 ; prefetch_l3 r25 ; cmpltsi r15, r16, 5 }
{ cmovnez r5, r6, r7 ; prefetch_l3_fault r25 ; addxi r15, r16, 5 }
{ cmovnez r5, r6, r7 ; prefetch_l3_fault r25 ; sub r15, r16, r17 }
{ cmovnez r5, r6, r7 ; rotli r15, r16, 5 ; st2 r25, r26 }
{ cmovnez r5, r6, r7 ; shl1add r15, r16, r17 ; st4 r25, r26 }
{ cmovnez r5, r6, r7 ; shl2addx r15, r16, r17 ; ld r25, r26 }
{ cmovnez r5, r6, r7 ; shl3addx r15, r16, r17 ; ld1u r25, r26 }
{ cmovnez r5, r6, r7 ; shrs r15, r16, r17 ; ld1u r25, r26 }
{ cmovnez r5, r6, r7 ; shru r15, r16, r17 ; ld2u r25, r26 }
{ cmovnez r5, r6, r7 ; st r25, r26 ; addxi r15, r16, 5 }
{ cmovnez r5, r6, r7 ; st r25, r26 ; sub r15, r16, r17 }
{ cmovnez r5, r6, r7 ; st1 r25, r26 ; shl2addx r15, r16, r17 }
{ cmovnez r5, r6, r7 ; st2 r25, r26 ; nop }
{ cmovnez r5, r6, r7 ; st4 r25, r26 ; jalr r15 }
{ cmovnez r5, r6, r7 ; sub r15, r16, r17 ; ld r25, r26 }
{ cmovnez r5, r6, r7 ; v1addi r15, r16, 5 }
{ cmovnez r5, r6, r7 ; v2int_l r15, r16, r17 }
{ cmovnez r5, r6, r7 ; xor r15, r16, r17 ; prefetch_l1_fault r25 }
{ cmpeq r15, r16, r17 ; addi r5, r6, 5 ; prefetch_l2 r25 }
{ cmpeq r15, r16, r17 ; addxi r5, r6, 5 ; prefetch_l2_fault r25 }
{ cmpeq r15, r16, r17 ; andi r5, r6, 5 ; prefetch_l2_fault r25 }
{ cmpeq r15, r16, r17 ; cmoveqz r5, r6, r7 ; prefetch_l2 r25 }
{ cmpeq r15, r16, r17 ; cmpeq r5, r6, r7 ; prefetch_l3 r25 }
{ cmpeq r15, r16, r17 ; cmples r5, r6, r7 ; st r25, r26 }
{ cmpeq r15, r16, r17 ; cmplts r5, r6, r7 ; st2 r25, r26 }
{ cmpeq r15, r16, r17 ; cmpltu r5, r6, r7 }
{ cmpeq r15, r16, r17 ; ctz r5, r6 ; prefetch_l2 r25 }
{ cmpeq r15, r16, r17 ; fsingle_add1 r5, r6, r7 }
{ cmpeq r15, r16, r17 ; info 19 ; st1 r25, r26 }
{ cmpeq r15, r16, r17 ; ld r25, r26 ; nop }
{ cmpeq r15, r16, r17 ; ld1s r25, r26 ; cmpleu r5, r6, r7 }
{ cmpeq r15, r16, r17 ; ld1s r25, r26 ; shrsi r5, r6, 5 }
{ cmpeq r15, r16, r17 ; ld1u r25, r26 ; mula_hu_hu r5, r6, r7 }
{ cmpeq r15, r16, r17 ; ld2s r25, r26 ; clz r5, r6 }
{ cmpeq r15, r16, r17 ; ld2s r25, r26 ; shl2add r5, r6, r7 }
{ cmpeq r15, r16, r17 ; ld2u r25, r26 ; movei r5, 5 }
{ cmpeq r15, r16, r17 ; ld4s r25, r26 ; add r5, r6, r7 }
{ cmpeq r15, r16, r17 ; ld4s r25, r26 ; revbytes r5, r6 }
{ cmpeq r15, r16, r17 ; ld4u r25, r26 ; ctz r5, r6 }
{ cmpeq r15, r16, r17 ; ld4u r25, r26 ; tblidxb0 r5, r6 }
{ cmpeq r15, r16, r17 ; move r5, r6 ; st r25, r26 }
{ cmpeq r15, r16, r17 ; mul_hs_hs r5, r6, r7 ; st1 r25, r26 }
{ cmpeq r15, r16, r17 ; mul_ls_ls r5, r6, r7 ; prefetch_l3 r25 }
{ cmpeq r15, r16, r17 ; mula_hs_hs r5, r6, r7 ; prefetch_l3_fault r25 }
{ cmpeq r15, r16, r17 ; mula_ls_ls r5, r6, r7 ; prefetch_l2 r25 }
{ cmpeq r15, r16, r17 ; mulax r5, r6, r7 ; prefetch_l2_fault r25 }
{ cmpeq r15, r16, r17 ; mz r5, r6, r7 ; prefetch_l3_fault r25 }
{ cmpeq r15, r16, r17 ; nor r5, r6, r7 ; st1 r25, r26 }
{ cmpeq r15, r16, r17 ; pcnt r5, r6 ; st2 r25, r26 }
{ cmpeq r15, r16, r17 ; prefetch r25 ; or r5, r6, r7 }
{ cmpeq r15, r16, r17 ; prefetch_l1 r25 ; cmpltsi r5, r6, 5 }
{ cmpeq r15, r16, r17 ; prefetch_l1 r25 ; shrui r5, r6, 5 }
{ cmpeq r15, r16, r17 ; prefetch_l1_fault r25 ; mula_lu_lu r5, r6, r7 }
{ cmpeq r15, r16, r17 ; prefetch_l2 r25 ; cmovnez r5, r6, r7 }
{ cmpeq r15, r16, r17 ; prefetch_l2 r25 ; shl3add r5, r6, r7 }
{ cmpeq r15, r16, r17 ; prefetch_l2_fault r25 ; mul_hu_hu r5, r6, r7 }
{ cmpeq r15, r16, r17 ; prefetch_l3 r25 ; addx r5, r6, r7 }
{ cmpeq r15, r16, r17 ; prefetch_l3 r25 ; rotli r5, r6, 5 }
{ cmpeq r15, r16, r17 ; prefetch_l3_fault r25 ; fsingle_pack1 r5, r6 }
{ cmpeq r15, r16, r17 ; prefetch_l3_fault r25 ; tblidxb2 r5, r6 }
{ cmpeq r15, r16, r17 ; revbytes r5, r6 ; st4 r25, r26 }
{ cmpeq r15, r16, r17 ; shl r5, r6, r7 ; ld r25, r26 }
{ cmpeq r15, r16, r17 ; shl1addx r5, r6, r7 ; ld1s r25, r26 }
{ cmpeq r15, r16, r17 ; shl2addx r5, r6, r7 ; ld2s r25, r26 }
{ cmpeq r15, r16, r17 ; shl3addx r5, r6, r7 ; ld4s r25, r26 }
{ cmpeq r15, r16, r17 ; shrs r5, r6, r7 ; ld4s r25, r26 }
{ cmpeq r15, r16, r17 ; shru r5, r6, r7 ; prefetch r25 }
{ cmpeq r15, r16, r17 ; st r25, r26 ; clz r5, r6 }
{ cmpeq r15, r16, r17 ; st r25, r26 ; shl2add r5, r6, r7 }
{ cmpeq r15, r16, r17 ; st1 r25, r26 ; movei r5, 5 }
{ cmpeq r15, r16, r17 ; st2 r25, r26 ; add r5, r6, r7 }
{ cmpeq r15, r16, r17 ; st2 r25, r26 ; revbytes r5, r6 }
{ cmpeq r15, r16, r17 ; st4 r25, r26 ; ctz r5, r6 }
{ cmpeq r15, r16, r17 ; st4 r25, r26 ; tblidxb0 r5, r6 }
{ cmpeq r15, r16, r17 ; subx r5, r6, r7 ; st1 r25, r26 }
{ cmpeq r15, r16, r17 ; tblidxb1 r5, r6 ; st2 r25, r26 }
{ cmpeq r15, r16, r17 ; tblidxb3 r5, r6 }
{ cmpeq r15, r16, r17 ; v1shrs r5, r6, r7 }
{ cmpeq r15, r16, r17 ; v2shl r5, r6, r7 }
{ cmpeq r5, r6, r7 ; add r15, r16, r17 ; ld r25, r26 }
{ cmpeq r5, r6, r7 ; addx r15, r16, r17 ; ld1s r25, r26 }
{ cmpeq r5, r6, r7 ; and r15, r16, r17 ; ld1s r25, r26 }
{ cmpeq r5, r6, r7 ; cmpeq r15, r16, r17 ; ld2s r25, r26 }
{ cmpeq r5, r6, r7 ; cmples r15, r16, r17 ; ld2s r25, r26 }
{ cmpeq r5, r6, r7 ; cmplts r15, r16, r17 ; ld4s r25, r26 }
{ cmpeq r5, r6, r7 ; cmpltu r15, r16, r17 ; prefetch r25 }
{ cmpeq r5, r6, r7 ; fetchaddgez r15, r16, r17 }
{ cmpeq r5, r6, r7 ; ill ; prefetch_l2_fault r25 }
{ cmpeq r5, r6, r7 ; jalr r15 ; prefetch_l2 r25 }
{ cmpeq r5, r6, r7 ; jr r15 ; prefetch_l3 r25 }
{ cmpeq r5, r6, r7 ; ld r25, r26 ; cmpne r15, r16, r17 }
{ cmpeq r5, r6, r7 ; ld1s r25, r26 ; andi r15, r16, 5 }
{ cmpeq r5, r6, r7 ; ld1s r25, r26 ; xor r15, r16, r17 }
{ cmpeq r5, r6, r7 ; ld1u r25, r26 ; shl3add r15, r16, r17 }
{ cmpeq r5, r6, r7 ; ld2s r25, r26 ; nor r15, r16, r17 }
{ cmpeq r5, r6, r7 ; ld2u r25, r26 ; jalrp r15 }
{ cmpeq r5, r6, r7 ; ld4s r25, r26 ; cmpleu r15, r16, r17 }
{ cmpeq r5, r6, r7 ; ld4u r25, r26 ; add r15, r16, r17 }
{ cmpeq r5, r6, r7 ; ld4u r25, r26 ; shrsi r15, r16, 5 }
{ cmpeq r5, r6, r7 ; lnk r15 ; st1 r25, r26 }
{ cmpeq r5, r6, r7 ; move r15, r16 ; st1 r25, r26 }
{ cmpeq r5, r6, r7 ; mz r15, r16, r17 ; st1 r25, r26 }
{ cmpeq r5, r6, r7 ; nor r15, r16, r17 ; st4 r25, r26 }
{ cmpeq r5, r6, r7 ; prefetch r25 ; jalr r15 }
{ cmpeq r5, r6, r7 ; prefetch_l1 r25 ; addxi r15, r16, 5 }
{ cmpeq r5, r6, r7 ; prefetch_l1 r25 ; sub r15, r16, r17 }
{ cmpeq r5, r6, r7 ; prefetch_l1_fault r25 ; shl2addx r15, r16, r17 }
{ cmpeq r5, r6, r7 ; prefetch_l2 r25 ; nor r15, r16, r17 }
{ cmpeq r5, r6, r7 ; prefetch_l2_fault r25 ; jr r15 }
{ cmpeq r5, r6, r7 ; prefetch_l3 r25 ; cmpltsi r15, r16, 5 }
{ cmpeq r5, r6, r7 ; prefetch_l3_fault r25 ; addxi r15, r16, 5 }
{ cmpeq r5, r6, r7 ; prefetch_l3_fault r25 ; sub r15, r16, r17 }
{ cmpeq r5, r6, r7 ; rotli r15, r16, 5 ; st2 r25, r26 }
{ cmpeq r5, r6, r7 ; shl1add r15, r16, r17 ; st4 r25, r26 }
{ cmpeq r5, r6, r7 ; shl2addx r15, r16, r17 ; ld r25, r26 }
{ cmpeq r5, r6, r7 ; shl3addx r15, r16, r17 ; ld1u r25, r26 }
{ cmpeq r5, r6, r7 ; shrs r15, r16, r17 ; ld1u r25, r26 }
{ cmpeq r5, r6, r7 ; shru r15, r16, r17 ; ld2u r25, r26 }
{ cmpeq r5, r6, r7 ; st r25, r26 ; addxi r15, r16, 5 }
{ cmpeq r5, r6, r7 ; st r25, r26 ; sub r15, r16, r17 }
{ cmpeq r5, r6, r7 ; st1 r25, r26 ; shl2addx r15, r16, r17 }
{ cmpeq r5, r6, r7 ; st2 r25, r26 ; nop }
{ cmpeq r5, r6, r7 ; st4 r25, r26 ; jalr r15 }
{ cmpeq r5, r6, r7 ; sub r15, r16, r17 ; ld r25, r26 }
{ cmpeq r5, r6, r7 ; v1addi r15, r16, 5 }
{ cmpeq r5, r6, r7 ; v2int_l r15, r16, r17 }
{ cmpeq r5, r6, r7 ; xor r15, r16, r17 ; prefetch_l1_fault r25 }
{ cmpeqi r15, r16, 5 ; addi r5, r6, 5 ; prefetch_l2 r25 }
{ cmpeqi r15, r16, 5 ; addxi r5, r6, 5 ; prefetch_l2_fault r25 }
{ cmpeqi r15, r16, 5 ; andi r5, r6, 5 ; prefetch_l2_fault r25 }
{ cmpeqi r15, r16, 5 ; cmoveqz r5, r6, r7 ; prefetch_l2 r25 }
{ cmpeqi r15, r16, 5 ; cmpeq r5, r6, r7 ; prefetch_l3 r25 }
{ cmpeqi r15, r16, 5 ; cmples r5, r6, r7 ; st r25, r26 }
{ cmpeqi r15, r16, 5 ; cmplts r5, r6, r7 ; st2 r25, r26 }
{ cmpeqi r15, r16, 5 ; cmpltu r5, r6, r7 }
{ cmpeqi r15, r16, 5 ; ctz r5, r6 ; prefetch_l2 r25 }
{ cmpeqi r15, r16, 5 ; fsingle_add1 r5, r6, r7 }
{ cmpeqi r15, r16, 5 ; info 19 ; st1 r25, r26 }
{ cmpeqi r15, r16, 5 ; ld r25, r26 ; nop }
{ cmpeqi r15, r16, 5 ; ld1s r25, r26 ; cmpleu r5, r6, r7 }
{ cmpeqi r15, r16, 5 ; ld1s r25, r26 ; shrsi r5, r6, 5 }
{ cmpeqi r15, r16, 5 ; ld1u r25, r26 ; mula_hu_hu r5, r6, r7 }
{ cmpeqi r15, r16, 5 ; ld2s r25, r26 ; clz r5, r6 }
{ cmpeqi r15, r16, 5 ; ld2s r25, r26 ; shl2add r5, r6, r7 }
{ cmpeqi r15, r16, 5 ; ld2u r25, r26 ; movei r5, 5 }
{ cmpeqi r15, r16, 5 ; ld4s r25, r26 ; add r5, r6, r7 }
{ cmpeqi r15, r16, 5 ; ld4s r25, r26 ; revbytes r5, r6 }
{ cmpeqi r15, r16, 5 ; ld4u r25, r26 ; ctz r5, r6 }
{ cmpeqi r15, r16, 5 ; ld4u r25, r26 ; tblidxb0 r5, r6 }
{ cmpeqi r15, r16, 5 ; move r5, r6 ; st r25, r26 }
{ cmpeqi r15, r16, 5 ; mul_hs_hs r5, r6, r7 ; st1 r25, r26 }
{ cmpeqi r15, r16, 5 ; mul_ls_ls r5, r6, r7 ; prefetch_l3 r25 }
{ cmpeqi r15, r16, 5 ; mula_hs_hs r5, r6, r7 ; prefetch_l3_fault r25 }
{ cmpeqi r15, r16, 5 ; mula_ls_ls r5, r6, r7 ; prefetch_l2 r25 }
{ cmpeqi r15, r16, 5 ; mulax r5, r6, r7 ; prefetch_l2_fault r25 }
{ cmpeqi r15, r16, 5 ; mz r5, r6, r7 ; prefetch_l3_fault r25 }
{ cmpeqi r15, r16, 5 ; nor r5, r6, r7 ; st1 r25, r26 }
{ cmpeqi r15, r16, 5 ; pcnt r5, r6 ; st2 r25, r26 }
{ cmpeqi r15, r16, 5 ; prefetch r25 ; or r5, r6, r7 }
{ cmpeqi r15, r16, 5 ; prefetch_l1 r25 ; cmpltsi r5, r6, 5 }
{ cmpeqi r15, r16, 5 ; prefetch_l1 r25 ; shrui r5, r6, 5 }
{ cmpeqi r15, r16, 5 ; prefetch_l1_fault r25 ; mula_lu_lu r5, r6, r7 }
{ cmpeqi r15, r16, 5 ; prefetch_l2 r25 ; cmovnez r5, r6, r7 }
{ cmpeqi r15, r16, 5 ; prefetch_l2 r25 ; shl3add r5, r6, r7 }
{ cmpeqi r15, r16, 5 ; prefetch_l2_fault r25 ; mul_hu_hu r5, r6, r7 }
{ cmpeqi r15, r16, 5 ; prefetch_l3 r25 ; addx r5, r6, r7 }
{ cmpeqi r15, r16, 5 ; prefetch_l3 r25 ; rotli r5, r6, 5 }
{ cmpeqi r15, r16, 5 ; prefetch_l3_fault r25 ; fsingle_pack1 r5, r6 }
{ cmpeqi r15, r16, 5 ; prefetch_l3_fault r25 ; tblidxb2 r5, r6 }
{ cmpeqi r15, r16, 5 ; revbytes r5, r6 ; st4 r25, r26 }
{ cmpeqi r15, r16, 5 ; shl r5, r6, r7 ; ld r25, r26 }
{ cmpeqi r15, r16, 5 ; shl1addx r5, r6, r7 ; ld1s r25, r26 }
{ cmpeqi r15, r16, 5 ; shl2addx r5, r6, r7 ; ld2s r25, r26 }
{ cmpeqi r15, r16, 5 ; shl3addx r5, r6, r7 ; ld4s r25, r26 }
{ cmpeqi r15, r16, 5 ; shrs r5, r6, r7 ; ld4s r25, r26 }
{ cmpeqi r15, r16, 5 ; shru r5, r6, r7 ; prefetch r25 }
{ cmpeqi r15, r16, 5 ; st r25, r26 ; clz r5, r6 }
{ cmpeqi r15, r16, 5 ; st r25, r26 ; shl2add r5, r6, r7 }
{ cmpeqi r15, r16, 5 ; st1 r25, r26 ; movei r5, 5 }
{ cmpeqi r15, r16, 5 ; st2 r25, r26 ; add r5, r6, r7 }
{ cmpeqi r15, r16, 5 ; st2 r25, r26 ; revbytes r5, r6 }
{ cmpeqi r15, r16, 5 ; st4 r25, r26 ; ctz r5, r6 }
{ cmpeqi r15, r16, 5 ; st4 r25, r26 ; tblidxb0 r5, r6 }
{ cmpeqi r15, r16, 5 ; subx r5, r6, r7 ; st1 r25, r26 }
{ cmpeqi r15, r16, 5 ; tblidxb1 r5, r6 ; st2 r25, r26 }
{ cmpeqi r15, r16, 5 ; tblidxb3 r5, r6 }
{ cmpeqi r15, r16, 5 ; v1shrs r5, r6, r7 }
{ cmpeqi r15, r16, 5 ; v2shl r5, r6, r7 }
{ cmpeqi r5, r6, 5 ; add r15, r16, r17 ; ld r25, r26 }
{ cmpeqi r5, r6, 5 ; addx r15, r16, r17 ; ld1s r25, r26 }
{ cmpeqi r5, r6, 5 ; and r15, r16, r17 ; ld1s r25, r26 }
{ cmpeqi r5, r6, 5 ; cmpeq r15, r16, r17 ; ld2s r25, r26 }
{ cmpeqi r5, r6, 5 ; cmples r15, r16, r17 ; ld2s r25, r26 }
{ cmpeqi r5, r6, 5 ; cmplts r15, r16, r17 ; ld4s r25, r26 }
{ cmpeqi r5, r6, 5 ; cmpltu r15, r16, r17 ; prefetch r25 }
{ cmpeqi r5, r6, 5 ; fetchaddgez r15, r16, r17 }
{ cmpeqi r5, r6, 5 ; ill ; prefetch_l2_fault r25 }
{ cmpeqi r5, r6, 5 ; jalr r15 ; prefetch_l2 r25 }
{ cmpeqi r5, r6, 5 ; jr r15 ; prefetch_l3 r25 }
{ cmpeqi r5, r6, 5 ; ld r25, r26 ; cmpne r15, r16, r17 }
{ cmpeqi r5, r6, 5 ; ld1s r25, r26 ; andi r15, r16, 5 }
{ cmpeqi r5, r6, 5 ; ld1s r25, r26 ; xor r15, r16, r17 }
{ cmpeqi r5, r6, 5 ; ld1u r25, r26 ; shl3add r15, r16, r17 }
{ cmpeqi r5, r6, 5 ; ld2s r25, r26 ; nor r15, r16, r17 }
{ cmpeqi r5, r6, 5 ; ld2u r25, r26 ; jalrp r15 }
{ cmpeqi r5, r6, 5 ; ld4s r25, r26 ; cmpleu r15, r16, r17 }
{ cmpeqi r5, r6, 5 ; ld4u r25, r26 ; add r15, r16, r17 }
{ cmpeqi r5, r6, 5 ; ld4u r25, r26 ; shrsi r15, r16, 5 }
{ cmpeqi r5, r6, 5 ; lnk r15 ; st1 r25, r26 }
{ cmpeqi r5, r6, 5 ; move r15, r16 ; st1 r25, r26 }
{ cmpeqi r5, r6, 5 ; mz r15, r16, r17 ; st1 r25, r26 }
{ cmpeqi r5, r6, 5 ; nor r15, r16, r17 ; st4 r25, r26 }
{ cmpeqi r5, r6, 5 ; prefetch r25 ; jalr r15 }
{ cmpeqi r5, r6, 5 ; prefetch_l1 r25 ; addxi r15, r16, 5 }
{ cmpeqi r5, r6, 5 ; prefetch_l1 r25 ; sub r15, r16, r17 }
{ cmpeqi r5, r6, 5 ; prefetch_l1_fault r25 ; shl2addx r15, r16, r17 }
{ cmpeqi r5, r6, 5 ; prefetch_l2 r25 ; nor r15, r16, r17 }
{ cmpeqi r5, r6, 5 ; prefetch_l2_fault r25 ; jr r15 }
{ cmpeqi r5, r6, 5 ; prefetch_l3 r25 ; cmpltsi r15, r16, 5 }
{ cmpeqi r5, r6, 5 ; prefetch_l3_fault r25 ; addxi r15, r16, 5 }
{ cmpeqi r5, r6, 5 ; prefetch_l3_fault r25 ; sub r15, r16, r17 }
{ cmpeqi r5, r6, 5 ; rotli r15, r16, 5 ; st2 r25, r26 }
{ cmpeqi r5, r6, 5 ; shl1add r15, r16, r17 ; st4 r25, r26 }
{ cmpeqi r5, r6, 5 ; shl2addx r15, r16, r17 ; ld r25, r26 }
{ cmpeqi r5, r6, 5 ; shl3addx r15, r16, r17 ; ld1u r25, r26 }
{ cmpeqi r5, r6, 5 ; shrs r15, r16, r17 ; ld1u r25, r26 }
{ cmpeqi r5, r6, 5 ; shru r15, r16, r17 ; ld2u r25, r26 }
{ cmpeqi r5, r6, 5 ; st r25, r26 ; addxi r15, r16, 5 }
{ cmpeqi r5, r6, 5 ; st r25, r26 ; sub r15, r16, r17 }
{ cmpeqi r5, r6, 5 ; st1 r25, r26 ; shl2addx r15, r16, r17 }
{ cmpeqi r5, r6, 5 ; st2 r25, r26 ; nop }
{ cmpeqi r5, r6, 5 ; st4 r25, r26 ; jalr r15 }
{ cmpeqi r5, r6, 5 ; sub r15, r16, r17 ; ld r25, r26 }
{ cmpeqi r5, r6, 5 ; v1addi r15, r16, 5 }
{ cmpeqi r5, r6, 5 ; v2int_l r15, r16, r17 }
{ cmpeqi r5, r6, 5 ; xor r15, r16, r17 ; prefetch_l1_fault r25 }
{ cmpexch r15, r16, r17 ; cmulh r5, r6, r7 }
{ cmpexch r15, r16, r17 ; mul_ls_lu r5, r6, r7 }
{ cmpexch r15, r16, r17 ; shruxi r5, r6, 5 }
{ cmpexch r15, r16, r17 ; v1multu r5, r6, r7 }
{ cmpexch r15, r16, r17 ; v2mz r5, r6, r7 }
{ cmpexch4 r15, r16, r17 ; bfextu r5, r6, 5, 7 }
{ cmpexch4 r15, r16, r17 ; fsingle_mul2 r5, r6, r7 }
{ cmpexch4 r15, r16, r17 ; revbytes r5, r6 }
{ cmpexch4 r15, r16, r17 ; v1cmpltui r5, r6, 5 }
{ cmpexch4 r15, r16, r17 ; v2cmples r5, r6, r7 }
{ cmpexch4 r15, r16, r17 ; v4packsc r5, r6, r7 }
{ cmples r15, r16, r17 ; addi r5, r6, 5 ; prefetch_l3 r25 }
{ cmples r15, r16, r17 ; addxi r5, r6, 5 ; prefetch_l3_fault r25 }
{ cmples r15, r16, r17 ; andi r5, r6, 5 ; prefetch_l3_fault r25 }
{ cmples r15, r16, r17 ; cmoveqz r5, r6, r7 ; prefetch_l3 r25 }
{ cmples r15, r16, r17 ; cmpeq r5, r6, r7 ; st r25, r26 }
{ cmples r15, r16, r17 ; cmples r5, r6, r7 ; st2 r25, r26 }
{ cmples r15, r16, r17 ; cmplts r5, r6, r7 }
{ cmples r15, r16, r17 ; cmpne r5, r6, r7 ; ld r25, r26 }
{ cmples r15, r16, r17 ; ctz r5, r6 ; prefetch_l3 r25 }
{ cmples r15, r16, r17 ; fsingle_mul1 r5, r6, r7 }
{ cmples r15, r16, r17 ; info 19 ; st4 r25, r26 }
{ cmples r15, r16, r17 ; ld r25, r26 ; or r5, r6, r7 }
{ cmples r15, r16, r17 ; ld1s r25, r26 ; cmpltsi r5, r6, 5 }
{ cmples r15, r16, r17 ; ld1s r25, r26 ; shrui r5, r6, 5 }
{ cmples r15, r16, r17 ; ld1u r25, r26 ; mula_lu_lu r5, r6, r7 }
{ cmples r15, r16, r17 ; ld2s r25, r26 ; cmovnez r5, r6, r7 }
{ cmples r15, r16, r17 ; ld2s r25, r26 ; shl3add r5, r6, r7 }
{ cmples r15, r16, r17 ; ld2u r25, r26 ; mul_hu_hu r5, r6, r7 }
{ cmples r15, r16, r17 ; ld4s r25, r26 ; addx r5, r6, r7 }
{ cmples r15, r16, r17 ; ld4s r25, r26 ; rotli r5, r6, 5 }
{ cmples r15, r16, r17 ; ld4u r25, r26 ; fsingle_pack1 r5, r6 }
{ cmples r15, r16, r17 ; ld4u r25, r26 ; tblidxb2 r5, r6 }
{ cmples r15, r16, r17 ; move r5, r6 ; st2 r25, r26 }
{ cmples r15, r16, r17 ; mul_hs_hs r5, r6, r7 ; st4 r25, r26 }
{ cmples r15, r16, r17 ; mul_ls_ls r5, r6, r7 ; st r25, r26 }
{ cmples r15, r16, r17 ; mula_hs_hs r5, r6, r7 ; st1 r25, r26 }
{ cmples r15, r16, r17 ; mula_ls_ls r5, r6, r7 ; prefetch_l3 r25 }
{ cmples r15, r16, r17 ; mulax r5, r6, r7 ; prefetch_l3_fault r25 }
{ cmples r15, r16, r17 ; mz r5, r6, r7 ; st1 r25, r26 }
{ cmples r15, r16, r17 ; nor r5, r6, r7 ; st4 r25, r26 }
{ cmples r15, r16, r17 ; pcnt r5, r6 }
{ cmples r15, r16, r17 ; prefetch r25 ; revbits r5, r6 }
{ cmples r15, r16, r17 ; prefetch_l1 r25 ; cmpne r5, r6, r7 }
{ cmples r15, r16, r17 ; prefetch_l1 r25 ; subx r5, r6, r7 }
{ cmples r15, r16, r17 ; prefetch_l1_fault r25 ; mulx r5, r6, r7 }
{ cmples r15, r16, r17 ; prefetch_l2 r25 ; cmpeqi r5, r6, 5 }
{ cmples r15, r16, r17 ; prefetch_l2 r25 ; shli r5, r6, 5 }
{ cmples r15, r16, r17 ; prefetch_l2_fault r25 ; mul_lu_lu r5, r6, r7 }
{ cmples r15, r16, r17 ; prefetch_l3 r25 ; and r5, r6, r7 }
{ cmples r15, r16, r17 ; prefetch_l3 r25 ; shl1add r5, r6, r7 }
{ cmples r15, r16, r17 ; prefetch_l3_fault r25 ; mnz r5, r6, r7 }
{ cmples r15, r16, r17 ; prefetch_l3_fault r25 ; xor r5, r6, r7 }
{ cmples r15, r16, r17 ; rotl r5, r6, r7 ; ld r25, r26 }
{ cmples r15, r16, r17 ; shl r5, r6, r7 ; ld1u r25, r26 }
{ cmples r15, r16, r17 ; shl1addx r5, r6, r7 ; ld2s r25, r26 }
{ cmples r15, r16, r17 ; shl2addx r5, r6, r7 ; ld4s r25, r26 }
{ cmples r15, r16, r17 ; shl3addx r5, r6, r7 ; prefetch r25 }
{ cmples r15, r16, r17 ; shrs r5, r6, r7 ; prefetch r25 }
{ cmples r15, r16, r17 ; shru r5, r6, r7 ; prefetch_l1_fault r25 }
{ cmples r15, r16, r17 ; st r25, r26 ; cmovnez r5, r6, r7 }
{ cmples r15, r16, r17 ; st r25, r26 ; shl3add r5, r6, r7 }
{ cmples r15, r16, r17 ; st1 r25, r26 ; mul_hu_hu r5, r6, r7 }
{ cmples r15, r16, r17 ; st2 r25, r26 ; addx r5, r6, r7 }
{ cmples r15, r16, r17 ; st2 r25, r26 ; rotli r5, r6, 5 }
{ cmples r15, r16, r17 ; st4 r25, r26 ; fsingle_pack1 r5, r6 }
{ cmples r15, r16, r17 ; st4 r25, r26 ; tblidxb2 r5, r6 }
{ cmples r15, r16, r17 ; subx r5, r6, r7 ; st4 r25, r26 }
{ cmples r15, r16, r17 ; tblidxb1 r5, r6 }
{ cmples r15, r16, r17 ; v1addi r5, r6, 5 }
{ cmples r15, r16, r17 ; v1shru r5, r6, r7 }
{ cmples r15, r16, r17 ; v2shlsc r5, r6, r7 }
{ cmples r5, r6, r7 ; add r15, r16, r17 ; ld1u r25, r26 }
{ cmples r5, r6, r7 ; addx r15, r16, r17 ; ld2s r25, r26 }
{ cmples r5, r6, r7 ; and r15, r16, r17 ; ld2s r25, r26 }
{ cmples r5, r6, r7 ; cmpeq r15, r16, r17 ; ld4s r25, r26 }
{ cmples r5, r6, r7 ; cmples r15, r16, r17 ; ld4s r25, r26 }
{ cmples r5, r6, r7 ; cmplts r15, r16, r17 ; prefetch r25 }
{ cmples r5, r6, r7 ; cmpltu r15, r16, r17 ; prefetch_l1_fault r25 }
{ cmples r5, r6, r7 ; fetchand r15, r16, r17 }
{ cmples r5, r6, r7 ; ill ; prefetch_l3_fault r25 }
{ cmples r5, r6, r7 ; jalr r15 ; prefetch_l3 r25 }
{ cmples r5, r6, r7 ; jr r15 ; st r25, r26 }
{ cmples r5, r6, r7 ; ld r25, r26 ; ill }
{ cmples r5, r6, r7 ; ld1s r25, r26 ; cmpeqi r15, r16, 5 }
{ cmples r5, r6, r7 ; ld1s_add r15, r16, 5 }
{ cmples r5, r6, r7 ; ld1u r25, r26 ; shli r15, r16, 5 }
{ cmples r5, r6, r7 ; ld2s r25, r26 ; rotl r15, r16, r17 }
{ cmples r5, r6, r7 ; ld2u r25, r26 ; jrp r15 }
{ cmples r5, r6, r7 ; ld4s r25, r26 ; cmpltsi r15, r16, 5 }
{ cmples r5, r6, r7 ; ld4u r25, r26 ; addx r15, r16, r17 }
{ cmples r5, r6, r7 ; ld4u r25, r26 ; shrui r15, r16, 5 }
{ cmples r5, r6, r7 ; lnk r15 ; st4 r25, r26 }
{ cmples r5, r6, r7 ; move r15, r16 ; st4 r25, r26 }
{ cmples r5, r6, r7 ; mz r15, r16, r17 ; st4 r25, r26 }
{ cmples r5, r6, r7 ; or r15, r16, r17 ; ld r25, r26 }
{ cmples r5, r6, r7 ; prefetch r25 ; jr r15 }
{ cmples r5, r6, r7 ; prefetch_l1 r25 ; andi r15, r16, 5 }
{ cmples r5, r6, r7 ; prefetch_l1 r25 ; xor r15, r16, r17 }
{ cmples r5, r6, r7 ; prefetch_l1_fault r25 ; shl3addx r15, r16, r17 }
{ cmples r5, r6, r7 ; prefetch_l2 r25 ; rotl r15, r16, r17 }
{ cmples r5, r6, r7 ; prefetch_l2_fault r25 ; lnk r15 }
{ cmples r5, r6, r7 ; prefetch_l3 r25 ; cmpne r15, r16, r17 }
{ cmples r5, r6, r7 ; prefetch_l3_fault r25 ; andi r15, r16, 5 }
{ cmples r5, r6, r7 ; prefetch_l3_fault r25 ; xor r15, r16, r17 }
{ cmples r5, r6, r7 ; rotli r15, r16, 5 }
{ cmples r5, r6, r7 ; shl1addx r15, r16, r17 ; ld r25, r26 }
{ cmples r5, r6, r7 ; shl2addx r15, r16, r17 ; ld1u r25, r26 }
{ cmples r5, r6, r7 ; shl3addx r15, r16, r17 ; ld2u r25, r26 }
{ cmples r5, r6, r7 ; shrs r15, r16, r17 ; ld2u r25, r26 }
{ cmples r5, r6, r7 ; shru r15, r16, r17 ; ld4u r25, r26 }
{ cmples r5, r6, r7 ; st r25, r26 ; andi r15, r16, 5 }
{ cmples r5, r6, r7 ; st r25, r26 ; xor r15, r16, r17 }
{ cmples r5, r6, r7 ; st1 r25, r26 ; shl3addx r15, r16, r17 }
{ cmples r5, r6, r7 ; st2 r25, r26 ; or r15, r16, r17 }
{ cmples r5, r6, r7 ; st4 r25, r26 ; jr r15 }
{ cmples r5, r6, r7 ; sub r15, r16, r17 ; ld1u r25, r26 }
{ cmples r5, r6, r7 ; v1cmpeq r15, r16, r17 }
{ cmples r5, r6, r7 ; v2maxsi r15, r16, 5 }
{ cmples r5, r6, r7 ; xor r15, r16, r17 ; prefetch_l2_fault r25 }
{ cmpleu r15, r16, r17 ; addi r5, r6, 5 ; prefetch_l3 r25 }
{ cmpleu r15, r16, r17 ; addxi r5, r6, 5 ; prefetch_l3_fault r25 }
{ cmpleu r15, r16, r17 ; andi r5, r6, 5 ; prefetch_l3_fault r25 }
{ cmpleu r15, r16, r17 ; cmoveqz r5, r6, r7 ; prefetch_l3 r25 }
{ cmpleu r15, r16, r17 ; cmpeq r5, r6, r7 ; st r25, r26 }
{ cmpleu r15, r16, r17 ; cmples r5, r6, r7 ; st2 r25, r26 }
{ cmpleu r15, r16, r17 ; cmplts r5, r6, r7 }
{ cmpleu r15, r16, r17 ; cmpne r5, r6, r7 ; ld r25, r26 }
{ cmpleu r15, r16, r17 ; ctz r5, r6 ; prefetch_l3 r25 }
{ cmpleu r15, r16, r17 ; fsingle_mul1 r5, r6, r7 }
{ cmpleu r15, r16, r17 ; info 19 ; st4 r25, r26 }
{ cmpleu r15, r16, r17 ; ld r25, r26 ; or r5, r6, r7 }
{ cmpleu r15, r16, r17 ; ld1s r25, r26 ; cmpltsi r5, r6, 5 }
{ cmpleu r15, r16, r17 ; ld1s r25, r26 ; shrui r5, r6, 5 }
{ cmpleu r15, r16, r17 ; ld1u r25, r26 ; mula_lu_lu r5, r6, r7 }
{ cmpleu r15, r16, r17 ; ld2s r25, r26 ; cmovnez r5, r6, r7 }
{ cmpleu r15, r16, r17 ; ld2s r25, r26 ; shl3add r5, r6, r7 }
{ cmpleu r15, r16, r17 ; ld2u r25, r26 ; mul_hu_hu r5, r6, r7 }
{ cmpleu r15, r16, r17 ; ld4s r25, r26 ; addx r5, r6, r7 }
{ cmpleu r15, r16, r17 ; ld4s r25, r26 ; rotli r5, r6, 5 }
{ cmpleu r15, r16, r17 ; ld4u r25, r26 ; fsingle_pack1 r5, r6 }
{ cmpleu r15, r16, r17 ; ld4u r25, r26 ; tblidxb2 r5, r6 }
{ cmpleu r15, r16, r17 ; move r5, r6 ; st2 r25, r26 }
{ cmpleu r15, r16, r17 ; mul_hs_hs r5, r6, r7 ; st4 r25, r26 }
{ cmpleu r15, r16, r17 ; mul_ls_ls r5, r6, r7 ; st r25, r26 }
{ cmpleu r15, r16, r17 ; mula_hs_hs r5, r6, r7 ; st1 r25, r26 }
{ cmpleu r15, r16, r17 ; mula_ls_ls r5, r6, r7 ; prefetch_l3 r25 }
{ cmpleu r15, r16, r17 ; mulax r5, r6, r7 ; prefetch_l3_fault r25 }
{ cmpleu r15, r16, r17 ; mz r5, r6, r7 ; st1 r25, r26 }
{ cmpleu r15, r16, r17 ; nor r5, r6, r7 ; st4 r25, r26 }
{ cmpleu r15, r16, r17 ; pcnt r5, r6 }
{ cmpleu r15, r16, r17 ; prefetch r25 ; revbits r5, r6 }
{ cmpleu r15, r16, r17 ; prefetch_l1 r25 ; cmpne r5, r6, r7 }
{ cmpleu r15, r16, r17 ; prefetch_l1 r25 ; subx r5, r6, r7 }
{ cmpleu r15, r16, r17 ; prefetch_l1_fault r25 ; mulx r5, r6, r7 }
{ cmpleu r15, r16, r17 ; prefetch_l2 r25 ; cmpeqi r5, r6, 5 }
{ cmpleu r15, r16, r17 ; prefetch_l2 r25 ; shli r5, r6, 5 }
{ cmpleu r15, r16, r17 ; prefetch_l2_fault r25 ; mul_lu_lu r5, r6, r7 }
{ cmpleu r15, r16, r17 ; prefetch_l3 r25 ; and r5, r6, r7 }
{ cmpleu r15, r16, r17 ; prefetch_l3 r25 ; shl1add r5, r6, r7 }
{ cmpleu r15, r16, r17 ; prefetch_l3_fault r25 ; mnz r5, r6, r7 }
{ cmpleu r15, r16, r17 ; prefetch_l3_fault r25 ; xor r5, r6, r7 }
{ cmpleu r15, r16, r17 ; rotl r5, r6, r7 ; ld r25, r26 }
{ cmpleu r15, r16, r17 ; shl r5, r6, r7 ; ld1u r25, r26 }
{ cmpleu r15, r16, r17 ; shl1addx r5, r6, r7 ; ld2s r25, r26 }
{ cmpleu r15, r16, r17 ; shl2addx r5, r6, r7 ; ld4s r25, r26 }
{ cmpleu r15, r16, r17 ; shl3addx r5, r6, r7 ; prefetch r25 }
{ cmpleu r15, r16, r17 ; shrs r5, r6, r7 ; prefetch r25 }
{ cmpleu r15, r16, r17 ; shru r5, r6, r7 ; prefetch_l1_fault r25 }
{ cmpleu r15, r16, r17 ; st r25, r26 ; cmovnez r5, r6, r7 }
{ cmpleu r15, r16, r17 ; st r25, r26 ; shl3add r5, r6, r7 }
{ cmpleu r15, r16, r17 ; st1 r25, r26 ; mul_hu_hu r5, r6, r7 }
{ cmpleu r15, r16, r17 ; st2 r25, r26 ; addx r5, r6, r7 }
{ cmpleu r15, r16, r17 ; st2 r25, r26 ; rotli r5, r6, 5 }
{ cmpleu r15, r16, r17 ; st4 r25, r26 ; fsingle_pack1 r5, r6 }
{ cmpleu r15, r16, r17 ; st4 r25, r26 ; tblidxb2 r5, r6 }
{ cmpleu r15, r16, r17 ; subx r5, r6, r7 ; st4 r25, r26 }
{ cmpleu r15, r16, r17 ; tblidxb1 r5, r6 }
{ cmpleu r15, r16, r17 ; v1addi r5, r6, 5 }
{ cmpleu r15, r16, r17 ; v1shru r5, r6, r7 }
{ cmpleu r15, r16, r17 ; v2shlsc r5, r6, r7 }
{ cmpleu r5, r6, r7 ; add r15, r16, r17 ; ld1u r25, r26 }
{ cmpleu r5, r6, r7 ; addx r15, r16, r17 ; ld2s r25, r26 }
{ cmpleu r5, r6, r7 ; and r15, r16, r17 ; ld2s r25, r26 }
{ cmpleu r5, r6, r7 ; cmpeq r15, r16, r17 ; ld4s r25, r26 }
{ cmpleu r5, r6, r7 ; cmples r15, r16, r17 ; ld4s r25, r26 }
{ cmpleu r5, r6, r7 ; cmplts r15, r16, r17 ; prefetch r25 }
{ cmpleu r5, r6, r7 ; cmpltu r15, r16, r17 ; prefetch_l1_fault r25 }
{ cmpleu r5, r6, r7 ; fetchand r15, r16, r17 }
{ cmpleu r5, r6, r7 ; ill ; prefetch_l3_fault r25 }
{ cmpleu r5, r6, r7 ; jalr r15 ; prefetch_l3 r25 }
{ cmpleu r5, r6, r7 ; jr r15 ; st r25, r26 }
{ cmpleu r5, r6, r7 ; ld r25, r26 ; ill }
{ cmpleu r5, r6, r7 ; ld1s r25, r26 ; cmpeqi r15, r16, 5 }
{ cmpleu r5, r6, r7 ; ld1s_add r15, r16, 5 }
{ cmpleu r5, r6, r7 ; ld1u r25, r26 ; shli r15, r16, 5 }
{ cmpleu r5, r6, r7 ; ld2s r25, r26 ; rotl r15, r16, r17 }
{ cmpleu r5, r6, r7 ; ld2u r25, r26 ; jrp r15 }
{ cmpleu r5, r6, r7 ; ld4s r25, r26 ; cmpltsi r15, r16, 5 }
{ cmpleu r5, r6, r7 ; ld4u r25, r26 ; addx r15, r16, r17 }
{ cmpleu r5, r6, r7 ; ld4u r25, r26 ; shrui r15, r16, 5 }
{ cmpleu r5, r6, r7 ; lnk r15 ; st4 r25, r26 }
{ cmpleu r5, r6, r7 ; move r15, r16 ; st4 r25, r26 }
{ cmpleu r5, r6, r7 ; mz r15, r16, r17 ; st4 r25, r26 }
{ cmpleu r5, r6, r7 ; or r15, r16, r17 ; ld r25, r26 }
{ cmpleu r5, r6, r7 ; prefetch r25 ; jr r15 }
{ cmpleu r5, r6, r7 ; prefetch_l1 r25 ; andi r15, r16, 5 }
{ cmpleu r5, r6, r7 ; prefetch_l1 r25 ; xor r15, r16, r17 }
{ cmpleu r5, r6, r7 ; prefetch_l1_fault r25 ; shl3addx r15, r16, r17 }
{ cmpleu r5, r6, r7 ; prefetch_l2 r25 ; rotl r15, r16, r17 }
{ cmpleu r5, r6, r7 ; prefetch_l2_fault r25 ; lnk r15 }
{ cmpleu r5, r6, r7 ; prefetch_l3 r25 ; cmpne r15, r16, r17 }
{ cmpleu r5, r6, r7 ; prefetch_l3_fault r25 ; andi r15, r16, 5 }
{ cmpleu r5, r6, r7 ; prefetch_l3_fault r25 ; xor r15, r16, r17 }
{ cmpleu r5, r6, r7 ; rotli r15, r16, 5 }
{ cmpleu r5, r6, r7 ; shl1addx r15, r16, r17 ; ld r25, r26 }
{ cmpleu r5, r6, r7 ; shl2addx r15, r16, r17 ; ld1u r25, r26 }
{ cmpleu r5, r6, r7 ; shl3addx r15, r16, r17 ; ld2u r25, r26 }
{ cmpleu r5, r6, r7 ; shrs r15, r16, r17 ; ld2u r25, r26 }
{ cmpleu r5, r6, r7 ; shru r15, r16, r17 ; ld4u r25, r26 }
{ cmpleu r5, r6, r7 ; st r25, r26 ; andi r15, r16, 5 }
{ cmpleu r5, r6, r7 ; st r25, r26 ; xor r15, r16, r17 }
{ cmpleu r5, r6, r7 ; st1 r25, r26 ; shl3addx r15, r16, r17 }
{ cmpleu r5, r6, r7 ; st2 r25, r26 ; or r15, r16, r17 }
{ cmpleu r5, r6, r7 ; st4 r25, r26 ; jr r15 }
{ cmpleu r5, r6, r7 ; sub r15, r16, r17 ; ld1u r25, r26 }
{ cmpleu r5, r6, r7 ; v1cmpeq r15, r16, r17 }
{ cmpleu r5, r6, r7 ; v2maxsi r15, r16, 5 }
{ cmpleu r5, r6, r7 ; xor r15, r16, r17 ; prefetch_l2_fault r25 }
{ cmplts r15, r16, r17 ; addi r5, r6, 5 ; prefetch_l3 r25 }
{ cmplts r15, r16, r17 ; addxi r5, r6, 5 ; prefetch_l3_fault r25 }
{ cmplts r15, r16, r17 ; andi r5, r6, 5 ; prefetch_l3_fault r25 }
{ cmplts r15, r16, r17 ; cmoveqz r5, r6, r7 ; prefetch_l3 r25 }
{ cmplts r15, r16, r17 ; cmpeq r5, r6, r7 ; st r25, r26 }
{ cmplts r15, r16, r17 ; cmples r5, r6, r7 ; st2 r25, r26 }
{ cmplts r15, r16, r17 ; cmplts r5, r6, r7 }
{ cmplts r15, r16, r17 ; cmpne r5, r6, r7 ; ld r25, r26 }
{ cmplts r15, r16, r17 ; ctz r5, r6 ; prefetch_l3 r25 }
{ cmplts r15, r16, r17 ; fsingle_mul1 r5, r6, r7 }
{ cmplts r15, r16, r17 ; info 19 ; st4 r25, r26 }
{ cmplts r15, r16, r17 ; ld r25, r26 ; or r5, r6, r7 }
{ cmplts r15, r16, r17 ; ld1s r25, r26 ; cmpltsi r5, r6, 5 }
{ cmplts r15, r16, r17 ; ld1s r25, r26 ; shrui r5, r6, 5 }
{ cmplts r15, r16, r17 ; ld1u r25, r26 ; mula_lu_lu r5, r6, r7 }
{ cmplts r15, r16, r17 ; ld2s r25, r26 ; cmovnez r5, r6, r7 }
{ cmplts r15, r16, r17 ; ld2s r25, r26 ; shl3add r5, r6, r7 }
{ cmplts r15, r16, r17 ; ld2u r25, r26 ; mul_hu_hu r5, r6, r7 }
{ cmplts r15, r16, r17 ; ld4s r25, r26 ; addx r5, r6, r7 }
{ cmplts r15, r16, r17 ; ld4s r25, r26 ; rotli r5, r6, 5 }
{ cmplts r15, r16, r17 ; ld4u r25, r26 ; fsingle_pack1 r5, r6 }
{ cmplts r15, r16, r17 ; ld4u r25, r26 ; tblidxb2 r5, r6 }
{ cmplts r15, r16, r17 ; move r5, r6 ; st2 r25, r26 }
{ cmplts r15, r16, r17 ; mul_hs_hs r5, r6, r7 ; st4 r25, r26 }
{ cmplts r15, r16, r17 ; mul_ls_ls r5, r6, r7 ; st r25, r26 }
{ cmplts r15, r16, r17 ; mula_hs_hs r5, r6, r7 ; st1 r25, r26 }
{ cmplts r15, r16, r17 ; mula_ls_ls r5, r6, r7 ; prefetch_l3 r25 }
{ cmplts r15, r16, r17 ; mulax r5, r6, r7 ; prefetch_l3_fault r25 }
{ cmplts r15, r16, r17 ; mz r5, r6, r7 ; st1 r25, r26 }
{ cmplts r15, r16, r17 ; nor r5, r6, r7 ; st4 r25, r26 }
{ cmplts r15, r16, r17 ; pcnt r5, r6 }
{ cmplts r15, r16, r17 ; prefetch r25 ; revbits r5, r6 }
{ cmplts r15, r16, r17 ; prefetch_l1 r25 ; cmpne r5, r6, r7 }
{ cmplts r15, r16, r17 ; prefetch_l1 r25 ; subx r5, r6, r7 }
{ cmplts r15, r16, r17 ; prefetch_l1_fault r25 ; mulx r5, r6, r7 }
{ cmplts r15, r16, r17 ; prefetch_l2 r25 ; cmpeqi r5, r6, 5 }
{ cmplts r15, r16, r17 ; prefetch_l2 r25 ; shli r5, r6, 5 }
{ cmplts r15, r16, r17 ; prefetch_l2_fault r25 ; mul_lu_lu r5, r6, r7 }
{ cmplts r15, r16, r17 ; prefetch_l3 r25 ; and r5, r6, r7 }
{ cmplts r15, r16, r17 ; prefetch_l3 r25 ; shl1add r5, r6, r7 }
{ cmplts r15, r16, r17 ; prefetch_l3_fault r25 ; mnz r5, r6, r7 }
{ cmplts r15, r16, r17 ; prefetch_l3_fault r25 ; xor r5, r6, r7 }
{ cmplts r15, r16, r17 ; rotl r5, r6, r7 ; ld r25, r26 }
{ cmplts r15, r16, r17 ; shl r5, r6, r7 ; ld1u r25, r26 }
{ cmplts r15, r16, r17 ; shl1addx r5, r6, r7 ; ld2s r25, r26 }
{ cmplts r15, r16, r17 ; shl2addx r5, r6, r7 ; ld4s r25, r26 }
{ cmplts r15, r16, r17 ; shl3addx r5, r6, r7 ; prefetch r25 }
{ cmplts r15, r16, r17 ; shrs r5, r6, r7 ; prefetch r25 }
{ cmplts r15, r16, r17 ; shru r5, r6, r7 ; prefetch_l1_fault r25 }
{ cmplts r15, r16, r17 ; st r25, r26 ; cmovnez r5, r6, r7 }
{ cmplts r15, r16, r17 ; st r25, r26 ; shl3add r5, r6, r7 }
{ cmplts r15, r16, r17 ; st1 r25, r26 ; mul_hu_hu r5, r6, r7 }
{ cmplts r15, r16, r17 ; st2 r25, r26 ; addx r5, r6, r7 }
{ cmplts r15, r16, r17 ; st2 r25, r26 ; rotli r5, r6, 5 }
{ cmplts r15, r16, r17 ; st4 r25, r26 ; fsingle_pack1 r5, r6 }
{ cmplts r15, r16, r17 ; st4 r25, r26 ; tblidxb2 r5, r6 }
{ cmplts r15, r16, r17 ; subx r5, r6, r7 ; st4 r25, r26 }
{ cmplts r15, r16, r17 ; tblidxb1 r5, r6 }
{ cmplts r15, r16, r17 ; v1addi r5, r6, 5 }
{ cmplts r15, r16, r17 ; v1shru r5, r6, r7 }
{ cmplts r15, r16, r17 ; v2shlsc r5, r6, r7 }
{ cmplts r5, r6, r7 ; add r15, r16, r17 ; ld1u r25, r26 }
{ cmplts r5, r6, r7 ; addx r15, r16, r17 ; ld2s r25, r26 }
{ cmplts r5, r6, r7 ; and r15, r16, r17 ; ld2s r25, r26 }
{ cmplts r5, r6, r7 ; cmpeq r15, r16, r17 ; ld4s r25, r26 }
{ cmplts r5, r6, r7 ; cmples r15, r16, r17 ; ld4s r25, r26 }
{ cmplts r5, r6, r7 ; cmplts r15, r16, r17 ; prefetch r25 }
{ cmplts r5, r6, r7 ; cmpltu r15, r16, r17 ; prefetch_l1_fault r25 }
{ cmplts r5, r6, r7 ; fetchand r15, r16, r17 }
{ cmplts r5, r6, r7 ; ill ; prefetch_l3_fault r25 }
{ cmplts r5, r6, r7 ; jalr r15 ; prefetch_l3 r25 }
{ cmplts r5, r6, r7 ; jr r15 ; st r25, r26 }
{ cmplts r5, r6, r7 ; ld r25, r26 ; ill }
{ cmplts r5, r6, r7 ; ld1s r25, r26 ; cmpeqi r15, r16, 5 }
{ cmplts r5, r6, r7 ; ld1s_add r15, r16, 5 }
{ cmplts r5, r6, r7 ; ld1u r25, r26 ; shli r15, r16, 5 }
{ cmplts r5, r6, r7 ; ld2s r25, r26 ; rotl r15, r16, r17 }
{ cmplts r5, r6, r7 ; ld2u r25, r26 ; jrp r15 }
{ cmplts r5, r6, r7 ; ld4s r25, r26 ; cmpltsi r15, r16, 5 }
{ cmplts r5, r6, r7 ; ld4u r25, r26 ; addx r15, r16, r17 }
{ cmplts r5, r6, r7 ; ld4u r25, r26 ; shrui r15, r16, 5 }
{ cmplts r5, r6, r7 ; lnk r15 ; st4 r25, r26 }
{ cmplts r5, r6, r7 ; move r15, r16 ; st4 r25, r26 }
{ cmplts r5, r6, r7 ; mz r15, r16, r17 ; st4 r25, r26 }
{ cmplts r5, r6, r7 ; or r15, r16, r17 ; ld r25, r26 }
{ cmplts r5, r6, r7 ; prefetch r25 ; jr r15 }
{ cmplts r5, r6, r7 ; prefetch_l1 r25 ; andi r15, r16, 5 }
{ cmplts r5, r6, r7 ; prefetch_l1 r25 ; xor r15, r16, r17 }
{ cmplts r5, r6, r7 ; prefetch_l1_fault r25 ; shl3addx r15, r16, r17 }
{ cmplts r5, r6, r7 ; prefetch_l2 r25 ; rotl r15, r16, r17 }
{ cmplts r5, r6, r7 ; prefetch_l2_fault r25 ; lnk r15 }
{ cmplts r5, r6, r7 ; prefetch_l3 r25 ; cmpne r15, r16, r17 }
{ cmplts r5, r6, r7 ; prefetch_l3_fault r25 ; andi r15, r16, 5 }
{ cmplts r5, r6, r7 ; prefetch_l3_fault r25 ; xor r15, r16, r17 }
{ cmplts r5, r6, r7 ; rotli r15, r16, 5 }
{ cmplts r5, r6, r7 ; shl1addx r15, r16, r17 ; ld r25, r26 }
{ cmplts r5, r6, r7 ; shl2addx r15, r16, r17 ; ld1u r25, r26 }
{ cmplts r5, r6, r7 ; shl3addx r15, r16, r17 ; ld2u r25, r26 }
{ cmplts r5, r6, r7 ; shrs r15, r16, r17 ; ld2u r25, r26 }
{ cmplts r5, r6, r7 ; shru r15, r16, r17 ; ld4u r25, r26 }
{ cmplts r5, r6, r7 ; st r25, r26 ; andi r15, r16, 5 }
{ cmplts r5, r6, r7 ; st r25, r26 ; xor r15, r16, r17 }
{ cmplts r5, r6, r7 ; st1 r25, r26 ; shl3addx r15, r16, r17 }
{ cmplts r5, r6, r7 ; st2 r25, r26 ; or r15, r16, r17 }
{ cmplts r5, r6, r7 ; st4 r25, r26 ; jr r15 }
{ cmplts r5, r6, r7 ; sub r15, r16, r17 ; ld1u r25, r26 }
{ cmplts r5, r6, r7 ; v1cmpeq r15, r16, r17 }
{ cmplts r5, r6, r7 ; v2maxsi r15, r16, 5 }
{ cmplts r5, r6, r7 ; xor r15, r16, r17 ; prefetch_l2_fault r25 }
{ cmpltsi r15, r16, 5 ; addi r5, r6, 5 ; prefetch_l3 r25 }
{ cmpltsi r15, r16, 5 ; addxi r5, r6, 5 ; prefetch_l3_fault r25 }
{ cmpltsi r15, r16, 5 ; andi r5, r6, 5 ; prefetch_l3_fault r25 }
{ cmpltsi r15, r16, 5 ; cmoveqz r5, r6, r7 ; prefetch_l3 r25 }
{ cmpltsi r15, r16, 5 ; cmpeq r5, r6, r7 ; st r25, r26 }
{ cmpltsi r15, r16, 5 ; cmples r5, r6, r7 ; st2 r25, r26 }
{ cmpltsi r15, r16, 5 ; cmplts r5, r6, r7 }
{ cmpltsi r15, r16, 5 ; cmpne r5, r6, r7 ; ld r25, r26 }
{ cmpltsi r15, r16, 5 ; ctz r5, r6 ; prefetch_l3 r25 }
{ cmpltsi r15, r16, 5 ; fsingle_mul1 r5, r6, r7 }
{ cmpltsi r15, r16, 5 ; info 19 ; st4 r25, r26 }
{ cmpltsi r15, r16, 5 ; ld r25, r26 ; or r5, r6, r7 }
{ cmpltsi r15, r16, 5 ; ld1s r25, r26 ; cmpltsi r5, r6, 5 }
{ cmpltsi r15, r16, 5 ; ld1s r25, r26 ; shrui r5, r6, 5 }
{ cmpltsi r15, r16, 5 ; ld1u r25, r26 ; mula_lu_lu r5, r6, r7 }
{ cmpltsi r15, r16, 5 ; ld2s r25, r26 ; cmovnez r5, r6, r7 }
{ cmpltsi r15, r16, 5 ; ld2s r25, r26 ; shl3add r5, r6, r7 }
{ cmpltsi r15, r16, 5 ; ld2u r25, r26 ; mul_hu_hu r5, r6, r7 }
{ cmpltsi r15, r16, 5 ; ld4s r25, r26 ; addx r5, r6, r7 }
{ cmpltsi r15, r16, 5 ; ld4s r25, r26 ; rotli r5, r6, 5 }
{ cmpltsi r15, r16, 5 ; ld4u r25, r26 ; fsingle_pack1 r5, r6 }
{ cmpltsi r15, r16, 5 ; ld4u r25, r26 ; tblidxb2 r5, r6 }
{ cmpltsi r15, r16, 5 ; move r5, r6 ; st2 r25, r26 }
{ cmpltsi r15, r16, 5 ; mul_hs_hs r5, r6, r7 ; st4 r25, r26 }
{ cmpltsi r15, r16, 5 ; mul_ls_ls r5, r6, r7 ; st r25, r26 }
{ cmpltsi r15, r16, 5 ; mula_hs_hs r5, r6, r7 ; st1 r25, r26 }
{ cmpltsi r15, r16, 5 ; mula_ls_ls r5, r6, r7 ; prefetch_l3 r25 }
{ cmpltsi r15, r16, 5 ; mulax r5, r6, r7 ; prefetch_l3_fault r25 }
{ cmpltsi r15, r16, 5 ; mz r5, r6, r7 ; st1 r25, r26 }
{ cmpltsi r15, r16, 5 ; nor r5, r6, r7 ; st4 r25, r26 }
{ cmpltsi r15, r16, 5 ; pcnt r5, r6 }
{ cmpltsi r15, r16, 5 ; prefetch r25 ; revbits r5, r6 }
{ cmpltsi r15, r16, 5 ; prefetch_l1 r25 ; cmpne r5, r6, r7 }
{ cmpltsi r15, r16, 5 ; prefetch_l1 r25 ; subx r5, r6, r7 }
{ cmpltsi r15, r16, 5 ; prefetch_l1_fault r25 ; mulx r5, r6, r7 }
{ cmpltsi r15, r16, 5 ; prefetch_l2 r25 ; cmpeqi r5, r6, 5 }
{ cmpltsi r15, r16, 5 ; prefetch_l2 r25 ; shli r5, r6, 5 }
{ cmpltsi r15, r16, 5 ; prefetch_l2_fault r25 ; mul_lu_lu r5, r6, r7 }
{ cmpltsi r15, r16, 5 ; prefetch_l3 r25 ; and r5, r6, r7 }
{ cmpltsi r15, r16, 5 ; prefetch_l3 r25 ; shl1add r5, r6, r7 }
{ cmpltsi r15, r16, 5 ; prefetch_l3_fault r25 ; mnz r5, r6, r7 }
{ cmpltsi r15, r16, 5 ; prefetch_l3_fault r25 ; xor r5, r6, r7 }
{ cmpltsi r15, r16, 5 ; rotl r5, r6, r7 ; ld r25, r26 }
{ cmpltsi r15, r16, 5 ; shl r5, r6, r7 ; ld1u r25, r26 }
{ cmpltsi r15, r16, 5 ; shl1addx r5, r6, r7 ; ld2s r25, r26 }
{ cmpltsi r15, r16, 5 ; shl2addx r5, r6, r7 ; ld4s r25, r26 }
{ cmpltsi r15, r16, 5 ; shl3addx r5, r6, r7 ; prefetch r25 }
{ cmpltsi r15, r16, 5 ; shrs r5, r6, r7 ; prefetch r25 }
{ cmpltsi r15, r16, 5 ; shru r5, r6, r7 ; prefetch_l1_fault r25 }
{ cmpltsi r15, r16, 5 ; st r25, r26 ; cmovnez r5, r6, r7 }
{ cmpltsi r15, r16, 5 ; st r25, r26 ; shl3add r5, r6, r7 }
{ cmpltsi r15, r16, 5 ; st1 r25, r26 ; mul_hu_hu r5, r6, r7 }
{ cmpltsi r15, r16, 5 ; st2 r25, r26 ; addx r5, r6, r7 }
{ cmpltsi r15, r16, 5 ; st2 r25, r26 ; rotli r5, r6, 5 }
{ cmpltsi r15, r16, 5 ; st4 r25, r26 ; fsingle_pack1 r5, r6 }
{ cmpltsi r15, r16, 5 ; st4 r25, r26 ; tblidxb2 r5, r6 }
{ cmpltsi r15, r16, 5 ; subx r5, r6, r7 ; st4 r25, r26 }
{ cmpltsi r15, r16, 5 ; tblidxb1 r5, r6 }
{ cmpltsi r15, r16, 5 ; v1addi r5, r6, 5 }
{ cmpltsi r15, r16, 5 ; v1shru r5, r6, r7 }
{ cmpltsi r15, r16, 5 ; v2shlsc r5, r6, r7 }
{ cmpltsi r5, r6, 5 ; add r15, r16, r17 ; ld1u r25, r26 }
{ cmpltsi r5, r6, 5 ; addx r15, r16, r17 ; ld2s r25, r26 }
{ cmpltsi r5, r6, 5 ; and r15, r16, r17 ; ld2s r25, r26 }
{ cmpltsi r5, r6, 5 ; cmpeq r15, r16, r17 ; ld4s r25, r26 }
{ cmpltsi r5, r6, 5 ; cmples r15, r16, r17 ; ld4s r25, r26 }
{ cmpltsi r5, r6, 5 ; cmplts r15, r16, r17 ; prefetch r25 }
{ cmpltsi r5, r6, 5 ; cmpltu r15, r16, r17 ; prefetch_l1_fault r25 }
{ cmpltsi r5, r6, 5 ; fetchand r15, r16, r17 }
{ cmpltsi r5, r6, 5 ; ill ; prefetch_l3_fault r25 }
{ cmpltsi r5, r6, 5 ; jalr r15 ; prefetch_l3 r25 }
{ cmpltsi r5, r6, 5 ; jr r15 ; st r25, r26 }
{ cmpltsi r5, r6, 5 ; ld r25, r26 ; ill }
{ cmpltsi r5, r6, 5 ; ld1s r25, r26 ; cmpeqi r15, r16, 5 }
{ cmpltsi r5, r6, 5 ; ld1s_add r15, r16, 5 }
{ cmpltsi r5, r6, 5 ; ld1u r25, r26 ; shli r15, r16, 5 }
{ cmpltsi r5, r6, 5 ; ld2s r25, r26 ; rotl r15, r16, r17 }
{ cmpltsi r5, r6, 5 ; ld2u r25, r26 ; jrp r15 }
{ cmpltsi r5, r6, 5 ; ld4s r25, r26 ; cmpltsi r15, r16, 5 }
{ cmpltsi r5, r6, 5 ; ld4u r25, r26 ; addx r15, r16, r17 }
{ cmpltsi r5, r6, 5 ; ld4u r25, r26 ; shrui r15, r16, 5 }
{ cmpltsi r5, r6, 5 ; lnk r15 ; st4 r25, r26 }
{ cmpltsi r5, r6, 5 ; move r15, r16 ; st4 r25, r26 }
{ cmpltsi r5, r6, 5 ; mz r15, r16, r17 ; st4 r25, r26 }
{ cmpltsi r5, r6, 5 ; or r15, r16, r17 ; ld r25, r26 }
{ cmpltsi r5, r6, 5 ; prefetch r25 ; jr r15 }
{ cmpltsi r5, r6, 5 ; prefetch_l1 r25 ; andi r15, r16, 5 }
{ cmpltsi r5, r6, 5 ; prefetch_l1 r25 ; xor r15, r16, r17 }
{ cmpltsi r5, r6, 5 ; prefetch_l1_fault r25 ; shl3addx r15, r16, r17 }
{ cmpltsi r5, r6, 5 ; prefetch_l2 r25 ; rotl r15, r16, r17 }
{ cmpltsi r5, r6, 5 ; prefetch_l2_fault r25 ; lnk r15 }
{ cmpltsi r5, r6, 5 ; prefetch_l3 r25 ; cmpne r15, r16, r17 }
{ cmpltsi r5, r6, 5 ; prefetch_l3_fault r25 ; andi r15, r16, 5 }
{ cmpltsi r5, r6, 5 ; prefetch_l3_fault r25 ; xor r15, r16, r17 }
{ cmpltsi r5, r6, 5 ; rotli r15, r16, 5 }
{ cmpltsi r5, r6, 5 ; shl1addx r15, r16, r17 ; ld r25, r26 }
{ cmpltsi r5, r6, 5 ; shl2addx r15, r16, r17 ; ld1u r25, r26 }
{ cmpltsi r5, r6, 5 ; shl3addx r15, r16, r17 ; ld2u r25, r26 }
{ cmpltsi r5, r6, 5 ; shrs r15, r16, r17 ; ld2u r25, r26 }
{ cmpltsi r5, r6, 5 ; shru r15, r16, r17 ; ld4u r25, r26 }
{ cmpltsi r5, r6, 5 ; st r25, r26 ; andi r15, r16, 5 }
{ cmpltsi r5, r6, 5 ; st r25, r26 ; xor r15, r16, r17 }
{ cmpltsi r5, r6, 5 ; st1 r25, r26 ; shl3addx r15, r16, r17 }
{ cmpltsi r5, r6, 5 ; st2 r25, r26 ; or r15, r16, r17 }
{ cmpltsi r5, r6, 5 ; st4 r25, r26 ; jr r15 }
{ cmpltsi r5, r6, 5 ; sub r15, r16, r17 ; ld1u r25, r26 }
{ cmpltsi r5, r6, 5 ; v1cmpeq r15, r16, r17 }
{ cmpltsi r5, r6, 5 ; v2maxsi r15, r16, 5 }
{ cmpltsi r5, r6, 5 ; xor r15, r16, r17 ; prefetch_l2_fault r25 }
{ cmpltu r15, r16, r17 ; addi r5, r6, 5 ; prefetch_l3 r25 }
{ cmpltu r15, r16, r17 ; addxi r5, r6, 5 ; prefetch_l3_fault r25 }
{ cmpltu r15, r16, r17 ; andi r5, r6, 5 ; prefetch_l3_fault r25 }
{ cmpltu r15, r16, r17 ; cmoveqz r5, r6, r7 ; prefetch_l3 r25 }
{ cmpltu r15, r16, r17 ; cmpeq r5, r6, r7 ; st r25, r26 }
{ cmpltu r15, r16, r17 ; cmples r5, r6, r7 ; st2 r25, r26 }
{ cmpltu r15, r16, r17 ; cmplts r5, r6, r7 }
{ cmpltu r15, r16, r17 ; cmpne r5, r6, r7 ; ld r25, r26 }
{ cmpltu r15, r16, r17 ; ctz r5, r6 ; prefetch_l3 r25 }
{ cmpltu r15, r16, r17 ; fsingle_mul1 r5, r6, r7 }
{ cmpltu r15, r16, r17 ; info 19 ; st4 r25, r26 }
{ cmpltu r15, r16, r17 ; ld r25, r26 ; or r5, r6, r7 }
{ cmpltu r15, r16, r17 ; ld1s r25, r26 ; cmpltsi r5, r6, 5 }
{ cmpltu r15, r16, r17 ; ld1s r25, r26 ; shrui r5, r6, 5 }
{ cmpltu r15, r16, r17 ; ld1u r25, r26 ; mula_lu_lu r5, r6, r7 }
{ cmpltu r15, r16, r17 ; ld2s r25, r26 ; cmovnez r5, r6, r7 }
{ cmpltu r15, r16, r17 ; ld2s r25, r26 ; shl3add r5, r6, r7 }
{ cmpltu r15, r16, r17 ; ld2u r25, r26 ; mul_hu_hu r5, r6, r7 }
{ cmpltu r15, r16, r17 ; ld4s r25, r26 ; addx r5, r6, r7 }
{ cmpltu r15, r16, r17 ; ld4s r25, r26 ; rotli r5, r6, 5 }
{ cmpltu r15, r16, r17 ; ld4u r25, r26 ; fsingle_pack1 r5, r6 }
{ cmpltu r15, r16, r17 ; ld4u r25, r26 ; tblidxb2 r5, r6 }
{ cmpltu r15, r16, r17 ; move r5, r6 ; st2 r25, r26 }
{ cmpltu r15, r16, r17 ; mul_hs_hs r5, r6, r7 ; st4 r25, r26 }
{ cmpltu r15, r16, r17 ; mul_ls_ls r5, r6, r7 ; st r25, r26 }
{ cmpltu r15, r16, r17 ; mula_hs_hs r5, r6, r7 ; st1 r25, r26 }
{ cmpltu r15, r16, r17 ; mula_ls_ls r5, r6, r7 ; prefetch_l3 r25 }
{ cmpltu r15, r16, r17 ; mulax r5, r6, r7 ; prefetch_l3_fault r25 }
{ cmpltu r15, r16, r17 ; mz r5, r6, r7 ; st1 r25, r26 }
{ cmpltu r15, r16, r17 ; nor r5, r6, r7 ; st4 r25, r26 }
{ cmpltu r15, r16, r17 ; pcnt r5, r6 }
{ cmpltu r15, r16, r17 ; prefetch r25 ; revbits r5, r6 }
{ cmpltu r15, r16, r17 ; prefetch_l1 r25 ; cmpne r5, r6, r7 }
{ cmpltu r15, r16, r17 ; prefetch_l1 r25 ; subx r5, r6, r7 }
{ cmpltu r15, r16, r17 ; prefetch_l1_fault r25 ; mulx r5, r6, r7 }
{ cmpltu r15, r16, r17 ; prefetch_l2 r25 ; cmpeqi r5, r6, 5 }
{ cmpltu r15, r16, r17 ; prefetch_l2 r25 ; shli r5, r6, 5 }
{ cmpltu r15, r16, r17 ; prefetch_l2_fault r25 ; mul_lu_lu r5, r6, r7 }
{ cmpltu r15, r16, r17 ; prefetch_l3 r25 ; and r5, r6, r7 }
{ cmpltu r15, r16, r17 ; prefetch_l3 r25 ; shl1add r5, r6, r7 }
{ cmpltu r15, r16, r17 ; prefetch_l3_fault r25 ; mnz r5, r6, r7 }
{ cmpltu r15, r16, r17 ; prefetch_l3_fault r25 ; xor r5, r6, r7 }
{ cmpltu r15, r16, r17 ; rotl r5, r6, r7 ; ld r25, r26 }
{ cmpltu r15, r16, r17 ; shl r5, r6, r7 ; ld1u r25, r26 }
{ cmpltu r15, r16, r17 ; shl1addx r5, r6, r7 ; ld2s r25, r26 }
{ cmpltu r15, r16, r17 ; shl2addx r5, r6, r7 ; ld4s r25, r26 }
{ cmpltu r15, r16, r17 ; shl3addx r5, r6, r7 ; prefetch r25 }
{ cmpltu r15, r16, r17 ; shrs r5, r6, r7 ; prefetch r25 }
{ cmpltu r15, r16, r17 ; shru r5, r6, r7 ; prefetch_l1_fault r25 }
{ cmpltu r15, r16, r17 ; st r25, r26 ; cmovnez r5, r6, r7 }
{ cmpltu r15, r16, r17 ; st r25, r26 ; shl3add r5, r6, r7 }
{ cmpltu r15, r16, r17 ; st1 r25, r26 ; mul_hu_hu r5, r6, r7 }
{ cmpltu r15, r16, r17 ; st2 r25, r26 ; addx r5, r6, r7 }
{ cmpltu r15, r16, r17 ; st2 r25, r26 ; rotli r5, r6, 5 }
{ cmpltu r15, r16, r17 ; st4 r25, r26 ; fsingle_pack1 r5, r6 }
{ cmpltu r15, r16, r17 ; st4 r25, r26 ; tblidxb2 r5, r6 }
{ cmpltu r15, r16, r17 ; subx r5, r6, r7 ; st4 r25, r26 }
{ cmpltu r15, r16, r17 ; tblidxb1 r5, r6 }
{ cmpltu r15, r16, r17 ; v1addi r5, r6, 5 }
{ cmpltu r15, r16, r17 ; v1shru r5, r6, r7 }
{ cmpltu r15, r16, r17 ; v2shlsc r5, r6, r7 }
{ cmpltu r5, r6, r7 ; add r15, r16, r17 ; ld1u r25, r26 }
{ cmpltu r5, r6, r7 ; addx r15, r16, r17 ; ld2s r25, r26 }
{ cmpltu r5, r6, r7 ; and r15, r16, r17 ; ld2s r25, r26 }
{ cmpltu r5, r6, r7 ; cmpeq r15, r16, r17 ; ld4s r25, r26 }
{ cmpltu r5, r6, r7 ; cmples r15, r16, r17 ; ld4s r25, r26 }
{ cmpltu r5, r6, r7 ; cmplts r15, r16, r17 ; prefetch r25 }
{ cmpltu r5, r6, r7 ; cmpltu r15, r16, r17 ; prefetch_l1_fault r25 }
{ cmpltu r5, r6, r7 ; fetchand r15, r16, r17 }
{ cmpltu r5, r6, r7 ; ill ; prefetch_l3_fault r25 }
{ cmpltu r5, r6, r7 ; jalr r15 ; prefetch_l3 r25 }
{ cmpltu r5, r6, r7 ; jr r15 ; st r25, r26 }
{ cmpltu r5, r6, r7 ; ld r25, r26 ; ill }
{ cmpltu r5, r6, r7 ; ld1s r25, r26 ; cmpeqi r15, r16, 5 }
{ cmpltu r5, r6, r7 ; ld1s_add r15, r16, 5 }
{ cmpltu r5, r6, r7 ; ld1u r25, r26 ; shli r15, r16, 5 }
{ cmpltu r5, r6, r7 ; ld2s r25, r26 ; rotl r15, r16, r17 }
{ cmpltu r5, r6, r7 ; ld2u r25, r26 ; jrp r15 }
{ cmpltu r5, r6, r7 ; ld4s r25, r26 ; cmpltsi r15, r16, 5 }
{ cmpltu r5, r6, r7 ; ld4u r25, r26 ; addx r15, r16, r17 }
{ cmpltu r5, r6, r7 ; ld4u r25, r26 ; shrui r15, r16, 5 }
{ cmpltu r5, r6, r7 ; lnk r15 ; st4 r25, r26 }
{ cmpltu r5, r6, r7 ; move r15, r16 ; st4 r25, r26 }
{ cmpltu r5, r6, r7 ; mz r15, r16, r17 ; st4 r25, r26 }
{ cmpltu r5, r6, r7 ; or r15, r16, r17 ; ld r25, r26 }
{ cmpltu r5, r6, r7 ; prefetch r25 ; jr r15 }
{ cmpltu r5, r6, r7 ; prefetch_l1 r25 ; andi r15, r16, 5 }
{ cmpltu r5, r6, r7 ; prefetch_l1 r25 ; xor r15, r16, r17 }
{ cmpltu r5, r6, r7 ; prefetch_l1_fault r25 ; shl3addx r15, r16, r17 }
{ cmpltu r5, r6, r7 ; prefetch_l2 r25 ; rotl r15, r16, r17 }
{ cmpltu r5, r6, r7 ; prefetch_l2_fault r25 ; lnk r15 }
{ cmpltu r5, r6, r7 ; prefetch_l3 r25 ; cmpne r15, r16, r17 }
{ cmpltu r5, r6, r7 ; prefetch_l3_fault r25 ; andi r15, r16, 5 }
{ cmpltu r5, r6, r7 ; prefetch_l3_fault r25 ; xor r15, r16, r17 }
{ cmpltu r5, r6, r7 ; rotli r15, r16, 5 }
{ cmpltu r5, r6, r7 ; shl1addx r15, r16, r17 ; ld r25, r26 }
{ cmpltu r5, r6, r7 ; shl2addx r15, r16, r17 ; ld1u r25, r26 }
{ cmpltu r5, r6, r7 ; shl3addx r15, r16, r17 ; ld2u r25, r26 }
{ cmpltu r5, r6, r7 ; shrs r15, r16, r17 ; ld2u r25, r26 }
{ cmpltu r5, r6, r7 ; shru r15, r16, r17 ; ld4u r25, r26 }
{ cmpltu r5, r6, r7 ; st r25, r26 ; andi r15, r16, 5 }
{ cmpltu r5, r6, r7 ; st r25, r26 ; xor r15, r16, r17 }
{ cmpltu r5, r6, r7 ; st1 r25, r26 ; shl3addx r15, r16, r17 }
{ cmpltu r5, r6, r7 ; st2 r25, r26 ; or r15, r16, r17 }
{ cmpltu r5, r6, r7 ; st4 r25, r26 ; jr r15 }
{ cmpltu r5, r6, r7 ; sub r15, r16, r17 ; ld1u r25, r26 }
{ cmpltu r5, r6, r7 ; v1cmpeq r15, r16, r17 }
{ cmpltu r5, r6, r7 ; v2maxsi r15, r16, 5 }
{ cmpltu r5, r6, r7 ; xor r15, r16, r17 ; prefetch_l2_fault r25 }
{ cmpltui r15, r16, 5 ; crc32_32 r5, r6, r7 }
{ cmpltui r15, r16, 5 ; mula_hs_hs r5, r6, r7 }
{ cmpltui r15, r16, 5 ; sub r5, r6, r7 }
{ cmpltui r15, r16, 5 ; v1mulus r5, r6, r7 }
{ cmpltui r15, r16, 5 ; v2packl r5, r6, r7 }
{ cmpltui r5, r6, 5 ; cmpexch4 r15, r16, r17 }
{ cmpltui r5, r6, 5 ; ld1u_add r15, r16, 5 }
{ cmpltui r5, r6, 5 ; prefetch_add_l1 r15, 5 }
{ cmpltui r5, r6, 5 ; stnt r15, r16 }
{ cmpltui r5, r6, 5 ; v2addi r15, r16, 5 }
{ cmpltui r5, r6, 5 ; v4sub r15, r16, r17 }
{ cmpne r15, r16, r17 ; addi r5, r6, 5 ; st2 r25, r26 }
{ cmpne r15, r16, r17 ; addxi r5, r6, 5 ; st4 r25, r26 }
{ cmpne r15, r16, r17 ; andi r5, r6, 5 ; st4 r25, r26 }
{ cmpne r15, r16, r17 ; cmoveqz r5, r6, r7 ; st2 r25, r26 }
{ cmpne r15, r16, r17 ; cmpeq r5, r6, r7 }
{ cmpne r15, r16, r17 ; cmpleu r5, r6, r7 ; ld1s r25, r26 }
{ cmpne r15, r16, r17 ; cmpltsi r5, r6, 5 ; ld2s r25, r26 }
{ cmpne r15, r16, r17 ; cmpne r5, r6, r7 ; ld2u r25, r26 }
{ cmpne r15, r16, r17 ; ctz r5, r6 ; st2 r25, r26 }
{ cmpne r15, r16, r17 ; fsingle_pack1 r5, r6 ; ld1u r25, r26 }
{ cmpne r15, r16, r17 ; ld r25, r26 ; addi r5, r6, 5 }
{ cmpne r15, r16, r17 ; ld r25, r26 ; rotl r5, r6, r7 }
{ cmpne r15, r16, r17 ; ld1s r25, r26 ; fnop }
{ cmpne r15, r16, r17 ; ld1s r25, r26 ; tblidxb1 r5, r6 }
{ cmpne r15, r16, r17 ; ld1u r25, r26 ; nop }
{ cmpne r15, r16, r17 ; ld2s r25, r26 ; cmpleu r5, r6, r7 }
{ cmpne r15, r16, r17 ; ld2s r25, r26 ; shrsi r5, r6, 5 }
{ cmpne r15, r16, r17 ; ld2u r25, r26 ; mula_hu_hu r5, r6, r7 }
{ cmpne r15, r16, r17 ; ld4s r25, r26 ; clz r5, r6 }
{ cmpne r15, r16, r17 ; ld4s r25, r26 ; shl2add r5, r6, r7 }
{ cmpne r15, r16, r17 ; ld4u r25, r26 ; movei r5, 5 }
{ cmpne r15, r16, r17 ; mm r5, r6, 5, 7 }
{ cmpne r15, r16, r17 ; movei r5, 5 ; ld1s r25, r26 }
{ cmpne r15, r16, r17 ; mul_hs_lu r5, r6, r7 }
{ cmpne r15, r16, r17 ; mul_ls_ls r5, r6, r7 }
{ cmpne r15, r16, r17 ; mula_hs_hu r5, r6, r7 }
{ cmpne r15, r16, r17 ; mula_ls_ls r5, r6, r7 ; st2 r25, r26 }
{ cmpne r15, r16, r17 ; mulax r5, r6, r7 ; st4 r25, r26 }
{ cmpne r15, r16, r17 ; nop ; ld r25, r26 }
{ cmpne r15, r16, r17 ; or r5, r6, r7 ; ld1u r25, r26 }
{ cmpne r15, r16, r17 ; prefetch r25 ; addxi r5, r6, 5 }
{ cmpne r15, r16, r17 ; prefetch r25 ; shl r5, r6, r7 }
{ cmpne r15, r16, r17 ; prefetch_l1 r25 ; info 19 }
{ cmpne r15, r16, r17 ; prefetch_l1 r25 ; tblidxb3 r5, r6 }
{ cmpne r15, r16, r17 ; prefetch_l1_fault r25 ; or r5, r6, r7 }
{ cmpne r15, r16, r17 ; prefetch_l2 r25 ; cmpltsi r5, r6, 5 }
{ cmpne r15, r16, r17 ; prefetch_l2 r25 ; shrui r5, r6, 5 }
{ cmpne r15, r16, r17 ; prefetch_l2_fault r25 ; mula_lu_lu r5, r6, r7 }
{ cmpne r15, r16, r17 ; prefetch_l3 r25 ; cmovnez r5, r6, r7 }
{ cmpne r15, r16, r17 ; prefetch_l3 r25 ; shl3add r5, r6, r7 }
{ cmpne r15, r16, r17 ; prefetch_l3_fault r25 ; mul_hu_hu r5, r6, r7 }
{ cmpne r15, r16, r17 ; revbits r5, r6 ; ld1u r25, r26 }
{ cmpne r15, r16, r17 ; rotl r5, r6, r7 ; ld2u r25, r26 }
{ cmpne r15, r16, r17 ; shl r5, r6, r7 ; ld4u r25, r26 }
{ cmpne r15, r16, r17 ; shl1addx r5, r6, r7 ; prefetch r25 }
{ cmpne r15, r16, r17 ; shl2addx r5, r6, r7 ; prefetch_l1_fault r25 }
{ cmpne r15, r16, r17 ; shl3addx r5, r6, r7 ; prefetch_l2_fault r25 }
{ cmpne r15, r16, r17 ; shrs r5, r6, r7 ; prefetch_l2_fault r25 }
{ cmpne r15, r16, r17 ; shru r5, r6, r7 ; prefetch_l3_fault r25 }
{ cmpne r15, r16, r17 ; st r25, r26 ; cmpleu r5, r6, r7 }
{ cmpne r15, r16, r17 ; st r25, r26 ; shrsi r5, r6, 5 }
{ cmpne r15, r16, r17 ; st1 r25, r26 ; mula_hu_hu r5, r6, r7 }
{ cmpne r15, r16, r17 ; st2 r25, r26 ; clz r5, r6 }
{ cmpne r15, r16, r17 ; st2 r25, r26 ; shl2add r5, r6, r7 }
{ cmpne r15, r16, r17 ; st4 r25, r26 ; movei r5, 5 }
{ cmpne r15, r16, r17 ; sub r5, r6, r7 ; ld r25, r26 }
{ cmpne r15, r16, r17 ; tblidxb0 r5, r6 ; ld1s r25, r26 }
{ cmpne r15, r16, r17 ; tblidxb2 r5, r6 ; ld2s r25, r26 }
{ cmpne r15, r16, r17 ; v1cmpeq r5, r6, r7 }
{ cmpne r15, r16, r17 ; v2add r5, r6, r7 }
{ cmpne r15, r16, r17 ; v2shrui r5, r6, 5 }
{ cmpne r5, r6, r7 ; add r15, r16, r17 ; ld4u r25, r26 }
{ cmpne r5, r6, r7 ; addx r15, r16, r17 ; prefetch r25 }
{ cmpne r5, r6, r7 ; and r15, r16, r17 ; prefetch r25 }
{ cmpne r5, r6, r7 ; cmpeq r15, r16, r17 ; prefetch_l1_fault r25 }
{ cmpne r5, r6, r7 ; cmples r15, r16, r17 ; prefetch_l1_fault r25 }
{ cmpne r5, r6, r7 ; cmplts r15, r16, r17 ; prefetch_l2_fault r25 }
{ cmpne r5, r6, r7 ; cmpltu r15, r16, r17 ; prefetch_l3_fault r25 }
{ cmpne r5, r6, r7 ; finv r15 }
{ cmpne r5, r6, r7 ; ill ; st4 r25, r26 }
{ cmpne r5, r6, r7 ; jalr r15 ; st2 r25, r26 }
{ cmpne r5, r6, r7 ; jr r15 }
{ cmpne r5, r6, r7 ; ld r25, r26 ; jr r15 }
{ cmpne r5, r6, r7 ; ld1s r25, r26 ; cmpltsi r15, r16, 5 }
{ cmpne r5, r6, r7 ; ld1u r25, r26 ; addx r15, r16, r17 }
{ cmpne r5, r6, r7 ; ld1u r25, r26 ; shrui r15, r16, 5 }
{ cmpne r5, r6, r7 ; ld2s r25, r26 ; shl1addx r15, r16, r17 }
{ cmpne r5, r6, r7 ; ld2u r25, r26 ; movei r15, 5 }
{ cmpne r5, r6, r7 ; ld4s r25, r26 ; ill }
{ cmpne r5, r6, r7 ; ld4u r25, r26 ; cmpeq r15, r16, r17 }
{ cmpne r5, r6, r7 ; ld4u r25, r26 }
{ cmpne r5, r6, r7 ; mnz r15, r16, r17 ; ld r25, r26 }
{ cmpne r5, r6, r7 ; movei r15, 5 ; ld1u r25, r26 }
{ cmpne r5, r6, r7 ; nop ; ld1u r25, r26 }
{ cmpne r5, r6, r7 ; or r15, r16, r17 ; ld2u r25, r26 }
{ cmpne r5, r6, r7 ; prefetch r25 ; move r15, r16 }
{ cmpne r5, r6, r7 ; prefetch_l1 r25 ; cmpleu r15, r16, r17 }
{ cmpne r5, r6, r7 ; prefetch_l1_fault r25 ; addi r15, r16, 5 }
{ cmpne r5, r6, r7 ; prefetch_l1_fault r25 ; shru r15, r16, r17 }
{ cmpne r5, r6, r7 ; prefetch_l2 r25 ; shl1addx r15, r16, r17 }
{ cmpne r5, r6, r7 ; prefetch_l2_fault r25 ; mz r15, r16, r17 }
{ cmpne r5, r6, r7 ; prefetch_l3 r25 ; jalr r15 }
{ cmpne r5, r6, r7 ; prefetch_l3_fault r25 ; cmpleu r15, r16, r17 }
{ cmpne r5, r6, r7 ; rotl r15, r16, r17 ; ld1s r25, r26 }
{ cmpne r5, r6, r7 ; shl r15, r16, r17 ; ld2s r25, r26 }
{ cmpne r5, r6, r7 ; shl1addx r15, r16, r17 ; ld2u r25, r26 }
{ cmpne r5, r6, r7 ; shl2addx r15, r16, r17 ; ld4u r25, r26 }
{ cmpne r5, r6, r7 ; shl3addx r15, r16, r17 ; prefetch_l1 r25 }
{ cmpne r5, r6, r7 ; shrs r15, r16, r17 ; prefetch_l1 r25 }
{ cmpne r5, r6, r7 ; shru r15, r16, r17 ; prefetch_l2 r25 }
{ cmpne r5, r6, r7 ; st r25, r26 ; cmpleu r15, r16, r17 }
{ cmpne r5, r6, r7 ; st1 r25, r26 ; addi r15, r16, 5 }
{ cmpne r5, r6, r7 ; st1 r25, r26 ; shru r15, r16, r17 }
{ cmpne r5, r6, r7 ; st2 r25, r26 ; shl1add r15, r16, r17 }
{ cmpne r5, r6, r7 ; st4 r25, r26 ; move r15, r16 }
{ cmpne r5, r6, r7 ; sub r15, r16, r17 ; ld4u r25, r26 }
{ cmpne r5, r6, r7 ; v1cmplts r15, r16, r17 }
{ cmpne r5, r6, r7 ; v2mz r15, r16, r17 }
{ cmpne r5, r6, r7 ; xor r15, r16, r17 ; st1 r25, r26 }
{ cmul r5, r6, r7 ; flush r15 }
{ cmul r5, r6, r7 ; ldnt4u r15, r16 }
{ cmul r5, r6, r7 ; shli r15, r16, 5 }
{ cmul r5, r6, r7 ; v1int_h r15, r16, r17 }
{ cmul r5, r6, r7 ; v2shli r15, r16, 5 }
{ cmula r5, r6, r7 ; cmpltui r15, r16, 5 }
{ cmula r5, r6, r7 ; ld4s_add r15, r16, 5 }
{ cmula r5, r6, r7 ; prefetch_l1 r15 }
{ cmula r5, r6, r7 ; stnt4_add r15, r16, 5 }
{ cmula r5, r6, r7 ; v2cmplts r15, r16, r17 }
{ cmulaf r5, r6, r7 ; addi r15, r16, 5 }
{ cmulaf r5, r6, r7 ; infol 0x1234 }
{ cmulaf r5, r6, r7 ; mnz r15, r16, r17 }
{ cmulaf r5, r6, r7 ; shrui r15, r16, 5 }
{ cmulaf r5, r6, r7 ; v1mnz r15, r16, r17 }
{ cmulaf r5, r6, r7 ; v2sub r15, r16, r17 }
{ cmulf r5, r6, r7 ; exch r15, r16, r17 }
{ cmulf r5, r6, r7 ; ldnt r15, r16 }
{ cmulf r5, r6, r7 ; raise }
{ cmulf r5, r6, r7 ; v1addi r15, r16, 5 }
{ cmulf r5, r6, r7 ; v2int_l r15, r16, r17 }
{ cmulfr r5, r6, r7 ; and r15, r16, r17 }
{ cmulfr r5, r6, r7 ; jrp r15 }
{ cmulfr r5, r6, r7 ; nop }
{ cmulfr r5, r6, r7 ; st2 r15, r16 }
{ cmulfr r5, r6, r7 ; v1shru r15, r16, r17 }
{ cmulfr r5, r6, r7 ; v4packsc r15, r16, r17 }
{ cmulh r5, r6, r7 ; fetchand r15, r16, r17 }
{ cmulh r5, r6, r7 ; ldnt2s_add r15, r16, 5 }
{ cmulh r5, r6, r7 ; shl1addx r15, r16, r17 }
{ cmulh r5, r6, r7 ; v1cmplts r15, r16, r17 }
{ cmulh r5, r6, r7 ; v2mz r15, r16, r17 }
{ cmulhr r5, r6, r7 ; cmples r15, r16, r17 }
{ cmulhr r5, r6, r7 ; ld2s r15, r16 }
{ cmulhr r5, r6, r7 ; prefetch_add_l1_fault r15, 5 }
{ cmulhr r5, r6, r7 ; stnt1 r15, r16 }
{ cmulhr r5, r6, r7 ; v2addsc r15, r16, r17 }
{ cmulhr r5, r6, r7 ; v4subsc r15, r16, r17 }
{ crc32_32 r5, r6, r7 ; flushwb }
{ crc32_32 r5, r6, r7 ; ldnt4u_add r15, r16, 5 }
{ crc32_32 r5, r6, r7 ; shlx r15, r16, r17 }
{ crc32_32 r5, r6, r7 ; v1int_l r15, r16, r17 }
{ crc32_32 r5, r6, r7 ; v2shlsc r15, r16, r17 }
{ crc32_8 r5, r6, r7 ; cmpne r15, r16, r17 }
{ crc32_8 r5, r6, r7 ; ld4u r15, r16 }
{ crc32_8 r5, r6, r7 ; prefetch_l1_fault r15 }
{ crc32_8 r5, r6, r7 ; stnt_add r15, r16, 5 }
{ crc32_8 r5, r6, r7 ; v2cmpltsi r15, r16, 5 }
{ ctz r5, r6 ; add r15, r16, r17 ; ld1u r25, r26 }
{ ctz r5, r6 ; addx r15, r16, r17 ; ld2s r25, r26 }
{ ctz r5, r6 ; and r15, r16, r17 ; ld2s r25, r26 }
{ ctz r5, r6 ; cmpeq r15, r16, r17 ; ld4s r25, r26 }
{ ctz r5, r6 ; cmples r15, r16, r17 ; ld4s r25, r26 }
{ ctz r5, r6 ; cmplts r15, r16, r17 ; prefetch r25 }
{ ctz r5, r6 ; cmpltu r15, r16, r17 ; prefetch_l1_fault r25 }
{ ctz r5, r6 ; fetchand r15, r16, r17 }
{ ctz r5, r6 ; ill ; prefetch_l3_fault r25 }
{ ctz r5, r6 ; jalr r15 ; prefetch_l3 r25 }
{ ctz r5, r6 ; jr r15 ; st r25, r26 }
{ ctz r5, r6 ; ld r25, r26 ; ill }
{ ctz r5, r6 ; ld1s r25, r26 ; cmpeqi r15, r16, 5 }
{ ctz r5, r6 ; ld1s_add r15, r16, 5 }
{ ctz r5, r6 ; ld1u r25, r26 ; shli r15, r16, 5 }
{ ctz r5, r6 ; ld2s r25, r26 ; rotl r15, r16, r17 }
{ ctz r5, r6 ; ld2u r25, r26 ; jrp r15 }
{ ctz r5, r6 ; ld4s r25, r26 ; cmpltsi r15, r16, 5 }
{ ctz r5, r6 ; ld4u r25, r26 ; addx r15, r16, r17 }
{ ctz r5, r6 ; ld4u r25, r26 ; shrui r15, r16, 5 }
{ ctz r5, r6 ; lnk r15 ; st4 r25, r26 }
{ ctz r5, r6 ; move r15, r16 ; st4 r25, r26 }
{ ctz r5, r6 ; mz r15, r16, r17 ; st4 r25, r26 }
{ ctz r5, r6 ; or r15, r16, r17 ; ld r25, r26 }
{ ctz r5, r6 ; prefetch r25 ; jr r15 }
{ ctz r5, r6 ; prefetch_l1 r25 ; andi r15, r16, 5 }
{ ctz r5, r6 ; prefetch_l1 r25 ; xor r15, r16, r17 }
{ ctz r5, r6 ; prefetch_l1_fault r25 ; shl3addx r15, r16, r17 }
{ ctz r5, r6 ; prefetch_l2 r25 ; rotl r15, r16, r17 }
{ ctz r5, r6 ; prefetch_l2_fault r25 ; lnk r15 }
{ ctz r5, r6 ; prefetch_l3 r25 ; cmpne r15, r16, r17 }
{ ctz r5, r6 ; prefetch_l3_fault r25 ; andi r15, r16, 5 }
{ ctz r5, r6 ; prefetch_l3_fault r25 ; xor r15, r16, r17 }
{ ctz r5, r6 ; rotli r15, r16, 5 }
{ ctz r5, r6 ; shl1addx r15, r16, r17 ; ld r25, r26 }
{ ctz r5, r6 ; shl2addx r15, r16, r17 ; ld1u r25, r26 }
{ ctz r5, r6 ; shl3addx r15, r16, r17 ; ld2u r25, r26 }
{ ctz r5, r6 ; shrs r15, r16, r17 ; ld2u r25, r26 }
{ ctz r5, r6 ; shru r15, r16, r17 ; ld4u r25, r26 }
{ ctz r5, r6 ; st r25, r26 ; andi r15, r16, 5 }
{ ctz r5, r6 ; st r25, r26 ; xor r15, r16, r17 }
{ ctz r5, r6 ; st1 r25, r26 ; shl3addx r15, r16, r17 }
{ ctz r5, r6 ; st2 r25, r26 ; or r15, r16, r17 }
{ ctz r5, r6 ; st4 r25, r26 ; jr r15 }
{ ctz r5, r6 ; sub r15, r16, r17 ; ld1u r25, r26 }
{ ctz r5, r6 ; v1cmpeq r15, r16, r17 }
{ ctz r5, r6 ; v2maxsi r15, r16, 5 }
{ ctz r5, r6 ; xor r15, r16, r17 ; prefetch_l2_fault r25 }
{ dblalign r5, r6, r7 ; fetchand4 r15, r16, r17 }
{ dblalign r5, r6, r7 ; ldnt2u r15, r16 }
{ dblalign r5, r6, r7 ; shl2add r15, r16, r17 }
{ dblalign r5, r6, r7 ; v1cmpltsi r15, r16, 5 }
{ dblalign r5, r6, r7 ; v2packh r15, r16, r17 }
{ dblalign2 r15, r16, r17 ; cmovnez r5, r6, r7 }
{ dblalign2 r15, r16, r17 ; info 19 }
{ dblalign2 r15, r16, r17 ; shl16insli r5, r6, 0x1234 }
{ dblalign2 r15, r16, r17 ; v1ddotpus r5, r6, r7 }
{ dblalign2 r15, r16, r17 ; v2cmpltu r5, r6, r7 }
{ dblalign2 r15, r16, r17 ; v4shru r5, r6, r7 }
{ dblalign2 r5, r6, r7 ; flush r15 }
{ dblalign2 r5, r6, r7 ; ldnt4u r15, r16 }
{ dblalign2 r5, r6, r7 ; shli r15, r16, 5 }
{ dblalign2 r5, r6, r7 ; v1int_h r15, r16, r17 }
{ dblalign2 r5, r6, r7 ; v2shli r15, r16, 5 }
{ dblalign4 r15, r16, r17 ; cmpleu r5, r6, r7 }
{ dblalign4 r15, r16, r17 ; move r5, r6 }
{ dblalign4 r15, r16, r17 ; shl2addx r5, r6, r7 }
{ dblalign4 r15, r16, r17 ; v1dotpu r5, r6, r7 }
{ dblalign4 r15, r16, r17 ; v2dotpa r5, r6, r7 }
{ dblalign4 r15, r16, r17 ; xori r5, r6, 5 }
{ dblalign4 r5, r6, r7 ; ill }
{ dblalign4 r5, r6, r7 ; mf }
{ dblalign4 r5, r6, r7 ; shrsi r15, r16, 5 }
{ dblalign4 r5, r6, r7 ; v1minu r15, r16, r17 }
{ dblalign4 r5, r6, r7 ; v2shru r15, r16, r17 }
{ dblalign6 r15, r16, r17 ; cmpltui r5, r6, 5 }
{ dblalign6 r15, r16, r17 ; mul_hs_hu r5, r6, r7 }
{ dblalign6 r15, r16, r17 ; shlx r5, r6, r7 }
{ dblalign6 r15, r16, r17 ; v1int_h r5, r6, r7 }
{ dblalign6 r15, r16, r17 ; v2maxsi r5, r6, 5 }
{ dblalign6 r5, r6, r7 ; addx r15, r16, r17 }
{ dblalign6 r5, r6, r7 ; iret }
{ dblalign6 r5, r6, r7 ; movei r15, 5 }
{ dblalign6 r5, r6, r7 ; shruxi r15, r16, 5 }
{ dblalign6 r5, r6, r7 ; v1shl r15, r16, r17 }
{ dblalign6 r5, r6, r7 ; v4add r15, r16, r17 }
{ dtlbpr r15 ; cmula r5, r6, r7 }
{ dtlbpr r15 ; mul_hu_hu r5, r6, r7 }
{ dtlbpr r15 ; shrsi r5, r6, 5 }
{ dtlbpr r15 ; v1maxui r5, r6, 5 }
{ dtlbpr r15 ; v2mnz r5, r6, r7 }
{ exch r15, r16, r17 ; addxsc r5, r6, r7 }
{ exch r15, r16, r17 ; fnop }
{ exch r15, r16, r17 ; or r5, r6, r7 }
{ exch r15, r16, r17 ; v1cmpleu r5, r6, r7 }
{ exch r15, r16, r17 ; v2adiffs r5, r6, r7 }
{ exch r15, r16, r17 ; v4add r5, r6, r7 }
{ exch4 r15, r16, r17 ; cmulf r5, r6, r7 }
{ exch4 r15, r16, r17 ; mul_hu_lu r5, r6, r7 }
{ exch4 r15, r16, r17 ; shrui r5, r6, 5 }
{ exch4 r15, r16, r17 ; v1minui r5, r6, 5 }
{ exch4 r15, r16, r17 ; v2muls r5, r6, r7 }
{ fdouble_add_flags r5, r6, r7 ; andi r15, r16, 5 }
{ fdouble_add_flags r5, r6, r7 ; ld r15, r16 }
{ fdouble_add_flags r5, r6, r7 ; nor r15, r16, r17 }
{ fdouble_add_flags r5, r6, r7 ; st2_add r15, r16, 5 }
{ fdouble_add_flags r5, r6, r7 ; v1shrui r15, r16, 5 }
{ fdouble_add_flags r5, r6, r7 ; v4shl r15, r16, r17 }
{ fdouble_addsub r5, r6, r7 ; fetchand4 r15, r16, r17 }
{ fdouble_addsub r5, r6, r7 ; ldnt2u r15, r16 }
{ fdouble_addsub r5, r6, r7 ; shl2add r15, r16, r17 }
{ fdouble_addsub r5, r6, r7 ; v1cmpltsi r15, r16, 5 }
{ fdouble_addsub r5, r6, r7 ; v2packh r15, r16, r17 }
{ fdouble_mul_flags r5, r6, r7 ; cmpleu r15, r16, r17 }
{ fdouble_mul_flags r5, r6, r7 ; ld2s_add r15, r16, 5 }
{ fdouble_mul_flags r5, r6, r7 ; prefetch_add_l2 r15, 5 }
{ fdouble_mul_flags r5, r6, r7 ; stnt1_add r15, r16, 5 }
{ fdouble_mul_flags r5, r6, r7 ; v2cmpeq r15, r16, r17 }
{ fdouble_mul_flags r5, r6, r7 ; wh64 r15 }
{ fdouble_pack1 r5, r6, r7 ; fnop }
{ fdouble_pack1 r5, r6, r7 ; ldnt_add r15, r16, 5 }
{ fdouble_pack1 r5, r6, r7 ; shlxi r15, r16, 5 }
{ fdouble_pack1 r5, r6, r7 ; v1maxu r15, r16, r17 }
{ fdouble_pack1 r5, r6, r7 ; v2shrs r15, r16, r17 }
{ fdouble_pack2 r5, r6, r7 ; dblalign2 r15, r16, r17 }
{ fdouble_pack2 r5, r6, r7 ; ld4u_add r15, r16, 5 }
{ fdouble_pack2 r5, r6, r7 ; prefetch_l2 r15 }
{ fdouble_pack2 r5, r6, r7 ; sub r15, r16, r17 }
{ fdouble_pack2 r5, r6, r7 ; v2cmpltu r15, r16, r17 }
{ fdouble_sub_flags r5, r6, r7 ; addx r15, r16, r17 }
{ fdouble_sub_flags r5, r6, r7 ; iret }
{ fdouble_sub_flags r5, r6, r7 ; movei r15, 5 }
{ fdouble_sub_flags r5, r6, r7 ; shruxi r15, r16, 5 }
{ fdouble_sub_flags r5, r6, r7 ; v1shl r15, r16, r17 }
{ fdouble_sub_flags r5, r6, r7 ; v4add r15, r16, r17 }
{ fdouble_unpack_max r5, r6, r7 ; fetchadd r15, r16, r17 }
{ fdouble_unpack_max r5, r6, r7 ; ldnt1s_add r15, r16, 5 }
{ fdouble_unpack_max r5, r6, r7 ; rotli r15, r16, 5 }
{ fdouble_unpack_max r5, r6, r7 ; v1cmpeq r15, r16, r17 }
{ fdouble_unpack_max r5, r6, r7 ; v2maxsi r15, r16, 5 }
{ fdouble_unpack_min r5, r6, r7 ; cmpeq r15, r16, r17 }
{ fdouble_unpack_min r5, r6, r7 ; ld1s r15, r16 }
{ fdouble_unpack_min r5, r6, r7 ; or r15, r16, r17 }
{ fdouble_unpack_min r5, r6, r7 ; st4 r15, r16 }
{ fdouble_unpack_min r5, r6, r7 ; v1sub r15, r16, r17 }
{ fdouble_unpack_min r5, r6, r7 ; v4shlsc r15, r16, r17 }
{ fetchadd r15, r16, r17 ; crc32_8 r5, r6, r7 }
{ fetchadd r15, r16, r17 ; mula_hs_hu r5, r6, r7 }
{ fetchadd r15, r16, r17 ; subx r5, r6, r7 }
{ fetchadd r15, r16, r17 ; v1mz r5, r6, r7 }
{ fetchadd r15, r16, r17 ; v2packuc r5, r6, r7 }
{ fetchadd4 r15, r16, r17 ; cmoveqz r5, r6, r7 }
{ fetchadd4 r15, r16, r17 ; fsingle_sub1 r5, r6, r7 }
{ fetchadd4 r15, r16, r17 ; shl r5, r6, r7 }
{ fetchadd4 r15, r16, r17 ; v1ddotpua r5, r6, r7 }
{ fetchadd4 r15, r16, r17 ; v2cmpltsi r5, r6, 5 }
{ fetchadd4 r15, r16, r17 ; v4shrs r5, r6, r7 }
{ fetchaddgez r15, r16, r17 ; dblalign r5, r6, r7 }
{ fetchaddgez r15, r16, r17 ; mula_hs_lu r5, r6, r7 }
{ fetchaddgez r15, r16, r17 ; tblidxb0 r5, r6 }
{ fetchaddgez r15, r16, r17 ; v1sadu r5, r6, r7 }
{ fetchaddgez r15, r16, r17 ; v2sadau r5, r6, r7 }
{ fetchaddgez4 r15, r16, r17 ; cmpeq r5, r6, r7 }
{ fetchaddgez4 r15, r16, r17 ; infol 0x1234 }
{ fetchaddgez4 r15, r16, r17 ; shl1add r5, r6, r7 }
{ fetchaddgez4 r15, r16, r17 ; v1ddotpusa r5, r6, r7 }
{ fetchaddgez4 r15, r16, r17 ; v2cmpltui r5, r6, 5 }
{ fetchaddgez4 r15, r16, r17 ; v4sub r5, r6, r7 }
{ fetchand r15, r16, r17 ; dblalign4 r5, r6, r7 }
{ fetchand r15, r16, r17 ; mula_hu_ls r5, r6, r7 }
{ fetchand r15, r16, r17 ; tblidxb2 r5, r6 }
{ fetchand r15, r16, r17 ; v1shli r5, r6, 5 }
{ fetchand r15, r16, r17 ; v2sadu r5, r6, r7 }
{ fetchand4 r15, r16, r17 ; cmples r5, r6, r7 }
{ fetchand4 r15, r16, r17 ; mnz r5, r6, r7 }
{ fetchand4 r15, r16, r17 ; shl2add r5, r6, r7 }
{ fetchand4 r15, r16, r17 ; v1dotpa r5, r6, r7 }
{ fetchand4 r15, r16, r17 ; v2dotp r5, r6, r7 }
{ fetchand4 r15, r16, r17 ; xor r5, r6, r7 }
{ fetchor r15, r16, r17 ; fdouble_add_flags r5, r6, r7 }
{ fetchor r15, r16, r17 ; mula_ls_ls r5, r6, r7 }
{ fetchor r15, r16, r17 ; v1add r5, r6, r7 }
{ fetchor r15, r16, r17 ; v1shrsi r5, r6, 5 }
{ fetchor r15, r16, r17 ; v2shli r5, r6, 5 }
{ fetchor4 r15, r16, r17 ; cmplts r5, r6, r7 }
{ fetchor4 r15, r16, r17 ; movei r5, 5 }
{ fetchor4 r15, r16, r17 ; shl3add r5, r6, r7 }
{ fetchor4 r15, r16, r17 ; v1dotpua r5, r6, r7 }
{ fetchor4 r15, r16, r17 ; v2int_h r5, r6, r7 }
{ finv r15 ; add r5, r6, r7 }
{ finv r15 ; fdouble_mul_flags r5, r6, r7 }
{ finv r15 ; mula_lu_lu r5, r6, r7 }
{ finv r15 ; v1adduc r5, r6, r7 }
{ finv r15 ; v1shrui r5, r6, 5 }
{ finv r15 ; v2shrs r5, r6, r7 }
{ flush r15 ; cmpltu r5, r6, r7 }
{ flush r15 ; mul_hs_hs r5, r6, r7 }
{ flush r15 ; shli r5, r6, 5 }
{ flush r15 ; v1dotpusa r5, r6, r7 }
{ flush r15 ; v2maxs r5, r6, r7 }
{ flushwb ; addli r5, r6, 0x1234 }
{ flushwb ; fdouble_pack2 r5, r6, r7 }
{ flushwb ; mulx r5, r6, r7 }
{ flushwb ; v1avgu r5, r6, r7 }
{ flushwb ; v1subuc r5, r6, r7 }
{ flushwb ; v2shru r5, r6, r7 }
{ fnop ; add r5, r6, r7 ; ld2u r25, r26 }
{ fnop ; addi r5, r6, 5 ; ld4u r25, r26 }
{ fnop ; addx r5, r6, r7 ; ld4u r25, r26 }
{ fnop ; addxi r5, r6, 5 ; prefetch_l1 r25 }
{ fnop ; and r5, r6, r7 ; ld4u r25, r26 }
{ fnop ; andi r5, r6, 5 ; prefetch_l1 r25 }
{ fnop ; cmoveqz r5, r6, r7 ; prefetch r25 }
{ fnop ; cmpeq r15, r16, r17 ; prefetch_l1_fault r25 }
{ fnop ; cmpeqi r15, r16, 5 ; prefetch_l2_fault r25 }
{ fnop ; cmples r15, r16, r17 ; prefetch_l2_fault r25 }
{ fnop ; cmpleu r15, r16, r17 ; prefetch_l3_fault r25 }
{ fnop ; cmplts r15, r16, r17 ; st1 r25, r26 }
{ fnop ; cmpltsi r15, r16, 5 ; st4 r25, r26 }
{ fnop ; cmpltu r5, r6, r7 ; ld r25, r26 }
{ fnop ; cmpne r5, r6, r7 ; ld r25, r26 }
{ fnop ; ctz r5, r6 ; prefetch_l3 r25 }
{ fnop ; fnop ; ld2u r25, r26 }
{ fnop ; icoh r15 }
{ fnop ; inv r15 }
{ fnop ; jr r15 ; ld r25, r26 }
{ fnop ; ld r25, r26 ; add r5, r6, r7 }
{ fnop ; ld r25, r26 ; mnz r15, r16, r17 }
{ fnop ; ld r25, r26 ; shl3add r15, r16, r17 }
{ fnop ; ld1s r25, r26 ; cmovnez r5, r6, r7 }
{ fnop ; ld1s r25, r26 ; mula_lu_lu r5, r6, r7 }
{ fnop ; ld1s r25, r26 ; shrui r5, r6, 5 }
{ fnop ; ld1u r25, r26 ; cmpltsi r5, r6, 5 }
{ fnop ; ld1u r25, r26 ; revbytes r5, r6 }
{ fnop ; ld1u_add r15, r16, 5 }
{ fnop ; ld2s r25, r26 ; jr r15 }
{ fnop ; ld2s r25, r26 ; shl2add r5, r6, r7 }
{ fnop ; ld2u r25, r26 ; andi r15, r16, 5 }
{ fnop ; ld2u r25, r26 ; mul_lu_lu r5, r6, r7 }
{ fnop ; ld2u r25, r26 ; shrsi r5, r6, 5 }
{ fnop ; ld4s r25, r26 ; cmpleu r5, r6, r7 }
{ fnop ; ld4s r25, r26 ; or r15, r16, r17 }
{ fnop ; ld4s r25, r26 ; tblidxb3 r5, r6 }
{ fnop ; ld4u r25, r26 ; ill }
{ fnop ; ld4u r25, r26 ; shl1add r5, r6, r7 }
{ fnop ; ldnt1u_add r15, r16, 5 }
{ fnop ; mnz r15, r16, r17 ; prefetch_l1 r25 }
{ fnop ; move r15, r16 ; prefetch_l2 r25 }
{ fnop ; movei r15, 5 ; prefetch_l3 r25 }
{ fnop ; mul_hs_hs r5, r6, r7 ; prefetch_l2_fault r25 }
{ fnop ; mul_ls_ls r5, r6, r7 ; prefetch_l1 r25 }
{ fnop ; mula_hs_hs r5, r6, r7 ; prefetch_l1_fault r25 }
{ fnop ; mula_ls_ls r5, r6, r7 ; ld4u r25, r26 }
{ fnop ; mulax r5, r6, r7 ; prefetch r25 }
{ fnop ; mz r15, r16, r17 ; prefetch_l1_fault r25 }
{ fnop ; nop ; prefetch_l2_fault r25 }
{ fnop ; nor r5, r6, r7 ; prefetch_l3_fault r25 }
{ fnop ; or r5, r6, r7 ; st1 r25, r26 }
{ fnop ; prefetch r25 ; cmovnez r5, r6, r7 }
{ fnop ; prefetch r25 ; mula_lu_lu r5, r6, r7 }
{ fnop ; prefetch r25 ; shrui r5, r6, 5 }
{ fnop ; prefetch_l1 r25 ; cmpleu r15, r16, r17 }
{ fnop ; prefetch_l1 r25 ; nor r5, r6, r7 }
{ fnop ; prefetch_l1 r25 ; tblidxb2 r5, r6 }
{ fnop ; prefetch_l1_fault r25 ; ill }
{ fnop ; prefetch_l1_fault r25 ; shl1add r5, r6, r7 }
{ fnop ; prefetch_l2 r25 ; addxi r5, r6, 5 }
{ fnop ; prefetch_l2 r25 ; mul_hs_hs r5, r6, r7 }
{ fnop ; prefetch_l2 r25 ; shrs r15, r16, r17 }
{ fnop ; prefetch_l2_fault r25 ; cmples r5, r6, r7 }
{ fnop ; prefetch_l2_fault r25 ; nor r15, r16, r17 }
{ fnop ; prefetch_l2_fault r25 ; tblidxb1 r5, r6 }
{ fnop ; prefetch_l3 r25 ; fsingle_pack1 r5, r6 }
{ fnop ; prefetch_l3 r25 ; shl1add r15, r16, r17 }
{ fnop ; prefetch_l3_fault r25 ; addxi r15, r16, 5 }
{ fnop ; prefetch_l3_fault r25 ; movei r5, 5 }
{ fnop ; prefetch_l3_fault r25 ; shli r5, r6, 5 }
{ fnop ; revbytes r5, r6 ; ld r25, r26 }
{ fnop ; rotl r5, r6, r7 ; ld1u r25, r26 }
{ fnop ; rotli r5, r6, 5 ; ld2u r25, r26 }
{ fnop ; shl r5, r6, r7 ; ld4u r25, r26 }
{ fnop ; shl1add r5, r6, r7 ; ld4u r25, r26 }
{ fnop ; shl1addx r5, r6, r7 ; prefetch_l1 r25 }
{ fnop ; shl2add r5, r6, r7 ; prefetch_l2 r25 }
{ fnop ; shl2addx r5, r6, r7 ; prefetch_l3 r25 }
{ fnop ; shl3add r5, r6, r7 ; st r25, r26 }
{ fnop ; shl3addx r5, r6, r7 ; st2 r25, r26 }
{ fnop ; shli r5, r6, 5 }
{ fnop ; shrs r5, r6, r7 ; st2 r25, r26 }
{ fnop ; shrsi r5, r6, 5 }
{ fnop ; shrui r15, r16, 5 ; ld1s r25, r26 }
{ fnop ; shruxi r5, r6, 5 }
{ fnop ; st r25, r26 ; jalrp r15 }
{ fnop ; st r25, r26 ; shl2add r15, r16, r17 }
{ fnop ; st1 r25, r26 ; andi r15, r16, 5 }
{ fnop ; st1 r25, r26 ; mul_lu_lu r5, r6, r7 }
{ fnop ; st1 r25, r26 ; shrsi r5, r6, 5 }
{ fnop ; st2 r25, r26 ; cmpleu r5, r6, r7 }
{ fnop ; st2 r25, r26 ; or r15, r16, r17 }
{ fnop ; st2 r25, r26 ; tblidxb3 r5, r6 }
{ fnop ; st4 r25, r26 ; ill }
{ fnop ; st4 r25, r26 ; shl1add r5, r6, r7 }
{ fnop ; stnt4_add r15, r16, 5 }
{ fnop ; subx r15, r16, r17 ; ld r25, r26 }
{ fnop ; tblidxb0 r5, r6 ; ld r25, r26 }
{ fnop ; tblidxb2 r5, r6 ; ld1u r25, r26 }
{ fnop ; v1adduc r15, r16, r17 }
{ fnop ; v1minu r15, r16, r17 }
{ fnop ; v2cmpeqi r5, r6, 5 }
{ fnop ; v2packuc r15, r16, r17 }
{ fnop ; v4shru r15, r16, r17 }
{ fnop ; xor r5, r6, r7 ; st r25, r26 }
{ fsingle_add1 r5, r6, r7 ; fetchor4 r15, r16, r17 }
{ fsingle_add1 r5, r6, r7 ; ldnt4s r15, r16 }
{ fsingle_add1 r5, r6, r7 ; shl3add r15, r16, r17 }
{ fsingle_add1 r5, r6, r7 ; v1cmpltui r15, r16, 5 }
{ fsingle_add1 r5, r6, r7 ; v2packuc r15, r16, r17 }
{ fsingle_addsub2 r5, r6, r7 ; cmpltsi r15, r16, 5 }
{ fsingle_addsub2 r5, r6, r7 ; ld2u_add r15, r16, 5 }
{ fsingle_addsub2 r5, r6, r7 ; prefetch_add_l3 r15, 5 }
{ fsingle_addsub2 r5, r6, r7 ; stnt2_add r15, r16, 5 }
{ fsingle_addsub2 r5, r6, r7 ; v2cmples r15, r16, r17 }
{ fsingle_addsub2 r5, r6, r7 ; xori r15, r16, 5 }
{ fsingle_mul1 r5, r6, r7 ; ill }
{ fsingle_mul1 r5, r6, r7 ; mf }
{ fsingle_mul1 r5, r6, r7 ; shrsi r15, r16, 5 }
{ fsingle_mul1 r5, r6, r7 ; v1minu r15, r16, r17 }
{ fsingle_mul1 r5, r6, r7 ; v2shru r15, r16, r17 }
{ fsingle_mul2 r5, r6, r7 ; dblalign6 r15, r16, r17 }
{ fsingle_mul2 r5, r6, r7 ; ldna r15, r16 }
{ fsingle_mul2 r5, r6, r7 ; prefetch_l3 r15 }
{ fsingle_mul2 r5, r6, r7 ; subxsc r15, r16, r17 }
{ fsingle_mul2 r5, r6, r7 ; v2cmpne r15, r16, r17 }
{ fsingle_pack1 r5, r6 ; add r15, r16, r17 ; ld4s r25, r26 }
{ fsingle_pack1 r5, r6 ; addx r15, r16, r17 ; ld4u r25, r26 }
{ fsingle_pack1 r5, r6 ; and r15, r16, r17 ; ld4u r25, r26 }
{ fsingle_pack1 r5, r6 ; cmpeq r15, r16, r17 ; prefetch_l1 r25 }
{ fsingle_pack1 r5, r6 ; cmples r15, r16, r17 ; prefetch_l1 r25 }
{ fsingle_pack1 r5, r6 ; cmplts r15, r16, r17 ; prefetch_l2 r25 }
{ fsingle_pack1 r5, r6 ; cmpltu r15, r16, r17 ; prefetch_l3 r25 }
{ fsingle_pack1 r5, r6 ; fetchor4 r15, r16, r17 }
{ fsingle_pack1 r5, r6 ; ill ; st2 r25, r26 }
{ fsingle_pack1 r5, r6 ; jalr r15 ; st1 r25, r26 }
{ fsingle_pack1 r5, r6 ; jr r15 ; st4 r25, r26 }
{ fsingle_pack1 r5, r6 ; ld r25, r26 ; jalrp r15 }
{ fsingle_pack1 r5, r6 ; ld1s r25, r26 ; cmplts r15, r16, r17 }
{ fsingle_pack1 r5, r6 ; ld1u r25, r26 ; addi r15, r16, 5 }
{ fsingle_pack1 r5, r6 ; ld1u r25, r26 ; shru r15, r16, r17 }
{ fsingle_pack1 r5, r6 ; ld2s r25, r26 ; shl1add r15, r16, r17 }
{ fsingle_pack1 r5, r6 ; ld2u r25, r26 ; move r15, r16 }
{ fsingle_pack1 r5, r6 ; ld4s r25, r26 ; fnop }
{ fsingle_pack1 r5, r6 ; ld4u r25, r26 ; andi r15, r16, 5 }
{ fsingle_pack1 r5, r6 ; ld4u r25, r26 ; xor r15, r16, r17 }
{ fsingle_pack1 r5, r6 ; mfspr r16, 0x5 }
{ fsingle_pack1 r5, r6 ; movei r15, 5 ; ld1s r25, r26 }
{ fsingle_pack1 r5, r6 ; nop ; ld1s r25, r26 }
{ fsingle_pack1 r5, r6 ; or r15, r16, r17 ; ld2s r25, r26 }
{ fsingle_pack1 r5, r6 ; prefetch r25 ; mnz r15, r16, r17 }
{ fsingle_pack1 r5, r6 ; prefetch_l1 r25 ; cmples r15, r16, r17 }
{ fsingle_pack1 r5, r6 ; prefetch_l1_fault r25 ; add r15, r16, r17 }
{ fsingle_pack1 r5, r6 ; prefetch_l1_fault r25 ; shrsi r15, r16, 5 }
{ fsingle_pack1 r5, r6 ; prefetch_l2 r25 ; shl1add r15, r16, r17 }
{ fsingle_pack1 r5, r6 ; prefetch_l2_fault r25 ; movei r15, 5 }
{ fsingle_pack1 r5, r6 ; prefetch_l3 r25 ; info 19 }
{ fsingle_pack1 r5, r6 ; prefetch_l3_fault r25 ; cmples r15, r16, r17 }
{ fsingle_pack1 r5, r6 ; rotl r15, r16, r17 ; ld r25, r26 }
{ fsingle_pack1 r5, r6 ; shl r15, r16, r17 ; ld1u r25, r26 }
{ fsingle_pack1 r5, r6 ; shl1addx r15, r16, r17 ; ld2s r25, r26 }
{ fsingle_pack1 r5, r6 ; shl2addx r15, r16, r17 ; ld4s r25, r26 }
{ fsingle_pack1 r5, r6 ; shl3addx r15, r16, r17 ; prefetch r25 }
{ fsingle_pack1 r5, r6 ; shrs r15, r16, r17 ; prefetch r25 }
{ fsingle_pack1 r5, r6 ; shru r15, r16, r17 ; prefetch_l1_fault r25 }
{ fsingle_pack1 r5, r6 ; st r25, r26 ; cmples r15, r16, r17 }
{ fsingle_pack1 r5, r6 ; st1 r25, r26 ; add r15, r16, r17 }
{ fsingle_pack1 r5, r6 ; st1 r25, r26 ; shrsi r15, r16, 5 }
{ fsingle_pack1 r5, r6 ; st2 r25, r26 ; shl r15, r16, r17 }
{ fsingle_pack1 r5, r6 ; st4 r25, r26 ; mnz r15, r16, r17 }
{ fsingle_pack1 r5, r6 ; sub r15, r16, r17 ; ld4s r25, r26 }
{ fsingle_pack1 r5, r6 ; v1cmpleu r15, r16, r17 }
{ fsingle_pack1 r5, r6 ; v2mnz r15, r16, r17 }
{ fsingle_pack1 r5, r6 ; xor r15, r16, r17 ; st r25, r26 }
{ fsingle_pack2 r5, r6, r7 ; finv r15 }
{ fsingle_pack2 r5, r6, r7 ; ldnt4s_add r15, r16, 5 }
{ fsingle_pack2 r5, r6, r7 ; shl3addx r15, r16, r17 }
{ fsingle_pack2 r5, r6, r7 ; v1cmpne r15, r16, r17 }
{ fsingle_pack2 r5, r6, r7 ; v2shl r15, r16, r17 }
{ fsingle_sub1 r5, r6, r7 ; cmpltu r15, r16, r17 }
{ fsingle_sub1 r5, r6, r7 ; ld4s r15, r16 }
{ fsingle_sub1 r5, r6, r7 ; prefetch_add_l3_fault r15, 5 }
{ fsingle_sub1 r5, r6, r7 ; stnt4 r15, r16 }
{ fsingle_sub1 r5, r6, r7 ; v2cmpleu r15, r16, r17 }
{ icoh r15 ; add r5, r6, r7 }
{ icoh r15 ; fdouble_mul_flags r5, r6, r7 }
{ icoh r15 ; mula_lu_lu r5, r6, r7 }
{ icoh r15 ; v1adduc r5, r6, r7 }
{ icoh r15 ; v1shrui r5, r6, 5 }
{ icoh r15 ; v2shrs r5, r6, r7 }
{ ill ; addi r5, r6, 5 ; ld1u r25, r26 }
{ ill ; addxi r5, r6, 5 ; ld2s r25, r26 }
{ ill ; andi r5, r6, 5 ; ld2s r25, r26 }
{ ill ; cmoveqz r5, r6, r7 ; ld1u r25, r26 }
{ ill ; cmpeq r5, r6, r7 ; ld2u r25, r26 }
{ ill ; cmples r5, r6, r7 ; ld4u r25, r26 }
{ ill ; cmplts r5, r6, r7 ; prefetch_l1 r25 }
{ ill ; cmpltu r5, r6, r7 ; prefetch_l2 r25 }
{ ill ; ctz r5, r6 ; ld1u r25, r26 }
{ ill ; fnop ; prefetch_l2_fault r25 }
{ ill ; info 19 ; prefetch r25 }
{ ill ; ld r25, r26 ; mul_lu_lu r5, r6, r7 }
{ ill ; ld1s r25, r26 ; and r5, r6, r7 }
{ ill ; ld1s r25, r26 ; shl1add r5, r6, r7 }
{ ill ; ld1u r25, r26 ; mnz r5, r6, r7 }
{ ill ; ld1u r25, r26 ; xor r5, r6, r7 }
{ ill ; ld2s r25, r26 ; pcnt r5, r6 }
{ ill ; ld2u r25, r26 ; cmpltu r5, r6, r7 }
{ ill ; ld2u r25, r26 ; sub r5, r6, r7 }
{ ill ; ld4s r25, r26 ; mulax r5, r6, r7 }
{ ill ; ld4u r25, r26 ; cmpeq r5, r6, r7 }
{ ill ; ld4u r25, r26 ; shl3addx r5, r6, r7 }
{ ill ; move r5, r6 ; ld4u r25, r26 }
{ ill ; mul_hs_hs r5, r6, r7 ; prefetch r25 }
{ ill ; mul_ls_ls r5, r6, r7 ; ld2u r25, r26 }
{ ill ; mula_hs_hs r5, r6, r7 ; ld4s r25, r26 }
{ ill ; mula_ls_ls r5, r6, r7 ; ld1u r25, r26 }
{ ill ; mulax r5, r6, r7 ; ld2s r25, r26 }
{ ill ; mz r5, r6, r7 ; ld4s r25, r26 }
{ ill ; nor r5, r6, r7 ; prefetch r25 }
{ ill ; pcnt r5, r6 ; prefetch_l1 r25 }
{ ill ; prefetch r25 ; mula_hu_hu r5, r6, r7 }
{ ill ; prefetch_l1 r25 ; clz r5, r6 }
{ ill ; prefetch_l1 r25 ; shl2add r5, r6, r7 }
{ ill ; prefetch_l1_fault r25 ; movei r5, 5 }
{ ill ; prefetch_l2 r25 ; add r5, r6, r7 }
{ ill ; prefetch_l2 r25 ; revbytes r5, r6 }
{ ill ; prefetch_l2_fault r25 ; ctz r5, r6 }
{ ill ; prefetch_l2_fault r25 ; tblidxb0 r5, r6 }
{ ill ; prefetch_l3 r25 ; mz r5, r6, r7 }
{ ill ; prefetch_l3_fault r25 ; cmples r5, r6, r7 }
{ ill ; prefetch_l3_fault r25 ; shrs r5, r6, r7 }
{ ill ; revbytes r5, r6 ; prefetch_l1_fault r25 }
{ ill ; rotli r5, r6, 5 ; prefetch_l2_fault r25 }
{ ill ; shl1add r5, r6, r7 ; prefetch_l3 r25 }
{ ill ; shl2add r5, r6, r7 ; st r25, r26 }
{ ill ; shl3add r5, r6, r7 ; st2 r25, r26 }
{ ill ; shli r5, r6, 5 }
{ ill ; shrsi r5, r6, 5 }
{ ill ; shruxi r5, r6, 5 }
{ ill ; st r25, r26 ; pcnt r5, r6 }
{ ill ; st1 r25, r26 ; cmpltu r5, r6, r7 }
{ ill ; st1 r25, r26 ; sub r5, r6, r7 }
{ ill ; st2 r25, r26 ; mulax r5, r6, r7 }
{ ill ; st4 r25, r26 ; cmpeq r5, r6, r7 }
{ ill ; st4 r25, r26 ; shl3addx r5, r6, r7 }
{ ill ; subx r5, r6, r7 ; prefetch r25 }
{ ill ; tblidxb1 r5, r6 ; prefetch_l1 r25 }
{ ill ; tblidxb3 r5, r6 ; prefetch_l2 r25 }
{ ill ; v1multu r5, r6, r7 }
{ ill ; v2mz r5, r6, r7 }
{ ill ; xor r5, r6, r7 ; prefetch_l3 r25 }
{ info 19 ; add r5, r6, r7 ; prefetch_l3_fault r25 }
{ info 19 ; addi r5, r6, 5 ; st1 r25, r26 }
{ info 19 ; addx r5, r6, r7 ; st1 r25, r26 }
{ info 19 ; addxi r5, r6, 5 ; st4 r25, r26 }
{ info 19 ; and r5, r6, r7 ; st1 r25, r26 }
{ info 19 ; andi r5, r6, 5 ; st4 r25, r26 }
{ info 19 ; cmoveqz r5, r6, r7 ; st2 r25, r26 }
{ info 19 ; cmpeq r15, r16, r17 }
{ info 19 ; cmpeqi r5, r6, 5 ; ld1s r25, r26 }
{ info 19 ; cmples r5, r6, r7 ; ld1s r25, r26 }
{ info 19 ; cmpleu r5, r6, r7 ; ld2s r25, r26 }
{ info 19 ; cmplts r5, r6, r7 ; ld4s r25, r26 }
{ info 19 ; cmpltsi r5, r6, 5 ; prefetch r25 }
{ info 19 ; cmpltu r5, r6, r7 ; prefetch_l1_fault r25 }
{ info 19 ; cmpne r5, r6, r7 ; prefetch_l1_fault r25 }
{ info 19 ; dblalign2 r5, r6, r7 }
{ info 19 ; fnop ; prefetch_l3_fault r25 }
{ info 19 ; ill ; prefetch_l1 r25 }
{ info 19 ; jalr r15 ; prefetch r25 }
{ info 19 ; jr r15 ; prefetch_l1_fault r25 }
{ info 19 ; ld r25, r26 ; andi r15, r16, 5 }
{ info 19 ; ld r25, r26 ; mul_lu_lu r5, r6, r7 }
{ info 19 ; ld r25, r26 ; shrsi r5, r6, 5 }
{ info 19 ; ld1s r25, r26 ; cmplts r15, r16, r17 }
{ info 19 ; ld1s r25, r26 ; or r5, r6, r7 }
{ info 19 ; ld1s r25, r26 ; xor r15, r16, r17 }
{ info 19 ; ld1u r25, r26 ; info 19 }
{ info 19 ; ld1u r25, r26 ; shl1addx r15, r16, r17 }
{ info 19 ; ld2s r25, r26 ; addxi r5, r6, 5 }
{ info 19 ; ld2s r25, r26 ; mul_hs_hs r5, r6, r7 }
{ info 19 ; ld2s r25, r26 ; shrs r15, r16, r17 }
{ info 19 ; ld2u r25, r26 ; cmples r15, r16, r17 }
{ info 19 ; ld2u r25, r26 ; nop }
{ info 19 ; ld2u r25, r26 ; tblidxb0 r5, r6 }
{ info 19 ; ld4s r25, r26 ; ctz r5, r6 }
{ info 19 ; ld4s r25, r26 ; shl r15, r16, r17 }
{ info 19 ; ld4u r25, r26 ; addi r5, r6, 5 }
{ info 19 ; ld4u r25, r26 ; move r15, r16 }
{ info 19 ; ld4u r25, r26 ; shl3addx r15, r16, r17 }
{ info 19 ; ldnt_add r15, r16, 5 }
{ info 19 ; mnz r15, r16, r17 ; st4 r25, r26 }
{ info 19 ; move r5, r6 ; ld r25, r26 }
{ info 19 ; movei r5, 5 ; ld1u r25, r26 }
{ info 19 ; mul_hs_ls r5, r6, r7 }
{ info 19 ; mul_ls_ls r5, r6, r7 ; st4 r25, r26 }
{ info 19 ; mula_hs_hs r5, r6, r7 }
{ info 19 ; mula_ls_ls r5, r6, r7 ; st1 r25, r26 }
{ info 19 ; mulax r5, r6, r7 ; st2 r25, r26 }
{ info 19 ; mz r15, r16, r17 }
{ info 19 ; nor r15, r16, r17 ; ld1s r25, r26 }
{ info 19 ; or r15, r16, r17 ; ld2s r25, r26 }
{ info 19 ; pcnt r5, r6 ; ld2s r25, r26 }
{ info 19 ; prefetch r25 ; cmplts r15, r16, r17 }
{ info 19 ; prefetch r25 ; or r5, r6, r7 }
{ info 19 ; prefetch r25 ; xor r15, r16, r17 }
{ info 19 ; prefetch_l1 r25 ; cmpne r5, r6, r7 }
{ info 19 ; prefetch_l1 r25 ; rotli r5, r6, 5 }
{ info 19 ; prefetch_l1_fault r25 ; addi r5, r6, 5 }
{ info 19 ; prefetch_l1_fault r25 ; move r15, r16 }
{ info 19 ; prefetch_l1_fault r25 ; shl3addx r15, r16, r17 }
{ info 19 ; prefetch_l2 r25 ; cmpeq r5, r6, r7 }
{ info 19 ; prefetch_l2 r25 ; mulx r5, r6, r7 }
{ info 19 ; prefetch_l2 r25 ; sub r5, r6, r7 }
{ info 19 ; prefetch_l2_fault r25 ; cmpne r15, r16, r17 }
{ info 19 ; prefetch_l2_fault r25 ; rotli r15, r16, 5 }
{ info 19 ; prefetch_l3 r25 ; addi r15, r16, 5 }
{ info 19 ; prefetch_l3 r25 ; mnz r5, r6, r7 }
{ info 19 ; prefetch_l3 r25 ; shl3add r5, r6, r7 }
{ info 19 ; prefetch_l3_fault r25 ; cmpeq r15, r16, r17 }
{ info 19 ; prefetch_l3_fault r25 ; mulax r5, r6, r7 }
{ info 19 ; prefetch_l3_fault r25 ; sub r15, r16, r17 }
{ info 19 ; revbytes r5, r6 ; prefetch_l1_fault r25 }
{ info 19 ; rotl r5, r6, r7 ; prefetch_l2_fault r25 }
{ info 19 ; rotli r5, r6, 5 ; prefetch_l3_fault r25 }
{ info 19 ; shl r5, r6, r7 ; st1 r25, r26 }
{ info 19 ; shl1add r5, r6, r7 ; st1 r25, r26 }
{ info 19 ; shl1addx r5, r6, r7 ; st4 r25, r26 }
{ info 19 ; shl2addx r15, r16, r17 ; ld r25, r26 }
{ info 19 ; shl3add r15, r16, r17 ; ld1u r25, r26 }
{ info 19 ; shl3addx r15, r16, r17 ; ld2u r25, r26 }
{ info 19 ; shli r15, r16, 5 ; ld4u r25, r26 }
{ info 19 ; shrs r15, r16, r17 ; ld2u r25, r26 }
{ info 19 ; shrsi r15, r16, 5 ; ld4u r25, r26 }
{ info 19 ; shru r15, r16, r17 ; prefetch_l1 r25 }
{ info 19 ; shrui r15, r16, 5 ; prefetch_l2 r25 }
{ info 19 ; st r25, r26 ; addxi r15, r16, 5 }
{ info 19 ; st r25, r26 ; movei r5, 5 }
{ info 19 ; st r25, r26 ; shli r5, r6, 5 }
{ info 19 ; st1 r25, r26 ; cmples r15, r16, r17 }
{ info 19 ; st1 r25, r26 ; nop }
{ info 19 ; st1 r25, r26 ; tblidxb0 r5, r6 }
{ info 19 ; st2 r25, r26 ; ctz r5, r6 }
{ info 19 ; st2 r25, r26 ; shl r15, r16, r17 }
{ info 19 ; st4 r25, r26 ; addi r5, r6, 5 }
{ info 19 ; st4 r25, r26 ; move r15, r16 }
{ info 19 ; st4 r25, r26 ; shl3addx r15, r16, r17 }
{ info 19 ; sub r15, r16, r17 ; prefetch r25 }
{ info 19 ; subx r15, r16, r17 ; prefetch_l1_fault r25 }
{ info 19 ; tblidxb0 r5, r6 ; prefetch_l1_fault r25 }
{ info 19 ; tblidxb2 r5, r6 ; prefetch_l2_fault r25 }
{ info 19 ; v1cmples r5, r6, r7 }
{ info 19 ; v1mz r15, r16, r17 }
{ info 19 ; v2cmpltu r15, r16, r17 }
{ info 19 ; v2shli r5, r6, 5 }
{ info 19 ; xor r15, r16, r17 ; ld1u r25, r26 }
{ infol 0x1234 ; addi r15, r16, 5 }
{ infol 0x1234 ; cmpne r15, r16, r17 }
{ infol 0x1234 ; flushwb }
{ infol 0x1234 ; ldnt2s r15, r16 }
{ infol 0x1234 ; mula_ls_lu r5, r6, r7 }
{ infol 0x1234 ; shl1addx r15, r16, r17 }
{ infol 0x1234 ; stnt2 r15, r16 }
{ infol 0x1234 ; v1cmpne r5, r6, r7 }
{ infol 0x1234 ; v1shru r15, r16, r17 }
{ infol 0x1234 ; v2maxs r15, r16, r17 }
{ infol 0x1234 ; v2sub r5, r6, r7 }
{ inv r15 ; bfextu r5, r6, 5, 7 }
{ inv r15 ; fsingle_mul2 r5, r6, r7 }
{ inv r15 ; revbytes r5, r6 }
{ inv r15 ; v1cmpltui r5, r6, 5 }
{ inv r15 ; v2cmples r5, r6, r7 }
{ inv r15 ; v4packsc r5, r6, r7 }
{ iret ; crc32_32 r5, r6, r7 }
{ iret ; mula_hs_hs r5, r6, r7 }
{ iret ; sub r5, r6, r7 }
{ iret ; v1mulus r5, r6, r7 }
{ iret ; v2packl r5, r6, r7 }
{ jalr r15 ; add r5, r6, r7 ; prefetch_l3 r25 }
{ jalr r15 ; addx r5, r6, r7 ; prefetch_l3_fault r25 }
{ jalr r15 ; and r5, r6, r7 ; prefetch_l3_fault r25 }
{ jalr r15 ; clz r5, r6 ; prefetch_l3 r25 }
{ jalr r15 ; cmovnez r5, r6, r7 ; st r25, r26 }
{ jalr r15 ; cmpeqi r5, r6, 5 ; st2 r25, r26 }
{ jalr r15 ; cmpleu r5, r6, r7 }
{ jalr r15 ; cmpltu r5, r6, r7 ; ld1s r25, r26 }
{ jalr r15 ; cmulaf r5, r6, r7 }
{ jalr r15 ; fnop ; ld1u r25, r26 }
{ jalr r15 ; fsingle_pack2 r5, r6, r7 }
{ jalr r15 ; ld r25, r26 ; fnop }
{ jalr r15 ; ld r25, r26 ; tblidxb1 r5, r6 }
{ jalr r15 ; ld1s r25, r26 ; nop }
{ jalr r15 ; ld1u r25, r26 ; cmpleu r5, r6, r7 }
{ jalr r15 ; ld1u r25, r26 ; shrsi r5, r6, 5 }
{ jalr r15 ; ld2s r25, r26 ; mula_hu_hu r5, r6, r7 }
{ jalr r15 ; ld2u r25, r26 ; clz r5, r6 }
{ jalr r15 ; ld2u r25, r26 ; shl2add r5, r6, r7 }
{ jalr r15 ; ld4s r25, r26 ; movei r5, 5 }
{ jalr r15 ; ld4u r25, r26 ; add r5, r6, r7 }
{ jalr r15 ; ld4u r25, r26 ; revbytes r5, r6 }
{ jalr r15 ; mnz r5, r6, r7 ; st2 r25, r26 }
{ jalr r15 ; movei r5, 5 }
{ jalr r15 ; mul_hu_hu r5, r6, r7 ; st2 r25, r26 }
{ jalr r15 ; mul_lu_lu r5, r6, r7 ; st1 r25, r26 }
{ jalr r15 ; mula_hu_hu r5, r6, r7 ; st r25, r26 }
{ jalr r15 ; mula_lu_lu r5, r6, r7 ; prefetch_l3_fault r25 }
{ jalr r15 ; mulx r5, r6, r7 ; st1 r25, r26 }
{ jalr r15 ; nop ; st4 r25, r26 }
{ jalr r15 ; ori r5, r6, 5 }
{ jalr r15 ; prefetch r25 ; info 19 }
{ jalr r15 ; prefetch r25 ; tblidxb3 r5, r6 }
{ jalr r15 ; prefetch_l1 r25 ; or r5, r6, r7 }
{ jalr r15 ; prefetch_l1_fault r25 ; cmpltsi r5, r6, 5 }
{ jalr r15 ; prefetch_l1_fault r25 ; shrui r5, r6, 5 }
{ jalr r15 ; prefetch_l2 r25 ; mula_lu_lu r5, r6, r7 }
{ jalr r15 ; prefetch_l2_fault r25 ; cmovnez r5, r6, r7 }
{ jalr r15 ; prefetch_l2_fault r25 ; shl3add r5, r6, r7 }
{ jalr r15 ; prefetch_l3 r25 ; mul_hu_hu r5, r6, r7 }
{ jalr r15 ; prefetch_l3_fault r25 ; addx r5, r6, r7 }
{ jalr r15 ; prefetch_l3_fault r25 ; rotli r5, r6, 5 }
{ jalr r15 ; revbytes r5, r6 ; ld r25, r26 }
{ jalr r15 ; rotli r5, r6, 5 ; ld1u r25, r26 }
{ jalr r15 ; shl1add r5, r6, r7 ; ld2s r25, r26 }
{ jalr r15 ; shl2add r5, r6, r7 ; ld4s r25, r26 }
{ jalr r15 ; shl3add r5, r6, r7 ; prefetch r25 }
{ jalr r15 ; shli r5, r6, 5 ; prefetch_l1_fault r25 }
{ jalr r15 ; shrsi r5, r6, 5 ; prefetch_l1_fault r25 }
{ jalr r15 ; shrui r5, r6, 5 ; prefetch_l2_fault r25 }
{ jalr r15 ; st r25, r26 ; mula_hu_hu r5, r6, r7 }
{ jalr r15 ; st1 r25, r26 ; clz r5, r6 }
{ jalr r15 ; st1 r25, r26 ; shl2add r5, r6, r7 }
{ jalr r15 ; st2 r25, r26 ; movei r5, 5 }
{ jalr r15 ; st4 r25, r26 ; add r5, r6, r7 }
{ jalr r15 ; st4 r25, r26 ; revbytes r5, r6 }
{ jalr r15 ; sub r5, r6, r7 ; st4 r25, r26 }
{ jalr r15 ; tblidxb0 r5, r6 }
{ jalr r15 ; tblidxb3 r5, r6 ; ld1s r25, r26 }
{ jalr r15 ; v1dotpus r5, r6, r7 }
{ jalr r15 ; v2int_l r5, r6, r7 }
{ jalr r15 ; xor r5, r6, r7 ; ld2s r25, r26 }
{ jalrp r15 ; addi r5, r6, 5 ; ld2u r25, r26 }
{ jalrp r15 ; addxi r5, r6, 5 ; ld4s r25, r26 }
{ jalrp r15 ; andi r5, r6, 5 ; ld4s r25, r26 }
{ jalrp r15 ; cmoveqz r5, r6, r7 ; ld2u r25, r26 }
{ jalrp r15 ; cmpeq r5, r6, r7 ; ld4u r25, r26 }
{ jalrp r15 ; cmples r5, r6, r7 ; prefetch_l1 r25 }
{ jalrp r15 ; cmplts r5, r6, r7 ; prefetch_l2 r25 }
{ jalrp r15 ; cmpltu r5, r6, r7 ; prefetch_l3 r25 }
{ jalrp r15 ; ctz r5, r6 ; ld2u r25, r26 }
{ jalrp r15 ; fnop ; prefetch_l3_fault r25 }
{ jalrp r15 ; info 19 ; prefetch_l1_fault r25 }
{ jalrp r15 ; ld r25, r26 ; mula_hu_hu r5, r6, r7 }
{ jalrp r15 ; ld1s r25, r26 ; clz r5, r6 }
{ jalrp r15 ; ld1s r25, r26 ; shl2add r5, r6, r7 }
{ jalrp r15 ; ld1u r25, r26 ; movei r5, 5 }
{ jalrp r15 ; ld2s r25, r26 ; add r5, r6, r7 }
{ jalrp r15 ; ld2s r25, r26 ; revbytes r5, r6 }
{ jalrp r15 ; ld2u r25, r26 ; ctz r5, r6 }
{ jalrp r15 ; ld2u r25, r26 ; tblidxb0 r5, r6 }
{ jalrp r15 ; ld4s r25, r26 ; mz r5, r6, r7 }
{ jalrp r15 ; ld4u r25, r26 ; cmples r5, r6, r7 }
{ jalrp r15 ; ld4u r25, r26 ; shrs r5, r6, r7 }
{ jalrp r15 ; move r5, r6 ; prefetch_l1 r25 }
{ jalrp r15 ; mul_hs_hs r5, r6, r7 ; prefetch_l1_fault r25 }
{ jalrp r15 ; mul_ls_ls r5, r6, r7 ; ld4u r25, r26 }
{ jalrp r15 ; mula_hs_hs r5, r6, r7 ; prefetch r25 }
{ jalrp r15 ; mula_ls_ls r5, r6, r7 ; ld2u r25, r26 }
{ jalrp r15 ; mulax r5, r6, r7 ; ld4s r25, r26 }
{ jalrp r15 ; mz r5, r6, r7 ; prefetch r25 }
{ jalrp r15 ; nor r5, r6, r7 ; prefetch_l1_fault r25 }
{ jalrp r15 ; pcnt r5, r6 ; prefetch_l2 r25 }
{ jalrp r15 ; prefetch r25 ; mula_lu_lu r5, r6, r7 }
{ jalrp r15 ; prefetch_l1 r25 ; cmovnez r5, r6, r7 }
{ jalrp r15 ; prefetch_l1 r25 ; shl3add r5, r6, r7 }
{ jalrp r15 ; prefetch_l1_fault r25 ; mul_hu_hu r5, r6, r7 }
{ jalrp r15 ; prefetch_l2 r25 ; addx r5, r6, r7 }
{ jalrp r15 ; prefetch_l2 r25 ; rotli r5, r6, 5 }
{ jalrp r15 ; prefetch_l2_fault r25 ; fsingle_pack1 r5, r6 }
{ jalrp r15 ; prefetch_l2_fault r25 ; tblidxb2 r5, r6 }
{ jalrp r15 ; prefetch_l3 r25 ; nor r5, r6, r7 }
{ jalrp r15 ; prefetch_l3_fault r25 ; cmplts r5, r6, r7 }
{ jalrp r15 ; prefetch_l3_fault r25 ; shru r5, r6, r7 }
{ jalrp r15 ; revbytes r5, r6 ; prefetch_l2_fault r25 }
{ jalrp r15 ; rotli r5, r6, 5 ; prefetch_l3_fault r25 }
{ jalrp r15 ; shl1add r5, r6, r7 ; st r25, r26 }
{ jalrp r15 ; shl2add r5, r6, r7 ; st2 r25, r26 }
{ jalrp r15 ; shl3add r5, r6, r7 }
{ jalrp r15 ; shlxi r5, r6, 5 }
{ jalrp r15 ; shru r5, r6, r7 ; ld1s r25, r26 }
{ jalrp r15 ; st r25, r26 ; add r5, r6, r7 }
{ jalrp r15 ; st r25, r26 ; revbytes r5, r6 }
{ jalrp r15 ; st1 r25, r26 ; ctz r5, r6 }
{ jalrp r15 ; st1 r25, r26 ; tblidxb0 r5, r6 }
{ jalrp r15 ; st2 r25, r26 ; mz r5, r6, r7 }
{ jalrp r15 ; st4 r25, r26 ; cmples r5, r6, r7 }
{ jalrp r15 ; st4 r25, r26 ; shrs r5, r6, r7 }
{ jalrp r15 ; subx r5, r6, r7 ; prefetch_l1_fault r25 }
{ jalrp r15 ; tblidxb1 r5, r6 ; prefetch_l2 r25 }
{ jalrp r15 ; tblidxb3 r5, r6 ; prefetch_l3 r25 }
{ jalrp r15 ; v1mulus r5, r6, r7 }
{ jalrp r15 ; v2packl r5, r6, r7 }
{ jalrp r15 ; xor r5, r6, r7 ; st r25, r26 }
{ jr r15 ; addi r5, r6, 5 ; st1 r25, r26 }
{ jr r15 ; addxi r5, r6, 5 ; st2 r25, r26 }
{ jr r15 ; andi r5, r6, 5 ; st2 r25, r26 }
{ jr r15 ; cmoveqz r5, r6, r7 ; st1 r25, r26 }
{ jr r15 ; cmpeq r5, r6, r7 ; st4 r25, r26 }
{ jr r15 ; cmpleu r5, r6, r7 ; ld r25, r26 }
{ jr r15 ; cmpltsi r5, r6, 5 ; ld1u r25, r26 }
{ jr r15 ; cmpne r5, r6, r7 ; ld2s r25, r26 }
{ jr r15 ; ctz r5, r6 ; st1 r25, r26 }
{ jr r15 ; fsingle_pack1 r5, r6 ; ld1s r25, r26 }
{ jr r15 ; ld r25, r26 ; add r5, r6, r7 }
{ jr r15 ; ld r25, r26 ; revbytes r5, r6 }
{ jr r15 ; ld1s r25, r26 ; ctz r5, r6 }
{ jr r15 ; ld1s r25, r26 ; tblidxb0 r5, r6 }
{ jr r15 ; ld1u r25, r26 ; mz r5, r6, r7 }
{ jr r15 ; ld2s r25, r26 ; cmples r5, r6, r7 }
{ jr r15 ; ld2s r25, r26 ; shrs r5, r6, r7 }
{ jr r15 ; ld2u r25, r26 ; mula_hs_hs r5, r6, r7 }
{ jr r15 ; ld4s r25, r26 ; andi r5, r6, 5 }
{ jr r15 ; ld4s r25, r26 ; shl1addx r5, r6, r7 }
{ jr r15 ; ld4u r25, r26 ; move r5, r6 }
{ jr r15 ; ld4u r25, r26 }
{ jr r15 ; movei r5, 5 ; ld r25, r26 }
{ jr r15 ; mul_hs_ls r5, r6, r7 }
{ jr r15 ; mul_ls_ls r5, r6, r7 ; st4 r25, r26 }
{ jr r15 ; mula_hs_hs r5, r6, r7 }
{ jr r15 ; mula_ls_ls r5, r6, r7 ; st1 r25, r26 }
{ jr r15 ; mulax r5, r6, r7 ; st2 r25, r26 }
{ jr r15 ; mz r5, r6, r7 }
{ jr r15 ; or r5, r6, r7 ; ld1s r25, r26 }
{ jr r15 ; prefetch r25 ; addx r5, r6, r7 }
{ jr r15 ; prefetch r25 ; rotli r5, r6, 5 }
{ jr r15 ; prefetch_l1 r25 ; fsingle_pack1 r5, r6 }
{ jr r15 ; prefetch_l1 r25 ; tblidxb2 r5, r6 }
{ jr r15 ; prefetch_l1_fault r25 ; nor r5, r6, r7 }
{ jr r15 ; prefetch_l2 r25 ; cmplts r5, r6, r7 }
{ jr r15 ; prefetch_l2 r25 ; shru r5, r6, r7 }
{ jr r15 ; prefetch_l2_fault r25 ; mula_ls_ls r5, r6, r7 }
{ jr r15 ; prefetch_l3 r25 ; cmoveqz r5, r6, r7 }
{ jr r15 ; prefetch_l3 r25 ; shl2addx r5, r6, r7 }
{ jr r15 ; prefetch_l3_fault r25 ; mul_hs_hs r5, r6, r7 }
{ jr r15 ; revbits r5, r6 ; ld1s r25, r26 }
{ jr r15 ; rotl r5, r6, r7 ; ld2s r25, r26 }
{ jr r15 ; shl r5, r6, r7 ; ld4s r25, r26 }
{ jr r15 ; shl1addx r5, r6, r7 ; ld4u r25, r26 }
{ jr r15 ; shl2addx r5, r6, r7 ; prefetch_l1 r25 }
{ jr r15 ; shl3addx r5, r6, r7 ; prefetch_l2 r25 }
{ jr r15 ; shrs r5, r6, r7 ; prefetch_l2 r25 }
{ jr r15 ; shru r5, r6, r7 ; prefetch_l3 r25 }
{ jr r15 ; st r25, r26 ; cmples r5, r6, r7 }
{ jr r15 ; st r25, r26 ; shrs r5, r6, r7 }
{ jr r15 ; st1 r25, r26 ; mula_hs_hs r5, r6, r7 }
{ jr r15 ; st2 r25, r26 ; andi r5, r6, 5 }
{ jr r15 ; st2 r25, r26 ; shl1addx r5, r6, r7 }
{ jr r15 ; st4 r25, r26 ; move r5, r6 }
{ jr r15 ; st4 r25, r26 }
{ jr r15 ; tblidxb0 r5, r6 ; ld r25, r26 }
{ jr r15 ; tblidxb2 r5, r6 ; ld1u r25, r26 }
{ jr r15 ; v1avgu r5, r6, r7 }
{ jr r15 ; v1subuc r5, r6, r7 }
{ jr r15 ; v2shru r5, r6, r7 }
{ jrp r15 ; add r5, r6, r7 ; ld4s r25, r26 }
{ jrp r15 ; addx r5, r6, r7 ; ld4u r25, r26 }
{ jrp r15 ; and r5, r6, r7 ; ld4u r25, r26 }
{ jrp r15 ; clz r5, r6 ; ld4s r25, r26 }
{ jrp r15 ; cmovnez r5, r6, r7 ; prefetch r25 }
{ jrp r15 ; cmpeqi r5, r6, 5 ; prefetch_l1_fault r25 }
{ jrp r15 ; cmpleu r5, r6, r7 ; prefetch_l2_fault r25 }
{ jrp r15 ; cmpltsi r5, r6, 5 ; prefetch_l3_fault r25 }
{ jrp r15 ; cmpne r5, r6, r7 ; st r25, r26 }
{ jrp r15 ; fdouble_pack1 r5, r6, r7 }
{ jrp r15 ; fsingle_pack1 r5, r6 ; prefetch_l3 r25 }
{ jrp r15 ; ld r25, r26 ; cmples r5, r6, r7 }
{ jrp r15 ; ld r25, r26 ; shrs r5, r6, r7 }
{ jrp r15 ; ld1s r25, r26 ; mula_hs_hs r5, r6, r7 }
{ jrp r15 ; ld1u r25, r26 ; andi r5, r6, 5 }
{ jrp r15 ; ld1u r25, r26 ; shl1addx r5, r6, r7 }
{ jrp r15 ; ld2s r25, r26 ; move r5, r6 }
{ jrp r15 ; ld2s r25, r26 }
{ jrp r15 ; ld2u r25, r26 ; revbits r5, r6 }
{ jrp r15 ; ld4s r25, r26 ; cmpne r5, r6, r7 }
{ jrp r15 ; ld4s r25, r26 ; subx r5, r6, r7 }
{ jrp r15 ; ld4u r25, r26 ; mulx r5, r6, r7 }
{ jrp r15 ; mnz r5, r6, r7 ; prefetch_l1_fault r25 }
{ jrp r15 ; movei r5, 5 ; prefetch_l2_fault r25 }
{ jrp r15 ; mul_hu_hu r5, r6, r7 ; prefetch_l1_fault r25 }
{ jrp r15 ; mul_lu_lu r5, r6, r7 ; prefetch_l1 r25 }
{ jrp r15 ; mula_hu_hu r5, r6, r7 ; prefetch r25 }
{ jrp r15 ; mula_lu_lu r5, r6, r7 ; ld4u r25, r26 }
{ jrp r15 ; mulx r5, r6, r7 ; prefetch_l1 r25 }
{ jrp r15 ; nop ; prefetch_l2 r25 }
{ jrp r15 ; or r5, r6, r7 ; prefetch_l3 r25 }
{ jrp r15 ; prefetch r25 ; cmplts r5, r6, r7 }
{ jrp r15 ; prefetch r25 ; shru r5, r6, r7 }
{ jrp r15 ; prefetch_l1 r25 ; mula_ls_ls r5, r6, r7 }
{ jrp r15 ; prefetch_l1_fault r25 ; cmoveqz r5, r6, r7 }
{ jrp r15 ; prefetch_l1_fault r25 ; shl2addx r5, r6, r7 }
{ jrp r15 ; prefetch_l2 r25 ; mul_hs_hs r5, r6, r7 }
{ jrp r15 ; prefetch_l2_fault r25 ; addi r5, r6, 5 }
{ jrp r15 ; prefetch_l2_fault r25 ; rotl r5, r6, r7 }
{ jrp r15 ; prefetch_l3 r25 ; fnop }
{ jrp r15 ; prefetch_l3 r25 ; tblidxb1 r5, r6 }
{ jrp r15 ; prefetch_l3_fault r25 ; nop }
{ jrp r15 ; revbits r5, r6 ; prefetch_l3 r25 }
{ jrp r15 ; rotl r5, r6, r7 ; st r25, r26 }
{ jrp r15 ; shl r5, r6, r7 ; st2 r25, r26 }
{ jrp r15 ; shl1addx r5, r6, r7 ; st4 r25, r26 }
{ jrp r15 ; shl3add r5, r6, r7 ; ld r25, r26 }
{ jrp r15 ; shli r5, r6, 5 ; ld1u r25, r26 }
{ jrp r15 ; shrsi r5, r6, 5 ; ld1u r25, r26 }
{ jrp r15 ; shrui r5, r6, 5 ; ld2u r25, r26 }
{ jrp r15 ; st r25, r26 ; move r5, r6 }
{ jrp r15 ; st r25, r26 }
{ jrp r15 ; st1 r25, r26 ; revbits r5, r6 }
{ jrp r15 ; st2 r25, r26 ; cmpne r5, r6, r7 }
{ jrp r15 ; st2 r25, r26 ; subx r5, r6, r7 }
{ jrp r15 ; st4 r25, r26 ; mulx r5, r6, r7 }
{ jrp r15 ; sub r5, r6, r7 ; prefetch_l2 r25 }
{ jrp r15 ; tblidxb0 r5, r6 ; prefetch_l2_fault r25 }
{ jrp r15 ; tblidxb2 r5, r6 ; prefetch_l3_fault r25 }
{ jrp r15 ; v1ddotpua r5, r6, r7 }
{ jrp r15 ; v2cmpltsi r5, r6, 5 }
{ jrp r15 ; v4shrs r5, r6, r7 }
{ ld r15, r16 ; cmpeqi r5, r6, 5 }
{ ld r15, r16 ; mm r5, r6, 5, 7 }
{ ld r15, r16 ; shl1addx r5, r6, r7 }
{ ld r15, r16 ; v1dotp r5, r6, r7 }
{ ld r15, r16 ; v2cmpne r5, r6, r7 }
{ ld r15, r16 ; v4subsc r5, r6, r7 }
{ ld r25, r26 ; add r15, r16, r17 ; or r5, r6, r7 }
{ ld r25, r26 ; add r5, r6, r7 ; fnop }
{ ld r25, r26 ; addi r15, r16, 5 ; cmoveqz r5, r6, r7 }
{ ld r25, r26 ; addi r15, r16, 5 ; shl2addx r5, r6, r7 }
{ ld r25, r26 ; addi r5, r6, 5 ; movei r15, 5 }
{ ld r25, r26 ; addx r15, r16, r17 ; ctz r5, r6 }
{ ld r25, r26 ; addx r15, r16, r17 ; tblidxb0 r5, r6 }
{ ld r25, r26 ; addx r5, r6, r7 ; shl2add r15, r16, r17 }
{ ld r25, r26 ; addxi r15, r16, 5 ; mul_lu_lu r5, r6, r7 }
{ ld r25, r26 ; addxi r5, r6, 5 ; and r15, r16, r17 }
{ ld r25, r26 ; addxi r5, r6, 5 ; subx r15, r16, r17 }
{ ld r25, r26 ; and r15, r16, r17 ; or r5, r6, r7 }
{ ld r25, r26 ; and r5, r6, r7 ; fnop }
{ ld r25, r26 ; andi r15, r16, 5 ; cmoveqz r5, r6, r7 }
{ ld r25, r26 ; andi r15, r16, 5 ; shl2addx r5, r6, r7 }
{ ld r25, r26 ; andi r5, r6, 5 ; movei r15, 5 }
{ ld r25, r26 ; clz r5, r6 ; jalr r15 }
{ ld r25, r26 ; cmoveqz r5, r6, r7 ; cmplts r15, r16, r17 }
{ ld r25, r26 ; cmovnez r5, r6, r7 ; addxi r15, r16, 5 }
{ ld r25, r26 ; cmovnez r5, r6, r7 ; sub r15, r16, r17 }
{ ld r25, r26 ; cmpeq r15, r16, r17 ; nor r5, r6, r7 }
{ ld r25, r26 ; cmpeq r5, r6, r7 ; cmpne r15, r16, r17 }
{ ld r25, r26 ; cmpeqi r15, r16, 5 ; clz r5, r6 }
{ ld r25, r26 ; cmpeqi r15, r16, 5 ; shl2add r5, r6, r7 }
{ ld r25, r26 ; cmpeqi r5, r6, 5 ; move r15, r16 }
{ ld r25, r26 ; cmples r15, r16, r17 ; cmpne r5, r6, r7 }
{ ld r25, r26 ; cmples r15, r16, r17 ; subx r5, r6, r7 }
{ ld r25, r26 ; cmples r5, r6, r7 ; shl1addx r15, r16, r17 }
{ ld r25, r26 ; cmpleu r15, r16, r17 ; mul_ls_ls r5, r6, r7 }
{ ld r25, r26 ; cmpleu r5, r6, r7 ; addxi r15, r16, 5 }
{ ld r25, r26 ; cmpleu r5, r6, r7 ; sub r15, r16, r17 }
{ ld r25, r26 ; cmplts r15, r16, r17 ; nor r5, r6, r7 }
{ ld r25, r26 ; cmplts r5, r6, r7 ; cmpne r15, r16, r17 }
{ ld r25, r26 ; cmpltsi r15, r16, 5 ; clz r5, r6 }
{ ld r25, r26 ; cmpltsi r15, r16, 5 ; shl2add r5, r6, r7 }
{ ld r25, r26 ; cmpltsi r5, r6, 5 ; move r15, r16 }
{ ld r25, r26 ; cmpltu r15, r16, r17 ; cmpne r5, r6, r7 }
{ ld r25, r26 ; cmpltu r15, r16, r17 ; subx r5, r6, r7 }
{ ld r25, r26 ; cmpltu r5, r6, r7 ; shl1addx r15, r16, r17 }
{ ld r25, r26 ; cmpne r15, r16, r17 ; mul_ls_ls r5, r6, r7 }
{ ld r25, r26 ; cmpne r5, r6, r7 ; addxi r15, r16, 5 }
{ ld r25, r26 ; cmpne r5, r6, r7 ; sub r15, r16, r17 }
{ ld r25, r26 ; ctz r5, r6 ; shl3add r15, r16, r17 }
{ ld r25, r26 ; fnop ; cmpne r15, r16, r17 }
{ ld r25, r26 ; fnop ; rotli r15, r16, 5 }
{ ld r25, r26 ; fsingle_pack1 r5, r6 ; addxi r15, r16, 5 }
{ ld r25, r26 ; fsingle_pack1 r5, r6 ; sub r15, r16, r17 }
{ ld r25, r26 ; ill ; nor r5, r6, r7 }
{ ld r25, r26 ; info 19 ; cmoveqz r5, r6, r7 }
{ ld r25, r26 ; info 19 ; mula_ls_ls r5, r6, r7 }
{ ld r25, r26 ; info 19 ; shrui r15, r16, 5 }
{ ld r25, r26 ; jalr r15 ; mul_lu_lu r5, r6, r7 }
{ ld r25, r26 ; jalrp r15 ; and r5, r6, r7 }
{ ld r25, r26 ; jalrp r15 ; shl1add r5, r6, r7 }
{ ld r25, r26 ; jr r15 ; mnz r5, r6, r7 }
{ ld r25, r26 ; jr r15 ; xor r5, r6, r7 }
{ ld r25, r26 ; jrp r15 ; pcnt r5, r6 }
{ ld r25, r26 ; lnk r15 ; cmpltu r5, r6, r7 }
{ ld r25, r26 ; lnk r15 ; sub r5, r6, r7 }
{ ld r25, r26 ; mnz r15, r16, r17 ; mulax r5, r6, r7 }
{ ld r25, r26 ; mnz r5, r6, r7 ; cmpleu r15, r16, r17 }
{ ld r25, r26 ; move r15, r16 ; addx r5, r6, r7 }
{ ld r25, r26 ; move r15, r16 ; rotli r5, r6, 5 }
{ ld r25, r26 ; move r5, r6 ; jr r15 }
{ ld r25, r26 ; movei r15, 5 ; cmpleu r5, r6, r7 }
{ ld r25, r26 ; movei r15, 5 ; shrsi r5, r6, 5 }
{ ld r25, r26 ; movei r5, 5 ; rotl r15, r16, r17 }
{ ld r25, r26 ; mul_hs_hs r5, r6, r7 ; mnz r15, r16, r17 }
{ ld r25, r26 ; mul_hu_hu r5, r6, r7 ; ill }
{ ld r25, r26 ; mul_ls_ls r5, r6, r7 ; cmples r15, r16, r17 }
{ ld r25, r26 ; mul_lu_lu r5, r6, r7 ; addi r15, r16, 5 }
{ ld r25, r26 ; mul_lu_lu r5, r6, r7 ; shru r15, r16, r17 }
{ ld r25, r26 ; mula_hs_hs r5, r6, r7 ; shl2add r15, r16, r17 }
{ ld r25, r26 ; mula_hu_hu r5, r6, r7 ; nor r15, r16, r17 }
{ ld r25, r26 ; mula_ls_ls r5, r6, r7 ; jrp r15 }
{ ld r25, r26 ; mula_lu_lu r5, r6, r7 ; cmpne r15, r16, r17 }
{ ld r25, r26 ; mulax r5, r6, r7 ; cmpeq r15, r16, r17 }
{ ld r25, r26 ; mulax r5, r6, r7 }
{ ld r25, r26 ; mulx r5, r6, r7 ; shrs r15, r16, r17 }
{ ld r25, r26 ; mz r15, r16, r17 ; mulax r5, r6, r7 }
{ ld r25, r26 ; mz r5, r6, r7 ; cmpleu r15, r16, r17 }
{ ld r25, r26 ; nop ; addi r15, r16, 5 }
{ ld r25, r26 ; nop ; mnz r5, r6, r7 }
{ ld r25, r26 ; nop ; shl3add r5, r6, r7 }
{ ld r25, r26 ; nor r15, r16, r17 ; cmpne r5, r6, r7 }
{ ld r25, r26 ; nor r15, r16, r17 ; subx r5, r6, r7 }
{ ld r25, r26 ; nor r5, r6, r7 ; shl1addx r15, r16, r17 }
{ ld r25, r26 ; or r15, r16, r17 ; mul_ls_ls r5, r6, r7 }
{ ld r25, r26 ; or r5, r6, r7 ; addxi r15, r16, 5 }
{ ld r25, r26 ; or r5, r6, r7 ; sub r15, r16, r17 }
{ ld r25, r26 ; pcnt r5, r6 ; shl3add r15, r16, r17 }
{ ld r25, r26 ; revbits r5, r6 ; rotl r15, r16, r17 }
{ ld r25, r26 ; revbytes r5, r6 ; mnz r15, r16, r17 }
{ ld r25, r26 ; rotl r15, r16, r17 ; cmpltu r5, r6, r7 }
{ ld r25, r26 ; rotl r15, r16, r17 ; sub r5, r6, r7 }
{ ld r25, r26 ; rotl r5, r6, r7 ; shl1add r15, r16, r17 }
{ ld r25, r26 ; rotli r15, r16, 5 ; mul_hu_hu r5, r6, r7 }
{ ld r25, r26 ; rotli r5, r6, 5 ; addx r15, r16, r17 }
{ ld r25, r26 ; rotli r5, r6, 5 ; shrui r15, r16, 5 }
{ ld r25, r26 ; shl r15, r16, r17 ; nop }
{ ld r25, r26 ; shl r5, r6, r7 ; cmpltu r15, r16, r17 }
{ ld r25, r26 ; shl1add r15, r16, r17 ; andi r5, r6, 5 }
{ ld r25, r26 ; shl1add r15, r16, r17 ; shl1addx r5, r6, r7 }
{ ld r25, r26 ; shl1add r5, r6, r7 ; mnz r15, r16, r17 }
{ ld r25, r26 ; shl1addx r15, r16, r17 ; cmpltu r5, r6, r7 }
{ ld r25, r26 ; shl1addx r15, r16, r17 ; sub r5, r6, r7 }
{ ld r25, r26 ; shl1addx r5, r6, r7 ; shl1add r15, r16, r17 }
{ ld r25, r26 ; shl2add r15, r16, r17 ; mul_hu_hu r5, r6, r7 }
{ ld r25, r26 ; shl2add r5, r6, r7 ; addx r15, r16, r17 }
{ ld r25, r26 ; shl2add r5, r6, r7 ; shrui r15, r16, 5 }
{ ld r25, r26 ; shl2addx r15, r16, r17 ; nop }
{ ld r25, r26 ; shl2addx r5, r6, r7 ; cmpltu r15, r16, r17 }
{ ld r25, r26 ; shl3add r15, r16, r17 ; andi r5, r6, 5 }
{ ld r25, r26 ; shl3add r15, r16, r17 ; shl1addx r5, r6, r7 }
{ ld r25, r26 ; shl3add r5, r6, r7 ; mnz r15, r16, r17 }
{ ld r25, r26 ; shl3addx r15, r16, r17 ; cmpltu r5, r6, r7 }
{ ld r25, r26 ; shl3addx r15, r16, r17 ; sub r5, r6, r7 }
{ ld r25, r26 ; shl3addx r5, r6, r7 ; shl1add r15, r16, r17 }
{ ld r25, r26 ; shli r15, r16, 5 ; mul_hu_hu r5, r6, r7 }
{ ld r25, r26 ; shli r5, r6, 5 ; addx r15, r16, r17 }
{ ld r25, r26 ; shli r5, r6, 5 ; shrui r15, r16, 5 }
{ ld r25, r26 ; shrs r15, r16, r17 ; nop }
{ ld r25, r26 ; shrs r5, r6, r7 ; cmpltu r15, r16, r17 }
{ ld r25, r26 ; shrsi r15, r16, 5 ; andi r5, r6, 5 }
{ ld r25, r26 ; shrsi r15, r16, 5 ; shl1addx r5, r6, r7 }
{ ld r25, r26 ; shrsi r5, r6, 5 ; mnz r15, r16, r17 }
{ ld r25, r26 ; shru r15, r16, r17 ; cmpltu r5, r6, r7 }
{ ld r25, r26 ; shru r15, r16, r17 ; sub r5, r6, r7 }
{ ld r25, r26 ; shru r5, r6, r7 ; shl1add r15, r16, r17 }
{ ld r25, r26 ; shrui r15, r16, 5 ; mul_hu_hu r5, r6, r7 }
{ ld r25, r26 ; shrui r5, r6, 5 ; addx r15, r16, r17 }
{ ld r25, r26 ; shrui r5, r6, 5 ; shrui r15, r16, 5 }
{ ld r25, r26 ; sub r15, r16, r17 ; nop }
{ ld r25, r26 ; sub r5, r6, r7 ; cmpltu r15, r16, r17 }
{ ld r25, r26 ; subx r15, r16, r17 ; andi r5, r6, 5 }
{ ld r25, r26 ; subx r15, r16, r17 ; shl1addx r5, r6, r7 }
{ ld r25, r26 ; subx r5, r6, r7 ; mnz r15, r16, r17 }
{ ld r25, r26 ; tblidxb0 r5, r6 ; ill }
{ ld r25, r26 ; tblidxb1 r5, r6 ; cmples r15, r16, r17 }
{ ld r25, r26 ; tblidxb2 r5, r6 ; addi r15, r16, 5 }
{ ld r25, r26 ; tblidxb2 r5, r6 ; shru r15, r16, r17 }
{ ld r25, r26 ; tblidxb3 r5, r6 ; shl2add r15, r16, r17 }
{ ld r25, r26 ; xor r15, r16, r17 ; mul_lu_lu r5, r6, r7 }
{ ld r25, r26 ; xor r5, r6, r7 ; and r15, r16, r17 }
{ ld r25, r26 ; xor r5, r6, r7 ; subx r15, r16, r17 }
{ ld1s r15, r16 ; dblalign6 r5, r6, r7 }
{ ld1s r15, r16 ; mula_hu_lu r5, r6, r7 }
{ ld1s r15, r16 ; tblidxb3 r5, r6 }
{ ld1s r15, r16 ; v1shrs r5, r6, r7 }
{ ld1s r15, r16 ; v2shl r5, r6, r7 }
{ ld1s r25, r26 ; add r15, r16, r17 ; fnop }
{ ld1s r25, r26 ; add r15, r16, r17 ; tblidxb1 r5, r6 }
{ ld1s r25, r26 ; add r5, r6, r7 ; shl2addx r15, r16, r17 }
{ ld1s r25, r26 ; addi r15, r16, 5 ; mula_hs_hs r5, r6, r7 }
{ ld1s r25, r26 ; addi r5, r6, 5 ; andi r15, r16, 5 }
{ ld1s r25, r26 ; addi r5, r6, 5 ; xor r15, r16, r17 }
{ ld1s r25, r26 ; addx r15, r16, r17 ; pcnt r5, r6 }
{ ld1s r25, r26 ; addx r5, r6, r7 ; ill }
{ ld1s r25, r26 ; addxi r15, r16, 5 ; cmovnez r5, r6, r7 }
{ ld1s r25, r26 ; addxi r15, r16, 5 ; shl3add r5, r6, r7 }
{ ld1s r25, r26 ; addxi r5, r6, 5 ; mz r15, r16, r17 }
{ ld1s r25, r26 ; and r15, r16, r17 ; fnop }
{ ld1s r25, r26 ; and r15, r16, r17 ; tblidxb1 r5, r6 }
{ ld1s r25, r26 ; and r5, r6, r7 ; shl2addx r15, r16, r17 }
{ ld1s r25, r26 ; andi r15, r16, 5 ; mula_hs_hs r5, r6, r7 }
{ ld1s r25, r26 ; andi r5, r6, 5 ; andi r15, r16, 5 }
{ ld1s r25, r26 ; andi r5, r6, 5 ; xor r15, r16, r17 }
{ ld1s r25, r26 ; clz r5, r6 ; shli r15, r16, 5 }
{ ld1s r25, r26 ; cmoveqz r5, r6, r7 ; shl r15, r16, r17 }
{ ld1s r25, r26 ; cmovnez r5, r6, r7 ; movei r15, 5 }
{ ld1s r25, r26 ; cmpeq r15, r16, r17 ; ctz r5, r6 }
{ ld1s r25, r26 ; cmpeq r15, r16, r17 ; tblidxb0 r5, r6 }
{ ld1s r25, r26 ; cmpeq r5, r6, r7 ; shl2add r15, r16, r17 }
{ ld1s r25, r26 ; cmpeqi r15, r16, 5 ; mul_lu_lu r5, r6, r7 }
{ ld1s r25, r26 ; cmpeqi r5, r6, 5 ; and r15, r16, r17 }
{ ld1s r25, r26 ; cmpeqi r5, r6, 5 ; subx r15, r16, r17 }
{ ld1s r25, r26 ; cmples r15, r16, r17 ; or r5, r6, r7 }
{ ld1s r25, r26 ; cmples r5, r6, r7 ; fnop }
{ ld1s r25, r26 ; cmpleu r15, r16, r17 ; cmoveqz r5, r6, r7 }
{ ld1s r25, r26 ; cmpleu r15, r16, r17 ; shl2addx r5, r6, r7 }
{ ld1s r25, r26 ; cmpleu r5, r6, r7 ; movei r15, 5 }
{ ld1s r25, r26 ; cmplts r15, r16, r17 ; ctz r5, r6 }
{ ld1s r25, r26 ; cmplts r15, r16, r17 ; tblidxb0 r5, r6 }
{ ld1s r25, r26 ; cmplts r5, r6, r7 ; shl2add r15, r16, r17 }
{ ld1s r25, r26 ; cmpltsi r15, r16, 5 ; mul_lu_lu r5, r6, r7 }
{ ld1s r25, r26 ; cmpltsi r5, r6, 5 ; and r15, r16, r17 }
{ ld1s r25, r26 ; cmpltsi r5, r6, 5 ; subx r15, r16, r17 }
{ ld1s r25, r26 ; cmpltu r15, r16, r17 ; or r5, r6, r7 }
{ ld1s r25, r26 ; cmpltu r5, r6, r7 ; fnop }
{ ld1s r25, r26 ; cmpne r15, r16, r17 ; cmoveqz r5, r6, r7 }
{ ld1s r25, r26 ; cmpne r15, r16, r17 ; shl2addx r5, r6, r7 }
{ ld1s r25, r26 ; cmpne r5, r6, r7 ; movei r15, 5 }
{ ld1s r25, r26 ; ctz r5, r6 ; jalr r15 }
{ ld1s r25, r26 ; fnop ; andi r15, r16, 5 }
{ ld1s r25, r26 ; fnop ; mul_lu_lu r5, r6, r7 }
{ ld1s r25, r26 ; fnop ; shrsi r5, r6, 5 }
{ ld1s r25, r26 ; fsingle_pack1 r5, r6 ; movei r15, 5 }
{ ld1s r25, r26 ; ill ; ctz r5, r6 }
{ ld1s r25, r26 ; ill ; tblidxb0 r5, r6 }
{ ld1s r25, r26 ; info 19 ; ill }
{ ld1s r25, r26 ; info 19 ; shl1add r5, r6, r7 }
{ ld1s r25, r26 ; jalr r15 ; cmovnez r5, r6, r7 }
{ ld1s r25, r26 ; jalr r15 ; shl3add r5, r6, r7 }
{ ld1s r25, r26 ; jalrp r15 ; mul_hu_hu r5, r6, r7 }
{ ld1s r25, r26 ; jr r15 ; addx r5, r6, r7 }
{ ld1s r25, r26 ; jr r15 ; rotli r5, r6, 5 }
{ ld1s r25, r26 ; jrp r15 ; fsingle_pack1 r5, r6 }
{ ld1s r25, r26 ; jrp r15 ; tblidxb2 r5, r6 }
{ ld1s r25, r26 ; lnk r15 ; nor r5, r6, r7 }
{ ld1s r25, r26 ; mnz r15, r16, r17 ; cmplts r5, r6, r7 }
{ ld1s r25, r26 ; mnz r15, r16, r17 ; shru r5, r6, r7 }
{ ld1s r25, r26 ; mnz r5, r6, r7 ; rotli r15, r16, 5 }
{ ld1s r25, r26 ; move r15, r16 ; movei r5, 5 }
{ ld1s r25, r26 ; move r5, r6 ; add r15, r16, r17 }
{ ld1s r25, r26 ; move r5, r6 ; shrsi r15, r16, 5 }
{ ld1s r25, r26 ; movei r15, 5 ; mulx r5, r6, r7 }
{ ld1s r25, r26 ; movei r5, 5 ; cmplts r15, r16, r17 }
{ ld1s r25, r26 ; mul_hs_hs r5, r6, r7 ; addxi r15, r16, 5 }
{ ld1s r25, r26 ; mul_hs_hs r5, r6, r7 ; sub r15, r16, r17 }
{ ld1s r25, r26 ; mul_hu_hu r5, r6, r7 ; shl3add r15, r16, r17 }
{ ld1s r25, r26 ; mul_ls_ls r5, r6, r7 ; rotl r15, r16, r17 }
{ ld1s r25, r26 ; mul_lu_lu r5, r6, r7 ; mnz r15, r16, r17 }
{ ld1s r25, r26 ; mula_hs_hs r5, r6, r7 ; ill }
{ ld1s r25, r26 ; mula_hu_hu r5, r6, r7 ; cmples r15, r16, r17 }
{ ld1s r25, r26 ; mula_ls_ls r5, r6, r7 ; addi r15, r16, 5 }
{ ld1s r25, r26 ; mula_ls_ls r5, r6, r7 ; shru r15, r16, r17 }
{ ld1s r25, r26 ; mula_lu_lu r5, r6, r7 ; shl2add r15, r16, r17 }
{ ld1s r25, r26 ; mulax r5, r6, r7 ; nor r15, r16, r17 }
{ ld1s r25, r26 ; mulx r5, r6, r7 ; jrp r15 }
{ ld1s r25, r26 ; mz r15, r16, r17 ; cmplts r5, r6, r7 }
{ ld1s r25, r26 ; mz r15, r16, r17 ; shru r5, r6, r7 }
{ ld1s r25, r26 ; mz r5, r6, r7 ; rotli r15, r16, 5 }
{ ld1s r25, r26 ; nop ; cmplts r15, r16, r17 }
{ ld1s r25, r26 ; nop ; or r5, r6, r7 }
{ ld1s r25, r26 ; nop ; xor r15, r16, r17 }
{ ld1s r25, r26 ; nor r15, r16, r17 ; or r5, r6, r7 }
{ ld1s r25, r26 ; nor r5, r6, r7 ; fnop }
{ ld1s r25, r26 ; or r15, r16, r17 ; cmoveqz r5, r6, r7 }
{ ld1s r25, r26 ; or r15, r16, r17 ; shl2addx r5, r6, r7 }
{ ld1s r25, r26 ; or r5, r6, r7 ; movei r15, 5 }
{ ld1s r25, r26 ; pcnt r5, r6 ; jalr r15 }
{ ld1s r25, r26 ; revbits r5, r6 ; cmplts r15, r16, r17 }
{ ld1s r25, r26 ; revbytes r5, r6 ; addxi r15, r16, 5 }
{ ld1s r25, r26 ; revbytes r5, r6 ; sub r15, r16, r17 }
{ ld1s r25, r26 ; rotl r15, r16, r17 ; nor r5, r6, r7 }
{ ld1s r25, r26 ; rotl r5, r6, r7 ; cmpne r15, r16, r17 }
{ ld1s r25, r26 ; rotli r15, r16, 5 ; clz r5, r6 }
{ ld1s r25, r26 ; rotli r15, r16, 5 ; shl2add r5, r6, r7 }
{ ld1s r25, r26 ; rotli r5, r6, 5 ; move r15, r16 }
{ ld1s r25, r26 ; shl r15, r16, r17 ; cmpne r5, r6, r7 }
{ ld1s r25, r26 ; shl r15, r16, r17 ; subx r5, r6, r7 }
{ ld1s r25, r26 ; shl r5, r6, r7 ; shl1addx r15, r16, r17 }
{ ld1s r25, r26 ; shl1add r15, r16, r17 ; mul_ls_ls r5, r6, r7 }
{ ld1s r25, r26 ; shl1add r5, r6, r7 ; addxi r15, r16, 5 }
{ ld1s r25, r26 ; shl1add r5, r6, r7 ; sub r15, r16, r17 }
{ ld1s r25, r26 ; shl1addx r15, r16, r17 ; nor r5, r6, r7 }
{ ld1s r25, r26 ; shl1addx r5, r6, r7 ; cmpne r15, r16, r17 }
{ ld1s r25, r26 ; shl2add r15, r16, r17 ; clz r5, r6 }
{ ld1s r25, r26 ; shl2add r15, r16, r17 ; shl2add r5, r6, r7 }
{ ld1s r25, r26 ; shl2add r5, r6, r7 ; move r15, r16 }
{ ld1s r25, r26 ; shl2addx r15, r16, r17 ; cmpne r5, r6, r7 }
{ ld1s r25, r26 ; shl2addx r15, r16, r17 ; subx r5, r6, r7 }
{ ld1s r25, r26 ; shl2addx r5, r6, r7 ; shl1addx r15, r16, r17 }
{ ld1s r25, r26 ; shl3add r15, r16, r17 ; mul_ls_ls r5, r6, r7 }
{ ld1s r25, r26 ; shl3add r5, r6, r7 ; addxi r15, r16, 5 }
{ ld1s r25, r26 ; shl3add r5, r6, r7 ; sub r15, r16, r17 }
{ ld1s r25, r26 ; shl3addx r15, r16, r17 ; nor r5, r6, r7 }
{ ld1s r25, r26 ; shl3addx r5, r6, r7 ; cmpne r15, r16, r17 }
{ ld1s r25, r26 ; shli r15, r16, 5 ; clz r5, r6 }
{ ld1s r25, r26 ; shli r15, r16, 5 ; shl2add r5, r6, r7 }
{ ld1s r25, r26 ; shli r5, r6, 5 ; move r15, r16 }
{ ld1s r25, r26 ; shrs r15, r16, r17 ; cmpne r5, r6, r7 }
{ ld1s r25, r26 ; shrs r15, r16, r17 ; subx r5, r6, r7 }
{ ld1s r25, r26 ; shrs r5, r6, r7 ; shl1addx r15, r16, r17 }
{ ld1s r25, r26 ; shrsi r15, r16, 5 ; mul_ls_ls r5, r6, r7 }
{ ld1s r25, r26 ; shrsi r5, r6, 5 ; addxi r15, r16, 5 }
{ ld1s r25, r26 ; shrsi r5, r6, 5 ; sub r15, r16, r17 }
{ ld1s r25, r26 ; shru r15, r16, r17 ; nor r5, r6, r7 }
{ ld1s r25, r26 ; shru r5, r6, r7 ; cmpne r15, r16, r17 }
{ ld1s r25, r26 ; shrui r15, r16, 5 ; clz r5, r6 }
{ ld1s r25, r26 ; shrui r15, r16, 5 ; shl2add r5, r6, r7 }
{ ld1s r25, r26 ; shrui r5, r6, 5 ; move r15, r16 }
{ ld1s r25, r26 ; sub r15, r16, r17 ; cmpne r5, r6, r7 }
{ ld1s r25, r26 ; sub r15, r16, r17 ; subx r5, r6, r7 }
{ ld1s r25, r26 ; sub r5, r6, r7 ; shl1addx r15, r16, r17 }
{ ld1s r25, r26 ; subx r15, r16, r17 ; mul_ls_ls r5, r6, r7 }
{ ld1s r25, r26 ; subx r5, r6, r7 ; addxi r15, r16, 5 }
{ ld1s r25, r26 ; subx r5, r6, r7 ; sub r15, r16, r17 }
{ ld1s r25, r26 ; tblidxb0 r5, r6 ; shl3add r15, r16, r17 }
{ ld1s r25, r26 ; tblidxb1 r5, r6 ; rotl r15, r16, r17 }
{ ld1s r25, r26 ; tblidxb2 r5, r6 ; mnz r15, r16, r17 }
{ ld1s r25, r26 ; tblidxb3 r5, r6 ; ill }
{ ld1s r25, r26 ; xor r15, r16, r17 ; cmovnez r5, r6, r7 }
{ ld1s r25, r26 ; xor r15, r16, r17 ; shl3add r5, r6, r7 }
{ ld1s r25, r26 ; xor r5, r6, r7 ; mz r15, r16, r17 }
{ ld1s_add r15, r16, 5 ; cmpleu r5, r6, r7 }
{ ld1s_add r15, r16, 5 ; move r5, r6 }
{ ld1s_add r15, r16, 5 ; shl2addx r5, r6, r7 }
{ ld1s_add r15, r16, 5 ; v1dotpu r5, r6, r7 }
{ ld1s_add r15, r16, 5 ; v2dotpa r5, r6, r7 }
{ ld1s_add r15, r16, 5 ; xori r5, r6, 5 }
{ ld1u r15, r16 ; fdouble_addsub r5, r6, r7 }
{ ld1u r15, r16 ; mula_ls_lu r5, r6, r7 }
{ ld1u r15, r16 ; v1addi r5, r6, 5 }
{ ld1u r15, r16 ; v1shru r5, r6, r7 }
{ ld1u r15, r16 ; v2shlsc r5, r6, r7 }
{ ld1u r25, r26 ; add r15, r16, r17 ; info 19 }
{ ld1u r25, r26 ; add r15, r16, r17 ; tblidxb3 r5, r6 }
{ ld1u r25, r26 ; add r5, r6, r7 ; shl3addx r15, r16, r17 }
{ ld1u r25, r26 ; addi r15, r16, 5 ; mula_ls_ls r5, r6, r7 }
{ ld1u r25, r26 ; addi r5, r6, 5 ; cmpeqi r15, r16, 5 }
{ ld1u r25, r26 ; addx r15, r16, r17 ; add r5, r6, r7 }
{ ld1u r25, r26 ; addx r15, r16, r17 ; revbytes r5, r6 }
{ ld1u r25, r26 ; addx r5, r6, r7 ; jalr r15 }
{ ld1u r25, r26 ; addxi r15, r16, 5 ; cmpeqi r5, r6, 5 }
{ ld1u r25, r26 ; addxi r15, r16, 5 ; shli r5, r6, 5 }
{ ld1u r25, r26 ; addxi r5, r6, 5 ; nor r15, r16, r17 }
{ ld1u r25, r26 ; and r15, r16, r17 ; info 19 }
{ ld1u r25, r26 ; and r15, r16, r17 ; tblidxb3 r5, r6 }
{ ld1u r25, r26 ; and r5, r6, r7 ; shl3addx r15, r16, r17 }
{ ld1u r25, r26 ; andi r15, r16, 5 ; mula_ls_ls r5, r6, r7 }
{ ld1u r25, r26 ; andi r5, r6, 5 ; cmpeqi r15, r16, 5 }
{ ld1u r25, r26 ; clz r5, r6 ; add r15, r16, r17 }
{ ld1u r25, r26 ; clz r5, r6 ; shrsi r15, r16, 5 }
{ ld1u r25, r26 ; cmoveqz r5, r6, r7 ; shl1addx r15, r16, r17 }
{ ld1u r25, r26 ; cmovnez r5, r6, r7 ; nop }
{ ld1u r25, r26 ; cmpeq r15, r16, r17 ; fsingle_pack1 r5, r6 }
{ ld1u r25, r26 ; cmpeq r15, r16, r17 ; tblidxb2 r5, r6 }
{ ld1u r25, r26 ; cmpeq r5, r6, r7 ; shl3add r15, r16, r17 }
{ ld1u r25, r26 ; cmpeqi r15, r16, 5 ; mula_hu_hu r5, r6, r7 }
{ ld1u r25, r26 ; cmpeqi r5, r6, 5 ; cmpeq r15, r16, r17 }
{ ld1u r25, r26 ; cmpeqi r5, r6, 5 }
{ ld1u r25, r26 ; cmples r15, r16, r17 ; revbits r5, r6 }
{ ld1u r25, r26 ; cmples r5, r6, r7 ; info 19 }
{ ld1u r25, r26 ; cmpleu r15, r16, r17 ; cmpeq r5, r6, r7 }
{ ld1u r25, r26 ; cmpleu r15, r16, r17 ; shl3addx r5, r6, r7 }
{ ld1u r25, r26 ; cmpleu r5, r6, r7 ; nop }
{ ld1u r25, r26 ; cmplts r15, r16, r17 ; fsingle_pack1 r5, r6 }
{ ld1u r25, r26 ; cmplts r15, r16, r17 ; tblidxb2 r5, r6 }
{ ld1u r25, r26 ; cmplts r5, r6, r7 ; shl3add r15, r16, r17 }
{ ld1u r25, r26 ; cmpltsi r15, r16, 5 ; mula_hu_hu r5, r6, r7 }
{ ld1u r25, r26 ; cmpltsi r5, r6, 5 ; cmpeq r15, r16, r17 }
{ ld1u r25, r26 ; cmpltsi r5, r6, 5 }
{ ld1u r25, r26 ; cmpltu r15, r16, r17 ; revbits r5, r6 }
{ ld1u r25, r26 ; cmpltu r5, r6, r7 ; info 19 }
{ ld1u r25, r26 ; cmpne r15, r16, r17 ; cmpeq r5, r6, r7 }
{ ld1u r25, r26 ; cmpne r15, r16, r17 ; shl3addx r5, r6, r7 }
{ ld1u r25, r26 ; cmpne r5, r6, r7 ; nop }
{ ld1u r25, r26 ; ctz r5, r6 ; jr r15 }
{ ld1u r25, r26 ; fnop ; clz r5, r6 }
{ ld1u r25, r26 ; fnop ; mula_hu_hu r5, r6, r7 }
{ ld1u r25, r26 ; fnop ; shru r5, r6, r7 }
{ ld1u r25, r26 ; fsingle_pack1 r5, r6 ; nop }
{ ld1u r25, r26 ; ill ; fsingle_pack1 r5, r6 }
{ ld1u r25, r26 ; ill ; tblidxb2 r5, r6 }
{ ld1u r25, r26 ; info 19 ; jalr r15 }
{ ld1u r25, r26 ; info 19 ; shl1addx r5, r6, r7 }
{ ld1u r25, r26 ; jalr r15 ; cmpeqi r5, r6, 5 }
{ ld1u r25, r26 ; jalr r15 ; shli r5, r6, 5 }
{ ld1u r25, r26 ; jalrp r15 ; mul_lu_lu r5, r6, r7 }
{ ld1u r25, r26 ; jr r15 ; and r5, r6, r7 }
{ ld1u r25, r26 ; jr r15 ; shl1add r5, r6, r7 }
{ ld1u r25, r26 ; jrp r15 ; mnz r5, r6, r7 }
{ ld1u r25, r26 ; jrp r15 ; xor r5, r6, r7 }
{ ld1u r25, r26 ; lnk r15 ; pcnt r5, r6 }
{ ld1u r25, r26 ; mnz r15, r16, r17 ; cmpltu r5, r6, r7 }
{ ld1u r25, r26 ; mnz r15, r16, r17 ; sub r5, r6, r7 }
{ ld1u r25, r26 ; mnz r5, r6, r7 ; shl1add r15, r16, r17 }
{ ld1u r25, r26 ; move r15, r16 ; mul_hu_hu r5, r6, r7 }
{ ld1u r25, r26 ; move r5, r6 ; addx r15, r16, r17 }
{ ld1u r25, r26 ; move r5, r6 ; shrui r15, r16, 5 }
{ ld1u r25, r26 ; movei r15, 5 ; nop }
{ ld1u r25, r26 ; movei r5, 5 ; cmpltu r15, r16, r17 }
{ ld1u r25, r26 ; mul_hs_hs r5, r6, r7 ; andi r15, r16, 5 }
{ ld1u r25, r26 ; mul_hs_hs r5, r6, r7 ; xor r15, r16, r17 }
{ ld1u r25, r26 ; mul_hu_hu r5, r6, r7 ; shli r15, r16, 5 }
{ ld1u r25, r26 ; mul_ls_ls r5, r6, r7 ; shl r15, r16, r17 }
{ ld1u r25, r26 ; mul_lu_lu r5, r6, r7 ; movei r15, 5 }
{ ld1u r25, r26 ; mula_hs_hs r5, r6, r7 ; jalr r15 }
{ ld1u r25, r26 ; mula_hu_hu r5, r6, r7 ; cmplts r15, r16, r17 }
{ ld1u r25, r26 ; mula_ls_ls r5, r6, r7 ; addxi r15, r16, 5 }
{ ld1u r25, r26 ; mula_ls_ls r5, r6, r7 ; sub r15, r16, r17 }
{ ld1u r25, r26 ; mula_lu_lu r5, r6, r7 ; shl3add r15, r16, r17 }
{ ld1u r25, r26 ; mulax r5, r6, r7 ; rotl r15, r16, r17 }
{ ld1u r25, r26 ; mulx r5, r6, r7 ; mnz r15, r16, r17 }
{ ld1u r25, r26 ; mz r15, r16, r17 ; cmpltu r5, r6, r7 }
{ ld1u r25, r26 ; mz r15, r16, r17 ; sub r5, r6, r7 }
{ ld1u r25, r26 ; mz r5, r6, r7 ; shl1add r15, r16, r17 }
{ ld1u r25, r26 ; nop ; cmpltsi r15, r16, 5 }
{ ld1u r25, r26 ; nop ; revbits r5, r6 }
{ ld1u r25, r26 ; nop }
{ ld1u r25, r26 ; nor r15, r16, r17 ; revbits r5, r6 }
{ ld1u r25, r26 ; nor r5, r6, r7 ; info 19 }
{ ld1u r25, r26 ; or r15, r16, r17 ; cmpeq r5, r6, r7 }
{ ld1u r25, r26 ; or r15, r16, r17 ; shl3addx r5, r6, r7 }
{ ld1u r25, r26 ; or r5, r6, r7 ; nop }
{ ld1u r25, r26 ; pcnt r5, r6 ; jr r15 }
{ ld1u r25, r26 ; revbits r5, r6 ; cmpltu r15, r16, r17 }
{ ld1u r25, r26 ; revbytes r5, r6 ; andi r15, r16, 5 }
{ ld1u r25, r26 ; revbytes r5, r6 ; xor r15, r16, r17 }
{ ld1u r25, r26 ; rotl r15, r16, r17 ; pcnt r5, r6 }
{ ld1u r25, r26 ; rotl r5, r6, r7 ; ill }
{ ld1u r25, r26 ; rotli r15, r16, 5 ; cmovnez r5, r6, r7 }
{ ld1u r25, r26 ; rotli r15, r16, 5 ; shl3add r5, r6, r7 }
{ ld1u r25, r26 ; rotli r5, r6, 5 ; mz r15, r16, r17 }
{ ld1u r25, r26 ; shl r15, r16, r17 ; fnop }
{ ld1u r25, r26 ; shl r15, r16, r17 ; tblidxb1 r5, r6 }
{ ld1u r25, r26 ; shl r5, r6, r7 ; shl2addx r15, r16, r17 }
{ ld1u r25, r26 ; shl1add r15, r16, r17 ; mula_hs_hs r5, r6, r7 }
{ ld1u r25, r26 ; shl1add r5, r6, r7 ; andi r15, r16, 5 }
{ ld1u r25, r26 ; shl1add r5, r6, r7 ; xor r15, r16, r17 }
{ ld1u r25, r26 ; shl1addx r15, r16, r17 ; pcnt r5, r6 }
{ ld1u r25, r26 ; shl1addx r5, r6, r7 ; ill }
{ ld1u r25, r26 ; shl2add r15, r16, r17 ; cmovnez r5, r6, r7 }
{ ld1u r25, r26 ; shl2add r15, r16, r17 ; shl3add r5, r6, r7 }
{ ld1u r25, r26 ; shl2add r5, r6, r7 ; mz r15, r16, r17 }
{ ld1u r25, r26 ; shl2addx r15, r16, r17 ; fnop }
{ ld1u r25, r26 ; shl2addx r15, r16, r17 ; tblidxb1 r5, r6 }
{ ld1u r25, r26 ; shl2addx r5, r6, r7 ; shl2addx r15, r16, r17 }
{ ld1u r25, r26 ; shl3add r15, r16, r17 ; mula_hs_hs r5, r6, r7 }
{ ld1u r25, r26 ; shl3add r5, r6, r7 ; andi r15, r16, 5 }
{ ld1u r25, r26 ; shl3add r5, r6, r7 ; xor r15, r16, r17 }
{ ld1u r25, r26 ; shl3addx r15, r16, r17 ; pcnt r5, r6 }
{ ld1u r25, r26 ; shl3addx r5, r6, r7 ; ill }
{ ld1u r25, r26 ; shli r15, r16, 5 ; cmovnez r5, r6, r7 }
{ ld1u r25, r26 ; shli r15, r16, 5 ; shl3add r5, r6, r7 }
{ ld1u r25, r26 ; shli r5, r6, 5 ; mz r15, r16, r17 }
{ ld1u r25, r26 ; shrs r15, r16, r17 ; fnop }
{ ld1u r25, r26 ; shrs r15, r16, r17 ; tblidxb1 r5, r6 }
{ ld1u r25, r26 ; shrs r5, r6, r7 ; shl2addx r15, r16, r17 }
{ ld1u r25, r26 ; shrsi r15, r16, 5 ; mula_hs_hs r5, r6, r7 }
{ ld1u r25, r26 ; shrsi r5, r6, 5 ; andi r15, r16, 5 }
{ ld1u r25, r26 ; shrsi r5, r6, 5 ; xor r15, r16, r17 }
{ ld1u r25, r26 ; shru r15, r16, r17 ; pcnt r5, r6 }
{ ld1u r25, r26 ; shru r5, r6, r7 ; ill }
{ ld1u r25, r26 ; shrui r15, r16, 5 ; cmovnez r5, r6, r7 }
{ ld1u r25, r26 ; shrui r15, r16, 5 ; shl3add r5, r6, r7 }
{ ld1u r25, r26 ; shrui r5, r6, 5 ; mz r15, r16, r17 }
{ ld1u r25, r26 ; sub r15, r16, r17 ; fnop }
{ ld1u r25, r26 ; sub r15, r16, r17 ; tblidxb1 r5, r6 }
{ ld1u r25, r26 ; sub r5, r6, r7 ; shl2addx r15, r16, r17 }
{ ld1u r25, r26 ; subx r15, r16, r17 ; mula_hs_hs r5, r6, r7 }
{ ld1u r25, r26 ; subx r5, r6, r7 ; andi r15, r16, 5 }
{ ld1u r25, r26 ; subx r5, r6, r7 ; xor r15, r16, r17 }
{ ld1u r25, r26 ; tblidxb0 r5, r6 ; shli r15, r16, 5 }
{ ld1u r25, r26 ; tblidxb1 r5, r6 ; shl r15, r16, r17 }
{ ld1u r25, r26 ; tblidxb2 r5, r6 ; movei r15, 5 }
{ ld1u r25, r26 ; tblidxb3 r5, r6 ; jalr r15 }
{ ld1u r25, r26 ; xor r15, r16, r17 ; cmpeqi r5, r6, 5 }
{ ld1u r25, r26 ; xor r15, r16, r17 ; shli r5, r6, 5 }
{ ld1u r25, r26 ; xor r5, r6, r7 ; nor r15, r16, r17 }
{ ld1u_add r15, r16, 5 ; cmpltsi r5, r6, 5 }
{ ld1u_add r15, r16, 5 ; moveli r5, 0x1234 }
{ ld1u_add r15, r16, 5 ; shl3addx r5, r6, r7 }
{ ld1u_add r15, r16, 5 ; v1dotpus r5, r6, r7 }
{ ld1u_add r15, r16, 5 ; v2int_l r5, r6, r7 }
{ ld2s r15, r16 ; addi r5, r6, 5 }
{ ld2s r15, r16 ; fdouble_pack1 r5, r6, r7 }
{ ld2s r15, r16 ; mulax r5, r6, r7 }
{ ld2s r15, r16 ; v1adiffu r5, r6, r7 }
{ ld2s r15, r16 ; v1sub r5, r6, r7 }
{ ld2s r15, r16 ; v2shrsi r5, r6, 5 }
{ ld2s r25, r26 ; add r15, r16, r17 ; move r5, r6 }
{ ld2s r25, r26 ; add r15, r16, r17 }
{ ld2s r25, r26 ; add r5, r6, r7 ; shrs r15, r16, r17 }
{ ld2s r25, r26 ; addi r15, r16, 5 ; mulax r5, r6, r7 }
{ ld2s r25, r26 ; addi r5, r6, 5 ; cmpleu r15, r16, r17 }
{ ld2s r25, r26 ; addx r15, r16, r17 ; addx r5, r6, r7 }
{ ld2s r25, r26 ; addx r15, r16, r17 ; rotli r5, r6, 5 }
{ ld2s r25, r26 ; addx r5, r6, r7 ; jr r15 }
{ ld2s r25, r26 ; addxi r15, r16, 5 ; cmpleu r5, r6, r7 }
{ ld2s r25, r26 ; addxi r15, r16, 5 ; shrsi r5, r6, 5 }
{ ld2s r25, r26 ; addxi r5, r6, 5 ; rotl r15, r16, r17 }
{ ld2s r25, r26 ; and r15, r16, r17 ; move r5, r6 }
{ ld2s r25, r26 ; and r15, r16, r17 }
{ ld2s r25, r26 ; and r5, r6, r7 ; shrs r15, r16, r17 }
{ ld2s r25, r26 ; andi r15, r16, 5 ; mulax r5, r6, r7 }
{ ld2s r25, r26 ; andi r5, r6, 5 ; cmpleu r15, r16, r17 }
{ ld2s r25, r26 ; clz r5, r6 ; addx r15, r16, r17 }
{ ld2s r25, r26 ; clz r5, r6 ; shrui r15, r16, 5 }
{ ld2s r25, r26 ; cmoveqz r5, r6, r7 ; shl2addx r15, r16, r17 }
{ ld2s r25, r26 ; cmovnez r5, r6, r7 ; or r15, r16, r17 }
{ ld2s r25, r26 ; cmpeq r15, r16, r17 ; mnz r5, r6, r7 }
{ ld2s r25, r26 ; cmpeq r15, r16, r17 ; xor r5, r6, r7 }
{ ld2s r25, r26 ; cmpeq r5, r6, r7 ; shli r15, r16, 5 }
{ ld2s r25, r26 ; cmpeqi r15, r16, 5 ; mula_lu_lu r5, r6, r7 }
{ ld2s r25, r26 ; cmpeqi r5, r6, 5 ; cmples r15, r16, r17 }
{ ld2s r25, r26 ; cmples r15, r16, r17 ; addi r5, r6, 5 }
{ ld2s r25, r26 ; cmples r15, r16, r17 ; rotl r5, r6, r7 }
{ ld2s r25, r26 ; cmples r5, r6, r7 ; jalrp r15 }
{ ld2s r25, r26 ; cmpleu r15, r16, r17 ; cmples r5, r6, r7 }
{ ld2s r25, r26 ; cmpleu r15, r16, r17 ; shrs r5, r6, r7 }
{ ld2s r25, r26 ; cmpleu r5, r6, r7 ; or r15, r16, r17 }
{ ld2s r25, r26 ; cmplts r15, r16, r17 ; mnz r5, r6, r7 }
{ ld2s r25, r26 ; cmplts r15, r16, r17 ; xor r5, r6, r7 }
{ ld2s r25, r26 ; cmplts r5, r6, r7 ; shli r15, r16, 5 }
{ ld2s r25, r26 ; cmpltsi r15, r16, 5 ; mula_lu_lu r5, r6, r7 }
{ ld2s r25, r26 ; cmpltsi r5, r6, 5 ; cmples r15, r16, r17 }
{ ld2s r25, r26 ; cmpltu r15, r16, r17 ; addi r5, r6, 5 }
{ ld2s r25, r26 ; cmpltu r15, r16, r17 ; rotl r5, r6, r7 }
{ ld2s r25, r26 ; cmpltu r5, r6, r7 ; jalrp r15 }
{ ld2s r25, r26 ; cmpne r15, r16, r17 ; cmples r5, r6, r7 }
{ ld2s r25, r26 ; cmpne r15, r16, r17 ; shrs r5, r6, r7 }
{ ld2s r25, r26 ; cmpne r5, r6, r7 ; or r15, r16, r17 }
{ ld2s r25, r26 ; ctz r5, r6 ; lnk r15 }
{ ld2s r25, r26 ; fnop ; cmovnez r5, r6, r7 }
{ ld2s r25, r26 ; fnop ; mula_lu_lu r5, r6, r7 }
{ ld2s r25, r26 ; fnop ; shrui r5, r6, 5 }
{ ld2s r25, r26 ; fsingle_pack1 r5, r6 ; or r15, r16, r17 }
{ ld2s r25, r26 ; ill ; mnz r5, r6, r7 }
{ ld2s r25, r26 ; ill ; xor r5, r6, r7 }
{ ld2s r25, r26 ; info 19 ; jr r15 }
{ ld2s r25, r26 ; info 19 ; shl2add r5, r6, r7 }
{ ld2s r25, r26 ; jalr r15 ; cmpleu r5, r6, r7 }
{ ld2s r25, r26 ; jalr r15 ; shrsi r5, r6, 5 }
{ ld2s r25, r26 ; jalrp r15 ; mula_hu_hu r5, r6, r7 }
{ ld2s r25, r26 ; jr r15 ; clz r5, r6 }
{ ld2s r25, r26 ; jr r15 ; shl2add r5, r6, r7 }
{ ld2s r25, r26 ; jrp r15 ; movei r5, 5 }
{ ld2s r25, r26 ; lnk r15 ; add r5, r6, r7 }
{ ld2s r25, r26 ; lnk r15 ; revbytes r5, r6 }
{ ld2s r25, r26 ; mnz r15, r16, r17 ; ctz r5, r6 }
{ ld2s r25, r26 ; mnz r15, r16, r17 ; tblidxb0 r5, r6 }
{ ld2s r25, r26 ; mnz r5, r6, r7 ; shl2add r15, r16, r17 }
{ ld2s r25, r26 ; move r15, r16 ; mul_lu_lu r5, r6, r7 }
{ ld2s r25, r26 ; move r5, r6 ; and r15, r16, r17 }
{ ld2s r25, r26 ; move r5, r6 ; subx r15, r16, r17 }
{ ld2s r25, r26 ; movei r15, 5 ; or r5, r6, r7 }
{ ld2s r25, r26 ; movei r5, 5 ; fnop }
{ ld2s r25, r26 ; mul_hs_hs r5, r6, r7 ; cmpeqi r15, r16, 5 }
{ ld2s r25, r26 ; mul_hu_hu r5, r6, r7 ; add r15, r16, r17 }
{ ld2s r25, r26 ; mul_hu_hu r5, r6, r7 ; shrsi r15, r16, 5 }
{ ld2s r25, r26 ; mul_ls_ls r5, r6, r7 ; shl1addx r15, r16, r17 }
{ ld2s r25, r26 ; mul_lu_lu r5, r6, r7 ; nop }
{ ld2s r25, r26 ; mula_hs_hs r5, r6, r7 ; jr r15 }
{ ld2s r25, r26 ; mula_hu_hu r5, r6, r7 ; cmpltu r15, r16, r17 }
{ ld2s r25, r26 ; mula_ls_ls r5, r6, r7 ; andi r15, r16, 5 }
{ ld2s r25, r26 ; mula_ls_ls r5, r6, r7 ; xor r15, r16, r17 }
{ ld2s r25, r26 ; mula_lu_lu r5, r6, r7 ; shli r15, r16, 5 }
{ ld2s r25, r26 ; mulax r5, r6, r7 ; shl r15, r16, r17 }
{ ld2s r25, r26 ; mulx r5, r6, r7 ; movei r15, 5 }
{ ld2s r25, r26 ; mz r15, r16, r17 ; ctz r5, r6 }
{ ld2s r25, r26 ; mz r15, r16, r17 ; tblidxb0 r5, r6 }
{ ld2s r25, r26 ; mz r5, r6, r7 ; shl2add r15, r16, r17 }
{ ld2s r25, r26 ; nop ; cmpltu r15, r16, r17 }
{ ld2s r25, r26 ; nop ; rotl r15, r16, r17 }
{ ld2s r25, r26 ; nor r15, r16, r17 ; addi r5, r6, 5 }
{ ld2s r25, r26 ; nor r15, r16, r17 ; rotl r5, r6, r7 }
{ ld2s r25, r26 ; nor r5, r6, r7 ; jalrp r15 }
{ ld2s r25, r26 ; or r15, r16, r17 ; cmples r5, r6, r7 }
{ ld2s r25, r26 ; or r15, r16, r17 ; shrs r5, r6, r7 }
{ ld2s r25, r26 ; or r5, r6, r7 ; or r15, r16, r17 }
{ ld2s r25, r26 ; pcnt r5, r6 ; lnk r15 }
{ ld2s r25, r26 ; revbits r5, r6 ; fnop }
{ ld2s r25, r26 ; revbytes r5, r6 ; cmpeqi r15, r16, 5 }
{ ld2s r25, r26 ; rotl r15, r16, r17 ; add r5, r6, r7 }
{ ld2s r25, r26 ; rotl r15, r16, r17 ; revbytes r5, r6 }
{ ld2s r25, r26 ; rotl r5, r6, r7 ; jalr r15 }
{ ld2s r25, r26 ; rotli r15, r16, 5 ; cmpeqi r5, r6, 5 }
{ ld2s r25, r26 ; rotli r15, r16, 5 ; shli r5, r6, 5 }
{ ld2s r25, r26 ; rotli r5, r6, 5 ; nor r15, r16, r17 }
{ ld2s r25, r26 ; shl r15, r16, r17 ; info 19 }
{ ld2s r25, r26 ; shl r15, r16, r17 ; tblidxb3 r5, r6 }
{ ld2s r25, r26 ; shl r5, r6, r7 ; shl3addx r15, r16, r17 }
{ ld2s r25, r26 ; shl1add r15, r16, r17 ; mula_ls_ls r5, r6, r7 }
{ ld2s r25, r26 ; shl1add r5, r6, r7 ; cmpeqi r15, r16, 5 }
{ ld2s r25, r26 ; shl1addx r15, r16, r17 ; add r5, r6, r7 }
{ ld2s r25, r26 ; shl1addx r15, r16, r17 ; revbytes r5, r6 }
{ ld2s r25, r26 ; shl1addx r5, r6, r7 ; jalr r15 }
{ ld2s r25, r26 ; shl2add r15, r16, r17 ; cmpeqi r5, r6, 5 }
{ ld2s r25, r26 ; shl2add r15, r16, r17 ; shli r5, r6, 5 }
{ ld2s r25, r26 ; shl2add r5, r6, r7 ; nor r15, r16, r17 }
{ ld2s r25, r26 ; shl2addx r15, r16, r17 ; info 19 }
{ ld2s r25, r26 ; shl2addx r15, r16, r17 ; tblidxb3 r5, r6 }
{ ld2s r25, r26 ; shl2addx r5, r6, r7 ; shl3addx r15, r16, r17 }
{ ld2s r25, r26 ; shl3add r15, r16, r17 ; mula_ls_ls r5, r6, r7 }
{ ld2s r25, r26 ; shl3add r5, r6, r7 ; cmpeqi r15, r16, 5 }
{ ld2s r25, r26 ; shl3addx r15, r16, r17 ; add r5, r6, r7 }
{ ld2s r25, r26 ; shl3addx r15, r16, r17 ; revbytes r5, r6 }
{ ld2s r25, r26 ; shl3addx r5, r6, r7 ; jalr r15 }
{ ld2s r25, r26 ; shli r15, r16, 5 ; cmpeqi r5, r6, 5 }
{ ld2s r25, r26 ; shli r15, r16, 5 ; shli r5, r6, 5 }
{ ld2s r25, r26 ; shli r5, r6, 5 ; nor r15, r16, r17 }
{ ld2s r25, r26 ; shrs r15, r16, r17 ; info 19 }
{ ld2s r25, r26 ; shrs r15, r16, r17 ; tblidxb3 r5, r6 }
{ ld2s r25, r26 ; shrs r5, r6, r7 ; shl3addx r15, r16, r17 }
{ ld2s r25, r26 ; shrsi r15, r16, 5 ; mula_ls_ls r5, r6, r7 }
{ ld2s r25, r26 ; shrsi r5, r6, 5 ; cmpeqi r15, r16, 5 }
{ ld2s r25, r26 ; shru r15, r16, r17 ; add r5, r6, r7 }
{ ld2s r25, r26 ; shru r15, r16, r17 ; revbytes r5, r6 }
{ ld2s r25, r26 ; shru r5, r6, r7 ; jalr r15 }
{ ld2s r25, r26 ; shrui r15, r16, 5 ; cmpeqi r5, r6, 5 }
{ ld2s r25, r26 ; shrui r15, r16, 5 ; shli r5, r6, 5 }
{ ld2s r25, r26 ; shrui r5, r6, 5 ; nor r15, r16, r17 }
{ ld2s r25, r26 ; sub r15, r16, r17 ; info 19 }
{ ld2s r25, r26 ; sub r15, r16, r17 ; tblidxb3 r5, r6 }
{ ld2s r25, r26 ; sub r5, r6, r7 ; shl3addx r15, r16, r17 }
{ ld2s r25, r26 ; subx r15, r16, r17 ; mula_ls_ls r5, r6, r7 }
{ ld2s r25, r26 ; subx r5, r6, r7 ; cmpeqi r15, r16, 5 }
{ ld2s r25, r26 ; tblidxb0 r5, r6 ; add r15, r16, r17 }
{ ld2s r25, r26 ; tblidxb0 r5, r6 ; shrsi r15, r16, 5 }
{ ld2s r25, r26 ; tblidxb1 r5, r6 ; shl1addx r15, r16, r17 }
{ ld2s r25, r26 ; tblidxb2 r5, r6 ; nop }
{ ld2s r25, r26 ; tblidxb3 r5, r6 ; jr r15 }
{ ld2s r25, r26 ; xor r15, r16, r17 ; cmpleu r5, r6, r7 }
{ ld2s r25, r26 ; xor r15, r16, r17 ; shrsi r5, r6, 5 }
{ ld2s r25, r26 ; xor r5, r6, r7 ; rotl r15, r16, r17 }
{ ld2s_add r15, r16, 5 ; cmpltui r5, r6, 5 }
{ ld2s_add r15, r16, 5 ; mul_hs_hu r5, r6, r7 }
{ ld2s_add r15, r16, 5 ; shlx r5, r6, r7 }
{ ld2s_add r15, r16, 5 ; v1int_h r5, r6, r7 }
{ ld2s_add r15, r16, 5 ; v2maxsi r5, r6, 5 }
{ ld2u r15, r16 ; addx r5, r6, r7 }
{ ld2u r15, r16 ; fdouble_sub_flags r5, r6, r7 }
{ ld2u r15, r16 ; mz r5, r6, r7 }
{ ld2u r15, r16 ; v1cmpeq r5, r6, r7 }
{ ld2u r15, r16 ; v2add r5, r6, r7 }
{ ld2u r15, r16 ; v2shrui r5, r6, 5 }
{ ld2u r25, r26 ; add r15, r16, r17 ; mul_hs_hs r5, r6, r7 }
{ ld2u r25, r26 ; add r5, r6, r7 ; addi r15, r16, 5 }
{ ld2u r25, r26 ; add r5, r6, r7 ; shru r15, r16, r17 }
{ ld2u r25, r26 ; addi r15, r16, 5 ; mz r5, r6, r7 }
{ ld2u r25, r26 ; addi r5, r6, 5 ; cmpltsi r15, r16, 5 }
{ ld2u r25, r26 ; addx r15, r16, r17 ; and r5, r6, r7 }
{ ld2u r25, r26 ; addx r15, r16, r17 ; shl1add r5, r6, r7 }
{ ld2u r25, r26 ; addx r5, r6, r7 ; lnk r15 }
{ ld2u r25, r26 ; addxi r15, r16, 5 ; cmpltsi r5, r6, 5 }
{ ld2u r25, r26 ; addxi r15, r16, 5 ; shrui r5, r6, 5 }
{ ld2u r25, r26 ; addxi r5, r6, 5 ; shl r15, r16, r17 }
{ ld2u r25, r26 ; and r15, r16, r17 ; mul_hs_hs r5, r6, r7 }
{ ld2u r25, r26 ; and r5, r6, r7 ; addi r15, r16, 5 }
{ ld2u r25, r26 ; and r5, r6, r7 ; shru r15, r16, r17 }
{ ld2u r25, r26 ; andi r15, r16, 5 ; mz r5, r6, r7 }
{ ld2u r25, r26 ; andi r5, r6, 5 ; cmpltsi r15, r16, 5 }
{ ld2u r25, r26 ; clz r5, r6 ; and r15, r16, r17 }
{ ld2u r25, r26 ; clz r5, r6 ; subx r15, r16, r17 }
{ ld2u r25, r26 ; cmoveqz r5, r6, r7 ; shl3addx r15, r16, r17 }
{ ld2u r25, r26 ; cmovnez r5, r6, r7 ; rotli r15, r16, 5 }
{ ld2u r25, r26 ; cmpeq r15, r16, r17 ; movei r5, 5 }
{ ld2u r25, r26 ; cmpeq r5, r6, r7 ; add r15, r16, r17 }
{ ld2u r25, r26 ; cmpeq r5, r6, r7 ; shrsi r15, r16, 5 }
{ ld2u r25, r26 ; cmpeqi r15, r16, 5 ; mulx r5, r6, r7 }
{ ld2u r25, r26 ; cmpeqi r5, r6, 5 ; cmplts r15, r16, r17 }
{ ld2u r25, r26 ; cmples r15, r16, r17 ; addxi r5, r6, 5 }
{ ld2u r25, r26 ; cmples r15, r16, r17 ; shl r5, r6, r7 }
{ ld2u r25, r26 ; cmples r5, r6, r7 ; jrp r15 }
{ ld2u r25, r26 ; cmpleu r15, r16, r17 ; cmplts r5, r6, r7 }
{ ld2u r25, r26 ; cmpleu r15, r16, r17 ; shru r5, r6, r7 }
{ ld2u r25, r26 ; cmpleu r5, r6, r7 ; rotli r15, r16, 5 }
{ ld2u r25, r26 ; cmplts r15, r16, r17 ; movei r5, 5 }
{ ld2u r25, r26 ; cmplts r5, r6, r7 ; add r15, r16, r17 }
{ ld2u r25, r26 ; cmplts r5, r6, r7 ; shrsi r15, r16, 5 }
{ ld2u r25, r26 ; cmpltsi r15, r16, 5 ; mulx r5, r6, r7 }
{ ld2u r25, r26 ; cmpltsi r5, r6, 5 ; cmplts r15, r16, r17 }
{ ld2u r25, r26 ; cmpltu r15, r16, r17 ; addxi r5, r6, 5 }
{ ld2u r25, r26 ; cmpltu r15, r16, r17 ; shl r5, r6, r7 }
{ ld2u r25, r26 ; cmpltu r5, r6, r7 ; jrp r15 }
{ ld2u r25, r26 ; cmpne r15, r16, r17 ; cmplts r5, r6, r7 }
{ ld2u r25, r26 ; cmpne r15, r16, r17 ; shru r5, r6, r7 }
{ ld2u r25, r26 ; cmpne r5, r6, r7 ; rotli r15, r16, 5 }
{ ld2u r25, r26 ; ctz r5, r6 ; move r15, r16 }
{ ld2u r25, r26 ; fnop ; cmpeq r5, r6, r7 }
{ ld2u r25, r26 ; fnop ; mulx r5, r6, r7 }
{ ld2u r25, r26 ; fnop ; sub r5, r6, r7 }
{ ld2u r25, r26 ; fsingle_pack1 r5, r6 ; rotli r15, r16, 5 }
{ ld2u r25, r26 ; ill ; movei r5, 5 }
{ ld2u r25, r26 ; info 19 ; add r15, r16, r17 }
{ ld2u r25, r26 ; info 19 ; lnk r15 }
{ ld2u r25, r26 ; info 19 ; shl2addx r5, r6, r7 }
{ ld2u r25, r26 ; jalr r15 ; cmpltsi r5, r6, 5 }
{ ld2u r25, r26 ; jalr r15 ; shrui r5, r6, 5 }
{ ld2u r25, r26 ; jalrp r15 ; mula_lu_lu r5, r6, r7 }
{ ld2u r25, r26 ; jr r15 ; cmovnez r5, r6, r7 }
{ ld2u r25, r26 ; jr r15 ; shl3add r5, r6, r7 }
{ ld2u r25, r26 ; jrp r15 ; mul_hu_hu r5, r6, r7 }
{ ld2u r25, r26 ; lnk r15 ; addx r5, r6, r7 }
{ ld2u r25, r26 ; lnk r15 ; rotli r5, r6, 5 }
{ ld2u r25, r26 ; mnz r15, r16, r17 ; fsingle_pack1 r5, r6 }
{ ld2u r25, r26 ; mnz r15, r16, r17 ; tblidxb2 r5, r6 }
{ ld2u r25, r26 ; mnz r5, r6, r7 ; shl3add r15, r16, r17 }
{ ld2u r25, r26 ; move r15, r16 ; mula_hu_hu r5, r6, r7 }
{ ld2u r25, r26 ; move r5, r6 ; cmpeq r15, r16, r17 }
{ ld2u r25, r26 ; move r5, r6 }
{ ld2u r25, r26 ; movei r15, 5 ; revbits r5, r6 }
{ ld2u r25, r26 ; movei r5, 5 ; info 19 }
{ ld2u r25, r26 ; mul_hs_hs r5, r6, r7 ; cmpleu r15, r16, r17 }
{ ld2u r25, r26 ; mul_hu_hu r5, r6, r7 ; addx r15, r16, r17 }
{ ld2u r25, r26 ; mul_hu_hu r5, r6, r7 ; shrui r15, r16, 5 }
{ ld2u r25, r26 ; mul_ls_ls r5, r6, r7 ; shl2addx r15, r16, r17 }
{ ld2u r25, r26 ; mul_lu_lu r5, r6, r7 ; or r15, r16, r17 }
{ ld2u r25, r26 ; mula_hs_hs r5, r6, r7 ; lnk r15 }
{ ld2u r25, r26 ; mula_hu_hu r5, r6, r7 ; fnop }
{ ld2u r25, r26 ; mula_ls_ls r5, r6, r7 ; cmpeqi r15, r16, 5 }
{ ld2u r25, r26 ; mula_lu_lu r5, r6, r7 ; add r15, r16, r17 }
{ ld2u r25, r26 ; mula_lu_lu r5, r6, r7 ; shrsi r15, r16, 5 }
{ ld2u r25, r26 ; mulax r5, r6, r7 ; shl1addx r15, r16, r17 }
{ ld2u r25, r26 ; mulx r5, r6, r7 ; nop }
{ ld2u r25, r26 ; mz r15, r16, r17 ; fsingle_pack1 r5, r6 }
{ ld2u r25, r26 ; mz r15, r16, r17 ; tblidxb2 r5, r6 }
{ ld2u r25, r26 ; mz r5, r6, r7 ; shl3add r15, r16, r17 }
{ ld2u r25, r26 ; nop ; cmpne r15, r16, r17 }
{ ld2u r25, r26 ; nop ; rotli r15, r16, 5 }
{ ld2u r25, r26 ; nor r15, r16, r17 ; addxi r5, r6, 5 }
{ ld2u r25, r26 ; nor r15, r16, r17 ; shl r5, r6, r7 }
{ ld2u r25, r26 ; nor r5, r6, r7 ; jrp r15 }
{ ld2u r25, r26 ; or r15, r16, r17 ; cmplts r5, r6, r7 }
{ ld2u r25, r26 ; or r15, r16, r17 ; shru r5, r6, r7 }
{ ld2u r25, r26 ; or r5, r6, r7 ; rotli r15, r16, 5 }
{ ld2u r25, r26 ; pcnt r5, r6 ; move r15, r16 }
{ ld2u r25, r26 ; revbits r5, r6 ; info 19 }
{ ld2u r25, r26 ; revbytes r5, r6 ; cmpleu r15, r16, r17 }
{ ld2u r25, r26 ; rotl r15, r16, r17 ; addx r5, r6, r7 }
{ ld2u r25, r26 ; rotl r15, r16, r17 ; rotli r5, r6, 5 }
{ ld2u r25, r26 ; rotl r5, r6, r7 ; jr r15 }
{ ld2u r25, r26 ; rotli r15, r16, 5 ; cmpleu r5, r6, r7 }
{ ld2u r25, r26 ; rotli r15, r16, 5 ; shrsi r5, r6, 5 }
{ ld2u r25, r26 ; rotli r5, r6, 5 ; rotl r15, r16, r17 }
{ ld2u r25, r26 ; shl r15, r16, r17 ; move r5, r6 }
{ ld2u r25, r26 ; shl r15, r16, r17 }
{ ld2u r25, r26 ; shl r5, r6, r7 ; shrs r15, r16, r17 }
{ ld2u r25, r26 ; shl1add r15, r16, r17 ; mulax r5, r6, r7 }
{ ld2u r25, r26 ; shl1add r5, r6, r7 ; cmpleu r15, r16, r17 }
{ ld2u r25, r26 ; shl1addx r15, r16, r17 ; addx r5, r6, r7 }
{ ld2u r25, r26 ; shl1addx r15, r16, r17 ; rotli r5, r6, 5 }
{ ld2u r25, r26 ; shl1addx r5, r6, r7 ; jr r15 }
{ ld2u r25, r26 ; shl2add r15, r16, r17 ; cmpleu r5, r6, r7 }
{ ld2u r25, r26 ; shl2add r15, r16, r17 ; shrsi r5, r6, 5 }
{ ld2u r25, r26 ; shl2add r5, r6, r7 ; rotl r15, r16, r17 }
{ ld2u r25, r26 ; shl2addx r15, r16, r17 ; move r5, r6 }
{ ld2u r25, r26 ; shl2addx r15, r16, r17 }
{ ld2u r25, r26 ; shl2addx r5, r6, r7 ; shrs r15, r16, r17 }
{ ld2u r25, r26 ; shl3add r15, r16, r17 ; mulax r5, r6, r7 }
{ ld2u r25, r26 ; shl3add r5, r6, r7 ; cmpleu r15, r16, r17 }
{ ld2u r25, r26 ; shl3addx r15, r16, r17 ; addx r5, r6, r7 }
{ ld2u r25, r26 ; shl3addx r15, r16, r17 ; rotli r5, r6, 5 }
{ ld2u r25, r26 ; shl3addx r5, r6, r7 ; jr r15 }
{ ld2u r25, r26 ; shli r15, r16, 5 ; cmpleu r5, r6, r7 }
{ ld2u r25, r26 ; shli r15, r16, 5 ; shrsi r5, r6, 5 }
{ ld2u r25, r26 ; shli r5, r6, 5 ; rotl r15, r16, r17 }
{ ld2u r25, r26 ; shrs r15, r16, r17 ; move r5, r6 }
{ ld2u r25, r26 ; shrs r15, r16, r17 }
{ ld2u r25, r26 ; shrs r5, r6, r7 ; shrs r15, r16, r17 }
{ ld2u r25, r26 ; shrsi r15, r16, 5 ; mulax r5, r6, r7 }
{ ld2u r25, r26 ; shrsi r5, r6, 5 ; cmpleu r15, r16, r17 }
{ ld2u r25, r26 ; shru r15, r16, r17 ; addx r5, r6, r7 }
{ ld2u r25, r26 ; shru r15, r16, r17 ; rotli r5, r6, 5 }
{ ld2u r25, r26 ; shru r5, r6, r7 ; jr r15 }
{ ld2u r25, r26 ; shrui r15, r16, 5 ; cmpleu r5, r6, r7 }
{ ld2u r25, r26 ; shrui r15, r16, 5 ; shrsi r5, r6, 5 }
{ ld2u r25, r26 ; shrui r5, r6, 5 ; rotl r15, r16, r17 }
{ ld2u r25, r26 ; sub r15, r16, r17 ; move r5, r6 }
{ ld2u r25, r26 ; sub r15, r16, r17 }
{ ld2u r25, r26 ; sub r5, r6, r7 ; shrs r15, r16, r17 }
{ ld2u r25, r26 ; subx r15, r16, r17 ; mulax r5, r6, r7 }
{ ld2u r25, r26 ; subx r5, r6, r7 ; cmpleu r15, r16, r17 }
{ ld2u r25, r26 ; tblidxb0 r5, r6 ; addx r15, r16, r17 }
{ ld2u r25, r26 ; tblidxb0 r5, r6 ; shrui r15, r16, 5 }
{ ld2u r25, r26 ; tblidxb1 r5, r6 ; shl2addx r15, r16, r17 }
{ ld2u r25, r26 ; tblidxb2 r5, r6 ; or r15, r16, r17 }
{ ld2u r25, r26 ; tblidxb3 r5, r6 ; lnk r15 }
{ ld2u r25, r26 ; xor r15, r16, r17 ; cmpltsi r5, r6, 5 }
{ ld2u r25, r26 ; xor r15, r16, r17 ; shrui r5, r6, 5 }
{ ld2u r25, r26 ; xor r5, r6, r7 ; shl r15, r16, r17 }
{ ld2u_add r15, r16, 5 ; cmul r5, r6, r7 }
{ ld2u_add r15, r16, 5 ; mul_hs_lu r5, r6, r7 }
{ ld2u_add r15, r16, 5 ; shrs r5, r6, r7 }
{ ld2u_add r15, r16, 5 ; v1maxu r5, r6, r7 }
{ ld2u_add r15, r16, 5 ; v2minsi r5, r6, 5 }
{ ld4s r15, r16 ; addxli r5, r6, 0x1234 }
{ ld4s r15, r16 ; fdouble_unpack_min r5, r6, r7 }
{ ld4s r15, r16 ; nor r5, r6, r7 }
{ ld4s r15, r16 ; v1cmples r5, r6, r7 }
{ ld4s r15, r16 ; v2addsc r5, r6, r7 }
{ ld4s r15, r16 ; v2subsc r5, r6, r7 }
{ ld4s r25, r26 ; add r15, r16, r17 ; mul_ls_ls r5, r6, r7 }
{ ld4s r25, r26 ; add r5, r6, r7 ; addxi r15, r16, 5 }
{ ld4s r25, r26 ; add r5, r6, r7 ; sub r15, r16, r17 }
{ ld4s r25, r26 ; addi r15, r16, 5 ; nor r5, r6, r7 }
{ ld4s r25, r26 ; addi r5, r6, 5 ; cmpne r15, r16, r17 }
{ ld4s r25, r26 ; addx r15, r16, r17 ; clz r5, r6 }
{ ld4s r25, r26 ; addx r15, r16, r17 ; shl2add r5, r6, r7 }
{ ld4s r25, r26 ; addx r5, r6, r7 ; move r15, r16 }
{ ld4s r25, r26 ; addxi r15, r16, 5 ; cmpne r5, r6, r7 }
{ ld4s r25, r26 ; addxi r15, r16, 5 ; subx r5, r6, r7 }
{ ld4s r25, r26 ; addxi r5, r6, 5 ; shl1addx r15, r16, r17 }
{ ld4s r25, r26 ; and r15, r16, r17 ; mul_ls_ls r5, r6, r7 }
{ ld4s r25, r26 ; and r5, r6, r7 ; addxi r15, r16, 5 }
{ ld4s r25, r26 ; and r5, r6, r7 ; sub r15, r16, r17 }
{ ld4s r25, r26 ; andi r15, r16, 5 ; nor r5, r6, r7 }
{ ld4s r25, r26 ; andi r5, r6, 5 ; cmpne r15, r16, r17 }
{ ld4s r25, r26 ; clz r5, r6 ; cmpeq r15, r16, r17 }
{ ld4s r25, r26 ; clz r5, r6 }
{ ld4s r25, r26 ; cmoveqz r5, r6, r7 ; shrs r15, r16, r17 }
{ ld4s r25, r26 ; cmovnez r5, r6, r7 ; shl1add r15, r16, r17 }
{ ld4s r25, r26 ; cmpeq r15, r16, r17 ; mul_hu_hu r5, r6, r7 }
{ ld4s r25, r26 ; cmpeq r5, r6, r7 ; addx r15, r16, r17 }
{ ld4s r25, r26 ; cmpeq r5, r6, r7 ; shrui r15, r16, 5 }
{ ld4s r25, r26 ; cmpeqi r15, r16, 5 ; nop }
{ ld4s r25, r26 ; cmpeqi r5, r6, 5 ; cmpltu r15, r16, r17 }
{ ld4s r25, r26 ; cmples r15, r16, r17 ; andi r5, r6, 5 }
{ ld4s r25, r26 ; cmples r15, r16, r17 ; shl1addx r5, r6, r7 }
{ ld4s r25, r26 ; cmples r5, r6, r7 ; mnz r15, r16, r17 }
{ ld4s r25, r26 ; cmpleu r15, r16, r17 ; cmpltu r5, r6, r7 }
{ ld4s r25, r26 ; cmpleu r15, r16, r17 ; sub r5, r6, r7 }
{ ld4s r25, r26 ; cmpleu r5, r6, r7 ; shl1add r15, r16, r17 }
{ ld4s r25, r26 ; cmplts r15, r16, r17 ; mul_hu_hu r5, r6, r7 }
{ ld4s r25, r26 ; cmplts r5, r6, r7 ; addx r15, r16, r17 }
{ ld4s r25, r26 ; cmplts r5, r6, r7 ; shrui r15, r16, 5 }
{ ld4s r25, r26 ; cmpltsi r15, r16, 5 ; nop }
{ ld4s r25, r26 ; cmpltsi r5, r6, 5 ; cmpltu r15, r16, r17 }
{ ld4s r25, r26 ; cmpltu r15, r16, r17 ; andi r5, r6, 5 }
{ ld4s r25, r26 ; cmpltu r15, r16, r17 ; shl1addx r5, r6, r7 }
{ ld4s r25, r26 ; cmpltu r5, r6, r7 ; mnz r15, r16, r17 }
{ ld4s r25, r26 ; cmpne r15, r16, r17 ; cmpltu r5, r6, r7 }
{ ld4s r25, r26 ; cmpne r15, r16, r17 ; sub r5, r6, r7 }
{ ld4s r25, r26 ; cmpne r5, r6, r7 ; shl1add r15, r16, r17 }
{ ld4s r25, r26 ; ctz r5, r6 ; mz r15, r16, r17 }
{ ld4s r25, r26 ; fnop ; cmpeqi r5, r6, 5 }
{ ld4s r25, r26 ; fnop ; mz r5, r6, r7 }
{ ld4s r25, r26 ; fnop ; subx r5, r6, r7 }
{ ld4s r25, r26 ; fsingle_pack1 r5, r6 ; shl1add r15, r16, r17 }
{ ld4s r25, r26 ; ill ; mul_hu_hu r5, r6, r7 }
{ ld4s r25, r26 ; info 19 ; addi r15, r16, 5 }
{ ld4s r25, r26 ; info 19 ; mnz r5, r6, r7 }
{ ld4s r25, r26 ; info 19 ; shl3add r5, r6, r7 }
{ ld4s r25, r26 ; jalr r15 ; cmpne r5, r6, r7 }
{ ld4s r25, r26 ; jalr r15 ; subx r5, r6, r7 }
{ ld4s r25, r26 ; jalrp r15 ; mulx r5, r6, r7 }
{ ld4s r25, r26 ; jr r15 ; cmpeqi r5, r6, 5 }
{ ld4s r25, r26 ; jr r15 ; shli r5, r6, 5 }
{ ld4s r25, r26 ; jrp r15 ; mul_lu_lu r5, r6, r7 }
{ ld4s r25, r26 ; lnk r15 ; and r5, r6, r7 }
{ ld4s r25, r26 ; lnk r15 ; shl1add r5, r6, r7 }
{ ld4s r25, r26 ; mnz r15, r16, r17 ; mnz r5, r6, r7 }
{ ld4s r25, r26 ; mnz r15, r16, r17 ; xor r5, r6, r7 }
{ ld4s r25, r26 ; mnz r5, r6, r7 ; shli r15, r16, 5 }
{ ld4s r25, r26 ; move r15, r16 ; mula_lu_lu r5, r6, r7 }
{ ld4s r25, r26 ; move r5, r6 ; cmples r15, r16, r17 }
{ ld4s r25, r26 ; movei r15, 5 ; addi r5, r6, 5 }
{ ld4s r25, r26 ; movei r15, 5 ; rotl r5, r6, r7 }
{ ld4s r25, r26 ; movei r5, 5 ; jalrp r15 }
{ ld4s r25, r26 ; mul_hs_hs r5, r6, r7 ; cmpltsi r15, r16, 5 }
{ ld4s r25, r26 ; mul_hu_hu r5, r6, r7 ; and r15, r16, r17 }
{ ld4s r25, r26 ; mul_hu_hu r5, r6, r7 ; subx r15, r16, r17 }
{ ld4s r25, r26 ; mul_ls_ls r5, r6, r7 ; shl3addx r15, r16, r17 }
{ ld4s r25, r26 ; mul_lu_lu r5, r6, r7 ; rotli r15, r16, 5 }
{ ld4s r25, r26 ; mula_hs_hs r5, r6, r7 ; move r15, r16 }
{ ld4s r25, r26 ; mula_hu_hu r5, r6, r7 ; info 19 }
{ ld4s r25, r26 ; mula_ls_ls r5, r6, r7 ; cmpleu r15, r16, r17 }
{ ld4s r25, r26 ; mula_lu_lu r5, r6, r7 ; addx r15, r16, r17 }
{ ld4s r25, r26 ; mula_lu_lu r5, r6, r7 ; shrui r15, r16, 5 }
{ ld4s r25, r26 ; mulax r5, r6, r7 ; shl2addx r15, r16, r17 }
{ ld4s r25, r26 ; mulx r5, r6, r7 ; or r15, r16, r17 }
{ ld4s r25, r26 ; mz r15, r16, r17 ; mnz r5, r6, r7 }
{ ld4s r25, r26 ; mz r15, r16, r17 ; xor r5, r6, r7 }
{ ld4s r25, r26 ; mz r5, r6, r7 ; shli r15, r16, 5 }
{ ld4s r25, r26 ; nop ; ctz r5, r6 }
{ ld4s r25, r26 ; nop ; shl r15, r16, r17 }
{ ld4s r25, r26 ; nor r15, r16, r17 ; andi r5, r6, 5 }
{ ld4s r25, r26 ; nor r15, r16, r17 ; shl1addx r5, r6, r7 }
{ ld4s r25, r26 ; nor r5, r6, r7 ; mnz r15, r16, r17 }
{ ld4s r25, r26 ; or r15, r16, r17 ; cmpltu r5, r6, r7 }
{ ld4s r25, r26 ; or r15, r16, r17 ; sub r5, r6, r7 }
{ ld4s r25, r26 ; or r5, r6, r7 ; shl1add r15, r16, r17 }
{ ld4s r25, r26 ; pcnt r5, r6 ; mz r15, r16, r17 }
{ ld4s r25, r26 ; revbits r5, r6 ; jalrp r15 }
{ ld4s r25, r26 ; revbytes r5, r6 ; cmpltsi r15, r16, 5 }
{ ld4s r25, r26 ; rotl r15, r16, r17 ; and r5, r6, r7 }
{ ld4s r25, r26 ; rotl r15, r16, r17 ; shl1add r5, r6, r7 }
{ ld4s r25, r26 ; rotl r5, r6, r7 ; lnk r15 }
{ ld4s r25, r26 ; rotli r15, r16, 5 ; cmpltsi r5, r6, 5 }
{ ld4s r25, r26 ; rotli r15, r16, 5 ; shrui r5, r6, 5 }
{ ld4s r25, r26 ; rotli r5, r6, 5 ; shl r15, r16, r17 }
{ ld4s r25, r26 ; shl r15, r16, r17 ; mul_hs_hs r5, r6, r7 }
{ ld4s r25, r26 ; shl r5, r6, r7 ; addi r15, r16, 5 }
{ ld4s r25, r26 ; shl r5, r6, r7 ; shru r15, r16, r17 }
{ ld4s r25, r26 ; shl1add r15, r16, r17 ; mz r5, r6, r7 }
{ ld4s r25, r26 ; shl1add r5, r6, r7 ; cmpltsi r15, r16, 5 }
{ ld4s r25, r26 ; shl1addx r15, r16, r17 ; and r5, r6, r7 }
{ ld4s r25, r26 ; shl1addx r15, r16, r17 ; shl1add r5, r6, r7 }
{ ld4s r25, r26 ; shl1addx r5, r6, r7 ; lnk r15 }
{ ld4s r25, r26 ; shl2add r15, r16, r17 ; cmpltsi r5, r6, 5 }
{ ld4s r25, r26 ; shl2add r15, r16, r17 ; shrui r5, r6, 5 }
{ ld4s r25, r26 ; shl2add r5, r6, r7 ; shl r15, r16, r17 }
{ ld4s r25, r26 ; shl2addx r15, r16, r17 ; mul_hs_hs r5, r6, r7 }
{ ld4s r25, r26 ; shl2addx r5, r6, r7 ; addi r15, r16, 5 }
{ ld4s r25, r26 ; shl2addx r5, r6, r7 ; shru r15, r16, r17 }
{ ld4s r25, r26 ; shl3add r15, r16, r17 ; mz r5, r6, r7 }
{ ld4s r25, r26 ; shl3add r5, r6, r7 ; cmpltsi r15, r16, 5 }
{ ld4s r25, r26 ; shl3addx r15, r16, r17 ; and r5, r6, r7 }
{ ld4s r25, r26 ; shl3addx r15, r16, r17 ; shl1add r5, r6, r7 }
{ ld4s r25, r26 ; shl3addx r5, r6, r7 ; lnk r15 }
{ ld4s r25, r26 ; shli r15, r16, 5 ; cmpltsi r5, r6, 5 }
{ ld4s r25, r26 ; shli r15, r16, 5 ; shrui r5, r6, 5 }
{ ld4s r25, r26 ; shli r5, r6, 5 ; shl r15, r16, r17 }
{ ld4s r25, r26 ; shrs r15, r16, r17 ; mul_hs_hs r5, r6, r7 }
{ ld4s r25, r26 ; shrs r5, r6, r7 ; addi r15, r16, 5 }
{ ld4s r25, r26 ; shrs r5, r6, r7 ; shru r15, r16, r17 }
{ ld4s r25, r26 ; shrsi r15, r16, 5 ; mz r5, r6, r7 }
{ ld4s r25, r26 ; shrsi r5, r6, 5 ; cmpltsi r15, r16, 5 }
{ ld4s r25, r26 ; shru r15, r16, r17 ; and r5, r6, r7 }
{ ld4s r25, r26 ; shru r15, r16, r17 ; shl1add r5, r6, r7 }
{ ld4s r25, r26 ; shru r5, r6, r7 ; lnk r15 }
{ ld4s r25, r26 ; shrui r15, r16, 5 ; cmpltsi r5, r6, 5 }
{ ld4s r25, r26 ; shrui r15, r16, 5 ; shrui r5, r6, 5 }
{ ld4s r25, r26 ; shrui r5, r6, 5 ; shl r15, r16, r17 }
{ ld4s r25, r26 ; sub r15, r16, r17 ; mul_hs_hs r5, r6, r7 }
{ ld4s r25, r26 ; sub r5, r6, r7 ; addi r15, r16, 5 }
{ ld4s r25, r26 ; sub r5, r6, r7 ; shru r15, r16, r17 }
{ ld4s r25, r26 ; subx r15, r16, r17 ; mz r5, r6, r7 }
{ ld4s r25, r26 ; subx r5, r6, r7 ; cmpltsi r15, r16, 5 }
{ ld4s r25, r26 ; tblidxb0 r5, r6 ; and r15, r16, r17 }
{ ld4s r25, r26 ; tblidxb0 r5, r6 ; subx r15, r16, r17 }
{ ld4s r25, r26 ; tblidxb1 r5, r6 ; shl3addx r15, r16, r17 }
{ ld4s r25, r26 ; tblidxb2 r5, r6 ; rotli r15, r16, 5 }
{ ld4s r25, r26 ; tblidxb3 r5, r6 ; move r15, r16 }
{ ld4s r25, r26 ; xor r15, r16, r17 ; cmpne r5, r6, r7 }
{ ld4s r25, r26 ; xor r15, r16, r17 ; subx r5, r6, r7 }
{ ld4s r25, r26 ; xor r5, r6, r7 ; shl1addx r15, r16, r17 }
{ ld4s_add r15, r16, 5 ; cmulaf r5, r6, r7 }
{ ld4s_add r15, r16, 5 ; mul_hu_ls r5, r6, r7 }
{ ld4s_add r15, r16, 5 ; shru r5, r6, r7 }
{ ld4s_add r15, r16, 5 ; v1minu r5, r6, r7 }
{ ld4s_add r15, r16, 5 ; v2mulfsc r5, r6, r7 }
{ ld4u r15, r16 ; and r5, r6, r7 }
{ ld4u r15, r16 ; fsingle_add1 r5, r6, r7 }
{ ld4u r15, r16 ; ori r5, r6, 5 }
{ ld4u r15, r16 ; v1cmplts r5, r6, r7 }
{ ld4u r15, r16 ; v2avgs r5, r6, r7 }
{ ld4u r15, r16 ; v4addsc r5, r6, r7 }
{ ld4u r25, r26 ; add r15, r16, r17 ; mula_hs_hs r5, r6, r7 }
{ ld4u r25, r26 ; add r5, r6, r7 ; andi r15, r16, 5 }
{ ld4u r25, r26 ; add r5, r6, r7 ; xor r15, r16, r17 }
{ ld4u r25, r26 ; addi r15, r16, 5 ; pcnt r5, r6 }
{ ld4u r25, r26 ; addi r5, r6, 5 ; ill }
{ ld4u r25, r26 ; addx r15, r16, r17 ; cmovnez r5, r6, r7 }
{ ld4u r25, r26 ; addx r15, r16, r17 ; shl3add r5, r6, r7 }
{ ld4u r25, r26 ; addx r5, r6, r7 ; mz r15, r16, r17 }
{ ld4u r25, r26 ; addxi r15, r16, 5 ; fnop }
{ ld4u r25, r26 ; addxi r15, r16, 5 ; tblidxb1 r5, r6 }
{ ld4u r25, r26 ; addxi r5, r6, 5 ; shl2addx r15, r16, r17 }
{ ld4u r25, r26 ; and r15, r16, r17 ; mula_hs_hs r5, r6, r7 }
{ ld4u r25, r26 ; and r5, r6, r7 ; andi r15, r16, 5 }
{ ld4u r25, r26 ; and r5, r6, r7 ; xor r15, r16, r17 }
{ ld4u r25, r26 ; andi r15, r16, 5 ; pcnt r5, r6 }
{ ld4u r25, r26 ; andi r5, r6, 5 ; ill }
{ ld4u r25, r26 ; clz r5, r6 ; cmples r15, r16, r17 }
{ ld4u r25, r26 ; cmoveqz r5, r6, r7 ; addi r15, r16, 5 }
{ ld4u r25, r26 ; cmoveqz r5, r6, r7 ; shru r15, r16, r17 }
{ ld4u r25, r26 ; cmovnez r5, r6, r7 ; shl2add r15, r16, r17 }
{ ld4u r25, r26 ; cmpeq r15, r16, r17 ; mul_lu_lu r5, r6, r7 }
{ ld4u r25, r26 ; cmpeq r5, r6, r7 ; and r15, r16, r17 }
{ ld4u r25, r26 ; cmpeq r5, r6, r7 ; subx r15, r16, r17 }
{ ld4u r25, r26 ; cmpeqi r15, r16, 5 ; or r5, r6, r7 }
{ ld4u r25, r26 ; cmpeqi r5, r6, 5 ; fnop }
{ ld4u r25, r26 ; cmples r15, r16, r17 ; cmoveqz r5, r6, r7 }
{ ld4u r25, r26 ; cmples r15, r16, r17 ; shl2addx r5, r6, r7 }
{ ld4u r25, r26 ; cmples r5, r6, r7 ; movei r15, 5 }
{ ld4u r25, r26 ; cmpleu r15, r16, r17 ; ctz r5, r6 }
{ ld4u r25, r26 ; cmpleu r15, r16, r17 ; tblidxb0 r5, r6 }
{ ld4u r25, r26 ; cmpleu r5, r6, r7 ; shl2add r15, r16, r17 }
{ ld4u r25, r26 ; cmplts r15, r16, r17 ; mul_lu_lu r5, r6, r7 }
{ ld4u r25, r26 ; cmplts r5, r6, r7 ; and r15, r16, r17 }
{ ld4u r25, r26 ; cmplts r5, r6, r7 ; subx r15, r16, r17 }
{ ld4u r25, r26 ; cmpltsi r15, r16, 5 ; or r5, r6, r7 }
{ ld4u r25, r26 ; cmpltsi r5, r6, 5 ; fnop }
{ ld4u r25, r26 ; cmpltu r15, r16, r17 ; cmoveqz r5, r6, r7 }
{ ld4u r25, r26 ; cmpltu r15, r16, r17 ; shl2addx r5, r6, r7 }
{ ld4u r25, r26 ; cmpltu r5, r6, r7 ; movei r15, 5 }
{ ld4u r25, r26 ; cmpne r15, r16, r17 ; ctz r5, r6 }
{ ld4u r25, r26 ; cmpne r15, r16, r17 ; tblidxb0 r5, r6 }
{ ld4u r25, r26 ; cmpne r5, r6, r7 ; shl2add r15, r16, r17 }
{ ld4u r25, r26 ; ctz r5, r6 ; nor r15, r16, r17 }
{ ld4u r25, r26 ; fnop ; cmples r5, r6, r7 }
{ ld4u r25, r26 ; fnop ; nor r15, r16, r17 }
{ ld4u r25, r26 ; fnop ; tblidxb1 r5, r6 }
{ ld4u r25, r26 ; fsingle_pack1 r5, r6 ; shl2add r15, r16, r17 }
{ ld4u r25, r26 ; ill ; mul_lu_lu r5, r6, r7 }
{ ld4u r25, r26 ; info 19 ; addx r15, r16, r17 }
{ ld4u r25, r26 ; info 19 ; move r5, r6 }
{ ld4u r25, r26 ; info 19 ; shl3addx r5, r6, r7 }
{ ld4u r25, r26 ; jalr r15 ; fnop }
{ ld4u r25, r26 ; jalr r15 ; tblidxb1 r5, r6 }
{ ld4u r25, r26 ; jalrp r15 ; nop }
{ ld4u r25, r26 ; jr r15 ; cmpleu r5, r6, r7 }
{ ld4u r25, r26 ; jr r15 ; shrsi r5, r6, 5 }
{ ld4u r25, r26 ; jrp r15 ; mula_hu_hu r5, r6, r7 }
{ ld4u r25, r26 ; lnk r15 ; clz r5, r6 }
{ ld4u r25, r26 ; lnk r15 ; shl2add r5, r6, r7 }
{ ld4u r25, r26 ; mnz r15, r16, r17 ; movei r5, 5 }
{ ld4u r25, r26 ; mnz r5, r6, r7 ; add r15, r16, r17 }
{ ld4u r25, r26 ; mnz r5, r6, r7 ; shrsi r15, r16, 5 }
{ ld4u r25, r26 ; move r15, r16 ; mulx r5, r6, r7 }
{ ld4u r25, r26 ; move r5, r6 ; cmplts r15, r16, r17 }
{ ld4u r25, r26 ; movei r15, 5 ; addxi r5, r6, 5 }
{ ld4u r25, r26 ; movei r15, 5 ; shl r5, r6, r7 }
{ ld4u r25, r26 ; movei r5, 5 ; jrp r15 }
{ ld4u r25, r26 ; mul_hs_hs r5, r6, r7 ; cmpne r15, r16, r17 }
{ ld4u r25, r26 ; mul_hu_hu r5, r6, r7 ; cmpeq r15, r16, r17 }
{ ld4u r25, r26 ; mul_hu_hu r5, r6, r7 }
{ ld4u r25, r26 ; mul_ls_ls r5, r6, r7 ; shrs r15, r16, r17 }
{ ld4u r25, r26 ; mul_lu_lu r5, r6, r7 ; shl1add r15, r16, r17 }
{ ld4u r25, r26 ; mula_hs_hs r5, r6, r7 ; mz r15, r16, r17 }
{ ld4u r25, r26 ; mula_hu_hu r5, r6, r7 ; jalrp r15 }
{ ld4u r25, r26 ; mula_ls_ls r5, r6, r7 ; cmpltsi r15, r16, 5 }
{ ld4u r25, r26 ; mula_lu_lu r5, r6, r7 ; and r15, r16, r17 }
{ ld4u r25, r26 ; mula_lu_lu r5, r6, r7 ; subx r15, r16, r17 }
{ ld4u r25, r26 ; mulax r5, r6, r7 ; shl3addx r15, r16, r17 }
{ ld4u r25, r26 ; mulx r5, r6, r7 ; rotli r15, r16, 5 }
{ ld4u r25, r26 ; mz r15, r16, r17 ; movei r5, 5 }
{ ld4u r25, r26 ; mz r5, r6, r7 ; add r15, r16, r17 }
{ ld4u r25, r26 ; mz r5, r6, r7 ; shrsi r15, r16, 5 }
{ ld4u r25, r26 ; nop ; fsingle_pack1 r5, r6 }
{ ld4u r25, r26 ; nop ; shl1add r15, r16, r17 }
{ ld4u r25, r26 ; nor r15, r16, r17 ; cmoveqz r5, r6, r7 }
{ ld4u r25, r26 ; nor r15, r16, r17 ; shl2addx r5, r6, r7 }
{ ld4u r25, r26 ; nor r5, r6, r7 ; movei r15, 5 }
{ ld4u r25, r26 ; or r15, r16, r17 ; ctz r5, r6 }
{ ld4u r25, r26 ; or r15, r16, r17 ; tblidxb0 r5, r6 }
{ ld4u r25, r26 ; or r5, r6, r7 ; shl2add r15, r16, r17 }
{ ld4u r25, r26 ; pcnt r5, r6 ; nor r15, r16, r17 }
{ ld4u r25, r26 ; revbits r5, r6 ; jrp r15 }
{ ld4u r25, r26 ; revbytes r5, r6 ; cmpne r15, r16, r17 }
{ ld4u r25, r26 ; rotl r15, r16, r17 ; clz r5, r6 }
{ ld4u r25, r26 ; rotl r15, r16, r17 ; shl2add r5, r6, r7 }
{ ld4u r25, r26 ; rotl r5, r6, r7 ; move r15, r16 }
{ ld4u r25, r26 ; rotli r15, r16, 5 ; cmpne r5, r6, r7 }
{ ld4u r25, r26 ; rotli r15, r16, 5 ; subx r5, r6, r7 }
{ ld4u r25, r26 ; rotli r5, r6, 5 ; shl1addx r15, r16, r17 }
{ ld4u r25, r26 ; shl r15, r16, r17 ; mul_ls_ls r5, r6, r7 }
{ ld4u r25, r26 ; shl r5, r6, r7 ; addxi r15, r16, 5 }
{ ld4u r25, r26 ; shl r5, r6, r7 ; sub r15, r16, r17 }
{ ld4u r25, r26 ; shl1add r15, r16, r17 ; nor r5, r6, r7 }
{ ld4u r25, r26 ; shl1add r5, r6, r7 ; cmpne r15, r16, r17 }
{ ld4u r25, r26 ; shl1addx r15, r16, r17 ; clz r5, r6 }
{ ld4u r25, r26 ; shl1addx r15, r16, r17 ; shl2add r5, r6, r7 }
{ ld4u r25, r26 ; shl1addx r5, r6, r7 ; move r15, r16 }
{ ld4u r25, r26 ; shl2add r15, r16, r17 ; cmpne r5, r6, r7 }
{ ld4u r25, r26 ; shl2add r15, r16, r17 ; subx r5, r6, r7 }
{ ld4u r25, r26 ; shl2add r5, r6, r7 ; shl1addx r15, r16, r17 }
{ ld4u r25, r26 ; shl2addx r15, r16, r17 ; mul_ls_ls r5, r6, r7 }
{ ld4u r25, r26 ; shl2addx r5, r6, r7 ; addxi r15, r16, 5 }
{ ld4u r25, r26 ; shl2addx r5, r6, r7 ; sub r15, r16, r17 }
{ ld4u r25, r26 ; shl3add r15, r16, r17 ; nor r5, r6, r7 }
{ ld4u r25, r26 ; shl3add r5, r6, r7 ; cmpne r15, r16, r17 }
{ ld4u r25, r26 ; shl3addx r15, r16, r17 ; clz r5, r6 }
{ ld4u r25, r26 ; shl3addx r15, r16, r17 ; shl2add r5, r6, r7 }
{ ld4u r25, r26 ; shl3addx r5, r6, r7 ; move r15, r16 }
{ ld4u r25, r26 ; shli r15, r16, 5 ; cmpne r5, r6, r7 }
{ ld4u r25, r26 ; shli r15, r16, 5 ; subx r5, r6, r7 }
{ ld4u r25, r26 ; shli r5, r6, 5 ; shl1addx r15, r16, r17 }
{ ld4u r25, r26 ; shrs r15, r16, r17 ; mul_ls_ls r5, r6, r7 }
{ ld4u r25, r26 ; shrs r5, r6, r7 ; addxi r15, r16, 5 }
{ ld4u r25, r26 ; shrs r5, r6, r7 ; sub r15, r16, r17 }
{ ld4u r25, r26 ; shrsi r15, r16, 5 ; nor r5, r6, r7 }
{ ld4u r25, r26 ; shrsi r5, r6, 5 ; cmpne r15, r16, r17 }
{ ld4u r25, r26 ; shru r15, r16, r17 ; clz r5, r6 }
{ ld4u r25, r26 ; shru r15, r16, r17 ; shl2add r5, r6, r7 }
{ ld4u r25, r26 ; shru r5, r6, r7 ; move r15, r16 }
{ ld4u r25, r26 ; shrui r15, r16, 5 ; cmpne r5, r6, r7 }
{ ld4u r25, r26 ; shrui r15, r16, 5 ; subx r5, r6, r7 }
{ ld4u r25, r26 ; shrui r5, r6, 5 ; shl1addx r15, r16, r17 }
{ ld4u r25, r26 ; sub r15, r16, r17 ; mul_ls_ls r5, r6, r7 }
{ ld4u r25, r26 ; sub r5, r6, r7 ; addxi r15, r16, 5 }
{ ld4u r25, r26 ; sub r5, r6, r7 ; sub r15, r16, r17 }
{ ld4u r25, r26 ; subx r15, r16, r17 ; nor r5, r6, r7 }
{ ld4u r25, r26 ; subx r5, r6, r7 ; cmpne r15, r16, r17 }
{ ld4u r25, r26 ; tblidxb0 r5, r6 ; cmpeq r15, r16, r17 }
{ ld4u r25, r26 ; tblidxb0 r5, r6 }
{ ld4u r25, r26 ; tblidxb1 r5, r6 ; shrs r15, r16, r17 }
{ ld4u r25, r26 ; tblidxb2 r5, r6 ; shl1add r15, r16, r17 }
{ ld4u r25, r26 ; tblidxb3 r5, r6 ; mz r15, r16, r17 }
{ ld4u r25, r26 ; xor r15, r16, r17 ; fnop }
{ ld4u r25, r26 ; xor r15, r16, r17 ; tblidxb1 r5, r6 }
{ ld4u r25, r26 ; xor r5, r6, r7 ; shl2addx r15, r16, r17 }
{ ld4u_add r15, r16, 5 ; cmulfr r5, r6, r7 }
{ ld4u_add r15, r16, 5 ; mul_ls_ls r5, r6, r7 }
{ ld4u_add r15, r16, 5 ; shrux r5, r6, r7 }
{ ld4u_add r15, r16, 5 ; v1mnz r5, r6, r7 }
{ ld4u_add r15, r16, 5 ; v2mults r5, r6, r7 }
{ ld_add r15, r16, 5 ; bfexts r5, r6, 5, 7 }
{ ld_add r15, r16, 5 ; fsingle_mul1 r5, r6, r7 }
{ ld_add r15, r16, 5 ; revbits r5, r6 }
{ ld_add r15, r16, 5 ; v1cmpltu r5, r6, r7 }
{ ld_add r15, r16, 5 ; v2cmpeqi r5, r6, 5 }
{ ld_add r15, r16, 5 ; v4int_l r5, r6, r7 }
{ ldna r15, r16 ; cmulhr r5, r6, r7 }
{ ldna r15, r16 ; mul_lu_lu r5, r6, r7 }
{ ldna r15, r16 ; shufflebytes r5, r6, r7 }
{ ldna r15, r16 ; v1mulu r5, r6, r7 }
{ ldna r15, r16 ; v2packh r5, r6, r7 }
{ ldna_add r15, r16, 5 ; bfins r5, r6, 5, 7 }
{ ldna_add r15, r16, 5 ; fsingle_pack1 r5, r6 }
{ ldna_add r15, r16, 5 ; rotl r5, r6, r7 }
{ ldna_add r15, r16, 5 ; v1cmpne r5, r6, r7 }
{ ldna_add r15, r16, 5 ; v2cmpleu r5, r6, r7 }
{ ldna_add r15, r16, 5 ; v4shl r5, r6, r7 }
{ ldnt r15, r16 ; crc32_8 r5, r6, r7 }
{ ldnt r15, r16 ; mula_hs_hu r5, r6, r7 }
{ ldnt r15, r16 ; subx r5, r6, r7 }
{ ldnt r15, r16 ; v1mz r5, r6, r7 }
{ ldnt r15, r16 ; v2packuc r5, r6, r7 }
{ ldnt1s r15, r16 ; cmoveqz r5, r6, r7 }
{ ldnt1s r15, r16 ; fsingle_sub1 r5, r6, r7 }
{ ldnt1s r15, r16 ; shl r5, r6, r7 }
{ ldnt1s r15, r16 ; v1ddotpua r5, r6, r7 }
{ ldnt1s r15, r16 ; v2cmpltsi r5, r6, 5 }
{ ldnt1s r15, r16 ; v4shrs r5, r6, r7 }
{ ldnt1s_add r15, r16, 5 ; dblalign r5, r6, r7 }
{ ldnt1s_add r15, r16, 5 ; mula_hs_lu r5, r6, r7 }
{ ldnt1s_add r15, r16, 5 ; tblidxb0 r5, r6 }
{ ldnt1s_add r15, r16, 5 ; v1sadu r5, r6, r7 }
{ ldnt1s_add r15, r16, 5 ; v2sadau r5, r6, r7 }
{ ldnt1u r15, r16 ; cmpeq r5, r6, r7 }
{ ldnt1u r15, r16 ; infol 0x1234 }
{ ldnt1u r15, r16 ; shl1add r5, r6, r7 }
{ ldnt1u r15, r16 ; v1ddotpusa r5, r6, r7 }
{ ldnt1u r15, r16 ; v2cmpltui r5, r6, 5 }
{ ldnt1u r15, r16 ; v4sub r5, r6, r7 }
{ ldnt1u_add r15, r16, 5 ; dblalign4 r5, r6, r7 }
{ ldnt1u_add r15, r16, 5 ; mula_hu_ls r5, r6, r7 }
{ ldnt1u_add r15, r16, 5 ; tblidxb2 r5, r6 }
{ ldnt1u_add r15, r16, 5 ; v1shli r5, r6, 5 }
{ ldnt1u_add r15, r16, 5 ; v2sadu r5, r6, r7 }
{ ldnt2s r15, r16 ; cmples r5, r6, r7 }
{ ldnt2s r15, r16 ; mnz r5, r6, r7 }
{ ldnt2s r15, r16 ; shl2add r5, r6, r7 }
{ ldnt2s r15, r16 ; v1dotpa r5, r6, r7 }
{ ldnt2s r15, r16 ; v2dotp r5, r6, r7 }
{ ldnt2s r15, r16 ; xor r5, r6, r7 }
{ ldnt2s_add r15, r16, 5 ; fdouble_add_flags r5, r6, r7 }
{ ldnt2s_add r15, r16, 5 ; mula_ls_ls r5, r6, r7 }
{ ldnt2s_add r15, r16, 5 ; v1add r5, r6, r7 }
{ ldnt2s_add r15, r16, 5 ; v1shrsi r5, r6, 5 }
{ ldnt2s_add r15, r16, 5 ; v2shli r5, r6, 5 }
{ ldnt2u r15, r16 ; cmplts r5, r6, r7 }
{ ldnt2u r15, r16 ; movei r5, 5 }
{ ldnt2u r15, r16 ; shl3add r5, r6, r7 }
{ ldnt2u r15, r16 ; v1dotpua r5, r6, r7 }
{ ldnt2u r15, r16 ; v2int_h r5, r6, r7 }
{ ldnt2u_add r15, r16, 5 ; add r5, r6, r7 }
{ ldnt2u_add r15, r16, 5 ; fdouble_mul_flags r5, r6, r7 }
{ ldnt2u_add r15, r16, 5 ; mula_lu_lu r5, r6, r7 }
{ ldnt2u_add r15, r16, 5 ; v1adduc r5, r6, r7 }
{ ldnt2u_add r15, r16, 5 ; v1shrui r5, r6, 5 }
{ ldnt2u_add r15, r16, 5 ; v2shrs r5, r6, r7 }
{ ldnt4s r15, r16 ; cmpltu r5, r6, r7 }
{ ldnt4s r15, r16 ; mul_hs_hs r5, r6, r7 }
{ ldnt4s r15, r16 ; shli r5, r6, 5 }
{ ldnt4s r15, r16 ; v1dotpusa r5, r6, r7 }
{ ldnt4s r15, r16 ; v2maxs r5, r6, r7 }
{ ldnt4s_add r15, r16, 5 ; addli r5, r6, 0x1234 }
{ ldnt4s_add r15, r16, 5 ; fdouble_pack2 r5, r6, r7 }
{ ldnt4s_add r15, r16, 5 ; mulx r5, r6, r7 }
{ ldnt4s_add r15, r16, 5 ; v1avgu r5, r6, r7 }
{ ldnt4s_add r15, r16, 5 ; v1subuc r5, r6, r7 }
{ ldnt4s_add r15, r16, 5 ; v2shru r5, r6, r7 }
{ ldnt4u r15, r16 ; cmpne r5, r6, r7 }
{ ldnt4u r15, r16 ; mul_hs_ls r5, r6, r7 }
{ ldnt4u r15, r16 ; shlxi r5, r6, 5 }
{ ldnt4u r15, r16 ; v1int_l r5, r6, r7 }
{ ldnt4u r15, r16 ; v2mins r5, r6, r7 }
{ ldnt4u_add r15, r16, 5 ; addxi r5, r6, 5 }
{ ldnt4u_add r15, r16, 5 ; fdouble_unpack_max r5, r6, r7 }
{ ldnt4u_add r15, r16, 5 ; nop }
{ ldnt4u_add r15, r16, 5 ; v1cmpeqi r5, r6, 5 }
{ ldnt4u_add r15, r16, 5 ; v2addi r5, r6, 5 }
{ ldnt4u_add r15, r16, 5 ; v2sub r5, r6, r7 }
{ ldnt_add r15, r16, 5 ; cmula r5, r6, r7 }
{ ldnt_add r15, r16, 5 ; mul_hu_hu r5, r6, r7 }
{ ldnt_add r15, r16, 5 ; shrsi r5, r6, 5 }
{ ldnt_add r15, r16, 5 ; v1maxui r5, r6, 5 }
{ ldnt_add r15, r16, 5 ; v2mnz r5, r6, r7 }
{ lnk r15 ; add r5, r6, r7 ; ld4u r25, r26 }
{ lnk r15 ; addx r5, r6, r7 ; prefetch r25 }
{ lnk r15 ; and r5, r6, r7 ; prefetch r25 }
{ lnk r15 ; clz r5, r6 ; ld4u r25, r26 }
{ lnk r15 ; cmovnez r5, r6, r7 ; prefetch_l1 r25 }
{ lnk r15 ; cmpeqi r5, r6, 5 ; prefetch_l2 r25 }
{ lnk r15 ; cmpleu r5, r6, r7 ; prefetch_l3 r25 }
{ lnk r15 ; cmpltsi r5, r6, 5 ; st r25, r26 }
{ lnk r15 ; cmpne r5, r6, r7 ; st1 r25, r26 }
{ lnk r15 ; fdouble_pack2 r5, r6, r7 }
{ lnk r15 ; fsingle_pack1 r5, r6 ; prefetch_l3_fault r25 }
{ lnk r15 ; ld r25, r26 ; cmpleu r5, r6, r7 }
{ lnk r15 ; ld r25, r26 ; shrsi r5, r6, 5 }
{ lnk r15 ; ld1s r25, r26 ; mula_hu_hu r5, r6, r7 }
{ lnk r15 ; ld1u r25, r26 ; clz r5, r6 }
{ lnk r15 ; ld1u r25, r26 ; shl2add r5, r6, r7 }
{ lnk r15 ; ld2s r25, r26 ; movei r5, 5 }
{ lnk r15 ; ld2u r25, r26 ; add r5, r6, r7 }
{ lnk r15 ; ld2u r25, r26 ; revbytes r5, r6 }
{ lnk r15 ; ld4s r25, r26 ; ctz r5, r6 }
{ lnk r15 ; ld4s r25, r26 ; tblidxb0 r5, r6 }
{ lnk r15 ; ld4u r25, r26 ; mz r5, r6, r7 }
{ lnk r15 ; mnz r5, r6, r7 ; prefetch_l2 r25 }
{ lnk r15 ; movei r5, 5 ; prefetch_l3 r25 }
{ lnk r15 ; mul_hu_hu r5, r6, r7 ; prefetch_l2 r25 }
{ lnk r15 ; mul_lu_lu r5, r6, r7 ; prefetch_l1_fault r25 }
{ lnk r15 ; mula_hu_hu r5, r6, r7 ; prefetch_l1 r25 }
{ lnk r15 ; mula_lu_lu r5, r6, r7 ; prefetch r25 }
{ lnk r15 ; mulx r5, r6, r7 ; prefetch_l1_fault r25 }
{ lnk r15 ; nop ; prefetch_l2_fault r25 }
{ lnk r15 ; or r5, r6, r7 ; prefetch_l3_fault r25 }
{ lnk r15 ; prefetch r25 ; cmpltsi r5, r6, 5 }
{ lnk r15 ; prefetch r25 ; shrui r5, r6, 5 }
{ lnk r15 ; prefetch_l1 r25 ; mula_lu_lu r5, r6, r7 }
{ lnk r15 ; prefetch_l1_fault r25 ; cmovnez r5, r6, r7 }
{ lnk r15 ; prefetch_l1_fault r25 ; shl3add r5, r6, r7 }
{ lnk r15 ; prefetch_l2 r25 ; mul_hu_hu r5, r6, r7 }
{ lnk r15 ; prefetch_l2_fault r25 ; addx r5, r6, r7 }
{ lnk r15 ; prefetch_l2_fault r25 ; rotli r5, r6, 5 }
{ lnk r15 ; prefetch_l3 r25 ; fsingle_pack1 r5, r6 }
{ lnk r15 ; prefetch_l3 r25 ; tblidxb2 r5, r6 }
{ lnk r15 ; prefetch_l3_fault r25 ; nor r5, r6, r7 }
{ lnk r15 ; revbits r5, r6 ; prefetch_l3_fault r25 }
{ lnk r15 ; rotl r5, r6, r7 ; st1 r25, r26 }
{ lnk r15 ; shl r5, r6, r7 ; st4 r25, r26 }
{ lnk r15 ; shl1addx r5, r6, r7 }
{ lnk r15 ; shl3add r5, r6, r7 ; ld1s r25, r26 }
{ lnk r15 ; shli r5, r6, 5 ; ld2s r25, r26 }
{ lnk r15 ; shrsi r5, r6, 5 ; ld2s r25, r26 }
{ lnk r15 ; shrui r5, r6, 5 ; ld4s r25, r26 }
{ lnk r15 ; st r25, r26 ; movei r5, 5 }
{ lnk r15 ; st1 r25, r26 ; add r5, r6, r7 }
{ lnk r15 ; st1 r25, r26 ; revbytes r5, r6 }
{ lnk r15 ; st2 r25, r26 ; ctz r5, r6 }
{ lnk r15 ; st2 r25, r26 ; tblidxb0 r5, r6 }
{ lnk r15 ; st4 r25, r26 ; mz r5, r6, r7 }
{ lnk r15 ; sub r5, r6, r7 ; prefetch_l2_fault r25 }
{ lnk r15 ; tblidxb0 r5, r6 ; prefetch_l3 r25 }
{ lnk r15 ; tblidxb2 r5, r6 ; st r25, r26 }
{ lnk r15 ; v1ddotpus r5, r6, r7 }
{ lnk r15 ; v2cmpltu r5, r6, r7 }
{ lnk r15 ; v4shru r5, r6, r7 }
{ mf ; cmples r5, r6, r7 }
{ mf ; mnz r5, r6, r7 }
{ mf ; shl2add r5, r6, r7 }
{ mf ; v1dotpa r5, r6, r7 }
{ mf ; v2dotp r5, r6, r7 }
{ mf ; xor r5, r6, r7 }
{ mfspr r16, 0x5 ; fdouble_add_flags r5, r6, r7 }
{ mfspr r16, 0x5 ; mula_ls_ls r5, r6, r7 }
{ mfspr r16, 0x5 ; v1add r5, r6, r7 }
{ mfspr r16, 0x5 ; v1shrsi r5, r6, 5 }
{ mfspr r16, 0x5 ; v2shli r5, r6, 5 }
{ mm r5, r6, 5, 7 ; cmpne r15, r16, r17 }
{ mm r5, r6, 5, 7 ; ld4u r15, r16 }
{ mm r5, r6, 5, 7 ; prefetch_l1_fault r15 }
{ mm r5, r6, 5, 7 ; stnt_add r15, r16, 5 }
{ mm r5, r6, 5, 7 ; v2cmpltsi r15, r16, 5 }
{ mnz r15, r16, r17 ; add r5, r6, r7 ; ld1u r25, r26 }
{ mnz r15, r16, r17 ; addx r5, r6, r7 ; ld2s r25, r26 }
{ mnz r15, r16, r17 ; and r5, r6, r7 ; ld2s r25, r26 }
{ mnz r15, r16, r17 ; clz r5, r6 ; ld1u r25, r26 }
{ mnz r15, r16, r17 ; cmovnez r5, r6, r7 ; ld2u r25, r26 }
{ mnz r15, r16, r17 ; cmpeqi r5, r6, 5 ; ld4u r25, r26 }
{ mnz r15, r16, r17 ; cmpleu r5, r6, r7 ; prefetch_l1 r25 }
{ mnz r15, r16, r17 ; cmpltsi r5, r6, 5 ; prefetch_l2 r25 }
{ mnz r15, r16, r17 ; cmpne r5, r6, r7 ; prefetch_l2_fault r25 }
{ mnz r15, r16, r17 ; fdouble_add_flags r5, r6, r7 }
{ mnz r15, r16, r17 ; fsingle_pack1 r5, r6 ; prefetch_l1_fault r25 }
{ mnz r15, r16, r17 ; ld r25, r26 ; cmovnez r5, r6, r7 }
{ mnz r15, r16, r17 ; ld r25, r26 ; shl3add r5, r6, r7 }
{ mnz r15, r16, r17 ; ld1s r25, r26 ; mul_hu_hu r5, r6, r7 }
{ mnz r15, r16, r17 ; ld1u r25, r26 ; addx r5, r6, r7 }
{ mnz r15, r16, r17 ; ld1u r25, r26 ; rotli r5, r6, 5 }
{ mnz r15, r16, r17 ; ld2s r25, r26 ; fsingle_pack1 r5, r6 }
{ mnz r15, r16, r17 ; ld2s r25, r26 ; tblidxb2 r5, r6 }
{ mnz r15, r16, r17 ; ld2u r25, r26 ; nor r5, r6, r7 }
{ mnz r15, r16, r17 ; ld4s r25, r26 ; cmplts r5, r6, r7 }
{ mnz r15, r16, r17 ; ld4s r25, r26 ; shru r5, r6, r7 }
{ mnz r15, r16, r17 ; ld4u r25, r26 ; mula_ls_ls r5, r6, r7 }
{ mnz r15, r16, r17 ; mnz r5, r6, r7 ; ld4u r25, r26 }
{ mnz r15, r16, r17 ; movei r5, 5 ; prefetch_l1 r25 }
{ mnz r15, r16, r17 ; mul_hu_hu r5, r6, r7 ; ld4u r25, r26 }
{ mnz r15, r16, r17 ; mul_lu_lu r5, r6, r7 ; ld4s r25, r26 }
{ mnz r15, r16, r17 ; mula_hu_hu r5, r6, r7 ; ld2u r25, r26 }
{ mnz r15, r16, r17 ; mula_lu_lu r5, r6, r7 ; ld2s r25, r26 }
{ mnz r15, r16, r17 ; mulx r5, r6, r7 ; ld4s r25, r26 }
{ mnz r15, r16, r17 ; nop ; prefetch r25 }
{ mnz r15, r16, r17 ; or r5, r6, r7 ; prefetch_l1_fault r25 }
{ mnz r15, r16, r17 ; prefetch r25 ; cmpeqi r5, r6, 5 }
{ mnz r15, r16, r17 ; prefetch r25 ; shli r5, r6, 5 }
{ mnz r15, r16, r17 ; prefetch_l1 r25 ; mul_lu_lu r5, r6, r7 }
{ mnz r15, r16, r17 ; prefetch_l1_fault r25 ; and r5, r6, r7 }
{ mnz r15, r16, r17 ; prefetch_l1_fault r25 ; shl1add r5, r6, r7 }
{ mnz r15, r16, r17 ; prefetch_l2 r25 ; mnz r5, r6, r7 }
{ mnz r15, r16, r17 ; prefetch_l2 r25 ; xor r5, r6, r7 }
{ mnz r15, r16, r17 ; prefetch_l2_fault r25 ; pcnt r5, r6 }
{ mnz r15, r16, r17 ; prefetch_l3 r25 ; cmpltu r5, r6, r7 }
{ mnz r15, r16, r17 ; prefetch_l3 r25 ; sub r5, r6, r7 }
{ mnz r15, r16, r17 ; prefetch_l3_fault r25 ; mulax r5, r6, r7 }
{ mnz r15, r16, r17 ; revbits r5, r6 ; prefetch_l1_fault r25 }
{ mnz r15, r16, r17 ; rotl r5, r6, r7 ; prefetch_l2_fault r25 }
{ mnz r15, r16, r17 ; shl r5, r6, r7 ; prefetch_l3_fault r25 }
{ mnz r15, r16, r17 ; shl1addx r5, r6, r7 ; st r25, r26 }
{ mnz r15, r16, r17 ; shl2addx r5, r6, r7 ; st2 r25, r26 }
{ mnz r15, r16, r17 ; shl3addx r5, r6, r7 }
{ mnz r15, r16, r17 ; shrs r5, r6, r7 }
{ mnz r15, r16, r17 ; shrui r5, r6, 5 ; ld1s r25, r26 }
{ mnz r15, r16, r17 ; st r25, r26 ; fsingle_pack1 r5, r6 }
{ mnz r15, r16, r17 ; st r25, r26 ; tblidxb2 r5, r6 }
{ mnz r15, r16, r17 ; st1 r25, r26 ; nor r5, r6, r7 }
{ mnz r15, r16, r17 ; st2 r25, r26 ; cmplts r5, r6, r7 }
{ mnz r15, r16, r17 ; st2 r25, r26 ; shru r5, r6, r7 }
{ mnz r15, r16, r17 ; st4 r25, r26 ; mula_ls_ls r5, r6, r7 }
{ mnz r15, r16, r17 ; sub r5, r6, r7 ; prefetch r25 }
{ mnz r15, r16, r17 ; tblidxb0 r5, r6 ; prefetch_l1 r25 }
{ mnz r15, r16, r17 ; tblidxb2 r5, r6 ; prefetch_l2 r25 }
{ mnz r15, r16, r17 ; v1cmpltui r5, r6, 5 }
{ mnz r15, r16, r17 ; v2cmples r5, r6, r7 }
{ mnz r15, r16, r17 ; v4packsc r5, r6, r7 }
{ mnz r5, r6, r7 ; add r15, r16, r17 ; prefetch_l3_fault r25 }
{ mnz r5, r6, r7 ; addx r15, r16, r17 ; st r25, r26 }
{ mnz r5, r6, r7 ; and r15, r16, r17 ; st r25, r26 }
{ mnz r5, r6, r7 ; cmpeq r15, r16, r17 ; st2 r25, r26 }
{ mnz r5, r6, r7 ; cmples r15, r16, r17 ; st2 r25, r26 }
{ mnz r5, r6, r7 ; cmplts r15, r16, r17 }
{ mnz r5, r6, r7 ; cmpne r15, r16, r17 ; ld r25, r26 }
{ mnz r5, r6, r7 ; fnop ; ld2u r25, r26 }
{ mnz r5, r6, r7 ; info 19 ; ld4s r25, r26 }
{ mnz r5, r6, r7 ; jalrp r15 ; ld2u r25, r26 }
{ mnz r5, r6, r7 ; jrp r15 ; ld4u r25, r26 }
{ mnz r5, r6, r7 ; ld r25, r26 ; nop }
{ mnz r5, r6, r7 ; ld1s r25, r26 ; jalrp r15 }
{ mnz r5, r6, r7 ; ld1u r25, r26 ; cmpleu r15, r16, r17 }
{ mnz r5, r6, r7 ; ld2s r25, r26 ; add r15, r16, r17 }
{ mnz r5, r6, r7 ; ld2s r25, r26 ; shrsi r15, r16, 5 }
{ mnz r5, r6, r7 ; ld2u r25, r26 ; shl r15, r16, r17 }
{ mnz r5, r6, r7 ; ld4s r25, r26 ; mnz r15, r16, r17 }
{ mnz r5, r6, r7 ; ld4u r25, r26 ; cmpne r15, r16, r17 }
{ mnz r5, r6, r7 ; ldnt1s_add r15, r16, 5 }
{ mnz r5, r6, r7 ; mnz r15, r16, r17 ; prefetch r25 }
{ mnz r5, r6, r7 ; movei r15, 5 ; prefetch_l1_fault r25 }
{ mnz r5, r6, r7 ; nop ; prefetch_l1_fault r25 }
{ mnz r5, r6, r7 ; or r15, r16, r17 ; prefetch_l2_fault r25 }
{ mnz r5, r6, r7 ; prefetch r25 ; rotli r15, r16, 5 }
{ mnz r5, r6, r7 ; prefetch_l1 r25 ; info 19 }
{ mnz r5, r6, r7 ; prefetch_l1_fault r25 ; cmples r15, r16, r17 }
{ mnz r5, r6, r7 ; prefetch_l2 r25 ; add r15, r16, r17 }
{ mnz r5, r6, r7 ; prefetch_l2 r25 ; shrsi r15, r16, 5 }
{ mnz r5, r6, r7 ; prefetch_l2_fault r25 ; shl1add r15, r16, r17 }
{ mnz r5, r6, r7 ; prefetch_l3 r25 ; movei r15, 5 }
{ mnz r5, r6, r7 ; prefetch_l3_fault r25 ; info 19 }
{ mnz r5, r6, r7 ; rotl r15, r16, r17 ; prefetch_l1 r25 }
{ mnz r5, r6, r7 ; shl r15, r16, r17 ; prefetch_l2 r25 }
{ mnz r5, r6, r7 ; shl1addx r15, r16, r17 ; prefetch_l2_fault r25 }
{ mnz r5, r6, r7 ; shl2addx r15, r16, r17 ; prefetch_l3_fault r25 }
{ mnz r5, r6, r7 ; shl3addx r15, r16, r17 ; st1 r25, r26 }
{ mnz r5, r6, r7 ; shrs r15, r16, r17 ; st1 r25, r26 }
{ mnz r5, r6, r7 ; shru r15, r16, r17 ; st4 r25, r26 }
{ mnz r5, r6, r7 ; st r25, r26 ; info 19 }
{ mnz r5, r6, r7 ; st1 r25, r26 ; cmples r15, r16, r17 }
{ mnz r5, r6, r7 ; st2 r15, r16 }
{ mnz r5, r6, r7 ; st2 r25, r26 ; shrs r15, r16, r17 }
{ mnz r5, r6, r7 ; st4 r25, r26 ; rotli r15, r16, 5 }
{ mnz r5, r6, r7 ; sub r15, r16, r17 ; prefetch_l3_fault r25 }
{ mnz r5, r6, r7 ; v1maxu r15, r16, r17 }
{ mnz r5, r6, r7 ; v2shrs r15, r16, r17 }
{ move r15, r16 ; add r5, r6, r7 ; ld1u r25, r26 }
{ move r15, r16 ; addx r5, r6, r7 ; ld2s r25, r26 }
{ move r15, r16 ; and r5, r6, r7 ; ld2s r25, r26 }
{ move r15, r16 ; clz r5, r6 ; ld1u r25, r26 }
{ move r15, r16 ; cmovnez r5, r6, r7 ; ld2u r25, r26 }
{ move r15, r16 ; cmpeqi r5, r6, 5 ; ld4u r25, r26 }
{ move r15, r16 ; cmpleu r5, r6, r7 ; prefetch_l1 r25 }
{ move r15, r16 ; cmpltsi r5, r6, 5 ; prefetch_l2 r25 }
{ move r15, r16 ; cmpne r5, r6, r7 ; prefetch_l2_fault r25 }
{ move r15, r16 ; fdouble_add_flags r5, r6, r7 }
{ move r15, r16 ; fsingle_pack1 r5, r6 ; prefetch_l1_fault r25 }
{ move r15, r16 ; ld r25, r26 ; cmovnez r5, r6, r7 }
{ move r15, r16 ; ld r25, r26 ; shl3add r5, r6, r7 }
{ move r15, r16 ; ld1s r25, r26 ; mul_hu_hu r5, r6, r7 }
{ move r15, r16 ; ld1u r25, r26 ; addx r5, r6, r7 }
{ move r15, r16 ; ld1u r25, r26 ; rotli r5, r6, 5 }
{ move r15, r16 ; ld2s r25, r26 ; fsingle_pack1 r5, r6 }
{ move r15, r16 ; ld2s r25, r26 ; tblidxb2 r5, r6 }
{ move r15, r16 ; ld2u r25, r26 ; nor r5, r6, r7 }
{ move r15, r16 ; ld4s r25, r26 ; cmplts r5, r6, r7 }
{ move r15, r16 ; ld4s r25, r26 ; shru r5, r6, r7 }
{ move r15, r16 ; ld4u r25, r26 ; mula_ls_ls r5, r6, r7 }
{ move r15, r16 ; mnz r5, r6, r7 ; ld4u r25, r26 }
{ move r15, r16 ; movei r5, 5 ; prefetch_l1 r25 }
{ move r15, r16 ; mul_hu_hu r5, r6, r7 ; ld4u r25, r26 }
{ move r15, r16 ; mul_lu_lu r5, r6, r7 ; ld4s r25, r26 }
{ move r15, r16 ; mula_hu_hu r5, r6, r7 ; ld2u r25, r26 }
{ move r15, r16 ; mula_lu_lu r5, r6, r7 ; ld2s r25, r26 }
{ move r15, r16 ; mulx r5, r6, r7 ; ld4s r25, r26 }
{ move r15, r16 ; nop ; prefetch r25 }
{ move r15, r16 ; or r5, r6, r7 ; prefetch_l1_fault r25 }
{ move r15, r16 ; prefetch r25 ; cmpeqi r5, r6, 5 }
{ move r15, r16 ; prefetch r25 ; shli r5, r6, 5 }
{ move r15, r16 ; prefetch_l1 r25 ; mul_lu_lu r5, r6, r7 }
{ move r15, r16 ; prefetch_l1_fault r25 ; and r5, r6, r7 }
{ move r15, r16 ; prefetch_l1_fault r25 ; shl1add r5, r6, r7 }
{ move r15, r16 ; prefetch_l2 r25 ; mnz r5, r6, r7 }
{ move r15, r16 ; prefetch_l2 r25 ; xor r5, r6, r7 }
{ move r15, r16 ; prefetch_l2_fault r25 ; pcnt r5, r6 }
{ move r15, r16 ; prefetch_l3 r25 ; cmpltu r5, r6, r7 }
{ move r15, r16 ; prefetch_l3 r25 ; sub r5, r6, r7 }
{ move r15, r16 ; prefetch_l3_fault r25 ; mulax r5, r6, r7 }
{ move r15, r16 ; revbits r5, r6 ; prefetch_l1_fault r25 }
{ move r15, r16 ; rotl r5, r6, r7 ; prefetch_l2_fault r25 }
{ move r15, r16 ; shl r5, r6, r7 ; prefetch_l3_fault r25 }
{ move r15, r16 ; shl1addx r5, r6, r7 ; st r25, r26 }
{ move r15, r16 ; shl2addx r5, r6, r7 ; st2 r25, r26 }
{ move r15, r16 ; shl3addx r5, r6, r7 }
{ move r15, r16 ; shrs r5, r6, r7 }
{ move r15, r16 ; shrui r5, r6, 5 ; ld1s r25, r26 }
{ move r15, r16 ; st r25, r26 ; fsingle_pack1 r5, r6 }
{ move r15, r16 ; st r25, r26 ; tblidxb2 r5, r6 }
{ move r15, r16 ; st1 r25, r26 ; nor r5, r6, r7 }
{ move r15, r16 ; st2 r25, r26 ; cmplts r5, r6, r7 }
{ move r15, r16 ; st2 r25, r26 ; shru r5, r6, r7 }
{ move r15, r16 ; st4 r25, r26 ; mula_ls_ls r5, r6, r7 }
{ move r15, r16 ; sub r5, r6, r7 ; prefetch r25 }
{ move r15, r16 ; tblidxb0 r5, r6 ; prefetch_l1 r25 }
{ move r15, r16 ; tblidxb2 r5, r6 ; prefetch_l2 r25 }
{ move r15, r16 ; v1cmpltui r5, r6, 5 }
{ move r15, r16 ; v2cmples r5, r6, r7 }
{ move r15, r16 ; v4packsc r5, r6, r7 }
{ move r5, r6 ; add r15, r16, r17 ; prefetch_l3_fault r25 }
{ move r5, r6 ; addx r15, r16, r17 ; st r25, r26 }
{ move r5, r6 ; and r15, r16, r17 ; st r25, r26 }
{ move r5, r6 ; cmpeq r15, r16, r17 ; st2 r25, r26 }
{ move r5, r6 ; cmples r15, r16, r17 ; st2 r25, r26 }
{ move r5, r6 ; cmplts r15, r16, r17 }
{ move r5, r6 ; cmpne r15, r16, r17 ; ld r25, r26 }
{ move r5, r6 ; fnop ; ld2u r25, r26 }
{ move r5, r6 ; info 19 ; ld4s r25, r26 }
{ move r5, r6 ; jalrp r15 ; ld2u r25, r26 }
{ move r5, r6 ; jrp r15 ; ld4u r25, r26 }
{ move r5, r6 ; ld r25, r26 ; nop }
{ move r5, r6 ; ld1s r25, r26 ; jalrp r15 }
{ move r5, r6 ; ld1u r25, r26 ; cmpleu r15, r16, r17 }
{ move r5, r6 ; ld2s r25, r26 ; add r15, r16, r17 }
{ move r5, r6 ; ld2s r25, r26 ; shrsi r15, r16, 5 }
{ move r5, r6 ; ld2u r25, r26 ; shl r15, r16, r17 }
{ move r5, r6 ; ld4s r25, r26 ; mnz r15, r16, r17 }
{ move r5, r6 ; ld4u r25, r26 ; cmpne r15, r16, r17 }
{ move r5, r6 ; ldnt1s_add r15, r16, 5 }
{ move r5, r6 ; mnz r15, r16, r17 ; prefetch r25 }
{ move r5, r6 ; movei r15, 5 ; prefetch_l1_fault r25 }
{ move r5, r6 ; nop ; prefetch_l1_fault r25 }
{ move r5, r6 ; or r15, r16, r17 ; prefetch_l2_fault r25 }
{ move r5, r6 ; prefetch r25 ; rotli r15, r16, 5 }
{ move r5, r6 ; prefetch_l1 r25 ; info 19 }
{ move r5, r6 ; prefetch_l1_fault r25 ; cmples r15, r16, r17 }
{ move r5, r6 ; prefetch_l2 r25 ; add r15, r16, r17 }
{ move r5, r6 ; prefetch_l2 r25 ; shrsi r15, r16, 5 }
{ move r5, r6 ; prefetch_l2_fault r25 ; shl1add r15, r16, r17 }
{ move r5, r6 ; prefetch_l3 r25 ; movei r15, 5 }
{ move r5, r6 ; prefetch_l3_fault r25 ; info 19 }
{ move r5, r6 ; rotl r15, r16, r17 ; prefetch_l1 r25 }
{ move r5, r6 ; shl r15, r16, r17 ; prefetch_l2 r25 }
{ move r5, r6 ; shl1addx r15, r16, r17 ; prefetch_l2_fault r25 }
{ move r5, r6 ; shl2addx r15, r16, r17 ; prefetch_l3_fault r25 }
{ move r5, r6 ; shl3addx r15, r16, r17 ; st1 r25, r26 }
{ move r5, r6 ; shrs r15, r16, r17 ; st1 r25, r26 }
{ move r5, r6 ; shru r15, r16, r17 ; st4 r25, r26 }
{ move r5, r6 ; st r25, r26 ; info 19 }
{ move r5, r6 ; st1 r25, r26 ; cmples r15, r16, r17 }
{ move r5, r6 ; st2 r15, r16 }
{ move r5, r6 ; st2 r25, r26 ; shrs r15, r16, r17 }
{ move r5, r6 ; st4 r25, r26 ; rotli r15, r16, 5 }
{ move r5, r6 ; sub r15, r16, r17 ; prefetch_l3_fault r25 }
{ move r5, r6 ; v1maxu r15, r16, r17 }
{ move r5, r6 ; v2shrs r15, r16, r17 }
{ movei r15, 5 ; add r5, r6, r7 ; ld1u r25, r26 }
{ movei r15, 5 ; addx r5, r6, r7 ; ld2s r25, r26 }
{ movei r15, 5 ; and r5, r6, r7 ; ld2s r25, r26 }
{ movei r15, 5 ; clz r5, r6 ; ld1u r25, r26 }
{ movei r15, 5 ; cmovnez r5, r6, r7 ; ld2u r25, r26 }
{ movei r15, 5 ; cmpeqi r5, r6, 5 ; ld4u r25, r26 }
{ movei r15, 5 ; cmpleu r5, r6, r7 ; prefetch_l1 r25 }
{ movei r15, 5 ; cmpltsi r5, r6, 5 ; prefetch_l2 r25 }
{ movei r15, 5 ; cmpne r5, r6, r7 ; prefetch_l2_fault r25 }
{ movei r15, 5 ; fdouble_add_flags r5, r6, r7 }
{ movei r15, 5 ; fsingle_pack1 r5, r6 ; prefetch_l1_fault r25 }
{ movei r15, 5 ; ld r25, r26 ; cmovnez r5, r6, r7 }
{ movei r15, 5 ; ld r25, r26 ; shl3add r5, r6, r7 }
{ movei r15, 5 ; ld1s r25, r26 ; mul_hu_hu r5, r6, r7 }
{ movei r15, 5 ; ld1u r25, r26 ; addx r5, r6, r7 }
{ movei r15, 5 ; ld1u r25, r26 ; rotli r5, r6, 5 }
{ movei r15, 5 ; ld2s r25, r26 ; fsingle_pack1 r5, r6 }
{ movei r15, 5 ; ld2s r25, r26 ; tblidxb2 r5, r6 }
{ movei r15, 5 ; ld2u r25, r26 ; nor r5, r6, r7 }
{ movei r15, 5 ; ld4s r25, r26 ; cmplts r5, r6, r7 }
{ movei r15, 5 ; ld4s r25, r26 ; shru r5, r6, r7 }
{ movei r15, 5 ; ld4u r25, r26 ; mula_ls_ls r5, r6, r7 }
{ movei r15, 5 ; mnz r5, r6, r7 ; ld4u r25, r26 }
{ movei r15, 5 ; movei r5, 5 ; prefetch_l1 r25 }
{ movei r15, 5 ; mul_hu_hu r5, r6, r7 ; ld4u r25, r26 }
{ movei r15, 5 ; mul_lu_lu r5, r6, r7 ; ld4s r25, r26 }
{ movei r15, 5 ; mula_hu_hu r5, r6, r7 ; ld2u r25, r26 }
{ movei r15, 5 ; mula_lu_lu r5, r6, r7 ; ld2s r25, r26 }
{ movei r15, 5 ; mulx r5, r6, r7 ; ld4s r25, r26 }
{ movei r15, 5 ; nop ; prefetch r25 }
{ movei r15, 5 ; or r5, r6, r7 ; prefetch_l1_fault r25 }
{ movei r15, 5 ; prefetch r25 ; cmpeqi r5, r6, 5 }
{ movei r15, 5 ; prefetch r25 ; shli r5, r6, 5 }
{ movei r15, 5 ; prefetch_l1 r25 ; mul_lu_lu r5, r6, r7 }
{ movei r15, 5 ; prefetch_l1_fault r25 ; and r5, r6, r7 }
{ movei r15, 5 ; prefetch_l1_fault r25 ; shl1add r5, r6, r7 }
{ movei r15, 5 ; prefetch_l2 r25 ; mnz r5, r6, r7 }
{ movei r15, 5 ; prefetch_l2 r25 ; xor r5, r6, r7 }
{ movei r15, 5 ; prefetch_l2_fault r25 ; pcnt r5, r6 }
{ movei r15, 5 ; prefetch_l3 r25 ; cmpltu r5, r6, r7 }
{ movei r15, 5 ; prefetch_l3 r25 ; sub r5, r6, r7 }
{ movei r15, 5 ; prefetch_l3_fault r25 ; mulax r5, r6, r7 }
{ movei r15, 5 ; revbits r5, r6 ; prefetch_l1_fault r25 }
{ movei r15, 5 ; rotl r5, r6, r7 ; prefetch_l2_fault r25 }
{ movei r15, 5 ; shl r5, r6, r7 ; prefetch_l3_fault r25 }
{ movei r15, 5 ; shl1addx r5, r6, r7 ; st r25, r26 }
{ movei r15, 5 ; shl2addx r5, r6, r7 ; st2 r25, r26 }
{ movei r15, 5 ; shl3addx r5, r6, r7 }
{ movei r15, 5 ; shrs r5, r6, r7 }
{ movei r15, 5 ; shrui r5, r6, 5 ; ld1s r25, r26 }
{ movei r15, 5 ; st r25, r26 ; fsingle_pack1 r5, r6 }
{ movei r15, 5 ; st r25, r26 ; tblidxb2 r5, r6 }
{ movei r15, 5 ; st1 r25, r26 ; nor r5, r6, r7 }
{ movei r15, 5 ; st2 r25, r26 ; cmplts r5, r6, r7 }
{ movei r15, 5 ; st2 r25, r26 ; shru r5, r6, r7 }
{ movei r15, 5 ; st4 r25, r26 ; mula_ls_ls r5, r6, r7 }
{ movei r15, 5 ; sub r5, r6, r7 ; prefetch r25 }
{ movei r15, 5 ; tblidxb0 r5, r6 ; prefetch_l1 r25 }
{ movei r15, 5 ; tblidxb2 r5, r6 ; prefetch_l2 r25 }
{ movei r15, 5 ; v1cmpltui r5, r6, 5 }
{ movei r15, 5 ; v2cmples r5, r6, r7 }
{ movei r15, 5 ; v4packsc r5, r6, r7 }
{ movei r5, 5 ; add r15, r16, r17 ; prefetch_l3_fault r25 }
{ movei r5, 5 ; addx r15, r16, r17 ; st r25, r26 }
{ movei r5, 5 ; and r15, r16, r17 ; st r25, r26 }
{ movei r5, 5 ; cmpeq r15, r16, r17 ; st2 r25, r26 }
{ movei r5, 5 ; cmples r15, r16, r17 ; st2 r25, r26 }
{ movei r5, 5 ; cmplts r15, r16, r17 }
{ movei r5, 5 ; cmpne r15, r16, r17 ; ld r25, r26 }
{ movei r5, 5 ; fnop ; ld2u r25, r26 }
{ movei r5, 5 ; info 19 ; ld4s r25, r26 }
{ movei r5, 5 ; jalrp r15 ; ld2u r25, r26 }
{ movei r5, 5 ; jrp r15 ; ld4u r25, r26 }
{ movei r5, 5 ; ld r25, r26 ; nop }
{ movei r5, 5 ; ld1s r25, r26 ; jalrp r15 }
{ movei r5, 5 ; ld1u r25, r26 ; cmpleu r15, r16, r17 }
{ movei r5, 5 ; ld2s r25, r26 ; add r15, r16, r17 }
{ movei r5, 5 ; ld2s r25, r26 ; shrsi r15, r16, 5 }
{ movei r5, 5 ; ld2u r25, r26 ; shl r15, r16, r17 }
{ movei r5, 5 ; ld4s r25, r26 ; mnz r15, r16, r17 }
{ movei r5, 5 ; ld4u r25, r26 ; cmpne r15, r16, r17 }
{ movei r5, 5 ; ldnt1s_add r15, r16, 5 }
{ movei r5, 5 ; mnz r15, r16, r17 ; prefetch r25 }
{ movei r5, 5 ; movei r15, 5 ; prefetch_l1_fault r25 }
{ movei r5, 5 ; nop ; prefetch_l1_fault r25 }
{ movei r5, 5 ; or r15, r16, r17 ; prefetch_l2_fault r25 }
{ movei r5, 5 ; prefetch r25 ; rotli r15, r16, 5 }
{ movei r5, 5 ; prefetch_l1 r25 ; info 19 }
{ movei r5, 5 ; prefetch_l1_fault r25 ; cmples r15, r16, r17 }
{ movei r5, 5 ; prefetch_l2 r25 ; add r15, r16, r17 }
{ movei r5, 5 ; prefetch_l2 r25 ; shrsi r15, r16, 5 }
{ movei r5, 5 ; prefetch_l2_fault r25 ; shl1add r15, r16, r17 }
{ movei r5, 5 ; prefetch_l3 r25 ; movei r15, 5 }
{ movei r5, 5 ; prefetch_l3_fault r25 ; info 19 }
{ movei r5, 5 ; rotl r15, r16, r17 ; prefetch_l1 r25 }
{ movei r5, 5 ; shl r15, r16, r17 ; prefetch_l2 r25 }
{ movei r5, 5 ; shl1addx r15, r16, r17 ; prefetch_l2_fault r25 }
{ movei r5, 5 ; shl2addx r15, r16, r17 ; prefetch_l3_fault r25 }
{ movei r5, 5 ; shl3addx r15, r16, r17 ; st1 r25, r26 }
{ movei r5, 5 ; shrs r15, r16, r17 ; st1 r25, r26 }
{ movei r5, 5 ; shru r15, r16, r17 ; st4 r25, r26 }
{ movei r5, 5 ; st r25, r26 ; info 19 }
{ movei r5, 5 ; st1 r25, r26 ; cmples r15, r16, r17 }
{ movei r5, 5 ; st2 r15, r16 }
{ movei r5, 5 ; st2 r25, r26 ; shrs r15, r16, r17 }
{ movei r5, 5 ; st4 r25, r26 ; rotli r15, r16, 5 }
{ movei r5, 5 ; sub r15, r16, r17 ; prefetch_l3_fault r25 }
{ movei r5, 5 ; v1maxu r15, r16, r17 }
{ movei r5, 5 ; v2shrs r15, r16, r17 }
{ moveli r15, 0x1234 ; addli r5, r6, 0x1234 }
{ moveli r15, 0x1234 ; fdouble_pack2 r5, r6, r7 }
{ moveli r15, 0x1234 ; mulx r5, r6, r7 }
{ moveli r15, 0x1234 ; v1avgu r5, r6, r7 }
{ moveli r15, 0x1234 ; v1subuc r5, r6, r7 }
{ moveli r15, 0x1234 ; v2shru r5, r6, r7 }
{ moveli r5, 0x1234 ; dtlbpr r15 }
{ moveli r5, 0x1234 ; ldna_add r15, r16, 5 }
{ moveli r5, 0x1234 ; prefetch_l3_fault r15 }
{ moveli r5, 0x1234 ; v1add r15, r16, r17 }
{ moveli r5, 0x1234 ; v2int_h r15, r16, r17 }
{ mtspr 0x5, r16 ; addxsc r5, r6, r7 }
{ mtspr 0x5, r16 ; fnop }
{ mtspr 0x5, r16 ; or r5, r6, r7 }
{ mtspr 0x5, r16 ; v1cmpleu r5, r6, r7 }
{ mtspr 0x5, r16 ; v2adiffs r5, r6, r7 }
{ mtspr 0x5, r16 ; v4add r5, r6, r7 }
{ mul_hs_hs r5, r6, r7 ; addi r15, r16, 5 ; prefetch_l1 r25 }
{ mul_hs_hs r5, r6, r7 ; addxi r15, r16, 5 ; prefetch_l1_fault r25 }
{ mul_hs_hs r5, r6, r7 ; andi r15, r16, 5 ; prefetch_l1_fault r25 }
{ mul_hs_hs r5, r6, r7 ; cmpeqi r15, r16, 5 ; prefetch_l2_fault r25 }
{ mul_hs_hs r5, r6, r7 ; cmpleu r15, r16, r17 ; prefetch_l2_fault r25 }
{ mul_hs_hs r5, r6, r7 ; cmpltsi r15, r16, 5 ; prefetch_l3_fault r25 }
{ mul_hs_hs r5, r6, r7 ; cmpne r15, r16, r17 ; st r25, r26 }
{ mul_hs_hs r5, r6, r7 ; fnop }
{ mul_hs_hs r5, r6, r7 ; infol 0x1234 }
{ mul_hs_hs r5, r6, r7 ; jalrp r15 }
{ mul_hs_hs r5, r6, r7 ; ld r25, r26 ; add r15, r16, r17 }
{ mul_hs_hs r5, r6, r7 ; ld r25, r26 ; shrsi r15, r16, 5 }
{ mul_hs_hs r5, r6, r7 ; ld1s r25, r26 ; shl1add r15, r16, r17 }
{ mul_hs_hs r5, r6, r7 ; ld1u r25, r26 ; move r15, r16 }
{ mul_hs_hs r5, r6, r7 ; ld2s r25, r26 ; fnop }
{ mul_hs_hs r5, r6, r7 ; ld2u r25, r26 ; andi r15, r16, 5 }
{ mul_hs_hs r5, r6, r7 ; ld2u r25, r26 ; xor r15, r16, r17 }
{ mul_hs_hs r5, r6, r7 ; ld4s r25, r26 ; shl3add r15, r16, r17 }
{ mul_hs_hs r5, r6, r7 ; ld4u r25, r26 ; nor r15, r16, r17 }
{ mul_hs_hs r5, r6, r7 ; lnk r15 ; ld1u r25, r26 }
{ mul_hs_hs r5, r6, r7 ; move r15, r16 ; ld1u r25, r26 }
{ mul_hs_hs r5, r6, r7 ; mz r15, r16, r17 ; ld1u r25, r26 }
{ mul_hs_hs r5, r6, r7 ; nor r15, r16, r17 ; ld2u r25, r26 }
{ mul_hs_hs r5, r6, r7 ; prefetch r25 ; and r15, r16, r17 }
{ mul_hs_hs r5, r6, r7 ; prefetch r25 ; subx r15, r16, r17 }
{ mul_hs_hs r5, r6, r7 ; prefetch_l1 r25 ; rotli r15, r16, 5 }
{ mul_hs_hs r5, r6, r7 ; prefetch_l1_fault r25 ; mnz r15, r16, r17 }
{ mul_hs_hs r5, r6, r7 ; prefetch_l2 r25 ; fnop }
{ mul_hs_hs r5, r6, r7 ; prefetch_l2_fault r25 ; cmpeq r15, r16, r17 }
{ mul_hs_hs r5, r6, r7 ; prefetch_l2_fault r25 }
{ mul_hs_hs r5, r6, r7 ; prefetch_l3 r25 ; shli r15, r16, 5 }
{ mul_hs_hs r5, r6, r7 ; prefetch_l3_fault r25 ; rotli r15, r16, 5 }
{ mul_hs_hs r5, r6, r7 ; rotli r15, r16, 5 ; ld2s r25, r26 }
{ mul_hs_hs r5, r6, r7 ; shl1add r15, r16, r17 ; ld2u r25, r26 }
{ mul_hs_hs r5, r6, r7 ; shl2add r15, r16, r17 ; ld4u r25, r26 }
{ mul_hs_hs r5, r6, r7 ; shl3add r15, r16, r17 ; prefetch_l1 r25 }
{ mul_hs_hs r5, r6, r7 ; shli r15, r16, 5 ; prefetch_l2 r25 }
{ mul_hs_hs r5, r6, r7 ; shrsi r15, r16, 5 ; prefetch_l2 r25 }
{ mul_hs_hs r5, r6, r7 ; shrui r15, r16, 5 ; prefetch_l3 r25 }
{ mul_hs_hs r5, r6, r7 ; st r25, r26 ; rotli r15, r16, 5 }
{ mul_hs_hs r5, r6, r7 ; st1 r25, r26 ; mnz r15, r16, r17 }
{ mul_hs_hs r5, r6, r7 ; st2 r25, r26 ; cmpne r15, r16, r17 }
{ mul_hs_hs r5, r6, r7 ; st4 r25, r26 ; and r15, r16, r17 }
{ mul_hs_hs r5, r6, r7 ; st4 r25, r26 ; subx r15, r16, r17 }
{ mul_hs_hs r5, r6, r7 ; subx r15, r16, r17 ; prefetch_l1 r25 }
{ mul_hs_hs r5, r6, r7 ; v2add r15, r16, r17 }
{ mul_hs_hs r5, r6, r7 ; v4shru r15, r16, r17 }
{ mul_hs_hu r5, r6, r7 ; cmpltsi r15, r16, 5 }
{ mul_hs_hu r5, r6, r7 ; ld2u_add r15, r16, 5 }
{ mul_hs_hu r5, r6, r7 ; prefetch_add_l3 r15, 5 }
{ mul_hs_hu r5, r6, r7 ; stnt2_add r15, r16, 5 }
{ mul_hs_hu r5, r6, r7 ; v2cmples r15, r16, r17 }
{ mul_hs_hu r5, r6, r7 ; xori r15, r16, 5 }
{ mul_hs_ls r5, r6, r7 ; ill }
{ mul_hs_ls r5, r6, r7 ; mf }
{ mul_hs_ls r5, r6, r7 ; shrsi r15, r16, 5 }
{ mul_hs_ls r5, r6, r7 ; v1minu r15, r16, r17 }
{ mul_hs_ls r5, r6, r7 ; v2shru r15, r16, r17 }
{ mul_hs_lu r5, r6, r7 ; dblalign6 r15, r16, r17 }
{ mul_hs_lu r5, r6, r7 ; ldna r15, r16 }
{ mul_hs_lu r5, r6, r7 ; prefetch_l3 r15 }
{ mul_hs_lu r5, r6, r7 ; subxsc r15, r16, r17 }
{ mul_hs_lu r5, r6, r7 ; v2cmpne r15, r16, r17 }
{ mul_hu_hu r5, r6, r7 ; add r15, r16, r17 ; ld4s r25, r26 }
{ mul_hu_hu r5, r6, r7 ; addx r15, r16, r17 ; ld4u r25, r26 }
{ mul_hu_hu r5, r6, r7 ; and r15, r16, r17 ; ld4u r25, r26 }
{ mul_hu_hu r5, r6, r7 ; cmpeq r15, r16, r17 ; prefetch_l1 r25 }
{ mul_hu_hu r5, r6, r7 ; cmples r15, r16, r17 ; prefetch_l1 r25 }
{ mul_hu_hu r5, r6, r7 ; cmplts r15, r16, r17 ; prefetch_l2 r25 }
{ mul_hu_hu r5, r6, r7 ; cmpltu r15, r16, r17 ; prefetch_l3 r25 }
{ mul_hu_hu r5, r6, r7 ; fetchor4 r15, r16, r17 }
{ mul_hu_hu r5, r6, r7 ; ill ; st2 r25, r26 }
{ mul_hu_hu r5, r6, r7 ; jalr r15 ; st1 r25, r26 }
{ mul_hu_hu r5, r6, r7 ; jr r15 ; st4 r25, r26 }
{ mul_hu_hu r5, r6, r7 ; ld r25, r26 ; jalrp r15 }
{ mul_hu_hu r5, r6, r7 ; ld1s r25, r26 ; cmplts r15, r16, r17 }
{ mul_hu_hu r5, r6, r7 ; ld1u r25, r26 ; addi r15, r16, 5 }
{ mul_hu_hu r5, r6, r7 ; ld1u r25, r26 ; shru r15, r16, r17 }
{ mul_hu_hu r5, r6, r7 ; ld2s r25, r26 ; shl1add r15, r16, r17 }
{ mul_hu_hu r5, r6, r7 ; ld2u r25, r26 ; move r15, r16 }
{ mul_hu_hu r5, r6, r7 ; ld4s r25, r26 ; fnop }
{ mul_hu_hu r5, r6, r7 ; ld4u r25, r26 ; andi r15, r16, 5 }
{ mul_hu_hu r5, r6, r7 ; ld4u r25, r26 ; xor r15, r16, r17 }
{ mul_hu_hu r5, r6, r7 ; mfspr r16, 0x5 }
{ mul_hu_hu r5, r6, r7 ; movei r15, 5 ; ld1s r25, r26 }
{ mul_hu_hu r5, r6, r7 ; nop ; ld1s r25, r26 }
{ mul_hu_hu r5, r6, r7 ; or r15, r16, r17 ; ld2s r25, r26 }
{ mul_hu_hu r5, r6, r7 ; prefetch r25 ; mnz r15, r16, r17 }
{ mul_hu_hu r5, r6, r7 ; prefetch_l1 r25 ; cmples r15, r16, r17 }
{ mul_hu_hu r5, r6, r7 ; prefetch_l1_fault r25 ; add r15, r16, r17 }
{ mul_hu_hu r5, r6, r7 ; prefetch_l1_fault r25 ; shrsi r15, r16, 5 }
{ mul_hu_hu r5, r6, r7 ; prefetch_l2 r25 ; shl1add r15, r16, r17 }
{ mul_hu_hu r5, r6, r7 ; prefetch_l2_fault r25 ; movei r15, 5 }
{ mul_hu_hu r5, r6, r7 ; prefetch_l3 r25 ; info 19 }
{ mul_hu_hu r5, r6, r7 ; prefetch_l3_fault r25 ; cmples r15, r16, r17 }
{ mul_hu_hu r5, r6, r7 ; rotl r15, r16, r17 ; ld r25, r26 }
{ mul_hu_hu r5, r6, r7 ; shl r15, r16, r17 ; ld1u r25, r26 }
{ mul_hu_hu r5, r6, r7 ; shl1addx r15, r16, r17 ; ld2s r25, r26 }
{ mul_hu_hu r5, r6, r7 ; shl2addx r15, r16, r17 ; ld4s r25, r26 }
{ mul_hu_hu r5, r6, r7 ; shl3addx r15, r16, r17 ; prefetch r25 }
{ mul_hu_hu r5, r6, r7 ; shrs r15, r16, r17 ; prefetch r25 }
{ mul_hu_hu r5, r6, r7 ; shru r15, r16, r17 ; prefetch_l1_fault r25 }
{ mul_hu_hu r5, r6, r7 ; st r25, r26 ; cmples r15, r16, r17 }
{ mul_hu_hu r5, r6, r7 ; st1 r25, r26 ; add r15, r16, r17 }
{ mul_hu_hu r5, r6, r7 ; st1 r25, r26 ; shrsi r15, r16, 5 }
{ mul_hu_hu r5, r6, r7 ; st2 r25, r26 ; shl r15, r16, r17 }
{ mul_hu_hu r5, r6, r7 ; st4 r25, r26 ; mnz r15, r16, r17 }
{ mul_hu_hu r5, r6, r7 ; sub r15, r16, r17 ; ld4s r25, r26 }
{ mul_hu_hu r5, r6, r7 ; v1cmpleu r15, r16, r17 }
{ mul_hu_hu r5, r6, r7 ; v2mnz r15, r16, r17 }
{ mul_hu_hu r5, r6, r7 ; xor r15, r16, r17 ; st r25, r26 }
{ mul_hu_ls r5, r6, r7 ; finv r15 }
{ mul_hu_ls r5, r6, r7 ; ldnt4s_add r15, r16, 5 }
{ mul_hu_ls r5, r6, r7 ; shl3addx r15, r16, r17 }
{ mul_hu_ls r5, r6, r7 ; v1cmpne r15, r16, r17 }
{ mul_hu_ls r5, r6, r7 ; v2shl r15, r16, r17 }
{ mul_hu_lu r5, r6, r7 ; cmpltu r15, r16, r17 }
{ mul_hu_lu r5, r6, r7 ; ld4s r15, r16 }
{ mul_hu_lu r5, r6, r7 ; prefetch_add_l3_fault r15, 5 }
{ mul_hu_lu r5, r6, r7 ; stnt4 r15, r16 }
{ mul_hu_lu r5, r6, r7 ; v2cmpleu r15, r16, r17 }
{ mul_ls_ls r5, r6, r7 ; add r15, r16, r17 ; ld r25, r26 }
{ mul_ls_ls r5, r6, r7 ; addx r15, r16, r17 ; ld1s r25, r26 }
{ mul_ls_ls r5, r6, r7 ; and r15, r16, r17 ; ld1s r25, r26 }
{ mul_ls_ls r5, r6, r7 ; cmpeq r15, r16, r17 ; ld2s r25, r26 }
{ mul_ls_ls r5, r6, r7 ; cmples r15, r16, r17 ; ld2s r25, r26 }
{ mul_ls_ls r5, r6, r7 ; cmplts r15, r16, r17 ; ld4s r25, r26 }
{ mul_ls_ls r5, r6, r7 ; cmpltu r15, r16, r17 ; prefetch r25 }
{ mul_ls_ls r5, r6, r7 ; fetchaddgez r15, r16, r17 }
{ mul_ls_ls r5, r6, r7 ; ill ; prefetch_l2_fault r25 }
{ mul_ls_ls r5, r6, r7 ; jalr r15 ; prefetch_l2 r25 }
{ mul_ls_ls r5, r6, r7 ; jr r15 ; prefetch_l3 r25 }
{ mul_ls_ls r5, r6, r7 ; ld r25, r26 ; cmpne r15, r16, r17 }
{ mul_ls_ls r5, r6, r7 ; ld1s r25, r26 ; andi r15, r16, 5 }
{ mul_ls_ls r5, r6, r7 ; ld1s r25, r26 ; xor r15, r16, r17 }
{ mul_ls_ls r5, r6, r7 ; ld1u r25, r26 ; shl3add r15, r16, r17 }
{ mul_ls_ls r5, r6, r7 ; ld2s r25, r26 ; nor r15, r16, r17 }
{ mul_ls_ls r5, r6, r7 ; ld2u r25, r26 ; jalrp r15 }
{ mul_ls_ls r5, r6, r7 ; ld4s r25, r26 ; cmpleu r15, r16, r17 }
{ mul_ls_ls r5, r6, r7 ; ld4u r25, r26 ; add r15, r16, r17 }
{ mul_ls_ls r5, r6, r7 ; ld4u r25, r26 ; shrsi r15, r16, 5 }
{ mul_ls_ls r5, r6, r7 ; lnk r15 ; st1 r25, r26 }
{ mul_ls_ls r5, r6, r7 ; move r15, r16 ; st1 r25, r26 }
{ mul_ls_ls r5, r6, r7 ; mz r15, r16, r17 ; st1 r25, r26 }
{ mul_ls_ls r5, r6, r7 ; nor r15, r16, r17 ; st4 r25, r26 }
{ mul_ls_ls r5, r6, r7 ; prefetch r25 ; jalr r15 }
{ mul_ls_ls r5, r6, r7 ; prefetch_l1 r25 ; addxi r15, r16, 5 }
{ mul_ls_ls r5, r6, r7 ; prefetch_l1 r25 ; sub r15, r16, r17 }
{ mul_ls_ls r5, r6, r7 ; prefetch_l1_fault r25 ; shl2addx r15, r16, r17 }
{ mul_ls_ls r5, r6, r7 ; prefetch_l2 r25 ; nor r15, r16, r17 }
{ mul_ls_ls r5, r6, r7 ; prefetch_l2_fault r25 ; jr r15 }
{ mul_ls_ls r5, r6, r7 ; prefetch_l3 r25 ; cmpltsi r15, r16, 5 }
{ mul_ls_ls r5, r6, r7 ; prefetch_l3_fault r25 ; addxi r15, r16, 5 }
{ mul_ls_ls r5, r6, r7 ; prefetch_l3_fault r25 ; sub r15, r16, r17 }
{ mul_ls_ls r5, r6, r7 ; rotli r15, r16, 5 ; st2 r25, r26 }
{ mul_ls_ls r5, r6, r7 ; shl1add r15, r16, r17 ; st4 r25, r26 }
{ mul_ls_ls r5, r6, r7 ; shl2addx r15, r16, r17 ; ld r25, r26 }
{ mul_ls_ls r5, r6, r7 ; shl3addx r15, r16, r17 ; ld1u r25, r26 }
{ mul_ls_ls r5, r6, r7 ; shrs r15, r16, r17 ; ld1u r25, r26 }
{ mul_ls_ls r5, r6, r7 ; shru r15, r16, r17 ; ld2u r25, r26 }
{ mul_ls_ls r5, r6, r7 ; st r25, r26 ; addxi r15, r16, 5 }
{ mul_ls_ls r5, r6, r7 ; st r25, r26 ; sub r15, r16, r17 }
{ mul_ls_ls r5, r6, r7 ; st1 r25, r26 ; shl2addx r15, r16, r17 }
{ mul_ls_ls r5, r6, r7 ; st2 r25, r26 ; nop }
{ mul_ls_ls r5, r6, r7 ; st4 r25, r26 ; jalr r15 }
{ mul_ls_ls r5, r6, r7 ; sub r15, r16, r17 ; ld r25, r26 }
{ mul_ls_ls r5, r6, r7 ; v1addi r15, r16, 5 }
{ mul_ls_ls r5, r6, r7 ; v2int_l r15, r16, r17 }
{ mul_ls_ls r5, r6, r7 ; xor r15, r16, r17 ; prefetch_l1_fault r25 }
{ mul_ls_lu r5, r6, r7 ; fetchaddgez4 r15, r16, r17 }
{ mul_ls_lu r5, r6, r7 ; ldnt2s r15, r16 }
{ mul_ls_lu r5, r6, r7 ; shl1add r15, r16, r17 }
{ mul_ls_lu r5, r6, r7 ; v1cmpleu r15, r16, r17 }
{ mul_ls_lu r5, r6, r7 ; v2mnz r15, r16, r17 }
{ mul_lu_lu r5, r6, r7 ; add r15, r16, r17 ; prefetch_l3 r25 }
{ mul_lu_lu r5, r6, r7 ; addx r15, r16, r17 ; prefetch_l3_fault r25 }
{ mul_lu_lu r5, r6, r7 ; and r15, r16, r17 ; prefetch_l3_fault r25 }
{ mul_lu_lu r5, r6, r7 ; cmpeq r15, r16, r17 ; st1 r25, r26 }
{ mul_lu_lu r5, r6, r7 ; cmples r15, r16, r17 ; st1 r25, r26 }
{ mul_lu_lu r5, r6, r7 ; cmplts r15, r16, r17 ; st4 r25, r26 }
{ mul_lu_lu r5, r6, r7 ; cmpltui r15, r16, 5 }
{ mul_lu_lu r5, r6, r7 ; fnop ; ld2s r25, r26 }
{ mul_lu_lu r5, r6, r7 ; info 19 ; ld2u r25, r26 }
{ mul_lu_lu r5, r6, r7 ; jalrp r15 ; ld2s r25, r26 }
{ mul_lu_lu r5, r6, r7 ; jrp r15 ; ld4s r25, r26 }
{ mul_lu_lu r5, r6, r7 ; ld r25, r26 ; mz r15, r16, r17 }
{ mul_lu_lu r5, r6, r7 ; ld1s r25, r26 ; jalr r15 }
{ mul_lu_lu r5, r6, r7 ; ld1u r25, r26 ; cmples r15, r16, r17 }
{ mul_lu_lu r5, r6, r7 ; ld2s r15, r16 }
{ mul_lu_lu r5, r6, r7 ; ld2s r25, r26 ; shrs r15, r16, r17 }
{ mul_lu_lu r5, r6, r7 ; ld2u r25, r26 ; rotli r15, r16, 5 }
{ mul_lu_lu r5, r6, r7 ; ld4s r25, r26 ; lnk r15 }
{ mul_lu_lu r5, r6, r7 ; ld4u r25, r26 ; cmpltu r15, r16, r17 }
{ mul_lu_lu r5, r6, r7 ; ldnt1s r15, r16 }
{ mul_lu_lu r5, r6, r7 ; mnz r15, r16, r17 ; ld4u r25, r26 }
{ mul_lu_lu r5, r6, r7 ; movei r15, 5 ; prefetch_l1 r25 }
{ mul_lu_lu r5, r6, r7 ; nop ; prefetch_l1 r25 }
{ mul_lu_lu r5, r6, r7 ; or r15, r16, r17 ; prefetch_l2 r25 }
{ mul_lu_lu r5, r6, r7 ; prefetch r25 ; rotl r15, r16, r17 }
{ mul_lu_lu r5, r6, r7 ; prefetch_l1 r25 ; ill }
{ mul_lu_lu r5, r6, r7 ; prefetch_l1_fault r25 ; cmpeqi r15, r16, 5 }
{ mul_lu_lu r5, r6, r7 ; prefetch_l2 r15 }
{ mul_lu_lu r5, r6, r7 ; prefetch_l2 r25 ; shrs r15, r16, r17 }
{ mul_lu_lu r5, r6, r7 ; prefetch_l2_fault r25 ; shl r15, r16, r17 }
{ mul_lu_lu r5, r6, r7 ; prefetch_l3 r25 ; move r15, r16 }
{ mul_lu_lu r5, r6, r7 ; prefetch_l3_fault r25 ; ill }
{ mul_lu_lu r5, r6, r7 ; rotl r15, r16, r17 ; prefetch r25 }
{ mul_lu_lu r5, r6, r7 ; shl r15, r16, r17 ; prefetch_l1_fault r25 }
{ mul_lu_lu r5, r6, r7 ; shl1addx r15, r16, r17 ; prefetch_l2 r25 }
{ mul_lu_lu r5, r6, r7 ; shl2addx r15, r16, r17 ; prefetch_l3 r25 }
{ mul_lu_lu r5, r6, r7 ; shl3addx r15, r16, r17 ; st r25, r26 }
{ mul_lu_lu r5, r6, r7 ; shrs r15, r16, r17 ; st r25, r26 }
{ mul_lu_lu r5, r6, r7 ; shru r15, r16, r17 ; st2 r25, r26 }
{ mul_lu_lu r5, r6, r7 ; st r25, r26 ; ill }
{ mul_lu_lu r5, r6, r7 ; st1 r25, r26 ; cmpeqi r15, r16, 5 }
{ mul_lu_lu r5, r6, r7 ; st1_add r15, r16, 5 }
{ mul_lu_lu r5, r6, r7 ; st2 r25, r26 ; shli r15, r16, 5 }
{ mul_lu_lu r5, r6, r7 ; st4 r25, r26 ; rotl r15, r16, r17 }
{ mul_lu_lu r5, r6, r7 ; sub r15, r16, r17 ; prefetch_l3 r25 }
{ mul_lu_lu r5, r6, r7 ; v1int_l r15, r16, r17 }
{ mul_lu_lu r5, r6, r7 ; v2shlsc r15, r16, r17 }
{ mula_hs_hs r5, r6, r7 ; add r15, r16, r17 ; ld1s r25, r26 }
{ mula_hs_hs r5, r6, r7 ; addx r15, r16, r17 ; ld1u r25, r26 }
{ mula_hs_hs r5, r6, r7 ; and r15, r16, r17 ; ld1u r25, r26 }
{ mula_hs_hs r5, r6, r7 ; cmpeq r15, r16, r17 ; ld2u r25, r26 }
{ mula_hs_hs r5, r6, r7 ; cmples r15, r16, r17 ; ld2u r25, r26 }
{ mula_hs_hs r5, r6, r7 ; cmplts r15, r16, r17 ; ld4u r25, r26 }
{ mula_hs_hs r5, r6, r7 ; cmpltu r15, r16, r17 ; prefetch_l1 r25 }
{ mula_hs_hs r5, r6, r7 ; fetchaddgez4 r15, r16, r17 }
{ mula_hs_hs r5, r6, r7 ; ill ; prefetch_l3 r25 }
{ mula_hs_hs r5, r6, r7 ; jalr r15 ; prefetch_l2_fault r25 }
{ mula_hs_hs r5, r6, r7 ; jr r15 ; prefetch_l3_fault r25 }
{ mula_hs_hs r5, r6, r7 ; ld r25, r26 ; fnop }
{ mula_hs_hs r5, r6, r7 ; ld1s r25, r26 ; cmpeq r15, r16, r17 }
{ mula_hs_hs r5, r6, r7 ; ld1s r25, r26 }
{ mula_hs_hs r5, r6, r7 ; ld1u r25, r26 ; shl3addx r15, r16, r17 }
{ mula_hs_hs r5, r6, r7 ; ld2s r25, r26 ; or r15, r16, r17 }
{ mula_hs_hs r5, r6, r7 ; ld2u r25, r26 ; jr r15 }
{ mula_hs_hs r5, r6, r7 ; ld4s r25, r26 ; cmplts r15, r16, r17 }
{ mula_hs_hs r5, r6, r7 ; ld4u r25, r26 ; addi r15, r16, 5 }
{ mula_hs_hs r5, r6, r7 ; ld4u r25, r26 ; shru r15, r16, r17 }
{ mula_hs_hs r5, r6, r7 ; lnk r15 ; st2 r25, r26 }
{ mula_hs_hs r5, r6, r7 ; move r15, r16 ; st2 r25, r26 }
{ mula_hs_hs r5, r6, r7 ; mz r15, r16, r17 ; st2 r25, r26 }
{ mula_hs_hs r5, r6, r7 ; nor r15, r16, r17 }
{ mula_hs_hs r5, r6, r7 ; prefetch r25 ; jalrp r15 }
{ mula_hs_hs r5, r6, r7 ; prefetch_l1 r25 ; and r15, r16, r17 }
{ mula_hs_hs r5, r6, r7 ; prefetch_l1 r25 ; subx r15, r16, r17 }
{ mula_hs_hs r5, r6, r7 ; prefetch_l1_fault r25 ; shl3add r15, r16, r17 }
{ mula_hs_hs r5, r6, r7 ; prefetch_l2 r25 ; or r15, r16, r17 }
{ mula_hs_hs r5, r6, r7 ; prefetch_l2_fault r25 ; jrp r15 }
{ mula_hs_hs r5, r6, r7 ; prefetch_l3 r25 ; cmpltu r15, r16, r17 }
{ mula_hs_hs r5, r6, r7 ; prefetch_l3_fault r25 ; and r15, r16, r17 }
{ mula_hs_hs r5, r6, r7 ; prefetch_l3_fault r25 ; subx r15, r16, r17 }
{ mula_hs_hs r5, r6, r7 ; rotli r15, r16, 5 ; st4 r25, r26 }
{ mula_hs_hs r5, r6, r7 ; shl1add r15, r16, r17 }
{ mula_hs_hs r5, r6, r7 ; shl2addx r15, r16, r17 ; ld1s r25, r26 }
{ mula_hs_hs r5, r6, r7 ; shl3addx r15, r16, r17 ; ld2s r25, r26 }
{ mula_hs_hs r5, r6, r7 ; shrs r15, r16, r17 ; ld2s r25, r26 }
{ mula_hs_hs r5, r6, r7 ; shru r15, r16, r17 ; ld4s r25, r26 }
{ mula_hs_hs r5, r6, r7 ; st r25, r26 ; and r15, r16, r17 }
{ mula_hs_hs r5, r6, r7 ; st r25, r26 ; subx r15, r16, r17 }
{ mula_hs_hs r5, r6, r7 ; st1 r25, r26 ; shl3add r15, r16, r17 }
{ mula_hs_hs r5, r6, r7 ; st2 r25, r26 ; nor r15, r16, r17 }
{ mula_hs_hs r5, r6, r7 ; st4 r25, r26 ; jalrp r15 }
{ mula_hs_hs r5, r6, r7 ; sub r15, r16, r17 ; ld1s r25, r26 }
{ mula_hs_hs r5, r6, r7 ; v1adduc r15, r16, r17 }
{ mula_hs_hs r5, r6, r7 ; v2maxs r15, r16, r17 }
{ mula_hs_hs r5, r6, r7 ; xor r15, r16, r17 ; prefetch_l2 r25 }
{ mula_hs_hu r5, r6, r7 ; fetchand r15, r16, r17 }
{ mula_hs_hu r5, r6, r7 ; ldnt2s_add r15, r16, 5 }
{ mula_hs_hu r5, r6, r7 ; shl1addx r15, r16, r17 }
{ mula_hs_hu r5, r6, r7 ; v1cmplts r15, r16, r17 }
{ mula_hs_hu r5, r6, r7 ; v2mz r15, r16, r17 }
{ mula_hs_ls r5, r6, r7 ; cmples r15, r16, r17 }
{ mula_hs_ls r5, r6, r7 ; ld2s r15, r16 }
{ mula_hs_ls r5, r6, r7 ; prefetch_add_l1_fault r15, 5 }
{ mula_hs_ls r5, r6, r7 ; stnt1 r15, r16 }
{ mula_hs_ls r5, r6, r7 ; v2addsc r15, r16, r17 }
{ mula_hs_ls r5, r6, r7 ; v4subsc r15, r16, r17 }
{ mula_hs_lu r5, r6, r7 ; flushwb }
{ mula_hs_lu r5, r6, r7 ; ldnt4u_add r15, r16, 5 }
{ mula_hs_lu r5, r6, r7 ; shlx r15, r16, r17 }
{ mula_hs_lu r5, r6, r7 ; v1int_l r15, r16, r17 }
{ mula_hs_lu r5, r6, r7 ; v2shlsc r15, r16, r17 }
{ mula_hu_hu r5, r6, r7 ; addi r15, r16, 5 ; ld r25, r26 }
{ mula_hu_hu r5, r6, r7 ; addxi r15, r16, 5 ; ld1s r25, r26 }
{ mula_hu_hu r5, r6, r7 ; andi r15, r16, 5 ; ld1s r25, r26 }
{ mula_hu_hu r5, r6, r7 ; cmpeqi r15, r16, 5 ; ld2s r25, r26 }
{ mula_hu_hu r5, r6, r7 ; cmpleu r15, r16, r17 ; ld2s r25, r26 }
{ mula_hu_hu r5, r6, r7 ; cmpltsi r15, r16, 5 ; ld4s r25, r26 }
{ mula_hu_hu r5, r6, r7 ; cmpne r15, r16, r17 ; ld4u r25, r26 }
{ mula_hu_hu r5, r6, r7 ; fnop ; prefetch_l2 r25 }
{ mula_hu_hu r5, r6, r7 ; info 19 ; prefetch_l2_fault r25 }
{ mula_hu_hu r5, r6, r7 ; jalrp r15 ; prefetch_l2 r25 }
{ mula_hu_hu r5, r6, r7 ; jrp r15 ; prefetch_l3 r25 }
{ mula_hu_hu r5, r6, r7 ; ld r25, r26 ; shl1add r15, r16, r17 }
{ mula_hu_hu r5, r6, r7 ; ld1s r25, r26 ; movei r15, 5 }
{ mula_hu_hu r5, r6, r7 ; ld1u r25, r26 ; ill }
{ mula_hu_hu r5, r6, r7 ; ld2s r25, r26 ; cmpeq r15, r16, r17 }
{ mula_hu_hu r5, r6, r7 ; ld2s r25, r26 }
{ mula_hu_hu r5, r6, r7 ; ld2u r25, r26 ; shl3addx r15, r16, r17 }
{ mula_hu_hu r5, r6, r7 ; ld4s r25, r26 ; or r15, r16, r17 }
{ mula_hu_hu r5, r6, r7 ; ld4u r25, r26 ; jr r15 }
{ mula_hu_hu r5, r6, r7 ; ldnt2u_add r15, r16, 5 }
{ mula_hu_hu r5, r6, r7 ; mnz r15, r16, r17 ; prefetch_l3_fault r25 }
{ mula_hu_hu r5, r6, r7 ; movei r15, 5 ; st1 r25, r26 }
{ mula_hu_hu r5, r6, r7 ; nop ; st1 r25, r26 }
{ mula_hu_hu r5, r6, r7 ; or r15, r16, r17 ; st4 r25, r26 }
{ mula_hu_hu r5, r6, r7 ; prefetch r25 ; shl3add r15, r16, r17 }
{ mula_hu_hu r5, r6, r7 ; prefetch_l1 r25 ; mnz r15, r16, r17 }
{ mula_hu_hu r5, r6, r7 ; prefetch_l1_fault r25 ; fnop }
{ mula_hu_hu r5, r6, r7 ; prefetch_l2 r25 ; cmpeq r15, r16, r17 }
{ mula_hu_hu r5, r6, r7 ; prefetch_l2 r25 }
{ mula_hu_hu r5, r6, r7 ; prefetch_l2_fault r25 ; shli r15, r16, 5 }
{ mula_hu_hu r5, r6, r7 ; prefetch_l3 r25 ; rotli r15, r16, 5 }
{ mula_hu_hu r5, r6, r7 ; prefetch_l3_fault r25 ; mnz r15, r16, r17 }
{ mula_hu_hu r5, r6, r7 ; rotl r15, r16, r17 ; st r25, r26 }
{ mula_hu_hu r5, r6, r7 ; shl r15, r16, r17 ; st2 r25, r26 }
{ mula_hu_hu r5, r6, r7 ; shl1addx r15, r16, r17 ; st4 r25, r26 }
{ mula_hu_hu r5, r6, r7 ; shl3add r15, r16, r17 ; ld r25, r26 }
{ mula_hu_hu r5, r6, r7 ; shli r15, r16, 5 ; ld1u r25, r26 }
{ mula_hu_hu r5, r6, r7 ; shrsi r15, r16, 5 ; ld1u r25, r26 }
{ mula_hu_hu r5, r6, r7 ; shrui r15, r16, 5 ; ld2u r25, r26 }
{ mula_hu_hu r5, r6, r7 ; st r25, r26 ; mnz r15, r16, r17 }
{ mula_hu_hu r5, r6, r7 ; st1 r25, r26 ; fnop }
{ mula_hu_hu r5, r6, r7 ; st2 r25, r26 ; andi r15, r16, 5 }
{ mula_hu_hu r5, r6, r7 ; st2 r25, r26 ; xor r15, r16, r17 }
{ mula_hu_hu r5, r6, r7 ; st4 r25, r26 ; shl3add r15, r16, r17 }
{ mula_hu_hu r5, r6, r7 ; subx r15, r16, r17 ; ld r25, r26 }
{ mula_hu_hu r5, r6, r7 ; v1shl r15, r16, r17 }
{ mula_hu_hu r5, r6, r7 ; v4add r15, r16, r17 }
{ mula_hu_ls r5, r6, r7 ; andi r15, r16, 5 }
{ mula_hu_ls r5, r6, r7 ; ld r15, r16 }
{ mula_hu_ls r5, r6, r7 ; nor r15, r16, r17 }
{ mula_hu_ls r5, r6, r7 ; st2_add r15, r16, 5 }
{ mula_hu_ls r5, r6, r7 ; v1shrui r15, r16, 5 }
{ mula_hu_ls r5, r6, r7 ; v4shl r15, r16, r17 }
{ mula_hu_lu r5, r6, r7 ; fetchand4 r15, r16, r17 }
{ mula_hu_lu r5, r6, r7 ; ldnt2u r15, r16 }
{ mula_hu_lu r5, r6, r7 ; shl2add r15, r16, r17 }
{ mula_hu_lu r5, r6, r7 ; v1cmpltsi r15, r16, 5 }
{ mula_hu_lu r5, r6, r7 ; v2packh r15, r16, r17 }
{ mula_ls_ls r5, r6, r7 ; add r15, r16, r17 ; st r25, r26 }
{ mula_ls_ls r5, r6, r7 ; addx r15, r16, r17 ; st1 r25, r26 }
{ mula_ls_ls r5, r6, r7 ; and r15, r16, r17 ; st1 r25, r26 }
{ mula_ls_ls r5, r6, r7 ; cmpeq r15, r16, r17 ; st4 r25, r26 }
{ mula_ls_ls r5, r6, r7 ; cmples r15, r16, r17 ; st4 r25, r26 }
{ mula_ls_ls r5, r6, r7 ; cmpltsi r15, r16, 5 ; ld r25, r26 }
{ mula_ls_ls r5, r6, r7 ; cmpne r15, r16, r17 ; ld1s r25, r26 }
{ mula_ls_ls r5, r6, r7 ; fnop ; ld4s r25, r26 }
{ mula_ls_ls r5, r6, r7 ; info 19 ; ld4u r25, r26 }
{ mula_ls_ls r5, r6, r7 ; jalrp r15 ; ld4s r25, r26 }
{ mula_ls_ls r5, r6, r7 ; jrp r15 ; prefetch r25 }
{ mula_ls_ls r5, r6, r7 ; ld r25, r26 ; nor r15, r16, r17 }
{ mula_ls_ls r5, r6, r7 ; ld1s r25, r26 ; jr r15 }
{ mula_ls_ls r5, r6, r7 ; ld1u r25, r26 ; cmplts r15, r16, r17 }
{ mula_ls_ls r5, r6, r7 ; ld2s r25, r26 ; addi r15, r16, 5 }
{ mula_ls_ls r5, r6, r7 ; ld2s r25, r26 ; shru r15, r16, r17 }
{ mula_ls_ls r5, r6, r7 ; ld2u r25, r26 ; shl1add r15, r16, r17 }
{ mula_ls_ls r5, r6, r7 ; ld4s r25, r26 ; move r15, r16 }
{ mula_ls_ls r5, r6, r7 ; ld4u r25, r26 ; fnop }
{ mula_ls_ls r5, r6, r7 ; ldnt1u r15, r16 }
{ mula_ls_ls r5, r6, r7 ; mnz r15, r16, r17 ; prefetch_l1 r25 }
{ mula_ls_ls r5, r6, r7 ; movei r15, 5 ; prefetch_l2 r25 }
{ mula_ls_ls r5, r6, r7 ; nop ; prefetch_l2 r25 }
{ mula_ls_ls r5, r6, r7 ; or r15, r16, r17 ; prefetch_l3 r25 }
{ mula_ls_ls r5, r6, r7 ; prefetch r25 ; shl r15, r16, r17 }
{ mula_ls_ls r5, r6, r7 ; prefetch_l1 r25 ; jalr r15 }
{ mula_ls_ls r5, r6, r7 ; prefetch_l1_fault r25 ; cmpleu r15, r16, r17 }
{ mula_ls_ls r5, r6, r7 ; prefetch_l2 r25 ; addi r15, r16, 5 }
{ mula_ls_ls r5, r6, r7 ; prefetch_l2 r25 ; shru r15, r16, r17 }
{ mula_ls_ls r5, r6, r7 ; prefetch_l2_fault r25 ; shl1addx r15, r16, r17 }
{ mula_ls_ls r5, r6, r7 ; prefetch_l3 r25 ; mz r15, r16, r17 }
{ mula_ls_ls r5, r6, r7 ; prefetch_l3_fault r25 ; jalr r15 }
{ mula_ls_ls r5, r6, r7 ; rotl r15, r16, r17 ; prefetch_l1_fault r25 }
{ mula_ls_ls r5, r6, r7 ; shl r15, r16, r17 ; prefetch_l2_fault r25 }
{ mula_ls_ls r5, r6, r7 ; shl1addx r15, r16, r17 ; prefetch_l3 r25 }
{ mula_ls_ls r5, r6, r7 ; shl2addx r15, r16, r17 ; st r25, r26 }
{ mula_ls_ls r5, r6, r7 ; shl3addx r15, r16, r17 ; st2 r25, r26 }
{ mula_ls_ls r5, r6, r7 ; shrs r15, r16, r17 ; st2 r25, r26 }
{ mula_ls_ls r5, r6, r7 ; shru r15, r16, r17 }
{ mula_ls_ls r5, r6, r7 ; st r25, r26 ; jalr r15 }
{ mula_ls_ls r5, r6, r7 ; st1 r25, r26 ; cmpleu r15, r16, r17 }
{ mula_ls_ls r5, r6, r7 ; st2 r25, r26 ; add r15, r16, r17 }
{ mula_ls_ls r5, r6, r7 ; st2 r25, r26 ; shrsi r15, r16, 5 }
{ mula_ls_ls r5, r6, r7 ; st4 r25, r26 ; shl r15, r16, r17 }
{ mula_ls_ls r5, r6, r7 ; sub r15, r16, r17 ; st r25, r26 }
{ mula_ls_ls r5, r6, r7 ; v1maxui r15, r16, 5 }
{ mula_ls_ls r5, r6, r7 ; v2shrsi r15, r16, 5 }
{ mula_ls_lu r5, r6, r7 ; addx r15, r16, r17 }
{ mula_ls_lu r5, r6, r7 ; iret }
{ mula_ls_lu r5, r6, r7 ; movei r15, 5 }
{ mula_ls_lu r5, r6, r7 ; shruxi r15, r16, 5 }
{ mula_ls_lu r5, r6, r7 ; v1shl r15, r16, r17 }
{ mula_ls_lu r5, r6, r7 ; v4add r15, r16, r17 }
{ mula_lu_lu r5, r6, r7 ; addi r15, r16, 5 ; prefetch r25 }
{ mula_lu_lu r5, r6, r7 ; addxi r15, r16, 5 ; prefetch_l1 r25 }
{ mula_lu_lu r5, r6, r7 ; andi r15, r16, 5 ; prefetch_l1 r25 }
{ mula_lu_lu r5, r6, r7 ; cmpeqi r15, r16, 5 ; prefetch_l2 r25 }
{ mula_lu_lu r5, r6, r7 ; cmpleu r15, r16, r17 ; prefetch_l2 r25 }
{ mula_lu_lu r5, r6, r7 ; cmpltsi r15, r16, 5 ; prefetch_l3 r25 }
{ mula_lu_lu r5, r6, r7 ; cmpne r15, r16, r17 ; prefetch_l3_fault r25 }
{ mula_lu_lu r5, r6, r7 ; fnop ; st4 r25, r26 }
{ mula_lu_lu r5, r6, r7 ; info 19 }
{ mula_lu_lu r5, r6, r7 ; jalrp r15 ; st4 r25, r26 }
{ mula_lu_lu r5, r6, r7 ; ld r15, r16 }
{ mula_lu_lu r5, r6, r7 ; ld r25, r26 ; shrs r15, r16, r17 }
{ mula_lu_lu r5, r6, r7 ; ld1s r25, r26 ; shl r15, r16, r17 }
{ mula_lu_lu r5, r6, r7 ; ld1u r25, r26 ; mnz r15, r16, r17 }
{ mula_lu_lu r5, r6, r7 ; ld2s r25, r26 ; cmpne r15, r16, r17 }
{ mula_lu_lu r5, r6, r7 ; ld2u r25, r26 ; and r15, r16, r17 }
{ mula_lu_lu r5, r6, r7 ; ld2u r25, r26 ; subx r15, r16, r17 }
{ mula_lu_lu r5, r6, r7 ; ld4s r25, r26 ; shl2addx r15, r16, r17 }
{ mula_lu_lu r5, r6, r7 ; ld4u r25, r26 ; nop }
{ mula_lu_lu r5, r6, r7 ; lnk r15 ; ld1s r25, r26 }
{ mula_lu_lu r5, r6, r7 ; move r15, r16 ; ld1s r25, r26 }
{ mula_lu_lu r5, r6, r7 ; mz r15, r16, r17 ; ld1s r25, r26 }
{ mula_lu_lu r5, r6, r7 ; nor r15, r16, r17 ; ld2s r25, r26 }
{ mula_lu_lu r5, r6, r7 ; prefetch r25 ; addxi r15, r16, 5 }
{ mula_lu_lu r5, r6, r7 ; prefetch r25 ; sub r15, r16, r17 }
{ mula_lu_lu r5, r6, r7 ; prefetch_l1 r25 ; rotl r15, r16, r17 }
{ mula_lu_lu r5, r6, r7 ; prefetch_l1_fault r25 ; lnk r15 }
{ mula_lu_lu r5, r6, r7 ; prefetch_l2 r25 ; cmpne r15, r16, r17 }
{ mula_lu_lu r5, r6, r7 ; prefetch_l2_fault r25 ; andi r15, r16, 5 }
{ mula_lu_lu r5, r6, r7 ; prefetch_l2_fault r25 ; xor r15, r16, r17 }
{ mula_lu_lu r5, r6, r7 ; prefetch_l3 r25 ; shl3addx r15, r16, r17 }
{ mula_lu_lu r5, r6, r7 ; prefetch_l3_fault r25 ; rotl r15, r16, r17 }
{ mula_lu_lu r5, r6, r7 ; rotli r15, r16, 5 ; ld1u r25, r26 }
{ mula_lu_lu r5, r6, r7 ; shl1add r15, r16, r17 ; ld2s r25, r26 }
{ mula_lu_lu r5, r6, r7 ; shl2add r15, r16, r17 ; ld4s r25, r26 }
{ mula_lu_lu r5, r6, r7 ; shl3add r15, r16, r17 ; prefetch r25 }
{ mula_lu_lu r5, r6, r7 ; shli r15, r16, 5 ; prefetch_l1_fault r25 }
{ mula_lu_lu r5, r6, r7 ; shrsi r15, r16, 5 ; prefetch_l1_fault r25 }
{ mula_lu_lu r5, r6, r7 ; shrui r15, r16, 5 ; prefetch_l2_fault r25 }
{ mula_lu_lu r5, r6, r7 ; st r25, r26 ; rotl r15, r16, r17 }
{ mula_lu_lu r5, r6, r7 ; st1 r25, r26 ; lnk r15 }
{ mula_lu_lu r5, r6, r7 ; st2 r25, r26 ; cmpltu r15, r16, r17 }
{ mula_lu_lu r5, r6, r7 ; st4 r25, r26 ; addxi r15, r16, 5 }
{ mula_lu_lu r5, r6, r7 ; st4 r25, r26 ; sub r15, r16, r17 }
{ mula_lu_lu r5, r6, r7 ; subx r15, r16, r17 ; prefetch r25 }
{ mula_lu_lu r5, r6, r7 ; v1subuc r15, r16, r17 }
{ mula_lu_lu r5, r6, r7 ; v4shrs r15, r16, r17 }
{ mulax r5, r6, r7 ; add r15, r16, r17 ; st1 r25, r26 }
{ mulax r5, r6, r7 ; addx r15, r16, r17 ; st2 r25, r26 }
{ mulax r5, r6, r7 ; and r15, r16, r17 ; st2 r25, r26 }
{ mulax r5, r6, r7 ; cmpeq r15, r16, r17 }
{ mulax r5, r6, r7 ; cmples r15, r16, r17 }
{ mulax r5, r6, r7 ; cmpltsi r15, r16, 5 ; ld1s r25, r26 }
{ mulax r5, r6, r7 ; cmpne r15, r16, r17 ; ld1u r25, r26 }
{ mulax r5, r6, r7 ; fnop ; ld4u r25, r26 }
{ mulax r5, r6, r7 ; info 19 ; prefetch r25 }
{ mulax r5, r6, r7 ; jalrp r15 ; ld4u r25, r26 }
{ mulax r5, r6, r7 ; jrp r15 ; prefetch_l1 r25 }
{ mulax r5, r6, r7 ; ld r25, r26 ; or r15, r16, r17 }
{ mulax r5, r6, r7 ; ld1s r25, r26 ; jrp r15 }
{ mulax r5, r6, r7 ; ld1u r25, r26 ; cmpltsi r15, r16, 5 }
{ mulax r5, r6, r7 ; ld2s r25, r26 ; addx r15, r16, r17 }
{ mulax r5, r6, r7 ; ld2s r25, r26 ; shrui r15, r16, 5 }
{ mulax r5, r6, r7 ; ld2u r25, r26 ; shl1addx r15, r16, r17 }
{ mulax r5, r6, r7 ; ld4s r25, r26 ; movei r15, 5 }
{ mulax r5, r6, r7 ; ld4u r25, r26 ; ill }
{ mulax r5, r6, r7 ; ldnt1u_add r15, r16, 5 }
{ mulax r5, r6, r7 ; mnz r15, r16, r17 ; prefetch_l1_fault r25 }
{ mulax r5, r6, r7 ; movei r15, 5 ; prefetch_l2_fault r25 }
{ mulax r5, r6, r7 ; nop ; prefetch_l2_fault r25 }
{ mulax r5, r6, r7 ; or r15, r16, r17 ; prefetch_l3_fault r25 }
{ mulax r5, r6, r7 ; prefetch r25 ; shl1add r15, r16, r17 }
{ mulax r5, r6, r7 ; prefetch_l1 r25 ; jalrp r15 }
{ mulax r5, r6, r7 ; prefetch_l1_fault r25 ; cmplts r15, r16, r17 }
{ mulax r5, r6, r7 ; prefetch_l2 r25 ; addx r15, r16, r17 }
{ mulax r5, r6, r7 ; prefetch_l2 r25 ; shrui r15, r16, 5 }
{ mulax r5, r6, r7 ; prefetch_l2_fault r25 ; shl2add r15, r16, r17 }
{ mulax r5, r6, r7 ; prefetch_l3 r25 ; nop }
{ mulax r5, r6, r7 ; prefetch_l3_fault r25 ; jalrp r15 }
{ mulax r5, r6, r7 ; rotl r15, r16, r17 ; prefetch_l2 r25 }
{ mulax r5, r6, r7 ; shl r15, r16, r17 ; prefetch_l3 r25 }
{ mulax r5, r6, r7 ; shl1addx r15, r16, r17 ; prefetch_l3_fault r25 }
{ mulax r5, r6, r7 ; shl2addx r15, r16, r17 ; st1 r25, r26 }
{ mulax r5, r6, r7 ; shl3addx r15, r16, r17 ; st4 r25, r26 }
{ mulax r5, r6, r7 ; shrs r15, r16, r17 ; st4 r25, r26 }
{ mulax r5, r6, r7 ; shrui r15, r16, 5 ; ld r25, r26 }
{ mulax r5, r6, r7 ; st r25, r26 ; jalrp r15 }
{ mulax r5, r6, r7 ; st1 r25, r26 ; cmplts r15, r16, r17 }
{ mulax r5, r6, r7 ; st2 r25, r26 ; addi r15, r16, 5 }
{ mulax r5, r6, r7 ; st2 r25, r26 ; shru r15, r16, r17 }
{ mulax r5, r6, r7 ; st4 r25, r26 ; shl1add r15, r16, r17 }
{ mulax r5, r6, r7 ; sub r15, r16, r17 ; st1 r25, r26 }
{ mulax r5, r6, r7 ; v1minu r15, r16, r17 }
{ mulax r5, r6, r7 ; v2shru r15, r16, r17 }
{ mulx r5, r6, r7 ; add r15, r16, r17 ; ld2u r25, r26 }
{ mulx r5, r6, r7 ; addx r15, r16, r17 ; ld4s r25, r26 }
{ mulx r5, r6, r7 ; and r15, r16, r17 ; ld4s r25, r26 }
{ mulx r5, r6, r7 ; cmpeq r15, r16, r17 ; prefetch r25 }
{ mulx r5, r6, r7 ; cmples r15, r16, r17 ; prefetch r25 }
{ mulx r5, r6, r7 ; cmplts r15, r16, r17 ; prefetch_l1_fault r25 }
{ mulx r5, r6, r7 ; cmpltu r15, r16, r17 ; prefetch_l2_fault r25 }
{ mulx r5, r6, r7 ; fetchor r15, r16, r17 }
{ mulx r5, r6, r7 ; ill ; st1 r25, r26 }
{ mulx r5, r6, r7 ; jalr r15 ; st r25, r26 }
{ mulx r5, r6, r7 ; jr r15 ; st2 r25, r26 }
{ mulx r5, r6, r7 ; ld r25, r26 ; jalr r15 }
{ mulx r5, r6, r7 ; ld1s r25, r26 ; cmpleu r15, r16, r17 }
{ mulx r5, r6, r7 ; ld1u r25, r26 ; add r15, r16, r17 }
{ mulx r5, r6, r7 ; ld1u r25, r26 ; shrsi r15, r16, 5 }
{ mulx r5, r6, r7 ; ld2s r25, r26 ; shl r15, r16, r17 }
{ mulx r5, r6, r7 ; ld2u r25, r26 ; mnz r15, r16, r17 }
{ mulx r5, r6, r7 ; ld4s r25, r26 ; cmpne r15, r16, r17 }
{ mulx r5, r6, r7 ; ld4u r25, r26 ; and r15, r16, r17 }
{ mulx r5, r6, r7 ; ld4u r25, r26 ; subx r15, r16, r17 }
{ mulx r5, r6, r7 ; mf }
{ mulx r5, r6, r7 ; movei r15, 5 ; ld r25, r26 }
{ mulx r5, r6, r7 ; nop ; ld r25, r26 }
{ mulx r5, r6, r7 ; or r15, r16, r17 ; ld1u r25, r26 }
{ mulx r5, r6, r7 ; prefetch r25 ; lnk r15 }
{ mulx r5, r6, r7 ; prefetch_l1 r25 ; cmpeqi r15, r16, 5 }
{ mulx r5, r6, r7 ; prefetch_l1_fault r15 }
{ mulx r5, r6, r7 ; prefetch_l1_fault r25 ; shrs r15, r16, r17 }
{ mulx r5, r6, r7 ; prefetch_l2 r25 ; shl r15, r16, r17 }
{ mulx r5, r6, r7 ; prefetch_l2_fault r25 ; move r15, r16 }
{ mulx r5, r6, r7 ; prefetch_l3 r25 ; ill }
{ mulx r5, r6, r7 ; prefetch_l3_fault r25 ; cmpeqi r15, r16, 5 }
{ mulx r5, r6, r7 ; raise }
{ mulx r5, r6, r7 ; shl r15, r16, r17 ; ld1s r25, r26 }
{ mulx r5, r6, r7 ; shl1addx r15, r16, r17 ; ld1u r25, r26 }
{ mulx r5, r6, r7 ; shl2addx r15, r16, r17 ; ld2u r25, r26 }
{ mulx r5, r6, r7 ; shl3addx r15, r16, r17 ; ld4u r25, r26 }
{ mulx r5, r6, r7 ; shrs r15, r16, r17 ; ld4u r25, r26 }
{ mulx r5, r6, r7 ; shru r15, r16, r17 ; prefetch_l1 r25 }
{ mulx r5, r6, r7 ; st r25, r26 ; cmpeqi r15, r16, 5 }
{ mulx r5, r6, r7 ; st1 r15, r16 }
{ mulx r5, r6, r7 ; st1 r25, r26 ; shrs r15, r16, r17 }
{ mulx r5, r6, r7 ; st2 r25, r26 ; rotli r15, r16, 5 }
{ mulx r5, r6, r7 ; st4 r25, r26 ; lnk r15 }
{ mulx r5, r6, r7 ; sub r15, r16, r17 ; ld2u r25, r26 }
{ mulx r5, r6, r7 ; v1cmples r15, r16, r17 }
{ mulx r5, r6, r7 ; v2minsi r15, r16, 5 }
{ mulx r5, r6, r7 ; xor r15, r16, r17 ; prefetch_l3_fault r25 }
{ mz r15, r16, r17 ; addi r5, r6, 5 ; st r25, r26 }
{ mz r15, r16, r17 ; addxi r5, r6, 5 ; st1 r25, r26 }
{ mz r15, r16, r17 ; andi r5, r6, 5 ; st1 r25, r26 }
{ mz r15, r16, r17 ; cmoveqz r5, r6, r7 ; st r25, r26 }
{ mz r15, r16, r17 ; cmpeq r5, r6, r7 ; st2 r25, r26 }
{ mz r15, r16, r17 ; cmples r5, r6, r7 }
{ mz r15, r16, r17 ; cmpltsi r5, r6, 5 ; ld1s r25, r26 }
{ mz r15, r16, r17 ; cmpne r5, r6, r7 ; ld1u r25, r26 }
{ mz r15, r16, r17 ; ctz r5, r6 ; st r25, r26 }
{ mz r15, r16, r17 ; fsingle_pack1 r5, r6 ; ld r25, r26 }
{ mz r15, r16, r17 ; infol 0x1234 }
{ mz r15, r16, r17 ; ld r25, r26 ; revbits r5, r6 }
{ mz r15, r16, r17 ; ld1s r25, r26 ; cmpne r5, r6, r7 }
{ mz r15, r16, r17 ; ld1s r25, r26 ; subx r5, r6, r7 }
{ mz r15, r16, r17 ; ld1u r25, r26 ; mulx r5, r6, r7 }
{ mz r15, r16, r17 ; ld2s r25, r26 ; cmpeqi r5, r6, 5 }
{ mz r15, r16, r17 ; ld2s r25, r26 ; shli r5, r6, 5 }
{ mz r15, r16, r17 ; ld2u r25, r26 ; mul_lu_lu r5, r6, r7 }
{ mz r15, r16, r17 ; ld4s r25, r26 ; and r5, r6, r7 }
{ mz r15, r16, r17 ; ld4s r25, r26 ; shl1add r5, r6, r7 }
{ mz r15, r16, r17 ; ld4u r25, r26 ; mnz r5, r6, r7 }
{ mz r15, r16, r17 ; ld4u r25, r26 ; xor r5, r6, r7 }
{ mz r15, r16, r17 ; move r5, r6 }
{ mz r15, r16, r17 ; mul_hs_hu r5, r6, r7 }
{ mz r15, r16, r17 ; mul_ls_ls r5, r6, r7 ; st2 r25, r26 }
{ mz r15, r16, r17 ; mula_hs_hs r5, r6, r7 ; st4 r25, r26 }
{ mz r15, r16, r17 ; mula_ls_ls r5, r6, r7 ; st r25, r26 }
{ mz r15, r16, r17 ; mulax r5, r6, r7 ; st1 r25, r26 }
{ mz r15, r16, r17 ; mz r5, r6, r7 ; st4 r25, r26 }
{ mz r15, r16, r17 ; or r5, r6, r7 ; ld r25, r26 }
{ mz r15, r16, r17 ; prefetch r25 ; addi r5, r6, 5 }
{ mz r15, r16, r17 ; prefetch r25 ; rotl r5, r6, r7 }
{ mz r15, r16, r17 ; prefetch_l1 r25 ; fnop }
{ mz r15, r16, r17 ; prefetch_l1 r25 ; tblidxb1 r5, r6 }
{ mz r15, r16, r17 ; prefetch_l1_fault r25 ; nop }
{ mz r15, r16, r17 ; prefetch_l2 r25 ; cmpleu r5, r6, r7 }
{ mz r15, r16, r17 ; prefetch_l2 r25 ; shrsi r5, r6, 5 }
{ mz r15, r16, r17 ; prefetch_l2_fault r25 ; mula_hu_hu r5, r6, r7 }
{ mz r15, r16, r17 ; prefetch_l3 r25 ; clz r5, r6 }
{ mz r15, r16, r17 ; prefetch_l3 r25 ; shl2add r5, r6, r7 }
{ mz r15, r16, r17 ; prefetch_l3_fault r25 ; movei r5, 5 }
{ mz r15, r16, r17 ; revbits r5, r6 ; ld r25, r26 }
{ mz r15, r16, r17 ; rotl r5, r6, r7 ; ld1u r25, r26 }
{ mz r15, r16, r17 ; shl r5, r6, r7 ; ld2u r25, r26 }
{ mz r15, r16, r17 ; shl1addx r5, r6, r7 ; ld4s r25, r26 }
{ mz r15, r16, r17 ; shl2addx r5, r6, r7 ; prefetch r25 }
{ mz r15, r16, r17 ; shl3addx r5, r6, r7 ; prefetch_l1_fault r25 }
{ mz r15, r16, r17 ; shrs r5, r6, r7 ; prefetch_l1_fault r25 }
{ mz r15, r16, r17 ; shru r5, r6, r7 ; prefetch_l2_fault r25 }
{ mz r15, r16, r17 ; st r25, r26 ; cmpeqi r5, r6, 5 }
{ mz r15, r16, r17 ; st r25, r26 ; shli r5, r6, 5 }
{ mz r15, r16, r17 ; st1 r25, r26 ; mul_lu_lu r5, r6, r7 }
{ mz r15, r16, r17 ; st2 r25, r26 ; and r5, r6, r7 }
{ mz r15, r16, r17 ; st2 r25, r26 ; shl1add r5, r6, r7 }
{ mz r15, r16, r17 ; st4 r25, r26 ; mnz r5, r6, r7 }
{ mz r15, r16, r17 ; st4 r25, r26 ; xor r5, r6, r7 }
{ mz r15, r16, r17 ; subxsc r5, r6, r7 }
{ mz r15, r16, r17 ; tblidxb2 r5, r6 ; ld1s r25, r26 }
{ mz r15, r16, r17 ; v1adiffu r5, r6, r7 }
{ mz r15, r16, r17 ; v1sub r5, r6, r7 }
{ mz r15, r16, r17 ; v2shrsi r5, r6, 5 }
{ mz r5, r6, r7 ; add r15, r16, r17 ; ld2u r25, r26 }
{ mz r5, r6, r7 ; addx r15, r16, r17 ; ld4s r25, r26 }
{ mz r5, r6, r7 ; and r15, r16, r17 ; ld4s r25, r26 }
{ mz r5, r6, r7 ; cmpeq r15, r16, r17 ; prefetch r25 }
{ mz r5, r6, r7 ; cmples r15, r16, r17 ; prefetch r25 }
{ mz r5, r6, r7 ; cmplts r15, r16, r17 ; prefetch_l1_fault r25 }
{ mz r5, r6, r7 ; cmpltu r15, r16, r17 ; prefetch_l2_fault r25 }
{ mz r5, r6, r7 ; fetchor r15, r16, r17 }
{ mz r5, r6, r7 ; ill ; st1 r25, r26 }
{ mz r5, r6, r7 ; jalr r15 ; st r25, r26 }
{ mz r5, r6, r7 ; jr r15 ; st2 r25, r26 }
{ mz r5, r6, r7 ; ld r25, r26 ; jalr r15 }
{ mz r5, r6, r7 ; ld1s r25, r26 ; cmpleu r15, r16, r17 }
{ mz r5, r6, r7 ; ld1u r25, r26 ; add r15, r16, r17 }
{ mz r5, r6, r7 ; ld1u r25, r26 ; shrsi r15, r16, 5 }
{ mz r5, r6, r7 ; ld2s r25, r26 ; shl r15, r16, r17 }
{ mz r5, r6, r7 ; ld2u r25, r26 ; mnz r15, r16, r17 }
{ mz r5, r6, r7 ; ld4s r25, r26 ; cmpne r15, r16, r17 }
{ mz r5, r6, r7 ; ld4u r25, r26 ; and r15, r16, r17 }
{ mz r5, r6, r7 ; ld4u r25, r26 ; subx r15, r16, r17 }
{ mz r5, r6, r7 ; mf }
{ mz r5, r6, r7 ; movei r15, 5 ; ld r25, r26 }
{ mz r5, r6, r7 ; nop ; ld r25, r26 }
{ mz r5, r6, r7 ; or r15, r16, r17 ; ld1u r25, r26 }
{ mz r5, r6, r7 ; prefetch r25 ; lnk r15 }
{ mz r5, r6, r7 ; prefetch_l1 r25 ; cmpeqi r15, r16, 5 }
{ mz r5, r6, r7 ; prefetch_l1_fault r15 }
{ mz r5, r6, r7 ; prefetch_l1_fault r25 ; shrs r15, r16, r17 }
{ mz r5, r6, r7 ; prefetch_l2 r25 ; shl r15, r16, r17 }
{ mz r5, r6, r7 ; prefetch_l2_fault r25 ; move r15, r16 }
{ mz r5, r6, r7 ; prefetch_l3 r25 ; ill }
{ mz r5, r6, r7 ; prefetch_l3_fault r25 ; cmpeqi r15, r16, 5 }
{ mz r5, r6, r7 ; raise }
{ mz r5, r6, r7 ; shl r15, r16, r17 ; ld1s r25, r26 }
{ mz r5, r6, r7 ; shl1addx r15, r16, r17 ; ld1u r25, r26 }
{ mz r5, r6, r7 ; shl2addx r15, r16, r17 ; ld2u r25, r26 }
{ mz r5, r6, r7 ; shl3addx r15, r16, r17 ; ld4u r25, r26 }
{ mz r5, r6, r7 ; shrs r15, r16, r17 ; ld4u r25, r26 }
{ mz r5, r6, r7 ; shru r15, r16, r17 ; prefetch_l1 r25 }
{ mz r5, r6, r7 ; st r25, r26 ; cmpeqi r15, r16, 5 }
{ mz r5, r6, r7 ; st1 r15, r16 }
{ mz r5, r6, r7 ; st1 r25, r26 ; shrs r15, r16, r17 }
{ mz r5, r6, r7 ; st2 r25, r26 ; rotli r15, r16, 5 }
{ mz r5, r6, r7 ; st4 r25, r26 ; lnk r15 }
{ mz r5, r6, r7 ; sub r15, r16, r17 ; ld2u r25, r26 }
{ mz r5, r6, r7 ; v1cmples r15, r16, r17 }
{ mz r5, r6, r7 ; v2minsi r15, r16, 5 }
{ mz r5, r6, r7 ; xor r15, r16, r17 ; prefetch_l3_fault r25 }
{ nop ; add r5, r6, r7 ; prefetch_l3_fault r25 }
{ nop ; addi r5, r6, 5 ; st1 r25, r26 }
{ nop ; addx r5, r6, r7 ; st1 r25, r26 }
{ nop ; addxi r5, r6, 5 ; st4 r25, r26 }
{ nop ; and r5, r6, r7 ; st1 r25, r26 }
{ nop ; andi r5, r6, 5 ; st4 r25, r26 }
{ nop ; cmoveqz r5, r6, r7 ; st1 r25, r26 }
{ nop ; cmpeq r15, r16, r17 ; st4 r25, r26 }
{ nop ; cmpeqi r5, r6, 5 ; ld r25, r26 }
{ nop ; cmples r5, r6, r7 ; ld r25, r26 }
{ nop ; cmpleu r5, r6, r7 ; ld1u r25, r26 }
{ nop ; cmplts r5, r6, r7 ; ld2u r25, r26 }
{ nop ; cmpltsi r5, r6, 5 ; ld4u r25, r26 }
{ nop ; cmpltu r5, r6, r7 ; prefetch_l1 r25 }
{ nop ; cmpne r5, r6, r7 ; prefetch_l1 r25 }
{ nop ; dblalign2 r15, r16, r17 }
{ nop ; fnop ; prefetch_l2_fault r25 }
{ nop ; ill ; ld4u r25, r26 }
{ nop ; jalr r15 ; ld4s r25, r26 }
{ nop ; jr r15 ; prefetch r25 }
{ nop ; ld r25, r26 ; and r15, r16, r17 }
{ nop ; ld r25, r26 ; mul_hu_hu r5, r6, r7 }
{ nop ; ld r25, r26 ; shrs r5, r6, r7 }
{ nop ; ld1s r25, r26 ; cmpleu r15, r16, r17 }
{ nop ; ld1s r25, r26 ; nor r5, r6, r7 }
{ nop ; ld1s r25, r26 ; tblidxb2 r5, r6 }
{ nop ; ld1u r25, r26 ; fsingle_pack1 r5, r6 }
{ nop ; ld1u r25, r26 ; shl1add r15, r16, r17 }
{ nop ; ld2s r25, r26 ; addx r5, r6, r7 }
{ nop ; ld2s r25, r26 ; movei r15, 5 }
{ nop ; ld2s r25, r26 ; shli r15, r16, 5 }
{ nop ; ld2u r25, r26 ; cmpeqi r15, r16, 5 }
{ nop ; ld2u r25, r26 ; mz r15, r16, r17 }
{ nop ; ld2u r25, r26 ; subx r15, r16, r17 }
{ nop ; ld4s r25, r26 ; cmpne r15, r16, r17 }
{ nop ; ld4s r25, r26 ; rotli r15, r16, 5 }
{ nop ; ld4u r25, r26 ; add r5, r6, r7 }
{ nop ; ld4u r25, r26 ; mnz r15, r16, r17 }
{ nop ; ld4u r25, r26 ; shl3add r15, r16, r17 }
{ nop ; ldnt4u r15, r16 }
{ nop ; mnz r15, r16, r17 ; st1 r25, r26 }
{ nop ; move r15, r16 ; st4 r25, r26 }
{ nop ; movei r5, 5 ; ld r25, r26 }
{ nop ; mul_hs_hs r5, r6, r7 }
{ nop ; mul_ls_ls r5, r6, r7 ; st1 r25, r26 }
{ nop ; mula_hs_hs r5, r6, r7 ; st2 r25, r26 }
{ nop ; mula_ls_ls r5, r6, r7 ; prefetch_l3_fault r25 }
{ nop ; mulax r5, r6, r7 ; st r25, r26 }
{ nop ; mz r15, r16, r17 ; st2 r25, r26 }
{ nop ; nop ; st4 r25, r26 }
{ nop ; or r15, r16, r17 ; ld r25, r26 }
{ nop ; pcnt r5, r6 ; ld r25, r26 }
{ nop ; prefetch r25 ; cmples r5, r6, r7 }
{ nop ; prefetch r25 ; nor r15, r16, r17 }
{ nop ; prefetch r25 ; tblidxb1 r5, r6 }
{ nop ; prefetch_l1 r25 ; cmpltu r15, r16, r17 }
{ nop ; prefetch_l1 r25 ; rotl r15, r16, r17 }
{ nop ; prefetch_l1_fault r25 ; add r15, r16, r17 }
{ nop ; prefetch_l1_fault r25 ; lnk r15 }
{ nop ; prefetch_l1_fault r25 ; shl2addx r5, r6, r7 }
{ nop ; prefetch_l2 r25 ; cmoveqz r5, r6, r7 }
{ nop ; prefetch_l2 r25 ; mula_ls_ls r5, r6, r7 }
{ nop ; prefetch_l2 r25 ; shrui r15, r16, 5 }
{ nop ; prefetch_l2_fault r25 ; cmpltsi r5, r6, 5 }
{ nop ; prefetch_l2_fault r25 ; revbytes r5, r6 }
{ nop ; prefetch_l3 r15 }
{ nop ; prefetch_l3 r25 ; jrp r15 }
{ nop ; prefetch_l3 r25 ; shl2addx r15, r16, r17 }
{ nop ; prefetch_l3_fault r25 ; clz r5, r6 }
{ nop ; prefetch_l3_fault r25 ; mula_hu_hu r5, r6, r7 }
{ nop ; prefetch_l3_fault r25 ; shru r5, r6, r7 }
{ nop ; revbytes r5, r6 ; ld4u r25, r26 }
{ nop ; rotl r5, r6, r7 ; prefetch_l1 r25 }
{ nop ; rotli r5, r6, 5 ; prefetch_l2 r25 }
{ nop ; shl r5, r6, r7 ; prefetch_l3 r25 }
{ nop ; shl1add r5, r6, r7 ; prefetch_l3 r25 }
{ nop ; shl1addx r5, r6, r7 ; st r25, r26 }
{ nop ; shl2add r5, r6, r7 ; st2 r25, r26 }
{ nop ; shl2addx r5, r6, r7 }
{ nop ; shl3addx r15, r16, r17 ; ld1s r25, r26 }
{ nop ; shli r15, r16, 5 ; ld2s r25, r26 }
{ nop ; shrs r15, r16, r17 ; ld1s r25, r26 }
{ nop ; shrsi r15, r16, 5 ; ld2s r25, r26 }
{ nop ; shru r15, r16, r17 ; ld4s r25, r26 }
{ nop ; shrui r15, r16, 5 ; prefetch r25 }
{ nop ; st r25, r26 ; addi r5, r6, 5 }
{ nop ; st r25, r26 ; move r15, r16 }
{ nop ; st r25, r26 ; shl3addx r15, r16, r17 }
{ nop ; st1 r25, r26 ; cmpeq r5, r6, r7 }
{ nop ; st1 r25, r26 ; mulx r5, r6, r7 }
{ nop ; st1 r25, r26 ; sub r5, r6, r7 }
{ nop ; st2 r25, r26 ; cmpltu r5, r6, r7 }
{ nop ; st2 r25, r26 ; rotl r5, r6, r7 }
{ nop ; st4 r25, r26 ; add r15, r16, r17 }
{ nop ; st4 r25, r26 ; lnk r15 }
{ nop ; st4 r25, r26 ; shl2addx r5, r6, r7 }
{ nop ; sub r15, r16, r17 ; ld2u r25, r26 }
{ nop ; subx r15, r16, r17 ; ld4u r25, r26 }
{ nop ; tblidxb0 r5, r6 ; ld1u r25, r26 }
{ nop ; tblidxb2 r5, r6 ; ld2u r25, r26 }
{ nop ; v1adiffu r5, r6, r7 }
{ nop ; v1minui r15, r16, 5 }
{ nop ; v2cmples r5, r6, r7 }
{ nop ; v2sadas r5, r6, r7 }
{ nop ; v4sub r15, r16, r17 }
{ nop ; xor r5, r6, r7 ; st2 r25, r26 }
{ nor r15, r16, r17 ; addi r5, r6, 5 ; st2 r25, r26 }
{ nor r15, r16, r17 ; addxi r5, r6, 5 ; st4 r25, r26 }
{ nor r15, r16, r17 ; andi r5, r6, 5 ; st4 r25, r26 }
{ nor r15, r16, r17 ; cmoveqz r5, r6, r7 ; st2 r25, r26 }
{ nor r15, r16, r17 ; cmpeq r5, r6, r7 }
{ nor r15, r16, r17 ; cmpleu r5, r6, r7 ; ld1s r25, r26 }
{ nor r15, r16, r17 ; cmpltsi r5, r6, 5 ; ld2s r25, r26 }
{ nor r15, r16, r17 ; cmpne r5, r6, r7 ; ld2u r25, r26 }
{ nor r15, r16, r17 ; ctz r5, r6 ; st2 r25, r26 }
{ nor r15, r16, r17 ; fsingle_pack1 r5, r6 ; ld1u r25, r26 }
{ nor r15, r16, r17 ; ld r25, r26 ; addi r5, r6, 5 }
{ nor r15, r16, r17 ; ld r25, r26 ; rotl r5, r6, r7 }
{ nor r15, r16, r17 ; ld1s r25, r26 ; fnop }
{ nor r15, r16, r17 ; ld1s r25, r26 ; tblidxb1 r5, r6 }
{ nor r15, r16, r17 ; ld1u r25, r26 ; nop }
{ nor r15, r16, r17 ; ld2s r25, r26 ; cmpleu r5, r6, r7 }
{ nor r15, r16, r17 ; ld2s r25, r26 ; shrsi r5, r6, 5 }
{ nor r15, r16, r17 ; ld2u r25, r26 ; mula_hu_hu r5, r6, r7 }
{ nor r15, r16, r17 ; ld4s r25, r26 ; clz r5, r6 }
{ nor r15, r16, r17 ; ld4s r25, r26 ; shl2add r5, r6, r7 }
{ nor r15, r16, r17 ; ld4u r25, r26 ; movei r5, 5 }
{ nor r15, r16, r17 ; mm r5, r6, 5, 7 }
{ nor r15, r16, r17 ; movei r5, 5 ; ld1s r25, r26 }
{ nor r15, r16, r17 ; mul_hs_lu r5, r6, r7 }
{ nor r15, r16, r17 ; mul_ls_ls r5, r6, r7 }
{ nor r15, r16, r17 ; mula_hs_hu r5, r6, r7 }
{ nor r15, r16, r17 ; mula_ls_ls r5, r6, r7 ; st2 r25, r26 }
{ nor r15, r16, r17 ; mulax r5, r6, r7 ; st4 r25, r26 }
{ nor r15, r16, r17 ; nop ; ld r25, r26 }
{ nor r15, r16, r17 ; or r5, r6, r7 ; ld1u r25, r26 }
{ nor r15, r16, r17 ; prefetch r25 ; addxi r5, r6, 5 }
{ nor r15, r16, r17 ; prefetch r25 ; shl r5, r6, r7 }
{ nor r15, r16, r17 ; prefetch_l1 r25 ; info 19 }
{ nor r15, r16, r17 ; prefetch_l1 r25 ; tblidxb3 r5, r6 }
{ nor r15, r16, r17 ; prefetch_l1_fault r25 ; or r5, r6, r7 }
{ nor r15, r16, r17 ; prefetch_l2 r25 ; cmpltsi r5, r6, 5 }
{ nor r15, r16, r17 ; prefetch_l2 r25 ; shrui r5, r6, 5 }
{ nor r15, r16, r17 ; prefetch_l2_fault r25 ; mula_lu_lu r5, r6, r7 }
{ nor r15, r16, r17 ; prefetch_l3 r25 ; cmovnez r5, r6, r7 }
{ nor r15, r16, r17 ; prefetch_l3 r25 ; shl3add r5, r6, r7 }
{ nor r15, r16, r17 ; prefetch_l3_fault r25 ; mul_hu_hu r5, r6, r7 }
{ nor r15, r16, r17 ; revbits r5, r6 ; ld1u r25, r26 }
{ nor r15, r16, r17 ; rotl r5, r6, r7 ; ld2u r25, r26 }
{ nor r15, r16, r17 ; shl r5, r6, r7 ; ld4u r25, r26 }
{ nor r15, r16, r17 ; shl1addx r5, r6, r7 ; prefetch r25 }
{ nor r15, r16, r17 ; shl2addx r5, r6, r7 ; prefetch_l1_fault r25 }
{ nor r15, r16, r17 ; shl3addx r5, r6, r7 ; prefetch_l2_fault r25 }
{ nor r15, r16, r17 ; shrs r5, r6, r7 ; prefetch_l2_fault r25 }
{ nor r15, r16, r17 ; shru r5, r6, r7 ; prefetch_l3_fault r25 }
{ nor r15, r16, r17 ; st r25, r26 ; cmpleu r5, r6, r7 }
{ nor r15, r16, r17 ; st r25, r26 ; shrsi r5, r6, 5 }
{ nor r15, r16, r17 ; st1 r25, r26 ; mula_hu_hu r5, r6, r7 }
{ nor r15, r16, r17 ; st2 r25, r26 ; clz r5, r6 }
{ nor r15, r16, r17 ; st2 r25, r26 ; shl2add r5, r6, r7 }
{ nor r15, r16, r17 ; st4 r25, r26 ; movei r5, 5 }
{ nor r15, r16, r17 ; sub r5, r6, r7 ; ld r25, r26 }
{ nor r15, r16, r17 ; tblidxb0 r5, r6 ; ld1s r25, r26 }
{ nor r15, r16, r17 ; tblidxb2 r5, r6 ; ld2s r25, r26 }
{ nor r15, r16, r17 ; v1cmpeq r5, r6, r7 }
{ nor r15, r16, r17 ; v2add r5, r6, r7 }
{ nor r15, r16, r17 ; v2shrui r5, r6, 5 }
{ nor r5, r6, r7 ; add r15, r16, r17 ; ld4u r25, r26 }
{ nor r5, r6, r7 ; addx r15, r16, r17 ; prefetch r25 }
{ nor r5, r6, r7 ; and r15, r16, r17 ; prefetch r25 }
{ nor r5, r6, r7 ; cmpeq r15, r16, r17 ; prefetch_l1_fault r25 }
{ nor r5, r6, r7 ; cmples r15, r16, r17 ; prefetch_l1_fault r25 }
{ nor r5, r6, r7 ; cmplts r15, r16, r17 ; prefetch_l2_fault r25 }
{ nor r5, r6, r7 ; cmpltu r15, r16, r17 ; prefetch_l3_fault r25 }
{ nor r5, r6, r7 ; finv r15 }
{ nor r5, r6, r7 ; ill ; st4 r25, r26 }
{ nor r5, r6, r7 ; jalr r15 ; st2 r25, r26 }
{ nor r5, r6, r7 ; jr r15 }
{ nor r5, r6, r7 ; ld r25, r26 ; jr r15 }
{ nor r5, r6, r7 ; ld1s r25, r26 ; cmpltsi r15, r16, 5 }
{ nor r5, r6, r7 ; ld1u r25, r26 ; addx r15, r16, r17 }
{ nor r5, r6, r7 ; ld1u r25, r26 ; shrui r15, r16, 5 }
{ nor r5, r6, r7 ; ld2s r25, r26 ; shl1addx r15, r16, r17 }
{ nor r5, r6, r7 ; ld2u r25, r26 ; movei r15, 5 }
{ nor r5, r6, r7 ; ld4s r25, r26 ; ill }
{ nor r5, r6, r7 ; ld4u r25, r26 ; cmpeq r15, r16, r17 }
{ nor r5, r6, r7 ; ld4u r25, r26 }
{ nor r5, r6, r7 ; mnz r15, r16, r17 ; ld r25, r26 }
{ nor r5, r6, r7 ; movei r15, 5 ; ld1u r25, r26 }
{ nor r5, r6, r7 ; nop ; ld1u r25, r26 }
{ nor r5, r6, r7 ; or r15, r16, r17 ; ld2u r25, r26 }
{ nor r5, r6, r7 ; prefetch r25 ; move r15, r16 }
{ nor r5, r6, r7 ; prefetch_l1 r25 ; cmpleu r15, r16, r17 }
{ nor r5, r6, r7 ; prefetch_l1_fault r25 ; addi r15, r16, 5 }
{ nor r5, r6, r7 ; prefetch_l1_fault r25 ; shru r15, r16, r17 }
{ nor r5, r6, r7 ; prefetch_l2 r25 ; shl1addx r15, r16, r17 }
{ nor r5, r6, r7 ; prefetch_l2_fault r25 ; mz r15, r16, r17 }
{ nor r5, r6, r7 ; prefetch_l3 r25 ; jalr r15 }
{ nor r5, r6, r7 ; prefetch_l3_fault r25 ; cmpleu r15, r16, r17 }
{ nor r5, r6, r7 ; rotl r15, r16, r17 ; ld1s r25, r26 }
{ nor r5, r6, r7 ; shl r15, r16, r17 ; ld2s r25, r26 }
{ nor r5, r6, r7 ; shl1addx r15, r16, r17 ; ld2u r25, r26 }
{ nor r5, r6, r7 ; shl2addx r15, r16, r17 ; ld4u r25, r26 }
{ nor r5, r6, r7 ; shl3addx r15, r16, r17 ; prefetch_l1 r25 }
{ nor r5, r6, r7 ; shrs r15, r16, r17 ; prefetch_l1 r25 }
{ nor r5, r6, r7 ; shru r15, r16, r17 ; prefetch_l2 r25 }
{ nor r5, r6, r7 ; st r25, r26 ; cmpleu r15, r16, r17 }
{ nor r5, r6, r7 ; st1 r25, r26 ; addi r15, r16, 5 }
{ nor r5, r6, r7 ; st1 r25, r26 ; shru r15, r16, r17 }
{ nor r5, r6, r7 ; st2 r25, r26 ; shl1add r15, r16, r17 }
{ nor r5, r6, r7 ; st4 r25, r26 ; move r15, r16 }
{ nor r5, r6, r7 ; sub r15, r16, r17 ; ld4u r25, r26 }
{ nor r5, r6, r7 ; v1cmplts r15, r16, r17 }
{ nor r5, r6, r7 ; v2mz r15, r16, r17 }
{ nor r5, r6, r7 ; xor r15, r16, r17 ; st1 r25, r26 }
{ or r15, r16, r17 ; addi r5, r6, 5 ; st2 r25, r26 }
{ or r15, r16, r17 ; addxi r5, r6, 5 ; st4 r25, r26 }
{ or r15, r16, r17 ; andi r5, r6, 5 ; st4 r25, r26 }
{ or r15, r16, r17 ; cmoveqz r5, r6, r7 ; st2 r25, r26 }
{ or r15, r16, r17 ; cmpeq r5, r6, r7 }
{ or r15, r16, r17 ; cmpleu r5, r6, r7 ; ld1s r25, r26 }
{ or r15, r16, r17 ; cmpltsi r5, r6, 5 ; ld2s r25, r26 }
{ or r15, r16, r17 ; cmpne r5, r6, r7 ; ld2u r25, r26 }
{ or r15, r16, r17 ; ctz r5, r6 ; st2 r25, r26 }
{ or r15, r16, r17 ; fsingle_pack1 r5, r6 ; ld1u r25, r26 }
{ or r15, r16, r17 ; ld r25, r26 ; addi r5, r6, 5 }
{ or r15, r16, r17 ; ld r25, r26 ; rotl r5, r6, r7 }
{ or r15, r16, r17 ; ld1s r25, r26 ; fnop }
{ or r15, r16, r17 ; ld1s r25, r26 ; tblidxb1 r5, r6 }
{ or r15, r16, r17 ; ld1u r25, r26 ; nop }
{ or r15, r16, r17 ; ld2s r25, r26 ; cmpleu r5, r6, r7 }
{ or r15, r16, r17 ; ld2s r25, r26 ; shrsi r5, r6, 5 }
{ or r15, r16, r17 ; ld2u r25, r26 ; mula_hu_hu r5, r6, r7 }
{ or r15, r16, r17 ; ld4s r25, r26 ; clz r5, r6 }
{ or r15, r16, r17 ; ld4s r25, r26 ; shl2add r5, r6, r7 }
{ or r15, r16, r17 ; ld4u r25, r26 ; movei r5, 5 }
{ or r15, r16, r17 ; mm r5, r6, 5, 7 }
{ or r15, r16, r17 ; movei r5, 5 ; ld1s r25, r26 }
{ or r15, r16, r17 ; mul_hs_lu r5, r6, r7 }
{ or r15, r16, r17 ; mul_ls_ls r5, r6, r7 }
{ or r15, r16, r17 ; mula_hs_hu r5, r6, r7 }
{ or r15, r16, r17 ; mula_ls_ls r5, r6, r7 ; st2 r25, r26 }
{ or r15, r16, r17 ; mulax r5, r6, r7 ; st4 r25, r26 }
{ or r15, r16, r17 ; nop ; ld r25, r26 }
{ or r15, r16, r17 ; or r5, r6, r7 ; ld1u r25, r26 }
{ or r15, r16, r17 ; prefetch r25 ; addxi r5, r6, 5 }
{ or r15, r16, r17 ; prefetch r25 ; shl r5, r6, r7 }
{ or r15, r16, r17 ; prefetch_l1 r25 ; info 19 }
{ or r15, r16, r17 ; prefetch_l1 r25 ; tblidxb3 r5, r6 }
{ or r15, r16, r17 ; prefetch_l1_fault r25 ; or r5, r6, r7 }
{ or r15, r16, r17 ; prefetch_l2 r25 ; cmpltsi r5, r6, 5 }
{ or r15, r16, r17 ; prefetch_l2 r25 ; shrui r5, r6, 5 }
{ or r15, r16, r17 ; prefetch_l2_fault r25 ; mula_lu_lu r5, r6, r7 }
{ or r15, r16, r17 ; prefetch_l3 r25 ; cmovnez r5, r6, r7 }
{ or r15, r16, r17 ; prefetch_l3 r25 ; shl3add r5, r6, r7 }
{ or r15, r16, r17 ; prefetch_l3_fault r25 ; mul_hu_hu r5, r6, r7 }
{ or r15, r16, r17 ; revbits r5, r6 ; ld1u r25, r26 }
{ or r15, r16, r17 ; rotl r5, r6, r7 ; ld2u r25, r26 }
{ or r15, r16, r17 ; shl r5, r6, r7 ; ld4u r25, r26 }
{ or r15, r16, r17 ; shl1addx r5, r6, r7 ; prefetch r25 }
{ or r15, r16, r17 ; shl2addx r5, r6, r7 ; prefetch_l1_fault r25 }
{ or r15, r16, r17 ; shl3addx r5, r6, r7 ; prefetch_l2_fault r25 }
{ or r15, r16, r17 ; shrs r5, r6, r7 ; prefetch_l2_fault r25 }
{ or r15, r16, r17 ; shru r5, r6, r7 ; prefetch_l3_fault r25 }
{ or r15, r16, r17 ; st r25, r26 ; cmpleu r5, r6, r7 }
{ or r15, r16, r17 ; st r25, r26 ; shrsi r5, r6, 5 }
{ or r15, r16, r17 ; st1 r25, r26 ; mula_hu_hu r5, r6, r7 }
{ or r15, r16, r17 ; st2 r25, r26 ; clz r5, r6 }
{ or r15, r16, r17 ; st2 r25, r26 ; shl2add r5, r6, r7 }
{ or r15, r16, r17 ; st4 r25, r26 ; movei r5, 5 }
{ or r15, r16, r17 ; sub r5, r6, r7 ; ld r25, r26 }
{ or r15, r16, r17 ; tblidxb0 r5, r6 ; ld1s r25, r26 }
{ or r15, r16, r17 ; tblidxb2 r5, r6 ; ld2s r25, r26 }
{ or r15, r16, r17 ; v1cmpeq r5, r6, r7 }
{ or r15, r16, r17 ; v2add r5, r6, r7 }
{ or r15, r16, r17 ; v2shrui r5, r6, 5 }
{ or r5, r6, r7 ; add r15, r16, r17 ; ld4u r25, r26 }
{ or r5, r6, r7 ; addx r15, r16, r17 ; prefetch r25 }
{ or r5, r6, r7 ; and r15, r16, r17 ; prefetch r25 }
{ or r5, r6, r7 ; cmpeq r15, r16, r17 ; prefetch_l1_fault r25 }
{ or r5, r6, r7 ; cmples r15, r16, r17 ; prefetch_l1_fault r25 }
{ or r5, r6, r7 ; cmplts r15, r16, r17 ; prefetch_l2_fault r25 }
{ or r5, r6, r7 ; cmpltu r15, r16, r17 ; prefetch_l3_fault r25 }
{ or r5, r6, r7 ; finv r15 }
{ or r5, r6, r7 ; ill ; st4 r25, r26 }
{ or r5, r6, r7 ; jalr r15 ; st2 r25, r26 }
{ or r5, r6, r7 ; jr r15 }
{ or r5, r6, r7 ; ld r25, r26 ; jr r15 }
{ or r5, r6, r7 ; ld1s r25, r26 ; cmpltsi r15, r16, 5 }
{ or r5, r6, r7 ; ld1u r25, r26 ; addx r15, r16, r17 }
{ or r5, r6, r7 ; ld1u r25, r26 ; shrui r15, r16, 5 }
{ or r5, r6, r7 ; ld2s r25, r26 ; shl1addx r15, r16, r17 }
{ or r5, r6, r7 ; ld2u r25, r26 ; movei r15, 5 }
{ or r5, r6, r7 ; ld4s r25, r26 ; ill }
{ or r5, r6, r7 ; ld4u r25, r26 ; cmpeq r15, r16, r17 }
{ or r5, r6, r7 ; ld4u r25, r26 }
{ or r5, r6, r7 ; mnz r15, r16, r17 ; ld r25, r26 }
{ or r5, r6, r7 ; movei r15, 5 ; ld1u r25, r26 }
{ or r5, r6, r7 ; nop ; ld1u r25, r26 }
{ or r5, r6, r7 ; or r15, r16, r17 ; ld2u r25, r26 }
{ or r5, r6, r7 ; prefetch r25 ; move r15, r16 }
{ or r5, r6, r7 ; prefetch_l1 r25 ; cmpleu r15, r16, r17 }
{ or r5, r6, r7 ; prefetch_l1_fault r25 ; addi r15, r16, 5 }
{ or r5, r6, r7 ; prefetch_l1_fault r25 ; shru r15, r16, r17 }
{ or r5, r6, r7 ; prefetch_l2 r25 ; shl1addx r15, r16, r17 }
{ or r5, r6, r7 ; prefetch_l2_fault r25 ; mz r15, r16, r17 }
{ or r5, r6, r7 ; prefetch_l3 r25 ; jalr r15 }
{ or r5, r6, r7 ; prefetch_l3_fault r25 ; cmpleu r15, r16, r17 }
{ or r5, r6, r7 ; rotl r15, r16, r17 ; ld1s r25, r26 }
{ or r5, r6, r7 ; shl r15, r16, r17 ; ld2s r25, r26 }
{ or r5, r6, r7 ; shl1addx r15, r16, r17 ; ld2u r25, r26 }
{ or r5, r6, r7 ; shl2addx r15, r16, r17 ; ld4u r25, r26 }
{ or r5, r6, r7 ; shl3addx r15, r16, r17 ; prefetch_l1 r25 }
{ or r5, r6, r7 ; shrs r15, r16, r17 ; prefetch_l1 r25 }
{ or r5, r6, r7 ; shru r15, r16, r17 ; prefetch_l2 r25 }
{ or r5, r6, r7 ; st r25, r26 ; cmpleu r15, r16, r17 }
{ or r5, r6, r7 ; st1 r25, r26 ; addi r15, r16, 5 }
{ or r5, r6, r7 ; st1 r25, r26 ; shru r15, r16, r17 }
{ or r5, r6, r7 ; st2 r25, r26 ; shl1add r15, r16, r17 }
{ or r5, r6, r7 ; st4 r25, r26 ; move r15, r16 }
{ or r5, r6, r7 ; sub r15, r16, r17 ; ld4u r25, r26 }
{ or r5, r6, r7 ; v1cmplts r15, r16, r17 }
{ or r5, r6, r7 ; v2mz r15, r16, r17 }
{ or r5, r6, r7 ; xor r15, r16, r17 ; st1 r25, r26 }
{ ori r15, r16, 5 ; dblalign2 r5, r6, r7 }
{ ori r15, r16, 5 ; mula_hu_hu r5, r6, r7 }
{ ori r15, r16, 5 ; tblidxb1 r5, r6 }
{ ori r15, r16, 5 ; v1shl r5, r6, r7 }
{ ori r15, r16, 5 ; v2sads r5, r6, r7 }
{ ori r5, r6, 5 ; cmpltsi r15, r16, 5 }
{ ori r5, r6, 5 ; ld2u_add r15, r16, 5 }
{ ori r5, r6, 5 ; prefetch_add_l3 r15, 5 }
{ ori r5, r6, 5 ; stnt2_add r15, r16, 5 }
{ ori r5, r6, 5 ; v2cmples r15, r16, r17 }
{ ori r5, r6, 5 ; xori r15, r16, 5 }
{ pcnt r5, r6 ; addx r15, r16, r17 ; ld r25, r26 }
{ pcnt r5, r6 ; and r15, r16, r17 ; ld r25, r26 }
{ pcnt r5, r6 ; cmpeq r15, r16, r17 ; ld1u r25, r26 }
{ pcnt r5, r6 ; cmples r15, r16, r17 ; ld1u r25, r26 }
{ pcnt r5, r6 ; cmplts r15, r16, r17 ; ld2u r25, r26 }
{ pcnt r5, r6 ; cmpltu r15, r16, r17 ; ld4u r25, r26 }
{ pcnt r5, r6 ; fetchadd4 r15, r16, r17 }
{ pcnt r5, r6 ; ill ; prefetch_l2 r25 }
{ pcnt r5, r6 ; jalr r15 ; prefetch_l1_fault r25 }
{ pcnt r5, r6 ; jr r15 ; prefetch_l2_fault r25 }
{ pcnt r5, r6 ; ld r25, r26 ; cmpltu r15, r16, r17 }
{ pcnt r5, r6 ; ld1s r25, r26 ; and r15, r16, r17 }
{ pcnt r5, r6 ; ld1s r25, r26 ; subx r15, r16, r17 }
{ pcnt r5, r6 ; ld1u r25, r26 ; shl2addx r15, r16, r17 }
{ pcnt r5, r6 ; ld2s r25, r26 ; nop }
{ pcnt r5, r6 ; ld2u r25, r26 ; jalr r15 }
{ pcnt r5, r6 ; ld4s r25, r26 ; cmples r15, r16, r17 }
{ pcnt r5, r6 ; ld4u r15, r16 }
{ pcnt r5, r6 ; ld4u r25, r26 ; shrs r15, r16, r17 }
{ pcnt r5, r6 ; lnk r15 ; st r25, r26 }
{ pcnt r5, r6 ; move r15, r16 ; st r25, r26 }
{ pcnt r5, r6 ; mz r15, r16, r17 ; st r25, r26 }
{ pcnt r5, r6 ; nor r15, r16, r17 ; st2 r25, r26 }
{ pcnt r5, r6 ; prefetch r25 ; info 19 }
{ pcnt r5, r6 ; prefetch_l1 r25 ; addx r15, r16, r17 }
{ pcnt r5, r6 ; prefetch_l1 r25 ; shrui r15, r16, 5 }
{ pcnt r5, r6 ; prefetch_l1_fault r25 ; shl2add r15, r16, r17 }
{ pcnt r5, r6 ; prefetch_l2 r25 ; nop }
{ pcnt r5, r6 ; prefetch_l2_fault r25 ; jalrp r15 }
{ pcnt r5, r6 ; prefetch_l3 r25 ; cmplts r15, r16, r17 }
{ pcnt r5, r6 ; prefetch_l3_fault r25 ; addx r15, r16, r17 }
{ pcnt r5, r6 ; prefetch_l3_fault r25 ; shrui r15, r16, 5 }
{ pcnt r5, r6 ; rotli r15, r16, 5 ; st1 r25, r26 }
{ pcnt r5, r6 ; shl1add r15, r16, r17 ; st2 r25, r26 }
{ pcnt r5, r6 ; shl2add r15, r16, r17 }
{ pcnt r5, r6 ; shl3addx r15, r16, r17 ; ld1s r25, r26 }
{ pcnt r5, r6 ; shrs r15, r16, r17 ; ld1s r25, r26 }
{ pcnt r5, r6 ; shru r15, r16, r17 ; ld2s r25, r26 }
{ pcnt r5, r6 ; st r25, r26 ; addx r15, r16, r17 }
{ pcnt r5, r6 ; st r25, r26 ; shrui r15, r16, 5 }
{ pcnt r5, r6 ; st1 r25, r26 ; shl2add r15, r16, r17 }
{ pcnt r5, r6 ; st2 r25, r26 ; mz r15, r16, r17 }
{ pcnt r5, r6 ; st4 r25, r26 ; info 19 }
{ pcnt r5, r6 ; stnt_add r15, r16, 5 }
{ pcnt r5, r6 ; v1add r15, r16, r17 }
{ pcnt r5, r6 ; v2int_h r15, r16, r17 }
{ pcnt r5, r6 ; xor r15, r16, r17 ; prefetch_l1 r25 }
{ prefetch r15 ; cmulfr r5, r6, r7 }
{ prefetch r15 ; mul_ls_ls r5, r6, r7 }
{ prefetch r15 ; shrux r5, r6, r7 }
{ prefetch r15 ; v1mnz r5, r6, r7 }
{ prefetch r15 ; v2mults r5, r6, r7 }
{ prefetch r25 ; add r15, r16, r17 ; cmpeq r5, r6, r7 }
{ prefetch r25 ; add r15, r16, r17 ; shl3addx r5, r6, r7 }
{ prefetch r25 ; add r5, r6, r7 ; nop }
{ prefetch r25 ; addi r15, r16, 5 ; fsingle_pack1 r5, r6 }
{ prefetch r25 ; addi r15, r16, 5 ; tblidxb2 r5, r6 }
{ prefetch r25 ; addi r5, r6, 5 ; shl3add r15, r16, r17 }
{ prefetch r25 ; addx r15, r16, r17 ; mula_hu_hu r5, r6, r7 }
{ prefetch r25 ; addx r5, r6, r7 ; cmpeq r15, r16, r17 }
{ prefetch r25 ; addx r5, r6, r7 }
{ prefetch r25 ; addxi r15, r16, 5 ; revbits r5, r6 }
{ prefetch r25 ; addxi r5, r6, 5 ; info 19 }
{ prefetch r25 ; and r15, r16, r17 ; cmpeq r5, r6, r7 }
{ prefetch r25 ; and r15, r16, r17 ; shl3addx r5, r6, r7 }
{ prefetch r25 ; and r5, r6, r7 ; nop }
{ prefetch r25 ; andi r15, r16, 5 ; fsingle_pack1 r5, r6 }
{ prefetch r25 ; andi r15, r16, 5 ; tblidxb2 r5, r6 }
{ prefetch r25 ; andi r5, r6, 5 ; shl3add r15, r16, r17 }
{ prefetch r25 ; clz r5, r6 ; rotl r15, r16, r17 }
{ prefetch r25 ; cmoveqz r5, r6, r7 ; mnz r15, r16, r17 }
{ prefetch r25 ; cmovnez r5, r6, r7 ; ill }
{ prefetch r25 ; cmpeq r15, r16, r17 ; cmovnez r5, r6, r7 }
{ prefetch r25 ; cmpeq r15, r16, r17 ; shl3add r5, r6, r7 }
{ prefetch r25 ; cmpeq r5, r6, r7 ; mz r15, r16, r17 }
{ prefetch r25 ; cmpeqi r15, r16, 5 ; fnop }
{ prefetch r25 ; cmpeqi r15, r16, 5 ; tblidxb1 r5, r6 }
{ prefetch r25 ; cmpeqi r5, r6, 5 ; shl2addx r15, r16, r17 }
{ prefetch r25 ; cmples r15, r16, r17 ; mula_hs_hs r5, r6, r7 }
{ prefetch r25 ; cmples r5, r6, r7 ; andi r15, r16, 5 }
{ prefetch r25 ; cmples r5, r6, r7 ; xor r15, r16, r17 }
{ prefetch r25 ; cmpleu r15, r16, r17 ; pcnt r5, r6 }
{ prefetch r25 ; cmpleu r5, r6, r7 ; ill }
{ prefetch r25 ; cmplts r15, r16, r17 ; cmovnez r5, r6, r7 }
{ prefetch r25 ; cmplts r15, r16, r17 ; shl3add r5, r6, r7 }
{ prefetch r25 ; cmplts r5, r6, r7 ; mz r15, r16, r17 }
{ prefetch r25 ; cmpltsi r15, r16, 5 ; fnop }
{ prefetch r25 ; cmpltsi r15, r16, 5 ; tblidxb1 r5, r6 }
{ prefetch r25 ; cmpltsi r5, r6, 5 ; shl2addx r15, r16, r17 }
{ prefetch r25 ; cmpltu r15, r16, r17 ; mula_hs_hs r5, r6, r7 }
{ prefetch r25 ; cmpltu r5, r6, r7 ; andi r15, r16, 5 }
{ prefetch r25 ; cmpltu r5, r6, r7 ; xor r15, r16, r17 }
{ prefetch r25 ; cmpne r15, r16, r17 ; pcnt r5, r6 }
{ prefetch r25 ; cmpne r5, r6, r7 ; ill }
{ prefetch r25 ; ctz r5, r6 ; cmples r15, r16, r17 }
{ prefetch r25 ; fnop ; add r5, r6, r7 }
{ prefetch r25 ; fnop ; mnz r15, r16, r17 }
{ prefetch r25 ; fnop ; shl3add r15, r16, r17 }
{ prefetch r25 ; fsingle_pack1 r5, r6 ; ill }
{ prefetch r25 ; ill ; cmovnez r5, r6, r7 }
{ prefetch r25 ; ill ; shl3add r5, r6, r7 }
{ prefetch r25 ; info 19 ; cmpltsi r15, r16, 5 }
{ prefetch r25 ; info 19 ; revbits r5, r6 }
{ prefetch r25 ; info 19 }
{ prefetch r25 ; jalr r15 ; revbits r5, r6 }
{ prefetch r25 ; jalrp r15 ; cmpne r5, r6, r7 }
{ prefetch r25 ; jalrp r15 ; subx r5, r6, r7 }
{ prefetch r25 ; jr r15 ; mulx r5, r6, r7 }
{ prefetch r25 ; jrp r15 ; cmpeqi r5, r6, 5 }
{ prefetch r25 ; jrp r15 ; shli r5, r6, 5 }
{ prefetch r25 ; lnk r15 ; mul_lu_lu r5, r6, r7 }
{ prefetch r25 ; mnz r15, r16, r17 ; and r5, r6, r7 }
{ prefetch r25 ; mnz r15, r16, r17 ; shl1add r5, r6, r7 }
{ prefetch r25 ; mnz r5, r6, r7 ; lnk r15 }
{ prefetch r25 ; move r15, r16 ; cmpltsi r5, r6, 5 }
{ prefetch r25 ; move r15, r16 ; shrui r5, r6, 5 }
{ prefetch r25 ; move r5, r6 ; shl r15, r16, r17 }
{ prefetch r25 ; movei r15, 5 ; mul_hs_hs r5, r6, r7 }
{ prefetch r25 ; movei r5, 5 ; addi r15, r16, 5 }
{ prefetch r25 ; movei r5, 5 ; shru r15, r16, r17 }
{ prefetch r25 ; mul_hs_hs r5, r6, r7 ; shl2add r15, r16, r17 }
{ prefetch r25 ; mul_hu_hu r5, r6, r7 ; nor r15, r16, r17 }
{ prefetch r25 ; mul_ls_ls r5, r6, r7 ; jrp r15 }
{ prefetch r25 ; mul_lu_lu r5, r6, r7 ; cmpne r15, r16, r17 }
{ prefetch r25 ; mula_hs_hs r5, r6, r7 ; cmpeq r15, r16, r17 }
{ prefetch r25 ; mula_hs_hs r5, r6, r7 }
{ prefetch r25 ; mula_hu_hu r5, r6, r7 ; shrs r15, r16, r17 }
{ prefetch r25 ; mula_ls_ls r5, r6, r7 ; shl1add r15, r16, r17 }
{ prefetch r25 ; mula_lu_lu r5, r6, r7 ; mz r15, r16, r17 }
{ prefetch r25 ; mulax r5, r6, r7 ; jalrp r15 }
{ prefetch r25 ; mulx r5, r6, r7 ; cmpltsi r15, r16, 5 }
{ prefetch r25 ; mz r15, r16, r17 ; and r5, r6, r7 }
{ prefetch r25 ; mz r15, r16, r17 ; shl1add r5, r6, r7 }
{ prefetch r25 ; mz r5, r6, r7 ; lnk r15 }
{ prefetch r25 ; nop ; cmovnez r5, r6, r7 }
{ prefetch r25 ; nop ; mula_lu_lu r5, r6, r7 }
{ prefetch r25 ; nop ; shrui r5, r6, 5 }
{ prefetch r25 ; nor r15, r16, r17 ; mula_hs_hs r5, r6, r7 }
{ prefetch r25 ; nor r5, r6, r7 ; andi r15, r16, 5 }
{ prefetch r25 ; nor r5, r6, r7 ; xor r15, r16, r17 }
{ prefetch r25 ; or r15, r16, r17 ; pcnt r5, r6 }
{ prefetch r25 ; or r5, r6, r7 ; ill }
{ prefetch r25 ; pcnt r5, r6 ; cmples r15, r16, r17 }
{ prefetch r25 ; revbits r5, r6 ; addi r15, r16, 5 }
{ prefetch r25 ; revbits r5, r6 ; shru r15, r16, r17 }
{ prefetch r25 ; revbytes r5, r6 ; shl2add r15, r16, r17 }
{ prefetch r25 ; rotl r15, r16, r17 ; mul_lu_lu r5, r6, r7 }
{ prefetch r25 ; rotl r5, r6, r7 ; and r15, r16, r17 }
{ prefetch r25 ; rotl r5, r6, r7 ; subx r15, r16, r17 }
{ prefetch r25 ; rotli r15, r16, 5 ; or r5, r6, r7 }
{ prefetch r25 ; rotli r5, r6, 5 ; fnop }
{ prefetch r25 ; shl r15, r16, r17 ; cmoveqz r5, r6, r7 }
{ prefetch r25 ; shl r15, r16, r17 ; shl2addx r5, r6, r7 }
{ prefetch r25 ; shl r5, r6, r7 ; movei r15, 5 }
{ prefetch r25 ; shl1add r15, r16, r17 ; ctz r5, r6 }
{ prefetch r25 ; shl1add r15, r16, r17 ; tblidxb0 r5, r6 }
{ prefetch r25 ; shl1add r5, r6, r7 ; shl2add r15, r16, r17 }
{ prefetch r25 ; shl1addx r15, r16, r17 ; mul_lu_lu r5, r6, r7 }
{ prefetch r25 ; shl1addx r5, r6, r7 ; and r15, r16, r17 }
{ prefetch r25 ; shl1addx r5, r6, r7 ; subx r15, r16, r17 }
{ prefetch r25 ; shl2add r15, r16, r17 ; or r5, r6, r7 }
{ prefetch r25 ; shl2add r5, r6, r7 ; fnop }
{ prefetch r25 ; shl2addx r15, r16, r17 ; cmoveqz r5, r6, r7 }
{ prefetch r25 ; shl2addx r15, r16, r17 ; shl2addx r5, r6, r7 }
{ prefetch r25 ; shl2addx r5, r6, r7 ; movei r15, 5 }
{ prefetch r25 ; shl3add r15, r16, r17 ; ctz r5, r6 }
{ prefetch r25 ; shl3add r15, r16, r17 ; tblidxb0 r5, r6 }
{ prefetch r25 ; shl3add r5, r6, r7 ; shl2add r15, r16, r17 }
{ prefetch r25 ; shl3addx r15, r16, r17 ; mul_lu_lu r5, r6, r7 }
{ prefetch r25 ; shl3addx r5, r6, r7 ; and r15, r16, r17 }
{ prefetch r25 ; shl3addx r5, r6, r7 ; subx r15, r16, r17 }
{ prefetch r25 ; shli r15, r16, 5 ; or r5, r6, r7 }
{ prefetch r25 ; shli r5, r6, 5 ; fnop }
{ prefetch r25 ; shrs r15, r16, r17 ; cmoveqz r5, r6, r7 }
{ prefetch r25 ; shrs r15, r16, r17 ; shl2addx r5, r6, r7 }
{ prefetch r25 ; shrs r5, r6, r7 ; movei r15, 5 }
{ prefetch r25 ; shrsi r15, r16, 5 ; ctz r5, r6 }
{ prefetch r25 ; shrsi r15, r16, 5 ; tblidxb0 r5, r6 }
{ prefetch r25 ; shrsi r5, r6, 5 ; shl2add r15, r16, r17 }
{ prefetch r25 ; shru r15, r16, r17 ; mul_lu_lu r5, r6, r7 }
{ prefetch r25 ; shru r5, r6, r7 ; and r15, r16, r17 }
{ prefetch r25 ; shru r5, r6, r7 ; subx r15, r16, r17 }
{ prefetch r25 ; shrui r15, r16, 5 ; or r5, r6, r7 }
{ prefetch r25 ; shrui r5, r6, 5 ; fnop }
{ prefetch r25 ; sub r15, r16, r17 ; cmoveqz r5, r6, r7 }
{ prefetch r25 ; sub r15, r16, r17 ; shl2addx r5, r6, r7 }
{ prefetch r25 ; sub r5, r6, r7 ; movei r15, 5 }
{ prefetch r25 ; subx r15, r16, r17 ; ctz r5, r6 }
{ prefetch r25 ; subx r15, r16, r17 ; tblidxb0 r5, r6 }
{ prefetch r25 ; subx r5, r6, r7 ; shl2add r15, r16, r17 }
{ prefetch r25 ; tblidxb0 r5, r6 ; nor r15, r16, r17 }
{ prefetch r25 ; tblidxb1 r5, r6 ; jrp r15 }
{ prefetch r25 ; tblidxb2 r5, r6 ; cmpne r15, r16, r17 }
{ prefetch r25 ; tblidxb3 r5, r6 ; cmpeq r15, r16, r17 }
{ prefetch r25 ; tblidxb3 r5, r6 }
{ prefetch r25 ; xor r15, r16, r17 ; revbits r5, r6 }
{ prefetch r25 ; xor r5, r6, r7 ; info 19 }
{ prefetch_add_l1 r15, 5 ; bfexts r5, r6, 5, 7 }
{ prefetch_add_l1 r15, 5 ; fsingle_mul1 r5, r6, r7 }
{ prefetch_add_l1 r15, 5 ; revbits r5, r6 }
{ prefetch_add_l1 r15, 5 ; v1cmpltu r5, r6, r7 }
{ prefetch_add_l1 r15, 5 ; v2cmpeqi r5, r6, 5 }
{ prefetch_add_l1 r15, 5 ; v4int_l r5, r6, r7 }
{ prefetch_add_l1_fault r15, 5 ; cmulhr r5, r6, r7 }
{ prefetch_add_l1_fault r15, 5 ; mul_lu_lu r5, r6, r7 }
{ prefetch_add_l1_fault r15, 5 ; shufflebytes r5, r6, r7 }
{ prefetch_add_l1_fault r15, 5 ; v1mulu r5, r6, r7 }
{ prefetch_add_l1_fault r15, 5 ; v2packh r5, r6, r7 }
{ prefetch_add_l2 r15, 5 ; bfins r5, r6, 5, 7 }
{ prefetch_add_l2 r15, 5 ; fsingle_pack1 r5, r6 }
{ prefetch_add_l2 r15, 5 ; rotl r5, r6, r7 }
{ prefetch_add_l2 r15, 5 ; v1cmpne r5, r6, r7 }
{ prefetch_add_l2 r15, 5 ; v2cmpleu r5, r6, r7 }
{ prefetch_add_l2 r15, 5 ; v4shl r5, r6, r7 }
{ prefetch_add_l2_fault r15, 5 ; crc32_8 r5, r6, r7 }
{ prefetch_add_l2_fault r15, 5 ; mula_hs_hu r5, r6, r7 }
{ prefetch_add_l2_fault r15, 5 ; subx r5, r6, r7 }
{ prefetch_add_l2_fault r15, 5 ; v1mz r5, r6, r7 }
{ prefetch_add_l2_fault r15, 5 ; v2packuc r5, r6, r7 }
{ prefetch_add_l3 r15, 5 ; cmoveqz r5, r6, r7 }
{ prefetch_add_l3 r15, 5 ; fsingle_sub1 r5, r6, r7 }
{ prefetch_add_l3 r15, 5 ; shl r5, r6, r7 }
{ prefetch_add_l3 r15, 5 ; v1ddotpua r5, r6, r7 }
{ prefetch_add_l3 r15, 5 ; v2cmpltsi r5, r6, 5 }
{ prefetch_add_l3 r15, 5 ; v4shrs r5, r6, r7 }
{ prefetch_add_l3_fault r15, 5 ; dblalign r5, r6, r7 }
{ prefetch_add_l3_fault r15, 5 ; mula_hs_lu r5, r6, r7 }
{ prefetch_add_l3_fault r15, 5 ; tblidxb0 r5, r6 }
{ prefetch_add_l3_fault r15, 5 ; v1sadu r5, r6, r7 }
{ prefetch_add_l3_fault r15, 5 ; v2sadau r5, r6, r7 }
{ prefetch_l1 r15 ; cmpeq r5, r6, r7 }
{ prefetch_l1 r15 ; infol 0x1234 }
{ prefetch_l1 r15 ; shl1add r5, r6, r7 }
{ prefetch_l1 r15 ; v1ddotpusa r5, r6, r7 }
{ prefetch_l1 r15 ; v2cmpltui r5, r6, 5 }
{ prefetch_l1 r15 ; v4sub r5, r6, r7 }
{ prefetch_l1 r25 ; add r15, r16, r17 ; nor r5, r6, r7 }
{ prefetch_l1 r25 ; add r5, r6, r7 ; cmpne r15, r16, r17 }
{ prefetch_l1 r25 ; addi r15, r16, 5 ; clz r5, r6 }
{ prefetch_l1 r25 ; addi r15, r16, 5 ; shl2add r5, r6, r7 }
{ prefetch_l1 r25 ; addi r5, r6, 5 ; move r15, r16 }
{ prefetch_l1 r25 ; addx r15, r16, r17 ; cmpne r5, r6, r7 }
{ prefetch_l1 r25 ; addx r15, r16, r17 ; subx r5, r6, r7 }
{ prefetch_l1 r25 ; addx r5, r6, r7 ; shl1addx r15, r16, r17 }
{ prefetch_l1 r25 ; addxi r15, r16, 5 ; mul_ls_ls r5, r6, r7 }
{ prefetch_l1 r25 ; addxi r5, r6, 5 ; addxi r15, r16, 5 }
{ prefetch_l1 r25 ; addxi r5, r6, 5 ; sub r15, r16, r17 }
{ prefetch_l1 r25 ; and r15, r16, r17 ; nor r5, r6, r7 }
{ prefetch_l1 r25 ; and r5, r6, r7 ; cmpne r15, r16, r17 }
{ prefetch_l1 r25 ; andi r15, r16, 5 ; clz r5, r6 }
{ prefetch_l1 r25 ; andi r15, r16, 5 ; shl2add r5, r6, r7 }
{ prefetch_l1 r25 ; andi r5, r6, 5 ; move r15, r16 }
{ prefetch_l1 r25 ; clz r5, r6 ; info 19 }
{ prefetch_l1 r25 ; cmoveqz r5, r6, r7 ; cmpleu r15, r16, r17 }
{ prefetch_l1 r25 ; cmovnez r5, r6, r7 ; addx r15, r16, r17 }
{ prefetch_l1 r25 ; cmovnez r5, r6, r7 ; shrui r15, r16, 5 }
{ prefetch_l1 r25 ; cmpeq r15, r16, r17 ; nop }
{ prefetch_l1 r25 ; cmpeq r5, r6, r7 ; cmpltu r15, r16, r17 }
{ prefetch_l1 r25 ; cmpeqi r15, r16, 5 ; andi r5, r6, 5 }
{ prefetch_l1 r25 ; cmpeqi r15, r16, 5 ; shl1addx r5, r6, r7 }
{ prefetch_l1 r25 ; cmpeqi r5, r6, 5 ; mnz r15, r16, r17 }
{ prefetch_l1 r25 ; cmples r15, r16, r17 ; cmpltu r5, r6, r7 }
{ prefetch_l1 r25 ; cmples r15, r16, r17 ; sub r5, r6, r7 }
{ prefetch_l1 r25 ; cmples r5, r6, r7 ; shl1add r15, r16, r17 }
{ prefetch_l1 r25 ; cmpleu r15, r16, r17 ; mul_hu_hu r5, r6, r7 }
{ prefetch_l1 r25 ; cmpleu r5, r6, r7 ; addx r15, r16, r17 }
{ prefetch_l1 r25 ; cmpleu r5, r6, r7 ; shrui r15, r16, 5 }
{ prefetch_l1 r25 ; cmplts r15, r16, r17 ; nop }
{ prefetch_l1 r25 ; cmplts r5, r6, r7 ; cmpltu r15, r16, r17 }
{ prefetch_l1 r25 ; cmpltsi r15, r16, 5 ; andi r5, r6, 5 }
{ prefetch_l1 r25 ; cmpltsi r15, r16, 5 ; shl1addx r5, r6, r7 }
{ prefetch_l1 r25 ; cmpltsi r5, r6, 5 ; mnz r15, r16, r17 }
{ prefetch_l1 r25 ; cmpltu r15, r16, r17 ; cmpltu r5, r6, r7 }
{ prefetch_l1 r25 ; cmpltu r15, r16, r17 ; sub r5, r6, r7 }
{ prefetch_l1 r25 ; cmpltu r5, r6, r7 ; shl1add r15, r16, r17 }
{ prefetch_l1 r25 ; cmpne r15, r16, r17 ; mul_hu_hu r5, r6, r7 }
{ prefetch_l1 r25 ; cmpne r5, r6, r7 ; addx r15, r16, r17 }
{ prefetch_l1 r25 ; cmpne r5, r6, r7 ; shrui r15, r16, 5 }
{ prefetch_l1 r25 ; ctz r5, r6 ; shl2addx r15, r16, r17 }
{ prefetch_l1 r25 ; fnop ; cmpltu r5, r6, r7 }
{ prefetch_l1 r25 ; fnop ; rotl r5, r6, r7 }
{ prefetch_l1 r25 ; fsingle_pack1 r5, r6 ; addx r15, r16, r17 }
{ prefetch_l1 r25 ; fsingle_pack1 r5, r6 ; shrui r15, r16, 5 }
{ prefetch_l1 r25 ; ill ; nop }
{ prefetch_l1 r25 ; info 19 ; clz r5, r6 }
{ prefetch_l1 r25 ; info 19 ; mula_hu_hu r5, r6, r7 }
{ prefetch_l1 r25 ; info 19 ; shru r5, r6, r7 }
{ prefetch_l1 r25 ; jalr r15 ; mul_ls_ls r5, r6, r7 }
{ prefetch_l1 r25 ; jalrp r15 ; addxi r5, r6, 5 }
{ prefetch_l1 r25 ; jalrp r15 ; shl r5, r6, r7 }
{ prefetch_l1 r25 ; jr r15 ; info 19 }
{ prefetch_l1 r25 ; jr r15 ; tblidxb3 r5, r6 }
{ prefetch_l1 r25 ; jrp r15 ; or r5, r6, r7 }
{ prefetch_l1 r25 ; lnk r15 ; cmpltsi r5, r6, 5 }
{ prefetch_l1 r25 ; lnk r15 ; shrui r5, r6, 5 }
{ prefetch_l1 r25 ; mnz r15, r16, r17 ; mula_lu_lu r5, r6, r7 }
{ prefetch_l1 r25 ; mnz r5, r6, r7 ; cmples r15, r16, r17 }
{ prefetch_l1 r25 ; move r15, r16 ; addi r5, r6, 5 }
{ prefetch_l1 r25 ; move r15, r16 ; rotl r5, r6, r7 }
{ prefetch_l1 r25 ; move r5, r6 ; jalrp r15 }
{ prefetch_l1 r25 ; movei r15, 5 ; cmples r5, r6, r7 }
{ prefetch_l1 r25 ; movei r15, 5 ; shrs r5, r6, r7 }
{ prefetch_l1 r25 ; movei r5, 5 ; or r15, r16, r17 }
{ prefetch_l1 r25 ; mul_hs_hs r5, r6, r7 ; lnk r15 }
{ prefetch_l1 r25 ; mul_hu_hu r5, r6, r7 ; fnop }
{ prefetch_l1 r25 ; mul_ls_ls r5, r6, r7 ; cmpeqi r15, r16, 5 }
{ prefetch_l1 r25 ; mul_lu_lu r5, r6, r7 ; add r15, r16, r17 }
{ prefetch_l1 r25 ; mul_lu_lu r5, r6, r7 ; shrsi r15, r16, 5 }
{ prefetch_l1 r25 ; mula_hs_hs r5, r6, r7 ; shl1addx r15, r16, r17 }
{ prefetch_l1 r25 ; mula_hu_hu r5, r6, r7 ; nop }
{ prefetch_l1 r25 ; mula_ls_ls r5, r6, r7 ; jr r15 }
{ prefetch_l1 r25 ; mula_lu_lu r5, r6, r7 ; cmpltu r15, r16, r17 }
{ prefetch_l1 r25 ; mulax r5, r6, r7 ; andi r15, r16, 5 }
{ prefetch_l1 r25 ; mulax r5, r6, r7 ; xor r15, r16, r17 }
{ prefetch_l1 r25 ; mulx r5, r6, r7 ; shli r15, r16, 5 }
{ prefetch_l1 r25 ; mz r15, r16, r17 ; mula_lu_lu r5, r6, r7 }
{ prefetch_l1 r25 ; mz r5, r6, r7 ; cmples r15, r16, r17 }
{ prefetch_l1 r25 ; nop ; add r5, r6, r7 }
{ prefetch_l1 r25 ; nop ; mnz r15, r16, r17 }
{ prefetch_l1 r25 ; nop ; shl3add r15, r16, r17 }
{ prefetch_l1 r25 ; nor r15, r16, r17 ; cmpltu r5, r6, r7 }
{ prefetch_l1 r25 ; nor r15, r16, r17 ; sub r5, r6, r7 }
{ prefetch_l1 r25 ; nor r5, r6, r7 ; shl1add r15, r16, r17 }
{ prefetch_l1 r25 ; or r15, r16, r17 ; mul_hu_hu r5, r6, r7 }
{ prefetch_l1 r25 ; or r5, r6, r7 ; addx r15, r16, r17 }
{ prefetch_l1 r25 ; or r5, r6, r7 ; shrui r15, r16, 5 }
{ prefetch_l1 r25 ; pcnt r5, r6 ; shl2addx r15, r16, r17 }
{ prefetch_l1 r25 ; revbits r5, r6 ; or r15, r16, r17 }
{ prefetch_l1 r25 ; revbytes r5, r6 ; lnk r15 }
{ prefetch_l1 r25 ; rotl r15, r16, r17 ; cmpltsi r5, r6, 5 }
{ prefetch_l1 r25 ; rotl r15, r16, r17 ; shrui r5, r6, 5 }
{ prefetch_l1 r25 ; rotl r5, r6, r7 ; shl r15, r16, r17 }
{ prefetch_l1 r25 ; rotli r15, r16, 5 ; mul_hs_hs r5, r6, r7 }
{ prefetch_l1 r25 ; rotli r5, r6, 5 ; addi r15, r16, 5 }
{ prefetch_l1 r25 ; rotli r5, r6, 5 ; shru r15, r16, r17 }
{ prefetch_l1 r25 ; shl r15, r16, r17 ; mz r5, r6, r7 }
{ prefetch_l1 r25 ; shl r5, r6, r7 ; cmpltsi r15, r16, 5 }
{ prefetch_l1 r25 ; shl1add r15, r16, r17 ; and r5, r6, r7 }
{ prefetch_l1 r25 ; shl1add r15, r16, r17 ; shl1add r5, r6, r7 }
{ prefetch_l1 r25 ; shl1add r5, r6, r7 ; lnk r15 }
{ prefetch_l1 r25 ; shl1addx r15, r16, r17 ; cmpltsi r5, r6, 5 }
{ prefetch_l1 r25 ; shl1addx r15, r16, r17 ; shrui r5, r6, 5 }
{ prefetch_l1 r25 ; shl1addx r5, r6, r7 ; shl r15, r16, r17 }
{ prefetch_l1 r25 ; shl2add r15, r16, r17 ; mul_hs_hs r5, r6, r7 }
{ prefetch_l1 r25 ; shl2add r5, r6, r7 ; addi r15, r16, 5 }
{ prefetch_l1 r25 ; shl2add r5, r6, r7 ; shru r15, r16, r17 }
{ prefetch_l1 r25 ; shl2addx r15, r16, r17 ; mz r5, r6, r7 }
{ prefetch_l1 r25 ; shl2addx r5, r6, r7 ; cmpltsi r15, r16, 5 }
{ prefetch_l1 r25 ; shl3add r15, r16, r17 ; and r5, r6, r7 }
{ prefetch_l1 r25 ; shl3add r15, r16, r17 ; shl1add r5, r6, r7 }
{ prefetch_l1 r25 ; shl3add r5, r6, r7 ; lnk r15 }
{ prefetch_l1 r25 ; shl3addx r15, r16, r17 ; cmpltsi r5, r6, 5 }
{ prefetch_l1 r25 ; shl3addx r15, r16, r17 ; shrui r5, r6, 5 }
{ prefetch_l1 r25 ; shl3addx r5, r6, r7 ; shl r15, r16, r17 }
{ prefetch_l1 r25 ; shli r15, r16, 5 ; mul_hs_hs r5, r6, r7 }
{ prefetch_l1 r25 ; shli r5, r6, 5 ; addi r15, r16, 5 }
{ prefetch_l1 r25 ; shli r5, r6, 5 ; shru r15, r16, r17 }
{ prefetch_l1 r25 ; shrs r15, r16, r17 ; mz r5, r6, r7 }
{ prefetch_l1 r25 ; shrs r5, r6, r7 ; cmpltsi r15, r16, 5 }
{ prefetch_l1 r25 ; shrsi r15, r16, 5 ; and r5, r6, r7 }
{ prefetch_l1 r25 ; shrsi r15, r16, 5 ; shl1add r5, r6, r7 }
{ prefetch_l1 r25 ; shrsi r5, r6, 5 ; lnk r15 }
{ prefetch_l1 r25 ; shru r15, r16, r17 ; cmpltsi r5, r6, 5 }
{ prefetch_l1 r25 ; shru r15, r16, r17 ; shrui r5, r6, 5 }
{ prefetch_l1 r25 ; shru r5, r6, r7 ; shl r15, r16, r17 }
{ prefetch_l1 r25 ; shrui r15, r16, 5 ; mul_hs_hs r5, r6, r7 }
{ prefetch_l1 r25 ; shrui r5, r6, 5 ; addi r15, r16, 5 }
{ prefetch_l1 r25 ; shrui r5, r6, 5 ; shru r15, r16, r17 }
{ prefetch_l1 r25 ; sub r15, r16, r17 ; mz r5, r6, r7 }
{ prefetch_l1 r25 ; sub r5, r6, r7 ; cmpltsi r15, r16, 5 }
{ prefetch_l1 r25 ; subx r15, r16, r17 ; and r5, r6, r7 }
{ prefetch_l1 r25 ; subx r15, r16, r17 ; shl1add r5, r6, r7 }
{ prefetch_l1 r25 ; subx r5, r6, r7 ; lnk r15 }
{ prefetch_l1 r25 ; tblidxb0 r5, r6 ; fnop }
{ prefetch_l1 r25 ; tblidxb1 r5, r6 ; cmpeqi r15, r16, 5 }
{ prefetch_l1 r25 ; tblidxb2 r5, r6 ; add r15, r16, r17 }
{ prefetch_l1 r25 ; tblidxb2 r5, r6 ; shrsi r15, r16, 5 }
{ prefetch_l1 r25 ; tblidxb3 r5, r6 ; shl1addx r15, r16, r17 }
{ prefetch_l1 r25 ; xor r15, r16, r17 ; mul_ls_ls r5, r6, r7 }
{ prefetch_l1 r25 ; xor r5, r6, r7 ; addxi r15, r16, 5 }
{ prefetch_l1 r25 ; xor r5, r6, r7 ; sub r15, r16, r17 }
{ prefetch_l1_fault r15 ; dblalign4 r5, r6, r7 }
{ prefetch_l1_fault r15 ; mula_hu_ls r5, r6, r7 }
{ prefetch_l1_fault r15 ; tblidxb2 r5, r6 }
{ prefetch_l1_fault r15 ; v1shli r5, r6, 5 }
{ prefetch_l1_fault r15 ; v2sadu r5, r6, r7 }
{ prefetch_l1_fault r25 ; add r15, r16, r17 ; ctz r5, r6 }
{ prefetch_l1_fault r25 ; add r15, r16, r17 ; tblidxb0 r5, r6 }
{ prefetch_l1_fault r25 ; add r5, r6, r7 ; shl2add r15, r16, r17 }
{ prefetch_l1_fault r25 ; addi r15, r16, 5 ; mul_lu_lu r5, r6, r7 }
{ prefetch_l1_fault r25 ; addi r5, r6, 5 ; and r15, r16, r17 }
{ prefetch_l1_fault r25 ; addi r5, r6, 5 ; subx r15, r16, r17 }
{ prefetch_l1_fault r25 ; addx r15, r16, r17 ; or r5, r6, r7 }
{ prefetch_l1_fault r25 ; addx r5, r6, r7 ; fnop }
{ prefetch_l1_fault r25 ; addxi r15, r16, 5 ; cmoveqz r5, r6, r7 }
{ prefetch_l1_fault r25 ; addxi r15, r16, 5 ; shl2addx r5, r6, r7 }
{ prefetch_l1_fault r25 ; addxi r5, r6, 5 ; movei r15, 5 }
{ prefetch_l1_fault r25 ; and r15, r16, r17 ; ctz r5, r6 }
{ prefetch_l1_fault r25 ; and r15, r16, r17 ; tblidxb0 r5, r6 }
{ prefetch_l1_fault r25 ; and r5, r6, r7 ; shl2add r15, r16, r17 }
{ prefetch_l1_fault r25 ; andi r15, r16, 5 ; mul_lu_lu r5, r6, r7 }
{ prefetch_l1_fault r25 ; andi r5, r6, 5 ; and r15, r16, r17 }
{ prefetch_l1_fault r25 ; andi r5, r6, 5 ; subx r15, r16, r17 }
{ prefetch_l1_fault r25 ; clz r5, r6 ; shl3addx r15, r16, r17 }
{ prefetch_l1_fault r25 ; cmoveqz r5, r6, r7 ; rotli r15, r16, 5 }
{ prefetch_l1_fault r25 ; cmovnez r5, r6, r7 ; move r15, r16 }
{ prefetch_l1_fault r25 ; cmpeq r15, r16, r17 ; cmpne r5, r6, r7 }
{ prefetch_l1_fault r25 ; cmpeq r15, r16, r17 ; subx r5, r6, r7 }
{ prefetch_l1_fault r25 ; cmpeq r5, r6, r7 ; shl1addx r15, r16, r17 }
{ prefetch_l1_fault r25 ; cmpeqi r15, r16, 5 ; mul_ls_ls r5, r6, r7 }
{ prefetch_l1_fault r25 ; cmpeqi r5, r6, 5 ; addxi r15, r16, 5 }
{ prefetch_l1_fault r25 ; cmpeqi r5, r6, 5 ; sub r15, r16, r17 }
{ prefetch_l1_fault r25 ; cmples r15, r16, r17 ; nor r5, r6, r7 }
{ prefetch_l1_fault r25 ; cmples r5, r6, r7 ; cmpne r15, r16, r17 }
{ prefetch_l1_fault r25 ; cmpleu r15, r16, r17 ; clz r5, r6 }
{ prefetch_l1_fault r25 ; cmpleu r15, r16, r17 ; shl2add r5, r6, r7 }
{ prefetch_l1_fault r25 ; cmpleu r5, r6, r7 ; move r15, r16 }
{ prefetch_l1_fault r25 ; cmplts r15, r16, r17 ; cmpne r5, r6, r7 }
{ prefetch_l1_fault r25 ; cmplts r15, r16, r17 ; subx r5, r6, r7 }
{ prefetch_l1_fault r25 ; cmplts r5, r6, r7 ; shl1addx r15, r16, r17 }
{ prefetch_l1_fault r25 ; cmpltsi r15, r16, 5 ; mul_ls_ls r5, r6, r7 }
{ prefetch_l1_fault r25 ; cmpltsi r5, r6, 5 ; addxi r15, r16, 5 }
{ prefetch_l1_fault r25 ; cmpltsi r5, r6, 5 ; sub r15, r16, r17 }
{ prefetch_l1_fault r25 ; cmpltu r15, r16, r17 ; nor r5, r6, r7 }
{ prefetch_l1_fault r25 ; cmpltu r5, r6, r7 ; cmpne r15, r16, r17 }
{ prefetch_l1_fault r25 ; cmpne r15, r16, r17 ; clz r5, r6 }
{ prefetch_l1_fault r25 ; cmpne r15, r16, r17 ; shl2add r5, r6, r7 }
{ prefetch_l1_fault r25 ; cmpne r5, r6, r7 ; move r15, r16 }
{ prefetch_l1_fault r25 ; ctz r5, r6 ; info 19 }
{ prefetch_l1_fault r25 ; fnop ; and r5, r6, r7 }
{ prefetch_l1_fault r25 ; fnop ; mul_ls_ls r5, r6, r7 }
{ prefetch_l1_fault r25 ; fnop ; shrsi r15, r16, 5 }
{ prefetch_l1_fault r25 ; fsingle_pack1 r5, r6 ; move r15, r16 }
{ prefetch_l1_fault r25 ; ill ; cmpne r5, r6, r7 }
{ prefetch_l1_fault r25 ; ill ; subx r5, r6, r7 }
{ prefetch_l1_fault r25 ; info 19 ; fsingle_pack1 r5, r6 }
{ prefetch_l1_fault r25 ; info 19 ; shl1add r15, r16, r17 }
{ prefetch_l1_fault r25 ; jalr r15 ; cmoveqz r5, r6, r7 }
{ prefetch_l1_fault r25 ; jalr r15 ; shl2addx r5, r6, r7 }
{ prefetch_l1_fault r25 ; jalrp r15 ; mul_hs_hs r5, r6, r7 }
{ prefetch_l1_fault r25 ; jr r15 ; addi r5, r6, 5 }
{ prefetch_l1_fault r25 ; jr r15 ; rotl r5, r6, r7 }
{ prefetch_l1_fault r25 ; jrp r15 ; fnop }
{ prefetch_l1_fault r25 ; jrp r15 ; tblidxb1 r5, r6 }
{ prefetch_l1_fault r25 ; lnk r15 ; nop }
{ prefetch_l1_fault r25 ; mnz r15, r16, r17 ; cmpleu r5, r6, r7 }
{ prefetch_l1_fault r25 ; mnz r15, r16, r17 ; shrsi r5, r6, 5 }
{ prefetch_l1_fault r25 ; mnz r5, r6, r7 ; rotl r15, r16, r17 }
{ prefetch_l1_fault r25 ; move r15, r16 ; move r5, r6 }
{ prefetch_l1_fault r25 ; move r15, r16 }
{ prefetch_l1_fault r25 ; move r5, r6 ; shrs r15, r16, r17 }
{ prefetch_l1_fault r25 ; movei r15, 5 ; mulax r5, r6, r7 }
{ prefetch_l1_fault r25 ; movei r5, 5 ; cmpleu r15, r16, r17 }
{ prefetch_l1_fault r25 ; mul_hs_hs r5, r6, r7 ; addx r15, r16, r17 }
{ prefetch_l1_fault r25 ; mul_hs_hs r5, r6, r7 ; shrui r15, r16, 5 }
{ prefetch_l1_fault r25 ; mul_hu_hu r5, r6, r7 ; shl2addx r15, r16, r17 }
{ prefetch_l1_fault r25 ; mul_ls_ls r5, r6, r7 ; or r15, r16, r17 }
{ prefetch_l1_fault r25 ; mul_lu_lu r5, r6, r7 ; lnk r15 }
{ prefetch_l1_fault r25 ; mula_hs_hs r5, r6, r7 ; fnop }
{ prefetch_l1_fault r25 ; mula_hu_hu r5, r6, r7 ; cmpeqi r15, r16, 5 }
{ prefetch_l1_fault r25 ; mula_ls_ls r5, r6, r7 ; add r15, r16, r17 }
{ prefetch_l1_fault r25 ; mula_ls_ls r5, r6, r7 ; shrsi r15, r16, 5 }
{ prefetch_l1_fault r25 ; mula_lu_lu r5, r6, r7 ; shl1addx r15, r16, r17 }
{ prefetch_l1_fault r25 ; mulax r5, r6, r7 ; nop }
{ prefetch_l1_fault r25 ; mulx r5, r6, r7 ; jr r15 }
{ prefetch_l1_fault r25 ; mz r15, r16, r17 ; cmpleu r5, r6, r7 }
{ prefetch_l1_fault r25 ; mz r15, r16, r17 ; shrsi r5, r6, 5 }
{ prefetch_l1_fault r25 ; mz r5, r6, r7 ; rotl r15, r16, r17 }
{ prefetch_l1_fault r25 ; nop ; cmpleu r5, r6, r7 }
{ prefetch_l1_fault r25 ; nop ; or r15, r16, r17 }
{ prefetch_l1_fault r25 ; nop ; tblidxb3 r5, r6 }
{ prefetch_l1_fault r25 ; nor r15, r16, r17 ; nor r5, r6, r7 }
{ prefetch_l1_fault r25 ; nor r5, r6, r7 ; cmpne r15, r16, r17 }
{ prefetch_l1_fault r25 ; or r15, r16, r17 ; clz r5, r6 }
{ prefetch_l1_fault r25 ; or r15, r16, r17 ; shl2add r5, r6, r7 }
{ prefetch_l1_fault r25 ; or r5, r6, r7 ; move r15, r16 }
{ prefetch_l1_fault r25 ; pcnt r5, r6 ; info 19 }
{ prefetch_l1_fault r25 ; revbits r5, r6 ; cmpleu r15, r16, r17 }
{ prefetch_l1_fault r25 ; revbytes r5, r6 ; addx r15, r16, r17 }
{ prefetch_l1_fault r25 ; revbytes r5, r6 ; shrui r15, r16, 5 }
{ prefetch_l1_fault r25 ; rotl r15, r16, r17 ; nop }
{ prefetch_l1_fault r25 ; rotl r5, r6, r7 ; cmpltu r15, r16, r17 }
{ prefetch_l1_fault r25 ; rotli r15, r16, 5 ; andi r5, r6, 5 }
{ prefetch_l1_fault r25 ; rotli r15, r16, 5 ; shl1addx r5, r6, r7 }
{ prefetch_l1_fault r25 ; rotli r5, r6, 5 ; mnz r15, r16, r17 }
{ prefetch_l1_fault r25 ; shl r15, r16, r17 ; cmpltu r5, r6, r7 }
{ prefetch_l1_fault r25 ; shl r15, r16, r17 ; sub r5, r6, r7 }
{ prefetch_l1_fault r25 ; shl r5, r6, r7 ; shl1add r15, r16, r17 }
{ prefetch_l1_fault r25 ; shl1add r15, r16, r17 ; mul_hu_hu r5, r6, r7 }
{ prefetch_l1_fault r25 ; shl1add r5, r6, r7 ; addx r15, r16, r17 }
{ prefetch_l1_fault r25 ; shl1add r5, r6, r7 ; shrui r15, r16, 5 }
{ prefetch_l1_fault r25 ; shl1addx r15, r16, r17 ; nop }
{ prefetch_l1_fault r25 ; shl1addx r5, r6, r7 ; cmpltu r15, r16, r17 }
{ prefetch_l1_fault r25 ; shl2add r15, r16, r17 ; andi r5, r6, 5 }
{ prefetch_l1_fault r25 ; shl2add r15, r16, r17 ; shl1addx r5, r6, r7 }
{ prefetch_l1_fault r25 ; shl2add r5, r6, r7 ; mnz r15, r16, r17 }
{ prefetch_l1_fault r25 ; shl2addx r15, r16, r17 ; cmpltu r5, r6, r7 }
{ prefetch_l1_fault r25 ; shl2addx r15, r16, r17 ; sub r5, r6, r7 }
{ prefetch_l1_fault r25 ; shl2addx r5, r6, r7 ; shl1add r15, r16, r17 }
{ prefetch_l1_fault r25 ; shl3add r15, r16, r17 ; mul_hu_hu r5, r6, r7 }
{ prefetch_l1_fault r25 ; shl3add r5, r6, r7 ; addx r15, r16, r17 }
{ prefetch_l1_fault r25 ; shl3add r5, r6, r7 ; shrui r15, r16, 5 }
{ prefetch_l1_fault r25 ; shl3addx r15, r16, r17 ; nop }
{ prefetch_l1_fault r25 ; shl3addx r5, r6, r7 ; cmpltu r15, r16, r17 }
{ prefetch_l1_fault r25 ; shli r15, r16, 5 ; andi r5, r6, 5 }
{ prefetch_l1_fault r25 ; shli r15, r16, 5 ; shl1addx r5, r6, r7 }
{ prefetch_l1_fault r25 ; shli r5, r6, 5 ; mnz r15, r16, r17 }
{ prefetch_l1_fault r25 ; shrs r15, r16, r17 ; cmpltu r5, r6, r7 }
{ prefetch_l1_fault r25 ; shrs r15, r16, r17 ; sub r5, r6, r7 }
{ prefetch_l1_fault r25 ; shrs r5, r6, r7 ; shl1add r15, r16, r17 }
{ prefetch_l1_fault r25 ; shrsi r15, r16, 5 ; mul_hu_hu r5, r6, r7 }
{ prefetch_l1_fault r25 ; shrsi r5, r6, 5 ; addx r15, r16, r17 }
{ prefetch_l1_fault r25 ; shrsi r5, r6, 5 ; shrui r15, r16, 5 }
{ prefetch_l1_fault r25 ; shru r15, r16, r17 ; nop }
{ prefetch_l1_fault r25 ; shru r5, r6, r7 ; cmpltu r15, r16, r17 }
{ prefetch_l1_fault r25 ; shrui r15, r16, 5 ; andi r5, r6, 5 }
{ prefetch_l1_fault r25 ; shrui r15, r16, 5 ; shl1addx r5, r6, r7 }
{ prefetch_l1_fault r25 ; shrui r5, r6, 5 ; mnz r15, r16, r17 }
{ prefetch_l1_fault r25 ; sub r15, r16, r17 ; cmpltu r5, r6, r7 }
{ prefetch_l1_fault r25 ; sub r15, r16, r17 ; sub r5, r6, r7 }
{ prefetch_l1_fault r25 ; sub r5, r6, r7 ; shl1add r15, r16, r17 }
{ prefetch_l1_fault r25 ; subx r15, r16, r17 ; mul_hu_hu r5, r6, r7 }
{ prefetch_l1_fault r25 ; subx r5, r6, r7 ; addx r15, r16, r17 }
{ prefetch_l1_fault r25 ; subx r5, r6, r7 ; shrui r15, r16, 5 }
{ prefetch_l1_fault r25 ; tblidxb0 r5, r6 ; shl2addx r15, r16, r17 }
{ prefetch_l1_fault r25 ; tblidxb1 r5, r6 ; or r15, r16, r17 }
{ prefetch_l1_fault r25 ; tblidxb2 r5, r6 ; lnk r15 }
{ prefetch_l1_fault r25 ; tblidxb3 r5, r6 ; fnop }
{ prefetch_l1_fault r25 ; xor r15, r16, r17 ; cmoveqz r5, r6, r7 }
{ prefetch_l1_fault r25 ; xor r15, r16, r17 ; shl2addx r5, r6, r7 }
{ prefetch_l1_fault r25 ; xor r5, r6, r7 ; movei r15, 5 }
{ prefetch_l2 r15 ; cmples r5, r6, r7 }
{ prefetch_l2 r15 ; mnz r5, r6, r7 }
{ prefetch_l2 r15 ; shl2add r5, r6, r7 }
{ prefetch_l2 r15 ; v1dotpa r5, r6, r7 }
{ prefetch_l2 r15 ; v2dotp r5, r6, r7 }
{ prefetch_l2 r15 ; xor r5, r6, r7 }
{ prefetch_l2 r25 ; add r15, r16, r17 ; pcnt r5, r6 }
{ prefetch_l2 r25 ; add r5, r6, r7 ; ill }
{ prefetch_l2 r25 ; addi r15, r16, 5 ; cmovnez r5, r6, r7 }
{ prefetch_l2 r25 ; addi r15, r16, 5 ; shl3add r5, r6, r7 }
{ prefetch_l2 r25 ; addi r5, r6, 5 ; mz r15, r16, r17 }
{ prefetch_l2 r25 ; addx r15, r16, r17 ; fnop }
{ prefetch_l2 r25 ; addx r15, r16, r17 ; tblidxb1 r5, r6 }
{ prefetch_l2 r25 ; addx r5, r6, r7 ; shl2addx r15, r16, r17 }
{ prefetch_l2 r25 ; addxi r15, r16, 5 ; mula_hs_hs r5, r6, r7 }
{ prefetch_l2 r25 ; addxi r5, r6, 5 ; andi r15, r16, 5 }
{ prefetch_l2 r25 ; addxi r5, r6, 5 ; xor r15, r16, r17 }
{ prefetch_l2 r25 ; and r15, r16, r17 ; pcnt r5, r6 }
{ prefetch_l2 r25 ; and r5, r6, r7 ; ill }
{ prefetch_l2 r25 ; andi r15, r16, 5 ; cmovnez r5, r6, r7 }
{ prefetch_l2 r25 ; andi r15, r16, 5 ; shl3add r5, r6, r7 }
{ prefetch_l2 r25 ; andi r5, r6, 5 ; mz r15, r16, r17 }
{ prefetch_l2 r25 ; clz r5, r6 ; jalrp r15 }
{ prefetch_l2 r25 ; cmoveqz r5, r6, r7 ; cmpltsi r15, r16, 5 }
{ prefetch_l2 r25 ; cmovnez r5, r6, r7 ; and r15, r16, r17 }
{ prefetch_l2 r25 ; cmovnez r5, r6, r7 ; subx r15, r16, r17 }
{ prefetch_l2 r25 ; cmpeq r15, r16, r17 ; or r5, r6, r7 }
{ prefetch_l2 r25 ; cmpeq r5, r6, r7 ; fnop }
{ prefetch_l2 r25 ; cmpeqi r15, r16, 5 ; cmoveqz r5, r6, r7 }
{ prefetch_l2 r25 ; cmpeqi r15, r16, 5 ; shl2addx r5, r6, r7 }
{ prefetch_l2 r25 ; cmpeqi r5, r6, 5 ; movei r15, 5 }
{ prefetch_l2 r25 ; cmples r15, r16, r17 ; ctz r5, r6 }
{ prefetch_l2 r25 ; cmples r15, r16, r17 ; tblidxb0 r5, r6 }
{ prefetch_l2 r25 ; cmples r5, r6, r7 ; shl2add r15, r16, r17 }
{ prefetch_l2 r25 ; cmpleu r15, r16, r17 ; mul_lu_lu r5, r6, r7 }
{ prefetch_l2 r25 ; cmpleu r5, r6, r7 ; and r15, r16, r17 }
{ prefetch_l2 r25 ; cmpleu r5, r6, r7 ; subx r15, r16, r17 }
{ prefetch_l2 r25 ; cmplts r15, r16, r17 ; or r5, r6, r7 }
{ prefetch_l2 r25 ; cmplts r5, r6, r7 ; fnop }
{ prefetch_l2 r25 ; cmpltsi r15, r16, 5 ; cmoveqz r5, r6, r7 }
{ prefetch_l2 r25 ; cmpltsi r15, r16, 5 ; shl2addx r5, r6, r7 }
{ prefetch_l2 r25 ; cmpltsi r5, r6, 5 ; movei r15, 5 }
{ prefetch_l2 r25 ; cmpltu r15, r16, r17 ; ctz r5, r6 }
{ prefetch_l2 r25 ; cmpltu r15, r16, r17 ; tblidxb0 r5, r6 }
{ prefetch_l2 r25 ; cmpltu r5, r6, r7 ; shl2add r15, r16, r17 }
{ prefetch_l2 r25 ; cmpne r15, r16, r17 ; mul_lu_lu r5, r6, r7 }
{ prefetch_l2 r25 ; cmpne r5, r6, r7 ; and r15, r16, r17 }
{ prefetch_l2 r25 ; cmpne r5, r6, r7 ; subx r15, r16, r17 }
{ prefetch_l2 r25 ; ctz r5, r6 ; shl3addx r15, r16, r17 }
{ prefetch_l2 r25 ; fnop ; cmpne r5, r6, r7 }
{ prefetch_l2 r25 ; fnop ; rotli r5, r6, 5 }
{ prefetch_l2 r25 ; fsingle_pack1 r5, r6 ; and r15, r16, r17 }
{ prefetch_l2 r25 ; fsingle_pack1 r5, r6 ; subx r15, r16, r17 }
{ prefetch_l2 r25 ; ill ; or r5, r6, r7 }
{ prefetch_l2 r25 ; info 19 ; cmovnez r5, r6, r7 }
{ prefetch_l2 r25 ; info 19 ; mula_lu_lu r5, r6, r7 }
{ prefetch_l2 r25 ; info 19 ; shrui r5, r6, 5 }
{ prefetch_l2 r25 ; jalr r15 ; mula_hs_hs r5, r6, r7 }
{ prefetch_l2 r25 ; jalrp r15 ; andi r5, r6, 5 }
{ prefetch_l2 r25 ; jalrp r15 ; shl1addx r5, r6, r7 }
{ prefetch_l2 r25 ; jr r15 ; move r5, r6 }
{ prefetch_l2 r25 ; jr r15 }
{ prefetch_l2 r25 ; jrp r15 ; revbits r5, r6 }
{ prefetch_l2 r25 ; lnk r15 ; cmpne r5, r6, r7 }
{ prefetch_l2 r25 ; lnk r15 ; subx r5, r6, r7 }
{ prefetch_l2 r25 ; mnz r15, r16, r17 ; mulx r5, r6, r7 }
{ prefetch_l2 r25 ; mnz r5, r6, r7 ; cmplts r15, r16, r17 }
{ prefetch_l2 r25 ; move r15, r16 ; addxi r5, r6, 5 }
{ prefetch_l2 r25 ; move r15, r16 ; shl r5, r6, r7 }
{ prefetch_l2 r25 ; move r5, r6 ; jrp r15 }
{ prefetch_l2 r25 ; movei r15, 5 ; cmplts r5, r6, r7 }
{ prefetch_l2 r25 ; movei r15, 5 ; shru r5, r6, r7 }
{ prefetch_l2 r25 ; movei r5, 5 ; rotli r15, r16, 5 }
{ prefetch_l2 r25 ; mul_hs_hs r5, r6, r7 ; move r15, r16 }
{ prefetch_l2 r25 ; mul_hu_hu r5, r6, r7 ; info 19 }
{ prefetch_l2 r25 ; mul_ls_ls r5, r6, r7 ; cmpleu r15, r16, r17 }
{ prefetch_l2 r25 ; mul_lu_lu r5, r6, r7 ; addx r15, r16, r17 }
{ prefetch_l2 r25 ; mul_lu_lu r5, r6, r7 ; shrui r15, r16, 5 }
{ prefetch_l2 r25 ; mula_hs_hs r5, r6, r7 ; shl2addx r15, r16, r17 }
{ prefetch_l2 r25 ; mula_hu_hu r5, r6, r7 ; or r15, r16, r17 }
{ prefetch_l2 r25 ; mula_ls_ls r5, r6, r7 ; lnk r15 }
{ prefetch_l2 r25 ; mula_lu_lu r5, r6, r7 ; fnop }
{ prefetch_l2 r25 ; mulax r5, r6, r7 ; cmpeqi r15, r16, 5 }
{ prefetch_l2 r25 ; mulx r5, r6, r7 ; add r15, r16, r17 }
{ prefetch_l2 r25 ; mulx r5, r6, r7 ; shrsi r15, r16, 5 }
{ prefetch_l2 r25 ; mz r15, r16, r17 ; mulx r5, r6, r7 }
{ prefetch_l2 r25 ; mz r5, r6, r7 ; cmplts r15, r16, r17 }
{ prefetch_l2 r25 ; nop ; addi r5, r6, 5 }
{ prefetch_l2 r25 ; nop ; move r15, r16 }
{ prefetch_l2 r25 ; nop ; shl3addx r15, r16, r17 }
{ prefetch_l2 r25 ; nor r15, r16, r17 ; ctz r5, r6 }
{ prefetch_l2 r25 ; nor r15, r16, r17 ; tblidxb0 r5, r6 }
{ prefetch_l2 r25 ; nor r5, r6, r7 ; shl2add r15, r16, r17 }
{ prefetch_l2 r25 ; or r15, r16, r17 ; mul_lu_lu r5, r6, r7 }
{ prefetch_l2 r25 ; or r5, r6, r7 ; and r15, r16, r17 }
{ prefetch_l2 r25 ; or r5, r6, r7 ; subx r15, r16, r17 }
{ prefetch_l2 r25 ; pcnt r5, r6 ; shl3addx r15, r16, r17 }
{ prefetch_l2 r25 ; revbits r5, r6 ; rotli r15, r16, 5 }
{ prefetch_l2 r25 ; revbytes r5, r6 ; move r15, r16 }
{ prefetch_l2 r25 ; rotl r15, r16, r17 ; cmpne r5, r6, r7 }
{ prefetch_l2 r25 ; rotl r15, r16, r17 ; subx r5, r6, r7 }
{ prefetch_l2 r25 ; rotl r5, r6, r7 ; shl1addx r15, r16, r17 }
{ prefetch_l2 r25 ; rotli r15, r16, 5 ; mul_ls_ls r5, r6, r7 }
{ prefetch_l2 r25 ; rotli r5, r6, 5 ; addxi r15, r16, 5 }
{ prefetch_l2 r25 ; rotli r5, r6, 5 ; sub r15, r16, r17 }
{ prefetch_l2 r25 ; shl r15, r16, r17 ; nor r5, r6, r7 }
{ prefetch_l2 r25 ; shl r5, r6, r7 ; cmpne r15, r16, r17 }
{ prefetch_l2 r25 ; shl1add r15, r16, r17 ; clz r5, r6 }
{ prefetch_l2 r25 ; shl1add r15, r16, r17 ; shl2add r5, r6, r7 }
{ prefetch_l2 r25 ; shl1add r5, r6, r7 ; move r15, r16 }
{ prefetch_l2 r25 ; shl1addx r15, r16, r17 ; cmpne r5, r6, r7 }
{ prefetch_l2 r25 ; shl1addx r15, r16, r17 ; subx r5, r6, r7 }
{ prefetch_l2 r25 ; shl1addx r5, r6, r7 ; shl1addx r15, r16, r17 }
{ prefetch_l2 r25 ; shl2add r15, r16, r17 ; mul_ls_ls r5, r6, r7 }
{ prefetch_l2 r25 ; shl2add r5, r6, r7 ; addxi r15, r16, 5 }
{ prefetch_l2 r25 ; shl2add r5, r6, r7 ; sub r15, r16, r17 }
{ prefetch_l2 r25 ; shl2addx r15, r16, r17 ; nor r5, r6, r7 }
{ prefetch_l2 r25 ; shl2addx r5, r6, r7 ; cmpne r15, r16, r17 }
{ prefetch_l2 r25 ; shl3add r15, r16, r17 ; clz r5, r6 }
{ prefetch_l2 r25 ; shl3add r15, r16, r17 ; shl2add r5, r6, r7 }
{ prefetch_l2 r25 ; shl3add r5, r6, r7 ; move r15, r16 }
{ prefetch_l2 r25 ; shl3addx r15, r16, r17 ; cmpne r5, r6, r7 }
{ prefetch_l2 r25 ; shl3addx r15, r16, r17 ; subx r5, r6, r7 }
{ prefetch_l2 r25 ; shl3addx r5, r6, r7 ; shl1addx r15, r16, r17 }
{ prefetch_l2 r25 ; shli r15, r16, 5 ; mul_ls_ls r5, r6, r7 }
{ prefetch_l2 r25 ; shli r5, r6, 5 ; addxi r15, r16, 5 }
{ prefetch_l2 r25 ; shli r5, r6, 5 ; sub r15, r16, r17 }
{ prefetch_l2 r25 ; shrs r15, r16, r17 ; nor r5, r6, r7 }
{ prefetch_l2 r25 ; shrs r5, r6, r7 ; cmpne r15, r16, r17 }
{ prefetch_l2 r25 ; shrsi r15, r16, 5 ; clz r5, r6 }
{ prefetch_l2 r25 ; shrsi r15, r16, 5 ; shl2add r5, r6, r7 }
{ prefetch_l2 r25 ; shrsi r5, r6, 5 ; move r15, r16 }
{ prefetch_l2 r25 ; shru r15, r16, r17 ; cmpne r5, r6, r7 }
{ prefetch_l2 r25 ; shru r15, r16, r17 ; subx r5, r6, r7 }
{ prefetch_l2 r25 ; shru r5, r6, r7 ; shl1addx r15, r16, r17 }
{ prefetch_l2 r25 ; shrui r15, r16, 5 ; mul_ls_ls r5, r6, r7 }
{ prefetch_l2 r25 ; shrui r5, r6, 5 ; addxi r15, r16, 5 }
{ prefetch_l2 r25 ; shrui r5, r6, 5 ; sub r15, r16, r17 }
{ prefetch_l2 r25 ; sub r15, r16, r17 ; nor r5, r6, r7 }
{ prefetch_l2 r25 ; sub r5, r6, r7 ; cmpne r15, r16, r17 }
{ prefetch_l2 r25 ; subx r15, r16, r17 ; clz r5, r6 }
{ prefetch_l2 r25 ; subx r15, r16, r17 ; shl2add r5, r6, r7 }
{ prefetch_l2 r25 ; subx r5, r6, r7 ; move r15, r16 }
{ prefetch_l2 r25 ; tblidxb0 r5, r6 ; info 19 }
{ prefetch_l2 r25 ; tblidxb1 r5, r6 ; cmpleu r15, r16, r17 }
{ prefetch_l2 r25 ; tblidxb2 r5, r6 ; addx r15, r16, r17 }
{ prefetch_l2 r25 ; tblidxb2 r5, r6 ; shrui r15, r16, 5 }
{ prefetch_l2 r25 ; tblidxb3 r5, r6 ; shl2addx r15, r16, r17 }
{ prefetch_l2 r25 ; xor r15, r16, r17 ; mula_hs_hs r5, r6, r7 }
{ prefetch_l2 r25 ; xor r5, r6, r7 ; andi r15, r16, 5 }
{ prefetch_l2 r25 ; xor r5, r6, r7 ; xor r15, r16, r17 }
{ prefetch_l2_fault r15 ; fdouble_add_flags r5, r6, r7 }
{ prefetch_l2_fault r15 ; mula_ls_ls r5, r6, r7 }
{ prefetch_l2_fault r15 ; v1add r5, r6, r7 }
{ prefetch_l2_fault r15 ; v1shrsi r5, r6, 5 }
{ prefetch_l2_fault r15 ; v2shli r5, r6, 5 }
{ prefetch_l2_fault r25 ; add r15, r16, r17 ; fsingle_pack1 r5, r6 }
{ prefetch_l2_fault r25 ; add r15, r16, r17 ; tblidxb2 r5, r6 }
{ prefetch_l2_fault r25 ; add r5, r6, r7 ; shl3add r15, r16, r17 }
{ prefetch_l2_fault r25 ; addi r15, r16, 5 ; mula_hu_hu r5, r6, r7 }
{ prefetch_l2_fault r25 ; addi r5, r6, 5 ; cmpeq r15, r16, r17 }
{ prefetch_l2_fault r25 ; addi r5, r6, 5 }
{ prefetch_l2_fault r25 ; addx r15, r16, r17 ; revbits r5, r6 }
{ prefetch_l2_fault r25 ; addx r5, r6, r7 ; info 19 }
{ prefetch_l2_fault r25 ; addxi r15, r16, 5 ; cmpeq r5, r6, r7 }
{ prefetch_l2_fault r25 ; addxi r15, r16, 5 ; shl3addx r5, r6, r7 }
{ prefetch_l2_fault r25 ; addxi r5, r6, 5 ; nop }
{ prefetch_l2_fault r25 ; and r15, r16, r17 ; fsingle_pack1 r5, r6 }
{ prefetch_l2_fault r25 ; and r15, r16, r17 ; tblidxb2 r5, r6 }
{ prefetch_l2_fault r25 ; and r5, r6, r7 ; shl3add r15, r16, r17 }
{ prefetch_l2_fault r25 ; andi r15, r16, 5 ; mula_hu_hu r5, r6, r7 }
{ prefetch_l2_fault r25 ; andi r5, r6, 5 ; cmpeq r15, r16, r17 }
{ prefetch_l2_fault r25 ; andi r5, r6, 5 }
{ prefetch_l2_fault r25 ; clz r5, r6 ; shrs r15, r16, r17 }
{ prefetch_l2_fault r25 ; cmoveqz r5, r6, r7 ; shl1add r15, r16, r17 }
{ prefetch_l2_fault r25 ; cmovnez r5, r6, r7 ; mz r15, r16, r17 }
{ prefetch_l2_fault r25 ; cmpeq r15, r16, r17 ; fnop }
{ prefetch_l2_fault r25 ; cmpeq r15, r16, r17 ; tblidxb1 r5, r6 }
{ prefetch_l2_fault r25 ; cmpeq r5, r6, r7 ; shl2addx r15, r16, r17 }
{ prefetch_l2_fault r25 ; cmpeqi r15, r16, 5 ; mula_hs_hs r5, r6, r7 }
{ prefetch_l2_fault r25 ; cmpeqi r5, r6, 5 ; andi r15, r16, 5 }
{ prefetch_l2_fault r25 ; cmpeqi r5, r6, 5 ; xor r15, r16, r17 }
{ prefetch_l2_fault r25 ; cmples r15, r16, r17 ; pcnt r5, r6 }
{ prefetch_l2_fault r25 ; cmples r5, r6, r7 ; ill }
{ prefetch_l2_fault r25 ; cmpleu r15, r16, r17 ; cmovnez r5, r6, r7 }
{ prefetch_l2_fault r25 ; cmpleu r15, r16, r17 ; shl3add r5, r6, r7 }
{ prefetch_l2_fault r25 ; cmpleu r5, r6, r7 ; mz r15, r16, r17 }
{ prefetch_l2_fault r25 ; cmplts r15, r16, r17 ; fnop }
{ prefetch_l2_fault r25 ; cmplts r15, r16, r17 ; tblidxb1 r5, r6 }
{ prefetch_l2_fault r25 ; cmplts r5, r6, r7 ; shl2addx r15, r16, r17 }
{ prefetch_l2_fault r25 ; cmpltsi r15, r16, 5 ; mula_hs_hs r5, r6, r7 }
{ prefetch_l2_fault r25 ; cmpltsi r5, r6, 5 ; andi r15, r16, 5 }
{ prefetch_l2_fault r25 ; cmpltsi r5, r6, 5 ; xor r15, r16, r17 }
{ prefetch_l2_fault r25 ; cmpltu r15, r16, r17 ; pcnt r5, r6 }
{ prefetch_l2_fault r25 ; cmpltu r5, r6, r7 ; ill }
{ prefetch_l2_fault r25 ; cmpne r15, r16, r17 ; cmovnez r5, r6, r7 }
{ prefetch_l2_fault r25 ; cmpne r15, r16, r17 ; shl3add r5, r6, r7 }
{ prefetch_l2_fault r25 ; cmpne r5, r6, r7 ; mz r15, r16, r17 }
{ prefetch_l2_fault r25 ; ctz r5, r6 ; jalrp r15 }
{ prefetch_l2_fault r25 ; fnop ; andi r5, r6, 5 }
{ prefetch_l2_fault r25 ; fnop ; mula_hs_hs r5, r6, r7 }
{ prefetch_l2_fault r25 ; fnop ; shru r15, r16, r17 }
{ prefetch_l2_fault r25 ; fsingle_pack1 r5, r6 ; mz r15, r16, r17 }
{ prefetch_l2_fault r25 ; ill ; fnop }
{ prefetch_l2_fault r25 ; ill ; tblidxb1 r5, r6 }
{ prefetch_l2_fault r25 ; info 19 ; info 19 }
{ prefetch_l2_fault r25 ; info 19 ; shl1addx r15, r16, r17 }
{ prefetch_l2_fault r25 ; jalr r15 ; cmpeq r5, r6, r7 }
{ prefetch_l2_fault r25 ; jalr r15 ; shl3addx r5, r6, r7 }
{ prefetch_l2_fault r25 ; jalrp r15 ; mul_ls_ls r5, r6, r7 }
{ prefetch_l2_fault r25 ; jr r15 ; addxi r5, r6, 5 }
{ prefetch_l2_fault r25 ; jr r15 ; shl r5, r6, r7 }
{ prefetch_l2_fault r25 ; jrp r15 ; info 19 }
{ prefetch_l2_fault r25 ; jrp r15 ; tblidxb3 r5, r6 }
{ prefetch_l2_fault r25 ; lnk r15 ; or r5, r6, r7 }
{ prefetch_l2_fault r25 ; mnz r15, r16, r17 ; cmpltsi r5, r6, 5 }
{ prefetch_l2_fault r25 ; mnz r15, r16, r17 ; shrui r5, r6, 5 }
{ prefetch_l2_fault r25 ; mnz r5, r6, r7 ; shl r15, r16, r17 }
{ prefetch_l2_fault r25 ; move r15, r16 ; mul_hs_hs r5, r6, r7 }
{ prefetch_l2_fault r25 ; move r5, r6 ; addi r15, r16, 5 }
{ prefetch_l2_fault r25 ; move r5, r6 ; shru r15, r16, r17 }
{ prefetch_l2_fault r25 ; movei r15, 5 ; mz r5, r6, r7 }
{ prefetch_l2_fault r25 ; movei r5, 5 ; cmpltsi r15, r16, 5 }
{ prefetch_l2_fault r25 ; mul_hs_hs r5, r6, r7 ; and r15, r16, r17 }
{ prefetch_l2_fault r25 ; mul_hs_hs r5, r6, r7 ; subx r15, r16, r17 }
{ prefetch_l2_fault r25 ; mul_hu_hu r5, r6, r7 ; shl3addx r15, r16, r17 }
{ prefetch_l2_fault r25 ; mul_ls_ls r5, r6, r7 ; rotli r15, r16, 5 }
{ prefetch_l2_fault r25 ; mul_lu_lu r5, r6, r7 ; move r15, r16 }
{ prefetch_l2_fault r25 ; mula_hs_hs r5, r6, r7 ; info 19 }
{ prefetch_l2_fault r25 ; mula_hu_hu r5, r6, r7 ; cmpleu r15, r16, r17 }
{ prefetch_l2_fault r25 ; mula_ls_ls r5, r6, r7 ; addx r15, r16, r17 }
{ prefetch_l2_fault r25 ; mula_ls_ls r5, r6, r7 ; shrui r15, r16, 5 }
{ prefetch_l2_fault r25 ; mula_lu_lu r5, r6, r7 ; shl2addx r15, r16, r17 }
{ prefetch_l2_fault r25 ; mulax r5, r6, r7 ; or r15, r16, r17 }
{ prefetch_l2_fault r25 ; mulx r5, r6, r7 ; lnk r15 }
{ prefetch_l2_fault r25 ; mz r15, r16, r17 ; cmpltsi r5, r6, 5 }
{ prefetch_l2_fault r25 ; mz r15, r16, r17 ; shrui r5, r6, 5 }
{ prefetch_l2_fault r25 ; mz r5, r6, r7 ; shl r15, r16, r17 }
{ prefetch_l2_fault r25 ; nop ; cmplts r5, r6, r7 }
{ prefetch_l2_fault r25 ; nop ; pcnt r5, r6 }
{ prefetch_l2_fault r25 ; nop ; xor r5, r6, r7 }
{ prefetch_l2_fault r25 ; nor r15, r16, r17 ; pcnt r5, r6 }
{ prefetch_l2_fault r25 ; nor r5, r6, r7 ; ill }
{ prefetch_l2_fault r25 ; or r15, r16, r17 ; cmovnez r5, r6, r7 }
{ prefetch_l2_fault r25 ; or r15, r16, r17 ; shl3add r5, r6, r7 }
{ prefetch_l2_fault r25 ; or r5, r6, r7 ; mz r15, r16, r17 }
{ prefetch_l2_fault r25 ; pcnt r5, r6 ; jalrp r15 }
{ prefetch_l2_fault r25 ; revbits r5, r6 ; cmpltsi r15, r16, 5 }
{ prefetch_l2_fault r25 ; revbytes r5, r6 ; and r15, r16, r17 }
{ prefetch_l2_fault r25 ; revbytes r5, r6 ; subx r15, r16, r17 }
{ prefetch_l2_fault r25 ; rotl r15, r16, r17 ; or r5, r6, r7 }
{ prefetch_l2_fault r25 ; rotl r5, r6, r7 ; fnop }
{ prefetch_l2_fault r25 ; rotli r15, r16, 5 ; cmoveqz r5, r6, r7 }
{ prefetch_l2_fault r25 ; rotli r15, r16, 5 ; shl2addx r5, r6, r7 }
{ prefetch_l2_fault r25 ; rotli r5, r6, 5 ; movei r15, 5 }
{ prefetch_l2_fault r25 ; shl r15, r16, r17 ; ctz r5, r6 }
{ prefetch_l2_fault r25 ; shl r15, r16, r17 ; tblidxb0 r5, r6 }
{ prefetch_l2_fault r25 ; shl r5, r6, r7 ; shl2add r15, r16, r17 }
{ prefetch_l2_fault r25 ; shl1add r15, r16, r17 ; mul_lu_lu r5, r6, r7 }
{ prefetch_l2_fault r25 ; shl1add r5, r6, r7 ; and r15, r16, r17 }
{ prefetch_l2_fault r25 ; shl1add r5, r6, r7 ; subx r15, r16, r17 }
{ prefetch_l2_fault r25 ; shl1addx r15, r16, r17 ; or r5, r6, r7 }
{ prefetch_l2_fault r25 ; shl1addx r5, r6, r7 ; fnop }
{ prefetch_l2_fault r25 ; shl2add r15, r16, r17 ; cmoveqz r5, r6, r7 }
{ prefetch_l2_fault r25 ; shl2add r15, r16, r17 ; shl2addx r5, r6, r7 }
{ prefetch_l2_fault r25 ; shl2add r5, r6, r7 ; movei r15, 5 }
{ prefetch_l2_fault r25 ; shl2addx r15, r16, r17 ; ctz r5, r6 }
{ prefetch_l2_fault r25 ; shl2addx r15, r16, r17 ; tblidxb0 r5, r6 }
{ prefetch_l2_fault r25 ; shl2addx r5, r6, r7 ; shl2add r15, r16, r17 }
{ prefetch_l2_fault r25 ; shl3add r15, r16, r17 ; mul_lu_lu r5, r6, r7 }
{ prefetch_l2_fault r25 ; shl3add r5, r6, r7 ; and r15, r16, r17 }
{ prefetch_l2_fault r25 ; shl3add r5, r6, r7 ; subx r15, r16, r17 }
{ prefetch_l2_fault r25 ; shl3addx r15, r16, r17 ; or r5, r6, r7 }
{ prefetch_l2_fault r25 ; shl3addx r5, r6, r7 ; fnop }
{ prefetch_l2_fault r25 ; shli r15, r16, 5 ; cmoveqz r5, r6, r7 }
{ prefetch_l2_fault r25 ; shli r15, r16, 5 ; shl2addx r5, r6, r7 }
{ prefetch_l2_fault r25 ; shli r5, r6, 5 ; movei r15, 5 }
{ prefetch_l2_fault r25 ; shrs r15, r16, r17 ; ctz r5, r6 }
{ prefetch_l2_fault r25 ; shrs r15, r16, r17 ; tblidxb0 r5, r6 }
{ prefetch_l2_fault r25 ; shrs r5, r6, r7 ; shl2add r15, r16, r17 }
{ prefetch_l2_fault r25 ; shrsi r15, r16, 5 ; mul_lu_lu r5, r6, r7 }
{ prefetch_l2_fault r25 ; shrsi r5, r6, 5 ; and r15, r16, r17 }
{ prefetch_l2_fault r25 ; shrsi r5, r6, 5 ; subx r15, r16, r17 }
{ prefetch_l2_fault r25 ; shru r15, r16, r17 ; or r5, r6, r7 }
{ prefetch_l2_fault r25 ; shru r5, r6, r7 ; fnop }
{ prefetch_l2_fault r25 ; shrui r15, r16, 5 ; cmoveqz r5, r6, r7 }
{ prefetch_l2_fault r25 ; shrui r15, r16, 5 ; shl2addx r5, r6, r7 }
{ prefetch_l2_fault r25 ; shrui r5, r6, 5 ; movei r15, 5 }
{ prefetch_l2_fault r25 ; sub r15, r16, r17 ; ctz r5, r6 }
{ prefetch_l2_fault r25 ; sub r15, r16, r17 ; tblidxb0 r5, r6 }
{ prefetch_l2_fault r25 ; sub r5, r6, r7 ; shl2add r15, r16, r17 }
{ prefetch_l2_fault r25 ; subx r15, r16, r17 ; mul_lu_lu r5, r6, r7 }
{ prefetch_l2_fault r25 ; subx r5, r6, r7 ; and r15, r16, r17 }
{ prefetch_l2_fault r25 ; subx r5, r6, r7 ; subx r15, r16, r17 }
{ prefetch_l2_fault r25 ; tblidxb0 r5, r6 ; shl3addx r15, r16, r17 }
{ prefetch_l2_fault r25 ; tblidxb1 r5, r6 ; rotli r15, r16, 5 }
{ prefetch_l2_fault r25 ; tblidxb2 r5, r6 ; move r15, r16 }
{ prefetch_l2_fault r25 ; tblidxb3 r5, r6 ; info 19 }
{ prefetch_l2_fault r25 ; xor r15, r16, r17 ; cmpeq r5, r6, r7 }
{ prefetch_l2_fault r25 ; xor r15, r16, r17 ; shl3addx r5, r6, r7 }
{ prefetch_l2_fault r25 ; xor r5, r6, r7 ; nop }
{ prefetch_l3 r15 ; cmplts r5, r6, r7 }
{ prefetch_l3 r15 ; movei r5, 5 }
{ prefetch_l3 r15 ; shl3add r5, r6, r7 }
{ prefetch_l3 r15 ; v1dotpua r5, r6, r7 }
{ prefetch_l3 r15 ; v2int_h r5, r6, r7 }
{ prefetch_l3 r25 ; add r15, r16, r17 ; add r5, r6, r7 }
{ prefetch_l3 r25 ; add r15, r16, r17 ; revbytes r5, r6 }
{ prefetch_l3 r25 ; add r5, r6, r7 ; jalr r15 }
{ prefetch_l3 r25 ; addi r15, r16, 5 ; cmpeqi r5, r6, 5 }
{ prefetch_l3 r25 ; addi r15, r16, 5 ; shli r5, r6, 5 }
{ prefetch_l3 r25 ; addi r5, r6, 5 ; nor r15, r16, r17 }
{ prefetch_l3 r25 ; addx r15, r16, r17 ; info 19 }
{ prefetch_l3 r25 ; addx r15, r16, r17 ; tblidxb3 r5, r6 }
{ prefetch_l3 r25 ; addx r5, r6, r7 ; shl3addx r15, r16, r17 }
{ prefetch_l3 r25 ; addxi r15, r16, 5 ; mula_ls_ls r5, r6, r7 }
{ prefetch_l3 r25 ; addxi r5, r6, 5 ; cmpeqi r15, r16, 5 }
{ prefetch_l3 r25 ; and r15, r16, r17 ; add r5, r6, r7 }
{ prefetch_l3 r25 ; and r15, r16, r17 ; revbytes r5, r6 }
{ prefetch_l3 r25 ; and r5, r6, r7 ; jalr r15 }
{ prefetch_l3 r25 ; andi r15, r16, 5 ; cmpeqi r5, r6, 5 }
{ prefetch_l3 r25 ; andi r15, r16, 5 ; shli r5, r6, 5 }
{ prefetch_l3 r25 ; andi r5, r6, 5 ; nor r15, r16, r17 }
{ prefetch_l3 r25 ; clz r5, r6 ; jrp r15 }
{ prefetch_l3 r25 ; cmoveqz r5, r6, r7 ; cmpne r15, r16, r17 }
{ prefetch_l3 r25 ; cmovnez r5, r6, r7 ; cmpeq r15, r16, r17 }
{ prefetch_l3 r25 ; cmovnez r5, r6, r7 }
{ prefetch_l3 r25 ; cmpeq r15, r16, r17 ; revbits r5, r6 }
{ prefetch_l3 r25 ; cmpeq r5, r6, r7 ; info 19 }
{ prefetch_l3 r25 ; cmpeqi r15, r16, 5 ; cmpeq r5, r6, r7 }
{ prefetch_l3 r25 ; cmpeqi r15, r16, 5 ; shl3addx r5, r6, r7 }
{ prefetch_l3 r25 ; cmpeqi r5, r6, 5 ; nop }
{ prefetch_l3 r25 ; cmples r15, r16, r17 ; fsingle_pack1 r5, r6 }
{ prefetch_l3 r25 ; cmples r15, r16, r17 ; tblidxb2 r5, r6 }
{ prefetch_l3 r25 ; cmples r5, r6, r7 ; shl3add r15, r16, r17 }
{ prefetch_l3 r25 ; cmpleu r15, r16, r17 ; mula_hu_hu r5, r6, r7 }
{ prefetch_l3 r25 ; cmpleu r5, r6, r7 ; cmpeq r15, r16, r17 }
{ prefetch_l3 r25 ; cmpleu r5, r6, r7 }
{ prefetch_l3 r25 ; cmplts r15, r16, r17 ; revbits r5, r6 }
{ prefetch_l3 r25 ; cmplts r5, r6, r7 ; info 19 }
{ prefetch_l3 r25 ; cmpltsi r15, r16, 5 ; cmpeq r5, r6, r7 }
{ prefetch_l3 r25 ; cmpltsi r15, r16, 5 ; shl3addx r5, r6, r7 }
{ prefetch_l3 r25 ; cmpltsi r5, r6, 5 ; nop }
{ prefetch_l3 r25 ; cmpltu r15, r16, r17 ; fsingle_pack1 r5, r6 }
{ prefetch_l3 r25 ; cmpltu r15, r16, r17 ; tblidxb2 r5, r6 }
{ prefetch_l3 r25 ; cmpltu r5, r6, r7 ; shl3add r15, r16, r17 }
{ prefetch_l3 r25 ; cmpne r15, r16, r17 ; mula_hu_hu r5, r6, r7 }
{ prefetch_l3 r25 ; cmpne r5, r6, r7 ; cmpeq r15, r16, r17 }
{ prefetch_l3 r25 ; cmpne r5, r6, r7 }
{ prefetch_l3 r25 ; ctz r5, r6 ; shrs r15, r16, r17 }
{ prefetch_l3 r25 ; fnop ; fnop }
{ prefetch_l3 r25 ; fnop ; shl r5, r6, r7 }
{ prefetch_l3 r25 ; fsingle_pack1 r5, r6 ; cmpeq r15, r16, r17 }
{ prefetch_l3 r25 ; fsingle_pack1 r5, r6 }
{ prefetch_l3 r25 ; ill ; revbits r5, r6 }
{ prefetch_l3 r25 ; info 19 ; cmpeq r5, r6, r7 }
{ prefetch_l3 r25 ; info 19 ; mulx r5, r6, r7 }
{ prefetch_l3 r25 ; info 19 ; sub r5, r6, r7 }
{ prefetch_l3 r25 ; jalr r15 ; mula_ls_ls r5, r6, r7 }
{ prefetch_l3 r25 ; jalrp r15 ; cmoveqz r5, r6, r7 }
{ prefetch_l3 r25 ; jalrp r15 ; shl2addx r5, r6, r7 }
{ prefetch_l3 r25 ; jr r15 ; mul_hs_hs r5, r6, r7 }
{ prefetch_l3 r25 ; jrp r15 ; addi r5, r6, 5 }
{ prefetch_l3 r25 ; jrp r15 ; rotl r5, r6, r7 }
{ prefetch_l3 r25 ; lnk r15 ; fnop }
{ prefetch_l3 r25 ; lnk r15 ; tblidxb1 r5, r6 }
{ prefetch_l3 r25 ; mnz r15, r16, r17 ; nop }
{ prefetch_l3 r25 ; mnz r5, r6, r7 ; cmpltu r15, r16, r17 }
{ prefetch_l3 r25 ; move r15, r16 ; andi r5, r6, 5 }
{ prefetch_l3 r25 ; move r15, r16 ; shl1addx r5, r6, r7 }
{ prefetch_l3 r25 ; move r5, r6 ; mnz r15, r16, r17 }
{ prefetch_l3 r25 ; movei r15, 5 ; cmpltu r5, r6, r7 }
{ prefetch_l3 r25 ; movei r15, 5 ; sub r5, r6, r7 }
{ prefetch_l3 r25 ; movei r5, 5 ; shl1add r15, r16, r17 }
{ prefetch_l3 r25 ; mul_hs_hs r5, r6, r7 ; mz r15, r16, r17 }
{ prefetch_l3 r25 ; mul_hu_hu r5, r6, r7 ; jalrp r15 }
{ prefetch_l3 r25 ; mul_ls_ls r5, r6, r7 ; cmpltsi r15, r16, 5 }
{ prefetch_l3 r25 ; mul_lu_lu r5, r6, r7 ; and r15, r16, r17 }
{ prefetch_l3 r25 ; mul_lu_lu r5, r6, r7 ; subx r15, r16, r17 }
{ prefetch_l3 r25 ; mula_hs_hs r5, r6, r7 ; shl3addx r15, r16, r17 }
{ prefetch_l3 r25 ; mula_hu_hu r5, r6, r7 ; rotli r15, r16, 5 }
{ prefetch_l3 r25 ; mula_ls_ls r5, r6, r7 ; move r15, r16 }
{ prefetch_l3 r25 ; mula_lu_lu r5, r6, r7 ; info 19 }
{ prefetch_l3 r25 ; mulax r5, r6, r7 ; cmpleu r15, r16, r17 }
{ prefetch_l3 r25 ; mulx r5, r6, r7 ; addx r15, r16, r17 }
{ prefetch_l3 r25 ; mulx r5, r6, r7 ; shrui r15, r16, 5 }
{ prefetch_l3 r25 ; mz r15, r16, r17 ; nop }
{ prefetch_l3 r25 ; mz r5, r6, r7 ; cmpltu r15, r16, r17 }
{ prefetch_l3 r25 ; nop ; addx r5, r6, r7 }
{ prefetch_l3 r25 ; nop ; movei r15, 5 }
{ prefetch_l3 r25 ; nop ; shli r15, r16, 5 }
{ prefetch_l3 r25 ; nor r15, r16, r17 ; fsingle_pack1 r5, r6 }
{ prefetch_l3 r25 ; nor r15, r16, r17 ; tblidxb2 r5, r6 }
{ prefetch_l3 r25 ; nor r5, r6, r7 ; shl3add r15, r16, r17 }
{ prefetch_l3 r25 ; or r15, r16, r17 ; mula_hu_hu r5, r6, r7 }
{ prefetch_l3 r25 ; or r5, r6, r7 ; cmpeq r15, r16, r17 }
{ prefetch_l3 r25 ; or r5, r6, r7 }
{ prefetch_l3 r25 ; pcnt r5, r6 ; shrs r15, r16, r17 }
{ prefetch_l3 r25 ; revbits r5, r6 ; shl1add r15, r16, r17 }
{ prefetch_l3 r25 ; revbytes r5, r6 ; mz r15, r16, r17 }
{ prefetch_l3 r25 ; rotl r15, r16, r17 ; fnop }
{ prefetch_l3 r25 ; rotl r15, r16, r17 ; tblidxb1 r5, r6 }
{ prefetch_l3 r25 ; rotl r5, r6, r7 ; shl2addx r15, r16, r17 }
{ prefetch_l3 r25 ; rotli r15, r16, 5 ; mula_hs_hs r5, r6, r7 }
{ prefetch_l3 r25 ; rotli r5, r6, 5 ; andi r15, r16, 5 }
{ prefetch_l3 r25 ; rotli r5, r6, 5 ; xor r15, r16, r17 }
{ prefetch_l3 r25 ; shl r15, r16, r17 ; pcnt r5, r6 }
{ prefetch_l3 r25 ; shl r5, r6, r7 ; ill }
{ prefetch_l3 r25 ; shl1add r15, r16, r17 ; cmovnez r5, r6, r7 }
{ prefetch_l3 r25 ; shl1add r15, r16, r17 ; shl3add r5, r6, r7 }
{ prefetch_l3 r25 ; shl1add r5, r6, r7 ; mz r15, r16, r17 }
{ prefetch_l3 r25 ; shl1addx r15, r16, r17 ; fnop }
{ prefetch_l3 r25 ; shl1addx r15, r16, r17 ; tblidxb1 r5, r6 }
{ prefetch_l3 r25 ; shl1addx r5, r6, r7 ; shl2addx r15, r16, r17 }
{ prefetch_l3 r25 ; shl2add r15, r16, r17 ; mula_hs_hs r5, r6, r7 }
{ prefetch_l3 r25 ; shl2add r5, r6, r7 ; andi r15, r16, 5 }
{ prefetch_l3 r25 ; shl2add r5, r6, r7 ; xor r15, r16, r17 }
{ prefetch_l3 r25 ; shl2addx r15, r16, r17 ; pcnt r5, r6 }
{ prefetch_l3 r25 ; shl2addx r5, r6, r7 ; ill }
{ prefetch_l3 r25 ; shl3add r15, r16, r17 ; cmovnez r5, r6, r7 }
{ prefetch_l3 r25 ; shl3add r15, r16, r17 ; shl3add r5, r6, r7 }
{ prefetch_l3 r25 ; shl3add r5, r6, r7 ; mz r15, r16, r17 }
{ prefetch_l3 r25 ; shl3addx r15, r16, r17 ; fnop }
{ prefetch_l3 r25 ; shl3addx r15, r16, r17 ; tblidxb1 r5, r6 }
{ prefetch_l3 r25 ; shl3addx r5, r6, r7 ; shl2addx r15, r16, r17 }
{ prefetch_l3 r25 ; shli r15, r16, 5 ; mula_hs_hs r5, r6, r7 }
{ prefetch_l3 r25 ; shli r5, r6, 5 ; andi r15, r16, 5 }
{ prefetch_l3 r25 ; shli r5, r6, 5 ; xor r15, r16, r17 }
{ prefetch_l3 r25 ; shrs r15, r16, r17 ; pcnt r5, r6 }
{ prefetch_l3 r25 ; shrs r5, r6, r7 ; ill }
{ prefetch_l3 r25 ; shrsi r15, r16, 5 ; cmovnez r5, r6, r7 }
{ prefetch_l3 r25 ; shrsi r15, r16, 5 ; shl3add r5, r6, r7 }
{ prefetch_l3 r25 ; shrsi r5, r6, 5 ; mz r15, r16, r17 }
{ prefetch_l3 r25 ; shru r15, r16, r17 ; fnop }
{ prefetch_l3 r25 ; shru r15, r16, r17 ; tblidxb1 r5, r6 }
{ prefetch_l3 r25 ; shru r5, r6, r7 ; shl2addx r15, r16, r17 }
{ prefetch_l3 r25 ; shrui r15, r16, 5 ; mula_hs_hs r5, r6, r7 }
{ prefetch_l3 r25 ; shrui r5, r6, 5 ; andi r15, r16, 5 }
{ prefetch_l3 r25 ; shrui r5, r6, 5 ; xor r15, r16, r17 }
{ prefetch_l3 r25 ; sub r15, r16, r17 ; pcnt r5, r6 }
{ prefetch_l3 r25 ; sub r5, r6, r7 ; ill }
{ prefetch_l3 r25 ; subx r15, r16, r17 ; cmovnez r5, r6, r7 }
{ prefetch_l3 r25 ; subx r15, r16, r17 ; shl3add r5, r6, r7 }
{ prefetch_l3 r25 ; subx r5, r6, r7 ; mz r15, r16, r17 }
{ prefetch_l3 r25 ; tblidxb0 r5, r6 ; jalrp r15 }
{ prefetch_l3 r25 ; tblidxb1 r5, r6 ; cmpltsi r15, r16, 5 }
{ prefetch_l3 r25 ; tblidxb2 r5, r6 ; and r15, r16, r17 }
{ prefetch_l3 r25 ; tblidxb2 r5, r6 ; subx r15, r16, r17 }
{ prefetch_l3 r25 ; tblidxb3 r5, r6 ; shl3addx r15, r16, r17 }
{ prefetch_l3 r25 ; xor r15, r16, r17 ; mula_ls_ls r5, r6, r7 }
{ prefetch_l3 r25 ; xor r5, r6, r7 ; cmpeqi r15, r16, 5 }
{ prefetch_l3_fault r15 ; add r5, r6, r7 }
{ prefetch_l3_fault r15 ; fdouble_mul_flags r5, r6, r7 }
{ prefetch_l3_fault r15 ; mula_lu_lu r5, r6, r7 }
{ prefetch_l3_fault r15 ; v1adduc r5, r6, r7 }
{ prefetch_l3_fault r15 ; v1shrui r5, r6, 5 }
{ prefetch_l3_fault r15 ; v2shrs r5, r6, r7 }
{ prefetch_l3_fault r25 ; add r15, r16, r17 ; mnz r5, r6, r7 }
{ prefetch_l3_fault r25 ; add r15, r16, r17 ; xor r5, r6, r7 }
{ prefetch_l3_fault r25 ; add r5, r6, r7 ; shli r15, r16, 5 }
{ prefetch_l3_fault r25 ; addi r15, r16, 5 ; mula_lu_lu r5, r6, r7 }
{ prefetch_l3_fault r25 ; addi r5, r6, 5 ; cmples r15, r16, r17 }
{ prefetch_l3_fault r25 ; addx r15, r16, r17 ; addi r5, r6, 5 }
{ prefetch_l3_fault r25 ; addx r15, r16, r17 ; rotl r5, r6, r7 }
{ prefetch_l3_fault r25 ; addx r5, r6, r7 ; jalrp r15 }
{ prefetch_l3_fault r25 ; addxi r15, r16, 5 ; cmples r5, r6, r7 }
{ prefetch_l3_fault r25 ; addxi r15, r16, 5 ; shrs r5, r6, r7 }
{ prefetch_l3_fault r25 ; addxi r5, r6, 5 ; or r15, r16, r17 }
{ prefetch_l3_fault r25 ; and r15, r16, r17 ; mnz r5, r6, r7 }
{ prefetch_l3_fault r25 ; and r15, r16, r17 ; xor r5, r6, r7 }
{ prefetch_l3_fault r25 ; and r5, r6, r7 ; shli r15, r16, 5 }
{ prefetch_l3_fault r25 ; andi r15, r16, 5 ; mula_lu_lu r5, r6, r7 }
{ prefetch_l3_fault r25 ; andi r5, r6, 5 ; cmples r15, r16, r17 }
{ prefetch_l3_fault r25 ; clz r5, r6 ; addi r15, r16, 5 }
{ prefetch_l3_fault r25 ; clz r5, r6 ; shru r15, r16, r17 }
{ prefetch_l3_fault r25 ; cmoveqz r5, r6, r7 ; shl2add r15, r16, r17 }
{ prefetch_l3_fault r25 ; cmovnez r5, r6, r7 ; nor r15, r16, r17 }
{ prefetch_l3_fault r25 ; cmpeq r15, r16, r17 ; info 19 }
{ prefetch_l3_fault r25 ; cmpeq r15, r16, r17 ; tblidxb3 r5, r6 }
{ prefetch_l3_fault r25 ; cmpeq r5, r6, r7 ; shl3addx r15, r16, r17 }
{ prefetch_l3_fault r25 ; cmpeqi r15, r16, 5 ; mula_ls_ls r5, r6, r7 }
{ prefetch_l3_fault r25 ; cmpeqi r5, r6, 5 ; cmpeqi r15, r16, 5 }
{ prefetch_l3_fault r25 ; cmples r15, r16, r17 ; add r5, r6, r7 }
{ prefetch_l3_fault r25 ; cmples r15, r16, r17 ; revbytes r5, r6 }
{ prefetch_l3_fault r25 ; cmples r5, r6, r7 ; jalr r15 }
{ prefetch_l3_fault r25 ; cmpleu r15, r16, r17 ; cmpeqi r5, r6, 5 }
{ prefetch_l3_fault r25 ; cmpleu r15, r16, r17 ; shli r5, r6, 5 }
{ prefetch_l3_fault r25 ; cmpleu r5, r6, r7 ; nor r15, r16, r17 }
{ prefetch_l3_fault r25 ; cmplts r15, r16, r17 ; info 19 }
{ prefetch_l3_fault r25 ; cmplts r15, r16, r17 ; tblidxb3 r5, r6 }
{ prefetch_l3_fault r25 ; cmplts r5, r6, r7 ; shl3addx r15, r16, r17 }
{ prefetch_l3_fault r25 ; cmpltsi r15, r16, 5 ; mula_ls_ls r5, r6, r7 }
{ prefetch_l3_fault r25 ; cmpltsi r5, r6, 5 ; cmpeqi r15, r16, 5 }
{ prefetch_l3_fault r25 ; cmpltu r15, r16, r17 ; add r5, r6, r7 }
{ prefetch_l3_fault r25 ; cmpltu r15, r16, r17 ; revbytes r5, r6 }
{ prefetch_l3_fault r25 ; cmpltu r5, r6, r7 ; jalr r15 }
{ prefetch_l3_fault r25 ; cmpne r15, r16, r17 ; cmpeqi r5, r6, 5 }
{ prefetch_l3_fault r25 ; cmpne r15, r16, r17 ; shli r5, r6, 5 }
{ prefetch_l3_fault r25 ; cmpne r5, r6, r7 ; nor r15, r16, r17 }
{ prefetch_l3_fault r25 ; ctz r5, r6 ; jrp r15 }
{ prefetch_l3_fault r25 ; fnop ; cmoveqz r5, r6, r7 }
{ prefetch_l3_fault r25 ; fnop ; mula_ls_ls r5, r6, r7 }
{ prefetch_l3_fault r25 ; fnop ; shrui r15, r16, 5 }
{ prefetch_l3_fault r25 ; fsingle_pack1 r5, r6 ; nor r15, r16, r17 }
{ prefetch_l3_fault r25 ; ill ; info 19 }
{ prefetch_l3_fault r25 ; ill ; tblidxb3 r5, r6 }
{ prefetch_l3_fault r25 ; info 19 ; jalrp r15 }
{ prefetch_l3_fault r25 ; info 19 ; shl2add r15, r16, r17 }
{ prefetch_l3_fault r25 ; jalr r15 ; cmples r5, r6, r7 }
{ prefetch_l3_fault r25 ; jalr r15 ; shrs r5, r6, r7 }
{ prefetch_l3_fault r25 ; jalrp r15 ; mula_hs_hs r5, r6, r7 }
{ prefetch_l3_fault r25 ; jr r15 ; andi r5, r6, 5 }
{ prefetch_l3_fault r25 ; jr r15 ; shl1addx r5, r6, r7 }
{ prefetch_l3_fault r25 ; jrp r15 ; move r5, r6 }
{ prefetch_l3_fault r25 ; jrp r15 }
{ prefetch_l3_fault r25 ; lnk r15 ; revbits r5, r6 }
{ prefetch_l3_fault r25 ; mnz r15, r16, r17 ; cmpne r5, r6, r7 }
{ prefetch_l3_fault r25 ; mnz r15, r16, r17 ; subx r5, r6, r7 }
{ prefetch_l3_fault r25 ; mnz r5, r6, r7 ; shl1addx r15, r16, r17 }
{ prefetch_l3_fault r25 ; move r15, r16 ; mul_ls_ls r5, r6, r7 }
{ prefetch_l3_fault r25 ; move r5, r6 ; addxi r15, r16, 5 }
{ prefetch_l3_fault r25 ; move r5, r6 ; sub r15, r16, r17 }
{ prefetch_l3_fault r25 ; movei r15, 5 ; nor r5, r6, r7 }
{ prefetch_l3_fault r25 ; movei r5, 5 ; cmpne r15, r16, r17 }
{ prefetch_l3_fault r25 ; mul_hs_hs r5, r6, r7 ; cmpeq r15, r16, r17 }
{ prefetch_l3_fault r25 ; mul_hs_hs r5, r6, r7 }
{ prefetch_l3_fault r25 ; mul_hu_hu r5, r6, r7 ; shrs r15, r16, r17 }
{ prefetch_l3_fault r25 ; mul_ls_ls r5, r6, r7 ; shl1add r15, r16, r17 }
{ prefetch_l3_fault r25 ; mul_lu_lu r5, r6, r7 ; mz r15, r16, r17 }
{ prefetch_l3_fault r25 ; mula_hs_hs r5, r6, r7 ; jalrp r15 }
{ prefetch_l3_fault r25 ; mula_hu_hu r5, r6, r7 ; cmpltsi r15, r16, 5 }
{ prefetch_l3_fault r25 ; mula_ls_ls r5, r6, r7 ; and r15, r16, r17 }
{ prefetch_l3_fault r25 ; mula_ls_ls r5, r6, r7 ; subx r15, r16, r17 }
{ prefetch_l3_fault r25 ; mula_lu_lu r5, r6, r7 ; shl3addx r15, r16, r17 }
{ prefetch_l3_fault r25 ; mulax r5, r6, r7 ; rotli r15, r16, 5 }
{ prefetch_l3_fault r25 ; mulx r5, r6, r7 ; move r15, r16 }
{ prefetch_l3_fault r25 ; mz r15, r16, r17 ; cmpne r5, r6, r7 }
{ prefetch_l3_fault r25 ; mz r15, r16, r17 ; subx r5, r6, r7 }
{ prefetch_l3_fault r25 ; mz r5, r6, r7 ; shl1addx r15, r16, r17 }
{ prefetch_l3_fault r25 ; nop ; cmpltsi r5, r6, 5 }
{ prefetch_l3_fault r25 ; nop ; revbytes r5, r6 }
{ prefetch_l3_fault r25 ; nor r15, r16, r17 ; add r5, r6, r7 }
{ prefetch_l3_fault r25 ; nor r15, r16, r17 ; revbytes r5, r6 }
{ prefetch_l3_fault r25 ; nor r5, r6, r7 ; jalr r15 }
{ prefetch_l3_fault r25 ; or r15, r16, r17 ; cmpeqi r5, r6, 5 }
{ prefetch_l3_fault r25 ; or r15, r16, r17 ; shli r5, r6, 5 }
{ prefetch_l3_fault r25 ; or r5, r6, r7 ; nor r15, r16, r17 }
{ prefetch_l3_fault r25 ; pcnt r5, r6 ; jrp r15 }
{ prefetch_l3_fault r25 ; revbits r5, r6 ; cmpne r15, r16, r17 }
{ prefetch_l3_fault r25 ; revbytes r5, r6 ; cmpeq r15, r16, r17 }
{ prefetch_l3_fault r25 ; revbytes r5, r6 }
{ prefetch_l3_fault r25 ; rotl r15, r16, r17 ; revbits r5, r6 }
{ prefetch_l3_fault r25 ; rotl r5, r6, r7 ; info 19 }
{ prefetch_l3_fault r25 ; rotli r15, r16, 5 ; cmpeq r5, r6, r7 }
{ prefetch_l3_fault r25 ; rotli r15, r16, 5 ; shl3addx r5, r6, r7 }
{ prefetch_l3_fault r25 ; rotli r5, r6, 5 ; nop }
{ prefetch_l3_fault r25 ; shl r15, r16, r17 ; fsingle_pack1 r5, r6 }
{ prefetch_l3_fault r25 ; shl r15, r16, r17 ; tblidxb2 r5, r6 }
{ prefetch_l3_fault r25 ; shl r5, r6, r7 ; shl3add r15, r16, r17 }
{ prefetch_l3_fault r25 ; shl1add r15, r16, r17 ; mula_hu_hu r5, r6, r7 }
{ prefetch_l3_fault r25 ; shl1add r5, r6, r7 ; cmpeq r15, r16, r17 }
{ prefetch_l3_fault r25 ; shl1add r5, r6, r7 }
{ prefetch_l3_fault r25 ; shl1addx r15, r16, r17 ; revbits r5, r6 }
{ prefetch_l3_fault r25 ; shl1addx r5, r6, r7 ; info 19 }
{ prefetch_l3_fault r25 ; shl2add r15, r16, r17 ; cmpeq r5, r6, r7 }
{ prefetch_l3_fault r25 ; shl2add r15, r16, r17 ; shl3addx r5, r6, r7 }
{ prefetch_l3_fault r25 ; shl2add r5, r6, r7 ; nop }
{ prefetch_l3_fault r25 ; shl2addx r15, r16, r17 ; fsingle_pack1 r5, r6 }
{ prefetch_l3_fault r25 ; shl2addx r15, r16, r17 ; tblidxb2 r5, r6 }
{ prefetch_l3_fault r25 ; shl2addx r5, r6, r7 ; shl3add r15, r16, r17 }
{ prefetch_l3_fault r25 ; shl3add r15, r16, r17 ; mula_hu_hu r5, r6, r7 }
{ prefetch_l3_fault r25 ; shl3add r5, r6, r7 ; cmpeq r15, r16, r17 }
{ prefetch_l3_fault r25 ; shl3add r5, r6, r7 }
{ prefetch_l3_fault r25 ; shl3addx r15, r16, r17 ; revbits r5, r6 }
{ prefetch_l3_fault r25 ; shl3addx r5, r6, r7 ; info 19 }
{ prefetch_l3_fault r25 ; shli r15, r16, 5 ; cmpeq r5, r6, r7 }
{ prefetch_l3_fault r25 ; shli r15, r16, 5 ; shl3addx r5, r6, r7 }
{ prefetch_l3_fault r25 ; shli r5, r6, 5 ; nop }
{ prefetch_l3_fault r25 ; shrs r15, r16, r17 ; fsingle_pack1 r5, r6 }
{ prefetch_l3_fault r25 ; shrs r15, r16, r17 ; tblidxb2 r5, r6 }
{ prefetch_l3_fault r25 ; shrs r5, r6, r7 ; shl3add r15, r16, r17 }
{ prefetch_l3_fault r25 ; shrsi r15, r16, 5 ; mula_hu_hu r5, r6, r7 }
{ prefetch_l3_fault r25 ; shrsi r5, r6, 5 ; cmpeq r15, r16, r17 }
{ prefetch_l3_fault r25 ; shrsi r5, r6, 5 }
{ prefetch_l3_fault r25 ; shru r15, r16, r17 ; revbits r5, r6 }
{ prefetch_l3_fault r25 ; shru r5, r6, r7 ; info 19 }
{ prefetch_l3_fault r25 ; shrui r15, r16, 5 ; cmpeq r5, r6, r7 }
{ prefetch_l3_fault r25 ; shrui r15, r16, 5 ; shl3addx r5, r6, r7 }
{ prefetch_l3_fault r25 ; shrui r5, r6, 5 ; nop }
{ prefetch_l3_fault r25 ; sub r15, r16, r17 ; fsingle_pack1 r5, r6 }
{ prefetch_l3_fault r25 ; sub r15, r16, r17 ; tblidxb2 r5, r6 }
{ prefetch_l3_fault r25 ; sub r5, r6, r7 ; shl3add r15, r16, r17 }
{ prefetch_l3_fault r25 ; subx r15, r16, r17 ; mula_hu_hu r5, r6, r7 }
{ prefetch_l3_fault r25 ; subx r5, r6, r7 ; cmpeq r15, r16, r17 }
{ prefetch_l3_fault r25 ; subx r5, r6, r7 }
{ prefetch_l3_fault r25 ; tblidxb0 r5, r6 ; shrs r15, r16, r17 }
{ prefetch_l3_fault r25 ; tblidxb1 r5, r6 ; shl1add r15, r16, r17 }
{ prefetch_l3_fault r25 ; tblidxb2 r5, r6 ; mz r15, r16, r17 }
{ prefetch_l3_fault r25 ; tblidxb3 r5, r6 ; jalrp r15 }
{ prefetch_l3_fault r25 ; xor r15, r16, r17 ; cmples r5, r6, r7 }
{ prefetch_l3_fault r25 ; xor r15, r16, r17 ; shrs r5, r6, r7 }
{ prefetch_l3_fault r25 ; xor r5, r6, r7 ; or r15, r16, r17 }
{ raise ; cmpltu r5, r6, r7 }
{ raise ; mul_hs_hs r5, r6, r7 }
{ raise ; shli r5, r6, 5 }
{ raise ; v1dotpusa r5, r6, r7 }
{ raise ; v2maxs r5, r6, r7 }
{ revbits r5, r6 ; add r15, r16, r17 ; ld1u r25, r26 }
{ revbits r5, r6 ; addx r15, r16, r17 ; ld2s r25, r26 }
{ revbits r5, r6 ; and r15, r16, r17 ; ld2s r25, r26 }
{ revbits r5, r6 ; cmpeq r15, r16, r17 ; ld4s r25, r26 }
{ revbits r5, r6 ; cmples r15, r16, r17 ; ld4s r25, r26 }
{ revbits r5, r6 ; cmplts r15, r16, r17 ; prefetch r25 }
{ revbits r5, r6 ; cmpltu r15, r16, r17 ; prefetch_l1_fault r25 }
{ revbits r5, r6 ; fetchand r15, r16, r17 }
{ revbits r5, r6 ; ill ; prefetch_l3_fault r25 }
{ revbits r5, r6 ; jalr r15 ; prefetch_l3 r25 }
{ revbits r5, r6 ; jr r15 ; st r25, r26 }
{ revbits r5, r6 ; ld r25, r26 ; ill }
{ revbits r5, r6 ; ld1s r25, r26 ; cmpeqi r15, r16, 5 }
{ revbits r5, r6 ; ld1s_add r15, r16, 5 }
{ revbits r5, r6 ; ld1u r25, r26 ; shli r15, r16, 5 }
{ revbits r5, r6 ; ld2s r25, r26 ; rotl r15, r16, r17 }
{ revbits r5, r6 ; ld2u r25, r26 ; jrp r15 }
{ revbits r5, r6 ; ld4s r25, r26 ; cmpltsi r15, r16, 5 }
{ revbits r5, r6 ; ld4u r25, r26 ; addx r15, r16, r17 }
{ revbits r5, r6 ; ld4u r25, r26 ; shrui r15, r16, 5 }
{ revbits r5, r6 ; lnk r15 ; st4 r25, r26 }
{ revbits r5, r6 ; move r15, r16 ; st4 r25, r26 }
{ revbits r5, r6 ; mz r15, r16, r17 ; st4 r25, r26 }
{ revbits r5, r6 ; or r15, r16, r17 ; ld r25, r26 }
{ revbits r5, r6 ; prefetch r25 ; jr r15 }
{ revbits r5, r6 ; prefetch_l1 r25 ; andi r15, r16, 5 }
{ revbits r5, r6 ; prefetch_l1 r25 ; xor r15, r16, r17 }
{ revbits r5, r6 ; prefetch_l1_fault r25 ; shl3addx r15, r16, r17 }
{ revbits r5, r6 ; prefetch_l2 r25 ; rotl r15, r16, r17 }
{ revbits r5, r6 ; prefetch_l2_fault r25 ; lnk r15 }
{ revbits r5, r6 ; prefetch_l3 r25 ; cmpne r15, r16, r17 }
{ revbits r5, r6 ; prefetch_l3_fault r25 ; andi r15, r16, 5 }
{ revbits r5, r6 ; prefetch_l3_fault r25 ; xor r15, r16, r17 }
{ revbits r5, r6 ; rotli r15, r16, 5 }
{ revbits r5, r6 ; shl1addx r15, r16, r17 ; ld r25, r26 }
{ revbits r5, r6 ; shl2addx r15, r16, r17 ; ld1u r25, r26 }
{ revbits r5, r6 ; shl3addx r15, r16, r17 ; ld2u r25, r26 }
{ revbits r5, r6 ; shrs r15, r16, r17 ; ld2u r25, r26 }
{ revbits r5, r6 ; shru r15, r16, r17 ; ld4u r25, r26 }
{ revbits r5, r6 ; st r25, r26 ; andi r15, r16, 5 }
{ revbits r5, r6 ; st r25, r26 ; xor r15, r16, r17 }
{ revbits r5, r6 ; st1 r25, r26 ; shl3addx r15, r16, r17 }
{ revbits r5, r6 ; st2 r25, r26 ; or r15, r16, r17 }
{ revbits r5, r6 ; st4 r25, r26 ; jr r15 }
{ revbits r5, r6 ; sub r15, r16, r17 ; ld1u r25, r26 }
{ revbits r5, r6 ; v1cmpeq r15, r16, r17 }
{ revbits r5, r6 ; v2maxsi r15, r16, 5 }
{ revbits r5, r6 ; xor r15, r16, r17 ; prefetch_l2_fault r25 }
{ revbytes r5, r6 ; addi r15, r16, 5 ; prefetch_l3 r25 }
{ revbytes r5, r6 ; addxi r15, r16, 5 ; prefetch_l3_fault r25 }
{ revbytes r5, r6 ; andi r15, r16, 5 ; prefetch_l3_fault r25 }
{ revbytes r5, r6 ; cmpeqi r15, r16, 5 ; st1 r25, r26 }
{ revbytes r5, r6 ; cmpleu r15, r16, r17 ; st1 r25, r26 }
{ revbytes r5, r6 ; cmpltsi r15, r16, 5 ; st4 r25, r26 }
{ revbytes r5, r6 ; cmpne r15, r16, r17 }
{ revbytes r5, r6 ; ill ; ld1u r25, r26 }
{ revbytes r5, r6 ; jalr r15 ; ld1s r25, r26 }
{ revbytes r5, r6 ; jr r15 ; ld2s r25, r26 }
{ revbytes r5, r6 ; ld r25, r26 ; and r15, r16, r17 }
{ revbytes r5, r6 ; ld r25, r26 ; subx r15, r16, r17 }
{ revbytes r5, r6 ; ld1s r25, r26 ; shl3add r15, r16, r17 }
{ revbytes r5, r6 ; ld1u r25, r26 ; nor r15, r16, r17 }
{ revbytes r5, r6 ; ld2s r25, r26 ; jalrp r15 }
{ revbytes r5, r6 ; ld2u r25, r26 ; cmpleu r15, r16, r17 }
{ revbytes r5, r6 ; ld4s r25, r26 ; add r15, r16, r17 }
{ revbytes r5, r6 ; ld4s r25, r26 ; shrsi r15, r16, 5 }
{ revbytes r5, r6 ; ld4u r25, r26 ; shl r15, r16, r17 }
{ revbytes r5, r6 ; lnk r15 ; ld4u r25, r26 }
{ revbytes r5, r6 ; move r15, r16 ; ld4u r25, r26 }
{ revbytes r5, r6 ; mz r15, r16, r17 ; ld4u r25, r26 }
{ revbytes r5, r6 ; nor r15, r16, r17 ; prefetch_l1 r25 }
{ revbytes r5, r6 ; prefetch r25 ; cmples r15, r16, r17 }
{ revbytes r5, r6 ; prefetch_add_l1_fault r15, 5 }
{ revbytes r5, r6 ; prefetch_l1 r25 ; shl2add r15, r16, r17 }
{ revbytes r5, r6 ; prefetch_l1_fault r25 ; nop }
{ revbytes r5, r6 ; prefetch_l2 r25 ; jalrp r15 }
{ revbytes r5, r6 ; prefetch_l2_fault r25 ; cmplts r15, r16, r17 }
{ revbytes r5, r6 ; prefetch_l3 r25 ; addx r15, r16, r17 }
{ revbytes r5, r6 ; prefetch_l3 r25 ; shrui r15, r16, 5 }
{ revbytes r5, r6 ; prefetch_l3_fault r25 ; shl2add r15, r16, r17 }
{ revbytes r5, r6 ; rotli r15, r16, 5 ; prefetch r25 }
{ revbytes r5, r6 ; shl1add r15, r16, r17 ; prefetch_l1 r25 }
{ revbytes r5, r6 ; shl2add r15, r16, r17 ; prefetch_l2 r25 }
{ revbytes r5, r6 ; shl3add r15, r16, r17 ; prefetch_l3 r25 }
{ revbytes r5, r6 ; shli r15, r16, 5 ; st r25, r26 }
{ revbytes r5, r6 ; shrsi r15, r16, 5 ; st r25, r26 }
{ revbytes r5, r6 ; shrui r15, r16, 5 ; st2 r25, r26 }
{ revbytes r5, r6 ; st r25, r26 ; shl2add r15, r16, r17 }
{ revbytes r5, r6 ; st1 r25, r26 ; nop }
{ revbytes r5, r6 ; st2 r25, r26 ; jalr r15 }
{ revbytes r5, r6 ; st4 r25, r26 ; cmples r15, r16, r17 }
{ revbytes r5, r6 ; st_add r15, r16, 5 }
{ revbytes r5, r6 ; subx r15, r16, r17 ; prefetch_l3 r25 }
{ revbytes r5, r6 ; v2cmpeqi r15, r16, 5 }
{ revbytes r5, r6 ; xor r15, r16, r17 ; ld r25, r26 }
{ rotl r15, r16, r17 ; addi r5, r6, 5 ; ld1s r25, r26 }
{ rotl r15, r16, r17 ; addxi r5, r6, 5 ; ld1u r25, r26 }
{ rotl r15, r16, r17 ; andi r5, r6, 5 ; ld1u r25, r26 }
{ rotl r15, r16, r17 ; cmoveqz r5, r6, r7 ; ld1s r25, r26 }
{ rotl r15, r16, r17 ; cmpeq r5, r6, r7 ; ld2s r25, r26 }
{ rotl r15, r16, r17 ; cmples r5, r6, r7 ; ld4s r25, r26 }
{ rotl r15, r16, r17 ; cmplts r5, r6, r7 ; prefetch r25 }
{ rotl r15, r16, r17 ; cmpltu r5, r6, r7 ; prefetch_l1_fault r25 }
{ rotl r15, r16, r17 ; ctz r5, r6 ; ld1s r25, r26 }
{ rotl r15, r16, r17 ; fnop ; prefetch_l2 r25 }
{ rotl r15, r16, r17 ; info 19 ; ld4u r25, r26 }
{ rotl r15, r16, r17 ; ld r25, r26 ; mul_ls_ls r5, r6, r7 }
{ rotl r15, r16, r17 ; ld1s r25, r26 ; addxi r5, r6, 5 }
{ rotl r15, r16, r17 ; ld1s r25, r26 ; shl r5, r6, r7 }
{ rotl r15, r16, r17 ; ld1u r25, r26 ; info 19 }
{ rotl r15, r16, r17 ; ld1u r25, r26 ; tblidxb3 r5, r6 }
{ rotl r15, r16, r17 ; ld2s r25, r26 ; or r5, r6, r7 }
{ rotl r15, r16, r17 ; ld2u r25, r26 ; cmpltsi r5, r6, 5 }
{ rotl r15, r16, r17 ; ld2u r25, r26 ; shrui r5, r6, 5 }
{ rotl r15, r16, r17 ; ld4s r25, r26 ; mula_lu_lu r5, r6, r7 }
{ rotl r15, r16, r17 ; ld4u r25, r26 ; cmovnez r5, r6, r7 }
{ rotl r15, r16, r17 ; ld4u r25, r26 ; shl3add r5, r6, r7 }
{ rotl r15, r16, r17 ; move r5, r6 ; ld4s r25, r26 }
{ rotl r15, r16, r17 ; mul_hs_hs r5, r6, r7 ; ld4u r25, r26 }
{ rotl r15, r16, r17 ; mul_ls_ls r5, r6, r7 ; ld2s r25, r26 }
{ rotl r15, r16, r17 ; mula_hs_hs r5, r6, r7 ; ld2u r25, r26 }
{ rotl r15, r16, r17 ; mula_ls_ls r5, r6, r7 ; ld1s r25, r26 }
{ rotl r15, r16, r17 ; mulax r5, r6, r7 ; ld1u r25, r26 }
{ rotl r15, r16, r17 ; mz r5, r6, r7 ; ld2u r25, r26 }
{ rotl r15, r16, r17 ; nor r5, r6, r7 ; ld4u r25, r26 }
{ rotl r15, r16, r17 ; pcnt r5, r6 ; prefetch r25 }
{ rotl r15, r16, r17 ; prefetch r25 ; mula_hs_hs r5, r6, r7 }
{ rotl r15, r16, r17 ; prefetch_l1 r25 ; andi r5, r6, 5 }
{ rotl r15, r16, r17 ; prefetch_l1 r25 ; shl1addx r5, r6, r7 }
{ rotl r15, r16, r17 ; prefetch_l1_fault r25 ; move r5, r6 }
{ rotl r15, r16, r17 ; prefetch_l1_fault r25 }
{ rotl r15, r16, r17 ; prefetch_l2 r25 ; revbits r5, r6 }
{ rotl r15, r16, r17 ; prefetch_l2_fault r25 ; cmpne r5, r6, r7 }
{ rotl r15, r16, r17 ; prefetch_l2_fault r25 ; subx r5, r6, r7 }
{ rotl r15, r16, r17 ; prefetch_l3 r25 ; mulx r5, r6, r7 }
{ rotl r15, r16, r17 ; prefetch_l3_fault r25 ; cmpeqi r5, r6, 5 }
{ rotl r15, r16, r17 ; prefetch_l3_fault r25 ; shli r5, r6, 5 }
{ rotl r15, r16, r17 ; revbytes r5, r6 ; prefetch_l1 r25 }
{ rotl r15, r16, r17 ; rotli r5, r6, 5 ; prefetch_l2 r25 }
{ rotl r15, r16, r17 ; shl1add r5, r6, r7 ; prefetch_l2_fault r25 }
{ rotl r15, r16, r17 ; shl2add r5, r6, r7 ; prefetch_l3_fault r25 }
{ rotl r15, r16, r17 ; shl3add r5, r6, r7 ; st1 r25, r26 }
{ rotl r15, r16, r17 ; shli r5, r6, 5 ; st4 r25, r26 }
{ rotl r15, r16, r17 ; shrsi r5, r6, 5 ; st4 r25, r26 }
{ rotl r15, r16, r17 ; shrux r5, r6, r7 }
{ rotl r15, r16, r17 ; st r25, r26 ; or r5, r6, r7 }
{ rotl r15, r16, r17 ; st1 r25, r26 ; cmpltsi r5, r6, 5 }
{ rotl r15, r16, r17 ; st1 r25, r26 ; shrui r5, r6, 5 }
{ rotl r15, r16, r17 ; st2 r25, r26 ; mula_lu_lu r5, r6, r7 }
{ rotl r15, r16, r17 ; st4 r25, r26 ; cmovnez r5, r6, r7 }
{ rotl r15, r16, r17 ; st4 r25, r26 ; shl3add r5, r6, r7 }
{ rotl r15, r16, r17 ; subx r5, r6, r7 ; ld4u r25, r26 }
{ rotl r15, r16, r17 ; tblidxb1 r5, r6 ; prefetch r25 }
{ rotl r15, r16, r17 ; tblidxb3 r5, r6 ; prefetch_l1_fault r25 }
{ rotl r15, r16, r17 ; v1mnz r5, r6, r7 }
{ rotl r15, r16, r17 ; v2mults r5, r6, r7 }
{ rotl r15, r16, r17 ; xor r5, r6, r7 ; prefetch_l2_fault r25 }
{ rotl r5, r6, r7 ; addi r15, r16, 5 ; prefetch_l3 r25 }
{ rotl r5, r6, r7 ; addxi r15, r16, 5 ; prefetch_l3_fault r25 }
{ rotl r5, r6, r7 ; andi r15, r16, 5 ; prefetch_l3_fault r25 }
{ rotl r5, r6, r7 ; cmpeqi r15, r16, 5 ; st1 r25, r26 }
{ rotl r5, r6, r7 ; cmpleu r15, r16, r17 ; st1 r25, r26 }
{ rotl r5, r6, r7 ; cmpltsi r15, r16, 5 ; st4 r25, r26 }
{ rotl r5, r6, r7 ; cmpne r15, r16, r17 }
{ rotl r5, r6, r7 ; ill ; ld1u r25, r26 }
{ rotl r5, r6, r7 ; jalr r15 ; ld1s r25, r26 }
{ rotl r5, r6, r7 ; jr r15 ; ld2s r25, r26 }
{ rotl r5, r6, r7 ; ld r25, r26 ; and r15, r16, r17 }
{ rotl r5, r6, r7 ; ld r25, r26 ; subx r15, r16, r17 }
{ rotl r5, r6, r7 ; ld1s r25, r26 ; shl3add r15, r16, r17 }
{ rotl r5, r6, r7 ; ld1u r25, r26 ; nor r15, r16, r17 }
{ rotl r5, r6, r7 ; ld2s r25, r26 ; jalrp r15 }
{ rotl r5, r6, r7 ; ld2u r25, r26 ; cmpleu r15, r16, r17 }
{ rotl r5, r6, r7 ; ld4s r25, r26 ; add r15, r16, r17 }
{ rotl r5, r6, r7 ; ld4s r25, r26 ; shrsi r15, r16, 5 }
{ rotl r5, r6, r7 ; ld4u r25, r26 ; shl r15, r16, r17 }
{ rotl r5, r6, r7 ; lnk r15 ; ld4u r25, r26 }
{ rotl r5, r6, r7 ; move r15, r16 ; ld4u r25, r26 }
{ rotl r5, r6, r7 ; mz r15, r16, r17 ; ld4u r25, r26 }
{ rotl r5, r6, r7 ; nor r15, r16, r17 ; prefetch_l1 r25 }
{ rotl r5, r6, r7 ; prefetch r25 ; cmples r15, r16, r17 }
{ rotl r5, r6, r7 ; prefetch_add_l1_fault r15, 5 }
{ rotl r5, r6, r7 ; prefetch_l1 r25 ; shl2add r15, r16, r17 }
{ rotl r5, r6, r7 ; prefetch_l1_fault r25 ; nop }
{ rotl r5, r6, r7 ; prefetch_l2 r25 ; jalrp r15 }
{ rotl r5, r6, r7 ; prefetch_l2_fault r25 ; cmplts r15, r16, r17 }
{ rotl r5, r6, r7 ; prefetch_l3 r25 ; addx r15, r16, r17 }
{ rotl r5, r6, r7 ; prefetch_l3 r25 ; shrui r15, r16, 5 }
{ rotl r5, r6, r7 ; prefetch_l3_fault r25 ; shl2add r15, r16, r17 }
{ rotl r5, r6, r7 ; rotli r15, r16, 5 ; prefetch r25 }
{ rotl r5, r6, r7 ; shl1add r15, r16, r17 ; prefetch_l1 r25 }
{ rotl r5, r6, r7 ; shl2add r15, r16, r17 ; prefetch_l2 r25 }
{ rotl r5, r6, r7 ; shl3add r15, r16, r17 ; prefetch_l3 r25 }
{ rotl r5, r6, r7 ; shli r15, r16, 5 ; st r25, r26 }
{ rotl r5, r6, r7 ; shrsi r15, r16, 5 ; st r25, r26 }
{ rotl r5, r6, r7 ; shrui r15, r16, 5 ; st2 r25, r26 }
{ rotl r5, r6, r7 ; st r25, r26 ; shl2add r15, r16, r17 }
{ rotl r5, r6, r7 ; st1 r25, r26 ; nop }
{ rotl r5, r6, r7 ; st2 r25, r26 ; jalr r15 }
{ rotl r5, r6, r7 ; st4 r25, r26 ; cmples r15, r16, r17 }
{ rotl r5, r6, r7 ; st_add r15, r16, 5 }
{ rotl r5, r6, r7 ; subx r15, r16, r17 ; prefetch_l3 r25 }
{ rotl r5, r6, r7 ; v2cmpeqi r15, r16, 5 }
{ rotl r5, r6, r7 ; xor r15, r16, r17 ; ld r25, r26 }
{ rotli r15, r16, 5 ; addi r5, r6, 5 ; ld1s r25, r26 }
{ rotli r15, r16, 5 ; addxi r5, r6, 5 ; ld1u r25, r26 }
{ rotli r15, r16, 5 ; andi r5, r6, 5 ; ld1u r25, r26 }
{ rotli r15, r16, 5 ; cmoveqz r5, r6, r7 ; ld1s r25, r26 }
{ rotli r15, r16, 5 ; cmpeq r5, r6, r7 ; ld2s r25, r26 }
{ rotli r15, r16, 5 ; cmples r5, r6, r7 ; ld4s r25, r26 }
{ rotli r15, r16, 5 ; cmplts r5, r6, r7 ; prefetch r25 }
{ rotli r15, r16, 5 ; cmpltu r5, r6, r7 ; prefetch_l1_fault r25 }
{ rotli r15, r16, 5 ; ctz r5, r6 ; ld1s r25, r26 }
{ rotli r15, r16, 5 ; fnop ; prefetch_l2 r25 }
{ rotli r15, r16, 5 ; info 19 ; ld4u r25, r26 }
{ rotli r15, r16, 5 ; ld r25, r26 ; mul_ls_ls r5, r6, r7 }
{ rotli r15, r16, 5 ; ld1s r25, r26 ; addxi r5, r6, 5 }
{ rotli r15, r16, 5 ; ld1s r25, r26 ; shl r5, r6, r7 }
{ rotli r15, r16, 5 ; ld1u r25, r26 ; info 19 }
{ rotli r15, r16, 5 ; ld1u r25, r26 ; tblidxb3 r5, r6 }
{ rotli r15, r16, 5 ; ld2s r25, r26 ; or r5, r6, r7 }
{ rotli r15, r16, 5 ; ld2u r25, r26 ; cmpltsi r5, r6, 5 }
{ rotli r15, r16, 5 ; ld2u r25, r26 ; shrui r5, r6, 5 }
{ rotli r15, r16, 5 ; ld4s r25, r26 ; mula_lu_lu r5, r6, r7 }
{ rotli r15, r16, 5 ; ld4u r25, r26 ; cmovnez r5, r6, r7 }
{ rotli r15, r16, 5 ; ld4u r25, r26 ; shl3add r5, r6, r7 }
{ rotli r15, r16, 5 ; move r5, r6 ; ld4s r25, r26 }
{ rotli r15, r16, 5 ; mul_hs_hs r5, r6, r7 ; ld4u r25, r26 }
{ rotli r15, r16, 5 ; mul_ls_ls r5, r6, r7 ; ld2s r25, r26 }
{ rotli r15, r16, 5 ; mula_hs_hs r5, r6, r7 ; ld2u r25, r26 }
{ rotli r15, r16, 5 ; mula_ls_ls r5, r6, r7 ; ld1s r25, r26 }
{ rotli r15, r16, 5 ; mulax r5, r6, r7 ; ld1u r25, r26 }
{ rotli r15, r16, 5 ; mz r5, r6, r7 ; ld2u r25, r26 }
{ rotli r15, r16, 5 ; nor r5, r6, r7 ; ld4u r25, r26 }
{ rotli r15, r16, 5 ; pcnt r5, r6 ; prefetch r25 }
{ rotli r15, r16, 5 ; prefetch r25 ; mula_hs_hs r5, r6, r7 }
{ rotli r15, r16, 5 ; prefetch_l1 r25 ; andi r5, r6, 5 }
{ rotli r15, r16, 5 ; prefetch_l1 r25 ; shl1addx r5, r6, r7 }
{ rotli r15, r16, 5 ; prefetch_l1_fault r25 ; move r5, r6 }
{ rotli r15, r16, 5 ; prefetch_l1_fault r25 }
{ rotli r15, r16, 5 ; prefetch_l2 r25 ; revbits r5, r6 }
{ rotli r15, r16, 5 ; prefetch_l2_fault r25 ; cmpne r5, r6, r7 }
{ rotli r15, r16, 5 ; prefetch_l2_fault r25 ; subx r5, r6, r7 }
{ rotli r15, r16, 5 ; prefetch_l3 r25 ; mulx r5, r6, r7 }
{ rotli r15, r16, 5 ; prefetch_l3_fault r25 ; cmpeqi r5, r6, 5 }
{ rotli r15, r16, 5 ; prefetch_l3_fault r25 ; shli r5, r6, 5 }
{ rotli r15, r16, 5 ; revbytes r5, r6 ; prefetch_l1 r25 }
{ rotli r15, r16, 5 ; rotli r5, r6, 5 ; prefetch_l2 r25 }
{ rotli r15, r16, 5 ; shl1add r5, r6, r7 ; prefetch_l2_fault r25 }
{ rotli r15, r16, 5 ; shl2add r5, r6, r7 ; prefetch_l3_fault r25 }
{ rotli r15, r16, 5 ; shl3add r5, r6, r7 ; st1 r25, r26 }
{ rotli r15, r16, 5 ; shli r5, r6, 5 ; st4 r25, r26 }
{ rotli r15, r16, 5 ; shrsi r5, r6, 5 ; st4 r25, r26 }
{ rotli r15, r16, 5 ; shrux r5, r6, r7 }
{ rotli r15, r16, 5 ; st r25, r26 ; or r5, r6, r7 }
{ rotli r15, r16, 5 ; st1 r25, r26 ; cmpltsi r5, r6, 5 }
{ rotli r15, r16, 5 ; st1 r25, r26 ; shrui r5, r6, 5 }
{ rotli r15, r16, 5 ; st2 r25, r26 ; mula_lu_lu r5, r6, r7 }
{ rotli r15, r16, 5 ; st4 r25, r26 ; cmovnez r5, r6, r7 }
{ rotli r15, r16, 5 ; st4 r25, r26 ; shl3add r5, r6, r7 }
{ rotli r15, r16, 5 ; subx r5, r6, r7 ; ld4u r25, r26 }
{ rotli r15, r16, 5 ; tblidxb1 r5, r6 ; prefetch r25 }
{ rotli r15, r16, 5 ; tblidxb3 r5, r6 ; prefetch_l1_fault r25 }
{ rotli r15, r16, 5 ; v1mnz r5, r6, r7 }
{ rotli r15, r16, 5 ; v2mults r5, r6, r7 }
{ rotli r15, r16, 5 ; xor r5, r6, r7 ; prefetch_l2_fault r25 }
{ rotli r5, r6, 5 ; addi r15, r16, 5 ; prefetch_l3 r25 }
{ rotli r5, r6, 5 ; addxi r15, r16, 5 ; prefetch_l3_fault r25 }
{ rotli r5, r6, 5 ; andi r15, r16, 5 ; prefetch_l3_fault r25 }
{ rotli r5, r6, 5 ; cmpeqi r15, r16, 5 ; st1 r25, r26 }
{ rotli r5, r6, 5 ; cmpleu r15, r16, r17 ; st1 r25, r26 }
{ rotli r5, r6, 5 ; cmpltsi r15, r16, 5 ; st4 r25, r26 }
{ rotli r5, r6, 5 ; cmpne r15, r16, r17 }
{ rotli r5, r6, 5 ; ill ; ld1u r25, r26 }
{ rotli r5, r6, 5 ; jalr r15 ; ld1s r25, r26 }
{ rotli r5, r6, 5 ; jr r15 ; ld2s r25, r26 }
{ rotli r5, r6, 5 ; ld r25, r26 ; and r15, r16, r17 }
{ rotli r5, r6, 5 ; ld r25, r26 ; subx r15, r16, r17 }
{ rotli r5, r6, 5 ; ld1s r25, r26 ; shl3add r15, r16, r17 }
{ rotli r5, r6, 5 ; ld1u r25, r26 ; nor r15, r16, r17 }
{ rotli r5, r6, 5 ; ld2s r25, r26 ; jalrp r15 }
{ rotli r5, r6, 5 ; ld2u r25, r26 ; cmpleu r15, r16, r17 }
{ rotli r5, r6, 5 ; ld4s r25, r26 ; add r15, r16, r17 }
{ rotli r5, r6, 5 ; ld4s r25, r26 ; shrsi r15, r16, 5 }
{ rotli r5, r6, 5 ; ld4u r25, r26 ; shl r15, r16, r17 }
{ rotli r5, r6, 5 ; lnk r15 ; ld4u r25, r26 }
{ rotli r5, r6, 5 ; move r15, r16 ; ld4u r25, r26 }
{ rotli r5, r6, 5 ; mz r15, r16, r17 ; ld4u r25, r26 }
{ rotli r5, r6, 5 ; nor r15, r16, r17 ; prefetch_l1 r25 }
{ rotli r5, r6, 5 ; prefetch r25 ; cmples r15, r16, r17 }
{ rotli r5, r6, 5 ; prefetch_add_l1_fault r15, 5 }
{ rotli r5, r6, 5 ; prefetch_l1 r25 ; shl2add r15, r16, r17 }
{ rotli r5, r6, 5 ; prefetch_l1_fault r25 ; nop }
{ rotli r5, r6, 5 ; prefetch_l2 r25 ; jalrp r15 }
{ rotli r5, r6, 5 ; prefetch_l2_fault r25 ; cmplts r15, r16, r17 }
{ rotli r5, r6, 5 ; prefetch_l3 r25 ; addx r15, r16, r17 }
{ rotli r5, r6, 5 ; prefetch_l3 r25 ; shrui r15, r16, 5 }
{ rotli r5, r6, 5 ; prefetch_l3_fault r25 ; shl2add r15, r16, r17 }
{ rotli r5, r6, 5 ; rotli r15, r16, 5 ; prefetch r25 }
{ rotli r5, r6, 5 ; shl1add r15, r16, r17 ; prefetch_l1 r25 }
{ rotli r5, r6, 5 ; shl2add r15, r16, r17 ; prefetch_l2 r25 }
{ rotli r5, r6, 5 ; shl3add r15, r16, r17 ; prefetch_l3 r25 }
{ rotli r5, r6, 5 ; shli r15, r16, 5 ; st r25, r26 }
{ rotli r5, r6, 5 ; shrsi r15, r16, 5 ; st r25, r26 }
{ rotli r5, r6, 5 ; shrui r15, r16, 5 ; st2 r25, r26 }
{ rotli r5, r6, 5 ; st r25, r26 ; shl2add r15, r16, r17 }
{ rotli r5, r6, 5 ; st1 r25, r26 ; nop }
{ rotli r5, r6, 5 ; st2 r25, r26 ; jalr r15 }
{ rotli r5, r6, 5 ; st4 r25, r26 ; cmples r15, r16, r17 }
{ rotli r5, r6, 5 ; st_add r15, r16, 5 }
{ rotli r5, r6, 5 ; subx r15, r16, r17 ; prefetch_l3 r25 }
{ rotli r5, r6, 5 ; v2cmpeqi r15, r16, 5 }
{ rotli r5, r6, 5 ; xor r15, r16, r17 ; ld r25, r26 }
{ shl r15, r16, r17 ; addi r5, r6, 5 ; ld1s r25, r26 }
{ shl r15, r16, r17 ; addxi r5, r6, 5 ; ld1u r25, r26 }
{ shl r15, r16, r17 ; andi r5, r6, 5 ; ld1u r25, r26 }
{ shl r15, r16, r17 ; cmoveqz r5, r6, r7 ; ld1s r25, r26 }
{ shl r15, r16, r17 ; cmpeq r5, r6, r7 ; ld2s r25, r26 }
{ shl r15, r16, r17 ; cmples r5, r6, r7 ; ld4s r25, r26 }
{ shl r15, r16, r17 ; cmplts r5, r6, r7 ; prefetch r25 }
{ shl r15, r16, r17 ; cmpltu r5, r6, r7 ; prefetch_l1_fault r25 }
{ shl r15, r16, r17 ; ctz r5, r6 ; ld1s r25, r26 }
{ shl r15, r16, r17 ; fnop ; prefetch_l2 r25 }
{ shl r15, r16, r17 ; info 19 ; ld4u r25, r26 }
{ shl r15, r16, r17 ; ld r25, r26 ; mul_ls_ls r5, r6, r7 }
{ shl r15, r16, r17 ; ld1s r25, r26 ; addxi r5, r6, 5 }
{ shl r15, r16, r17 ; ld1s r25, r26 ; shl r5, r6, r7 }
{ shl r15, r16, r17 ; ld1u r25, r26 ; info 19 }
{ shl r15, r16, r17 ; ld1u r25, r26 ; tblidxb3 r5, r6 }
{ shl r15, r16, r17 ; ld2s r25, r26 ; or r5, r6, r7 }
{ shl r15, r16, r17 ; ld2u r25, r26 ; cmpltsi r5, r6, 5 }
{ shl r15, r16, r17 ; ld2u r25, r26 ; shrui r5, r6, 5 }
{ shl r15, r16, r17 ; ld4s r25, r26 ; mula_lu_lu r5, r6, r7 }
{ shl r15, r16, r17 ; ld4u r25, r26 ; cmovnez r5, r6, r7 }
{ shl r15, r16, r17 ; ld4u r25, r26 ; shl3add r5, r6, r7 }
{ shl r15, r16, r17 ; move r5, r6 ; ld4s r25, r26 }
{ shl r15, r16, r17 ; mul_hs_hs r5, r6, r7 ; ld4u r25, r26 }
{ shl r15, r16, r17 ; mul_ls_ls r5, r6, r7 ; ld2s r25, r26 }
{ shl r15, r16, r17 ; mula_hs_hs r5, r6, r7 ; ld2u r25, r26 }
{ shl r15, r16, r17 ; mula_ls_ls r5, r6, r7 ; ld1s r25, r26 }
{ shl r15, r16, r17 ; mulax r5, r6, r7 ; ld1u r25, r26 }
{ shl r15, r16, r17 ; mz r5, r6, r7 ; ld2u r25, r26 }
{ shl r15, r16, r17 ; nor r5, r6, r7 ; ld4u r25, r26 }
{ shl r15, r16, r17 ; pcnt r5, r6 ; prefetch r25 }
{ shl r15, r16, r17 ; prefetch r25 ; mula_hs_hs r5, r6, r7 }
{ shl r15, r16, r17 ; prefetch_l1 r25 ; andi r5, r6, 5 }
{ shl r15, r16, r17 ; prefetch_l1 r25 ; shl1addx r5, r6, r7 }
{ shl r15, r16, r17 ; prefetch_l1_fault r25 ; move r5, r6 }
{ shl r15, r16, r17 ; prefetch_l1_fault r25 }
{ shl r15, r16, r17 ; prefetch_l2 r25 ; revbits r5, r6 }
{ shl r15, r16, r17 ; prefetch_l2_fault r25 ; cmpne r5, r6, r7 }
{ shl r15, r16, r17 ; prefetch_l2_fault r25 ; subx r5, r6, r7 }
{ shl r15, r16, r17 ; prefetch_l3 r25 ; mulx r5, r6, r7 }
{ shl r15, r16, r17 ; prefetch_l3_fault r25 ; cmpeqi r5, r6, 5 }
{ shl r15, r16, r17 ; prefetch_l3_fault r25 ; shli r5, r6, 5 }
{ shl r15, r16, r17 ; revbytes r5, r6 ; prefetch_l1 r25 }
{ shl r15, r16, r17 ; rotli r5, r6, 5 ; prefetch_l2 r25 }
{ shl r15, r16, r17 ; shl1add r5, r6, r7 ; prefetch_l2_fault r25 }
{ shl r15, r16, r17 ; shl2add r5, r6, r7 ; prefetch_l3_fault r25 }
{ shl r15, r16, r17 ; shl3add r5, r6, r7 ; st1 r25, r26 }
{ shl r15, r16, r17 ; shli r5, r6, 5 ; st4 r25, r26 }
{ shl r15, r16, r17 ; shrsi r5, r6, 5 ; st4 r25, r26 }
{ shl r15, r16, r17 ; shrux r5, r6, r7 }
{ shl r15, r16, r17 ; st r25, r26 ; or r5, r6, r7 }
{ shl r15, r16, r17 ; st1 r25, r26 ; cmpltsi r5, r6, 5 }
{ shl r15, r16, r17 ; st1 r25, r26 ; shrui r5, r6, 5 }
{ shl r15, r16, r17 ; st2 r25, r26 ; mula_lu_lu r5, r6, r7 }
{ shl r15, r16, r17 ; st4 r25, r26 ; cmovnez r5, r6, r7 }
{ shl r15, r16, r17 ; st4 r25, r26 ; shl3add r5, r6, r7 }
{ shl r15, r16, r17 ; subx r5, r6, r7 ; ld4u r25, r26 }
{ shl r15, r16, r17 ; tblidxb1 r5, r6 ; prefetch r25 }
{ shl r15, r16, r17 ; tblidxb3 r5, r6 ; prefetch_l1_fault r25 }
{ shl r15, r16, r17 ; v1mnz r5, r6, r7 }
{ shl r15, r16, r17 ; v2mults r5, r6, r7 }
{ shl r15, r16, r17 ; xor r5, r6, r7 ; prefetch_l2_fault r25 }
{ shl r5, r6, r7 ; addi r15, r16, 5 ; prefetch_l3 r25 }
{ shl r5, r6, r7 ; addxi r15, r16, 5 ; prefetch_l3_fault r25 }
{ shl r5, r6, r7 ; andi r15, r16, 5 ; prefetch_l3_fault r25 }
{ shl r5, r6, r7 ; cmpeqi r15, r16, 5 ; st1 r25, r26 }
{ shl r5, r6, r7 ; cmpleu r15, r16, r17 ; st1 r25, r26 }
{ shl r5, r6, r7 ; cmpltsi r15, r16, 5 ; st4 r25, r26 }
{ shl r5, r6, r7 ; cmpne r15, r16, r17 }
{ shl r5, r6, r7 ; ill ; ld1u r25, r26 }
{ shl r5, r6, r7 ; jalr r15 ; ld1s r25, r26 }
{ shl r5, r6, r7 ; jr r15 ; ld2s r25, r26 }
{ shl r5, r6, r7 ; ld r25, r26 ; and r15, r16, r17 }
{ shl r5, r6, r7 ; ld r25, r26 ; subx r15, r16, r17 }
{ shl r5, r6, r7 ; ld1s r25, r26 ; shl3add r15, r16, r17 }
{ shl r5, r6, r7 ; ld1u r25, r26 ; nor r15, r16, r17 }
{ shl r5, r6, r7 ; ld2s r25, r26 ; jalrp r15 }
{ shl r5, r6, r7 ; ld2u r25, r26 ; cmpleu r15, r16, r17 }
{ shl r5, r6, r7 ; ld4s r25, r26 ; add r15, r16, r17 }
{ shl r5, r6, r7 ; ld4s r25, r26 ; shrsi r15, r16, 5 }
{ shl r5, r6, r7 ; ld4u r25, r26 ; shl r15, r16, r17 }
{ shl r5, r6, r7 ; lnk r15 ; ld4u r25, r26 }
{ shl r5, r6, r7 ; move r15, r16 ; ld4u r25, r26 }
{ shl r5, r6, r7 ; mz r15, r16, r17 ; ld4u r25, r26 }
{ shl r5, r6, r7 ; nor r15, r16, r17 ; prefetch_l1 r25 }
{ shl r5, r6, r7 ; prefetch r25 ; cmples r15, r16, r17 }
{ shl r5, r6, r7 ; prefetch_add_l1_fault r15, 5 }
{ shl r5, r6, r7 ; prefetch_l1 r25 ; shl2add r15, r16, r17 }
{ shl r5, r6, r7 ; prefetch_l1_fault r25 ; nop }
{ shl r5, r6, r7 ; prefetch_l2 r25 ; jalrp r15 }
{ shl r5, r6, r7 ; prefetch_l2_fault r25 ; cmplts r15, r16, r17 }
{ shl r5, r6, r7 ; prefetch_l3 r25 ; addx r15, r16, r17 }
{ shl r5, r6, r7 ; prefetch_l3 r25 ; shrui r15, r16, 5 }
{ shl r5, r6, r7 ; prefetch_l3_fault r25 ; shl2add r15, r16, r17 }
{ shl r5, r6, r7 ; rotli r15, r16, 5 ; prefetch r25 }
{ shl r5, r6, r7 ; shl1add r15, r16, r17 ; prefetch_l1 r25 }
{ shl r5, r6, r7 ; shl2add r15, r16, r17 ; prefetch_l2 r25 }
{ shl r5, r6, r7 ; shl3add r15, r16, r17 ; prefetch_l3 r25 }
{ shl r5, r6, r7 ; shli r15, r16, 5 ; st r25, r26 }
{ shl r5, r6, r7 ; shrsi r15, r16, 5 ; st r25, r26 }
{ shl r5, r6, r7 ; shrui r15, r16, 5 ; st2 r25, r26 }
{ shl r5, r6, r7 ; st r25, r26 ; shl2add r15, r16, r17 }
{ shl r5, r6, r7 ; st1 r25, r26 ; nop }
{ shl r5, r6, r7 ; st2 r25, r26 ; jalr r15 }
{ shl r5, r6, r7 ; st4 r25, r26 ; cmples r15, r16, r17 }
{ shl r5, r6, r7 ; st_add r15, r16, 5 }
{ shl r5, r6, r7 ; subx r15, r16, r17 ; prefetch_l3 r25 }
{ shl r5, r6, r7 ; v2cmpeqi r15, r16, 5 }
{ shl r5, r6, r7 ; xor r15, r16, r17 ; ld r25, r26 }
{ shl16insli r15, r16, 0x1234 ; cmpltsi r5, r6, 5 }
{ shl16insli r15, r16, 0x1234 ; moveli r5, 0x1234 }
{ shl16insli r15, r16, 0x1234 ; shl3addx r5, r6, r7 }
{ shl16insli r15, r16, 0x1234 ; v1dotpus r5, r6, r7 }
{ shl16insli r15, r16, 0x1234 ; v2int_l r5, r6, r7 }
{ shl16insli r5, r6, 0x1234 ; addi r15, r16, 5 }
{ shl16insli r5, r6, 0x1234 ; infol 0x1234 }
{ shl16insli r5, r6, 0x1234 ; mnz r15, r16, r17 }
{ shl16insli r5, r6, 0x1234 ; shrui r15, r16, 5 }
{ shl16insli r5, r6, 0x1234 ; v1mnz r15, r16, r17 }
{ shl16insli r5, r6, 0x1234 ; v2sub r15, r16, r17 }
{ shl1add r15, r16, r17 ; addi r5, r6, 5 ; ld4s r25, r26 }
{ shl1add r15, r16, r17 ; addxi r5, r6, 5 ; ld4u r25, r26 }
{ shl1add r15, r16, r17 ; andi r5, r6, 5 ; ld4u r25, r26 }
{ shl1add r15, r16, r17 ; cmoveqz r5, r6, r7 ; ld4s r25, r26 }
{ shl1add r15, r16, r17 ; cmpeq r5, r6, r7 ; prefetch r25 }
{ shl1add r15, r16, r17 ; cmples r5, r6, r7 ; prefetch_l1_fault r25 }
{ shl1add r15, r16, r17 ; cmplts r5, r6, r7 ; prefetch_l2_fault r25 }
{ shl1add r15, r16, r17 ; cmpltu r5, r6, r7 ; prefetch_l3_fault r25 }
{ shl1add r15, r16, r17 ; ctz r5, r6 ; ld4s r25, r26 }
{ shl1add r15, r16, r17 ; fnop ; st r25, r26 }
{ shl1add r15, r16, r17 ; info 19 ; prefetch_l2 r25 }
{ shl1add r15, r16, r17 ; ld r25, r26 ; mula_ls_ls r5, r6, r7 }
{ shl1add r15, r16, r17 ; ld1s r25, r26 ; cmoveqz r5, r6, r7 }
{ shl1add r15, r16, r17 ; ld1s r25, r26 ; shl2addx r5, r6, r7 }
{ shl1add r15, r16, r17 ; ld1u r25, r26 ; mul_hs_hs r5, r6, r7 }
{ shl1add r15, r16, r17 ; ld2s r25, r26 ; addi r5, r6, 5 }
{ shl1add r15, r16, r17 ; ld2s r25, r26 ; rotl r5, r6, r7 }
{ shl1add r15, r16, r17 ; ld2u r25, r26 ; fnop }
{ shl1add r15, r16, r17 ; ld2u r25, r26 ; tblidxb1 r5, r6 }
{ shl1add r15, r16, r17 ; ld4s r25, r26 ; nop }
{ shl1add r15, r16, r17 ; ld4u r25, r26 ; cmpleu r5, r6, r7 }
{ shl1add r15, r16, r17 ; ld4u r25, r26 ; shrsi r5, r6, 5 }
{ shl1add r15, r16, r17 ; move r5, r6 ; prefetch_l1_fault r25 }
{ shl1add r15, r16, r17 ; mul_hs_hs r5, r6, r7 ; prefetch_l2 r25 }
{ shl1add r15, r16, r17 ; mul_ls_ls r5, r6, r7 ; prefetch r25 }
{ shl1add r15, r16, r17 ; mula_hs_hs r5, r6, r7 ; prefetch_l1 r25 }
{ shl1add r15, r16, r17 ; mula_ls_ls r5, r6, r7 ; ld4s r25, r26 }
{ shl1add r15, r16, r17 ; mulax r5, r6, r7 ; ld4u r25, r26 }
{ shl1add r15, r16, r17 ; mz r5, r6, r7 ; prefetch_l1 r25 }
{ shl1add r15, r16, r17 ; nor r5, r6, r7 ; prefetch_l2 r25 }
{ shl1add r15, r16, r17 ; pcnt r5, r6 ; prefetch_l2_fault r25 }
{ shl1add r15, r16, r17 ; prefetch r25 ; mulax r5, r6, r7 }
{ shl1add r15, r16, r17 ; prefetch_l1 r25 ; cmpeq r5, r6, r7 }
{ shl1add r15, r16, r17 ; prefetch_l1 r25 ; shl3addx r5, r6, r7 }
{ shl1add r15, r16, r17 ; prefetch_l1_fault r25 ; mul_ls_ls r5, r6, r7 }
{ shl1add r15, r16, r17 ; prefetch_l2 r25 ; addxi r5, r6, 5 }
{ shl1add r15, r16, r17 ; prefetch_l2 r25 ; shl r5, r6, r7 }
{ shl1add r15, r16, r17 ; prefetch_l2_fault r25 ; info 19 }
{ shl1add r15, r16, r17 ; prefetch_l2_fault r25 ; tblidxb3 r5, r6 }
{ shl1add r15, r16, r17 ; prefetch_l3 r25 ; or r5, r6, r7 }
{ shl1add r15, r16, r17 ; prefetch_l3_fault r25 ; cmpltsi r5, r6, 5 }
{ shl1add r15, r16, r17 ; prefetch_l3_fault r25 ; shrui r5, r6, 5 }
{ shl1add r15, r16, r17 ; revbytes r5, r6 ; prefetch_l3 r25 }
{ shl1add r15, r16, r17 ; rotli r5, r6, 5 ; st r25, r26 }
{ shl1add r15, r16, r17 ; shl1add r5, r6, r7 ; st1 r25, r26 }
{ shl1add r15, r16, r17 ; shl2add r5, r6, r7 ; st4 r25, r26 }
{ shl1add r15, r16, r17 ; shl3addx r5, r6, r7 ; ld r25, r26 }
{ shl1add r15, r16, r17 ; shrs r5, r6, r7 ; ld r25, r26 }
{ shl1add r15, r16, r17 ; shru r5, r6, r7 ; ld1u r25, r26 }
{ shl1add r15, r16, r17 ; st r25, r26 ; addi r5, r6, 5 }
{ shl1add r15, r16, r17 ; st r25, r26 ; rotl r5, r6, r7 }
{ shl1add r15, r16, r17 ; st1 r25, r26 ; fnop }
{ shl1add r15, r16, r17 ; st1 r25, r26 ; tblidxb1 r5, r6 }
{ shl1add r15, r16, r17 ; st2 r25, r26 ; nop }
{ shl1add r15, r16, r17 ; st4 r25, r26 ; cmpleu r5, r6, r7 }
{ shl1add r15, r16, r17 ; st4 r25, r26 ; shrsi r5, r6, 5 }
{ shl1add r15, r16, r17 ; subx r5, r6, r7 ; prefetch_l2 r25 }
{ shl1add r15, r16, r17 ; tblidxb1 r5, r6 ; prefetch_l2_fault r25 }
{ shl1add r15, r16, r17 ; tblidxb3 r5, r6 ; prefetch_l3_fault r25 }
{ shl1add r15, r16, r17 ; v1mz r5, r6, r7 }
{ shl1add r15, r16, r17 ; v2packuc r5, r6, r7 }
{ shl1add r15, r16, r17 ; xor r5, r6, r7 ; st1 r25, r26 }
{ shl1add r5, r6, r7 ; addi r15, r16, 5 ; st2 r25, r26 }
{ shl1add r5, r6, r7 ; addxi r15, r16, 5 ; st4 r25, r26 }
{ shl1add r5, r6, r7 ; andi r15, r16, 5 ; st4 r25, r26 }
{ shl1add r5, r6, r7 ; cmpexch r15, r16, r17 }
{ shl1add r5, r6, r7 ; cmplts r15, r16, r17 ; ld r25, r26 }
{ shl1add r5, r6, r7 ; cmpltu r15, r16, r17 ; ld1u r25, r26 }
{ shl1add r5, r6, r7 ; dtlbpr r15 }
{ shl1add r5, r6, r7 ; ill ; ld4u r25, r26 }
{ shl1add r5, r6, r7 ; jalr r15 ; ld4s r25, r26 }
{ shl1add r5, r6, r7 ; jr r15 ; prefetch r25 }
{ shl1add r5, r6, r7 ; ld r25, r26 ; cmples r15, r16, r17 }
{ shl1add r5, r6, r7 ; ld1s r25, r26 ; add r15, r16, r17 }
{ shl1add r5, r6, r7 ; ld1s r25, r26 ; shrsi r15, r16, 5 }
{ shl1add r5, r6, r7 ; ld1u r25, r26 ; shl r15, r16, r17 }
{ shl1add r5, r6, r7 ; ld2s r25, r26 ; mnz r15, r16, r17 }
{ shl1add r5, r6, r7 ; ld2u r25, r26 ; cmpne r15, r16, r17 }
{ shl1add r5, r6, r7 ; ld4s r25, r26 ; and r15, r16, r17 }
{ shl1add r5, r6, r7 ; ld4s r25, r26 ; subx r15, r16, r17 }
{ shl1add r5, r6, r7 ; ld4u r25, r26 ; shl2addx r15, r16, r17 }
{ shl1add r5, r6, r7 ; lnk r15 ; prefetch_l2 r25 }
{ shl1add r5, r6, r7 ; move r15, r16 ; prefetch_l2 r25 }
{ shl1add r5, r6, r7 ; mz r15, r16, r17 ; prefetch_l2 r25 }
{ shl1add r5, r6, r7 ; nor r15, r16, r17 ; prefetch_l3 r25 }
{ shl1add r5, r6, r7 ; prefetch r25 ; cmpltu r15, r16, r17 }
{ shl1add r5, r6, r7 ; prefetch_add_l3_fault r15, 5 }
{ shl1add r5, r6, r7 ; prefetch_l1 r25 ; shli r15, r16, 5 }
{ shl1add r5, r6, r7 ; prefetch_l1_fault r25 ; rotli r15, r16, 5 }
{ shl1add r5, r6, r7 ; prefetch_l2 r25 ; mnz r15, r16, r17 }
{ shl1add r5, r6, r7 ; prefetch_l2_fault r25 ; fnop }
{ shl1add r5, r6, r7 ; prefetch_l3 r25 ; cmpeq r15, r16, r17 }
{ shl1add r5, r6, r7 ; prefetch_l3 r25 }
{ shl1add r5, r6, r7 ; prefetch_l3_fault r25 ; shli r15, r16, 5 }
{ shl1add r5, r6, r7 ; rotli r15, r16, 5 ; prefetch_l2_fault r25 }
{ shl1add r5, r6, r7 ; shl1add r15, r16, r17 ; prefetch_l3 r25 }
{ shl1add r5, r6, r7 ; shl2add r15, r16, r17 ; st r25, r26 }
{ shl1add r5, r6, r7 ; shl3add r15, r16, r17 ; st2 r25, r26 }
{ shl1add r5, r6, r7 ; shli r15, r16, 5 }
{ shl1add r5, r6, r7 ; shrsi r15, r16, 5 }
{ shl1add r5, r6, r7 ; shruxi r15, r16, 5 }
{ shl1add r5, r6, r7 ; st r25, r26 ; shli r15, r16, 5 }
{ shl1add r5, r6, r7 ; st1 r25, r26 ; rotli r15, r16, 5 }
{ shl1add r5, r6, r7 ; st2 r25, r26 ; lnk r15 }
{ shl1add r5, r6, r7 ; st4 r25, r26 ; cmpltu r15, r16, r17 }
{ shl1add r5, r6, r7 ; stnt2 r15, r16 }
{ shl1add r5, r6, r7 ; subx r15, r16, r17 ; st2 r25, r26 }
{ shl1add r5, r6, r7 ; v2cmpltsi r15, r16, 5 }
{ shl1add r5, r6, r7 ; xor r15, r16, r17 ; ld2u r25, r26 }
{ shl1addx r15, r16, r17 ; addi r5, r6, 5 ; ld4s r25, r26 }
{ shl1addx r15, r16, r17 ; addxi r5, r6, 5 ; ld4u r25, r26 }
{ shl1addx r15, r16, r17 ; andi r5, r6, 5 ; ld4u r25, r26 }
{ shl1addx r15, r16, r17 ; cmoveqz r5, r6, r7 ; ld4s r25, r26 }
{ shl1addx r15, r16, r17 ; cmpeq r5, r6, r7 ; prefetch r25 }
{ shl1addx r15, r16, r17 ; cmples r5, r6, r7 ; prefetch_l1_fault r25 }
{ shl1addx r15, r16, r17 ; cmplts r5, r6, r7 ; prefetch_l2_fault r25 }
{ shl1addx r15, r16, r17 ; cmpltu r5, r6, r7 ; prefetch_l3_fault r25 }
{ shl1addx r15, r16, r17 ; ctz r5, r6 ; ld4s r25, r26 }
{ shl1addx r15, r16, r17 ; fnop ; st r25, r26 }
{ shl1addx r15, r16, r17 ; info 19 ; prefetch_l2 r25 }
{ shl1addx r15, r16, r17 ; ld r25, r26 ; mula_ls_ls r5, r6, r7 }
{ shl1addx r15, r16, r17 ; ld1s r25, r26 ; cmoveqz r5, r6, r7 }
{ shl1addx r15, r16, r17 ; ld1s r25, r26 ; shl2addx r5, r6, r7 }
{ shl1addx r15, r16, r17 ; ld1u r25, r26 ; mul_hs_hs r5, r6, r7 }
{ shl1addx r15, r16, r17 ; ld2s r25, r26 ; addi r5, r6, 5 }
{ shl1addx r15, r16, r17 ; ld2s r25, r26 ; rotl r5, r6, r7 }
{ shl1addx r15, r16, r17 ; ld2u r25, r26 ; fnop }
{ shl1addx r15, r16, r17 ; ld2u r25, r26 ; tblidxb1 r5, r6 }
{ shl1addx r15, r16, r17 ; ld4s r25, r26 ; nop }
{ shl1addx r15, r16, r17 ; ld4u r25, r26 ; cmpleu r5, r6, r7 }
{ shl1addx r15, r16, r17 ; ld4u r25, r26 ; shrsi r5, r6, 5 }
{ shl1addx r15, r16, r17 ; move r5, r6 ; prefetch_l1_fault r25 }
{ shl1addx r15, r16, r17 ; mul_hs_hs r5, r6, r7 ; prefetch_l2 r25 }
{ shl1addx r15, r16, r17 ; mul_ls_ls r5, r6, r7 ; prefetch r25 }
{ shl1addx r15, r16, r17 ; mula_hs_hs r5, r6, r7 ; prefetch_l1 r25 }
{ shl1addx r15, r16, r17 ; mula_ls_ls r5, r6, r7 ; ld4s r25, r26 }
{ shl1addx r15, r16, r17 ; mulax r5, r6, r7 ; ld4u r25, r26 }
{ shl1addx r15, r16, r17 ; mz r5, r6, r7 ; prefetch_l1 r25 }
{ shl1addx r15, r16, r17 ; nor r5, r6, r7 ; prefetch_l2 r25 }
{ shl1addx r15, r16, r17 ; pcnt r5, r6 ; prefetch_l2_fault r25 }
{ shl1addx r15, r16, r17 ; prefetch r25 ; mulax r5, r6, r7 }
{ shl1addx r15, r16, r17 ; prefetch_l1 r25 ; cmpeq r5, r6, r7 }
{ shl1addx r15, r16, r17 ; prefetch_l1 r25 ; shl3addx r5, r6, r7 }
{ shl1addx r15, r16, r17 ; prefetch_l1_fault r25 ; mul_ls_ls r5, r6, r7 }
{ shl1addx r15, r16, r17 ; prefetch_l2 r25 ; addxi r5, r6, 5 }
{ shl1addx r15, r16, r17 ; prefetch_l2 r25 ; shl r5, r6, r7 }
{ shl1addx r15, r16, r17 ; prefetch_l2_fault r25 ; info 19 }
{ shl1addx r15, r16, r17 ; prefetch_l2_fault r25 ; tblidxb3 r5, r6 }
{ shl1addx r15, r16, r17 ; prefetch_l3 r25 ; or r5, r6, r7 }
{ shl1addx r15, r16, r17 ; prefetch_l3_fault r25 ; cmpltsi r5, r6, 5 }
{ shl1addx r15, r16, r17 ; prefetch_l3_fault r25 ; shrui r5, r6, 5 }
{ shl1addx r15, r16, r17 ; revbytes r5, r6 ; prefetch_l3 r25 }
{ shl1addx r15, r16, r17 ; rotli r5, r6, 5 ; st r25, r26 }
{ shl1addx r15, r16, r17 ; shl1add r5, r6, r7 ; st1 r25, r26 }
{ shl1addx r15, r16, r17 ; shl2add r5, r6, r7 ; st4 r25, r26 }
{ shl1addx r15, r16, r17 ; shl3addx r5, r6, r7 ; ld r25, r26 }
{ shl1addx r15, r16, r17 ; shrs r5, r6, r7 ; ld r25, r26 }
{ shl1addx r15, r16, r17 ; shru r5, r6, r7 ; ld1u r25, r26 }
{ shl1addx r15, r16, r17 ; st r25, r26 ; addi r5, r6, 5 }
{ shl1addx r15, r16, r17 ; st r25, r26 ; rotl r5, r6, r7 }
{ shl1addx r15, r16, r17 ; st1 r25, r26 ; fnop }
{ shl1addx r15, r16, r17 ; st1 r25, r26 ; tblidxb1 r5, r6 }
{ shl1addx r15, r16, r17 ; st2 r25, r26 ; nop }
{ shl1addx r15, r16, r17 ; st4 r25, r26 ; cmpleu r5, r6, r7 }
{ shl1addx r15, r16, r17 ; st4 r25, r26 ; shrsi r5, r6, 5 }
{ shl1addx r15, r16, r17 ; subx r5, r6, r7 ; prefetch_l2 r25 }
{ shl1addx r15, r16, r17 ; tblidxb1 r5, r6 ; prefetch_l2_fault r25 }
{ shl1addx r15, r16, r17 ; tblidxb3 r5, r6 ; prefetch_l3_fault r25 }
{ shl1addx r15, r16, r17 ; v1mz r5, r6, r7 }
{ shl1addx r15, r16, r17 ; v2packuc r5, r6, r7 }
{ shl1addx r15, r16, r17 ; xor r5, r6, r7 ; st1 r25, r26 }
{ shl1addx r5, r6, r7 ; addi r15, r16, 5 ; st2 r25, r26 }
{ shl1addx r5, r6, r7 ; addxi r15, r16, 5 ; st4 r25, r26 }
{ shl1addx r5, r6, r7 ; andi r15, r16, 5 ; st4 r25, r26 }
{ shl1addx r5, r6, r7 ; cmpexch r15, r16, r17 }
{ shl1addx r5, r6, r7 ; cmplts r15, r16, r17 ; ld r25, r26 }
{ shl1addx r5, r6, r7 ; cmpltu r15, r16, r17 ; ld1u r25, r26 }
{ shl1addx r5, r6, r7 ; dtlbpr r15 }
{ shl1addx r5, r6, r7 ; ill ; ld4u r25, r26 }
{ shl1addx r5, r6, r7 ; jalr r15 ; ld4s r25, r26 }
{ shl1addx r5, r6, r7 ; jr r15 ; prefetch r25 }
{ shl1addx r5, r6, r7 ; ld r25, r26 ; cmples r15, r16, r17 }
{ shl1addx r5, r6, r7 ; ld1s r25, r26 ; add r15, r16, r17 }
{ shl1addx r5, r6, r7 ; ld1s r25, r26 ; shrsi r15, r16, 5 }
{ shl1addx r5, r6, r7 ; ld1u r25, r26 ; shl r15, r16, r17 }
{ shl1addx r5, r6, r7 ; ld2s r25, r26 ; mnz r15, r16, r17 }
{ shl1addx r5, r6, r7 ; ld2u r25, r26 ; cmpne r15, r16, r17 }
{ shl1addx r5, r6, r7 ; ld4s r25, r26 ; and r15, r16, r17 }
{ shl1addx r5, r6, r7 ; ld4s r25, r26 ; subx r15, r16, r17 }
{ shl1addx r5, r6, r7 ; ld4u r25, r26 ; shl2addx r15, r16, r17 }
{ shl1addx r5, r6, r7 ; lnk r15 ; prefetch_l2 r25 }
{ shl1addx r5, r6, r7 ; move r15, r16 ; prefetch_l2 r25 }
{ shl1addx r5, r6, r7 ; mz r15, r16, r17 ; prefetch_l2 r25 }
{ shl1addx r5, r6, r7 ; nor r15, r16, r17 ; prefetch_l3 r25 }
{ shl1addx r5, r6, r7 ; prefetch r25 ; cmpltu r15, r16, r17 }
{ shl1addx r5, r6, r7 ; prefetch_add_l3_fault r15, 5 }
{ shl1addx r5, r6, r7 ; prefetch_l1 r25 ; shli r15, r16, 5 }
{ shl1addx r5, r6, r7 ; prefetch_l1_fault r25 ; rotli r15, r16, 5 }
{ shl1addx r5, r6, r7 ; prefetch_l2 r25 ; mnz r15, r16, r17 }
{ shl1addx r5, r6, r7 ; prefetch_l2_fault r25 ; fnop }
{ shl1addx r5, r6, r7 ; prefetch_l3 r25 ; cmpeq r15, r16, r17 }
{ shl1addx r5, r6, r7 ; prefetch_l3 r25 }
{ shl1addx r5, r6, r7 ; prefetch_l3_fault r25 ; shli r15, r16, 5 }
{ shl1addx r5, r6, r7 ; rotli r15, r16, 5 ; prefetch_l2_fault r25 }
{ shl1addx r5, r6, r7 ; shl1add r15, r16, r17 ; prefetch_l3 r25 }
{ shl1addx r5, r6, r7 ; shl2add r15, r16, r17 ; st r25, r26 }
{ shl1addx r5, r6, r7 ; shl3add r15, r16, r17 ; st2 r25, r26 }
{ shl1addx r5, r6, r7 ; shli r15, r16, 5 }
{ shl1addx r5, r6, r7 ; shrsi r15, r16, 5 }
{ shl1addx r5, r6, r7 ; shruxi r15, r16, 5 }
{ shl1addx r5, r6, r7 ; st r25, r26 ; shli r15, r16, 5 }
{ shl1addx r5, r6, r7 ; st1 r25, r26 ; rotli r15, r16, 5 }
{ shl1addx r5, r6, r7 ; st2 r25, r26 ; lnk r15 }
{ shl1addx r5, r6, r7 ; st4 r25, r26 ; cmpltu r15, r16, r17 }
{ shl1addx r5, r6, r7 ; stnt2 r15, r16 }
{ shl1addx r5, r6, r7 ; subx r15, r16, r17 ; st2 r25, r26 }
{ shl1addx r5, r6, r7 ; v2cmpltsi r15, r16, 5 }
{ shl1addx r5, r6, r7 ; xor r15, r16, r17 ; ld2u r25, r26 }
{ shl2add r15, r16, r17 ; addi r5, r6, 5 ; ld4s r25, r26 }
{ shl2add r15, r16, r17 ; addxi r5, r6, 5 ; ld4u r25, r26 }
{ shl2add r15, r16, r17 ; andi r5, r6, 5 ; ld4u r25, r26 }
{ shl2add r15, r16, r17 ; cmoveqz r5, r6, r7 ; ld4s r25, r26 }
{ shl2add r15, r16, r17 ; cmpeq r5, r6, r7 ; prefetch r25 }
{ shl2add r15, r16, r17 ; cmples r5, r6, r7 ; prefetch_l1_fault r25 }
{ shl2add r15, r16, r17 ; cmplts r5, r6, r7 ; prefetch_l2_fault r25 }
{ shl2add r15, r16, r17 ; cmpltu r5, r6, r7 ; prefetch_l3_fault r25 }
{ shl2add r15, r16, r17 ; ctz r5, r6 ; ld4s r25, r26 }
{ shl2add r15, r16, r17 ; fnop ; st r25, r26 }
{ shl2add r15, r16, r17 ; info 19 ; prefetch_l2 r25 }
{ shl2add r15, r16, r17 ; ld r25, r26 ; mula_ls_ls r5, r6, r7 }
{ shl2add r15, r16, r17 ; ld1s r25, r26 ; cmoveqz r5, r6, r7 }
{ shl2add r15, r16, r17 ; ld1s r25, r26 ; shl2addx r5, r6, r7 }
{ shl2add r15, r16, r17 ; ld1u r25, r26 ; mul_hs_hs r5, r6, r7 }
{ shl2add r15, r16, r17 ; ld2s r25, r26 ; addi r5, r6, 5 }
{ shl2add r15, r16, r17 ; ld2s r25, r26 ; rotl r5, r6, r7 }
{ shl2add r15, r16, r17 ; ld2u r25, r26 ; fnop }
{ shl2add r15, r16, r17 ; ld2u r25, r26 ; tblidxb1 r5, r6 }
{ shl2add r15, r16, r17 ; ld4s r25, r26 ; nop }
{ shl2add r15, r16, r17 ; ld4u r25, r26 ; cmpleu r5, r6, r7 }
{ shl2add r15, r16, r17 ; ld4u r25, r26 ; shrsi r5, r6, 5 }
{ shl2add r15, r16, r17 ; move r5, r6 ; prefetch_l1_fault r25 }
{ shl2add r15, r16, r17 ; mul_hs_hs r5, r6, r7 ; prefetch_l2 r25 }
{ shl2add r15, r16, r17 ; mul_ls_ls r5, r6, r7 ; prefetch r25 }
{ shl2add r15, r16, r17 ; mula_hs_hs r5, r6, r7 ; prefetch_l1 r25 }
{ shl2add r15, r16, r17 ; mula_ls_ls r5, r6, r7 ; ld4s r25, r26 }
{ shl2add r15, r16, r17 ; mulax r5, r6, r7 ; ld4u r25, r26 }
{ shl2add r15, r16, r17 ; mz r5, r6, r7 ; prefetch_l1 r25 }
{ shl2add r15, r16, r17 ; nor r5, r6, r7 ; prefetch_l2 r25 }
{ shl2add r15, r16, r17 ; pcnt r5, r6 ; prefetch_l2_fault r25 }
{ shl2add r15, r16, r17 ; prefetch r25 ; mulax r5, r6, r7 }
{ shl2add r15, r16, r17 ; prefetch_l1 r25 ; cmpeq r5, r6, r7 }
{ shl2add r15, r16, r17 ; prefetch_l1 r25 ; shl3addx r5, r6, r7 }
{ shl2add r15, r16, r17 ; prefetch_l1_fault r25 ; mul_ls_ls r5, r6, r7 }
{ shl2add r15, r16, r17 ; prefetch_l2 r25 ; addxi r5, r6, 5 }
{ shl2add r15, r16, r17 ; prefetch_l2 r25 ; shl r5, r6, r7 }
{ shl2add r15, r16, r17 ; prefetch_l2_fault r25 ; info 19 }
{ shl2add r15, r16, r17 ; prefetch_l2_fault r25 ; tblidxb3 r5, r6 }
{ shl2add r15, r16, r17 ; prefetch_l3 r25 ; or r5, r6, r7 }
{ shl2add r15, r16, r17 ; prefetch_l3_fault r25 ; cmpltsi r5, r6, 5 }
{ shl2add r15, r16, r17 ; prefetch_l3_fault r25 ; shrui r5, r6, 5 }
{ shl2add r15, r16, r17 ; revbytes r5, r6 ; prefetch_l3 r25 }
{ shl2add r15, r16, r17 ; rotli r5, r6, 5 ; st r25, r26 }
{ shl2add r15, r16, r17 ; shl1add r5, r6, r7 ; st1 r25, r26 }
{ shl2add r15, r16, r17 ; shl2add r5, r6, r7 ; st4 r25, r26 }
{ shl2add r15, r16, r17 ; shl3addx r5, r6, r7 ; ld r25, r26 }
{ shl2add r15, r16, r17 ; shrs r5, r6, r7 ; ld r25, r26 }
{ shl2add r15, r16, r17 ; shru r5, r6, r7 ; ld1u r25, r26 }
{ shl2add r15, r16, r17 ; st r25, r26 ; addi r5, r6, 5 }
{ shl2add r15, r16, r17 ; st r25, r26 ; rotl r5, r6, r7 }
{ shl2add r15, r16, r17 ; st1 r25, r26 ; fnop }
{ shl2add r15, r16, r17 ; st1 r25, r26 ; tblidxb1 r5, r6 }
{ shl2add r15, r16, r17 ; st2 r25, r26 ; nop }
{ shl2add r15, r16, r17 ; st4 r25, r26 ; cmpleu r5, r6, r7 }
{ shl2add r15, r16, r17 ; st4 r25, r26 ; shrsi r5, r6, 5 }
{ shl2add r15, r16, r17 ; subx r5, r6, r7 ; prefetch_l2 r25 }
{ shl2add r15, r16, r17 ; tblidxb1 r5, r6 ; prefetch_l2_fault r25 }
{ shl2add r15, r16, r17 ; tblidxb3 r5, r6 ; prefetch_l3_fault r25 }
{ shl2add r15, r16, r17 ; v1mz r5, r6, r7 }
{ shl2add r15, r16, r17 ; v2packuc r5, r6, r7 }
{ shl2add r15, r16, r17 ; xor r5, r6, r7 ; st1 r25, r26 }
{ shl2add r5, r6, r7 ; addi r15, r16, 5 ; st2 r25, r26 }
{ shl2add r5, r6, r7 ; addxi r15, r16, 5 ; st4 r25, r26 }
{ shl2add r5, r6, r7 ; andi r15, r16, 5 ; st4 r25, r26 }
{ shl2add r5, r6, r7 ; cmpexch r15, r16, r17 }
{ shl2add r5, r6, r7 ; cmplts r15, r16, r17 ; ld r25, r26 }
{ shl2add r5, r6, r7 ; cmpltu r15, r16, r17 ; ld1u r25, r26 }
{ shl2add r5, r6, r7 ; dtlbpr r15 }
{ shl2add r5, r6, r7 ; ill ; ld4u r25, r26 }
{ shl2add r5, r6, r7 ; jalr r15 ; ld4s r25, r26 }
{ shl2add r5, r6, r7 ; jr r15 ; prefetch r25 }
{ shl2add r5, r6, r7 ; ld r25, r26 ; cmples r15, r16, r17 }
{ shl2add r5, r6, r7 ; ld1s r25, r26 ; add r15, r16, r17 }
{ shl2add r5, r6, r7 ; ld1s r25, r26 ; shrsi r15, r16, 5 }
{ shl2add r5, r6, r7 ; ld1u r25, r26 ; shl r15, r16, r17 }
{ shl2add r5, r6, r7 ; ld2s r25, r26 ; mnz r15, r16, r17 }
{ shl2add r5, r6, r7 ; ld2u r25, r26 ; cmpne r15, r16, r17 }
{ shl2add r5, r6, r7 ; ld4s r25, r26 ; and r15, r16, r17 }
{ shl2add r5, r6, r7 ; ld4s r25, r26 ; subx r15, r16, r17 }
{ shl2add r5, r6, r7 ; ld4u r25, r26 ; shl2addx r15, r16, r17 }
{ shl2add r5, r6, r7 ; lnk r15 ; prefetch_l2 r25 }
{ shl2add r5, r6, r7 ; move r15, r16 ; prefetch_l2 r25 }
{ shl2add r5, r6, r7 ; mz r15, r16, r17 ; prefetch_l2 r25 }
{ shl2add r5, r6, r7 ; nor r15, r16, r17 ; prefetch_l3 r25 }
{ shl2add r5, r6, r7 ; prefetch r25 ; cmpltu r15, r16, r17 }
{ shl2add r5, r6, r7 ; prefetch_add_l3_fault r15, 5 }
{ shl2add r5, r6, r7 ; prefetch_l1 r25 ; shli r15, r16, 5 }
{ shl2add r5, r6, r7 ; prefetch_l1_fault r25 ; rotli r15, r16, 5 }
{ shl2add r5, r6, r7 ; prefetch_l2 r25 ; mnz r15, r16, r17 }
{ shl2add r5, r6, r7 ; prefetch_l2_fault r25 ; fnop }
{ shl2add r5, r6, r7 ; prefetch_l3 r25 ; cmpeq r15, r16, r17 }
{ shl2add r5, r6, r7 ; prefetch_l3 r25 }
{ shl2add r5, r6, r7 ; prefetch_l3_fault r25 ; shli r15, r16, 5 }
{ shl2add r5, r6, r7 ; rotli r15, r16, 5 ; prefetch_l2_fault r25 }
{ shl2add r5, r6, r7 ; shl1add r15, r16, r17 ; prefetch_l3 r25 }
{ shl2add r5, r6, r7 ; shl2add r15, r16, r17 ; st r25, r26 }
{ shl2add r5, r6, r7 ; shl3add r15, r16, r17 ; st2 r25, r26 }
{ shl2add r5, r6, r7 ; shli r15, r16, 5 }
{ shl2add r5, r6, r7 ; shrsi r15, r16, 5 }
{ shl2add r5, r6, r7 ; shruxi r15, r16, 5 }
{ shl2add r5, r6, r7 ; st r25, r26 ; shli r15, r16, 5 }
{ shl2add r5, r6, r7 ; st1 r25, r26 ; rotli r15, r16, 5 }
{ shl2add r5, r6, r7 ; st2 r25, r26 ; lnk r15 }
{ shl2add r5, r6, r7 ; st4 r25, r26 ; cmpltu r15, r16, r17 }
{ shl2add r5, r6, r7 ; stnt2 r15, r16 }
{ shl2add r5, r6, r7 ; subx r15, r16, r17 ; st2 r25, r26 }
{ shl2add r5, r6, r7 ; v2cmpltsi r15, r16, 5 }
{ shl2add r5, r6, r7 ; xor r15, r16, r17 ; ld2u r25, r26 }
{ shl2addx r15, r16, r17 ; addi r5, r6, 5 ; ld4s r25, r26 }
{ shl2addx r15, r16, r17 ; addxi r5, r6, 5 ; ld4u r25, r26 }
{ shl2addx r15, r16, r17 ; andi r5, r6, 5 ; ld4u r25, r26 }
{ shl2addx r15, r16, r17 ; cmoveqz r5, r6, r7 ; ld4s r25, r26 }
{ shl2addx r15, r16, r17 ; cmpeq r5, r6, r7 ; prefetch r25 }
{ shl2addx r15, r16, r17 ; cmples r5, r6, r7 ; prefetch_l1_fault r25 }
{ shl2addx r15, r16, r17 ; cmplts r5, r6, r7 ; prefetch_l2_fault r25 }
{ shl2addx r15, r16, r17 ; cmpltu r5, r6, r7 ; prefetch_l3_fault r25 }
{ shl2addx r15, r16, r17 ; ctz r5, r6 ; ld4s r25, r26 }
{ shl2addx r15, r16, r17 ; fnop ; st r25, r26 }
{ shl2addx r15, r16, r17 ; info 19 ; prefetch_l2 r25 }
{ shl2addx r15, r16, r17 ; ld r25, r26 ; mula_ls_ls r5, r6, r7 }
{ shl2addx r15, r16, r17 ; ld1s r25, r26 ; cmoveqz r5, r6, r7 }
{ shl2addx r15, r16, r17 ; ld1s r25, r26 ; shl2addx r5, r6, r7 }
{ shl2addx r15, r16, r17 ; ld1u r25, r26 ; mul_hs_hs r5, r6, r7 }
{ shl2addx r15, r16, r17 ; ld2s r25, r26 ; addi r5, r6, 5 }
{ shl2addx r15, r16, r17 ; ld2s r25, r26 ; rotl r5, r6, r7 }
{ shl2addx r15, r16, r17 ; ld2u r25, r26 ; fnop }
{ shl2addx r15, r16, r17 ; ld2u r25, r26 ; tblidxb1 r5, r6 }
{ shl2addx r15, r16, r17 ; ld4s r25, r26 ; nop }
{ shl2addx r15, r16, r17 ; ld4u r25, r26 ; cmpleu r5, r6, r7 }
{ shl2addx r15, r16, r17 ; ld4u r25, r26 ; shrsi r5, r6, 5 }
{ shl2addx r15, r16, r17 ; move r5, r6 ; prefetch_l1_fault r25 }
{ shl2addx r15, r16, r17 ; mul_hs_hs r5, r6, r7 ; prefetch_l2 r25 }
{ shl2addx r15, r16, r17 ; mul_ls_ls r5, r6, r7 ; prefetch r25 }
{ shl2addx r15, r16, r17 ; mula_hs_hs r5, r6, r7 ; prefetch_l1 r25 }
{ shl2addx r15, r16, r17 ; mula_ls_ls r5, r6, r7 ; ld4s r25, r26 }
{ shl2addx r15, r16, r17 ; mulax r5, r6, r7 ; ld4u r25, r26 }
{ shl2addx r15, r16, r17 ; mz r5, r6, r7 ; prefetch_l1 r25 }
{ shl2addx r15, r16, r17 ; nor r5, r6, r7 ; prefetch_l2 r25 }
{ shl2addx r15, r16, r17 ; pcnt r5, r6 ; prefetch_l2_fault r25 }
{ shl2addx r15, r16, r17 ; prefetch r25 ; mulax r5, r6, r7 }
{ shl2addx r15, r16, r17 ; prefetch_l1 r25 ; cmpeq r5, r6, r7 }
{ shl2addx r15, r16, r17 ; prefetch_l1 r25 ; shl3addx r5, r6, r7 }
{ shl2addx r15, r16, r17 ; prefetch_l1_fault r25 ; mul_ls_ls r5, r6, r7 }
{ shl2addx r15, r16, r17 ; prefetch_l2 r25 ; addxi r5, r6, 5 }
{ shl2addx r15, r16, r17 ; prefetch_l2 r25 ; shl r5, r6, r7 }
{ shl2addx r15, r16, r17 ; prefetch_l2_fault r25 ; info 19 }
{ shl2addx r15, r16, r17 ; prefetch_l2_fault r25 ; tblidxb3 r5, r6 }
{ shl2addx r15, r16, r17 ; prefetch_l3 r25 ; or r5, r6, r7 }
{ shl2addx r15, r16, r17 ; prefetch_l3_fault r25 ; cmpltsi r5, r6, 5 }
{ shl2addx r15, r16, r17 ; prefetch_l3_fault r25 ; shrui r5, r6, 5 }
{ shl2addx r15, r16, r17 ; revbytes r5, r6 ; prefetch_l3 r25 }
{ shl2addx r15, r16, r17 ; rotli r5, r6, 5 ; st r25, r26 }
{ shl2addx r15, r16, r17 ; shl1add r5, r6, r7 ; st1 r25, r26 }
{ shl2addx r15, r16, r17 ; shl2add r5, r6, r7 ; st4 r25, r26 }
{ shl2addx r15, r16, r17 ; shl3addx r5, r6, r7 ; ld r25, r26 }
{ shl2addx r15, r16, r17 ; shrs r5, r6, r7 ; ld r25, r26 }
{ shl2addx r15, r16, r17 ; shru r5, r6, r7 ; ld1u r25, r26 }
{ shl2addx r15, r16, r17 ; st r25, r26 ; addi r5, r6, 5 }
{ shl2addx r15, r16, r17 ; st r25, r26 ; rotl r5, r6, r7 }
{ shl2addx r15, r16, r17 ; st1 r25, r26 ; fnop }
{ shl2addx r15, r16, r17 ; st1 r25, r26 ; tblidxb1 r5, r6 }
{ shl2addx r15, r16, r17 ; st2 r25, r26 ; nop }
{ shl2addx r15, r16, r17 ; st4 r25, r26 ; cmpleu r5, r6, r7 }
{ shl2addx r15, r16, r17 ; st4 r25, r26 ; shrsi r5, r6, 5 }
{ shl2addx r15, r16, r17 ; subx r5, r6, r7 ; prefetch_l2 r25 }
{ shl2addx r15, r16, r17 ; tblidxb1 r5, r6 ; prefetch_l2_fault r25 }
{ shl2addx r15, r16, r17 ; tblidxb3 r5, r6 ; prefetch_l3_fault r25 }
{ shl2addx r15, r16, r17 ; v1mz r5, r6, r7 }
{ shl2addx r15, r16, r17 ; v2packuc r5, r6, r7 }
{ shl2addx r15, r16, r17 ; xor r5, r6, r7 ; st1 r25, r26 }
{ shl2addx r5, r6, r7 ; addi r15, r16, 5 ; st2 r25, r26 }
{ shl2addx r5, r6, r7 ; addxi r15, r16, 5 ; st4 r25, r26 }
{ shl2addx r5, r6, r7 ; andi r15, r16, 5 ; st4 r25, r26 }
{ shl2addx r5, r6, r7 ; cmpexch r15, r16, r17 }
{ shl2addx r5, r6, r7 ; cmplts r15, r16, r17 ; ld r25, r26 }
{ shl2addx r5, r6, r7 ; cmpltu r15, r16, r17 ; ld1u r25, r26 }
{ shl2addx r5, r6, r7 ; dtlbpr r15 }
{ shl2addx r5, r6, r7 ; ill ; ld4u r25, r26 }
{ shl2addx r5, r6, r7 ; jalr r15 ; ld4s r25, r26 }
{ shl2addx r5, r6, r7 ; jr r15 ; prefetch r25 }
{ shl2addx r5, r6, r7 ; ld r25, r26 ; cmples r15, r16, r17 }
{ shl2addx r5, r6, r7 ; ld1s r25, r26 ; add r15, r16, r17 }
{ shl2addx r5, r6, r7 ; ld1s r25, r26 ; shrsi r15, r16, 5 }
{ shl2addx r5, r6, r7 ; ld1u r25, r26 ; shl r15, r16, r17 }
{ shl2addx r5, r6, r7 ; ld2s r25, r26 ; mnz r15, r16, r17 }
{ shl2addx r5, r6, r7 ; ld2u r25, r26 ; cmpne r15, r16, r17 }
{ shl2addx r5, r6, r7 ; ld4s r25, r26 ; and r15, r16, r17 }
{ shl2addx r5, r6, r7 ; ld4s r25, r26 ; subx r15, r16, r17 }
{ shl2addx r5, r6, r7 ; ld4u r25, r26 ; shl2addx r15, r16, r17 }
{ shl2addx r5, r6, r7 ; lnk r15 ; prefetch_l2 r25 }
{ shl2addx r5, r6, r7 ; move r15, r16 ; prefetch_l2 r25 }
{ shl2addx r5, r6, r7 ; mz r15, r16, r17 ; prefetch_l2 r25 }
{ shl2addx r5, r6, r7 ; nor r15, r16, r17 ; prefetch_l3 r25 }
{ shl2addx r5, r6, r7 ; prefetch r25 ; cmpltu r15, r16, r17 }
{ shl2addx r5, r6, r7 ; prefetch_add_l3_fault r15, 5 }
{ shl2addx r5, r6, r7 ; prefetch_l1 r25 ; shli r15, r16, 5 }
{ shl2addx r5, r6, r7 ; prefetch_l1_fault r25 ; rotli r15, r16, 5 }
{ shl2addx r5, r6, r7 ; prefetch_l2 r25 ; mnz r15, r16, r17 }
{ shl2addx r5, r6, r7 ; prefetch_l2_fault r25 ; fnop }
{ shl2addx r5, r6, r7 ; prefetch_l3 r25 ; cmpeq r15, r16, r17 }
{ shl2addx r5, r6, r7 ; prefetch_l3 r25 }
{ shl2addx r5, r6, r7 ; prefetch_l3_fault r25 ; shli r15, r16, 5 }
{ shl2addx r5, r6, r7 ; rotli r15, r16, 5 ; prefetch_l2_fault r25 }
{ shl2addx r5, r6, r7 ; shl1add r15, r16, r17 ; prefetch_l3 r25 }
{ shl2addx r5, r6, r7 ; shl2add r15, r16, r17 ; st r25, r26 }
{ shl2addx r5, r6, r7 ; shl3add r15, r16, r17 ; st2 r25, r26 }
{ shl2addx r5, r6, r7 ; shli r15, r16, 5 }
{ shl2addx r5, r6, r7 ; shrsi r15, r16, 5 }
{ shl2addx r5, r6, r7 ; shruxi r15, r16, 5 }
{ shl2addx r5, r6, r7 ; st r25, r26 ; shli r15, r16, 5 }
{ shl2addx r5, r6, r7 ; st1 r25, r26 ; rotli r15, r16, 5 }
{ shl2addx r5, r6, r7 ; st2 r25, r26 ; lnk r15 }
{ shl2addx r5, r6, r7 ; st4 r25, r26 ; cmpltu r15, r16, r17 }
{ shl2addx r5, r6, r7 ; stnt2 r15, r16 }
{ shl2addx r5, r6, r7 ; subx r15, r16, r17 ; st2 r25, r26 }
{ shl2addx r5, r6, r7 ; v2cmpltsi r15, r16, 5 }
{ shl2addx r5, r6, r7 ; xor r15, r16, r17 ; ld2u r25, r26 }
{ shl3add r15, r16, r17 ; addi r5, r6, 5 ; ld4s r25, r26 }
{ shl3add r15, r16, r17 ; addxi r5, r6, 5 ; ld4u r25, r26 }
{ shl3add r15, r16, r17 ; andi r5, r6, 5 ; ld4u r25, r26 }
{ shl3add r15, r16, r17 ; cmoveqz r5, r6, r7 ; ld4s r25, r26 }
{ shl3add r15, r16, r17 ; cmpeq r5, r6, r7 ; prefetch r25 }
{ shl3add r15, r16, r17 ; cmples r5, r6, r7 ; prefetch_l1_fault r25 }
{ shl3add r15, r16, r17 ; cmplts r5, r6, r7 ; prefetch_l2_fault r25 }
{ shl3add r15, r16, r17 ; cmpltu r5, r6, r7 ; prefetch_l3_fault r25 }
{ shl3add r15, r16, r17 ; ctz r5, r6 ; ld4s r25, r26 }
{ shl3add r15, r16, r17 ; fnop ; st r25, r26 }
{ shl3add r15, r16, r17 ; info 19 ; prefetch_l2 r25 }
{ shl3add r15, r16, r17 ; ld r25, r26 ; mula_ls_ls r5, r6, r7 }
{ shl3add r15, r16, r17 ; ld1s r25, r26 ; cmoveqz r5, r6, r7 }
{ shl3add r15, r16, r17 ; ld1s r25, r26 ; shl2addx r5, r6, r7 }
{ shl3add r15, r16, r17 ; ld1u r25, r26 ; mul_hs_hs r5, r6, r7 }
{ shl3add r15, r16, r17 ; ld2s r25, r26 ; addi r5, r6, 5 }
{ shl3add r15, r16, r17 ; ld2s r25, r26 ; rotl r5, r6, r7 }
{ shl3add r15, r16, r17 ; ld2u r25, r26 ; fnop }
{ shl3add r15, r16, r17 ; ld2u r25, r26 ; tblidxb1 r5, r6 }
{ shl3add r15, r16, r17 ; ld4s r25, r26 ; nop }
{ shl3add r15, r16, r17 ; ld4u r25, r26 ; cmpleu r5, r6, r7 }
{ shl3add r15, r16, r17 ; ld4u r25, r26 ; shrsi r5, r6, 5 }
{ shl3add r15, r16, r17 ; move r5, r6 ; prefetch_l1_fault r25 }
{ shl3add r15, r16, r17 ; mul_hs_hs r5, r6, r7 ; prefetch_l2 r25 }
{ shl3add r15, r16, r17 ; mul_ls_ls r5, r6, r7 ; prefetch r25 }
{ shl3add r15, r16, r17 ; mula_hs_hs r5, r6, r7 ; prefetch_l1 r25 }
{ shl3add r15, r16, r17 ; mula_ls_ls r5, r6, r7 ; ld4s r25, r26 }
{ shl3add r15, r16, r17 ; mulax r5, r6, r7 ; ld4u r25, r26 }
{ shl3add r15, r16, r17 ; mz r5, r6, r7 ; prefetch_l1 r25 }
{ shl3add r15, r16, r17 ; nor r5, r6, r7 ; prefetch_l2 r25 }
{ shl3add r15, r16, r17 ; pcnt r5, r6 ; prefetch_l2_fault r25 }
{ shl3add r15, r16, r17 ; prefetch r25 ; mulax r5, r6, r7 }
{ shl3add r15, r16, r17 ; prefetch_l1 r25 ; cmpeq r5, r6, r7 }
{ shl3add r15, r16, r17 ; prefetch_l1 r25 ; shl3addx r5, r6, r7 }
{ shl3add r15, r16, r17 ; prefetch_l1_fault r25 ; mul_ls_ls r5, r6, r7 }
{ shl3add r15, r16, r17 ; prefetch_l2 r25 ; addxi r5, r6, 5 }
{ shl3add r15, r16, r17 ; prefetch_l2 r25 ; shl r5, r6, r7 }
{ shl3add r15, r16, r17 ; prefetch_l2_fault r25 ; info 19 }
{ shl3add r15, r16, r17 ; prefetch_l2_fault r25 ; tblidxb3 r5, r6 }
{ shl3add r15, r16, r17 ; prefetch_l3 r25 ; or r5, r6, r7 }
{ shl3add r15, r16, r17 ; prefetch_l3_fault r25 ; cmpltsi r5, r6, 5 }
{ shl3add r15, r16, r17 ; prefetch_l3_fault r25 ; shrui r5, r6, 5 }
{ shl3add r15, r16, r17 ; revbytes r5, r6 ; prefetch_l3 r25 }
{ shl3add r15, r16, r17 ; rotli r5, r6, 5 ; st r25, r26 }
{ shl3add r15, r16, r17 ; shl1add r5, r6, r7 ; st1 r25, r26 }
{ shl3add r15, r16, r17 ; shl2add r5, r6, r7 ; st4 r25, r26 }
{ shl3add r15, r16, r17 ; shl3addx r5, r6, r7 ; ld r25, r26 }
{ shl3add r15, r16, r17 ; shrs r5, r6, r7 ; ld r25, r26 }
{ shl3add r15, r16, r17 ; shru r5, r6, r7 ; ld1u r25, r26 }
{ shl3add r15, r16, r17 ; st r25, r26 ; addi r5, r6, 5 }
{ shl3add r15, r16, r17 ; st r25, r26 ; rotl r5, r6, r7 }
{ shl3add r15, r16, r17 ; st1 r25, r26 ; fnop }
{ shl3add r15, r16, r17 ; st1 r25, r26 ; tblidxb1 r5, r6 }
{ shl3add r15, r16, r17 ; st2 r25, r26 ; nop }
{ shl3add r15, r16, r17 ; st4 r25, r26 ; cmpleu r5, r6, r7 }
{ shl3add r15, r16, r17 ; st4 r25, r26 ; shrsi r5, r6, 5 }
{ shl3add r15, r16, r17 ; subx r5, r6, r7 ; prefetch_l2 r25 }
{ shl3add r15, r16, r17 ; tblidxb1 r5, r6 ; prefetch_l2_fault r25 }
{ shl3add r15, r16, r17 ; tblidxb3 r5, r6 ; prefetch_l3_fault r25 }
{ shl3add r15, r16, r17 ; v1mz r5, r6, r7 }
{ shl3add r15, r16, r17 ; v2packuc r5, r6, r7 }
{ shl3add r15, r16, r17 ; xor r5, r6, r7 ; st1 r25, r26 }
{ shl3add r5, r6, r7 ; addi r15, r16, 5 ; st2 r25, r26 }
{ shl3add r5, r6, r7 ; addxi r15, r16, 5 ; st4 r25, r26 }
{ shl3add r5, r6, r7 ; andi r15, r16, 5 ; st4 r25, r26 }
{ shl3add r5, r6, r7 ; cmpexch r15, r16, r17 }
{ shl3add r5, r6, r7 ; cmplts r15, r16, r17 ; ld r25, r26 }
{ shl3add r5, r6, r7 ; cmpltu r15, r16, r17 ; ld1u r25, r26 }
{ shl3add r5, r6, r7 ; dtlbpr r15 }
{ shl3add r5, r6, r7 ; ill ; ld4u r25, r26 }
{ shl3add r5, r6, r7 ; jalr r15 ; ld4s r25, r26 }
{ shl3add r5, r6, r7 ; jr r15 ; prefetch r25 }
{ shl3add r5, r6, r7 ; ld r25, r26 ; cmples r15, r16, r17 }
{ shl3add r5, r6, r7 ; ld1s r25, r26 ; add r15, r16, r17 }
{ shl3add r5, r6, r7 ; ld1s r25, r26 ; shrsi r15, r16, 5 }
{ shl3add r5, r6, r7 ; ld1u r25, r26 ; shl r15, r16, r17 }
{ shl3add r5, r6, r7 ; ld2s r25, r26 ; mnz r15, r16, r17 }
{ shl3add r5, r6, r7 ; ld2u r25, r26 ; cmpne r15, r16, r17 }
{ shl3add r5, r6, r7 ; ld4s r25, r26 ; and r15, r16, r17 }
{ shl3add r5, r6, r7 ; ld4s r25, r26 ; subx r15, r16, r17 }
{ shl3add r5, r6, r7 ; ld4u r25, r26 ; shl2addx r15, r16, r17 }
{ shl3add r5, r6, r7 ; lnk r15 ; prefetch_l2 r25 }
{ shl3add r5, r6, r7 ; move r15, r16 ; prefetch_l2 r25 }
{ shl3add r5, r6, r7 ; mz r15, r16, r17 ; prefetch_l2 r25 }
{ shl3add r5, r6, r7 ; nor r15, r16, r17 ; prefetch_l3 r25 }
{ shl3add r5, r6, r7 ; prefetch r25 ; cmpltu r15, r16, r17 }
{ shl3add r5, r6, r7 ; prefetch_add_l3_fault r15, 5 }
{ shl3add r5, r6, r7 ; prefetch_l1 r25 ; shli r15, r16, 5 }
{ shl3add r5, r6, r7 ; prefetch_l1_fault r25 ; rotli r15, r16, 5 }
{ shl3add r5, r6, r7 ; prefetch_l2 r25 ; mnz r15, r16, r17 }
{ shl3add r5, r6, r7 ; prefetch_l2_fault r25 ; fnop }
{ shl3add r5, r6, r7 ; prefetch_l3 r25 ; cmpeq r15, r16, r17 }
{ shl3add r5, r6, r7 ; prefetch_l3 r25 }
{ shl3add r5, r6, r7 ; prefetch_l3_fault r25 ; shli r15, r16, 5 }
{ shl3add r5, r6, r7 ; rotli r15, r16, 5 ; prefetch_l2_fault r25 }
{ shl3add r5, r6, r7 ; shl1add r15, r16, r17 ; prefetch_l3 r25 }
{ shl3add r5, r6, r7 ; shl2add r15, r16, r17 ; st r25, r26 }
{ shl3add r5, r6, r7 ; shl3add r15, r16, r17 ; st2 r25, r26 }
{ shl3add r5, r6, r7 ; shli r15, r16, 5 }
{ shl3add r5, r6, r7 ; shrsi r15, r16, 5 }
{ shl3add r5, r6, r7 ; shruxi r15, r16, 5 }
{ shl3add r5, r6, r7 ; st r25, r26 ; shli r15, r16, 5 }
{ shl3add r5, r6, r7 ; st1 r25, r26 ; rotli r15, r16, 5 }
{ shl3add r5, r6, r7 ; st2 r25, r26 ; lnk r15 }
{ shl3add r5, r6, r7 ; st4 r25, r26 ; cmpltu r15, r16, r17 }
{ shl3add r5, r6, r7 ; stnt2 r15, r16 }
{ shl3add r5, r6, r7 ; subx r15, r16, r17 ; st2 r25, r26 }
{ shl3add r5, r6, r7 ; v2cmpltsi r15, r16, 5 }
{ shl3add r5, r6, r7 ; xor r15, r16, r17 ; ld2u r25, r26 }
{ shl3addx r15, r16, r17 ; addi r5, r6, 5 ; ld4s r25, r26 }
{ shl3addx r15, r16, r17 ; addxi r5, r6, 5 ; ld4u r25, r26 }
{ shl3addx r15, r16, r17 ; andi r5, r6, 5 ; ld4u r25, r26 }
{ shl3addx r15, r16, r17 ; cmoveqz r5, r6, r7 ; ld4s r25, r26 }
{ shl3addx r15, r16, r17 ; cmpeq r5, r6, r7 ; prefetch r25 }
{ shl3addx r15, r16, r17 ; cmples r5, r6, r7 ; prefetch_l1_fault r25 }
{ shl3addx r15, r16, r17 ; cmplts r5, r6, r7 ; prefetch_l2_fault r25 }
{ shl3addx r15, r16, r17 ; cmpltu r5, r6, r7 ; prefetch_l3_fault r25 }
{ shl3addx r15, r16, r17 ; ctz r5, r6 ; ld4s r25, r26 }
{ shl3addx r15, r16, r17 ; fnop ; st r25, r26 }
{ shl3addx r15, r16, r17 ; info 19 ; prefetch_l2 r25 }
{ shl3addx r15, r16, r17 ; ld r25, r26 ; mula_ls_ls r5, r6, r7 }
{ shl3addx r15, r16, r17 ; ld1s r25, r26 ; cmoveqz r5, r6, r7 }
{ shl3addx r15, r16, r17 ; ld1s r25, r26 ; shl2addx r5, r6, r7 }
{ shl3addx r15, r16, r17 ; ld1u r25, r26 ; mul_hs_hs r5, r6, r7 }
{ shl3addx r15, r16, r17 ; ld2s r25, r26 ; addi r5, r6, 5 }
{ shl3addx r15, r16, r17 ; ld2s r25, r26 ; rotl r5, r6, r7 }
{ shl3addx r15, r16, r17 ; ld2u r25, r26 ; fnop }
{ shl3addx r15, r16, r17 ; ld2u r25, r26 ; tblidxb1 r5, r6 }
{ shl3addx r15, r16, r17 ; ld4s r25, r26 ; nop }
{ shl3addx r15, r16, r17 ; ld4u r25, r26 ; cmpleu r5, r6, r7 }
{ shl3addx r15, r16, r17 ; ld4u r25, r26 ; shrsi r5, r6, 5 }
{ shl3addx r15, r16, r17 ; move r5, r6 ; prefetch_l1_fault r25 }
{ shl3addx r15, r16, r17 ; mul_hs_hs r5, r6, r7 ; prefetch_l2 r25 }
{ shl3addx r15, r16, r17 ; mul_ls_ls r5, r6, r7 ; prefetch r25 }
{ shl3addx r15, r16, r17 ; mula_hs_hs r5, r6, r7 ; prefetch_l1 r25 }
{ shl3addx r15, r16, r17 ; mula_ls_ls r5, r6, r7 ; ld4s r25, r26 }
{ shl3addx r15, r16, r17 ; mulax r5, r6, r7 ; ld4u r25, r26 }
{ shl3addx r15, r16, r17 ; mz r5, r6, r7 ; prefetch_l1 r25 }
{ shl3addx r15, r16, r17 ; nor r5, r6, r7 ; prefetch_l2 r25 }
{ shl3addx r15, r16, r17 ; pcnt r5, r6 ; prefetch_l2_fault r25 }
{ shl3addx r15, r16, r17 ; prefetch r25 ; mulax r5, r6, r7 }
{ shl3addx r15, r16, r17 ; prefetch_l1 r25 ; cmpeq r5, r6, r7 }
{ shl3addx r15, r16, r17 ; prefetch_l1 r25 ; shl3addx r5, r6, r7 }
{ shl3addx r15, r16, r17 ; prefetch_l1_fault r25 ; mul_ls_ls r5, r6, r7 }
{ shl3addx r15, r16, r17 ; prefetch_l2 r25 ; addxi r5, r6, 5 }
{ shl3addx r15, r16, r17 ; prefetch_l2 r25 ; shl r5, r6, r7 }
{ shl3addx r15, r16, r17 ; prefetch_l2_fault r25 ; info 19 }
{ shl3addx r15, r16, r17 ; prefetch_l2_fault r25 ; tblidxb3 r5, r6 }
{ shl3addx r15, r16, r17 ; prefetch_l3 r25 ; or r5, r6, r7 }
{ shl3addx r15, r16, r17 ; prefetch_l3_fault r25 ; cmpltsi r5, r6, 5 }
{ shl3addx r15, r16, r17 ; prefetch_l3_fault r25 ; shrui r5, r6, 5 }
{ shl3addx r15, r16, r17 ; revbytes r5, r6 ; prefetch_l3 r25 }
{ shl3addx r15, r16, r17 ; rotli r5, r6, 5 ; st r25, r26 }
{ shl3addx r15, r16, r17 ; shl1add r5, r6, r7 ; st1 r25, r26 }
{ shl3addx r15, r16, r17 ; shl2add r5, r6, r7 ; st4 r25, r26 }
{ shl3addx r15, r16, r17 ; shl3addx r5, r6, r7 ; ld r25, r26 }
{ shl3addx r15, r16, r17 ; shrs r5, r6, r7 ; ld r25, r26 }
{ shl3addx r15, r16, r17 ; shru r5, r6, r7 ; ld1u r25, r26 }
{ shl3addx r15, r16, r17 ; st r25, r26 ; addi r5, r6, 5 }
{ shl3addx r15, r16, r17 ; st r25, r26 ; rotl r5, r6, r7 }
{ shl3addx r15, r16, r17 ; st1 r25, r26 ; fnop }
{ shl3addx r15, r16, r17 ; st1 r25, r26 ; tblidxb1 r5, r6 }
{ shl3addx r15, r16, r17 ; st2 r25, r26 ; nop }
{ shl3addx r15, r16, r17 ; st4 r25, r26 ; cmpleu r5, r6, r7 }
{ shl3addx r15, r16, r17 ; st4 r25, r26 ; shrsi r5, r6, 5 }
{ shl3addx r15, r16, r17 ; subx r5, r6, r7 ; prefetch_l2 r25 }
{ shl3addx r15, r16, r17 ; tblidxb1 r5, r6 ; prefetch_l2_fault r25 }
{ shl3addx r15, r16, r17 ; tblidxb3 r5, r6 ; prefetch_l3_fault r25 }
{ shl3addx r15, r16, r17 ; v1mz r5, r6, r7 }
{ shl3addx r15, r16, r17 ; v2packuc r5, r6, r7 }
{ shl3addx r15, r16, r17 ; xor r5, r6, r7 ; st1 r25, r26 }
{ shl3addx r5, r6, r7 ; addi r15, r16, 5 ; st2 r25, r26 }
{ shl3addx r5, r6, r7 ; addxi r15, r16, 5 ; st4 r25, r26 }
{ shl3addx r5, r6, r7 ; andi r15, r16, 5 ; st4 r25, r26 }
{ shl3addx r5, r6, r7 ; cmpexch r15, r16, r17 }
{ shl3addx r5, r6, r7 ; cmplts r15, r16, r17 ; ld r25, r26 }
{ shl3addx r5, r6, r7 ; cmpltu r15, r16, r17 ; ld1u r25, r26 }
{ shl3addx r5, r6, r7 ; dtlbpr r15 }
{ shl3addx r5, r6, r7 ; ill ; ld4u r25, r26 }
{ shl3addx r5, r6, r7 ; jalr r15 ; ld4s r25, r26 }
{ shl3addx r5, r6, r7 ; jr r15 ; prefetch r25 }
{ shl3addx r5, r6, r7 ; ld r25, r26 ; cmples r15, r16, r17 }
{ shl3addx r5, r6, r7 ; ld1s r25, r26 ; add r15, r16, r17 }
{ shl3addx r5, r6, r7 ; ld1s r25, r26 ; shrsi r15, r16, 5 }
{ shl3addx r5, r6, r7 ; ld1u r25, r26 ; shl r15, r16, r17 }
{ shl3addx r5, r6, r7 ; ld2s r25, r26 ; mnz r15, r16, r17 }
{ shl3addx r5, r6, r7 ; ld2u r25, r26 ; cmpne r15, r16, r17 }
{ shl3addx r5, r6, r7 ; ld4s r25, r26 ; and r15, r16, r17 }
{ shl3addx r5, r6, r7 ; ld4s r25, r26 ; subx r15, r16, r17 }
{ shl3addx r5, r6, r7 ; ld4u r25, r26 ; shl2addx r15, r16, r17 }
{ shl3addx r5, r6, r7 ; lnk r15 ; prefetch_l2 r25 }
{ shl3addx r5, r6, r7 ; move r15, r16 ; prefetch_l2 r25 }
{ shl3addx r5, r6, r7 ; mz r15, r16, r17 ; prefetch_l2 r25 }
{ shl3addx r5, r6, r7 ; nor r15, r16, r17 ; prefetch_l3 r25 }
{ shl3addx r5, r6, r7 ; prefetch r25 ; cmpltu r15, r16, r17 }
{ shl3addx r5, r6, r7 ; prefetch_add_l3_fault r15, 5 }
{ shl3addx r5, r6, r7 ; prefetch_l1 r25 ; shli r15, r16, 5 }
{ shl3addx r5, r6, r7 ; prefetch_l1_fault r25 ; rotli r15, r16, 5 }
{ shl3addx r5, r6, r7 ; prefetch_l2 r25 ; mnz r15, r16, r17 }
{ shl3addx r5, r6, r7 ; prefetch_l2_fault r25 ; fnop }
{ shl3addx r5, r6, r7 ; prefetch_l3 r25 ; cmpeq r15, r16, r17 }
{ shl3addx r5, r6, r7 ; prefetch_l3 r25 }
{ shl3addx r5, r6, r7 ; prefetch_l3_fault r25 ; shli r15, r16, 5 }
{ shl3addx r5, r6, r7 ; rotli r15, r16, 5 ; prefetch_l2_fault r25 }
{ shl3addx r5, r6, r7 ; shl1add r15, r16, r17 ; prefetch_l3 r25 }
{ shl3addx r5, r6, r7 ; shl2add r15, r16, r17 ; st r25, r26 }
{ shl3addx r5, r6, r7 ; shl3add r15, r16, r17 ; st2 r25, r26 }
{ shl3addx r5, r6, r7 ; shli r15, r16, 5 }
{ shl3addx r5, r6, r7 ; shrsi r15, r16, 5 }
{ shl3addx r5, r6, r7 ; shruxi r15, r16, 5 }
{ shl3addx r5, r6, r7 ; st r25, r26 ; shli r15, r16, 5 }
{ shl3addx r5, r6, r7 ; st1 r25, r26 ; rotli r15, r16, 5 }
{ shl3addx r5, r6, r7 ; st2 r25, r26 ; lnk r15 }
{ shl3addx r5, r6, r7 ; st4 r25, r26 ; cmpltu r15, r16, r17 }
{ shl3addx r5, r6, r7 ; stnt2 r15, r16 }
{ shl3addx r5, r6, r7 ; subx r15, r16, r17 ; st2 r25, r26 }
{ shl3addx r5, r6, r7 ; v2cmpltsi r15, r16, 5 }
{ shl3addx r5, r6, r7 ; xor r15, r16, r17 ; ld2u r25, r26 }
{ shli r15, r16, 5 ; addi r5, r6, 5 ; ld4s r25, r26 }
{ shli r15, r16, 5 ; addxi r5, r6, 5 ; ld4u r25, r26 }
{ shli r15, r16, 5 ; andi r5, r6, 5 ; ld4u r25, r26 }
{ shli r15, r16, 5 ; cmoveqz r5, r6, r7 ; ld4s r25, r26 }
{ shli r15, r16, 5 ; cmpeq r5, r6, r7 ; prefetch r25 }
{ shli r15, r16, 5 ; cmples r5, r6, r7 ; prefetch_l1_fault r25 }
{ shli r15, r16, 5 ; cmplts r5, r6, r7 ; prefetch_l2_fault r25 }
{ shli r15, r16, 5 ; cmpltu r5, r6, r7 ; prefetch_l3_fault r25 }
{ shli r15, r16, 5 ; ctz r5, r6 ; ld4s r25, r26 }
{ shli r15, r16, 5 ; fnop ; st r25, r26 }
{ shli r15, r16, 5 ; info 19 ; prefetch_l2 r25 }
{ shli r15, r16, 5 ; ld r25, r26 ; mula_ls_ls r5, r6, r7 }
{ shli r15, r16, 5 ; ld1s r25, r26 ; cmoveqz r5, r6, r7 }
{ shli r15, r16, 5 ; ld1s r25, r26 ; shl2addx r5, r6, r7 }
{ shli r15, r16, 5 ; ld1u r25, r26 ; mul_hs_hs r5, r6, r7 }
{ shli r15, r16, 5 ; ld2s r25, r26 ; addi r5, r6, 5 }
{ shli r15, r16, 5 ; ld2s r25, r26 ; rotl r5, r6, r7 }
{ shli r15, r16, 5 ; ld2u r25, r26 ; fnop }
{ shli r15, r16, 5 ; ld2u r25, r26 ; tblidxb1 r5, r6 }
{ shli r15, r16, 5 ; ld4s r25, r26 ; nop }
{ shli r15, r16, 5 ; ld4u r25, r26 ; cmpleu r5, r6, r7 }
{ shli r15, r16, 5 ; ld4u r25, r26 ; shrsi r5, r6, 5 }
{ shli r15, r16, 5 ; move r5, r6 ; prefetch_l1_fault r25 }
{ shli r15, r16, 5 ; mul_hs_hs r5, r6, r7 ; prefetch_l2 r25 }
{ shli r15, r16, 5 ; mul_ls_ls r5, r6, r7 ; prefetch r25 }
{ shli r15, r16, 5 ; mula_hs_hs r5, r6, r7 ; prefetch_l1 r25 }
{ shli r15, r16, 5 ; mula_ls_ls r5, r6, r7 ; ld4s r25, r26 }
{ shli r15, r16, 5 ; mulax r5, r6, r7 ; ld4u r25, r26 }
{ shli r15, r16, 5 ; mz r5, r6, r7 ; prefetch_l1 r25 }
{ shli r15, r16, 5 ; nor r5, r6, r7 ; prefetch_l2 r25 }
{ shli r15, r16, 5 ; pcnt r5, r6 ; prefetch_l2_fault r25 }
{ shli r15, r16, 5 ; prefetch r25 ; mulax r5, r6, r7 }
{ shli r15, r16, 5 ; prefetch_l1 r25 ; cmpeq r5, r6, r7 }
{ shli r15, r16, 5 ; prefetch_l1 r25 ; shl3addx r5, r6, r7 }
{ shli r15, r16, 5 ; prefetch_l1_fault r25 ; mul_ls_ls r5, r6, r7 }
{ shli r15, r16, 5 ; prefetch_l2 r25 ; addxi r5, r6, 5 }
{ shli r15, r16, 5 ; prefetch_l2 r25 ; shl r5, r6, r7 }
{ shli r15, r16, 5 ; prefetch_l2_fault r25 ; info 19 }
{ shli r15, r16, 5 ; prefetch_l2_fault r25 ; tblidxb3 r5, r6 }
{ shli r15, r16, 5 ; prefetch_l3 r25 ; or r5, r6, r7 }
{ shli r15, r16, 5 ; prefetch_l3_fault r25 ; cmpltsi r5, r6, 5 }
{ shli r15, r16, 5 ; prefetch_l3_fault r25 ; shrui r5, r6, 5 }
{ shli r15, r16, 5 ; revbytes r5, r6 ; prefetch_l3 r25 }
{ shli r15, r16, 5 ; rotli r5, r6, 5 ; st r25, r26 }
{ shli r15, r16, 5 ; shl1add r5, r6, r7 ; st1 r25, r26 }
{ shli r15, r16, 5 ; shl2add r5, r6, r7 ; st4 r25, r26 }
{ shli r15, r16, 5 ; shl3addx r5, r6, r7 ; ld r25, r26 }
{ shli r15, r16, 5 ; shrs r5, r6, r7 ; ld r25, r26 }
{ shli r15, r16, 5 ; shru r5, r6, r7 ; ld1u r25, r26 }
{ shli r15, r16, 5 ; st r25, r26 ; addi r5, r6, 5 }
{ shli r15, r16, 5 ; st r25, r26 ; rotl r5, r6, r7 }
{ shli r15, r16, 5 ; st1 r25, r26 ; fnop }
{ shli r15, r16, 5 ; st1 r25, r26 ; tblidxb1 r5, r6 }
{ shli r15, r16, 5 ; st2 r25, r26 ; nop }
{ shli r15, r16, 5 ; st4 r25, r26 ; cmpleu r5, r6, r7 }
{ shli r15, r16, 5 ; st4 r25, r26 ; shrsi r5, r6, 5 }
{ shli r15, r16, 5 ; subx r5, r6, r7 ; prefetch_l2 r25 }
{ shli r15, r16, 5 ; tblidxb1 r5, r6 ; prefetch_l2_fault r25 }
{ shli r15, r16, 5 ; tblidxb3 r5, r6 ; prefetch_l3_fault r25 }
{ shli r15, r16, 5 ; v1mz r5, r6, r7 }
{ shli r15, r16, 5 ; v2packuc r5, r6, r7 }
{ shli r15, r16, 5 ; xor r5, r6, r7 ; st1 r25, r26 }
{ shli r5, r6, 5 ; addi r15, r16, 5 ; st2 r25, r26 }
{ shli r5, r6, 5 ; addxi r15, r16, 5 ; st4 r25, r26 }
{ shli r5, r6, 5 ; andi r15, r16, 5 ; st4 r25, r26 }
{ shli r5, r6, 5 ; cmpexch r15, r16, r17 }
{ shli r5, r6, 5 ; cmplts r15, r16, r17 ; ld r25, r26 }
{ shli r5, r6, 5 ; cmpltu r15, r16, r17 ; ld1u r25, r26 }
{ shli r5, r6, 5 ; dtlbpr r15 }
{ shli r5, r6, 5 ; ill ; ld4u r25, r26 }
{ shli r5, r6, 5 ; jalr r15 ; ld4s r25, r26 }
{ shli r5, r6, 5 ; jr r15 ; prefetch r25 }
{ shli r5, r6, 5 ; ld r25, r26 ; cmples r15, r16, r17 }
{ shli r5, r6, 5 ; ld1s r25, r26 ; add r15, r16, r17 }
{ shli r5, r6, 5 ; ld1s r25, r26 ; shrsi r15, r16, 5 }
{ shli r5, r6, 5 ; ld1u r25, r26 ; shl r15, r16, r17 }
{ shli r5, r6, 5 ; ld2s r25, r26 ; mnz r15, r16, r17 }
{ shli r5, r6, 5 ; ld2u r25, r26 ; cmpne r15, r16, r17 }
{ shli r5, r6, 5 ; ld4s r25, r26 ; and r15, r16, r17 }
{ shli r5, r6, 5 ; ld4s r25, r26 ; subx r15, r16, r17 }
{ shli r5, r6, 5 ; ld4u r25, r26 ; shl2addx r15, r16, r17 }
{ shli r5, r6, 5 ; lnk r15 ; prefetch_l2 r25 }
{ shli r5, r6, 5 ; move r15, r16 ; prefetch_l2 r25 }
{ shli r5, r6, 5 ; mz r15, r16, r17 ; prefetch_l2 r25 }
{ shli r5, r6, 5 ; nor r15, r16, r17 ; prefetch_l3 r25 }
{ shli r5, r6, 5 ; prefetch r25 ; cmpltu r15, r16, r17 }
{ shli r5, r6, 5 ; prefetch_add_l3_fault r15, 5 }
{ shli r5, r6, 5 ; prefetch_l1 r25 ; shli r15, r16, 5 }
{ shli r5, r6, 5 ; prefetch_l1_fault r25 ; rotli r15, r16, 5 }
{ shli r5, r6, 5 ; prefetch_l2 r25 ; mnz r15, r16, r17 }
{ shli r5, r6, 5 ; prefetch_l2_fault r25 ; fnop }
{ shli r5, r6, 5 ; prefetch_l3 r25 ; cmpeq r15, r16, r17 }
{ shli r5, r6, 5 ; prefetch_l3 r25 }
{ shli r5, r6, 5 ; prefetch_l3_fault r25 ; shli r15, r16, 5 }
{ shli r5, r6, 5 ; rotli r15, r16, 5 ; prefetch_l2_fault r25 }
{ shli r5, r6, 5 ; shl1add r15, r16, r17 ; prefetch_l3 r25 }
{ shli r5, r6, 5 ; shl2add r15, r16, r17 ; st r25, r26 }
{ shli r5, r6, 5 ; shl3add r15, r16, r17 ; st2 r25, r26 }
{ shli r5, r6, 5 ; shli r15, r16, 5 }
{ shli r5, r6, 5 ; shrsi r15, r16, 5 }
{ shli r5, r6, 5 ; shruxi r15, r16, 5 }
{ shli r5, r6, 5 ; st r25, r26 ; shli r15, r16, 5 }
{ shli r5, r6, 5 ; st1 r25, r26 ; rotli r15, r16, 5 }
{ shli r5, r6, 5 ; st2 r25, r26 ; lnk r15 }
{ shli r5, r6, 5 ; st4 r25, r26 ; cmpltu r15, r16, r17 }
{ shli r5, r6, 5 ; stnt2 r15, r16 }
{ shli r5, r6, 5 ; subx r15, r16, r17 ; st2 r25, r26 }
{ shli r5, r6, 5 ; v2cmpltsi r15, r16, 5 }
{ shli r5, r6, 5 ; xor r15, r16, r17 ; ld2u r25, r26 }
{ shlx r15, r16, r17 ; cmul r5, r6, r7 }
{ shlx r15, r16, r17 ; mul_hs_lu r5, r6, r7 }
{ shlx r15, r16, r17 ; shrs r5, r6, r7 }
{ shlx r15, r16, r17 ; v1maxu r5, r6, r7 }
{ shlx r15, r16, r17 ; v2minsi r5, r6, 5 }
{ shlx r5, r6, r7 ; addxli r15, r16, 0x1234 }
{ shlx r5, r6, r7 ; jalrp r15 }
{ shlx r5, r6, r7 ; mtspr 0x5, r16 }
{ shlx r5, r6, r7 ; st1 r15, r16 }
{ shlx r5, r6, r7 ; v1shrs r15, r16, r17 }
{ shlx r5, r6, r7 ; v4int_h r15, r16, r17 }
{ shlxi r15, r16, 5 ; cmulfr r5, r6, r7 }
{ shlxi r15, r16, 5 ; mul_ls_ls r5, r6, r7 }
{ shlxi r15, r16, 5 ; shrux r5, r6, r7 }
{ shlxi r15, r16, 5 ; v1mnz r5, r6, r7 }
{ shlxi r15, r16, 5 ; v2mults r5, r6, r7 }
{ shlxi r5, r6, 5 ; cmpeq r15, r16, r17 }
{ shlxi r5, r6, 5 ; ld1s r15, r16 }
{ shlxi r5, r6, 5 ; or r15, r16, r17 }
{ shlxi r5, r6, 5 ; st4 r15, r16 }
{ shlxi r5, r6, 5 ; v1sub r15, r16, r17 }
{ shlxi r5, r6, 5 ; v4shlsc r15, r16, r17 }
{ shrs r15, r16, r17 ; addi r5, r6, 5 ; prefetch_l3_fault r25 }
{ shrs r15, r16, r17 ; addxi r5, r6, 5 ; st r25, r26 }
{ shrs r15, r16, r17 ; andi r5, r6, 5 ; st r25, r26 }
{ shrs r15, r16, r17 ; cmoveqz r5, r6, r7 ; prefetch_l3_fault r25 }
{ shrs r15, r16, r17 ; cmpeq r5, r6, r7 ; st1 r25, r26 }
{ shrs r15, r16, r17 ; cmples r5, r6, r7 ; st4 r25, r26 }
{ shrs r15, r16, r17 ; cmpltsi r5, r6, 5 ; ld r25, r26 }
{ shrs r15, r16, r17 ; cmpne r5, r6, r7 ; ld1s r25, r26 }
{ shrs r15, r16, r17 ; ctz r5, r6 ; prefetch_l3_fault r25 }
{ shrs r15, r16, r17 ; fsingle_mul2 r5, r6, r7 }
{ shrs r15, r16, r17 ; info 19 }
{ shrs r15, r16, r17 ; ld r25, r26 ; pcnt r5, r6 }
{ shrs r15, r16, r17 ; ld1s r25, r26 ; cmpltu r5, r6, r7 }
{ shrs r15, r16, r17 ; ld1s r25, r26 ; sub r5, r6, r7 }
{ shrs r15, r16, r17 ; ld1u r25, r26 ; mulax r5, r6, r7 }
{ shrs r15, r16, r17 ; ld2s r25, r26 ; cmpeq r5, r6, r7 }
{ shrs r15, r16, r17 ; ld2s r25, r26 ; shl3addx r5, r6, r7 }
{ shrs r15, r16, r17 ; ld2u r25, r26 ; mul_ls_ls r5, r6, r7 }
{ shrs r15, r16, r17 ; ld4s r25, r26 ; addxi r5, r6, 5 }
{ shrs r15, r16, r17 ; ld4s r25, r26 ; shl r5, r6, r7 }
{ shrs r15, r16, r17 ; ld4u r25, r26 ; info 19 }
{ shrs r15, r16, r17 ; ld4u r25, r26 ; tblidxb3 r5, r6 }
{ shrs r15, r16, r17 ; move r5, r6 ; st4 r25, r26 }
{ shrs r15, r16, r17 ; mul_hs_hs r5, r6, r7 }
{ shrs r15, r16, r17 ; mul_ls_ls r5, r6, r7 ; st1 r25, r26 }
{ shrs r15, r16, r17 ; mula_hs_hs r5, r6, r7 ; st2 r25, r26 }
{ shrs r15, r16, r17 ; mula_ls_ls r5, r6, r7 ; prefetch_l3_fault r25 }
{ shrs r15, r16, r17 ; mulax r5, r6, r7 ; st r25, r26 }
{ shrs r15, r16, r17 ; mz r5, r6, r7 ; st2 r25, r26 }
{ shrs r15, r16, r17 ; nor r5, r6, r7 }
{ shrs r15, r16, r17 ; prefetch r25 ; add r5, r6, r7 }
{ shrs r15, r16, r17 ; prefetch r25 ; revbytes r5, r6 }
{ shrs r15, r16, r17 ; prefetch_l1 r25 ; ctz r5, r6 }
{ shrs r15, r16, r17 ; prefetch_l1 r25 ; tblidxb0 r5, r6 }
{ shrs r15, r16, r17 ; prefetch_l1_fault r25 ; mz r5, r6, r7 }
{ shrs r15, r16, r17 ; prefetch_l2 r25 ; cmples r5, r6, r7 }
{ shrs r15, r16, r17 ; prefetch_l2 r25 ; shrs r5, r6, r7 }
{ shrs r15, r16, r17 ; prefetch_l2_fault r25 ; mula_hs_hs r5, r6, r7 }
{ shrs r15, r16, r17 ; prefetch_l3 r25 ; andi r5, r6, 5 }
{ shrs r15, r16, r17 ; prefetch_l3 r25 ; shl1addx r5, r6, r7 }
{ shrs r15, r16, r17 ; prefetch_l3_fault r25 ; move r5, r6 }
{ shrs r15, r16, r17 ; prefetch_l3_fault r25 }
{ shrs r15, r16, r17 ; rotl r5, r6, r7 ; ld1s r25, r26 }
{ shrs r15, r16, r17 ; shl r5, r6, r7 ; ld2s r25, r26 }
{ shrs r15, r16, r17 ; shl1addx r5, r6, r7 ; ld2u r25, r26 }
{ shrs r15, r16, r17 ; shl2addx r5, r6, r7 ; ld4u r25, r26 }
{ shrs r15, r16, r17 ; shl3addx r5, r6, r7 ; prefetch_l1 r25 }
{ shrs r15, r16, r17 ; shrs r5, r6, r7 ; prefetch_l1 r25 }
{ shrs r15, r16, r17 ; shru r5, r6, r7 ; prefetch_l2 r25 }
{ shrs r15, r16, r17 ; st r25, r26 ; cmpeq r5, r6, r7 }
{ shrs r15, r16, r17 ; st r25, r26 ; shl3addx r5, r6, r7 }
{ shrs r15, r16, r17 ; st1 r25, r26 ; mul_ls_ls r5, r6, r7 }
{ shrs r15, r16, r17 ; st2 r25, r26 ; addxi r5, r6, 5 }
{ shrs r15, r16, r17 ; st2 r25, r26 ; shl r5, r6, r7 }
{ shrs r15, r16, r17 ; st4 r25, r26 ; info 19 }
{ shrs r15, r16, r17 ; st4 r25, r26 ; tblidxb3 r5, r6 }
{ shrs r15, r16, r17 ; subx r5, r6, r7 }
{ shrs r15, r16, r17 ; tblidxb2 r5, r6 ; ld r25, r26 }
{ shrs r15, r16, r17 ; v1adduc r5, r6, r7 }
{ shrs r15, r16, r17 ; v1shrui r5, r6, 5 }
{ shrs r15, r16, r17 ; v2shrs r5, r6, r7 }
{ shrs r5, r6, r7 ; add r15, r16, r17 ; ld2s r25, r26 }
{ shrs r5, r6, r7 ; addx r15, r16, r17 ; ld2u r25, r26 }
{ shrs r5, r6, r7 ; and r15, r16, r17 ; ld2u r25, r26 }
{ shrs r5, r6, r7 ; cmpeq r15, r16, r17 ; ld4u r25, r26 }
{ shrs r5, r6, r7 ; cmples r15, r16, r17 ; ld4u r25, r26 }
{ shrs r5, r6, r7 ; cmplts r15, r16, r17 ; prefetch_l1 r25 }
{ shrs r5, r6, r7 ; cmpltu r15, r16, r17 ; prefetch_l2 r25 }
{ shrs r5, r6, r7 ; fetchand4 r15, r16, r17 }
{ shrs r5, r6, r7 ; ill ; st r25, r26 }
{ shrs r5, r6, r7 ; jalr r15 ; prefetch_l3_fault r25 }
{ shrs r5, r6, r7 ; jr r15 ; st1 r25, r26 }
{ shrs r5, r6, r7 ; ld r25, r26 ; info 19 }
{ shrs r5, r6, r7 ; ld1s r25, r26 ; cmples r15, r16, r17 }
{ shrs r5, r6, r7 ; ld1u r15, r16 }
{ shrs r5, r6, r7 ; ld1u r25, r26 ; shrs r15, r16, r17 }
{ shrs r5, r6, r7 ; ld2s r25, r26 ; rotli r15, r16, 5 }
{ shrs r5, r6, r7 ; ld2u r25, r26 ; lnk r15 }
{ shrs r5, r6, r7 ; ld4s r25, r26 ; cmpltu r15, r16, r17 }
{ shrs r5, r6, r7 ; ld4u r25, r26 ; addxi r15, r16, 5 }
{ shrs r5, r6, r7 ; ld4u r25, r26 ; sub r15, r16, r17 }
{ shrs r5, r6, r7 ; lnk r15 }
{ shrs r5, r6, r7 ; move r15, r16 }
{ shrs r5, r6, r7 ; mz r15, r16, r17 }
{ shrs r5, r6, r7 ; or r15, r16, r17 ; ld1s r25, r26 }
{ shrs r5, r6, r7 ; prefetch r25 ; jrp r15 }
{ shrs r5, r6, r7 ; prefetch_l1 r25 ; cmpeq r15, r16, r17 }
{ shrs r5, r6, r7 ; prefetch_l1 r25 }
{ shrs r5, r6, r7 ; prefetch_l1_fault r25 ; shli r15, r16, 5 }
{ shrs r5, r6, r7 ; prefetch_l2 r25 ; rotli r15, r16, 5 }
{ shrs r5, r6, r7 ; prefetch_l2_fault r25 ; mnz r15, r16, r17 }
{ shrs r5, r6, r7 ; prefetch_l3 r25 ; fnop }
{ shrs r5, r6, r7 ; prefetch_l3_fault r25 ; cmpeq r15, r16, r17 }
{ shrs r5, r6, r7 ; prefetch_l3_fault r25 }
{ shrs r5, r6, r7 ; shl r15, r16, r17 ; ld r25, r26 }
{ shrs r5, r6, r7 ; shl1addx r15, r16, r17 ; ld1s r25, r26 }
{ shrs r5, r6, r7 ; shl2addx r15, r16, r17 ; ld2s r25, r26 }
{ shrs r5, r6, r7 ; shl3addx r15, r16, r17 ; ld4s r25, r26 }
{ shrs r5, r6, r7 ; shrs r15, r16, r17 ; ld4s r25, r26 }
{ shrs r5, r6, r7 ; shru r15, r16, r17 ; prefetch r25 }
{ shrs r5, r6, r7 ; st r25, r26 ; cmpeq r15, r16, r17 }
{ shrs r5, r6, r7 ; st r25, r26 }
{ shrs r5, r6, r7 ; st1 r25, r26 ; shli r15, r16, 5 }
{ shrs r5, r6, r7 ; st2 r25, r26 ; rotl r15, r16, r17 }
{ shrs r5, r6, r7 ; st4 r25, r26 ; jrp r15 }
{ shrs r5, r6, r7 ; sub r15, r16, r17 ; ld2s r25, r26 }
{ shrs r5, r6, r7 ; v1cmpeqi r15, r16, 5 }
{ shrs r5, r6, r7 ; v2mins r15, r16, r17 }
{ shrs r5, r6, r7 ; xor r15, r16, r17 ; prefetch_l3 r25 }
{ shrsi r15, r16, 5 ; addi r5, r6, 5 ; prefetch_l3_fault r25 }
{ shrsi r15, r16, 5 ; addxi r5, r6, 5 ; st r25, r26 }
{ shrsi r15, r16, 5 ; andi r5, r6, 5 ; st r25, r26 }
{ shrsi r15, r16, 5 ; cmoveqz r5, r6, r7 ; prefetch_l3_fault r25 }
{ shrsi r15, r16, 5 ; cmpeq r5, r6, r7 ; st1 r25, r26 }
{ shrsi r15, r16, 5 ; cmples r5, r6, r7 ; st4 r25, r26 }
{ shrsi r15, r16, 5 ; cmpltsi r5, r6, 5 ; ld r25, r26 }
{ shrsi r15, r16, 5 ; cmpne r5, r6, r7 ; ld1s r25, r26 }
{ shrsi r15, r16, 5 ; ctz r5, r6 ; prefetch_l3_fault r25 }
{ shrsi r15, r16, 5 ; fsingle_mul2 r5, r6, r7 }
{ shrsi r15, r16, 5 ; info 19 }
{ shrsi r15, r16, 5 ; ld r25, r26 ; pcnt r5, r6 }
{ shrsi r15, r16, 5 ; ld1s r25, r26 ; cmpltu r5, r6, r7 }
{ shrsi r15, r16, 5 ; ld1s r25, r26 ; sub r5, r6, r7 }
{ shrsi r15, r16, 5 ; ld1u r25, r26 ; mulax r5, r6, r7 }
{ shrsi r15, r16, 5 ; ld2s r25, r26 ; cmpeq r5, r6, r7 }
{ shrsi r15, r16, 5 ; ld2s r25, r26 ; shl3addx r5, r6, r7 }
{ shrsi r15, r16, 5 ; ld2u r25, r26 ; mul_ls_ls r5, r6, r7 }
{ shrsi r15, r16, 5 ; ld4s r25, r26 ; addxi r5, r6, 5 }
{ shrsi r15, r16, 5 ; ld4s r25, r26 ; shl r5, r6, r7 }
{ shrsi r15, r16, 5 ; ld4u r25, r26 ; info 19 }
{ shrsi r15, r16, 5 ; ld4u r25, r26 ; tblidxb3 r5, r6 }
{ shrsi r15, r16, 5 ; move r5, r6 ; st4 r25, r26 }
{ shrsi r15, r16, 5 ; mul_hs_hs r5, r6, r7 }
{ shrsi r15, r16, 5 ; mul_ls_ls r5, r6, r7 ; st1 r25, r26 }
{ shrsi r15, r16, 5 ; mula_hs_hs r5, r6, r7 ; st2 r25, r26 }
{ shrsi r15, r16, 5 ; mula_ls_ls r5, r6, r7 ; prefetch_l3_fault r25 }
{ shrsi r15, r16, 5 ; mulax r5, r6, r7 ; st r25, r26 }
{ shrsi r15, r16, 5 ; mz r5, r6, r7 ; st2 r25, r26 }
{ shrsi r15, r16, 5 ; nor r5, r6, r7 }
{ shrsi r15, r16, 5 ; prefetch r25 ; add r5, r6, r7 }
{ shrsi r15, r16, 5 ; prefetch r25 ; revbytes r5, r6 }
{ shrsi r15, r16, 5 ; prefetch_l1 r25 ; ctz r5, r6 }
{ shrsi r15, r16, 5 ; prefetch_l1 r25 ; tblidxb0 r5, r6 }
{ shrsi r15, r16, 5 ; prefetch_l1_fault r25 ; mz r5, r6, r7 }
{ shrsi r15, r16, 5 ; prefetch_l2 r25 ; cmples r5, r6, r7 }
{ shrsi r15, r16, 5 ; prefetch_l2 r25 ; shrs r5, r6, r7 }
{ shrsi r15, r16, 5 ; prefetch_l2_fault r25 ; mula_hs_hs r5, r6, r7 }
{ shrsi r15, r16, 5 ; prefetch_l3 r25 ; andi r5, r6, 5 }
{ shrsi r15, r16, 5 ; prefetch_l3 r25 ; shl1addx r5, r6, r7 }
{ shrsi r15, r16, 5 ; prefetch_l3_fault r25 ; move r5, r6 }
{ shrsi r15, r16, 5 ; prefetch_l3_fault r25 }
{ shrsi r15, r16, 5 ; rotl r5, r6, r7 ; ld1s r25, r26 }
{ shrsi r15, r16, 5 ; shl r5, r6, r7 ; ld2s r25, r26 }
{ shrsi r15, r16, 5 ; shl1addx r5, r6, r7 ; ld2u r25, r26 }
{ shrsi r15, r16, 5 ; shl2addx r5, r6, r7 ; ld4u r25, r26 }
{ shrsi r15, r16, 5 ; shl3addx r5, r6, r7 ; prefetch_l1 r25 }
{ shrsi r15, r16, 5 ; shrs r5, r6, r7 ; prefetch_l1 r25 }
{ shrsi r15, r16, 5 ; shru r5, r6, r7 ; prefetch_l2 r25 }
{ shrsi r15, r16, 5 ; st r25, r26 ; cmpeq r5, r6, r7 }
{ shrsi r15, r16, 5 ; st r25, r26 ; shl3addx r5, r6, r7 }
{ shrsi r15, r16, 5 ; st1 r25, r26 ; mul_ls_ls r5, r6, r7 }
{ shrsi r15, r16, 5 ; st2 r25, r26 ; addxi r5, r6, 5 }
{ shrsi r15, r16, 5 ; st2 r25, r26 ; shl r5, r6, r7 }
{ shrsi r15, r16, 5 ; st4 r25, r26 ; info 19 }
{ shrsi r15, r16, 5 ; st4 r25, r26 ; tblidxb3 r5, r6 }
{ shrsi r15, r16, 5 ; subx r5, r6, r7 }
{ shrsi r15, r16, 5 ; tblidxb2 r5, r6 ; ld r25, r26 }
{ shrsi r15, r16, 5 ; v1adduc r5, r6, r7 }
{ shrsi r15, r16, 5 ; v1shrui r5, r6, 5 }
{ shrsi r15, r16, 5 ; v2shrs r5, r6, r7 }
{ shrsi r5, r6, 5 ; add r15, r16, r17 ; ld2s r25, r26 }
{ shrsi r5, r6, 5 ; addx r15, r16, r17 ; ld2u r25, r26 }
{ shrsi r5, r6, 5 ; and r15, r16, r17 ; ld2u r25, r26 }
{ shrsi r5, r6, 5 ; cmpeq r15, r16, r17 ; ld4u r25, r26 }
{ shrsi r5, r6, 5 ; cmples r15, r16, r17 ; ld4u r25, r26 }
{ shrsi r5, r6, 5 ; cmplts r15, r16, r17 ; prefetch_l1 r25 }
{ shrsi r5, r6, 5 ; cmpltu r15, r16, r17 ; prefetch_l2 r25 }
{ shrsi r5, r6, 5 ; fetchand4 r15, r16, r17 }
{ shrsi r5, r6, 5 ; ill ; st r25, r26 }
{ shrsi r5, r6, 5 ; jalr r15 ; prefetch_l3_fault r25 }
{ shrsi r5, r6, 5 ; jr r15 ; st1 r25, r26 }
{ shrsi r5, r6, 5 ; ld r25, r26 ; info 19 }
{ shrsi r5, r6, 5 ; ld1s r25, r26 ; cmples r15, r16, r17 }
{ shrsi r5, r6, 5 ; ld1u r15, r16 }
{ shrsi r5, r6, 5 ; ld1u r25, r26 ; shrs r15, r16, r17 }
{ shrsi r5, r6, 5 ; ld2s r25, r26 ; rotli r15, r16, 5 }
{ shrsi r5, r6, 5 ; ld2u r25, r26 ; lnk r15 }
{ shrsi r5, r6, 5 ; ld4s r25, r26 ; cmpltu r15, r16, r17 }
{ shrsi r5, r6, 5 ; ld4u r25, r26 ; addxi r15, r16, 5 }
{ shrsi r5, r6, 5 ; ld4u r25, r26 ; sub r15, r16, r17 }
{ shrsi r5, r6, 5 ; lnk r15 }
{ shrsi r5, r6, 5 ; move r15, r16 }
{ shrsi r5, r6, 5 ; mz r15, r16, r17 }
{ shrsi r5, r6, 5 ; or r15, r16, r17 ; ld1s r25, r26 }
{ shrsi r5, r6, 5 ; prefetch r25 ; jrp r15 }
{ shrsi r5, r6, 5 ; prefetch_l1 r25 ; cmpeq r15, r16, r17 }
{ shrsi r5, r6, 5 ; prefetch_l1 r25 }
{ shrsi r5, r6, 5 ; prefetch_l1_fault r25 ; shli r15, r16, 5 }
{ shrsi r5, r6, 5 ; prefetch_l2 r25 ; rotli r15, r16, 5 }
{ shrsi r5, r6, 5 ; prefetch_l2_fault r25 ; mnz r15, r16, r17 }
{ shrsi r5, r6, 5 ; prefetch_l3 r25 ; fnop }
{ shrsi r5, r6, 5 ; prefetch_l3_fault r25 ; cmpeq r15, r16, r17 }
{ shrsi r5, r6, 5 ; prefetch_l3_fault r25 }
{ shrsi r5, r6, 5 ; shl r15, r16, r17 ; ld r25, r26 }
{ shrsi r5, r6, 5 ; shl1addx r15, r16, r17 ; ld1s r25, r26 }
{ shrsi r5, r6, 5 ; shl2addx r15, r16, r17 ; ld2s r25, r26 }
{ shrsi r5, r6, 5 ; shl3addx r15, r16, r17 ; ld4s r25, r26 }
{ shrsi r5, r6, 5 ; shrs r15, r16, r17 ; ld4s r25, r26 }
{ shrsi r5, r6, 5 ; shru r15, r16, r17 ; prefetch r25 }
{ shrsi r5, r6, 5 ; st r25, r26 ; cmpeq r15, r16, r17 }
{ shrsi r5, r6, 5 ; st r25, r26 }
{ shrsi r5, r6, 5 ; st1 r25, r26 ; shli r15, r16, 5 }
{ shrsi r5, r6, 5 ; st2 r25, r26 ; rotl r15, r16, r17 }
{ shrsi r5, r6, 5 ; st4 r25, r26 ; jrp r15 }
{ shrsi r5, r6, 5 ; sub r15, r16, r17 ; ld2s r25, r26 }
{ shrsi r5, r6, 5 ; v1cmpeqi r15, r16, 5 }
{ shrsi r5, r6, 5 ; v2mins r15, r16, r17 }
{ shrsi r5, r6, 5 ; xor r15, r16, r17 ; prefetch_l3 r25 }
{ shru r15, r16, r17 ; addi r5, r6, 5 ; prefetch_l3_fault r25 }
{ shru r15, r16, r17 ; addxi r5, r6, 5 ; st r25, r26 }
{ shru r15, r16, r17 ; andi r5, r6, 5 ; st r25, r26 }
{ shru r15, r16, r17 ; cmoveqz r5, r6, r7 ; prefetch_l3_fault r25 }
{ shru r15, r16, r17 ; cmpeq r5, r6, r7 ; st1 r25, r26 }
{ shru r15, r16, r17 ; cmples r5, r6, r7 ; st4 r25, r26 }
{ shru r15, r16, r17 ; cmpltsi r5, r6, 5 ; ld r25, r26 }
{ shru r15, r16, r17 ; cmpne r5, r6, r7 ; ld1s r25, r26 }
{ shru r15, r16, r17 ; ctz r5, r6 ; prefetch_l3_fault r25 }
{ shru r15, r16, r17 ; fsingle_mul2 r5, r6, r7 }
{ shru r15, r16, r17 ; info 19 }
{ shru r15, r16, r17 ; ld r25, r26 ; pcnt r5, r6 }
{ shru r15, r16, r17 ; ld1s r25, r26 ; cmpltu r5, r6, r7 }
{ shru r15, r16, r17 ; ld1s r25, r26 ; sub r5, r6, r7 }
{ shru r15, r16, r17 ; ld1u r25, r26 ; mulax r5, r6, r7 }
{ shru r15, r16, r17 ; ld2s r25, r26 ; cmpeq r5, r6, r7 }
{ shru r15, r16, r17 ; ld2s r25, r26 ; shl3addx r5, r6, r7 }
{ shru r15, r16, r17 ; ld2u r25, r26 ; mul_ls_ls r5, r6, r7 }
{ shru r15, r16, r17 ; ld4s r25, r26 ; addxi r5, r6, 5 }
{ shru r15, r16, r17 ; ld4s r25, r26 ; shl r5, r6, r7 }
{ shru r15, r16, r17 ; ld4u r25, r26 ; info 19 }
{ shru r15, r16, r17 ; ld4u r25, r26 ; tblidxb3 r5, r6 }
{ shru r15, r16, r17 ; move r5, r6 ; st4 r25, r26 }
{ shru r15, r16, r17 ; mul_hs_hs r5, r6, r7 }
{ shru r15, r16, r17 ; mul_ls_ls r5, r6, r7 ; st1 r25, r26 }
{ shru r15, r16, r17 ; mula_hs_hs r5, r6, r7 ; st2 r25, r26 }
{ shru r15, r16, r17 ; mula_ls_ls r5, r6, r7 ; prefetch_l3_fault r25 }
{ shru r15, r16, r17 ; mulax r5, r6, r7 ; st r25, r26 }
{ shru r15, r16, r17 ; mz r5, r6, r7 ; st2 r25, r26 }
{ shru r15, r16, r17 ; nor r5, r6, r7 }
{ shru r15, r16, r17 ; prefetch r25 ; add r5, r6, r7 }
{ shru r15, r16, r17 ; prefetch r25 ; revbytes r5, r6 }
{ shru r15, r16, r17 ; prefetch_l1 r25 ; ctz r5, r6 }
{ shru r15, r16, r17 ; prefetch_l1 r25 ; tblidxb0 r5, r6 }
{ shru r15, r16, r17 ; prefetch_l1_fault r25 ; mz r5, r6, r7 }
{ shru r15, r16, r17 ; prefetch_l2 r25 ; cmples r5, r6, r7 }
{ shru r15, r16, r17 ; prefetch_l2 r25 ; shrs r5, r6, r7 }
{ shru r15, r16, r17 ; prefetch_l2_fault r25 ; mula_hs_hs r5, r6, r7 }
{ shru r15, r16, r17 ; prefetch_l3 r25 ; andi r5, r6, 5 }
{ shru r15, r16, r17 ; prefetch_l3 r25 ; shl1addx r5, r6, r7 }
{ shru r15, r16, r17 ; prefetch_l3_fault r25 ; move r5, r6 }
{ shru r15, r16, r17 ; prefetch_l3_fault r25 }
{ shru r15, r16, r17 ; rotl r5, r6, r7 ; ld1s r25, r26 }
{ shru r15, r16, r17 ; shl r5, r6, r7 ; ld2s r25, r26 }
{ shru r15, r16, r17 ; shl1addx r5, r6, r7 ; ld2u r25, r26 }
{ shru r15, r16, r17 ; shl2addx r5, r6, r7 ; ld4u r25, r26 }
{ shru r15, r16, r17 ; shl3addx r5, r6, r7 ; prefetch_l1 r25 }
{ shru r15, r16, r17 ; shrs r5, r6, r7 ; prefetch_l1 r25 }
{ shru r15, r16, r17 ; shru r5, r6, r7 ; prefetch_l2 r25 }
{ shru r15, r16, r17 ; st r25, r26 ; cmpeq r5, r6, r7 }
{ shru r15, r16, r17 ; st r25, r26 ; shl3addx r5, r6, r7 }
{ shru r15, r16, r17 ; st1 r25, r26 ; mul_ls_ls r5, r6, r7 }
{ shru r15, r16, r17 ; st2 r25, r26 ; addxi r5, r6, 5 }
{ shru r15, r16, r17 ; st2 r25, r26 ; shl r5, r6, r7 }
{ shru r15, r16, r17 ; st4 r25, r26 ; info 19 }
{ shru r15, r16, r17 ; st4 r25, r26 ; tblidxb3 r5, r6 }
{ shru r15, r16, r17 ; subx r5, r6, r7 }
{ shru r15, r16, r17 ; tblidxb2 r5, r6 ; ld r25, r26 }
{ shru r15, r16, r17 ; v1adduc r5, r6, r7 }
{ shru r15, r16, r17 ; v1shrui r5, r6, 5 }
{ shru r15, r16, r17 ; v2shrs r5, r6, r7 }
{ shru r5, r6, r7 ; add r15, r16, r17 ; ld2s r25, r26 }
{ shru r5, r6, r7 ; addx r15, r16, r17 ; ld2u r25, r26 }
{ shru r5, r6, r7 ; and r15, r16, r17 ; ld2u r25, r26 }
{ shru r5, r6, r7 ; cmpeq r15, r16, r17 ; ld4u r25, r26 }
{ shru r5, r6, r7 ; cmples r15, r16, r17 ; ld4u r25, r26 }
{ shru r5, r6, r7 ; cmplts r15, r16, r17 ; prefetch_l1 r25 }
{ shru r5, r6, r7 ; cmpltu r15, r16, r17 ; prefetch_l2 r25 }
{ shru r5, r6, r7 ; fetchand4 r15, r16, r17 }
{ shru r5, r6, r7 ; ill ; st r25, r26 }
{ shru r5, r6, r7 ; jalr r15 ; prefetch_l3_fault r25 }
{ shru r5, r6, r7 ; jr r15 ; st1 r25, r26 }
{ shru r5, r6, r7 ; ld r25, r26 ; info 19 }
{ shru r5, r6, r7 ; ld1s r25, r26 ; cmples r15, r16, r17 }
{ shru r5, r6, r7 ; ld1u r15, r16 }
{ shru r5, r6, r7 ; ld1u r25, r26 ; shrs r15, r16, r17 }
{ shru r5, r6, r7 ; ld2s r25, r26 ; rotli r15, r16, 5 }
{ shru r5, r6, r7 ; ld2u r25, r26 ; lnk r15 }
{ shru r5, r6, r7 ; ld4s r25, r26 ; cmpltu r15, r16, r17 }
{ shru r5, r6, r7 ; ld4u r25, r26 ; addxi r15, r16, 5 }
{ shru r5, r6, r7 ; ld4u r25, r26 ; sub r15, r16, r17 }
{ shru r5, r6, r7 ; lnk r15 }
{ shru r5, r6, r7 ; move r15, r16 }
{ shru r5, r6, r7 ; mz r15, r16, r17 }
{ shru r5, r6, r7 ; or r15, r16, r17 ; ld1s r25, r26 }
{ shru r5, r6, r7 ; prefetch r25 ; jrp r15 }
{ shru r5, r6, r7 ; prefetch_l1 r25 ; cmpeq r15, r16, r17 }
{ shru r5, r6, r7 ; prefetch_l1 r25 }
{ shru r5, r6, r7 ; prefetch_l1_fault r25 ; shli r15, r16, 5 }
{ shru r5, r6, r7 ; prefetch_l2 r25 ; rotli r15, r16, 5 }
{ shru r5, r6, r7 ; prefetch_l2_fault r25 ; mnz r15, r16, r17 }
{ shru r5, r6, r7 ; prefetch_l3 r25 ; fnop }
{ shru r5, r6, r7 ; prefetch_l3_fault r25 ; cmpeq r15, r16, r17 }
{ shru r5, r6, r7 ; prefetch_l3_fault r25 }
{ shru r5, r6, r7 ; shl r15, r16, r17 ; ld r25, r26 }
{ shru r5, r6, r7 ; shl1addx r15, r16, r17 ; ld1s r25, r26 }
{ shru r5, r6, r7 ; shl2addx r15, r16, r17 ; ld2s r25, r26 }
{ shru r5, r6, r7 ; shl3addx r15, r16, r17 ; ld4s r25, r26 }
{ shru r5, r6, r7 ; shrs r15, r16, r17 ; ld4s r25, r26 }
{ shru r5, r6, r7 ; shru r15, r16, r17 ; prefetch r25 }
{ shru r5, r6, r7 ; st r25, r26 ; cmpeq r15, r16, r17 }
{ shru r5, r6, r7 ; st r25, r26 }
{ shru r5, r6, r7 ; st1 r25, r26 ; shli r15, r16, 5 }
{ shru r5, r6, r7 ; st2 r25, r26 ; rotl r15, r16, r17 }
{ shru r5, r6, r7 ; st4 r25, r26 ; jrp r15 }
{ shru r5, r6, r7 ; sub r15, r16, r17 ; ld2s r25, r26 }
{ shru r5, r6, r7 ; v1cmpeqi r15, r16, 5 }
{ shru r5, r6, r7 ; v2mins r15, r16, r17 }
{ shru r5, r6, r7 ; xor r15, r16, r17 ; prefetch_l3 r25 }
{ shrui r15, r16, 5 ; addi r5, r6, 5 ; prefetch_l3_fault r25 }
{ shrui r15, r16, 5 ; addxi r5, r6, 5 ; st r25, r26 }
{ shrui r15, r16, 5 ; andi r5, r6, 5 ; st r25, r26 }
{ shrui r15, r16, 5 ; cmoveqz r5, r6, r7 ; prefetch_l3_fault r25 }
{ shrui r15, r16, 5 ; cmpeq r5, r6, r7 ; st1 r25, r26 }
{ shrui r15, r16, 5 ; cmples r5, r6, r7 ; st4 r25, r26 }
{ shrui r15, r16, 5 ; cmpltsi r5, r6, 5 ; ld r25, r26 }
{ shrui r15, r16, 5 ; cmpne r5, r6, r7 ; ld1s r25, r26 }
{ shrui r15, r16, 5 ; ctz r5, r6 ; prefetch_l3_fault r25 }
{ shrui r15, r16, 5 ; fsingle_mul2 r5, r6, r7 }
{ shrui r15, r16, 5 ; info 19 }
{ shrui r15, r16, 5 ; ld r25, r26 ; pcnt r5, r6 }
{ shrui r15, r16, 5 ; ld1s r25, r26 ; cmpltu r5, r6, r7 }
{ shrui r15, r16, 5 ; ld1s r25, r26 ; sub r5, r6, r7 }
{ shrui r15, r16, 5 ; ld1u r25, r26 ; mulax r5, r6, r7 }
{ shrui r15, r16, 5 ; ld2s r25, r26 ; cmpeq r5, r6, r7 }
{ shrui r15, r16, 5 ; ld2s r25, r26 ; shl3addx r5, r6, r7 }
{ shrui r15, r16, 5 ; ld2u r25, r26 ; mul_ls_ls r5, r6, r7 }
{ shrui r15, r16, 5 ; ld4s r25, r26 ; addxi r5, r6, 5 }
{ shrui r15, r16, 5 ; ld4s r25, r26 ; shl r5, r6, r7 }
{ shrui r15, r16, 5 ; ld4u r25, r26 ; info 19 }
{ shrui r15, r16, 5 ; ld4u r25, r26 ; tblidxb3 r5, r6 }
{ shrui r15, r16, 5 ; move r5, r6 ; st4 r25, r26 }
{ shrui r15, r16, 5 ; mul_hs_hs r5, r6, r7 }
{ shrui r15, r16, 5 ; mul_ls_ls r5, r6, r7 ; st1 r25, r26 }
{ shrui r15, r16, 5 ; mula_hs_hs r5, r6, r7 ; st2 r25, r26 }
{ shrui r15, r16, 5 ; mula_ls_ls r5, r6, r7 ; prefetch_l3_fault r25 }
{ shrui r15, r16, 5 ; mulax r5, r6, r7 ; st r25, r26 }
{ shrui r15, r16, 5 ; mz r5, r6, r7 ; st2 r25, r26 }
{ shrui r15, r16, 5 ; nor r5, r6, r7 }
{ shrui r15, r16, 5 ; prefetch r25 ; add r5, r6, r7 }
{ shrui r15, r16, 5 ; prefetch r25 ; revbytes r5, r6 }
{ shrui r15, r16, 5 ; prefetch_l1 r25 ; ctz r5, r6 }
{ shrui r15, r16, 5 ; prefetch_l1 r25 ; tblidxb0 r5, r6 }
{ shrui r15, r16, 5 ; prefetch_l1_fault r25 ; mz r5, r6, r7 }
{ shrui r15, r16, 5 ; prefetch_l2 r25 ; cmples r5, r6, r7 }
{ shrui r15, r16, 5 ; prefetch_l2 r25 ; shrs r5, r6, r7 }
{ shrui r15, r16, 5 ; prefetch_l2_fault r25 ; mula_hs_hs r5, r6, r7 }
{ shrui r15, r16, 5 ; prefetch_l3 r25 ; andi r5, r6, 5 }
{ shrui r15, r16, 5 ; prefetch_l3 r25 ; shl1addx r5, r6, r7 }
{ shrui r15, r16, 5 ; prefetch_l3_fault r25 ; move r5, r6 }
{ shrui r15, r16, 5 ; prefetch_l3_fault r25 }
{ shrui r15, r16, 5 ; rotl r5, r6, r7 ; ld1s r25, r26 }
{ shrui r15, r16, 5 ; shl r5, r6, r7 ; ld2s r25, r26 }
{ shrui r15, r16, 5 ; shl1addx r5, r6, r7 ; ld2u r25, r26 }
{ shrui r15, r16, 5 ; shl2addx r5, r6, r7 ; ld4u r25, r26 }
{ shrui r15, r16, 5 ; shl3addx r5, r6, r7 ; prefetch_l1 r25 }
{ shrui r15, r16, 5 ; shrs r5, r6, r7 ; prefetch_l1 r25 }
{ shrui r15, r16, 5 ; shru r5, r6, r7 ; prefetch_l2 r25 }
{ shrui r15, r16, 5 ; st r25, r26 ; cmpeq r5, r6, r7 }
{ shrui r15, r16, 5 ; st r25, r26 ; shl3addx r5, r6, r7 }
{ shrui r15, r16, 5 ; st1 r25, r26 ; mul_ls_ls r5, r6, r7 }
{ shrui r15, r16, 5 ; st2 r25, r26 ; addxi r5, r6, 5 }
{ shrui r15, r16, 5 ; st2 r25, r26 ; shl r5, r6, r7 }
{ shrui r15, r16, 5 ; st4 r25, r26 ; info 19 }
{ shrui r15, r16, 5 ; st4 r25, r26 ; tblidxb3 r5, r6 }
{ shrui r15, r16, 5 ; subx r5, r6, r7 }
{ shrui r15, r16, 5 ; tblidxb2 r5, r6 ; ld r25, r26 }
{ shrui r15, r16, 5 ; v1adduc r5, r6, r7 }
{ shrui r15, r16, 5 ; v1shrui r5, r6, 5 }
{ shrui r15, r16, 5 ; v2shrs r5, r6, r7 }
{ shrui r5, r6, 5 ; add r15, r16, r17 ; ld2s r25, r26 }
{ shrui r5, r6, 5 ; addx r15, r16, r17 ; ld2u r25, r26 }
{ shrui r5, r6, 5 ; and r15, r16, r17 ; ld2u r25, r26 }
{ shrui r5, r6, 5 ; cmpeq r15, r16, r17 ; ld4u r25, r26 }
{ shrui r5, r6, 5 ; cmples r15, r16, r17 ; ld4u r25, r26 }
{ shrui r5, r6, 5 ; cmplts r15, r16, r17 ; prefetch_l1 r25 }
{ shrui r5, r6, 5 ; cmpltu r15, r16, r17 ; prefetch_l2 r25 }
{ shrui r5, r6, 5 ; fetchand4 r15, r16, r17 }
{ shrui r5, r6, 5 ; ill ; st r25, r26 }
{ shrui r5, r6, 5 ; jalr r15 ; prefetch_l3_fault r25 }
{ shrui r5, r6, 5 ; jr r15 ; st1 r25, r26 }
{ shrui r5, r6, 5 ; ld r25, r26 ; info 19 }
{ shrui r5, r6, 5 ; ld1s r25, r26 ; cmples r15, r16, r17 }
{ shrui r5, r6, 5 ; ld1u r15, r16 }
{ shrui r5, r6, 5 ; ld1u r25, r26 ; shrs r15, r16, r17 }
{ shrui r5, r6, 5 ; ld2s r25, r26 ; rotli r15, r16, 5 }
{ shrui r5, r6, 5 ; ld2u r25, r26 ; lnk r15 }
{ shrui r5, r6, 5 ; ld4s r25, r26 ; cmpltu r15, r16, r17 }
{ shrui r5, r6, 5 ; ld4u r25, r26 ; addxi r15, r16, 5 }
{ shrui r5, r6, 5 ; ld4u r25, r26 ; sub r15, r16, r17 }
{ shrui r5, r6, 5 ; lnk r15 }
{ shrui r5, r6, 5 ; move r15, r16 }
{ shrui r5, r6, 5 ; mz r15, r16, r17 }
{ shrui r5, r6, 5 ; or r15, r16, r17 ; ld1s r25, r26 }
{ shrui r5, r6, 5 ; prefetch r25 ; jrp r15 }
{ shrui r5, r6, 5 ; prefetch_l1 r25 ; cmpeq r15, r16, r17 }
{ shrui r5, r6, 5 ; prefetch_l1 r25 }
{ shrui r5, r6, 5 ; prefetch_l1_fault r25 ; shli r15, r16, 5 }
{ shrui r5, r6, 5 ; prefetch_l2 r25 ; rotli r15, r16, 5 }
{ shrui r5, r6, 5 ; prefetch_l2_fault r25 ; mnz r15, r16, r17 }
{ shrui r5, r6, 5 ; prefetch_l3 r25 ; fnop }
{ shrui r5, r6, 5 ; prefetch_l3_fault r25 ; cmpeq r15, r16, r17 }
{ shrui r5, r6, 5 ; prefetch_l3_fault r25 }
{ shrui r5, r6, 5 ; shl r15, r16, r17 ; ld r25, r26 }
{ shrui r5, r6, 5 ; shl1addx r15, r16, r17 ; ld1s r25, r26 }
{ shrui r5, r6, 5 ; shl2addx r15, r16, r17 ; ld2s r25, r26 }
{ shrui r5, r6, 5 ; shl3addx r15, r16, r17 ; ld4s r25, r26 }
{ shrui r5, r6, 5 ; shrs r15, r16, r17 ; ld4s r25, r26 }
{ shrui r5, r6, 5 ; shru r15, r16, r17 ; prefetch r25 }
{ shrui r5, r6, 5 ; st r25, r26 ; cmpeq r15, r16, r17 }
{ shrui r5, r6, 5 ; st r25, r26 }
{ shrui r5, r6, 5 ; st1 r25, r26 ; shli r15, r16, 5 }
{ shrui r5, r6, 5 ; st2 r25, r26 ; rotl r15, r16, r17 }
{ shrui r5, r6, 5 ; st4 r25, r26 ; jrp r15 }
{ shrui r5, r6, 5 ; sub r15, r16, r17 ; ld2s r25, r26 }
{ shrui r5, r6, 5 ; v1cmpeqi r15, r16, 5 }
{ shrui r5, r6, 5 ; v2mins r15, r16, r17 }
{ shrui r5, r6, 5 ; xor r15, r16, r17 ; prefetch_l3 r25 }
{ shrux r15, r16, r17 ; crc32_8 r5, r6, r7 }
{ shrux r15, r16, r17 ; mula_hs_hu r5, r6, r7 }
{ shrux r15, r16, r17 ; subx r5, r6, r7 }
{ shrux r15, r16, r17 ; v1mz r5, r6, r7 }
{ shrux r15, r16, r17 ; v2packuc r5, r6, r7 }
{ shrux r5, r6, r7 ; cmples r15, r16, r17 }
{ shrux r5, r6, r7 ; ld2s r15, r16 }
{ shrux r5, r6, r7 ; prefetch_add_l1_fault r15, 5 }
{ shrux r5, r6, r7 ; stnt1 r15, r16 }
{ shrux r5, r6, r7 ; v2addsc r15, r16, r17 }
{ shrux r5, r6, r7 ; v4subsc r15, r16, r17 }
{ shruxi r15, r16, 5 ; dblalign4 r5, r6, r7 }
{ shruxi r15, r16, 5 ; mula_hu_ls r5, r6, r7 }
{ shruxi r15, r16, 5 ; tblidxb2 r5, r6 }
{ shruxi r15, r16, 5 ; v1shli r5, r6, 5 }
{ shruxi r15, r16, 5 ; v2sadu r5, r6, r7 }
{ shruxi r5, r6, 5 ; cmpltu r15, r16, r17 }
{ shruxi r5, r6, 5 ; ld4s r15, r16 }
{ shruxi r5, r6, 5 ; prefetch_add_l3_fault r15, 5 }
{ shruxi r5, r6, 5 ; stnt4 r15, r16 }
{ shruxi r5, r6, 5 ; v2cmpleu r15, r16, r17 }
{ shufflebytes r5, r6, r7 ; add r15, r16, r17 }
{ shufflebytes r5, r6, r7 ; info 19 }
{ shufflebytes r5, r6, r7 ; mfspr r16, 0x5 }
{ shufflebytes r5, r6, r7 ; shru r15, r16, r17 }
{ shufflebytes r5, r6, r7 ; v1minui r15, r16, 5 }
{ shufflebytes r5, r6, r7 ; v2shrui r15, r16, 5 }
{ st r15, r16 ; cmpne r5, r6, r7 }
{ st r15, r16 ; mul_hs_ls r5, r6, r7 }
{ st r15, r16 ; shlxi r5, r6, 5 }
{ st r15, r16 ; v1int_l r5, r6, r7 }
{ st r15, r16 ; v2mins r5, r6, r7 }
{ st r25, r26 ; add r15, r16, r17 ; and r5, r6, r7 }
{ st r25, r26 ; add r15, r16, r17 ; shl1add r5, r6, r7 }
{ st r25, r26 ; add r5, r6, r7 ; lnk r15 }
{ st r25, r26 ; addi r15, r16, 5 ; cmpltsi r5, r6, 5 }
{ st r25, r26 ; addi r15, r16, 5 ; shrui r5, r6, 5 }
{ st r25, r26 ; addi r5, r6, 5 ; shl r15, r16, r17 }
{ st r25, r26 ; addx r15, r16, r17 ; mul_hs_hs r5, r6, r7 }
{ st r25, r26 ; addx r5, r6, r7 ; addi r15, r16, 5 }
{ st r25, r26 ; addx r5, r6, r7 ; shru r15, r16, r17 }
{ st r25, r26 ; addxi r15, r16, 5 ; mz r5, r6, r7 }
{ st r25, r26 ; addxi r5, r6, 5 ; cmpltsi r15, r16, 5 }
{ st r25, r26 ; and r15, r16, r17 ; and r5, r6, r7 }
{ st r25, r26 ; and r15, r16, r17 ; shl1add r5, r6, r7 }
{ st r25, r26 ; and r5, r6, r7 ; lnk r15 }
{ st r25, r26 ; andi r15, r16, 5 ; cmpltsi r5, r6, 5 }
{ st r25, r26 ; andi r15, r16, 5 ; shrui r5, r6, 5 }
{ st r25, r26 ; andi r5, r6, 5 ; shl r15, r16, r17 }
{ st r25, r26 ; clz r5, r6 ; movei r15, 5 }
{ st r25, r26 ; cmoveqz r5, r6, r7 ; jalr r15 }
{ st r25, r26 ; cmovnez r5, r6, r7 ; cmplts r15, r16, r17 }
{ st r25, r26 ; cmpeq r15, r16, r17 ; addxi r5, r6, 5 }
{ st r25, r26 ; cmpeq r15, r16, r17 ; shl r5, r6, r7 }
{ st r25, r26 ; cmpeq r5, r6, r7 ; jrp r15 }
{ st r25, r26 ; cmpeqi r15, r16, 5 ; cmplts r5, r6, r7 }
{ st r25, r26 ; cmpeqi r15, r16, 5 ; shru r5, r6, r7 }
{ st r25, r26 ; cmpeqi r5, r6, 5 ; rotli r15, r16, 5 }
{ st r25, r26 ; cmples r15, r16, r17 ; movei r5, 5 }
{ st r25, r26 ; cmples r5, r6, r7 ; add r15, r16, r17 }
{ st r25, r26 ; cmples r5, r6, r7 ; shrsi r15, r16, 5 }
{ st r25, r26 ; cmpleu r15, r16, r17 ; mulx r5, r6, r7 }
{ st r25, r26 ; cmpleu r5, r6, r7 ; cmplts r15, r16, r17 }
{ st r25, r26 ; cmplts r15, r16, r17 ; addxi r5, r6, 5 }
{ st r25, r26 ; cmplts r15, r16, r17 ; shl r5, r6, r7 }
{ st r25, r26 ; cmplts r5, r6, r7 ; jrp r15 }
{ st r25, r26 ; cmpltsi r15, r16, 5 ; cmplts r5, r6, r7 }
{ st r25, r26 ; cmpltsi r15, r16, 5 ; shru r5, r6, r7 }
{ st r25, r26 ; cmpltsi r5, r6, 5 ; rotli r15, r16, 5 }
{ st r25, r26 ; cmpltu r15, r16, r17 ; movei r5, 5 }
{ st r25, r26 ; cmpltu r5, r6, r7 ; add r15, r16, r17 }
{ st r25, r26 ; cmpltu r5, r6, r7 ; shrsi r15, r16, 5 }
{ st r25, r26 ; cmpne r15, r16, r17 ; mulx r5, r6, r7 }
{ st r25, r26 ; cmpne r5, r6, r7 ; cmplts r15, r16, r17 }
{ st r25, r26 ; ctz r5, r6 ; addxi r15, r16, 5 }
{ st r25, r26 ; ctz r5, r6 ; sub r15, r16, r17 }
{ st r25, r26 ; fnop ; jalr r15 }
{ st r25, r26 ; fnop ; shl1addx r5, r6, r7 }
{ st r25, r26 ; fsingle_pack1 r5, r6 ; cmplts r15, r16, r17 }
{ st r25, r26 ; ill ; addxi r5, r6, 5 }
{ st r25, r26 ; ill ; shl r5, r6, r7 }
{ st r25, r26 ; info 19 ; cmples r5, r6, r7 }
{ st r25, r26 ; info 19 ; nor r15, r16, r17 }
{ st r25, r26 ; info 19 ; tblidxb1 r5, r6 }
{ st r25, r26 ; jalr r15 ; mz r5, r6, r7 }
{ st r25, r26 ; jalrp r15 ; cmples r5, r6, r7 }
{ st r25, r26 ; jalrp r15 ; shrs r5, r6, r7 }
{ st r25, r26 ; jr r15 ; mula_hs_hs r5, r6, r7 }
{ st r25, r26 ; jrp r15 ; andi r5, r6, 5 }
{ st r25, r26 ; jrp r15 ; shl1addx r5, r6, r7 }
{ st r25, r26 ; lnk r15 ; move r5, r6 }
{ st r25, r26 ; lnk r15 }
{ st r25, r26 ; mnz r15, r16, r17 ; revbits r5, r6 }
{ st r25, r26 ; mnz r5, r6, r7 ; info 19 }
{ st r25, r26 ; move r15, r16 ; cmpeq r5, r6, r7 }
{ st r25, r26 ; move r15, r16 ; shl3addx r5, r6, r7 }
{ st r25, r26 ; move r5, r6 ; nop }
{ st r25, r26 ; movei r15, 5 ; fsingle_pack1 r5, r6 }
{ st r25, r26 ; movei r15, 5 ; tblidxb2 r5, r6 }
{ st r25, r26 ; movei r5, 5 ; shl3add r15, r16, r17 }
{ st r25, r26 ; mul_hs_hs r5, r6, r7 ; rotl r15, r16, r17 }
{ st r25, r26 ; mul_hu_hu r5, r6, r7 ; mnz r15, r16, r17 }
{ st r25, r26 ; mul_ls_ls r5, r6, r7 ; ill }
{ st r25, r26 ; mul_lu_lu r5, r6, r7 ; cmples r15, r16, r17 }
{ st r25, r26 ; mula_hs_hs r5, r6, r7 ; addi r15, r16, 5 }
{ st r25, r26 ; mula_hs_hs r5, r6, r7 ; shru r15, r16, r17 }
{ st r25, r26 ; mula_hu_hu r5, r6, r7 ; shl2add r15, r16, r17 }
{ st r25, r26 ; mula_ls_ls r5, r6, r7 ; nor r15, r16, r17 }
{ st r25, r26 ; mula_lu_lu r5, r6, r7 ; jrp r15 }
{ st r25, r26 ; mulax r5, r6, r7 ; cmpne r15, r16, r17 }
{ st r25, r26 ; mulx r5, r6, r7 ; cmpeq r15, r16, r17 }
{ st r25, r26 ; mulx r5, r6, r7 }
{ st r25, r26 ; mz r15, r16, r17 ; revbits r5, r6 }
{ st r25, r26 ; mz r5, r6, r7 ; info 19 }
{ st r25, r26 ; nop ; and r5, r6, r7 }
{ st r25, r26 ; nop ; mul_ls_ls r5, r6, r7 }
{ st r25, r26 ; nop ; shrsi r15, r16, 5 }
{ st r25, r26 ; nor r15, r16, r17 ; movei r5, 5 }
{ st r25, r26 ; nor r5, r6, r7 ; add r15, r16, r17 }
{ st r25, r26 ; nor r5, r6, r7 ; shrsi r15, r16, 5 }
{ st r25, r26 ; or r15, r16, r17 ; mulx r5, r6, r7 }
{ st r25, r26 ; or r5, r6, r7 ; cmplts r15, r16, r17 }
{ st r25, r26 ; pcnt r5, r6 ; addxi r15, r16, 5 }
{ st r25, r26 ; pcnt r5, r6 ; sub r15, r16, r17 }
{ st r25, r26 ; revbits r5, r6 ; shl3add r15, r16, r17 }
{ st r25, r26 ; revbytes r5, r6 ; rotl r15, r16, r17 }
{ st r25, r26 ; rotl r15, r16, r17 ; move r5, r6 }
{ st r25, r26 ; rotl r15, r16, r17 }
{ st r25, r26 ; rotl r5, r6, r7 ; shrs r15, r16, r17 }
{ st r25, r26 ; rotli r15, r16, 5 ; mulax r5, r6, r7 }
{ st r25, r26 ; rotli r5, r6, 5 ; cmpleu r15, r16, r17 }
{ st r25, r26 ; shl r15, r16, r17 ; addx r5, r6, r7 }
{ st r25, r26 ; shl r15, r16, r17 ; rotli r5, r6, 5 }
{ st r25, r26 ; shl r5, r6, r7 ; jr r15 }
{ st r25, r26 ; shl1add r15, r16, r17 ; cmpleu r5, r6, r7 }
{ st r25, r26 ; shl1add r15, r16, r17 ; shrsi r5, r6, 5 }
{ st r25, r26 ; shl1add r5, r6, r7 ; rotl r15, r16, r17 }
{ st r25, r26 ; shl1addx r15, r16, r17 ; move r5, r6 }
{ st r25, r26 ; shl1addx r15, r16, r17 }
{ st r25, r26 ; shl1addx r5, r6, r7 ; shrs r15, r16, r17 }
{ st r25, r26 ; shl2add r15, r16, r17 ; mulax r5, r6, r7 }
{ st r25, r26 ; shl2add r5, r6, r7 ; cmpleu r15, r16, r17 }
{ st r25, r26 ; shl2addx r15, r16, r17 ; addx r5, r6, r7 }
{ st r25, r26 ; shl2addx r15, r16, r17 ; rotli r5, r6, 5 }
{ st r25, r26 ; shl2addx r5, r6, r7 ; jr r15 }
{ st r25, r26 ; shl3add r15, r16, r17 ; cmpleu r5, r6, r7 }
{ st r25, r26 ; shl3add r15, r16, r17 ; shrsi r5, r6, 5 }
{ st r25, r26 ; shl3add r5, r6, r7 ; rotl r15, r16, r17 }
{ st r25, r26 ; shl3addx r15, r16, r17 ; move r5, r6 }
{ st r25, r26 ; shl3addx r15, r16, r17 }
{ st r25, r26 ; shl3addx r5, r6, r7 ; shrs r15, r16, r17 }
{ st r25, r26 ; shli r15, r16, 5 ; mulax r5, r6, r7 }
{ st r25, r26 ; shli r5, r6, 5 ; cmpleu r15, r16, r17 }
{ st r25, r26 ; shrs r15, r16, r17 ; addx r5, r6, r7 }
{ st r25, r26 ; shrs r15, r16, r17 ; rotli r5, r6, 5 }
{ st r25, r26 ; shrs r5, r6, r7 ; jr r15 }
{ st r25, r26 ; shrsi r15, r16, 5 ; cmpleu r5, r6, r7 }
{ st r25, r26 ; shrsi r15, r16, 5 ; shrsi r5, r6, 5 }
{ st r25, r26 ; shrsi r5, r6, 5 ; rotl r15, r16, r17 }
{ st r25, r26 ; shru r15, r16, r17 ; move r5, r6 }
{ st r25, r26 ; shru r15, r16, r17 }
{ st r25, r26 ; shru r5, r6, r7 ; shrs r15, r16, r17 }
{ st r25, r26 ; shrui r15, r16, 5 ; mulax r5, r6, r7 }
{ st r25, r26 ; shrui r5, r6, 5 ; cmpleu r15, r16, r17 }
{ st r25, r26 ; sub r15, r16, r17 ; addx r5, r6, r7 }
{ st r25, r26 ; sub r15, r16, r17 ; rotli r5, r6, 5 }
{ st r25, r26 ; sub r5, r6, r7 ; jr r15 }
{ st r25, r26 ; subx r15, r16, r17 ; cmpleu r5, r6, r7 }
{ st r25, r26 ; subx r15, r16, r17 ; shrsi r5, r6, 5 }
{ st r25, r26 ; subx r5, r6, r7 ; rotl r15, r16, r17 }
{ st r25, r26 ; tblidxb0 r5, r6 ; mnz r15, r16, r17 }
{ st r25, r26 ; tblidxb1 r5, r6 ; ill }
{ st r25, r26 ; tblidxb2 r5, r6 ; cmples r15, r16, r17 }
{ st r25, r26 ; tblidxb3 r5, r6 ; addi r15, r16, 5 }
{ st r25, r26 ; tblidxb3 r5, r6 ; shru r15, r16, r17 }
{ st r25, r26 ; xor r15, r16, r17 ; mz r5, r6, r7 }
{ st r25, r26 ; xor r5, r6, r7 ; cmpltsi r15, r16, 5 }
{ st1 r15, r16 ; addxi r5, r6, 5 }
{ st1 r15, r16 ; fdouble_unpack_max r5, r6, r7 }
{ st1 r15, r16 ; nop }
{ st1 r15, r16 ; v1cmpeqi r5, r6, 5 }
{ st1 r15, r16 ; v2addi r5, r6, 5 }
{ st1 r15, r16 ; v2sub r5, r6, r7 }
{ st1 r25, r26 ; add r15, r16, r17 ; mul_hu_hu r5, r6, r7 }
{ st1 r25, r26 ; add r5, r6, r7 ; addx r15, r16, r17 }
{ st1 r25, r26 ; add r5, r6, r7 ; shrui r15, r16, 5 }
{ st1 r25, r26 ; addi r15, r16, 5 ; nop }
{ st1 r25, r26 ; addi r5, r6, 5 ; cmpltu r15, r16, r17 }
{ st1 r25, r26 ; addx r15, r16, r17 ; andi r5, r6, 5 }
{ st1 r25, r26 ; addx r15, r16, r17 ; shl1addx r5, r6, r7 }
{ st1 r25, r26 ; addx r5, r6, r7 ; mnz r15, r16, r17 }
{ st1 r25, r26 ; addxi r15, r16, 5 ; cmpltu r5, r6, r7 }
{ st1 r25, r26 ; addxi r15, r16, 5 ; sub r5, r6, r7 }
{ st1 r25, r26 ; addxi r5, r6, 5 ; shl1add r15, r16, r17 }
{ st1 r25, r26 ; and r15, r16, r17 ; mul_hu_hu r5, r6, r7 }
{ st1 r25, r26 ; and r5, r6, r7 ; addx r15, r16, r17 }
{ st1 r25, r26 ; and r5, r6, r7 ; shrui r15, r16, 5 }
{ st1 r25, r26 ; andi r15, r16, 5 ; nop }
{ st1 r25, r26 ; andi r5, r6, 5 ; cmpltu r15, r16, r17 }
{ st1 r25, r26 ; clz r5, r6 ; andi r15, r16, 5 }
{ st1 r25, r26 ; clz r5, r6 ; xor r15, r16, r17 }
{ st1 r25, r26 ; cmoveqz r5, r6, r7 ; shli r15, r16, 5 }
{ st1 r25, r26 ; cmovnez r5, r6, r7 ; shl r15, r16, r17 }
{ st1 r25, r26 ; cmpeq r15, r16, r17 ; mul_hs_hs r5, r6, r7 }
{ st1 r25, r26 ; cmpeq r5, r6, r7 ; addi r15, r16, 5 }
{ st1 r25, r26 ; cmpeq r5, r6, r7 ; shru r15, r16, r17 }
{ st1 r25, r26 ; cmpeqi r15, r16, 5 ; mz r5, r6, r7 }
{ st1 r25, r26 ; cmpeqi r5, r6, 5 ; cmpltsi r15, r16, 5 }
{ st1 r25, r26 ; cmples r15, r16, r17 ; and r5, r6, r7 }
{ st1 r25, r26 ; cmples r15, r16, r17 ; shl1add r5, r6, r7 }
{ st1 r25, r26 ; cmples r5, r6, r7 ; lnk r15 }
{ st1 r25, r26 ; cmpleu r15, r16, r17 ; cmpltsi r5, r6, 5 }
{ st1 r25, r26 ; cmpleu r15, r16, r17 ; shrui r5, r6, 5 }
{ st1 r25, r26 ; cmpleu r5, r6, r7 ; shl r15, r16, r17 }
{ st1 r25, r26 ; cmplts r15, r16, r17 ; mul_hs_hs r5, r6, r7 }
{ st1 r25, r26 ; cmplts r5, r6, r7 ; addi r15, r16, 5 }
{ st1 r25, r26 ; cmplts r5, r6, r7 ; shru r15, r16, r17 }
{ st1 r25, r26 ; cmpltsi r15, r16, 5 ; mz r5, r6, r7 }
{ st1 r25, r26 ; cmpltsi r5, r6, 5 ; cmpltsi r15, r16, 5 }
{ st1 r25, r26 ; cmpltu r15, r16, r17 ; and r5, r6, r7 }
{ st1 r25, r26 ; cmpltu r15, r16, r17 ; shl1add r5, r6, r7 }
{ st1 r25, r26 ; cmpltu r5, r6, r7 ; lnk r15 }
{ st1 r25, r26 ; cmpne r15, r16, r17 ; cmpltsi r5, r6, 5 }
{ st1 r25, r26 ; cmpne r15, r16, r17 ; shrui r5, r6, 5 }
{ st1 r25, r26 ; cmpne r5, r6, r7 ; shl r15, r16, r17 }
{ st1 r25, r26 ; ctz r5, r6 ; movei r15, 5 }
{ st1 r25, r26 ; fnop ; cmpeqi r15, r16, 5 }
{ st1 r25, r26 ; fnop ; mz r15, r16, r17 }
{ st1 r25, r26 ; fnop ; subx r15, r16, r17 }
{ st1 r25, r26 ; fsingle_pack1 r5, r6 ; shl r15, r16, r17 }
{ st1 r25, r26 ; ill ; mul_hs_hs r5, r6, r7 }
{ st1 r25, r26 ; info 19 ; add r5, r6, r7 }
{ st1 r25, r26 ; info 19 ; mnz r15, r16, r17 }
{ st1 r25, r26 ; info 19 ; shl3add r15, r16, r17 }
{ st1 r25, r26 ; jalr r15 ; cmpltu r5, r6, r7 }
{ st1 r25, r26 ; jalr r15 ; sub r5, r6, r7 }
{ st1 r25, r26 ; jalrp r15 ; mulax r5, r6, r7 }
{ st1 r25, r26 ; jr r15 ; cmpeq r5, r6, r7 }
{ st1 r25, r26 ; jr r15 ; shl3addx r5, r6, r7 }
{ st1 r25, r26 ; jrp r15 ; mul_ls_ls r5, r6, r7 }
{ st1 r25, r26 ; lnk r15 ; addxi r5, r6, 5 }
{ st1 r25, r26 ; lnk r15 ; shl r5, r6, r7 }
{ st1 r25, r26 ; mnz r15, r16, r17 ; info 19 }
{ st1 r25, r26 ; mnz r15, r16, r17 ; tblidxb3 r5, r6 }
{ st1 r25, r26 ; mnz r5, r6, r7 ; shl3addx r15, r16, r17 }
{ st1 r25, r26 ; move r15, r16 ; mula_ls_ls r5, r6, r7 }
{ st1 r25, r26 ; move r5, r6 ; cmpeqi r15, r16, 5 }
{ st1 r25, r26 ; movei r15, 5 ; add r5, r6, r7 }
{ st1 r25, r26 ; movei r15, 5 ; revbytes r5, r6 }
{ st1 r25, r26 ; movei r5, 5 ; jalr r15 }
{ st1 r25, r26 ; mul_hs_hs r5, r6, r7 ; cmplts r15, r16, r17 }
{ st1 r25, r26 ; mul_hu_hu r5, r6, r7 ; addxi r15, r16, 5 }
{ st1 r25, r26 ; mul_hu_hu r5, r6, r7 ; sub r15, r16, r17 }
{ st1 r25, r26 ; mul_ls_ls r5, r6, r7 ; shl3add r15, r16, r17 }
{ st1 r25, r26 ; mul_lu_lu r5, r6, r7 ; rotl r15, r16, r17 }
{ st1 r25, r26 ; mula_hs_hs r5, r6, r7 ; mnz r15, r16, r17 }
{ st1 r25, r26 ; mula_hu_hu r5, r6, r7 ; ill }
{ st1 r25, r26 ; mula_ls_ls r5, r6, r7 ; cmples r15, r16, r17 }
{ st1 r25, r26 ; mula_lu_lu r5, r6, r7 ; addi r15, r16, 5 }
{ st1 r25, r26 ; mula_lu_lu r5, r6, r7 ; shru r15, r16, r17 }
{ st1 r25, r26 ; mulax r5, r6, r7 ; shl2add r15, r16, r17 }
{ st1 r25, r26 ; mulx r5, r6, r7 ; nor r15, r16, r17 }
{ st1 r25, r26 ; mz r15, r16, r17 ; info 19 }
{ st1 r25, r26 ; mz r15, r16, r17 ; tblidxb3 r5, r6 }
{ st1 r25, r26 ; mz r5, r6, r7 ; shl3addx r15, r16, r17 }
{ st1 r25, r26 ; nop ; cmpne r5, r6, r7 }
{ st1 r25, r26 ; nop ; rotli r5, r6, 5 }
{ st1 r25, r26 ; nor r15, r16, r17 ; and r5, r6, r7 }
{ st1 r25, r26 ; nor r15, r16, r17 ; shl1add r5, r6, r7 }
{ st1 r25, r26 ; nor r5, r6, r7 ; lnk r15 }
{ st1 r25, r26 ; or r15, r16, r17 ; cmpltsi r5, r6, 5 }
{ st1 r25, r26 ; or r15, r16, r17 ; shrui r5, r6, 5 }
{ st1 r25, r26 ; or r5, r6, r7 ; shl r15, r16, r17 }
{ st1 r25, r26 ; pcnt r5, r6 ; movei r15, 5 }
{ st1 r25, r26 ; revbits r5, r6 ; jalr r15 }
{ st1 r25, r26 ; revbytes r5, r6 ; cmplts r15, r16, r17 }
{ st1 r25, r26 ; rotl r15, r16, r17 ; addxi r5, r6, 5 }
{ st1 r25, r26 ; rotl r15, r16, r17 ; shl r5, r6, r7 }
{ st1 r25, r26 ; rotl r5, r6, r7 ; jrp r15 }
{ st1 r25, r26 ; rotli r15, r16, 5 ; cmplts r5, r6, r7 }
{ st1 r25, r26 ; rotli r15, r16, 5 ; shru r5, r6, r7 }
{ st1 r25, r26 ; rotli r5, r6, 5 ; rotli r15, r16, 5 }
{ st1 r25, r26 ; shl r15, r16, r17 ; movei r5, 5 }
{ st1 r25, r26 ; shl r5, r6, r7 ; add r15, r16, r17 }
{ st1 r25, r26 ; shl r5, r6, r7 ; shrsi r15, r16, 5 }
{ st1 r25, r26 ; shl1add r15, r16, r17 ; mulx r5, r6, r7 }
{ st1 r25, r26 ; shl1add r5, r6, r7 ; cmplts r15, r16, r17 }
{ st1 r25, r26 ; shl1addx r15, r16, r17 ; addxi r5, r6, 5 }
{ st1 r25, r26 ; shl1addx r15, r16, r17 ; shl r5, r6, r7 }
{ st1 r25, r26 ; shl1addx r5, r6, r7 ; jrp r15 }
{ st1 r25, r26 ; shl2add r15, r16, r17 ; cmplts r5, r6, r7 }
{ st1 r25, r26 ; shl2add r15, r16, r17 ; shru r5, r6, r7 }
{ st1 r25, r26 ; shl2add r5, r6, r7 ; rotli r15, r16, 5 }
{ st1 r25, r26 ; shl2addx r15, r16, r17 ; movei r5, 5 }
{ st1 r25, r26 ; shl2addx r5, r6, r7 ; add r15, r16, r17 }
{ st1 r25, r26 ; shl2addx r5, r6, r7 ; shrsi r15, r16, 5 }
{ st1 r25, r26 ; shl3add r15, r16, r17 ; mulx r5, r6, r7 }
{ st1 r25, r26 ; shl3add r5, r6, r7 ; cmplts r15, r16, r17 }
{ st1 r25, r26 ; shl3addx r15, r16, r17 ; addxi r5, r6, 5 }
{ st1 r25, r26 ; shl3addx r15, r16, r17 ; shl r5, r6, r7 }
{ st1 r25, r26 ; shl3addx r5, r6, r7 ; jrp r15 }
{ st1 r25, r26 ; shli r15, r16, 5 ; cmplts r5, r6, r7 }
{ st1 r25, r26 ; shli r15, r16, 5 ; shru r5, r6, r7 }
{ st1 r25, r26 ; shli r5, r6, 5 ; rotli r15, r16, 5 }
{ st1 r25, r26 ; shrs r15, r16, r17 ; movei r5, 5 }
{ st1 r25, r26 ; shrs r5, r6, r7 ; add r15, r16, r17 }
{ st1 r25, r26 ; shrs r5, r6, r7 ; shrsi r15, r16, 5 }
{ st1 r25, r26 ; shrsi r15, r16, 5 ; mulx r5, r6, r7 }
{ st1 r25, r26 ; shrsi r5, r6, 5 ; cmplts r15, r16, r17 }
{ st1 r25, r26 ; shru r15, r16, r17 ; addxi r5, r6, 5 }
{ st1 r25, r26 ; shru r15, r16, r17 ; shl r5, r6, r7 }
{ st1 r25, r26 ; shru r5, r6, r7 ; jrp r15 }
{ st1 r25, r26 ; shrui r15, r16, 5 ; cmplts r5, r6, r7 }
{ st1 r25, r26 ; shrui r15, r16, 5 ; shru r5, r6, r7 }
{ st1 r25, r26 ; shrui r5, r6, 5 ; rotli r15, r16, 5 }
{ st1 r25, r26 ; sub r15, r16, r17 ; movei r5, 5 }
{ st1 r25, r26 ; sub r5, r6, r7 ; add r15, r16, r17 }
{ st1 r25, r26 ; sub r5, r6, r7 ; shrsi r15, r16, 5 }
{ st1 r25, r26 ; subx r15, r16, r17 ; mulx r5, r6, r7 }
{ st1 r25, r26 ; subx r5, r6, r7 ; cmplts r15, r16, r17 }
{ st1 r25, r26 ; tblidxb0 r5, r6 ; addxi r15, r16, 5 }
{ st1 r25, r26 ; tblidxb0 r5, r6 ; sub r15, r16, r17 }
{ st1 r25, r26 ; tblidxb1 r5, r6 ; shl3add r15, r16, r17 }
{ st1 r25, r26 ; tblidxb2 r5, r6 ; rotl r15, r16, r17 }
{ st1 r25, r26 ; tblidxb3 r5, r6 ; mnz r15, r16, r17 }
{ st1 r25, r26 ; xor r15, r16, r17 ; cmpltu r5, r6, r7 }
{ st1 r25, r26 ; xor r15, r16, r17 ; sub r5, r6, r7 }
{ st1 r25, r26 ; xor r5, r6, r7 ; shl1add r15, r16, r17 }
{ st1_add r15, r16, 5 ; cmula r5, r6, r7 }
{ st1_add r15, r16, 5 ; mul_hu_hu r5, r6, r7 }
{ st1_add r15, r16, 5 ; shrsi r5, r6, 5 }
{ st1_add r15, r16, 5 ; v1maxui r5, r6, 5 }
{ st1_add r15, r16, 5 ; v2mnz r5, r6, r7 }
{ st2 r15, r16 ; addxsc r5, r6, r7 }
{ st2 r15, r16 ; fnop }
{ st2 r15, r16 ; or r5, r6, r7 }
{ st2 r15, r16 ; v1cmpleu r5, r6, r7 }
{ st2 r15, r16 ; v2adiffs r5, r6, r7 }
{ st2 r15, r16 ; v4add r5, r6, r7 }
{ st2 r25, r26 ; add r15, r16, r17 ; mul_lu_lu r5, r6, r7 }
{ st2 r25, r26 ; add r5, r6, r7 ; and r15, r16, r17 }
{ st2 r25, r26 ; add r5, r6, r7 ; subx r15, r16, r17 }
{ st2 r25, r26 ; addi r15, r16, 5 ; or r5, r6, r7 }
{ st2 r25, r26 ; addi r5, r6, 5 ; fnop }
{ st2 r25, r26 ; addx r15, r16, r17 ; cmoveqz r5, r6, r7 }
{ st2 r25, r26 ; addx r15, r16, r17 ; shl2addx r5, r6, r7 }
{ st2 r25, r26 ; addx r5, r6, r7 ; movei r15, 5 }
{ st2 r25, r26 ; addxi r15, r16, 5 ; ctz r5, r6 }
{ st2 r25, r26 ; addxi r15, r16, 5 ; tblidxb0 r5, r6 }
{ st2 r25, r26 ; addxi r5, r6, 5 ; shl2add r15, r16, r17 }
{ st2 r25, r26 ; and r15, r16, r17 ; mul_lu_lu r5, r6, r7 }
{ st2 r25, r26 ; and r5, r6, r7 ; and r15, r16, r17 }
{ st2 r25, r26 ; and r5, r6, r7 ; subx r15, r16, r17 }
{ st2 r25, r26 ; andi r15, r16, 5 ; or r5, r6, r7 }
{ st2 r25, r26 ; andi r5, r6, 5 ; fnop }
{ st2 r25, r26 ; clz r5, r6 ; cmpeqi r15, r16, 5 }
{ st2 r25, r26 ; cmoveqz r5, r6, r7 ; add r15, r16, r17 }
{ st2 r25, r26 ; cmoveqz r5, r6, r7 ; shrsi r15, r16, 5 }
{ st2 r25, r26 ; cmovnez r5, r6, r7 ; shl1addx r15, r16, r17 }
{ st2 r25, r26 ; cmpeq r15, r16, r17 ; mul_ls_ls r5, r6, r7 }
{ st2 r25, r26 ; cmpeq r5, r6, r7 ; addxi r15, r16, 5 }
{ st2 r25, r26 ; cmpeq r5, r6, r7 ; sub r15, r16, r17 }
{ st2 r25, r26 ; cmpeqi r15, r16, 5 ; nor r5, r6, r7 }
{ st2 r25, r26 ; cmpeqi r5, r6, 5 ; cmpne r15, r16, r17 }
{ st2 r25, r26 ; cmples r15, r16, r17 ; clz r5, r6 }
{ st2 r25, r26 ; cmples r15, r16, r17 ; shl2add r5, r6, r7 }
{ st2 r25, r26 ; cmples r5, r6, r7 ; move r15, r16 }
{ st2 r25, r26 ; cmpleu r15, r16, r17 ; cmpne r5, r6, r7 }
{ st2 r25, r26 ; cmpleu r15, r16, r17 ; subx r5, r6, r7 }
{ st2 r25, r26 ; cmpleu r5, r6, r7 ; shl1addx r15, r16, r17 }
{ st2 r25, r26 ; cmplts r15, r16, r17 ; mul_ls_ls r5, r6, r7 }
{ st2 r25, r26 ; cmplts r5, r6, r7 ; addxi r15, r16, 5 }
{ st2 r25, r26 ; cmplts r5, r6, r7 ; sub r15, r16, r17 }
{ st2 r25, r26 ; cmpltsi r15, r16, 5 ; nor r5, r6, r7 }
{ st2 r25, r26 ; cmpltsi r5, r6, 5 ; cmpne r15, r16, r17 }
{ st2 r25, r26 ; cmpltu r15, r16, r17 ; clz r5, r6 }
{ st2 r25, r26 ; cmpltu r15, r16, r17 ; shl2add r5, r6, r7 }
{ st2 r25, r26 ; cmpltu r5, r6, r7 ; move r15, r16 }
{ st2 r25, r26 ; cmpne r15, r16, r17 ; cmpne r5, r6, r7 }
{ st2 r25, r26 ; cmpne r15, r16, r17 ; subx r5, r6, r7 }
{ st2 r25, r26 ; cmpne r5, r6, r7 ; shl1addx r15, r16, r17 }
{ st2 r25, r26 ; ctz r5, r6 ; nop }
{ st2 r25, r26 ; fnop ; cmples r15, r16, r17 }
{ st2 r25, r26 ; fnop ; nop }
{ st2 r25, r26 ; fnop ; tblidxb0 r5, r6 }
{ st2 r25, r26 ; fsingle_pack1 r5, r6 ; shl1addx r15, r16, r17 }
{ st2 r25, r26 ; ill ; mul_ls_ls r5, r6, r7 }
{ st2 r25, r26 ; info 19 ; addi r5, r6, 5 }
{ st2 r25, r26 ; info 19 ; move r15, r16 }
{ st2 r25, r26 ; info 19 ; shl3addx r15, r16, r17 }
{ st2 r25, r26 ; jalr r15 ; ctz r5, r6 }
{ st2 r25, r26 ; jalr r15 ; tblidxb0 r5, r6 }
{ st2 r25, r26 ; jalrp r15 ; mz r5, r6, r7 }
{ st2 r25, r26 ; jr r15 ; cmples r5, r6, r7 }
{ st2 r25, r26 ; jr r15 ; shrs r5, r6, r7 }
{ st2 r25, r26 ; jrp r15 ; mula_hs_hs r5, r6, r7 }
{ st2 r25, r26 ; lnk r15 ; andi r5, r6, 5 }
{ st2 r25, r26 ; lnk r15 ; shl1addx r5, r6, r7 }
{ st2 r25, r26 ; mnz r15, r16, r17 ; move r5, r6 }
{ st2 r25, r26 ; mnz r15, r16, r17 }
{ st2 r25, r26 ; mnz r5, r6, r7 ; shrs r15, r16, r17 }
{ st2 r25, r26 ; move r15, r16 ; mulax r5, r6, r7 }
{ st2 r25, r26 ; move r5, r6 ; cmpleu r15, r16, r17 }
{ st2 r25, r26 ; movei r15, 5 ; addx r5, r6, r7 }
{ st2 r25, r26 ; movei r15, 5 ; rotli r5, r6, 5 }
{ st2 r25, r26 ; movei r5, 5 ; jr r15 }
{ st2 r25, r26 ; mul_hs_hs r5, r6, r7 ; cmpltu r15, r16, r17 }
{ st2 r25, r26 ; mul_hu_hu r5, r6, r7 ; andi r15, r16, 5 }
{ st2 r25, r26 ; mul_hu_hu r5, r6, r7 ; xor r15, r16, r17 }
{ st2 r25, r26 ; mul_ls_ls r5, r6, r7 ; shli r15, r16, 5 }
{ st2 r25, r26 ; mul_lu_lu r5, r6, r7 ; shl r15, r16, r17 }
{ st2 r25, r26 ; mula_hs_hs r5, r6, r7 ; movei r15, 5 }
{ st2 r25, r26 ; mula_hu_hu r5, r6, r7 ; jalr r15 }
{ st2 r25, r26 ; mula_ls_ls r5, r6, r7 ; cmplts r15, r16, r17 }
{ st2 r25, r26 ; mula_lu_lu r5, r6, r7 ; addxi r15, r16, 5 }
{ st2 r25, r26 ; mula_lu_lu r5, r6, r7 ; sub r15, r16, r17 }
{ st2 r25, r26 ; mulax r5, r6, r7 ; shl3add r15, r16, r17 }
{ st2 r25, r26 ; mulx r5, r6, r7 ; rotl r15, r16, r17 }
{ st2 r25, r26 ; mz r15, r16, r17 ; move r5, r6 }
{ st2 r25, r26 ; mz r15, r16, r17 }
{ st2 r25, r26 ; mz r5, r6, r7 ; shrs r15, r16, r17 }
{ st2 r25, r26 ; nop ; fnop }
{ st2 r25, r26 ; nop ; shl r5, r6, r7 }
{ st2 r25, r26 ; nor r15, r16, r17 ; clz r5, r6 }
{ st2 r25, r26 ; nor r15, r16, r17 ; shl2add r5, r6, r7 }
{ st2 r25, r26 ; nor r5, r6, r7 ; move r15, r16 }
{ st2 r25, r26 ; or r15, r16, r17 ; cmpne r5, r6, r7 }
{ st2 r25, r26 ; or r15, r16, r17 ; subx r5, r6, r7 }
{ st2 r25, r26 ; or r5, r6, r7 ; shl1addx r15, r16, r17 }
{ st2 r25, r26 ; pcnt r5, r6 ; nop }
{ st2 r25, r26 ; revbits r5, r6 ; jr r15 }
{ st2 r25, r26 ; revbytes r5, r6 ; cmpltu r15, r16, r17 }
{ st2 r25, r26 ; rotl r15, r16, r17 ; andi r5, r6, 5 }
{ st2 r25, r26 ; rotl r15, r16, r17 ; shl1addx r5, r6, r7 }
{ st2 r25, r26 ; rotl r5, r6, r7 ; mnz r15, r16, r17 }
{ st2 r25, r26 ; rotli r15, r16, 5 ; cmpltu r5, r6, r7 }
{ st2 r25, r26 ; rotli r15, r16, 5 ; sub r5, r6, r7 }
{ st2 r25, r26 ; rotli r5, r6, 5 ; shl1add r15, r16, r17 }
{ st2 r25, r26 ; shl r15, r16, r17 ; mul_hu_hu r5, r6, r7 }
{ st2 r25, r26 ; shl r5, r6, r7 ; addx r15, r16, r17 }
{ st2 r25, r26 ; shl r5, r6, r7 ; shrui r15, r16, 5 }
{ st2 r25, r26 ; shl1add r15, r16, r17 ; nop }
{ st2 r25, r26 ; shl1add r5, r6, r7 ; cmpltu r15, r16, r17 }
{ st2 r25, r26 ; shl1addx r15, r16, r17 ; andi r5, r6, 5 }
{ st2 r25, r26 ; shl1addx r15, r16, r17 ; shl1addx r5, r6, r7 }
{ st2 r25, r26 ; shl1addx r5, r6, r7 ; mnz r15, r16, r17 }
{ st2 r25, r26 ; shl2add r15, r16, r17 ; cmpltu r5, r6, r7 }
{ st2 r25, r26 ; shl2add r15, r16, r17 ; sub r5, r6, r7 }
{ st2 r25, r26 ; shl2add r5, r6, r7 ; shl1add r15, r16, r17 }
{ st2 r25, r26 ; shl2addx r15, r16, r17 ; mul_hu_hu r5, r6, r7 }
{ st2 r25, r26 ; shl2addx r5, r6, r7 ; addx r15, r16, r17 }
{ st2 r25, r26 ; shl2addx r5, r6, r7 ; shrui r15, r16, 5 }
{ st2 r25, r26 ; shl3add r15, r16, r17 ; nop }
{ st2 r25, r26 ; shl3add r5, r6, r7 ; cmpltu r15, r16, r17 }
{ st2 r25, r26 ; shl3addx r15, r16, r17 ; andi r5, r6, 5 }
{ st2 r25, r26 ; shl3addx r15, r16, r17 ; shl1addx r5, r6, r7 }
{ st2 r25, r26 ; shl3addx r5, r6, r7 ; mnz r15, r16, r17 }
{ st2 r25, r26 ; shli r15, r16, 5 ; cmpltu r5, r6, r7 }
{ st2 r25, r26 ; shli r15, r16, 5 ; sub r5, r6, r7 }
{ st2 r25, r26 ; shli r5, r6, 5 ; shl1add r15, r16, r17 }
{ st2 r25, r26 ; shrs r15, r16, r17 ; mul_hu_hu r5, r6, r7 }
{ st2 r25, r26 ; shrs r5, r6, r7 ; addx r15, r16, r17 }
{ st2 r25, r26 ; shrs r5, r6, r7 ; shrui r15, r16, 5 }
{ st2 r25, r26 ; shrsi r15, r16, 5 ; nop }
{ st2 r25, r26 ; shrsi r5, r6, 5 ; cmpltu r15, r16, r17 }
{ st2 r25, r26 ; shru r15, r16, r17 ; andi r5, r6, 5 }
{ st2 r25, r26 ; shru r15, r16, r17 ; shl1addx r5, r6, r7 }
{ st2 r25, r26 ; shru r5, r6, r7 ; mnz r15, r16, r17 }
{ st2 r25, r26 ; shrui r15, r16, 5 ; cmpltu r5, r6, r7 }
{ st2 r25, r26 ; shrui r15, r16, 5 ; sub r5, r6, r7 }
{ st2 r25, r26 ; shrui r5, r6, 5 ; shl1add r15, r16, r17 }
{ st2 r25, r26 ; sub r15, r16, r17 ; mul_hu_hu r5, r6, r7 }
{ st2 r25, r26 ; sub r5, r6, r7 ; addx r15, r16, r17 }
{ st2 r25, r26 ; sub r5, r6, r7 ; shrui r15, r16, 5 }
{ st2 r25, r26 ; subx r15, r16, r17 ; nop }
{ st2 r25, r26 ; subx r5, r6, r7 ; cmpltu r15, r16, r17 }
{ st2 r25, r26 ; tblidxb0 r5, r6 ; andi r15, r16, 5 }
{ st2 r25, r26 ; tblidxb0 r5, r6 ; xor r15, r16, r17 }
{ st2 r25, r26 ; tblidxb1 r5, r6 ; shli r15, r16, 5 }
{ st2 r25, r26 ; tblidxb2 r5, r6 ; shl r15, r16, r17 }
{ st2 r25, r26 ; tblidxb3 r5, r6 ; movei r15, 5 }
{ st2 r25, r26 ; xor r15, r16, r17 ; ctz r5, r6 }
{ st2 r25, r26 ; xor r15, r16, r17 ; tblidxb0 r5, r6 }
{ st2 r25, r26 ; xor r5, r6, r7 ; shl2add r15, r16, r17 }
{ st2_add r15, r16, 5 ; cmulf r5, r6, r7 }
{ st2_add r15, r16, 5 ; mul_hu_lu r5, r6, r7 }
{ st2_add r15, r16, 5 ; shrui r5, r6, 5 }
{ st2_add r15, r16, 5 ; v1minui r5, r6, 5 }
{ st2_add r15, r16, 5 ; v2muls r5, r6, r7 }
{ st4 r15, r16 ; andi r5, r6, 5 }
{ st4 r15, r16 ; fsingle_addsub2 r5, r6, r7 }
{ st4 r15, r16 ; pcnt r5, r6 }
{ st4 r15, r16 ; v1cmpltsi r5, r6, 5 }
{ st4 r15, r16 ; v2cmpeq r5, r6, r7 }
{ st4 r15, r16 ; v4int_h r5, r6, r7 }
{ st4 r25, r26 ; add r15, r16, r17 ; mula_hu_hu r5, r6, r7 }
{ st4 r25, r26 ; add r5, r6, r7 ; cmpeq r15, r16, r17 }
{ st4 r25, r26 ; add r5, r6, r7 }
{ st4 r25, r26 ; addi r15, r16, 5 ; revbits r5, r6 }
{ st4 r25, r26 ; addi r5, r6, 5 ; info 19 }
{ st4 r25, r26 ; addx r15, r16, r17 ; cmpeq r5, r6, r7 }
{ st4 r25, r26 ; addx r15, r16, r17 ; shl3addx r5, r6, r7 }
{ st4 r25, r26 ; addx r5, r6, r7 ; nop }
{ st4 r25, r26 ; addxi r15, r16, 5 ; fsingle_pack1 r5, r6 }
{ st4 r25, r26 ; addxi r15, r16, 5 ; tblidxb2 r5, r6 }
{ st4 r25, r26 ; addxi r5, r6, 5 ; shl3add r15, r16, r17 }
{ st4 r25, r26 ; and r15, r16, r17 ; mula_hu_hu r5, r6, r7 }
{ st4 r25, r26 ; and r5, r6, r7 ; cmpeq r15, r16, r17 }
{ st4 r25, r26 ; and r5, r6, r7 }
{ st4 r25, r26 ; andi r15, r16, 5 ; revbits r5, r6 }
{ st4 r25, r26 ; andi r5, r6, 5 ; info 19 }
{ st4 r25, r26 ; clz r5, r6 ; cmpleu r15, r16, r17 }
{ st4 r25, r26 ; cmoveqz r5, r6, r7 ; addx r15, r16, r17 }
{ st4 r25, r26 ; cmoveqz r5, r6, r7 ; shrui r15, r16, 5 }
{ st4 r25, r26 ; cmovnez r5, r6, r7 ; shl2addx r15, r16, r17 }
{ st4 r25, r26 ; cmpeq r15, r16, r17 ; mula_hs_hs r5, r6, r7 }
{ st4 r25, r26 ; cmpeq r5, r6, r7 ; andi r15, r16, 5 }
{ st4 r25, r26 ; cmpeq r5, r6, r7 ; xor r15, r16, r17 }
{ st4 r25, r26 ; cmpeqi r15, r16, 5 ; pcnt r5, r6 }
{ st4 r25, r26 ; cmpeqi r5, r6, 5 ; ill }
{ st4 r25, r26 ; cmples r15, r16, r17 ; cmovnez r5, r6, r7 }
{ st4 r25, r26 ; cmples r15, r16, r17 ; shl3add r5, r6, r7 }
{ st4 r25, r26 ; cmples r5, r6, r7 ; mz r15, r16, r17 }
{ st4 r25, r26 ; cmpleu r15, r16, r17 ; fnop }
{ st4 r25, r26 ; cmpleu r15, r16, r17 ; tblidxb1 r5, r6 }
{ st4 r25, r26 ; cmpleu r5, r6, r7 ; shl2addx r15, r16, r17 }
{ st4 r25, r26 ; cmplts r15, r16, r17 ; mula_hs_hs r5, r6, r7 }
{ st4 r25, r26 ; cmplts r5, r6, r7 ; andi r15, r16, 5 }
{ st4 r25, r26 ; cmplts r5, r6, r7 ; xor r15, r16, r17 }
{ st4 r25, r26 ; cmpltsi r15, r16, 5 ; pcnt r5, r6 }
{ st4 r25, r26 ; cmpltsi r5, r6, 5 ; ill }
{ st4 r25, r26 ; cmpltu r15, r16, r17 ; cmovnez r5, r6, r7 }
{ st4 r25, r26 ; cmpltu r15, r16, r17 ; shl3add r5, r6, r7 }
{ st4 r25, r26 ; cmpltu r5, r6, r7 ; mz r15, r16, r17 }
{ st4 r25, r26 ; cmpne r15, r16, r17 ; fnop }
{ st4 r25, r26 ; cmpne r15, r16, r17 ; tblidxb1 r5, r6 }
{ st4 r25, r26 ; cmpne r5, r6, r7 ; shl2addx r15, r16, r17 }
{ st4 r25, r26 ; ctz r5, r6 ; or r15, r16, r17 }
{ st4 r25, r26 ; fnop ; cmpleu r15, r16, r17 }
{ st4 r25, r26 ; fnop ; nor r5, r6, r7 }
{ st4 r25, r26 ; fnop ; tblidxb2 r5, r6 }
{ st4 r25, r26 ; fsingle_pack1 r5, r6 ; shl2addx r15, r16, r17 }
{ st4 r25, r26 ; ill ; mula_hs_hs r5, r6, r7 }
{ st4 r25, r26 ; info 19 ; addx r5, r6, r7 }
{ st4 r25, r26 ; info 19 ; movei r15, 5 }
{ st4 r25, r26 ; info 19 ; shli r15, r16, 5 }
{ st4 r25, r26 ; jalr r15 ; fsingle_pack1 r5, r6 }
{ st4 r25, r26 ; jalr r15 ; tblidxb2 r5, r6 }
{ st4 r25, r26 ; jalrp r15 ; nor r5, r6, r7 }
{ st4 r25, r26 ; jr r15 ; cmplts r5, r6, r7 }
{ st4 r25, r26 ; jr r15 ; shru r5, r6, r7 }
{ st4 r25, r26 ; jrp r15 ; mula_ls_ls r5, r6, r7 }
{ st4 r25, r26 ; lnk r15 ; cmoveqz r5, r6, r7 }
{ st4 r25, r26 ; lnk r15 ; shl2addx r5, r6, r7 }
{ st4 r25, r26 ; mnz r15, r16, r17 ; mul_hs_hs r5, r6, r7 }
{ st4 r25, r26 ; mnz r5, r6, r7 ; addi r15, r16, 5 }
{ st4 r25, r26 ; mnz r5, r6, r7 ; shru r15, r16, r17 }
{ st4 r25, r26 ; move r15, r16 ; mz r5, r6, r7 }
{ st4 r25, r26 ; move r5, r6 ; cmpltsi r15, r16, 5 }
{ st4 r25, r26 ; movei r15, 5 ; and r5, r6, r7 }
{ st4 r25, r26 ; movei r15, 5 ; shl1add r5, r6, r7 }
{ st4 r25, r26 ; movei r5, 5 ; lnk r15 }
{ st4 r25, r26 ; mul_hs_hs r5, r6, r7 ; fnop }
{ st4 r25, r26 ; mul_hu_hu r5, r6, r7 ; cmpeqi r15, r16, 5 }
{ st4 r25, r26 ; mul_ls_ls r5, r6, r7 ; add r15, r16, r17 }
{ st4 r25, r26 ; mul_ls_ls r5, r6, r7 ; shrsi r15, r16, 5 }
{ st4 r25, r26 ; mul_lu_lu r5, r6, r7 ; shl1addx r15, r16, r17 }
{ st4 r25, r26 ; mula_hs_hs r5, r6, r7 ; nop }
{ st4 r25, r26 ; mula_hu_hu r5, r6, r7 ; jr r15 }
{ st4 r25, r26 ; mula_ls_ls r5, r6, r7 ; cmpltu r15, r16, r17 }
{ st4 r25, r26 ; mula_lu_lu r5, r6, r7 ; andi r15, r16, 5 }
{ st4 r25, r26 ; mula_lu_lu r5, r6, r7 ; xor r15, r16, r17 }
{ st4 r25, r26 ; mulax r5, r6, r7 ; shli r15, r16, 5 }
{ st4 r25, r26 ; mulx r5, r6, r7 ; shl r15, r16, r17 }
{ st4 r25, r26 ; mz r15, r16, r17 ; mul_hs_hs r5, r6, r7 }
{ st4 r25, r26 ; mz r5, r6, r7 ; addi r15, r16, 5 }
{ st4 r25, r26 ; mz r5, r6, r7 ; shru r15, r16, r17 }
{ st4 r25, r26 ; nop ; ill }
{ st4 r25, r26 ; nop ; shl1add r5, r6, r7 }
{ st4 r25, r26 ; nor r15, r16, r17 ; cmovnez r5, r6, r7 }
{ st4 r25, r26 ; nor r15, r16, r17 ; shl3add r5, r6, r7 }
{ st4 r25, r26 ; nor r5, r6, r7 ; mz r15, r16, r17 }
{ st4 r25, r26 ; or r15, r16, r17 ; fnop }
{ st4 r25, r26 ; or r15, r16, r17 ; tblidxb1 r5, r6 }
{ st4 r25, r26 ; or r5, r6, r7 ; shl2addx r15, r16, r17 }
{ st4 r25, r26 ; pcnt r5, r6 ; or r15, r16, r17 }
{ st4 r25, r26 ; revbits r5, r6 ; lnk r15 }
{ st4 r25, r26 ; revbytes r5, r6 ; fnop }
{ st4 r25, r26 ; rotl r15, r16, r17 ; cmoveqz r5, r6, r7 }
{ st4 r25, r26 ; rotl r15, r16, r17 ; shl2addx r5, r6, r7 }
{ st4 r25, r26 ; rotl r5, r6, r7 ; movei r15, 5 }
{ st4 r25, r26 ; rotli r15, r16, 5 ; ctz r5, r6 }
{ st4 r25, r26 ; rotli r15, r16, 5 ; tblidxb0 r5, r6 }
{ st4 r25, r26 ; rotli r5, r6, 5 ; shl2add r15, r16, r17 }
{ st4 r25, r26 ; shl r15, r16, r17 ; mul_lu_lu r5, r6, r7 }
{ st4 r25, r26 ; shl r5, r6, r7 ; and r15, r16, r17 }
{ st4 r25, r26 ; shl r5, r6, r7 ; subx r15, r16, r17 }
{ st4 r25, r26 ; shl1add r15, r16, r17 ; or r5, r6, r7 }
{ st4 r25, r26 ; shl1add r5, r6, r7 ; fnop }
{ st4 r25, r26 ; shl1addx r15, r16, r17 ; cmoveqz r5, r6, r7 }
{ st4 r25, r26 ; shl1addx r15, r16, r17 ; shl2addx r5, r6, r7 }
{ st4 r25, r26 ; shl1addx r5, r6, r7 ; movei r15, 5 }
{ st4 r25, r26 ; shl2add r15, r16, r17 ; ctz r5, r6 }
{ st4 r25, r26 ; shl2add r15, r16, r17 ; tblidxb0 r5, r6 }
{ st4 r25, r26 ; shl2add r5, r6, r7 ; shl2add r15, r16, r17 }
{ st4 r25, r26 ; shl2addx r15, r16, r17 ; mul_lu_lu r5, r6, r7 }
{ st4 r25, r26 ; shl2addx r5, r6, r7 ; and r15, r16, r17 }
{ st4 r25, r26 ; shl2addx r5, r6, r7 ; subx r15, r16, r17 }
{ st4 r25, r26 ; shl3add r15, r16, r17 ; or r5, r6, r7 }
{ st4 r25, r26 ; shl3add r5, r6, r7 ; fnop }
{ st4 r25, r26 ; shl3addx r15, r16, r17 ; cmoveqz r5, r6, r7 }
{ st4 r25, r26 ; shl3addx r15, r16, r17 ; shl2addx r5, r6, r7 }
{ st4 r25, r26 ; shl3addx r5, r6, r7 ; movei r15, 5 }
{ st4 r25, r26 ; shli r15, r16, 5 ; ctz r5, r6 }
{ st4 r25, r26 ; shli r15, r16, 5 ; tblidxb0 r5, r6 }
{ st4 r25, r26 ; shli r5, r6, 5 ; shl2add r15, r16, r17 }
{ st4 r25, r26 ; shrs r15, r16, r17 ; mul_lu_lu r5, r6, r7 }
{ st4 r25, r26 ; shrs r5, r6, r7 ; and r15, r16, r17 }
{ st4 r25, r26 ; shrs r5, r6, r7 ; subx r15, r16, r17 }
{ st4 r25, r26 ; shrsi r15, r16, 5 ; or r5, r6, r7 }
{ st4 r25, r26 ; shrsi r5, r6, 5 ; fnop }
{ st4 r25, r26 ; shru r15, r16, r17 ; cmoveqz r5, r6, r7 }
{ st4 r25, r26 ; shru r15, r16, r17 ; shl2addx r5, r6, r7 }
{ st4 r25, r26 ; shru r5, r6, r7 ; movei r15, 5 }
{ st4 r25, r26 ; shrui r15, r16, 5 ; ctz r5, r6 }
{ st4 r25, r26 ; shrui r15, r16, 5 ; tblidxb0 r5, r6 }
{ st4 r25, r26 ; shrui r5, r6, 5 ; shl2add r15, r16, r17 }
{ st4 r25, r26 ; sub r15, r16, r17 ; mul_lu_lu r5, r6, r7 }
{ st4 r25, r26 ; sub r5, r6, r7 ; and r15, r16, r17 }
{ st4 r25, r26 ; sub r5, r6, r7 ; subx r15, r16, r17 }
{ st4 r25, r26 ; subx r15, r16, r17 ; or r5, r6, r7 }
{ st4 r25, r26 ; subx r5, r6, r7 ; fnop }
{ st4 r25, r26 ; tblidxb0 r5, r6 ; cmpeqi r15, r16, 5 }
{ st4 r25, r26 ; tblidxb1 r5, r6 ; add r15, r16, r17 }
{ st4 r25, r26 ; tblidxb1 r5, r6 ; shrsi r15, r16, 5 }
{ st4 r25, r26 ; tblidxb2 r5, r6 ; shl1addx r15, r16, r17 }
{ st4 r25, r26 ; tblidxb3 r5, r6 ; nop }
{ st4 r25, r26 ; xor r15, r16, r17 ; fsingle_pack1 r5, r6 }
{ st4 r25, r26 ; xor r15, r16, r17 ; tblidxb2 r5, r6 }
{ st4 r25, r26 ; xor r5, r6, r7 ; shl3add r15, r16, r17 }
{ st4_add r15, r16, 5 ; cmulh r5, r6, r7 }
{ st4_add r15, r16, 5 ; mul_ls_lu r5, r6, r7 }
{ st4_add r15, r16, 5 ; shruxi r5, r6, 5 }
{ st4_add r15, r16, 5 ; v1multu r5, r6, r7 }
{ st4_add r15, r16, 5 ; v2mz r5, r6, r7 }
{ st_add r15, r16, 5 ; bfextu r5, r6, 5, 7 }
{ st_add r15, r16, 5 ; fsingle_mul2 r5, r6, r7 }
{ st_add r15, r16, 5 ; revbytes r5, r6 }
{ st_add r15, r16, 5 ; v1cmpltui r5, r6, 5 }
{ st_add r15, r16, 5 ; v2cmples r5, r6, r7 }
{ st_add r15, r16, 5 ; v4packsc r5, r6, r7 }
{ stnt r15, r16 ; crc32_32 r5, r6, r7 }
{ stnt r15, r16 ; mula_hs_hs r5, r6, r7 }
{ stnt r15, r16 ; sub r5, r6, r7 }
{ stnt r15, r16 ; v1mulus r5, r6, r7 }
{ stnt r15, r16 ; v2packl r5, r6, r7 }
{ stnt1 r15, r16 ; clz r5, r6 }
{ stnt1 r15, r16 ; fsingle_pack2 r5, r6, r7 }
{ stnt1 r15, r16 ; rotli r5, r6, 5 }
{ stnt1 r15, r16 ; v1ddotpu r5, r6, r7 }
{ stnt1 r15, r16 ; v2cmplts r5, r6, r7 }
{ stnt1 r15, r16 ; v4shlsc r5, r6, r7 }
{ stnt1_add r15, r16, 5 ; ctz r5, r6 }
{ stnt1_add r15, r16, 5 ; mula_hs_ls r5, r6, r7 }
{ stnt1_add r15, r16, 5 ; subxsc r5, r6, r7 }
{ stnt1_add r15, r16, 5 ; v1sadau r5, r6, r7 }
{ stnt1_add r15, r16, 5 ; v2sadas r5, r6, r7 }
{ stnt2 r15, r16 ; cmovnez r5, r6, r7 }
{ stnt2 r15, r16 ; info 19 }
{ stnt2 r15, r16 ; shl16insli r5, r6, 0x1234 }
{ stnt2 r15, r16 ; v1ddotpus r5, r6, r7 }
{ stnt2 r15, r16 ; v2cmpltu r5, r6, r7 }
{ stnt2 r15, r16 ; v4shru r5, r6, r7 }
{ stnt2_add r15, r16, 5 ; dblalign2 r5, r6, r7 }
{ stnt2_add r15, r16, 5 ; mula_hu_hu r5, r6, r7 }
{ stnt2_add r15, r16, 5 ; tblidxb1 r5, r6 }
{ stnt2_add r15, r16, 5 ; v1shl r5, r6, r7 }
{ stnt2_add r15, r16, 5 ; v2sads r5, r6, r7 }
{ stnt4 r15, r16 ; cmpeqi r5, r6, 5 }
{ stnt4 r15, r16 ; mm r5, r6, 5, 7 }
{ stnt4 r15, r16 ; shl1addx r5, r6, r7 }
{ stnt4 r15, r16 ; v1dotp r5, r6, r7 }
{ stnt4 r15, r16 ; v2cmpne r5, r6, r7 }
{ stnt4 r15, r16 ; v4subsc r5, r6, r7 }
{ stnt4_add r15, r16, 5 ; dblalign6 r5, r6, r7 }
{ stnt4_add r15, r16, 5 ; mula_hu_lu r5, r6, r7 }
{ stnt4_add r15, r16, 5 ; tblidxb3 r5, r6 }
{ stnt4_add r15, r16, 5 ; v1shrs r5, r6, r7 }
{ stnt4_add r15, r16, 5 ; v2shl r5, r6, r7 }
{ stnt_add r15, r16, 5 ; cmpleu r5, r6, r7 }
{ stnt_add r15, r16, 5 ; move r5, r6 }
{ stnt_add r15, r16, 5 ; shl2addx r5, r6, r7 }
{ stnt_add r15, r16, 5 ; v1dotpu r5, r6, r7 }
{ stnt_add r15, r16, 5 ; v2dotpa r5, r6, r7 }
{ stnt_add r15, r16, 5 ; xori r5, r6, 5 }
{ sub r15, r16, r17 ; addx r5, r6, r7 ; ld r25, r26 }
{ sub r15, r16, r17 ; and r5, r6, r7 ; ld r25, r26 }
{ sub r15, r16, r17 ; bfins r5, r6, 5, 7 }
{ sub r15, r16, r17 ; cmovnez r5, r6, r7 ; ld1s r25, r26 }
{ sub r15, r16, r17 ; cmpeqi r5, r6, 5 ; ld2s r25, r26 }
{ sub r15, r16, r17 ; cmpleu r5, r6, r7 ; ld4s r25, r26 }
{ sub r15, r16, r17 ; cmpltsi r5, r6, 5 ; prefetch r25 }
{ sub r15, r16, r17 ; cmpne r5, r6, r7 ; prefetch_l1 r25 }
{ sub r15, r16, r17 ; dblalign2 r5, r6, r7 }
{ sub r15, r16, r17 ; fsingle_pack1 r5, r6 ; ld4u r25, r26 }
{ sub r15, r16, r17 ; ld r25, r26 ; andi r5, r6, 5 }
{ sub r15, r16, r17 ; ld r25, r26 ; shl1addx r5, r6, r7 }
{ sub r15, r16, r17 ; ld1s r25, r26 ; move r5, r6 }
{ sub r15, r16, r17 ; ld1s r25, r26 }
{ sub r15, r16, r17 ; ld1u r25, r26 ; revbits r5, r6 }
{ sub r15, r16, r17 ; ld2s r25, r26 ; cmpne r5, r6, r7 }
{ sub r15, r16, r17 ; ld2s r25, r26 ; subx r5, r6, r7 }
{ sub r15, r16, r17 ; ld2u r25, r26 ; mulx r5, r6, r7 }
{ sub r15, r16, r17 ; ld4s r25, r26 ; cmpeqi r5, r6, 5 }
{ sub r15, r16, r17 ; ld4s r25, r26 ; shli r5, r6, 5 }
{ sub r15, r16, r17 ; ld4u r25, r26 ; mul_lu_lu r5, r6, r7 }
{ sub r15, r16, r17 ; mnz r5, r6, r7 ; ld2s r25, r26 }
{ sub r15, r16, r17 ; movei r5, 5 ; ld4s r25, r26 }
{ sub r15, r16, r17 ; mul_hu_hu r5, r6, r7 ; ld2s r25, r26 }
{ sub r15, r16, r17 ; mul_lu_lu r5, r6, r7 ; ld1u r25, r26 }
{ sub r15, r16, r17 ; mula_hu_hu r5, r6, r7 ; ld1s r25, r26 }
{ sub r15, r16, r17 ; mula_lu_lu r5, r6, r7 ; ld r25, r26 }
{ sub r15, r16, r17 ; mulx r5, r6, r7 ; ld1u r25, r26 }
{ sub r15, r16, r17 ; nop ; ld2u r25, r26 }
{ sub r15, r16, r17 ; or r5, r6, r7 ; ld4u r25, r26 }
{ sub r15, r16, r17 ; prefetch r25 ; cmoveqz r5, r6, r7 }
{ sub r15, r16, r17 ; prefetch r25 ; shl2addx r5, r6, r7 }
{ sub r15, r16, r17 ; prefetch_l1 r25 ; mul_hs_hs r5, r6, r7 }
{ sub r15, r16, r17 ; prefetch_l1_fault r25 ; addi r5, r6, 5 }
{ sub r15, r16, r17 ; prefetch_l1_fault r25 ; rotl r5, r6, r7 }
{ sub r15, r16, r17 ; prefetch_l2 r25 ; fnop }
{ sub r15, r16, r17 ; prefetch_l2 r25 ; tblidxb1 r5, r6 }
{ sub r15, r16, r17 ; prefetch_l2_fault r25 ; nop }
{ sub r15, r16, r17 ; prefetch_l3 r25 ; cmpleu r5, r6, r7 }
{ sub r15, r16, r17 ; prefetch_l3 r25 ; shrsi r5, r6, 5 }
{ sub r15, r16, r17 ; prefetch_l3_fault r25 ; mula_hu_hu r5, r6, r7 }
{ sub r15, r16, r17 ; revbits r5, r6 ; ld4u r25, r26 }
{ sub r15, r16, r17 ; rotl r5, r6, r7 ; prefetch_l1 r25 }
{ sub r15, r16, r17 ; shl r5, r6, r7 ; prefetch_l2 r25 }
{ sub r15, r16, r17 ; shl1addx r5, r6, r7 ; prefetch_l2_fault r25 }
{ sub r15, r16, r17 ; shl2addx r5, r6, r7 ; prefetch_l3_fault r25 }
{ sub r15, r16, r17 ; shl3addx r5, r6, r7 ; st1 r25, r26 }
{ sub r15, r16, r17 ; shrs r5, r6, r7 ; st1 r25, r26 }
{ sub r15, r16, r17 ; shru r5, r6, r7 ; st4 r25, r26 }
{ sub r15, r16, r17 ; st r25, r26 ; cmpne r5, r6, r7 }
{ sub r15, r16, r17 ; st r25, r26 ; subx r5, r6, r7 }
{ sub r15, r16, r17 ; st1 r25, r26 ; mulx r5, r6, r7 }
{ sub r15, r16, r17 ; st2 r25, r26 ; cmpeqi r5, r6, 5 }
{ sub r15, r16, r17 ; st2 r25, r26 ; shli r5, r6, 5 }
{ sub r15, r16, r17 ; st4 r25, r26 ; mul_lu_lu r5, r6, r7 }
{ sub r15, r16, r17 ; sub r5, r6, r7 ; ld2u r25, r26 }
{ sub r15, r16, r17 ; tblidxb0 r5, r6 ; ld4s r25, r26 }
{ sub r15, r16, r17 ; tblidxb2 r5, r6 ; prefetch r25 }
{ sub r15, r16, r17 ; v1cmplts r5, r6, r7 }
{ sub r15, r16, r17 ; v2avgs r5, r6, r7 }
{ sub r15, r16, r17 ; v4addsc r5, r6, r7 }
{ sub r5, r6, r7 ; add r15, r16, r17 ; prefetch_l2 r25 }
{ sub r5, r6, r7 ; addx r15, r16, r17 ; prefetch_l2_fault r25 }
{ sub r5, r6, r7 ; and r15, r16, r17 ; prefetch_l2_fault r25 }
{ sub r5, r6, r7 ; cmpeq r15, r16, r17 ; prefetch_l3_fault r25 }
{ sub r5, r6, r7 ; cmples r15, r16, r17 ; prefetch_l3_fault r25 }
{ sub r5, r6, r7 ; cmplts r15, r16, r17 ; st1 r25, r26 }
{ sub r5, r6, r7 ; cmpltu r15, r16, r17 ; st4 r25, r26 }
{ sub r5, r6, r7 ; fnop ; ld1s r25, r26 }
{ sub r5, r6, r7 ; info 19 ; ld1u r25, r26 }
{ sub r5, r6, r7 ; jalrp r15 ; ld1s r25, r26 }
{ sub r5, r6, r7 ; jrp r15 ; ld2s r25, r26 }
{ sub r5, r6, r7 ; ld r25, r26 ; move r15, r16 }
{ sub r5, r6, r7 ; ld1s r25, r26 ; ill }
{ sub r5, r6, r7 ; ld1u r25, r26 ; cmpeq r15, r16, r17 }
{ sub r5, r6, r7 ; ld1u r25, r26 }
{ sub r5, r6, r7 ; ld2s r25, r26 ; shl3addx r15, r16, r17 }
{ sub r5, r6, r7 ; ld2u r25, r26 ; or r15, r16, r17 }
{ sub r5, r6, r7 ; ld4s r25, r26 ; jr r15 }
{ sub r5, r6, r7 ; ld4u r25, r26 ; cmplts r15, r16, r17 }
{ sub r5, r6, r7 ; ldna_add r15, r16, 5 }
{ sub r5, r6, r7 ; mnz r15, r16, r17 ; ld2u r25, r26 }
{ sub r5, r6, r7 ; movei r15, 5 ; ld4u r25, r26 }
{ sub r5, r6, r7 ; nop ; ld4u r25, r26 }
{ sub r5, r6, r7 ; or r15, r16, r17 ; prefetch_l1 r25 }
{ sub r5, r6, r7 ; prefetch r25 ; nor r15, r16, r17 }
{ sub r5, r6, r7 ; prefetch_l1 r25 ; cmpne r15, r16, r17 }
{ sub r5, r6, r7 ; prefetch_l1_fault r25 ; andi r15, r16, 5 }
{ sub r5, r6, r7 ; prefetch_l1_fault r25 ; xor r15, r16, r17 }
{ sub r5, r6, r7 ; prefetch_l2 r25 ; shl3addx r15, r16, r17 }
{ sub r5, r6, r7 ; prefetch_l2_fault r25 ; rotl r15, r16, r17 }
{ sub r5, r6, r7 ; prefetch_l3 r25 ; lnk r15 }
{ sub r5, r6, r7 ; prefetch_l3_fault r25 ; cmpne r15, r16, r17 }
{ sub r5, r6, r7 ; rotl r15, r16, r17 ; ld4s r25, r26 }
{ sub r5, r6, r7 ; shl r15, r16, r17 ; prefetch r25 }
{ sub r5, r6, r7 ; shl1addx r15, r16, r17 ; prefetch_l1 r25 }
{ sub r5, r6, r7 ; shl2addx r15, r16, r17 ; prefetch_l2 r25 }
{ sub r5, r6, r7 ; shl3addx r15, r16, r17 ; prefetch_l3 r25 }
{ sub r5, r6, r7 ; shrs r15, r16, r17 ; prefetch_l3 r25 }
{ sub r5, r6, r7 ; shru r15, r16, r17 ; st r25, r26 }
{ sub r5, r6, r7 ; st r25, r26 ; cmpne r15, r16, r17 }
{ sub r5, r6, r7 ; st1 r25, r26 ; andi r15, r16, 5 }
{ sub r5, r6, r7 ; st1 r25, r26 ; xor r15, r16, r17 }
{ sub r5, r6, r7 ; st2 r25, r26 ; shl3add r15, r16, r17 }
{ sub r5, r6, r7 ; st4 r25, r26 ; nor r15, r16, r17 }
{ sub r5, r6, r7 ; sub r15, r16, r17 ; prefetch_l2 r25 }
{ sub r5, r6, r7 ; v1cmpne r15, r16, r17 }
{ sub r5, r6, r7 ; v2shl r15, r16, r17 }
{ sub r5, r6, r7 ; xori r15, r16, 5 }
{ subx r15, r16, r17 ; addx r5, r6, r7 ; ld r25, r26 }
{ subx r15, r16, r17 ; and r5, r6, r7 ; ld r25, r26 }
{ subx r15, r16, r17 ; bfins r5, r6, 5, 7 }
{ subx r15, r16, r17 ; cmovnez r5, r6, r7 ; ld1s r25, r26 }
{ subx r15, r16, r17 ; cmpeqi r5, r6, 5 ; ld2s r25, r26 }
{ subx r15, r16, r17 ; cmpleu r5, r6, r7 ; ld4s r25, r26 }
{ subx r15, r16, r17 ; cmpltsi r5, r6, 5 ; prefetch r25 }
{ subx r15, r16, r17 ; cmpne r5, r6, r7 ; prefetch_l1 r25 }
{ subx r15, r16, r17 ; dblalign2 r5, r6, r7 }
{ subx r15, r16, r17 ; fsingle_pack1 r5, r6 ; ld4u r25, r26 }
{ subx r15, r16, r17 ; ld r25, r26 ; andi r5, r6, 5 }
{ subx r15, r16, r17 ; ld r25, r26 ; shl1addx r5, r6, r7 }
{ subx r15, r16, r17 ; ld1s r25, r26 ; move r5, r6 }
{ subx r15, r16, r17 ; ld1s r25, r26 }
{ subx r15, r16, r17 ; ld1u r25, r26 ; revbits r5, r6 }
{ subx r15, r16, r17 ; ld2s r25, r26 ; cmpne r5, r6, r7 }
{ subx r15, r16, r17 ; ld2s r25, r26 ; subx r5, r6, r7 }
{ subx r15, r16, r17 ; ld2u r25, r26 ; mulx r5, r6, r7 }
{ subx r15, r16, r17 ; ld4s r25, r26 ; cmpeqi r5, r6, 5 }
{ subx r15, r16, r17 ; ld4s r25, r26 ; shli r5, r6, 5 }
{ subx r15, r16, r17 ; ld4u r25, r26 ; mul_lu_lu r5, r6, r7 }
{ subx r15, r16, r17 ; mnz r5, r6, r7 ; ld2s r25, r26 }
{ subx r15, r16, r17 ; movei r5, 5 ; ld4s r25, r26 }
{ subx r15, r16, r17 ; mul_hu_hu r5, r6, r7 ; ld2s r25, r26 }
{ subx r15, r16, r17 ; mul_lu_lu r5, r6, r7 ; ld1u r25, r26 }
{ subx r15, r16, r17 ; mula_hu_hu r5, r6, r7 ; ld1s r25, r26 }
{ subx r15, r16, r17 ; mula_lu_lu r5, r6, r7 ; ld r25, r26 }
{ subx r15, r16, r17 ; mulx r5, r6, r7 ; ld1u r25, r26 }
{ subx r15, r16, r17 ; nop ; ld2u r25, r26 }
{ subx r15, r16, r17 ; or r5, r6, r7 ; ld4u r25, r26 }
{ subx r15, r16, r17 ; prefetch r25 ; cmoveqz r5, r6, r7 }
{ subx r15, r16, r17 ; prefetch r25 ; shl2addx r5, r6, r7 }
{ subx r15, r16, r17 ; prefetch_l1 r25 ; mul_hs_hs r5, r6, r7 }
{ subx r15, r16, r17 ; prefetch_l1_fault r25 ; addi r5, r6, 5 }
{ subx r15, r16, r17 ; prefetch_l1_fault r25 ; rotl r5, r6, r7 }
{ subx r15, r16, r17 ; prefetch_l2 r25 ; fnop }
{ subx r15, r16, r17 ; prefetch_l2 r25 ; tblidxb1 r5, r6 }
{ subx r15, r16, r17 ; prefetch_l2_fault r25 ; nop }
{ subx r15, r16, r17 ; prefetch_l3 r25 ; cmpleu r5, r6, r7 }
{ subx r15, r16, r17 ; prefetch_l3 r25 ; shrsi r5, r6, 5 }
{ subx r15, r16, r17 ; prefetch_l3_fault r25 ; mula_hu_hu r5, r6, r7 }
{ subx r15, r16, r17 ; revbits r5, r6 ; ld4u r25, r26 }
{ subx r15, r16, r17 ; rotl r5, r6, r7 ; prefetch_l1 r25 }
{ subx r15, r16, r17 ; shl r5, r6, r7 ; prefetch_l2 r25 }
{ subx r15, r16, r17 ; shl1addx r5, r6, r7 ; prefetch_l2_fault r25 }
{ subx r15, r16, r17 ; shl2addx r5, r6, r7 ; prefetch_l3_fault r25 }
{ subx r15, r16, r17 ; shl3addx r5, r6, r7 ; st1 r25, r26 }
{ subx r15, r16, r17 ; shrs r5, r6, r7 ; st1 r25, r26 }
{ subx r15, r16, r17 ; shru r5, r6, r7 ; st4 r25, r26 }
{ subx r15, r16, r17 ; st r25, r26 ; cmpne r5, r6, r7 }
{ subx r15, r16, r17 ; st r25, r26 ; subx r5, r6, r7 }
{ subx r15, r16, r17 ; st1 r25, r26 ; mulx r5, r6, r7 }
{ subx r15, r16, r17 ; st2 r25, r26 ; cmpeqi r5, r6, 5 }
{ subx r15, r16, r17 ; st2 r25, r26 ; shli r5, r6, 5 }
{ subx r15, r16, r17 ; st4 r25, r26 ; mul_lu_lu r5, r6, r7 }
{ subx r15, r16, r17 ; sub r5, r6, r7 ; ld2u r25, r26 }
{ subx r15, r16, r17 ; tblidxb0 r5, r6 ; ld4s r25, r26 }
{ subx r15, r16, r17 ; tblidxb2 r5, r6 ; prefetch r25 }
{ subx r15, r16, r17 ; v1cmplts r5, r6, r7 }
{ subx r15, r16, r17 ; v2avgs r5, r6, r7 }
{ subx r15, r16, r17 ; v4addsc r5, r6, r7 }
{ subx r5, r6, r7 ; add r15, r16, r17 ; prefetch_l2 r25 }
{ subx r5, r6, r7 ; addx r15, r16, r17 ; prefetch_l2_fault r25 }
{ subx r5, r6, r7 ; and r15, r16, r17 ; prefetch_l2_fault r25 }
{ subx r5, r6, r7 ; cmpeq r15, r16, r17 ; prefetch_l3_fault r25 }
{ subx r5, r6, r7 ; cmples r15, r16, r17 ; prefetch_l3_fault r25 }
{ subx r5, r6, r7 ; cmplts r15, r16, r17 ; st1 r25, r26 }
{ subx r5, r6, r7 ; cmpltu r15, r16, r17 ; st4 r25, r26 }
{ subx r5, r6, r7 ; fnop ; ld1s r25, r26 }
{ subx r5, r6, r7 ; info 19 ; ld1u r25, r26 }
{ subx r5, r6, r7 ; jalrp r15 ; ld1s r25, r26 }
{ subx r5, r6, r7 ; jrp r15 ; ld2s r25, r26 }
{ subx r5, r6, r7 ; ld r25, r26 ; move r15, r16 }
{ subx r5, r6, r7 ; ld1s r25, r26 ; ill }
{ subx r5, r6, r7 ; ld1u r25, r26 ; cmpeq r15, r16, r17 }
{ subx r5, r6, r7 ; ld1u r25, r26 }
{ subx r5, r6, r7 ; ld2s r25, r26 ; shl3addx r15, r16, r17 }
{ subx r5, r6, r7 ; ld2u r25, r26 ; or r15, r16, r17 }
{ subx r5, r6, r7 ; ld4s r25, r26 ; jr r15 }
{ subx r5, r6, r7 ; ld4u r25, r26 ; cmplts r15, r16, r17 }
{ subx r5, r6, r7 ; ldna_add r15, r16, 5 }
{ subx r5, r6, r7 ; mnz r15, r16, r17 ; ld2u r25, r26 }
{ subx r5, r6, r7 ; movei r15, 5 ; ld4u r25, r26 }
{ subx r5, r6, r7 ; nop ; ld4u r25, r26 }
{ subx r5, r6, r7 ; or r15, r16, r17 ; prefetch_l1 r25 }
{ subx r5, r6, r7 ; prefetch r25 ; nor r15, r16, r17 }
{ subx r5, r6, r7 ; prefetch_l1 r25 ; cmpne r15, r16, r17 }
{ subx r5, r6, r7 ; prefetch_l1_fault r25 ; andi r15, r16, 5 }
{ subx r5, r6, r7 ; prefetch_l1_fault r25 ; xor r15, r16, r17 }
{ subx r5, r6, r7 ; prefetch_l2 r25 ; shl3addx r15, r16, r17 }
{ subx r5, r6, r7 ; prefetch_l2_fault r25 ; rotl r15, r16, r17 }
{ subx r5, r6, r7 ; prefetch_l3 r25 ; lnk r15 }
{ subx r5, r6, r7 ; prefetch_l3_fault r25 ; cmpne r15, r16, r17 }
{ subx r5, r6, r7 ; rotl r15, r16, r17 ; ld4s r25, r26 }
{ subx r5, r6, r7 ; shl r15, r16, r17 ; prefetch r25 }
{ subx r5, r6, r7 ; shl1addx r15, r16, r17 ; prefetch_l1 r25 }
{ subx r5, r6, r7 ; shl2addx r15, r16, r17 ; prefetch_l2 r25 }
{ subx r5, r6, r7 ; shl3addx r15, r16, r17 ; prefetch_l3 r25 }
{ subx r5, r6, r7 ; shrs r15, r16, r17 ; prefetch_l3 r25 }
{ subx r5, r6, r7 ; shru r15, r16, r17 ; st r25, r26 }
{ subx r5, r6, r7 ; st r25, r26 ; cmpne r15, r16, r17 }
{ subx r5, r6, r7 ; st1 r25, r26 ; andi r15, r16, 5 }
{ subx r5, r6, r7 ; st1 r25, r26 ; xor r15, r16, r17 }
{ subx r5, r6, r7 ; st2 r25, r26 ; shl3add r15, r16, r17 }
{ subx r5, r6, r7 ; st4 r25, r26 ; nor r15, r16, r17 }
{ subx r5, r6, r7 ; sub r15, r16, r17 ; prefetch_l2 r25 }
{ subx r5, r6, r7 ; v1cmpne r15, r16, r17 }
{ subx r5, r6, r7 ; v2shl r15, r16, r17 }
{ subx r5, r6, r7 ; xori r15, r16, 5 }
{ subxsc r15, r16, r17 ; fdouble_addsub r5, r6, r7 }
{ subxsc r15, r16, r17 ; mula_ls_lu r5, r6, r7 }
{ subxsc r15, r16, r17 ; v1addi r5, r6, 5 }
{ subxsc r15, r16, r17 ; v1shru r5, r6, r7 }
{ subxsc r15, r16, r17 ; v2shlsc r5, r6, r7 }
{ subxsc r5, r6, r7 ; dblalign2 r15, r16, r17 }
{ subxsc r5, r6, r7 ; ld4u_add r15, r16, 5 }
{ subxsc r5, r6, r7 ; prefetch_l2 r15 }
{ subxsc r5, r6, r7 ; sub r15, r16, r17 }
{ subxsc r5, r6, r7 ; v2cmpltu r15, r16, r17 }
{ swint3 ; nop }
{ tblidxb0 r5, r6 ; addx r15, r16, r17 ; ld r25, r26 }
{ tblidxb0 r5, r6 ; and r15, r16, r17 ; ld r25, r26 }
{ tblidxb0 r5, r6 ; cmpeq r15, r16, r17 ; ld1u r25, r26 }
{ tblidxb0 r5, r6 ; cmples r15, r16, r17 ; ld1u r25, r26 }
{ tblidxb0 r5, r6 ; cmplts r15, r16, r17 ; ld2u r25, r26 }
{ tblidxb0 r5, r6 ; cmpltu r15, r16, r17 ; ld4u r25, r26 }
{ tblidxb0 r5, r6 ; fetchadd4 r15, r16, r17 }
{ tblidxb0 r5, r6 ; ill ; prefetch_l2 r25 }
{ tblidxb0 r5, r6 ; jalr r15 ; prefetch_l1_fault r25 }
{ tblidxb0 r5, r6 ; jr r15 ; prefetch_l2_fault r25 }
{ tblidxb0 r5, r6 ; ld r25, r26 ; cmpltu r15, r16, r17 }
{ tblidxb0 r5, r6 ; ld1s r25, r26 ; and r15, r16, r17 }
{ tblidxb0 r5, r6 ; ld1s r25, r26 ; subx r15, r16, r17 }
{ tblidxb0 r5, r6 ; ld1u r25, r26 ; shl2addx r15, r16, r17 }
{ tblidxb0 r5, r6 ; ld2s r25, r26 ; nop }
{ tblidxb0 r5, r6 ; ld2u r25, r26 ; jalr r15 }
{ tblidxb0 r5, r6 ; ld4s r25, r26 ; cmples r15, r16, r17 }
{ tblidxb0 r5, r6 ; ld4u r15, r16 }
{ tblidxb0 r5, r6 ; ld4u r25, r26 ; shrs r15, r16, r17 }
{ tblidxb0 r5, r6 ; lnk r15 ; st r25, r26 }
{ tblidxb0 r5, r6 ; move r15, r16 ; st r25, r26 }
{ tblidxb0 r5, r6 ; mz r15, r16, r17 ; st r25, r26 }
{ tblidxb0 r5, r6 ; nor r15, r16, r17 ; st2 r25, r26 }
{ tblidxb0 r5, r6 ; prefetch r25 ; info 19 }
{ tblidxb0 r5, r6 ; prefetch_l1 r25 ; addx r15, r16, r17 }
{ tblidxb0 r5, r6 ; prefetch_l1 r25 ; shrui r15, r16, 5 }
{ tblidxb0 r5, r6 ; prefetch_l1_fault r25 ; shl2add r15, r16, r17 }
{ tblidxb0 r5, r6 ; prefetch_l2 r25 ; nop }
{ tblidxb0 r5, r6 ; prefetch_l2_fault r25 ; jalrp r15 }
{ tblidxb0 r5, r6 ; prefetch_l3 r25 ; cmplts r15, r16, r17 }
{ tblidxb0 r5, r6 ; prefetch_l3_fault r25 ; addx r15, r16, r17 }
{ tblidxb0 r5, r6 ; prefetch_l3_fault r25 ; shrui r15, r16, 5 }
{ tblidxb0 r5, r6 ; rotli r15, r16, 5 ; st1 r25, r26 }
{ tblidxb0 r5, r6 ; shl1add r15, r16, r17 ; st2 r25, r26 }
{ tblidxb0 r5, r6 ; shl2add r15, r16, r17 }
{ tblidxb0 r5, r6 ; shl3addx r15, r16, r17 ; ld1s r25, r26 }
{ tblidxb0 r5, r6 ; shrs r15, r16, r17 ; ld1s r25, r26 }
{ tblidxb0 r5, r6 ; shru r15, r16, r17 ; ld2s r25, r26 }
{ tblidxb0 r5, r6 ; st r25, r26 ; addx r15, r16, r17 }
{ tblidxb0 r5, r6 ; st r25, r26 ; shrui r15, r16, 5 }
{ tblidxb0 r5, r6 ; st1 r25, r26 ; shl2add r15, r16, r17 }
{ tblidxb0 r5, r6 ; st2 r25, r26 ; mz r15, r16, r17 }
{ tblidxb0 r5, r6 ; st4 r25, r26 ; info 19 }
{ tblidxb0 r5, r6 ; stnt_add r15, r16, 5 }
{ tblidxb0 r5, r6 ; v1add r15, r16, r17 }
{ tblidxb0 r5, r6 ; v2int_h r15, r16, r17 }
{ tblidxb0 r5, r6 ; xor r15, r16, r17 ; prefetch_l1 r25 }
{ tblidxb1 r5, r6 ; addi r15, r16, 5 ; prefetch_l1_fault r25 }
{ tblidxb1 r5, r6 ; addxi r15, r16, 5 ; prefetch_l2 r25 }
{ tblidxb1 r5, r6 ; andi r15, r16, 5 ; prefetch_l2 r25 }
{ tblidxb1 r5, r6 ; cmpeqi r15, r16, 5 ; prefetch_l3 r25 }
{ tblidxb1 r5, r6 ; cmpleu r15, r16, r17 ; prefetch_l3 r25 }
{ tblidxb1 r5, r6 ; cmpltsi r15, r16, 5 ; st r25, r26 }
{ tblidxb1 r5, r6 ; cmpne r15, r16, r17 ; st1 r25, r26 }
{ tblidxb1 r5, r6 ; icoh r15 }
{ tblidxb1 r5, r6 ; inv r15 }
{ tblidxb1 r5, r6 ; jr r15 ; ld r25, r26 }
{ tblidxb1 r5, r6 ; ld r25, r26 ; addi r15, r16, 5 }
{ tblidxb1 r5, r6 ; ld r25, r26 ; shru r15, r16, r17 }
{ tblidxb1 r5, r6 ; ld1s r25, r26 ; shl1addx r15, r16, r17 }
{ tblidxb1 r5, r6 ; ld1u r25, r26 ; movei r15, 5 }
{ tblidxb1 r5, r6 ; ld2s r25, r26 ; ill }
{ tblidxb1 r5, r6 ; ld2u r25, r26 ; cmpeq r15, r16, r17 }
{ tblidxb1 r5, r6 ; ld2u r25, r26 }
{ tblidxb1 r5, r6 ; ld4s r25, r26 ; shl3addx r15, r16, r17 }
{ tblidxb1 r5, r6 ; ld4u r25, r26 ; or r15, r16, r17 }
{ tblidxb1 r5, r6 ; lnk r15 ; ld2s r25, r26 }
{ tblidxb1 r5, r6 ; move r15, r16 ; ld2s r25, r26 }
{ tblidxb1 r5, r6 ; mz r15, r16, r17 ; ld2s r25, r26 }
{ tblidxb1 r5, r6 ; nor r15, r16, r17 ; ld4s r25, r26 }
{ tblidxb1 r5, r6 ; prefetch r25 ; andi r15, r16, 5 }
{ tblidxb1 r5, r6 ; prefetch r25 ; xor r15, r16, r17 }
{ tblidxb1 r5, r6 ; prefetch_l1 r25 ; shl r15, r16, r17 }
{ tblidxb1 r5, r6 ; prefetch_l1_fault r25 ; move r15, r16 }
{ tblidxb1 r5, r6 ; prefetch_l2 r25 ; ill }
{ tblidxb1 r5, r6 ; prefetch_l2_fault r25 ; cmpeqi r15, r16, 5 }
{ tblidxb1 r5, r6 ; prefetch_l3 r15 }
{ tblidxb1 r5, r6 ; prefetch_l3 r25 ; shrs r15, r16, r17 }
{ tblidxb1 r5, r6 ; prefetch_l3_fault r25 ; shl r15, r16, r17 }
{ tblidxb1 r5, r6 ; rotli r15, r16, 5 ; ld2u r25, r26 }
{ tblidxb1 r5, r6 ; shl1add r15, r16, r17 ; ld4s r25, r26 }
{ tblidxb1 r5, r6 ; shl2add r15, r16, r17 ; prefetch r25 }
{ tblidxb1 r5, r6 ; shl3add r15, r16, r17 ; prefetch_l1_fault r25 }
{ tblidxb1 r5, r6 ; shli r15, r16, 5 ; prefetch_l2_fault r25 }
{ tblidxb1 r5, r6 ; shrsi r15, r16, 5 ; prefetch_l2_fault r25 }
{ tblidxb1 r5, r6 ; shrui r15, r16, 5 ; prefetch_l3_fault r25 }
{ tblidxb1 r5, r6 ; st r25, r26 ; shl r15, r16, r17 }
{ tblidxb1 r5, r6 ; st1 r25, r26 ; move r15, r16 }
{ tblidxb1 r5, r6 ; st2 r25, r26 ; fnop }
{ tblidxb1 r5, r6 ; st4 r25, r26 ; andi r15, r16, 5 }
{ tblidxb1 r5, r6 ; st4 r25, r26 ; xor r15, r16, r17 }
{ tblidxb1 r5, r6 ; subx r15, r16, r17 ; prefetch_l1_fault r25 }
{ tblidxb1 r5, r6 ; v2addi r15, r16, 5 }
{ tblidxb1 r5, r6 ; v4sub r15, r16, r17 }
{ tblidxb2 r5, r6 ; add r15, r16, r17 ; st4 r25, r26 }
{ tblidxb2 r5, r6 ; addx r15, r16, r17 }
{ tblidxb2 r5, r6 ; and r15, r16, r17 }
{ tblidxb2 r5, r6 ; cmpeqi r15, r16, 5 ; ld1s r25, r26 }
{ tblidxb2 r5, r6 ; cmpleu r15, r16, r17 ; ld1s r25, r26 }
{ tblidxb2 r5, r6 ; cmpltsi r15, r16, 5 ; ld2s r25, r26 }
{ tblidxb2 r5, r6 ; cmpne r15, r16, r17 ; ld2u r25, r26 }
{ tblidxb2 r5, r6 ; fnop ; prefetch_l1 r25 }
{ tblidxb2 r5, r6 ; info 19 ; prefetch_l1_fault r25 }
{ tblidxb2 r5, r6 ; jalrp r15 ; prefetch_l1 r25 }
{ tblidxb2 r5, r6 ; jrp r15 ; prefetch_l2 r25 }
{ tblidxb2 r5, r6 ; ld r25, r26 ; rotli r15, r16, 5 }
{ tblidxb2 r5, r6 ; ld1s r25, r26 ; mnz r15, r16, r17 }
{ tblidxb2 r5, r6 ; ld1u r25, r26 ; cmpne r15, r16, r17 }
{ tblidxb2 r5, r6 ; ld2s r25, r26 ; and r15, r16, r17 }
{ tblidxb2 r5, r6 ; ld2s r25, r26 ; subx r15, r16, r17 }
{ tblidxb2 r5, r6 ; ld2u r25, r26 ; shl2addx r15, r16, r17 }
{ tblidxb2 r5, r6 ; ld4s r25, r26 ; nop }
{ tblidxb2 r5, r6 ; ld4u r25, r26 ; jalr r15 }
{ tblidxb2 r5, r6 ; ldnt2s_add r15, r16, 5 }
{ tblidxb2 r5, r6 ; mnz r15, r16, r17 ; prefetch_l2_fault r25 }
{ tblidxb2 r5, r6 ; movei r15, 5 ; prefetch_l3_fault r25 }
{ tblidxb2 r5, r6 ; nop ; prefetch_l3_fault r25 }
{ tblidxb2 r5, r6 ; or r15, r16, r17 ; st1 r25, r26 }
{ tblidxb2 r5, r6 ; prefetch r25 ; shl2add r15, r16, r17 }
{ tblidxb2 r5, r6 ; prefetch_l1 r25 ; jrp r15 }
{ tblidxb2 r5, r6 ; prefetch_l1_fault r25 ; cmpltu r15, r16, r17 }
{ tblidxb2 r5, r6 ; prefetch_l2 r25 ; and r15, r16, r17 }
{ tblidxb2 r5, r6 ; prefetch_l2 r25 ; subx r15, r16, r17 }
{ tblidxb2 r5, r6 ; prefetch_l2_fault r25 ; shl3add r15, r16, r17 }
{ tblidxb2 r5, r6 ; prefetch_l3 r25 ; or r15, r16, r17 }
{ tblidxb2 r5, r6 ; prefetch_l3_fault r25 ; jrp r15 }
{ tblidxb2 r5, r6 ; rotl r15, r16, r17 ; prefetch_l3 r25 }
{ tblidxb2 r5, r6 ; shl r15, r16, r17 ; st r25, r26 }
{ tblidxb2 r5, r6 ; shl1addx r15, r16, r17 ; st1 r25, r26 }
{ tblidxb2 r5, r6 ; shl2addx r15, r16, r17 ; st4 r25, r26 }
{ tblidxb2 r5, r6 ; shli r15, r16, 5 ; ld r25, r26 }
{ tblidxb2 r5, r6 ; shrsi r15, r16, 5 ; ld r25, r26 }
{ tblidxb2 r5, r6 ; shrui r15, r16, 5 ; ld1u r25, r26 }
{ tblidxb2 r5, r6 ; st r25, r26 ; jrp r15 }
{ tblidxb2 r5, r6 ; st1 r25, r26 ; cmpltu r15, r16, r17 }
{ tblidxb2 r5, r6 ; st2 r25, r26 ; addxi r15, r16, 5 }
{ tblidxb2 r5, r6 ; st2 r25, r26 ; sub r15, r16, r17 }
{ tblidxb2 r5, r6 ; st4 r25, r26 ; shl2add r15, r16, r17 }
{ tblidxb2 r5, r6 ; sub r15, r16, r17 ; st4 r25, r26 }
{ tblidxb2 r5, r6 ; v1mnz r15, r16, r17 }
{ tblidxb2 r5, r6 ; v2sub r15, r16, r17 }
{ tblidxb3 r5, r6 ; add r15, r16, r17 ; ld4u r25, r26 }
{ tblidxb3 r5, r6 ; addx r15, r16, r17 ; prefetch r25 }
{ tblidxb3 r5, r6 ; and r15, r16, r17 ; prefetch r25 }
{ tblidxb3 r5, r6 ; cmpeq r15, r16, r17 ; prefetch_l1_fault r25 }
{ tblidxb3 r5, r6 ; cmples r15, r16, r17 ; prefetch_l1_fault r25 }
{ tblidxb3 r5, r6 ; cmplts r15, r16, r17 ; prefetch_l2_fault r25 }
{ tblidxb3 r5, r6 ; cmpltu r15, r16, r17 ; prefetch_l3_fault r25 }
{ tblidxb3 r5, r6 ; finv r15 }
{ tblidxb3 r5, r6 ; ill ; st4 r25, r26 }
{ tblidxb3 r5, r6 ; jalr r15 ; st2 r25, r26 }
{ tblidxb3 r5, r6 ; jr r15 }
{ tblidxb3 r5, r6 ; ld r25, r26 ; jr r15 }
{ tblidxb3 r5, r6 ; ld1s r25, r26 ; cmpltsi r15, r16, 5 }
{ tblidxb3 r5, r6 ; ld1u r25, r26 ; addx r15, r16, r17 }
{ tblidxb3 r5, r6 ; ld1u r25, r26 ; shrui r15, r16, 5 }
{ tblidxb3 r5, r6 ; ld2s r25, r26 ; shl1addx r15, r16, r17 }
{ tblidxb3 r5, r6 ; ld2u r25, r26 ; movei r15, 5 }
{ tblidxb3 r5, r6 ; ld4s r25, r26 ; ill }
{ tblidxb3 r5, r6 ; ld4u r25, r26 ; cmpeq r15, r16, r17 }
{ tblidxb3 r5, r6 ; ld4u r25, r26 }
{ tblidxb3 r5, r6 ; mnz r15, r16, r17 ; ld r25, r26 }
{ tblidxb3 r5, r6 ; movei r15, 5 ; ld1u r25, r26 }
{ tblidxb3 r5, r6 ; nop ; ld1u r25, r26 }
{ tblidxb3 r5, r6 ; or r15, r16, r17 ; ld2u r25, r26 }
{ tblidxb3 r5, r6 ; prefetch r25 ; move r15, r16 }
{ tblidxb3 r5, r6 ; prefetch_l1 r25 ; cmpleu r15, r16, r17 }
{ tblidxb3 r5, r6 ; prefetch_l1_fault r25 ; addi r15, r16, 5 }
{ tblidxb3 r5, r6 ; prefetch_l1_fault r25 ; shru r15, r16, r17 }
{ tblidxb3 r5, r6 ; prefetch_l2 r25 ; shl1addx r15, r16, r17 }
{ tblidxb3 r5, r6 ; prefetch_l2_fault r25 ; mz r15, r16, r17 }
{ tblidxb3 r5, r6 ; prefetch_l3 r25 ; jalr r15 }
{ tblidxb3 r5, r6 ; prefetch_l3_fault r25 ; cmpleu r15, r16, r17 }
{ tblidxb3 r5, r6 ; rotl r15, r16, r17 ; ld1s r25, r26 }
{ tblidxb3 r5, r6 ; shl r15, r16, r17 ; ld2s r25, r26 }
{ tblidxb3 r5, r6 ; shl1addx r15, r16, r17 ; ld2u r25, r26 }
{ tblidxb3 r5, r6 ; shl2addx r15, r16, r17 ; ld4u r25, r26 }
{ tblidxb3 r5, r6 ; shl3addx r15, r16, r17 ; prefetch_l1 r25 }
{ tblidxb3 r5, r6 ; shrs r15, r16, r17 ; prefetch_l1 r25 }
{ tblidxb3 r5, r6 ; shru r15, r16, r17 ; prefetch_l2 r25 }
{ tblidxb3 r5, r6 ; st r25, r26 ; cmpleu r15, r16, r17 }
{ tblidxb3 r5, r6 ; st1 r25, r26 ; addi r15, r16, 5 }
{ tblidxb3 r5, r6 ; st1 r25, r26 ; shru r15, r16, r17 }
{ tblidxb3 r5, r6 ; st2 r25, r26 ; shl1add r15, r16, r17 }
{ tblidxb3 r5, r6 ; st4 r25, r26 ; move r15, r16 }
{ tblidxb3 r5, r6 ; sub r15, r16, r17 ; ld4u r25, r26 }
{ tblidxb3 r5, r6 ; v1cmplts r15, r16, r17 }
{ tblidxb3 r5, r6 ; v2mz r15, r16, r17 }
{ tblidxb3 r5, r6 ; xor r15, r16, r17 ; st1 r25, r26 }
{ v1add r15, r16, r17 ; dblalign2 r5, r6, r7 }
{ v1add r15, r16, r17 ; mula_hu_hu r5, r6, r7 }
{ v1add r15, r16, r17 ; tblidxb1 r5, r6 }
{ v1add r15, r16, r17 ; v1shl r5, r6, r7 }
{ v1add r15, r16, r17 ; v2sads r5, r6, r7 }
{ v1add r5, r6, r7 ; cmpltsi r15, r16, 5 }
{ v1add r5, r6, r7 ; ld2u_add r15, r16, 5 }
{ v1add r5, r6, r7 ; prefetch_add_l3 r15, 5 }
{ v1add r5, r6, r7 ; stnt2_add r15, r16, 5 }
{ v1add r5, r6, r7 ; v2cmples r15, r16, r17 }
{ v1add r5, r6, r7 ; xori r15, r16, 5 }
{ v1addi r15, r16, 5 ; fdouble_addsub r5, r6, r7 }
{ v1addi r15, r16, 5 ; mula_ls_lu r5, r6, r7 }
{ v1addi r15, r16, 5 ; v1addi r5, r6, 5 }
{ v1addi r15, r16, 5 ; v1shru r5, r6, r7 }
{ v1addi r15, r16, 5 ; v2shlsc r5, r6, r7 }
{ v1addi r5, r6, 5 ; dblalign2 r15, r16, r17 }
{ v1addi r5, r6, 5 ; ld4u_add r15, r16, 5 }
{ v1addi r5, r6, 5 ; prefetch_l2 r15 }
{ v1addi r5, r6, 5 ; sub r15, r16, r17 }
{ v1addi r5, r6, 5 ; v2cmpltu r15, r16, r17 }
{ v1adduc r15, r16, r17 ; addx r5, r6, r7 }
{ v1adduc r15, r16, r17 ; fdouble_sub_flags r5, r6, r7 }
{ v1adduc r15, r16, r17 ; mz r5, r6, r7 }
{ v1adduc r15, r16, r17 ; v1cmpeq r5, r6, r7 }
{ v1adduc r15, r16, r17 ; v2add r5, r6, r7 }
{ v1adduc r15, r16, r17 ; v2shrui r5, r6, 5 }
{ v1adduc r5, r6, r7 ; exch r15, r16, r17 }
{ v1adduc r5, r6, r7 ; ldnt r15, r16 }
{ v1adduc r5, r6, r7 ; raise }
{ v1adduc r5, r6, r7 ; v1addi r15, r16, 5 }
{ v1adduc r5, r6, r7 ; v2int_l r15, r16, r17 }
{ v1adiffu r5, r6, r7 ; and r15, r16, r17 }
{ v1adiffu r5, r6, r7 ; jrp r15 }
{ v1adiffu r5, r6, r7 ; nop }
{ v1adiffu r5, r6, r7 ; st2 r15, r16 }
{ v1adiffu r5, r6, r7 ; v1shru r15, r16, r17 }
{ v1adiffu r5, r6, r7 ; v4packsc r15, r16, r17 }
{ v1avgu r5, r6, r7 ; fetchand r15, r16, r17 }
{ v1avgu r5, r6, r7 ; ldnt2s_add r15, r16, 5 }
{ v1avgu r5, r6, r7 ; shl1addx r15, r16, r17 }
{ v1avgu r5, r6, r7 ; v1cmplts r15, r16, r17 }
{ v1avgu r5, r6, r7 ; v2mz r15, r16, r17 }
{ v1cmpeq r15, r16, r17 ; cmoveqz r5, r6, r7 }
{ v1cmpeq r15, r16, r17 ; fsingle_sub1 r5, r6, r7 }
{ v1cmpeq r15, r16, r17 ; shl r5, r6, r7 }
{ v1cmpeq r15, r16, r17 ; v1ddotpua r5, r6, r7 }
{ v1cmpeq r15, r16, r17 ; v2cmpltsi r5, r6, 5 }
{ v1cmpeq r15, r16, r17 ; v4shrs r5, r6, r7 }
{ v1cmpeq r5, r6, r7 ; finv r15 }
{ v1cmpeq r5, r6, r7 ; ldnt4s_add r15, r16, 5 }
{ v1cmpeq r5, r6, r7 ; shl3addx r15, r16, r17 }
{ v1cmpeq r5, r6, r7 ; v1cmpne r15, r16, r17 }
{ v1cmpeq r5, r6, r7 ; v2shl r15, r16, r17 }
{ v1cmpeqi r15, r16, 5 ; cmples r5, r6, r7 }
{ v1cmpeqi r15, r16, 5 ; mnz r5, r6, r7 }
{ v1cmpeqi r15, r16, 5 ; shl2add r5, r6, r7 }
{ v1cmpeqi r15, r16, 5 ; v1dotpa r5, r6, r7 }
{ v1cmpeqi r15, r16, 5 ; v2dotp r5, r6, r7 }
{ v1cmpeqi r15, r16, 5 ; xor r5, r6, r7 }
{ v1cmpeqi r5, r6, 5 ; icoh r15 }
{ v1cmpeqi r5, r6, 5 ; lnk r15 }
{ v1cmpeqi r5, r6, 5 ; shrs r15, r16, r17 }
{ v1cmpeqi r5, r6, 5 ; v1maxui r15, r16, 5 }
{ v1cmpeqi r5, r6, 5 ; v2shrsi r15, r16, 5 }
{ v1cmples r15, r16, r17 ; cmpltu r5, r6, r7 }
{ v1cmples r15, r16, r17 ; mul_hs_hs r5, r6, r7 }
{ v1cmples r15, r16, r17 ; shli r5, r6, 5 }
{ v1cmples r15, r16, r17 ; v1dotpusa r5, r6, r7 }
{ v1cmples r15, r16, r17 ; v2maxs r5, r6, r7 }
{ v1cmples r5, r6, r7 ; addli r15, r16, 0x1234 }
{ v1cmples r5, r6, r7 ; inv r15 }
{ v1cmples r5, r6, r7 ; move r15, r16 }
{ v1cmples r5, r6, r7 ; shrux r15, r16, r17 }
{ v1cmples r5, r6, r7 ; v1mz r15, r16, r17 }
{ v1cmples r5, r6, r7 ; v2subsc r15, r16, r17 }
{ v1cmpleu r15, r16, r17 ; cmula r5, r6, r7 }
{ v1cmpleu r15, r16, r17 ; mul_hu_hu r5, r6, r7 }
{ v1cmpleu r15, r16, r17 ; shrsi r5, r6, 5 }
{ v1cmpleu r15, r16, r17 ; v1maxui r5, r6, 5 }
{ v1cmpleu r15, r16, r17 ; v2mnz r5, r6, r7 }
{ v1cmpleu r5, r6, r7 ; addxsc r15, r16, r17 }
{ v1cmpleu r5, r6, r7 ; jr r15 }
{ v1cmpleu r5, r6, r7 ; mz r15, r16, r17 }
{ v1cmpleu r5, r6, r7 ; st1_add r15, r16, 5 }
{ v1cmpleu r5, r6, r7 ; v1shrsi r15, r16, 5 }
{ v1cmpleu r5, r6, r7 ; v4int_l r15, r16, r17 }
{ v1cmplts r15, r16, r17 ; cmulh r5, r6, r7 }
{ v1cmplts r15, r16, r17 ; mul_ls_lu r5, r6, r7 }
{ v1cmplts r15, r16, r17 ; shruxi r5, r6, 5 }
{ v1cmplts r15, r16, r17 ; v1multu r5, r6, r7 }
{ v1cmplts r15, r16, r17 ; v2mz r5, r6, r7 }
{ v1cmplts r5, r6, r7 ; cmpeqi r15, r16, 5 }
{ v1cmplts r5, r6, r7 ; ld1s_add r15, r16, 5 }
{ v1cmplts r5, r6, r7 ; ori r15, r16, 5 }
{ v1cmplts r5, r6, r7 ; st4_add r15, r16, 5 }
{ v1cmplts r5, r6, r7 ; v1subuc r15, r16, r17 }
{ v1cmplts r5, r6, r7 ; v4shrs r15, r16, r17 }
{ v1cmpltsi r15, r16, 5 ; ctz r5, r6 }
{ v1cmpltsi r15, r16, 5 ; mula_hs_ls r5, r6, r7 }
{ v1cmpltsi r15, r16, 5 ; subxsc r5, r6, r7 }
{ v1cmpltsi r15, r16, 5 ; v1sadau r5, r6, r7 }
{ v1cmpltsi r15, r16, 5 ; v2sadas r5, r6, r7 }
{ v1cmpltsi r5, r6, 5 ; cmpleu r15, r16, r17 }
{ v1cmpltsi r5, r6, 5 ; ld2s_add r15, r16, 5 }
{ v1cmpltsi r5, r6, 5 ; prefetch_add_l2 r15, 5 }
{ v1cmpltsi r5, r6, 5 ; stnt1_add r15, r16, 5 }
{ v1cmpltsi r5, r6, 5 ; v2cmpeq r15, r16, r17 }
{ v1cmpltsi r5, r6, 5 ; wh64 r15 }
{ v1cmpltu r15, r16, r17 ; dblalign6 r5, r6, r7 }
{ v1cmpltu r15, r16, r17 ; mula_hu_lu r5, r6, r7 }
{ v1cmpltu r15, r16, r17 ; tblidxb3 r5, r6 }
{ v1cmpltu r15, r16, r17 ; v1shrs r5, r6, r7 }
{ v1cmpltu r15, r16, r17 ; v2shl r5, r6, r7 }
{ v1cmpltu r5, r6, r7 ; cmpltui r15, r16, 5 }
{ v1cmpltu r5, r6, r7 ; ld4s_add r15, r16, 5 }
{ v1cmpltu r5, r6, r7 ; prefetch_l1 r15 }
{ v1cmpltu r5, r6, r7 ; stnt4_add r15, r16, 5 }
{ v1cmpltu r5, r6, r7 ; v2cmplts r15, r16, r17 }
{ v1cmpltui r15, r16, 5 ; addi r5, r6, 5 }
{ v1cmpltui r15, r16, 5 ; fdouble_pack1 r5, r6, r7 }
{ v1cmpltui r15, r16, 5 ; mulax r5, r6, r7 }
{ v1cmpltui r15, r16, 5 ; v1adiffu r5, r6, r7 }
{ v1cmpltui r15, r16, 5 ; v1sub r5, r6, r7 }
{ v1cmpltui r15, r16, 5 ; v2shrsi r5, r6, 5 }
{ v1cmpltui r5, r6, 5 ; dblalign6 r15, r16, r17 }
{ v1cmpltui r5, r6, 5 ; ldna r15, r16 }
{ v1cmpltui r5, r6, 5 ; prefetch_l3 r15 }
{ v1cmpltui r5, r6, 5 ; subxsc r15, r16, r17 }
{ v1cmpltui r5, r6, 5 ; v2cmpne r15, r16, r17 }
{ v1cmpne r15, r16, r17 ; addxli r5, r6, 0x1234 }
{ v1cmpne r15, r16, r17 ; fdouble_unpack_min r5, r6, r7 }
{ v1cmpne r15, r16, r17 ; nor r5, r6, r7 }
{ v1cmpne r15, r16, r17 ; v1cmples r5, r6, r7 }
{ v1cmpne r15, r16, r17 ; v2addsc r5, r6, r7 }
{ v1cmpne r15, r16, r17 ; v2subsc r5, r6, r7 }
{ v1cmpne r5, r6, r7 ; fetchadd r15, r16, r17 }
{ v1cmpne r5, r6, r7 ; ldnt1s_add r15, r16, 5 }
{ v1cmpne r5, r6, r7 ; rotli r15, r16, 5 }
{ v1cmpne r5, r6, r7 ; v1cmpeq r15, r16, r17 }
{ v1cmpne r5, r6, r7 ; v2maxsi r15, r16, 5 }
{ v1ddotpu r5, r6, r7 ; cmpeq r15, r16, r17 }
{ v1ddotpu r5, r6, r7 ; ld1s r15, r16 }
{ v1ddotpu r5, r6, r7 ; or r15, r16, r17 }
{ v1ddotpu r5, r6, r7 ; st4 r15, r16 }
{ v1ddotpu r5, r6, r7 ; v1sub r15, r16, r17 }
{ v1ddotpu r5, r6, r7 ; v4shlsc r15, r16, r17 }
{ v1ddotpua r5, r6, r7 ; fetchor r15, r16, r17 }
{ v1ddotpua r5, r6, r7 ; ldnt2u_add r15, r16, 5 }
{ v1ddotpua r5, r6, r7 ; shl2addx r15, r16, r17 }
{ v1ddotpua r5, r6, r7 ; v1cmpltu r15, r16, r17 }
{ v1ddotpua r5, r6, r7 ; v2packl r15, r16, r17 }
{ v1ddotpus r5, r6, r7 ; cmplts r15, r16, r17 }
{ v1ddotpus r5, r6, r7 ; ld2u r15, r16 }
{ v1ddotpus r5, r6, r7 ; prefetch_add_l2_fault r15, 5 }
{ v1ddotpus r5, r6, r7 ; stnt2 r15, r16 }
{ v1ddotpus r5, r6, r7 ; v2cmpeqi r15, r16, 5 }
{ v1ddotpus r5, r6, r7 ; xor r15, r16, r17 }
{ v1ddotpusa r5, r6, r7 ; icoh r15 }
{ v1ddotpusa r5, r6, r7 ; lnk r15 }
{ v1ddotpusa r5, r6, r7 ; shrs r15, r16, r17 }
{ v1ddotpusa r5, r6, r7 ; v1maxui r15, r16, 5 }
{ v1ddotpusa r5, r6, r7 ; v2shrsi r15, r16, 5 }
{ v1dotp r5, r6, r7 ; dblalign4 r15, r16, r17 }
{ v1dotp r5, r6, r7 ; ld_add r15, r16, 5 }
{ v1dotp r5, r6, r7 ; prefetch_l2_fault r15 }
{ v1dotp r5, r6, r7 ; subx r15, r16, r17 }
{ v1dotp r5, r6, r7 ; v2cmpltui r15, r16, 5 }
{ v1dotpa r5, r6, r7 ; addxi r15, r16, 5 }
{ v1dotpa r5, r6, r7 ; jalr r15 }
{ v1dotpa r5, r6, r7 ; moveli r15, 0x1234 }
{ v1dotpa r5, r6, r7 ; st r15, r16 }
{ v1dotpa r5, r6, r7 ; v1shli r15, r16, 5 }
{ v1dotpa r5, r6, r7 ; v4addsc r15, r16, r17 }
{ v1dotpu r5, r6, r7 ; fetchadd4 r15, r16, r17 }
{ v1dotpu r5, r6, r7 ; ldnt1u r15, r16 }
{ v1dotpu r5, r6, r7 ; shl r15, r16, r17 }
{ v1dotpu r5, r6, r7 ; v1cmpeqi r15, r16, 5 }
{ v1dotpu r5, r6, r7 ; v2mins r15, r16, r17 }
{ v1dotpua r5, r6, r7 ; cmpeqi r15, r16, 5 }
{ v1dotpua r5, r6, r7 ; ld1s_add r15, r16, 5 }
{ v1dotpua r5, r6, r7 ; ori r15, r16, 5 }
{ v1dotpua r5, r6, r7 ; st4_add r15, r16, 5 }
{ v1dotpua r5, r6, r7 ; v1subuc r15, r16, r17 }
{ v1dotpua r5, r6, r7 ; v4shrs r15, r16, r17 }
{ v1dotpus r5, r6, r7 ; fetchor4 r15, r16, r17 }
{ v1dotpus r5, r6, r7 ; ldnt4s r15, r16 }
{ v1dotpus r5, r6, r7 ; shl3add r15, r16, r17 }
{ v1dotpus r5, r6, r7 ; v1cmpltui r15, r16, 5 }
{ v1dotpus r5, r6, r7 ; v2packuc r15, r16, r17 }
{ v1dotpusa r5, r6, r7 ; cmpltsi r15, r16, 5 }
{ v1dotpusa r5, r6, r7 ; ld2u_add r15, r16, 5 }
{ v1dotpusa r5, r6, r7 ; prefetch_add_l3 r15, 5 }
{ v1dotpusa r5, r6, r7 ; stnt2_add r15, r16, 5 }
{ v1dotpusa r5, r6, r7 ; v2cmples r15, r16, r17 }
{ v1dotpusa r5, r6, r7 ; xori r15, r16, 5 }
{ v1int_h r15, r16, r17 ; fdouble_addsub r5, r6, r7 }
{ v1int_h r15, r16, r17 ; mula_ls_lu r5, r6, r7 }
{ v1int_h r15, r16, r17 ; v1addi r5, r6, 5 }
{ v1int_h r15, r16, r17 ; v1shru r5, r6, r7 }
{ v1int_h r15, r16, r17 ; v2shlsc r5, r6, r7 }
{ v1int_h r5, r6, r7 ; dblalign2 r15, r16, r17 }
{ v1int_h r5, r6, r7 ; ld4u_add r15, r16, 5 }
{ v1int_h r5, r6, r7 ; prefetch_l2 r15 }
{ v1int_h r5, r6, r7 ; sub r15, r16, r17 }
{ v1int_h r5, r6, r7 ; v2cmpltu r15, r16, r17 }
{ v1int_l r15, r16, r17 ; addx r5, r6, r7 }
{ v1int_l r15, r16, r17 ; fdouble_sub_flags r5, r6, r7 }
{ v1int_l r15, r16, r17 ; mz r5, r6, r7 }
{ v1int_l r15, r16, r17 ; v1cmpeq r5, r6, r7 }
{ v1int_l r15, r16, r17 ; v2add r5, r6, r7 }
{ v1int_l r15, r16, r17 ; v2shrui r5, r6, 5 }
{ v1int_l r5, r6, r7 ; exch r15, r16, r17 }
{ v1int_l r5, r6, r7 ; ldnt r15, r16 }
{ v1int_l r5, r6, r7 ; raise }
{ v1int_l r5, r6, r7 ; v1addi r15, r16, 5 }
{ v1int_l r5, r6, r7 ; v2int_l r15, r16, r17 }
{ v1maxu r15, r16, r17 ; and r5, r6, r7 }
{ v1maxu r15, r16, r17 ; fsingle_add1 r5, r6, r7 }
{ v1maxu r15, r16, r17 ; ori r5, r6, 5 }
{ v1maxu r15, r16, r17 ; v1cmplts r5, r6, r7 }
{ v1maxu r15, r16, r17 ; v2avgs r5, r6, r7 }
{ v1maxu r15, r16, r17 ; v4addsc r5, r6, r7 }
{ v1maxu r5, r6, r7 ; fetchaddgez r15, r16, r17 }
{ v1maxu r5, r6, r7 ; ldnt1u_add r15, r16, 5 }
{ v1maxu r5, r6, r7 ; shl16insli r15, r16, 0x1234 }
{ v1maxu r5, r6, r7 ; v1cmples r15, r16, r17 }
{ v1maxu r5, r6, r7 ; v2minsi r15, r16, 5 }
{ v1maxui r15, r16, 5 ; bfins r5, r6, 5, 7 }
{ v1maxui r15, r16, 5 ; fsingle_pack1 r5, r6 }
{ v1maxui r15, r16, 5 ; rotl r5, r6, r7 }
{ v1maxui r15, r16, 5 ; v1cmpne r5, r6, r7 }
{ v1maxui r15, r16, 5 ; v2cmpleu r5, r6, r7 }
{ v1maxui r15, r16, 5 ; v4shl r5, r6, r7 }
{ v1maxui r5, r6, 5 ; fetchor r15, r16, r17 }
{ v1maxui r5, r6, 5 ; ldnt2u_add r15, r16, 5 }
{ v1maxui r5, r6, 5 ; shl2addx r15, r16, r17 }
{ v1maxui r5, r6, 5 ; v1cmpltu r15, r16, r17 }
{ v1maxui r5, r6, 5 ; v2packl r15, r16, r17 }
{ v1minu r15, r16, r17 ; cmpeq r5, r6, r7 }
{ v1minu r15, r16, r17 ; infol 0x1234 }
{ v1minu r15, r16, r17 ; shl1add r5, r6, r7 }
{ v1minu r15, r16, r17 ; v1ddotpusa r5, r6, r7 }
{ v1minu r15, r16, r17 ; v2cmpltui r5, r6, 5 }
{ v1minu r15, r16, r17 ; v4sub r5, r6, r7 }
{ v1minu r5, r6, r7 ; flushwb }
{ v1minu r5, r6, r7 ; ldnt4u_add r15, r16, 5 }
{ v1minu r5, r6, r7 ; shlx r15, r16, r17 }
{ v1minu r5, r6, r7 ; v1int_l r15, r16, r17 }
{ v1minu r5, r6, r7 ; v2shlsc r15, r16, r17 }
{ v1minui r15, r16, 5 ; cmplts r5, r6, r7 }
{ v1minui r15, r16, 5 ; movei r5, 5 }
{ v1minui r15, r16, 5 ; shl3add r5, r6, r7 }
{ v1minui r15, r16, 5 ; v1dotpua r5, r6, r7 }
{ v1minui r15, r16, 5 ; v2int_h r5, r6, r7 }
{ v1minui r5, r6, 5 ; add r15, r16, r17 }
{ v1minui r5, r6, 5 ; info 19 }
{ v1minui r5, r6, 5 ; mfspr r16, 0x5 }
{ v1minui r5, r6, 5 ; shru r15, r16, r17 }
{ v1minui r5, r6, 5 ; v1minui r15, r16, 5 }
{ v1minui r5, r6, 5 ; v2shrui r15, r16, 5 }
{ v1mnz r15, r16, r17 ; cmpne r5, r6, r7 }
{ v1mnz r15, r16, r17 ; mul_hs_ls r5, r6, r7 }
{ v1mnz r15, r16, r17 ; shlxi r5, r6, 5 }
{ v1mnz r15, r16, r17 ; v1int_l r5, r6, r7 }
{ v1mnz r15, r16, r17 ; v2mins r5, r6, r7 }
{ v1mnz r5, r6, r7 ; addxi r15, r16, 5 }
{ v1mnz r5, r6, r7 ; jalr r15 }
{ v1mnz r5, r6, r7 ; moveli r15, 0x1234 }
{ v1mnz r5, r6, r7 ; st r15, r16 }
{ v1mnz r5, r6, r7 ; v1shli r15, r16, 5 }
{ v1mnz r5, r6, r7 ; v4addsc r15, r16, r17 }
{ v1multu r5, r6, r7 ; fetchadd4 r15, r16, r17 }
{ v1multu r5, r6, r7 ; ldnt1u r15, r16 }
{ v1multu r5, r6, r7 ; shl r15, r16, r17 }
{ v1multu r5, r6, r7 ; v1cmpeqi r15, r16, 5 }
{ v1multu r5, r6, r7 ; v2mins r15, r16, r17 }
{ v1mulu r5, r6, r7 ; cmpeqi r15, r16, 5 }
{ v1mulu r5, r6, r7 ; ld1s_add r15, r16, 5 }
{ v1mulu r5, r6, r7 ; ori r15, r16, 5 }
{ v1mulu r5, r6, r7 ; st4_add r15, r16, 5 }
{ v1mulu r5, r6, r7 ; v1subuc r15, r16, r17 }
{ v1mulu r5, r6, r7 ; v4shrs r15, r16, r17 }
{ v1mulus r5, r6, r7 ; fetchor4 r15, r16, r17 }
{ v1mulus r5, r6, r7 ; ldnt4s r15, r16 }
{ v1mulus r5, r6, r7 ; shl3add r15, r16, r17 }
{ v1mulus r5, r6, r7 ; v1cmpltui r15, r16, 5 }
{ v1mulus r5, r6, r7 ; v2packuc r15, r16, r17 }
{ v1mz r15, r16, r17 ; cmpeqi r5, r6, 5 }
{ v1mz r15, r16, r17 ; mm r5, r6, 5, 7 }
{ v1mz r15, r16, r17 ; shl1addx r5, r6, r7 }
{ v1mz r15, r16, r17 ; v1dotp r5, r6, r7 }
{ v1mz r15, r16, r17 ; v2cmpne r5, r6, r7 }
{ v1mz r15, r16, r17 ; v4subsc r5, r6, r7 }
{ v1mz r5, r6, r7 ; fnop }
{ v1mz r5, r6, r7 ; ldnt_add r15, r16, 5 }
{ v1mz r5, r6, r7 ; shlxi r15, r16, 5 }
{ v1mz r5, r6, r7 ; v1maxu r15, r16, r17 }
{ v1mz r5, r6, r7 ; v2shrs r15, r16, r17 }
{ v1sadau r5, r6, r7 ; dblalign2 r15, r16, r17 }
{ v1sadau r5, r6, r7 ; ld4u_add r15, r16, 5 }
{ v1sadau r5, r6, r7 ; prefetch_l2 r15 }
{ v1sadau r5, r6, r7 ; sub r15, r16, r17 }
{ v1sadau r5, r6, r7 ; v2cmpltu r15, r16, r17 }
{ v1sadu r5, r6, r7 ; addx r15, r16, r17 }
{ v1sadu r5, r6, r7 ; iret }
{ v1sadu r5, r6, r7 ; movei r15, 5 }
{ v1sadu r5, r6, r7 ; shruxi r15, r16, 5 }
{ v1sadu r5, r6, r7 ; v1shl r15, r16, r17 }
{ v1sadu r5, r6, r7 ; v4add r15, r16, r17 }
{ v1shl r15, r16, r17 ; cmulaf r5, r6, r7 }
{ v1shl r15, r16, r17 ; mul_hu_ls r5, r6, r7 }
{ v1shl r15, r16, r17 ; shru r5, r6, r7 }
{ v1shl r15, r16, r17 ; v1minu r5, r6, r7 }
{ v1shl r15, r16, r17 ; v2mulfsc r5, r6, r7 }
{ v1shl r5, r6, r7 ; and r15, r16, r17 }
{ v1shl r5, r6, r7 ; jrp r15 }
{ v1shl r5, r6, r7 ; nop }
{ v1shl r5, r6, r7 ; st2 r15, r16 }
{ v1shl r5, r6, r7 ; v1shru r15, r16, r17 }
{ v1shl r5, r6, r7 ; v4packsc r15, r16, r17 }
{ v1shli r15, r16, 5 ; cmulhr r5, r6, r7 }
{ v1shli r15, r16, 5 ; mul_lu_lu r5, r6, r7 }
{ v1shli r15, r16, 5 ; shufflebytes r5, r6, r7 }
{ v1shli r15, r16, 5 ; v1mulu r5, r6, r7 }
{ v1shli r15, r16, 5 ; v2packh r5, r6, r7 }
{ v1shli r5, r6, 5 ; cmpexch r15, r16, r17 }
{ v1shli r5, r6, 5 ; ld1u r15, r16 }
{ v1shli r5, r6, 5 ; prefetch r15 }
{ v1shli r5, r6, 5 ; st_add r15, r16, 5 }
{ v1shli r5, r6, 5 ; v2add r15, r16, r17 }
{ v1shli r5, r6, 5 ; v4shru r15, r16, r17 }
{ v1shrs r15, r16, r17 ; dblalign r5, r6, r7 }
{ v1shrs r15, r16, r17 ; mula_hs_lu r5, r6, r7 }
{ v1shrs r15, r16, r17 ; tblidxb0 r5, r6 }
{ v1shrs r15, r16, r17 ; v1sadu r5, r6, r7 }
{ v1shrs r15, r16, r17 ; v2sadau r5, r6, r7 }
{ v1shrs r5, r6, r7 ; cmplts r15, r16, r17 }
{ v1shrs r5, r6, r7 ; ld2u r15, r16 }
{ v1shrs r5, r6, r7 ; prefetch_add_l2_fault r15, 5 }
{ v1shrs r5, r6, r7 ; stnt2 r15, r16 }
{ v1shrs r5, r6, r7 ; v2cmpeqi r15, r16, 5 }
{ v1shrs r5, r6, r7 ; xor r15, r16, r17 }
{ v1shrsi r15, r16, 5 ; fdouble_add_flags r5, r6, r7 }
{ v1shrsi r15, r16, 5 ; mula_ls_ls r5, r6, r7 }
{ v1shrsi r15, r16, 5 ; v1add r5, r6, r7 }
{ v1shrsi r15, r16, 5 ; v1shrsi r5, r6, 5 }
{ v1shrsi r15, r16, 5 ; v2shli r5, r6, 5 }
{ v1shrsi r5, r6, 5 ; cmpne r15, r16, r17 }
{ v1shrsi r5, r6, 5 ; ld4u r15, r16 }
{ v1shrsi r5, r6, 5 ; prefetch_l1_fault r15 }
{ v1shrsi r5, r6, 5 ; stnt_add r15, r16, 5 }
{ v1shrsi r5, r6, 5 ; v2cmpltsi r15, r16, 5 }
{ v1shru r15, r16, r17 ; addli r5, r6, 0x1234 }
{ v1shru r15, r16, r17 ; fdouble_pack2 r5, r6, r7 }
{ v1shru r15, r16, r17 ; mulx r5, r6, r7 }
{ v1shru r15, r16, r17 ; v1avgu r5, r6, r7 }
{ v1shru r15, r16, r17 ; v1subuc r5, r6, r7 }
{ v1shru r15, r16, r17 ; v2shru r5, r6, r7 }
{ v1shru r5, r6, r7 ; dtlbpr r15 }
{ v1shru r5, r6, r7 ; ldna_add r15, r16, 5 }
{ v1shru r5, r6, r7 ; prefetch_l3_fault r15 }
{ v1shru r5, r6, r7 ; v1add r15, r16, r17 }
{ v1shru r5, r6, r7 ; v2int_h r15, r16, r17 }
{ v1shrui r15, r16, 5 ; addxsc r5, r6, r7 }
{ v1shrui r15, r16, 5 ; fnop }
{ v1shrui r15, r16, 5 ; or r5, r6, r7 }
{ v1shrui r15, r16, 5 ; v1cmpleu r5, r6, r7 }
{ v1shrui r15, r16, 5 ; v2adiffs r5, r6, r7 }
{ v1shrui r15, r16, 5 ; v4add r5, r6, r7 }
{ v1shrui r5, r6, 5 ; fetchadd4 r15, r16, r17 }
{ v1shrui r5, r6, 5 ; ldnt1u r15, r16 }
{ v1shrui r5, r6, 5 ; shl r15, r16, r17 }
{ v1shrui r5, r6, 5 ; v1cmpeqi r15, r16, 5 }
{ v1shrui r5, r6, 5 ; v2mins r15, r16, r17 }
{ v1sub r15, r16, r17 ; bfextu r5, r6, 5, 7 }
{ v1sub r15, r16, r17 ; fsingle_mul2 r5, r6, r7 }
{ v1sub r15, r16, r17 ; revbytes r5, r6 }
{ v1sub r15, r16, r17 ; v1cmpltui r5, r6, 5 }
{ v1sub r15, r16, r17 ; v2cmples r5, r6, r7 }
{ v1sub r15, r16, r17 ; v4packsc r5, r6, r7 }
{ v1sub r5, r6, r7 ; fetchand4 r15, r16, r17 }
{ v1sub r5, r6, r7 ; ldnt2u r15, r16 }
{ v1sub r5, r6, r7 ; shl2add r15, r16, r17 }
{ v1sub r5, r6, r7 ; v1cmpltsi r15, r16, 5 }
{ v1sub r5, r6, r7 ; v2packh r15, r16, r17 }
{ v1subuc r15, r16, r17 ; cmovnez r5, r6, r7 }
{ v1subuc r15, r16, r17 ; info 19 }
{ v1subuc r15, r16, r17 ; shl16insli r5, r6, 0x1234 }
{ v1subuc r15, r16, r17 ; v1ddotpus r5, r6, r7 }
{ v1subuc r15, r16, r17 ; v2cmpltu r5, r6, r7 }
{ v1subuc r15, r16, r17 ; v4shru r5, r6, r7 }
{ v1subuc r5, r6, r7 ; flush r15 }
{ v1subuc r5, r6, r7 ; ldnt4u r15, r16 }
{ v1subuc r5, r6, r7 ; shli r15, r16, 5 }
{ v1subuc r5, r6, r7 ; v1int_h r15, r16, r17 }
{ v1subuc r5, r6, r7 ; v2shli r15, r16, 5 }
{ v2add r15, r16, r17 ; cmpleu r5, r6, r7 }
{ v2add r15, r16, r17 ; move r5, r6 }
{ v2add r15, r16, r17 ; shl2addx r5, r6, r7 }
{ v2add r15, r16, r17 ; v1dotpu r5, r6, r7 }
{ v2add r15, r16, r17 ; v2dotpa r5, r6, r7 }
{ v2add r15, r16, r17 ; xori r5, r6, 5 }
{ v2add r5, r6, r7 ; ill }
{ v2add r5, r6, r7 ; mf }
{ v2add r5, r6, r7 ; shrsi r15, r16, 5 }
{ v2add r5, r6, r7 ; v1minu r15, r16, r17 }
{ v2add r5, r6, r7 ; v2shru r15, r16, r17 }
{ v2addi r15, r16, 5 ; cmpltui r5, r6, 5 }
{ v2addi r15, r16, 5 ; mul_hs_hu r5, r6, r7 }
{ v2addi r15, r16, 5 ; shlx r5, r6, r7 }
{ v2addi r15, r16, 5 ; v1int_h r5, r6, r7 }
{ v2addi r15, r16, 5 ; v2maxsi r5, r6, 5 }
{ v2addi r5, r6, 5 ; addx r15, r16, r17 }
{ v2addi r5, r6, 5 ; iret }
{ v2addi r5, r6, 5 ; movei r15, 5 }
{ v2addi r5, r6, 5 ; shruxi r15, r16, 5 }
{ v2addi r5, r6, 5 ; v1shl r15, r16, r17 }
{ v2addi r5, r6, 5 ; v4add r15, r16, r17 }
{ v2addsc r15, r16, r17 ; cmulaf r5, r6, r7 }
{ v2addsc r15, r16, r17 ; mul_hu_ls r5, r6, r7 }
{ v2addsc r15, r16, r17 ; shru r5, r6, r7 }
{ v2addsc r15, r16, r17 ; v1minu r5, r6, r7 }
{ v2addsc r15, r16, r17 ; v2mulfsc r5, r6, r7 }
{ v2addsc r5, r6, r7 ; and r15, r16, r17 }
{ v2addsc r5, r6, r7 ; jrp r15 }
{ v2addsc r5, r6, r7 ; nop }
{ v2addsc r5, r6, r7 ; st2 r15, r16 }
{ v2addsc r5, r6, r7 ; v1shru r15, r16, r17 }
{ v2addsc r5, r6, r7 ; v4packsc r15, r16, r17 }
{ v2adiffs r5, r6, r7 ; fetchand r15, r16, r17 }
{ v2adiffs r5, r6, r7 ; ldnt2s_add r15, r16, 5 }
{ v2adiffs r5, r6, r7 ; shl1addx r15, r16, r17 }
{ v2adiffs r5, r6, r7 ; v1cmplts r15, r16, r17 }
{ v2adiffs r5, r6, r7 ; v2mz r15, r16, r17 }
{ v2avgs r5, r6, r7 ; cmples r15, r16, r17 }
{ v2avgs r5, r6, r7 ; ld2s r15, r16 }
{ v2avgs r5, r6, r7 ; prefetch_add_l1_fault r15, 5 }
{ v2avgs r5, r6, r7 ; stnt1 r15, r16 }
{ v2avgs r5, r6, r7 ; v2addsc r15, r16, r17 }
{ v2avgs r5, r6, r7 ; v4subsc r15, r16, r17 }
{ v2cmpeq r15, r16, r17 ; dblalign4 r5, r6, r7 }
{ v2cmpeq r15, r16, r17 ; mula_hu_ls r5, r6, r7 }
{ v2cmpeq r15, r16, r17 ; tblidxb2 r5, r6 }
{ v2cmpeq r15, r16, r17 ; v1shli r5, r6, 5 }
{ v2cmpeq r15, r16, r17 ; v2sadu r5, r6, r7 }
{ v2cmpeq r5, r6, r7 ; cmpltu r15, r16, r17 }
{ v2cmpeq r5, r6, r7 ; ld4s r15, r16 }
{ v2cmpeq r5, r6, r7 ; prefetch_add_l3_fault r15, 5 }
{ v2cmpeq r5, r6, r7 ; stnt4 r15, r16 }
{ v2cmpeq r5, r6, r7 ; v2cmpleu r15, r16, r17 }
{ v2cmpeqi r15, r16, 5 ; add r5, r6, r7 }
{ v2cmpeqi r15, r16, 5 ; fdouble_mul_flags r5, r6, r7 }
{ v2cmpeqi r15, r16, 5 ; mula_lu_lu r5, r6, r7 }
{ v2cmpeqi r15, r16, 5 ; v1adduc r5, r6, r7 }
{ v2cmpeqi r15, r16, 5 ; v1shrui r5, r6, 5 }
{ v2cmpeqi r15, r16, 5 ; v2shrs r5, r6, r7 }
{ v2cmpeqi r5, r6, 5 ; dblalign4 r15, r16, r17 }
{ v2cmpeqi r5, r6, 5 ; ld_add r15, r16, 5 }
{ v2cmpeqi r5, r6, 5 ; prefetch_l2_fault r15 }
{ v2cmpeqi r5, r6, 5 ; subx r15, r16, r17 }
{ v2cmpeqi r5, r6, 5 ; v2cmpltui r15, r16, 5 }
{ v2cmples r15, r16, r17 ; addxi r5, r6, 5 }
{ v2cmples r15, r16, r17 ; fdouble_unpack_max r5, r6, r7 }
{ v2cmples r15, r16, r17 ; nop }
{ v2cmples r15, r16, r17 ; v1cmpeqi r5, r6, 5 }
{ v2cmples r15, r16, r17 ; v2addi r5, r6, 5 }
{ v2cmples r15, r16, r17 ; v2sub r5, r6, r7 }
{ v2cmples r5, r6, r7 ; exch4 r15, r16, r17 }
{ v2cmples r5, r6, r7 ; ldnt1s r15, r16 }
{ v2cmples r5, r6, r7 ; rotl r15, r16, r17 }
{ v2cmples r5, r6, r7 ; v1adduc r15, r16, r17 }
{ v2cmples r5, r6, r7 ; v2maxs r15, r16, r17 }
{ v2cmpleu r15, r16, r17 ; andi r5, r6, 5 }
{ v2cmpleu r15, r16, r17 ; fsingle_addsub2 r5, r6, r7 }
{ v2cmpleu r15, r16, r17 ; pcnt r5, r6 }
{ v2cmpleu r15, r16, r17 ; v1cmpltsi r5, r6, 5 }
{ v2cmpleu r15, r16, r17 ; v2cmpeq r5, r6, r7 }
{ v2cmpleu r15, r16, r17 ; v4int_h r5, r6, r7 }
{ v2cmpleu r5, r6, r7 ; fetchaddgez4 r15, r16, r17 }
{ v2cmpleu r5, r6, r7 ; ldnt2s r15, r16 }
{ v2cmpleu r5, r6, r7 ; shl1add r15, r16, r17 }
{ v2cmpleu r5, r6, r7 ; v1cmpleu r15, r16, r17 }
{ v2cmpleu r5, r6, r7 ; v2mnz r15, r16, r17 }
{ v2cmplts r15, r16, r17 ; clz r5, r6 }
{ v2cmplts r15, r16, r17 ; fsingle_pack2 r5, r6, r7 }
{ v2cmplts r15, r16, r17 ; rotli r5, r6, 5 }
{ v2cmplts r15, r16, r17 ; v1ddotpu r5, r6, r7 }
{ v2cmplts r15, r16, r17 ; v2cmplts r5, r6, r7 }
{ v2cmplts r15, r16, r17 ; v4shlsc r5, r6, r7 }
{ v2cmplts r5, r6, r7 ; fetchor4 r15, r16, r17 }
{ v2cmplts r5, r6, r7 ; ldnt4s r15, r16 }
{ v2cmplts r5, r6, r7 ; shl3add r15, r16, r17 }
{ v2cmplts r5, r6, r7 ; v1cmpltui r15, r16, 5 }
{ v2cmplts r5, r6, r7 ; v2packuc r15, r16, r17 }
{ v2cmpltsi r15, r16, 5 ; cmpeqi r5, r6, 5 }
{ v2cmpltsi r15, r16, 5 ; mm r5, r6, 5, 7 }
{ v2cmpltsi r15, r16, 5 ; shl1addx r5, r6, r7 }
{ v2cmpltsi r15, r16, 5 ; v1dotp r5, r6, r7 }
{ v2cmpltsi r15, r16, 5 ; v2cmpne r5, r6, r7 }
{ v2cmpltsi r15, r16, 5 ; v4subsc r5, r6, r7 }
{ v2cmpltsi r5, r6, 5 ; fnop }
{ v2cmpltsi r5, r6, 5 ; ldnt_add r15, r16, 5 }
{ v2cmpltsi r5, r6, 5 ; shlxi r15, r16, 5 }
{ v2cmpltsi r5, r6, 5 ; v1maxu r15, r16, r17 }
{ v2cmpltsi r5, r6, 5 ; v2shrs r15, r16, r17 }
{ v2cmpltu r15, r16, r17 ; cmpltsi r5, r6, 5 }
{ v2cmpltu r15, r16, r17 ; moveli r5, 0x1234 }
{ v2cmpltu r15, r16, r17 ; shl3addx r5, r6, r7 }
{ v2cmpltu r15, r16, r17 ; v1dotpus r5, r6, r7 }
{ v2cmpltu r15, r16, r17 ; v2int_l r5, r6, r7 }
{ v2cmpltu r5, r6, r7 ; addi r15, r16, 5 }
{ v2cmpltu r5, r6, r7 ; infol 0x1234 }
{ v2cmpltu r5, r6, r7 ; mnz r15, r16, r17 }
{ v2cmpltu r5, r6, r7 ; shrui r15, r16, 5 }
{ v2cmpltu r5, r6, r7 ; v1mnz r15, r16, r17 }
{ v2cmpltu r5, r6, r7 ; v2sub r15, r16, r17 }
{ v2cmpltui r15, r16, 5 ; cmul r5, r6, r7 }
{ v2cmpltui r15, r16, 5 ; mul_hs_lu r5, r6, r7 }
{ v2cmpltui r15, r16, 5 ; shrs r5, r6, r7 }
{ v2cmpltui r15, r16, 5 ; v1maxu r5, r6, r7 }
{ v2cmpltui r15, r16, 5 ; v2minsi r5, r6, 5 }
{ v2cmpltui r5, r6, 5 ; addxli r15, r16, 0x1234 }
{ v2cmpltui r5, r6, 5 ; jalrp r15 }
{ v2cmpltui r5, r6, 5 ; mtspr 0x5, r16 }
{ v2cmpltui r5, r6, 5 ; st1 r15, r16 }
{ v2cmpltui r5, r6, 5 ; v1shrs r15, r16, r17 }
{ v2cmpltui r5, r6, 5 ; v4int_h r15, r16, r17 }
{ v2cmpne r15, r16, r17 ; cmulfr r5, r6, r7 }
{ v2cmpne r15, r16, r17 ; mul_ls_ls r5, r6, r7 }
{ v2cmpne r15, r16, r17 ; shrux r5, r6, r7 }
{ v2cmpne r15, r16, r17 ; v1mnz r5, r6, r7 }
{ v2cmpne r15, r16, r17 ; v2mults r5, r6, r7 }
{ v2cmpne r5, r6, r7 ; cmpeq r15, r16, r17 }
{ v2cmpne r5, r6, r7 ; ld1s r15, r16 }
{ v2cmpne r5, r6, r7 ; or r15, r16, r17 }
{ v2cmpne r5, r6, r7 ; st4 r15, r16 }
{ v2cmpne r5, r6, r7 ; v1sub r15, r16, r17 }
{ v2cmpne r5, r6, r7 ; v4shlsc r15, r16, r17 }
{ v2dotp r5, r6, r7 ; fetchor r15, r16, r17 }
{ v2dotp r5, r6, r7 ; ldnt2u_add r15, r16, 5 }
{ v2dotp r5, r6, r7 ; shl2addx r15, r16, r17 }
{ v2dotp r5, r6, r7 ; v1cmpltu r15, r16, r17 }
{ v2dotp r5, r6, r7 ; v2packl r15, r16, r17 }
{ v2dotpa r5, r6, r7 ; cmplts r15, r16, r17 }
{ v2dotpa r5, r6, r7 ; ld2u r15, r16 }
{ v2dotpa r5, r6, r7 ; prefetch_add_l2_fault r15, 5 }
{ v2dotpa r5, r6, r7 ; stnt2 r15, r16 }
{ v2dotpa r5, r6, r7 ; v2cmpeqi r15, r16, 5 }
{ v2dotpa r5, r6, r7 ; xor r15, r16, r17 }
{ v2int_h r15, r16, r17 ; fdouble_add_flags r5, r6, r7 }
{ v2int_h r15, r16, r17 ; mula_ls_ls r5, r6, r7 }
{ v2int_h r15, r16, r17 ; v1add r5, r6, r7 }
{ v2int_h r15, r16, r17 ; v1shrsi r5, r6, 5 }
{ v2int_h r15, r16, r17 ; v2shli r5, r6, 5 }
{ v2int_h r5, r6, r7 ; cmpne r15, r16, r17 }
{ v2int_h r5, r6, r7 ; ld4u r15, r16 }
{ v2int_h r5, r6, r7 ; prefetch_l1_fault r15 }
{ v2int_h r5, r6, r7 ; stnt_add r15, r16, 5 }
{ v2int_h r5, r6, r7 ; v2cmpltsi r15, r16, 5 }
{ v2int_l r15, r16, r17 ; addli r5, r6, 0x1234 }
{ v2int_l r15, r16, r17 ; fdouble_pack2 r5, r6, r7 }
{ v2int_l r15, r16, r17 ; mulx r5, r6, r7 }
{ v2int_l r15, r16, r17 ; v1avgu r5, r6, r7 }
{ v2int_l r15, r16, r17 ; v1subuc r5, r6, r7 }
{ v2int_l r15, r16, r17 ; v2shru r5, r6, r7 }
{ v2int_l r5, r6, r7 ; dtlbpr r15 }
{ v2int_l r5, r6, r7 ; ldna_add r15, r16, 5 }
{ v2int_l r5, r6, r7 ; prefetch_l3_fault r15 }
{ v2int_l r5, r6, r7 ; v1add r15, r16, r17 }
{ v2int_l r5, r6, r7 ; v2int_h r15, r16, r17 }
{ v2maxs r15, r16, r17 ; addxsc r5, r6, r7 }
{ v2maxs r15, r16, r17 ; fnop }
{ v2maxs r15, r16, r17 ; or r5, r6, r7 }
{ v2maxs r15, r16, r17 ; v1cmpleu r5, r6, r7 }
{ v2maxs r15, r16, r17 ; v2adiffs r5, r6, r7 }
{ v2maxs r15, r16, r17 ; v4add r5, r6, r7 }
{ v2maxs r5, r6, r7 ; fetchadd4 r15, r16, r17 }
{ v2maxs r5, r6, r7 ; ldnt1u r15, r16 }
{ v2maxs r5, r6, r7 ; shl r15, r16, r17 }
{ v2maxs r5, r6, r7 ; v1cmpeqi r15, r16, 5 }
{ v2maxs r5, r6, r7 ; v2mins r15, r16, r17 }
{ v2maxsi r15, r16, 5 ; bfextu r5, r6, 5, 7 }
{ v2maxsi r15, r16, 5 ; fsingle_mul2 r5, r6, r7 }
{ v2maxsi r15, r16, 5 ; revbytes r5, r6 }
{ v2maxsi r15, r16, 5 ; v1cmpltui r5, r6, 5 }
{ v2maxsi r15, r16, 5 ; v2cmples r5, r6, r7 }
{ v2maxsi r15, r16, 5 ; v4packsc r5, r6, r7 }
{ v2maxsi r5, r6, 5 ; fetchand4 r15, r16, r17 }
{ v2maxsi r5, r6, 5 ; ldnt2u r15, r16 }
{ v2maxsi r5, r6, 5 ; shl2add r15, r16, r17 }
{ v2maxsi r5, r6, 5 ; v1cmpltsi r15, r16, 5 }
{ v2maxsi r5, r6, 5 ; v2packh r15, r16, r17 }
{ v2mins r15, r16, r17 ; cmovnez r5, r6, r7 }
{ v2mins r15, r16, r17 ; info 19 }
{ v2mins r15, r16, r17 ; shl16insli r5, r6, 0x1234 }
{ v2mins r15, r16, r17 ; v1ddotpus r5, r6, r7 }
{ v2mins r15, r16, r17 ; v2cmpltu r5, r6, r7 }
{ v2mins r15, r16, r17 ; v4shru r5, r6, r7 }
{ v2mins r5, r6, r7 ; flush r15 }
{ v2mins r5, r6, r7 ; ldnt4u r15, r16 }
{ v2mins r5, r6, r7 ; shli r15, r16, 5 }
{ v2mins r5, r6, r7 ; v1int_h r15, r16, r17 }
{ v2mins r5, r6, r7 ; v2shli r15, r16, 5 }
{ v2minsi r15, r16, 5 ; cmpleu r5, r6, r7 }
{ v2minsi r15, r16, 5 ; move r5, r6 }
{ v2minsi r15, r16, 5 ; shl2addx r5, r6, r7 }
{ v2minsi r15, r16, 5 ; v1dotpu r5, r6, r7 }
{ v2minsi r15, r16, 5 ; v2dotpa r5, r6, r7 }
{ v2minsi r15, r16, 5 ; xori r5, r6, 5 }
{ v2minsi r5, r6, 5 ; ill }
{ v2minsi r5, r6, 5 ; mf }
{ v2minsi r5, r6, 5 ; shrsi r15, r16, 5 }
{ v2minsi r5, r6, 5 ; v1minu r15, r16, r17 }
{ v2minsi r5, r6, 5 ; v2shru r15, r16, r17 }
{ v2mnz r15, r16, r17 ; cmpltui r5, r6, 5 }
{ v2mnz r15, r16, r17 ; mul_hs_hu r5, r6, r7 }
{ v2mnz r15, r16, r17 ; shlx r5, r6, r7 }
{ v2mnz r15, r16, r17 ; v1int_h r5, r6, r7 }
{ v2mnz r15, r16, r17 ; v2maxsi r5, r6, 5 }
{ v2mnz r5, r6, r7 ; addx r15, r16, r17 }
{ v2mnz r5, r6, r7 ; iret }
{ v2mnz r5, r6, r7 ; movei r15, 5 }
{ v2mnz r5, r6, r7 ; shruxi r15, r16, 5 }
{ v2mnz r5, r6, r7 ; v1shl r15, r16, r17 }
{ v2mnz r5, r6, r7 ; v4add r15, r16, r17 }
{ v2mulfsc r5, r6, r7 ; fetchadd r15, r16, r17 }
{ v2mulfsc r5, r6, r7 ; ldnt1s_add r15, r16, 5 }
{ v2mulfsc r5, r6, r7 ; rotli r15, r16, 5 }
{ v2mulfsc r5, r6, r7 ; v1cmpeq r15, r16, r17 }
{ v2mulfsc r5, r6, r7 ; v2maxsi r15, r16, 5 }
{ v2muls r5, r6, r7 ; cmpeq r15, r16, r17 }
{ v2muls r5, r6, r7 ; ld1s r15, r16 }
{ v2muls r5, r6, r7 ; or r15, r16, r17 }
{ v2muls r5, r6, r7 ; st4 r15, r16 }
{ v2muls r5, r6, r7 ; v1sub r15, r16, r17 }
{ v2muls r5, r6, r7 ; v4shlsc r15, r16, r17 }
{ v2mults r5, r6, r7 ; fetchor r15, r16, r17 }
{ v2mults r5, r6, r7 ; ldnt2u_add r15, r16, 5 }
{ v2mults r5, r6, r7 ; shl2addx r15, r16, r17 }
{ v2mults r5, r6, r7 ; v1cmpltu r15, r16, r17 }
{ v2mults r5, r6, r7 ; v2packl r15, r16, r17 }
{ v2mz r15, r16, r17 ; cmpeq r5, r6, r7 }
{ v2mz r15, r16, r17 ; infol 0x1234 }
{ v2mz r15, r16, r17 ; shl1add r5, r6, r7 }
{ v2mz r15, r16, r17 ; v1ddotpusa r5, r6, r7 }
{ v2mz r15, r16, r17 ; v2cmpltui r5, r6, 5 }
{ v2mz r15, r16, r17 ; v4sub r5, r6, r7 }
{ v2mz r5, r6, r7 ; flushwb }
{ v2mz r5, r6, r7 ; ldnt4u_add r15, r16, 5 }
{ v2mz r5, r6, r7 ; shlx r15, r16, r17 }
{ v2mz r5, r6, r7 ; v1int_l r15, r16, r17 }
{ v2mz r5, r6, r7 ; v2shlsc r15, r16, r17 }
{ v2packh r15, r16, r17 ; cmplts r5, r6, r7 }
{ v2packh r15, r16, r17 ; movei r5, 5 }
{ v2packh r15, r16, r17 ; shl3add r5, r6, r7 }
{ v2packh r15, r16, r17 ; v1dotpua r5, r6, r7 }
{ v2packh r15, r16, r17 ; v2int_h r5, r6, r7 }
{ v2packh r5, r6, r7 ; add r15, r16, r17 }
{ v2packh r5, r6, r7 ; info 19 }
{ v2packh r5, r6, r7 ; mfspr r16, 0x5 }
{ v2packh r5, r6, r7 ; shru r15, r16, r17 }
{ v2packh r5, r6, r7 ; v1minui r15, r16, 5 }
{ v2packh r5, r6, r7 ; v2shrui r15, r16, 5 }
{ v2packl r15, r16, r17 ; cmpne r5, r6, r7 }
{ v2packl r15, r16, r17 ; mul_hs_ls r5, r6, r7 }
{ v2packl r15, r16, r17 ; shlxi r5, r6, 5 }
{ v2packl r15, r16, r17 ; v1int_l r5, r6, r7 }
{ v2packl r15, r16, r17 ; v2mins r5, r6, r7 }
{ v2packl r5, r6, r7 ; addxi r15, r16, 5 }
{ v2packl r5, r6, r7 ; jalr r15 }
{ v2packl r5, r6, r7 ; moveli r15, 0x1234 }
{ v2packl r5, r6, r7 ; st r15, r16 }
{ v2packl r5, r6, r7 ; v1shli r15, r16, 5 }
{ v2packl r5, r6, r7 ; v4addsc r15, r16, r17 }
{ v2packuc r15, r16, r17 ; cmulf r5, r6, r7 }
{ v2packuc r15, r16, r17 ; mul_hu_lu r5, r6, r7 }
{ v2packuc r15, r16, r17 ; shrui r5, r6, 5 }
{ v2packuc r15, r16, r17 ; v1minui r5, r6, 5 }
{ v2packuc r15, r16, r17 ; v2muls r5, r6, r7 }
{ v2packuc r5, r6, r7 ; andi r15, r16, 5 }
{ v2packuc r5, r6, r7 ; ld r15, r16 }
{ v2packuc r5, r6, r7 ; nor r15, r16, r17 }
{ v2packuc r5, r6, r7 ; st2_add r15, r16, 5 }
{ v2packuc r5, r6, r7 ; v1shrui r15, r16, 5 }
{ v2packuc r5, r6, r7 ; v4shl r15, r16, r17 }
{ v2sadas r5, r6, r7 ; fetchand4 r15, r16, r17 }
{ v2sadas r5, r6, r7 ; ldnt2u r15, r16 }
{ v2sadas r5, r6, r7 ; shl2add r15, r16, r17 }
{ v2sadas r5, r6, r7 ; v1cmpltsi r15, r16, 5 }
{ v2sadas r5, r6, r7 ; v2packh r15, r16, r17 }
{ v2sadau r5, r6, r7 ; cmpleu r15, r16, r17 }
{ v2sadau r5, r6, r7 ; ld2s_add r15, r16, 5 }
{ v2sadau r5, r6, r7 ; prefetch_add_l2 r15, 5 }
{ v2sadau r5, r6, r7 ; stnt1_add r15, r16, 5 }
{ v2sadau r5, r6, r7 ; v2cmpeq r15, r16, r17 }
{ v2sadau r5, r6, r7 ; wh64 r15 }
{ v2sads r5, r6, r7 ; fnop }
{ v2sads r5, r6, r7 ; ldnt_add r15, r16, 5 }
{ v2sads r5, r6, r7 ; shlxi r15, r16, 5 }
{ v2sads r5, r6, r7 ; v1maxu r15, r16, r17 }
{ v2sads r5, r6, r7 ; v2shrs r15, r16, r17 }
{ v2sadu r5, r6, r7 ; dblalign2 r15, r16, r17 }
{ v2sadu r5, r6, r7 ; ld4u_add r15, r16, 5 }
{ v2sadu r5, r6, r7 ; prefetch_l2 r15 }
{ v2sadu r5, r6, r7 ; sub r15, r16, r17 }
{ v2sadu r5, r6, r7 ; v2cmpltu r15, r16, r17 }
{ v2shl r15, r16, r17 ; addx r5, r6, r7 }
{ v2shl r15, r16, r17 ; fdouble_sub_flags r5, r6, r7 }
{ v2shl r15, r16, r17 ; mz r5, r6, r7 }
{ v2shl r15, r16, r17 ; v1cmpeq r5, r6, r7 }
{ v2shl r15, r16, r17 ; v2add r5, r6, r7 }
{ v2shl r15, r16, r17 ; v2shrui r5, r6, 5 }
{ v2shl r5, r6, r7 ; exch r15, r16, r17 }
{ v2shl r5, r6, r7 ; ldnt r15, r16 }
{ v2shl r5, r6, r7 ; raise }
{ v2shl r5, r6, r7 ; v1addi r15, r16, 5 }
{ v2shl r5, r6, r7 ; v2int_l r15, r16, r17 }
{ v2shli r15, r16, 5 ; and r5, r6, r7 }
{ v2shli r15, r16, 5 ; fsingle_add1 r5, r6, r7 }
{ v2shli r15, r16, 5 ; ori r5, r6, 5 }
{ v2shli r15, r16, 5 ; v1cmplts r5, r6, r7 }
{ v2shli r15, r16, 5 ; v2avgs r5, r6, r7 }
{ v2shli r15, r16, 5 ; v4addsc r5, r6, r7 }
{ v2shli r5, r6, 5 ; fetchaddgez r15, r16, r17 }
{ v2shli r5, r6, 5 ; ldnt1u_add r15, r16, 5 }
{ v2shli r5, r6, 5 ; shl16insli r15, r16, 0x1234 }
{ v2shli r5, r6, 5 ; v1cmples r15, r16, r17 }
{ v2shli r5, r6, 5 ; v2minsi r15, r16, 5 }
{ v2shlsc r15, r16, r17 ; bfins r5, r6, 5, 7 }
{ v2shlsc r15, r16, r17 ; fsingle_pack1 r5, r6 }
{ v2shlsc r15, r16, r17 ; rotl r5, r6, r7 }
{ v2shlsc r15, r16, r17 ; v1cmpne r5, r6, r7 }
{ v2shlsc r15, r16, r17 ; v2cmpleu r5, r6, r7 }
{ v2shlsc r15, r16, r17 ; v4shl r5, r6, r7 }
{ v2shlsc r5, r6, r7 ; fetchor r15, r16, r17 }
{ v2shlsc r5, r6, r7 ; ldnt2u_add r15, r16, 5 }
{ v2shlsc r5, r6, r7 ; shl2addx r15, r16, r17 }
{ v2shlsc r5, r6, r7 ; v1cmpltu r15, r16, r17 }
{ v2shlsc r5, r6, r7 ; v2packl r15, r16, r17 }
{ v2shrs r15, r16, r17 ; cmpeq r5, r6, r7 }
{ v2shrs r15, r16, r17 ; infol 0x1234 }
{ v2shrs r15, r16, r17 ; shl1add r5, r6, r7 }
{ v2shrs r15, r16, r17 ; v1ddotpusa r5, r6, r7 }
{ v2shrs r15, r16, r17 ; v2cmpltui r5, r6, 5 }
{ v2shrs r15, r16, r17 ; v4sub r5, r6, r7 }
{ v2shrs r5, r6, r7 ; flushwb }
{ v2shrs r5, r6, r7 ; ldnt4u_add r15, r16, 5 }
{ v2shrs r5, r6, r7 ; shlx r15, r16, r17 }
{ v2shrs r5, r6, r7 ; v1int_l r15, r16, r17 }
{ v2shrs r5, r6, r7 ; v2shlsc r15, r16, r17 }
{ v2shrsi r15, r16, 5 ; cmplts r5, r6, r7 }
{ v2shrsi r15, r16, 5 ; movei r5, 5 }
{ v2shrsi r15, r16, 5 ; shl3add r5, r6, r7 }
{ v2shrsi r15, r16, 5 ; v1dotpua r5, r6, r7 }
{ v2shrsi r15, r16, 5 ; v2int_h r5, r6, r7 }
{ v2shrsi r5, r6, 5 ; add r15, r16, r17 }
{ v2shrsi r5, r6, 5 ; info 19 }
{ v2shrsi r5, r6, 5 ; mfspr r16, 0x5 }
{ v2shrsi r5, r6, 5 ; shru r15, r16, r17 }
{ v2shrsi r5, r6, 5 ; v1minui r15, r16, 5 }
{ v2shrsi r5, r6, 5 ; v2shrui r15, r16, 5 }
{ v2shru r15, r16, r17 ; cmpne r5, r6, r7 }
{ v2shru r15, r16, r17 ; mul_hs_ls r5, r6, r7 }
{ v2shru r15, r16, r17 ; shlxi r5, r6, 5 }
{ v2shru r15, r16, r17 ; v1int_l r5, r6, r7 }
{ v2shru r15, r16, r17 ; v2mins r5, r6, r7 }
{ v2shru r5, r6, r7 ; addxi r15, r16, 5 }
{ v2shru r5, r6, r7 ; jalr r15 }
{ v2shru r5, r6, r7 ; moveli r15, 0x1234 }
{ v2shru r5, r6, r7 ; st r15, r16 }
{ v2shru r5, r6, r7 ; v1shli r15, r16, 5 }
{ v2shru r5, r6, r7 ; v4addsc r15, r16, r17 }
{ v2shrui r15, r16, 5 ; cmulf r5, r6, r7 }
{ v2shrui r15, r16, 5 ; mul_hu_lu r5, r6, r7 }
{ v2shrui r15, r16, 5 ; shrui r5, r6, 5 }
{ v2shrui r15, r16, 5 ; v1minui r5, r6, 5 }
{ v2shrui r15, r16, 5 ; v2muls r5, r6, r7 }
{ v2shrui r5, r6, 5 ; andi r15, r16, 5 }
{ v2shrui r5, r6, 5 ; ld r15, r16 }
{ v2shrui r5, r6, 5 ; nor r15, r16, r17 }
{ v2shrui r5, r6, 5 ; st2_add r15, r16, 5 }
{ v2shrui r5, r6, 5 ; v1shrui r15, r16, 5 }
{ v2shrui r5, r6, 5 ; v4shl r15, r16, r17 }
{ v2sub r15, r16, r17 ; crc32_32 r5, r6, r7 }
{ v2sub r15, r16, r17 ; mula_hs_hs r5, r6, r7 }
{ v2sub r15, r16, r17 ; sub r5, r6, r7 }
{ v2sub r15, r16, r17 ; v1mulus r5, r6, r7 }
{ v2sub r15, r16, r17 ; v2packl r5, r6, r7 }
{ v2sub r5, r6, r7 ; cmpexch4 r15, r16, r17 }
{ v2sub r5, r6, r7 ; ld1u_add r15, r16, 5 }
{ v2sub r5, r6, r7 ; prefetch_add_l1 r15, 5 }
{ v2sub r5, r6, r7 ; stnt r15, r16 }
{ v2sub r5, r6, r7 ; v2addi r15, r16, 5 }
{ v2sub r5, r6, r7 ; v4sub r15, r16, r17 }
{ v2subsc r15, r16, r17 ; dblalign2 r5, r6, r7 }
{ v2subsc r15, r16, r17 ; mula_hu_hu r5, r6, r7 }
{ v2subsc r15, r16, r17 ; tblidxb1 r5, r6 }
{ v2subsc r15, r16, r17 ; v1shl r5, r6, r7 }
{ v2subsc r15, r16, r17 ; v2sads r5, r6, r7 }
{ v2subsc r5, r6, r7 ; cmpltsi r15, r16, 5 }
{ v2subsc r5, r6, r7 ; ld2u_add r15, r16, 5 }
{ v2subsc r5, r6, r7 ; prefetch_add_l3 r15, 5 }
{ v2subsc r5, r6, r7 ; stnt2_add r15, r16, 5 }
{ v2subsc r5, r6, r7 ; v2cmples r15, r16, r17 }
{ v2subsc r5, r6, r7 ; xori r15, r16, 5 }
{ v4add r15, r16, r17 ; fdouble_addsub r5, r6, r7 }
{ v4add r15, r16, r17 ; mula_ls_lu r5, r6, r7 }
{ v4add r15, r16, r17 ; v1addi r5, r6, 5 }
{ v4add r15, r16, r17 ; v1shru r5, r6, r7 }
{ v4add r15, r16, r17 ; v2shlsc r5, r6, r7 }
{ v4add r5, r6, r7 ; dblalign2 r15, r16, r17 }
{ v4add r5, r6, r7 ; ld4u_add r15, r16, 5 }
{ v4add r5, r6, r7 ; prefetch_l2 r15 }
{ v4add r5, r6, r7 ; sub r15, r16, r17 }
{ v4add r5, r6, r7 ; v2cmpltu r15, r16, r17 }
{ v4addsc r15, r16, r17 ; addx r5, r6, r7 }
{ v4addsc r15, r16, r17 ; fdouble_sub_flags r5, r6, r7 }
{ v4addsc r15, r16, r17 ; mz r5, r6, r7 }
{ v4addsc r15, r16, r17 ; v1cmpeq r5, r6, r7 }
{ v4addsc r15, r16, r17 ; v2add r5, r6, r7 }
{ v4addsc r15, r16, r17 ; v2shrui r5, r6, 5 }
{ v4addsc r5, r6, r7 ; exch r15, r16, r17 }
{ v4addsc r5, r6, r7 ; ldnt r15, r16 }
{ v4addsc r5, r6, r7 ; raise }
{ v4addsc r5, r6, r7 ; v1addi r15, r16, 5 }
{ v4addsc r5, r6, r7 ; v2int_l r15, r16, r17 }
{ v4int_h r15, r16, r17 ; and r5, r6, r7 }
{ v4int_h r15, r16, r17 ; fsingle_add1 r5, r6, r7 }
{ v4int_h r15, r16, r17 ; ori r5, r6, 5 }
{ v4int_h r15, r16, r17 ; v1cmplts r5, r6, r7 }
{ v4int_h r15, r16, r17 ; v2avgs r5, r6, r7 }
{ v4int_h r15, r16, r17 ; v4addsc r5, r6, r7 }
{ v4int_h r5, r6, r7 ; fetchaddgez r15, r16, r17 }
{ v4int_h r5, r6, r7 ; ldnt1u_add r15, r16, 5 }
{ v4int_h r5, r6, r7 ; shl16insli r15, r16, 0x1234 }
{ v4int_h r5, r6, r7 ; v1cmples r15, r16, r17 }
{ v4int_h r5, r6, r7 ; v2minsi r15, r16, 5 }
{ v4int_l r15, r16, r17 ; bfins r5, r6, 5, 7 }
{ v4int_l r15, r16, r17 ; fsingle_pack1 r5, r6 }
{ v4int_l r15, r16, r17 ; rotl r5, r6, r7 }
{ v4int_l r15, r16, r17 ; v1cmpne r5, r6, r7 }
{ v4int_l r15, r16, r17 ; v2cmpleu r5, r6, r7 }
{ v4int_l r15, r16, r17 ; v4shl r5, r6, r7 }
{ v4int_l r5, r6, r7 ; fetchor r15, r16, r17 }
{ v4int_l r5, r6, r7 ; ldnt2u_add r15, r16, 5 }
{ v4int_l r5, r6, r7 ; shl2addx r15, r16, r17 }
{ v4int_l r5, r6, r7 ; v1cmpltu r15, r16, r17 }
{ v4int_l r5, r6, r7 ; v2packl r15, r16, r17 }
{ v4packsc r15, r16, r17 ; cmpeq r5, r6, r7 }
{ v4packsc r15, r16, r17 ; infol 0x1234 }
{ v4packsc r15, r16, r17 ; shl1add r5, r6, r7 }
{ v4packsc r15, r16, r17 ; v1ddotpusa r5, r6, r7 }
{ v4packsc r15, r16, r17 ; v2cmpltui r5, r6, 5 }
{ v4packsc r15, r16, r17 ; v4sub r5, r6, r7 }
{ v4packsc r5, r6, r7 ; flushwb }
{ v4packsc r5, r6, r7 ; ldnt4u_add r15, r16, 5 }
{ v4packsc r5, r6, r7 ; shlx r15, r16, r17 }
{ v4packsc r5, r6, r7 ; v1int_l r15, r16, r17 }
{ v4packsc r5, r6, r7 ; v2shlsc r15, r16, r17 }
{ v4shl r15, r16, r17 ; cmplts r5, r6, r7 }
{ v4shl r15, r16, r17 ; movei r5, 5 }
{ v4shl r15, r16, r17 ; shl3add r5, r6, r7 }
{ v4shl r15, r16, r17 ; v1dotpua r5, r6, r7 }
{ v4shl r15, r16, r17 ; v2int_h r5, r6, r7 }
{ v4shl r5, r6, r7 ; add r15, r16, r17 }
{ v4shl r5, r6, r7 ; info 19 }
{ v4shl r5, r6, r7 ; mfspr r16, 0x5 }
{ v4shl r5, r6, r7 ; shru r15, r16, r17 }
{ v4shl r5, r6, r7 ; v1minui r15, r16, 5 }
{ v4shl r5, r6, r7 ; v2shrui r15, r16, 5 }
{ v4shlsc r15, r16, r17 ; cmpne r5, r6, r7 }
{ v4shlsc r15, r16, r17 ; mul_hs_ls r5, r6, r7 }
{ v4shlsc r15, r16, r17 ; shlxi r5, r6, 5 }
{ v4shlsc r15, r16, r17 ; v1int_l r5, r6, r7 }
{ v4shlsc r15, r16, r17 ; v2mins r5, r6, r7 }
{ v4shlsc r5, r6, r7 ; addxi r15, r16, 5 }
{ v4shlsc r5, r6, r7 ; jalr r15 }
{ v4shlsc r5, r6, r7 ; moveli r15, 0x1234 }
{ v4shlsc r5, r6, r7 ; st r15, r16 }
{ v4shlsc r5, r6, r7 ; v1shli r15, r16, 5 }
{ v4shlsc r5, r6, r7 ; v4addsc r15, r16, r17 }
{ v4shrs r15, r16, r17 ; cmulf r5, r6, r7 }
{ v4shrs r15, r16, r17 ; mul_hu_lu r5, r6, r7 }
{ v4shrs r15, r16, r17 ; shrui r5, r6, 5 }
{ v4shrs r15, r16, r17 ; v1minui r5, r6, 5 }
{ v4shrs r15, r16, r17 ; v2muls r5, r6, r7 }
{ v4shrs r5, r6, r7 ; andi r15, r16, 5 }
{ v4shrs r5, r6, r7 ; ld r15, r16 }
{ v4shrs r5, r6, r7 ; nor r15, r16, r17 }
{ v4shrs r5, r6, r7 ; st2_add r15, r16, 5 }
{ v4shrs r5, r6, r7 ; v1shrui r15, r16, 5 }
{ v4shrs r5, r6, r7 ; v4shl r15, r16, r17 }
{ v4shru r15, r16, r17 ; crc32_32 r5, r6, r7 }
{ v4shru r15, r16, r17 ; mula_hs_hs r5, r6, r7 }
{ v4shru r15, r16, r17 ; sub r5, r6, r7 }
{ v4shru r15, r16, r17 ; v1mulus r5, r6, r7 }
{ v4shru r15, r16, r17 ; v2packl r5, r6, r7 }
{ v4shru r5, r6, r7 ; cmpexch4 r15, r16, r17 }
{ v4shru r5, r6, r7 ; ld1u_add r15, r16, 5 }
{ v4shru r5, r6, r7 ; prefetch_add_l1 r15, 5 }
{ v4shru r5, r6, r7 ; stnt r15, r16 }
{ v4shru r5, r6, r7 ; v2addi r15, r16, 5 }
{ v4shru r5, r6, r7 ; v4sub r15, r16, r17 }
{ v4sub r15, r16, r17 ; dblalign2 r5, r6, r7 }
{ v4sub r15, r16, r17 ; mula_hu_hu r5, r6, r7 }
{ v4sub r15, r16, r17 ; tblidxb1 r5, r6 }
{ v4sub r15, r16, r17 ; v1shl r5, r6, r7 }
{ v4sub r15, r16, r17 ; v2sads r5, r6, r7 }
{ v4sub r5, r6, r7 ; cmpltsi r15, r16, 5 }
{ v4sub r5, r6, r7 ; ld2u_add r15, r16, 5 }
{ v4sub r5, r6, r7 ; prefetch_add_l3 r15, 5 }
{ v4sub r5, r6, r7 ; stnt2_add r15, r16, 5 }
{ v4sub r5, r6, r7 ; v2cmples r15, r16, r17 }
{ v4sub r5, r6, r7 ; xori r15, r16, 5 }
{ v4subsc r15, r16, r17 ; fdouble_addsub r5, r6, r7 }
{ v4subsc r15, r16, r17 ; mula_ls_lu r5, r6, r7 }
{ v4subsc r15, r16, r17 ; v1addi r5, r6, 5 }
{ v4subsc r15, r16, r17 ; v1shru r5, r6, r7 }
{ v4subsc r15, r16, r17 ; v2shlsc r5, r6, r7 }
{ v4subsc r5, r6, r7 ; dblalign2 r15, r16, r17 }
{ v4subsc r5, r6, r7 ; ld4u_add r15, r16, 5 }
{ v4subsc r5, r6, r7 ; prefetch_l2 r15 }
{ v4subsc r5, r6, r7 ; sub r15, r16, r17 }
{ v4subsc r5, r6, r7 ; v2cmpltu r15, r16, r17 }
{ wh64 r15 ; addx r5, r6, r7 }
{ wh64 r15 ; fdouble_sub_flags r5, r6, r7 }
{ wh64 r15 ; mz r5, r6, r7 }
{ wh64 r15 ; v1cmpeq r5, r6, r7 }
{ wh64 r15 ; v2add r5, r6, r7 }
{ wh64 r15 ; v2shrui r5, r6, 5 }
{ xor r15, r16, r17 ; addi r5, r6, 5 ; ld4s r25, r26 }
{ xor r15, r16, r17 ; addxi r5, r6, 5 ; ld4u r25, r26 }
{ xor r15, r16, r17 ; andi r5, r6, 5 ; ld4u r25, r26 }
{ xor r15, r16, r17 ; cmoveqz r5, r6, r7 ; ld4s r25, r26 }
{ xor r15, r16, r17 ; cmpeq r5, r6, r7 ; prefetch r25 }
{ xor r15, r16, r17 ; cmples r5, r6, r7 ; prefetch_l1_fault r25 }
{ xor r15, r16, r17 ; cmplts r5, r6, r7 ; prefetch_l2_fault r25 }
{ xor r15, r16, r17 ; cmpltu r5, r6, r7 ; prefetch_l3_fault r25 }
{ xor r15, r16, r17 ; ctz r5, r6 ; ld4s r25, r26 }
{ xor r15, r16, r17 ; fnop ; st r25, r26 }
{ xor r15, r16, r17 ; info 19 ; prefetch_l2 r25 }
{ xor r15, r16, r17 ; ld r25, r26 ; mula_ls_ls r5, r6, r7 }
{ xor r15, r16, r17 ; ld1s r25, r26 ; cmoveqz r5, r6, r7 }
{ xor r15, r16, r17 ; ld1s r25, r26 ; shl2addx r5, r6, r7 }
{ xor r15, r16, r17 ; ld1u r25, r26 ; mul_hs_hs r5, r6, r7 }
{ xor r15, r16, r17 ; ld2s r25, r26 ; addi r5, r6, 5 }
{ xor r15, r16, r17 ; ld2s r25, r26 ; rotl r5, r6, r7 }
{ xor r15, r16, r17 ; ld2u r25, r26 ; fnop }
{ xor r15, r16, r17 ; ld2u r25, r26 ; tblidxb1 r5, r6 }
{ xor r15, r16, r17 ; ld4s r25, r26 ; nop }
{ xor r15, r16, r17 ; ld4u r25, r26 ; cmpleu r5, r6, r7 }
{ xor r15, r16, r17 ; ld4u r25, r26 ; shrsi r5, r6, 5 }
{ xor r15, r16, r17 ; move r5, r6 ; prefetch_l1_fault r25 }
{ xor r15, r16, r17 ; mul_hs_hs r5, r6, r7 ; prefetch_l2 r25 }
{ xor r15, r16, r17 ; mul_ls_ls r5, r6, r7 ; prefetch r25 }
{ xor r15, r16, r17 ; mula_hs_hs r5, r6, r7 ; prefetch_l1 r25 }
{ xor r15, r16, r17 ; mula_ls_ls r5, r6, r7 ; ld4s r25, r26 }
{ xor r15, r16, r17 ; mulax r5, r6, r7 ; ld4u r25, r26 }
{ xor r15, r16, r17 ; mz r5, r6, r7 ; prefetch_l1 r25 }
{ xor r15, r16, r17 ; nor r5, r6, r7 ; prefetch_l2 r25 }
{ xor r15, r16, r17 ; pcnt r5, r6 ; prefetch_l2_fault r25 }
{ xor r15, r16, r17 ; prefetch r25 ; mulax r5, r6, r7 }
{ xor r15, r16, r17 ; prefetch_l1 r25 ; cmpeq r5, r6, r7 }
{ xor r15, r16, r17 ; prefetch_l1 r25 ; shl3addx r5, r6, r7 }
{ xor r15, r16, r17 ; prefetch_l1_fault r25 ; mul_ls_ls r5, r6, r7 }
{ xor r15, r16, r17 ; prefetch_l2 r25 ; addxi r5, r6, 5 }
{ xor r15, r16, r17 ; prefetch_l2 r25 ; shl r5, r6, r7 }
{ xor r15, r16, r17 ; prefetch_l2_fault r25 ; info 19 }
{ xor r15, r16, r17 ; prefetch_l2_fault r25 ; tblidxb3 r5, r6 }
{ xor r15, r16, r17 ; prefetch_l3 r25 ; or r5, r6, r7 }
{ xor r15, r16, r17 ; prefetch_l3_fault r25 ; cmpltsi r5, r6, 5 }
{ xor r15, r16, r17 ; prefetch_l3_fault r25 ; shrui r5, r6, 5 }
{ xor r15, r16, r17 ; revbytes r5, r6 ; prefetch_l3 r25 }
{ xor r15, r16, r17 ; rotli r5, r6, 5 ; st r25, r26 }
{ xor r15, r16, r17 ; shl1add r5, r6, r7 ; st1 r25, r26 }
{ xor r15, r16, r17 ; shl2add r5, r6, r7 ; st4 r25, r26 }
{ xor r15, r16, r17 ; shl3addx r5, r6, r7 ; ld r25, r26 }
{ xor r15, r16, r17 ; shrs r5, r6, r7 ; ld r25, r26 }
{ xor r15, r16, r17 ; shru r5, r6, r7 ; ld1u r25, r26 }
{ xor r15, r16, r17 ; st r25, r26 ; addi r5, r6, 5 }
{ xor r15, r16, r17 ; st r25, r26 ; rotl r5, r6, r7 }
{ xor r15, r16, r17 ; st1 r25, r26 ; fnop }
{ xor r15, r16, r17 ; st1 r25, r26 ; tblidxb1 r5, r6 }
{ xor r15, r16, r17 ; st2 r25, r26 ; nop }
{ xor r15, r16, r17 ; st4 r25, r26 ; cmpleu r5, r6, r7 }
{ xor r15, r16, r17 ; st4 r25, r26 ; shrsi r5, r6, 5 }
{ xor r15, r16, r17 ; subx r5, r6, r7 ; prefetch_l2 r25 }
{ xor r15, r16, r17 ; tblidxb1 r5, r6 ; prefetch_l2_fault r25 }
{ xor r15, r16, r17 ; tblidxb3 r5, r6 ; prefetch_l3_fault r25 }
{ xor r15, r16, r17 ; v1mz r5, r6, r7 }
{ xor r15, r16, r17 ; v2packuc r5, r6, r7 }
{ xor r15, r16, r17 ; xor r5, r6, r7 ; st1 r25, r26 }
{ xor r5, r6, r7 ; addi r15, r16, 5 ; st2 r25, r26 }
{ xor r5, r6, r7 ; addxi r15, r16, 5 ; st4 r25, r26 }
{ xor r5, r6, r7 ; andi r15, r16, 5 ; st4 r25, r26 }
{ xor r5, r6, r7 ; cmpexch r15, r16, r17 }
{ xor r5, r6, r7 ; cmplts r15, r16, r17 ; ld r25, r26 }
{ xor r5, r6, r7 ; cmpltu r15, r16, r17 ; ld1u r25, r26 }
{ xor r5, r6, r7 ; dtlbpr r15 }
{ xor r5, r6, r7 ; ill ; ld4u r25, r26 }
{ xor r5, r6, r7 ; jalr r15 ; ld4s r25, r26 }
{ xor r5, r6, r7 ; jr r15 ; prefetch r25 }
{ xor r5, r6, r7 ; ld r25, r26 ; cmples r15, r16, r17 }
{ xor r5, r6, r7 ; ld1s r25, r26 ; add r15, r16, r17 }
{ xor r5, r6, r7 ; ld1s r25, r26 ; shrsi r15, r16, 5 }
{ xor r5, r6, r7 ; ld1u r25, r26 ; shl r15, r16, r17 }
{ xor r5, r6, r7 ; ld2s r25, r26 ; mnz r15, r16, r17 }
{ xor r5, r6, r7 ; ld2u r25, r26 ; cmpne r15, r16, r17 }
{ xor r5, r6, r7 ; ld4s r25, r26 ; and r15, r16, r17 }
{ xor r5, r6, r7 ; ld4s r25, r26 ; subx r15, r16, r17 }
{ xor r5, r6, r7 ; ld4u r25, r26 ; shl2addx r15, r16, r17 }
{ xor r5, r6, r7 ; lnk r15 ; prefetch_l2 r25 }
{ xor r5, r6, r7 ; move r15, r16 ; prefetch_l2 r25 }
{ xor r5, r6, r7 ; mz r15, r16, r17 ; prefetch_l2 r25 }
{ xor r5, r6, r7 ; nor r15, r16, r17 ; prefetch_l3 r25 }
{ xor r5, r6, r7 ; prefetch r25 ; cmpltu r15, r16, r17 }
{ xor r5, r6, r7 ; prefetch_add_l3_fault r15, 5 }
{ xor r5, r6, r7 ; prefetch_l1 r25 ; shli r15, r16, 5 }
{ xor r5, r6, r7 ; prefetch_l1_fault r25 ; rotli r15, r16, 5 }
{ xor r5, r6, r7 ; prefetch_l2 r25 ; mnz r15, r16, r17 }
{ xor r5, r6, r7 ; prefetch_l2_fault r25 ; fnop }
{ xor r5, r6, r7 ; prefetch_l3 r25 ; cmpeq r15, r16, r17 }
{ xor r5, r6, r7 ; prefetch_l3 r25 }
{ xor r5, r6, r7 ; prefetch_l3_fault r25 ; shli r15, r16, 5 }
{ xor r5, r6, r7 ; rotli r15, r16, 5 ; prefetch_l2_fault r25 }
{ xor r5, r6, r7 ; shl1add r15, r16, r17 ; prefetch_l3 r25 }
{ xor r5, r6, r7 ; shl2add r15, r16, r17 ; st r25, r26 }
{ xor r5, r6, r7 ; shl3add r15, r16, r17 ; st2 r25, r26 }
{ xor r5, r6, r7 ; shli r15, r16, 5 }
{ xor r5, r6, r7 ; shrsi r15, r16, 5 }
{ xor r5, r6, r7 ; shruxi r15, r16, 5 }
{ xor r5, r6, r7 ; st r25, r26 ; shli r15, r16, 5 }
{ xor r5, r6, r7 ; st1 r25, r26 ; rotli r15, r16, 5 }
{ xor r5, r6, r7 ; st2 r25, r26 ; lnk r15 }
{ xor r5, r6, r7 ; st4 r25, r26 ; cmpltu r15, r16, r17 }
{ xor r5, r6, r7 ; stnt2 r15, r16 }
{ xor r5, r6, r7 ; subx r15, r16, r17 ; st2 r25, r26 }
{ xor r5, r6, r7 ; v2cmpltsi r15, r16, 5 }
{ xor r5, r6, r7 ; xor r15, r16, r17 ; ld2u r25, r26 }
{ xori r15, r16, 5 ; cmul r5, r6, r7 }
{ xori r15, r16, 5 ; mul_hs_lu r5, r6, r7 }
{ xori r15, r16, 5 ; shrs r5, r6, r7 }
{ xori r15, r16, 5 ; v1maxu r5, r6, r7 }
{ xori r15, r16, 5 ; v2minsi r5, r6, 5 }
{ xori r5, r6, 5 ; addxli r15, r16, 0x1234 }
{ xori r5, r6, 5 ; jalrp r15 }
{ xori r5, r6, 5 ; mtspr 0x5, r16 }
{ xori r5, r6, 5 ; st1 r15, r16 }
{ xori r5, r6, 5 ; v1shrs r15, r16, r17 }
{ xori r5, r6, 5 ; v4int_h r15, r16, r17 }
|
tactcomplabs/xbgas-binutils-gdb
| 1,449
|
gas/testsuite/gas/or1k/reloc-1.s
|
l.movhi r3,hi(x)
l.ori r3,r4,hi(x)
l.addi r3,r4,hi(x)
l.lwz r3,hi(x)(r4)
l.movhi r3,lo(x)
l.ori r3,r4,lo(x)
l.addi r3,r4,lo(x)
l.lwz r3,lo(x)(r4)
l.lws r3,lo(x)(r4)
l.lhz r3,lo(x)(r4)
l.lhs r3,lo(x)(r4)
l.lbz r3,lo(x)(r4)
l.lbs r3,lo(x)(r4)
l.lwa r3,lo(x)(r4)
l.sw lo(x)(r4),r3
l.sh lo(x)(r4),r3
l.sb lo(x)(r4),r3
l.swa lo(x)(r4),r3
l.movhi r3,ha(x)
l.ori r3,r4,ha(x)
l.addi r3,r4,ha(x)
l.ori r3,r0,got(x)
l.addi r3,r4,got(x)
l.lwz r3,got(x)(r4)
l.movhi r3,gotpchi(_GLOBAL_OFFSET_TABLE_-4)
l.ori r3,r3,gotpclo(_GLOBAL_OFFSET_TABLE_-8)
l.movhi r3,gotoffhi(x)
l.ori r3,r3,gotofflo(x)
l.movhi r3,gotoffha(x)
l.lwz r3,gotofflo(x)(r3)
l.sw gotofflo(x)(r3),r3
l.movhi r3,tlsgdhi(x)
l.ori r3,r3,tlsgdlo(x)
l.movhi r3,tlsldmhi(x)
l.ori r3,r3,tlsldmlo(x)
l.movhi r3,dtpoffhi(x)
l.ori r3,r3,dtpofflo(x)
l.movhi r3,gottpoffhi(x)
l.ori r3,r3,gottpofflo(x)
l.movhi r3,gottpoffha(x)
l.lwz r3,gottpofflo(x)(r3)
l.movhi r3,tpoffhi(x)
l.ori r3,r3,tpofflo(x)
l.movhi r3,tpoffha(x)
l.lwz r3,tpofflo(x)(r3)
l.sw tpofflo(x)(r3),r3
l.j plta(x)
l.jal plta(x)
l.bf plta(x)
l.bnf plta(x)
l.adrp r3,got(x)
l.adrp r3,tlsgd(x)
l.adrp r3,tlsldm(x)
l.adrp r3,gottp(x)
l.ori r4,r3,po(x)
l.ori r4,r3,gotpo(x)
l.ori r4,r3,tlsgdpo(x)
l.ori r4,r3,tlsldmpo(x)
l.ori r4,r3,gottppo(x)
l.lbz r5,po(x)(r3)
l.lbz r5,gotpo(x)(r3)
l.sb po(x)(r3),r6
l.movhi r4,gotha(x)
l.ori r3,r4,gotha(x)
l.addi r3,r4,gotha(x)
|
tactcomplabs/xbgas-binutils-gdb
| 10,694
|
gas/testsuite/gas/or1k/allinsn.s
|
.data
localdata:
.word 42
.text
localtext:
l.nop
.data
.global globaldata
globaldata:
.word 43
.text
.global globaltext
globaltext:
l.nop
l_j:
l.j -4
l.j 4
l.j 0
l.j localtext
l.j localdata
l.j globaltext
l.j globaldata
l.j l_j
l.j l_jal
.text
l_jal:
l.jal -4
l.jal 4
l.jal 0
l.jal localtext
l.jal localdata
l.jal globaltext
l.jal globaldata
l.jal l_j
l.jal l_jal
.text
l_jr:
l.jr r0
l.jr r31
l.jr r16
l.jr r15
l.jr r1
l.jr r27
l.jr r14
l.jr r22
.text
l_jalr:
l.jalr r0
l.jalr r31
l.jalr r16
l.jalr r15
l.jalr r1
l.jalr r27
l.jalr r14
l.jalr r22
.text
l_bnf:
l.bnf -4
l.bnf 4
l.bnf 0
l.bnf localtext
l.bnf localdata
l.bnf globaltext
l.bnf globaldata
l.bnf l_j
l.bnf l_jal
.text
l_bf:
l.bf -4
l.bf 4
l.bf 0
l.bf localtext
l.bf localdata
l.bf globaltext
l.bf globaldata
l.bf l_j
l.bf l_jal
.text
l_trap:
l.trap 0
l.trap 65535
l.trap 32768
l.trap 32767
l.trap 1
l.trap 53583
l.trap 32636
l.trap 53834
.text
l_sys:
l.sys 0
l.sys 65535
l.sys 32768
l.sys 32767
l.sys 1
l.sys 53893
l.sys 58133
l.sys 33018
.text
l_rfe:
l.rfe
.text
l_nop:
l.nop
.text
l_movhi:
l.movhi r0,0
l.movhi r31,-1
l.movhi r16,-32768
l.movhi r15,32767
l.movhi r1,1
l.movhi r28,-32306
l.movhi r23,-5972
l.movhi r19,-10048
.text
l_mfspr:
l.mfspr r0,r0,0
l.mfspr r31,r31,65535
l.mfspr r16,r16,32768
l.mfspr r15,r15,32767
l.mfspr r1,r1,1
l.mfspr r23,r29,54424
l.mfspr r19,r20,4481
l.mfspr r26,r2,63446
.text
l_mtspr:
l.mtspr r0,r0,0
l.mtspr r31,r31,-1
l.mtspr r16,r16,-32768
l.mtspr r15,r15,32767
l.mtspr r1,r1,1
l.mtspr r30,r6,15223
l.mtspr r9,r7,-21300
l.mtspr r25,r7,-645
.text
l_lwz:
l.lwz r0,0(r0)
l.lwz r31,-1(r31)
l.lwz r16,-32768(r16)
l.lwz r15,32767(r15)
l.lwz r1,1(r1)
l.lwz r15,2933(r25)
l.lwz r17,-799(r21)
l.lwz r0,-17595(r18)
.text
l_lws:
l.lws r0,0(r0)
l.lws r31,-1(r31)
l.lws r16,-32768(r16)
l.lws r15,32767(r15)
l.lws r1,1(r1)
l.lws r1,-17606(r21)
l.lws r14,26891(r31)
l.lws r8,27552(r0)
.text
l_lbz:
l.lbz r0,0(r0)
l.lbz r31,-1(r31)
l.lbz r16,-32768(r16)
l.lbz r15,32767(r15)
l.lbz r1,1(r1)
l.lbz r19,25635(r20)
l.lbz r15,-3416(r9)
l.lbz r3,17748(r1)
.text
l_lbs:
l.lbs r0,0(r0)
l.lbs r31,-1(r31)
l.lbs r16,-32768(r16)
l.lbs r15,32767(r15)
l.lbs r1,1(r1)
l.lbs r26,17606(r8)
l.lbs r22,-31072(r16)
l.lbs r6,17440(r9)
.text
l_lhz:
l.lhz r0,0(r0)
l.lhz r31,-1(r31)
l.lhz r16,-32768(r16)
l.lhz r15,32767(r15)
l.lhz r1,1(r1)
l.lhz r5,-5667(r4)
l.lhz r24,5848(r4)
l.lhz r10,31675(r7)
.text
l_lhs:
l.lhs r0,0(r0)
l.lhs r31,-1(r31)
l.lhs r16,-32768(r16)
l.lhs r15,32767(r15)
l.lhs r1,1(r1)
l.lhs r6,-142(r11)
l.lhs r20,-5306(r29)
l.lhs r15,4178(r21)
.text
l_sw:
l.sw 0(r0),r0
l.sw -1(r31),r31
l.sw -32768(r16),r16
l.sw 32767(r15),r15
l.sw 1(r1),r1
l.sw -7967(r17),r10
l.sw 1824(r30),r10
l.sw 31566(r15),r4
.text
l_sb:
l.sb 0(r0),r0
l.sb -1(r31),r31
l.sb -32768(r16),r16
l.sb 32767(r15),r15
l.sb 1(r1),r1
l.sb 22200(r10),r0
l.sb 9995(r16),r27
l.sb -28260(r14),r31
.text
l_sh:
l.sh 0(r0),r0
l.sh -1(r31),r31
l.sh -32768(r16),r16
l.sh 32767(r15),r15
l.sh 1(r1),r1
l.sh 10685(r21),r25
l.sh -13066(r28),r5
l.sh -26800(r9),r29
.text
l_sll:
l.sll r0,r0,r0
l.sll r31,r31,r31
l.sll r16,r16,r16
l.sll r15,r15,r15
l.sll r1,r1,r1
l.sll r31,r16,r8
l.sll r31,r17,r22
l.sll r15,r14,r5
.text
l_slli:
l.slli r0,r0,0
l.slli r31,r31,63
l.slli r16,r16,32
l.slli r15,r15,31
l.slli r1,r1,1
l.slli r11,r14,49
l.slli r7,r27,23
l.slli r30,r16,11
.text
l_srl:
l.srl r0,r0,r0
l.srl r31,r31,r31
l.srl r16,r16,r16
l.srl r15,r15,r15
l.srl r1,r1,r1
l.srl r15,r25,r13
l.srl r19,r0,r17
l.srl r13,r0,r23
.text
l_srli:
l.srli r0,r0,0
l.srli r31,r31,63
l.srli r16,r16,32
l.srli r15,r15,31
l.srli r1,r1,1
l.srli r15,r30,13
l.srli r13,r3,63
l.srli r2,r18,30
.text
l_sra:
l.sra r0,r0,r0
l.sra r31,r31,r31
l.sra r16,r16,r16
l.sra r15,r15,r15
l.sra r1,r1,r1
l.sra r3,r26,r0
l.sra r29,r18,r27
l.sra r27,r29,r3
.text
l_srai:
l.srai r0,r0,0
l.srai r31,r31,63
l.srai r16,r16,32
l.srai r15,r15,31
l.srai r1,r1,1
l.srai r10,r11,28
l.srai r23,r15,48
l.srai r16,r15,38
.text
l_ror:
l.ror r0,r0,r0
l.ror r31,r31,r31
l.ror r16,r16,r16
l.ror r15,r15,r15
l.ror r1,r1,r1
l.ror r29,r12,r5
l.ror r18,r6,r4
l.ror r2,r16,r17
.text
l_rori:
l.rori r0,r0,0
l.rori r31,r31,63
l.rori r16,r16,32
l.rori r15,r15,31
l.rori r1,r1,1
l.rori r17,r0,23
l.rori r16,r31,42
l.rori r13,r21,12
.text
l_add:
l.add r0,r0,r0
l.add r31,r31,r31
l.add r16,r16,r16
l.add r15,r15,r15
l.add r1,r1,r1
l.add r29,r7,r4
l.add r29,r10,r18
l.add r18,r22,r23
.text
l_sub:
l.sub r0,r0,r0
l.sub r31,r31,r31
l.sub r16,r16,r16
l.sub r15,r15,r15
l.sub r1,r1,r1
l.sub r23,r26,r14
l.sub r10,r24,r15
l.sub r11,r4,r18
.text
l_and:
l.and r0,r0,r0
l.and r31,r31,r31
l.and r16,r16,r16
l.and r15,r15,r15
l.and r1,r1,r1
l.and r0,r31,r25
l.and r30,r7,r19
l.and r19,r2,r26
.text
l_or:
l.or r0,r0,r0
l.or r31,r31,r31
l.or r16,r16,r16
l.or r15,r15,r15
l.or r1,r1,r1
l.or r17,r10,r2
l.or r7,r19,r29
l.or r3,r17,r17
.text
l_xor:
l.xor r0,r0,r0
l.xor r31,r31,r31
l.xor r16,r16,r16
l.xor r15,r15,r15
l.xor r1,r1,r1
l.xor r31,r5,r17
l.xor r22,r4,r5
l.xor r30,r20,r26
.text
l_addc:
l.addc r0,r0,r0
l.addc r31,r31,r31
l.addc r16,r16,r16
l.addc r15,r15,r15
l.addc r1,r1,r1
l.addc r8,r26,r24
l.addc r18,r6,r4
l.addc r29,r0,r18
.text
l_mul:
l.mul r0,r0,r0
l.mul r31,r31,r31
l.mul r16,r16,r16
l.mul r15,r15,r15
l.mul r1,r1,r1
l.mul r8,r25,r13
l.mul r8,r21,r29
l.mul r27,r3,r17
.text
l_mulu:
l.mulu r0,r0,r0
l.mulu r31,r31,r31
l.mulu r16,r16,r16
l.mulu r15,r15,r15
l.mulu r1,r1,r1
l.mulu r26,r14,r16
l.mulu r1,r18,r11
l.mulu r14,r18,r17
.text
l_div:
l.div r0,r0,r0
l.div r31,r31,r31
l.div r16,r16,r16
l.div r15,r15,r15
l.div r1,r1,r1
l.div r0,r2,r28
l.div r26,r7,r31
l.div r2,r18,r20
.text
l_divu:
l.divu r0,r0,r0
l.divu r31,r31,r31
l.divu r16,r16,r16
l.divu r15,r15,r15
l.divu r1,r1,r1
l.divu r5,r4,r25
l.divu r8,r11,r29
l.divu r11,r19,r2
.text
l_addi:
l.addi r0,r0,0
l.addi r31,r31,-1
l.addi r16,r16,-32768
l.addi r15,r15,32767
l.addi r1,r1,1
l.addi r14,r0,7020
l.addi r13,r14,14131
l.addi r14,r16,-26821
.text
l_andi:
l.andi r0,r0,0
l.andi r31,r31,-1
l.andi r16,r16,-32768
l.andi r15,r15,32767
l.andi r1,r1,1
l.andi r27,r21,11927
l.andi r21,r23,12059
l.andi r30,r30,-31804
.text
l_ori:
l.ori r0,r0,0
l.ori r31,r31,-1
l.ori r16,r16,-32768
l.ori r15,r15,32767
l.ori r1,r1,1
l.ori r22,r27,-10111
l.ori r17,r31,128
l.ori r13,r20,-12435
.text
l_xori:
l.xori r0,r0,0
l.xori r31,r31,-1
l.xori r16,r16,-32768
l.xori r15,r15,32767
l.xori r1,r1,1
l.xori r18,r16,65535
l.xori r25,r13,-16331
l.xori r12,r29,-32727
.text
l_muli:
l.muli r0,r0,0
l.muli r31,r31,-1
l.muli r16,r16,-32768
l.muli r15,r15,32767
l.muli r1,r1,1
l.muli r27,r7,-4731
l.muli r7,r20,65535
l.muli r24,r21,23219
.text
l_addic:
l.addic r0,r0,0
l.addic r31,r31,-1
l.addic r16,r16,-32768
l.addic r15,r15,32767
l.addic r1,r1,1
l.addic r6,r22,-32700
l.addic r19,r9,65535
l.addic r27,r28,6891
.text
l_sfgtu:
l.sfgtu r0,r0
l.sfgtu r31,r31
l.sfgtu r16,r16
l.sfgtu r15,r15
l.sfgtu r1,r1
l.sfgtu r8,r4
l.sfgtu r17,r21
l.sfgtu r6,r5
.text
l_sfgeu:
l.sfgeu r0,r0
l.sfgeu r31,r31
l.sfgeu r16,r16
l.sfgeu r15,r15
l.sfgeu r1,r1
l.sfgeu r14,r12
l.sfgeu r22,r7
l.sfgeu r13,r1
.text
l_sfltu:
l.sfltu r0,r0
l.sfltu r31,r31
l.sfltu r16,r16
l.sfltu r15,r15
l.sfltu r1,r1
l.sfltu r1,r13
l.sfltu r22,r30
l.sfltu r20,r6
.text
l_sfleu:
l.sfleu r0,r0
l.sfleu r31,r31
l.sfleu r16,r16
l.sfleu r15,r15
l.sfleu r1,r1
l.sfleu r19,r8
l.sfleu r27,r15
l.sfleu r27,r3
.text
l_sfgts:
l.sfgts r0,r0
l.sfgts r31,r31
l.sfgts r16,r16
l.sfgts r15,r15
l.sfgts r1,r1
l.sfgts r5,r5
l.sfgts r31,r5
l.sfgts r30,r18
.text
l_sfges:
l.sfges r0,r0
l.sfges r31,r31
l.sfges r16,r16
l.sfges r15,r15
l.sfges r1,r1
l.sfges r17,r18
l.sfges r0,r9
l.sfges r22,r25
.text
l_sflts:
l.sflts r0,r0
l.sflts r31,r31
l.sflts r16,r16
l.sflts r15,r15
l.sflts r1,r1
l.sflts r25,r24
l.sflts r23,r13
l.sflts r15,r8
.text
l_sfles:
l.sfles r0,r0
l.sfles r31,r31
l.sfles r16,r16
l.sfles r15,r15
l.sfles r1,r1
l.sfles r17,r13
l.sfles r30,r25
l.sfles r0,r12
.text
l_sfgtui:
l.sfgtui r0,0
l.sfgtui r31,65535
l.sfgtui r16,32768
l.sfgtui r15,32767
l.sfgtui r1,1
l.sfgtui r5,19233
l.sfgtui r23,37154
l.sfgtui r17,9693
.text
l_sfgeui:
l.sfgeui r0,0
l.sfgeui r31,65535
l.sfgeui r16,32768
l.sfgeui r15,32767
l.sfgeui r1,1
l.sfgeui r17,60598
l.sfgeui r15,16403
l.sfgeui r6,61860
.text
l_sfltui:
l.sfltui r0,0
l.sfltui r31,65535
l.sfltui r16,32768
l.sfltui r15,32767
l.sfltui r1,1
l.sfltui r3,52399
l.sfltui r24,19709
l.sfltui r10,830
.text
l_sfleui:
l.sfleui r0,0
l.sfleui r31,65535
l.sfleui r16,32768
l.sfleui r15,32767
l.sfleui r1,1
l.sfleui r23,39782
l.sfleui r17,46807
l.sfleui r9,43137
.text
l_sfgtsi:
l.sfgtsi r0,0
l.sfgtsi r31,-1
l.sfgtsi r16,-32768
l.sfgtsi r15,32767
l.sfgtsi r1,1
l.sfgtsi r13,-18814
l.sfgtsi r13,-10657
l.sfgtsi r28,-26667
.text
l_sfgesi:
l.sfgesi r0,0
l.sfgesi r31,-1
l.sfgesi r16,-32768
l.sfgesi r15,32767
l.sfgesi r1,1
l.sfgesi r12,2376
l.sfgesi r9,32059
l.sfgesi r13,20696
.text
l_sfltsi:
l.sfltsi r0,0
l.sfltsi r31,-1
l.sfltsi r16,-32768
l.sfltsi r15,32767
l.sfltsi r1,1
l.sfltsi r30,3021
l.sfltsi r5,-27813
l.sfltsi r28,-8816
.text
l_sflesi:
l.sflesi r0,0
l.sflesi r31,-1
l.sflesi r16,-32768
l.sflesi r15,32767
l.sflesi r1,1
l.sflesi r18,11338
l.sflesi r29,18873
l.sflesi r28,26050
.text
l_sfeq:
l.sfeq r0,r0
l.sfeq r31,r31
l.sfeq r16,r16
l.sfeq r15,r15
l.sfeq r1,r1
l.sfeq r28,r26
l.sfeq r13,r6
l.sfeq r26,r9
.text
l_sfeqi:
l.sfeqi r0,0
l.sfeqi r31,-1
l.sfeqi r16,-32768
l.sfeqi r15,32767
l.sfeqi r1,1
l.sfeqi r10,25887
l.sfeqi r21,19894
l.sfeqi r18,-13419
.text
l_sfne:
l.sfne r0,r0
l.sfne r31,r31
l.sfne r16,r16
l.sfne r15,r15
l.sfne r1,r1
l.sfne r18,r27
l.sfne r6,r18
l.sfne r0,r30
.text
l_sfnei:
l.sfnei r0,0
l.sfnei r31,-1
l.sfnei r16,-32768
l.sfnei r15,32767
l.sfnei r1,1
l.sfnei r8,11410
l.sfnei r6,-19239
l.sfnei r20,-22783
l_lo:
l.addi r1, r1, lo(0xdeadbeef)
l_hi:
l.movhi r1, hi(0xdeadbeef)
l_ha:
l.movhi r1, ha(0xdeadbeef)
l_mac:
l.mac r1,r2
l_maci:
l.maci r1,0
l.maci r2,-1
l.maci r2,32767
l.maci r2,-32768
l_adrp:
l.adrp r3,globaldata
l.adrp r3,localdata
l_muld:
l.muld r0,r0
l.muld r31,r31
l.muld r3,r4
l_muldu:
l.muldu r0,r0
l.muldu r31,r31
l.muldu r3,r4
l_macu:
l.macu r0,r0
l.macu r31,r31
l.macu r3,r4
l_msb:
l.msb r0,r0
l.msb r31,r31
l.msb r3,r4
l_msbu:
l.msbu r0,r0
l.msbu r31,r31
l.msbu r3,r4
|
tactcomplabs/xbgas-binutils-gdb
| 12,136
|
gas/testsuite/gas/arc/nps400-11.s
|
.text
; cp16/cp32 xa
cp16.na [cm:r1],[xa:r2]
cp16 [cm:r1],[xa:r2]
cp32.na [cm:r1],[xa:r2]
cp32 [cm:r1],[xa:r2]
cp16.na [cm:r1],[xa:r2,r1]
cp16 [cm:r1],[xa:r2,r1]
cp32.na [cm:r1],[xa:r2,r1]
cp32 [cm:r1],[xa:r2,r1]
cp16.na r2, [cm:r1],[xa:r2]
cp16 r2, [cm:r1],[xa:r2]
cp32.na r2, [cm:r1],[xa:r2]
cp32 r2, [cm:r1],[xa:r2]
cp16.na r2, [cm:r1],[xa:r2,r1]
cp16 r2, [cm:r1],[xa:r2,r1]
cp32.na r2, [cm:r1],[xa:r2,r1]
cp32 r2, [cm:r1],[xa:r2,r1]
;; cp16/cp32 jid
cp32 [cm:r1],[jid:r2]
cp32 r2, [cm:r1],[jid:r2]
;; cp16/cp32 sd
cp16 [cm:r2],[sd:r1,16,0]
cp16.na [cm:r2],[sd:r1,16,0]
cp16 r1, [cm:r2],[sd:r1,16,0]
cp16.na r1, [cm:r2],[sd:r1,16,0]
cp16 [cm:r2],[sd:r1,32,0]
cp16.na [cm:r2],[sd:r1,32,0]
cp16 r1, [cm:r2],[sd:r1,32,0]
cp16.na r1, [cm:r2],[sd:r1,32,0]
cp16 [cm:r2],[sd:r1,64,0]
cp16.na [cm:r2],[sd:r1,64,0]
cp16 r1, [cm:r2],[sd:r1,64,0]
cp16.na r1, [cm:r2],[sd:r1,64,0]
cp16 [cm:r2],[sd:r1,128,0]
cp16.na [cm:r2],[sd:r1,128,0]
cp16 r1, [cm:r2],[sd:r1,128,0]
cp16.na r1, [cm:r2],[sd:r1,128,0]
cp16 [cm:r2],[sd:r1,16,0]
cp16.na [cm:r2],[sd:r1,16,0]
cp16 r1, [cm:r2],[sd:r1,16,0]
cp16.na r1, [cm:r2],[sd:r1,16,0]
cp16 [cm:r2],[sd:r1,16,16]
cp16.na [cm:r2],[sd:r1,16,16]
cp16 r1, [cm:r2],[sd:r1,16,16]
cp16.na r1, [cm:r2],[sd:r1,16,16]
cp16 [cm:r2],[sd:r1,16,32]
cp16.na [cm:r2],[sd:r1,16,32]
cp16 r1, [cm:r2],[sd:r1,16,32]
cp16.na r1, [cm:r2],[sd:r1,16,32]
cp16 [cm:r2],[sd:r1,16,48]
cp16.na [cm:r2],[sd:r1,16,48]
cp16 r1, [cm:r2],[sd:r1,16,48]
cp16.na r1, [cm:r2],[sd:r1,16,48]
cp16 [cm:r2],[sd:r1,16,64]
cp16.na [cm:r2],[sd:r1,16,64]
cp16 r1, [cm:r2],[sd:r1,16,64]
cp16.na r1, [cm:r2],[sd:r1,16,64]
cp16 [cm:r2],[sd:r1,16,0, r2]
cp16.na [cm:r2],[sd:r1,16,0, r2]
cp16 r1, [cm:r2],[sd:r1,16,0,r2]
cp16.na r1, [cm:r2],[sd:r1,16,0,r2]
cp16 [cm:r2],[sd:r1,32,0, r2]
cp16.na [cm:r2],[sd:r1,32,0, r2]
cp16 r1, [cm:r2],[sd:r1,32,0, r2]
cp16.na r1, [cm:r2],[sd:r1,32,0, r2]
cp16 [cm:r2],[sd:r1,64,0, r2]
cp16.na [cm:r2],[sd:r1,64,0, r2]
cp16 r1, [cm:r2],[sd:r1,64,0, r2]
cp16.na r1, [cm:r2],[sd:r1,64,0, r2]
cp16 [cm:r2],[sd:r1,128,0, r2]
cp16.na [cm:r2],[sd:r1,128,0, r2]
cp16 r1, [cm:r2],[sd:r1,128,0, r2]
cp16.na r1, [cm:r2],[sd:r1,128,0, r2]
cp16 [cm:r2],[sd:r1,r2,r2]
cp16.na [cm:r2],[sd:r1,r2,r2]
cp16 r1, [cm:r2],[sd:r1,r2,r2]
cp16.na r1, [cm:r2],[sd:r1,r2,r2]
cp16 [cm:r2],[sd:r1,r2,r2,r2]
cp16.na [cm:r2],[sd:r1,r2,r2,r2]
cp16 r1, [cm:r2],[sd:r1,r2,r2,r2]
cp16.na r1, [cm:r2],[sd:r1,r2,r2,r2]
cp32 [cm:r2],[sd:r1,16,0]
cp32.na [cm:r2],[sd:r1,16,0]
cp32 r1, [cm:r2],[sd:r1,16,0]
cp32.na r1, [cm:r2],[sd:r1,16,0]
cp32 [cm:r2],[sd:r1,32,0]
cp32.na [cm:r2],[sd:r1,32,0]
cp32 r1, [cm:r2],[sd:r1,32,0]
cp32.na r1, [cm:r2],[sd:r1,32,0]
cp32 [cm:r2],[sd:r1,64,0]
cp32.na [cm:r2],[sd:r1,64,0]
cp32 r1, [cm:r2],[sd:r1,64,0]
cp32.na r1, [cm:r2],[sd:r1,64,0]
cp32 [cm:r2],[sd:r1,128,0]
cp32.na [cm:r2],[sd:r1,128,0]
cp32 r1, [cm:r2],[sd:r1,128,0]
cp32.na r1, [cm:r2],[sd:r1,128,0]
cp32 [cm:r2],[sd:r1,16,0]
cp32.na [cm:r2],[sd:r1,16,0]
cp32 r1, [cm:r2],[sd:r1,16,0]
cp32.na r1, [cm:r2],[sd:r1,16,0]
cp32 [cm:r2],[sd:r1,16,16]
cp32.na [cm:r2],[sd:r1,16,16]
cp32 r1, [cm:r2],[sd:r1,16,16]
cp32.na r1, [cm:r2],[sd:r1,16,16]
cp32 [cm:r2],[sd:r1,16,32]
cp32.na [cm:r2],[sd:r1,16,32]
cp32 r1, [cm:r2],[sd:r1,16,32]
cp32.na r1, [cm:r2],[sd:r1,16,32]
cp32 [cm:r2],[sd:r1,16,48]
cp32.na [cm:r2],[sd:r1,16,48]
cp32 r1, [cm:r2],[sd:r1,16,48]
cp32.na r1, [cm:r2],[sd:r1,16,48]
cp32 [cm:r2],[sd:r1,16,64]
cp32.na [cm:r2],[sd:r1,16,64]
cp32 r1, [cm:r2],[sd:r1,16,64]
cp32.na r1, [cm:r2],[sd:r1,16,64]
cp32 [cm:r2],[sd:r1,16,0, r2]
cp32.na [cm:r2],[sd:r1,16,0, r2]
cp32 r1, [cm:r2],[sd:r1,16,0,r2]
cp32.na r1, [cm:r2],[sd:r1,16,0,r2]
cp32 [cm:r2],[sd:r1,32,0, r2]
cp32.na [cm:r2],[sd:r1,32,0, r2]
cp32 r1, [cm:r2],[sd:r1,32,0, r2]
cp32.na r1, [cm:r2],[sd:r1,32,0, r2]
cp32 [cm:r2],[sd:r1,64,0, r2]
cp32.na [cm:r2],[sd:r1,64,0, r2]
cp32 r1, [cm:r2],[sd:r1,64,0, r2]
cp32.na r1, [cm:r2],[sd:r1,64,0, r2]
cp32 [cm:r2],[sd:r1,128,0, r2]
cp32.na [cm:r2],[sd:r1,128,0, r2]
cp32 r1, [cm:r2],[sd:r1,128,0, r2]
cp32.na r1, [cm:r2],[sd:r1,128,0, r2]
cp32 [cm:r2],[sd:r1,r2,r2]
cp32.na [cm:r2],[sd:r1,r2,r2]
cp32 r1, [cm:r2],[sd:r1,r2,r2]
cp32.na r1, [cm:r2],[sd:r1,r2,r2]
cp32 [cm:r2],[sd:r1,r2,r2,r2]
cp32.na [cm:r2],[sd:r1,r2,r2,r2]
cp32 r1, [cm:r2],[sd:r1,r2,r2,r2]
cp32.na r1, [cm:r2],[sd:r1,r2,r2,r2]
; cp16/cp32 xd
cp16 [cm:r2],[xd:r1,16,0]
cp16.na [cm:r2],[xd:r1,16,0]
cp16 r1, [cm:r2],[xd:r1,16,0]
cp16.na r1, [cm:r2],[xd:r1,16,0]
cp16 [cm:r2],[xd:r1,32,0]
cp16.na [cm:r2],[xd:r1,32,0]
cp16 r1, [cm:r2],[xd:r1,32,0]
cp16.na r1, [cm:r2],[xd:r1,32,0]
cp16 [cm:r2],[xd:r1,64,0]
cp16.na [cm:r2],[xd:r1,64,0]
cp16 r1, [cm:r2],[xd:r1,64,0]
cp16.na r1, [cm:r2],[xd:r1,64,0]
cp16 [cm:r2],[xd:r1,128,0]
cp16.na [cm:r2],[xd:r1,128,0]
cp16 r1, [cm:r2],[xd:r1,128,0]
cp16.na r1, [cm:r2],[xd:r1,128,0]
cp16 [cm:r2],[xd:r1,16,0]
cp16.na [cm:r2],[xd:r1,16,0]
cp16 r1, [cm:r2],[xd:r1,16,0]
cp16.na r1, [cm:r2],[xd:r1,16,0]
cp16 [cm:r2],[xd:r1,16,16]
cp16.na [cm:r2],[xd:r1,16,16]
cp16 r1, [cm:r2],[xd:r1,16,16]
cp16.na r1, [cm:r2],[xd:r1,16,16]
cp16 [cm:r2],[xd:r1,16,32]
cp16.na [cm:r2],[xd:r1,16,32]
cp16 r1, [cm:r2],[xd:r1,16,32]
cp16.na r1, [cm:r2],[xd:r1,16,32]
cp16 [cm:r2],[xd:r1,16,48]
cp16.na [cm:r2],[xd:r1,16,48]
cp16 r1, [cm:r2],[xd:r1,16,48]
cp16.na r1, [cm:r2],[xd:r1,16,48]
cp16 [cm:r2],[xd:r1,16,64]
cp16.na [cm:r2],[xd:r1,16,64]
cp16 r1, [cm:r2],[xd:r1,16,64]
cp16.na r1, [cm:r2],[xd:r1,16,64]
cp16 [cm:r2],[xd:r1,16,0, r2]
cp16.na [cm:r2],[xd:r1,16,0, r2]
cp16 r1, [cm:r2],[xd:r1,16,0,r2]
cp16.na r1, [cm:r2],[xd:r1,16,0,r2]
cp16 [cm:r2],[xd:r1,32,0, r2]
cp16.na [cm:r2],[xd:r1,32,0, r2]
cp16 r1, [cm:r2],[xd:r1,32,0, r2]
cp16.na r1, [cm:r2],[xd:r1,32,0, r2]
cp16 [cm:r2],[xd:r1,64,0, r2]
cp16.na [cm:r2],[xd:r1,64,0, r2]
cp16 r1, [cm:r2],[xd:r1,64,0, r2]
cp16.na r1, [cm:r2],[xd:r1,64,0, r2]
cp16 [cm:r2],[xd:r1,128,0, r2]
cp16.na [cm:r2],[xd:r1,128,0, r2]
cp16 r1, [cm:r2],[xd:r1,128,0, r2]
cp16.na r1, [cm:r2],[xd:r1,128,0, r2]
cp16 [cm:r2],[xd:r1,r2,r2]
cp16.na [cm:r2],[xd:r1,r2,r2]
cp16 r1, [cm:r2],[xd:r1,r2,r2]
cp16.na r1, [cm:r2],[xd:r1,r2,r2]
cp16 [cm:r2],[xd:r1,r2,r2,r2]
cp16.na [cm:r2],[xd:r1,r2,r2,r2]
cp16 r1, [cm:r2],[xd:r1,r2,r2,r2]
cp16.na r1, [cm:r2],[xd:r1,r2,r2,r2]
cp32 [cm:r2],[xd:r1,16,0]
cp32.na [cm:r2],[xd:r1,16,0]
cp32 r1, [cm:r2],[xd:r1,16,0]
cp32.na r1, [cm:r2],[xd:r1,16,0]
cp32 [cm:r2],[xd:r1,32,0]
cp32.na [cm:r2],[xd:r1,32,0]
cp32 r1, [cm:r2],[xd:r1,32,0]
cp32.na r1, [cm:r2],[xd:r1,32,0]
cp32 [cm:r2],[xd:r1,64,0]
cp32.na [cm:r2],[xd:r1,64,0]
cp32 r1, [cm:r2],[xd:r1,64,0]
cp32.na r1, [cm:r2],[xd:r1,64,0]
cp32 [cm:r2],[xd:r1,128,0]
cp32.na [cm:r2],[xd:r1,128,0]
cp32 r1, [cm:r2],[xd:r1,128,0]
cp32.na r1, [cm:r2],[xd:r1,128,0]
cp32 [cm:r2],[xd:r1,16,0]
cp32.na [cm:r2],[xd:r1,16,0]
cp32 r1, [cm:r2],[xd:r1,16,0]
cp32.na r1, [cm:r2],[xd:r1,16,0]
cp32 [cm:r2],[xd:r1,16,16]
cp32.na [cm:r2],[xd:r1,16,16]
cp32 r1, [cm:r2],[xd:r1,16,16]
cp32.na r1, [cm:r2],[xd:r1,16,16]
cp32 [cm:r2],[xd:r1,16,32]
cp32.na [cm:r2],[xd:r1,16,32]
cp32 r1, [cm:r2],[xd:r1,16,32]
cp32.na r1, [cm:r2],[xd:r1,16,32]
cp32 [cm:r2],[xd:r1,16,48]
cp32.na [cm:r2],[xd:r1,16,48]
cp32 r1, [cm:r2],[xd:r1,16,48]
cp32.na r1, [cm:r2],[xd:r1,16,48]
cp32 [cm:r2],[xd:r1,16,64]
cp32.na [cm:r2],[xd:r1,16,64]
cp32 r1, [cm:r2],[xd:r1,16,64]
cp32.na r1, [cm:r2],[xd:r1,16,64]
cp32 [cm:r2],[xd:r1,16,0, r2]
cp32.na [cm:r2],[xd:r1,16,0, r2]
cp32 r1, [cm:r2],[xd:r1,16,0,r2]
cp32.na r1, [cm:r2],[xd:r1,16,0,r2]
cp32 [cm:r2],[xd:r1,32,0, r2]
cp32.na [cm:r2],[xd:r1,32,0, r2]
cp32 r1, [cm:r2],[xd:r1,32,0, r2]
cp32.na r1, [cm:r2],[xd:r1,32,0, r2]
cp32 [cm:r2],[xd:r1,64,0, r2]
cp32.na [cm:r2],[xd:r1,64,0, r2]
cp32 r1, [cm:r2],[xd:r1,64,0, r2]
cp32.na r1, [cm:r2],[xd:r1,64,0, r2]
cp32 [cm:r2],[xd:r1,128,0, r2]
cp32.na [cm:r2],[xd:r1,128,0, r2]
cp32 r1, [cm:r2],[xd:r1,128,0, r2]
cp32.na r1, [cm:r2],[xd:r1,128,0, r2]
cp32 [cm:r2],[xd:r1,r2,r2]
cp32.na [cm:r2],[xd:r1,r2,r2]
cp32 r1, [cm:r2],[xd:r1,r2,r2]
cp32.na r1, [cm:r2],[xd:r1,r2,r2]
cp32 [cm:r2],[xd:r1,r2,r2,r2]
cp32.na [cm:r2],[xd:r1,r2,r2,r2]
cp32 r1, [cm:r2],[xd:r1,r2,r2,r2]
cp32.na r1, [cm:r2],[xd:r1,r2,r2,r2]
;cp16/32 cm to xa
cp16 [xa:r1],[cm:r2]
cp16.na [xa:r1],[cm:r2]
cp32 [xa:r1],[cm:r2]
cp32.na [xa:r1],[cm:r2]
cp32 [jid:r1],[cm:r2]
cp16 [sd:r1,0x20,0x10],[cm:r2]
cp16.na [sd:r1,0x20,0x10],[cm:r2]
cp16 [xd:r1,0x20,0x10],[cm:r2]
cp16.na [xd:r1,0x20,0x10],[cm:r2]
cp32 [sd:r1,0x20,0x10],[cm:r2]
cp32.na [sd:r1,0x20,0x10],[cm:r2]
cp32 [xd:r1,0x20,0x10],[cm:r2]
cp32.na [xd:r1,0x20,0x10],[cm:r2]
cp16 [sd:r1,0x20,0x10,r2],[cm:r2]
cp16.na [sd:r1,0x20,0x10,r2],[cm:r2]
cp16 [xd:r1,0x20,0x10,r2],[cm:r2]
cp16.na [xd:r1,0x20,0x10,r2],[cm:r2]
cp32 [sd:r1,0x20,0x10,r2],[cm:r2]
cp32.na [sd:r1,0x20,0x10,r2],[cm:r2]
cp32 [xd:r1,0x20,0x10,r2],[cm:r2]
cp32.na [xd:r1,0x20,0x10,r2],[cm:r2]
cp16 [sd:r1,r2,r2],[cm:r2]
cp16.na [sd:r1,r2,r2],[cm:r2]
cp16 [xd:r1,r2,r2],[cm:r2]
cp16.na [xd:r1,r2,r2],[cm:r2]
cp32 [sd:r1,r2,r2],[cm:r2]
cp32.na [sd:r1,r2,r2],[cm:r2]
cp32 [xd:r1,r2,r2],[cm:r2]
cp32.na [xd:r1,r2,r2],[cm:r2]
cp16 [sd:r1,r2,r2,r2],[cm:r2]
cp16.na [sd:r1,r2,r2,r2],[cm:r2]
cp16 [xd:r1,r2,r2,r2],[cm:r2]
cp16.na [xd:r1,r2,r2,r2],[cm:r2]
cp32 [sd:r1,r2,r2,r2],[cm:r2]
cp32.na [sd:r1,r2,r2,r2],[cm:r2]
cp32 [xd:r1,r2,r2,r2],[cm:r2]
cp32.na [xd:r1,r2,r2,r2],[cm:r2]
|
tactcomplabs/xbgas-binutils-gdb
| 3,845
|
gas/testsuite/gas/arc/taux.s
|
lr r5, [lp_start]
lr r5, [lp_end]
lr r5, [identity]
lr r5, [debug]
lr r5, [pc]
lr r5, [status32]
lr r5, [ic_ivic]
lr r5, [ic_ctrl]
lr r5, [ic_ivil]
lr r5, [ic_ram_address]
lr r5, [ic_tag]
lr r5, [ic_wp]
lr r5, [ic_data]
lr r5, [count0]
lr r5, [control0]
lr r5, [limit0]
lr r5, [dc_ivdc]
lr r5, [dc_ctrl]
lr r5, [dc_ldl]
lr r5, [dc_ivdl]
lr r5, [dc_flsh]
lr r5, [dc_ram_addr]
lr r5, [dc_tag]
lr r5, [dc_wp]
lr r5, [dc_data]
lr r5, [dccm_base_build]
lr r5, [crc_build]
lr r5, [bta_link_build]
lr r5, [vbfdw_build]
lr r5, [ea_build]
lr r5, [dataspace]
lr r5, [memsubsys]
lr r5, [vecbase_ac_build]
lr r5, [p_base_addr]
lr r5, [data_uncached_build]
lr r5, [fp_build]
lr r5, [dpfp_build]
lr r5, [mpu_build]
lr r5, [rf_build]
lr r5, [mmu_build]
lr r5, [vecbase_build]
lr r5, [d_cache_build]
lr r5, [madi_build]
lr r5, [dccm_build]
lr r5, [timer_build]
lr r5, [ap_build]
lr r5, [i_cache_build]
lr r5, [iccm_build]
lr r5, [dspram_build]
lr r5, [mac_build]
lr r5, [multiply_build]
lr r5, [swap_build]
lr r5, [norm_build]
lr r5, [minmax_build]
lr r5, [barrel_build]
lr r5, [ax0]
lr r5, [ax1]
lr r5, [ax2]
lr r5, [ax3]
lr r5, [ay0]
lr r5, [ay1]
lr r5, [ay2]
lr r5, [ay3]
lr r5, [mx00]
lr r5, [mx01]
lr r5, [mx10]
lr r5, [mx11]
lr r5, [mx20]
lr r5, [mx21]
lr r5, [mx30]
lr r5, [mx31]
lr r5, [my00]
lr r5, [my01]
lr r5, [my10]
lr r5, [my11]
lr r5, [my20]
lr r5, [my21]
lr r5, [my30]
lr r5, [my31]
lr r5, [xyconfig]
lr r5, [burstsys]
lr r5, [burstxym]
lr r5, [burstsz]
lr r5, [burstval]
lr r5, [xylsbasex]
lr r5, [xylsbasey]
lr r5, [aux_xmaclw_h]
lr r5, [aux_xmaclw_l]
lr r5, [se_ctrl]
lr r5, [se_stat]
lr r5, [se_err]
lr r5, [se_eadr]
lr r5, [se_spc]
lr r5, [sdm_base]
lr r5, [scm_base]
lr r5, [se_dbg_ctrl]
lr r5, [se_dbg_data0]
lr r5, [se_dbg_data1]
lr r5, [se_dbg_data2]
lr r5, [se_dbg_data3]
lr r5, [se_watch]
lr r5, [bpu_build]
lr r5, [isa_config]
lr r5, [hwp_build]
lr r5, [pct_build]
lr r5, [cc_build]
lr r5, [pm_bcr]
lr r5, [scq_switch_build]
lr r5, [vraptor_build]
lr r5, [dma_config]
lr r5, [simd_config]
lr r5, [vlc_build]
lr r5, [simd_dma_build]
lr r5, [ifetch_queue_build]
lr r5, [smart_build]
lr r5, [count1]
lr r5, [control1]
lr r5, [limit1]
lr r5, [timer_xx]
lr r5, [aux_irq_hint]
lr r5, [ap_amv0]
lr r5, [ap_amm0]
lr r5, [ap_ac0]
lr r5, [ap_amv1]
lr r5, [ap_amm1]
lr r5, [ap_ac1]
lr r5, [ap_amv2]
lr r5, [ap_amm2]
lr r5, [ap_ac2]
lr r5, [ap_amv3]
lr r5, [ap_amm3]
lr r5, [ap_ac3]
lr r5, [ap_amv4]
lr r5, [ap_amm4]
lr r5, [ap_ac4]
lr r5, [ap_amv5]
lr r5, [ap_amm5]
lr r5, [ap_ac5]
lr r5, [ap_amv6]
lr r5, [ap_amm6]
lr r5, [ap_ac6]
lr r5, [ap_amv7]
lr r5, [ap_amm7]
lr r5, [ap_ac7]
lr r5, [fp_status]
lr r5, [aux_dpfp1l]
lr r5, [d1l]
lr r5, [aux_dpfp1h]
lr r5, [d1h]
lr r5, [d1l]
lr r5, [aux_dpfp2l]
lr r5, [d2l]
lr r5, [d1h]
lr r5, [aux_dpfp2h]
lr r5, [d2h]
lr r5, [d2l]
lr r5, [dpfp_status]
lr r5, [d2h]
lr r5, [eret]
lr r5, [erbta]
lr r5, [erstatus]
lr r5, [ecr]
lr r5, [efa]
lr r5, [mpuen]
lr r5, [icause1]
lr r5, [icause2]
lr r5, [aux_ienable]
lr r5, [aux_itrigger]
lr r5, [xpu]
lr r5, [bta]
lr r5, [aux_irq_pulse_cancel]
lr r5, [aux_irq_pending]
lr r5, [mpuic]
lr r5, [mpufa]
lr r5, [mpurdb0]
lr r5, [mpurdp0]
lr r5, [mpurdb1]
lr r5, [mpurdp1]
lr r5, [mpurdb2]
lr r5, [mpurdp2]
lr r5, [mpurdb3]
lr r5, [mpurdp3]
lr r5, [mpurdb4]
lr r5, [mpurdp4]
lr r5, [mpurdb5]
lr r5, [mpurdp5]
lr r5, [mpurdb6]
lr r5, [mpurdp6]
lr r5, [mpurdb7]
lr r5, [mpurdp7]
lr r5, [mpurdb8]
lr r5, [mpurdp8]
lr r5, [mpurdb9]
lr r5, [mpurdp9]
lr r5, [mpurdb10]
lr r5, [mpurdp10]
lr r5, [mpurdb11]
lr r5, [mpurdp11]
lr r5, [mpurdb12]
lr r5, [mpurdp12]
lr r5, [mpurdb13]
lr r5, [mpurdp13]
lr r5, [mpurdb14]
lr r5, [mpurdp14]
lr r5, [mpurdb15]
lr r5, [mpurdp15]
|
tactcomplabs/xbgas-binutils-gdb
| 2,044
|
gas/testsuite/gas/arc/nps400-8.s
|
.text
;; bdalc / sbdalc
bdalc r0,[cm:r0],r0,r0
bdalc r1,[cm:r2],r2,r3
bdalc r0,[cm:r0],r0,0,1
bdalc r2,[cm:r3],r3,1,1
bdalc r3,[cm:r4],r4,1,8
sbdalc r0, r0, 0
sbdalc r3, r4, 1
;; bdfre / sbdfre
bdfre 0,[cm:r0],r0,r0
bdfre 0,[cm:r1],r1,r2
bdfre 0,[cm:r0],r0,1
bdfre 0,[cm:r2],r2,8
bdfre 0,[cm:r0],r0,0,1
bdfre 0,[cm:r6],r6,0,8
bdfre 0,[cm:r0],r0,1,1
bdfre 0,[cm:r6],r6,1,8
sbdfre 0, r0, r0
sbdfre 0, r1, r2
;; bdbgt
bdbgt 0,r0,r0
bdbgt 0,r4,r6
;; idxalc / sidxalc
idxalc r0,[cm:r0],r0,r0
idxalc r1,[cm:r2],r2,r3
idxalc r4,[cm:r5],r5,2
sidxalc r0,r0
sidxalc r4,r2
;; idxfre / sidxfre
idxfre 0,[cm:r0],r0,r0
idxfre 0,[cm:r1],r1,r2
idxfre 0,[cm:r0],r0,1
idxfre 0,[cm:r2],r2,8
sidxfre 0, r0, r0
sidxfre 0, r1, r2
;; idxbgt
idxbgt 0,r0,r0
idxbgt 0,r7,r8
;; efabgt
efabgt 0,0x0,r0
efabgt 0,0xffffffff,r3
efabgt 0,r0,0x0
efabgt 0,r4,0xffffffff
efabgt 0,r0,r0
efabgt 0,r7,r8
efabgt r0,0x0,r0
efabgt r4,0xffffffff,r6
efabgt r0,r0,0x0
efabgt r2,r3,0xffffffff
efabgt r0,r0,r0
efabgt r7,r8,r9
;; jobget
jobget 0,[cjid:r0]
jobget 0,[cjid:r6]
jobget.cl 0,[cjid:r0]
jobget.cl 0,[cjid:r6]
;; jobdn
jobdn 0,[cjid:r0],r0,r0
jobdn 0,[cjid:r2],r2,r4
jobdn 0,[cjid:r0],r0,0
jobdn 0,[cjid:r2],r2,15
;; jobalc / sjobalc
jobalc r0,[cm:r0],r0,r0
jobalc r1,[cm:r2],r2,r3
jobalc r0,[cm:r0],r0,1
jobalc r1,[cm:r2],r2,4
sjobalc r0,r0
sjobalc r6,r5
;; jobbgt
jobbgt r0,r0,r0
jobbgt r2,r5,r6
;; cnljob
cnljob 0
;; qseq
qseq r0,[r0]
qseq r2,[r4]
|
tactcomplabs/xbgas-binutils-gdb
| 1,827
|
gas/testsuite/gas/arc/pseudos.s
|
# Test pseudo instructions generation.
push r0
pop r1
.L1:
brgt r0, r1, @.L1 ; Encode as BRLT<.d> c,b,s9
brgt r0, -1, @.L1 ; Encode as BRGE<.d> b,u6+1,s9
brgt r0, 0x3F, @.L1 ; Encode as BRLT limm,b,s9
brgt r0, -2, @.L1 ; Encode as BRLT limm,b,s9
brgt -2, r0, @.L1 ; Encode as BRLT c,limm,s9
brgt -2, -1, @.L1 ; Encode as BRGE limm,u6+1,s9
brgt -2, 0x3E, @.L1 ; Encode as BRGE limm,u6+1,s9
brhi r1, r1, @.L1 ; BRHI<.d> b,c,s9 Encode as BRLO<.d> c,b,s9
brhi r1, -1, @.L1 ; BRHI<.d> b,u6,s9 Encode as BRHS<.d> b,u6+1,s9
brhi r1, 0x3F, @.L1 ; BRHI b,limm,s9 Encode as BRLO limm,b,s9
brhi r1, -2, @.L1 ; BRHI b,limm,s9 Encode as BRLO limm,b,s9
brhi -2, r0, @.L1 ; BRHI limm,c,s9 Encode as BRLO c,limm,s9
brhi -2, -1, @.L1 ; BRHI limm,u6,s9 Encode as BRHS limm,u6+1,s9
brhi -2, 0x3E, @.L1 ; BRHI limm,u6,s9 Encode as BRHS limm,u6+1,s9
brle r1, r1, @.L1 ; BRLE<.d> b,c,s9 Encode as BRGE<.d> c,b,s9
brle r1, -1, @.L1 ; BRLE<.d> b,u6,s9 Encode as BRLT<.d> b,u6+1,s9
brle r1, 0x3F, @.L1 ; BRLE b,limm,s9 Encode as BRGE limm,b,s9
brle r1, -2, @.L1 ; BRLE b,limm,s9 Encode as BRGE limm,b,s9
brle -2, r0, @.L1 ; BRLE limm,c,s9 Encode as BRGE c,limm,s9
brle -2, -1, @.L1 ; BRLE limm,u6,s9 Encode as BRLT limm,u6+1,s9
brle -2, 0x3E, @.L1 ; BRLE limm,u6,s9 Encode as BRLT limm,u6+1,s9
brle r1, r1, @.L1 ; BRLS<.d> b,c,s9 Encode as BRHS<.d> c,b,s9
brle r1, -1, @.L1 ; BRLS<.d> b,u6,s9 Encode as BRLO b,u6+1,s9
brle r1, 0x3F, @.L1 ; BRLS b,limm,s9 Encode as BRHS limm,b,s9
brle r1, -2, @.L1 ; BRLS limm,c,s9 Encode as BRHS c,limm,s9
brle -2, r0, @.L1 ; BRLS limm,c,s9 Encode as BRHS c,limm,s9
brle -2, -1, @.L1 ; BRLS limm,u6,s9 Encode as BRLO limm,u6+1,s9
brle -2, 0x3E, @.L1 ; BRLS limm,u6,s9 Encode as BRLO limm,u6+1,s9
|
tactcomplabs/xbgas-binutils-gdb
| 1,185
|
gas/testsuite/gas/arc/textinsn3op.s
|
# Insn 3op .extInstruction test
.extInstruction myinsn, 0x07, 0x30, SUFFIX_FLAG|SUFFIX_COND, SYNTAX_3OP
myinsn r0,r1,r2
myinsn r26,fp,sp
myinsn ilink1,ilink2,blink
myinsn r0,r1,0
myinsn r0,0,r2
myinsn 0,r1,r2
myinsn r0,r1,-1
myinsn r0,-1,r2
myinsn r0,r1,255
myinsn r0,255,r2
myinsn r0,r1,-256
myinsn r0,-256,r2
myinsn r0,r1,256
myinsn r0,-257,r2
myinsn r0,256,256
myinsn r0,r1,foo
myinsn.al r0,r0,r2
myinsn.ra r3,r3,r5
myinsn.eq r6,r6,r8
myinsn.z r9,r9,r11
myinsn.ne r12,r12,r14
myinsn.nz r15,r15,r17
myinsn.pl r18,r18,r20
myinsn.p r21,r21,r23
myinsn.mi r24,r24,r26
myinsn.n r27,r27,r29
myinsn.cs r30,r30,r31
myinsn.c r3,r3,r3
myinsn.lo r3,r3,r8
myinsn.cc r3,r3,r4
myinsn.nc r4,r4,r4
myinsn.hs r4,r4,r7
myinsn.vs r4,r4,r5
myinsn.v r5,r5,r5
myinsn.vc r5,r5,r5
myinsn.nv r5,r5,r5
myinsn.gt r6,r6,r0
myinsn.ge r0,r0,0
myinsn.lt r1,r1,1
myinsn.hi r3,r3,3
myinsn.ls r4,r4,4
myinsn.pnz r5,r5,5
myinsn.f r0,r1,r2
myinsn.f r0,r1,1
myinsn.f r0,1,r2
myinsn.f 0,r1,r2
myinsn.f r0,r1,512
myinsn.f r0,512,r2
myinsn.eq.f r1,r1,r2
myinsn.ne.f r0,r0,0
myinsn.lt.f r2,r2,r2
myinsn.gt.f 0,1,2
myinsn.le.f 0,512,512
myinsn.ge.f 0,512,2
|
tactcomplabs/xbgas-binutils-gdb
| 1,338
|
gas/testsuite/gas/arc/ext3op.s
|
# 3 operand insn test
dsp_fp_div r0,r1,r2
dsp_fp_div gp,fp,sp
dsp_fp_div ilink,ilink,blink
dsp_fp_div r0,r1,0
dsp_fp_div r0,0,r2
dsp_fp_div 0,r1,r2
dsp_fp_div r0,r1,-1
dsp_fp_div r0,-1,r2
dsp_fp_div r0,r1,255
dsp_fp_div r0,255,r2
dsp_fp_div r0,r1,-256
dsp_fp_div r0,-256,r2
dsp_fp_div r1,r1,256
dsp_fp_div r0,r1,0x3F
dsp_fp_div r0,-257,r2
dsp_fp_div r0,256,256
dsp_fp_div r0,r1,foo
dsp_fp_div.al r0,r0,r2
dsp_fp_div.ra r3,r3,r5
dsp_fp_div.eq r6,r6,r8
dsp_fp_div.z r9,r9,r11
dsp_fp_div.ne r12,r12,r14
dsp_fp_div.nz r15,r15,r17
dsp_fp_div.pl r18,r18,r20
dsp_fp_div.p r21,r21,r23
dsp_fp_div.mi r24,r24,r26
dsp_fp_div.n r27,r27,r29
dsp_fp_div.cs r30,r30,r31
dsp_fp_div.c r3,r3,r3
dsp_fp_div.lo r3,r3,r8
dsp_fp_div.cc r3,r3,r4
dsp_fp_div.nc r4,r4,r4
dsp_fp_div.hs r4,r4,r7
dsp_fp_div.vs r4,r4,r5
dsp_fp_div.v r5,r5,r5
dsp_fp_div.vc r5,r5,r5
dsp_fp_div.nv r5,r5,r5
dsp_fp_div.gt r6,r6,r0
dsp_fp_div.ge r0,r0,0
dsp_fp_div.lt r1,r1,1
dsp_fp_div.hi r3,r3,3
dsp_fp_div.ls r4,r4,4
dsp_fp_div.pnz r5,r5,5
dsp_fp_div.f r0,r1,r2
dsp_fp_div.f r0,r1,1
dsp_fp_div.f r0,1,r2
dsp_fp_div.f 0,r1,r2
dsp_fp_div.f r0,r1,512
dsp_fp_div.f r0,512,r2
dsp_fp_div.eq.f r1,r1,r2
dsp_fp_div.ne.f r0,r0,0
dsp_fp_div.lt.f r2,r2,r2
dsp_fp_div.gt.f 0,1,2
dsp_fp_div.le.f 0,512,512
dsp_fp_div.ge.f 0,512,2
|
tactcomplabs/xbgas-binutils-gdb
| 1,321
|
gas/testsuite/gas/arc/nps400-7.s
|
.text
;; mrgb
mrgb r0,r0,r1,4,5,3,8,6,2
mrgb.cl r2,r2,r1,4,5,3,8,6,2
;; mov2b
mov2b r1,r1,r2,4,3,2,8,1,6
mov2b.cl r1,r2,4,3,2,8,1,6
;; ext4b
ext4b r3,r3,r12,28,5,10,30,31
ext4b.cl r2,r13,28,5,10,30,31
;; ins4b
ins4b r3,r3,r12,5,10,30,31,28
ins4b.cl r2,r13,5,10,30,31,28
;; mov3b
mov3b r14,r14,r12, 1,0,6, 7,3,2, 20,2,21
mov3b r1,r1,r12, 4,1,1, 3,0,16, 3,3,8
mov3b r14,r14,r12, 8,2,14, 8,1,2, 14,0,3
mov3b r1,r1,r12, 12,3,1, 3,2,13, 5,1,2
;; mov3bcl
mov3bcl r0,r1, 1,0,1, 0,1,1, 12,3,0
mov3b.cl r0,r1, 2,1,5, 22,2,2, 31,2,3
mov3bcl r0,r1, 3,2,9, 23,3,6, 30,1,31
mov3b.cl r0,r1, 4,3,11, 24,0,30, 30,0,30
;; mov4b
mov4b r0,r0,r14, 10,3,20, 2,2,0, 6,1,7, 14,0,3
mov4b r0,r0,r14, 1,0,11, 12,3,4, 31,2,11, 24,1,2
mov4b r0,r0,r14, 5,1,8, 21,0,30, 3,3,31, 8,2,8
mov4b r0,r0,r14, 15,2,13, 22,1,22, 13,0,30, 4,3,4
;; mov4bl
mov4bcl r12,r13,1,1,1,2,2,2,3,3,3,4,0,4
mov4b.cl r13,r14,1,2,1,2,3,2,3,0,3,4,1,4
mov4bcl r2,r3, 1,3,1,2,0,2,3,1,3,4,2,4
mov4b.cl r1,r2, 1,0,1,2,1,2,3,2,3,4,3,4
|
tactcomplabs/xbgas-binutils-gdb
| 2,004
|
gas/testsuite/gas/arc/nps400-1.s
|
.text
movb r0, r0, r1, 4, 5, 6
movb r0, r0, r12, 4, 5, 6
movb r15, r15, r12, 4, 5, 6
movb.cl r0, r1, 4, 5, 6
movb.cl r0, r14, 4, 5, 6
movb.cl r13, r1, 4, 5, 6
movh r0, r0, 1234
movh r3, r3, 0xffff
movh.cl r0, 1234
movh.cl r3, 0xffff
/* movbi */
movbi r14, r14, 6, 8, 4
movbi.f r23, r23, 20, 11, 1
movbi.cl r30, 10, 18, 2
movbi.f.cl r6, 9, 0, 8
/* decode1 */
decode1 r0, r0, r2, 5, 11
decode1.f r0, r0, r2, 5, 11
decode1.cl r0, r2, 11
decode1.cl.f r0, r2, 18
/* fbset */
fbset r1, r1, r3, 3, 15
fbset.f r1, r1, r3, 3, 15
/* fbclear */
fbclr r2, r2, r12, 3, 15
fbclr.f r3, r3, r12, 3, 15
/* encode0 */
encode0 r2, r1, 18, 1
encode0.f r0, r0, 0, 32
/* encode1 */
encode1 r2, r1, 31, 1
encode1.f r0, r0, 0, 32
/* rflt */
rflt r10,r12,r20
rflt r0,0x12345678,r20
rflt r6,r7,0xffffffff
rflt r8,0xffffffff,0xffffffff
rflt 0,r14,r13
rflt 0,0xffffffff,r10
rflt 0,r12,0xffffffff
rflt r4,r5,0x1
rflt r3,0x12345678,0x2
rflt 0,r1,0x4
rflt 0,0xffffffff,0x1
.macro crc_test mnem
\mnem r1,r2,r3
\mnem r4,0xffffffff,r5
\mnem r6,r7,0xffffffff
\mnem r8,0xffffffff,0xffffffff
\mnem 0,r9,r10
\mnem 0,0xffffffff,r11
\mnem 0,r12,0xffffffff
\mnem r13,r14,0x3f
\mnem r15,0xffffffff,0x3f
\mnem 0,r16,0x3f
\mnem 0,0xffffffff,0x3f
.endm
/* crc16 */
crc_test crc16
crc_test crc16.r
/* crc32 */
crc_test crc32
crc_test crc32.r
|
tactcomplabs/xbgas-binutils-gdb
| 1,633
|
gas/testsuite/gas/arc/dsp.s
|
#Test if disassembler correctly prints DSP instructions.
vmac2hnfr r0,r2,r4
abssh r0,r2
aslacc r0
aslsacc r0
asrsr r0,r2,r4
cbflyhf0r r0,r2,r4
cbflyhf1r r0,r2
cmacchfr r0,r2,r4
cmacchnfr r0,r2,r4
cmachfr r0,r2,r4
cmachnfr r0,r2,r4
cmpychfr r0,r2,r4
cmpychnfr r0,r2,r4
cmpyhfmr r0,r2,r4
cmpyhfr r0,r2,r4
cmpyhnfr r0,r2,r4
divacc r0
dmachbl r0,r2,r4
dmachbm r0,r2,r4
dmachf r0,r2,r4
dmachfr r0,r2,r4
dmpyhbl r0,r2,r4
dmpyhbm r0,r2,r4
dmpyhf r0,r2,r4
dmpyhfr r0,r2,r4
dmpyhwf r0,r2,r4
flagacc r0
getacc r0,r2
macf r0,r2,r4
macfr r0,r2,r4
macwhfm r0,r2,r4
macwhfmr r0,r2,r4
macwhl r0,r2,r4
macwhul r0,r2,r4
mpyf r0,r2,r4
mpyfr r0,r2,r4
mpywhfl r0,r2,r4
mpywhflr r0,r2,r4
mpywhfm r0,r2,r4
mpywhfmr r0,r2,r4
mpywhl r0,r2,r4
mpywhul r0,r2,r4
msubdf r0,r2,r4
msubf r0,r2,r4
msubfr r0,r2,r4
negsh r0,r2
normacc r0,r2
rndh r0,r2
sath r0,r2
setacc r0,r2,r4
sqrtacc r0
vabs2h r0,r2
vabss2h r0,r2
vadd4b r0,r2,r4
vadds2h r0,r2,r4
vaddsubs2h r0,r2,r4
valgn2h r0,r2,r4
vasl2h r0,r2,r4
vasls2h r0,r2,r4
vasr2h r0,r2,r4
vasrs2h r0,r2,r4
vasrsr2h r0,r2,r4
vext2bhl r0,r2
vext2bhm r0,r2
vlsr2h r0,r2,r4
vmac2h r0,r2,r4
vmac2hf r0,r2,r4
vmac2hfr r0,r2,r4
vmac2hu r0,r2,r4
vmax2h r0,r2,r4
vmin2h r0,r2,r4
vmpy2h r0,r2,r4
vmpy2hf r0,r2,r4
vmpy2hfr r0,r2,r4
vmpy2hu r0,r2,r4
vmpy2hwf r0,r2,r4
vmsub2hf r0,r2,r4
vmsub2hfr r0,r2,r4
vmsub2hnfr r0,r2,r4
vneg2h r0,r2
vnegs2h r0,r2
vnorm2h r0,r2
vrep2hl r0,r2
vrep2hm r0,r2
vsext2bhl r0,r2
vsext2bhm r0,r2
vsub4b r0,r2,r4
vsubadds2h r0,r2,r4
vsubs2h r0,r2,r4
|
tactcomplabs/xbgas-binutils-gdb
| 1,915
|
gas/testsuite/gas/arc/nps400-12.s
|
.text
; Miscellaneous
; whash
whash r2,[cm:r0],r1
whash r5,[cm:r3],r14
whash 0,[cm:r0],r1
whash 0,[cm:r3],r14
whash r2,[cm:r0],7
whash 0,[cm:r0],7
whash r2,[cm:r0],64
whash 0,[cm:r0],64
; mcmp
mcmp r0,[cm:r0],[cm:r1],r1
mcmp.s r0,[cm:r0],[cm:r1],r1
mcmp.m r0,[cm:r0],[cm:r1],r1
mcmp.s.m r0,[cm:r0],[cm:r1],r1
mcmp r0,[cm:r0,r0],[cm:r1],r1
mcmp.s r0,[cm:r0,r0],[cm:r1],r1
mcmp.m r0,[cm:r0,r0],[cm:r1],r1
mcmp.s.m r0,[cm:r0,r0],[cm:r1],r1
mcmp r0,[cm:r0,4],[cm:r1],r1
mcmp.s r0,[cm:r0,4],[cm:r1],r1
mcmp.m r0,[cm:r0,4],[cm:r1],r1
mcmp.s.m r0,[cm:r0,4],[cm:r1],r1
mcmp r0,[cm:r0,8],[cm:r1],r1
mcmp r0,[cm:r0,12],[cm:r1],r1
mcmp r0,[cm:r0],[cm:r1],4
mcmp.s r0,[cm:r0],[cm:r1],4
mcmp.m r0,[cm:r0],[cm:r1],4
mcmp.s.m r0,[cm:r0],[cm:r1],8
mcmp r0,[cm:r0],[cm:r1],127
mcmp r0,[cm:r0,8],[cm:r1],4
mcmp.s r0,[cm:r0,8],[cm:r1],4
mcmp.m r0,[cm:r0,8],[cm:r1],4
mcmp.s.m r0,[cm:r0,8],[cm:r1],4
mcmp r0,[cm:r0,r0],[cm:r1],46
mcmp.s r0,[cm:r0,r0],[cm:r1],70
mcmp.m r0,[cm:r0,r0],[cm:r1],72
mcmp.s.m r0,[cm:r0,r0],[cm:r1],125
;asri
asri 0, r0
asri.core 0, r0
asri.clsr 0,r0
asri.all 0,r0
asri.gic 0,r0
rspi.gic 0,r0
;wkup
wkup 0,r0
wkup.cl
;getsti
getsti r2,[cm:r0]
getsti 0,[cm:r0]
label:
;getrtc
getrtc r2,[cm:r0]
getrtc 0,[cm:r0]
;b<cc>
bnj label
bnm label
bnt label
|
tactcomplabs/xbgas-binutils-gdb
| 1,428
|
gas/testsuite/gas/arc/nps400-9.s
|
.text
;; dcmac
dcmac r0,[cm:r0],[cm:r0],r0
dcmac r2,[cm:r4],[cm:r4],r7
dcmac r31,[cm:r31],[cm:r31],r31
dcmac r0,[cm:r0],[cm:0x0],r0
dcmac r2,[cm:r4],[cm:0x1234],r7
dcmac r31,[cm:r31],[cm:0xffff],r31
dcmac r0,[cm:0x0],[cm:r0],r0
dcmac r2,[cm:0x4321],[cm:r4],r7
dcmac r31,[cm:0xffff],[cm:r31],r31
dcmac 0,[cm:r0],[cm:r0],r0
dcmac 0,[cm:r4],[cm:r4],r7
dcmac 0,[cm:r31],[cm:r31],r31
dcmac 0,[cm:r0],[cm:0x0],r0
dcmac 0,[cm:r4],[cm:0x1234],r7
dcmac 0,[cm:r31],[cm:0xffff],r31
dcmac 0,[cm:0x0],[cm:r0],r0
dcmac 0,[cm:0x4321],[cm:r4],r7
dcmac 0,[cm:0xffff],[cm:r31],r31
dcmac r0,[cm:r0],[cm:r0],1
dcmac r2,[cm:r4],[cm:r4],0xf
dcmac r31,[cm:r31],[cm:r31],0x3f
dcmac r0,[cm:r0],[cm:0x0],1
dcmac r2,[cm:r4],[cm:0x1234],0xf
dcmac r31,[cm:r31],[cm:0xffff],0x3f
dcmac r0,[cm:0x0],[cm:r0],1
dcmac r2,[cm:0x4321],[cm:r4],0xf
dcmac r31,[cm:0xffff],[cm:r31],0x3f
dcmac 0,[cm:r0],[cm:r0],1
dcmac 0,[cm:r4],[cm:r4],0xf
dcmac 0,[cm:r31],[cm:r31],64
dcmac 0,[cm:r0],[cm:0x0],1
dcmac 0,[cm:r4],[cm:0x1234],0xf
dcmac 0,[cm:r31],[cm:0xffff],64
dcmac 0,[cm:0x0],[cm:r0],1
dcmac 0,[cm:0x4321],[cm:r4],0xf
dcmac 0,[cm:0xffff],[cm:r31],64
|
tactcomplabs/xbgas-binutils-gdb
| 6,388
|
gas/testsuite/gas/arc/nps400-6.s
|
.text
.macro addb_like_test mnem
\mnem r0,r0,r1,0,8,2
\mnem\().f r0,r0,r1,16,8,2
\mnem\().f.sx r0,r0,r1,8,24,6
.endm
.macro andb_like_test mnem, size
\mnem r0,r0,r1,0,8,\size
\mnem\().f r0,r0,r1,16,8,\size
.endm
.macro notb_like_test mnem
\mnem r0,r1,0,8
\mnem\().f r0,r1,16,16
.endm
.macro div_like_test mnem
\mnem r0,r0,r2,8,8
\mnem\().f r0,r0,0xf,8
.endm
.macro qcmp_test mnem
\mnem r2,r2,r0,8,8,0,1,3
\mnem r2,r2,r0,8,8,1,1
\mnem r2,r2,r0,8,8,1
\mnem r2,r2,r0,8,8
.endm
.macro calcsxd_test mnem
\mnem\() r0, r0, r0, 1
\mnem\().f r1, r1, r0, 2
\mnem\() r2, r2, r3, 4
\mnem\().f r0, r0, r0, 8
\mnem\() r3, r3, r0, 16
\mnem\().f r0, r0, r0, 32
\mnem\() r0, r0, r1, 64
\mnem\().f r2, r2, r0, 128
\mnem\() r1, r1, r2, 256
.endm
.macro calcbsxdkey_test mnem
\mnem\() r0, r0, r0
\mnem\().f r1, r1, r0
\mnem\() r1, r1, r2
\mnem\().f r3, r3, r2
.endm
.macro mxb_like_test mnem
\mnem\() r0, r1, 0, 1, 2
\mnem\() r0, r1, 7, 8, 7
\mnem\() r0, r1, 7, 7, 8
\mnem\().s r2, r3, 1, 4, 3, 2
\mnem\().s r2, r3, 7, 8, 7, 7
\mnem\().s r2, r3, 7, 7, 8, 7
\mnem\().s r2, r3, 7, 8, 7, 8
.endm
.macro addsubl_test mnem
\mnem\() r0, r0, 0
\mnem\() r2, r2, 32767
\mnem\() r5, r5, -32768
\mnem\().f r10, r10, 0
\mnem\().f r11, r11, 1
\mnem\().f r12, r12, -1
.endm
.macro andorxorl_test mnem
\mnem\() r0, r0, 0
\mnem\() r1, r1, 1
\mnem\() r2, r2, 65535
\mnem\().f r10, r10, 0
\mnem\().f r11, r11, 1
\mnem\().f r12, r12, 65535
.endm
.macro andorab_test mnem
\mnem\() r0, r0, 0, 1
\mnem\() r1, r2, 15, 16
\mnem\().f r2, r3, 0, 1
\mnem\().f r12, r13, 16, 16
\mnem\() r0, r0, r0, 0, 1
\mnem\() r1, r1, r2, 15, 16
\mnem\().f r2, r2, r3, 0, 1
\mnem\().f r12, r12, r13, 16, 16
.endm
addb_like_test addb
addb_like_test subb
addb_like_test adcb
addb_like_test sbcb
andb_like_test andb, 2
andb_like_test xorb, 2
andb_like_test orb, 2
andb_like_test shlb, 2
andb_like_test shrb, 2
andb_like_test fxorb, 8
andb_like_test wxorb, 16
notb_like_test notb
notb_like_test cntbb
div_like_test div
div_like_test mod
div_like_test divm
qcmp_test qcmp.ar
qcmp_test qcmp.al
calcsxd_test calcsd
calcsxd_test calcxd
calcbsxdkey_test calcbsd
calcbsxdkey_test calcbxd
calcbsxdkey_test calckey
calcbsxdkey_test calcxkey
mxb_like_test mxb
mxb_like_test imxb
addsubl_test addl
addsubl_test subl
andorxorl_test andl
andorxorl_test orl
andorxorl_test xorl
andorab_test andab
andorab_test orab
lbdsize r0, r1
lbdsize r2, r3
lbdsize.f r0, r1
lbdsize.f r2, r3
bdlen r0, r1, 1
bdlen r1, r3, 256
bdlen r1, r2, 240
bdlen r12, r13
bdlen.f r0, r1, 1
bdlen.f r1, r3, 256
bdlen.f r12, r13
.macro csma_like_test mnem
\mnem\() r10,r12,r20
\mnem\() r0,0x12345678,r20
\mnem\() r6,r7,0xffffffff
\mnem\() r8,0xffffffff,0xffffffff
\mnem\() 0,r14,r13
\mnem\() 0,0xffffffff,r10
\mnem\() 0,r12,0xffffffff
\mnem\() r4,r5,0x1
\mnem\() r3,0x12345678,0x2
\mnem\() 0,r1,0x4
\mnem\() 0,0xffffffff,0x1
.endm
csma_like_test csma
csma_like_test csms
csma_like_test cbba
csma_like_test cbba.f
csma_like_test tr
csma_like_test tr.f
csma_like_test utf8
csma_like_test utf8.f
csma_like_test addf
csma_like_test addf.f
.macro zncv_test mnem
\mnem\() r10,r12,r20
\mnem\() r0,0x12345678,r20
\mnem\() r6,r7,0xffffffff
\mnem\() r8,0xffffffff,0xffffffff
\mnem\() 0,r14,r13
\mnem\() 0,0xffffffff,r10
\mnem\() 0,r12,0xffffffff
\mnem\() r4,r5,0x1
\mnem\() r3,0x12345678,0x2
\mnem\() 0,r1,0x4
\mnem\() 0,0xffffffff,0x1
\mnem\() r1,r1,-1
\mnem\() 0,0xffffffff,-1
.endm
zncv_test zncv.rd
zncv_test zncv.wr
hofs r1, r2, r3
hofs.f r4, r5, r6
hofs r7, r8, 240, 0
hofs.f r7, r8, 0, 1
hash r1, r2, r3, 1, 0, 0, 0
hash r12, r13, r14, 32, 7, 1, 1
.macro hash_p_test mnem
\mnem\() r1, r2, r3, 1, 1, 0, 0
\mnem\() r12, r13, r14, 32, 8, 3, 1
.endm
hash_p_test hash.p0
hash_p_test hash.p1
hash_p_test hash.p2
hash_p_test hash.p3
e4by r0,r1,r2,0,0,0,4
e4by r7,r12,r13,1,2,3,4
e4by r20,r12,r13,7,7,7,7
.macro ldbit_test mnem
\mnem\() r0,[r1]
\mnem\() r0,[r1,1]
\mnem\() r1,[r2,-1]
\mnem\() r3,[0xffffffff,1]
\mnem\() r4,[0x12345678]
\mnem\() r5,[r6,r7]
\mnem\() r8,[r9,0xfeffffff]
\mnem\() r10,[0xffffffff,r11]
.endm
ldbit_test ldbit.di
ldbit_test ldbit.di.cl
ldbit_test ldbit.x2.di
ldbit_test ldbit.x2.di.cl
ldbit_test ldbit.x4.di
ldbit_test ldbit.x4.di.cl
|
tactcomplabs/xbgas-binutils-gdb
| 3,644
|
gas/testsuite/gas/msp430/msp430x.s
|
.text
.global foo
foo:
adc r4 ; MSP430 instruction for comparison purposes.
adcx r4
adcx.a bar
adcx.b r6
adcx.w r7
addcx r8, r9
addcx.a #0x12345, r10
addcx.b r11, r12
addcx.w r13, r14
ADDX @R9, PC
ADDX R9, PC
ADDX.A #FE000h, PC
ADDX.A &EDE, PC
ADDX.A @R9+, PC
ADDX.A EDE, PC
addx.b r1, r2
addx.w r3, r4
ADDX K(R4), R5
ANDX #1234, 4(R6)
ANDX 4(R7), 4(R6)
ANDX @R5+, 4(R6)
ANDX EDE, 4(R6)
ANDX EDE, TONI
ANDX.A @R5, 4(R6)
ANDX.A R5, 4(R6)
ANDX.B &EDE, 4(R6)
andx.w r1, r2
bicx #0xa0, r14
bicx.a #0xa0, r14
bicx.b #0xa0, r14
bicx.w #0xa0, r14
bisx #8, r11
bisx.a #8, r11
bisx.b #8, r11
bisx.w #8, r11
BITX #20, R8
BITX &EDE, &TONI
BITX &EDE, R8
BITX 2(R5), R8
BITX 8(SP), &EDE
BITX @R5+, &EDE
BITX @R5+, R8
BITX @R5, R8
BITX EDE, &TONI
BITX.B #12, &EDE
BITX.B @R5, &EDE
BITX.B EDE, R8
BITX.B R5, R8
BITX.W R5, &EDE
clrx TONI
clrx.a fooz
clrx.b bar
clrx.w baz
cmpx #0, r15
cmpx.a #01800h, ede
cmpx.b @r1, r15
cmpx.w @r2+, &pin
dadcx fooz
dadcx.a 0(r12)
dadcx.b bar
dadcx.w r12
daddx @r5, r7
daddx.a #10h, &decdr
daddx.b 2(r6), r4
daddx.w bcd, r4
decx toni
decx.a fooz
decx.b bar
decx.w fred
decdx toni
decdx.a fooz
decdx.b bar
decdx.w fred
incx r4
incx.a r5
incx.b r6
incx.w r7
incdx r8
incdx.a r9
incdx.b r10
incdx.w r11
invx r12
invx.a LEO
invx.b r14
invx.w r15
movx #foo, r4
movx.a #foo, r5
movx.b #foo, r6
movx.w #foo, r7
MOVX &X, R5
MOVX #X, R5
MOVX R5, &Y
MOVX #0xabcde, &Y
MOVX &X, &Y
MOVX #X, &Y
MOVX X, R5
MOVX R5, Y
MOVX #0xabcde, Y
MOVX X, Y
sbcx r15
sbcx.a 012345h
sbcx.b r15
sbcx.w 0(r7)
subcx r15, r15
subcx.a #012345h, r15
subcx.b r15, r15
subcx.w @r5+, 0(r7)
SUBX 2(R6), PC
SUBX.A #4455, ede
SUBX.B 2(R6), PC
SUBX.W 2(R6), PC
tstx LEO
tstx.a foo
tstx.b bar
tstx.w baz
XORX #5A5Ah, EDE
XORX &EDE, TONI
XORX @R8, EDE
XORX R8, EDE
XORX.B 2(R6), EDE
XORX.B @R8+, EDE
xorx.a toni, &cntr
xorx.w @r5, r6
xorx.a #12345, 0x45678h(r15)
adda #0x12345, r7
adda r6, r14
bra #bar
bra #011044H
bra r5
bra &ede
bra @r5
bra @r5+
bra 0x9876(r5)
calla r5
calla 0x1234(r6)
calla @r7
calla @r8+
calla &foo
calla bar
calla #011004h
clra r6
cmpa r1, r2
cmpa #0xfedcb, r3
decda r5
incda r5
mova R9,R8
MOVA #12345h,R12
MOVA 100h(R9),R8
MOVA &EDE,R12
MOVA @R9,R8
MOVA @R9+,R8
MOVA R8,100h(R9)
MOVA R13,&EDE
reta
reti
suba r5, r6
suba #0xfffff, r6
tsta fooz
popm #1, r5
popm.a #3, r15
popm.w #8, r12
popx r10
popx.a r10
popx.b r10
popx.w r10
pushm #1, r9
pushm.a #2, r9
pushm.w #3, r9
pushx r8
pushx.a r8
pushx.b &ede
pushx.w r8
rlam #1, r15
rlam.a #2, r15
rlam.w #3, r15
rlax r6
rlax.a r6
rlax.w r6
rlcx r6
rlcx.a r6
rlcx.w r6
rram #1, r6
rram.a #4, r6
rram.w #2, r6
rrax r11
rrax.a r11
rrax.w r11
rrcm #4, r5
rrcm.a #1, r5
rrcm.w #3, r5
rrcx r13
rrcx.a r13
rrcx.w r13
rrum #3, r4
rrum.a #2, r4
rrum.w #1, r4
rrux r4
rrux.a r7
rrux.b r5
rrux.w r6
swpbx r1
swpbx.a ede
swpbx.w r12
sxtx r2
sxtx.a &ede
sxtx.w r2
rpt #5
rrax.a r5
rpt r5
rrax.a r5
;; The following are all aliases for similarly named instructions
;; without the period. Eg: add.a -> adda
add.a r1, r2
br.a r1
call.a r1
clr.a r1
cmp.a r1, r2
decd.a r1
incd.a r1
mov.a r1, r2
ret.a
sub.a r1, r2
tst.a fooz
;; Check that repeat counts can be used with shift instructions.
rpt r1 { rrux.w r1
rpt #2 { rrcx.w r2
rpt #3 { rrax.b r7
rpt r4 { rrax.a r4
rpt #5 { rlax.b r5
rpt #6 { rlcx.a r6
|
tactcomplabs/xbgas-binutils-gdb
| 1,279
|
gas/testsuite/gas/msp430/nop-int.s
|
.text
;;; Test some common instruction patterns for disabling/enabling interrupts.
;;; "MOV &FOO,r10" is used as an artbitrary statement which isn't a NOP, to
;;; break up the instructions being tested.
fn1:
;;; 1: Test EINT
;; 430 ISA: NOP *not* required before *or* after EINT
;; 430x ISA: NOP *is* required before *and* after EINT
MOV &FOO,r10
EINT
MOV &FOO,r10
BIS.W #8,SR ; Alias for EINT
MOV &FOO,r10
;;; 2: Test DINT
;; 430 ISA: NOP *is* required after DINT
;; 430x ISA: NOP *is* required after DINT
MOV &FOO,r10
DINT
NOP
MOV &FOO,r10
BIC.W #8,SR ; Alias for DINT
NOP
MOV &FOO,r10
;;; 3: Test EINT immediately before DINT
;; 430 ISA: NOP *not* required.
;; 430x ISA: NOP *is* required between EINT and DINT
MOV &FOO,r10
NOP
EINT
DINT
NOP
MOV &FOO,r10
NOP
BIS.W #8,SR ; Alias for EINT
BIC.W #8,SR ; Alias for DINT
NOP
MOV &FOO,r10
;;; 4: Test DINT immediately before EINT
;; 430 ISA: NOP *is* required after DINT.
;; 430x ISA: NOP *is* required after DINT and before EINT. Ensure only one
;; warning is emitted.
MOV &FOO,r10
NOP
DINT
EINT
NOP
MOV &FOO,r10
BIC.W #8,SR ; Alias for DINT
BIS.W #8,SR ; Alias for EINT
NOP
MOV &FOO,r10
;;; 5: Test EINT last insn in file
NOP
EINT
|
tactcomplabs/xbgas-binutils-gdb
| 20,650
|
gas/testsuite/gas/xstormy16/allinsn.s
|
.data
foodata: .word 42
.text
footext:
.text
.global movlmemimm
movlmemimm:
mov.b 0,#0
mov.w 255,#65535
mov.w 128,#32768
mov.b 127,#32767
mov.w 1,#1
mov.w 81,#64681
mov.w 247,#42230
mov.b 84,#16647
.text
.global movhmemimm
movhmemimm:
mov.b 0x7f00+0,#0
mov.w 0x7f00+255,#65535
mov.w 0x7f00+128,#32768
mov.b 0x7f00+127,#32767
mov.w 0x7f00+1,#1
mov.b 0x7f00+165,#1944
mov.w 0x7f00+186,#11517
mov.b 0x7f00+63,#25556
.text
.global movlgrmem
movlgrmem:
mov.b r0,0
mov.w r7,255
mov.w r4,128
mov.b r3,127
mov.w r1,1
mov.w r6,179
mov.w r0,183
mov.b r3,41
.text
.global movhgrmem
movhgrmem:
mov.b r0,0x7f00+0
mov.w r7,0x7f00+255
mov.w r4,0x7f00+128
mov.b r3,0x7f00+127
mov.w r1,0x7f00+1
mov.b r2,0x7f00+114
mov.w r2,0x7f00+210
mov.w r5,0x7f00+181
.text
.global movlmemgr
movlmemgr:
mov.b 0,r0
mov.w 255,r7
mov.w 128,r4
mov.b 127,r3
mov.w 1,r1
mov.w 137,r0
mov.w 26,r0
mov.b 127,r4
.text
.global movhmemgr
movhmemgr:
mov.b 0x7f00+0,r0
mov.w 0x7f00+255,r7
mov.w 0x7f00+128,r4
mov.b 0x7f00+127,r3
mov.w 0x7f00+1,r1
mov.w 0x7f00+98,r3
mov.w 0x7f00+135,r7
mov.b 0x7f00+229,r2
.text
.global movgrgri
movgrgri:
mov.b r0,(r0)
mov.w r7,(r15)
mov.w r4,(r8)
mov.b r3,(r7)
mov.w r1,(r1)
mov.w r6,(r4)
mov.b r0,(r12)
mov.w r5,(r9)
.text
.global movgrgripostinc
movgrgripostinc:
mov.b r0,(r0++)
mov.w r7,(r15++)
mov.w r4,(r8++)
mov.b r3,(r7++)
mov.w r1,(r1++)
mov.w r4,(r8++)
mov.w r3,(r12++)
mov.b r6,(r4++)
.text
.global movgrgripredec
movgrgripredec:
mov.b r0,(--r0)
mov.w r7,(--r15)
mov.w r4,(--r8)
mov.b r3,(--r7)
mov.w r1,(--r1)
mov.w r5,(--r9)
mov.w r4,(--r14)
mov.b r4,(--r7)
.text
.global movgrigr
movgrigr:
mov.b (r0),r0
mov.w (r15),r7
mov.w (r8),r4
mov.b (r7),r3
mov.w (r1),r1
mov.w (r4),r3
mov.b (r3),r6
mov.w (r7),r0
.text
.global movgripostincgr
movgripostincgr:
mov.b (r0++),r0
mov.w (r15++),r7
mov.w (r8++),r4
mov.b (r7++),r3
mov.w (r1++),r1
mov.w (r12++),r5
mov.b (r4++),r2
mov.b (r11++),r6
.text
.global movgripredecgr
movgripredecgr:
mov.b (--r0),r0
mov.w (--r15),r7
mov.w (--r8),r4
mov.b (--r7),r3
mov.w (--r1),r1
mov.b (--r8),r3
mov.b (--r11),r4
mov.w (--r1),r6
.text
.global movgrgrii
movgrgrii:
mov.b r0,(r0,0)
mov.w r7,(r15,-1)
mov.w r4,(r8,-2048)
mov.b r3,(r7,2047)
mov.w r1,(r1,1)
mov.w r6,(r8,-452)
mov.w r4,(r11,572)
mov.b r1,(r1,-1718)
.text
.global movgrgriipostinc
movgrgriipostinc:
mov.b r0,(r0++,0)
mov.w r7,(r15++,-1)
mov.w r4,(r8++,-2048)
mov.b r3,(r7++,2047)
mov.w r1,(r1++,1)
mov.w r6,(r0++,-64)
mov.b r7,(r15++,1060)
mov.b r0,(r7++,847)
.text
.global movgrgriipredec
movgrgriipredec:
mov.b r0,(--r0,0)
mov.w r7,(--r15,-1)
mov.w r4,(--r8,-2048)
mov.b r3,(--r7,2047)
mov.w r1,(--r1,1)
mov.w r0,(--r15,1780)
mov.w r6,(--r1,1506)
mov.w r7,(--r3,-2033)
.text
.global movgriigr
movgriigr:
mov.b (r0,0),r0
mov.w (r15,-1),r7
mov.w (r8,-2048),r4
mov.b (r7,2047),r3
mov.w (r1,1),r1
mov.w (r7,1948),r5
mov.b (r3,-844),r4
mov.w (r15,1704),r0
.text
.global movgriipostincgr
movgriipostincgr:
mov.b (r0++,0),r0
mov.w (r15++,-1),r7
mov.w (r8++,-2048),r4
mov.b (r7++,2047),r3
mov.w (r1++,1),r1
mov.w (r2++,-176),r7
mov.w (r8++,1389),r4
mov.b (r3++,47),r0
.text
.global movgriipredecgr
movgriipredecgr:
mov.b (--r0,0),r0
mov.w (--r15,-1),r7
mov.w (--r8,-2048),r4
mov.b (--r7,2047),r3
mov.w (--r1,1),r1
mov.b (--r8,1004),r4
mov.w (--r14,-1444),r2
mov.b (--r5,-927),r4
.text
.global movgrgr
movgrgr:
mov r0,r0
mov r15,r15
mov r8,r8
mov r7,r7
mov r1,r1
mov r9,r14
mov r7,r15
mov r12,r15
.text
.global movimm8
movimm8:
mov Rx,#0
mov Rx,#255
mov Rx,#128
mov Rx,#127
mov Rx,#1
mov Rx,#136
mov Rx,#83
mov Rx,#104
.text
.global movwimm8
movwimm8:
mov.w Rx,#0
mov.w Rx,#255
mov.w Rx,#128
mov.w Rx,#127
mov.w Rx,#1
mov.w Rx,#92
mov.w Rx,#97
mov.w Rx,#4
.text
.global movgrimm8
movgrimm8:
mov r0,#0
mov r7,#255
mov r4,#128
mov r3,#127
mov r1,#1
mov r2,#206
mov r4,#55
mov r2,#3
.text
.global movwgrimm8
movwgrimm8:
mov.w r0,#0
mov.w r7,#255
mov.w r4,#128
mov.w r3,#127
mov.w r1,#1
mov.w r4,#243
mov.w r3,#55
mov.w r2,#108
.text
.global movgrimm16
movgrimm16:
mov r0,#0
mov r15,#65535
mov r8,#32768
mov r7,#32767
mov r1,#1
mov r4,#20066
mov r3,#7190
mov r2,#15972
.text
.global movwgrimm16
movwgrimm16:
mov.w r0,#0
mov.w r15,#65535
mov.w r8,#32768
mov.w r7,#32767
mov.w r1,#1
mov.w r6,#16648
mov.w r8,#26865
mov.w r10,#20010
.text
.global movlowgr
movlowgr:
mov.b r0,RxL
mov.b r15,RxL
mov.b r8,RxL
mov.b r7,RxL
mov.b r1,RxL
mov.b r11,RxL
mov.b r5,RxL
mov.b r2,RxL
.text
.global movhighgr
movhighgr:
mov.b r0,RxH
mov.b r15,RxH
mov.b r8,RxH
mov.b r7,RxH
mov.b r1,RxH
mov.b r2,RxH
mov.b r7,RxH
mov.b r2,RxH
.text
.global movfgrgri
movfgrgri:
movf.b r0,(r0)
movf.w r7,(r15)
movf.w r4,(r8)
movf.b r3,(r7)
movf.w r1,(r1)
movf.b r6,(r15)
movf.b r1,(r10)
movf.b r6,(r1)
.text
.global movfgrgripostinc
movfgrgripostinc:
movf.b r0,(r0++)
movf.w r7,(r15++)
movf.w r4,(r8++)
movf.b r3,(r7++)
movf.w r1,(r1++)
movf.b r2,(r5++)
movf.w r5,(r10++)
movf.w r7,(r5++)
.text
.global movfgrgripredec
movfgrgripredec:
movf.b r0,(--r0)
movf.w r7,(--r15)
movf.w r4,(--r8)
movf.b r3,(--r7)
movf.w r1,(--r1)
movf.w r6,(--r10)
movf.b r1,(--r14)
movf.w r3,(--r7)
.text
.global movfgrigr
movfgrigr:
movf.b (r0),r0
movf.w (r15),r7
movf.w (r8),r4
movf.b (r7),r3
movf.w (r1),r1
movf.b (r5),r4
movf.b (r3),r4
movf.w (r12),r3
.text
.global movfgripostincgr
movfgripostincgr:
movf.b (r0++),r0
movf.w (r15++),r7
movf.w (r8++),r4
movf.b (r7++),r3
movf.w (r1++),r1
movf.b (r9++),r5
movf.w (r10++),r4
movf.b (r9++),r1
.text
.global movfgripredecgr
movfgripredecgr:
movf.b (--r0),r0
movf.w (--r15),r7
movf.w (--r8),r4
movf.b (--r7),r3
movf.w (--r1),r1
movf.b (--r0),r2
movf.w (--r11),r2
movf.b (--r10),r5
.text
.global movfgrgrii
movfgrgrii:
movf.b r0,(r8,r0,0)
movf.w r7,(r15,r15,-1)
movf.w r4,(r12,r8,-2048)
movf.b r3,(r11,r7,2047)
movf.w r1,(r9,r1,1)
movf.b r7,(r15,r0,1473)
movf.w r2,(r8,r9,-1522)
movf.w r2,(r13,r1,480)
.text
.global movfgrgriipostinc
movfgrgriipostinc:
movf.b r0,(r8,r0++,0)
movf.w r7,(r15,r15++,-1)
movf.w r4,(r12,r8++,-2048)
movf.b r3,(r11,r7++,2047)
movf.w r1,(r9,r1++,1)
movf.b r1,(r8,r2++,1398)
movf.w r4,(r8,r9++,-778)
movf.w r1,(r13,r14++,1564)
.text
.global movfgrgriipredec
movfgrgriipredec:
movf.b r0,(r8,--r0,0)
movf.w r7,(r15,--r15,-1)
movf.w r4,(r12,--r8,-2048)
movf.b r3,(r11,--r7,2047)
movf.w r1,(r9,--r1,1)
movf.b r6,(r8,--r7,254)
movf.w r5,(r12,--r12,1673)
movf.b r0,(r8,--r10,-38)
.text
.global movfgriigr
movfgriigr:
movf.b (r8,r0,0),r0
movf.w (r15,r15,-1),r7
movf.w (r12,r8,-2048),r4
movf.b (r11,r7,2047),r3
movf.w (r9,r1,1),r1
movf.w (r15,r2,-1636),r3
movf.w (r14,r12,1626),r1
movf.b (r11,r14,1540),r0
.text
.global movfgriipostincgr
movfgriipostincgr:
movf.b (r8,r0++,0),r0
movf.w (r15,r15++,-1),r7
movf.w (r12,r8++,-2048),r4
movf.b (r11,r7++,2047),r3
movf.w (r9,r1++,1),r1
movf.b (r15,r13++,466),r3
movf.b (r11,r11++,250),r4
movf.b (r10,r10++,-1480),r7
.text
.global movfgriipredecgr
movfgriipredecgr:
movf.b (r8,--r0,0),r0
movf.w (r15,--r15,-1),r7
movf.w (r12,--r8,-2048),r4
movf.b (r11,--r7,2047),r3
movf.w (r9,--r1,1),r1
movf.b (r13,--r10,-608),r0
movf.b (r9,--r11,831),r7
movf.w (r15,--r15,-2036),r6
.text
.global maskgrgr
maskgrgr:
mask r0,r0
mask r15,r15
mask r8,r8
mask r7,r7
mask r1,r1
mask r4,r0
mask r6,r11
mask r8,r4
.text
.global maskgrimm16
maskgrimm16:
mask r0,#0
mask r15,#65535
mask r8,#32768
mask r7,#32767
mask r1,#1
mask r7,#18153
mask r15,#7524
mask r14,#34349
.text
.global pushgr
pushgr:
push r0
push r15
push r8
push r7
push r1
push r9
push r4
push r3
.text
.global popgr
popgr:
pop r0
pop r15
pop r8
pop r7
pop r1
pop r3
pop r2
pop r12
.text
.global swpn
swpn:
swpn r0
swpn r15
swpn r8
swpn r7
swpn r1
swpn r15
swpn r4
swpn r3
.text
.global swpb
swpb:
swpb r0
swpb r15
swpb r8
swpb r7
swpb r1
swpb r2
swpb r12
swpb r2
.text
.global swpw
swpw:
swpw r0,r0
swpw r15,r15
swpw r8,r8
swpw r7,r7
swpw r1,r1
swpw r12,r4
swpw r8,r2
swpw r5,r13
.text
.global andgrgr
andgrgr:
and r0,r0
and r15,r15
and r8,r8
and r7,r7
and r1,r1
and r2,r2
and r15,r5
and r7,r5
.text
.global andimm8
andimm8:
and Rx,#0
and Rx,#255
and Rx,#128
and Rx,#127
and Rx,#1
and Rx,#206
and Rx,#11
and Rx,#232
.text
.global andgrimm16
andgrimm16:
and r0,#0
and r15,#65535
and r8,#32768
and r7,#32767
and r1,#1
and r10,#17229
and r11,#61451
and r5,#46925
.text
.global orgrgr
orgrgr:
or r0,r0
or r15,r15
or r8,r8
or r7,r7
or r1,r1
or r3,r5
or r14,r15
or r5,r12
.text
.global orimm8
orimm8:
or Rx,#0
or Rx,#255
or Rx,#128
or Rx,#127
or Rx,#1
or Rx,#4
or Rx,#38
or Rx,#52
.text
.global orgrimm16
orgrimm16:
or r0,#0
or r15,#65535
or r8,#32768
or r7,#32767
or r1,#1
or r2,#64563
or r2,#18395
or r1,#63059
.text
.global xorgrgr
xorgrgr:
xor r0,r0
xor r15,r15
xor r8,r8
xor r7,r7
xor r1,r1
xor r14,r1
xor r9,r9
xor r12,r8
.text
.global xorimm8
xorimm8:
xor Rx,#0
xor Rx,#255
xor Rx,#128
xor Rx,#127
xor Rx,#1
xor Rx,#208
xor Rx,#126
xor Rx,#55
.text
.global xorgrimm16
xorgrimm16:
xor r0,#0
xor r15,#65535
xor r8,#32768
xor r7,#32767
xor r1,#1
xor r15,#56437
xor r3,#901
xor r2,#37017
.text
.global notgr
notgr:
not r0
not r15
not r8
not r7
not r1
not r4
not r3
not r3
.text
.global addgrgr
addgrgr:
add r0,r0
add r15,r15
add r8,r8
add r7,r7
add r1,r1
add r12,r7
add r1,r10
add r14,r14
.text
.global addgrimm4
addgrimm4:
add r0,#0
add r15,#15
add r8,#8
add r7,#7
add r1,#1
add r7,#0
add r10,#9
add r7,#8
.text
.global addimm8
addimm8:
add Rx,#0
add Rx,#255
add Rx,#128
add Rx,#127
add Rx,#1
add Rx,#25
add Rx,#247
add Rx,#221
.text
.global addgrimm16
addgrimm16:
add r0,#0
add r15,#255
add r8,#128
add r7,#127
add r1,#1
add r3,#99
add r0,#15
add r7,#214
.text
.global adcgrgr
adcgrgr:
adc r0,r0
adc r15,r15
adc r8,r8
adc r7,r7
adc r1,r1
adc r2,r13
adc r14,r10
adc r2,r15
.text
.global adcgrimm4
adcgrimm4:
adc r0,#0
adc r15,#15
adc r8,#8
adc r7,#7
adc r1,#1
adc r15,#1
adc r1,#3
adc r6,#11
.text
.global adcimm8
adcimm8:
adc Rx,#0
adc Rx,#255
adc Rx,#128
adc Rx,#127
adc Rx,#1
adc Rx,#225
adc Rx,#75
adc Rx,#18
.text
.global adcgrimm16
adcgrimm16:
adc r0,#0
adc r15,#65535
adc r8,#32768
adc r7,#32767
adc r1,#1
adc r13,#63129
adc r3,#23795
adc r11,#49245
.text
.global subgrgr
subgrgr:
sub r0,r0
sub r15,r15
sub r8,r8
sub r7,r7
sub r1,r1
sub r8,r8
sub r9,r9
sub r9,r15
.text
.global subgrimm4
subgrimm4:
sub r0,#0
sub r15,#15
sub r8,#8
sub r7,#7
sub r1,#1
sub r2,#15
sub r12,#9
sub r8,#4
.text
.global subimm8
subimm8:
sub Rx,#0
sub Rx,#255
sub Rx,#128
sub Rx,#127
sub Rx,#1
sub Rx,#205
sub Rx,#153
sub Rx,#217
.text
.global subgrimm16
subgrimm16:
sub r0,#0
sub r15,#65535
sub r8,#32768
sub r7,#32767
sub r1,#1
sub r3,#51895
sub r11,#23617
sub r10,#7754
.text
.global sbcgrgr
sbcgrgr:
sbc r0,r0
sbc r15,r15
sbc r8,r8
sbc r7,r7
sbc r1,r1
sbc r11,r2
sbc r9,r1
sbc r4,r15
.text
.global sbcgrimm4
sbcgrimm4:
sbc r0,#0
sbc r15,#15
sbc r8,#8
sbc r7,#7
sbc r1,#1
sbc r10,#11
sbc r11,#10
sbc r13,#10
.text
.global sbcgrimm8
sbcgrimm8:
sbc Rx,#0
sbc Rx,#255
sbc Rx,#128
sbc Rx,#127
sbc Rx,#1
sbc Rx,#137
sbc Rx,#224
sbc Rx,#156
.text
.global sbcgrimm16
sbcgrimm16:
sbc r0,#0
sbc r15,#65535
sbc r8,#32768
sbc r7,#32767
sbc r1,#1
sbc r0,#32507
sbc r7,#8610
sbc r14,#20373
.text
.global incgr
incgr:
inc r0
inc r15
inc r8
inc r7
inc r1
inc r13
inc r1
inc r11
.text
.global incgrimm2
incgrimm2:
inc r0,#0
inc r15,#3
inc r8,#2
inc r7,#1
inc r1,#1
inc r14,#1
inc r5,#0
inc r12,#3
.text
.global decgr
decgr:
dec r0
dec r15
dec r8
dec r7
dec r1
dec r12
dec r8
dec r10
.text
.global decgrimm2
decgrimm2:
dec r0,#0
dec r15,#3
dec r8,#2
dec r7,#1
dec r1,#1
dec r5,#0
dec r13,#0
dec r13,#2
.text
.global rrcgrgr
rrcgrgr:
rrc r0,r0
rrc r15,r15
rrc r8,r8
rrc r7,r7
rrc r1,r1
rrc r8,r4
rrc r10,r14
rrc r15,r9
.text
.global rrcgrimm4
rrcgrimm4:
rrc r0,#0
rrc r15,#15
rrc r8,#8
rrc r7,#7
rrc r1,#1
rrc r11,#3
rrc r14,#12
rrc r2,#15
.text
.global rlcgrgr
rlcgrgr:
rlc r0,r0
rlc r15,r15
rlc r8,r8
rlc r7,r7
rlc r1,r1
rlc r15,r3
rlc r15,r7
rlc r15,r10
.text
.global rlcgrimm4
rlcgrimm4:
rlc r0,#0
rlc r15,#15
rlc r8,#8
rlc r7,#7
rlc r1,#1
rlc r8,#2
rlc r2,#6
rlc r6,#10
.text
.global shrgrgr
shrgrgr:
shr r0,r0
shr r15,r15
shr r8,r8
shr r7,r7
shr r1,r1
shr r13,r2
shr r7,r8
shr r6,r8
.text
.global shrgrimm
shrgrimm:
shr r0,#0
shr r15,#15
shr r8,#8
shr r7,#7
shr r1,#1
shr r9,#13
shr r2,#7
shr r8,#8
.text
.global shlgrgr
shlgrgr:
shl r0,r0
shl r15,r15
shl r8,r8
shl r7,r7
shl r1,r1
shl r2,r3
shl r0,r3
shl r2,r1
.text
.global shlgrimm
shlgrimm:
shl r0,#0
shl r15,#15
shl r8,#8
shl r7,#7
shl r1,#1
shl r6,#13
shl r3,#6
shl r15,#15
.text
.global asrgrgr
asrgrgr:
asr r0,r0
asr r15,r15
asr r8,r8
asr r7,r7
asr r1,r1
asr r5,r10
asr r3,r5
asr r6,r11
.text
.global asrgrimm
asrgrimm:
asr r0,#0
asr r15,#15
asr r8,#8
asr r7,#7
asr r1,#1
asr r13,#4
asr r0,#13
asr r6,#3
.text
.global set1grimm
set1grimm:
set1 r0,#0
set1 r15,#15
set1 r8,#8
set1 r7,#7
set1 r1,#1
set1 r6,#10
set1 r13,#1
set1 r13,#15
.text
.global set1grgr
set1grgr:
set1 r0,r0
set1 r15,r15
set1 r8,r8
set1 r7,r7
set1 r1,r1
set1 r6,r0
set1 r6,r7
set1 r14,r2
.text
.global set1lmemimm
set1lmemimm:
set1 0,#0
set1 255,#7
set1 128,#4
set1 127,#3
set1 1,#1
set1 244,#3
set1 55,#7
set1 252,#5
.text
.global set1hmemimm
set1hmemimm:
set1 0x7f00+0,#0
set1 0x7f00+255,#7
set1 0x7f00+128,#4
set1 0x7f00+127,#3
set1 0x7f00+1,#1
set1 0x7f00+10,#3
set1 0x7f00+99,#4
set1 0x7f00+148,#3
.text
.global clr1grimm
clr1grimm:
clr1 r0,#0
clr1 r15,#15
clr1 r8,#8
clr1 r7,#7
clr1 r1,#1
clr1 r12,#0
clr1 r8,#11
clr1 r7,#7
.text
.global clr1grgr
clr1grgr:
clr1 r0,r0
clr1 r15,r15
clr1 r8,r8
clr1 r7,r7
clr1 r1,r1
clr1 r3,r3
clr1 r0,r1
clr1 r15,r0
.text
.global clr1lmemimm
clr1lmemimm:
clr1 0,#0
clr1 255,#7
clr1 128,#4
clr1 127,#3
clr1 1,#1
clr1 114,#7
clr1 229,#4
clr1 86,#1
.text
.global clr1hmemimm
clr1hmemimm:
clr1 0x7f00+0,#0
clr1 0x7f00+255,#7
clr1 0x7f00+128,#4
clr1 0x7f00+127,#3
clr1 0x7f00+1,#1
clr1 0x7f00+44,#3
clr1 0x7f00+212,#5
clr1 0x7f00+67,#7
.text
.global cbwgr
cbwgr:
cbw r0
cbw r15
cbw r8
cbw r7
cbw r1
cbw r8
cbw r11
cbw r3
.text
.global revgr
revgr:
rev r0
rev r15
rev r8
rev r7
rev r1
rev r1
rev r1
rev r14
.text
.global bgr
bgr:
br r0
br r15
br r8
br r7
br r1
br r0
br r15
br r12
.text
.global jmp
jmp:
jmp r8,r0
jmp r9,r15
jmp r9,r8
jmp r8,r7
jmp r9,r1
jmp r9,r7
jmp r9,r5
jmp r8,r12
.text
.global jmpf
jmpf:
jmpf 0
jmpf 16777215
jmpf 8388608
jmpf 8388607
jmpf 1
jmpf 10731629
jmpf 15094866
jmpf 1464024
.text
.global callrgr
callrgr:
callr r0
callr r15
callr r8
callr r7
callr r1
callr r1
callr r12
callr r8
.text
.global callgr
callgr:
call r8,r0
call r9,r15
call r9,r8
call r8,r7
call r9,r1
call r9,r6
call r9,r14
call r8,r12
.text
.global callfimm
callfimm:
callf 0
callf 16777215
callf 8388608
callf 8388607
callf 1
callf 13546070
callf 10837983
callf 15197875
.text
.global icallrgr
icallrgr:
icallr r0
icallr r15
icallr r8
icallr r7
icallr r1
icallr r15
icallr r12
icallr r9
.text
.global icallgr
icallgr:
icall r8,r0
icall r9,r15
icall r9,r8
icall r8,r7
icall r9,r1
icall r9,r10
icall r8,r15
icall r8,r10
.text
.global icallfimm
icallfimm:
icallf 0
icallf 16777215
icallf 8388608
icallf 8388607
icallf 1
icallf 9649954
icallf 1979758
icallf 7661640
.text
.global iret
iret:
iret
.text
.global ret
ret:
ret
.text
.global mul
mul:
mul
.text
.global div
div:
div
.text
.global sdiv
sdiv:
sdiv
.text
.global divlh
divlh:
divlh
.text
.global sdivlh
sdivlh:
sdivlh
.text
.global nop
nop:
nop
ret
.text
.global halt
halt:
halt
.text
.global hold
hold:
hold
.text
.global holdx
holdx:
holdx
.text
.global brk
brk:
brk
.text
.global bccgrgr
bccgrgr:
bge r0,r0,0+(.+4)
bz r15,r15,-1+(.+4)
bpl r8,r8,-2048+(.+4)
bls r7,r7,2047+(.+4)
bnc r1,r1,1+(.+4)
bc r3,r13,1799+(.+4)
bge r1,r10,-2019+(.+4)
bz r0,r5,-1132+(.+4)
.text
.global bccgrimm8
bccgrimm8:
bge r0,#0,0+(.+4)
bz r7,#255,-1+(.+4)
bpl r4,#128,-2048+(.+4)
bls r3,#127,2047+(.+4)
bnc r1,#1,1+(.+4)
bnc r3,#8,1473+(.+4)
bnz.b r5,#203,1619+(.+4)
bc r7,#225,978+(.+4)
.text
.global bccimm16
bccimm16:
bge Rx,#0,0+(.+4)
bz Rx,#65535,-1+(.+4)
bpl Rx,#32768,-128+(.+4)
bls Rx,#32767,127+(.+4)
bnc Rx,#1,1+(.+4)
bz.b Rx,#30715,4+(.+4)
bnv Rx,#62266,-13+(.+4)
bnv Rx,#48178,108+(.+4)
.text
.global bngrimm4
bngrimm4:
bn r0,#0,0+(.+4)
bn r15,#15,-1+(.+4)
bn r8,#8,-2048+(.+4)
bn r7,#7,2047+(.+4)
bn r1,#1,1+(.+4)
bn r11,#3,-1975+(.+4)
bn r15,#4,-1205+(.+4)
bn r10,#8,1691+(.+4)
.text
.global bngrgr
bngrgr:
bn r0,r0,0+(.+4)
bn r15,r15,-1+(.+4)
bn r8,r8,-2048+(.+4)
bn r7,r7,2047+(.+4)
bn r1,r1,1+(.+4)
bn r4,r3,1181+(.+4)
bn r5,r2,77+(.+4)
bn r3,r7,631+(.+4)
.text
.global bnlmemimm
bnlmemimm:
bn 0,#0,0+(.+4)
bn 255,#7,-1+(.+4)
bn 128,#4,-2048+(.+4)
bn 127,#3,2047+(.+4)
bn 1,#1,1+(.+4)
bn 153,#7,-847+(.+4)
bn 204,#0,-1881+(.+4)
bn 242,#7,1396+(.+4)
.text
.global bnhmemimm
bnhmemimm:
bn 0x7f00+0,#0,0+(.+4)
bn 0x7f00+255,#7,-1+(.+4)
bn 0x7f00+128,#4,-2048+(.+4)
bn 0x7f00+127,#3,2047+(.+4)
bn 0x7f00+1,#1,1+(.+4)
bn 0x7f00+185,#3,-614+(.+4)
bn 0x7f00+105,#1,-668+(.+4)
bn 0x7f00+79,#7,1312+(.+4)
.text
.global bpgrimm4
bpgrimm4:
bp r0,#0,0+(.+4)
bp r15,#15,-1+(.+4)
bp r8,#8,-2048+(.+4)
bp r7,#7,2047+(.+4)
bp r1,#1,1+(.+4)
bp r0,#12,1075+(.+4)
bp r1,#5,551+(.+4)
bp r6,#8,1588+(.+4)
.text
.global bpgrgr
bpgrgr:
bp r0,r0,0+(.+4)
bp r15,r15,-1+(.+4)
bp r8,r8,-2048+(.+4)
bp r7,r7,2047+(.+4)
bp r1,r1,1+(.+4)
bp r4,r9,-614+(.+4)
bp r9,r10,-1360+(.+4)
bp r4,r1,407+(.+4)
.text
.global bplmemimm
bplmemimm:
bp 0,#0,0+(.+4)
bp 255,#7,-1+(.+4)
bp 128,#4,-2048+(.+4)
bp 127,#3,2047+(.+4)
bp 1,#1,1+(.+4)
bp 193,#3,-398+(.+4)
bp 250,#2,-1553+(.+4)
bp 180,#6,579+(.+4)
.text
.global bphmemimm
bphmemimm:
bp 0x7f00+0,#0,0+(.+4)
bp 0x7f00+255,#7,-1+(.+4)
bp 0x7f00+128,#4,-2048+(.+4)
bp 0x7f00+127,#3,2047+(.+4)
bp 0x7f00+1,#1,1+(.+4)
bp 0x7f00+195,#1,-432+(.+4)
bp 0x7f00+129,#5,-1508+(.+4)
bp 0x7f00+56,#3,1723+(.+4)
.text
.global bcc
bcc:
bge 0+(.+2)
bz -1+(.+2)
bpl -128+(.+2)
bls 127+(.+2)
bnc 1+(.+2)
bnz.b 48+(.+2)
bnc -7+(.+2)
bnz.b 74+(.+2)
.text
.global br
br:
br 0+(.+2)
br -2+(.+2)
br -2048+(.+2)
br 2046+(.+2)
br 1+(.+2)
br 1472+(.+2)
br 1618+(.+2)
br 978+(.+2)
.text
.global callrimm
callrimm:
callr 0+(.+2)
callr -2+(.+2)
callr -2048+(.+2)
callr 2046+(.+2)
callr 1+(.+2)
callr 1472+(.+2)
callr 1618+(.+2)
callr 978+(.+2)
movgrgrsi:
mov.b r0,(r0,extsym)
mov.w r7,(r15,extsym-1)
mov.w r4,(r8,extsym-2048)
mov.b r3,(r7,extsym+2047)
mov.w r1,(r1,extsym+1)
mov.w r6,(r8,extsym-452)
mov.w r4,(r11,extsym+572)
mov.b r1,(r1,extsym-1718)
.text
.global movgrgriipostinc
movgrgrsipostinc:
mov.b r0,(r0++,extsym)
mov.w r7,(r15++,extsym-1)
mov.w r4,(r8++,extsym-2048)
mov.b r3,(r7++,extsym+2047)
mov.w r1,(r1++,extsym+1)
mov.w r6,(r0++,extsym-64)
mov.b r7,(r15++,extsym+1060)
mov.b r0,(r7++,extsym+847)
.text
.global movgrgriipredec
movgrgrsipredec:
mov.b r0,(--r0,extsym)
mov.w r7,(--r15,extsym-1)
mov.w r4,(--r8,extsym-2048)
mov.b r3,(--r7,extsym+2047)
mov.w r1,(--r1,extsym+1)
mov.w r0,(--r15,extsym+1780)
mov.w r6,(--r1,extsym+1506)
mov.w r7,(--r3,extsym-2033)
.text
.global movgriigr
movgrsigr:
mov.b (r0,extsym),r0
mov.w (r15,extsym-1),r7
mov.w (r8,extsym-2048),r4
mov.b (r7,extsym+2047),r3
mov.w (r1,extsym+1),r1
mov.w (r7,extsym+1948),r5
mov.b (r3,extsym-844),r4
mov.w (r15,extsym+1704),r0
.text
.global movgriipostincgr
movgrsipostincgr:
mov.b (r0++,extsym),r0
mov.w (r15++,extsym-1),r7
mov.w (r8++,extsym-2048),r4
mov.b (r7++,extsym+2047),r3
mov.w (r1++,extsym+1),r1
mov.w (r2++,extsym-176),r7
mov.w (r8++,extsym+1389),r4
mov.b (r3++,extsym+47),r0
.text
.global movgriipredecgr
movgrsipredecgr:
mov.b (--r0,extsym),r0
mov.w (--r15,extsym-1),r7
mov.w (--r8,extsym-2048),r4
mov.b (--r7,extsym+2047),r3
mov.w (--r1,extsym+1),r1
mov.b (--r8,extsym+1004),r4
mov.w (--r14,extsym-1444),r2
mov.b (--r5,extsym-927),r4
|
tactcomplabs/xbgas-binutils-gdb
| 2,145
|
gas/testsuite/gas/wasm32/allinsn.s
|
block[]
br 0
br_if 0
br_table 1 1 1
call 0
call_indirect 0 0
drop
else
end
f32.abs
f32.add
f32.ceil
f32.const 3.14159
f32.convert_s/i32
f32.convert_s/i64
f32.convert_u/i32
f32.convert_u/i64
f32.copysign
f32.demote/f64
f32.div
f32.eq
f32.floor
f32.ge
f32.gt
f32.le
f32.load a=0 0
f32.lt
f32.max
f32.min
f32.mul
f32.ne
f32.nearest
f32.neg
f32.reinterpret/i32
f32.sqrt
f32.store a=0 0
f32.sub
f32.trunc
f64.abs
f64.add
f64.ceil
f64.const 3.14159e200
f64.convert_s/i32
f64.convert_s/i64
f64.convert_u/i32
f64.convert_u/i64
f64.copysign
f64.div
f64.eq
f64.floor
f64.ge
f64.gt
f64.le
f64.load a=0 0
f64.lt
f64.max
f64.min
f64.mul
f64.ne
f64.nearest
f64.neg
f64.promote/f32
f64.reinterpret/i64
f64.sqrt
f64.store a=0 0
f64.sub
f64.trunc
get_global 0
get_local 0
i32.add
i32.and
i32.clz
i32.const 0xdeadbeef
i32.ctz
i32.div_s
i32.div_u
i32.eq
i32.eqz
i32.ge_s
i32.ge_u
i32.gt_s
i32.gt_u
i32.le_s
i32.le_u
i32.load a=0 0
i32.load16_s a=0 0
i32.load16_u a=0 0
i32.load8_s a=0 0
i32.load8_u a=0 0
i32.lt_s
i32.lt_u
i32.mul
i32.ne
i32.or
i32.popcnt
i32.reinterpret/f32
i32.rem_s
i32.rem_u
i32.rotl
i32.rotr
i32.shl
i32.shr_s
i32.shr_u
i32.store a=0 0
i32.store16 a=0 0
i32.store8 a=0 0
i32.sub
i32.trunc_s/f32
i32.trunc_s/f64
i32.trunc_u/f32
i32.trunc_u/f64
i32.wrap/i64
i32.xor
i64.add
i64.and
i64.clz
i64.const 0xdeadbeefdeadbeef
i64.ctz
i64.div_s
i64.div_u
i64.eq
i64.eqz
i64.extend_s/i32
i64.extend_u/i32
i64.ge_s
i64.ge_u
i64.gt_s
i64.gt_u
i64.le_s
i64.le_u
i64.load a=0 0
i64.load16_s a=0 0
i64.load16_u a=0 0
i64.load32_s a=0 0
i64.load32_u a=0 0
i64.load8_s a=0 0
i64.load8_u a=0 0
i64.lt_s
i64.lt_u
i64.mul
i64.ne
i64.or
i64.popcnt
i64.reinterpret/f64
i64.rem_s
i64.rem_u
i64.rotl
i64.rotr
i64.shl
i64.shr_s
i64.shr_u
i64.store a=0 0
i64.store16 a=0 0
i64.store32 a=0 0
i64.store8 a=0 0
i64.sub
i64.trunc_s/f32
i64.trunc_s/f64
i64.trunc_u/f32
i64.trunc_u/f64
i64.xor
if[i]
loop[l]
nop
return
select
set_global 0
set_local 0
signature FvildffdliE
tee_local 0
unreachable
|
tactcomplabs/xbgas-binutils-gdb
| 1,247
|
gas/testsuite/gas/hppa/reloc/reduce2.s
|
.SPACE $PRIVATE$
.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31
.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82
.SPACE $TEXT$
.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44
.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY
.IMPORT $global$,DATA
.IMPORT $$dyncall,MILLICODE
; gcc_compiled.:
.SPACE $TEXT$
.SUBSPA $LIT$
.align 8
L$P0000
.word 0x12345678
.word 0x0
.align 8
L$C0000
.word 0x3ff00000
.word 0x0
.SPACE $TEXT$
.SUBSPA $CODE$
.align 4
.EXPORT g,ENTRY,PRIV_LEV=3,RTNVAL=FR
g
.PROC
.CALLINFO FRAME=0,NO_CALLS
.ENTRY
stw %r19,-32(%r30)
ldw T'L$C0000(%r19),%r20
bv %r0(%r2)
fldds 0(%r20),%fr4
.EXIT
.PROCEND
.IMPORT abort,CODE
.IMPORT exit,CODE
.SPACE $TEXT$
.SUBSPA $LIT$
.align 8
L$C0001
.word 0x3ff00000
.word 0x0
.SPACE $TEXT$
.SUBSPA $CODE$
.align 4
.EXPORT main,ENTRY,PRIV_LEV=3,RTNVAL=GR
main
.PROC
.CALLINFO FRAME=128,CALLS,SAVE_RP,ENTRY_GR=3
.ENTRY
stw %r2,-20(%r30)
ldo 128(%r30),%r30
stw %r19,-32(%r30)
stw %r4,-128(%r30)
copy %r19,%r4
.CALL
bl g,%r2
copy %r4,%r19
copy %r4,%r19
ldw T'L$C0001(%r19),%r20
fldds 0(%r20),%fr8
fcmp,dbl,= %fr4,%fr8
ftest
add,tr %r0,%r0,%r0
b,n L$0003
.CALL
bl abort,%r2
nop
L$0003
.CALL ARGW0=GR
bl exit,%r2
ldi 0,%r26
nop
.EXIT
.PROCEND
|
tactcomplabs/xbgas-binutils-gdb
| 2,882
|
gas/testsuite/gas/hppa/reloc/funcrelocbug.s
|
.code
.align 4
.EXPORT g,CODE
.EXPORT g,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,ARGW2=GR,RTNVAL=GR
g:
.PROC
.CALLINFO FRAME=128,CALLS,SAVE_RP,SAVE_SP,ENTRY_GR=3
.ENTRY
stw %r2,-20(%r30)
copy %r3,%r1
copy %r30,%r3
stwm %r1,128(%r30)
stw %r26,-36(%r3)
stw %r25,-40(%r3)
stw %r24,-44(%r3)
ldw -36(%r3),%r26
ldw -40(%r3),%r25
ldw -44(%r3),%r19
copy %r19,%r22
.CALL ARGW0=GR
bl $$dyncall,%r31
copy %r31,%r2
copy %r28,%r19
comiclr,<> 0,%r19,%r0
bl,n L$0002,%r0
ldw -36(%r3),%r28
bl,n L$0001,%r0
bl,n L$0003,%r0
L$0002:
ldw -40(%r3),%r28
bl,n L$0001,%r0
L$0003:
L$0001:
ldw -20(%r3),%r2
ldo 64(%r3),%r30
ldwm -64(%r30),%r3
bv,n %r0(%r2)
.EXIT
.PROCEND
.align 4
f2___4:
.PROC
.CALLINFO FRAME=64,NO_CALLS,SAVE_SP,ENTRY_GR=3
.ENTRY
copy %r3,%r1
copy %r30,%r3
stwm %r1,64(%r30)
stw %r29,8(%r3)
stw %r26,-36(%r3)
stw %r25,-40(%r3)
ldw -36(%r3),%r19
ldw -40(%r3),%r20
comclr,>= %r20,%r19,%r19
ldi 1,%r19
copy %r19,%r28
bl,n L$0005,%r0
L$0005:
ldo 64(%r3),%r30
ldwm -64(%r30),%r3
bv,n %r0(%r2)
.EXIT
.PROCEND
.IMPORT abort,CODE
.data
.align 4
L$TRAMP0000:
ldw 36(%r22),%r21
bb,>=,n %r21,30,.+16
depi 0,31,2,%r21
ldw 4(%r21),%r19
ldw 0(%r21),%r21
ldsid (%r21),%r1
mtsp %r1,%sr0
be 0(%sr0,%r21)
ldw 40(%r22),%r29
.word 0
.word 0
.code
.align 4
.EXPORT f,CODE
.EXPORT f,ENTRY,PRIV_LEV=3,RTNVAL=GR
f:
.PROC
.CALLINFO FRAME=192,CALLS,SAVE_RP,SAVE_SP,ENTRY_GR=3
.ENTRY
stw %r2,-20(%r30)
copy %r3,%r1
copy %r30,%r3
stwm %r1,192(%r30)
ldo 16(%r3),%r19
addil L'L$TRAMP0000-$global$,%r27
ldo R'L$TRAMP0000-$global$(%r1),%r22
ldo 40(%r0),%r20
ldws,ma 4(%r22),%r21
addib,>= -4,%r20,.-4
stws,ma %r21,4(%r19)
ldil L'f2___4,%r20
ldo R'f2___4(%r20),%r19
stw %r19,52(%r3)
ldo 8(%r3),%r19
stw %r19,56(%r3)
ldo 16(%r3),%r19
ldo 48(%r3),%r20
fdc %r0(%r19)
fdc %r0(%r20)
sync
ldo 32(%r19),%r22
mfsp %sr0,%r21
ldsid (%r19),%r20
mtsp %r20,%sr0
fic %r0(%sr0,%r19)
fic %r0(%sr0,%r22)
sync
mtsp %r21,%sr0
nop
nop
nop
nop
nop
nop
ldo 16(%r3),%r19
ldi 1,%r26
ldi 2,%r25
copy %r19,%r24
.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO
bl g,%r2
nop
copy %r28,%r19
comiclr,<> 2,%r19,%r0
bl,n L$0006,%r0
.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO
bl abort,%r2
nop
L$0006:
L$0004:
ldw -20(%r3),%r2
ldo 64(%r3),%r30
ldwm -64(%r30),%r3
bv,n %r0(%r2)
.EXIT
.PROCEND
.IMPORT __main,CODE
.IMPORT exit,CODE
.align 4
.EXPORT main,CODE
.EXPORT main,ENTRY,PRIV_LEV=3,RTNVAL=GR
main:
.PROC
.CALLINFO FRAME=128,CALLS,SAVE_RP,SAVE_SP,ENTRY_GR=3
.ENTRY
stw %r2,-20(%r30)
copy %r3,%r1
copy %r30,%r3
stwm %r1,128(%r30)
.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO
bl __main,%r2
nop
.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO
bl f,%r2
nop
copy %r0,%r26
.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO
bl exit,%r2
nop
L$0007:
ldw -20(%r3),%r2
ldo 64(%r3),%r30
ldwm -64(%r30),%r3
bv,n %r0(%r2)
.EXIT
.PROCEND
|
tactcomplabs/xbgas-binutils-gdb
| 2,026
|
gas/testsuite/gas/hppa/reloc/applybug.s
|
.IMPORT $global$,DATA
.IMPORT $$dyncall,MILLICODE
; gcc_compiled.:
.data
.align 4
tab___2:
.word L$0002
.word L$0003
.word L$0004
.code
.align 4
.EXPORT execute,CODE
.EXPORT execute,ENTRY,PRIV_LEV=3,ARGW0=GR,RTNVAL=GR
execute:
.PROC
.CALLINFO FRAME=0,NO_CALLS
.ENTRY
addil L'buf-$global$,%r27
ldo R'buf-$global$(%r1),%r20
ldil L'L$0002,%r19
movb,<> %r26,%r26,L$0002
ldo R'L$0002(%r19),%r22
copy %r0,%r21
addil L'tab___2-$global$,%r27
ldo R'tab___2-$global$(%r1),%r23
addil L'optab-$global$,%r27
ldo R'optab-$global$(%r1),%r20
L$0009:
sh2add %r21,%r23,%r19
ldh 2(%r19),%r19
ldo 1(%r21),%r21
sub %r19,%r22,%r19
comib,>= 2,%r21,L$0009
sths,ma %r19,2(%r20)
bv,n %r0(%r2)
L$0002:
ldi 120,%r19
stbs,ma %r19,1(%r20)
ldhs,ma 2(%r26),%r19
add %r22,%r19,%r19
bv,n %r0(%r19)
L$0003:
ldi 121,%r19
stbs,ma %r19,1(%r20)
ldhs,ma 2(%r26),%r19
add %r22,%r19,%r19
bv,n %r0(%r19)
L$0004:
ldi 122,%r19
stb %r19,0(%r20)
bv %r0(%r2)
stbs,mb %r0,1(%r20)
.EXIT
.PROCEND
.IMPORT __main,CODE
.IMPORT strcmp,CODE
.align 4
L$C0000:
.STRING "xyxyz\x00"
.IMPORT abort,CODE
.IMPORT exit,CODE
.code
.align 4
.EXPORT main,CODE
.EXPORT main,ENTRY,PRIV_LEV=3,RTNVAL=GR
main:
.PROC
.CALLINFO FRAME=128,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(%r30)
.CALL
bl __main,%r2
ldo 128(%r30),%r30
.CALL ARGW0=GR
bl execute,%r2
copy %r0,%r26
addil L'optab-$global$,%r27
copy %r1,%r19
ldo R'optab-$global$(%r19),%r21
ldh 2(%r21),%r20
ldh R'optab-$global$(%r19),%r19
addil L'p-$global$,%r27
copy %r1,%r22
sth %r20,R'p-$global$(%r22)
ldo R'p-$global$(%r22),%r26
sth %r20,4(%r26)
sth %r19,2(%r26)
ldh 4(%r21),%r19
.CALL ARGW0=GR
bl execute,%r2
sth %r19,6(%r26)
addil L'buf-$global$,%r27
copy %r1,%r19
ldo R'buf-$global$(%r19),%r26
ldil L'L$C0000,%r25
.CALL ARGW0=GR,ARGW1=GR
bl strcmp,%r2
ldo R'L$C0000(%r25),%r25
comib,=,n 0,%r28,L$0011
.CALL
bl abort,%r2
nop
L$0011:
.CALL ARGW0=GR
bl exit,%r2
copy %r0,%r26
nop
.EXIT
.PROCEND
.data
optab: .comm 10
buf: .comm 10
p: .comm 10
|
tactcomplabs/xbgas-binutils-gdb
| 106,210
|
gas/testsuite/gas/hppa/unsorted/brlenbug.s
|
.IMPORT $global$,DATA
.IMPORT $$dyncall,MILLICODE
; gcc_compiled.:
.data
.align 4
done___2
.word 0
.IMPORT memset,CODE
.EXPORT re_syntax_options,DATA
.align 4
re_syntax_options
.word 0
.align 4
re_error_msg
.word 0
.word L$C0000
.word L$C0001
.word L$C0002
.word L$C0003
.word L$C0004
.word L$C0005
.word L$C0006
.word L$C0007
.word L$C0008
.word L$C0009
.word L$C0010
.word L$C0011
.word L$C0012
.word L$C0013
.word L$C0014
.word L$C0015
.code
.align 4
L$C0015
.STRING "Unmatched ) or \\)\x00"
.align 4
L$C0014
.STRING "Regular expression too big\x00"
.align 4
L$C0013
.STRING "Premature end of regular expression\x00"
.align 4
L$C0012
.STRING "Invalid preceding regular expression\x00"
.align 4
L$C0011
.STRING "Memory exhausted\x00"
.align 4
L$C0010
.STRING "Invalid range end\x00"
.align 4
L$C0009
.STRING "Invalid content of \\{\\}\x00"
.align 4
L$C0008
.STRING "Unmatched \\{\x00"
.align 4
L$C0007
.STRING "Unmatched ( or \\(\x00"
.align 4
L$C0006
.STRING "Unmatched [ or [^\x00"
.align 4
L$C0005
.STRING "Invalid back reference\x00"
.align 4
L$C0004
.STRING "Trailing backslash\x00"
.align 4
L$C0003
.STRING "Invalid character class name\x00"
.align 4
L$C0002
.STRING "Invalid collation character\x00"
.align 4
L$C0001
.STRING "Invalid regular expression\x00"
.align 4
L$C0000
.STRING "No match\x00"
.EXPORT re_max_failures,DATA
.data
.align 4
re_max_failures
.word 2000
.IMPORT malloc,CODE
.IMPORT realloc,CODE
.IMPORT free,CODE
.IMPORT strcmp,CODE
.code
.align 4
L$C0016
.STRING "alnum\x00"
.align 4
L$C0017
.STRING "alpha\x00"
.align 4
L$C0018
.STRING "blank\x00"
.align 4
L$C0019
.STRING "cntrl\x00"
.align 4
L$C0020
.STRING "digit\x00"
.align 4
L$C0021
.STRING "graph\x00"
.align 4
L$C0022
.STRING "lower\x00"
.align 4
L$C0023
.STRING "print\x00"
.align 4
L$C0024
.STRING "punct\x00"
.align 4
L$C0025
.STRING "space\x00"
.align 4
L$C0026
.STRING "upper\x00"
.align 4
L$C0027
.STRING "xdigit\x00"
.IMPORT __alnum,DATA
.IMPORT __ctype2,DATA
.IMPORT __ctype,DATA
.IMPORT at_begline_loc_p,CODE
.IMPORT at_endline_loc_p,CODE
.IMPORT store_op1,CODE
.IMPORT insert_op1,CODE
.IMPORT store_op2,CODE
.IMPORT insert_op2,CODE
.IMPORT compile_range,CODE
.IMPORT group_in_compile_stack,CODE
.code
.align 4
regex_compile
.PROC
.CALLINFO FRAME=320,CALLS,SAVE_RP,ENTRY_GR=18
.ENTRY
stw %r2,-20(%r30) ;# 8989 reload_outsi+2/6
ldo 320(%r30),%r30 ;# 8991 addsi3/2
stw %r18,-168(%r30) ;# 8993 reload_outsi+2/6
stw %r17,-164(%r30) ;# 8995 reload_outsi+2/6
stw %r16,-160(%r30) ;# 8997 reload_outsi+2/6
stw %r15,-156(%r30) ;# 8999 reload_outsi+2/6
stw %r14,-152(%r30) ;# 9001 reload_outsi+2/6
stw %r13,-148(%r30) ;# 9003 reload_outsi+2/6
stw %r12,-144(%r30) ;# 9005 reload_outsi+2/6
stw %r11,-140(%r30) ;# 9007 reload_outsi+2/6
stw %r10,-136(%r30) ;# 9009 reload_outsi+2/6
stw %r9,-132(%r30) ;# 9011 reload_outsi+2/6
stw %r8,-128(%r30) ;# 9013 reload_outsi+2/6
stw %r7,-124(%r30) ;# 9015 reload_outsi+2/6
stw %r6,-120(%r30) ;# 9017 reload_outsi+2/6
stw %r5,-116(%r30) ;# 9019 reload_outsi+2/6
stw %r4,-112(%r30) ;# 9021 reload_outsi+2/6
stw %r3,-108(%r30) ;# 9023 reload_outsi+2/6
stw %r26,-276(%r30) ;# 4 reload_outsi+2/6
ldi 0,%r9 ;# 25 reload_outsi+2/2
ldi 0,%r8 ;# 28 reload_outsi+2/2
stw %r0,-260(%r30) ;# 34 reload_outsi+2/6
ldi 0,%r10 ;# 31 reload_outsi+2/2
ldi 640,%r26 ;# 37 reload_outsi+2/2
ldw -276(%r30),%r1 ;# 8774 reload_outsi+2/5
copy %r24,%r15 ;# 8 reload_outsi+2/1
stw %r1,-296(%r30) ;# 2325 reload_outsi+2/6
copy %r23,%r5 ;# 10 reload_outsi+2/1
addl %r1,%r25,%r16 ;# 19 addsi3/1
.CALL ARGW0=GR
bl malloc,%r2 ;# 39 call_value_internal_symref
ldw 20(%r5),%r14 ;# 22 reload_outsi+2/5
comib,<> 0,%r28,L$0021 ;# 48 bleu+1
stw %r28,-312(%r30) ;# 43 reload_outsi+2/6
L$0953
bl L$0867,%r0 ;# 53 jump
ldi 12,%r28 ;# 51 reload_outsi+2/2
L$0021
ldi 32,%r19 ;# 58 reload_outsi+2/2
stw %r19,-308(%r30) ;# 59 reload_outsi+2/6
stw %r0,-304(%r30) ;# 62 reload_outsi+2/6
stw %r15,12(%r5) ;# 65 reload_outsi+2/6
stw %r0,8(%r5) ;# 85 reload_outsi+2/6
stw %r0,24(%r5) ;# 88 reload_outsi+2/6
addil LR'done___2-$global$,%r27 ;# 92 pic2_lo_sum+1
ldw 28(%r5),%r19 ;# 68 reload_outsi+2/5
ldw RR'done___2-$global$(%r1),%r20 ;# 94 reload_outsi+2/5
depi 0,3,1,%r19 ;# 69 andsi3/2
depi 0,6,2,%r19 ;# 80 andsi3/2
comib,<> 0,%r20,L$0022 ;# 95 bleu+1
stw %r19,28(%r5) ;# 82 reload_outsi+2/6
addil LR're_syntax_table-$global$,%r27 ;# 99 pic2_lo_sum+1
ldo RR're_syntax_table-$global$(%r1),%r4 ;# 100 movhi-2
copy %r4,%r26 ;# 101 reload_outsi+2/1
ldi 0,%r25 ;# 102 reload_outsi+2/2
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl memset,%r2 ;# 104 call_value_internal_symref
ldi 256,%r24 ;# 103 reload_outsi+2/2
ldi 1,%r20 ;# 8732 movqi+1/2
ldo 97(%r4),%r19 ;# 8736 addsi3/2
ldo 122(%r4),%r4 ;# 8738 addsi3/2
stbs,ma %r20,1(%r19) ;# 115 movqi+1/6
L$1155
comb,>=,n %r4,%r19,L$1155 ;# 121 bleu+1
stbs,ma %r20,1(%r19) ;# 115 movqi+1/6
ldi 1,%r21 ;# 8717 movqi+1/2
addil LR're_syntax_table-$global$,%r27 ;# 8712 pic2_lo_sum+1
ldo RR're_syntax_table-$global$(%r1),%r19 ;# 8715 movhi-2
ldo 65(%r19),%r20 ;# 8721 addsi3/2
ldo 90(%r19),%r19 ;# 8723 addsi3/2
stbs,ma %r21,1(%r20) ;# 138 movqi+1/6
L$1156
comb,>=,n %r19,%r20,L$1156 ;# 144 bleu+1
stbs,ma %r21,1(%r20) ;# 138 movqi+1/6
ldi 48,%r20 ;# 151 reload_outsi+2/2
ldi 57,%r22 ;# 7976 reload_outsi+2/2
ldi 1,%r21 ;# 8707 movqi+1/2
addil LR're_syntax_table-$global$+48,%r27 ;# 8705 pic2_lo_sum+1
ldo RR're_syntax_table-$global$+48(%r1),%r19 ;# 8711 movhi-2
L$0037
ldo 1(%r20),%r20 ;# 164 addsi3/2
comb,>= %r22,%r20,L$0037 ;# 167 bleu+1
stbs,ma %r21,1(%r19) ;# 161 movqi+1/6
addil LR're_syntax_table-$global$,%r27 ;# 174 pic2_lo_sum+1
ldo RR're_syntax_table-$global$(%r1),%r19 ;# 175 movhi-2
ldi 1,%r20 ;# 176 movqi+1/2
stb %r20,95(%r19) ;# 177 movqi+1/6
addil LR'done___2-$global$,%r27 ;# 178 pic2_lo_sum+1
ldi 1,%r19 ;# 180 reload_outsi+2/2
stw %r19,RR'done___2-$global$(%r1) ;# 181 reload_outsi+2/6
L$0022
ldw 4(%r5),%r19 ;# 187 reload_outsi+2/5
comib,<>,n 0,%r19,L$0039 ;# 189 bleu+1
ldw 0(%r5),%r26 ;# 193 reload_outsi+2/5
comib,=,n 0,%r26,L$0040 ;# 195 bleu+1
.CALL ARGW0=GR,ARGW1=GR
bl realloc,%r2 ;# 205 call_value_internal_symref
ldi 32,%r25 ;# 203 reload_outsi+2/2
bl L$1157,%r0 ;# 211 jump
stw %r28,0(%r5) ;# 223 reload_outsi+2/6
L$0040
.CALL ARGW0=GR
bl malloc,%r2 ;# 219 call_value_internal_symref
ldi 32,%r26 ;# 217 reload_outsi+2/2
stw %r28,0(%r5) ;# 223 reload_outsi+2/6
L$1157
ldw 0(%r5),%r19 ;# 228 reload_outsi+2/5
comib,<> 0,%r19,L$0042 ;# 230 bleu+1
ldi 32,%r19 ;# 243 reload_outsi+2/2
.CALL ARGW0=GR
bl free,%r2 ;# 234 call_internal_symref
ldw -312(%r30),%r26 ;# 232 reload_outsi+2/5
bl L$0867,%r0 ;# 238 jump
ldi 12,%r28 ;# 51 reload_outsi+2/2
L$0042
stw %r19,4(%r5) ;# 244 reload_outsi+2/6
L$0039
ldw 0(%r5),%r6 ;# 249 reload_outsi+2/5
ldw -296(%r30),%r19 ;# 7981 reload_outsi+2/5
comclr,<> %r16,%r19,%r0 ;# 7982 bleu+1
bl L$0044,%r0
copy %r6,%r12 ;# 253 reload_outsi+2/1
ldw -296(%r30),%r19 ;# 2334 reload_outsi+2/5
L$1178
ldbs,ma 1(%r19),%r7 ;# 277 zero_extendqisi2/2
comib,= 0,%r14,L$0047 ;# 282 bleu+1
stw %r19,-296(%r30) ;# 2337 reload_outsi+2/6
addl %r14,%r7,%r19 ;# 283 addsi3/1
ldb 0(%r19),%r7 ;# 286 zero_extendqisi2/2
L$0047
ldo -10(%r7),%r19 ;# 7895 addsi3/2
addi,uv -115,%r19,%r0 ;# 7896 casesi0
blr,n %r19,%r0
b,n L$0076
L$0863
bl L$0376,%r0
nop ;# 9092 switch_jump
L$0954
bl L$0076,%r0
nop ;# 9095 switch_jump
L$0955
bl L$0076,%r0
nop ;# 9098 switch_jump
L$0956
bl L$0076,%r0
nop ;# 9101 switch_jump
L$0957
bl L$0076,%r0
nop ;# 9104 switch_jump
L$0958
bl L$0076,%r0
nop ;# 9107 switch_jump
L$0959
bl L$0076,%r0
nop ;# 9110 switch_jump
L$0960
bl L$0076,%r0
nop ;# 9113 switch_jump
L$0961
bl L$0076,%r0
nop ;# 9116 switch_jump
L$0962
bl L$0076,%r0
nop ;# 9119 switch_jump
L$0963
bl L$0076,%r0
nop ;# 9122 switch_jump
L$0964
bl L$0076,%r0
nop ;# 9125 switch_jump
L$0965
bl L$0076,%r0
nop ;# 9128 switch_jump
L$0966
bl L$0076,%r0
nop ;# 9131 switch_jump
L$0967
bl L$0076,%r0
nop ;# 9134 switch_jump
L$0968
bl L$0076,%r0
nop ;# 9137 switch_jump
L$0969
bl L$0076,%r0
nop ;# 9140 switch_jump
L$0970
bl L$0076,%r0
nop ;# 9143 switch_jump
L$0971
bl L$0076,%r0
nop ;# 9146 switch_jump
L$0972
bl L$0076,%r0
nop ;# 9149 switch_jump
L$0973
bl L$0076,%r0
nop ;# 9152 switch_jump
L$0974
bl L$0076,%r0
nop ;# 9155 switch_jump
L$0975
bl L$0076,%r0
nop ;# 9158 switch_jump
L$0976
bl L$0076,%r0
nop ;# 9161 switch_jump
L$0977
bl L$0076,%r0
nop ;# 9164 switch_jump
L$0978
bl L$0076,%r0
nop ;# 9167 switch_jump
L$0979
bl L$0077,%r0 ;# 9170 switch_jump
ldw -296(%r30),%r26 ;# 2349 reload_outsi+2/5
L$0980
bl L$0076,%r0
nop ;# 9173 switch_jump
L$0981
bl L$0076,%r0
nop ;# 9176 switch_jump
L$0982
bl L$0076,%r0
nop ;# 9179 switch_jump
L$0983
bl L$0368,%r0
nop ;# 9182 switch_jump
L$0984
bl L$0372,%r0
nop ;# 9185 switch_jump
L$0985
bl L$0104,%r0
nop ;# 9188 switch_jump
L$0986
bl L$1158,%r0 ;# 9191 switch_jump
ldi 1026,%r19 ;# 662 reload_outsi+2/2
L$0987
bl L$0076,%r0
nop ;# 9194 switch_jump
L$0988
bl L$0076,%r0
nop ;# 9197 switch_jump
L$0989
bl L$0196,%r0 ;# 9200 switch_jump
ldw 0(%r5),%r4 ;# 8027 reload_outsi+2/5
L$0990
bl L$0076,%r0
nop ;# 9203 switch_jump
L$0991
bl L$0076,%r0
nop ;# 9206 switch_jump
L$0992
bl L$0076,%r0
nop ;# 9209 switch_jump
L$0993
bl L$0076,%r0
nop ;# 9212 switch_jump
L$0994
bl L$0076,%r0
nop ;# 9215 switch_jump
L$0995
bl L$0076,%r0
nop ;# 9218 switch_jump
L$0996
bl L$0076,%r0
nop ;# 9221 switch_jump
L$0997
bl L$0076,%r0
nop ;# 9224 switch_jump
L$0998
bl L$0076,%r0
nop ;# 9227 switch_jump
L$0999
bl L$0076,%r0
nop ;# 9230 switch_jump
L$1000
bl L$0076,%r0
nop ;# 9233 switch_jump
L$1001
bl L$0076,%r0
nop ;# 9236 switch_jump
L$1002
bl L$0076,%r0
nop ;# 9239 switch_jump
L$1003
bl L$0076,%r0
nop ;# 9242 switch_jump
L$1004
bl L$0076,%r0
nop ;# 9245 switch_jump
L$1005
bl L$0076,%r0
nop ;# 9248 switch_jump
L$1006
bl L$0101,%r0 ;# 9251 switch_jump
ldi 1026,%r19 ;# 662 reload_outsi+2/2
L$1007
bl L$0076,%r0
nop ;# 9254 switch_jump
L$1008
bl L$0076,%r0
nop ;# 9257 switch_jump
L$1009
bl L$0076,%r0
nop ;# 9260 switch_jump
L$1010
bl L$0076,%r0
nop ;# 9263 switch_jump
L$1011
bl L$0076,%r0
nop ;# 9266 switch_jump
L$1012
bl L$0076,%r0
nop ;# 9269 switch_jump
L$1013
bl L$0076,%r0
nop ;# 9272 switch_jump
L$1014
bl L$0076,%r0
nop ;# 9275 switch_jump
L$1015
bl L$0076,%r0
nop ;# 9278 switch_jump
L$1016
bl L$0076,%r0
nop ;# 9281 switch_jump
L$1017
bl L$0076,%r0
nop ;# 9284 switch_jump
L$1018
bl L$0076,%r0
nop ;# 9287 switch_jump
L$1019
bl L$0076,%r0
nop ;# 9290 switch_jump
L$1020
bl L$0076,%r0
nop ;# 9293 switch_jump
L$1021
bl L$0076,%r0
nop ;# 9296 switch_jump
L$1022
bl L$0076,%r0
nop ;# 9299 switch_jump
L$1023
bl L$0076,%r0
nop ;# 9302 switch_jump
L$1024
bl L$0076,%r0
nop ;# 9305 switch_jump
L$1025
bl L$0076,%r0
nop ;# 9308 switch_jump
L$1026
bl L$0076,%r0
nop ;# 9311 switch_jump
L$1027
bl L$0076,%r0
nop ;# 9314 switch_jump
L$1028
bl L$0076,%r0
nop ;# 9317 switch_jump
L$1029
bl L$0076,%r0
nop ;# 9320 switch_jump
L$1030
bl L$0076,%r0
nop ;# 9323 switch_jump
L$1031
bl L$0076,%r0
nop ;# 9326 switch_jump
L$1032
bl L$0076,%r0
nop ;# 9329 switch_jump
L$1033
bl L$0076,%r0
nop ;# 9332 switch_jump
L$1034
bl L$0216,%r0 ;# 9335 switch_jump
ldw -296(%r30),%r19 ;# 2418 reload_outsi+2/5
L$1035
bl L$0387,%r0 ;# 9338 switch_jump
ldw -296(%r30),%r19 ;# 3797 reload_outsi+2/5
L$1036
bl L$0076,%r0
nop ;# 9341 switch_jump
L$1037
bl L$0053,%r0 ;# 9344 switch_jump
ldw -276(%r30),%r1 ;# 8777 reload_outsi+2/5
L$1038
bl L$0076,%r0
nop ;# 9347 switch_jump
L$1039
bl L$0076,%r0
nop ;# 9350 switch_jump
L$1040
bl L$0076,%r0
nop ;# 9353 switch_jump
L$1041
bl L$0076,%r0
nop ;# 9356 switch_jump
L$1042
bl L$0076,%r0
nop ;# 9359 switch_jump
L$1043
bl L$0076,%r0
nop ;# 9362 switch_jump
L$1044
bl L$0076,%r0
nop ;# 9365 switch_jump
L$1045
bl L$0076,%r0
nop ;# 9368 switch_jump
L$1046
bl L$0076,%r0
nop ;# 9371 switch_jump
L$1047
bl L$0076,%r0
nop ;# 9374 switch_jump
L$1048
bl L$0076,%r0
nop ;# 9377 switch_jump
L$1049
bl L$0076,%r0
nop ;# 9380 switch_jump
L$1050
bl L$0076,%r0
nop ;# 9383 switch_jump
L$1051
bl L$0076,%r0
nop ;# 9386 switch_jump
L$1052
bl L$0076,%r0
nop ;# 9389 switch_jump
L$1053
bl L$0076,%r0
nop ;# 9392 switch_jump
L$1054
bl L$0076,%r0
nop ;# 9395 switch_jump
L$1055
bl L$0076,%r0
nop ;# 9398 switch_jump
L$1056
bl L$0076,%r0
nop ;# 9401 switch_jump
L$1057
bl L$0076,%r0
nop ;# 9404 switch_jump
L$1058
bl L$0076,%r0
nop ;# 9407 switch_jump
L$1059
bl L$0076,%r0
nop ;# 9410 switch_jump
L$1060
bl L$0076,%r0
nop ;# 9413 switch_jump
L$1061
bl L$0076,%r0
nop ;# 9416 switch_jump
L$1062
bl L$0076,%r0
nop ;# 9419 switch_jump
L$1063
bl L$0076,%r0
nop ;# 9422 switch_jump
L$1064
bl L$0076,%r0
nop ;# 9425 switch_jump
L$1065
bl L$0076,%r0
nop ;# 9428 switch_jump
L$1066
bl L$0383,%r0 ;# 9431 switch_jump
ldi 4608,%r20 ;# 3778 reload_outsi+2/2
L$1067
bl L$0380,%r0
nop ;# 9434 switch_jump
L$1068
bl,n L$0076,%r0 ;# 7899 jump
L$0053
ldw -296(%r30),%r25 ;# 2343 reload_outsi+2/5
ldo 1(%r1),%r19 ;# 306 addsi3/2
comb,=,n %r19,%r25,L$0055 ;# 308 bleu+1
bb,< %r15,28,L$0055 ;# 313 bleu+3
ldw -276(%r30),%r26 ;# 315 reload_outsi+2/5
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl at_begline_loc_p,%r2 ;# 321 call_value_internal_symref
copy %r15,%r24 ;# 319 reload_outsi+2/1
extrs %r28,31,8,%r28 ;# 324 extendqisi2
comiclr,<> 0,%r28,%r0 ;# 326 bleu+1
bl,n L$0076,%r0
L$0055
ldw 0(%r5),%r4 ;# 7986 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 7989 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 7987 subsi3/1
ldo 1(%r19),%r19 ;# 7988 addsi3/2
comb,>>=,n %r20,%r19,L$0060 ;# 7990 bleu+1
ldil L'65536,%r3 ;# 8701 reload_outsi+2/3
L$0061
comclr,<> %r3,%r20,%r0 ;# 357 bleu+1
bl L$0944,%r0
zdep %r20,30,31,%r19 ;# 367 ashlsi3+1
comb,>>= %r3,%r19,L$0066 ;# 375 bleu+1
stw %r19,4(%r5) ;# 369 reload_outsi+2/6
stw %r3,4(%r5) ;# 378 reload_outsi+2/6
L$0066
ldw 0(%r5),%r26 ;# 385 reload_outsi+2/5
.CALL ARGW0=GR,ARGW1=GR
bl realloc,%r2 ;# 389 call_value_internal_symref
ldw 4(%r5),%r25 ;# 387 reload_outsi+2/5
comib,= 0,%r28,L$0953 ;# 397 bleu+1
stw %r28,0(%r5) ;# 393 reload_outsi+2/6
comb,= %r28,%r4,L$0059 ;# 407 bleu+1
sub %r6,%r4,%r19 ;# 409 subsi3/1
addl %r28,%r19,%r6 ;# 412 addsi3/1
sub %r12,%r4,%r19 ;# 413 subsi3/1
comib,= 0,%r10,L$0069 ;# 418 bleu+1
addl %r28,%r19,%r12 ;# 416 addsi3/1
sub %r10,%r4,%r19 ;# 419 subsi3/1
addl %r28,%r19,%r10 ;# 422 addsi3/1
L$0069
comib,= 0,%r8,L$0070 ;# 425 bleu+1
sub %r8,%r4,%r19 ;# 426 subsi3/1
addl %r28,%r19,%r8 ;# 429 addsi3/1
L$0070
comib,= 0,%r9,L$0059 ;# 432 bleu+1
sub %r9,%r4,%r19 ;# 433 subsi3/1
addl %r28,%r19,%r9 ;# 436 addsi3/1
L$0059
ldw 0(%r5),%r4 ;# 337 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 341 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 338 subsi3/1
ldo 1(%r19),%r19 ;# 339 addsi3/2
comb,<< %r20,%r19,L$0061
nop ;# 343 bleu+1
L$0060
ldi 8,%r19 ;# 458 movqi+1/2
bl L$0043,%r0 ;# 479 jump
stbs,ma %r19,1(%r6) ;# 459 movqi+1/6
L$0077
comb,=,n %r16,%r26,L$0079 ;# 485 bleu+1
bb,< %r15,28,L$0079 ;# 490 bleu+3
copy %r16,%r25 ;# 494 reload_outsi+2/1
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl at_endline_loc_p,%r2 ;# 498 call_value_internal_symref
copy %r15,%r24 ;# 496 reload_outsi+2/1
extrs %r28,31,8,%r28 ;# 501 extendqisi2
comiclr,<> 0,%r28,%r0 ;# 503 bleu+1
bl,n L$0076,%r0
L$0079
ldw 0(%r5),%r4 ;# 7994 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 7997 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 7995 subsi3/1
ldo 1(%r19),%r19 ;# 7996 addsi3/2
comb,>>=,n %r20,%r19,L$0084 ;# 7998 bleu+1
ldil L'65536,%r3 ;# 8699 reload_outsi+2/3
L$0085
comclr,<> %r3,%r20,%r0 ;# 534 bleu+1
bl L$0944,%r0
zdep %r20,30,31,%r19 ;# 544 ashlsi3+1
comb,>>= %r3,%r19,L$0090 ;# 552 bleu+1
stw %r19,4(%r5) ;# 546 reload_outsi+2/6
stw %r3,4(%r5) ;# 555 reload_outsi+2/6
L$0090
ldw 0(%r5),%r26 ;# 562 reload_outsi+2/5
.CALL ARGW0=GR,ARGW1=GR
bl realloc,%r2 ;# 566 call_value_internal_symref
ldw 4(%r5),%r25 ;# 564 reload_outsi+2/5
comib,= 0,%r28,L$0953 ;# 574 bleu+1
stw %r28,0(%r5) ;# 570 reload_outsi+2/6
comb,= %r28,%r4,L$0083 ;# 584 bleu+1
sub %r6,%r4,%r19 ;# 586 subsi3/1
addl %r28,%r19,%r6 ;# 589 addsi3/1
sub %r12,%r4,%r19 ;# 590 subsi3/1
comib,= 0,%r10,L$0093 ;# 595 bleu+1
addl %r28,%r19,%r12 ;# 593 addsi3/1
sub %r10,%r4,%r19 ;# 596 subsi3/1
addl %r28,%r19,%r10 ;# 599 addsi3/1
L$0093
comib,= 0,%r8,L$0094 ;# 602 bleu+1
sub %r8,%r4,%r19 ;# 603 subsi3/1
addl %r28,%r19,%r8 ;# 606 addsi3/1
L$0094
comib,= 0,%r9,L$0083 ;# 609 bleu+1
sub %r9,%r4,%r19 ;# 610 subsi3/1
addl %r28,%r19,%r9 ;# 613 addsi3/1
L$0083
ldw 0(%r5),%r4 ;# 514 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 518 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 515 subsi3/1
ldo 1(%r19),%r19 ;# 516 addsi3/2
comb,<< %r20,%r19,L$0085
nop ;# 520 bleu+1
L$0084
ldi 9,%r19 ;# 635 movqi+1/2
bl L$0043,%r0 ;# 656 jump
stbs,ma %r19,1(%r6) ;# 636 movqi+1/6
L$0877
bl L$0110,%r0 ;# 897 jump
stw %r21,-296(%r30) ;# 2391 reload_outsi+2/6
L$0101
L$1158
and %r15,%r19,%r19 ;# 663 andsi3/1
comiclr,= 0,%r19,%r0 ;# 665 bleu+1
bl,n L$0076,%r0
L$0104
comib,<> 0,%r8,L$0105 ;# 674 bleu+1
ldi 0,%r13 ;# 711 reload_outsi+2/2
extrs,>= %r15,26,1,%r0 ;# 681 bleu+3
extrs,< %r15,27,1,%r0 ;# 700 movsi-4
nop
bl,n L$0076,%r0
L$0105
ldi 0,%r11 ;# 714 reload_outsi+2/2
ldi 0,%r22 ;# 716 reload_outsi+2/2
ldi 43,%r24 ;# 8688 reload_outsi+2/2
ldi 63,%r23 ;# 8690 reload_outsi+2/2
ldi 42,%r28 ;# 8692 reload_outsi+2/2
ldi 2,%r19 ;# 8694 reload_outsi+2/2
and %r15,%r19,%r25 ;# 8695 andsi3/1
ldi 92,%r26 ;# 8697 reload_outsi+2/2
L$0109
comb,= %r24,%r7,L$0112 ;# 727 bleu+1
copy %r11,%r19 ;# 8780 reload_outsi+2/1
depi -1,31,1,%r19 ;# 729 iorsi3+1/2
bl L$0113,%r0 ;# 731 jump
extrs %r19,31,8,%r19 ;# 730 extendqisi2
L$0112
extrs %r11,31,8,%r19 ;# 734 extendqisi2
L$0113
L$1159
comb,= %r23,%r7,L$0114 ;# 744 bleu+1
copy %r19,%r11 ;# 737 reload_outsi+2/1
copy %r22,%r19 ;# 8783 reload_outsi+2/1
depi -1,31,1,%r19 ;# 746 iorsi3+1/2
bl L$0115,%r0 ;# 748 jump
extrs %r19,31,8,%r19 ;# 747 extendqisi2
L$0114
extrs %r22,31,8,%r19 ;# 751 extendqisi2
L$0115
ldw -296(%r30),%r21 ;# 2355 reload_outsi+2/5
comb,= %r16,%r21,L$0110 ;# 757 bleu+1
copy %r19,%r22 ;# 754 reload_outsi+2/1
copy %r21,%r20 ;# 8743 reload_outsi+2/1
ldbs,ma 1(%r20),%r7 ;# 776 zero_extendqisi2/2
comib,= 0,%r14,L$0118 ;# 781 bleu+1
stw %r20,-296(%r30) ;# 2364 reload_outsi+2/6
addl %r14,%r7,%r19 ;# 782 addsi3/1
ldb 0(%r19),%r7 ;# 785 zero_extendqisi2/2
L$0118
comb,= %r28,%r7,L$0109
nop ;# 802 bleu+1
comib,<>,n 0,%r25,L$0869 ;# 807 bleu+1
comb,= %r24,%r7,L$1159 ;# 811 bleu+1
extrs %r11,31,8,%r19 ;# 734 extendqisi2
comb,= %r23,%r7,L$0109 ;# 815 bleu+1
ldw -296(%r30),%r19 ;# 2400 reload_outsi+2/5
bl,n L$1160,%r0 ;# 827 jump
L$0869
comb,<> %r26,%r7,L$0126 ;# 831 bleu+1
ldw -296(%r30),%r19 ;# 2400 reload_outsi+2/5
comclr,<> %r16,%r20,%r0 ;# 835 bleu+1
bl L$0903,%r0
ldo 1(%r20),%r19 ;# 863 addsi3/2
ldb 1(%r21),%r3 ;# 860 zero_extendqisi2/2
comib,= 0,%r14,L$0129 ;# 865 bleu+1
stw %r19,-296(%r30) ;# 2379 reload_outsi+2/6
addl %r14,%r3,%r19 ;# 866 addsi3/1
ldb 0(%r19),%r3 ;# 869 zero_extendqisi2/2
L$0129
comb,= %r24,%r3,L$0109 ;# 886 bleu+1
copy %r3,%r7 ;# 903 reload_outsi+2/1
comb,<> %r23,%r3,L$0877
nop ;# 890 bleu+1
bl,n L$0109,%r0 ;# 905 jump
L$0126
L$1160
ldo -1(%r19),%r19 ;# 910 addsi3/2
stw %r19,-296(%r30) ;# 2397 reload_outsi+2/6
L$0110
comiclr,<> 0,%r8,%r0 ;# 927 bleu+1
bl L$1161,%r0
ldw -296(%r30),%r19 ;# 2328 reload_outsi+2/5
comib,=,n 0,%r22,L$0137 ;# 934 bleu+1
ldw 0(%r5),%r3 ;# 8002 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 8005 reload_outsi+2/5
sub %r6,%r3,%r19 ;# 8003 subsi3/1
ldo 3(%r19),%r19 ;# 8004 addsi3/2
comb,>>=,n %r20,%r19,L$0139 ;# 8006 bleu+1
ldil L'65536,%r4 ;# 8686 reload_outsi+2/3
L$0140
comclr,<> %r4,%r20,%r0 ;# 961 bleu+1
bl L$0944,%r0
zdep %r20,30,31,%r19 ;# 971 ashlsi3+1
comb,>>= %r4,%r19,L$0145 ;# 979 bleu+1
stw %r19,4(%r5) ;# 973 reload_outsi+2/6
stw %r4,4(%r5) ;# 982 reload_outsi+2/6
L$0145
ldw 0(%r5),%r26 ;# 989 reload_outsi+2/5
.CALL ARGW0=GR,ARGW1=GR
bl realloc,%r2 ;# 993 call_value_internal_symref
ldw 4(%r5),%r25 ;# 991 reload_outsi+2/5
comib,= 0,%r28,L$0953 ;# 1001 bleu+1
stw %r28,0(%r5) ;# 997 reload_outsi+2/6
comb,= %r28,%r3,L$0138 ;# 1011 bleu+1
sub %r6,%r3,%r19 ;# 1013 subsi3/1
addl %r28,%r19,%r6 ;# 1016 addsi3/1
sub %r12,%r3,%r19 ;# 1017 subsi3/1
comib,= 0,%r10,L$0148 ;# 1022 bleu+1
addl %r28,%r19,%r12 ;# 1020 addsi3/1
sub %r10,%r3,%r19 ;# 1023 subsi3/1
addl %r28,%r19,%r10 ;# 1026 addsi3/1
L$0148
comib,= 0,%r8,L$0149 ;# 1029 bleu+1
sub %r8,%r3,%r19 ;# 1030 subsi3/1
addl %r28,%r19,%r8 ;# 1033 addsi3/1
L$0149
comib,= 0,%r9,L$0138 ;# 1036 bleu+1
sub %r9,%r3,%r19 ;# 1037 subsi3/1
addl %r28,%r19,%r9 ;# 1040 addsi3/1
L$0138
ldw 0(%r5),%r3 ;# 941 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 945 reload_outsi+2/5
sub %r6,%r3,%r19 ;# 942 subsi3/1
ldo 3(%r19),%r19 ;# 943 addsi3/2
comb,<< %r20,%r19,L$0140
nop ;# 947 bleu+1
L$0139
comib,= 0,%r14,L$0154 ;# 1063 bleu+1
ldw -296(%r30),%r19 ;# 2403 reload_outsi+2/5
ldb -2(%r19),%r19 ;# 1066 zero_extendqisi2/2
addl %r14,%r19,%r19 ;# 1067 addsi3/1
bl L$0947,%r0 ;# 1071 jump
ldb 0(%r19),%r19 ;# 1069 movqi+1/5
L$0154
ldb -2(%r19),%r19 ;# 1075 movqi+1/5
L$0947
comib,= 0,%r14,L$0156 ;# 1079 bleu+1
extrs %r19,31,8,%r20 ;# 1076 extendqisi2
ldb 46(%r14),%r19 ;# 1081 movqi+1/5
extrs %r19,31,8,%r19 ;# 1082 extendqisi2
comb,= %r19,%r20,L$0157 ;# 1084 bleu+1
ldi 17,%r26 ;# 1159 reload_outsi+2/2
bl,n L$1162,%r0 ;# 1085 jump
L$0156
ldi 46,%r19 ;# 1089 reload_outsi+2/2
comb,<> %r19,%r20,L$1162 ;# 1091 bleu+1
ldi 17,%r26 ;# 1159 reload_outsi+2/2
L$0157
comib,= 0,%r11,L$0153 ;# 1096 bleu+1
ldw -296(%r30),%r19 ;# 2409 reload_outsi+2/5
comb,<<= %r16,%r19,L$1162 ;# 1098 bleu+1
ldi 17,%r26 ;# 1159 reload_outsi+2/2
comib,=,n 0,%r14,L$0158 ;# 1100 bleu+1
ldb 0(%r19),%r19 ;# 1103 zero_extendqisi2/2
addl %r14,%r19,%r19 ;# 1104 addsi3/1
L$0158
ldb 0(%r19),%r19 ;# 1112 movqi+1/5
comib,= 0,%r14,L$0160 ;# 1116 bleu+1
extrs %r19,31,8,%r20 ;# 1113 extendqisi2
ldb 10(%r14),%r19 ;# 1118 movqi+1/5
extrs %r19,31,8,%r19 ;# 1119 extendqisi2
comb,= %r19,%r20,L$0161 ;# 1121 bleu+1
ldi 17,%r26 ;# 1159 reload_outsi+2/2
bl,n L$1162,%r0 ;# 1122 jump
L$0160
comib,<> 10,%r20,L$1162 ;# 1126 bleu+1
ldi 17,%r26 ;# 1159 reload_outsi+2/2
L$0161
bb,< %r15,25,L$1162 ;# 1134 bleu+3
ldi 17,%r26 ;# 1159 reload_outsi+2/2
ldi 12,%r26 ;# 1140 reload_outsi+2/2
copy %r6,%r25 ;# 1142 reload_outsi+2/1
sub %r8,%r6,%r24 ;# 1137 subsi3/1
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl store_op1,%r2 ;# 1146 call_internal_symref
ldo -3(%r24),%r24 ;# 1144 addsi3/2
bl L$0162,%r0 ;# 1151 jump
ldi 1,%r13 ;# 1149 reload_outsi+2/2
L$0153
ldi 17,%r26 ;# 1159 reload_outsi+2/2
L$1162
copy %r6,%r25 ;# 1161 reload_outsi+2/1
sub %r8,%r6,%r24 ;# 1156 subsi3/1
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl store_op1,%r2 ;# 1165 call_internal_symref
ldo -6(%r24),%r24 ;# 1163 addsi3/2
L$0162
ldo 3(%r6),%r6 ;# 1168 addsi3/2
L$0137
ldw 0(%r5),%r3 ;# 8010 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 8013 reload_outsi+2/5
sub %r6,%r3,%r19 ;# 8011 subsi3/1
ldo 3(%r19),%r19 ;# 8012 addsi3/2
comb,>>=,n %r20,%r19,L$0164 ;# 8014 bleu+1
ldil L'65536,%r4 ;# 8684 reload_outsi+2/3
L$0165
comclr,<> %r4,%r20,%r0 ;# 1195 bleu+1
bl L$0944,%r0
zdep %r20,30,31,%r19 ;# 1205 ashlsi3+1
comb,>>= %r4,%r19,L$0170 ;# 1213 bleu+1
stw %r19,4(%r5) ;# 1207 reload_outsi+2/6
stw %r4,4(%r5) ;# 1216 reload_outsi+2/6
L$0170
ldw 0(%r5),%r26 ;# 1223 reload_outsi+2/5
.CALL ARGW0=GR,ARGW1=GR
bl realloc,%r2 ;# 1227 call_value_internal_symref
ldw 4(%r5),%r25 ;# 1225 reload_outsi+2/5
comib,= 0,%r28,L$0953 ;# 1235 bleu+1
stw %r28,0(%r5) ;# 1231 reload_outsi+2/6
comb,= %r28,%r3,L$0163 ;# 1245 bleu+1
sub %r6,%r3,%r19 ;# 1247 subsi3/1
addl %r28,%r19,%r6 ;# 1250 addsi3/1
sub %r12,%r3,%r19 ;# 1251 subsi3/1
comib,= 0,%r10,L$0173 ;# 1256 bleu+1
addl %r28,%r19,%r12 ;# 1254 addsi3/1
sub %r10,%r3,%r19 ;# 1257 subsi3/1
addl %r28,%r19,%r10 ;# 1260 addsi3/1
L$0173
comib,= 0,%r8,L$0174 ;# 1263 bleu+1
sub %r8,%r3,%r19 ;# 1264 subsi3/1
addl %r28,%r19,%r8 ;# 1267 addsi3/1
L$0174
comib,= 0,%r9,L$0163 ;# 1270 bleu+1
sub %r9,%r3,%r19 ;# 1271 subsi3/1
addl %r28,%r19,%r9 ;# 1274 addsi3/1
L$0163
ldw 0(%r5),%r3 ;# 1175 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 1179 reload_outsi+2/5
sub %r6,%r3,%r19 ;# 1176 subsi3/1
ldo 3(%r19),%r19 ;# 1177 addsi3/2
comb,<< %r20,%r19,L$0165
nop ;# 1181 bleu+1
L$0164
ldi 14,%r26 ;# 8786 reload_outsi+2/2
comiclr,= 0,%r13,%r0 ;# 1310 beq-1/2
ldi 15,%r26
copy %r8,%r25 ;# 1312 reload_outsi+2/1
sub %r6,%r8,%r24 ;# 1314 subsi3/1
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl insert_op1,%r2 ;# 1318 call_internal_symref
copy %r6,%r23 ;# 1316 reload_outsi+2/1
ldi 0,%r9 ;# 1321 reload_outsi+2/2
comib,<> 0,%r11,L$0043 ;# 1326 bleu+1
ldo 3(%r6),%r6 ;# 1323 addsi3/2
ldw 0(%r5),%r3 ;# 8019 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 8022 reload_outsi+2/5
sub %r6,%r3,%r19 ;# 8020 subsi3/1
ldo 3(%r19),%r19 ;# 8021 addsi3/2
comb,>>=,n %r20,%r19,L$0182 ;# 8023 bleu+1
ldil L'65536,%r4 ;# 8682 reload_outsi+2/3
L$0183
comb,= %r4,%r20,L$0944 ;# 1352 bleu+1
zdep %r20,30,31,%r19 ;# 1362 ashlsi3+1
comb,>>= %r4,%r19,L$0188 ;# 1370 bleu+1
stw %r19,4(%r5) ;# 1364 reload_outsi+2/6
stw %r4,4(%r5) ;# 1373 reload_outsi+2/6
L$0188
ldw 0(%r5),%r26 ;# 1380 reload_outsi+2/5
.CALL ARGW0=GR,ARGW1=GR
bl realloc,%r2 ;# 1384 call_value_internal_symref
ldw 4(%r5),%r25 ;# 1382 reload_outsi+2/5
comib,= 0,%r28,L$0953 ;# 1392 bleu+1
stw %r28,0(%r5) ;# 1388 reload_outsi+2/6
comb,= %r28,%r3,L$0181 ;# 1402 bleu+1
sub %r6,%r3,%r19 ;# 1404 subsi3/1
addl %r28,%r19,%r6 ;# 1407 addsi3/1
sub %r12,%r3,%r19 ;# 1408 subsi3/1
comib,= 0,%r10,L$0191 ;# 1413 bleu+1
addl %r28,%r19,%r12 ;# 1411 addsi3/1
sub %r10,%r3,%r19 ;# 1414 subsi3/1
addl %r28,%r19,%r10 ;# 1417 addsi3/1
L$0191
comib,= 0,%r8,L$0192 ;# 1420 bleu+1
sub %r8,%r3,%r19 ;# 1421 subsi3/1
addl %r28,%r19,%r8 ;# 1424 addsi3/1
L$0192
comib,= 0,%r9,L$0181 ;# 1427 bleu+1
sub %r9,%r3,%r19 ;# 1428 subsi3/1
addl %r28,%r19,%r9 ;# 1431 addsi3/1
L$0181
ldw 0(%r5),%r3 ;# 1332 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 1336 reload_outsi+2/5
sub %r6,%r3,%r19 ;# 1333 subsi3/1
ldo 3(%r19),%r19 ;# 1334 addsi3/2
comb,<< %r20,%r19,L$0183
nop ;# 1338 bleu+1
L$0182
ldi 18,%r26 ;# 1454 reload_outsi+2/2
copy %r8,%r25 ;# 1456 reload_outsi+2/1
ldi 3,%r24 ;# 1458 reload_outsi+2/2
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl insert_op1,%r2 ;# 1462 call_internal_symref
copy %r6,%r23 ;# 1460 reload_outsi+2/1
bl L$0043,%r0 ;# 1470 jump
ldo 3(%r6),%r6 ;# 1464 addsi3/2
L$0196
ldw 4(%r5),%r20 ;# 8030 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 8028 subsi3/1
ldo 1(%r19),%r19 ;# 8029 addsi3/2
comb,>>= %r20,%r19,L$0201 ;# 8031 bleu+1
copy %r6,%r8 ;# 1475 reload_outsi+2/1
ldil L'65536,%r3 ;# 8680 reload_outsi+2/3
L$0202
comb,= %r3,%r20,L$0944 ;# 1503 bleu+1
zdep %r20,30,31,%r19 ;# 1513 ashlsi3+1
comb,>>= %r3,%r19,L$0207 ;# 1521 bleu+1
stw %r19,4(%r5) ;# 1515 reload_outsi+2/6
stw %r3,4(%r5) ;# 1524 reload_outsi+2/6
L$0207
ldw 0(%r5),%r26 ;# 1531 reload_outsi+2/5
.CALL ARGW0=GR,ARGW1=GR
bl realloc,%r2 ;# 1535 call_value_internal_symref
ldw 4(%r5),%r25 ;# 1533 reload_outsi+2/5
comib,= 0,%r28,L$0953 ;# 1543 bleu+1
stw %r28,0(%r5) ;# 1539 reload_outsi+2/6
comb,= %r28,%r4,L$0200 ;# 1553 bleu+1
sub %r6,%r4,%r19 ;# 1555 subsi3/1
addl %r28,%r19,%r6 ;# 1558 addsi3/1
sub %r12,%r4,%r19 ;# 1559 subsi3/1
comib,= 0,%r10,L$0210 ;# 1564 bleu+1
addl %r28,%r19,%r12 ;# 1562 addsi3/1
sub %r10,%r4,%r19 ;# 1565 subsi3/1
addl %r28,%r19,%r10 ;# 1568 addsi3/1
L$0210
comib,= 0,%r8,L$0211 ;# 1571 bleu+1
sub %r8,%r4,%r19 ;# 1572 subsi3/1
addl %r28,%r19,%r8 ;# 1575 addsi3/1
L$0211
comib,= 0,%r9,L$0200 ;# 1578 bleu+1
sub %r9,%r4,%r19 ;# 1579 subsi3/1
addl %r28,%r19,%r9 ;# 1582 addsi3/1
L$0200
ldw 0(%r5),%r4 ;# 1483 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 1487 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 1484 subsi3/1
ldo 1(%r19),%r19 ;# 1485 addsi3/2
comb,<< %r20,%r19,L$0202
nop ;# 1489 bleu+1
L$0201
ldi 2,%r19 ;# 1604 movqi+1/2
bl L$0043,%r0 ;# 1617 jump
stbs,ma %r19,1(%r6) ;# 1605 movqi+1/6
L$0216
comb,= %r16,%r19,L$0902 ;# 1626 bleu+1
ldi 0,%r13 ;# 1623 reload_outsi+2/2
ldw 0(%r5),%r3 ;# 8035 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 8038 reload_outsi+2/5
sub %r6,%r3,%r19 ;# 8036 subsi3/1
ldo 34(%r19),%r19 ;# 8037 addsi3/2
comb,>>= %r20,%r19,L$0219 ;# 8039 bleu+1
ldil L'65536,%r4 ;# 8678 reload_outsi+2/3
L$0220
comb,= %r4,%r20,L$0944 ;# 1661 bleu+1
zdep %r20,30,31,%r19 ;# 1671 ashlsi3+1
comb,>>= %r4,%r19,L$0225 ;# 1679 bleu+1
stw %r19,4(%r5) ;# 1673 reload_outsi+2/6
stw %r4,4(%r5) ;# 1682 reload_outsi+2/6
L$0225
ldw 0(%r5),%r26 ;# 1689 reload_outsi+2/5
.CALL ARGW0=GR,ARGW1=GR
bl realloc,%r2 ;# 1693 call_value_internal_symref
ldw 4(%r5),%r25 ;# 1691 reload_outsi+2/5
comib,= 0,%r28,L$0953 ;# 1701 bleu+1
stw %r28,0(%r5) ;# 1697 reload_outsi+2/6
comb,= %r28,%r3,L$0218 ;# 1711 bleu+1
sub %r6,%r3,%r19 ;# 1713 subsi3/1
addl %r28,%r19,%r6 ;# 1716 addsi3/1
sub %r12,%r3,%r19 ;# 1717 subsi3/1
comib,= 0,%r10,L$0228 ;# 1722 bleu+1
addl %r28,%r19,%r12 ;# 1720 addsi3/1
sub %r10,%r3,%r19 ;# 1723 subsi3/1
addl %r28,%r19,%r10 ;# 1726 addsi3/1
L$0228
comib,= 0,%r8,L$0229 ;# 1729 bleu+1
sub %r8,%r3,%r19 ;# 1730 subsi3/1
addl %r28,%r19,%r8 ;# 1733 addsi3/1
L$0229
comib,= 0,%r9,L$0218 ;# 1736 bleu+1
sub %r9,%r3,%r19 ;# 1737 subsi3/1
addl %r28,%r19,%r9 ;# 1740 addsi3/1
L$0218
ldw 0(%r5),%r3 ;# 1641 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 1645 reload_outsi+2/5
sub %r6,%r3,%r19 ;# 1642 subsi3/1
ldo 34(%r19),%r19 ;# 1643 addsi3/2
comb,<< %r20,%r19,L$0220
nop ;# 1647 bleu+1
L$0219
ldw 0(%r5),%r4 ;# 8043 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 8046 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 8044 subsi3/1
ldo 1(%r19),%r19 ;# 8045 addsi3/2
comb,>>= %r20,%r19,L$0237 ;# 8047 bleu+1
copy %r6,%r8 ;# 1763 reload_outsi+2/1
ldil L'65536,%r3 ;# 8676 reload_outsi+2/3
L$0238
comb,= %r3,%r20,L$0944 ;# 1791 bleu+1
zdep %r20,30,31,%r19 ;# 1801 ashlsi3+1
comb,>>= %r3,%r19,L$0243 ;# 1809 bleu+1
stw %r19,4(%r5) ;# 1803 reload_outsi+2/6
stw %r3,4(%r5) ;# 1812 reload_outsi+2/6
L$0243
ldw 0(%r5),%r26 ;# 1819 reload_outsi+2/5
.CALL ARGW0=GR,ARGW1=GR
bl realloc,%r2 ;# 1823 call_value_internal_symref
ldw 4(%r5),%r25 ;# 1821 reload_outsi+2/5
comib,= 0,%r28,L$0953 ;# 1831 bleu+1
stw %r28,0(%r5) ;# 1827 reload_outsi+2/6
comb,= %r28,%r4,L$0236 ;# 1841 bleu+1
sub %r6,%r4,%r19 ;# 1843 subsi3/1
addl %r28,%r19,%r6 ;# 1846 addsi3/1
sub %r12,%r4,%r19 ;# 1847 subsi3/1
comib,= 0,%r10,L$0246 ;# 1852 bleu+1
addl %r28,%r19,%r12 ;# 1850 addsi3/1
sub %r10,%r4,%r19 ;# 1853 subsi3/1
addl %r28,%r19,%r10 ;# 1856 addsi3/1
L$0246
comib,= 0,%r8,L$0247 ;# 1859 bleu+1
sub %r8,%r4,%r19 ;# 1860 subsi3/1
addl %r28,%r19,%r8 ;# 1863 addsi3/1
L$0247
comib,= 0,%r9,L$0236 ;# 1866 bleu+1
sub %r9,%r4,%r19 ;# 1867 subsi3/1
addl %r28,%r19,%r9 ;# 1870 addsi3/1
L$0236
ldw 0(%r5),%r4 ;# 1771 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 1775 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 1772 subsi3/1
ldo 1(%r19),%r19 ;# 1773 addsi3/2
comb,<< %r20,%r19,L$0238
nop ;# 1777 bleu+1
L$0237
copy %r6,%r22 ;# 1909 reload_outsi+2/1
ldo 1(%r6),%r6 ;# 1891 addsi3/2
ldw -296(%r30),%r19 ;# 2421 reload_outsi+2/5
ldb 0(%r19),%r19 ;# 1893 movqi+1/5
ldi 94,%r21 ;# 1896 reload_outsi+2/2
extrs %r19,31,8,%r19 ;# 1894 extendqisi2
comb,<> %r21,%r19,L$0251 ;# 1898 bleu+1
ldi 3,%r20 ;# 8051 movqi+1/2
ldi 4,%r20 ;# 1900 movqi+1/2
L$0251
stb %r20,0(%r22) ;# 1911 movqi+1/6
ldw -296(%r30),%r20 ;# 2424 reload_outsi+2/5
ldb 0(%r20),%r19 ;# 1923 movqi+1/5
extrs %r19,31,8,%r19 ;# 1924 extendqisi2
comb,<> %r21,%r19,L$0254 ;# 1928 bleu+1
ldo 1(%r20),%r19 ;# 1930 addsi3/2
stw %r19,-296(%r30) ;# 2427 reload_outsi+2/6
L$0254
ldw 0(%r5),%r4 ;# 8052 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 8055 reload_outsi+2/5
ldw -296(%r30),%r1 ;# 2433 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 8053 subsi3/1
ldo 1(%r19),%r19 ;# 8054 addsi3/2
comb,>>= %r20,%r19,L$0259 ;# 8056 bleu+1
stw %r1,-268(%r30) ;# 8789 reload_outsi+2/6
ldil L'65536,%r3 ;# 8674 reload_outsi+2/3
L$0260
comb,= %r3,%r20,L$0944 ;# 1962 bleu+1
zdep %r20,30,31,%r19 ;# 1972 ashlsi3+1
comb,>>= %r3,%r19,L$0265 ;# 1980 bleu+1
stw %r19,4(%r5) ;# 1974 reload_outsi+2/6
stw %r3,4(%r5) ;# 1983 reload_outsi+2/6
L$0265
ldw 0(%r5),%r26 ;# 1990 reload_outsi+2/5
.CALL ARGW0=GR,ARGW1=GR
bl realloc,%r2 ;# 1994 call_value_internal_symref
ldw 4(%r5),%r25 ;# 1992 reload_outsi+2/5
comib,= 0,%r28,L$0953 ;# 2002 bleu+1
stw %r28,0(%r5) ;# 1998 reload_outsi+2/6
comb,= %r28,%r4,L$0258 ;# 2012 bleu+1
sub %r6,%r4,%r19 ;# 2014 subsi3/1
addl %r28,%r19,%r6 ;# 2017 addsi3/1
sub %r12,%r4,%r19 ;# 2018 subsi3/1
comib,= 0,%r10,L$0268 ;# 2023 bleu+1
addl %r28,%r19,%r12 ;# 2021 addsi3/1
sub %r10,%r4,%r19 ;# 2024 subsi3/1
addl %r28,%r19,%r10 ;# 2027 addsi3/1
L$0268
comib,= 0,%r8,L$0269 ;# 2030 bleu+1
sub %r8,%r4,%r19 ;# 2031 subsi3/1
addl %r28,%r19,%r8 ;# 2034 addsi3/1
L$0269
comib,= 0,%r9,L$0258 ;# 2037 bleu+1
sub %r9,%r4,%r19 ;# 2038 subsi3/1
addl %r28,%r19,%r9 ;# 2041 addsi3/1
L$0258
ldw 0(%r5),%r4 ;# 1942 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 1946 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 1943 subsi3/1
ldo 1(%r19),%r19 ;# 1944 addsi3/2
comb,<< %r20,%r19,L$0260
nop ;# 1948 bleu+1
L$0259
ldi 32,%r19 ;# 2063 movqi+1/2
stbs,ma %r19,1(%r6) ;# 2064 movqi+1/6
copy %r6,%r26 ;# 2077 reload_outsi+2/1
ldi 0,%r25 ;# 2079 reload_outsi+2/2
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl memset,%r2 ;# 2083 call_value_internal_symref
ldi 32,%r24 ;# 2081 reload_outsi+2/2
ldb -2(%r6),%r19 ;# 2087 zero_extendqisi2/2
comib,<> 4,%r19,L$0274 ;# 2089 bleu+1
ldi 93,%r17 ;# 8622 reload_outsi+2/2
bb,>=,n %r15,23,L$0274 ;# 2094 movsi-4
ldb 1(%r6),%r19 ;# 2097 movqi+1/5
depi -1,29,1,%r19 ;# 2099 iorsi3+1/2
stb %r19,1(%r6) ;# 2101 movqi+1/6
L$0274
ldi 4,%r18 ;# 8628 reload_outsi+2/2
and %r15,%r18,%r1 ;# 8629 andsi3/1
stw %r1,-252(%r30) ;# 8792 reload_outsi+2/6
ldo -288(%r30),%r11 ;# 8632 addsi3/2
L$0275
ldw -296(%r30),%r20 ;# 2436 reload_outsi+2/5
L$1165
comb,= %r16,%r20,L$0902 ;# 2109 bleu+1
copy %r20,%r21 ;# 8745 reload_outsi+2/1
ldbs,ma 1(%r21),%r7 ;# 2134 zero_extendqisi2/2
comib,= 0,%r14,L$0280 ;# 2139 bleu+1
stw %r21,-296(%r30) ;# 2445 reload_outsi+2/6
addl %r14,%r7,%r19 ;# 2140 addsi3/1
ldb 0(%r19),%r7 ;# 2143 zero_extendqisi2/2
L$0280
bb,>= %r15,31,L$0285 ;# 2159 movsi-4
ldi 92,%r19 ;# 2161 reload_outsi+2/2
comb,<>,n %r19,%r7,L$0285 ;# 2163 bleu+1
comb,= %r16,%r21,L$0903 ;# 2167 bleu+1
ldo 1(%r21),%r19 ;# 2195 addsi3/2
ldb 1(%r20),%r3 ;# 2192 zero_extendqisi2/2
comib,= 0,%r14,L$0288 ;# 2197 bleu+1
stw %r19,-296(%r30) ;# 2460 reload_outsi+2/6
addl %r14,%r3,%r19 ;# 2198 addsi3/1
ldb 0(%r19),%r3 ;# 2201 zero_extendqisi2/2
L$0288
extru %r3,28,29,%r19 ;# 2216 lshrsi3/2
addl %r6,%r19,%r19 ;# 2219 addsi3/1
bl L$0948,%r0 ;# 2235 jump
extru %r3,31,3,%r20 ;# 2222 andsi3/1
L$0285
comb,<>,n %r17,%r7,L$0293 ;# 2243 bleu+1
ldw -268(%r30),%r1 ;# 8798 reload_outsi+2/5
ldw -296(%r30),%r20 ;# 2466 reload_outsi+2/5
ldo 1(%r1),%r19 ;# 2244 addsi3/2
comb,<>,n %r19,%r20,L$0276 ;# 2246 bleu+1
L$0293
comib,= 0,%r13,L$0294 ;# 2253 bleu+1
ldi 45,%r1 ;# 8801 reload_outsi+2/2
comb,<> %r1,%r7,L$1163 ;# 2257 bleu+1
ldw -296(%r30),%r20 ;# 2524 reload_outsi+2/5
ldw -296(%r30),%r19 ;# 2469 reload_outsi+2/5
ldb 0(%r19),%r19 ;# 2259 movqi+1/5
extrs %r19,31,8,%r19 ;# 2260 extendqisi2
comb,<>,n %r17,%r19,L$0895 ;# 2264 bleu+1
L$0294
ldi 45,%r1 ;# 8804 reload_outsi+2/2
comb,<> %r1,%r7,L$1163 ;# 2280 bleu+1
ldw -296(%r30),%r20 ;# 2524 reload_outsi+2/5
ldw -276(%r30),%r1 ;# 8807 reload_outsi+2/5
ldo -2(%r20),%r19 ;# 2281 addsi3/2
comb,>>,n %r1,%r19,L$1179 ;# 2283 bleu+1
ldb -2(%r20),%r19 ;# 2285 movqi+1/5
ldi 91,%r1 ;# 8810 reload_outsi+2/2
extrs %r19,31,8,%r19 ;# 2286 extendqisi2
comb,= %r1,%r19,L$1163 ;# 2290 bleu+1
ldw -276(%r30),%r1 ;# 8813 reload_outsi+2/5
L$1179
ldo -3(%r20),%r19 ;# 2294 addsi3/2
comb,>>,n %r1,%r19,L$0297 ;# 2296 bleu+1
ldb -3(%r20),%r19 ;# 2298 movqi+1/5
ldi 91,%r1 ;# 8816 reload_outsi+2/2
extrs %r19,31,8,%r19 ;# 2299 extendqisi2
comb,<> %r1,%r19,L$1164 ;# 2303 bleu+1
ldw -296(%r30),%r19 ;# 2487 reload_outsi+2/5
ldb -2(%r20),%r19 ;# 2305 movqi+1/5
ldi 94,%r20 ;# 2308 reload_outsi+2/2
extrs %r19,31,8,%r19 ;# 2306 extendqisi2
comb,= %r20,%r19,L$1163 ;# 2310 bleu+1
ldw -296(%r30),%r20 ;# 2524 reload_outsi+2/5
L$0297
ldw -296(%r30),%r19 ;# 2487 reload_outsi+2/5
L$1164
ldb 0(%r19),%r19 ;# 2315 movqi+1/5
extrs %r19,31,8,%r19 ;# 2316 extendqisi2
comb,<> %r17,%r19,L$0302 ;# 2320 bleu+1
ldw -296(%r30),%r20 ;# 2524 reload_outsi+2/5
L$1163
ldb 0(%r20),%r19 ;# 2526 movqi+1/5
ldi 45,%r1 ;# 8819 reload_outsi+2/2
extrs %r19,31,8,%r19 ;# 2527 extendqisi2
comb,<>,n %r1,%r19,L$0300 ;# 2531 bleu+1
ldb 1(%r20),%r19 ;# 2535 movqi+1/5
extrs %r19,31,8,%r19 ;# 2536 extendqisi2
comb,=,n %r17,%r19,L$0300 ;# 2540 bleu+1
comb,= %r16,%r20,L$0922 ;# 2550 bleu+1
ldo 1(%r20),%r19 ;# 2559 addsi3/2
stw %r19,-296(%r30) ;# 2561 reload_outsi+2/6
L$0302
stw %r6,-52(%r30) ;# 2588 reload_outsi+2/6
ldo -296(%r30),%r26 ;# 2590 addsi3/2
copy %r16,%r25 ;# 2592 reload_outsi+2/1
copy %r14,%r24 ;# 2594 reload_outsi+2/1
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl compile_range,%r2 ;# 2598 call_value_internal_symref
copy %r15,%r23 ;# 2596 reload_outsi+2/1
movb,= %r28,%r4,L$1165 ;# 2603 decrement_and_branch_until_zero+2/1
ldw -296(%r30),%r20 ;# 2436 reload_outsi+2/5
.CALL ARGW0=GR
bl free,%r2 ;# 2607 call_internal_symref
ldw -312(%r30),%r26 ;# 2605 reload_outsi+2/5
bl L$0867,%r0 ;# 2611 jump
copy %r4,%r28 ;# 2609 reload_outsi+2/1
L$0300
ldw -252(%r30),%r1 ;# 8822 reload_outsi+2/5
comib,= 0,%r1,L$0309 ;# 2624 bleu+1
ldi 91,%r1 ;# 8825 reload_outsi+2/2
comb,<> %r1,%r7,L$1166 ;# 2628 bleu+1
ldi 0,%r13 ;# 3624 reload_outsi+2/2
ldw -296(%r30),%r20 ;# 2630 reload_outsi+2/5
ldb 0(%r20),%r19 ;# 2632 movqi+1/5
ldi 58,%r1 ;# 8828 reload_outsi+2/2
extrs %r19,31,8,%r19 ;# 2633 extendqisi2
comb,<>,n %r1,%r19,L$1166 ;# 2637 bleu+1
comb,= %r16,%r20,L$0922 ;# 2647 bleu+1
ldo 1(%r20),%r19 ;# 2656 addsi3/2
stw %r19,-296(%r30) ;# 2658 reload_outsi+2/6
comb,= %r16,%r19,L$0902 ;# 2689 bleu+1
ldi 0,%r3 ;# 2684 reload_outsi+2/2
L$0317
ldw -296(%r30),%r19 ;# 2709 reload_outsi+2/5
comb,= %r16,%r19,L$0922 ;# 2711 bleu+1
ldo 1(%r19),%r20 ;# 2720 addsi3/2
stw %r20,-296(%r30) ;# 2722 reload_outsi+2/6
comib,= 0,%r14,L$0321 ;# 2729 bleu+1
ldb 0(%r19),%r7 ;# 2725 zero_extendqisi2/2
addl %r14,%r7,%r19 ;# 2730 addsi3/1
ldb 0(%r19),%r7 ;# 2733 zero_extendqisi2/2
L$0321
ldi 58,%r1 ;# 8831 reload_outsi+2/2
comb,= %r1,%r7,L$1167 ;# 2750 bleu+1
addl %r11,%r3,%r19 ;# 2789 addsi3/1
comb,=,n %r17,%r7,L$1167 ;# 2754 bleu+1
comb,=,n %r16,%r20,L$1167 ;# 2758 bleu+1
comib,= 6,%r3,L$1167 ;# 2760 bleu+1
copy %r3,%r20 ;# 2770 reload_outsi+2/1
ldo 1(%r20),%r19 ;# 2771 addsi3/2
extru %r19,31,8,%r3 ;# 2772 zero_extendqisi2/1
addl %r11,%r20,%r20 ;# 2776 addsi3/1
bl L$0317,%r0 ;# 2783 jump
stb %r7,0(%r20) ;# 2778 movqi+1/6
L$1167
comb,<> %r1,%r7,L$0328 ;# 2796 bleu+1
stb %r0,0(%r19) ;# 2791 movqi+1/6
ldw -296(%r30),%r19 ;# 2798 reload_outsi+2/5
ldb 0(%r19),%r19 ;# 2800 movqi+1/5
extrs %r19,31,8,%r19 ;# 2801 extendqisi2
comb,<> %r17,%r19,L$1168 ;# 2805 bleu+1
ldi 255,%r19 ;# 8069 reload_outsi+2/2
copy %r11,%r26 ;# 2813 reload_outsi+2/1
ldil LR'L$C0016,%r1 ;# 8835 add_high_const+3
ldo RR'L$C0016(%r1),%r1 ;# 8836 movhi-2
.CALL ARGW0=GR,ARGW1=GR
bl strcmp,%r2 ;# 2817 call_value_internal_symref
copy %r1,%r25 ;# 2815 reload_outsi+2/1
copy %r11,%r26 ;# 2829 reload_outsi+2/1
ldil LR'L$C0017,%r1 ;# 8837 add_high_const+3
ldo RR'L$C0017(%r1),%r1 ;# 8838 movhi-2
copy %r1,%r25 ;# 2831 reload_outsi+2/1
comiclr,<> 0,%r28,%r28 ;# 2821 scc
ldi 1,%r28
.CALL ARGW0=GR,ARGW1=GR
bl strcmp,%r2 ;# 2833 call_value_internal_symref
stw %r28,-244(%r30) ;# 8841 reload_outsi+2/6
copy %r11,%r26 ;# 2845 reload_outsi+2/1
ldil LR'L$C0018,%r1 ;# 8842 add_high_const+3
ldo RR'L$C0018(%r1),%r1 ;# 8843 movhi-2
copy %r1,%r25 ;# 2847 reload_outsi+2/1
comiclr,<> 0,%r28,%r28 ;# 2837 scc
ldi 1,%r28
.CALL ARGW0=GR,ARGW1=GR
bl strcmp,%r2 ;# 2849 call_value_internal_symref
stw %r28,-236(%r30) ;# 8846 reload_outsi+2/6
copy %r11,%r26 ;# 2861 reload_outsi+2/1
ldil LR'L$C0019,%r1 ;# 8847 add_high_const+3
ldo RR'L$C0019(%r1),%r1 ;# 8848 movhi-2
copy %r1,%r25 ;# 2863 reload_outsi+2/1
comiclr,<> 0,%r28,%r28 ;# 2853 scc
ldi 1,%r28
.CALL ARGW0=GR,ARGW1=GR
bl strcmp,%r2 ;# 2865 call_value_internal_symref
stw %r28,-228(%r30) ;# 8851 reload_outsi+2/6
copy %r11,%r26 ;# 2877 reload_outsi+2/1
ldil LR'L$C0020,%r1 ;# 8852 add_high_const+3
ldo RR'L$C0020(%r1),%r1 ;# 8853 movhi-2
copy %r1,%r25 ;# 2879 reload_outsi+2/1
comiclr,<> 0,%r28,%r28 ;# 2869 scc
ldi 1,%r28
.CALL ARGW0=GR,ARGW1=GR
bl strcmp,%r2 ;# 2881 call_value_internal_symref
stw %r28,-220(%r30) ;# 8856 reload_outsi+2/6
copy %r11,%r26 ;# 2893 reload_outsi+2/1
ldil LR'L$C0021,%r1 ;# 8857 add_high_const+3
ldo RR'L$C0021(%r1),%r1 ;# 8858 movhi-2
copy %r1,%r25 ;# 2895 reload_outsi+2/1
comiclr,<> 0,%r28,%r28 ;# 2885 scc
ldi 1,%r28
.CALL ARGW0=GR,ARGW1=GR
bl strcmp,%r2 ;# 2897 call_value_internal_symref
stw %r28,-212(%r30) ;# 8861 reload_outsi+2/6
copy %r11,%r26 ;# 2909 reload_outsi+2/1
ldil LR'L$C0022,%r1 ;# 8862 add_high_const+3
ldo RR'L$C0022(%r1),%r1 ;# 8863 movhi-2
copy %r1,%r25 ;# 2911 reload_outsi+2/1
comiclr,<> 0,%r28,%r28 ;# 2901 scc
ldi 1,%r28
.CALL ARGW0=GR,ARGW1=GR
bl strcmp,%r2 ;# 2913 call_value_internal_symref
stw %r28,-204(%r30) ;# 8866 reload_outsi+2/6
copy %r11,%r26 ;# 2925 reload_outsi+2/1
ldil LR'L$C0023,%r1 ;# 8867 add_high_const+3
ldo RR'L$C0023(%r1),%r1 ;# 8868 movhi-2
copy %r1,%r25 ;# 2927 reload_outsi+2/1
comiclr,<> 0,%r28,%r28 ;# 2917 scc
ldi 1,%r28
.CALL ARGW0=GR,ARGW1=GR
bl strcmp,%r2 ;# 2929 call_value_internal_symref
stw %r28,-196(%r30) ;# 8871 reload_outsi+2/6
copy %r11,%r26 ;# 2941 reload_outsi+2/1
ldil LR'L$C0024,%r1 ;# 8872 add_high_const+3
ldo RR'L$C0024(%r1),%r1 ;# 8873 movhi-2
copy %r1,%r25 ;# 2943 reload_outsi+2/1
comiclr,<> 0,%r28,%r28 ;# 2933 scc
ldi 1,%r28
.CALL ARGW0=GR,ARGW1=GR
bl strcmp,%r2 ;# 2945 call_value_internal_symref
stw %r28,-188(%r30) ;# 8876 reload_outsi+2/6
copy %r11,%r26 ;# 2957 reload_outsi+2/1
ldil LR'L$C0025,%r1 ;# 8877 add_high_const+3
ldo RR'L$C0025(%r1),%r1 ;# 8878 movhi-2
copy %r1,%r25 ;# 2959 reload_outsi+2/1
comiclr,<> 0,%r28,%r28 ;# 2949 scc
ldi 1,%r28
.CALL ARGW0=GR,ARGW1=GR
bl strcmp,%r2 ;# 2961 call_value_internal_symref
stw %r28,-180(%r30) ;# 8881 reload_outsi+2/6
copy %r11,%r26 ;# 2973 reload_outsi+2/1
ldil LR'L$C0026,%r19 ;# 2970 add_high_const+3
ldo RR'L$C0026(%r19),%r3 ;# 2971 movhi-2
copy %r3,%r25 ;# 2975 reload_outsi+2/1
comiclr,<> 0,%r28,%r28 ;# 2965 scc
ldi 1,%r28
.CALL ARGW0=GR,ARGW1=GR
bl strcmp,%r2 ;# 2977 call_value_internal_symref
stw %r28,-172(%r30) ;# 8884 reload_outsi+2/6
copy %r11,%r26 ;# 2989 reload_outsi+2/1
ldil LR'L$C0027,%r19 ;# 2986 add_high_const+3
ldo RR'L$C0027(%r19),%r4 ;# 2987 movhi-2
comiclr,<> 0,%r28,%r13 ;# 2981 scc
ldi 1,%r13
.CALL ARGW0=GR,ARGW1=GR
bl strcmp,%r2 ;# 2993 call_value_internal_symref
copy %r4,%r25 ;# 2991 reload_outsi+2/1
copy %r11,%r26 ;# 3005 reload_outsi+2/1
ldil LR'L$C0017,%r1 ;# 8885 add_high_const+3
ldo RR'L$C0017(%r1),%r1 ;# 8886 movhi-2
comiclr,<> 0,%r28,%r7 ;# 2997 scc
ldi 1,%r7
.CALL ARGW0=GR,ARGW1=GR
bl strcmp,%r2 ;# 3009 call_value_internal_symref
copy %r1,%r25 ;# 3007 reload_outsi+2/1
comib,= 0,%r28,L$0329 ;# 3013 bleu+1
copy %r11,%r26 ;# 3018 reload_outsi+2/1
.CALL ARGW0=GR,ARGW1=GR
bl strcmp,%r2 ;# 3022 call_value_internal_symref
copy %r3,%r25 ;# 3020 reload_outsi+2/1
comib,= 0,%r28,L$0329 ;# 3026 bleu+1
copy %r11,%r26 ;# 3031 reload_outsi+2/1
ldil LR'L$C0022,%r1 ;# 8887 add_high_const+3
ldo RR'L$C0022(%r1),%r1 ;# 8888 movhi-2
.CALL ARGW0=GR,ARGW1=GR
bl strcmp,%r2 ;# 3035 call_value_internal_symref
copy %r1,%r25 ;# 3033 reload_outsi+2/1
comib,= 0,%r28,L$0329 ;# 3039 bleu+1
copy %r11,%r26 ;# 3044 reload_outsi+2/1
ldil LR'L$C0020,%r1 ;# 8889 add_high_const+3
ldo RR'L$C0020(%r1),%r1 ;# 8890 movhi-2
.CALL ARGW0=GR,ARGW1=GR
bl strcmp,%r2 ;# 3048 call_value_internal_symref
copy %r1,%r25 ;# 3046 reload_outsi+2/1
comib,= 0,%r28,L$0329 ;# 3052 bleu+1
copy %r11,%r26 ;# 3057 reload_outsi+2/1
ldil LR'L$C0016,%r1 ;# 8891 add_high_const+3
ldo RR'L$C0016(%r1),%r1 ;# 8892 movhi-2
.CALL ARGW0=GR,ARGW1=GR
bl strcmp,%r2 ;# 3061 call_value_internal_symref
copy %r1,%r25 ;# 3059 reload_outsi+2/1
comib,= 0,%r28,L$0329 ;# 3065 bleu+1
copy %r11,%r26 ;# 3070 reload_outsi+2/1
.CALL ARGW0=GR,ARGW1=GR
bl strcmp,%r2 ;# 3074 call_value_internal_symref
copy %r4,%r25 ;# 3072 reload_outsi+2/1
comib,= 0,%r28,L$0329 ;# 3078 bleu+1
copy %r11,%r26 ;# 3083 reload_outsi+2/1
ldil LR'L$C0025,%r1 ;# 8893 add_high_const+3
ldo RR'L$C0025(%r1),%r1 ;# 8894 movhi-2
.CALL ARGW0=GR,ARGW1=GR
bl strcmp,%r2 ;# 3087 call_value_internal_symref
copy %r1,%r25 ;# 3085 reload_outsi+2/1
comib,= 0,%r28,L$0329 ;# 3091 bleu+1
copy %r11,%r26 ;# 3096 reload_outsi+2/1
ldil LR'L$C0023,%r1 ;# 8895 add_high_const+3
ldo RR'L$C0023(%r1),%r1 ;# 8896 movhi-2
.CALL ARGW0=GR,ARGW1=GR
bl strcmp,%r2 ;# 3100 call_value_internal_symref
copy %r1,%r25 ;# 3098 reload_outsi+2/1
comib,= 0,%r28,L$0329 ;# 3104 bleu+1
copy %r11,%r26 ;# 3109 reload_outsi+2/1
ldil LR'L$C0024,%r1 ;# 8897 add_high_const+3
ldo RR'L$C0024(%r1),%r1 ;# 8898 movhi-2
.CALL ARGW0=GR,ARGW1=GR
bl strcmp,%r2 ;# 3113 call_value_internal_symref
copy %r1,%r25 ;# 3111 reload_outsi+2/1
comib,= 0,%r28,L$0329 ;# 3117 bleu+1
copy %r11,%r26 ;# 3122 reload_outsi+2/1
ldil LR'L$C0021,%r1 ;# 8899 add_high_const+3
ldo RR'L$C0021(%r1),%r1 ;# 8900 movhi-2
.CALL ARGW0=GR,ARGW1=GR
bl strcmp,%r2 ;# 3126 call_value_internal_symref
copy %r1,%r25 ;# 3124 reload_outsi+2/1
comib,= 0,%r28,L$0329 ;# 3130 bleu+1
copy %r11,%r26 ;# 3135 reload_outsi+2/1
ldil LR'L$C0019,%r1 ;# 8901 add_high_const+3
ldo RR'L$C0019(%r1),%r1 ;# 8902 movhi-2
.CALL ARGW0=GR,ARGW1=GR
bl strcmp,%r2 ;# 3139 call_value_internal_symref
copy %r1,%r25 ;# 3137 reload_outsi+2/1
comib,= 0,%r28,L$0329 ;# 3143 bleu+1
copy %r11,%r26 ;# 3148 reload_outsi+2/1
ldil LR'L$C0018,%r1 ;# 8903 add_high_const+3
ldo RR'L$C0018(%r1),%r1 ;# 8904 movhi-2
.CALL ARGW0=GR,ARGW1=GR
bl strcmp,%r2 ;# 3152 call_value_internal_symref
copy %r1,%r25 ;# 3150 reload_outsi+2/1
comib,<>,n 0,%r28,L$0900 ;# 3156 bleu+1
L$0329
ldw -296(%r30),%r19 ;# 3173 reload_outsi+2/5
comb,= %r16,%r19,L$0922 ;# 3175 bleu+1
ldo 1(%r19),%r19 ;# 3184 addsi3/2
comb,= %r16,%r19,L$0902 ;# 3214 bleu+1
stw %r19,-296(%r30) ;# 3186 reload_outsi+2/6
ldi 0,%r22 ;# 3227 reload_outsi+2/2
addil LR'__alnum-$global$,%r27 ;# 8596 pic2_lo_sum+1
copy %r1,%r2 ;# 8907 reload_outsi+2/1
addil LR'__ctype2-$global$,%r27 ;# 8598 pic2_lo_sum+1
copy %r1,%r23 ;# 8910 reload_outsi+2/1
addil LR'__ctype-$global$,%r27 ;# 8600 pic2_lo_sum+1
copy %r1,%r4 ;# 8913 reload_outsi+2/1
ldi 32,%r25 ;# 8605 reload_outsi+2/2
ldi 2,%r24 ;# 8607 reload_outsi+2/2
ldi 16,%r31 ;# 8609 reload_outsi+2/2
ldi 8,%r29 ;# 8611 reload_outsi+2/2
ldi 128,%r28 ;# 8613 reload_outsi+2/2
ldi 255,%r26 ;# 8615 reload_outsi+2/2
ldw -244(%r30),%r1 ;# 8916 reload_outsi+2/5
L$1173
comib,=,n 0,%r1,L$0343 ;# 3240 bleu+1
stw %r22,RR'__alnum-$global$(%r2) ;# 3244 reload_outsi+2/6
ldw RR'__ctype2-$global$(%r23),%r19 ;# 3248 reload_outsi+2/5
ldw RR'__ctype-$global$(%r4),%r21 ;# 3260 reload_outsi+2/5
addl %r19,%r22,%r19 ;# 3253 addsi3/1
addl %r21,%r22,%r21 ;# 3265 addsi3/1
ldb 0(%r19),%r20 ;# 3255 movqi+1/5
ldb 0(%r21),%r19 ;# 3267 movqi+1/5
extru %r20,31,1,%r20 ;# 3256 andsi3/1
and %r19,%r18,%r19 ;# 3270 andsi3/1
or %r20,%r19,%r20 ;# 3278 xordi3-1
comib,<> 0,%r20,L$1169 ;# 3280 bleu+1
extru %r22,31,8,%r19 ;# 3330 zero_extendqisi2/1
L$0343
ldw -236(%r30),%r1 ;# 8919 reload_outsi+2/5
comib,= 0,%r1,L$0344 ;# 3285 bleu+1
ldw RR'__ctype2-$global$(%r23),%r19 ;# 3289 reload_outsi+2/5
addl %r19,%r22,%r19 ;# 3290 addsi3/1
ldb 0(%r19),%r19 ;# 3292 movqi+1/5
bb,< %r19,31,L$1169 ;# 3296 bleu+3
extru %r22,31,8,%r19 ;# 3330 zero_extendqisi2/1
L$0344
ldw -228(%r30),%r1 ;# 8922 reload_outsi+2/5
comib,=,n 0,%r1,L$0345 ;# 3301 bleu+1
comb,= %r25,%r22,L$1169 ;# 3305 bleu+1
extru %r22,31,8,%r19 ;# 3330 zero_extendqisi2/1
comib,= 9,%r22,L$1170 ;# 3307 bleu+1
extru %r19,28,29,%r21 ;# 3332 lshrsi3/2
L$0345
ldw -220(%r30),%r1 ;# 8925 reload_outsi+2/5
comib,= 0,%r1,L$0341 ;# 3312 bleu+1
ldw RR'__ctype-$global$(%r4),%r19 ;# 3316 reload_outsi+2/5
addl %r19,%r22,%r19 ;# 3317 addsi3/1
ldb 0(%r19),%r19 ;# 3319 movqi+1/5
and %r19,%r25,%r19 ;# 3322 andsi3/1
comib,= 0,%r19,L$0341 ;# 3325 bleu+1
extru %r22,31,8,%r19 ;# 3330 zero_extendqisi2/1
L$1169
extru %r19,28,29,%r21 ;# 3332 lshrsi3/2
L$1170
addl %r6,%r21,%r21 ;# 3335 addsi3/1
extru %r19,31,3,%r19 ;# 3339 andsi3/1
subi 31,%r19,%r19 ;# 3340 subsi3/2
ldb 0(%r21),%r20 ;# 3343 movqi+1/5
mtsar %r19 ;# 8928 reload_outsi+2/7
vdepi -1,1,%r20 ;# 3348 vdepi_ior
stb %r20,0(%r21) ;# 3350 movqi+1/6
L$0341
ldw -212(%r30),%r1 ;# 8931 reload_outsi+2/5
comib,= 0,%r1,L$0348 ;# 3354 bleu+1
ldw RR'__ctype-$global$(%r4),%r19 ;# 3358 reload_outsi+2/5
addl %r19,%r22,%r19 ;# 3359 addsi3/1
ldb 0(%r19),%r19 ;# 3361 movqi+1/5
and %r19,%r18,%r19 ;# 3364 andsi3/1
comib,<> 0,%r19,L$1171 ;# 3367 bleu+1
extru %r22,31,8,%r19 ;# 3426 zero_extendqisi2/1
L$0348
ldw -204(%r30),%r1 ;# 8934 reload_outsi+2/5
comib,= 0,%r1,L$0349 ;# 3372 bleu+1
ldw RR'__ctype2-$global$(%r23),%r19 ;# 3376 reload_outsi+2/5
addl %r19,%r22,%r19 ;# 3377 addsi3/1
ldb 0(%r19),%r19 ;# 3379 movqi+1/5
and %r19,%r24,%r19 ;# 3382 andsi3/1
comib,<> 0,%r19,L$1171 ;# 3385 bleu+1
extru %r22,31,8,%r19 ;# 3426 zero_extendqisi2/1
L$0349
ldw -196(%r30),%r1 ;# 8937 reload_outsi+2/5
comib,= 0,%r1,L$0350 ;# 3390 bleu+1
ldw RR'__ctype-$global$(%r4),%r19 ;# 3394 reload_outsi+2/5
addl %r19,%r22,%r19 ;# 3395 addsi3/1
ldb 0(%r19),%r19 ;# 3397 movqi+1/5
and %r19,%r24,%r19 ;# 3400 andsi3/1
comib,<> 0,%r19,L$1171 ;# 3403 bleu+1
extru %r22,31,8,%r19 ;# 3426 zero_extendqisi2/1
L$0350
ldw -188(%r30),%r1 ;# 8940 reload_outsi+2/5
comib,= 0,%r1,L$0346 ;# 3408 bleu+1
ldw RR'__ctype2-$global$(%r23),%r19 ;# 3412 reload_outsi+2/5
addl %r19,%r22,%r19 ;# 3413 addsi3/1
ldb 0(%r19),%r19 ;# 3415 movqi+1/5
and %r19,%r18,%r19 ;# 3418 andsi3/1
comib,= 0,%r19,L$0346 ;# 3421 bleu+1
extru %r22,31,8,%r19 ;# 3426 zero_extendqisi2/1
L$1171
extru %r19,28,29,%r21 ;# 3428 lshrsi3/2
addl %r6,%r21,%r21 ;# 3431 addsi3/1
extru %r19,31,3,%r19 ;# 3435 andsi3/1
subi 31,%r19,%r19 ;# 3436 subsi3/2
ldb 0(%r21),%r20 ;# 3439 movqi+1/5
mtsar %r19 ;# 8943 reload_outsi+2/7
vdepi -1,1,%r20 ;# 3444 vdepi_ior
stb %r20,0(%r21) ;# 3446 movqi+1/6
L$0346
ldw -180(%r30),%r1 ;# 8946 reload_outsi+2/5
comib,= 0,%r1,L$0353 ;# 3450 bleu+1
ldw RR'__ctype-$global$(%r4),%r19 ;# 3454 reload_outsi+2/5
addl %r19,%r22,%r19 ;# 3455 addsi3/1
ldb 0(%r19),%r19 ;# 3457 movqi+1/5
and %r19,%r31,%r19 ;# 3460 andsi3/1
comib,<> 0,%r19,L$1172 ;# 3463 bleu+1
extru %r22,31,8,%r19 ;# 3520 zero_extendqisi2/1
L$0353
ldw -172(%r30),%r1 ;# 8949 reload_outsi+2/5
comib,= 0,%r1,L$0354 ;# 3468 bleu+1
ldw RR'__ctype-$global$(%r4),%r19 ;# 3472 reload_outsi+2/5
addl %r19,%r22,%r19 ;# 3473 addsi3/1
ldb 0(%r19),%r19 ;# 3475 movqi+1/5
and %r19,%r29,%r19 ;# 3478 andsi3/1
comib,<> 0,%r19,L$1172 ;# 3481 bleu+1
extru %r22,31,8,%r19 ;# 3520 zero_extendqisi2/1
L$0354
comib,= 0,%r13,L$0355 ;# 3486 bleu+1
ldw RR'__ctype-$global$(%r4),%r19 ;# 3490 reload_outsi+2/5
addl %r19,%r22,%r19 ;# 3491 addsi3/1
ldb 0(%r19),%r19 ;# 3493 movqi+1/5
bb,< %r19,31,L$1172 ;# 3497 bleu+3
extru %r22,31,8,%r19 ;# 3520 zero_extendqisi2/1
L$0355
comib,= 0,%r7,L$0339 ;# 3502 bleu+1
ldw RR'__ctype-$global$(%r4),%r19 ;# 3506 reload_outsi+2/5
addl %r19,%r22,%r19 ;# 3507 addsi3/1
ldb 0(%r19),%r19 ;# 3509 movqi+1/5
and %r19,%r28,%r19 ;# 3512 andsi3/1
comib,= 0,%r19,L$0339 ;# 3515 bleu+1
extru %r22,31,8,%r19 ;# 3520 zero_extendqisi2/1
L$1172
extru %r19,28,29,%r21 ;# 3522 lshrsi3/2
addl %r6,%r21,%r21 ;# 3525 addsi3/1
extru %r19,31,3,%r19 ;# 3529 andsi3/1
subi 31,%r19,%r19 ;# 3530 subsi3/2
ldb 0(%r21),%r20 ;# 3533 movqi+1/5
mtsar %r19 ;# 8952 reload_outsi+2/7
vdepi -1,1,%r20 ;# 3538 vdepi_ior
stb %r20,0(%r21) ;# 3540 movqi+1/6
L$0339
ldo 1(%r22),%r22 ;# 3546 addsi3/2
comb,>=,n %r26,%r22,L$1173 ;# 3233 bleu+1
ldw -244(%r30),%r1 ;# 8916 reload_outsi+2/5
bl L$0275,%r0 ;# 3559 jump
ldi 1,%r13 ;# 3556 reload_outsi+2/2
L$0328
ldi 255,%r19 ;# 8069 reload_outsi+2/2
L$1168
comb,= %r19,%r3,L$0359 ;# 8070 bleu+1
copy %r19,%r21 ;# 8595 reload_outsi+2/1
L$0360
ldo -1(%r3),%r20 ;# 3571 addsi3/2
ldw -296(%r30),%r19 ;# 3583 reload_outsi+2/5
extru %r20,31,8,%r3 ;# 3572 zero_extendqisi2/1
ldo -1(%r19),%r19 ;# 3584 addsi3/2
comb,<> %r21,%r3,L$0360 ;# 3577 bleu+1
stw %r19,-296(%r30) ;# 3588 reload_outsi+2/6
L$0359
ldb 11(%r6),%r19 ;# 3599 movqi+1/5
depi -1,28,1,%r19 ;# 3601 iorsi3+1/2
stb %r19,11(%r6) ;# 3603 movqi+1/6
ldb 7(%r6),%r19 ;# 3606 movqi+1/5
ldi 0,%r13 ;# 3613 reload_outsi+2/2
depi -1,29,1,%r19 ;# 3608 iorsi3+1/2
bl L$0275,%r0 ;# 3618 jump
stb %r19,7(%r6) ;# 3610 movqi+1/6
L$0309
ldi 0,%r13 ;# 3624 reload_outsi+2/2
L$1166
extru %r7,21+8-1,8,%r19 ;# 3627 extzv
addl %r6,%r19,%r19 ;# 3630 addsi3/1
extru %r7,31,3,%r20 ;# 3633 andsi3/1
L$0948
subi 31,%r20,%r20 ;# 3634 subsi3/2
ldb 0(%r19),%r21 ;# 3637 movqi+1/5
mtsar %r20 ;# 8955 reload_outsi+2/7
vdepi -1,1,%r21 ;# 3642 vdepi_ior
bl L$0275,%r0 ;# 3653 jump
stb %r21,0(%r19) ;# 3644 movqi+1/6
L$0276
ldb -1(%r6),%r20 ;# 8074 movqi+1/5
extru %r20,31,8,%r19 ;# 8075 zero_extendqisi2/1
comib,= 0,%r19,L$0364 ;# 8076 bleu+1
addl %r19,%r6,%r19 ;# 8079 addsi3/1
ldb -1(%r19),%r19 ;# 8082 zero_extendqisi2/2
comib,<> 0,%r19,L$0364 ;# 8083 bleu+1
ldo -1(%r20),%r19 ;# 8242 addsi3/2
bl L$1183,%r0 ;# 8253 jump
stb %r19,-1(%r6) ;# 3688 movqi+1/6
L$0365
ldo -1(%r19),%r19 ;# 3686 addsi3/2
stb %r19,-1(%r6) ;# 3688 movqi+1/6
L$1183
extru %r19,31,8,%r19 ;# 3662 zero_extendqisi2/1
comib,= 0,%r19,L$0364 ;# 3664 bleu+1
addl %r19,%r6,%r19 ;# 3668 addsi3/1
ldb -1(%r19),%r19 ;# 3672 zero_extendqisi2/2
comib,=,n 0,%r19,L$0365 ;# 3674 bleu+1
ldb -1(%r6),%r19 ;# 3683 movqi+1/5
L$0364
ldb -1(%r6),%r19 ;# 3700 zero_extendqisi2/2
bl L$0043,%r0 ;# 3705 jump
addl %r6,%r19,%r6 ;# 3701 addsi3/1
L$0368
bb,>=,n %r15,18,L$0076 ;# 3713 movsi-4
bl L$1181,%r0 ;# 3721 jump
ldw 24(%r5),%r19 ;# 3861 reload_outsi+2/5
L$0372
bb,>=,n %r15,18,L$0076 ;# 3730 movsi-4
bl,n L$0374,%r0 ;# 3738 jump
L$0376
bb,>=,n %r15,20,L$0076 ;# 3747 movsi-4
bl,n L$0378,%r0 ;# 3755 jump
L$0380
bb,>=,n %r15,16,L$0076 ;# 3764 movsi-4
bl,n L$0378,%r0 ;# 3772 jump
L$0383
and %r15,%r20,%r19 ;# 3779 andsi3/1
comb,= %r20,%r19,L$1174 ;# 3783 bleu+1
ldi -1,%r4 ;# 5074 reload_outsi+2/2
bl,n L$0076,%r0 ;# 3791 jump
L$0387
comb,=,n %r16,%r19,L$0903 ;# 3799 bleu+1
ldb 0(%r19),%r7 ;# 3831 zero_extendqisi2/2
ldo 1(%r19),%r19 ;# 3826 addsi3/2
stw %r19,-296(%r30) ;# 3828 reload_outsi+2/6
ldo -39(%r7),%r19 ;# 7446 addsi3/2
addi,uv -86,%r19,%r0 ;# 7447 casesi0
blr,n %r19,%r0
b,n L$0397
L$0817
bl L$0759,%r0 ;# 9437 switch_jump
ldw 0(%r5),%r4 ;# 8204 reload_outsi+2/5
L$1069
bl L$0395,%r0
nop ;# 9440 switch_jump
L$1070
bl L$0422,%r0
nop ;# 9443 switch_jump
L$1071
bl L$0397,%r0
nop ;# 9446 switch_jump
L$1072
bl L$0811,%r0
nop ;# 9449 switch_jump
L$1073
bl L$0397,%r0
nop ;# 9452 switch_jump
L$1074
bl L$0397,%r0
nop ;# 9455 switch_jump
L$1075
bl L$0397,%r0
nop ;# 9458 switch_jump
L$1076
bl L$0397,%r0
nop ;# 9461 switch_jump
L$1077
bl L$0397,%r0
nop ;# 9464 switch_jump
L$1078
bl L$0787,%r0
nop ;# 9467 switch_jump
L$1079
bl L$0787,%r0
nop ;# 9470 switch_jump
L$1080
bl L$0787,%r0
nop ;# 9473 switch_jump
L$1081
bl L$0787,%r0
nop ;# 9476 switch_jump
L$1082
bl L$0787,%r0
nop ;# 9479 switch_jump
L$1083
bl L$0787,%r0
nop ;# 9482 switch_jump
L$1084
bl L$0787,%r0
nop ;# 9485 switch_jump
L$1085
bl L$0787,%r0
nop ;# 9488 switch_jump
L$1086
bl L$0787,%r0
nop ;# 9491 switch_jump
L$1087
bl L$0397,%r0
nop ;# 9494 switch_jump
L$1088
bl L$0397,%r0
nop ;# 9497 switch_jump
L$1089
bl L$0659,%r0 ;# 9500 switch_jump
ldw 0(%r5),%r4 ;# 8164 reload_outsi+2/5
L$1090
bl L$0397,%r0
nop ;# 9503 switch_jump
L$1091
bl L$0679,%r0 ;# 9506 switch_jump
ldw 0(%r5),%r4 ;# 8172 reload_outsi+2/5
L$1092
bl L$0811,%r0
nop ;# 9509 switch_jump
L$1093
bl L$0397,%r0
nop ;# 9512 switch_jump
L$1094
bl L$0397,%r0
nop ;# 9515 switch_jump
L$1095
bl L$0719,%r0 ;# 9518 switch_jump
ldw 0(%r5),%r4 ;# 8188 reload_outsi+2/5
L$1096
bl L$0397,%r0
nop ;# 9521 switch_jump
L$1097
bl L$0397,%r0
nop ;# 9524 switch_jump
L$1098
bl L$0397,%r0
nop ;# 9527 switch_jump
L$1099
bl L$0397,%r0
nop ;# 9530 switch_jump
L$1100
bl L$0397,%r0
nop ;# 9533 switch_jump
L$1101
bl L$0397,%r0
nop ;# 9536 switch_jump
L$1102
bl L$0397,%r0
nop ;# 9539 switch_jump
L$1103
bl L$0397,%r0
nop ;# 9542 switch_jump
L$1104
bl L$0397,%r0
nop ;# 9545 switch_jump
L$1105
bl L$0397,%r0
nop ;# 9548 switch_jump
L$1106
bl L$0397,%r0
nop ;# 9551 switch_jump
L$1107
bl L$0397,%r0
nop ;# 9554 switch_jump
L$1108
bl L$0397,%r0
nop ;# 9557 switch_jump
L$1109
bl L$0397,%r0
nop ;# 9560 switch_jump
L$1110
bl L$0397,%r0
nop ;# 9563 switch_jump
L$1111
bl L$0397,%r0
nop ;# 9566 switch_jump
L$1112
bl L$0397,%r0
nop ;# 9569 switch_jump
L$1113
bl L$0397,%r0
nop ;# 9572 switch_jump
L$1114
bl L$0397,%r0
nop ;# 9575 switch_jump
L$1115
bl L$0397,%r0
nop ;# 9578 switch_jump
L$1116
bl L$0639,%r0 ;# 9581 switch_jump
ldw 0(%r5),%r4 ;# 8156 reload_outsi+2/5
L$1117
bl L$0397,%r0
nop ;# 9584 switch_jump
L$1118
bl L$0397,%r0
nop ;# 9587 switch_jump
L$1119
bl L$0397,%r0
nop ;# 9590 switch_jump
L$1120
bl L$0397,%r0
nop ;# 9593 switch_jump
L$1121
bl L$0397,%r0
nop ;# 9596 switch_jump
L$1122
bl L$0397,%r0
nop ;# 9599 switch_jump
L$1123
bl L$0397,%r0
nop ;# 9602 switch_jump
L$1124
bl L$0397,%r0
nop ;# 9605 switch_jump
L$1125
bl L$0739,%r0 ;# 9608 switch_jump
ldw 0(%r5),%r4 ;# 8196 reload_outsi+2/5
L$1126
bl L$0397,%r0
nop ;# 9611 switch_jump
L$1127
bl L$0699,%r0 ;# 9614 switch_jump
ldw 0(%r5),%r4 ;# 8180 reload_outsi+2/5
L$1128
bl L$0397,%r0
nop ;# 9617 switch_jump
L$1129
bl L$0397,%r0
nop ;# 9620 switch_jump
L$1130
bl L$0397,%r0
nop ;# 9623 switch_jump
L$1131
bl L$0397,%r0
nop ;# 9626 switch_jump
L$1132
bl L$0397,%r0
nop ;# 9629 switch_jump
L$1133
bl L$0397,%r0
nop ;# 9632 switch_jump
L$1134
bl L$0397,%r0
nop ;# 9635 switch_jump
L$1135
bl L$0397,%r0
nop ;# 9638 switch_jump
L$1136
bl L$0397,%r0
nop ;# 9641 switch_jump
L$1137
bl L$0397,%r0
nop ;# 9644 switch_jump
L$1138
bl L$0397,%r0
nop ;# 9647 switch_jump
L$1139
bl L$0397,%r0
nop ;# 9650 switch_jump
L$1140
bl L$0397,%r0
nop ;# 9653 switch_jump
L$1141
bl L$0397,%r0
nop ;# 9656 switch_jump
L$1142
bl L$0397,%r0
nop ;# 9659 switch_jump
L$1143
bl L$0397,%r0
nop ;# 9662 switch_jump
L$1144
bl L$0397,%r0
nop ;# 9665 switch_jump
L$1145
bl L$0397,%r0
nop ;# 9668 switch_jump
L$1146
bl L$0397,%r0
nop ;# 9671 switch_jump
L$1147
bl L$0397,%r0
nop ;# 9674 switch_jump
L$1148
bl L$0619,%r0 ;# 9677 switch_jump
ldw 0(%r5),%r4 ;# 8148 reload_outsi+2/5
L$1149
bl L$0397,%r0
nop ;# 9680 switch_jump
L$1150
bl L$0397,%r0
nop ;# 9683 switch_jump
L$1151
bl L$0397,%r0
nop ;# 9686 switch_jump
L$1152
bl L$0506,%r0
nop ;# 9689 switch_jump
L$1153
bl L$0472,%r0 ;# 9692 switch_jump
ldil L'33792,%r19 ;# 4724 add_high_const+3
L$1154
bl,n L$0397,%r0 ;# 7450 jump
L$0395
bb,<,n %r15,18,L$0397 ;# 3853 bleu+3
ldw 24(%r5),%r19 ;# 3861 reload_outsi+2/5
L$1181
ldo 1(%r19),%r19 ;# 3862 addsi3/2
stw %r19,24(%r5) ;# 3866 reload_outsi+2/6
ldw -304(%r30),%r20 ;# 3871 reload_outsi+2/5
ldw -260(%r30),%r1 ;# 8958 reload_outsi+2/5
ldw -308(%r30),%r19 ;# 3873 reload_outsi+2/5
ldo 1(%r1),%r1 ;# 3868 addsi3/2
comb,<> %r19,%r20,L$0398 ;# 3875 bleu+1
stw %r1,-260(%r30) ;# 8961 reload_outsi+2/6
zdep %r20,28,29,%r25 ;# 3885 ashlsi3+1
sh1addl %r20,%r25,%r25 ;# 3886 ashlsi3-2
ldw -312(%r30),%r26 ;# 3890 reload_outsi+2/5
.CALL ARGW0=GR,ARGW1=GR
bl realloc,%r2 ;# 3894 call_value_internal_symref
zdep %r25,29,30,%r25 ;# 3892 ashlsi3+1
comib,= 0,%r28,L$0953 ;# 3903 bleu+1
stw %r28,-312(%r30) ;# 3898 reload_outsi+2/6
ldw -308(%r30),%r19 ;# 3912 reload_outsi+2/5
zdep %r19,30,31,%r19 ;# 3914 ashlsi3+1
stw %r19,-308(%r30) ;# 3916 reload_outsi+2/6
L$0398
ldw -304(%r30),%r20 ;# 3921 reload_outsi+2/5
ldw -312(%r30),%r21 ;# 3923 reload_outsi+2/5
ldw 0(%r5),%r19 ;# 3933 reload_outsi+2/5
sh2addl %r20,%r20,%r20 ;# 3928 ashlsi3-2
sh2addl %r20,%r21,%r21 ;# 3931 ashlsi3-2
sub %r12,%r19,%r19 ;# 3934 subsi3/1
stw %r19,0(%r21) ;# 3936 reload_outsi+2/6
ldw -304(%r30),%r19 ;# 3939 reload_outsi+2/5
ldw -312(%r30),%r20 ;# 3941 reload_outsi+2/5
sh2addl %r19,%r19,%r19 ;# 3946 ashlsi3-2
comib,= 0,%r10,L$0400 ;# 3951 bleu+1
sh2addl %r19,%r20,%r20 ;# 3949 ashlsi3-2
ldw 0(%r5),%r19 ;# 3953 reload_outsi+2/5
sub %r10,%r19,%r19 ;# 3954 subsi3/1
ldo 1(%r19),%r19 ;# 3955 addsi3/2
bl L$0401,%r0 ;# 3958 jump
stw %r19,4(%r20) ;# 3957 reload_outsi+2/6
L$0400
stw %r0,4(%r20) ;# 3962 reload_outsi+2/6
L$0401
ldw -304(%r30),%r20 ;# 3966 reload_outsi+2/5
ldw -312(%r30),%r21 ;# 3968 reload_outsi+2/5
ldw 0(%r5),%r19 ;# 3978 reload_outsi+2/5
sh2addl %r20,%r20,%r20 ;# 3973 ashlsi3-2
sh2addl %r20,%r21,%r21 ;# 3976 ashlsi3-2
sub %r6,%r19,%r19 ;# 3979 subsi3/1
stw %r19,12(%r21) ;# 3981 reload_outsi+2/6
ldw -304(%r30),%r19 ;# 3984 reload_outsi+2/5
ldw -312(%r30),%r20 ;# 3986 reload_outsi+2/5
ldw -260(%r30),%r1 ;# 8964 reload_outsi+2/5
sh2addl %r19,%r19,%r19 ;# 3991 ashlsi3-2
sh2addl %r19,%r20,%r20 ;# 3994 ashlsi3-2
ldi 255,%r19 ;# 3999 reload_outsi+2/2
comb,<< %r19,%r1,L$0402 ;# 4001 bleu+1
stw %r1,16(%r20) ;# 3996 reload_outsi+2/6
ldw -304(%r30),%r20 ;# 4005 reload_outsi+2/5
ldw -312(%r30),%r21 ;# 4007 reload_outsi+2/5
ldw 0(%r5),%r19 ;# 4017 reload_outsi+2/5
sh2addl %r20,%r20,%r20 ;# 4012 ashlsi3-2
sh2addl %r20,%r21,%r21 ;# 4015 ashlsi3-2
sub %r6,%r19,%r19 ;# 4018 subsi3/1
ldo 2(%r19),%r19 ;# 4019 addsi3/2
stw %r19,8(%r21) ;# 4021 reload_outsi+2/6
ldw 0(%r5),%r4 ;# 8087 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 8090 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 8088 subsi3/1
ldo 3(%r19),%r19 ;# 8089 addsi3/2
comb,>>=,n %r20,%r19,L$0407 ;# 8091 bleu+1
ldil L'65536,%r3 ;# 8593 reload_outsi+2/3
L$0408
comb,= %r3,%r20,L$0944 ;# 4049 bleu+1
zdep %r20,30,31,%r19 ;# 4059 ashlsi3+1
comb,>>= %r3,%r19,L$0413 ;# 4067 bleu+1
stw %r19,4(%r5) ;# 4061 reload_outsi+2/6
stw %r3,4(%r5) ;# 4070 reload_outsi+2/6
L$0413
ldw 0(%r5),%r26 ;# 4077 reload_outsi+2/5
.CALL ARGW0=GR,ARGW1=GR
bl realloc,%r2 ;# 4081 call_value_internal_symref
ldw 4(%r5),%r25 ;# 4079 reload_outsi+2/5
comib,= 0,%r28,L$0953 ;# 4089 bleu+1
stw %r28,0(%r5) ;# 4085 reload_outsi+2/6
comb,= %r28,%r4,L$0406 ;# 4099 bleu+1
sub %r6,%r4,%r19 ;# 4101 subsi3/1
comib,= 0,%r10,L$0416 ;# 4110 bleu+1
addl %r28,%r19,%r6 ;# 4104 addsi3/1
sub %r10,%r4,%r19 ;# 4111 subsi3/1
addl %r28,%r19,%r10 ;# 4114 addsi3/1
L$0416
comib,= 0,%r8,L$0417 ;# 4117 bleu+1
sub %r8,%r4,%r19 ;# 4118 subsi3/1
addl %r28,%r19,%r8 ;# 4121 addsi3/1
L$0417
comib,= 0,%r9,L$0406 ;# 4124 bleu+1
sub %r9,%r4,%r19 ;# 4125 subsi3/1
addl %r28,%r19,%r9 ;# 4128 addsi3/1
L$0406
ldw 0(%r5),%r4 ;# 4029 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 4033 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 4030 subsi3/1
ldo 3(%r19),%r19 ;# 4031 addsi3/2
comb,<< %r20,%r19,L$0408
nop ;# 4035 bleu+1
L$0407
ldi 5,%r19 ;# 4150 movqi+1/2
stbs,ma %r19,1(%r6) ;# 4151 movqi+1/6
ldb -257(%r30),%r1 ;# 4156 movqi+1/5
stbs,ma %r1,1(%r6) ;# 8968 movqi+1/6
stbs,ma %r0,1(%r6) ;# 4159 movqi+1/6
L$0402
ldi 0,%r10 ;# 4182 reload_outsi+2/2
ldi 0,%r8 ;# 4185 reload_outsi+2/2
copy %r6,%r12 ;# 4188 reload_outsi+2/1
ldw -304(%r30),%r19 ;# 4174 reload_outsi+2/5
ldi 0,%r9 ;# 4191 reload_outsi+2/2
ldo 1(%r19),%r19 ;# 4175 addsi3/2
bl L$0043,%r0 ;# 4193 jump
stw %r19,-304(%r30) ;# 4179 reload_outsi+2/6
L$0422
bb,< %r15,18,L$0397 ;# 4201 bleu+3
ldw -304(%r30),%r19 ;# 4207 reload_outsi+2/5
comib,<>,n 0,%r19,L$0374 ;# 4209 bleu+1
bb,>=,n %r15,14,L$0950 ;# 4215 movsi-4
bl,n L$0397,%r0 ;# 4230 jump
L$0374
comib,=,n 0,%r10,L$0427 ;# 4237 bleu+1
ldw 0(%r5),%r4 ;# 8095 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 8098 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 8096 subsi3/1
ldo 1(%r19),%r19 ;# 8097 addsi3/2
comb,>>=,n %r20,%r19,L$0432 ;# 8099 bleu+1
ldil L'65536,%r3 ;# 8591 reload_outsi+2/3
L$0433
comb,= %r3,%r20,L$0944 ;# 4266 bleu+1
zdep %r20,30,31,%r19 ;# 4276 ashlsi3+1
comb,>>= %r3,%r19,L$0438 ;# 4284 bleu+1
stw %r19,4(%r5) ;# 4278 reload_outsi+2/6
stw %r3,4(%r5) ;# 4287 reload_outsi+2/6
L$0438
ldw 0(%r5),%r26 ;# 4294 reload_outsi+2/5
.CALL ARGW0=GR,ARGW1=GR
bl realloc,%r2 ;# 4298 call_value_internal_symref
ldw 4(%r5),%r25 ;# 4296 reload_outsi+2/5
comib,= 0,%r28,L$0953 ;# 4306 bleu+1
stw %r28,0(%r5) ;# 4302 reload_outsi+2/6
comb,= %r28,%r4,L$0431 ;# 4316 bleu+1
sub %r6,%r4,%r19 ;# 4318 subsi3/1
addl %r28,%r19,%r6 ;# 4321 addsi3/1
sub %r12,%r4,%r19 ;# 4322 subsi3/1
comib,= 0,%r10,L$0441 ;# 4327 bleu+1
addl %r28,%r19,%r12 ;# 4325 addsi3/1
sub %r10,%r4,%r19 ;# 4328 subsi3/1
addl %r28,%r19,%r10 ;# 4331 addsi3/1
L$0441
comib,= 0,%r8,L$0442 ;# 4334 bleu+1
sub %r8,%r4,%r19 ;# 4335 subsi3/1
addl %r28,%r19,%r8 ;# 4338 addsi3/1
L$0442
comib,= 0,%r9,L$0431 ;# 4341 bleu+1
sub %r9,%r4,%r19 ;# 4342 subsi3/1
addl %r28,%r19,%r9 ;# 4345 addsi3/1
L$0431
ldw 0(%r5),%r4 ;# 4246 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 4250 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 4247 subsi3/1
ldo 1(%r19),%r19 ;# 4248 addsi3/2
comb,<< %r20,%r19,L$0433
nop ;# 4252 bleu+1
L$0432
ldi 19,%r19 ;# 4367 movqi+1/2
stbs,ma %r19,1(%r6) ;# 4368 movqi+1/6
uaddcm %r6,%r10,%r24 ;# 4381 adddi3+1
ldi 13,%r26 ;# 4384 reload_outsi+2/2
copy %r10,%r25 ;# 4386 reload_outsi+2/1
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl store_op1,%r2 ;# 4390 call_internal_symref
ldo -3(%r24),%r24 ;# 4388 addsi3/2
L$0427
ldw -304(%r30),%r19 ;# 4395 reload_outsi+2/5
comib,<>,n 0,%r19,L$0447 ;# 4397 bleu+1
bb,<,n %r15,14,L$0076 ;# 4403 bleu+3
L$0950
.CALL ARGW0=GR
bl free,%r2 ;# 4414 call_internal_symref
ldw -312(%r30),%r26 ;# 4412 reload_outsi+2/5
bl L$0867,%r0 ;# 4418 jump
ldi 16,%r28 ;# 4416 reload_outsi+2/2
L$0447
ldo -1(%r19),%r19 ;# 4427 addsi3/2
stw %r19,-304(%r30) ;# 4431 reload_outsi+2/6
ldw -312(%r30),%r20 ;# 4436 reload_outsi+2/5
sh2addl %r19,%r19,%r19 ;# 4441 ashlsi3-2
sh2addl %r19,%r20,%r20 ;# 4444 ashlsi3-2
ldw 0(%r5),%r21 ;# 4446 reload_outsi+2/5
ldw 0(%r20),%r19 ;# 4448 reload_outsi+2/5
ldw 4(%r20),%r20 ;# 4464 reload_outsi+2/5
comib,= 0,%r20,L$0450 ;# 4466 bleu+1
addl %r21,%r19,%r12 ;# 4449 addsi3/1
addl %r21,%r20,%r19 ;# 4483 addsi3/1
bl L$0451,%r0 ;# 4485 jump
ldo -1(%r19),%r10 ;# 4484 addsi3/2
L$0450
ldi 0,%r10 ;# 4489 reload_outsi+2/2
L$0451
ldw -304(%r30),%r19 ;# 4493 reload_outsi+2/5
ldw -312(%r30),%r20 ;# 4495 reload_outsi+2/5
ldw 0(%r5),%r21 ;# 4505 reload_outsi+2/5
sh2addl %r19,%r19,%r19 ;# 4500 ashlsi3-2
sh2addl %r19,%r20,%r20 ;# 4503 ashlsi3-2
ldw 12(%r20),%r19 ;# 4507 reload_outsi+2/5
ldw 16(%r20),%r7 ;# 4523 reload_outsi+2/5
addl %r21,%r19,%r8 ;# 4508 addsi3/1
ldi 255,%r19 ;# 4529 reload_outsi+2/2
comb,<< %r19,%r7,L$0043 ;# 4531 bleu+1
ldi 0,%r9 ;# 4526 reload_outsi+2/2
ldw 8(%r20),%r19 ;# 4550 reload_outsi+2/5
ldw -260(%r30),%r1 ;# 8971 reload_outsi+2/5
addl %r21,%r19,%r19 ;# 4551 addsi3/1
sub %r1,%r7,%r20 ;# 4557 subsi3/1
stb %r20,0(%r19) ;# 4559 movqi+1/6
ldw 0(%r5),%r4 ;# 8103 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 8106 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 8104 subsi3/1
ldo 3(%r19),%r19 ;# 8105 addsi3/2
comb,>>=,n %r20,%r19,L$0457 ;# 8107 bleu+1
ldil L'65536,%r3 ;# 8589 reload_outsi+2/3
L$0458
comb,= %r3,%r20,L$0944 ;# 4587 bleu+1
zdep %r20,30,31,%r19 ;# 4597 ashlsi3+1
comb,>>= %r3,%r19,L$0463 ;# 4605 bleu+1
stw %r19,4(%r5) ;# 4599 reload_outsi+2/6
stw %r3,4(%r5) ;# 4608 reload_outsi+2/6
L$0463
ldw 0(%r5),%r26 ;# 4615 reload_outsi+2/5
.CALL ARGW0=GR,ARGW1=GR
bl realloc,%r2 ;# 4619 call_value_internal_symref
ldw 4(%r5),%r25 ;# 4617 reload_outsi+2/5
comib,= 0,%r28,L$0953 ;# 4627 bleu+1
stw %r28,0(%r5) ;# 4623 reload_outsi+2/6
comb,= %r28,%r4,L$0456 ;# 4637 bleu+1
sub %r6,%r4,%r19 ;# 4639 subsi3/1
addl %r28,%r19,%r6 ;# 4642 addsi3/1
sub %r12,%r4,%r19 ;# 4643 subsi3/1
comib,= 0,%r10,L$0466 ;# 4648 bleu+1
addl %r28,%r19,%r12 ;# 4646 addsi3/1
sub %r10,%r4,%r19 ;# 4649 subsi3/1
addl %r28,%r19,%r10 ;# 4652 addsi3/1
L$0466
comib,= 0,%r8,L$0467 ;# 4655 bleu+1
sub %r8,%r4,%r19 ;# 4656 subsi3/1
addl %r28,%r19,%r8 ;# 4659 addsi3/1
L$0467
comib,= 0,%r9,L$0456 ;# 4662 bleu+1
sub %r9,%r4,%r19 ;# 4663 subsi3/1
addl %r28,%r19,%r9 ;# 4666 addsi3/1
L$0456
ldw 0(%r5),%r4 ;# 4567 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 4571 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 4568 subsi3/1
ldo 3(%r19),%r19 ;# 4569 addsi3/2
comb,<< %r20,%r19,L$0458
nop ;# 4573 bleu+1
L$0457
ldi 6,%r19 ;# 4688 movqi+1/2
stbs,ma %r19,1(%r6) ;# 4689 movqi+1/6
stbs,ma %r7,1(%r6) ;# 4694 movqi+1/6
ldw -260(%r30),%r1 ;# 8974 reload_outsi+2/5
sub %r1,%r7,%r19 ;# 4700 subsi3/1
bl L$0043,%r0 ;# 4720 jump
stbs,ma %r19,1(%r6) ;# 4702 movqi+1/6
L$0472
ldo R'33792(%r19),%r19 ;# 4725 movhi-2
and %r15,%r19,%r19 ;# 4726 andsi3/1
comib,<>,n 0,%r19,L$0397 ;# 4728 bleu+1
L$0378
bb,<,n %r15,21,L$0076 ;# 4739 bleu+3
ldw 0(%r5),%r3 ;# 8111 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 8114 reload_outsi+2/5
sub %r6,%r3,%r19 ;# 8112 subsi3/1
ldo 3(%r19),%r19 ;# 8113 addsi3/2
comb,>>=,n %r20,%r19,L$0476 ;# 8115 bleu+1
ldil L'65536,%r4 ;# 8587 reload_outsi+2/3
L$0477
comb,= %r4,%r20,L$0944 ;# 4768 bleu+1
zdep %r20,30,31,%r19 ;# 4778 ashlsi3+1
comb,>>= %r4,%r19,L$0482 ;# 4786 bleu+1
stw %r19,4(%r5) ;# 4780 reload_outsi+2/6
stw %r4,4(%r5) ;# 4789 reload_outsi+2/6
L$0482
ldw 0(%r5),%r26 ;# 4796 reload_outsi+2/5
.CALL ARGW0=GR,ARGW1=GR
bl realloc,%r2 ;# 4800 call_value_internal_symref
ldw 4(%r5),%r25 ;# 4798 reload_outsi+2/5
comib,= 0,%r28,L$0953 ;# 4808 bleu+1
stw %r28,0(%r5) ;# 4804 reload_outsi+2/6
comb,= %r28,%r3,L$0475 ;# 4818 bleu+1
sub %r6,%r3,%r19 ;# 4820 subsi3/1
addl %r28,%r19,%r6 ;# 4823 addsi3/1
sub %r12,%r3,%r19 ;# 4824 subsi3/1
comib,= 0,%r10,L$0485 ;# 4829 bleu+1
addl %r28,%r19,%r12 ;# 4827 addsi3/1
sub %r10,%r3,%r19 ;# 4830 subsi3/1
addl %r28,%r19,%r10 ;# 4833 addsi3/1
L$0485
comib,= 0,%r8,L$0486 ;# 4836 bleu+1
sub %r8,%r3,%r19 ;# 4837 subsi3/1
addl %r28,%r19,%r8 ;# 4840 addsi3/1
L$0486
comib,= 0,%r9,L$0475 ;# 4843 bleu+1
sub %r9,%r3,%r19 ;# 4844 subsi3/1
addl %r28,%r19,%r9 ;# 4847 addsi3/1
L$0475
ldw 0(%r5),%r3 ;# 4748 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 4752 reload_outsi+2/5
sub %r6,%r3,%r19 ;# 4749 subsi3/1
ldo 3(%r19),%r19 ;# 4750 addsi3/2
comb,<< %r20,%r19,L$0477
nop ;# 4754 bleu+1
L$0476
ldi 14,%r26 ;# 4873 reload_outsi+2/2
copy %r12,%r25 ;# 4875 reload_outsi+2/1
sub %r6,%r25,%r24 ;# 4870 subsi3/1
ldo 3(%r24),%r24 ;# 4877 addsi3/2
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl insert_op1,%r2 ;# 4881 call_internal_symref
copy %r6,%r23 ;# 4879 reload_outsi+2/1
ldi 0,%r9 ;# 4884 reload_outsi+2/2
comib,= 0,%r10,L$0490 ;# 4889 bleu+1
ldo 3(%r6),%r6 ;# 4886 addsi3/2
ldi 13,%r26 ;# 4894 reload_outsi+2/2
copy %r10,%r25 ;# 4896 reload_outsi+2/1
sub %r6,%r25,%r24 ;# 4891 subsi3/1
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl store_op1,%r2 ;# 4900 call_internal_symref
ldo -3(%r24),%r24 ;# 4898 addsi3/2
L$0490
ldw 0(%r5),%r3 ;# 8119 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 8122 reload_outsi+2/5
sub %r6,%r3,%r19 ;# 8120 subsi3/1
ldo 3(%r19),%r19 ;# 8121 addsi3/2
comb,>>= %r20,%r19,L$0492 ;# 8123 bleu+1
copy %r6,%r10 ;# 4904 reload_outsi+2/1
ldil L'65536,%r4 ;# 8585 reload_outsi+2/3
L$0493
comb,= %r4,%r20,L$0944 ;# 4929 bleu+1
zdep %r20,30,31,%r19 ;# 4939 ashlsi3+1
comb,>>= %r4,%r19,L$0498 ;# 4947 bleu+1
stw %r19,4(%r5) ;# 4941 reload_outsi+2/6
stw %r4,4(%r5) ;# 4950 reload_outsi+2/6
L$0498
ldw 0(%r5),%r26 ;# 4957 reload_outsi+2/5
.CALL ARGW0=GR,ARGW1=GR
bl realloc,%r2 ;# 4961 call_value_internal_symref
ldw 4(%r5),%r25 ;# 4959 reload_outsi+2/5
comib,= 0,%r28,L$0953 ;# 4969 bleu+1
stw %r28,0(%r5) ;# 4965 reload_outsi+2/6
comb,= %r28,%r3,L$0491 ;# 4979 bleu+1
sub %r6,%r3,%r19 ;# 4981 subsi3/1
comib,= 0,%r10,L$0501 ;# 4990 bleu+1
addl %r28,%r19,%r6 ;# 4984 addsi3/1
sub %r10,%r3,%r19 ;# 4991 subsi3/1
addl %r28,%r19,%r10 ;# 4994 addsi3/1
L$0501
comib,= 0,%r8,L$0502 ;# 4997 bleu+1
sub %r8,%r3,%r19 ;# 4998 subsi3/1
addl %r28,%r19,%r8 ;# 5001 addsi3/1
L$0502
comib,= 0,%r9,L$0491 ;# 5004 bleu+1
sub %r9,%r3,%r19 ;# 5005 subsi3/1
addl %r28,%r19,%r9 ;# 5008 addsi3/1
L$0491
ldw 0(%r5),%r3 ;# 4909 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 4913 reload_outsi+2/5
sub %r6,%r3,%r19 ;# 4910 subsi3/1
ldo 3(%r19),%r19 ;# 4911 addsi3/2
comb,<< %r20,%r19,L$0493
nop ;# 4915 bleu+1
L$0492
ldo 3(%r6),%r6 ;# 5030 addsi3/2
ldi 0,%r8 ;# 5033 reload_outsi+2/2
bl L$0043,%r0 ;# 5038 jump
copy %r6,%r12 ;# 5036 reload_outsi+2/1
L$0506
bb,>= %r15,22,L$0397 ;# 5046 movsi-4
ldi 4608,%r20 ;# 5048 reload_outsi+2/2
and %r15,%r20,%r19 ;# 5049 andsi3/1
comb,= %r20,%r19,L$0397 ;# 5053 bleu+1
ldw -296(%r30),%r20 ;# 5055 reload_outsi+2/5
ldw -276(%r30),%r1 ;# 8977 reload_outsi+2/5
ldo -2(%r20),%r19 ;# 5056 addsi3/2
comb,<> %r1,%r19,L$1175 ;# 5058 bleu+1
ldi -1,%r4 ;# 5074 reload_outsi+2/2
comb,=,n %r16,%r20,L$0397 ;# 5062 bleu+1
L$1174
ldw -296(%r30),%r20 ;# 5079 reload_outsi+2/5
L$1175
copy %r4,%r11 ;# 5076 reload_outsi+2/1
comb,<> %r16,%r20,L$0517 ;# 5085 bleu+1
ldo -1(%r20),%r23 ;# 5080 addsi3/2
bb,>=,n %r15,19,L$0915 ;# 5092 movsi-4
bl L$1182,%r0 ;# 5107 jump
stw %r23,-296(%r30) ;# 5968 reload_outsi+2/6
L$0517
ldo 1(%r20),%r19 ;# 5134 addsi3/2
stw %r19,-296(%r30) ;# 5136 reload_outsi+2/6
comib,= 0,%r14,L$0515 ;# 5143 bleu+1
ldb 0(%r20),%r7 ;# 5139 zero_extendqisi2/2
addl %r14,%r7,%r19 ;# 5144 addsi3/1
ldb 0(%r19),%r7 ;# 5147 zero_extendqisi2/2
L$0515
addil LR'__ctype-$global$,%r27 ;# 8257 pic2_lo_sum+1
ldw RR'__ctype-$global$(%r1),%r21 ;# 8259 reload_outsi+2/5
addl %r21,%r7,%r19 ;# 8260 addsi3/1
ldb 0(%r19),%r19 ;# 8261 movqi+1/5
bb,>= %r19,29,L$0513 ;# 8265 movsi-4
ldi 4,%r20 ;# 8263 reload_outsi+2/2
copy %r20,%r22 ;# 8583 reload_outsi+2/1
L$0522
comiclr,< -1,%r11,%r0 ;# 8128 movsicc+1/1
ldi 0,%r11
sh2addl %r11,%r11,%r19 ;# 5188 ashlsi3-2
sh1addl %r19,%r7,%r19 ;# 5191 ashlsi3-2
ldw -296(%r30),%r20 ;# 5194 reload_outsi+2/5
comb,= %r16,%r20,L$0513 ;# 5196 bleu+1
ldo -48(%r19),%r11 ;# 5192 addsi3/2
ldo 1(%r20),%r19 ;# 5215 addsi3/2
stw %r19,-296(%r30) ;# 5217 reload_outsi+2/6
comib,= 0,%r14,L$0520 ;# 5224 bleu+1
ldb 0(%r20),%r7 ;# 5220 zero_extendqisi2/2
addl %r14,%r7,%r19 ;# 5225 addsi3/1
ldb 0(%r19),%r7 ;# 5228 zero_extendqisi2/2
L$0520
addl %r21,%r7,%r19 ;# 5166 addsi3/1
ldb 0(%r19),%r19 ;# 5168 movqi+1/5
and %r19,%r22,%r19 ;# 5172 andsi3/1
comib,<> 0,%r19,L$0522
nop ;# 5174 bleu+1
L$0513
ldi 44,%r19 ;# 5252 reload_outsi+2/2
comb,<> %r19,%r7,L$0532 ;# 5254 bleu+1
ldw -296(%r30),%r20 ;# 5259 reload_outsi+2/5
comb,= %r16,%r20,L$0533 ;# 5261 bleu+1
ldo 1(%r20),%r19 ;# 5278 addsi3/2
stw %r19,-296(%r30) ;# 5280 reload_outsi+2/6
comib,= 0,%r14,L$0535 ;# 5287 bleu+1
ldb 0(%r20),%r7 ;# 5283 zero_extendqisi2/2
addl %r14,%r7,%r19 ;# 5288 addsi3/1
ldb 0(%r19),%r7 ;# 5291 zero_extendqisi2/2
L$0535
addil LR'__ctype-$global$,%r27 ;# 8269 pic2_lo_sum+1
ldw RR'__ctype-$global$(%r1),%r21 ;# 8271 reload_outsi+2/5
addl %r21,%r7,%r19 ;# 8272 addsi3/1
ldb 0(%r19),%r19 ;# 8273 movqi+1/5
bb,>= %r19,29,L$0533 ;# 8277 movsi-4
ldi 4,%r20 ;# 8275 reload_outsi+2/2
copy %r20,%r22 ;# 8578 reload_outsi+2/1
L$0542
comiclr,< -1,%r4,%r0 ;# 8132 movsicc+1/1
ldi 0,%r4
sh2addl %r4,%r4,%r19 ;# 5332 ashlsi3-2
sh1addl %r19,%r7,%r19 ;# 5335 ashlsi3-2
ldw -296(%r30),%r20 ;# 5338 reload_outsi+2/5
comb,= %r16,%r20,L$0533 ;# 5340 bleu+1
ldo -48(%r19),%r4 ;# 5336 addsi3/2
ldo 1(%r20),%r19 ;# 5359 addsi3/2
stw %r19,-296(%r30) ;# 5361 reload_outsi+2/6
comib,= 0,%r14,L$0540 ;# 5368 bleu+1
ldb 0(%r20),%r7 ;# 5364 zero_extendqisi2/2
addl %r14,%r7,%r19 ;# 5369 addsi3/1
ldb 0(%r19),%r7 ;# 5372 zero_extendqisi2/2
L$0540
addl %r21,%r7,%r19 ;# 5310 addsi3/1
ldb 0(%r19),%r19 ;# 5312 movqi+1/5
and %r19,%r22,%r19 ;# 5316 andsi3/1
comib,<> 0,%r19,L$0542
nop ;# 5318 bleu+1
L$0533
comiclr,< -1,%r4,%r0 ;# 8136 beq-1/4
zdepi -1,31,15,%r4
bl,n L$0553,%r0 ;# 5401 jump
L$0532
copy %r11,%r4 ;# 5406 reload_outsi+2/1
L$0553
comib,> 0,%r11,L$0951 ;# 5410 bleu+1
zdepi -1,31,15,%r19 ;# 5412 reload_outsi+2/4
comb,<,n %r19,%r4,L$0951 ;# 5414 bleu+1
comb,<,n %r4,%r11,L$0951 ;# 5416 bleu+1
bb,< %r15,19,L$1176 ;# 5451 bleu+3
ldi 125,%r19 ;# 5514 reload_outsi+2/2
ldi 92,%r19 ;# 5455 reload_outsi+2/2
comb,<> %r19,%r7,L$0915 ;# 5457 bleu+1
ldw -296(%r30),%r20 ;# 5473 reload_outsi+2/5
comb,= %r16,%r20,L$0922 ;# 5475 bleu+1
ldo 1(%r20),%r19 ;# 5484 addsi3/2
stw %r19,-296(%r30) ;# 5486 reload_outsi+2/6
comib,= 0,%r14,L$0558 ;# 5493 bleu+1
ldb 0(%r20),%r7 ;# 5489 zero_extendqisi2/2
addl %r14,%r7,%r19 ;# 5494 addsi3/1
ldb 0(%r19),%r7 ;# 5497 zero_extendqisi2/2
L$0558
ldi 125,%r19 ;# 5514 reload_outsi+2/2
L$1176
comb,=,n %r19,%r7,L$0566 ;# 5516 bleu+1
L$0951
bb,<,n %r15,19,L$0511 ;# 5523 bleu+3
.CALL ARGW0=GR
bl free,%r2 ;# 5534 call_internal_symref
ldw -312(%r30),%r26 ;# 5532 reload_outsi+2/5
bl L$0867,%r0 ;# 5538 jump
ldi 10,%r28 ;# 5536 reload_outsi+2/2
L$0566
comib,<>,n 0,%r8,L$0569 ;# 5545 bleu+1
bb,<,n %r15,26,L$0917 ;# 5552 bleu+3
bb,>=,n %r15,27,L$0511 ;# 5571 movsi-4
copy %r6,%r8 ;# 5574 reload_outsi+2/1
L$0569
comib,<> 0,%r4,L$0574 ;# 5587 bleu+1
ldi 10,%r13 ;# 8980 reload_outsi+2/2
ldw 0(%r5),%r3 ;# 8139 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 8142 reload_outsi+2/5
sub %r6,%r3,%r19 ;# 8140 subsi3/1
ldo 3(%r19),%r19 ;# 8141 addsi3/2
comb,>>=,n %r20,%r19,L$0576 ;# 8143 bleu+1
ldil L'65536,%r4 ;# 8573 reload_outsi+2/3
L$0577
comb,= %r4,%r20,L$0944 ;# 5613 bleu+1
zdep %r20,30,31,%r19 ;# 5623 ashlsi3+1
comb,>>= %r4,%r19,L$0582 ;# 5631 bleu+1
stw %r19,4(%r5) ;# 5625 reload_outsi+2/6
stw %r4,4(%r5) ;# 5634 reload_outsi+2/6
L$0582
ldw 0(%r5),%r26 ;# 5641 reload_outsi+2/5
.CALL ARGW0=GR,ARGW1=GR
bl realloc,%r2 ;# 5645 call_value_internal_symref
ldw 4(%r5),%r25 ;# 5643 reload_outsi+2/5
comib,= 0,%r28,L$0953 ;# 5653 bleu+1
stw %r28,0(%r5) ;# 5649 reload_outsi+2/6
comb,= %r28,%r3,L$0575 ;# 5663 bleu+1
sub %r6,%r3,%r19 ;# 5665 subsi3/1
addl %r28,%r19,%r6 ;# 5668 addsi3/1
sub %r12,%r3,%r19 ;# 5669 subsi3/1
comib,= 0,%r10,L$0585 ;# 5674 bleu+1
addl %r28,%r19,%r12 ;# 5672 addsi3/1
sub %r10,%r3,%r19 ;# 5675 subsi3/1
addl %r28,%r19,%r10 ;# 5678 addsi3/1
L$0585
comib,= 0,%r8,L$0586 ;# 5681 bleu+1
sub %r8,%r3,%r19 ;# 5682 subsi3/1
addl %r28,%r19,%r8 ;# 5685 addsi3/1
L$0586
comib,= 0,%r9,L$0575 ;# 5688 bleu+1
sub %r9,%r3,%r19 ;# 5689 subsi3/1
addl %r28,%r19,%r9 ;# 5692 addsi3/1
L$0575
ldw 0(%r5),%r3 ;# 5593 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 5597 reload_outsi+2/5
sub %r6,%r3,%r19 ;# 5594 subsi3/1
ldo 3(%r19),%r19 ;# 5595 addsi3/2
comb,<< %r20,%r19,L$0577
nop ;# 5599 bleu+1
L$0576
ldi 12,%r26 ;# 5718 reload_outsi+2/2
copy %r8,%r25 ;# 5720 reload_outsi+2/1
sub %r6,%r8,%r24 ;# 5722 subsi3/1
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl insert_op1,%r2 ;# 5726 call_internal_symref
copy %r6,%r23 ;# 5724 reload_outsi+2/1
bl L$0590,%r0 ;# 5730 jump
ldo 3(%r6),%r6 ;# 5728 addsi3/2
L$0574
comiclr,> 2,%r4,%r0 ;# 8282 beq-1/2
ldi 20,%r13
ldw 0(%r5),%r3 ;# 8285 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 8288 reload_outsi+2/5
sub %r6,%r3,%r19 ;# 8286 subsi3/1
addl %r19,%r13,%r19 ;# 8287 addsi3/1
comb,>>=,n %r20,%r19,L$0868 ;# 8289 bleu+1
ldil L'65536,%r7 ;# 8571 reload_outsi+2/3
L$0595
comb,= %r7,%r20,L$0944 ;# 5769 bleu+1
zdep %r20,30,31,%r19 ;# 5779 ashlsi3+1
comb,>>= %r7,%r19,L$0600 ;# 5787 bleu+1
stw %r19,4(%r5) ;# 5781 reload_outsi+2/6
stw %r7,4(%r5) ;# 5790 reload_outsi+2/6
L$0600
ldw 0(%r5),%r26 ;# 5797 reload_outsi+2/5
.CALL ARGW0=GR,ARGW1=GR
bl realloc,%r2 ;# 5801 call_value_internal_symref
ldw 4(%r5),%r25 ;# 5799 reload_outsi+2/5
comib,= 0,%r28,L$0953 ;# 5809 bleu+1
stw %r28,0(%r5) ;# 5805 reload_outsi+2/6
comb,= %r28,%r3,L$0593 ;# 5819 bleu+1
sub %r6,%r3,%r19 ;# 5821 subsi3/1
addl %r28,%r19,%r6 ;# 5824 addsi3/1
sub %r12,%r3,%r19 ;# 5825 subsi3/1
comib,= 0,%r10,L$0603 ;# 5830 bleu+1
addl %r28,%r19,%r12 ;# 5828 addsi3/1
sub %r10,%r3,%r19 ;# 5831 subsi3/1
addl %r28,%r19,%r10 ;# 5834 addsi3/1
L$0603
comib,= 0,%r8,L$0604 ;# 5837 bleu+1
sub %r8,%r3,%r19 ;# 5838 subsi3/1
addl %r28,%r19,%r8 ;# 5841 addsi3/1
L$0604
comib,= 0,%r9,L$0593 ;# 5844 bleu+1
sub %r9,%r3,%r19 ;# 5845 subsi3/1
addl %r28,%r19,%r9 ;# 5848 addsi3/1
L$0593
ldw 0(%r5),%r3 ;# 5749 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 5753 reload_outsi+2/5
sub %r6,%r3,%r19 ;# 5750 subsi3/1
addl %r19,%r13,%r19 ;# 5751 addsi3/1
comb,<< %r20,%r19,L$0595
nop ;# 5755 bleu+1
L$0868
comib,>= 1,%r4,L$0608 ;# 5872 bleu+1
ldo 5(%r6),%r19 ;# 5870 addsi3/2
sub %r19,%r8,%r19 ;# 5874 subsi3/1
bl L$0609,%r0 ;# 5876 jump
ldo 2(%r19),%r24 ;# 5875 addsi3/2
L$0608
sub %r19,%r8,%r19 ;# 5879 subsi3/1
ldo -3(%r19),%r24 ;# 5880 addsi3/2
L$0609
ldi 20,%r26 ;# 5885 reload_outsi+2/2
copy %r8,%r25 ;# 5887 reload_outsi+2/1
copy %r11,%r23 ;# 5891 reload_outsi+2/1
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl insert_op2,%r2 ;# 5893 call_internal_symref
stw %r6,-52(%r30) ;# 5883 reload_outsi+2/6
ldo 5(%r6),%r6 ;# 5895 addsi3/2
ldi 22,%r26 ;# 5900 reload_outsi+2/2
copy %r8,%r25 ;# 5902 reload_outsi+2/1
ldi 5,%r24 ;# 5904 reload_outsi+2/2
copy %r11,%r23 ;# 5906 reload_outsi+2/1
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl insert_op2,%r2 ;# 5908 call_internal_symref
stw %r6,-52(%r30) ;# 5898 reload_outsi+2/6
comib,>= 1,%r4,L$0590 ;# 5913 bleu+1
ldo 5(%r6),%r6 ;# 5910 addsi3/2
ldi 21,%r26 ;# 5921 reload_outsi+2/2
copy %r6,%r25 ;# 5923 reload_outsi+2/1
sub %r8,%r6,%r24 ;# 5917 subsi3/1
ldo 2(%r24),%r24 ;# 5925 addsi3/2
ldo -1(%r4),%r4 ;# 5919 addsi3/2
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl store_op2,%r2 ;# 5929 call_internal_symref
copy %r4,%r23 ;# 5927 reload_outsi+2/1
ldo 5(%r6),%r6 ;# 5931 addsi3/2
stw %r6,-52(%r30) ;# 5936 reload_outsi+2/6
ldi 22,%r26 ;# 5938 reload_outsi+2/2
copy %r8,%r25 ;# 5940 reload_outsi+2/1
sub %r6,%r8,%r24 ;# 5942 subsi3/1
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl insert_op2,%r2 ;# 5946 call_internal_symref
copy %r4,%r23 ;# 5944 reload_outsi+2/1
ldo 5(%r6),%r6 ;# 5948 addsi3/2
L$0590
bl L$0043,%r0 ;# 5963 jump
ldi 0,%r9 ;# 5956 reload_outsi+2/2
L$0511
stw %r23,-296(%r30) ;# 5968 reload_outsi+2/6
L$1182
ldw -296(%r30),%r20 ;# 5977 reload_outsi+2/5
comb,= %r16,%r20,L$0922 ;# 5979 bleu+1
ldo 1(%r20),%r21 ;# 5988 addsi3/2
ldb 0(%r20),%r20 ;# 5992 movqi+1/5
stw %r21,-296(%r30) ;# 5990 reload_outsi+2/6
comib,= 0,%r14,L$0612 ;# 5997 bleu+1
extru %r20,31,8,%r7 ;# 5993 zero_extendqisi2/1
addl %r14,%r7,%r19 ;# 5998 addsi3/1
ldb 0(%r19),%r7 ;# 6001 zero_extendqisi2/2
L$0612
bb,< %r15,19,L$0076 ;# 6019 bleu+3
ldw -276(%r30),%r1 ;# 8983 reload_outsi+2/5
comb,>>= %r1,%r21,L$0076 ;# 6025 bleu+1
extrs %r20,31,8,%r20 ;# 6030 extendqisi2
ldi 92,%r19 ;# 6032 reload_outsi+2/2
comb,=,n %r19,%r20,L$0397 ;# 6034 bleu+1
bl,n L$0076,%r0 ;# 6042 jump
L$0619
ldw 4(%r5),%r20 ;# 8151 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 8149 subsi3/1
ldo 1(%r19),%r19 ;# 8150 addsi3/2
comb,>>= %r20,%r19,L$0624 ;# 8152 bleu+1
copy %r6,%r8 ;# 6047 reload_outsi+2/1
ldil L'65536,%r3 ;# 8569 reload_outsi+2/3
L$0625
comb,= %r3,%r20,L$0944 ;# 6075 bleu+1
zdep %r20,30,31,%r19 ;# 6085 ashlsi3+1
comb,>>= %r3,%r19,L$0630 ;# 6093 bleu+1
stw %r19,4(%r5) ;# 6087 reload_outsi+2/6
stw %r3,4(%r5) ;# 6096 reload_outsi+2/6
L$0630
ldw 0(%r5),%r26 ;# 6103 reload_outsi+2/5
.CALL ARGW0=GR,ARGW1=GR
bl realloc,%r2 ;# 6107 call_value_internal_symref
ldw 4(%r5),%r25 ;# 6105 reload_outsi+2/5
comiclr,<> 0,%r28,%r0 ;# 6115 bleu+1
bl L$0953,%r0
stw %r28,0(%r5) ;# 6111 reload_outsi+2/6
comb,= %r28,%r4,L$0623 ;# 6125 bleu+1
sub %r6,%r4,%r19 ;# 6127 subsi3/1
addl %r28,%r19,%r6 ;# 6130 addsi3/1
sub %r12,%r4,%r19 ;# 6131 subsi3/1
comib,= 0,%r10,L$0633 ;# 6136 bleu+1
addl %r28,%r19,%r12 ;# 6134 addsi3/1
sub %r10,%r4,%r19 ;# 6137 subsi3/1
addl %r28,%r19,%r10 ;# 6140 addsi3/1
L$0633
comib,= 0,%r8,L$0634 ;# 6143 bleu+1
sub %r8,%r4,%r19 ;# 6144 subsi3/1
addl %r28,%r19,%r8 ;# 6147 addsi3/1
L$0634
comib,= 0,%r9,L$0623 ;# 6150 bleu+1
sub %r9,%r4,%r19 ;# 6151 subsi3/1
addl %r28,%r19,%r9 ;# 6154 addsi3/1
L$0623
ldw 0(%r5),%r4 ;# 6055 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 6059 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 6056 subsi3/1
ldo 1(%r19),%r19 ;# 6057 addsi3/2
comb,<< %r20,%r19,L$0625
nop ;# 6061 bleu+1
L$0624
ldi 23,%r19 ;# 6176 movqi+1/2
bl L$0043,%r0 ;# 6189 jump
stbs,ma %r19,1(%r6) ;# 6177 movqi+1/6
L$0639
ldw 4(%r5),%r20 ;# 8159 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 8157 subsi3/1
ldo 1(%r19),%r19 ;# 8158 addsi3/2
comb,>>= %r20,%r19,L$0644 ;# 8160 bleu+1
copy %r6,%r8 ;# 6194 reload_outsi+2/1
ldil L'65536,%r3 ;# 8567 reload_outsi+2/3
L$0645
comb,= %r3,%r20,L$0944 ;# 6222 bleu+1
zdep %r20,30,31,%r19 ;# 6232 ashlsi3+1
comb,>>= %r3,%r19,L$0650 ;# 6240 bleu+1
stw %r19,4(%r5) ;# 6234 reload_outsi+2/6
stw %r3,4(%r5) ;# 6243 reload_outsi+2/6
L$0650
ldw 0(%r5),%r26 ;# 6250 reload_outsi+2/5
.CALL ARGW0=GR,ARGW1=GR
bl realloc,%r2 ;# 6254 call_value_internal_symref
ldw 4(%r5),%r25 ;# 6252 reload_outsi+2/5
comiclr,<> 0,%r28,%r0 ;# 6262 bleu+1
bl L$0953,%r0
stw %r28,0(%r5) ;# 6258 reload_outsi+2/6
comb,= %r28,%r4,L$0643 ;# 6272 bleu+1
sub %r6,%r4,%r19 ;# 6274 subsi3/1
addl %r28,%r19,%r6 ;# 6277 addsi3/1
sub %r12,%r4,%r19 ;# 6278 subsi3/1
comib,= 0,%r10,L$0653 ;# 6283 bleu+1
addl %r28,%r19,%r12 ;# 6281 addsi3/1
sub %r10,%r4,%r19 ;# 6284 subsi3/1
addl %r28,%r19,%r10 ;# 6287 addsi3/1
L$0653
comib,= 0,%r8,L$0654 ;# 6290 bleu+1
sub %r8,%r4,%r19 ;# 6291 subsi3/1
addl %r28,%r19,%r8 ;# 6294 addsi3/1
L$0654
comib,= 0,%r9,L$0643 ;# 6297 bleu+1
sub %r9,%r4,%r19 ;# 6298 subsi3/1
addl %r28,%r19,%r9 ;# 6301 addsi3/1
L$0643
ldw 0(%r5),%r4 ;# 6202 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 6206 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 6203 subsi3/1
ldo 1(%r19),%r19 ;# 6204 addsi3/2
comb,<< %r20,%r19,L$0645
nop ;# 6208 bleu+1
L$0644
ldi 24,%r19 ;# 6323 movqi+1/2
bl L$0043,%r0 ;# 6336 jump
stbs,ma %r19,1(%r6) ;# 6324 movqi+1/6
L$0659
ldw 4(%r5),%r20 ;# 8167 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 8165 subsi3/1
ldo 1(%r19),%r19 ;# 8166 addsi3/2
comb,>>=,n %r20,%r19,L$0664 ;# 8168 bleu+1
ldil L'65536,%r3 ;# 8565 reload_outsi+2/3
L$0665
comb,= %r3,%r20,L$0944 ;# 6366 bleu+1
zdep %r20,30,31,%r19 ;# 6376 ashlsi3+1
comb,>>= %r3,%r19,L$0670 ;# 6384 bleu+1
stw %r19,4(%r5) ;# 6378 reload_outsi+2/6
stw %r3,4(%r5) ;# 6387 reload_outsi+2/6
L$0670
ldw 0(%r5),%r26 ;# 6394 reload_outsi+2/5
.CALL ARGW0=GR,ARGW1=GR
bl realloc,%r2 ;# 6398 call_value_internal_symref
ldw 4(%r5),%r25 ;# 6396 reload_outsi+2/5
comiclr,<> 0,%r28,%r0 ;# 6406 bleu+1
bl L$0953,%r0
stw %r28,0(%r5) ;# 6402 reload_outsi+2/6
comb,= %r28,%r4,L$0663 ;# 6416 bleu+1
sub %r6,%r4,%r19 ;# 6418 subsi3/1
addl %r28,%r19,%r6 ;# 6421 addsi3/1
sub %r12,%r4,%r19 ;# 6422 subsi3/1
comib,= 0,%r10,L$0673 ;# 6427 bleu+1
addl %r28,%r19,%r12 ;# 6425 addsi3/1
sub %r10,%r4,%r19 ;# 6428 subsi3/1
addl %r28,%r19,%r10 ;# 6431 addsi3/1
L$0673
comib,= 0,%r8,L$0674 ;# 6434 bleu+1
sub %r8,%r4,%r19 ;# 6435 subsi3/1
addl %r28,%r19,%r8 ;# 6438 addsi3/1
L$0674
comib,= 0,%r9,L$0663 ;# 6441 bleu+1
sub %r9,%r4,%r19 ;# 6442 subsi3/1
addl %r28,%r19,%r9 ;# 6445 addsi3/1
L$0663
ldw 0(%r5),%r4 ;# 6346 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 6350 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 6347 subsi3/1
ldo 1(%r19),%r19 ;# 6348 addsi3/2
comb,<< %r20,%r19,L$0665
nop ;# 6352 bleu+1
L$0664
ldi 25,%r19 ;# 6467 movqi+1/2
bl L$0043,%r0 ;# 6480 jump
stbs,ma %r19,1(%r6) ;# 6468 movqi+1/6
L$0679
ldw 4(%r5),%r20 ;# 8175 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 8173 subsi3/1
ldo 1(%r19),%r19 ;# 8174 addsi3/2
comb,>>=,n %r20,%r19,L$0684 ;# 8176 bleu+1
ldil L'65536,%r3 ;# 8563 reload_outsi+2/3
L$0685
comb,= %r3,%r20,L$0944 ;# 6510 bleu+1
zdep %r20,30,31,%r19 ;# 6520 ashlsi3+1
comb,>>= %r3,%r19,L$0690 ;# 6528 bleu+1
stw %r19,4(%r5) ;# 6522 reload_outsi+2/6
stw %r3,4(%r5) ;# 6531 reload_outsi+2/6
L$0690
ldw 0(%r5),%r26 ;# 6538 reload_outsi+2/5
.CALL ARGW0=GR,ARGW1=GR
bl realloc,%r2 ;# 6542 call_value_internal_symref
ldw 4(%r5),%r25 ;# 6540 reload_outsi+2/5
comiclr,<> 0,%r28,%r0 ;# 6550 bleu+1
bl L$0953,%r0
stw %r28,0(%r5) ;# 6546 reload_outsi+2/6
comb,= %r28,%r4,L$0683 ;# 6560 bleu+1
sub %r6,%r4,%r19 ;# 6562 subsi3/1
addl %r28,%r19,%r6 ;# 6565 addsi3/1
sub %r12,%r4,%r19 ;# 6566 subsi3/1
comib,= 0,%r10,L$0693 ;# 6571 bleu+1
addl %r28,%r19,%r12 ;# 6569 addsi3/1
sub %r10,%r4,%r19 ;# 6572 subsi3/1
addl %r28,%r19,%r10 ;# 6575 addsi3/1
L$0693
comib,= 0,%r8,L$0694 ;# 6578 bleu+1
sub %r8,%r4,%r19 ;# 6579 subsi3/1
addl %r28,%r19,%r8 ;# 6582 addsi3/1
L$0694
comib,= 0,%r9,L$0683 ;# 6585 bleu+1
sub %r9,%r4,%r19 ;# 6586 subsi3/1
addl %r28,%r19,%r9 ;# 6589 addsi3/1
L$0683
ldw 0(%r5),%r4 ;# 6490 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 6494 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 6491 subsi3/1
ldo 1(%r19),%r19 ;# 6492 addsi3/2
comb,<< %r20,%r19,L$0685
nop ;# 6496 bleu+1
L$0684
ldi 26,%r19 ;# 6611 movqi+1/2
bl L$0043,%r0 ;# 6624 jump
stbs,ma %r19,1(%r6) ;# 6612 movqi+1/6
L$0699
ldw 4(%r5),%r20 ;# 8183 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 8181 subsi3/1
ldo 1(%r19),%r19 ;# 8182 addsi3/2
comb,>>=,n %r20,%r19,L$0704 ;# 8184 bleu+1
ldil L'65536,%r3 ;# 8561 reload_outsi+2/3
L$0705
comb,= %r3,%r20,L$0944 ;# 6654 bleu+1
zdep %r20,30,31,%r19 ;# 6664 ashlsi3+1
comb,>>= %r3,%r19,L$0710 ;# 6672 bleu+1
stw %r19,4(%r5) ;# 6666 reload_outsi+2/6
stw %r3,4(%r5) ;# 6675 reload_outsi+2/6
L$0710
ldw 0(%r5),%r26 ;# 6682 reload_outsi+2/5
.CALL ARGW0=GR,ARGW1=GR
bl realloc,%r2 ;# 6686 call_value_internal_symref
ldw 4(%r5),%r25 ;# 6684 reload_outsi+2/5
comiclr,<> 0,%r28,%r0 ;# 6694 bleu+1
bl L$0953,%r0
stw %r28,0(%r5) ;# 6690 reload_outsi+2/6
comb,= %r28,%r4,L$0703 ;# 6704 bleu+1
sub %r6,%r4,%r19 ;# 6706 subsi3/1
addl %r28,%r19,%r6 ;# 6709 addsi3/1
sub %r12,%r4,%r19 ;# 6710 subsi3/1
comib,= 0,%r10,L$0713 ;# 6715 bleu+1
addl %r28,%r19,%r12 ;# 6713 addsi3/1
sub %r10,%r4,%r19 ;# 6716 subsi3/1
addl %r28,%r19,%r10 ;# 6719 addsi3/1
L$0713
comib,= 0,%r8,L$0714 ;# 6722 bleu+1
sub %r8,%r4,%r19 ;# 6723 subsi3/1
addl %r28,%r19,%r8 ;# 6726 addsi3/1
L$0714
comib,= 0,%r9,L$0703 ;# 6729 bleu+1
sub %r9,%r4,%r19 ;# 6730 subsi3/1
addl %r28,%r19,%r9 ;# 6733 addsi3/1
L$0703
ldw 0(%r5),%r4 ;# 6634 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 6638 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 6635 subsi3/1
ldo 1(%r19),%r19 ;# 6636 addsi3/2
comb,<< %r20,%r19,L$0705
nop ;# 6640 bleu+1
L$0704
ldi 27,%r19 ;# 6755 movqi+1/2
bl L$0043,%r0 ;# 6768 jump
stbs,ma %r19,1(%r6) ;# 6756 movqi+1/6
L$0719
ldw 4(%r5),%r20 ;# 8191 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 8189 subsi3/1
ldo 1(%r19),%r19 ;# 8190 addsi3/2
comb,>>=,n %r20,%r19,L$0724 ;# 8192 bleu+1
ldil L'65536,%r3 ;# 8559 reload_outsi+2/3
L$0725
comb,= %r3,%r20,L$0944 ;# 6798 bleu+1
zdep %r20,30,31,%r19 ;# 6808 ashlsi3+1
comb,>>= %r3,%r19,L$0730 ;# 6816 bleu+1
stw %r19,4(%r5) ;# 6810 reload_outsi+2/6
stw %r3,4(%r5) ;# 6819 reload_outsi+2/6
L$0730
ldw 0(%r5),%r26 ;# 6826 reload_outsi+2/5
.CALL ARGW0=GR,ARGW1=GR
bl realloc,%r2 ;# 6830 call_value_internal_symref
ldw 4(%r5),%r25 ;# 6828 reload_outsi+2/5
comiclr,<> 0,%r28,%r0 ;# 6838 bleu+1
bl L$0953,%r0
stw %r28,0(%r5) ;# 6834 reload_outsi+2/6
comb,= %r28,%r4,L$0723 ;# 6848 bleu+1
sub %r6,%r4,%r19 ;# 6850 subsi3/1
addl %r28,%r19,%r6 ;# 6853 addsi3/1
sub %r12,%r4,%r19 ;# 6854 subsi3/1
comib,= 0,%r10,L$0733 ;# 6859 bleu+1
addl %r28,%r19,%r12 ;# 6857 addsi3/1
sub %r10,%r4,%r19 ;# 6860 subsi3/1
addl %r28,%r19,%r10 ;# 6863 addsi3/1
L$0733
comib,= 0,%r8,L$0734 ;# 6866 bleu+1
sub %r8,%r4,%r19 ;# 6867 subsi3/1
addl %r28,%r19,%r8 ;# 6870 addsi3/1
L$0734
comib,= 0,%r9,L$0723 ;# 6873 bleu+1
sub %r9,%r4,%r19 ;# 6874 subsi3/1
addl %r28,%r19,%r9 ;# 6877 addsi3/1
L$0723
ldw 0(%r5),%r4 ;# 6778 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 6782 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 6779 subsi3/1
ldo 1(%r19),%r19 ;# 6780 addsi3/2
comb,<< %r20,%r19,L$0725
nop ;# 6784 bleu+1
L$0724
ldi 28,%r19 ;# 6899 movqi+1/2
bl L$0043,%r0 ;# 6912 jump
stbs,ma %r19,1(%r6) ;# 6900 movqi+1/6
L$0739
ldw 4(%r5),%r20 ;# 8199 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 8197 subsi3/1
ldo 1(%r19),%r19 ;# 8198 addsi3/2
comb,>>=,n %r20,%r19,L$0744 ;# 8200 bleu+1
ldil L'65536,%r3 ;# 8557 reload_outsi+2/3
L$0745
comb,= %r3,%r20,L$0944 ;# 6942 bleu+1
zdep %r20,30,31,%r19 ;# 6952 ashlsi3+1
comb,>>= %r3,%r19,L$0750 ;# 6960 bleu+1
stw %r19,4(%r5) ;# 6954 reload_outsi+2/6
stw %r3,4(%r5) ;# 6963 reload_outsi+2/6
L$0750
ldw 0(%r5),%r26 ;# 6970 reload_outsi+2/5
.CALL ARGW0=GR,ARGW1=GR
bl realloc,%r2 ;# 6974 call_value_internal_symref
ldw 4(%r5),%r25 ;# 6972 reload_outsi+2/5
comiclr,<> 0,%r28,%r0 ;# 6982 bleu+1
bl L$0953,%r0
stw %r28,0(%r5) ;# 6978 reload_outsi+2/6
comb,= %r28,%r4,L$0743 ;# 6992 bleu+1
sub %r6,%r4,%r19 ;# 6994 subsi3/1
addl %r28,%r19,%r6 ;# 6997 addsi3/1
sub %r12,%r4,%r19 ;# 6998 subsi3/1
comib,= 0,%r10,L$0753 ;# 7003 bleu+1
addl %r28,%r19,%r12 ;# 7001 addsi3/1
sub %r10,%r4,%r19 ;# 7004 subsi3/1
addl %r28,%r19,%r10 ;# 7007 addsi3/1
L$0753
comib,= 0,%r8,L$0754 ;# 7010 bleu+1
sub %r8,%r4,%r19 ;# 7011 subsi3/1
addl %r28,%r19,%r8 ;# 7014 addsi3/1
L$0754
comib,= 0,%r9,L$0743 ;# 7017 bleu+1
sub %r9,%r4,%r19 ;# 7018 subsi3/1
addl %r28,%r19,%r9 ;# 7021 addsi3/1
L$0743
ldw 0(%r5),%r4 ;# 6922 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 6926 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 6923 subsi3/1
ldo 1(%r19),%r19 ;# 6924 addsi3/2
comb,<< %r20,%r19,L$0745
nop ;# 6928 bleu+1
L$0744
ldi 10,%r19 ;# 7043 movqi+1/2
bl L$0043,%r0 ;# 7056 jump
stbs,ma %r19,1(%r6) ;# 7044 movqi+1/6
L$0759
ldw 4(%r5),%r20 ;# 8207 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 8205 subsi3/1
ldo 1(%r19),%r19 ;# 8206 addsi3/2
comb,>>=,n %r20,%r19,L$0764 ;# 8208 bleu+1
ldil L'65536,%r3 ;# 8555 reload_outsi+2/3
L$0765
comb,= %r3,%r20,L$0944 ;# 7086 bleu+1
zdep %r20,30,31,%r19 ;# 7096 ashlsi3+1
comb,>>= %r3,%r19,L$0770 ;# 7104 bleu+1
stw %r19,4(%r5) ;# 7098 reload_outsi+2/6
stw %r3,4(%r5) ;# 7107 reload_outsi+2/6
L$0770
ldw 0(%r5),%r26 ;# 7114 reload_outsi+2/5
.CALL ARGW0=GR,ARGW1=GR
bl realloc,%r2 ;# 7118 call_value_internal_symref
ldw 4(%r5),%r25 ;# 7116 reload_outsi+2/5
comiclr,<> 0,%r28,%r0 ;# 7126 bleu+1
bl L$0953,%r0
stw %r28,0(%r5) ;# 7122 reload_outsi+2/6
comb,= %r28,%r4,L$0763 ;# 7136 bleu+1
sub %r6,%r4,%r19 ;# 7138 subsi3/1
addl %r28,%r19,%r6 ;# 7141 addsi3/1
sub %r12,%r4,%r19 ;# 7142 subsi3/1
comib,= 0,%r10,L$0773 ;# 7147 bleu+1
addl %r28,%r19,%r12 ;# 7145 addsi3/1
sub %r10,%r4,%r19 ;# 7148 subsi3/1
addl %r28,%r19,%r10 ;# 7151 addsi3/1
L$0773
comib,= 0,%r8,L$0774 ;# 7154 bleu+1
sub %r8,%r4,%r19 ;# 7155 subsi3/1
addl %r28,%r19,%r8 ;# 7158 addsi3/1
L$0774
comib,= 0,%r9,L$0763 ;# 7161 bleu+1
sub %r9,%r4,%r19 ;# 7162 subsi3/1
addl %r28,%r19,%r9 ;# 7165 addsi3/1
L$0763
ldw 0(%r5),%r4 ;# 7066 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 7070 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 7067 subsi3/1
ldo 1(%r19),%r19 ;# 7068 addsi3/2
comb,<< %r20,%r19,L$0765
nop ;# 7072 bleu+1
L$0764
ldi 11,%r19 ;# 7187 movqi+1/2
bl L$0043,%r0 ;# 7200 jump
stbs,ma %r19,1(%r6) ;# 7188 movqi+1/6
L$0787
bb,< %r15,17,L$0076 ;# 7216 bleu+3
ldo -48(%r7),%r19 ;# 7224 addsi3/2
ldw -260(%r30),%r1 ;# 8986 reload_outsi+2/5
extru %r19,31,8,%r3 ;# 7225 zero_extendqisi2/1
comb,<< %r1,%r3,L$0939 ;# 7230 bleu+1
ldo -312(%r30),%r26 ;# 7244 addsi3/2
.CALL ARGW0=GR,ARGW1=GR
bl group_in_compile_stack,%r2 ;# 7248 call_value_internal_symref
copy %r3,%r25 ;# 7246 reload_outsi+2/1
extrs %r28,31,8,%r28 ;# 7251 extendqisi2
comib,<>,n 0,%r28,L$0076 ;# 7253 bleu+1
ldw 0(%r5),%r4 ;# 8212 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 8215 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 8213 subsi3/1
ldo 2(%r19),%r19 ;# 8214 addsi3/2
comb,>>= %r20,%r19,L$0795 ;# 8216 bleu+1
copy %r6,%r8 ;# 7260 reload_outsi+2/1
ldil L'65536,%r7 ;# 8553 reload_outsi+2/3
L$0796
comb,= %r7,%r20,L$0944 ;# 7288 bleu+1
zdep %r20,30,31,%r19 ;# 7298 ashlsi3+1
comb,>>= %r7,%r19,L$0801 ;# 7306 bleu+1
stw %r19,4(%r5) ;# 7300 reload_outsi+2/6
stw %r7,4(%r5) ;# 7309 reload_outsi+2/6
L$0801
ldw 0(%r5),%r26 ;# 7316 reload_outsi+2/5
.CALL ARGW0=GR,ARGW1=GR
bl realloc,%r2 ;# 7320 call_value_internal_symref
ldw 4(%r5),%r25 ;# 7318 reload_outsi+2/5
comiclr,<> 0,%r28,%r0 ;# 7328 bleu+1
bl L$0953,%r0
stw %r28,0(%r5) ;# 7324 reload_outsi+2/6
comb,= %r28,%r4,L$0794 ;# 7338 bleu+1
sub %r6,%r4,%r19 ;# 7340 subsi3/1
addl %r28,%r19,%r6 ;# 7343 addsi3/1
sub %r12,%r4,%r19 ;# 7344 subsi3/1
comib,= 0,%r10,L$0804 ;# 7349 bleu+1
addl %r28,%r19,%r12 ;# 7347 addsi3/1
sub %r10,%r4,%r19 ;# 7350 subsi3/1
addl %r28,%r19,%r10 ;# 7353 addsi3/1
L$0804
comib,= 0,%r8,L$0805 ;# 7356 bleu+1
sub %r8,%r4,%r19 ;# 7357 subsi3/1
addl %r28,%r19,%r8 ;# 7360 addsi3/1
L$0805
comib,= 0,%r9,L$0794 ;# 7363 bleu+1
sub %r9,%r4,%r19 ;# 7364 subsi3/1
addl %r28,%r19,%r9 ;# 7367 addsi3/1
L$0794
ldw 0(%r5),%r4 ;# 7268 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 7272 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 7269 subsi3/1
ldo 2(%r19),%r19 ;# 7270 addsi3/2
comb,<< %r20,%r19,L$0796
nop ;# 7274 bleu+1
L$0795
ldi 7,%r19 ;# 7389 movqi+1/2
stbs,ma %r19,1(%r6) ;# 7390 movqi+1/6
bl L$0043,%r0 ;# 7405 jump
stbs,ma %r3,1(%r6) ;# 7393 movqi+1/6
L$0811
bb,< %r15,30,L$0104
nop ;# 7414 bleu+3
L$0397
comib,= 0,%r14,L$0815 ;# 7429 bleu+1
addl %r14,%r7,%r19 ;# 7430 addsi3/1
bl L$0816,%r0 ;# 7434 jump
ldb 0(%r19),%r19 ;# 7433 zero_extendqisi2/2
L$0815
copy %r7,%r19 ;# 7438 reload_outsi+2/1
L$0816
copy %r19,%r7 ;# 7441 reload_outsi+2/1
L$0076
comib,=,n 0,%r9,L$0820 ;# 7460 bleu+1
ldb 0(%r9),%r20 ;# 7463 zero_extendqisi2/2
addl %r9,%r20,%r19 ;# 7464 addsi3/1
ldo 1(%r19),%r19 ;# 7465 addsi3/2
comb,<> %r6,%r19,L$0820 ;# 7467 bleu+1
ldi 255,%r19 ;# 7472 reload_outsi+2/2
comb,= %r19,%r20,L$0820 ;# 7474 bleu+1
ldw -296(%r30),%r21 ;# 7476 reload_outsi+2/5
ldb 0(%r21),%r19 ;# 7478 movqi+1/5
extrs %r19,31,8,%r20 ;# 7479 extendqisi2
ldi 42,%r19 ;# 7481 reload_outsi+2/2
comb,= %r19,%r20,L$0820 ;# 7483 bleu+1
ldi 94,%r19 ;# 7490 reload_outsi+2/2
comb,=,n %r19,%r20,L$0820 ;# 7492 bleu+1
bb,>= %r15,30,L$0821 ;# 7497 movsi-4
ldi 92,%r19 ;# 7504 reload_outsi+2/2
comb,<>,n %r19,%r20,L$0822 ;# 7506 bleu+1
ldb 1(%r21),%r19 ;# 7510 movqi+1/5
extrs %r19,31,8,%r20 ;# 7511 extendqisi2
L$0821
ldi 43,%r19 ;# 7534 reload_outsi+2/2
comb,= %r19,%r20,L$0820 ;# 7536 bleu+1
ldi 63,%r19 ;# 7543 reload_outsi+2/2
comb,=,n %r19,%r20,L$0820 ;# 7545 bleu+1
L$0822
bb,>=,n %r15,22,L$0819 ;# 7553 movsi-4
bb,>= %r15,19,L$0823 ;# 7558 movsi-4
ldw -296(%r30),%r19 ;# 7560 reload_outsi+2/5
ldb 0(%r19),%r19 ;# 7562 movqi+1/5
ldi 123,%r20 ;# 7565 reload_outsi+2/2
extrs %r19,31,8,%r19 ;# 7563 extendqisi2
comb,=,n %r20,%r19,L$0820 ;# 7567 bleu+1
ldw 0(%r5),%r4 ;# 8228 reload_outsi+2/5
bl,n L$1177,%r0 ;# 7568 jump
L$0823
ldw -296(%r30),%r21 ;# 7572 reload_outsi+2/5
ldb 0(%r21),%r19 ;# 7574 movqi+1/5
ldi 92,%r20 ;# 7577 reload_outsi+2/2
extrs %r19,31,8,%r19 ;# 7575 extendqisi2
comb,<>,n %r20,%r19,L$0819 ;# 7579 bleu+1
ldb 1(%r21),%r19 ;# 7583 movqi+1/5
ldi 123,%r20 ;# 7586 reload_outsi+2/2
extrs %r19,31,8,%r19 ;# 7584 extendqisi2
comb,<>,n %r20,%r19,L$0819 ;# 7588 bleu+1
L$0820
ldw 0(%r5),%r4 ;# 8220 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 8223 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 8221 subsi3/1
ldo 2(%r19),%r19 ;# 8222 addsi3/2
comb,>>= %r20,%r19,L$0829 ;# 8224 bleu+1
copy %r6,%r8 ;# 7596 reload_outsi+2/1
ldil L'65536,%r3 ;# 8551 reload_outsi+2/3
L$0830
comb,= %r3,%r20,L$0944 ;# 7624 bleu+1
zdep %r20,30,31,%r19 ;# 7634 ashlsi3+1
comb,>>= %r3,%r19,L$0835 ;# 7642 bleu+1
stw %r19,4(%r5) ;# 7636 reload_outsi+2/6
stw %r3,4(%r5) ;# 7645 reload_outsi+2/6
L$0835
ldw 0(%r5),%r26 ;# 7652 reload_outsi+2/5
.CALL ARGW0=GR,ARGW1=GR
bl realloc,%r2 ;# 7656 call_value_internal_symref
ldw 4(%r5),%r25 ;# 7654 reload_outsi+2/5
comiclr,<> 0,%r28,%r0 ;# 7664 bleu+1
bl L$0953,%r0
stw %r28,0(%r5) ;# 7660 reload_outsi+2/6
comb,= %r28,%r4,L$0828 ;# 7674 bleu+1
sub %r6,%r4,%r19 ;# 7676 subsi3/1
addl %r28,%r19,%r6 ;# 7679 addsi3/1
sub %r12,%r4,%r19 ;# 7680 subsi3/1
comib,= 0,%r10,L$0838 ;# 7685 bleu+1
addl %r28,%r19,%r12 ;# 7683 addsi3/1
sub %r10,%r4,%r19 ;# 7686 subsi3/1
addl %r28,%r19,%r10 ;# 7689 addsi3/1
L$0838
comib,= 0,%r8,L$0839 ;# 7692 bleu+1
sub %r8,%r4,%r19 ;# 7693 subsi3/1
addl %r28,%r19,%r8 ;# 7696 addsi3/1
L$0839
comib,= 0,%r9,L$0828 ;# 7699 bleu+1
sub %r9,%r4,%r19 ;# 7700 subsi3/1
addl %r28,%r19,%r9 ;# 7703 addsi3/1
L$0828
ldw 0(%r5),%r4 ;# 7604 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 7608 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 7605 subsi3/1
ldo 2(%r19),%r19 ;# 7606 addsi3/2
comb,<< %r20,%r19,L$0830
nop ;# 7610 bleu+1
L$0829
ldi 1,%r19 ;# 7725 movqi+1/2
stbs,ma %r19,1(%r6) ;# 7726 movqi+1/6
stbs,ma %r0,1(%r6) ;# 7729 movqi+1/6
ldo -1(%r6),%r9 ;# 7741 addsi3/2
L$0819
ldw 0(%r5),%r4 ;# 8228 reload_outsi+2/5
L$1177
ldw 4(%r5),%r20 ;# 8231 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 8229 subsi3/1
ldo 1(%r19),%r19 ;# 8230 addsi3/2
comb,>>=,n %r20,%r19,L$0848 ;# 8232 bleu+1
ldil L'65536,%r3 ;# 8549 reload_outsi+2/3
L$0849
comb,= %r3,%r20,L$0944 ;# 7771 bleu+1
zdep %r20,30,31,%r19 ;# 7781 ashlsi3+1
comb,>>= %r3,%r19,L$0854 ;# 7789 bleu+1
stw %r19,4(%r5) ;# 7783 reload_outsi+2/6
stw %r3,4(%r5) ;# 7792 reload_outsi+2/6
L$0854
ldw 0(%r5),%r26 ;# 7799 reload_outsi+2/5
.CALL ARGW0=GR,ARGW1=GR
bl realloc,%r2 ;# 7803 call_value_internal_symref
ldw 4(%r5),%r25 ;# 7801 reload_outsi+2/5
comiclr,<> 0,%r28,%r0 ;# 7811 bleu+1
bl L$0953,%r0
stw %r28,0(%r5) ;# 7807 reload_outsi+2/6
comb,= %r28,%r4,L$0847 ;# 7821 bleu+1
sub %r6,%r4,%r19 ;# 7823 subsi3/1
addl %r28,%r19,%r6 ;# 7826 addsi3/1
sub %r12,%r4,%r19 ;# 7827 subsi3/1
comib,= 0,%r10,L$0857 ;# 7832 bleu+1
addl %r28,%r19,%r12 ;# 7830 addsi3/1
sub %r10,%r4,%r19 ;# 7833 subsi3/1
addl %r28,%r19,%r10 ;# 7836 addsi3/1
L$0857
comib,= 0,%r8,L$0858 ;# 7839 bleu+1
sub %r8,%r4,%r19 ;# 7840 subsi3/1
addl %r28,%r19,%r8 ;# 7843 addsi3/1
L$0858
comib,= 0,%r9,L$0847 ;# 7846 bleu+1
sub %r9,%r4,%r19 ;# 7847 subsi3/1
addl %r28,%r19,%r9 ;# 7850 addsi3/1
L$0847
ldw 0(%r5),%r4 ;# 7751 reload_outsi+2/5
ldw 4(%r5),%r20 ;# 7755 reload_outsi+2/5
sub %r6,%r4,%r19 ;# 7752 subsi3/1
ldo 1(%r19),%r19 ;# 7753 addsi3/2
comb,<< %r20,%r19,L$0849
nop ;# 7757 bleu+1
L$0848
stbs,ma %r7,1(%r6) ;# 7872 movqi+1/6
ldb 0(%r9),%r19 ;# 7885 movqi+1/5
ldo 1(%r19),%r19 ;# 7888 addsi3/2
stb %r19,0(%r9) ;# 7890 movqi+1/6
L$0043
ldw -296(%r30),%r19 ;# 2328 reload_outsi+2/5
L$1161
comclr,= %r16,%r19,%r0 ;# 258 bleu+1
bl L$1178,%r0
ldw -296(%r30),%r19 ;# 2334 reload_outsi+2/5
L$0044
comib,= 0,%r10,L$0865 ;# 7913 bleu+1
ldi 13,%r26 ;# 7918 reload_outsi+2/2
copy %r10,%r25 ;# 7920 reload_outsi+2/1
sub %r6,%r25,%r24 ;# 7915 subsi3/1
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl store_op1,%r2 ;# 7924 call_internal_symref
ldo -3(%r24),%r24 ;# 7922 addsi3/2
L$0865
ldw -304(%r30),%r19 ;# 7928 reload_outsi+2/5
comib,<>,n 0,%r19,L$0866 ;# 7930 bleu+1
.CALL ARGW0=GR
bl free,%r2 ;# 7946 call_internal_symref
ldw -312(%r30),%r26 ;# 7944 reload_outsi+2/5
ldw 0(%r5),%r19 ;# 7949 reload_outsi+2/5
ldi 0,%r28 ;# 7955 reload_outsi+2/2
sub %r6,%r19,%r19 ;# 7950 subsi3/1
bl L$0867,%r0 ;# 7957 jump
stw %r19,8(%r5) ;# 7952 reload_outsi+2/6
L$0895
.CALL ARGW0=GR
bl free,%r2 ;# 2269 call_internal_symref
ldw -312(%r30),%r26 ;# 2267 reload_outsi+2/5
bl L$0867,%r0 ;# 2273 jump
ldi 11,%r28 ;# 2271 reload_outsi+2/2
L$0900
.CALL ARGW0=GR
bl free,%r2 ;# 3161 call_internal_symref
ldw -312(%r30),%r26 ;# 3159 reload_outsi+2/5
bl L$0867,%r0 ;# 3165 jump
ldi 4,%r28 ;# 3163 reload_outsi+2/2
L$0902
.CALL ARGW0=GR
bl free,%r2 ;# 3218 call_internal_symref
ldw -312(%r30),%r26 ;# 3216 reload_outsi+2/5
bl L$0867,%r0 ;# 3222 jump
ldi 7,%r28 ;# 3220 reload_outsi+2/2
L$0903
.CALL ARGW0=GR
bl free,%r2 ;# 3803 call_internal_symref
ldw -312(%r30),%r26 ;# 3801 reload_outsi+2/5
bl L$0867,%r0 ;# 3807 jump
ldi 5,%r28 ;# 3805 reload_outsi+2/2
L$0915
.CALL ARGW0=GR
bl free,%r2 ;# 5461 call_internal_symref
ldw -312(%r30),%r26 ;# 5459 reload_outsi+2/5
bl L$0867,%r0 ;# 5465 jump
ldi 9,%r28 ;# 5463 reload_outsi+2/2
L$0917
.CALL ARGW0=GR
bl free,%r2 ;# 5557 call_internal_symref
ldw -312(%r30),%r26 ;# 5555 reload_outsi+2/5
bl L$0867,%r0 ;# 5561 jump
ldi 13,%r28 ;# 5559 reload_outsi+2/2
L$0922
bl L$0867,%r0 ;# 5983 jump
ldi 14,%r28 ;# 5981 reload_outsi+2/2
L$0939
.CALL ARGW0=GR
bl free,%r2 ;# 7235 call_internal_symref
ldw -312(%r30),%r26 ;# 7233 reload_outsi+2/5
bl L$0867,%r0 ;# 7239 jump
ldi 6,%r28 ;# 7237 reload_outsi+2/2
L$0944
bl L$0867,%r0 ;# 7775 jump
ldi 15,%r28 ;# 7773 reload_outsi+2/2
L$0866
.CALL ARGW0=GR
bl free,%r2 ;# 7935 call_internal_symref
ldw -312(%r30),%r26 ;# 7933 reload_outsi+2/5
ldi 8,%r28 ;# 7937 reload_outsi+2/2
L$0867
ldw -340(%r30),%r2 ;# 9026 reload_outsi+2/5
ldw -168(%r30),%r18 ;# 9028 reload_outsi+2/5
ldw -164(%r30),%r17 ;# 9030 reload_outsi+2/5
ldw -160(%r30),%r16 ;# 9032 reload_outsi+2/5
ldw -156(%r30),%r15 ;# 9034 reload_outsi+2/5
ldw -152(%r30),%r14 ;# 9036 reload_outsi+2/5
ldw -148(%r30),%r13 ;# 9038 reload_outsi+2/5
ldw -144(%r30),%r12 ;# 9040 reload_outsi+2/5
ldw -140(%r30),%r11 ;# 9042 reload_outsi+2/5
ldw -136(%r30),%r10 ;# 9044 reload_outsi+2/5
ldw -132(%r30),%r9 ;# 9046 reload_outsi+2/5
ldw -128(%r30),%r8 ;# 9048 reload_outsi+2/5
ldw -124(%r30),%r7 ;# 9050 reload_outsi+2/5
ldw -120(%r30),%r6 ;# 9052 reload_outsi+2/5
ldw -116(%r30),%r5 ;# 9054 reload_outsi+2/5
ldw -112(%r30),%r4 ;# 9056 reload_outsi+2/5
ldw -108(%r30),%r3 ;# 9058 reload_outsi+2/5
bv %r0(%r2) ;# 9061 return_internal
ldo -320(%r30),%r30 ;# 9060 addsi3/2
.EXIT
.PROCEND
.data
.align 1
re_syntax_table
.block 256
|
tactcomplabs/xbgas-binutils-gdb
| 1,143
|
gas/testsuite/gas/hppa/basic/fmemLRbug.s
|
.code
.export f
f:
.proc
.callinfo frame=0,no_calls
.entry
fstws %fr6R,0(%r26)
fstws %fr6L,4(%r26)
fstws %fr6,8(%r26)
fstds %fr6L,4(%r26)
fstds %fr6,8(%r26)
fldws 0(%r26),%fr6R
fldws 4(%r26),%fr6L
fldws 8(%r26),%fr6
fldds 4(%r26),%fr6L
fldds 8(%r26),%fr6
fstws %fr6R,0(%sr0,%r26)
fstws %fr6L,4(%sr0,%r26)
fstws %fr6,8(%sr0,%r26)
fstds %fr6L,4(%sr0,%r26)
fstds %fr6,8(%sr0,%r26)
fldws 0(%sr0,%r26),%fr6R
fldws 4(%sr0,%r26),%fr6L
fldws 8(%sr0,%r26),%fr6
fldds 4(%sr0,%r26),%fr6L
fldds 8(%sr0,%r26),%fr6
fstwx %fr6R,%r25(%r26)
fstwx %fr6L,%r25(%r26)
fstwx %fr6,%r25(%r26)
fstdx %fr6L,%r25(%r26)
fstdx %fr6,%r25(%r26)
fldwx %r25(%r26),%fr6R
fldwx %r25(%r26),%fr6L
fldwx %r25(%r26),%fr6
flddx %r25(%r26),%fr6L
flddx %r25(%r26),%fr6
fstwx %fr6R,%r25(%sr0,%r26)
fstwx %fr6L,%r25(%sr0,%r26)
fstwx %fr6,%r25(%sr0,%r26)
fstdx %fr6L,%r25(%sr0,%r26)
fstdx %fr6,%r25(%sr0,%r26)
fldwx %r25(%sr0,%r26),%fr6R
fldwx %r25(%sr0,%r26),%fr6L
fldwx %r25(%sr0,%r26),%fr6
flddx %r25(%sr0,%r26),%fr6L
flddx %r25(%sr0,%r26),%fr6
bv %r0(%r2)
nop
.exit
.procend
|
tactcomplabs/xbgas-binutils-gdb
| 2,409
|
gas/testsuite/gas/hppa/basic/add2.s
|
.LEVEL 2.0
.code
.align 4
; Basic add/sh?add instruction tests.
;
; We could/should test some of the corner cases for register and
; immediate fields. We should also check the assorted field
; selectors to make sure they're handled correctly.
add,* %r4,%r5,%r6
add,*= %r4,%r5,%r6
add,*< %r4,%r5,%r6
add,*<= %r4,%r5,%r6
add,*nuv %r4,%r5,%r6
add,*znv %r4,%r5,%r6
add,*sv %r4,%r5,%r6
add,*od %r4,%r5,%r6
add,*tr %r4,%r5,%r6
add,*<> %r4,%r5,%r6
add,*>= %r4,%r5,%r6
add,*> %r4,%r5,%r6
add,*uv %r4,%r5,%r6
add,*vnz %r4,%r5,%r6
add,*nsv %r4,%r5,%r6
add,*ev %r4,%r5,%r6
add,l,* %r4,%r5,%r6
add,l,*= %r4,%r5,%r6
add,l,*< %r4,%r5,%r6
add,l,*<= %r4,%r5,%r6
add,l,*nuv %r4,%r5,%r6
add,l,*znv %r4,%r5,%r6
add,l,*sv %r4,%r5,%r6
add,l,*od %r4,%r5,%r6
add,l,*tr %r4,%r5,%r6
add,l,*<> %r4,%r5,%r6
add,l,*>= %r4,%r5,%r6
add,l,*> %r4,%r5,%r6
add,l,*uv %r4,%r5,%r6
add,l,*vnz %r4,%r5,%r6
add,l,*nsv %r4,%r5,%r6
add,l,*ev %r4,%r5,%r6
add,tsv,* %r4,%r5,%r6
add,tsv,*= %r4,%r5,%r6
add,tsv,*< %r4,%r5,%r6
add,tsv,*<= %r4,%r5,%r6
add,tsv,*nuv %r4,%r5,%r6
add,tsv,*znv %r4,%r5,%r6
add,tsv,*sv %r4,%r5,%r6
add,tsv,*od %r4,%r5,%r6
add,tsv,*tr %r4,%r5,%r6
add,tsv,*<> %r4,%r5,%r6
add,tsv,*>= %r4,%r5,%r6
add,tsv,*> %r4,%r5,%r6
add,tsv,*uv %r4,%r5,%r6
add,tsv,*vnz %r4,%r5,%r6
add,tsv,*nsv %r4,%r5,%r6
add,tsv,*ev %r4,%r5,%r6
add,dc,* %r4,%r5,%r6
add,dc,*= %r4,%r5,%r6
add,dc,*< %r4,%r5,%r6
add,dc,*<= %r4,%r5,%r6
add,dc,*nuv %r4,%r5,%r6
add,dc,*znv %r4,%r5,%r6
add,dc,*sv %r4,%r5,%r6
add,dc,*od %r4,%r5,%r6
add,dc,*tr %r4,%r5,%r6
add,dc,*<> %r4,%r5,%r6
add,dc,*>= %r4,%r5,%r6
add,dc,*> %r4,%r5,%r6
add,dc,*uv %r4,%r5,%r6
add,dc,*vnz %r4,%r5,%r6
add,dc,*nsv %r4,%r5,%r6
add,dc,*ev %r4,%r5,%r6
add,dc,tsv,* %r4,%r5,%r6
add,dc,tsv,*= %r4,%r5,%r6
add,dc,tsv,*< %r4,%r5,%r6
add,dc,tsv,*<= %r4,%r5,%r6
add,dc,tsv,*nuv %r4,%r5,%r6
add,dc,tsv,*znv %r4,%r5,%r6
add,dc,tsv,*sv %r4,%r5,%r6
add,dc,tsv,*od %r4,%r5,%r6
add,tsv,dc,*tr %r4,%r5,%r6
add,tsv,dc,*<> %r4,%r5,%r6
add,tsv,dc,*>= %r4,%r5,%r6
add,tsv,dc,*> %r4,%r5,%r6
add,tsv,dc,*uv %r4,%r5,%r6
add,tsv,dc,*vnz %r4,%r5,%r6
add,tsv,dc,*nsv %r4,%r5,%r6
add,tsv,dc,*ev %r4,%r5,%r6
;; PR gas/11395: Check for the correct assembly
;; of unconditional 32-bit and 64-bit add instructions.
add %r1,%r1,%r1
add,dc %r1,%r1,%r1
|
tactcomplabs/xbgas-binutils-gdb
| 1,085
|
gas/testsuite/gas/hppa/basic/extract3.s
|
.LEVEL 2.0
.code
.align 4
; Basic immediate instruction tests.
;
; We could/should test some of the corner cases for register and
; immediate fields. We should also check the assorted field
; selectors to make sure they're handled correctly.
extrd,u,* %r4,10,5,%r6
extrd,u,*= %r4,10,5,%r6
extrd,u,*< %r4,10,5,%r6
extrd,u,*od %r4,10,5,%r6
extrd,u,*tr %r4,10,5,%r6
extrd,u,*<> %r4,10,5,%r6
extrd,u,*>= %r4,10,5,%r6
extrd,u,*ev %r4,10,5,%r6
extrd,s,* %r4,10,5,%r6
extrd,s,*= %r4,10,5,%r6
extrd,s,*< %r4,10,5,%r6
extrd,s,*od %r4,10,5,%r6
extrd,*tr %r4,10,5,%r6
extrd,*<> %r4,10,5,%r6
extrd,*>= %r4,10,5,%r6
extrd,*ev %r4,10,5,%r6
extrd,u,* %r4,%sar,5,%r6
extrd,u,*= %r4,%sar,5,%r6
extrd,u,*< %r4,%sar,5,%r6
extrd,u,*od %r4,%sar,5,%r6
extrd,u,*tr %r4,%sar,5,%r6
extrd,u,*<> %r4,%sar,5,%r6
extrd,u,*>= %r4,%sar,5,%r6
extrd,u,*ev %r4,%sar,5,%r6
extrd,s,* %r4,%sar,5,%r6
extrd,s,*= %r4,%sar,5,%r6
extrd,s,*< %r4,%sar,5,%r6
extrd,s,*od %r4,%sar,5,%r6
extrd,*tr %r4,%sar,5,%r6
extrd,*<> %r4,%sar,5,%r6
extrd,*>= %r4,%sar,5,%r6
extrd,*ev %r4,%sar,5,%r6
|
tactcomplabs/xbgas-binutils-gdb
| 1,732
|
gas/testsuite/gas/hppa/basic/deposit2.s
|
.code
.align 4
; Deposit instruction tests.
;
; We could/should test some of the corner cases for register and
; immediate fields. We should also check the assorted field
; selectors to make sure they're handled correctly.
depw,z %r4,5,10,%r6
depw,z,= %r4,5,10,%r6
depw,z,< %r4,5,10,%r6
depw,z,od %r4,5,10,%r6
depw,z,tr %r4,5,10,%r6
depw,z,<> %r4,5,10,%r6
depw,z,>= %r4,5,10,%r6
depw,z,ev %r4,5,10,%r6
depw %r4,5,10,%r6
depw,= %r4,5,10,%r6
depw,< %r4,5,10,%r6
depw,od %r4,5,10,%r6
depw,tr %r4,5,10,%r6
depw,<> %r4,5,10,%r6
depw,>= %r4,5,10,%r6
depw,ev %r4,5,10,%r6
depw,z %r4,%sar,5,%r6
depw,z,= %r4,%sar,5,%r6
depw,z,< %r4,%sar,5,%r6
depw,z,od %r4,%sar,5,%r6
depw,z,tr %r4,%sar,5,%r6
depw,z,<> %r4,%sar,5,%r6
depw,z,>= %r4,%sar,5,%r6
depw,z,ev %r4,%sar,5,%r6
depw %r4,%sar,5,%r6
depw,= %r4,%sar,5,%r6
depw,< %r4,%sar,5,%r6
depw,od %r4,%sar,5,%r6
depw,tr %r4,%sar,5,%r6
depw,<> %r4,%sar,5,%r6
depw,>= %r4,%sar,5,%r6
depw,ev %r4,%sar,5,%r6
depwi -1,%sar,5,%r6
depwi,= -1,%sar,5,%r6
depwi,< -1,%sar,5,%r6
depwi,od -1,%sar,5,%r6
depwi,tr -1,%sar,5,%r6
depwi,<> -1,%sar,5,%r6
depwi,>= -1,%sar,5,%r6
depwi,ev -1,%sar,5,%r6
depwi,z -1,%sar,5,%r6
depwi,z,= -1,%sar,5,%r6
depwi,z,< -1,%sar,5,%r6
depwi,z,od -1,%sar,5,%r6
depwi,z,tr -1,%sar,5,%r6
depwi,z,<> -1,%sar,5,%r6
depwi,z,>= -1,%sar,5,%r6
depwi,z,ev -1,%sar,5,%r6
depwi -1,4,10,%r6
depwi,= -1,4,10,%r6
depwi,< -1,4,10,%r6
depwi,od -1,4,10,%r6
depwi,tr -1,4,10,%r6
depwi,<> -1,4,10,%r6
depwi,>= -1,4,10,%r6
depwi,ev -1,4,10,%r6
depwi,z -1,4,10,%r6
depwi,z,= -1,4,10,%r6
depwi,z,< -1,4,10,%r6
depwi,z,od -1,4,10,%r6
depwi,z,tr -1,4,10,%r6
depwi,z,<> -1,4,10,%r6
depwi,z,>= -1,4,10,%r6
depwi,z,ev -1,4,10,%r6
|
tactcomplabs/xbgas-binutils-gdb
| 5,704
|
gas/testsuite/gas/hppa/basic/branch.s
|
.level 1.1
.code
.align 4
; More branching instructions than you ever knew what to do with.
;
; We could/should test some of the corner cases for register and
; immediate fields. We should also check the assorted field
; selectors to make sure they're handled correctly.
branch_tests:
bl branch_tests,%r2
bl,n branch_tests,%r2
b branch_tests
b,n branch_tests
gate branch_tests,%r2
gate,n branch_tests,%r2
blr %r4,%r2
blr,n %r4,%r2
blr %r4,%r0
blr,n %r4,%r0
bv %r0(%r2)
bv,n %r0(%r2)
be 0x1234(%sr1,%r2)
be,n 0x1234(%sr1,%r2)
ble 0x1234(%sr1,%r2)
ble,n 0x1234(%sr1,%r2)
movb_tests:
movb %r4,%r26,movb_tests
movb,= %r4,%r26,movb_tests
movb,< %r4,%r26,movb_tests
movb,od %r4,%r26,movb_tests
movb,tr %r4,%r26,movb_tests
movb,<> %r4,%r26,movb_tests
movb,>= %r4,%r26,movb_tests
movb,ev %r4,%r26,movb_tests
movb_nullified_tests:
movb,n %r4,%r26,movb_tests
movb,=,n %r4,%r26,movb_tests
movb,<,n %r4,%r26,movb_tests
movb,od,n %r4,%r26,movb_tests
movb,tr,n %r4,%r26,movb_tests
movb,<>,n %r4,%r26,movb_tests
movb,>=,n %r4,%r26,movb_tests
movb,ev,n %r4,%r26,movb_tests
movib_tests:
movib 5,%r26,movib_tests
movib,= 5,%r26,movib_tests
movib,< 5,%r26,movib_tests
movib,od 5,%r26,movib_tests
movib,tr 5,%r26,movib_tests
movib,<> 5,%r26,movib_tests
movib,>= 5,%r26,movib_tests
movib,ev 5,%r26,movib_tests
movib_nullified_tests:
movib,n 5,%r26,movib_tests
movib,=,n 5,%r26,movib_tests
movib,<,n 5,%r26,movib_tests
movib,od,n 5,%r26,movib_tests
movib,tr,n 5,%r26,movib_tests
movib,<>,n 5,%r26,movib_tests
movib,>=,n 5,%r26,movib_tests
movib,ev,n 5,%r26,movib_tests
comb_tests:
comb %r0,%r4,comb_tests
comb,= %r0,%r4,comb_tests
comb,< %r0,%r4,comb_tests
comb,<= %r0,%r4,comb_tests
comb,<< %r0,%r4,comb_tests
comb,<<= %r0,%r4,comb_tests
comb,sv %r0,%r4,comb_tests
comb,od %r0,%r4,comb_tests
comb,tr %r0,%r4,comb_tests
comb,<> %r0,%r4,comb_tests
comb,>= %r0,%r4,comb_tests
comb,> %r0,%r4,comb_tests
comb,>>= %r0,%r4,comb_tests
comb,>> %r0,%r4,comb_tests
comb,nsv %r0,%r4,comb_tests
comb,ev %r0,%r4,comb_tests
comb_nullified_tests:
comb,n %r0,%r4,comb_tests
comb,=,n %r0,%r4,comb_tests
comb,<,n %r0,%r4,comb_tests
comb,<=,n %r0,%r4,comb_tests
comb,<<,n %r0,%r4,comb_tests
comb,<<=,n %r0,%r4,comb_tests
comb,sv,n %r0,%r4,comb_tests
comb,od,n %r0,%r4,comb_tests
comb,tr,n %r0,%r4,comb_tests
comb,<>,n %r0,%r4,comb_tests
comb,>=,n %r0,%r4,comb_tests
comb,>,n %r0,%r4,comb_tests
comb,>>=,n %r0,%r4,comb_tests
comb,>>,n %r0,%r4,comb_tests
comb,nsv,n %r0,%r4,comb_tests
comb,ev,n %r0,%r4,comb_tests
comib_tests:
comib 0,%r4,comib_tests
comib,< 0,%r4,comib_tests
comib,<= 0,%r4,comib_tests
comib,<< 0,%r4,comib_tests
comib,<<= 0,%r4,comib_tests
comib,sv 0,%r4,comib_tests
comib,od 0,%r4,comib_tests
comib,tr 0,%r4,comib_tests
comib,<> 0,%r4,comib_tests
comib,>= 0,%r4,comib_tests
comib,> 0,%r4,comib_tests
comib,>>= 0,%r4,comib_tests
comib,>> 0,%r4,comib_tests
comib,nsv 0,%r4,comib_tests
comib,ev 0,%r4,comb_tests
comib_nullified_tests:
comib,n 0,%r4,comib_tests
comib,=,n 0,%r4,comib_tests
comib,<,n 0,%r4,comib_tests
comib,<=,n 0,%r4,comib_tests
comib,<<,n 0,%r4,comib_tests
comib,<<=,n 0,%r4,comib_tests
comib,sv,n 0,%r4,comib_tests
comib,od,n 0,%r4,comib_tests
comib,tr,n 0,%r4,comib_tests
comib,<>,n 0,%r4,comib_tests
comib,>=,n 0,%r4,comib_tests
comib,>,n 0,%r4,comib_tests
comib,>>=,n 0,%r4,comib_tests
comib,>>,n 0,%r4,comib_tests
comib,nsv,n 0,%r4,comib_tests
comib,ev,n 0,%r4,comib_tests
addb_tests:
addb %r1,%r4,addb_tests
addb,= %r1,%r4,addb_tests
addb,< %r1,%r4,addb_tests
addb,<= %r1,%r4,addb_tests
addb,nuv %r1,%r4,addb_tests
addb,znv %r1,%r4,addb_tests
addb,sv %r1,%r4,addb_tests
addb,od %r1,%r4,addb_tests
addb,tr %r1,%r4,addb_tests
addb,<> %r1,%r4,addb_tests
addb,>= %r1,%r4,addb_tests
addb,> %r1,%r4,addb_tests
addb,uv %r1,%r4,addb_tests
addb,vnz %r1,%r4,addb_tests
addb,nsv %r1,%r4,addb_tests
addb,ev %r1,%r4,addb_tests
addb_nullified_tests:
addb,n %r1,%r4,addb_tests
addb,=,n %r1,%r4,addb_tests
addb,<,n %r1,%r4,addb_tests
addb,<=,n %r1,%r4,addb_tests
addb,nuv,n %r1,%r4,addb_tests
addb,znv,n %r1,%r4,addb_tests
addb,sv,n %r1,%r4,addb_tests
addb,od,n %r1,%r4,addb_tests
addb,tr,n %r1,%r4,addb_tests
addb,<>,n %r1,%r4,addb_tests
addb,>=,n %r1,%r4,addb_tests
addb,>,n %r1,%r4,addb_tests
addb,uv,n %r1,%r4,addb_tests
addb,vnz,n %r1,%r4,addb_tests
addb,nsv,n %r1,%r4,addb_tests
addb,ev,n %r1,%r4,addb_tests
addib_tests:
addib -1,%r4,addib_tests
addib,= -1,%r4,addib_tests
addib,< -1,%r4,addib_tests
addib,<= -1,%r4,addib_tests
addib,nuv -1,%r4,addib_tests
addib,znv -1,%r4,addib_tests
addib,sv -1,%r4,addib_tests
addib,od -1,%r4,addib_tests
addib,tr -1,%r4,addib_tests
addib,<> -1,%r4,addib_tests
addib,>= -1,%r4,addib_tests
addib,> -1,%r4,addib_tests
addib,uv -1,%r4,addib_tests
addib,vnz -1,%r4,addib_tests
addib,nsv -1,%r4,addib_tests
addib,ev -1,%r4,comb_tests
addib_nullified_tests:
addib,n -1,%r4,addib_tests
addib,=,n -1,%r4,addib_tests
addib,<,n -1,%r4,addib_tests
addib,<=,n -1,%r4,addib_tests
addib,nuv,n -1,%r4,addib_tests
addib,znv,n -1,%r4,addib_tests
addib,sv,n -1,%r4,addib_tests
addib,od,n -1,%r4,addib_tests
addib,tr,n -1,%r4,addib_tests
addib,<>,n -1,%r4,addib_tests
addib,>=,n -1,%r4,addib_tests
addib,>,n -1,%r4,addib_tests
addib,uv,n -1,%r4,addib_tests
addib,vnz,n -1,%r4,addib_tests
addib,nsv,n -1,%r4,addib_tests
addib,ev,n -1,%r4,addib_tests
; Needs to check lots of stuff (like corner bit cases)
bb_tests:
bvb,< %r4,bb_tests
bvb,>= %r4,bb_tests
bvb,<,n %r4,bb_tests
bvb,>=,n %r4,bb_tests
bb,< %r4,5,bb_tests
bb,>= %r4,5,bb_tests
bb,<,n %r4,5,bb_tests
bb,>=,n %r4,5,bb_tests
|
tactcomplabs/xbgas-binutils-gdb
| 3,568
|
gas/testsuite/gas/hppa/basic/add.s
|
.level 1.1
.code
.align 4
; Basic add/sh?add instruction tests.
;
; We could/should test some of the corner cases for register and
; immediate fields. We should also check the assorted field
; selectors to make sure they're handled correctly.
add %r4,%r5,%r6
add,= %r4,%r5,%r6
add,< %r4,%r5,%r6
add,<= %r4,%r5,%r6
add,nuv %r4,%r5,%r6
add,znv %r4,%r5,%r6
add,sv %r4,%r5,%r6
add,od %r4,%r5,%r6
add,tr %r4,%r5,%r6
add,<> %r4,%r5,%r6
add,>= %r4,%r5,%r6
add,> %r4,%r5,%r6
add,uv %r4,%r5,%r6
add,vnz %r4,%r5,%r6
add,nsv %r4,%r5,%r6
add,ev %r4,%r5,%r6
addl %r4,%r5,%r6
addl,= %r4,%r5,%r6
addl,< %r4,%r5,%r6
addl,<= %r4,%r5,%r6
addl,nuv %r4,%r5,%r6
addl,znv %r4,%r5,%r6
addl,sv %r4,%r5,%r6
addl,od %r4,%r5,%r6
addl,tr %r4,%r5,%r6
addl,<> %r4,%r5,%r6
addl,>= %r4,%r5,%r6
addl,> %r4,%r5,%r6
addl,uv %r4,%r5,%r6
addl,vnz %r4,%r5,%r6
addl,nsv %r4,%r5,%r6
addl,ev %r4,%r5,%r6
addo %r4,%r5,%r6
addo,= %r4,%r5,%r6
addo,< %r4,%r5,%r6
addo,<= %r4,%r5,%r6
addo,nuv %r4,%r5,%r6
addo,znv %r4,%r5,%r6
addo,sv %r4,%r5,%r6
addo,od %r4,%r5,%r6
addo,tr %r4,%r5,%r6
addo,<> %r4,%r5,%r6
addo,>= %r4,%r5,%r6
addo,> %r4,%r5,%r6
addo,uv %r4,%r5,%r6
addo,vnz %r4,%r5,%r6
addo,nsv %r4,%r5,%r6
addo,ev %r4,%r5,%r6
addc %r4,%r5,%r6
addc,= %r4,%r5,%r6
addc,< %r4,%r5,%r6
addc,<= %r4,%r5,%r6
addc,nuv %r4,%r5,%r6
addc,znv %r4,%r5,%r6
addc,sv %r4,%r5,%r6
addc,od %r4,%r5,%r6
addc,tr %r4,%r5,%r6
addc,<> %r4,%r5,%r6
addc,>= %r4,%r5,%r6
addc,> %r4,%r5,%r6
addc,uv %r4,%r5,%r6
addc,vnz %r4,%r5,%r6
addc,nsv %r4,%r5,%r6
addc,ev %r4,%r5,%r6
addco %r4,%r5,%r6
addco,= %r4,%r5,%r6
addco,< %r4,%r5,%r6
addco,<= %r4,%r5,%r6
addco,nuv %r4,%r5,%r6
addco,znv %r4,%r5,%r6
addco,sv %r4,%r5,%r6
addco,od %r4,%r5,%r6
addco,tr %r4,%r5,%r6
addco,<> %r4,%r5,%r6
addco,>= %r4,%r5,%r6
addco,> %r4,%r5,%r6
addco,uv %r4,%r5,%r6
addco,vnz %r4,%r5,%r6
addco,nsv %r4,%r5,%r6
addco,ev %r4,%r5,%r6
add,l %r4,%r5,%r6
add,l,= %r4,%r5,%r6
add,l,< %r4,%r5,%r6
add,l,<= %r4,%r5,%r6
add,l,nuv %r4,%r5,%r6
add,l,znv %r4,%r5,%r6
add,l,sv %r4,%r5,%r6
add,l,od %r4,%r5,%r6
add,l,tr %r4,%r5,%r6
add,l,<> %r4,%r5,%r6
add,l,>= %r4,%r5,%r6
add,l,> %r4,%r5,%r6
add,l,uv %r4,%r5,%r6
add,l,vnz %r4,%r5,%r6
add,l,nsv %r4,%r5,%r6
add,l,ev %r4,%r5,%r6
add,tsv %r4,%r5,%r6
add,tsv,= %r4,%r5,%r6
add,tsv,< %r4,%r5,%r6
add,tsv,<= %r4,%r5,%r6
add,tsv,nuv %r4,%r5,%r6
add,tsv,znv %r4,%r5,%r6
add,tsv,sv %r4,%r5,%r6
add,tsv,od %r4,%r5,%r6
add,tsv,tr %r4,%r5,%r6
add,tsv,<> %r4,%r5,%r6
add,tsv,>= %r4,%r5,%r6
add,tsv,> %r4,%r5,%r6
add,tsv,uv %r4,%r5,%r6
add,tsv,vnz %r4,%r5,%r6
add,tsv,nsv %r4,%r5,%r6
add,tsv,ev %r4,%r5,%r6
add,c %r4,%r5,%r6
add,c,= %r4,%r5,%r6
add,c,< %r4,%r5,%r6
add,c,<= %r4,%r5,%r6
add,c,nuv %r4,%r5,%r6
add,c,znv %r4,%r5,%r6
add,c,sv %r4,%r5,%r6
add,c,od %r4,%r5,%r6
add,c,tr %r4,%r5,%r6
add,c,<> %r4,%r5,%r6
add,c,>= %r4,%r5,%r6
add,c,> %r4,%r5,%r6
add,c,uv %r4,%r5,%r6
add,c,vnz %r4,%r5,%r6
add,c,nsv %r4,%r5,%r6
add,c,ev %r4,%r5,%r6
add,c,tsv %r4,%r5,%r6
add,c,tsv,= %r4,%r5,%r6
add,c,tsv,< %r4,%r5,%r6
add,c,tsv,<= %r4,%r5,%r6
add,c,tsv,nuv %r4,%r5,%r6
add,c,tsv,znv %r4,%r5,%r6
add,c,tsv,sv %r4,%r5,%r6
add,c,tsv,od %r4,%r5,%r6
add,tsv,c,tr %r4,%r5,%r6
add,tsv,c,<> %r4,%r5,%r6
add,tsv,c,>= %r4,%r5,%r6
add,tsv,c,> %r4,%r5,%r6
add,tsv,c,uv %r4,%r5,%r6
add,tsv,c,vnz %r4,%r5,%r6
add,tsv,c,nsv %r4,%r5,%r6
add,tsv,c,ev %r4,%r5,%r6
|
tactcomplabs/xbgas-binutils-gdb
| 2,815
|
gas/testsuite/gas/hppa/basic/sub2.s
|
.LEVEL 2.0
.code
.align 4
; Basic immediate instruction tests.
;
; We could/should test some of the corner cases for register and
; immediate fields. We should also check the assorted field
; selectors to make sure they're handled correctly.
sub,* %r4,%r5,%r6
sub,*= %r4,%r5,%r6
sub,*< %r4,%r5,%r6
sub,*<= %r4,%r5,%r6
sub,*<< %r4,%r5,%r6
sub,*<<= %r4,%r5,%r6
sub,*sv %r4,%r5,%r6
sub,*od %r4,%r5,%r6
sub,*tr %r4,%r5,%r6
sub,*<> %r4,%r5,%r6
sub,*>= %r4,%r5,%r6
sub,*> %r4,%r5,%r6
sub,*>>= %r4,%r5,%r6
sub,*>> %r4,%r5,%r6
sub,*nsv %r4,%r5,%r6
sub,*ev %r4,%r5,%r6
sub,tsv,* %r4,%r5,%r6
sub,tsv,*= %r4,%r5,%r6
sub,tsv,*< %r4,%r5,%r6
sub,tsv,*<= %r4,%r5,%r6
sub,tsv,*<< %r4,%r5,%r6
sub,tsv,*<<= %r4,%r5,%r6
sub,tsv,*sv %r4,%r5,%r6
sub,tsv,*od %r4,%r5,%r6
sub,tsv,*tr %r4,%r5,%r6
sub,tsv,*<> %r4,%r5,%r6
sub,tsv,*>= %r4,%r5,%r6
sub,tsv,*> %r4,%r5,%r6
sub,tsv,*>>= %r4,%r5,%r6
sub,tsv,*>> %r4,%r5,%r6
sub,tsv,*nsv %r4,%r5,%r6
sub,tsv,*ev %r4,%r5,%r6
sub,db,* %r4,%r5,%r6
sub,db,*= %r4,%r5,%r6
sub,db,*< %r4,%r5,%r6
sub,db,*<= %r4,%r5,%r6
sub,db,*<< %r4,%r5,%r6
sub,db,*<<= %r4,%r5,%r6
sub,db,*sv %r4,%r5,%r6
sub,db,*od %r4,%r5,%r6
sub,db,*tr %r4,%r5,%r6
sub,db,*<> %r4,%r5,%r6
sub,db,*>= %r4,%r5,%r6
sub,db,*> %r4,%r5,%r6
sub,db,*>>= %r4,%r5,%r6
sub,db,*>> %r4,%r5,%r6
sub,db,*nsv %r4,%r5,%r6
sub,db,*ev %r4,%r5,%r6
sub,db,tsv,* %r4,%r5,%r6
sub,db,tsv,*= %r4,%r5,%r6
sub,db,tsv,*< %r4,%r5,%r6
sub,db,tsv,*<= %r4,%r5,%r6
sub,db,tsv,*<< %r4,%r5,%r6
sub,db,tsv,*<<= %r4,%r5,%r6
sub,db,tsv,*sv %r4,%r5,%r6
sub,db,tsv,*od %r4,%r5,%r6
sub,tsv,db,*tr %r4,%r5,%r6
sub,tsv,db,*<> %r4,%r5,%r6
sub,tsv,db,*>= %r4,%r5,%r6
sub,tsv,db,*> %r4,%r5,%r6
sub,tsv,db,*>>= %r4,%r5,%r6
sub,tsv,db,*>> %r4,%r5,%r6
sub,tsv,db,*nsv %r4,%r5,%r6
sub,tsv,db,*ev %r4,%r5,%r6
sub,tc,* %r4,%r5,%r6
sub,tc,*= %r4,%r5,%r6
sub,tc,*< %r4,%r5,%r6
sub,tc,*<= %r4,%r5,%r6
sub,tc,*<< %r4,%r5,%r6
sub,tc,*<<= %r4,%r5,%r6
sub,tc,*sv %r4,%r5,%r6
sub,tc,*od %r4,%r5,%r6
sub,tc,*tr %r4,%r5,%r6
sub,tc,*<> %r4,%r5,%r6
sub,tc,*>= %r4,%r5,%r6
sub,tc,*> %r4,%r5,%r6
sub,tc,*>>= %r4,%r5,%r6
sub,tc,*>> %r4,%r5,%r6
sub,tc,*nsv %r4,%r5,%r6
sub,tc,*ev %r4,%r5,%r6
sub,tc,tsv,* %r4,%r5,%r6
sub,tc,tsv,*= %r4,%r5,%r6
sub,tc,tsv,*< %r4,%r5,%r6
sub,tc,tsv,*<= %r4,%r5,%r6
sub,tc,tsv,*<< %r4,%r5,%r6
sub,tc,tsv,*<<= %r4,%r5,%r6
sub,tc,tsv,*sv %r4,%r5,%r6
sub,tc,tsv,*od %r4,%r5,%r6
sub,tsv,tc,*tr %r4,%r5,%r6
sub,tsv,tc,*<> %r4,%r5,%r6
sub,tsv,tc,*>= %r4,%r5,%r6
sub,tsv,tc,*> %r4,%r5,%r6
sub,tsv,tc,*>>= %r4,%r5,%r6
sub,tsv,tc,*>> %r4,%r5,%r6
sub,tsv,tc,*nsv %r4,%r5,%r6
sub,tsv,tc,*ev %r4,%r5,%r6
;; PR gas/11395: Check for the correct assembly
;; of unconditional 32-bit and 64-bit sub instructions.
sub %r1,%r1,%r1
sub,db %r1,%r1,%r1
|
tactcomplabs/xbgas-binutils-gdb
| 1,418
|
gas/testsuite/gas/hppa/basic/sh3add.s
|
.code
.align 4
; Basic immediate instruction tests.
;
; We could/should test some of the corner cases for register and
; immediate fields. We should also check the assorted field
; selectors to make sure they're handled correctly.
sh3add %r4,%r5,%r6
sh3add,= %r4,%r5,%r6
sh3add,< %r4,%r5,%r6
sh3add,<= %r4,%r5,%r6
sh3add,nuv %r4,%r5,%r6
sh3add,znv %r4,%r5,%r6
sh3add,sv %r4,%r5,%r6
sh3add,od %r4,%r5,%r6
sh3add,tr %r4,%r5,%r6
sh3add,<> %r4,%r5,%r6
sh3add,>= %r4,%r5,%r6
sh3add,> %r4,%r5,%r6
sh3add,uv %r4,%r5,%r6
sh3add,vnz %r4,%r5,%r6
sh3add,nsv %r4,%r5,%r6
sh3add,ev %r4,%r5,%r6
sh3addl %r4,%r5,%r6
sh3addl,= %r4,%r5,%r6
sh3addl,< %r4,%r5,%r6
sh3addl,<= %r4,%r5,%r6
sh3addl,nuv %r4,%r5,%r6
sh3addl,znv %r4,%r5,%r6
sh3addl,sv %r4,%r5,%r6
sh3addl,od %r4,%r5,%r6
sh3addl,tr %r4,%r5,%r6
sh3addl,<> %r4,%r5,%r6
sh3addl,>= %r4,%r5,%r6
sh3addl,> %r4,%r5,%r6
sh3addl,uv %r4,%r5,%r6
sh3addl,vnz %r4,%r5,%r6
sh3addl,nsv %r4,%r5,%r6
sh3addl,ev %r4,%r5,%r6
sh3addo %r4,%r5,%r6
sh3addo,= %r4,%r5,%r6
sh3addo,< %r4,%r5,%r6
sh3addo,<= %r4,%r5,%r6
sh3addo,nuv %r4,%r5,%r6
sh3addo,znv %r4,%r5,%r6
sh3addo,sv %r4,%r5,%r6
sh3addo,od %r4,%r5,%r6
sh3addo,tr %r4,%r5,%r6
sh3addo,<> %r4,%r5,%r6
sh3addo,>= %r4,%r5,%r6
sh3addo,> %r4,%r5,%r6
sh3addo,uv %r4,%r5,%r6
sh3addo,vnz %r4,%r5,%r6
sh3addo,nsv %r4,%r5,%r6
sh3addo,ev %r4,%r5,%r6
|
tactcomplabs/xbgas-binutils-gdb
| 1,418
|
gas/testsuite/gas/hppa/basic/sh2add.s
|
.code
.align 4
; Basic immediate instruction tests.
;
; We could/should test some of the corner cases for register and
; immediate fields. We should also check the assorted field
; selectors to make sure they're handled correctly.
sh2add %r4,%r5,%r6
sh2add,= %r4,%r5,%r6
sh2add,< %r4,%r5,%r6
sh2add,<= %r4,%r5,%r6
sh2add,nuv %r4,%r5,%r6
sh2add,znv %r4,%r5,%r6
sh2add,sv %r4,%r5,%r6
sh2add,od %r4,%r5,%r6
sh2add,tr %r4,%r5,%r6
sh2add,<> %r4,%r5,%r6
sh2add,>= %r4,%r5,%r6
sh2add,> %r4,%r5,%r6
sh2add,uv %r4,%r5,%r6
sh2add,vnz %r4,%r5,%r6
sh2add,nsv %r4,%r5,%r6
sh2add,ev %r4,%r5,%r6
sh2addl %r4,%r5,%r6
sh2addl,= %r4,%r5,%r6
sh2addl,< %r4,%r5,%r6
sh2addl,<= %r4,%r5,%r6
sh2addl,nuv %r4,%r5,%r6
sh2addl,znv %r4,%r5,%r6
sh2addl,sv %r4,%r5,%r6
sh2addl,od %r4,%r5,%r6
sh2addl,tr %r4,%r5,%r6
sh2addl,<> %r4,%r5,%r6
sh2addl,>= %r4,%r5,%r6
sh2addl,> %r4,%r5,%r6
sh2addl,uv %r4,%r5,%r6
sh2addl,vnz %r4,%r5,%r6
sh2addl,nsv %r4,%r5,%r6
sh2addl,ev %r4,%r5,%r6
sh2addo %r4,%r5,%r6
sh2addo,= %r4,%r5,%r6
sh2addo,< %r4,%r5,%r6
sh2addo,<= %r4,%r5,%r6
sh2addo,nuv %r4,%r5,%r6
sh2addo,znv %r4,%r5,%r6
sh2addo,sv %r4,%r5,%r6
sh2addo,od %r4,%r5,%r6
sh2addo,tr %r4,%r5,%r6
sh2addo,<> %r4,%r5,%r6
sh2addo,>= %r4,%r5,%r6
sh2addo,> %r4,%r5,%r6
sh2addo,uv %r4,%r5,%r6
sh2addo,vnz %r4,%r5,%r6
sh2addo,nsv %r4,%r5,%r6
sh2addo,ev %r4,%r5,%r6
|
tactcomplabs/xbgas-binutils-gdb
| 1,037
|
gas/testsuite/gas/hppa/basic/extract2.s
|
.code
.align 4
; Basic immediate instruction tests.
;
; We could/should test some of the corner cases for register and
; immediate fields. We should also check the assorted field
; selectors to make sure they're handled correctly.
extrw,u %r4,5,10,%r6
extrw,u,= %r4,5,10,%r6
extrw,u,< %r4,5,10,%r6
extrw,u,od %r4,5,10,%r6
extrw,u,tr %r4,5,10,%r6
extrw,u,<> %r4,5,10,%r6
extrw,u,>= %r4,5,10,%r6
extrw,u,ev %r4,5,10,%r6
extrw,s %r4,5,10,%r6
extrw,s,= %r4,5,10,%r6
extrw,s,< %r4,5,10,%r6
extrw,s,od %r4,5,10,%r6
extrw,tr %r4,5,10,%r6
extrw,<> %r4,5,10,%r6
extrw,>= %r4,5,10,%r6
extrw,ev %r4,5,10,%r6
extrw,u %r4,%sar,5,%r6
extrw,u,= %r4,%sar,5,%r6
extrw,u,< %r4,%sar,5,%r6
extrw,u,od %r4,%sar,5,%r6
extrw,u,tr %r4,%sar,5,%r6
extrw,u,<> %r4,%sar,5,%r6
extrw,u,>= %r4,%sar,5,%r6
extrw,u,ev %r4,%sar,5,%r6
extrw,s %r4,%sar,5,%r6
extrw,s,= %r4,%sar,5,%r6
extrw,s,< %r4,%sar,5,%r6
extrw,s,od %r4,%sar,5,%r6
extrw,tr %r4,%sar,5,%r6
extrw,<> %r4,%sar,5,%r6
extrw,>= %r4,%sar,5,%r6
extrw,ev %r4,%sar,5,%r6
|
tactcomplabs/xbgas-binutils-gdb
| 1,183
|
gas/testsuite/gas/hppa/basic/fmem.s
|
.code
.align 4
; Basic immediate instruction tests.
;
; We could/should test some of the corner cases for register and
; immediate fields. We should also check the assorted field
; selectors to make sure they're handled correctly.
fldwx %r4(%sr0,%r5),%fr6
fldwx,s %r4(%sr0,%r5),%fr6
fldwx,m %r4(%sr0,%r5),%fr6
fldwx,sm %r4(%sr0,%r5),%fr6
flddx %r4(%sr0,%r5),%fr6
flddx,s %r4(%sr0,%r5),%fr6
flddx,m %r4(%sr0,%r5),%fr6
flddx,sm %r4(%sr0,%r5),%fr6
fstwx %fr6,%r4(%sr0,%r5)
fstwx,s %fr6,%r4(%sr0,%r5)
fstwx,m %fr6,%r4(%sr0,%r5)
fstwx,sm %fr6,%r4(%sr0,%r5)
fstdx %fr6,%r4(%sr0,%r5)
fstdx,s %fr6,%r4(%sr0,%r5)
fstdx,m %fr6,%r4(%sr0,%r5)
fstdx,sm %fr6,%r4(%sr0,%r5)
fstqx %fr6,%r4(%sr0,%r5)
fstqx,s %fr6,%r4(%sr0,%r5)
fstqx,m %fr6,%r4(%sr0,%r5)
fstqx,sm %fr6,%r4(%sr0,%r5)
fldws 0(%sr0,%r5),%fr6
fldws,mb 0(%sr0,%r5),%fr6
fldws,ma 0(%sr0,%r5),%fr6
fldds 0(%sr0,%r5),%fr6
fldds,mb 0(%sr0,%r5),%fr6
fldds,ma 0(%sr0,%r5),%fr6
fstws %fr6,0(%sr0,%r5)
fstws,mb %fr6,0(%sr0,%r5)
fstws,ma %fr6,0(%sr0,%r5)
fstds %fr6,0(%sr0,%r5)
fstds,mb %fr6,0(%sr0,%r5)
fstds,ma %fr6,0(%sr0,%r5)
fstqs %fr6,0(%sr0,%r5)
fstqs,mb %fr6,0(%sr0,%r5)
fstqs,ma %fr6,0(%sr0,%r5)
|
tactcomplabs/xbgas-binutils-gdb
| 1,039
|
gas/testsuite/gas/hppa/basic/logical.s
|
.level 1.1
.code
.align 4
; Basic immediate instruction tests.
;
; We could/should test some of the corner cases for register and
; immediate fields. We should also check the assorted field
; selectors to make sure they're handled correctly.
or %r4,%r5,%r6
or,= %r4,%r5,%r6
or,< %r4,%r5,%r6
or,<= %r4,%r5,%r6
or,od %r4,%r5,%r6
or,tr %r4,%r5,%r6
or,<> %r4,%r5,%r6
or,>= %r4,%r5,%r6
or,> %r4,%r5,%r6
or,ev %r4,%r5,%r6
xor %r4,%r5,%r6
xor,= %r4,%r5,%r6
xor,< %r4,%r5,%r6
xor,<= %r4,%r5,%r6
xor,od %r4,%r5,%r6
xor,tr %r4,%r5,%r6
xor,<> %r4,%r5,%r6
xor,>= %r4,%r5,%r6
xor,> %r4,%r5,%r6
xor,ev %r4,%r5,%r6
and %r4,%r5,%r6
and,= %r4,%r5,%r6
and,< %r4,%r5,%r6
and,<= %r4,%r5,%r6
and,od %r4,%r5,%r6
and,tr %r4,%r5,%r6
and,<> %r4,%r5,%r6
and,>= %r4,%r5,%r6
and,> %r4,%r5,%r6
and,ev %r4,%r5,%r6
andcm %r4,%r5,%r6
andcm,= %r4,%r5,%r6
andcm,< %r4,%r5,%r6
andcm,<= %r4,%r5,%r6
andcm,od %r4,%r5,%r6
andcm,tr %r4,%r5,%r6
andcm,<> %r4,%r5,%r6
andcm,>= %r4,%r5,%r6
andcm,> %r4,%r5,%r6
andcm,ev %r4,%r5,%r6
|
tactcomplabs/xbgas-binutils-gdb
| 2,161
|
gas/testsuite/gas/hppa/basic/imem.s
|
.code
.align 4
.EXPORT integer_memory_tests,CODE
.EXPORT integer_indexing_load,CODE
.EXPORT integer_load_short_memory,CODE
.EXPORT integer_store_short_memory,CODE
.EXPORT main,CODE
.EXPORT main,ENTRY,PRIV_LEV=3,RTNVAL=GR
; Basic integer memory tests which also test the various
; addressing modes and completers.
;
; We could/should test some of the corner cases for register and
; immediate fields. We should also check the assorted field
; selectors to make sure they're handled correctly.
;
integer_memory_tests:
ldw 0(%sr0,%r4),%r26
ldh 0(%sr0,%r4),%r26
ldb 0(%sr0,%r4),%r26
stw %r26,0(%sr0,%r4)
sth %r26,0(%sr0,%r4)
stb %r26,0(%sr0,%r4)
; Should make sure pre/post modes are recognized correctly.
ldwm 0(%sr0,%r4),%r26
stwm %r26,0(%sr0,%r4)
integer_indexing_load:
ldwx %r5(%sr0,%r4),%r26
ldwx,s %r5(%sr0,%r4),%r26
ldwx,m %r5(%sr0,%r4),%r26
ldwx,sm %r5(%sr0,%r4),%r26
ldhx %r5(%sr0,%r4),%r26
ldhx,s %r5(%sr0,%r4),%r26
ldhx,m %r5(%sr0,%r4),%r26
ldhx,sm %r5(%sr0,%r4),%r26
ldbx %r5(%sr0,%r4),%r26
ldbx,s %r5(%sr0,%r4),%r26
ldbx,m %r5(%sr0,%r4),%r26
ldbx,sm %r5(%sr0,%r4),%r26
ldwax %r5(%r4),%r26
ldwax,s %r5(%r4),%r26
ldwax,m %r5(%r4),%r26
ldwax,sm %r5(%r4),%r26
ldcwx %r5(%sr0,%r4),%r26
ldcwx,s %r5(%sr0,%r4),%r26
ldcwx,m %r5(%sr0,%r4),%r26
ldcwx,sm %r5(%sr0,%r4),%r26
integer_load_short_memory:
ldws 0(%sr0,%r4),%r26
ldws,mb 0(%sr0,%r4),%r26
ldws,ma 0(%sr0,%r4),%r26
ldhs 0(%sr0,%r4),%r26
ldhs,mb 0(%sr0,%r4),%r26
ldhs,ma 0(%sr0,%r4),%r26
ldbs 0(%sr0,%r4),%r26
ldbs,mb 0(%sr0,%r4),%r26
ldbs,ma 0(%sr0,%r4),%r26
ldwas 0(%r4),%r26
ldwas,mb 0(%r4),%r26
ldwas,ma 0(%r4),%r26
ldcws 0(%sr0,%r4),%r26
ldcws,mb 0(%sr0,%r4),%r26
ldcws,ma 0(%sr0,%r4),%r26
integer_store_short_memory:
stws %r26,0(%sr0,%r4)
stws,mb %r26,0(%sr0,%r4)
stws,ma %r26,0(%sr0,%r4)
sths %r26,0(%sr0,%r4)
sths,mb %r26,0(%sr0,%r4)
sths,ma %r26,0(%sr0,%r4)
stbs %r26,0(%sr0,%r4)
stbs,mb %r26,0(%sr0,%r4)
stbs,ma %r26,0(%sr0,%r4)
stwas %r26,0(%r4)
stwas,mb %r26,0(%r4)
stwas,ma %r26,0(%r4)
stbys %r26,0(%sr0,%r4)
stbys,b %r26,0(%sr0,%r4)
stbys,e %r26,0(%sr0,%r4)
stbys,b,m %r26,0(%sr0,%r4)
stbys,e,m %r26,0(%sr0,%r4)
|
tactcomplabs/xbgas-binutils-gdb
| 1,517
|
gas/testsuite/gas/hppa/basic/deposit.s
|
.code
.align 4
; Basic immediate instruction tests.
;
; We could/should test some of the corner cases for register and
; immediate fields. We should also check the assorted field
; selectors to make sure they're handled correctly.
zdep %r4,5,10,%r6
zdep,= %r4,5,10,%r6
zdep,< %r4,5,10,%r6
zdep,od %r4,5,10,%r6
zdep,tr %r4,5,10,%r6
zdep,<> %r4,5,10,%r6
zdep,>= %r4,5,10,%r6
zdep,ev %r4,5,10,%r6
dep %r4,5,10,%r6
dep,= %r4,5,10,%r6
dep,< %r4,5,10,%r6
dep,od %r4,5,10,%r6
dep,tr %r4,5,10,%r6
dep,<> %r4,5,10,%r6
dep,>= %r4,5,10,%r6
dep,ev %r4,5,10,%r6
zvdep %r4,5,%r6
zvdep,= %r4,5,%r6
zvdep,< %r4,5,%r6
zvdep,od %r4,5,%r6
zvdep,tr %r4,5,%r6
zvdep,<> %r4,5,%r6
zvdep,>= %r4,5,%r6
zvdep,ev %r4,5,%r6
vdep %r4,5,%r6
vdep,= %r4,5,%r6
vdep,< %r4,5,%r6
vdep,od %r4,5,%r6
vdep,tr %r4,5,%r6
vdep,<> %r4,5,%r6
vdep,>= %r4,5,%r6
vdep,ev %r4,5,%r6
vdepi -1,5,%r6
vdepi,= -1,5,%r6
vdepi,< -1,5,%r6
vdepi,od -1,5,%r6
vdepi,tr -1,5,%r6
vdepi,<> -1,5,%r6
vdepi,>= -1,5,%r6
vdepi,ev -1,5,%r6
zvdepi -1,5,%r6
zvdepi,= -1,5,%r6
zvdepi,< -1,5,%r6
zvdepi,od -1,5,%r6
zvdepi,tr -1,5,%r6
zvdepi,<> -1,5,%r6
zvdepi,>= -1,5,%r6
zvdepi,ev -1,5,%r6
depi -1,4,10,%r6
depi,= -1,4,10,%r6
depi,< -1,4,10,%r6
depi,od -1,4,10,%r6
depi,tr -1,4,10,%r6
depi,<> -1,4,10,%r6
depi,>= -1,4,10,%r6
depi,ev -1,4,10,%r6
zdepi -1,4,10,%r6
zdepi,= -1,4,10,%r6
zdepi,< -1,4,10,%r6
zdepi,od -1,4,10,%r6
zdepi,tr -1,4,10,%r6
zdepi,<> -1,4,10,%r6
zdepi,>= -1,4,10,%r6
zdepi,ev -1,4,10,%r6
|
tactcomplabs/xbgas-binutils-gdb
| 1,318
|
gas/testsuite/gas/hppa/basic/subi.s
|
.code
.align 4
; Basic immediate instruction tests.
;
; We could/should test some of the corner cases for register and
; immediate fields. We should also check the assorted field
; selectors to make sure they're handled correctly.
subi 123,%r5,%r6
subi,= 123,%r5,%r6
subi,< 123,%r5,%r6
subi,<= 123,%r5,%r6
subi,<< 123,%r5,%r6
subi,<<= 123,%r5,%r6
subi,sv 123,%r5,%r6
subi,od 123,%r5,%r6
subi,tr 123,%r5,%r6
subi,<> 123,%r5,%r6
subi,>= 123,%r5,%r6
subi,> 123,%r5,%r6
subi,>>= 123,%r5,%r6
subi,>> 123,%r5,%r6
subi,nsv 123,%r5,%r6
subi,ev 123,%r5,%r6
subio 123,%r5,%r6
subio,= 123,%r5,%r6
subio,< 123,%r5,%r6
subio,<= 123,%r5,%r6
subio,<< 123,%r5,%r6
subio,<<= 123,%r5,%r6
subio,sv 123,%r5,%r6
subio,od 123,%r5,%r6
subio,tr 123,%r5,%r6
subio,<> 123,%r5,%r6
subio,>= 123,%r5,%r6
subio,> 123,%r5,%r6
subio,>>= 123,%r5,%r6
subio,>> 123,%r5,%r6
subio,nsv 123,%r5,%r6
subio,ev 123,%r5,%r6
subi,tsv 123,%r5,%r6
subi,tsv,= 123,%r5,%r6
subi,tsv,< 123,%r5,%r6
subi,tsv,<= 123,%r5,%r6
subi,tsv,<< 123,%r5,%r6
subi,tsv,<<= 123,%r5,%r6
subi,tsv,sv 123,%r5,%r6
subi,tsv,od 123,%r5,%r6
subi,tsv,tr 123,%r5,%r6
subi,tsv,<> 123,%r5,%r6
subi,tsv,>= 123,%r5,%r6
subi,tsv,> 123,%r5,%r6
subi,tsv,>>= 123,%r5,%r6
subi,tsv,>> 123,%r5,%r6
subi,tsv,nsv 123,%r5,%r6
subi,tsv,ev 123,%r5,%r6
|
tactcomplabs/xbgas-binutils-gdb
| 1,711
|
gas/testsuite/gas/hppa/basic/fp_comp.s
|
.level 1.1
.code
.align 4
; Basic immediate instruction tests.
;
; We could/should test some of the corner cases for register and
; immediate fields. We should also check the assorted field
; selectors to make sure they're handled correctly.
fcpy,sgl %fr5,%fr10
fcpy,dbl %fr5,%fr10
fcpy,quad %fr5,%fr10
fcpy,sgl %fr20,%fr24
fcpy,dbl %fr20,%fr24
fabs,sgl %fr5,%fr10
fabs,dbl %fr5,%fr10
fabs,quad %fr5,%fr10
fabs,sgl %fr20,%fr24
fabs,dbl %fr20,%fr24
fsqrt,sgl %fr5,%fr10
fsqrt,dbl %fr5,%fr10
fsqrt,quad %fr5,%fr10
fsqrt,sgl %fr20,%fr24
fsqrt,dbl %fr20,%fr24
frnd,sgl %fr5,%fr10
frnd,dbl %fr5,%fr10
frnd,quad %fr5,%fr10
frnd,sgl %fr20,%fr24
frnd,dbl %fr20,%fr24
fadd,sgl %fr4,%fr8,%fr12
fadd,dbl %fr4,%fr8,%fr12
fadd,quad %fr4,%fr8,%fr12
fadd,sgl %fr20,%fr24,%fr28
fadd,dbl %fr20,%fr24,%fr28
fadd,quad %fr20,%fr24,%fr28
fsub,sgl %fr4,%fr8,%fr12
fsub,dbl %fr4,%fr8,%fr12
fsub,quad %fr4,%fr8,%fr12
fsub,sgl %fr20,%fr24,%fr28
fsub,dbl %fr20,%fr24,%fr28
fsub,quad %fr20,%fr24,%fr28
fmpy,sgl %fr4,%fr8,%fr12
fmpy,dbl %fr4,%fr8,%fr12
fmpy,quad %fr4,%fr8,%fr12
fmpy,sgl %fr20,%fr24,%fr28
fmpy,dbl %fr20,%fr24,%fr28
fmpy,quad %fr20,%fr24,%fr28
fdiv,sgl %fr4,%fr8,%fr12
fdiv,dbl %fr4,%fr8,%fr12
fdiv,quad %fr4,%fr8,%fr12
fdiv,sgl %fr20,%fr24,%fr28
fdiv,dbl %fr20,%fr24,%fr28
fdiv,quad %fr20,%fr24,%fr28
frem,sgl %fr4,%fr8,%fr12
frem,dbl %fr4,%fr8,%fr12
frem,quad %fr4,%fr8,%fr12
frem,sgl %fr20,%fr24,%fr28
frem,dbl %fr20,%fr24,%fr28
frem,quad %fr20,%fr24,%fr28
fmpyadd,sgl %fr16,%fr17,%fr18,%fr19,%fr20
fmpyadd,dbl %fr16,%fr17,%fr18,%fr19,%fr20
fmpysub,sgl %fr16,%fr17,%fr18,%fr19,%fr20
fmpysub,dbl %fr16,%fr17,%fr18,%fr19,%fr20
xmpyu %fr4,%fr5,%fr6
|
tactcomplabs/xbgas-binutils-gdb
| 4,210
|
gas/testsuite/gas/hppa/basic/sub.s
|
.level 1.1
.code
.align 4
; Basic immediate instruction tests.
;
; We could/should test some of the corner cases for register and
; immediate fields. We should also check the assorted field
; selectors to make sure they're handled correctly.
sub %r4,%r5,%r6
sub,= %r4,%r5,%r6
sub,< %r4,%r5,%r6
sub,<= %r4,%r5,%r6
sub,<< %r4,%r5,%r6
sub,<<= %r4,%r5,%r6
sub,sv %r4,%r5,%r6
sub,od %r4,%r5,%r6
sub,tr %r4,%r5,%r6
sub,<> %r4,%r5,%r6
sub,>= %r4,%r5,%r6
sub,> %r4,%r5,%r6
sub,>>= %r4,%r5,%r6
sub,>> %r4,%r5,%r6
sub,nsv %r4,%r5,%r6
sub,ev %r4,%r5,%r6
subo %r4,%r5,%r6
subo,= %r4,%r5,%r6
subo,< %r4,%r5,%r6
subo,<= %r4,%r5,%r6
subo,<< %r4,%r5,%r6
subo,<<= %r4,%r5,%r6
subo,sv %r4,%r5,%r6
subo,od %r4,%r5,%r6
subo,tr %r4,%r5,%r6
subo,<> %r4,%r5,%r6
subo,>= %r4,%r5,%r6
subo,> %r4,%r5,%r6
subo,>>= %r4,%r5,%r6
subo,>> %r4,%r5,%r6
subo,nsv %r4,%r5,%r6
subo,ev %r4,%r5,%r6
subb %r4,%r5,%r6
subb,= %r4,%r5,%r6
subb,< %r4,%r5,%r6
subb,<= %r4,%r5,%r6
subb,<< %r4,%r5,%r6
subb,<<= %r4,%r5,%r6
subb,sv %r4,%r5,%r6
subb,od %r4,%r5,%r6
subb,tr %r4,%r5,%r6
subb,<> %r4,%r5,%r6
subb,>= %r4,%r5,%r6
subb,> %r4,%r5,%r6
subb,>>= %r4,%r5,%r6
subb,>> %r4,%r5,%r6
subb,nsv %r4,%r5,%r6
subb,ev %r4,%r5,%r6
subbo %r4,%r5,%r6
subbo,= %r4,%r5,%r6
subbo,< %r4,%r5,%r6
subbo,<= %r4,%r5,%r6
subbo,<< %r4,%r5,%r6
subbo,<<= %r4,%r5,%r6
subbo,sv %r4,%r5,%r6
subbo,od %r4,%r5,%r6
subbo,tr %r4,%r5,%r6
subbo,<> %r4,%r5,%r6
subbo,>= %r4,%r5,%r6
subbo,> %r4,%r5,%r6
subbo,>>= %r4,%r5,%r6
subbo,>> %r4,%r5,%r6
subbo,nsv %r4,%r5,%r6
subbo,ev %r4,%r5,%r6
subt %r4,%r5,%r6
subt,= %r4,%r5,%r6
subt,< %r4,%r5,%r6
subt,<= %r4,%r5,%r6
subt,<< %r4,%r5,%r6
subt,<<= %r4,%r5,%r6
subt,sv %r4,%r5,%r6
subt,od %r4,%r5,%r6
subt,tr %r4,%r5,%r6
subt,<> %r4,%r5,%r6
subt,>= %r4,%r5,%r6
subt,> %r4,%r5,%r6
subt,>>= %r4,%r5,%r6
subt,>> %r4,%r5,%r6
subt,nsv %r4,%r5,%r6
subt,ev %r4,%r5,%r6
subto %r4,%r5,%r6
subto,= %r4,%r5,%r6
subto,< %r4,%r5,%r6
subto,<= %r4,%r5,%r6
subto,<< %r4,%r5,%r6
subto,<<= %r4,%r5,%r6
subto,sv %r4,%r5,%r6
subto,od %r4,%r5,%r6
subto,tr %r4,%r5,%r6
subto,<> %r4,%r5,%r6
subto,>= %r4,%r5,%r6
subto,> %r4,%r5,%r6
subto,>>= %r4,%r5,%r6
subto,>> %r4,%r5,%r6
subto,nsv %r4,%r5,%r6
subto,ev %r4,%r5,%r6
sub,tsv %r4,%r5,%r6
sub,tsv,= %r4,%r5,%r6
sub,tsv,< %r4,%r5,%r6
sub,tsv,<= %r4,%r5,%r6
sub,tsv,<< %r4,%r5,%r6
sub,tsv,<<= %r4,%r5,%r6
sub,tsv,sv %r4,%r5,%r6
sub,tsv,od %r4,%r5,%r6
sub,tsv,tr %r4,%r5,%r6
sub,tsv,<> %r4,%r5,%r6
sub,tsv,>= %r4,%r5,%r6
sub,tsv,> %r4,%r5,%r6
sub,tsv,>>= %r4,%r5,%r6
sub,tsv,>> %r4,%r5,%r6
sub,tsv,nsv %r4,%r5,%r6
sub,tsv,ev %r4,%r5,%r6
sub,b %r4,%r5,%r6
sub,b,= %r4,%r5,%r6
sub,b,< %r4,%r5,%r6
sub,b,<= %r4,%r5,%r6
sub,b,<< %r4,%r5,%r6
sub,b,<<= %r4,%r5,%r6
sub,b,sv %r4,%r5,%r6
sub,b,od %r4,%r5,%r6
sub,b,tr %r4,%r5,%r6
sub,b,<> %r4,%r5,%r6
sub,b,>= %r4,%r5,%r6
sub,b,> %r4,%r5,%r6
sub,b,>>= %r4,%r5,%r6
sub,b,>> %r4,%r5,%r6
sub,b,nsv %r4,%r5,%r6
sub,b,ev %r4,%r5,%r6
sub,b,tsv %r4,%r5,%r6
sub,b,tsv,= %r4,%r5,%r6
sub,b,tsv,< %r4,%r5,%r6
sub,b,tsv,<= %r4,%r5,%r6
sub,b,tsv,<< %r4,%r5,%r6
sub,b,tsv,<<= %r4,%r5,%r6
sub,b,tsv,sv %r4,%r5,%r6
sub,b,tsv,od %r4,%r5,%r6
sub,tsv,b,tr %r4,%r5,%r6
sub,tsv,b,<> %r4,%r5,%r6
sub,tsv,b,>= %r4,%r5,%r6
sub,tsv,b,> %r4,%r5,%r6
sub,tsv,b,>>= %r4,%r5,%r6
sub,tsv,b,>> %r4,%r5,%r6
sub,tsv,b,nsv %r4,%r5,%r6
sub,tsv,b,ev %r4,%r5,%r6
sub,tc %r4,%r5,%r6
sub,tc,= %r4,%r5,%r6
sub,tc,< %r4,%r5,%r6
sub,tc,<= %r4,%r5,%r6
sub,tc,<< %r4,%r5,%r6
sub,tc,<<= %r4,%r5,%r6
sub,tc,sv %r4,%r5,%r6
sub,tc,od %r4,%r5,%r6
sub,tc,tr %r4,%r5,%r6
sub,tc,<> %r4,%r5,%r6
sub,tc,>= %r4,%r5,%r6
sub,tc,> %r4,%r5,%r6
sub,tc,>>= %r4,%r5,%r6
sub,tc,>> %r4,%r5,%r6
sub,tc,nsv %r4,%r5,%r6
sub,tc,ev %r4,%r5,%r6
sub,tc,tsv %r4,%r5,%r6
sub,tc,tsv,= %r4,%r5,%r6
sub,tc,tsv,< %r4,%r5,%r6
sub,tc,tsv,<= %r4,%r5,%r6
sub,tc,tsv,<< %r4,%r5,%r6
sub,tc,tsv,<<= %r4,%r5,%r6
sub,tc,tsv,sv %r4,%r5,%r6
sub,tc,tsv,od %r4,%r5,%r6
sub,tsv,tc,tr %r4,%r5,%r6
sub,tsv,tc,<> %r4,%r5,%r6
sub,tsv,tc,>= %r4,%r5,%r6
sub,tsv,tc,> %r4,%r5,%r6
sub,tsv,tc,>>= %r4,%r5,%r6
sub,tsv,tc,>> %r4,%r5,%r6
sub,tsv,tc,nsv %r4,%r5,%r6
sub,tsv,tc,ev %r4,%r5,%r6
|
tactcomplabs/xbgas-binutils-gdb
| 4,422
|
gas/testsuite/gas/hppa/basic/shladd2.s
|
.LEVEL 2.0
.code
.align 4
; PA2.0 shladd instruction tests.
;
; We could/should test some of the corner cases for register and
; immediate fields. We should also check the assorted field
; selectors to make sure they're handled correctly.
shladd,* %r4,1,%r5,%r6
shladd,*= %r4,1,%r5,%r6
shladd,*< %r4,1,%r5,%r6
shladd,*<= %r4,1,%r5,%r6
shladd,*nuv %r4,1,%r5,%r6
shladd,*znv %r4,1,%r5,%r6
shladd,*sv %r4,1,%r5,%r6
shladd,*od %r4,1,%r5,%r6
shladd,*tr %r4,1,%r5,%r6
shladd,*<> %r4,1,%r5,%r6
shladd,*>= %r4,1,%r5,%r6
shladd,*> %r4,1,%r5,%r6
shladd,*uv %r4,1,%r5,%r6
shladd,*vnz %r4,1,%r5,%r6
shladd,*nsv %r4,1,%r5,%r6
shladd,*ev %r4,1,%r5,%r6
shladd,l,* %r4,1,%r5,%r6
shladd,l,*= %r4,1,%r5,%r6
shladd,l,*< %r4,1,%r5,%r6
shladd,l,*<= %r4,1,%r5,%r6
shladd,l,*nuv %r4,1,%r5,%r6
shladd,l,*znv %r4,1,%r5,%r6
shladd,l,*sv %r4,1,%r5,%r6
shladd,l,*od %r4,1,%r5,%r6
shladd,l,*tr %r4,1,%r5,%r6
shladd,l,*<> %r4,1,%r5,%r6
shladd,l,*>= %r4,1,%r5,%r6
shladd,l,*> %r4,1,%r5,%r6
shladd,l,*uv %r4,1,%r5,%r6
shladd,l,*vnz %r4,1,%r5,%r6
shladd,l,*nsv %r4,1,%r5,%r6
shladd,l,*ev %r4,1,%r5,%r6
shladd,tsv,* %r4,1,%r5,%r6
shladd,tsv,*= %r4,1,%r5,%r6
shladd,tsv,*< %r4,1,%r5,%r6
shladd,tsv,*<= %r4,1,%r5,%r6
shladd,tsv,*nuv %r4,1,%r5,%r6
shladd,tsv,*znv %r4,1,%r5,%r6
shladd,tsv,*sv %r4,1,%r5,%r6
shladd,tsv,*od %r4,1,%r5,%r6
shladd,tsv,*tr %r4,1,%r5,%r6
shladd,tsv,*<> %r4,1,%r5,%r6
shladd,tsv,*>= %r4,1,%r5,%r6
shladd,tsv,*> %r4,1,%r5,%r6
shladd,tsv,*uv %r4,1,%r5,%r6
shladd,tsv,*vnz %r4,1,%r5,%r6
shladd,tsv,*nsv %r4,1,%r5,%r6
shladd,tsv,*ev %r4,1,%r5,%r6
shladd,* %r4,2,%r5,%r6
shladd,*= %r4,2,%r5,%r6
shladd,*< %r4,2,%r5,%r6
shladd,*<= %r4,2,%r5,%r6
shladd,*nuv %r4,2,%r5,%r6
shladd,*znv %r4,2,%r5,%r6
shladd,*sv %r4,2,%r5,%r6
shladd,*od %r4,2,%r5,%r6
shladd,*tr %r4,2,%r5,%r6
shladd,*<> %r4,2,%r5,%r6
shladd,*>= %r4,2,%r5,%r6
shladd,*> %r4,2,%r5,%r6
shladd,*uv %r4,2,%r5,%r6
shladd,*vnz %r4,2,%r5,%r6
shladd,*nsv %r4,2,%r5,%r6
shladd,*ev %r4,2,%r5,%r6
shladd,l,* %r4,2,%r5,%r6
shladd,l,*= %r4,2,%r5,%r6
shladd,l,*< %r4,2,%r5,%r6
shladd,l,*<= %r4,2,%r5,%r6
shladd,l,*nuv %r4,2,%r5,%r6
shladd,l,*znv %r4,2,%r5,%r6
shladd,l,*sv %r4,2,%r5,%r6
shladd,l,*od %r4,2,%r5,%r6
shladd,l,*tr %r4,2,%r5,%r6
shladd,l,*<> %r4,2,%r5,%r6
shladd,l,*>= %r4,2,%r5,%r6
shladd,l,*> %r4,2,%r5,%r6
shladd,l,*uv %r4,2,%r5,%r6
shladd,l,*vnz %r4,2,%r5,%r6
shladd,l,*nsv %r4,2,%r5,%r6
shladd,l,*ev %r4,2,%r5,%r6
shladd,tsv,* %r4,2,%r5,%r6
shladd,tsv,*= %r4,2,%r5,%r6
shladd,tsv,*< %r4,2,%r5,%r6
shladd,tsv,*<= %r4,2,%r5,%r6
shladd,tsv,*nuv %r4,2,%r5,%r6
shladd,tsv,*znv %r4,2,%r5,%r6
shladd,tsv,*sv %r4,2,%r5,%r6
shladd,tsv,*od %r4,2,%r5,%r6
shladd,tsv,*tr %r4,2,%r5,%r6
shladd,tsv,*<> %r4,2,%r5,%r6
shladd,tsv,*>= %r4,2,%r5,%r6
shladd,tsv,*> %r4,2,%r5,%r6
shladd,tsv,*uv %r4,2,%r5,%r6
shladd,tsv,*vnz %r4,2,%r5,%r6
shladd,tsv,*nsv %r4,2,%r5,%r6
shladd,tsv,*ev %r4,2,%r5,%r6
shladd,* %r4,3,%r5,%r6
shladd,*= %r4,3,%r5,%r6
shladd,*< %r4,3,%r5,%r6
shladd,*<= %r4,3,%r5,%r6
shladd,*nuv %r4,3,%r5,%r6
shladd,*znv %r4,3,%r5,%r6
shladd,*sv %r4,3,%r5,%r6
shladd,*od %r4,3,%r5,%r6
shladd,*tr %r4,3,%r5,%r6
shladd,*<> %r4,3,%r5,%r6
shladd,*>= %r4,3,%r5,%r6
shladd,*> %r4,3,%r5,%r6
shladd,*uv %r4,3,%r5,%r6
shladd,*vnz %r4,3,%r5,%r6
shladd,*nsv %r4,3,%r5,%r6
shladd,*ev %r4,3,%r5,%r6
shladd,l,* %r4,3,%r5,%r6
shladd,l,*= %r4,3,%r5,%r6
shladd,l,*< %r4,3,%r5,%r6
shladd,l,*<= %r4,3,%r5,%r6
shladd,l,*nuv %r4,3,%r5,%r6
shladd,l,*znv %r4,3,%r5,%r6
shladd,l,*sv %r4,3,%r5,%r6
shladd,l,*od %r4,3,%r5,%r6
shladd,l,*tr %r4,3,%r5,%r6
shladd,l,*<> %r4,3,%r5,%r6
shladd,l,*>= %r4,3,%r5,%r6
shladd,l,*> %r4,3,%r5,%r6
shladd,l,*uv %r4,3,%r5,%r6
shladd,l,*vnz %r4,3,%r5,%r6
shladd,l,*nsv %r4,3,%r5,%r6
shladd,l,*ev %r4,3,%r5,%r6
shladd,tsv,* %r4,3,%r5,%r6
shladd,tsv,*= %r4,3,%r5,%r6
shladd,tsv,*< %r4,3,%r5,%r6
shladd,tsv,*<= %r4,3,%r5,%r6
shladd,tsv,*nuv %r4,3,%r5,%r6
shladd,tsv,*znv %r4,3,%r5,%r6
shladd,tsv,*sv %r4,3,%r5,%r6
shladd,tsv,*od %r4,3,%r5,%r6
shladd,tsv,*tr %r4,3,%r5,%r6
shladd,tsv,*<> %r4,3,%r5,%r6
shladd,tsv,*>= %r4,3,%r5,%r6
shladd,tsv,*> %r4,3,%r5,%r6
shladd,tsv,*uv %r4,3,%r5,%r6
shladd,tsv,*vnz %r4,3,%r5,%r6
shladd,tsv,*nsv %r4,3,%r5,%r6
shladd,tsv,*ev %r4,3,%r5,%r6
|
tactcomplabs/xbgas-binutils-gdb
| 2,985
|
gas/testsuite/gas/hppa/basic/addi.s
|
.code
.align 4
; Basic add immediate instruction tests.
;
; We could/should test some of the corner cases for register and
; immediate fields. We should also check the assorted field
; selectors to make sure they're handled correctly.
addi 123,%r5,%r6
addi,= 123,%r5,%r6
addi,< 123,%r5,%r6
addi,<= 123,%r5,%r6
addi,nuv 123,%r5,%r6
addi,znv 123,%r5,%r6
addi,sv 123,%r5,%r6
addi,od 123,%r5,%r6
addi,tr 123,%r5,%r6
addi,<> 123,%r5,%r6
addi,>= 123,%r5,%r6
addi,> 123,%r5,%r6
addi,uv 123,%r5,%r6
addi,vnz 123,%r5,%r6
addi,nsv 123,%r5,%r6
addi,ev 123,%r5,%r6
addio 123,%r5,%r6
addio,= 123,%r5,%r6
addio,< 123,%r5,%r6
addio,<= 123,%r5,%r6
addio,nuv 123,%r5,%r6
addio,znv 123,%r5,%r6
addio,sv 123,%r5,%r6
addio,od 123,%r5,%r6
addio,tr 123,%r5,%r6
addio,<> 123,%r5,%r6
addio,>= 123,%r5,%r6
addio,> 123,%r5,%r6
addio,uv 123,%r5,%r6
addio,vnz 123,%r5,%r6
addio,nsv 123,%r5,%r6
addio,ev 123,%r5,%r6
addit 123,%r5,%r6
addit,= 123,%r5,%r6
addit,< 123,%r5,%r6
addit,<= 123,%r5,%r6
addit,nuv 123,%r5,%r6
addit,znv 123,%r5,%r6
addit,sv 123,%r5,%r6
addit,od 123,%r5,%r6
addit,tr 123,%r5,%r6
addit,<> 123,%r5,%r6
addit,>= 123,%r5,%r6
addit,> 123,%r5,%r6
addit,uv 123,%r5,%r6
addit,vnz 123,%r5,%r6
addit,nsv 123,%r5,%r6
addit,ev 123,%r5,%r6
addito 123,%r5,%r6
addito,= 123,%r5,%r6
addito,< 123,%r5,%r6
addito,<= 123,%r5,%r6
addito,nuv 123,%r5,%r6
addito,znv 123,%r5,%r6
addito,sv 123,%r5,%r6
addito,od 123,%r5,%r6
addito,tr 123,%r5,%r6
addito,<> 123,%r5,%r6
addito,>= 123,%r5,%r6
addito,> 123,%r5,%r6
addito,uv 123,%r5,%r6
addito,vnz 123,%r5,%r6
addito,nsv 123,%r5,%r6
addito,ev 123,%r5,%r6
addi,tsv 123,%r5,%r6
addi,tsv,= 123,%r5,%r6
addi,tsv,< 123,%r5,%r6
addi,tsv,<= 123,%r5,%r6
addi,tsv,nuv 123,%r5,%r6
addi,tsv,znv 123,%r5,%r6
addi,tsv,sv 123,%r5,%r6
addi,tsv,od 123,%r5,%r6
addi,tsv,tr 123,%r5,%r6
addi,tsv,<> 123,%r5,%r6
addi,tsv,>= 123,%r5,%r6
addi,tsv,> 123,%r5,%r6
addi,tsv,uv 123,%r5,%r6
addi,tsv,vnz 123,%r5,%r6
addi,tsv,nsv 123,%r5,%r6
addi,tsv,ev 123,%r5,%r6
addi,tc 123,%r5,%r6
addi,tc,= 123,%r5,%r6
addi,tc,< 123,%r5,%r6
addi,tc,<= 123,%r5,%r6
addi,tc,nuv 123,%r5,%r6
addi,tc,znv 123,%r5,%r6
addi,tc,sv 123,%r5,%r6
addi,tc,od 123,%r5,%r6
addi,tc,tr 123,%r5,%r6
addi,tc,<> 123,%r5,%r6
addi,tc,>= 123,%r5,%r6
addi,tc,> 123,%r5,%r6
addi,tc,uv 123,%r5,%r6
addi,tc,vnz 123,%r5,%r6
addi,tc,nsv 123,%r5,%r6
addi,tc,ev 123,%r5,%r6
addi,tc,tsv 123,%r5,%r6
addi,tc,tsv,= 123,%r5,%r6
addi,tc,tsv,< 123,%r5,%r6
addi,tc,tsv,<= 123,%r5,%r6
addi,tc,tsv,nuv 123,%r5,%r6
addi,tc,tsv,znv 123,%r5,%r6
addi,tc,tsv,sv 123,%r5,%r6
addi,tc,tsv,od 123,%r5,%r6
addi,tsv,tc,tr 123,%r5,%r6
addi,tsv,tc,<> 123,%r5,%r6
addi,tsv,tc,>= 123,%r5,%r6
addi,tsv,tc,> 123,%r5,%r6
addi,tsv,tc,uv 123,%r5,%r6
addi,tsv,tc,vnz 123,%r5,%r6
addi,tsv,tc,nsv 123,%r5,%r6
addi,tsv,tc,ev 123,%r5,%r6
|
tactcomplabs/xbgas-binutils-gdb
| 1,256
|
gas/testsuite/gas/hppa/basic/coprmem.s
|
.code
.align 4
; Basic copr memory tests which also test the various
; addressing modes and completers.
;
; We could/should test some of the corner cases for register and
; immediate fields. We should also check the assorted field
; selectors to make sure they're handled correctly.
;
copr_indexing_load:
cldwx,4 %r5(%sr0,%r4),%r26
cldwx,4,s %r5(%sr0,%r4),%r26
cldwx,4,m %r5(%sr0,%r4),%r26
cldwx,4,sm %r5(%sr0,%r4),%r26
clddx,4 %r5(%sr0,%r4),%r26
clddx,4,s %r5(%sr0,%r4),%r26
clddx,4,m %r5(%sr0,%r4),%r26
clddx,4,sm %r5(%sr0,%r4),%r26
copr_indexing_store:
cstwx,4 %r26,%r5(%sr0,%r4)
cstwx,4,s %r26,%r5(%sr0,%r4)
cstwx,4,m %r26,%r5(%sr0,%r4)
cstwx,4,sm %r26,%r5(%sr0,%r4)
cstdx,4 %r26,%r5(%sr0,%r4)
cstdx,4,s %r26,%r5(%sr0,%r4)
cstdx,4,m %r26,%r5(%sr0,%r4)
cstdx,4,sm %r26,%r5(%sr0,%r4)
copr_short_memory:
cldws,4 0(%sr0,%r4),%r26
cldws,4,mb 0(%sr0,%r4),%r26
cldws,4,ma 0(%sr0,%r4),%r26
cldds,4 0(%sr0,%r4),%r26
cldds,4,mb 0(%sr0,%r4),%r26
cldds,4,ma 0(%sr0,%r4),%r26
cstws,4 %r26,0(%sr0,%r4)
cstws,4,mb %r26,0(%sr0,%r4)
cstws,4,ma %r26,0(%sr0,%r4)
cstds,4 %r26,0(%sr0,%r4)
cstds,4,mb %r26,0(%sr0,%r4)
cstds,4,ma %r26,0(%sr0,%r4)
; gas fucks this up thinks it gets the expression 4 modulo 5
; cldwx,4 %r5(0,%r4),%r%r26
|
tactcomplabs/xbgas-binutils-gdb
| 2,551
|
gas/testsuite/gas/hppa/basic/fp_fcmp.s
|
.code
.align 4
; Basic immediate instruction tests.
;
; We could/should test some of the corner cases for register and
; immediate fields. We should also check the assorted field
; selectors to make sure they're handled correctly.
fcmp,sgl,false? %fr4,%fr5
fcmp,sgl,false %fr4,%fr5
fcmp,sgl,? %fr4,%fr5
fcmp,sgl,!<=> %fr4,%fr5
fcmp,sgl,= %fr4,%fr5
fcmp,sgl,=T %fr4,%fr5
fcmp,sgl,?= %fr4,%fr5
fcmp,sgl,!<> %fr4,%fr5
fcmp,sgl,!?>= %fr4,%fr5
fcmp,sgl,< %fr4,%fr5
fcmp,sgl,?< %fr4,%fr5
fcmp,sgl,!>= %fr4,%fr5
fcmp,sgl,!?> %fr4,%fr5
fcmp,sgl,<= %fr4,%fr5
fcmp,sgl,?<= %fr4,%fr5
fcmp,sgl,!> %fr4,%fr5
fcmp,sgl,!?<= %fr4,%fr5
fcmp,sgl,> %fr4,%fr5
fcmp,sgl,?> %fr4,%fr5
fcmp,sgl,!<= %fr4,%fr5
fcmp,sgl,!?< %fr4,%fr5
fcmp,sgl,>= %fr4,%fr5
fcmp,sgl,?>= %fr4,%fr5
fcmp,sgl,!< %fr4,%fr5
fcmp,sgl,!?= %fr4,%fr5
fcmp,sgl,<> %fr4,%fr5
fcmp,sgl,!= %fr4,%fr5
fcmp,sgl,!=T %fr4,%fr5
fcmp,sgl,!? %fr4,%fr5
fcmp,sgl,<=> %fr4,%fr5
fcmp,sgl,true? %fr4,%fr5
fcmp,sgl,true %fr4,%fr5
fcmp,dbl,false? %fr4,%fr5
fcmp,dbl,false %fr4,%fr5
fcmp,dbl,? %fr4,%fr5
fcmp,dbl,!<=> %fr4,%fr5
fcmp,dbl,= %fr4,%fr5
fcmp,dbl,=T %fr4,%fr5
fcmp,dbl,?= %fr4,%fr5
fcmp,dbl,!<> %fr4,%fr5
fcmp,dbl,!?>= %fr4,%fr5
fcmp,dbl,< %fr4,%fr5
fcmp,dbl,?< %fr4,%fr5
fcmp,dbl,!>= %fr4,%fr5
fcmp,dbl,!?> %fr4,%fr5
fcmp,dbl,<= %fr4,%fr5
fcmp,dbl,?<= %fr4,%fr5
fcmp,dbl,!> %fr4,%fr5
fcmp,dbl,!?<= %fr4,%fr5
fcmp,dbl,> %fr4,%fr5
fcmp,dbl,?> %fr4,%fr5
fcmp,dbl,!<= %fr4,%fr5
fcmp,dbl,!?< %fr4,%fr5
fcmp,dbl,>= %fr4,%fr5
fcmp,dbl,?>= %fr4,%fr5
fcmp,dbl,!< %fr4,%fr5
fcmp,dbl,!?= %fr4,%fr5
fcmp,dbl,<> %fr4,%fr5
fcmp,dbl,!= %fr4,%fr5
fcmp,dbl,!=T %fr4,%fr5
fcmp,dbl,!? %fr4,%fr5
fcmp,dbl,<=> %fr4,%fr5
fcmp,dbl,true? %fr4,%fr5
fcmp,dbl,true %fr4,%fr5
fcmp,quad,false? %fr4,%fr5
fcmp,quad,false %fr4,%fr5
fcmp,quad,? %fr4,%fr5
fcmp,quad,!<=> %fr4,%fr5
fcmp,quad,= %fr4,%fr5
fcmp,quad,=T %fr4,%fr5
fcmp,quad,?= %fr4,%fr5
fcmp,quad,!<> %fr4,%fr5
fcmp,quad,!?>= %fr4,%fr5
fcmp,quad,< %fr4,%fr5
fcmp,quad,?< %fr4,%fr5
fcmp,quad,!>= %fr4,%fr5
fcmp,quad,!?> %fr4,%fr5
fcmp,quad,<= %fr4,%fr5
fcmp,quad,?<= %fr4,%fr5
fcmp,quad,!> %fr4,%fr5
fcmp,quad,!?<= %fr4,%fr5
fcmp,quad,> %fr4,%fr5
fcmp,quad,?> %fr4,%fr5
fcmp,quad,!<= %fr4,%fr5
fcmp,quad,!?< %fr4,%fr5
fcmp,quad,>= %fr4,%fr5
fcmp,quad,?>= %fr4,%fr5
fcmp,quad,!< %fr4,%fr5
fcmp,quad,!?= %fr4,%fr5
fcmp,quad,<> %fr4,%fr5
fcmp,quad,!= %fr4,%fr5
fcmp,quad,!=T %fr4,%fr5
fcmp,quad,!? %fr4,%fr5
fcmp,quad,<=> %fr4,%fr5
fcmp,quad,true? %fr4,%fr5
fcmp,quad,true %fr4,%fr5
|
tactcomplabs/xbgas-binutils-gdb
| 1,823
|
gas/testsuite/gas/hppa/basic/deposit3.s
|
.LEVEL 2.0
.code
.align 4
; PA 2.0 Deposit instruction tests.
;
; We could/should test some of the corner cases for register and
; immediate fields. We should also check the assorted field
; selectors to make sure they're handled correctly.
depd,z,* %r4,10,5,%r6
depd,z,*= %r4,10,5,%r6
depd,z,*< %r4,10,5,%r6
depd,z,*od %r4,10,5,%r6
depd,z,*tr %r4,10,5,%r6
depd,z,*<> %r4,10,5,%r6
depd,z,*>= %r4,10,5,%r6
depd,z,*ev %r4,10,5,%r6
depd,* %r4,10,5,%r6
depd,*= %r4,10,5,%r6
depd,*< %r4,10,5,%r6
depd,*od %r4,10,5,%r6
depd,*tr %r4,10,5,%r6
depd,*<> %r4,10,5,%r6
depd,*>= %r4,10,5,%r6
depd,*ev %r4,10,5,%r6
depd,z,* %r4,%sar,5,%r6
depd,z,*= %r4,%sar,5,%r6
depd,z,*< %r4,%sar,5,%r6
depd,z,*od %r4,%sar,5,%r6
depd,z,*tr %r4,%sar,5,%r6
depd,z,*<> %r4,%sar,5,%r6
depd,z,*>= %r4,%sar,5,%r6
depd,z,*ev %r4,%sar,5,%r6
depd,* %r4,%sar,5,%r6
depd,*= %r4,%sar,5,%r6
depd,*< %r4,%sar,5,%r6
depd,*od %r4,%sar,5,%r6
depd,*tr %r4,%sar,5,%r6
depd,*<> %r4,%sar,5,%r6
depd,*>= %r4,%sar,5,%r6
depd,*ev %r4,%sar,5,%r6
depdi,* -1,%sar,5,%r6
depdi,*= -1,%sar,5,%r6
depdi,*< -1,%sar,5,%r6
depdi,*od -1,%sar,5,%r6
depdi,*tr -1,%sar,5,%r6
depdi,*<> -1,%sar,5,%r6
depdi,*>= -1,%sar,5,%r6
depdi,*ev -1,%sar,5,%r6
depdi,z,* -1,%sar,5,%r6
depdi,z,*= -1,%sar,5,%r6
depdi,z,*< -1,%sar,5,%r6
depdi,z,*od -1,%sar,5,%r6
depdi,z,*tr -1,%sar,5,%r6
depdi,z,*<> -1,%sar,5,%r6
depdi,z,*>= -1,%sar,5,%r6
depdi,z,*ev -1,%sar,5,%r6
depdi,* -1,10,4,%r6
depdi,*= -1,10,4,%r6
depdi,*< -1,10,4,%r6
depdi,*od -1,10,4,%r6
depdi,*tr -1,10,4,%r6
depdi,*<> -1,10,4,%r6
depdi,*>= -1,10,4,%r6
depdi,*ev -1,10,4,%r6
depdi,z,* -1,10,4,%r6
depdi,z,*= -1,10,4,%r6
depdi,z,*< -1,10,4,%r6
depdi,z,*od -1,10,4,%r6
depdi,z,*tr -1,10,4,%r6
depdi,z,*<> -1,10,4,%r6
depdi,z,*>= -1,10,4,%r6
depdi,z,*ev -1,10,4,%r6
|
tactcomplabs/xbgas-binutils-gdb
| 2,287
|
gas/testsuite/gas/hppa/basic/fp_conv.s
|
.code
.align 4
; Basic immediate instruction tests.
;
; We could/should test some of the corner cases for register and
; immediate fields. We should also check the assorted field
; selectors to make sure they're handled correctly.
fcnvff,sgl,sgl %fr5,%fr10
fcnvff,sgl,dbl %fr5,%fr10
fcnvff,sgl,quad %fr5,%fr10
fcnvff,dbl,sgl %fr5,%fr10
fcnvff,dbl,dbl %fr5,%fr10
fcnvff,dbl,quad %fr5,%fr10
fcnvff,quad,sgl %fr5,%fr10
fcnvff,quad,dbl %fr5,%fr10
fcnvff,quad,quad %fr5,%fr10
fcnvff,sgl,sgl %fr20,%fr24
fcnvff,sgl,dbl %fr20,%fr24
fcnvff,sgl,quad %fr20,%fr24
fcnvff,dbl,sgl %fr20,%fr24
fcnvff,dbl,dbl %fr20,%fr24
fcnvff,dbl,quad %fr20,%fr24
fcnvff,quad,sgl %fr20,%fr24
fcnvff,quad,dbl %fr20,%fr24
fcnvff,quad,quad %fr20,%fr24
fcnvxf,sgl,sgl %fr5,%fr10
fcnvxf,sgl,dbl %fr5,%fr10
fcnvxf,sgl,quad %fr5,%fr10
fcnvxf,dbl,sgl %fr5,%fr10
fcnvxf,dbl,dbl %fr5,%fr10
fcnvxf,dbl,quad %fr5,%fr10
fcnvxf,quad,sgl %fr5,%fr10
fcnvxf,quad,dbl %fr5,%fr10
fcnvxf,quad,quad %fr5,%fr10
fcnvxf,sgl,sgl %fr20,%fr24
fcnvxf,sgl,dbl %fr20,%fr24
fcnvxf,sgl,quad %fr20,%fr24
fcnvxf,dbl,sgl %fr20,%fr24
fcnvxf,dbl,dbl %fr20,%fr24
fcnvxf,dbl,quad %fr20,%fr24
fcnvxf,quad,sgl %fr20,%fr24
fcnvxf,quad,dbl %fr20,%fr24
fcnvxf,quad,quad %fr20,%fr24
fcnvfx,sgl,sgl %fr5,%fr10
fcnvfx,sgl,dbl %fr5,%fr10
fcnvfx,sgl,quad %fr5,%fr10
fcnvfx,dbl,sgl %fr5,%fr10
fcnvfx,dbl,dbl %fr5,%fr10
fcnvfx,dbl,quad %fr5,%fr10
fcnvfx,quad,sgl %fr5,%fr10
fcnvfx,quad,dbl %fr5,%fr10
fcnvfx,quad,quad %fr5,%fr10
fcnvfx,sgl,sgl %fr20,%fr24
fcnvfx,sgl,dbl %fr20,%fr24
fcnvfx,sgl,quad %fr20,%fr24
fcnvfx,dbl,sgl %fr20,%fr24
fcnvfx,dbl,dbl %fr20,%fr24
fcnvfx,dbl,quad %fr20,%fr24
fcnvfx,quad,sgl %fr20,%fr24
fcnvfx,quad,dbl %fr20,%fr24
fcnvfx,quad,quad %fr20,%fr24
fcnvfxt,sgl,sgl %fr5,%fr10
fcnvfxt,sgl,dbl %fr5,%fr10
fcnvfxt,sgl,quad %fr5,%fr10
fcnvfxt,dbl,sgl %fr5,%fr10
fcnvfxt,dbl,dbl %fr5,%fr10
fcnvfxt,dbl,quad %fr5,%fr10
fcnvfxt,quad,sgl %fr5,%fr10
fcnvfxt,quad,dbl %fr5,%fr10
fcnvfxt,quad,quad %fr5,%fr10
fcnvfxt,sgl,sgl %fr20,%fr24
fcnvfxt,sgl,dbl %fr20,%fr24
fcnvfxt,sgl,quad %fr20,%fr24
fcnvfxt,dbl,sgl %fr20,%fr24
fcnvfxt,dbl,dbl %fr20,%fr24
fcnvfxt,dbl,quad %fr20,%fr24
fcnvfxt,quad,sgl %fr20,%fr24
fcnvfxt,quad,dbl %fr20,%fr24
fcnvfxt,quad,quad %fr20,%fr24
|
tactcomplabs/xbgas-binutils-gdb
| 1,418
|
gas/testsuite/gas/hppa/basic/sh1add.s
|
.code
.align 4
; Basic immediate instruction tests.
;
; We could/should test some of the corner cases for register and
; immediate fields. We should also check the assorted field
; selectors to make sure they're handled correctly.
sh1add %r4,%r5,%r6
sh1add,= %r4,%r5,%r6
sh1add,< %r4,%r5,%r6
sh1add,<= %r4,%r5,%r6
sh1add,nuv %r4,%r5,%r6
sh1add,znv %r4,%r5,%r6
sh1add,sv %r4,%r5,%r6
sh1add,od %r4,%r5,%r6
sh1add,tr %r4,%r5,%r6
sh1add,<> %r4,%r5,%r6
sh1add,>= %r4,%r5,%r6
sh1add,> %r4,%r5,%r6
sh1add,uv %r4,%r5,%r6
sh1add,vnz %r4,%r5,%r6
sh1add,nsv %r4,%r5,%r6
sh1add,ev %r4,%r5,%r6
sh1addl %r4,%r5,%r6
sh1addl,= %r4,%r5,%r6
sh1addl,< %r4,%r5,%r6
sh1addl,<= %r4,%r5,%r6
sh1addl,nuv %r4,%r5,%r6
sh1addl,znv %r4,%r5,%r6
sh1addl,sv %r4,%r5,%r6
sh1addl,od %r4,%r5,%r6
sh1addl,tr %r4,%r5,%r6
sh1addl,<> %r4,%r5,%r6
sh1addl,>= %r4,%r5,%r6
sh1addl,> %r4,%r5,%r6
sh1addl,uv %r4,%r5,%r6
sh1addl,vnz %r4,%r5,%r6
sh1addl,nsv %r4,%r5,%r6
sh1addl,ev %r4,%r5,%r6
sh1addo %r4,%r5,%r6
sh1addo,= %r4,%r5,%r6
sh1addo,< %r4,%r5,%r6
sh1addo,<= %r4,%r5,%r6
sh1addo,nuv %r4,%r5,%r6
sh1addo,znv %r4,%r5,%r6
sh1addo,sv %r4,%r5,%r6
sh1addo,od %r4,%r5,%r6
sh1addo,tr %r4,%r5,%r6
sh1addo,<> %r4,%r5,%r6
sh1addo,>= %r4,%r5,%r6
sh1addo,> %r4,%r5,%r6
sh1addo,uv %r4,%r5,%r6
sh1addo,vnz %r4,%r5,%r6
sh1addo,nsv %r4,%r5,%r6
sh1addo,ev %r4,%r5,%r6
|
tactcomplabs/xbgas-binutils-gdb
| 1,272
|
gas/testsuite/gas/hppa/basic/unit.s
|
.level 1.1
.code
.align 4
; Basic unit instruction tests.
;
; We could/should test some of the corner cases for register and
; immediate fields. We should also check the assorted field
; selectors to make sure they're handled correctly.
uxor %r4,%r5,%r6
uxor,sbz %r4,%r5,%r6
uxor,shz %r4,%r5,%r6
uxor,tr %r4,%r5,%r6
uxor,nbz %r4,%r5,%r6
uxor,nhz %r4,%r5,%r6
uaddcm %r4,%r5,%r6
uaddcm,sbz %r4,%r5,%r6
uaddcm,shz %r4,%r5,%r6
uaddcm,sdc %r4,%r5,%r6
uaddcm,sbc %r4,%r5,%r6
uaddcm,shc %r4,%r5,%r6
uaddcm,tr %r4,%r5,%r6
uaddcm,nbz %r4,%r5,%r6
uaddcm,nhz %r4,%r5,%r6
uaddcm,ndc %r4,%r5,%r6
uaddcm,nbc %r4,%r5,%r6
uaddcm,nhc %r4,%r5,%r6
uaddcmt %r4,%r5,%r6
uaddcmt,sbz %r4,%r5,%r6
uaddcmt,shz %r4,%r5,%r6
uaddcmt,sdc %r4,%r5,%r6
uaddcmt,sbc %r4,%r5,%r6
uaddcmt,shc %r4,%r5,%r6
uaddcmt,tr %r4,%r5,%r6
uaddcmt,nbz %r4,%r5,%r6
uaddcmt,nhz %r4,%r5,%r6
uaddcmt,ndc %r4,%r5,%r6
uaddcmt,nbc %r4,%r5,%r6
uaddcmt,nhc %r4,%r5,%r6
uaddcm,tc %r4,%r5,%r6
uaddcm,tc,sbz %r4,%r5,%r6
uaddcm,tc,shz %r4,%r5,%r6
uaddcm,tc,sdc %r4,%r5,%r6
uaddcm,tc,sbc %r4,%r5,%r6
uaddcm,tc,shc %r4,%r5,%r6
uaddcm,tc,tr %r4,%r5,%r6
uaddcm,tc,nbz %r4,%r5,%r6
uaddcm,tc,nhz %r4,%r5,%r6
uaddcm,tc,ndc %r4,%r5,%r6
uaddcm,tc,nbc %r4,%r5,%r6
uaddcm,tc,nhc %r4,%r5,%r6
|
tactcomplabs/xbgas-binutils-gdb
| 4,269
|
gas/testsuite/gas/hppa/basic/shladd.s
|
.level 1.1
.code
.align 4
; Basic shladd instruction tests.
;
; We could/should test some of the corner cases for register and
; immediate fields. We should also check the assorted field
; selectors to make sure they're handled correctly.
shladd %r4,1,%r5,%r6
shladd,= %r4,1,%r5,%r6
shladd,< %r4,1,%r5,%r6
shladd,<= %r4,1,%r5,%r6
shladd,nuv %r4,1,%r5,%r6
shladd,znv %r4,1,%r5,%r6
shladd,sv %r4,1,%r5,%r6
shladd,od %r4,1,%r5,%r6
shladd,tr %r4,1,%r5,%r6
shladd,<> %r4,1,%r5,%r6
shladd,>= %r4,1,%r5,%r6
shladd,> %r4,1,%r5,%r6
shladd,uv %r4,1,%r5,%r6
shladd,vnz %r4,1,%r5,%r6
shladd,nsv %r4,1,%r5,%r6
shladd,ev %r4,1,%r5,%r6
shladd,l %r4,1,%r5,%r6
shladd,l,= %r4,1,%r5,%r6
shladd,l,< %r4,1,%r5,%r6
shladd,l,<= %r4,1,%r5,%r6
shladd,l,nuv %r4,1,%r5,%r6
shladd,l,znv %r4,1,%r5,%r6
shladd,l,sv %r4,1,%r5,%r6
shladd,l,od %r4,1,%r5,%r6
shladd,l,tr %r4,1,%r5,%r6
shladd,l,<> %r4,1,%r5,%r6
shladd,l,>= %r4,1,%r5,%r6
shladd,l,> %r4,1,%r5,%r6
shladd,l,uv %r4,1,%r5,%r6
shladd,l,vnz %r4,1,%r5,%r6
shladd,l,nsv %r4,1,%r5,%r6
shladd,l,ev %r4,1,%r5,%r6
shladd,tsv %r4,1,%r5,%r6
shladd,tsv,= %r4,1,%r5,%r6
shladd,tsv,< %r4,1,%r5,%r6
shladd,tsv,<= %r4,1,%r5,%r6
shladd,tsv,nuv %r4,1,%r5,%r6
shladd,tsv,znv %r4,1,%r5,%r6
shladd,tsv,sv %r4,1,%r5,%r6
shladd,tsv,od %r4,1,%r5,%r6
shladd,tsv,tr %r4,1,%r5,%r6
shladd,tsv,<> %r4,1,%r5,%r6
shladd,tsv,>= %r4,1,%r5,%r6
shladd,tsv,> %r4,1,%r5,%r6
shladd,tsv,uv %r4,1,%r5,%r6
shladd,tsv,vnz %r4,1,%r5,%r6
shladd,tsv,nsv %r4,1,%r5,%r6
shladd,tsv,ev %r4,1,%r5,%r6
shladd %r4,2,%r5,%r6
shladd,= %r4,2,%r5,%r6
shladd,< %r4,2,%r5,%r6
shladd,<= %r4,2,%r5,%r6
shladd,nuv %r4,2,%r5,%r6
shladd,znv %r4,2,%r5,%r6
shladd,sv %r4,2,%r5,%r6
shladd,od %r4,2,%r5,%r6
shladd,tr %r4,2,%r5,%r6
shladd,<> %r4,2,%r5,%r6
shladd,>= %r4,2,%r5,%r6
shladd,> %r4,2,%r5,%r6
shladd,uv %r4,2,%r5,%r6
shladd,vnz %r4,2,%r5,%r6
shladd,nsv %r4,2,%r5,%r6
shladd,ev %r4,2,%r5,%r6
shladd,l %r4,2,%r5,%r6
shladd,l,= %r4,2,%r5,%r6
shladd,l,< %r4,2,%r5,%r6
shladd,l,<= %r4,2,%r5,%r6
shladd,l,nuv %r4,2,%r5,%r6
shladd,l,znv %r4,2,%r5,%r6
shladd,l,sv %r4,2,%r5,%r6
shladd,l,od %r4,2,%r5,%r6
shladd,l,tr %r4,2,%r5,%r6
shladd,l,<> %r4,2,%r5,%r6
shladd,l,>= %r4,2,%r5,%r6
shladd,l,> %r4,2,%r5,%r6
shladd,l,uv %r4,2,%r5,%r6
shladd,l,vnz %r4,2,%r5,%r6
shladd,l,nsv %r4,2,%r5,%r6
shladd,l,ev %r4,2,%r5,%r6
shladd,tsv %r4,2,%r5,%r6
shladd,tsv,= %r4,2,%r5,%r6
shladd,tsv,< %r4,2,%r5,%r6
shladd,tsv,<= %r4,2,%r5,%r6
shladd,tsv,nuv %r4,2,%r5,%r6
shladd,tsv,znv %r4,2,%r5,%r6
shladd,tsv,sv %r4,2,%r5,%r6
shladd,tsv,od %r4,2,%r5,%r6
shladd,tsv,tr %r4,2,%r5,%r6
shladd,tsv,<> %r4,2,%r5,%r6
shladd,tsv,>= %r4,2,%r5,%r6
shladd,tsv,> %r4,2,%r5,%r6
shladd,tsv,uv %r4,2,%r5,%r6
shladd,tsv,vnz %r4,2,%r5,%r6
shladd,tsv,nsv %r4,2,%r5,%r6
shladd,tsv,ev %r4,2,%r5,%r6
shladd %r4,3,%r5,%r6
shladd,= %r4,3,%r5,%r6
shladd,< %r4,3,%r5,%r6
shladd,<= %r4,3,%r5,%r6
shladd,nuv %r4,3,%r5,%r6
shladd,znv %r4,3,%r5,%r6
shladd,sv %r4,3,%r5,%r6
shladd,od %r4,3,%r5,%r6
shladd,tr %r4,3,%r5,%r6
shladd,<> %r4,3,%r5,%r6
shladd,>= %r4,3,%r5,%r6
shladd,> %r4,3,%r5,%r6
shladd,uv %r4,3,%r5,%r6
shladd,vnz %r4,3,%r5,%r6
shladd,nsv %r4,3,%r5,%r6
shladd,ev %r4,3,%r5,%r6
shladd,l %r4,3,%r5,%r6
shladd,l,= %r4,3,%r5,%r6
shladd,l,< %r4,3,%r5,%r6
shladd,l,<= %r4,3,%r5,%r6
shladd,l,nuv %r4,3,%r5,%r6
shladd,l,znv %r4,3,%r5,%r6
shladd,l,sv %r4,3,%r5,%r6
shladd,l,od %r4,3,%r5,%r6
shladd,l,tr %r4,3,%r5,%r6
shladd,l,<> %r4,3,%r5,%r6
shladd,l,>= %r4,3,%r5,%r6
shladd,l,> %r4,3,%r5,%r6
shladd,l,uv %r4,3,%r5,%r6
shladd,l,vnz %r4,3,%r5,%r6
shladd,l,nsv %r4,3,%r5,%r6
shladd,l,ev %r4,3,%r5,%r6
shladd,tsv %r4,3,%r5,%r6
shladd,tsv,= %r4,3,%r5,%r6
shladd,tsv,< %r4,3,%r5,%r6
shladd,tsv,<= %r4,3,%r5,%r6
shladd,tsv,nuv %r4,3,%r5,%r6
shladd,tsv,znv %r4,3,%r5,%r6
shladd,tsv,sv %r4,3,%r5,%r6
shladd,tsv,od %r4,3,%r5,%r6
shladd,tsv,tr %r4,3,%r5,%r6
shladd,tsv,<> %r4,3,%r5,%r6
shladd,tsv,>= %r4,3,%r5,%r6
shladd,tsv,> %r4,3,%r5,%r6
shladd,tsv,uv %r4,3,%r5,%r6
shladd,tsv,vnz %r4,3,%r5,%r6
shladd,tsv,nsv %r4,3,%r5,%r6
shladd,tsv,ev %r4,3,%r5,%r6
|
tactcomplabs/xbgas-binutils-gdb
| 41,373
|
gas/testsuite/gas/hppa/basic/weird.s
|
.stabs "weird.c",0x64,0,0,Label0
Label0:
.stabs "inttype:t1=bu4;0;32;",0x80,0,0,0
.stabs "sym32: !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type32:t32= !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "attr104:G404=@h !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr105:G405=@i !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "var0:G300=@a8;1",0x20,0,0, 0
.export var0
.data
.align 4
var0:
.long 42
.stabs "sym33:! !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym35:# !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym36:$ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym37:% !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym38:& !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym39:' !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym40:( !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym41:) !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym42:* !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym43:+ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym44:, !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym45:- !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.export attr122
.data
.align 4
attr122:
.long 42
.export attr123
.data
.align 4
attr123:
.long 42
.export attr124
.data
.align 4
attr124:
.long 42
.stabs "sym46:. !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym47:/ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym48:0 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym49:1 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym50:2 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "attr96:G396=@` !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr97:G397=@a !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr98:G398=@b !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr99:G399=@c !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "sym51:3 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym52:4 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym53:5 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym54:6 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym55:7 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym56:8 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym57:9 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym58:: !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym59:; !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym60:< !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym61:= !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym62:> !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym63:? !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym64:@ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym65:A !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym66:B !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym67:C !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym68:D !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym69:E !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym70:F !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym71:G !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym72:H !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym73:I !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym74:J !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym75:K !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym76:L !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym77:M !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym78:N !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym79:O !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym80:P !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym81:Q !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym82:R !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym83:S !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym84:T !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym85:U !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym86:V !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym87:W !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym88:X !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym89:Y !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym90:Z !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym91:[ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym93:] !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym94:^ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym95:_ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym96:` !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym97:a !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym98:b !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym99:c !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym100:d !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym101:e !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym102:f !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym103:g !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym104:h !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym105:i !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym106:j !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym107:k !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym108:l !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym109:m !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym110:n !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym111:o !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym112:p !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym113:q !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym114:r !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym115:s !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym116:t !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym117:u !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym118:v !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym119:w !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym120:x !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym121:y !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym122:z !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym123:{ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym124:| !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym125:} !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "sym126:~ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type33:t33=! !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type35:t35=# !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type36:t36=$ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type37:t37=% !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type38:t38=& !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type39:t39=' !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type40:t40=( !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type41:t41=) !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type42:t42=* !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type43:t43=+ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type44:t44=, !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type45:t45=- !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type46:t46=. !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type47:t47=/ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type48:t48=0 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type49:t49=1 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type50:t50=2 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type51:t51=3 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type52:t52=4 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type53:t53=5 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type54:t54=6 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type55:t55=7 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type56:t56=8 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type57:t57=9 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type58:t58=: !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type59:t59=; !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type60:t60=< !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type61:t61== !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type62:t62=> !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type63:t63=? !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type64:t64=@ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type65:t65=A !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type66:t66=B !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type67:t67=C !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.export attr66
.data
.align 4
attr66:
.long 42
.export attr67
.data
.align 4
attr67:
.long 42
.export attr68
.data
.align 4
attr68:
.long 42
.export attr69
.data
.align 4
attr69:
.long 42
.stabs "type68:t68=D !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type69:t69=E !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type70:t70=F !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type71:t71=G !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type72:t72=H !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type73:t73=I !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type74:t74=J !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type75:t75=K !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type76:t76=L !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type77:t77=M !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type78:t78=N !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type79:t79=O !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type80:t80=P !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type81:t81=Q !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type82:t82=R !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type83:t83=S !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type84:t84=T !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type85:t85=U !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type86:t86=V !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type87:t87=W !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "attr69:G369=@E !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr70:G370=@F !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr71:G371=@G !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "type88:t88=X !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type89:t89=Y !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type90:t90=Z !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type91:t91=[ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type93:t93=] !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type94:t94=^ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type95:t95=_ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type96:t96=` !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type97:t97=a !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type98:t98=b !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type99:t99=c !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type100:t100=d !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type101:t101=e !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type102:t102=f !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type103:t103=g !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type104:t104=h !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type105:t105=i !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type106:t106=j !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type107:t107=k !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type108:t108=l !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type109:t109=m !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type110:t110=n !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type111:t111=o !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type112:t112=p !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type113:t113=q !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type114:t114=r !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type115:t115=s !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type116:t116=t !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type117:t117=u !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type118:t118=v !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type119:t119=w !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type120:t120=x !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type121:t121=y !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type122:t122=z !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type123:t123={ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type124:t124=| !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type125:t125=} !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type126:t126=~ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "attr32:G332=@ !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr33:G333=@! !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr35:G334=@# !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "primary:G200=ered:0,green:1,blue:2,;", 0x20,0,0, 0
.stabs "attr36:G335=@$ !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.export primary
.data
.align 4
primary:
.long 42
.stabs "attr37:G337=@% !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "const69:c=e1,69", 0x80,0,0, 0
.stabs "const70:c=e190=bs2;0;16;,70", 0x80,0,0, 0
.stabs "attr38:G338=@& !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "bad_neg0type:t201=s8field0:1,0,32;field2:-534,32,64;field3:-1,96,32;;", 0x80,0,0, 0
.stabs "bad_neg0:G201", 0x20,0,0, 0
.export bad_neg0
.data
.align 4
bad_neg0:
.long 42
.long 43, 44, 45
.stabs "attr39:G339=@' !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr41:G341=@) !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr42:G342=@* !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr43:G343=@+ !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr44:G344=@, !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr46:G346=@. !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr47:G347=@/ !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr58:G358=@: !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr59:G359=@;@ !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr60:G360=@< !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr61:G361=@= !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr62:G362=@> !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr63:G363=@? !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr64:G364=@@ !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr65:G365=@A !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr66:G366=@B !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr67:G367=@C !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr68:G368=@D !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr72:G372=@H !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr73:G373=@I !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr74:G374=@J !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr75:G375=@K !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr76:G376=@L !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr77:G377=@M !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr78:G378=@N !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr79:G379=@O !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr80:G380=@P !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr81:G381=@Q !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr82:G382=@R !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr83:G383=@S !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr84:G384=@T !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr85:G385=@U !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr86:G386=@V !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr87:G387=@W !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr88:G388=@X !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr89:G389=@Y !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr90:G390=@Z !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr91:G391=@[ !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr93:G393=@] !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.export _common0
.data
.align 4
_common0:
.long 42
.long 24
.long 22
.export common0
.data
.align 4
common0:
.long 42
.long 24
.long 22
.stabs "common0",0xe2,0,0,0
.stabs "common0var0:S1", 0x20,0,0, 0
.stabs "common0var1:S1", 0x20,0,0, 4
.stabs "common0var2:S1", 0x20,0,0, 8
.stabs "common0",0xe4,0,0,0
.stabs "attr94:G394=@^ !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr95:G395=@_ !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr100:G400=@d !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr101:G401=@e !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr102:G402=@f !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr103:G403=@g !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr106:G406=@j !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr107:G407=@k !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr108:G408=@l !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr109:G409=@m !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr110:G410=@n !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr111:G411=@o !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr112:G412=@p !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr113:G413=@q !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr114:G414=@r !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr115:G415=@s !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr116:G416=@t !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr117:G417=@u !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr118:G418=@v !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr119:G419=@w !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr120:G420=@x !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr121:G421=@y !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr122:G422=@z !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr123:G423=@{ !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr124:G424=@| !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr125:G425=@} !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.stabs "attr126:G426=@~ !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
.export attr32
.data
.align 4
attr32:
.long 42
.export attr33
.data
.align 4
attr33:
.long 42
.export attr35
.data
.align 4
attr35:
.long 42
.export attr36
.data
.align 4
attr36:
.long 42
.export attr37
.data
.align 4
attr37:
.long 42
.export attr38
.data
.align 4
attr38:
.long 42
.export attr39
.data
.align 4
attr39:
.long 42
.export attr41
.data
.align 4
attr41:
.long 42
.export attr42
.data
.align 4
attr42:
.long 42
.export attr43
.data
.align 4
attr43:
.long 42
.export attr44
.data
.align 4
attr44:
.long 42
.export attr46
.data
.align 4
attr46:
.long 42
.export attr47
.data
.align 4
attr47:
.long 42
.export attr58
.data
.align 4
attr58:
.long 42
.export attr59
.data
.align 4
attr59:
.long 42
.export attr60
.data
.align 4
attr60:
.long 42
.export attr61
.data
.align 4
attr61:
.long 42
.export attr62
.data
.align 4
attr62:
.long 42
.export attr63
.data
.align 4
attr63:
.long 42
.export attr64
.data
.align 4
attr64:
.long 42
.export attr65
.data
.align 4
attr65:
.long 42
.export attr70
.data
.align 4
attr70:
.long 42
.export attr71
.data
.align 4
attr71:
.long 42
.export attr72
.data
.align 4
attr72:
.long 42
.export attr73
.data
.align 4
attr73:
.long 42
.export attr74
.data
.align 4
attr74:
.long 42
.export attr75
.data
.align 4
attr75:
.long 42
.export attr76
.data
.align 4
attr76:
.long 42
.export attr77
.data
.align 4
attr77:
.long 42
.export attr78
.data
.align 4
attr78:
.long 42
.export attr79
.data
.align 4
attr79:
.long 42
.export attr80
.data
.align 4
attr80:
.long 42
.export attr81
.data
.align 4
attr81:
.long 42
.export attr82
.data
.align 4
attr82:
.long 42
.export attr83
.data
.align 4
attr83:
.long 42
.export attr84
.data
.align 4
attr84:
.long 42
.stabs "float72type:t202=R87;9;", 0x80,0,0, 0
.stabs "int256var:G203=bu32;0;256;", 0x20,0,0, 0
.export int256var
.data
.align 4
int256var:
.long 42
.long 0x2b, 0x2c, 0x2d, 0x2d, 0x2c, 0x2b, 0x2a
.stabs "consth:c=e1,4294967296", 0x80,0,0, 0
.stabs "consth2:c=e1,-734723985732642758928475678987234563284937456", 0x80,0,0, 0
.stabs "bad_neg0const:c=S201,128,128,11222211343434345656565677888877", 0x80,0,0, 0
.stabs "bad_type0:t(-3,7)", 0x80,0,0, 0
.stabs "bad_type1:t(42,6)", 0x80,0,0, 0
.stabs "array_index0:t205=r1;0;5;", 0x80,0,0, 0
.stabs "array0:G206=a205;1", 0x20,0,0, 0
.export array0
.data
.align 4
array0:
.long 42
.long 43, 44, 45, 46, 47
.stabs "array_index1:t207=", 0x80,0,0, 0
.stabs "array1:G208=aeai1_red:0,ai1_green:1,ai1_blue:2,;;1", 0x20,0,0, 0
.export array1
.data
.align 4
array1:
.long 42
.long 43, 44
.stabs "inttype_one:t209=1", 0x80,0,0, 0
.stabs "inttype_two:t210=1", 0x80,0,0, 0
.stabs "one_var:G209", 0x20,0,0, 0
.export one_var
.data
.align 4
one_var:
.long 42
.stabs "two_var:G210", 0x20,0,0, 0
.export two_var
.data
.align 4
two_var:
.long 42
.stabs "intp:t211=*1", 0x80,0,0, 0
.stabs "pointer_to_int_var:G212=*1", 0x80,0,0, 0
.stabs "intp_var:G211", 0x20,0,0, 0
.export intp_var
.data
.align 4
intp_var:
.long 42
.stabs "unrecog_const:c=xjksdflskd33,4;473;", 0x80,0,0, 0
.export attr85
.data
.align 4
attr85:
.long 42
.export attr86
.data
.align 4
attr86:
.long 42
.export attr87
.data
.align 4
attr87:
.long 42
.export attr88
.data
.align 4
attr88:
.long 42
.export attr89
.data
.align 4
attr89:
.long 42
.export attr90
.data
.align 4
attr90:
.long 42
.export attr91
.data
.align 4
attr91:
.long 42
.export attr92
.data
.align 4
attr92:
.long 42
.export attr93
.data
.align 4
attr93:
.long 42
.export attr94
.data
.align 4
attr94:
.long 42
.export attr95
.data
.align 4
attr95:
.long 42
.export attr96
.data
.align 4
attr96:
.long 42
.export attr97
.data
.align 4
attr97:
.long 42
.export attr98
.data
.align 4
attr98:
.long 42
.export attr99
.data
.align 4
attr99:
.long 42
.export attr100
.data
.align 4
attr100:
.long 42
.export attr101
.data
.align 4
attr101:
.long 42
.export attr102
.data
.align 4
attr102:
.long 42
.export attr103
.data
.align 4
attr103:
.long 42
.export attr104
.data
.align 4
attr104:
.long 42
.export attr105
.data
.align 4
attr105:
.long 42
.export attr106
.data
.align 4
attr106:
.long 42
.export attr107
.data
.align 4
attr107:
.long 42
.export attr108
.data
.align 4
attr108:
.long 42
.export attr109
.data
.align 4
attr109:
.long 42
.export attr110
.data
.align 4
attr110:
.long 42
.export attr111
.data
.align 4
attr111:
.long 42
.export attr112
.data
.align 4
attr112:
.long 42
.export attr113
.data
.align 4
attr113:
.long 42
.export attr114
.data
.align 4
attr114:
.long 42
.export attr115
.data
.align 4
attr115:
.long 42
.export attr116
.data
.align 4
attr116:
.long 42
.export attr117
.data
.align 4
attr117:
.long 42
.export attr118
.data
.align 4
attr118:
.long 42
.export attr119
.data
.align 4
attr119:
.long 42
.export attr120
.data
.align 4
attr120:
.long 42
.export attr121
.data
.align 4
attr121:
.long 42
.export attr125
.data
.align 4
attr125:
.long 42
.export attr126
.data
.align 4
attr126:
.long 42
.stabs "var1:G301=@s32;1",0x20,0,0, 0
.export var1
.data
.align 4
var1:
.long 42
.stabs "var2:G302=@p42;1",0x20,0,0, 0
.export var2
.data
.align 4
var2:
.long 42
.stabs "var3:G303=@P;1",0x20,0,0, 0
.export var3
.data
.align 4
var3:
.long 42
.stabs "v_comb:G448=s24!2,020,445=s12!1,120,444=s4x:1,0,32;;;$vb444:446=*444,0;a:/01,32,32;;;0264,447=s12!1,120,444;$vb444:446,0;b:/01,32,32;;;comb:/01,128,32;;", 0x20,0,0, 0
.export v_comb
.align 1
v_comb:
.long v_comb_shared
.long 43
.long v_comb_shared
.long 44
.long 45
v_comb_shared:
.long 42
.stabs "sym92:\\ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "type92:t92=\\ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0
.stabs "attr92:G392=@\\ !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0
|
tactcomplabs/xbgas-binutils-gdb
| 3,215
|
gas/testsuite/gas/hppa/parse/calldatabug.s
|
.code
.align 4
LC$0000:
.STRING "%d %lf %d\x0a\x00"
.align 4
.EXPORT error__3AAAiidi
.EXPORT error__3AAAiidi,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=FR,ARGW4=FU,RTNVAL=GR
error__3AAAiidi:
.PROC
.CALLINFO FRAME=128,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(%r30)
copy %r4,%r1
copy %r30,%r4
stwm %r1,128(%r30)
stw %r9,8(%r4)
stw %r8,12(%r4)
stw %r7,16(%r4)
stw %r6,20(%r4)
stw %r5,24(%r4)
copy %r26,%r5
ldo -8(%r0),%r6
ldo -32(%r4),%r19
add %r19,%r6,%r7
stw %r25,0(%r7)
ldo -12(%r0),%r8
ldo -32(%r4),%r19
add %r19,%r8,%r9
stw %r24,0(%r9)
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldo -24(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
ldo -28(%r0),%r21
ldo -32(%r4),%r22
add %r22,%r21,%r21
ldw 0(%r21),%r22
stw %r22,-52(%r30)
ldil L'LC$0000,%r26
ldo R'LC$0000(%r26),%r26
ldw 0(%r19),%r25
fldds 0(%r20),%fr7
.CALL ARGW0=GR,ARGW1=GR,ARGW2=FR,ARGW3=FU
bl printf,%r2
nop
bl,n L$0002,%r0
bl,n L$0001,%r0
L$0002:
L$0001:
ldw 8(%r4),%r9
ldw 12(%r4),%r8
ldw 16(%r4),%r7
ldw 20(%r4),%r6
ldw 24(%r4),%r5
ldo 8(%r4),%r30
ldw -28(%r30),%r2
bv %r0(%r2)
ldwm -8(%r30),%r4
.EXIT
.PROCEND
.align 4
.EXPORT ok__3AAAidi
.EXPORT ok__3AAAidi,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,ARGW2=FR,ARGW3=FU,RTNVAL=GR
ok__3AAAidi:
.PROC
.CALLINFO FRAME=128,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(%r30)
copy %r4,%r1
copy %r30,%r4
stwm %r1,128(%r30)
stw %r9,8(%r4)
stw %r8,12(%r4)
stw %r7,16(%r4)
stw %r6,20(%r4)
stw %r5,24(%r4)
copy %r26,%r5
ldo -8(%r0),%r6
ldo -32(%r4),%r19
add %r19,%r6,%r7
stw %r25,0(%r7)
ldo -16(%r0),%r8
ldo -32(%r4),%r19
add %r19,%r8,%r9
fstds %fr7,0(%r9)
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldo -16(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
ldo -20(%r0),%r21
ldo -32(%r4),%r22
add %r22,%r21,%r21
ldw 0(%r21),%r22
stw %r22,-52(%r30)
ldil L'LC$0000,%r26
ldo R'LC$0000(%r26),%r26
ldw 0(%r19),%r25
fldds 0(%r20),%fr7
.CALL ARGW0=GR,ARGW1=GR,ARGW2=FR,ARGW3=FU
bl printf,%r2
nop
bl,n L$0004,%r0
bl,n L$0003,%r0
L$0004:
L$0003:
ldw 8(%r4),%r9
ldw 12(%r4),%r8
ldw 16(%r4),%r7
ldw 20(%r4),%r6
ldw 24(%r4),%r5
ldo 8(%r4),%r30
ldw -28(%r30),%r2
bv %r0(%r2)
ldwm -8(%r30),%r4
.EXIT
.PROCEND
.IMPORT __main,CODE
.align 8
LC$0001:
; .double 5.50000000000000000000e+00
.word 1075183616 ; = 0x40160000
.word 0 ; = 0x0
.align 4
.EXPORT main
.EXPORT main,PRIV_LEV=3,RTNVAL=GR
main:
.PROC
.CALLINFO FRAME=128,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(%r30)
copy %r4,%r1
copy %r30,%r4
stwm %r1,128(%r30)
.CALL
bl __main,%r2
nop
ldo -24(%r0),%r19
ldo -32(%r30),%r20
add %r20,%r19,%r19
ldil L'LC$0001,%r20
ldo R'LC$0001(%r20),%r21
ldw 0(%r21),%r22
ldw 4(%r21),%r23
stw %r22,0(%r19)
stw %r23,4(%r19)
ldo 3(%r0),%r19
stw %r19,-60(%r30)
ldo 8(%r4),%r26
ldo 1(%r0),%r25
ldo 4(%r0),%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl error__3AAAiidi,%r2
nop
ldo 3(%r0),%r19
stw %r19,-52(%r30)
ldo 8(%r4),%r26
ldo 1(%r0),%r25
ldil L'LC$0001,%r19
ldo R'LC$0001(%r19),%r20
fldds 0(%r20),%fr7
.CALL ARGW0=GR,ARGW1=GR,ARGW2=FR,ARGW3=FU
bl ok__3AAAidi,%r2
nop
copy %r0,%r28
bl,n L$0005,%r0
bl,n L$0005,%r0
L$0005:
ldo 8(%r4),%r30
ldw -28(%r30),%r2
bv %r0(%r2)
ldwm -8(%r30),%r4
.EXIT
.PROCEND
|
tactcomplabs/xbgas-binutils-gdb
| 110,003
|
gas/testsuite/gas/hppa/parse/fixup7bug.s
|
.IMPORT $global$,DATA
.IMPORT $$dyncall,MILLICODE
.code
.align 4
.EXPORT alloc_type,CODE
.EXPORT alloc_type,ENTRY,PRIV_LEV=3,ARGW0=GR,RTNVAL=GR
alloc_type:
.PROC
.CALLINFO FRAME=192,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(%r30)
copy %r4,%r1
copy %r30,%r4
stwm %r1,192(%r30)
stw %r7,32(%r4)
stw %r6,36(%r4)
stw %r5,40(%r4)
ldo -4(%r0),%r5
ldo -32(%r4),%r19
add %r19,%r5,%r6
stw %r26,0(%r6)
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
comiclr,= 0,%r20,%r0
bl L$0002,%r0
nop
ldo 52(%r0),%r26
.CALL ARGW0=GR
bl xmalloc,%r2
nop
copy %r28,%r7
bl,n L$0003,%r0
L$0002:
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldo 120(%r19),%r20
stw %r20,8(%r4)
ldw 8(%r4),%r19
stw %r19,12(%r4)
ldo 52(%r0),%r19
stw %r19,16(%r4)
ldw 12(%r4),%r19
ldw 12(%r4),%r20
ldw 16(%r19),%r19
ldw 12(%r20),%r20
sub %r19,%r20,%r19
ldw 16(%r4),%r20
comclr,< %r19,%r20,%r0
bl L$0004,%r0
nop
ldw 12(%r4),%r26
ldw 16(%r4),%r25
.CALL ARGW0=GR,ARGW1=GR
bl _obstack_newchunk,%r2
nop
copy %r0,%r19
bl,n L$0005,%r0
L$0004:
copy %r0,%r19
L$0005:
ldw 12(%r4),%r19
ldw 12(%r4),%r20
ldw 12(%r20),%r21
ldw 16(%r4),%r22
add %r21,%r22,%r20
copy %r20,%r21
stw %r21,12(%r19)
ldw 8(%r4),%r19
stw %r19,20(%r4)
ldw 20(%r4),%r19
ldw 8(%r19),%r20
stw %r20,24(%r4)
ldw 20(%r4),%r19
ldw 12(%r19),%r20
ldw 24(%r4),%r19
comclr,= %r20,%r19,%r0
bl L$0006,%r0
nop
ldw 20(%r4),%r19
ldw 40(%r19),%r20
copy %r20,%r21
depi -1,1,1,%r21
stw %r21,40(%r19)
L$0006:
ldw 20(%r4),%r19
ldw 20(%r4),%r20
ldw 20(%r4),%r21
ldw 12(%r20),%r20
ldw 24(%r21),%r21
add %r20,%r21,%r20
ldw 20(%r4),%r21
ldw 24(%r21),%r22
uaddcm %r0,%r22,%r21
and %r20,%r21,%r20
copy %r20,%r21
stw %r21,12(%r19)
ldw 20(%r4),%r19
ldw 20(%r4),%r20
ldw 12(%r19),%r19
ldw 4(%r20),%r20
sub %r19,%r20,%r19
ldw 20(%r4),%r20
ldw 20(%r4),%r21
ldw 16(%r20),%r20
ldw 4(%r21),%r21
sub %r20,%r21,%r20
comclr,> %r19,%r20,%r0
bl L$0007,%r0
nop
ldw 20(%r4),%r19
ldw 20(%r4),%r20
ldw 16(%r20),%r21
stw %r21,12(%r19)
copy %r21,%r19
bl,n L$0008,%r0
L$0007:
copy %r0,%r19
L$0008:
ldw 20(%r4),%r19
ldw 20(%r4),%r20
ldw 12(%r20),%r21
stw %r21,8(%r19)
ldw 24(%r4),%r7
L$0003:
copy %r7,%r26
copy %r0,%r25
ldo 52(%r0),%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl memset,%r2
nop
stw %r0,0(%r7)
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
stw %r20,12(%r7)
ldo -1(%r0),%r19
stw %r19,44(%r7)
copy %r7,%r28
bl,n L$0001,%r0
L$0001:
ldw 32(%r4),%r7
ldw 36(%r4),%r6
ldw 40(%r4),%r5
ldo 8(%r4),%r30
ldw -28(%r30),%r2
bv %r0(%r2)
ldwm -8(%r30),%r4
.EXIT
.PROCEND
.align 4
.EXPORT make_pointer_type,CODE
.EXPORT make_pointer_type,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,RTNVAL=GR
make_pointer_type:
.PROC
.CALLINFO FRAME=192,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(%r30)
copy %r4,%r1
copy %r30,%r4
stwm %r1,192(%r30)
stw %r9,16(%r4)
stw %r8,20(%r4)
stw %r7,24(%r4)
stw %r6,28(%r4)
stw %r5,32(%r4)
ldo -4(%r0),%r5
ldo -32(%r4),%r19
add %r19,%r5,%r6
stw %r26,0(%r6)
ldo -8(%r0),%r7
ldo -32(%r4),%r19
add %r19,%r7,%r8
stw %r25,0(%r8)
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 20(%r19),%r9
comiclr,<> 0,%r9,%r0
bl L$0010,%r0
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
comiclr,= 0,%r20,%r0
bl L$0011,%r0
nop
copy %r9,%r28
bl,n L$0009,%r0
bl,n L$0012,%r0
L$0011:
ldo -8(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 0(%r19),%r20
comiclr,= 0,%r20,%r0
bl L$0013,%r0
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
stw %r9,0(%r19)
copy %r9,%r28
bl,n L$0009,%r0
L$0013:
L$0012:
L$0010:
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
comiclr,<> 0,%r20,%r0
bl L$0015,%r0
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 0(%r19),%r20
comiclr,= 0,%r20,%r0
bl L$0014,%r0
nop
bl,n L$0015,%r0
L$0015:
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 12(%r19),%r26
.CALL ARGW0=GR
bl alloc_type,%r2
nop
copy %r28,%r9
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
comiclr,<> 0,%r20,%r0
bl L$0016,%r0
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
stw %r9,0(%r19)
L$0016:
bl,n L$0017,%r0
L$0014:
ldo -8(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 0(%r19),%r9
ldw 12(%r9),%r19
stw %r19,8(%r4)
copy %r9,%r26
copy %r0,%r25
ldo 52(%r0),%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl memset,%r2
nop
ldw 8(%r4),%r19
stw %r19,12(%r9)
L$0017:
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
stw %r20,16(%r9)
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
stw %r9,20(%r19)
ldo 4(%r0),%r19
stw %r19,8(%r9)
ldo 1(%r0),%r19
stw %r19,0(%r9)
ldh 32(%r9),%r19
copy %r19,%r20
depi -1,31,1,%r20
sth %r20,32(%r9)
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 20(%r19),%r20
comiclr,= 0,%r20,%r0
bl L$0018,%r0
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
stw %r9,20(%r19)
L$0018:
copy %r9,%r28
bl,n L$0009,%r0
L$0009:
ldw 16(%r4),%r9
ldw 20(%r4),%r8
ldw 24(%r4),%r7
ldw 28(%r4),%r6
ldw 32(%r4),%r5
ldo 8(%r4),%r30
ldw -28(%r30),%r2
bv %r0(%r2)
ldwm -8(%r30),%r4
.EXIT
.PROCEND
.align 4
.EXPORT lookup_pointer_type,CODE
.EXPORT lookup_pointer_type,ENTRY,PRIV_LEV=3,ARGW0=GR,RTNVAL=GR
lookup_pointer_type:
.PROC
.CALLINFO FRAME=128,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(%r30)
copy %r4,%r1
copy %r30,%r4
stwm %r1,128(%r30)
stw %r6,8(%r4)
stw %r5,12(%r4)
ldo -4(%r0),%r5
ldo -32(%r4),%r19
add %r19,%r5,%r6
stw %r26,0(%r6)
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r26
copy %r0,%r25
.CALL ARGW0=GR,ARGW1=GR
bl make_pointer_type,%r2
nop
bl,n L$0019,%r0
L$0019:
ldw 8(%r4),%r6
ldw 12(%r4),%r5
ldo 8(%r4),%r30
ldw -28(%r30),%r2
bv %r0(%r2)
ldwm -8(%r30),%r4
.EXIT
.PROCEND
.align 4
.EXPORT make_reference_type,CODE
.EXPORT make_reference_type,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,RTNVAL=GR
make_reference_type:
.PROC
.CALLINFO FRAME=192,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(%r30)
copy %r4,%r1
copy %r30,%r4
stwm %r1,192(%r30)
stw %r9,16(%r4)
stw %r8,20(%r4)
stw %r7,24(%r4)
stw %r6,28(%r4)
stw %r5,32(%r4)
ldo -4(%r0),%r5
ldo -32(%r4),%r19
add %r19,%r5,%r6
stw %r26,0(%r6)
ldo -8(%r0),%r7
ldo -32(%r4),%r19
add %r19,%r7,%r8
stw %r25,0(%r8)
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 24(%r19),%r9
comiclr,<> 0,%r9,%r0
bl L$0021,%r0
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
comiclr,= 0,%r20,%r0
bl L$0022,%r0
nop
copy %r9,%r28
bl,n L$0020,%r0
bl,n L$0023,%r0
L$0022:
ldo -8(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 0(%r19),%r20
comiclr,= 0,%r20,%r0
bl L$0024,%r0
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
stw %r9,0(%r19)
copy %r9,%r28
bl,n L$0020,%r0
L$0024:
L$0023:
L$0021:
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
comiclr,<> 0,%r20,%r0
bl L$0026,%r0
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 0(%r19),%r20
comiclr,= 0,%r20,%r0
bl L$0025,%r0
nop
bl,n L$0026,%r0
L$0026:
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 12(%r19),%r26
.CALL ARGW0=GR
bl alloc_type,%r2
nop
copy %r28,%r9
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
comiclr,<> 0,%r20,%r0
bl L$0027,%r0
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
stw %r9,0(%r19)
L$0027:
bl,n L$0028,%r0
L$0025:
ldo -8(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 0(%r19),%r9
ldw 12(%r9),%r19
stw %r19,8(%r4)
copy %r9,%r26
copy %r0,%r25
ldo 52(%r0),%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl memset,%r2
nop
ldw 8(%r4),%r19
stw %r19,12(%r9)
L$0028:
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
stw %r20,16(%r9)
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
stw %r9,24(%r19)
ldo 4(%r0),%r19
stw %r19,8(%r9)
ldo 16(%r0),%r19
stw %r19,0(%r9)
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 24(%r19),%r20
comiclr,= 0,%r20,%r0
bl L$0029,%r0
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
stw %r9,24(%r19)
L$0029:
copy %r9,%r28
bl,n L$0020,%r0
L$0020:
ldw 16(%r4),%r9
ldw 20(%r4),%r8
ldw 24(%r4),%r7
ldw 28(%r4),%r6
ldw 32(%r4),%r5
ldo 8(%r4),%r30
ldw -28(%r30),%r2
bv %r0(%r2)
ldwm -8(%r30),%r4
.EXIT
.PROCEND
.align 4
.EXPORT lookup_reference_type,CODE
.EXPORT lookup_reference_type,ENTRY,PRIV_LEV=3,ARGW0=GR,RTNVAL=GR
lookup_reference_type:
.PROC
.CALLINFO FRAME=128,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(%r30)
copy %r4,%r1
copy %r30,%r4
stwm %r1,128(%r30)
stw %r6,8(%r4)
stw %r5,12(%r4)
ldo -4(%r0),%r5
ldo -32(%r4),%r19
add %r19,%r5,%r6
stw %r26,0(%r6)
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r26
copy %r0,%r25
.CALL ARGW0=GR,ARGW1=GR
bl make_reference_type,%r2
nop
bl,n L$0030,%r0
L$0030:
ldw 8(%r4),%r6
ldw 12(%r4),%r5
ldo 8(%r4),%r30
ldw -28(%r30),%r2
bv %r0(%r2)
ldwm -8(%r30),%r4
.EXIT
.PROCEND
.align 4
.EXPORT make_function_type,CODE
.EXPORT make_function_type,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,RTNVAL=GR
make_function_type:
.PROC
.CALLINFO FRAME=192,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(%r30)
copy %r4,%r1
copy %r30,%r4
stwm %r1,192(%r30)
stw %r9,16(%r4)
stw %r8,20(%r4)
stw %r7,24(%r4)
stw %r6,28(%r4)
stw %r5,32(%r4)
ldo -4(%r0),%r5
ldo -32(%r4),%r19
add %r19,%r5,%r6
stw %r26,0(%r6)
ldo -8(%r0),%r7
ldo -32(%r4),%r19
add %r19,%r7,%r8
stw %r25,0(%r8)
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 28(%r19),%r9
comiclr,<> 0,%r9,%r0
bl L$0032,%r0
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
comiclr,= 0,%r20,%r0
bl L$0033,%r0
nop
copy %r9,%r28
bl,n L$0031,%r0
bl,n L$0034,%r0
L$0033:
ldo -8(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 0(%r19),%r20
comiclr,= 0,%r20,%r0
bl L$0035,%r0
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
stw %r9,0(%r19)
copy %r9,%r28
bl,n L$0031,%r0
L$0035:
L$0034:
L$0032:
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
comiclr,<> 0,%r20,%r0
bl L$0037,%r0
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 0(%r19),%r20
comiclr,= 0,%r20,%r0
bl L$0036,%r0
nop
bl,n L$0037,%r0
L$0037:
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 12(%r19),%r26
.CALL ARGW0=GR
bl alloc_type,%r2
nop
copy %r28,%r9
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
comiclr,<> 0,%r20,%r0
bl L$0038,%r0
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
stw %r9,0(%r19)
L$0038:
bl,n L$0039,%r0
L$0036:
ldo -8(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 0(%r19),%r9
ldw 12(%r9),%r19
stw %r19,8(%r4)
copy %r9,%r26
copy %r0,%r25
ldo 52(%r0),%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl memset,%r2
nop
ldw 8(%r4),%r19
stw %r19,12(%r9)
L$0039:
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
stw %r20,16(%r9)
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
stw %r9,28(%r19)
ldo 1(%r0),%r19
stw %r19,8(%r9)
ldo 6(%r0),%r19
stw %r19,0(%r9)
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 28(%r19),%r20
comiclr,= 0,%r20,%r0
bl L$0040,%r0
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
stw %r9,28(%r19)
L$0040:
copy %r9,%r28
bl,n L$0031,%r0
L$0031:
ldw 16(%r4),%r9
ldw 20(%r4),%r8
ldw 24(%r4),%r7
ldw 28(%r4),%r6
ldw 32(%r4),%r5
ldo 8(%r4),%r30
ldw -28(%r30),%r2
bv %r0(%r2)
ldwm -8(%r30),%r4
.EXIT
.PROCEND
.align 4
.EXPORT lookup_function_type,CODE
.EXPORT lookup_function_type,ENTRY,PRIV_LEV=3,ARGW0=GR,RTNVAL=GR
lookup_function_type:
.PROC
.CALLINFO FRAME=128,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(%r30)
copy %r4,%r1
copy %r30,%r4
stwm %r1,128(%r30)
stw %r6,8(%r4)
stw %r5,12(%r4)
ldo -4(%r0),%r5
ldo -32(%r4),%r19
add %r19,%r5,%r6
stw %r26,0(%r6)
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r26
copy %r0,%r25
.CALL ARGW0=GR,ARGW1=GR
bl make_function_type,%r2
nop
bl,n L$0041,%r0
L$0041:
ldw 8(%r4),%r6
ldw 12(%r4),%r5
ldo 8(%r4),%r30
ldw -28(%r30),%r2
bv %r0(%r2)
ldwm -8(%r30),%r4
.EXIT
.PROCEND
.IMPORT smash_to_member_type,CODE
.align 4
.EXPORT lookup_member_type,CODE
.EXPORT lookup_member_type,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,RTNVAL=GR
lookup_member_type:
.PROC
.CALLINFO FRAME=128,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(%r30)
copy %r4,%r1
copy %r30,%r4
stwm %r1,128(%r30)
stw %r8,8(%r4)
stw %r7,12(%r4)
stw %r6,16(%r4)
stw %r5,20(%r4)
ldo 24(%r4),%r1
fstds,ma %fr12,8(%r1)
ldo -4(%r0),%r5
ldo -32(%r4),%r19
add %r19,%r5,%r6
stw %r26,0(%r6)
ldo -8(%r0),%r7
ldo -32(%r4),%r19
add %r19,%r7,%r8
stw %r25,0(%r8)
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 12(%r19),%r26
.CALL ARGW0=GR
bl alloc_type,%r2
nop
stw %r28,-16(%r30)
fldws -16(%r30),%fr12
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
fstws %fr12,-16(%r30)
ldw -16(%r30),%r26
ldw 0(%r19),%r25
ldw 0(%r20),%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl smash_to_member_type,%r2
nop
fstws %fr12,-16(%r30)
ldw -16(%r30),%r28
bl,n L$0042,%r0
L$0042:
ldw 8(%r4),%r8
ldw 12(%r4),%r7
ldw 16(%r4),%r6
ldw 20(%r4),%r5
ldo 24(%r4),%r1
fldds,ma 8(%r1),%fr12
ldo 8(%r4),%r30
ldw -28(%r30),%r2
bv %r0(%r2)
ldwm -8(%r30),%r4
.EXIT
.PROCEND
.align 4
.EXPORT allocate_stub_method,CODE
.EXPORT allocate_stub_method,ENTRY,PRIV_LEV=3,ARGW0=GR,RTNVAL=GR
allocate_stub_method:
.PROC
.CALLINFO FRAME=128,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(%r30)
copy %r4,%r1
copy %r30,%r4
stwm %r1,128(%r30)
stw %r6,16(%r4)
stw %r5,20(%r4)
ldo -4(%r0),%r5
ldo -32(%r4),%r19
add %r19,%r5,%r6
stw %r26,0(%r6)
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 12(%r19),%r26
.CALL ARGW0=GR
bl alloc_type,%r2
nop
stw %r28,8(%r4)
ldw 8(%r4),%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
ldw 0(%r20),%r21
stw %r21,16(%r19)
ldw 8(%r4),%r19
ldo 4(%r0),%r20
sth %r20,32(%r19)
ldw 8(%r4),%r19
ldo 15(%r0),%r20
stw %r20,0(%r19)
ldw 8(%r4),%r19
ldo 1(%r0),%r20
stw %r20,8(%r19)
ldw 8(%r4),%r28
bl,n L$0043,%r0
L$0043:
ldw 16(%r4),%r6
ldw 20(%r4),%r5
ldo 8(%r4),%r30
ldw -28(%r30),%r2
bv %r0(%r2)
ldwm -8(%r30),%r4
.EXIT
.PROCEND
.IMPORT builtin_type_int,DATA
.align 4
.EXPORT create_array_type,CODE
.EXPORT create_array_type,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,RTNVAL=GR
create_array_type:
.PROC
.CALLINFO FRAME=192,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(%r30)
copy %r4,%r1
copy %r30,%r4
stwm %r1,192(%r30)
stw %r10,56(%r4)
stw %r9,60(%r4)
stw %r8,64(%r4)
stw %r7,68(%r4)
stw %r6,72(%r4)
stw %r5,76(%r4)
ldo -4(%r0),%r5
ldo -32(%r4),%r19
add %r19,%r5,%r6
stw %r26,0(%r6)
ldo -8(%r0),%r7
ldo -32(%r4),%r19
add %r19,%r7,%r8
stw %r25,0(%r8)
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 12(%r19),%r26
.CALL ARGW0=GR
bl alloc_type,%r2
nop
stw %r28,8(%r4)
ldw 8(%r4),%r19
ldo 2(%r0),%r20
stw %r20,0(%r19)
ldw 8(%r4),%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
ldw 0(%r20),%r21
stw %r21,16(%r19)
ldw 8(%r4),%r19
ldo -8(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
ldo -4(%r0),%r21
ldo -32(%r4),%r23
add %r23,%r21,%r22
ldw 0(%r22),%r21
ldw 0(%r20),%r20
ldw 8(%r21),%r21
stw %r20,-16(%r30)
fldws -16(%r30),%fr5
stw %r21,-16(%r30)
fldws -16(%r30),%fr5R
xmpyu %fr5,%fr5R,%fr4
fstws %fr4R,-16(%r30)
ldw -16(%r30),%r24
stw %r24,8(%r19)
ldw 8(%r4),%r19
ldo 1(%r0),%r20
sth %r20,34(%r19)
ldw 8(%r4),%r9
ldw 8(%r4),%r19
ldw 12(%r19),%r20
comiclr,<> 0,%r20,%r0
bl L$0050,%r0
nop
ldw 8(%r4),%r19
ldw 12(%r19),%r20
ldo 120(%r20),%r19
stw %r19,16(%r4)
ldw 16(%r4),%r19
stw %r19,20(%r4)
ldo 16(%r0),%r19
stw %r19,24(%r4)
ldw 20(%r4),%r19
ldw 20(%r4),%r20
ldw 16(%r19),%r19
ldw 12(%r20),%r20
sub %r19,%r20,%r19
ldw 24(%r4),%r20
comclr,< %r19,%r20,%r0
bl L$0045,%r0
nop
ldw 20(%r4),%r26
ldw 24(%r4),%r25
.CALL ARGW0=GR,ARGW1=GR
bl _obstack_newchunk,%r2
nop
copy %r0,%r19
bl,n L$0046,%r0
L$0045:
copy %r0,%r19
L$0046:
ldw 20(%r4),%r19
ldw 20(%r4),%r20
ldw 12(%r20),%r21
ldw 24(%r4),%r22
add %r21,%r22,%r20
copy %r20,%r21
stw %r21,12(%r19)
ldw 16(%r4),%r19
stw %r19,28(%r4)
ldw 28(%r4),%r19
ldw 8(%r19),%r20
stw %r20,32(%r4)
ldw 28(%r4),%r19
ldw 12(%r19),%r20
ldw 32(%r4),%r19
comclr,= %r20,%r19,%r0
bl L$0047,%r0
nop
ldw 28(%r4),%r19
ldw 40(%r19),%r20
copy %r20,%r21
depi -1,1,1,%r21
stw %r21,40(%r19)
L$0047:
ldw 28(%r4),%r19
ldw 28(%r4),%r20
ldw 28(%r4),%r21
ldw 12(%r20),%r20
ldw 24(%r21),%r21
add %r20,%r21,%r20
ldw 28(%r4),%r21
ldw 24(%r21),%r22
uaddcm %r0,%r22,%r21
and %r20,%r21,%r20
copy %r20,%r21
stw %r21,12(%r19)
ldw 28(%r4),%r19
ldw 28(%r4),%r20
ldw 12(%r19),%r19
ldw 4(%r20),%r20
sub %r19,%r20,%r19
ldw 28(%r4),%r20
ldw 28(%r4),%r21
ldw 16(%r20),%r20
ldw 4(%r21),%r21
sub %r20,%r21,%r20
comclr,> %r19,%r20,%r0
bl L$0048,%r0
nop
ldw 28(%r4),%r19
ldw 28(%r4),%r20
ldw 16(%r20),%r21
stw %r21,12(%r19)
copy %r21,%r19
bl,n L$0049,%r0
L$0048:
copy %r0,%r19
L$0049:
ldw 28(%r4),%r19
ldw 28(%r4),%r20
ldw 12(%r20),%r21
stw %r21,8(%r19)
ldw 32(%r4),%r10
bl,n L$0051,%r0
L$0050:
ldo 16(%r0),%r26
.CALL ARGW0=GR
bl xmalloc,%r2
nop
copy %r28,%r10
L$0051:
stw %r10,36(%r9)
ldw 8(%r4),%r19
ldw 12(%r19),%r26
.CALL ARGW0=GR
bl alloc_type,%r2
nop
stw %r28,12(%r4)
ldw 12(%r4),%r19
ldo 11(%r0),%r20
stw %r20,0(%r19)
ldw 12(%r4),%r19
addil L'builtin_type_int-$global$,%r27
ldw R'builtin_type_int-$global$(%r1),%r20
stw %r20,16(%r19)
ldw 12(%r4),%r19
ldo 4(%r0),%r20
stw %r20,8(%r19)
ldw 12(%r4),%r19
ldo 2(%r0),%r20
sth %r20,34(%r19)
ldw 12(%r4),%r9
ldw 12(%r4),%r19
ldw 12(%r19),%r20
comiclr,<> 0,%r20,%r0
bl L$0057,%r0
nop
ldw 12(%r4),%r19
ldw 12(%r19),%r20
ldo 120(%r20),%r19
stw %r19,36(%r4)
ldw 36(%r4),%r19
stw %r19,40(%r4)
ldo 32(%r0),%r19
stw %r19,44(%r4)
ldw 40(%r4),%r19
ldw 40(%r4),%r20
ldw 16(%r19),%r19
ldw 12(%r20),%r20
sub %r19,%r20,%r19
ldw 44(%r4),%r20
comclr,< %r19,%r20,%r0
bl L$0052,%r0
nop
ldw 40(%r4),%r26
ldw 44(%r4),%r25
.CALL ARGW0=GR,ARGW1=GR
bl _obstack_newchunk,%r2
nop
copy %r0,%r19
bl,n L$0053,%r0
L$0052:
copy %r0,%r19
L$0053:
ldw 40(%r4),%r19
ldw 40(%r4),%r20
ldw 12(%r20),%r21
ldw 44(%r4),%r22
add %r21,%r22,%r20
copy %r20,%r21
stw %r21,12(%r19)
ldw 36(%r4),%r19
stw %r19,48(%r4)
ldw 48(%r4),%r19
ldw 8(%r19),%r20
stw %r20,52(%r4)
ldw 48(%r4),%r19
ldw 12(%r19),%r20
ldw 52(%r4),%r19
comclr,= %r20,%r19,%r0
bl L$0054,%r0
nop
ldw 48(%r4),%r19
ldw 40(%r19),%r20
copy %r20,%r21
depi -1,1,1,%r21
stw %r21,40(%r19)
L$0054:
ldw 48(%r4),%r19
ldw 48(%r4),%r20
ldw 48(%r4),%r21
ldw 12(%r20),%r20
ldw 24(%r21),%r21
add %r20,%r21,%r20
ldw 48(%r4),%r21
ldw 24(%r21),%r22
uaddcm %r0,%r22,%r21
and %r20,%r21,%r20
copy %r20,%r21
stw %r21,12(%r19)
ldw 48(%r4),%r19
ldw 48(%r4),%r20
ldw 12(%r19),%r19
ldw 4(%r20),%r20
sub %r19,%r20,%r19
ldw 48(%r4),%r20
ldw 48(%r4),%r21
ldw 16(%r20),%r20
ldw 4(%r21),%r21
sub %r20,%r21,%r20
comclr,> %r19,%r20,%r0
bl L$0055,%r0
nop
ldw 48(%r4),%r19
ldw 48(%r4),%r20
ldw 16(%r20),%r21
stw %r21,12(%r19)
copy %r21,%r19
bl,n L$0056,%r0
L$0055:
copy %r0,%r19
L$0056:
ldw 48(%r4),%r19
ldw 48(%r4),%r20
ldw 12(%r20),%r21
stw %r21,8(%r19)
ldw 52(%r4),%r10
bl,n L$0058,%r0
L$0057:
ldo 32(%r0),%r26
.CALL ARGW0=GR
bl xmalloc,%r2
nop
copy %r28,%r10
L$0058:
stw %r10,36(%r9)
ldw 12(%r4),%r19
ldw 36(%r19),%r20
stw %r0,0(%r20)
ldw 12(%r4),%r19
ldo 16(%r0),%r20
ldw 36(%r19),%r21
add %r20,%r21,%r19
ldo -8(%r0),%r20
ldo -32(%r4),%r22
add %r22,%r20,%r21
ldw 0(%r21),%r20
ldo -1(%r20),%r21
stw %r21,0(%r19)
ldw 12(%r4),%r20
ldw 36(%r20),%r19
addil L'builtin_type_int-$global$,%r27
ldw R'builtin_type_int-$global$(%r1),%r20
stw %r20,8(%r19)
ldw 12(%r4),%r19
ldo 16(%r0),%r20
ldw 36(%r19),%r21
add %r20,%r21,%r19
addil L'builtin_type_int-$global$,%r27
ldw R'builtin_type_int-$global$(%r1),%r20
stw %r20,8(%r19)
ldw 8(%r4),%r19
ldw 36(%r19),%r20
ldw 12(%r4),%r19
stw %r19,8(%r20)
ldw 8(%r4),%r19
ldo -1(%r0),%r20
stw %r20,44(%r19)
ldw 8(%r4),%r28
bl,n L$0044,%r0
L$0044:
ldw 56(%r4),%r10
ldw 60(%r4),%r9
ldw 64(%r4),%r8
ldw 68(%r4),%r7
ldw 72(%r4),%r6
ldw 76(%r4),%r5
ldo 8(%r4),%r30
ldw -28(%r30),%r2
bv %r0(%r2)
ldwm -8(%r30),%r4
.EXIT
.PROCEND
.align 4
.EXPORT smash_to_member_type,CODE
.EXPORT smash_to_member_type,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,ARGW2=GR
smash_to_member_type:
.PROC
.CALLINFO FRAME=192,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(%r30)
copy %r4,%r1
copy %r30,%r4
stwm %r1,192(%r30)
stw %r10,16(%r4)
stw %r9,20(%r4)
stw %r8,24(%r4)
stw %r7,28(%r4)
stw %r6,32(%r4)
stw %r5,36(%r4)
ldo -4(%r0),%r5
ldo -32(%r4),%r19
add %r19,%r5,%r6
stw %r26,0(%r6)
ldo -8(%r0),%r7
ldo -32(%r4),%r19
add %r19,%r7,%r8
stw %r25,0(%r8)
ldo -12(%r0),%r9
ldo -32(%r4),%r19
add %r19,%r9,%r10
stw %r24,0(%r10)
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 12(%r19),%r20
stw %r20,8(%r4)
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r26
copy %r0,%r25
ldo 52(%r0),%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl memset,%r2
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 8(%r4),%r20
stw %r20,12(%r19)
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldo -12(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
ldw 0(%r20),%r21
stw %r21,16(%r19)
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldo -8(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
ldw 0(%r20),%r21
stw %r21,40(%r19)
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldo 1(%r0),%r20
stw %r20,8(%r19)
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldo 14(%r0),%r20
stw %r20,0(%r19)
L$0059:
ldw 16(%r4),%r10
ldw 20(%r4),%r9
ldw 24(%r4),%r8
ldw 28(%r4),%r7
ldw 32(%r4),%r6
ldw 36(%r4),%r5
ldo 8(%r4),%r30
ldw -28(%r30),%r2
bv %r0(%r2)
ldwm -8(%r30),%r4
.EXIT
.PROCEND
.align 4
.EXPORT smash_to_method_type,CODE
.EXPORT smash_to_method_type,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
smash_to_method_type:
.PROC
.CALLINFO FRAME=192,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(%r30)
copy %r4,%r1
copy %r30,%r4
stwm %r1,192(%r30)
stw %r12,16(%r4)
stw %r11,20(%r4)
stw %r10,24(%r4)
stw %r9,28(%r4)
stw %r8,32(%r4)
stw %r7,36(%r4)
stw %r6,40(%r4)
stw %r5,44(%r4)
ldo -4(%r0),%r5
ldo -32(%r4),%r19
add %r19,%r5,%r6
stw %r26,0(%r6)
ldo -8(%r0),%r7
ldo -32(%r4),%r19
add %r19,%r7,%r8
stw %r25,0(%r8)
ldo -12(%r0),%r9
ldo -32(%r4),%r19
add %r19,%r9,%r10
stw %r24,0(%r10)
ldo -16(%r0),%r11
ldo -32(%r4),%r19
add %r19,%r11,%r12
stw %r23,0(%r12)
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 12(%r19),%r20
stw %r20,8(%r4)
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r26
copy %r0,%r25
ldo 52(%r0),%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl memset,%r2
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 8(%r4),%r20
stw %r20,12(%r19)
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldo -12(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
ldw 0(%r20),%r21
stw %r21,16(%r19)
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldo -8(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
ldw 0(%r20),%r21
stw %r21,40(%r19)
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldo -16(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
ldw 0(%r20),%r21
stw %r21,48(%r19)
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldo 1(%r0),%r20
stw %r20,8(%r19)
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldo 15(%r0),%r20
stw %r20,0(%r19)
L$0060:
ldw 16(%r4),%r12
ldw 20(%r4),%r11
ldw 24(%r4),%r10
ldw 28(%r4),%r9
ldw 32(%r4),%r8
ldw 36(%r4),%r7
ldw 40(%r4),%r6
ldw 44(%r4),%r5
ldo 8(%r4),%r30
ldw -28(%r30),%r2
bv %r0(%r2)
ldwm -8(%r30),%r4
.EXIT
.PROCEND
.IMPORT strncmp,CODE
.align 4
LC$0000:
.STRING "struct \x00"
.align 4
LC$0001:
.STRING "union \x00"
.align 4
LC$0002:
.STRING "enum \x00"
.align 4
.EXPORT type_name_no_tag,CODE
.EXPORT type_name_no_tag,ENTRY,PRIV_LEV=3,ARGW0=GR,RTNVAL=GR
type_name_no_tag:
.PROC
.CALLINFO FRAME=128,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(%r30)
copy %r4,%r1
copy %r30,%r4
stwm %r1,128(%r30)
stw %r6,8(%r4)
stw %r5,12(%r4)
copy %r26,%r5
ldw 4(%r5),%r6
comiclr,<> 0,%r6,%r0
bl L$0062,%r0
nop
ldw 0(%r5),%r19
comiclr,<> 4,%r19,%r0
bl L$0066,%r0
nop
comiclr,>= 4,%r19,%r0
bl L$0072,%r0
nop
comiclr,<> 3,%r19,%r0
bl L$0064,%r0
nop
bl,n L$0070,%r0
L$0072:
comiclr,<> 5,%r19,%r0
bl L$0068,%r0
nop
bl,n L$0070,%r0
L$0064:
copy %r6,%r26
ldil L'LC$0000,%r25
ldo R'LC$0000(%r25),%r25
ldo 7(%r0),%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl strncmp,%r2
nop
copy %r28,%r19
comiclr,= 0,%r19,%r0
bl L$0065,%r0
nop
ldo 7(%r6),%r6
L$0065:
bl,n L$0063,%r0
L$0066:
copy %r6,%r26
ldil L'LC$0001,%r25
ldo R'LC$0001(%r25),%r25
ldo 6(%r0),%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl strncmp,%r2
nop
copy %r28,%r19
comiclr,= 0,%r19,%r0
bl L$0067,%r0
nop
ldo 6(%r6),%r6
L$0067:
bl,n L$0063,%r0
L$0068:
copy %r6,%r26
ldil L'LC$0002,%r25
ldo R'LC$0002(%r25),%r25
ldo 5(%r0),%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl strncmp,%r2
nop
copy %r28,%r19
comiclr,= 0,%r19,%r0
bl L$0069,%r0
nop
ldo 5(%r6),%r6
L$0069:
bl,n L$0063,%r0
L$0070:
bl,n L$0063,%r0
L$0063:
L$0062:
copy %r6,%r28
bl,n L$0061,%r0
L$0061:
ldw 8(%r4),%r6
ldw 12(%r4),%r5
ldo 8(%r4),%r30
ldw -28(%r30),%r2
bv %r0(%r2)
ldwm -8(%r30),%r4
.EXIT
.PROCEND
.IMPORT current_language,DATA
.IMPORT strcmp,CODE
.align 4
.EXPORT lookup_primitive_typename,CODE
.EXPORT lookup_primitive_typename,ENTRY,PRIV_LEV=3,ARGW0=GR,RTNVAL=GR
lookup_primitive_typename:
.PROC
.CALLINFO FRAME=128,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(%r30)
copy %r4,%r1
copy %r30,%r4
stwm %r1,128(%r30)
stw %r6,16(%r4)
stw %r5,20(%r4)
ldo -4(%r0),%r5
ldo -32(%r4),%r19
add %r19,%r5,%r6
stw %r26,0(%r6)
addil L'current_language-$global$,%r27
ldw R'current_language-$global$(%r1),%r19
ldw 8(%r19),%r20
stw %r20,8(%r4)
L$0074:
ldw 8(%r4),%r19
ldw 0(%r19),%r20
comiclr,<> 0,%r20,%r0
bl L$0075,%r0
nop
ldw 8(%r4),%r19
ldw 0(%r19),%r20
ldw 0(%r20),%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
ldw 4(%r19),%r26
ldw 0(%r20),%r25
.CALL ARGW0=GR,ARGW1=GR
bl strcmp,%r2
nop
copy %r28,%r19
comiclr,= 0,%r19,%r0
bl L$0077,%r0
nop
ldw 8(%r4),%r19
ldw 0(%r19),%r20
ldw 0(%r20),%r28
bl,n L$0073,%r0
L$0077:
L$0076:
ldw 8(%r4),%r19
ldo 4(%r19),%r20
stw %r20,8(%r4)
bl,n L$0074,%r0
L$0075:
copy %r0,%r28
bl,n L$0073,%r0
L$0073:
ldw 16(%r4),%r6
ldw 20(%r4),%r5
ldo 8(%r4),%r30
ldw -28(%r30),%r2
bv %r0(%r2)
ldwm -8(%r30),%r4
.EXIT
.PROCEND
.IMPORT lookup_symbol,CODE
.IMPORT error,CODE
.align 4
LC$0003:
.STRING "No type named %s.\x00"
.align 4
.EXPORT lookup_typename,CODE
.EXPORT lookup_typename,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,ARGW2=GR,RTNVAL=GR
lookup_typename:
.PROC
.CALLINFO FRAME=192,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(%r30)
copy %r4,%r1
copy %r30,%r4
stwm %r1,192(%r30)
stw %r12,8(%r4)
stw %r11,12(%r4)
stw %r10,16(%r4)
stw %r9,20(%r4)
stw %r8,24(%r4)
stw %r7,28(%r4)
stw %r6,32(%r4)
stw %r5,36(%r4)
ldo -4(%r0),%r5
ldo -32(%r4),%r19
add %r19,%r5,%r6
stw %r26,0(%r6)
ldo -8(%r0),%r7
ldo -32(%r4),%r19
add %r19,%r7,%r8
stw %r25,0(%r8)
ldo -12(%r0),%r9
ldo -32(%r4),%r19
add %r19,%r9,%r10
stw %r24,0(%r10)
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldo -8(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
stw %r0,-52(%r30)
ldw 0(%r19),%r26
ldw 0(%r20),%r25
ldo 1(%r0),%r24
copy %r0,%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl lookup_symbol,%r2
nop
copy %r28,%r11
comiclr,<> 0,%r11,%r0
bl L$0080,%r0
nop
ldw 8(%r11),%r19
comiclr,= 8,%r19,%r0
bl L$0080,%r0
nop
bl,n L$0079,%r0
L$0080:
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r26
.CALL ARGW0=GR
bl lookup_primitive_typename,%r2
nop
copy %r28,%r12
comiclr,<> 0,%r12,%r0
bl L$0081,%r0
nop
copy %r12,%r28
bl,n L$0078,%r0
bl,n L$0082,%r0
L$0081:
comiclr,= 0,%r12,%r0
bl L$0083,%r0
nop
ldo -12(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
comiclr,<> 0,%r20,%r0
bl L$0083,%r0
nop
copy %r0,%r28
bl,n L$0078,%r0
bl,n L$0084,%r0
L$0083:
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldil L'LC$0003,%r26
ldo R'LC$0003(%r26),%r26
ldw 0(%r19),%r25
.CALL ARGW0=GR,ARGW1=GR
bl error,%r2
nop
L$0084:
L$0082:
L$0079:
ldw 12(%r11),%r28
bl,n L$0078,%r0
L$0078:
ldw 8(%r4),%r12
ldw 12(%r4),%r11
ldw 16(%r4),%r10
ldw 20(%r4),%r9
ldw 24(%r4),%r8
ldw 28(%r4),%r7
ldw 32(%r4),%r6
ldw 36(%r4),%r5
ldo 8(%r4),%r30
ldw -28(%r30),%r2
bv %r0(%r2)
ldwm -8(%r30),%r4
.EXIT
.PROCEND
.IMPORT alloca,CODE
.IMPORT strlen,CODE
.IMPORT strcpy,CODE
.align 4
LC$0004:
.STRING "unsigned \x00"
.align 4
.EXPORT lookup_unsigned_typename,CODE
.EXPORT lookup_unsigned_typename,ENTRY,PRIV_LEV=3,ARGW0=GR,RTNVAL=GR
lookup_unsigned_typename:
.PROC
.CALLINFO FRAME=128,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(%r30)
copy %r4,%r1
copy %r30,%r4
stwm %r1,128(%r30)
stw %r6,16(%r4)
stw %r5,20(%r4)
ldo -4(%r0),%r5
ldo -32(%r4),%r19
add %r19,%r5,%r6
stw %r26,0(%r6)
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r26
.CALL ARGW0=GR
bl strlen,%r2
nop
copy %r28,%r19
ldo 10(%r19),%r20
ldo 7(%r20),%r21
copy %r21,%r19
ldo 63(%r19),%r20
extru %r20,25,26,%r19
zdep %r19,25,26,%r20
ldo -96(%r30),%r19
add %r30,%r20,%r30
ldo 7(%r19),%r20
extru %r20,28,29,%r19
zdep %r19,28,29,%r20
stw %r20,8(%r4)
ldw 8(%r4),%r26
ldil L'LC$0004,%r25
ldo R'LC$0004(%r25),%r25
.CALL ARGW0=GR,ARGW1=GR
bl strcpy,%r2
nop
ldw 8(%r4),%r20
ldo 9(%r20),%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
copy %r19,%r26
ldw 0(%r20),%r25
.CALL ARGW0=GR,ARGW1=GR
bl strcpy,%r2
nop
ldw 8(%r4),%r26
copy %r0,%r25
copy %r0,%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl lookup_typename,%r2
nop
bl,n L$0085,%r0
L$0085:
ldw 16(%r4),%r6
ldw 20(%r4),%r5
ldo 8(%r4),%r30
ldw -28(%r30),%r2
bv %r0(%r2)
ldwm -8(%r30),%r4
.EXIT
.PROCEND
.align 4
LC$0005:
.STRING "signed \x00"
.align 4
.EXPORT lookup_signed_typename,CODE
.EXPORT lookup_signed_typename,ENTRY,PRIV_LEV=3,ARGW0=GR,RTNVAL=GR
lookup_signed_typename:
.PROC
.CALLINFO FRAME=128,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(%r30)
copy %r4,%r1
copy %r30,%r4
stwm %r1,128(%r30)
stw %r6,16(%r4)
stw %r5,20(%r4)
ldo -4(%r0),%r5
ldo -32(%r4),%r19
add %r19,%r5,%r6
stw %r26,0(%r6)
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r26
.CALL ARGW0=GR
bl strlen,%r2
nop
copy %r28,%r19
ldo 8(%r19),%r20
ldo 7(%r20),%r21
copy %r21,%r19
ldo 63(%r19),%r20
extru %r20,25,26,%r19
zdep %r19,25,26,%r20
ldo -96(%r30),%r19
add %r30,%r20,%r30
ldo 7(%r19),%r20
extru %r20,28,29,%r19
zdep %r19,28,29,%r20
stw %r20,12(%r4)
ldw 12(%r4),%r26
ldil L'LC$0005,%r25
ldo R'LC$0005(%r25),%r25
.CALL ARGW0=GR,ARGW1=GR
bl strcpy,%r2
nop
ldw 12(%r4),%r20
ldo 7(%r20),%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
copy %r19,%r26
ldw 0(%r20),%r25
.CALL ARGW0=GR,ARGW1=GR
bl strcpy,%r2
nop
ldw 12(%r4),%r26
copy %r0,%r25
ldo 1(%r0),%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl lookup_typename,%r2
nop
stw %r28,8(%r4)
ldw 8(%r4),%r19
comiclr,<> 0,%r19,%r0
bl L$0087,%r0
nop
ldw 8(%r4),%r28
bl,n L$0086,%r0
L$0087:
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r26
copy %r0,%r25
copy %r0,%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl lookup_typename,%r2
nop
bl,n L$0086,%r0
L$0086:
ldw 16(%r4),%r6
ldw 20(%r4),%r5
ldo 8(%r4),%r30
ldw -28(%r30),%r2
bv %r0(%r2)
ldwm -8(%r30),%r4
.EXIT
.PROCEND
.align 4
LC$0006:
.STRING "No struct type named %s.\x00"
.align 4
LC$0007:
.STRING "This context has class, union or enum %s, not a struct.\x00"
.align 4
.EXPORT lookup_struct,CODE
.EXPORT lookup_struct,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,RTNVAL=GR
lookup_struct:
.PROC
.CALLINFO FRAME=128,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(%r30)
copy %r4,%r1
copy %r30,%r4
stwm %r1,128(%r30)
stw %r9,8(%r4)
stw %r8,12(%r4)
stw %r7,16(%r4)
stw %r6,20(%r4)
stw %r5,24(%r4)
ldo -4(%r0),%r5
ldo -32(%r4),%r19
add %r19,%r5,%r6
stw %r26,0(%r6)
ldo -8(%r0),%r7
ldo -32(%r4),%r19
add %r19,%r7,%r8
stw %r25,0(%r8)
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldo -8(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
stw %r0,-52(%r30)
ldw 0(%r19),%r26
ldw 0(%r20),%r25
ldo 2(%r0),%r24
copy %r0,%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl lookup_symbol,%r2
nop
copy %r28,%r9
comiclr,= 0,%r9,%r0
bl L$0089,%r0
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldil L'LC$0006,%r26
ldo R'LC$0006(%r26),%r26
ldw 0(%r19),%r25
.CALL ARGW0=GR,ARGW1=GR
bl error,%r2
nop
L$0089:
ldw 12(%r9),%r19
ldw 0(%r19),%r20
comiclr,<> 3,%r20,%r0
bl L$0090,%r0
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldil L'LC$0007,%r26
ldo R'LC$0007(%r26),%r26
ldw 0(%r19),%r25
.CALL ARGW0=GR,ARGW1=GR
bl error,%r2
nop
L$0090:
ldw 12(%r9),%r28
bl,n L$0088,%r0
L$0088:
ldw 8(%r4),%r9
ldw 12(%r4),%r8
ldw 16(%r4),%r7
ldw 20(%r4),%r6
ldw 24(%r4),%r5
ldo 8(%r4),%r30
ldw -28(%r30),%r2
bv %r0(%r2)
ldwm -8(%r30),%r4
.EXIT
.PROCEND
.align 4
LC$0008:
.STRING "No union type named %s.\x00"
.align 4
LC$0009:
.STRING "This context has class, struct or enum %s, not a union.\x00"
.align 4
.EXPORT lookup_union,CODE
.EXPORT lookup_union,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,RTNVAL=GR
lookup_union:
.PROC
.CALLINFO FRAME=128,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(%r30)
copy %r4,%r1
copy %r30,%r4
stwm %r1,128(%r30)
stw %r9,8(%r4)
stw %r8,12(%r4)
stw %r7,16(%r4)
stw %r6,20(%r4)
stw %r5,24(%r4)
ldo -4(%r0),%r5
ldo -32(%r4),%r19
add %r19,%r5,%r6
stw %r26,0(%r6)
ldo -8(%r0),%r7
ldo -32(%r4),%r19
add %r19,%r7,%r8
stw %r25,0(%r8)
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldo -8(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
stw %r0,-52(%r30)
ldw 0(%r19),%r26
ldw 0(%r20),%r25
ldo 2(%r0),%r24
copy %r0,%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl lookup_symbol,%r2
nop
copy %r28,%r9
comiclr,= 0,%r9,%r0
bl L$0092,%r0
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldil L'LC$0008,%r26
ldo R'LC$0008(%r26),%r26
ldw 0(%r19),%r25
.CALL ARGW0=GR,ARGW1=GR
bl error,%r2
nop
L$0092:
ldw 12(%r9),%r19
ldw 0(%r19),%r20
comiclr,<> 4,%r20,%r0
bl L$0093,%r0
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldil L'LC$0009,%r26
ldo R'LC$0009(%r26),%r26
ldw 0(%r19),%r25
.CALL ARGW0=GR,ARGW1=GR
bl error,%r2
nop
L$0093:
ldw 12(%r9),%r28
bl,n L$0091,%r0
L$0091:
ldw 8(%r4),%r9
ldw 12(%r4),%r8
ldw 16(%r4),%r7
ldw 20(%r4),%r6
ldw 24(%r4),%r5
ldo 8(%r4),%r30
ldw -28(%r30),%r2
bv %r0(%r2)
ldwm -8(%r30),%r4
.EXIT
.PROCEND
.align 4
LC$0010:
.STRING "No enum type named %s.\x00"
.align 4
LC$0011:
.STRING "This context has class, struct or union %s, not an enum.\x00"
.align 4
.EXPORT lookup_enum,CODE
.EXPORT lookup_enum,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,RTNVAL=GR
lookup_enum:
.PROC
.CALLINFO FRAME=128,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(%r30)
copy %r4,%r1
copy %r30,%r4
stwm %r1,128(%r30)
stw %r9,8(%r4)
stw %r8,12(%r4)
stw %r7,16(%r4)
stw %r6,20(%r4)
stw %r5,24(%r4)
ldo -4(%r0),%r5
ldo -32(%r4),%r19
add %r19,%r5,%r6
stw %r26,0(%r6)
ldo -8(%r0),%r7
ldo -32(%r4),%r19
add %r19,%r7,%r8
stw %r25,0(%r8)
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldo -8(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
stw %r0,-52(%r30)
ldw 0(%r19),%r26
ldw 0(%r20),%r25
ldo 2(%r0),%r24
copy %r0,%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl lookup_symbol,%r2
nop
copy %r28,%r9
comiclr,= 0,%r9,%r0
bl L$0095,%r0
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldil L'LC$0010,%r26
ldo R'LC$0010(%r26),%r26
ldw 0(%r19),%r25
.CALL ARGW0=GR,ARGW1=GR
bl error,%r2
nop
L$0095:
ldw 12(%r9),%r19
ldw 0(%r19),%r20
comiclr,<> 5,%r20,%r0
bl L$0096,%r0
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldil L'LC$0011,%r26
ldo R'LC$0011(%r26),%r26
ldw 0(%r19),%r25
.CALL ARGW0=GR,ARGW1=GR
bl error,%r2
nop
L$0096:
ldw 12(%r9),%r28
bl,n L$0094,%r0
L$0094:
ldw 8(%r4),%r9
ldw 12(%r4),%r8
ldw 16(%r4),%r7
ldw 20(%r4),%r6
ldw 24(%r4),%r5
ldo 8(%r4),%r30
ldw -28(%r30),%r2
bv %r0(%r2)
ldwm -8(%r30),%r4
.EXIT
.PROCEND
.IMPORT strcat,CODE
.align 4
LC$0012:
.STRING "<\x00"
.align 4
LC$0013:
.STRING " >\x00"
.align 4
LC$0014:
.STRING "No template type named %s.\x00"
.align 4
.EXPORT lookup_template_type,CODE
.EXPORT lookup_template_type,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,ARGW2=GR,RTNVAL=GR
lookup_template_type:
.PROC
.CALLINFO FRAME=192,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(%r30)
copy %r4,%r1
copy %r30,%r4
stwm %r1,192(%r30)
stw %r11,16(%r4)
stw %r10,20(%r4)
stw %r9,24(%r4)
stw %r8,28(%r4)
stw %r7,32(%r4)
stw %r6,36(%r4)
stw %r5,40(%r4)
ldo -4(%r0),%r5
ldo -32(%r4),%r19
add %r19,%r5,%r6
stw %r26,0(%r6)
ldo -8(%r0),%r7
ldo -32(%r4),%r19
add %r19,%r7,%r8
stw %r25,0(%r8)
ldo -12(%r0),%r9
ldo -32(%r4),%r19
add %r19,%r9,%r10
stw %r24,0(%r10)
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r26
.CALL ARGW0=GR
bl strlen,%r2
nop
copy %r28,%r11
ldo -8(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 4(%r19),%r26
.CALL ARGW0=GR
bl strlen,%r2
nop
copy %r28,%r19
add %r11,%r19,%r20
ldo 4(%r20),%r19
ldo 7(%r19),%r20
copy %r20,%r19
ldo 63(%r19),%r20
extru %r20,25,26,%r19
zdep %r19,25,26,%r20
ldo -96(%r30),%r19
add %r30,%r20,%r30
ldo 7(%r19),%r20
extru %r20,28,29,%r19
zdep %r19,28,29,%r20
stw %r20,12(%r4)
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 12(%r4),%r26
ldw 0(%r19),%r25
.CALL ARGW0=GR,ARGW1=GR
bl strcpy,%r2
nop
ldw 12(%r4),%r26
ldil L'LC$0012,%r25
ldo R'LC$0012(%r25),%r25
.CALL ARGW0=GR,ARGW1=GR
bl strcat,%r2
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 12(%r4),%r26
ldw 4(%r19),%r25
.CALL ARGW0=GR,ARGW1=GR
bl strcat,%r2
nop
ldw 12(%r4),%r26
ldil L'LC$0013,%r25
ldo R'LC$0013(%r25),%r25
.CALL ARGW0=GR,ARGW1=GR
bl strcat,%r2
nop
ldo -12(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
stw %r0,-52(%r30)
ldw 12(%r4),%r26
ldw 0(%r19),%r25
ldo 1(%r0),%r24
copy %r0,%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl lookup_symbol,%r2
nop
stw %r28,8(%r4)
ldw 8(%r4),%r19
comiclr,= 0,%r19,%r0
bl L$0098,%r0
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldil L'LC$0014,%r26
ldo R'LC$0014(%r26),%r26
ldw 0(%r19),%r25
.CALL ARGW0=GR,ARGW1=GR
bl error,%r2
nop
L$0098:
ldw 8(%r4),%r19
ldw 12(%r19),%r20
ldw 0(%r20),%r19
comiclr,<> 3,%r19,%r0
bl L$0099,%r0
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldil L'LC$0007,%r26
ldo R'LC$0007(%r26),%r26
ldw 0(%r19),%r25
.CALL ARGW0=GR,ARGW1=GR
bl error,%r2
nop
L$0099:
ldw 8(%r4),%r19
ldw 12(%r19),%r28
bl,n L$0097,%r0
L$0097:
ldw 16(%r4),%r11
ldw 20(%r4),%r10
ldw 24(%r4),%r9
ldw 28(%r4),%r8
ldw 32(%r4),%r7
ldw 36(%r4),%r6
ldw 40(%r4),%r5
ldo 8(%r4),%r30
ldw -28(%r30),%r2
bv %r0(%r2)
ldwm -8(%r30),%r4
.EXIT
.PROCEND
.IMPORT current_target,DATA
.IMPORT fflush,CODE
.IMPORT __iob,DATA
.IMPORT fprintf,CODE
.align 4
LC$0015:
.STRING "Type \x00"
.IMPORT type_print,CODE
.align 4
LC$0016:
.STRING "\x00"
.align 4
LC$0017:
.STRING " is not a structure or union type.\x00"
.IMPORT check_stub_type,CODE
.align 4
LC$0018:
.STRING " has no component named \x00"
.IMPORT fputs_filtered,CODE
.align 4
LC$0019:
.STRING ".\x00"
.align 4
.EXPORT lookup_struct_elt_type,CODE
.EXPORT lookup_struct_elt_type,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,ARGW2=GR,RTNVAL=GR
lookup_struct_elt_type:
.PROC
.CALLINFO FRAME=192,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(%r30)
copy %r4,%r1
copy %r30,%r4
stwm %r1,192(%r30)
stw %r11,24(%r4)
stw %r10,28(%r4)
stw %r9,32(%r4)
stw %r8,36(%r4)
stw %r7,40(%r4)
stw %r6,44(%r4)
stw %r5,48(%r4)
ldo -4(%r0),%r5
ldo -32(%r4),%r19
add %r19,%r5,%r6
stw %r26,0(%r6)
ldo -8(%r0),%r7
ldo -32(%r4),%r19
add %r19,%r7,%r8
stw %r25,0(%r8)
ldo -12(%r0),%r9
ldo -32(%r4),%r19
add %r19,%r9,%r10
stw %r24,0(%r10)
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 0(%r19),%r20
comiclr,<> 1,%r20,%r0
bl L$0102,%r0
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 0(%r19),%r20
ldo 16(%r0),%r19
comclr,<> %r20,%r19,%r0
bl L$0102,%r0
nop
bl,n L$0101,%r0
L$0102:
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r22
add %r22,%r20,%r21
ldw 0(%r21),%r20
ldw 16(%r20),%r21
stw %r21,0(%r19)
L$0101:
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 0(%r19),%r20
comiclr,<> 3,%r20,%r0
bl L$0103,%r0
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 0(%r19),%r20
comiclr,<> 4,%r20,%r0
bl L$0103,%r0
nop
addil L'current_target-$global$,%r27
ldw R'current_target-$global$(%r1),%r19
ldw 76(%r19),%r11
copy %r11,%r22
.CALL ARGW0=GR
bl $$dyncall,%r31
copy %r31,%r2
addil L'__iob-$global$+16,%r27
ldo R'__iob-$global$+16(%r1),%r26
.CALL ARGW0=GR
bl fflush,%r2
nop
addil L'__iob-$global$+32,%r27
ldo R'__iob-$global$+32(%r1),%r26
ldil L'LC$0015,%r25
ldo R'LC$0015(%r25),%r25
.CALL ARGW0=GR,ARGW1=GR
bl fprintf,%r2
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r26
ldil L'LC$0016,%r25
ldo R'LC$0016(%r25),%r25
addil L'__iob-$global$+32,%r27
ldo R'__iob-$global$+32(%r1),%r24
ldo -1(%r0),%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl type_print,%r2
nop
ldil L'LC$0017,%r26
ldo R'LC$0017(%r26),%r26
.CALL ARGW0=GR
bl error,%r2
nop
L$0103:
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r26
.CALL ARGW0=GR
bl check_stub_type,%r2
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldh 34(%r19),%r20
extrs %r20,31,16,%r19
ldo -1(%r19),%r20
stw %r20,8(%r4)
L$0104:
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 48(%r19),%r20
ldh 0(%r20),%r21
extrs %r21,31,16,%r19
ldw 8(%r4),%r20
comclr,>= %r20,%r19,%r0
bl L$0105,%r0
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 8(%r4),%r20
zdep %r20,27,28,%r21
ldw 36(%r19),%r20
add %r21,%r20,%r19
ldw 12(%r19),%r20
stw %r20,12(%r4)
ldw 12(%r4),%r19
comiclr,<> 0,%r19,%r0
bl L$0107,%r0
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 12(%r4),%r26
ldw 0(%r19),%r25
.CALL ARGW0=GR,ARGW1=GR
bl strcmp,%r2
nop
copy %r28,%r19
comiclr,= 0,%r19,%r0
bl L$0107,%r0
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 8(%r4),%r20
zdep %r20,27,28,%r21
ldw 36(%r19),%r20
add %r21,%r20,%r19
ldw 8(%r19),%r28
bl,n L$0100,%r0
L$0107:
L$0106:
ldw 8(%r4),%r19
ldo -1(%r19),%r20
stw %r20,8(%r4)
bl,n L$0104,%r0
L$0105:
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 48(%r19),%r20
ldh 0(%r20),%r21
extrs %r21,31,16,%r19
ldo -1(%r19),%r20
stw %r20,8(%r4)
L$0108:
ldw 8(%r4),%r19
comiclr,<= 0,%r19,%r0
bl L$0109,%r0
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 8(%r4),%r20
zdep %r20,27,28,%r21
ldw 36(%r19),%r20
add %r21,%r20,%r19
ldo -8(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
ldw 8(%r19),%r26
ldw 0(%r20),%r25
copy %r0,%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl lookup_struct_elt_type,%r2
nop
stw %r28,16(%r4)
ldw 16(%r4),%r19
comiclr,<> 0,%r19,%r0
bl L$0111,%r0
nop
ldw 16(%r4),%r28
bl,n L$0100,%r0
L$0111:
L$0110:
ldw 8(%r4),%r19
ldo -1(%r19),%r20
stw %r20,8(%r4)
bl,n L$0108,%r0
L$0109:
ldo -12(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
comiclr,<> 0,%r20,%r0
bl L$0112,%r0
nop
copy %r0,%r28
bl,n L$0100,%r0
L$0112:
addil L'current_target-$global$,%r27
ldw R'current_target-$global$(%r1),%r19
ldw 76(%r19),%r11
copy %r11,%r22
.CALL ARGW0=GR
bl $$dyncall,%r31
copy %r31,%r2
addil L'__iob-$global$+16,%r27
ldo R'__iob-$global$+16(%r1),%r26
.CALL ARGW0=GR
bl fflush,%r2
nop
addil L'__iob-$global$+32,%r27
ldo R'__iob-$global$+32(%r1),%r26
ldil L'LC$0015,%r25
ldo R'LC$0015(%r25),%r25
.CALL ARGW0=GR,ARGW1=GR
bl fprintf,%r2
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r26
ldil L'LC$0016,%r25
ldo R'LC$0016(%r25),%r25
addil L'__iob-$global$+32,%r27
ldo R'__iob-$global$+32(%r1),%r24
ldo -1(%r0),%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl type_print,%r2
nop
addil L'__iob-$global$+32,%r27
ldo R'__iob-$global$+32(%r1),%r26
ldil L'LC$0018,%r25
ldo R'LC$0018(%r25),%r25
.CALL ARGW0=GR,ARGW1=GR
bl fprintf,%r2
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r26
addil L'__iob-$global$+32,%r27
ldo R'__iob-$global$+32(%r1),%r25
.CALL ARGW0=GR,ARGW1=GR
bl fputs_filtered,%r2
nop
ldil L'LC$0019,%r26
ldo R'LC$0019(%r26),%r26
.CALL ARGW0=GR
bl error,%r2
nop
ldo -1(%r0),%r28
bl,n L$0100,%r0
L$0100:
ldw 24(%r4),%r11
ldw 28(%r4),%r10
ldw 32(%r4),%r9
ldw 36(%r4),%r8
ldw 40(%r4),%r7
ldw 44(%r4),%r6
ldw 48(%r4),%r5
ldo 8(%r4),%r30
ldw -28(%r30),%r2
bv %r0(%r2)
ldwm -8(%r30),%r4
.EXIT
.PROCEND
.align 4
.EXPORT fill_in_vptr_fieldno,CODE
.EXPORT fill_in_vptr_fieldno,ENTRY,PRIV_LEV=3,ARGW0=GR
fill_in_vptr_fieldno:
.PROC
.CALLINFO FRAME=128,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(%r30)
copy %r4,%r1
copy %r30,%r4
stwm %r1,128(%r30)
stw %r6,16(%r4)
stw %r5,20(%r4)
ldo -4(%r0),%r5
ldo -32(%r4),%r19
add %r19,%r5,%r6
stw %r26,0(%r6)
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 44(%r19),%r20
comiclr,> 0,%r20,%r0
bl L$0114,%r0
nop
ldo 1(%r0),%r19
stw %r19,8(%r4)
L$0115:
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 48(%r19),%r20
ldh 0(%r20),%r21
extrs %r21,31,16,%r19
ldw 8(%r4),%r20
comclr,< %r20,%r19,%r0
bl L$0116,%r0
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 8(%r4),%r20
zdep %r20,27,28,%r21
ldw 36(%r19),%r20
add %r21,%r20,%r19
ldw 8(%r19),%r26
.CALL ARGW0=GR
bl fill_in_vptr_fieldno,%r2
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 8(%r4),%r20
zdep %r20,27,28,%r21
ldw 36(%r19),%r20
add %r21,%r20,%r19
ldw 8(%r19),%r20
ldw 44(%r20),%r19
comiclr,<= 0,%r19,%r0
bl L$0118,%r0
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r22
add %r22,%r20,%r21
ldw 0(%r21),%r20
ldw 8(%r4),%r21
zdep %r21,27,28,%r22
ldw 36(%r20),%r21
add %r22,%r21,%r20
ldw 8(%r20),%r21
ldw 44(%r21),%r20
stw %r20,44(%r19)
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r22
add %r22,%r20,%r21
ldw 0(%r21),%r20
ldw 8(%r4),%r21
zdep %r21,27,28,%r22
ldw 36(%r20),%r21
add %r22,%r21,%r20
ldw 8(%r20),%r21
ldw 40(%r21),%r20
stw %r20,40(%r19)
bl,n L$0116,%r0
L$0118:
L$0117:
ldw 8(%r4),%r19
ldo 1(%r19),%r20
stw %r20,8(%r4)
bl,n L$0115,%r0
L$0116:
L$0114:
L$0113:
ldw 16(%r4),%r6
ldw 20(%r4),%r5
ldo 8(%r4),%r30
ldw -28(%r30),%r2
bv %r0(%r2)
ldwm -8(%r30),%r4
.EXIT
.PROCEND
.EXPORT stub_noname_complaint,DATA
.align 4
LC$0020:
.STRING "stub type has NULL name\x00"
.data
.align 4
stub_noname_complaint:
.word LC$0020
.word 0
.word 0
.IMPORT complain,CODE
.IMPORT memcpy,CODE
.code
.align 4
.EXPORT check_stub_type,CODE
.EXPORT check_stub_type,ENTRY,PRIV_LEV=3,ARGW0=GR
check_stub_type:
.PROC
.CALLINFO FRAME=128,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(%r30)
copy %r4,%r1
copy %r30,%r4
stwm %r1,128(%r30)
stw %r6,16(%r4)
stw %r5,20(%r4)
ldo -4(%r0),%r5
ldo -32(%r4),%r19
add %r19,%r5,%r6
stw %r26,0(%r6)
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldh 32(%r19),%r20
ldo 4(%r0),%r21
and %r20,%r21,%r19
extrs %r19,31,16,%r20
comiclr,<> 0,%r20,%r0
bl L$0120,%r0
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r26
.CALL ARGW0=GR
bl type_name_no_tag,%r2
nop
stw %r28,8(%r4)
ldw 8(%r4),%r19
comiclr,= 0,%r19,%r0
bl L$0121,%r0
nop
addil L'stub_noname_complaint-$global$,%r27
ldo R'stub_noname_complaint-$global$(%r1),%r26
copy %r0,%r25
.CALL ARGW0=GR,ARGW1=GR
bl complain,%r2
nop
bl,n L$0119,%r0
L$0121:
stw %r0,-52(%r30)
ldw 8(%r4),%r26
copy %r0,%r25
ldo 2(%r0),%r24
copy %r0,%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl lookup_symbol,%r2
nop
stw %r28,12(%r4)
ldw 12(%r4),%r19
comiclr,<> 0,%r19,%r0
bl L$0122,%r0
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 12(%r4),%r20
ldw 0(%r19),%r26
ldw 12(%r20),%r25
ldo 52(%r0),%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl memcpy,%r2
nop
L$0122:
L$0120:
L$0119:
ldw 16(%r4),%r6
ldw 20(%r4),%r5
ldo 8(%r4),%r30
ldw -28(%r30),%r2
bv %r0(%r2)
ldwm -8(%r30),%r4
.EXIT
.PROCEND
.IMPORT gdb_mangle_name,CODE
.IMPORT cplus_demangle,CODE
.align 4
LC$0021:
.STRING "Internal: Cannot demangle mangled name `%s'.\x00"
.IMPORT strchr,CODE
.IMPORT parse_and_eval_type,CODE
.IMPORT builtin_type_void,DATA
.IMPORT free,CODE
.align 4
.EXPORT check_stub_method,CODE
.EXPORT check_stub_method,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,ARGW2=GR
check_stub_method:
.PROC
.CALLINFO FRAME=192,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(%r30)
copy %r4,%r1
copy %r30,%r4
stwm %r1,192(%r30)
stw %r11,64(%r4)
stw %r10,68(%r4)
stw %r9,72(%r4)
stw %r8,76(%r4)
stw %r7,80(%r4)
stw %r6,84(%r4)
stw %r5,88(%r4)
ldo -4(%r0),%r5
ldo -32(%r4),%r19
add %r19,%r5,%r6
stw %r26,0(%r6)
ldo -8(%r0),%r7
ldo -32(%r4),%r19
add %r19,%r7,%r8
stw %r25,0(%r8)
ldo -12(%r0),%r9
ldo -32(%r4),%r19
add %r19,%r9,%r10
stw %r24,0(%r10)
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldo -8(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
ldo -12(%r0),%r21
ldo -32(%r4),%r22
add %r22,%r21,%r21
ldw 0(%r19),%r26
ldw 0(%r20),%r25
ldw 0(%r21),%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl gdb_mangle_name,%r2
nop
stw %r28,12(%r4)
ldw 12(%r4),%r26
ldo 3(%r0),%r25
.CALL ARGW0=GR,ARGW1=GR
bl cplus_demangle,%r2
nop
stw %r28,16(%r4)
stw %r0,28(%r4)
ldo 1(%r0),%r19
stw %r19,32(%r4)
ldw 16(%r4),%r19
comiclr,= 0,%r19,%r0
bl L$0124,%r0
nop
ldil L'LC$0021,%r26
ldo R'LC$0021(%r26),%r26
ldw 12(%r4),%r25
.CALL ARGW0=GR,ARGW1=GR
bl error,%r2
nop
L$0124:
ldw 16(%r4),%r26
ldo 40(%r0),%r25
.CALL ARGW0=GR,ARGW1=GR
bl strchr,%r2
nop
copy %r28,%r19
ldo 1(%r19),%r20
stw %r20,20(%r4)
ldw 20(%r4),%r19
stw %r19,24(%r4)
L$0125:
ldw 24(%r4),%r19
ldb 0(%r19),%r20
extrs %r20,31,8,%r19
comiclr,<> 0,%r19,%r0
bl L$0126,%r0
nop
ldw 24(%r4),%r19
ldb 0(%r19),%r20
extrs %r20,31,8,%r19
ldo 40(%r0),%r20
comclr,= %r19,%r20,%r0
bl L$0127,%r0
nop
ldw 28(%r4),%r19
ldo 1(%r19),%r20
stw %r20,28(%r4)
bl,n L$0128,%r0
L$0127:
ldw 24(%r4),%r19
ldb 0(%r19),%r20
extrs %r20,31,8,%r19
ldo 41(%r0),%r20
comclr,= %r19,%r20,%r0
bl L$0129,%r0
nop
ldw 28(%r4),%r19
ldo -1(%r19),%r20
stw %r20,28(%r4)
bl,n L$0130,%r0
L$0129:
ldw 24(%r4),%r19
ldb 0(%r19),%r20
extrs %r20,31,8,%r19
ldo 44(%r0),%r20
comclr,= %r19,%r20,%r0
bl L$0131,%r0
nop
ldw 28(%r4),%r19
comiclr,= 0,%r19,%r0
bl L$0131,%r0
nop
ldw 32(%r4),%r19
ldo 1(%r19),%r20
stw %r20,32(%r4)
L$0131:
L$0130:
L$0128:
ldw 24(%r4),%r19
ldo 1(%r19),%r20
stw %r20,24(%r4)
bl,n L$0125,%r0
L$0126:
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 12(%r19),%r20
comiclr,<> 0,%r20,%r0
bl L$0137,%r0
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 12(%r19),%r20
ldo 120(%r20),%r19
stw %r19,44(%r4)
ldw 44(%r4),%r19
stw %r19,48(%r4)
ldw 32(%r4),%r20
ldo 2(%r20),%r19
zdep %r19,29,30,%r20
stw %r20,52(%r4)
ldw 48(%r4),%r19
ldw 48(%r4),%r20
ldw 16(%r19),%r19
ldw 12(%r20),%r20
sub %r19,%r20,%r19
ldw 52(%r4),%r20
comclr,< %r19,%r20,%r0
bl L$0132,%r0
nop
ldw 48(%r4),%r26
ldw 52(%r4),%r25
.CALL ARGW0=GR,ARGW1=GR
bl _obstack_newchunk,%r2
nop
copy %r0,%r19
bl,n L$0133,%r0
L$0132:
copy %r0,%r19
L$0133:
ldw 48(%r4),%r19
ldw 48(%r4),%r20
ldw 12(%r20),%r21
ldw 52(%r4),%r22
add %r21,%r22,%r20
copy %r20,%r21
stw %r21,12(%r19)
ldw 44(%r4),%r19
stw %r19,56(%r4)
ldw 56(%r4),%r19
ldw 8(%r19),%r20
stw %r20,60(%r4)
ldw 56(%r4),%r19
ldw 12(%r19),%r20
ldw 60(%r4),%r19
comclr,= %r20,%r19,%r0
bl L$0134,%r0
nop
ldw 56(%r4),%r19
ldw 40(%r19),%r20
copy %r20,%r21
depi -1,1,1,%r21
stw %r21,40(%r19)
L$0134:
ldw 56(%r4),%r19
ldw 56(%r4),%r20
ldw 56(%r4),%r21
ldw 12(%r20),%r20
ldw 24(%r21),%r21
add %r20,%r21,%r20
ldw 56(%r4),%r21
ldw 24(%r21),%r22
uaddcm %r0,%r22,%r21
and %r20,%r21,%r20
copy %r20,%r21
stw %r21,12(%r19)
ldw 56(%r4),%r19
ldw 56(%r4),%r20
ldw 12(%r19),%r19
ldw 4(%r20),%r20
sub %r19,%r20,%r19
ldw 56(%r4),%r20
ldw 56(%r4),%r21
ldw 16(%r20),%r20
ldw 4(%r21),%r21
sub %r20,%r21,%r20
comclr,> %r19,%r20,%r0
bl L$0135,%r0
nop
ldw 56(%r4),%r19
ldw 56(%r4),%r20
ldw 16(%r20),%r21
stw %r21,12(%r19)
copy %r21,%r19
bl,n L$0136,%r0
L$0135:
copy %r0,%r19
L$0136:
ldw 56(%r4),%r19
ldw 56(%r4),%r20
ldw 12(%r20),%r21
stw %r21,8(%r19)
ldw 60(%r4),%r11
bl,n L$0138,%r0
L$0137:
ldw 32(%r4),%r20
ldo 2(%r20),%r19
zdep %r19,29,30,%r20
copy %r20,%r26
.CALL ARGW0=GR
bl xmalloc,%r2
nop
copy %r28,%r11
L$0138:
stw %r11,36(%r4)
ldw 20(%r4),%r19
stw %r19,24(%r4)
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r26
.CALL ARGW0=GR
bl lookup_pointer_type,%r2
nop
copy %r28,%r19
ldw 36(%r4),%r20
stw %r19,0(%r20)
ldo 1(%r0),%r19
stw %r19,32(%r4)
ldw 24(%r4),%r19
ldb 0(%r19),%r20
extrs %r20,31,8,%r19
ldo 41(%r0),%r20
comclr,<> %r19,%r20,%r0
bl L$0139,%r0
nop
stw %r0,28(%r4)
L$0140:
ldw 24(%r4),%r19
ldb 0(%r19),%r20
extrs %r20,31,8,%r19
comiclr,<> 0,%r19,%r0
bl L$0141,%r0
nop
ldw 28(%r4),%r19
comiclr,>= 0,%r19,%r0
bl L$0142,%r0
nop
ldw 24(%r4),%r19
ldb 0(%r19),%r20
extrs %r20,31,8,%r19
ldo 44(%r0),%r20
comclr,<> %r19,%r20,%r0
bl L$0143,%r0
nop
ldw 24(%r4),%r19
ldb 0(%r19),%r20
extrs %r20,31,8,%r19
ldo 41(%r0),%r20
comclr,<> %r19,%r20,%r0
bl L$0143,%r0
nop
bl,n L$0142,%r0
L$0143:
ldw 24(%r4),%r19
ldw 20(%r4),%r20
sub %r19,%r20,%r19
ldw 20(%r4),%r26
copy %r19,%r25
.CALL ARGW0=GR,ARGW1=GR
bl parse_and_eval_type,%r2
nop
copy %r28,%r19
ldw 32(%r4),%r20
zdep %r20,29,30,%r21
ldw 36(%r4),%r22
add %r21,%r22,%r20
stw %r19,0(%r20)
ldw 32(%r4),%r19
ldo 1(%r19),%r20
stw %r20,32(%r4)
ldw 24(%r4),%r19
ldo 1(%r19),%r20
stw %r20,20(%r4)
L$0142:
ldw 24(%r4),%r19
ldb 0(%r19),%r20
extrs %r20,31,8,%r19
ldo 40(%r0),%r20
comclr,= %r19,%r20,%r0
bl L$0144,%r0
nop
ldw 28(%r4),%r19
ldo 1(%r19),%r20
stw %r20,28(%r4)
bl,n L$0145,%r0
L$0144:
ldw 24(%r4),%r19
ldb 0(%r19),%r20
extrs %r20,31,8,%r19
ldo 41(%r0),%r20
comclr,= %r19,%r20,%r0
bl L$0146,%r0
nop
ldw 28(%r4),%r19
ldo -1(%r19),%r20
stw %r20,28(%r4)
L$0146:
L$0145:
ldw 24(%r4),%r19
ldo 1(%r19),%r20
stw %r20,24(%r4)
bl,n L$0140,%r0
L$0141:
L$0139:
ldo -2(%r0),%r19
ldw 24(%r4),%r20
add %r19,%r20,%r19
ldb 0(%r19),%r20
extrs %r20,31,8,%r19
ldo 46(%r0),%r20
comclr,<> %r19,%r20,%r0
bl L$0147,%r0
nop
ldw 32(%r4),%r19
zdep %r19,29,30,%r20
ldw 36(%r4),%r21
add %r20,%r21,%r19
addil L'builtin_type_void-$global$,%r27
ldw R'builtin_type_void-$global$(%r1),%r20
stw %r20,0(%r19)
bl,n L$0148,%r0
L$0147:
ldw 32(%r4),%r19
zdep %r19,29,30,%r20
ldw 36(%r4),%r21
add %r20,%r21,%r19
stw %r0,0(%r19)
L$0148:
ldw 16(%r4),%r26
.CALL ARGW0=GR
bl free,%r2
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
ldw 48(%r20),%r19
ldo -8(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
ldw 0(%r20),%r21
zdep %r21,30,31,%r20
add %r20,%r21,%r20
zdep %r20,29,30,%r20
ldw 20(%r19),%r21
add %r20,%r21,%r19
ldw 8(%r19),%r20
stw %r20,8(%r4)
ldo -12(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
zdep %r20,29,30,%r19
add %r19,%r20,%r19
zdep %r19,29,30,%r19
ldw 8(%r4),%r20
add %r19,%r20,%r19
ldw 12(%r4),%r20
stw %r20,0(%r19)
ldo -12(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
zdep %r20,29,30,%r19
add %r19,%r20,%r19
zdep %r19,29,30,%r19
ldw 8(%r4),%r20
add %r19,%r20,%r19
ldw 4(%r19),%r20
stw %r20,40(%r4)
ldw 40(%r4),%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
ldw 0(%r20),%r21
stw %r21,40(%r19)
ldw 40(%r4),%r19
ldw 36(%r4),%r20
stw %r20,48(%r19)
ldw 40(%r4),%r19
ldw 40(%r4),%r20
ldh 32(%r20),%r21
copy %r21,%r20
depi 0,29,1,%r20
sth %r20,32(%r19)
ldo -12(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
zdep %r20,29,30,%r19
add %r19,%r20,%r19
zdep %r19,29,30,%r19
ldw 8(%r4),%r20
add %r19,%r20,%r19
ldw 16(%r19),%r20
copy %r20,%r21
depi 0,4,1,%r21
stw %r21,16(%r19)
L$0123:
ldw 64(%r4),%r11
ldw 68(%r4),%r10
ldw 72(%r4),%r9
ldw 76(%r4),%r8
ldw 80(%r4),%r7
ldw 84(%r4),%r6
ldw 88(%r4),%r5
ldo 8(%r4),%r30
ldw -28(%r30),%r2
bv %r0(%r2)
ldwm -8(%r30),%r4
.EXIT
.PROCEND
.align 4
.EXPORT allocate_cplus_struct_type,CODE
.EXPORT allocate_cplus_struct_type,ENTRY,PRIV_LEV=3,ARGW0=GR
allocate_cplus_struct_type:
.PROC
.CALLINFO FRAME=192,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(%r30)
copy %r4,%r1
copy %r30,%r4
stwm %r1,192(%r30)
stw %r8,32(%r4)
stw %r7,36(%r4)
stw %r6,40(%r4)
stw %r5,44(%r4)
ldo -4(%r0),%r5
ldo -32(%r4),%r19
add %r19,%r5,%r6
stw %r26,0(%r6)
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
ldw 48(%r20),%r19
comclr,= %r19,%r20,%r0
bl L$0150,%r0
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r7
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 12(%r19),%r20
comiclr,<> 0,%r20,%r0
bl L$0156,%r0
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 12(%r19),%r20
ldo 120(%r20),%r19
stw %r19,8(%r4)
ldw 8(%r4),%r19
stw %r19,12(%r4)
ldo 24(%r0),%r19
stw %r19,16(%r4)
ldw 12(%r4),%r19
ldw 12(%r4),%r20
ldw 16(%r19),%r19
ldw 12(%r20),%r20
sub %r19,%r20,%r19
ldw 16(%r4),%r20
comclr,< %r19,%r20,%r0
bl L$0151,%r0
nop
ldw 12(%r4),%r26
ldw 16(%r4),%r25
.CALL ARGW0=GR,ARGW1=GR
bl _obstack_newchunk,%r2
nop
copy %r0,%r19
bl,n L$0152,%r0
L$0151:
copy %r0,%r19
L$0152:
ldw 12(%r4),%r19
ldw 12(%r4),%r20
ldw 12(%r20),%r21
ldw 16(%r4),%r22
add %r21,%r22,%r20
copy %r20,%r21
stw %r21,12(%r19)
ldw 8(%r4),%r19
stw %r19,20(%r4)
ldw 20(%r4),%r19
ldw 8(%r19),%r20
stw %r20,24(%r4)
ldw 20(%r4),%r19
ldw 12(%r19),%r20
ldw 24(%r4),%r19
comclr,= %r20,%r19,%r0
bl L$0153,%r0
nop
ldw 20(%r4),%r19
ldw 40(%r19),%r20
copy %r20,%r21
depi -1,1,1,%r21
stw %r21,40(%r19)
L$0153:
ldw 20(%r4),%r19
ldw 20(%r4),%r20
ldw 20(%r4),%r21
ldw 12(%r20),%r20
ldw 24(%r21),%r21
add %r20,%r21,%r20
ldw 20(%r4),%r21
ldw 24(%r21),%r22
uaddcm %r0,%r22,%r21
and %r20,%r21,%r20
copy %r20,%r21
stw %r21,12(%r19)
ldw 20(%r4),%r19
ldw 20(%r4),%r20
ldw 12(%r19),%r19
ldw 4(%r20),%r20
sub %r19,%r20,%r19
ldw 20(%r4),%r20
ldw 20(%r4),%r21
ldw 16(%r20),%r20
ldw 4(%r21),%r21
sub %r20,%r21,%r20
comclr,> %r19,%r20,%r0
bl L$0154,%r0
nop
ldw 20(%r4),%r19
ldw 20(%r4),%r20
ldw 16(%r20),%r21
stw %r21,12(%r19)
copy %r21,%r19
bl,n L$0155,%r0
L$0154:
copy %r0,%r19
L$0155:
ldw 20(%r4),%r19
ldw 20(%r4),%r20
ldw 12(%r20),%r21
stw %r21,8(%r19)
ldw 24(%r4),%r8
bl,n L$0157,%r0
L$0156:
ldo 24(%r0),%r26
.CALL ARGW0=GR
bl xmalloc,%r2
nop
copy %r28,%r8
L$0157:
stw %r8,48(%r7)
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 48(%r19),%r20
copy %r20,%r21
ldws,ma 4(%r22),%r19
ldws,ma 4(%r22),%r20
stws,ma %r19,4(%r21)
ldws,ma 4(%r22),%r19
stws,ma %r20,4(%r21)
ldws,ma 4(%r22),%r20
stws,ma %r19,4(%r21)
ldws,ma 4(%r22),%r19
stws,ma %r20,4(%r21)
ldws,ma 4(%r22),%r20
stws,ma %r19,4(%r21)
stw %r20,0(%r21)
L$0150:
L$0149:
ldw 32(%r4),%r8
ldw 36(%r4),%r7
ldw 40(%r4),%r6
ldw 44(%r4),%r5
ldo 8(%r4),%r30
ldw -28(%r30),%r2
bv %r0(%r2)
ldwm -8(%r30),%r4
.EXIT
.PROCEND
.IMPORT obsavestring,CODE
.align 4
.EXPORT init_type,CODE
.EXPORT init_type,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR,RTNVAL=GR
init_type:
.PROC
.CALLINFO FRAME=192,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(%r30)
copy %r4,%r1
copy %r30,%r4
stwm %r1,192(%r30)
stw %r14,8(%r4)
stw %r13,12(%r4)
stw %r12,16(%r4)
stw %r11,20(%r4)
stw %r10,24(%r4)
stw %r9,28(%r4)
stw %r8,32(%r4)
stw %r7,36(%r4)
stw %r6,40(%r4)
stw %r5,44(%r4)
ldo -4(%r0),%r5
ldo -32(%r4),%r19
add %r19,%r5,%r6
stw %r26,0(%r6)
ldo -8(%r0),%r7
ldo -32(%r4),%r19
add %r19,%r7,%r8
stw %r25,0(%r8)
ldo -12(%r0),%r9
ldo -32(%r4),%r19
add %r19,%r9,%r10
stw %r24,0(%r10)
ldo -16(%r0),%r11
ldo -32(%r4),%r19
add %r19,%r11,%r12
stw %r23,0(%r12)
ldo -20(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r26
.CALL ARGW0=GR
bl alloc_type,%r2
nop
copy %r28,%r13
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
stw %r20,0(%r13)
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
stw %r20,8(%r13)
ldo -12(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldh 32(%r13),%r20
ldh 2(%r19),%r19
or %r20,%r19,%r20
sth %r20,32(%r13)
ldo -16(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
comiclr,<> 0,%r20,%r0
bl L$0159,%r0
nop
ldo -20(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
comiclr,<> 0,%r20,%r0
bl L$0159,%r0
nop
ldo -16(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r14
ldo -16(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r26
.CALL ARGW0=GR
bl strlen,%r2
nop
copy %r28,%r19
ldo -20(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
ldw 0(%r20),%r21
ldo 120(%r21),%r20
ldw 0(%r14),%r26
copy %r19,%r25
copy %r20,%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl obsavestring,%r2
nop
copy %r28,%r19
stw %r19,4(%r13)
bl,n L$0160,%r0
L$0159:
ldo -16(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
stw %r20,4(%r13)
L$0160:
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
comiclr,<> 3,%r20,%r0
bl L$0162,%r0
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
comiclr,<> 4,%r20,%r0
bl L$0162,%r0
nop
bl,n L$0161,%r0
L$0162:
stw %r19,48(%r13)
L$0161:
copy %r13,%r28
bl,n L$0158,%r0
L$0158:
ldw 8(%r4),%r14
ldw 12(%r4),%r13
ldw 16(%r4),%r12
ldw 20(%r4),%r11
ldw 24(%r4),%r10
ldw 28(%r4),%r9
ldw 32(%r4),%r8
ldw 36(%r4),%r7
ldw 40(%r4),%r6
ldw 44(%r4),%r5
ldo 8(%r4),%r30
ldw -28(%r30),%r2
bv %r0(%r2)
ldwm -8(%r30),%r4
.EXIT
.PROCEND
.align 4
LC$0022:
.STRING "internal error - invalid fundamental type id %d\x00"
.align 4
LC$0023:
.STRING "internal error: unhandled type id %d\x00"
.align 4
LC$0024:
.STRING "void\x00"
.align 4
LC$0025:
.STRING "boolean\x00"
.align 4
LC$0026:
.STRING "string\x00"
.align 4
LC$0027:
.STRING "char\x00"
.align 4
LC$0028:
.STRING "signed char\x00"
.align 4
LC$0029:
.STRING "unsigned char\x00"
.align 4
LC$0030:
.STRING "short\x00"
.align 4
LC$0031:
.STRING "unsigned short\x00"
.align 4
LC$0032:
.STRING "int\x00"
.align 4
LC$0033:
.STRING "unsigned int\x00"
.align 4
LC$0034:
.STRING "fixed decimal\x00"
.align 4
LC$0035:
.STRING "long\x00"
.align 4
LC$0036:
.STRING "unsigned long\x00"
.align 4
LC$0037:
.STRING "long long\x00"
.align 4
LC$0038:
.STRING "signed long long\x00"
.align 4
LC$0039:
.STRING "unsigned long long\x00"
.align 4
LC$0040:
.STRING "float\x00"
.align 4
LC$0041:
.STRING "double\x00"
.align 4
LC$0042:
.STRING "floating decimal\x00"
.align 4
LC$0043:
.STRING "long double\x00"
.align 4
LC$0044:
.STRING "complex\x00"
.align 4
LC$0045:
.STRING "double complex\x00"
.align 4
LC$0046:
.STRING "long double complex\x00"
.align 4
.EXPORT lookup_fundamental_type,CODE
.EXPORT lookup_fundamental_type,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,RTNVAL=GR
lookup_fundamental_type:
.PROC
.CALLINFO FRAME=192,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(%r30)
copy %r4,%r1
copy %r30,%r4
stwm %r1,192(%r30)
stw %r12,32(%r4)
stw %r11,36(%r4)
stw %r10,40(%r4)
stw %r9,44(%r4)
stw %r8,48(%r4)
stw %r7,52(%r4)
stw %r6,56(%r4)
stw %r5,60(%r4)
ldo -4(%r0),%r5
ldo -32(%r4),%r19
add %r19,%r5,%r6
stw %r26,0(%r6)
ldo -8(%r0),%r7
ldo -32(%r4),%r19
add %r19,%r7,%r8
stw %r25,0(%r8)
copy %r0,%r9
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
comiclr,<= 0,%r20,%r0
bl L$0165,%r0
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
ldo 25(%r0),%r19
comclr,<= %r20,%r19,%r0
bl L$0165,%r0
nop
bl,n L$0164,%r0
L$0165:
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldil L'LC$0022,%r26
ldo R'LC$0022(%r26),%r26
ldw 0(%r19),%r25
.CALL ARGW0=GR,ARGW1=GR
bl error,%r2
nop
bl,n L$0166,%r0
L$0164:
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 196(%r19),%r20
comiclr,= 0,%r20,%r0
bl L$0167,%r0
nop
ldo 104(%r0),%r11
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r12
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldo 120(%r19),%r20
stw %r20,8(%r4)
ldw 8(%r4),%r19
stw %r19,12(%r4)
stw %r11,16(%r4)
ldw 12(%r4),%r19
ldw 12(%r4),%r20
ldw 16(%r19),%r19
ldw 12(%r20),%r20
sub %r19,%r20,%r19
ldw 16(%r4),%r20
comclr,< %r19,%r20,%r0
bl L$0168,%r0
nop
ldw 12(%r4),%r26
ldw 16(%r4),%r25
.CALL ARGW0=GR,ARGW1=GR
bl _obstack_newchunk,%r2
nop
copy %r0,%r19
bl,n L$0169,%r0
L$0168:
copy %r0,%r19
L$0169:
ldw 12(%r4),%r19
ldw 12(%r4),%r20
ldw 12(%r20),%r21
ldw 16(%r4),%r22
add %r21,%r22,%r20
copy %r20,%r21
stw %r21,12(%r19)
ldw 8(%r4),%r19
stw %r19,20(%r4)
ldw 20(%r4),%r19
ldw 8(%r19),%r20
stw %r20,24(%r4)
ldw 20(%r4),%r19
ldw 12(%r19),%r20
ldw 24(%r4),%r19
comclr,= %r20,%r19,%r0
bl L$0170,%r0
nop
ldw 20(%r4),%r19
ldw 40(%r19),%r20
copy %r20,%r21
depi -1,1,1,%r21
stw %r21,40(%r19)
L$0170:
ldw 20(%r4),%r19
ldw 20(%r4),%r20
ldw 20(%r4),%r21
ldw 12(%r20),%r20
ldw 24(%r21),%r21
add %r20,%r21,%r20
ldw 20(%r4),%r21
ldw 24(%r21),%r22
uaddcm %r0,%r22,%r21
and %r20,%r21,%r20
copy %r20,%r21
stw %r21,12(%r19)
ldw 20(%r4),%r19
ldw 20(%r4),%r20
ldw 12(%r19),%r19
ldw 4(%r20),%r20
sub %r19,%r20,%r19
ldw 20(%r4),%r20
ldw 20(%r4),%r21
ldw 16(%r20),%r20
ldw 4(%r21),%r21
sub %r20,%r21,%r20
comclr,> %r19,%r20,%r0
bl L$0171,%r0
nop
ldw 20(%r4),%r19
ldw 20(%r4),%r20
ldw 16(%r20),%r21
stw %r21,12(%r19)
copy %r21,%r19
bl,n L$0172,%r0
L$0171:
copy %r0,%r19
L$0172:
ldw 20(%r4),%r19
ldw 20(%r4),%r20
ldw 12(%r20),%r21
stw %r21,8(%r19)
ldw 24(%r4),%r19
stw %r19,196(%r12)
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 196(%r19),%r26
copy %r0,%r25
copy %r11,%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl memset,%r2
nop
L$0167:
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldo -8(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
ldw 0(%r20),%r21
zdep %r21,29,30,%r20
ldw 196(%r19),%r19
add %r20,%r19,%r10
ldw 0(%r10),%r9
comiclr,= 0,%r9,%r0
bl L$0173,%r0
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
addi,uv -26,%r20,%r0
blr,n %r20,%r0
b,n L$0175
L$0202:
b L$0176
nop
b L$0177
nop
b L$0179
nop
b L$0180
nop
b L$0181
nop
b L$0182
nop
b L$0183
nop
b L$0184
nop
b L$0185
nop
b L$0186
nop
b L$0187
nop
b L$0189
nop
b L$0190
nop
b L$0191
nop
b L$0192
nop
b L$0193
nop
b L$0194
nop
b L$0195
nop
b L$0196
nop
b L$0198
nop
b L$0199
nop
b L$0200
nop
b L$0201
nop
b L$0178
nop
b L$0188
nop
b L$0197
nop
L$0175:
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldil L'LC$0023,%r26
ldo R'LC$0023(%r26),%r26
ldw 0(%r19),%r25
.CALL ARGW0=GR,ARGW1=GR
bl error,%r2
nop
bl,n L$0174,%r0
L$0176:
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
stw %r20,-52(%r30)
ldo 9(%r0),%r26
ldo 1(%r0),%r25
copy %r0,%r24
ldil L'LC$0024,%r23
ldo R'LC$0024(%r23),%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl init_type,%r2
nop
copy %r28,%r9
bl,n L$0174,%r0
L$0177:
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
stw %r20,-52(%r30)
ldo 7(%r0),%r26
ldo 4(%r0),%r25
ldo 1(%r0),%r24
ldil L'LC$0025,%r23
ldo R'LC$0025(%r23),%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl init_type,%r2
nop
copy %r28,%r9
bl,n L$0174,%r0
L$0178:
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
stw %r20,-52(%r30)
ldo 12(%r0),%r26
ldo 1(%r0),%r25
copy %r0,%r24
ldil L'LC$0026,%r23
ldo R'LC$0026(%r23),%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl init_type,%r2
nop
copy %r28,%r9
bl,n L$0174,%r0
L$0179:
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
stw %r20,-52(%r30)
ldo 7(%r0),%r26
ldo 1(%r0),%r25
copy %r0,%r24
ldil L'LC$0027,%r23
ldo R'LC$0027(%r23),%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl init_type,%r2
nop
copy %r28,%r9
bl,n L$0174,%r0
L$0180:
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
stw %r20,-52(%r30)
ldo 7(%r0),%r26
ldo 1(%r0),%r25
ldo 2(%r0),%r24
ldil L'LC$0028,%r23
ldo R'LC$0028(%r23),%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl init_type,%r2
nop
copy %r28,%r9
bl,n L$0174,%r0
L$0181:
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
stw %r20,-52(%r30)
ldo 7(%r0),%r26
ldo 1(%r0),%r25
ldo 1(%r0),%r24
ldil L'LC$0029,%r23
ldo R'LC$0029(%r23),%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl init_type,%r2
nop
copy %r28,%r9
bl,n L$0174,%r0
L$0182:
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
stw %r20,-52(%r30)
ldo 7(%r0),%r26
ldo 2(%r0),%r25
copy %r0,%r24
ldil L'LC$0030,%r23
ldo R'LC$0030(%r23),%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl init_type,%r2
nop
copy %r28,%r9
bl,n L$0174,%r0
L$0183:
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
stw %r20,-52(%r30)
ldo 7(%r0),%r26
ldo 2(%r0),%r25
ldo 2(%r0),%r24
ldil L'LC$0030,%r23
ldo R'LC$0030(%r23),%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl init_type,%r2
nop
copy %r28,%r9
bl,n L$0174,%r0
L$0184:
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
stw %r20,-52(%r30)
ldo 7(%r0),%r26
ldo 2(%r0),%r25
ldo 1(%r0),%r24
ldil L'LC$0031,%r23
ldo R'LC$0031(%r23),%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl init_type,%r2
nop
copy %r28,%r9
bl,n L$0174,%r0
L$0185:
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
stw %r20,-52(%r30)
ldo 7(%r0),%r26
ldo 4(%r0),%r25
copy %r0,%r24
ldil L'LC$0032,%r23
ldo R'LC$0032(%r23),%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl init_type,%r2
nop
copy %r28,%r9
bl,n L$0174,%r0
L$0186:
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
stw %r20,-52(%r30)
ldo 7(%r0),%r26
ldo 4(%r0),%r25
ldo 2(%r0),%r24
ldil L'LC$0032,%r23
ldo R'LC$0032(%r23),%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl init_type,%r2
nop
copy %r28,%r9
bl,n L$0174,%r0
L$0187:
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
stw %r20,-52(%r30)
ldo 7(%r0),%r26
ldo 4(%r0),%r25
ldo 1(%r0),%r24
ldil L'LC$0033,%r23
ldo R'LC$0033(%r23),%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl init_type,%r2
nop
copy %r28,%r9
bl,n L$0174,%r0
L$0188:
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
stw %r20,-52(%r30)
ldo 7(%r0),%r26
ldo 4(%r0),%r25
copy %r0,%r24
ldil L'LC$0034,%r23
ldo R'LC$0034(%r23),%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl init_type,%r2
nop
copy %r28,%r9
bl,n L$0174,%r0
L$0189:
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
stw %r20,-52(%r30)
ldo 7(%r0),%r26
ldo 4(%r0),%r25
copy %r0,%r24
ldil L'LC$0035,%r23
ldo R'LC$0035(%r23),%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl init_type,%r2
nop
copy %r28,%r9
bl,n L$0174,%r0
L$0190:
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
stw %r20,-52(%r30)
ldo 7(%r0),%r26
ldo 4(%r0),%r25
ldo 2(%r0),%r24
ldil L'LC$0035,%r23
ldo R'LC$0035(%r23),%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl init_type,%r2
nop
copy %r28,%r9
bl,n L$0174,%r0
L$0191:
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
stw %r20,-52(%r30)
ldo 7(%r0),%r26
ldo 4(%r0),%r25
ldo 1(%r0),%r24
ldil L'LC$0036,%r23
ldo R'LC$0036(%r23),%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl init_type,%r2
nop
copy %r28,%r9
bl,n L$0174,%r0
L$0192:
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
stw %r20,-52(%r30)
ldo 7(%r0),%r26
ldo 8(%r0),%r25
copy %r0,%r24
ldil L'LC$0037,%r23
ldo R'LC$0037(%r23),%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl init_type,%r2
nop
copy %r28,%r9
bl,n L$0174,%r0
L$0193:
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
stw %r20,-52(%r30)
ldo 7(%r0),%r26
ldo 8(%r0),%r25
ldo 2(%r0),%r24
ldil L'LC$0038,%r23
ldo R'LC$0038(%r23),%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl init_type,%r2
nop
copy %r28,%r9
bl,n L$0174,%r0
L$0194:
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
stw %r20,-52(%r30)
ldo 7(%r0),%r26
ldo 8(%r0),%r25
ldo 1(%r0),%r24
ldil L'LC$0039,%r23
ldo R'LC$0039(%r23),%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl init_type,%r2
nop
copy %r28,%r9
bl,n L$0174,%r0
L$0195:
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
stw %r20,-52(%r30)
ldo 8(%r0),%r26
ldo 4(%r0),%r25
copy %r0,%r24
ldil L'LC$0040,%r23
ldo R'LC$0040(%r23),%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl init_type,%r2
nop
copy %r28,%r9
bl,n L$0174,%r0
L$0196:
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
stw %r20,-52(%r30)
ldo 8(%r0),%r26
ldo 8(%r0),%r25
copy %r0,%r24
ldil L'LC$0041,%r23
ldo R'LC$0041(%r23),%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl init_type,%r2
nop
copy %r28,%r9
bl,n L$0174,%r0
L$0197:
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
stw %r20,-52(%r30)
ldo 8(%r0),%r26
ldo 8(%r0),%r25
copy %r0,%r24
ldil L'LC$0042,%r23
ldo R'LC$0042(%r23),%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl init_type,%r2
nop
copy %r28,%r9
bl,n L$0174,%r0
L$0198:
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
stw %r20,-52(%r30)
ldo 8(%r0),%r26
ldo 16(%r0),%r25
copy %r0,%r24
ldil L'LC$0043,%r23
ldo R'LC$0043(%r23),%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl init_type,%r2
nop
copy %r28,%r9
bl,n L$0174,%r0
L$0199:
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
stw %r20,-52(%r30)
ldo 8(%r0),%r26
ldo 8(%r0),%r25
copy %r0,%r24
ldil L'LC$0044,%r23
ldo R'LC$0044(%r23),%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl init_type,%r2
nop
copy %r28,%r9
bl,n L$0174,%r0
L$0200:
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
stw %r20,-52(%r30)
ldo 8(%r0),%r26
ldo 16(%r0),%r25
copy %r0,%r24
ldil L'LC$0045,%r23
ldo R'LC$0045(%r23),%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl init_type,%r2
nop
copy %r28,%r9
bl,n L$0174,%r0
L$0201:
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
stw %r20,-52(%r30)
ldo 8(%r0),%r26
ldo 16(%r0),%r25
copy %r0,%r24
ldil L'LC$0046,%r23
ldo R'LC$0046(%r23),%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl init_type,%r2
nop
copy %r28,%r9
bl,n L$0174,%r0
L$0174:
stw %r9,0(%r10)
L$0173:
L$0166:
copy %r9,%r28
bl,n L$0163,%r0
L$0163:
ldw 32(%r4),%r12
ldw 36(%r4),%r11
ldw 40(%r4),%r10
ldw 44(%r4),%r9
ldw 48(%r4),%r8
ldw 52(%r4),%r7
ldw 56(%r4),%r6
ldw 60(%r4),%r5
ldo 8(%r4),%r30
ldw -28(%r30),%r2
bv %r0(%r2)
ldwm -8(%r30),%r4
.EXIT
.PROCEND
.IMPORT puts_filtered,CODE
.align 4
LC$0047:
.STRING " \x00"
.IMPORT printf_filtered,CODE
.align 4
LC$0048:
.STRING "1\x00"
.align 4
LC$0049:
.STRING "0\x00"
.align 4
print_bit_vector:
.PROC
.CALLINFO FRAME=128,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(%r30)
copy %r4,%r1
copy %r30,%r4
stwm %r1,128(%r30)
stw %r8,16(%r4)
stw %r7,20(%r4)
stw %r6,24(%r4)
stw %r5,28(%r4)
ldo -4(%r0),%r5
ldo -32(%r4),%r19
add %r19,%r5,%r6
stw %r26,0(%r6)
ldo -8(%r0),%r7
ldo -32(%r4),%r19
add %r19,%r7,%r8
stw %r25,0(%r8)
stw %r0,8(%r4)
L$0204:
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 8(%r4),%r20
ldw 0(%r19),%r19
comclr,< %r20,%r19,%r0
bl L$0205,%r0
nop
ldw 8(%r4),%r19
ldw 8(%r4),%r20
comiclr,> 0,%r19,%r0
bl L$0208,%r0
nop
ldo 7(%r19),%r19
L$0208:
extrs %r19,28,29,%r19
zdep %r19,28,29,%r21
sub %r20,%r21,%r19
comiclr,= 0,%r19,%r0
bl L$0207,%r0
nop
ldil L'LC$0047,%r26
ldo R'LC$0047(%r26),%r26
.CALL ARGW0=GR
bl puts_filtered,%r2
nop
L$0207:
ldw 8(%r4),%r20
extrs %r20,28,29,%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
ldw 0(%r20),%r21
add %r19,%r21,%r20
ldb 0(%r20),%r19
ldw 8(%r4),%r20
extru %r20,31,3,%r21
subi,>>= 31,%r21,%r20
copy %r0,%r20
mtsar %r20
vextrs %r19,32,%r19
extru %r19,31,1,%r20
comiclr,<> 0,%r20,%r0
bl L$0209,%r0
nop
ldil L'LC$0048,%r26
ldo R'LC$0048(%r26),%r26
.CALL ARGW0=GR
bl printf_filtered,%r2
nop
bl,n L$0210,%r0
L$0209:
ldil L'LC$0049,%r26
ldo R'LC$0049(%r26),%r26
.CALL ARGW0=GR
bl printf_filtered,%r2
nop
L$0210:
L$0206:
ldw 8(%r4),%r19
ldo 1(%r19),%r20
stw %r20,8(%r4)
bl,n L$0204,%r0
L$0205:
L$0203:
ldw 16(%r4),%r8
ldw 20(%r4),%r7
ldw 24(%r4),%r6
ldw 28(%r4),%r5
ldo 8(%r4),%r30
ldw -28(%r30),%r2
bv %r0(%r2)
ldwm -8(%r30),%r4
.EXIT
.PROCEND
.IMPORT recursive_dump_type,CODE
.align 4
print_arg_types:
.PROC
.CALLINFO FRAME=128,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(%r30)
copy %r4,%r1
copy %r30,%r4
stwm %r1,128(%r30)
stw %r8,8(%r4)
stw %r7,12(%r4)
stw %r6,16(%r4)
stw %r5,20(%r4)
ldo -4(%r0),%r5
ldo -32(%r4),%r19
add %r19,%r5,%r6
stw %r26,0(%r6)
ldo -8(%r0),%r7
ldo -32(%r4),%r19
add %r19,%r7,%r8
stw %r25,0(%r8)
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
comiclr,<> 0,%r20,%r0
bl L$0212,%r0
nop
L$0213:
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 0(%r19),%r20
comiclr,<> 0,%r20,%r0
bl L$0214,%r0
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldo -8(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
ldw 0(%r20),%r21
ldo 2(%r21),%r20
ldw 0(%r19),%r26
copy %r20,%r25
.CALL ARGW0=GR,ARGW1=GR
bl recursive_dump_type,%r2
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
ldo 4(%r20),%r21
stw %r21,0(%r19)
ldw 0(%r20),%r19
ldw 0(%r19),%r20
comiclr,= 9,%r20,%r0
bl L$0215,%r0
nop
bl,n L$0214,%r0
L$0215:
bl,n L$0213,%r0
L$0214:
L$0212:
L$0211:
ldw 8(%r4),%r8
ldw 12(%r4),%r7
ldw 16(%r4),%r6
ldw 20(%r4),%r5
ldo 8(%r4),%r30
ldw -28(%r30),%r2
bv %r0(%r2)
ldwm -8(%r30),%r4
.EXIT
.PROCEND
.IMPORT printfi_filtered,CODE
.align 4
LC$0050:
.STRING "fn_fieldlists 0x%x\x0a\x00"
.align 4
LC$0051:
.STRING "[%d] name '%s' (0x%x) length %d\x0a\x00"
.align 4
LC$0052:
.STRING "[%d] physname '%s' (0x%x)\x0a\x00"
.align 4
LC$0053:
.STRING "type 0x%x\x0a\x00"
.align 4
LC$0054:
.STRING "args 0x%x\x0a\x00"
.align 4
LC$0055:
.STRING "fcontext 0x%x\x0a\x00"
.align 4
LC$0056:
.STRING "is_const %d\x0a\x00"
.align 4
LC$0057:
.STRING "is_volatile %d\x0a\x00"
.align 4
LC$0058:
.STRING "is_private %d\x0a\x00"
.align 4
LC$0059:
.STRING "is_protected %d\x0a\x00"
.align 4
LC$0060:
.STRING "is_stub %d\x0a\x00"
.align 4
LC$0061:
.STRING "voffset %u\x0a\x00"
.align 4
dump_fn_fieldlists:
.PROC
.CALLINFO FRAME=192,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(%r30)
copy %r4,%r1
copy %r30,%r4
stwm %r1,192(%r30)
stw %r8,24(%r4)
stw %r7,28(%r4)
stw %r6,32(%r4)
stw %r5,36(%r4)
ldo -4(%r0),%r5
ldo -32(%r4),%r19
add %r19,%r5,%r6
stw %r26,0(%r6)
ldo -8(%r0),%r7
ldo -32(%r4),%r19
add %r19,%r7,%r8
stw %r25,0(%r8)
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
ldw 0(%r20),%r21
ldw 48(%r21),%r20
ldw 0(%r19),%r26
ldil L'LC$0050,%r25
ldo R'LC$0050(%r25),%r25
ldw 20(%r20),%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl printfi_filtered,%r2
nop
stw %r0,8(%r4)
L$0217:
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 48(%r19),%r20
ldh 2(%r20),%r21
extrs %r21,31,16,%r19
ldw 8(%r4),%r20
comclr,< %r20,%r19,%r0
bl L$0218,%r0
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
ldw 48(%r20),%r19
ldw 8(%r4),%r21
zdep %r21,30,31,%r20
add %r20,%r21,%r20
zdep %r20,29,30,%r20
ldw 20(%r19),%r21
add %r20,%r21,%r19
ldw 8(%r19),%r20
stw %r20,16(%r4)
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
ldo 2(%r20),%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
ldw 0(%r20),%r21
ldw 48(%r21),%r20
ldw 8(%r4),%r22
zdep %r22,30,31,%r21
add %r21,%r22,%r21
zdep %r21,29,30,%r21
ldw 20(%r20),%r22
add %r21,%r22,%r20
ldo -4(%r0),%r21
ldo -32(%r4),%r22
add %r22,%r21,%r21
ldw 0(%r21),%r22
ldw 48(%r22),%r21
ldw 8(%r4),%r23
zdep %r23,30,31,%r22
add %r22,%r23,%r22
zdep %r22,29,30,%r22
ldw 20(%r21),%r23
add %r22,%r23,%r21
ldw 0(%r21),%r22
stw %r22,-52(%r30)
ldo -4(%r0),%r21
ldo -32(%r4),%r22
add %r22,%r21,%r21
ldw 0(%r21),%r22
ldw 48(%r22),%r21
ldw 8(%r4),%r23
zdep %r23,30,31,%r22
add %r22,%r23,%r22
zdep %r22,29,30,%r22
ldw 20(%r21),%r23
add %r22,%r23,%r21
ldw 4(%r21),%r22
stw %r22,-56(%r30)
copy %r19,%r26
ldil L'LC$0051,%r25
ldo R'LC$0051(%r25),%r25
ldw 8(%r4),%r24
ldw 0(%r20),%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl printfi_filtered,%r2
nop
stw %r0,12(%r4)
L$0220:
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
ldw 48(%r20),%r19
ldw 8(%r4),%r21
zdep %r21,30,31,%r20
add %r20,%r21,%r20
zdep %r20,29,30,%r20
ldw 20(%r19),%r21
add %r20,%r21,%r19
ldw 12(%r4),%r20
ldw 4(%r19),%r19
comclr,< %r20,%r19,%r0
bl L$0221,%r0
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
ldo 4(%r20),%r19
ldw 12(%r4),%r21
zdep %r21,29,30,%r20
add %r20,%r21,%r20
zdep %r20,29,30,%r20
ldw 16(%r4),%r21
add %r20,%r21,%r20
ldw 12(%r4),%r22
zdep %r22,29,30,%r21
add %r21,%r22,%r21
zdep %r21,29,30,%r21
ldw 16(%r4),%r22
add %r21,%r22,%r21
ldw 0(%r21),%r22
stw %r22,-52(%r30)
copy %r19,%r26
ldil L'LC$0052,%r25
ldo R'LC$0052(%r25),%r25
ldw 12(%r4),%r24
ldw 0(%r20),%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl printfi_filtered,%r2
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
ldo 8(%r20),%r19
ldw 12(%r4),%r21
zdep %r21,29,30,%r20
add %r20,%r21,%r20
zdep %r20,29,30,%r20
ldw 16(%r4),%r21
add %r20,%r21,%r20
copy %r19,%r26
ldil L'LC$0053,%r25
ldo R'LC$0053(%r25),%r25
ldw 4(%r20),%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl printfi_filtered,%r2
nop
ldw 12(%r4),%r20
zdep %r20,29,30,%r19
add %r19,%r20,%r19
zdep %r19,29,30,%r19
ldw 16(%r4),%r20
add %r19,%r20,%r19
ldo -8(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
ldw 0(%r20),%r21
ldo 10(%r21),%r20
ldw 4(%r19),%r26
copy %r20,%r25
.CALL ARGW0=GR,ARGW1=GR
bl recursive_dump_type,%r2
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
ldo 8(%r20),%r19
ldw 12(%r4),%r21
zdep %r21,29,30,%r20
add %r20,%r21,%r20
zdep %r20,29,30,%r20
ldw 16(%r4),%r22
add %r20,%r22,%r21
ldw 4(%r21),%r20
copy %r19,%r26
ldil L'LC$0054,%r25
ldo R'LC$0054(%r25),%r25
ldw 48(%r20),%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl printfi_filtered,%r2
nop
ldw 12(%r4),%r20
zdep %r20,29,30,%r19
add %r19,%r20,%r19
zdep %r19,29,30,%r19
ldw 16(%r4),%r21
add %r19,%r21,%r20
ldw 4(%r20),%r19
ldo -8(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
ldw 48(%r19),%r26
ldw 0(%r20),%r25
.CALL ARGW0=GR,ARGW1=GR
bl print_arg_types,%r2
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
ldo 8(%r20),%r19
ldw 12(%r4),%r21
zdep %r21,29,30,%r20
add %r20,%r21,%r20
zdep %r20,29,30,%r20
ldw 16(%r4),%r21
add %r20,%r21,%r20
copy %r19,%r26
ldil L'LC$0055,%r25
ldo R'LC$0055(%r25),%r25
ldw 12(%r20),%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl printfi_filtered,%r2
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
ldo 8(%r20),%r19
ldw 12(%r4),%r21
zdep %r21,29,30,%r20
add %r20,%r21,%r20
zdep %r20,29,30,%r20
ldw 16(%r4),%r21
add %r20,%r21,%r20
ldw 16(%r20),%r21
extru %r21,0+1-1,1,%r20
copy %r19,%r26
ldil L'LC$0056,%r25
ldo R'LC$0056(%r25),%r25
copy %r20,%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl printfi_filtered,%r2
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
ldo 8(%r20),%r19
ldw 12(%r4),%r21
zdep %r21,29,30,%r20
add %r20,%r21,%r20
zdep %r20,29,30,%r20
ldw 16(%r4),%r21
add %r20,%r21,%r20
ldw 16(%r20),%r21
extru %r21,1+1-1,1,%r20
copy %r19,%r26
ldil L'LC$0057,%r25
ldo R'LC$0057(%r25),%r25
copy %r20,%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl printfi_filtered,%r2
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
ldo 8(%r20),%r19
ldw 12(%r4),%r21
zdep %r21,29,30,%r20
add %r20,%r21,%r20
zdep %r20,29,30,%r20
ldw 16(%r4),%r21
add %r20,%r21,%r20
ldw 16(%r20),%r21
extru %r21,2+1-1,1,%r20
copy %r19,%r26
ldil L'LC$0058,%r25
ldo R'LC$0058(%r25),%r25
copy %r20,%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl printfi_filtered,%r2
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
ldo 8(%r20),%r19
ldw 12(%r4),%r21
zdep %r21,29,30,%r20
add %r20,%r21,%r20
zdep %r20,29,30,%r20
ldw 16(%r4),%r21
add %r20,%r21,%r20
ldw 16(%r20),%r21
extru %r21,3+1-1,1,%r20
copy %r19,%r26
ldil L'LC$0059,%r25
ldo R'LC$0059(%r25),%r25
copy %r20,%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl printfi_filtered,%r2
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
ldo 8(%r20),%r19
ldw 12(%r4),%r21
zdep %r21,29,30,%r20
add %r20,%r21,%r20
zdep %r20,29,30,%r20
ldw 16(%r4),%r21
add %r20,%r21,%r20
ldw 16(%r20),%r21
extru %r21,4+1-1,1,%r20
copy %r19,%r26
ldil L'LC$0060,%r25
ldo R'LC$0060(%r25),%r25
copy %r20,%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl printfi_filtered,%r2
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
ldo 8(%r20),%r19
ldw 12(%r4),%r21
zdep %r21,29,30,%r20
add %r20,%r21,%r20
zdep %r20,29,30,%r20
ldw 16(%r4),%r21
add %r20,%r21,%r20
ldw 16(%r20),%r21
extru %r21,8+24-1,24,%r22
ldo -2(%r22),%r20
copy %r19,%r26
ldil L'LC$0061,%r25
ldo R'LC$0061(%r25),%r25
copy %r20,%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl printfi_filtered,%r2
nop
L$0222:
ldw 12(%r4),%r19
ldo 1(%r19),%r20
stw %r20,12(%r4)
bl,n L$0220,%r0
L$0221:
L$0219:
ldw 8(%r4),%r19
ldo 1(%r19),%r20
stw %r20,8(%r4)
bl,n L$0217,%r0
L$0218:
L$0216:
ldw 24(%r4),%r8
ldw 28(%r4),%r7
ldw 32(%r4),%r6
ldw 36(%r4),%r5
ldo 8(%r4),%r30
ldw -28(%r30),%r2
bv %r0(%r2)
ldwm -8(%r30),%r4
.EXIT
.PROCEND
.align 4
LC$0062:
.STRING "n_baseclasses %d\x0a\x00"
.align 4
LC$0063:
.STRING "nfn_fields %d\x0a\x00"
.align 4
LC$0064:
.STRING "nfn_fields_total %d\x0a\x00"
.align 4
LC$0065:
.STRING "virtual_field_bits (%d bits at *0x%x)\x00"
.align 4
LC$0066:
.STRING "\x0a\x00"
.align 4
LC$0067:
.STRING "private_field_bits (%d bits at *0x%x)\x00"
.align 4
LC$0068:
.STRING "protected_field_bits (%d bits at *0x%x)\x00"
.align 4
print_cplus_stuff:
.PROC
.CALLINFO FRAME=128,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(%r30)
copy %r4,%r1
copy %r30,%r4
stwm %r1,128(%r30)
stw %r8,16(%r4)
stw %r7,20(%r4)
stw %r6,24(%r4)
stw %r5,28(%r4)
ldo -4(%r0),%r5
ldo -32(%r4),%r19
add %r19,%r5,%r6
stw %r26,0(%r6)
ldo -8(%r0),%r7
ldo -32(%r4),%r19
add %r19,%r7,%r8
stw %r25,0(%r8)
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r22
add %r22,%r20,%r21
ldw 0(%r21),%r20
ldw 48(%r20),%r21
ldh 0(%r21),%r22
extrs %r22,31,16,%r20
ldw 0(%r19),%r26
ldil L'LC$0062,%r25
ldo R'LC$0062(%r25),%r25
copy %r20,%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl printfi_filtered,%r2
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r22
add %r22,%r20,%r21
ldw 0(%r21),%r20
ldw 48(%r20),%r21
ldh 2(%r21),%r22
extrs %r22,31,16,%r20
ldw 0(%r19),%r26
ldil L'LC$0063,%r25
ldo R'LC$0063(%r25),%r25
copy %r20,%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl printfi_filtered,%r2
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
ldw 0(%r20),%r21
ldw 48(%r21),%r20
ldw 0(%r19),%r26
ldil L'LC$0064,%r25
ldo R'LC$0064(%r25),%r25
ldw 4(%r20),%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl printfi_filtered,%r2
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 48(%r19),%r20
ldh 0(%r20),%r21
extrs %r21,31,16,%r19
comiclr,< 0,%r19,%r0
bl L$0224,%r0
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r22
add %r22,%r20,%r21
ldw 0(%r21),%r20
ldw 48(%r20),%r21
ldh 0(%r21),%r22
extrs %r22,31,16,%r20
ldo -4(%r0),%r21
ldo -32(%r4),%r22
add %r22,%r21,%r21
ldw 0(%r21),%r22
ldw 48(%r22),%r21
ldw 0(%r19),%r26
ldil L'LC$0065,%r25
ldo R'LC$0065(%r25),%r25
copy %r20,%r24
ldw 8(%r21),%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl printfi_filtered,%r2
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
ldw 48(%r20),%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r22
add %r22,%r20,%r21
ldw 0(%r21),%r20
ldw 48(%r20),%r21
ldh 0(%r21),%r22
extrs %r22,31,16,%r20
ldw 8(%r19),%r26
copy %r20,%r25
.CALL ARGW0=GR,ARGW1=GR
bl print_bit_vector,%r2
nop
ldil L'LC$0066,%r26
ldo R'LC$0066(%r26),%r26
.CALL ARGW0=GR
bl puts_filtered,%r2
nop
L$0224:
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldh 34(%r19),%r20
extrs %r20,31,16,%r19
comiclr,< 0,%r19,%r0
bl L$0225,%r0
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 48(%r19),%r20
ldw 12(%r20),%r19
comiclr,<> 0,%r19,%r0
bl L$0226,%r0
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r22
add %r22,%r20,%r21
ldw 0(%r21),%r20
ldh 34(%r20),%r21
extrs %r21,31,16,%r20
ldo -4(%r0),%r21
ldo -32(%r4),%r22
add %r22,%r21,%r21
ldw 0(%r21),%r22
ldw 48(%r22),%r21
ldw 0(%r19),%r26
ldil L'LC$0067,%r25
ldo R'LC$0067(%r25),%r25
copy %r20,%r24
ldw 12(%r21),%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl printfi_filtered,%r2
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
ldw 48(%r20),%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r22
add %r22,%r20,%r21
ldw 0(%r21),%r20
ldh 34(%r20),%r21
extrs %r21,31,16,%r20
ldw 12(%r19),%r26
copy %r20,%r25
.CALL ARGW0=GR,ARGW1=GR
bl print_bit_vector,%r2
nop
ldil L'LC$0066,%r26
ldo R'LC$0066(%r26),%r26
.CALL ARGW0=GR
bl puts_filtered,%r2
nop
L$0226:
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 48(%r19),%r20
ldw 16(%r20),%r19
comiclr,<> 0,%r19,%r0
bl L$0227,%r0
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r22
add %r22,%r20,%r21
ldw 0(%r21),%r20
ldh 34(%r20),%r21
extrs %r21,31,16,%r20
ldo -4(%r0),%r21
ldo -32(%r4),%r22
add %r22,%r21,%r21
ldw 0(%r21),%r22
ldw 48(%r22),%r21
ldw 0(%r19),%r26
ldil L'LC$0068,%r25
ldo R'LC$0068(%r25),%r25
copy %r20,%r24
ldw 16(%r21),%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl printfi_filtered,%r2
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
ldw 48(%r20),%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r22
add %r22,%r20,%r21
ldw 0(%r21),%r20
ldh 34(%r20),%r21
extrs %r21,31,16,%r20
ldw 16(%r19),%r26
copy %r20,%r25
.CALL ARGW0=GR,ARGW1=GR
bl print_bit_vector,%r2
nop
ldil L'LC$0066,%r26
ldo R'LC$0066(%r26),%r26
.CALL ARGW0=GR
bl puts_filtered,%r2
nop
L$0227:
L$0225:
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 48(%r19),%r20
ldh 2(%r20),%r21
extrs %r21,31,16,%r19
comiclr,< 0,%r19,%r0
bl L$0228,%r0
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldo -8(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
ldw 0(%r19),%r26
ldw 0(%r20),%r25
.CALL ARGW0=GR,ARGW1=GR
bl dump_fn_fieldlists,%r2
nop
L$0228:
L$0223:
ldw 16(%r4),%r8
ldw 20(%r4),%r7
ldw 24(%r4),%r6
ldw 28(%r4),%r5
ldo 8(%r4),%r30
ldw -28(%r30),%r2
bv %r0(%r2)
ldwm -8(%r30),%r4
.EXIT
.PROCEND
.align 4
LC$0069:
.STRING "type node 0x%x\x0a\x00"
.align 4
LC$0070:
.STRING "name '%s' (0x%x)\x0a\x00"
.align 4
LC$0071:
.STRING "<NULL>\x00"
.align 4
LC$0072:
.STRING "code 0x%x \x00"
.align 4
LC$0073:
.STRING "(TYPE_CODE_UNDEF)\x00"
.align 4
LC$0074:
.STRING "(TYPE_CODE_PTR)\x00"
.align 4
LC$0075:
.STRING "(TYPE_CODE_ARRAY)\x00"
.align 4
LC$0076:
.STRING "(TYPE_CODE_STRUCT)\x00"
.align 4
LC$0077:
.STRING "(TYPE_CODE_UNION)\x00"
.align 4
LC$0078:
.STRING "(TYPE_CODE_ENUM)\x00"
.align 4
LC$0079:
.STRING "(TYPE_CODE_FUNC)\x00"
.align 4
LC$0080:
.STRING "(TYPE_CODE_INT)\x00"
.align 4
LC$0081:
.STRING "(TYPE_CODE_FLT)\x00"
.align 4
LC$0082:
.STRING "(TYPE_CODE_VOID)\x00"
.align 4
LC$0083:
.STRING "(TYPE_CODE_SET)\x00"
.align 4
LC$0084:
.STRING "(TYPE_CODE_RANGE)\x00"
.align 4
LC$0085:
.STRING "(TYPE_CODE_PASCAL_ARRAY)\x00"
.align 4
LC$0086:
.STRING "(TYPE_CODE_ERROR)\x00"
.align 4
LC$0087:
.STRING "(TYPE_CODE_MEMBER)\x00"
.align 4
LC$0088:
.STRING "(TYPE_CODE_METHOD)\x00"
.align 4
LC$0089:
.STRING "(TYPE_CODE_REF)\x00"
.align 4
LC$0090:
.STRING "(TYPE_CODE_CHAR)\x00"
.align 4
LC$0091:
.STRING "(TYPE_CODE_BOOL)\x00"
.align 4
LC$0092:
.STRING "(UNKNOWN TYPE CODE)\x00"
.align 4
LC$0093:
.STRING "length %d\x0a\x00"
.align 4
LC$0094:
.STRING "objfile 0x%x\x0a\x00"
.align 4
LC$0095:
.STRING "target_type 0x%x\x0a\x00"
.align 4
LC$0096:
.STRING "pointer_type 0x%x\x0a\x00"
.align 4
LC$0097:
.STRING "reference_type 0x%x\x0a\x00"
.align 4
LC$0098:
.STRING "function_type 0x%x\x0a\x00"
.align 4
LC$0099:
.STRING "flags 0x%x\x00"
.align 4
LC$0100:
.STRING " TYPE_FLAG_UNSIGNED\x00"
.align 4
LC$0101:
.STRING " TYPE_FLAG_SIGNED\x00"
.align 4
LC$0102:
.STRING " TYPE_FLAG_STUB\x00"
.align 4
LC$0103:
.STRING "nfields %d 0x%x\x0a\x00"
.align 4
LC$0104:
.STRING "[%d] bitpos %d bitsize %d type 0x%x name '%s' (0x%x)\x0a\x00"
.align 4
LC$0105:
.STRING "vptr_basetype 0x%x\x0a\x00"
.align 4
LC$0106:
.STRING "vptr_fieldno %d\x0a\x00"
.align 4
LC$0107:
.STRING "arg_types 0x%x\x0a\x00"
.align 4
LC$0108:
.STRING "cplus_stuff 0x%x\x0a\x00"
.align 4
LC$0109:
.STRING "type_specific 0x%x\x00"
.align 4
LC$0110:
.STRING " (unknown data form)\x00"
.align 4
.EXPORT recursive_dump_type,CODE
.EXPORT recursive_dump_type,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR
recursive_dump_type:
.PROC
.CALLINFO FRAME=128,CALLS,SAVE_RP
.ENTRY
stw %r2,-20(%r30)
copy %r4,%r1
copy %r30,%r4
stwm %r1,128(%r30)
stw %r8,16(%r4)
stw %r7,20(%r4)
stw %r6,24(%r4)
stw %r5,28(%r4)
ldo -4(%r0),%r5
ldo -32(%r4),%r19
add %r19,%r5,%r6
stw %r26,0(%r6)
ldo -8(%r0),%r7
ldo -32(%r4),%r19
add %r19,%r7,%r8
stw %r25,0(%r8)
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
ldw 0(%r19),%r26
ldil L'LC$0069,%r25
ldo R'LC$0069(%r25),%r25
ldw 0(%r20),%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl printfi_filtered,%r2
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r22
add %r22,%r20,%r21
ldw 0(%r21),%r20
ldo -4(%r0),%r21
ldo -32(%r4),%r22
add %r22,%r21,%r21
ldw 0(%r21),%r22
ldw 4(%r22),%r21
ldo -4(%r0),%r22
ldo -32(%r4),%r24
add %r24,%r22,%r23
ldw 0(%r23),%r22
ldw 4(%r22),%r23
comiclr,= 0,%r23,%r0
bl L$0230,%r0
nop
ldil L'LC$0071,%r21
ldo R'LC$0071(%r21),%r21
L$0230:
ldw 0(%r19),%r26
ldil L'LC$0070,%r25
ldo R'LC$0070(%r25),%r25
ldw 4(%r20),%r24
copy %r21,%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl printfi_filtered,%r2
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r22
add %r22,%r20,%r21
ldw 0(%r21),%r20
ldw 0(%r19),%r26
ldil L'LC$0072,%r25
ldo R'LC$0072(%r25),%r25
ldw 0(%r20),%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl printfi_filtered,%r2
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 0(%r19),%r20
addi,uv -19,%r20,%r0
blr,n %r20,%r0
b,n L$0251
L$0252:
b L$0232
nop
b L$0233
nop
b L$0234
nop
b L$0235
nop
b L$0236
nop
b L$0237
nop
b L$0238
nop
b L$0239
nop
b L$0240
nop
b L$0241
nop
b L$0242
nop
b L$0243
nop
b L$0244
nop
b L$0245
nop
b L$0246
nop
b L$0247
nop
b L$0248
nop
b L$0249
nop
b L$0250
nop
L$0232:
ldil L'LC$0073,%r26
ldo R'LC$0073(%r26),%r26
.CALL ARGW0=GR
bl printf_filtered,%r2
nop
bl,n L$0231,%r0
L$0233:
ldil L'LC$0074,%r26
ldo R'LC$0074(%r26),%r26
.CALL ARGW0=GR
bl printf_filtered,%r2
nop
bl,n L$0231,%r0
L$0234:
ldil L'LC$0075,%r26
ldo R'LC$0075(%r26),%r26
.CALL ARGW0=GR
bl printf_filtered,%r2
nop
bl,n L$0231,%r0
L$0235:
ldil L'LC$0076,%r26
ldo R'LC$0076(%r26),%r26
.CALL ARGW0=GR
bl printf_filtered,%r2
nop
bl,n L$0231,%r0
L$0236:
ldil L'LC$0077,%r26
ldo R'LC$0077(%r26),%r26
.CALL ARGW0=GR
bl printf_filtered,%r2
nop
bl,n L$0231,%r0
L$0237:
ldil L'LC$0078,%r26
ldo R'LC$0078(%r26),%r26
.CALL ARGW0=GR
bl printf_filtered,%r2
nop
bl,n L$0231,%r0
L$0238:
ldil L'LC$0079,%r26
ldo R'LC$0079(%r26),%r26
.CALL ARGW0=GR
bl printf_filtered,%r2
nop
bl,n L$0231,%r0
L$0239:
ldil L'LC$0080,%r26
ldo R'LC$0080(%r26),%r26
.CALL ARGW0=GR
bl printf_filtered,%r2
nop
bl,n L$0231,%r0
L$0240:
ldil L'LC$0081,%r26
ldo R'LC$0081(%r26),%r26
.CALL ARGW0=GR
bl printf_filtered,%r2
nop
bl,n L$0231,%r0
L$0241:
ldil L'LC$0082,%r26
ldo R'LC$0082(%r26),%r26
.CALL ARGW0=GR
bl printf_filtered,%r2
nop
bl,n L$0231,%r0
L$0242:
ldil L'LC$0083,%r26
ldo R'LC$0083(%r26),%r26
.CALL ARGW0=GR
bl printf_filtered,%r2
nop
bl,n L$0231,%r0
L$0243:
ldil L'LC$0084,%r26
ldo R'LC$0084(%r26),%r26
.CALL ARGW0=GR
bl printf_filtered,%r2
nop
bl,n L$0231,%r0
L$0244:
ldil L'LC$0085,%r26
ldo R'LC$0085(%r26),%r26
.CALL ARGW0=GR
bl printf_filtered,%r2
nop
bl,n L$0231,%r0
L$0245:
ldil L'LC$0086,%r26
ldo R'LC$0086(%r26),%r26
.CALL ARGW0=GR
bl printf_filtered,%r2
nop
bl,n L$0231,%r0
L$0246:
ldil L'LC$0087,%r26
ldo R'LC$0087(%r26),%r26
.CALL ARGW0=GR
bl printf_filtered,%r2
nop
bl,n L$0231,%r0
L$0247:
ldil L'LC$0088,%r26
ldo R'LC$0088(%r26),%r26
.CALL ARGW0=GR
bl printf_filtered,%r2
nop
bl,n L$0231,%r0
L$0248:
ldil L'LC$0089,%r26
ldo R'LC$0089(%r26),%r26
.CALL ARGW0=GR
bl printf_filtered,%r2
nop
bl,n L$0231,%r0
L$0249:
ldil L'LC$0090,%r26
ldo R'LC$0090(%r26),%r26
.CALL ARGW0=GR
bl printf_filtered,%r2
nop
bl,n L$0231,%r0
L$0250:
ldil L'LC$0091,%r26
ldo R'LC$0091(%r26),%r26
.CALL ARGW0=GR
bl printf_filtered,%r2
nop
bl,n L$0231,%r0
L$0251:
ldil L'LC$0092,%r26
ldo R'LC$0092(%r26),%r26
.CALL ARGW0=GR
bl printf_filtered,%r2
nop
bl,n L$0231,%r0
L$0231:
ldil L'LC$0066,%r26
ldo R'LC$0066(%r26),%r26
.CALL ARGW0=GR
bl puts_filtered,%r2
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r22
add %r22,%r20,%r21
ldw 0(%r21),%r20
ldw 0(%r19),%r26
ldil L'LC$0093,%r25
ldo R'LC$0093(%r25),%r25
ldw 8(%r20),%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl printfi_filtered,%r2
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r22
add %r22,%r20,%r21
ldw 0(%r21),%r20
ldw 0(%r19),%r26
ldil L'LC$0094,%r25
ldo R'LC$0094(%r25),%r25
ldw 12(%r20),%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl printfi_filtered,%r2
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r22
add %r22,%r20,%r21
ldw 0(%r21),%r20
ldw 0(%r19),%r26
ldil L'LC$0095,%r25
ldo R'LC$0095(%r25),%r25
ldw 16(%r20),%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl printfi_filtered,%r2
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 16(%r19),%r20
comiclr,<> 0,%r20,%r0
bl L$0253,%r0
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldo -8(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
ldw 0(%r20),%r21
ldo 2(%r21),%r20
ldw 16(%r19),%r26
copy %r20,%r25
.CALL ARGW0=GR,ARGW1=GR
bl recursive_dump_type,%r2
nop
L$0253:
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r22
add %r22,%r20,%r21
ldw 0(%r21),%r20
ldw 0(%r19),%r26
ldil L'LC$0096,%r25
ldo R'LC$0096(%r25),%r25
ldw 20(%r20),%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl printfi_filtered,%r2
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r22
add %r22,%r20,%r21
ldw 0(%r21),%r20
ldw 0(%r19),%r26
ldil L'LC$0097,%r25
ldo R'LC$0097(%r25),%r25
ldw 24(%r20),%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl printfi_filtered,%r2
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r22
add %r22,%r20,%r21
ldw 0(%r21),%r20
ldw 0(%r19),%r26
ldil L'LC$0098,%r25
ldo R'LC$0098(%r25),%r25
ldw 28(%r20),%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl printfi_filtered,%r2
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r22
add %r22,%r20,%r21
ldw 0(%r21),%r20
ldh 32(%r20),%r21
extrs %r21,31,16,%r20
ldw 0(%r19),%r26
ldil L'LC$0099,%r25
ldo R'LC$0099(%r25),%r25
copy %r20,%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl printfi_filtered,%r2
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldh 32(%r19),%r20
extru %r20,31,1,%r19
extrs %r19,31,16,%r20
comiclr,<> 0,%r20,%r0
bl L$0254,%r0
nop
ldil L'LC$0100,%r26
ldo R'LC$0100(%r26),%r26
.CALL ARGW0=GR
bl puts_filtered,%r2
nop
L$0254:
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldh 32(%r19),%r20
ldo 2(%r0),%r21
and %r20,%r21,%r19
extrs %r19,31,16,%r20
comiclr,<> 0,%r20,%r0
bl L$0255,%r0
nop
ldil L'LC$0101,%r26
ldo R'LC$0101(%r26),%r26
.CALL ARGW0=GR
bl puts_filtered,%r2
nop
L$0255:
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldh 32(%r19),%r20
ldo 4(%r0),%r21
and %r20,%r21,%r19
extrs %r19,31,16,%r20
comiclr,<> 0,%r20,%r0
bl L$0256,%r0
nop
ldil L'LC$0102,%r26
ldo R'LC$0102(%r26),%r26
.CALL ARGW0=GR
bl puts_filtered,%r2
nop
L$0256:
ldil L'LC$0066,%r26
ldo R'LC$0066(%r26),%r26
.CALL ARGW0=GR
bl puts_filtered,%r2
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r22
add %r22,%r20,%r21
ldw 0(%r21),%r20
ldh 34(%r20),%r21
extrs %r21,31,16,%r20
ldo -4(%r0),%r21
ldo -32(%r4),%r23
add %r23,%r21,%r22
ldw 0(%r22),%r21
ldw 0(%r19),%r26
ldil L'LC$0103,%r25
ldo R'LC$0103(%r25),%r25
copy %r20,%r24
ldw 36(%r21),%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl printfi_filtered,%r2
nop
stw %r0,8(%r4)
L$0257:
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldh 34(%r19),%r20
extrs %r20,31,16,%r19
ldw 8(%r4),%r20
comclr,< %r20,%r19,%r0
bl L$0258,%r0
nop
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
ldo 2(%r20),%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r22
add %r22,%r20,%r21
ldw 0(%r21),%r20
ldw 8(%r4),%r21
zdep %r21,27,28,%r22
ldw 36(%r20),%r21
add %r22,%r21,%r20
ldo -4(%r0),%r21
ldo -32(%r4),%r23
add %r23,%r21,%r22
ldw 0(%r22),%r21
ldw 8(%r4),%r22
zdep %r22,27,28,%r23
ldw 36(%r21),%r22
add %r23,%r22,%r21
ldw 4(%r21),%r22
stw %r22,-52(%r30)
ldo -4(%r0),%r21
ldo -32(%r4),%r23
add %r23,%r21,%r22
ldw 0(%r22),%r21
ldw 8(%r4),%r22
zdep %r22,27,28,%r23
ldw 36(%r21),%r22
add %r23,%r22,%r21
ldw 8(%r21),%r22
stw %r22,-56(%r30)
ldo -4(%r0),%r21
ldo -32(%r4),%r23
add %r23,%r21,%r22
ldw 0(%r22),%r21
ldw 8(%r4),%r22
zdep %r22,27,28,%r23
ldw 36(%r21),%r22
add %r23,%r22,%r21
ldw 12(%r21),%r22
stw %r22,-60(%r30)
ldo -4(%r0),%r21
ldo -32(%r4),%r23
add %r23,%r21,%r22
ldw 0(%r22),%r21
ldw 8(%r4),%r22
zdep %r22,27,28,%r23
ldw 36(%r21),%r22
add %r23,%r22,%r21
ldw 12(%r21),%r22
stw %r22,-64(%r30)
ldo -4(%r0),%r21
ldo -32(%r4),%r23
add %r23,%r21,%r22
ldw 0(%r22),%r21
ldw 8(%r4),%r22
zdep %r22,27,28,%r23
ldw 36(%r21),%r22
add %r23,%r22,%r21
ldw 12(%r21),%r22
comiclr,= 0,%r22,%r0
bl L$0260,%r0
nop
ldil L'LC$0071,%r21
ldo R'LC$0071(%r21),%r21
stw %r21,-64(%r30)
L$0260:
copy %r19,%r26
ldil L'LC$0104,%r25
ldo R'LC$0104(%r25),%r25
ldw 8(%r4),%r24
ldw 0(%r20),%r23
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR
bl printfi_filtered,%r2
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 8(%r4),%r20
zdep %r20,27,28,%r21
ldw 36(%r19),%r20
add %r21,%r20,%r19
ldw 8(%r19),%r20
comiclr,<> 0,%r20,%r0
bl L$0261,%r0
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 8(%r4),%r20
zdep %r20,27,28,%r21
ldw 36(%r19),%r20
add %r21,%r20,%r19
ldo -8(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
ldw 0(%r20),%r21
ldo 4(%r21),%r20
ldw 8(%r19),%r26
copy %r20,%r25
.CALL ARGW0=GR,ARGW1=GR
bl recursive_dump_type,%r2
nop
L$0261:
L$0259:
ldw 8(%r4),%r19
ldo 1(%r19),%r20
stw %r20,8(%r4)
bl,n L$0257,%r0
L$0258:
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r22
add %r22,%r20,%r21
ldw 0(%r21),%r20
ldw 0(%r19),%r26
ldil L'LC$0105,%r25
ldo R'LC$0105(%r25),%r25
ldw 40(%r20),%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl printfi_filtered,%r2
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 40(%r19),%r20
comiclr,<> 0,%r20,%r0
bl L$0262,%r0
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldo -8(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
ldw 0(%r20),%r21
ldo 2(%r21),%r20
ldw 40(%r19),%r26
copy %r20,%r25
.CALL ARGW0=GR,ARGW1=GR
bl recursive_dump_type,%r2
nop
L$0262:
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r22
add %r22,%r20,%r21
ldw 0(%r21),%r20
ldw 0(%r19),%r26
ldil L'LC$0106,%r25
ldo R'LC$0106(%r25),%r25
ldw 44(%r20),%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl printfi_filtered,%r2
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldw 0(%r19),%r20
ldw 0(%r20),%r19
comiclr,<> 6,%r19,%r0
bl L$0265,%r0
nop
comiclr,>= 6,%r19,%r0
bl L$0270,%r0
nop
comiclr,<> 3,%r19,%r0
bl L$0266,%r0
nop
bl,n L$0267,%r0
L$0270:
comiclr,<> 15,%r19,%r0
bl L$0264,%r0
nop
bl,n L$0267,%r0
L$0264:
L$0265:
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r22
add %r22,%r20,%r21
ldw 0(%r21),%r20
ldw 0(%r19),%r26
ldil L'LC$0107,%r25
ldo R'LC$0107(%r25),%r25
ldw 48(%r20),%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl printfi_filtered,%r2
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldo -8(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
ldw 48(%r19),%r26
ldw 0(%r20),%r25
.CALL ARGW0=GR,ARGW1=GR
bl print_arg_types,%r2
nop
bl,n L$0263,%r0
L$0266:
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r22
add %r22,%r20,%r21
ldw 0(%r21),%r20
ldw 0(%r19),%r26
ldil L'LC$0108,%r25
ldo R'LC$0108(%r25),%r25
ldw 48(%r20),%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl printfi_filtered,%r2
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldo -8(%r0),%r20
ldo -32(%r4),%r21
add %r21,%r20,%r20
ldw 0(%r19),%r26
ldw 0(%r20),%r25
.CALL ARGW0=GR,ARGW1=GR
bl print_cplus_stuff,%r2
nop
bl,n L$0263,%r0
L$0267:
ldo -8(%r0),%r19
ldo -32(%r4),%r20
add %r20,%r19,%r19
ldo -4(%r0),%r20
ldo -32(%r4),%r22
add %r22,%r20,%r21
ldw 0(%r21),%r20
ldw 0(%r19),%r26
ldil L'LC$0109,%r25
ldo R'LC$0109(%r25),%r25
ldw 48(%r20),%r24
.CALL ARGW0=GR,ARGW1=GR,ARGW2=GR
bl printfi_filtered,%r2
nop
ldo -4(%r0),%r19
ldo -32(%r4),%r21
add %r21,%r19,%r20
ldw 0(%r20),%r19
ldw 48(%r19),%r20
comiclr,<> 0,%r20,%r0
bl L$0268,%r0
nop
ldil L'LC$0110,%r26
ldo R'LC$0110(%r26),%r26
.CALL ARGW0=GR
bl printf_filtered,%r2
nop
L$0268:
ldil L'LC$0066,%r26
ldo R'LC$0066(%r26),%r26
.CALL ARGW0=GR
bl printf_filtered,%r2
nop
bl,n L$0263,%r0
L$0263:
L$0229:
ldw 16(%r4),%r8
ldw 20(%r4),%r7
ldw 24(%r4),%r6
ldw 28(%r4),%r5
ldo 8(%r4),%r30
ldw -28(%r30),%r2
bv %r0(%r2)
ldwm -8(%r30),%r4
.EXIT
.PROCEND
|
tactcomplabs/xbgas-binutils-gdb
| 24,561
|
gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s
|
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl .
! This file should contain every instruction valid on
! architecture sh4-nommu-nofpu but no more.
! If the tests are failing because the expected results have changed then run
! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl'
! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files.
! Make sure there are no unexpected or missing instructions.
.section .text
sh4_nommu_nofpu:
! Instructions introduced into sh4-nommu-nofpu
ldc r4,SGR ;!/* 0100nnnn00111010 ldc <REG_N>,SGR */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
ldc r4,DBR ;!/* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
ldc.l @r4+,SGR ;!/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up}
ldc.l @r4+,DBR ;!/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up}
movca.l R0,@r4 ;!/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up}
ocbi @r4 ;!/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up}
ocbp @r4 ;!/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up}
ocbwb @r4 ;!/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up}
stc SGR,r4 ;!/* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
stc DBR,r4 ;!/* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh3_nommu_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
|
tactcomplabs/xbgas-binutils-gdb
| 35,839
|
gas/testsuite/gas/sh/arch/sh-dsp.s
|
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl .
! This file should contain every instruction valid on
! architecture sh-dsp but no more.
! If the tests are failing because the expected results have changed then run
! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl'
! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files.
! Make sure there are no unexpected or missing instructions.
.section .text
sh_dsp:
! Instructions introduced into sh-dsp
ldc r4,MOD ;!/* 0100nnnn01011110 ldc <REG_N>,MOD */{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up}
ldc r4,RE ;!/* 0100nnnn01111110 ldc <REG_N>,RE */{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up}
ldc r4,RS ;!/* 0100nnnn01101110 ldc <REG_N>,RS */{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up}
ldc.l @r4+,MOD ;!/* 0100nnnn01010111 ldc.l @<REG_N>+,MOD */{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up}
ldc.l @r4+,RE ;!/* 0100nnnn01110111 ldc.l @<REG_N>+,RE */{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up}
ldc.l @r4+,RS ;!/* 0100nnnn01100111 ldc.l @<REG_N>+,RS */{"ldc.l",{A_INC_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_7}, arch_sh_dsp_up}
ldre @(8,PC) ;!/* 10001110i8p2.... ldre @(<disp>,PC) */{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up}
ldrs @(8,PC) ;!/* 10001100i8p2.... ldrs @(<disp>,PC) */{"ldrs",{A_DISP_PC},{HEX_8,HEX_C,PCRELIMM_8BY2}, arch_sh_dsp_up}
lds r4,DSR ;!/* 0100nnnn01101010 lds <REG_N>,DSR */{"lds",{A_REG_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}
lds r4,A0 ;!/* 0100nnnn01111010 lds <REG_N>,A0 */{"lds",{A_REG_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}
lds r4,X0 ;!/* 0100nnnn10001010 lds <REG_N>,X0 */{"lds",{A_REG_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}
lds r4,X1 ;!/* 0100nnnn10011010 lds <REG_N>,X1 */{"lds",{A_REG_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}
lds r4,Y0 ;!/* 0100nnnn10101010 lds <REG_N>,Y0 */{"lds",{A_REG_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}
lds r4,Y1 ;!/* 0100nnnn10111010 lds <REG_N>,Y1 */{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}
lds.l @r4+,DSR ;!/* 0100nnnn01100110 lds.l @<REG_N>+,DSR */{"lds.l",{A_INC_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_6}, arch_sh_dsp_up}
lds.l @r4+,A0 ;!/* 0100nnnn01110110 lds.l @<REG_N>+,A0 */{"lds.l",{A_INC_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_6}, arch_sh_dsp_up}
lds.l @r4+,X0 ;!/* 0100nnnn10000110 lds.l @<REG_N>+,X0 */{"lds.l",{A_INC_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_6}, arch_sh_dsp_up}
lds.l @r4+,X1 ;!/* 0100nnnn10010110 lds.l @<REG_N>+,X1 */{"lds.l",{A_INC_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_6}, arch_sh_dsp_up}
lds.l @r4+,Y0 ;!/* 0100nnnn10100110 lds.l @<REG_N>+,Y0 */{"lds.l",{A_INC_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_6}, arch_sh_dsp_up}
lds.l @r4+,Y1 ;!/* 0100nnnn10110110 lds.l @<REG_N>+,Y1 */{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up}
setrc r4 ;!/* 0100nnnn00010100 setrc <REG_N> */{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
stc MOD,r4 ;!/* 0000nnnn01010010 stc MOD,<REG_N> */{"stc",{A_MOD,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_2}, arch_sh_dsp_up}
stc RE,r4 ;!/* 0000nnnn01110010 stc RE,<REG_N> */{"stc",{A_RE,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}
stc RS,r4 ;!/* 0000nnnn01100010 stc RS,<REG_N> */{"stc",{A_RS,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}
stc.l MOD,@-r4 ;!/* 0100nnnn01010011 stc.l MOD,@-<REG_N> */{"stc.l",{A_MOD,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_3}, arch_sh_dsp_up}
stc.l RE,@-r4 ;!/* 0100nnnn01110011 stc.l RE,@-<REG_N> */{"stc.l",{A_RE,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}, arch_sh_dsp_up}
stc.l RS,@-r4 ;!/* 0100nnnn01100011 stc.l RS,@-<REG_N> */{"stc.l",{A_RS,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}, arch_sh_dsp_up}
sts DSR,r4 ;!/* 0000nnnn01101010 sts DSR,<REG_N> */{"sts",{A_DSR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}
sts A0,r4 ;!/* 0000nnnn01111010 sts A0,<REG_N> */{"sts",{A_A0,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}
sts X0,r4 ;!/* 0000nnnn10001010 sts X0,<REG_N> */{"sts",{A_X0,A_REG_N},{HEX_0,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}
sts X1,r4 ;!/* 0000nnnn10011010 sts X1,<REG_N> */{"sts",{A_X1,A_REG_N},{HEX_0,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}
sts Y0,r4 ;!/* 0000nnnn10101010 sts Y0,<REG_N> */{"sts",{A_Y0,A_REG_N},{HEX_0,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}
sts Y1,r4 ;!/* 0000nnnn10111010 sts Y1,<REG_N> */{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}
sts.l DSR,@-r4 ;!/* 0100nnnn01100110 sts.l DSR,@-<REG_N> */{"sts.l",{A_DSR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}
sts.l A0,@-r4 ;!/* 0100nnnn01110110 sts.l A0,@-<REG_N> */{"sts.l",{A_A0,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}
sts.l X0,@-r4 ;!/* 0100nnnn10000110 sts.l X0,@-<REG_N> */{"sts.l",{A_X0,A_DEC_N},{HEX_4,REG_N,HEX_8,HEX_2}, arch_sh_dsp_up}
sts.l X1,@-r4 ;!/* 0100nnnn10010110 sts.l X1,@-<REG_N> */{"sts.l",{A_X1,A_DEC_N},{HEX_4,REG_N,HEX_9,HEX_2}, arch_sh_dsp_up}
sts.l Y0,@-r4 ;!/* 0100nnnn10100110 sts.l Y0,@-<REG_N> */{"sts.l",{A_Y0,A_DEC_N},{HEX_4,REG_N,HEX_A,HEX_2}, arch_sh_dsp_up}
sts.l Y1,@-r4 ;!/* 0100nnnn10110110 sts.l Y1,@-<REG_N> */{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up}
movs.w @-r4,a1 ;!/* 111101nnmmmm0000 movs.w @-<REG_N>,<DSP_REG_M> */ {"movs.w",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_0}, arch_sh_dsp_up}
movs.w @r4,a1 ;!/* 111101nnmmmm0001 movs.w @<REG_N>,<DSP_REG_M> */ {"movs.w",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_4}, arch_sh_dsp_up}
movs.w @r4+,a1 ;!/* 111101nnmmmm0010 movs.w @<REG_N>+,<DSP_REG_M> */ {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up}
movs.w @r4+r8,a1 ;!/* 111101nnmmmm0011 movs.w @<REG_N>+r8,<DSP_REG_M> */ {"movs.w",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up}
movs.w a1,@-r4 ;!/* 111101nnmmmm0100 movs.w <DSP_REG_M>,@-<REG_N> */ {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up}
movs.w a1,@r4 ;!/* 111101nnmmmm0101 movs.w <DSP_REG_M>,@<REG_N> */ {"movs.w",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_5}, arch_sh_dsp_up}
movs.w a1,@r4+ ;!/* 111101nnmmmm0110 movs.w <DSP_REG_M>,@<REG_N>+ */ {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up}
movs.w a1,@r4+r8 ;!/* 111101nnmmmm0111 movs.w <DSP_REG_M>,@<REG_N>+r8 */ {"movs.w",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up}
movs.l @-r4,a1 ;!/* 111101nnmmmm1000 movs.l @-<REG_N>,<DSP_REG_M> */ {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up}
movs.l @r4,a1 ;!/* 111101nnmmmm1001 movs.l @<REG_N>,<DSP_REG_M> */ {"movs.l",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_6}, arch_sh_dsp_up}
movs.l @r4+,a1 ;!/* 111101nnmmmm1010 movs.l @<REG_N>+,<DSP_REG_M> */ {"movs.l",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_A}, arch_sh_dsp_up}
movs.l @r4+r8,a1 ;!/* 111101nnmmmm1011 movs.l @<REG_N>+r8,<DSP_REG_M> */ {"movs.l",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up}
movs.l a1,@-r4 ;!/* 111101nnmmmm1100 movs.l <DSP_REG_M>,@-<REG_N> */ {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up}
movs.l a1,@r4 ;!/* 111101nnmmmm1101 movs.l <DSP_REG_M>,@<REG_N> */ {"movs.l",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_7}, arch_sh_dsp_up}
movs.l a1,@r4+ ;!/* 111101nnmmmm1110 movs.l <DSP_REG_M>,@<REG_N>+ */ {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up}
movs.l a1,@r4+r8 ;!/* 111101nnmmmm1111 movs.l <DSP_REG_M>,@<REG_N>+r8 */ {"movs.l",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up}
nopx ;!/* 0*0*0*00** nopx */ {"nopx",{0},{PPI,NOPX}, arch_sh_dsp_up}
nopy ;!/* *0*0*0**00 nopy */ {"nopy",{0},{PPI,NOPY}, arch_sh_dsp_up}
movx.w @r4,x1 ;!/* n*m*0*01** movx.w @<REG_N>,<DSP_REG_X> */ {"movx.w",{AX_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up}
movx.w @r4+,x1 ;!/* n*m*0*10** movx.w @<REG_N>+,<DSP_REG_X> */ {"movx.w",{AX_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up}
movx.w @r4+r8,x1 ;!/* n*m*0*11** movx.w @<REG_N>+r8,<DSP_REG_X> */ {"movx.w",{AX_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up}
movx.w a1,@r4 ;!/* n*m*1*01** movx.w <DSP_REG_M>,@<REG_N> */ {"movx.w",{DSP_REG_A_M,AX_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up}
movx.w a1,@r4+ ;!/* n*m*1*10** movx.w <DSP_REG_M>,@<REG_N>+ */ {"movx.w",{DSP_REG_A_M,AX_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up}
movx.w a1,@r4+r8 ;!/* n*m*1*11** movx.w <DSP_REG_M>,@<REG_N>+r8 */ {"movx.w",{DSP_REG_A_M,AX_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up}
movy.w @r6,y0 ;!/* *n*m*0**01 movy.w @<REG_N>,<DSP_REG_Y> */ {"movy.w",{AY_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up}
movy.w @r6+,y0 ;!/* *n*m*0**10 movy.w @<REG_N>+,<DSP_REG_Y> */ {"movy.w",{AY_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up}
movy.w @r6+r9,y0 ;!/* *n*m*0**11 movy.w @<REG_N>+r9,<DSP_REG_Y> */ {"movy.w",{AY_PMOD_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up}
movy.w a1,@r6 ;!/* *n*m*1**01 movy.w <DSP_REG_M>,@<REG_N> */ {"movy.w",{DSP_REG_A_M,AY_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up}
movy.w a1,@r6+ ;!/* *n*m*1**10 movy.w <DSP_REG_M>,@<REG_N>+ */ {"movy.w",{DSP_REG_A_M,AY_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up}
movy.w a1,@r6+r9 ;!/* *n*m*1**11 movy.w <DSP_REG_M>,@<REG_N>+r9 */ {"movy.w",{DSP_REG_A_M,AY_PMOD_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up}
pmuls x0,y0,m0 ;!/* 01aaeeffxxyyggnn pmuls Se,Sf,Dg */ {"pmuls",{DSP_REG_E,DSP_REG_F,DSP_REG_G},{PPI,PMUL}, arch_sh_dsp_up}
psubc x1,y0,m0 ;!/* 10100000xxyynnnn psubc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"psubc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_0}, arch_sh_dsp_up}
paddc x1,y0,m0 ;!/* 10110000xxyynnnn paddc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"paddc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_0}, arch_sh_dsp_up}
pcmp x1,y0 ;!/* 10000100xxyynnnn pcmp <DSP_REG_X>,<DSP_REG_Y> */ {"pcmp", {DSP_REG_X,DSP_REG_Y},{PPI,PPI3,HEX_8,HEX_4}, arch_sh_dsp_up}
pwsb x1,y0,m0 ;!/* 10100100xxyynnnn pwsb <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pwsb", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_4}, arch_sh_dsp_up}
pwad x1,y0,m0 ;!/* 10110100xxyynnnn pwad <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up}
pabs x1,m0 ;!/* 10001000xxyynnnn pabs <DSP_REG_X>,<DSP_REG_N> */ {"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_8,HEX_8}, arch_sh_dsp_up}
pabs y0,m0 ;!/* 10101000xxyynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */ {"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_A,HEX_8}, arch_sh_dsp_up}
prnd x1,m0 ;!/* 10011000xxyynnnn prnd <DSP_REG_X>,<DSP_REG_N> */ {"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_9,HEX_8}, arch_sh_dsp_up}
prnd y0,m0 ;!/* 10111000xxyynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */ {"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_B,HEX_8}, arch_sh_dsp_up}
dct pshl x1,y0,m0 ;!/* 10000001xxyynnnn pshl <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pshl", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_1}, arch_sh_dsp_up}
pshl #4,m0 ;!/* 00000iiiiiiinnnn pshl #<imm>,<DSP_REG_N> */ {"pshl",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_0}, arch_sh_dsp_up}
dct psha x1,y0,m0 ;!/* 10010001xxyynnnn psha <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"psha", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_1}, arch_sh_dsp_up}
psha #4,m0 ;!/* 00010iiiiiiinnnn psha #<imm>,<DSP_REG_N> */ {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up}
dct psub x1,y0,m0 ;!/* 10100001xxyynnnn psub <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up}
dct padd x1,y0,m0 ;!/* 10110001xxyynnnn padd <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"padd", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_1}, arch_sh_dsp_up}
dct pand x1,y0,m0 ;!/* 10010101xxyynnnn pand <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pand", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_5}, arch_sh_dsp_up}
dct pxor x1,y0,m0 ;!/* 10100101xxyynnnn pxor <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pxor", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_5}, arch_sh_dsp_up}
dct por x1,y0,m0 ;!/* 10110101xxyynnnn por <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"por", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_5}, arch_sh_dsp_up}
dct pdec x1,m0 ;!/* 10001001xxyynnnn pdec <DSP_REG_X>,<DSP_REG_N> */ {"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up}
dct pdec y0,m0 ;!/* 10101001xxyynnnn pdec <DSP_REG_Y>,<DSP_REG_N> */ {"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up}
dct pinc x1,m0 ;!/* 10011001xx00nnnn pinc <DSP_REG_X>,<DSP_REG_N> */ {"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_XX00}, arch_sh_dsp_up}
dct pinc y0,m0 ;!/* 1011100100yynnnn pinc <DSP_REG_Y>,<DSP_REG_N> */ {"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_00YY}, arch_sh_dsp_up}
dct pclr m0 ;!/* 10001101xxyynnnn pclr <DSP_REG_N> */ {"pclr", {DSP_REG_N},{PPI,PPIC,HEX_8,HEX_D}, arch_sh_dsp_up}
dct pdmsb x1,m0 ;!/* 10011101xx00nnnn pdmsb <DSP_REG_X>,<DSP_REG_N> */ {"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_XX00}, arch_sh_dsp_up}
dct pdmsb y0,m0 ;!/* 1011110100yynnnn pdmsb <DSP_REG_Y>,<DSP_REG_N> */ {"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_00YY}, arch_sh_dsp_up}
dct pneg x1,m0 ;!/* 11001001xxyynnnn pneg <DSP_REG_X>,<DSP_REG_N> */ {"pneg", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up}
dct pneg y0,m0 ;!/* 11101001xxyynnnn pneg <DSP_REG_Y>,<DSP_REG_N> */ {"pneg", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_E,HEX_9}, arch_sh_dsp_up}
dct pcopy x1,m0 ;!/* 11011001xxyynnnn pcopy <DSP_REG_X>,<DSP_REG_N> */ {"pcopy", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_9}, arch_sh_dsp_up}
dct pcopy y0,m0 ;!/* 11111001xxyynnnn pcopy <DSP_REG_Y>,<DSP_REG_N> */ {"pcopy", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_F,HEX_9}, arch_sh_dsp_up}
dct psts MACH,m0 ;!/* 11001101xxyynnnn psts MACH,<DSP_REG_N> */ {"psts", {A_MACH,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_D}, arch_sh_dsp_up}
dct psts MACL,m0 ;!/* 11011101xxyynnnn psts MACL,<DSP_REG_N> */ {"psts", {A_MACL,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_D}, arch_sh_dsp_up}
dct plds m0,MACH ;!/* 11101101xxyynnnn plds <DSP_REG_N>,MACH */ {"plds", {DSP_REG_N,A_MACH},{PPI,PPIC,HEX_E,HEX_D}, arch_sh_dsp_up}
dct plds m0,MACL ;!/* 11111101xxyynnnn plds <DSP_REG_N>,MACL */ {"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up}
! Instructions inherited from ancestors: sh sh2
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
|
tactcomplabs/xbgas-binutils-gdb
| 28,125
|
gas/testsuite/gas/sh/arch/sh3e.s
|
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl .
! This file should contain every instruction valid on
! architecture sh3e but no more.
! If the tests are failing because the expected results have changed then run
! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl'
! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files.
! Make sure there are no unexpected or missing instructions.
.section .text
sh3e:
! Instructions introduced into sh3e
! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh3_nommu_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds r4,FPUL ;!/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up}
lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
lds.l @r5+,FPUL ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up}
lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts FPUL,r4 ;!/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up}
sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sts.l FPUL,@-r4 ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up}
sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
fabs fr1 ;!/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}
fadd fr2,fr1 ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}
fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}
fdiv fr2,fr1 ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}
fldi0 fr1 ;!/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up}
fldi1 fr1 ;!/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up}
flds fr1,FPUL ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}
float FPUL,fr1 ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}
fmac FR0,fr2,fr1 ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}
fmov fr2,fr1 ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}
fmov @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
fmov fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
fmov @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
fmov fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
fmov @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
fmov fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
fmov.s @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
fmov.s fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
fmov.s @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
fmov.s fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
fmov.s @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
fmov.s fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
fmul fr2,fr1 ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}
fneg fr1 ;!/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}
fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
fsts FPUL,fr1 ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}
fsub fr2,fr1 ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}
ftrc fr1,FPUL ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}
|
tactcomplabs/xbgas-binutils-gdb
| 25,376
|
gas/testsuite/gas/sh/arch/sh2e.s
|
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl .
! This file should contain every instruction valid on
! architecture sh2e but no more.
! If the tests are failing because the expected results have changed then run
! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl'
! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files.
! Make sure there are no unexpected or missing instructions.
.section .text
sh2e:
! Instructions introduced into sh2e
lds r4,FPUL ;!/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up}
lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
lds.l @r5+,FPUL ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up}
lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
sts FPUL,r4 ;!/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up}
sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
sts.l FPUL,@-r4 ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up}
sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
fabs fr1 ;!/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}
fadd fr2,fr1 ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}
fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}
fdiv fr2,fr1 ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}
fldi0 fr1 ;!/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up}
fldi1 fr1 ;!/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up}
flds fr1,FPUL ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}
float FPUL,fr1 ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}
fmac FR0,fr2,fr1 ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}
fmov fr2,fr1 ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}
fmov @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
fmov fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
fmov @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
fmov fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
fmov @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
fmov fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
fmov.s @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
fmov.s fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
fmov.s @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
fmov.s fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
fmov.s @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
fmov.s fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
fmul fr2,fr1 ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}
fneg fr1 ;!/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}
fsts FPUL,fr1 ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}
fsub fr2,fr1 ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}
ftrc fr1,FPUL ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}
! Instructions inherited from ancestors: sh sh2
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
|
tactcomplabs/xbgas-binutils-gdb
| 20,277
|
gas/testsuite/gas/sh/arch/sh2.s
|
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl .
! This file should contain every instruction valid on
! architecture sh2 but no more.
! If the tests are failing because the expected results have changed then run
! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl'
! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files.
! Make sure there are no unexpected or missing instructions.
.section .text
sh2:
! Instructions introduced into sh2
bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
! Instructions inherited from ancestors: sh
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
|
tactcomplabs/xbgas-binutils-gdb
| 29,623
|
gas/testsuite/gas/sh/arch/sh2a-nofpu.s
|
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl .
! This file should contain every instruction valid on
! architecture sh2a-nofpu but no more.
! If the tests are failing because the expected results have changed then run
! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl'
! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files.
! Make sure there are no unexpected or missing instructions.
.section .text
sh2a_nofpu:
! Instructions introduced into sh2a-nofpu
ldc r5,TBR ;!/* 0100mmmm01001010 ldc <REG_M>,TBR */{"ldc",{A_REG_M,A_TBR},{HEX_4,REG_M,HEX_4,HEX_A}, arch_sh2a_nofpu_up}
mov.b R0,@r4+ ;!/* 0100nnnn10001011 mov.b R0,@<REG_N>+ */{"mov.b",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_8,HEX_B}, arch_sh2a_nofpu_up}
mov.b @-r5,R0 ;!/* 0100nnnn11001011 mov.b @-<REG_M>,R0 */{"mov.b",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_C,HEX_B}, arch_sh2a_nofpu_up}
mov.b r5,@(2048,r4) ;!/* 0011nnnnmmmm0001 0000dddddddddddd mov.b <REG_M>,@(<DISP12>,<REG_N>) */ {"mov.b",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
mov.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 0100dddddddddddd mov.b @(<DISP12>,<REG_M>),<REG_N> */ {"mov.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_4,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
mov.l R0,@r4+ ;!/* 0100nnnn10101011 mov.l R0,@<REG_N>+ */{"mov.l",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_A,HEX_B}, arch_sh2a_nofpu_up}
mov.l @-r5,R0 ;!/* 0100nnnn11001011 mov.l @-<REG_M>,R0 */{"mov.l",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_B}, arch_sh2a_nofpu_up}
mov.l r5,@(2048,r4) ;!/* 0011nnnnmmmm0001 0010dddddddddddd mov.l <REG_M>,@(<DISP12>,<REG_N>) */ {"mov.l",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_2,DISP1_12BY4}, arch_sh2a_nofpu_up | arch_op32}
mov.l @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 0110dddddddddddd mov.l @(<DISP12>,<REG_M>),<REG_N> */ {"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_6,DISP0_12BY4}, arch_sh2a_nofpu_up | arch_op32}
mov.w R0,@r4+ ;!/* 0100nnnn10011011 mov.w R0,@<REG_N>+ */{"mov.w",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_9,HEX_B}, arch_sh2a_nofpu_up}
mov.w @-r5,R0 ;!/* 0100nnnn11011011 mov.w @-<REG_M>,R0 */{"mov.w",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_D,HEX_B}, arch_sh2a_nofpu_up}
mov.w r5,@(2048,r4) ;!/* 0011nnnnmmmm0001 0001dddddddddddd mov.w <REG_M>,@(<DISP12>,<REG_N>) */ {"mov.w",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_1,DISP1_12BY2}, arch_sh2a_nofpu_up | arch_op32}
mov.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 0101dddddddddddd mov.w @(<DISP12>,<REG_M>),<REG_N> */ {"mov.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_5,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
stc TBR,r4 ;!/* 0000nnnn01001010 stc TBR,<REG_N> */ {"stc",{A_TBR,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_A}, arch_sh2a_nofpu_up}
bclr #4, r4 ;!/* 10000110nnnn0iii bclr #<imm>, <REG_N> */ {"bclr",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3c}, arch_sh2a_nofpu_up}
bclr.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0000dddddddddddd bclr.b #<imm>,@(<DISP12>,<REG_N>) */ {"bclr.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
bld #4, r4 ;!/* 10000111nnnn1iii bld #<imm>, <REG_N> */ {"bld",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3s}, arch_sh2a_nofpu_up}
bld.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0011dddddddddddd bld.b #<imm>,@(<DISP12>,<REG_N>) */ {"bld.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_3,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
bset #4, r4 ;!/* 10000110nnnn1iii bset #<imm>, <REG_N> */ {"bset",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3s}, arch_sh2a_nofpu_up}
bset.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0001dddddddddddd bset.b #<imm>,@(<DISP12>,<REG_N>) */ {"bset.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_1,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
bst #4, r4 ;!/* 10000111nnnn0iii bst #<imm>, <REG_N> */ {"bst",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3c}, arch_sh2a_nofpu_up}
bst.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0010dddddddddddd bst.b #<imm>,@(<DISP12>,<REG_N>) */ {"bst.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_2,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
clips.b r4 ;!/* 0100nnnn10010001 clips.b <REG_N> */ {"clips.b",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_1}, arch_sh2a_nofpu_up}
clips.w r4 ;!/* 0100nnnn10010101 clips.w <REG_N> */ {"clips.w",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_5}, arch_sh2a_nofpu_up}
clipu.b r4 ;!/* 0100nnnn10000001 clipu.b <REG_N> */ {"clipu.b",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_1}, arch_sh2a_nofpu_up}
clipu.w r4 ;!/* 0100nnnn10000101 clipu.w <REG_N> */ {"clipu.w",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_5}, arch_sh2a_nofpu_up}
divs R0,r4 ;!/* 0100nnnn10010100 divs R0,<REG_N> */ {"divs",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_9,HEX_4}, arch_sh2a_nofpu_up}
divu R0,r4 ;!/* 0100nnnn10000100 divu R0,<REG_N> */ {"divu",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_4}, arch_sh2a_nofpu_up}
jsr/n @r5 ;!/* 0100mmmm01001011 jsr/n @<REG_M> */ {"jsr/n",{A_IND_M},{HEX_4,REG_M,HEX_4,HEX_B}, arch_sh2a_nofpu_up}
jsr/n @@(8,TBR) ;!/* 10000011dddddddd jsr/n @@(<disp>,TBR) */ {"jsr/n",{A_DISP2_TBR},{HEX_8,HEX_3,IMM0_8BY4}, arch_sh2a_nofpu_up}
ldbank @r5,R0 ;!/* 0100mmmm11100101 ldbank @<REG_M>,R0 */ {"ldbank",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_5}, arch_sh2a_nofpu_up}
movml.l r5,@-R15 ;!/* 0100mmmm11110001 movml.l <REG_M>,@-R15 */ {"movml.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_1}, arch_sh2a_nofpu_up}
movml.l @R15+,r5 ;!/* 0100mmmm11110101 movml.l @R15+,<REG_M> */ {"movml.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_5}, arch_sh2a_nofpu_up}
movml.l r5,@-R15 ;!/* 0100mmmm11110000 movml.l <REG_M>,@-R15 */ {"movmu.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_0}, arch_sh2a_nofpu_up}
movml.l @R15+,r5 ;!/* 0100mmmm11110100 movml.l @R15+,<REG_M> */ {"movmu.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_4}, arch_sh2a_nofpu_up}
movrt r4 ;!/* 0000nnnn00111001 movrt <REG_N> */ {"movrt",{A_REG_N},{HEX_0,REG_N,HEX_3,HEX_9}, arch_sh2a_nofpu_up}
mulr R0,r4 ;!/* 0100nnnn10000000 mulr R0,<REG_N> */ {"mulr",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_0}, arch_sh2a_nofpu_up}
nott ;!/* 0000000001101000 nott */ {"nott",{A_END},{HEX_0,HEX_0,HEX_6,HEX_8}, arch_sh2a_nofpu_up}
resbank ;!/* 0000000001011011 resbank */ {"resbank",{A_END},{HEX_0,HEX_0,HEX_5,HEX_B}, arch_sh2a_nofpu_up}
rts/n ;!/* 0000000001101011 rts/n */ {"rts/n",{A_END},{HEX_0,HEX_0,HEX_6,HEX_B}, arch_sh2a_nofpu_up}
rtv/n r5 ;!/* 0000mmmm01111011 rtv/n <REG_M>*/ {"rtv/n",{A_REG_M},{HEX_0,REG_M,HEX_7,HEX_B}, arch_sh2a_nofpu_up}
stbank R0,@r4 ;!/* 0100nnnn11100001 stbank R0,@<REG_N>*/ {"stbank",{A_R0,A_IND_N},{HEX_4,REG_N,HEX_E,HEX_1}, arch_sh2a_nofpu_up}
band.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0100dddddddddddd band.b #<imm>,@(<DISP12>,<REG_N>) */ {"band.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_4,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
bandnot.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 1100dddddddddddd bandnot.b #<imm>,@(<DISP12>,<REG_N>) */ {"bandnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_C,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
bldnot.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 1011dddddddddddd bldnot.b #<imm>,@(<DISP12>,<REG_N>) */ {"bldnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_B,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
bor.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0101dddddddddddd bor.b #<imm>,@(<DISP12>,<REG_N>) */ {"bor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_5,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
bornot.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 1101dddddddddddd bornot.b #<imm>,@(<DISP12>,<REG_N>) */ {"bornot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_D,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
bxor.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0110dddddddddddd bxor.b #<imm>,@(<DISP12>,<REG_N>) */ {"bxor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_6,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
movi20 #4,r4 ;!/* 0000nnnniiii0000 iiiiiiiiiiiiiiii movi20 #<imm>,<REG_N> */ {"movi20",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_0,IMM0_20}, arch_sh2a_nofpu_up | arch_op32}
movi20s #1024,r4 ;!/* 0000nnnniiii0001 iiiiiiiiiiiiiiii movi20s #<imm>,<REG_N> */ {"movi20s",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_1,IMM0_20BY8}, arch_sh2a_nofpu_up | arch_op32}
movu.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
movu.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
|
tactcomplabs/xbgas-binutils-gdb
| 39,786
|
gas/testsuite/gas/sh/arch/sh2a.s
|
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl .
! This file should contain every instruction valid on
! architecture sh2a but no more.
! If the tests are failing because the expected results have changed then run
! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl'
! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files.
! Make sure there are no unexpected or missing instructions.
.section .text
sh2a:
! Instructions introduced into sh2a
fmov.d xd4,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.d <DX_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.d",{DX_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY8}, arch_sh2a_up | arch_op32}
fmov.d @(2048,r5),xd2 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.d @(<DISP12>,<REG_M>),<DX_REG_N> */ {"fmov.d",{A_DISP_REG_M,DX_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY8}, arch_sh2a_up | arch_op32}
fmov.s fr2,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32}
fmov.s @(2048,r5),fr1 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),<F_REG_N> */ {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32}
! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r5,TBR ;!/* 0100mmmm01001010 ldc <REG_M>,TBR */{"ldc",{A_REG_M,A_TBR},{HEX_4,REG_M,HEX_4,HEX_A}, arch_sh2a_nofpu_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds r4,FPUL ;!/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up}
lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
lds.l @r5+,FPUL ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up}
lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.b R0,@r4+ ;!/* 0100nnnn10001011 mov.b R0,@<REG_N>+ */{"mov.b",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_8,HEX_B}, arch_sh2a_nofpu_up}
mov.b @-r5,R0 ;!/* 0100nnnn11001011 mov.b @-<REG_M>,R0 */{"mov.b",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_C,HEX_B}, arch_sh2a_nofpu_up}
mov.b r5,@(2048,r4) ;!/* 0011nnnnmmmm0001 0000dddddddddddd mov.b <REG_M>,@(<DISP12>,<REG_N>) */ {"mov.b",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
mov.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 0100dddddddddddd mov.b @(<DISP12>,<REG_M>),<REG_N> */ {"mov.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_4,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.l R0,@r4+ ;!/* 0100nnnn10101011 mov.l R0,@<REG_N>+ */{"mov.l",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_A,HEX_B}, arch_sh2a_nofpu_up}
mov.l @-r5,R0 ;!/* 0100nnnn11001011 mov.l @-<REG_M>,R0 */{"mov.l",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_B}, arch_sh2a_nofpu_up}
mov.l r5,@(2048,r4) ;!/* 0011nnnnmmmm0001 0010dddddddddddd mov.l <REG_M>,@(<DISP12>,<REG_N>) */ {"mov.l",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_2,DISP1_12BY4}, arch_sh2a_nofpu_up | arch_op32}
mov.l @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 0110dddddddddddd mov.l @(<DISP12>,<REG_M>),<REG_N> */ {"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_6,DISP0_12BY4}, arch_sh2a_nofpu_up | arch_op32}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
mov.w R0,@r4+ ;!/* 0100nnnn10011011 mov.w R0,@<REG_N>+ */{"mov.w",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_9,HEX_B}, arch_sh2a_nofpu_up}
mov.w @-r5,R0 ;!/* 0100nnnn11011011 mov.w @-<REG_M>,R0 */{"mov.w",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_D,HEX_B}, arch_sh2a_nofpu_up}
mov.w r5,@(2048,r4) ;!/* 0011nnnnmmmm0001 0001dddddddddddd mov.w <REG_M>,@(<DISP12>,<REG_N>) */ {"mov.w",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_1,DISP1_12BY2}, arch_sh2a_nofpu_up | arch_op32}
mov.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 0101dddddddddddd mov.w @(<DISP12>,<REG_M>),<REG_N> */ {"mov.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_5,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc TBR,r4 ;!/* 0000nnnn01001010 stc TBR,<REG_N> */ {"stc",{A_TBR,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_A}, arch_sh2a_nofpu_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts FPUL,r4 ;!/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up}
sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sts.l FPUL,@-r4 ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up}
sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
fabs fr1 ;!/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}
fabs dr2 ;!/* 1111nnn001011101 fabs <D_REG_N> */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2a_or_sh4_up}
fadd fr2,fr1 ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}
fadd dr4,dr2 ;!/* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2a_or_sh4_up}
fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
fcmp/eq dr4,dr2 ;!/* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2a_or_sh4_up}
fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}
fcmp/gt dr4,dr2 ;!/* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2a_or_sh4_up}
fcnvds dr2,FPUL ;!/* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh2a_or_sh4_up}
fcnvsd FPUL,dr2 ;!/* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh2a_or_sh4_up}
fdiv fr2,fr1 ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}
fdiv dr4,dr2 ;!/* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2a_or_sh4_up}
fldi0 fr1 ;!/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up}
fldi1 fr1 ;!/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up}
flds fr1,FPUL ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}
float FPUL,fr1 ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}
float FPUL,dr2 ;!/* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2a_or_sh4_up}
fmac FR0,fr2,fr1 ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}
fmov fr2,fr1 ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}
fmov xd4,xd2 ;!/* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2a_or_sh4_up}
fmov @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
fmov @r5,xd2 ;!/* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}
fmov fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
fmov xd4,@r4 ;!/* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}
fmov @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
fmov @r5+,xd2 ;!/* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}
fmov fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
fmov xd4,@-r4 ;!/* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}
fmov @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
fmov @(R0,r5),xd2 ;!/* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}
fmov fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
fmov xd4,@(R0,r4) ;!/* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}
fmov.d @r5,xd2 ;!/* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}
fmov.d xd4,@r4 ;!/* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}
fmov.d @r5+,xd2 ;!/* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}
fmov.d xd4,@-r4 ;!/* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}
fmov.d @(R0,r5),xd2 ;!/* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}
fmov.d xd4,@(R0,r4) ;!/* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}
fmov.s @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
fmov.s fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
fmov.s @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
fmov.s fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
fmov.s @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
fmov.s fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
fmul fr2,fr1 ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}
fmul dr4,dr2 ;!/* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2a_or_sh4_up}
fneg fr1 ;!/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}
fneg dr2 ;!/* 1111nnn001001101 fneg <D_REG_N> */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2a_or_sh4_up}
fschg ;!/* 1111001111111101 fschg */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh2a_or_sh4_up}
fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
fsqrt dr2 ;!/* 1111nnn001101101 fsqrt <D_REG_N> */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh4_up}
fsts FPUL,fr1 ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}
fsub fr2,fr1 ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}
fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
ftrc fr1,FPUL ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}
ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
bclr #4, r4 ;!/* 10000110nnnn0iii bclr #<imm>, <REG_N> */ {"bclr",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3c}, arch_sh2a_nofpu_up}
bclr.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0000dddddddddddd bclr.b #<imm>,@(<DISP12>,<REG_N>) */ {"bclr.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
bld #4, r4 ;!/* 10000111nnnn1iii bld #<imm>, <REG_N> */ {"bld",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3s}, arch_sh2a_nofpu_up}
bld.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0011dddddddddddd bld.b #<imm>,@(<DISP12>,<REG_N>) */ {"bld.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_3,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
bset #4, r4 ;!/* 10000110nnnn1iii bset #<imm>, <REG_N> */ {"bset",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3s}, arch_sh2a_nofpu_up}
bset.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0001dddddddddddd bset.b #<imm>,@(<DISP12>,<REG_N>) */ {"bset.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_1,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
bst #4, r4 ;!/* 10000111nnnn0iii bst #<imm>, <REG_N> */ {"bst",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3c}, arch_sh2a_nofpu_up}
bst.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0010dddddddddddd bst.b #<imm>,@(<DISP12>,<REG_N>) */ {"bst.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_2,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
clips.b r4 ;!/* 0100nnnn10010001 clips.b <REG_N> */ {"clips.b",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_1}, arch_sh2a_nofpu_up}
clips.w r4 ;!/* 0100nnnn10010101 clips.w <REG_N> */ {"clips.w",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_5}, arch_sh2a_nofpu_up}
clipu.b r4 ;!/* 0100nnnn10000001 clipu.b <REG_N> */ {"clipu.b",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_1}, arch_sh2a_nofpu_up}
clipu.w r4 ;!/* 0100nnnn10000101 clipu.w <REG_N> */ {"clipu.w",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_5}, arch_sh2a_nofpu_up}
divs R0,r4 ;!/* 0100nnnn10010100 divs R0,<REG_N> */ {"divs",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_9,HEX_4}, arch_sh2a_nofpu_up}
divu R0,r4 ;!/* 0100nnnn10000100 divu R0,<REG_N> */ {"divu",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_4}, arch_sh2a_nofpu_up}
jsr/n @r5 ;!/* 0100mmmm01001011 jsr/n @<REG_M> */ {"jsr/n",{A_IND_M},{HEX_4,REG_M,HEX_4,HEX_B}, arch_sh2a_nofpu_up}
jsr/n @@(8,TBR) ;!/* 10000011dddddddd jsr/n @@(<disp>,TBR) */ {"jsr/n",{A_DISP2_TBR},{HEX_8,HEX_3,IMM0_8BY4}, arch_sh2a_nofpu_up}
ldbank @r5,R0 ;!/* 0100mmmm11100101 ldbank @<REG_M>,R0 */ {"ldbank",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_5}, arch_sh2a_nofpu_up}
movml.l r5,@-R15 ;!/* 0100mmmm11110001 movml.l <REG_M>,@-R15 */ {"movml.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_1}, arch_sh2a_nofpu_up}
movml.l @R15+,r5 ;!/* 0100mmmm11110101 movml.l @R15+,<REG_M> */ {"movml.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_5}, arch_sh2a_nofpu_up}
movml.l r5,@-R15 ;!/* 0100mmmm11110000 movml.l <REG_M>,@-R15 */ {"movmu.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_0}, arch_sh2a_nofpu_up}
movml.l @R15+,r5 ;!/* 0100mmmm11110100 movml.l @R15+,<REG_M> */ {"movmu.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_4}, arch_sh2a_nofpu_up}
movrt r4 ;!/* 0000nnnn00111001 movrt <REG_N> */ {"movrt",{A_REG_N},{HEX_0,REG_N,HEX_3,HEX_9}, arch_sh2a_nofpu_up}
mulr R0,r4 ;!/* 0100nnnn10000000 mulr R0,<REG_N> */ {"mulr",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_0}, arch_sh2a_nofpu_up}
nott ;!/* 0000000001101000 nott */ {"nott",{A_END},{HEX_0,HEX_0,HEX_6,HEX_8}, arch_sh2a_nofpu_up}
resbank ;!/* 0000000001011011 resbank */ {"resbank",{A_END},{HEX_0,HEX_0,HEX_5,HEX_B}, arch_sh2a_nofpu_up}
rts/n ;!/* 0000000001101011 rts/n */ {"rts/n",{A_END},{HEX_0,HEX_0,HEX_6,HEX_B}, arch_sh2a_nofpu_up}
rtv/n r5 ;!/* 0000mmmm01111011 rtv/n <REG_M>*/ {"rtv/n",{A_REG_M},{HEX_0,REG_M,HEX_7,HEX_B}, arch_sh2a_nofpu_up}
stbank R0,@r4 ;!/* 0100nnnn11100001 stbank R0,@<REG_N>*/ {"stbank",{A_R0,A_IND_N},{HEX_4,REG_N,HEX_E,HEX_1}, arch_sh2a_nofpu_up}
band.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0100dddddddddddd band.b #<imm>,@(<DISP12>,<REG_N>) */ {"band.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_4,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
bandnot.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 1100dddddddddddd bandnot.b #<imm>,@(<DISP12>,<REG_N>) */ {"bandnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_C,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
bldnot.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 1011dddddddddddd bldnot.b #<imm>,@(<DISP12>,<REG_N>) */ {"bldnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_B,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
bor.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0101dddddddddddd bor.b #<imm>,@(<DISP12>,<REG_N>) */ {"bor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_5,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
bornot.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 1101dddddddddddd bornot.b #<imm>,@(<DISP12>,<REG_N>) */ {"bornot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_D,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
bxor.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0110dddddddddddd bxor.b #<imm>,@(<DISP12>,<REG_N>) */ {"bxor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_6,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
movi20 #4,r4 ;!/* 0000nnnniiii0000 iiiiiiiiiiiiiiii movi20 #<imm>,<REG_N> */ {"movi20",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_0,IMM0_20}, arch_sh2a_nofpu_up | arch_op32}
movi20s #1024,r4 ;!/* 0000nnnniiii0001 iiiiiiiiiiiiiiii movi20s #<imm>,<REG_N> */ {"movi20s",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_1,IMM0_20BY8}, arch_sh2a_nofpu_up | arch_op32}
movu.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
movu.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
|
tactcomplabs/xbgas-binutils-gdb
| 20,848
|
gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
|
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl .
! This file should contain every instruction valid on
! architecture sh2a-nofpu-or-sh4-nommu-nofpu but no more.
! If the tests are failing because the expected results have changed then run
! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl'
! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files.
! Make sure there are no unexpected or missing instructions.
.section .text
sh2a_nofpu_or_sh4_nommu_nofpu:
! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu
! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
|
tactcomplabs/xbgas-binutils-gdb
| 24,687
|
gas/testsuite/gas/sh/arch/sh4-nofpu.s
|
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl .
! This file should contain every instruction valid on
! architecture sh4-nofpu but no more.
! If the tests are failing because the expected results have changed then run
! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl'
! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files.
! Make sure there are no unexpected or missing instructions.
.section .text
sh4_nofpu:
! Instructions introduced into sh4-nofpu
! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh3_nommu_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r4,SGR ;!/* 0100nnnn00111010 ldc <REG_N>,SGR */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
ldc r4,DBR ;!/* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
ldc.l @r4+,SGR ;!/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up}
ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,DBR ;!/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up}
ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movca.l R0,@r4 ;!/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
ocbi @r4 ;!/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up}
ocbp @r4 ;!/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up}
ocbwb @r4 ;!/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
stc SGR,r4 ;!/* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
stc DBR,r4 ;!/* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
|
tactcomplabs/xbgas-binutils-gdb
| 26,032
|
gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s
|
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl .
! This file should contain every instruction valid on
! architecture sh2a-or-sh3e but no more.
! If the tests are failing because the expected results have changed then run
! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl'
! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files.
! Make sure there are no unexpected or missing instructions.
.section .text
sh2a_or_sh3e:
! Instructions introduced into sh2a-or-sh3e
fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds r4,FPUL ;!/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up}
lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
lds.l @r5+,FPUL ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up}
lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts FPUL,r4 ;!/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up}
sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sts.l FPUL,@-r4 ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up}
sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
fabs fr1 ;!/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}
fadd fr2,fr1 ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}
fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}
fdiv fr2,fr1 ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}
fldi0 fr1 ;!/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up}
fldi1 fr1 ;!/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up}
flds fr1,FPUL ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}
float FPUL,fr1 ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}
fmac FR0,fr2,fr1 ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}
fmov fr2,fr1 ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}
fmov @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
fmov fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
fmov @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
fmov fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
fmov @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
fmov fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
fmov.s @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
fmov.s fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
fmov.s @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
fmov.s fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
fmov.s @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
fmov.s fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
fmul fr2,fr1 ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}
fneg fr1 ;!/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}
fsts FPUL,fr1 ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}
fsub fr2,fr1 ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}
ftrc fr1,FPUL ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}
|
tactcomplabs/xbgas-binutils-gdb
| 22,754
|
gas/testsuite/gas/sh/arch/sh3-nommu.s
|
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl .
! This file should contain every instruction valid on
! architecture sh3-nommu but no more.
! If the tests are failing because the expected results have changed then run
! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl'
! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files.
! Make sure there are no unexpected or missing instructions.
.section .text
sh3_nommu:
! Instructions introduced into sh3-nommu
clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh3_nommu_up}
ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
|
tactcomplabs/xbgas-binutils-gdb
| 22,870
|
gas/testsuite/gas/sh/arch/sh3.s
|
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl .
! This file should contain every instruction valid on
! architecture sh3 but no more.
! If the tests are failing because the expected results have changed then run
! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl'
! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files.
! Make sure there are no unexpected or missing instructions.
.section .text
sh3:
! Instructions introduced into sh3
ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh3_nommu_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
|
tactcomplabs/xbgas-binutils-gdb
| 20,806
|
gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s
|
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl .
! This file should contain every instruction valid on
! architecture sh2a-nofpu-or-sh3-nommu but no more.
! If the tests are failing because the expected results have changed then run
! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl'
! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files.
! Make sure there are no unexpected or missing instructions.
.section .text
sh2a_nofpu_or_sh3_nommu:
! Instructions introduced into sh2a-nofpu-or-sh3-nommu
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up}
shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
! Instructions inherited from ancestors: sh sh2
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
|
tactcomplabs/xbgas-binutils-gdb
| 25,681
|
gas/testsuite/gas/sh/arch/sh4a-nofpu.s
|
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl .
! This file should contain every instruction valid on
! architecture sh4a-nofpu but no more.
! If the tests are failing because the expected results have changed then run
! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl'
! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files.
! Make sure there are no unexpected or missing instructions.
.section .text
sh4a_nofpu:
! Instructions introduced into sh4a-nofpu
icbi @r4 ;!/* 0000nnnn11100011 icbi @<REG_N> */{"icbi",{A_IND_N},{HEX_0,REG_N,HEX_E,HEX_3}, arch_sh4a_nofpu_up}
movco.l r0,@r4 ;!/* 0000nnnn01110011 movco.l r0,@<REG_N> */{"movco.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_7,HEX_3}, arch_sh4a_nofpu_up}
movli.l @r5,r0 ;!/* 0000mmmm01100011 movli.l @<REG_M>,r0 */{"movli.l",{A_IND_M,A_R0},{HEX_0,REG_M,HEX_6,HEX_3}, arch_sh4a_nofpu_up}
movua.l @r5,r0 ;!/* 0100mmmm10101001 movua.l @<REG_M>,r0 */{"movua.l",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_A,HEX_9}, arch_sh4a_nofpu_up}
movua.l @r5+,r0 ;!/* 0100mmmm11101001 movua.l @<REG_M>+,r0 */{"movua.l",{A_INC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_9}, arch_sh4a_nofpu_up}
prefi @r4 ;!/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up}
synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up}
! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh3_nommu_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r4,SGR ;!/* 0100nnnn00111010 ldc <REG_N>,SGR */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
ldc r4,DBR ;!/* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
ldc.l @r4+,SGR ;!/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up}
ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,DBR ;!/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up}
ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movca.l R0,@r4 ;!/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
ocbi @r4 ;!/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up}
ocbp @r4 ;!/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up}
ocbwb @r4 ;!/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
stc SGR,r4 ;!/* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
stc DBR,r4 ;!/* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
|
tactcomplabs/xbgas-binutils-gdb
| 35,808
|
gas/testsuite/gas/sh/arch/sh4a.s
|
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl .
! This file should contain every instruction valid on
! architecture sh4a but no more.
! If the tests are failing because the expected results have changed then run
! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl'
! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files.
! Make sure there are no unexpected or missing instructions.
.section .text
sh4a:
! Instructions introduced into sh4a
fpchg ;!/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up}
! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh3_nommu_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
icbi @r4 ;!/* 0000nnnn11100011 icbi @<REG_N> */{"icbi",{A_IND_N},{HEX_0,REG_N,HEX_E,HEX_3}, arch_sh4a_nofpu_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r4,SGR ;!/* 0100nnnn00111010 ldc <REG_N>,SGR */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
ldc r4,DBR ;!/* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
ldc.l @r4+,SGR ;!/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up}
ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,DBR ;!/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up}
ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds r4,FPUL ;!/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up}
lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
lds.l @r5+,FPUL ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up}
lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movca.l R0,@r4 ;!/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up}
movco.l r0,@r4 ;!/* 0000nnnn01110011 movco.l r0,@<REG_N> */{"movco.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_7,HEX_3}, arch_sh4a_nofpu_up}
movli.l @r5,r0 ;!/* 0000mmmm01100011 movli.l @<REG_M>,r0 */{"movli.l",{A_IND_M,A_R0},{HEX_0,REG_M,HEX_6,HEX_3}, arch_sh4a_nofpu_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
movua.l @r5,r0 ;!/* 0100mmmm10101001 movua.l @<REG_M>,r0 */{"movua.l",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_A,HEX_9}, arch_sh4a_nofpu_up}
movua.l @r5+,r0 ;!/* 0100mmmm11101001 movua.l @<REG_M>+,r0 */{"movua.l",{A_INC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_9}, arch_sh4a_nofpu_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
ocbi @r4 ;!/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up}
ocbp @r4 ;!/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up}
ocbwb @r4 ;!/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up}
prefi @r4 ;!/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
stc SGR,r4 ;!/* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
stc DBR,r4 ;!/* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts FPUL,r4 ;!/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up}
sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sts.l FPUL,@-r4 ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up}
sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
fabs fr1 ;!/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}
fabs dr2 ;!/* 1111nnn001011101 fabs <D_REG_N> */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2a_or_sh4_up}
fadd fr2,fr1 ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}
fadd dr4,dr2 ;!/* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2a_or_sh4_up}
fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
fcmp/eq dr4,dr2 ;!/* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2a_or_sh4_up}
fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}
fcmp/gt dr4,dr2 ;!/* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2a_or_sh4_up}
fcnvds dr2,FPUL ;!/* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh2a_or_sh4_up}
fcnvsd FPUL,dr2 ;!/* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh2a_or_sh4_up}
fdiv fr2,fr1 ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}
fdiv dr4,dr2 ;!/* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2a_or_sh4_up}
fipr fv4,fv0 ;!/* 1111nnmm11101101 fipr <V_REG_M>,<V_REG_N>*/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up}
fldi0 fr1 ;!/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up}
fldi1 fr1 ;!/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up}
flds fr1,FPUL ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}
float FPUL,fr1 ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}
float FPUL,dr2 ;!/* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2a_or_sh4_up}
fmac FR0,fr2,fr1 ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}
fmov fr2,fr1 ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}
fmov xd4,xd2 ;!/* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2a_or_sh4_up}
fmov @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
fmov @r5,xd2 ;!/* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}
fmov fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
fmov xd4,@r4 ;!/* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}
fmov @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
fmov @r5+,xd2 ;!/* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}
fmov fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
fmov xd4,@-r4 ;!/* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}
fmov @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
fmov @(R0,r5),xd2 ;!/* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}
fmov fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
fmov xd4,@(R0,r4) ;!/* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}
fmov.d @r5,xd2 ;!/* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}
fmov.d xd4,@r4 ;!/* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}
fmov.d @r5+,xd2 ;!/* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}
fmov.d xd4,@-r4 ;!/* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}
fmov.d @(R0,r5),xd2 ;!/* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}
fmov.d xd4,@(R0,r4) ;!/* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}
fmov.s @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
fmov.s fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
fmov.s @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
fmov.s fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
fmov.s @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
fmov.s fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
fmul fr2,fr1 ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}
fmul dr4,dr2 ;!/* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2a_or_sh4_up}
fneg fr1 ;!/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}
fneg dr2 ;!/* 1111nnn001001101 fneg <D_REG_N> */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2a_or_sh4_up}
frchg ;!/* 1111101111111101 frchg */{"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}, arch_sh4_up}
fsca FPUL,dr2 ;!/* 1111nnn011111101 fsca FPUL,<D_REG_N> */{"fsca",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_F,HEX_D}, arch_sh4_up}
fschg ;!/* 1111001111111101 fschg */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh2a_or_sh4_up}
fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
fsqrt dr2 ;!/* 1111nnn001101101 fsqrt <D_REG_N> */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh4_up}
fsrra fr1 ;!/* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}
fsts FPUL,fr1 ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}
fsub fr2,fr1 ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}
fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
ftrc fr1,FPUL ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}
ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
ftrv xmtrx,fv0 ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}
|
tactcomplabs/xbgas-binutils-gdb
| 18,809
|
gas/testsuite/gas/sh/arch/sh.s
|
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl .
! This file should contain every instruction valid on
! architecture sh but no more.
! If the tests are failing because the expected results have changed then run
! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl'
! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files.
! Make sure there are no unexpected or missing instructions.
.section .text
sh:
! Instructions introduced into sh
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
! Instructions inherited from ancestors:
|
tactcomplabs/xbgas-binutils-gdb
| 38,442
|
gas/testsuite/gas/sh/arch/sh3-dsp.s
|
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl .
! This file should contain every instruction valid on
! architecture sh3-dsp but no more.
! If the tests are failing because the expected results have changed then run
! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl'
! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files.
! Make sure there are no unexpected or missing instructions.
.section .text
sh3_dsp:
! Instructions introduced into sh3-dsp
! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh3_nommu_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc r4,MOD ;!/* 0100nnnn01011110 ldc <REG_N>,MOD */{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up}
ldc r4,RE ;!/* 0100nnnn01111110 ldc <REG_N>,RE */{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up}
ldc r4,RS ;!/* 0100nnnn01101110 ldc <REG_N>,RS */{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up}
ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
ldc.l @r4+,MOD ;!/* 0100nnnn01010111 ldc.l @<REG_N>+,MOD */{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up}
ldc.l @r4+,RE ;!/* 0100nnnn01110111 ldc.l @<REG_N>+,RE */{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up}
ldc.l @r4+,RS ;!/* 0100nnnn01100111 ldc.l @<REG_N>+,RS */{"ldc.l",{A_INC_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_7}, arch_sh_dsp_up}
ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
ldre @(8,PC) ;!/* 10001110i8p2.... ldre @(<disp>,PC) */{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up}
ldrs @(8,PC) ;!/* 10001100i8p2.... ldrs @(<disp>,PC) */{"ldrs",{A_DISP_PC},{HEX_8,HEX_C,PCRELIMM_8BY2}, arch_sh_dsp_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds r4,DSR ;!/* 0100nnnn01101010 lds <REG_N>,DSR */{"lds",{A_REG_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}
lds r4,A0 ;!/* 0100nnnn01111010 lds <REG_N>,A0 */{"lds",{A_REG_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}
lds r4,X0 ;!/* 0100nnnn10001010 lds <REG_N>,X0 */{"lds",{A_REG_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}
lds r4,X1 ;!/* 0100nnnn10011010 lds <REG_N>,X1 */{"lds",{A_REG_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}
lds r4,Y0 ;!/* 0100nnnn10101010 lds <REG_N>,Y0 */{"lds",{A_REG_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}
lds r4,Y1 ;!/* 0100nnnn10111010 lds <REG_N>,Y1 */{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
lds.l @r4+,DSR ;!/* 0100nnnn01100110 lds.l @<REG_N>+,DSR */{"lds.l",{A_INC_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_6}, arch_sh_dsp_up}
lds.l @r4+,A0 ;!/* 0100nnnn01110110 lds.l @<REG_N>+,A0 */{"lds.l",{A_INC_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_6}, arch_sh_dsp_up}
lds.l @r4+,X0 ;!/* 0100nnnn10000110 lds.l @<REG_N>+,X0 */{"lds.l",{A_INC_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_6}, arch_sh_dsp_up}
lds.l @r4+,X1 ;!/* 0100nnnn10010110 lds.l @<REG_N>+,X1 */{"lds.l",{A_INC_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_6}, arch_sh_dsp_up}
lds.l @r4+,Y0 ;!/* 0100nnnn10100110 lds.l @<REG_N>+,Y0 */{"lds.l",{A_INC_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_6}, arch_sh_dsp_up}
lds.l @r4+,Y1 ;!/* 0100nnnn10110110 lds.l @<REG_N>+,Y1 */{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up}
ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
setrc r4 ;!/* 0100nnnn00010100 setrc <REG_N> */{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc MOD,r4 ;!/* 0000nnnn01010010 stc MOD,<REG_N> */{"stc",{A_MOD,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_2}, arch_sh_dsp_up}
stc RE,r4 ;!/* 0000nnnn01110010 stc RE,<REG_N> */{"stc",{A_RE,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}
stc RS,r4 ;!/* 0000nnnn01100010 stc RS,<REG_N> */{"stc",{A_RS,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}
stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l MOD,@-r4 ;!/* 0100nnnn01010011 stc.l MOD,@-<REG_N> */{"stc.l",{A_MOD,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_3}, arch_sh_dsp_up}
stc.l RE,@-r4 ;!/* 0100nnnn01110011 stc.l RE,@-<REG_N> */{"stc.l",{A_RE,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}, arch_sh_dsp_up}
stc.l RS,@-r4 ;!/* 0100nnnn01100011 stc.l RS,@-<REG_N> */{"stc.l",{A_RS,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}, arch_sh_dsp_up}
stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts DSR,r4 ;!/* 0000nnnn01101010 sts DSR,<REG_N> */{"sts",{A_DSR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}
sts A0,r4 ;!/* 0000nnnn01111010 sts A0,<REG_N> */{"sts",{A_A0,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}
sts X0,r4 ;!/* 0000nnnn10001010 sts X0,<REG_N> */{"sts",{A_X0,A_REG_N},{HEX_0,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}
sts X1,r4 ;!/* 0000nnnn10011010 sts X1,<REG_N> */{"sts",{A_X1,A_REG_N},{HEX_0,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}
sts Y0,r4 ;!/* 0000nnnn10101010 sts Y0,<REG_N> */{"sts",{A_Y0,A_REG_N},{HEX_0,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}
sts Y1,r4 ;!/* 0000nnnn10111010 sts Y1,<REG_N> */{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sts.l DSR,@-r4 ;!/* 0100nnnn01100110 sts.l DSR,@-<REG_N> */{"sts.l",{A_DSR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}
sts.l A0,@-r4 ;!/* 0100nnnn01110110 sts.l A0,@-<REG_N> */{"sts.l",{A_A0,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}
sts.l X0,@-r4 ;!/* 0100nnnn10000110 sts.l X0,@-<REG_N> */{"sts.l",{A_X0,A_DEC_N},{HEX_4,REG_N,HEX_8,HEX_2}, arch_sh_dsp_up}
sts.l X1,@-r4 ;!/* 0100nnnn10010110 sts.l X1,@-<REG_N> */{"sts.l",{A_X1,A_DEC_N},{HEX_4,REG_N,HEX_9,HEX_2}, arch_sh_dsp_up}
sts.l Y0,@-r4 ;!/* 0100nnnn10100110 sts.l Y0,@-<REG_N> */{"sts.l",{A_Y0,A_DEC_N},{HEX_4,REG_N,HEX_A,HEX_2}, arch_sh_dsp_up}
sts.l Y1,@-r4 ;!/* 0100nnnn10110110 sts.l Y1,@-<REG_N> */{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
movs.w @-r4,a1 ;!/* 111101nnmmmm0000 movs.w @-<REG_N>,<DSP_REG_M> */ {"movs.w",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_0}, arch_sh_dsp_up}
movs.w @r4,a1 ;!/* 111101nnmmmm0001 movs.w @<REG_N>,<DSP_REG_M> */ {"movs.w",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_4}, arch_sh_dsp_up}
movs.w @r4+,a1 ;!/* 111101nnmmmm0010 movs.w @<REG_N>+,<DSP_REG_M> */ {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up}
movs.w @r4+r8,a1 ;!/* 111101nnmmmm0011 movs.w @<REG_N>+r8,<DSP_REG_M> */ {"movs.w",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up}
movs.w a1,@-r4 ;!/* 111101nnmmmm0100 movs.w <DSP_REG_M>,@-<REG_N> */ {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up}
movs.w a1,@r4 ;!/* 111101nnmmmm0101 movs.w <DSP_REG_M>,@<REG_N> */ {"movs.w",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_5}, arch_sh_dsp_up}
movs.w a1,@r4+ ;!/* 111101nnmmmm0110 movs.w <DSP_REG_M>,@<REG_N>+ */ {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up}
movs.w a1,@r4+r8 ;!/* 111101nnmmmm0111 movs.w <DSP_REG_M>,@<REG_N>+r8 */ {"movs.w",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up}
movs.l @-r4,a1 ;!/* 111101nnmmmm1000 movs.l @-<REG_N>,<DSP_REG_M> */ {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up}
movs.l @r4,a1 ;!/* 111101nnmmmm1001 movs.l @<REG_N>,<DSP_REG_M> */ {"movs.l",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_6}, arch_sh_dsp_up}
movs.l @r4+,a1 ;!/* 111101nnmmmm1010 movs.l @<REG_N>+,<DSP_REG_M> */ {"movs.l",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_A}, arch_sh_dsp_up}
movs.l @r4+r8,a1 ;!/* 111101nnmmmm1011 movs.l @<REG_N>+r8,<DSP_REG_M> */ {"movs.l",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up}
movs.l a1,@-r4 ;!/* 111101nnmmmm1100 movs.l <DSP_REG_M>,@-<REG_N> */ {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up}
movs.l a1,@r4 ;!/* 111101nnmmmm1101 movs.l <DSP_REG_M>,@<REG_N> */ {"movs.l",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_7}, arch_sh_dsp_up}
movs.l a1,@r4+ ;!/* 111101nnmmmm1110 movs.l <DSP_REG_M>,@<REG_N>+ */ {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up}
movs.l a1,@r4+r8 ;!/* 111101nnmmmm1111 movs.l <DSP_REG_M>,@<REG_N>+r8 */ {"movs.l",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up}
nopx ;!/* 0*0*0*00** nopx */ {"nopx",{0},{PPI,NOPX}, arch_sh_dsp_up}
nopy ;!/* *0*0*0**00 nopy */ {"nopy",{0},{PPI,NOPY}, arch_sh_dsp_up}
movx.w @r4,x1 ;!/* n*m*0*01** movx.w @<REG_N>,<DSP_REG_X> */ {"movx.w",{AX_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up}
movx.w @r4+,x1 ;!/* n*m*0*10** movx.w @<REG_N>+,<DSP_REG_X> */ {"movx.w",{AX_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up}
movx.w @r4+r8,x1 ;!/* n*m*0*11** movx.w @<REG_N>+r8,<DSP_REG_X> */ {"movx.w",{AX_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up}
movx.w a1,@r4 ;!/* n*m*1*01** movx.w <DSP_REG_M>,@<REG_N> */ {"movx.w",{DSP_REG_A_M,AX_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up}
movx.w a1,@r4+ ;!/* n*m*1*10** movx.w <DSP_REG_M>,@<REG_N>+ */ {"movx.w",{DSP_REG_A_M,AX_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up}
movx.w a1,@r4+r8 ;!/* n*m*1*11** movx.w <DSP_REG_M>,@<REG_N>+r8 */ {"movx.w",{DSP_REG_A_M,AX_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up}
movy.w @r6,y0 ;!/* *n*m*0**01 movy.w @<REG_N>,<DSP_REG_Y> */ {"movy.w",{AY_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up}
movy.w @r6+,y0 ;!/* *n*m*0**10 movy.w @<REG_N>+,<DSP_REG_Y> */ {"movy.w",{AY_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up}
movy.w @r6+r9,y0 ;!/* *n*m*0**11 movy.w @<REG_N>+r9,<DSP_REG_Y> */ {"movy.w",{AY_PMOD_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up}
movy.w a1,@r6 ;!/* *n*m*1**01 movy.w <DSP_REG_M>,@<REG_N> */ {"movy.w",{DSP_REG_A_M,AY_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up}
movy.w a1,@r6+ ;!/* *n*m*1**10 movy.w <DSP_REG_M>,@<REG_N>+ */ {"movy.w",{DSP_REG_A_M,AY_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up}
movy.w a1,@r6+r9 ;!/* *n*m*1**11 movy.w <DSP_REG_M>,@<REG_N>+r9 */ {"movy.w",{DSP_REG_A_M,AY_PMOD_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up}
pmuls x0,y0,m0 ;!/* 01aaeeffxxyyggnn pmuls Se,Sf,Dg */ {"pmuls",{DSP_REG_E,DSP_REG_F,DSP_REG_G},{PPI,PMUL}, arch_sh_dsp_up}
psubc x1,y0,m0 ;!/* 10100000xxyynnnn psubc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"psubc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_0}, arch_sh_dsp_up}
paddc x1,y0,m0 ;!/* 10110000xxyynnnn paddc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"paddc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_0}, arch_sh_dsp_up}
pcmp x1,y0 ;!/* 10000100xxyynnnn pcmp <DSP_REG_X>,<DSP_REG_Y> */ {"pcmp", {DSP_REG_X,DSP_REG_Y},{PPI,PPI3,HEX_8,HEX_4}, arch_sh_dsp_up}
pwsb x1,y0,m0 ;!/* 10100100xxyynnnn pwsb <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pwsb", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_4}, arch_sh_dsp_up}
pwad x1,y0,m0 ;!/* 10110100xxyynnnn pwad <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up}
pabs x1,m0 ;!/* 10001000xxyynnnn pabs <DSP_REG_X>,<DSP_REG_N> */ {"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_8,HEX_8}, arch_sh_dsp_up}
pabs y0,m0 ;!/* 10101000xxyynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */ {"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_A,HEX_8}, arch_sh_dsp_up}
prnd x1,m0 ;!/* 10011000xxyynnnn prnd <DSP_REG_X>,<DSP_REG_N> */ {"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_9,HEX_8}, arch_sh_dsp_up}
prnd y0,m0 ;!/* 10111000xxyynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */ {"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_B,HEX_8}, arch_sh_dsp_up}
dct pshl x1,y0,m0 ;!/* 10000001xxyynnnn pshl <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pshl", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_1}, arch_sh_dsp_up}
pshl #4,m0 ;!/* 00000iiiiiiinnnn pshl #<imm>,<DSP_REG_N> */ {"pshl",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_0}, arch_sh_dsp_up}
dct psha x1,y0,m0 ;!/* 10010001xxyynnnn psha <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"psha", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_1}, arch_sh_dsp_up}
psha #4,m0 ;!/* 00010iiiiiiinnnn psha #<imm>,<DSP_REG_N> */ {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up}
dct psub x1,y0,m0 ;!/* 10100001xxyynnnn psub <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up}
dct padd x1,y0,m0 ;!/* 10110001xxyynnnn padd <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"padd", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_1}, arch_sh_dsp_up}
dct pand x1,y0,m0 ;!/* 10010101xxyynnnn pand <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pand", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_5}, arch_sh_dsp_up}
dct pxor x1,y0,m0 ;!/* 10100101xxyynnnn pxor <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pxor", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_5}, arch_sh_dsp_up}
dct por x1,y0,m0 ;!/* 10110101xxyynnnn por <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"por", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_5}, arch_sh_dsp_up}
dct pdec x1,m0 ;!/* 10001001xxyynnnn pdec <DSP_REG_X>,<DSP_REG_N> */ {"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up}
dct pdec y0,m0 ;!/* 10101001xxyynnnn pdec <DSP_REG_Y>,<DSP_REG_N> */ {"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up}
dct pinc x1,m0 ;!/* 10011001xx00nnnn pinc <DSP_REG_X>,<DSP_REG_N> */ {"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_XX00}, arch_sh_dsp_up}
dct pinc y0,m0 ;!/* 1011100100yynnnn pinc <DSP_REG_Y>,<DSP_REG_N> */ {"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_00YY}, arch_sh_dsp_up}
dct pclr m0 ;!/* 10001101xxyynnnn pclr <DSP_REG_N> */ {"pclr", {DSP_REG_N},{PPI,PPIC,HEX_8,HEX_D}, arch_sh_dsp_up}
dct pdmsb x1,m0 ;!/* 10011101xx00nnnn pdmsb <DSP_REG_X>,<DSP_REG_N> */ {"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_XX00}, arch_sh_dsp_up}
dct pdmsb y0,m0 ;!/* 1011110100yynnnn pdmsb <DSP_REG_Y>,<DSP_REG_N> */ {"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_00YY}, arch_sh_dsp_up}
dct pneg x1,m0 ;!/* 11001001xxyynnnn pneg <DSP_REG_X>,<DSP_REG_N> */ {"pneg", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up}
dct pneg y0,m0 ;!/* 11101001xxyynnnn pneg <DSP_REG_Y>,<DSP_REG_N> */ {"pneg", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_E,HEX_9}, arch_sh_dsp_up}
dct pcopy x1,m0 ;!/* 11011001xxyynnnn pcopy <DSP_REG_X>,<DSP_REG_N> */ {"pcopy", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_9}, arch_sh_dsp_up}
dct pcopy y0,m0 ;!/* 11111001xxyynnnn pcopy <DSP_REG_Y>,<DSP_REG_N> */ {"pcopy", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_F,HEX_9}, arch_sh_dsp_up}
dct psts MACH,m0 ;!/* 11001101xxyynnnn psts MACH,<DSP_REG_N> */ {"psts", {A_MACH,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_D}, arch_sh_dsp_up}
dct psts MACL,m0 ;!/* 11011101xxyynnnn psts MACL,<DSP_REG_N> */ {"psts", {A_MACL,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_D}, arch_sh_dsp_up}
dct plds m0,MACH ;!/* 11101101xxyynnnn plds <DSP_REG_N>,MACH */ {"plds", {DSP_REG_N,A_MACH},{PPI,PPIC,HEX_E,HEX_D}, arch_sh_dsp_up}
dct plds m0,MACL ;!/* 11111101xxyynnnn plds <DSP_REG_N>,MACL */ {"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up}
|
tactcomplabs/xbgas-binutils-gdb
| 34,684
|
gas/testsuite/gas/sh/arch/sh4.s
|
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl .
! This file should contain every instruction valid on
! architecture sh4 but no more.
! If the tests are failing because the expected results have changed then run
! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl'
! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files.
! Make sure there are no unexpected or missing instructions.
.section .text
sh4:
! Instructions introduced into sh4
fipr fv4,fv0 ;!/* 1111nnmm11101101 fipr <V_REG_M>,<V_REG_N>*/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up}
frchg ;!/* 1111101111111101 frchg */{"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}, arch_sh4_up}
fsca FPUL,dr2 ;!/* 1111nnn011111101 fsca FPUL,<D_REG_N> */{"fsca",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_F,HEX_D}, arch_sh4_up}
fsrra fr1 ;!/* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}
ftrv xmtrx,fv0 ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}
! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh3_nommu_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r4,SGR ;!/* 0100nnnn00111010 ldc <REG_N>,SGR */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
ldc r4,DBR ;!/* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
ldc.l @r4+,SGR ;!/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up}
ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,DBR ;!/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up}
ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds r4,FPUL ;!/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up}
lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
lds.l @r5+,FPUL ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up}
lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movca.l R0,@r4 ;!/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
ocbi @r4 ;!/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up}
ocbp @r4 ;!/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up}
ocbwb @r4 ;!/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
stc SGR,r4 ;!/* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
stc DBR,r4 ;!/* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts FPUL,r4 ;!/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up}
sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sts.l FPUL,@-r4 ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up}
sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
fabs fr1 ;!/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}
fabs dr2 ;!/* 1111nnn001011101 fabs <D_REG_N> */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2a_or_sh4_up}
fadd fr2,fr1 ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}
fadd dr4,dr2 ;!/* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2a_or_sh4_up}
fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
fcmp/eq dr4,dr2 ;!/* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2a_or_sh4_up}
fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}
fcmp/gt dr4,dr2 ;!/* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2a_or_sh4_up}
fcnvds dr2,FPUL ;!/* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh2a_or_sh4_up}
fcnvsd FPUL,dr2 ;!/* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh2a_or_sh4_up}
fdiv fr2,fr1 ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}
fdiv dr4,dr2 ;!/* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2a_or_sh4_up}
fldi0 fr1 ;!/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up}
fldi1 fr1 ;!/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up}
flds fr1,FPUL ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}
float FPUL,fr1 ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}
float FPUL,dr2 ;!/* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2a_or_sh4_up}
fmac FR0,fr2,fr1 ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}
fmov fr2,fr1 ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}
fmov xd4,xd2 ;!/* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2a_or_sh4_up}
fmov @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
fmov @r5,xd2 ;!/* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}
fmov fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
fmov xd4,@r4 ;!/* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}
fmov @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
fmov @r5+,xd2 ;!/* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}
fmov fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
fmov xd4,@-r4 ;!/* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}
fmov @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
fmov @(R0,r5),xd2 ;!/* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}
fmov fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
fmov xd4,@(R0,r4) ;!/* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}
fmov.d @r5,xd2 ;!/* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}
fmov.d xd4,@r4 ;!/* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}
fmov.d @r5+,xd2 ;!/* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}
fmov.d xd4,@-r4 ;!/* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}
fmov.d @(R0,r5),xd2 ;!/* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}
fmov.d xd4,@(R0,r4) ;!/* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}
fmov.s @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
fmov.s fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
fmov.s @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
fmov.s fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
fmov.s @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
fmov.s fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
fmul fr2,fr1 ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}
fmul dr4,dr2 ;!/* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2a_or_sh4_up}
fneg fr1 ;!/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}
fneg dr2 ;!/* 1111nnn001001101 fneg <D_REG_N> */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2a_or_sh4_up}
fschg ;!/* 1111001111111101 fschg */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh2a_or_sh4_up}
fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
fsqrt dr2 ;!/* 1111nnn001101101 fsqrt <D_REG_N> */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh4_up}
fsts FPUL,fr1 ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}
fsub fr2,fr1 ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}
fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
ftrc fr1,FPUL ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}
ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
|
tactcomplabs/xbgas-binutils-gdb
| 30,134
|
gas/testsuite/gas/sh/arch/sh2a-or-sh4.s
|
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl .
! This file should contain every instruction valid on
! architecture sh2a-or-sh4 but no more.
! If the tests are failing because the expected results have changed then run
! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl'
! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files.
! Make sure there are no unexpected or missing instructions.
.section .text
sh2a_or_sh4:
! Instructions introduced into sh2a-or-sh4
fabs dr2 ;!/* 1111nnn001011101 fabs <D_REG_N> */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2a_or_sh4_up}
fadd dr4,dr2 ;!/* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2a_or_sh4_up}
fcmp/eq dr4,dr2 ;!/* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2a_or_sh4_up}
fcmp/gt dr4,dr2 ;!/* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2a_or_sh4_up}
fcnvds dr2,FPUL ;!/* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh2a_or_sh4_up}
fcnvsd FPUL,dr2 ;!/* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh2a_or_sh4_up}
fdiv dr4,dr2 ;!/* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2a_or_sh4_up}
float FPUL,dr2 ;!/* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2a_or_sh4_up}
fmov xd4,xd2 ;!/* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2a_or_sh4_up}
fmov @r5,xd2 ;!/* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}
fmov xd4,@r4 ;!/* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}
fmov @r5+,xd2 ;!/* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}
fmov xd4,@-r4 ;!/* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}
fmov @(R0,r5),xd2 ;!/* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}
fmov xd4,@(R0,r4) ;!/* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}
fmov.d @r5,xd2 ;!/* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}
fmov.d xd4,@r4 ;!/* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}
fmov.d @r5+,xd2 ;!/* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}
fmov.d xd4,@-r4 ;!/* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}
fmov.d @(R0,r5),xd2 ;!/* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}
fmov.d xd4,@(R0,r4) ;!/* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}
fmul dr4,dr2 ;!/* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2a_or_sh4_up}
fneg dr2 ;!/* 1111nnn001001101 fneg <D_REG_N> */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2a_or_sh4_up}
fschg ;!/* 1111001111111101 fschg */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh2a_or_sh4_up}
fsqrt dr2 ;!/* 1111nnn001101101 fsqrt <D_REG_N> */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh4_up}
fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds r4,FPUL ;!/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up}
lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
lds.l @r5+,FPUL ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up}
lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts FPUL,r4 ;!/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up}
sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sts.l FPUL,@-r4 ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up}
sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
fabs fr1 ;!/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}
fadd fr2,fr1 ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}
fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}
fdiv fr2,fr1 ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}
fldi0 fr1 ;!/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up}
fldi1 fr1 ;!/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up}
flds fr1,FPUL ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}
float FPUL,fr1 ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}
fmac FR0,fr2,fr1 ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}
fmov fr2,fr1 ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}
fmov @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
fmov fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
fmov @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
fmov fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
fmov @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
fmov fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
fmov.s @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
fmov.s fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
fmov.s @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
fmov.s fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
fmov.s @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
fmov.s fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
fmul fr2,fr1 ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}
fneg fr1 ;!/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}
fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
fsts FPUL,fr1 ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}
fsub fr2,fr1 ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}
ftrc fr1,FPUL ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}
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