® | MOTOROLA | | | Me6S0gE | | | --------- | --- | --- | -------- | --- | 8-BIT MICROPROCESSING UNIT HMOS The MC6809E is a revolutionary high performance 8-bit microprocessor (HIGH-DENSITY N-CHANNEL, SILICON-GATE) which supports modern programming techniques such as position independ ence, reentrancy, and modular programming. a-BIT This third-generation addition to the M6800 Family has major architectural improvements which include additional registers, instructions, and addressing MICROPROCESSING | modes. | | | UNIT | | | ------------------------------------------------------------ | --- | ------- | ----- | --- | | The basic instructions of any computer are greatly enhanced | | by the | | | presence of powerful addressing modes. The MC6809E has the most com plete set of addressing modes available on any 8-bit microprocessor today. The MC6809E has hardware and software features which make it an ideal processor for higher level language execution or standard controller applica | tions. External clock inputs are | provided to allow synchronization with | | | | | ----------------------------------- | --------------------------------------- | --- | --- | --- | peripherals, systems, or other MPUs. MC6800 COMPATIBLE L SUFFIX • Hardware ~ Interfaces with All M6800 Peripherals CERAMIC PACKAGE • Software ~ Upward Source Code Compatible Instruction Set and CASE 715 Addressing Modes ARCHITECTURAL FEATURES • Two 16-Bit Index Registers • Two 16-Bit Indexable Stack Pointers | • Two 8-Bit Accumulators can | be Concatenated to Form One | 16-Bit | | | | ------------------------------ | ----------------------------- | ------- | --- | --- | Accumulator • Direct Page Register Allows Direct Addressing Throughout Memory HARDWARE FEATURES • External Clock Inputs, E and Q, Allow Synchronization • TSC Input Controls Internal Bus Buffers • LlC Indicates Opcode Fetch • AVMA Allows Efficient Use of Common Resources in a Multiprocessor System PIN ASSIGNMENT • BUSY is a Status Line for Multiprocessing • Fast Interrupt Request Input Stacks Only Condition Code Register and VSS HACi | Program Counter | | | NMi | TSe | | ---------------- | --- | --- | ---- | ---- | • Interrupt Acknowledge Output Allows Vectoring By Devices | | | | iAQ | Lie | | --- | --- | --- | ---- | ---- | • Sync Acknowledge Output Allows for Synchronization to External Event • Single Bus-Cycle RESET RESET • Single 5-Volt Supply Operation • NMI Inhibited After RESET Until After First Load of Stack Pointer BS AVMA | • Early Address Valid Allows Use With Slower Memories | | | | Q | | ------------------------------------------------------- | --- | --- | ---- | --- | | • Early Write Data for Dynamic Memories | | | Vee | | SOFlWARE FEATURES | | | | AO | BUSY | | --- | --- | --- | --- | ----- | • 10 Addressing Modes | • M6800 Upward Compatible Addressing Modes | | | Al | R/W | | -------------------------------------------- | --- | --- | --- | ---- | | • Direct Addressing Anywhere in Memory Map | | | A2 | DO | • Long Relative Branches Dl | • Program Counter Relative | | | A3 | | | ---------------------------- | --- | --- | --- | --- | | • True Indirect Addressing | | | A4 | | D2 • Expanded Indexed Addressing D3 0-, 5-, 8-, or 16-Bit Constant Offsets | 8-or 16-Bit Accumulator Offsets | | | | D4 | | ------------------------------------ | --- | --- | --- | --- | | Auto-Increment/ Decrement by 1 or 2 | | | A7 | D5 | • Improved Stack Manipulation | | | | AS | D6 | | --- | --- | --- | --- | --- | • 1464 Instruction with Unique Addressing Modes | • 8 x 8 Unsigned Multiply | | | | D7 | | --------------------------- | --- | --- | --- | ---- | | • 16-Bit Arithmetic | | | | A15 | • Transfer/Exchange All Registers | | | | All | A14 | | --- | --- | --- | ---- | ---- | • Push/ Pull Any Registers or Any Set of Registers | • Load Effective Address | | | | A13 | | -------------------------- | --- | --- | --- | ---- | Me6S09E MAXIMUM RATINGS This device contains circuitry to protect the Unit Rating Symbol Value inputs against damage due to high static Supply Voltage -0.3 to + 7.0 V voltages or electric fields; however, it is ad VCC Input Voltage Vin 0.3 to + 7.0 V vi s e d th a t n o r m a l p re c a u ti o n s b e t a k e n to | | | | | | | | a v o i d a p | p l ic a ti o n | o f a n y v o l ta g | e h i g h e r th a n | | --- | --- | --- | --- | --- | --- | --- | -------------- | ----------------- | ---------------------- | -------------------------- | Operating Temperature Range TL to TH maximum rated voltages to this high im | | | | | | o to + 70 | 'c | | | | | | ---------------------------- | --- | --- | --- | --- | ---------- | --- | ----------------- | --- | --- | --- | | MC6809E, MC68A09E, MC68809E | | | TA | | | | pedance circuit. | | | | MC6809EC, MC68A09EC, MC68809EC -40 to +85 Reliability of operation is enhanced if unus Storage Temperature Range Tstg -55to+150 'c ed inputs are tied to an appropriate logic voltage levelle.g., either VSS or VCCI. THERMAL CHARACTERISTICS | | Characteristic | | Symbol | | Value | Unit | | | | | | --- | --------------- | --- | ------- | --- | ------ | ----- | --- | --- | --- | --- | Thermal Resistance | Ceramic | | | | | 50 | | | | | | | -------- | --- | --- | --- | --- | --- | ----- | --- | --- | --- | --- | | Cerdip | | | | | 60 | 'C/W | | | | | 8JA | Plastic | | | | | 100 | | | | | | | -------- | --- | --- | --- | --- | ---- | --- | --- | --- | --- | --- | POWER CONSIDERATIONS The average chip-junction temperature, TJ, in 'c can be obtained from: | T J = TA + IPDoOJA) | | | | | | | | | | (1) | | -------------------- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---- | Where: T A"" Ambient Temperature, 'c OJAE Package Thermal Resistance, Junction-to-Ambient, °C/W PD'" PINT+ PPORT | | PINTEICC x VCC, Watts - | | Chip Internal Power | | | | | | | | | --- | --------------------------------------- | --- | -------------------- | --- | ---------------- | --- | --- | --- | --- | --- | | | PPORT'" Port Power Dissipation, Watts - | | | | User Determined | | | | | | For most applications PPORTOOQ<)! Not Valid NOTES: 1. Voltage levels shown are VL:SO.4 V, VH~2.4 V, unless otherwise specified. 2. Measurement points shown are 0.8 V and 2.0 V, unless otherwise specified. ® 3. Hold time.1 I for BA and BS is not specified. 4. Usable access time is computed-by: 1-4-11 max-17. Me6S09E FIGURE 2 - EXPANDED BLOCK DIAGRAM -+--VCC -+--VSS Instruction Register FIRQ IRQ '--.:;==---l~ LlC AVMA R/W TSC HAri' BA BS '-----:l~ BUS Y * Internal Three-State Control PROGRAMMING MODEL As shown in Figure 4, the MC6809E adds three registers to FIGURE 3 - BUS TIMING TEST LOAD the set available in the MC6800. The added registers include a direct page register, the user stack pointer." and a second 5.0 V index register. ACCUMULATORS lA, B, D) MMD6150 The A and B registers are general purpose accumulators or Equiv. which are used for arithmetic calculations and manipulation Test Point O-' ....- e--+t--. of data. Certain instructions concatenate the A and B registers to C R MMD7000 form a single 16-bit accumulator. This is referred to as theD· or Equiv. register, and is formed with the A register as the most signifi cant byte. DIRECT PAGE REGISTER lOP) C=3O pF for BA, BS, LlC, AVMA, BUSY The direct page register of the MC6809E serves to enhance 130 pF for 00-07 the direct addressing mode. The content of this register 90 pF for AO-A15, Riw appears at the higher address outputs (A8-A15) during direct R = 11.7 kO for 00-07 addressing instruction execution. This allows the direct 16.5 kO for AO-A 15, R/W mode to be used at any place in memory, under program 24 kO for BA, BS, LlC, AVMA, BUSY control. To ensure M6800 compatibility, all bits of this register are cleared during processor reset. Me6S09E FIGURE 4 - PROGRAMMING MODEL OF THE MICROPROCESSING UNIT 15 o x ~ Index Register } Y - Index Register ""'"'" ",""'"' U - User Stack Pointer S - Hardware Stack Pointer PC Program Counter , A I B Accumulators / V D 7 0 I I DP Direct Page Register ~--------------~ 7 0 I I I I I I I I ElF H I N z V C cc - Condition Code Register INDEX REGISTERS (X, VI FIGURE 5 - CONDITION CODE REGISTER FORMAT The index registers are used in indexed mode of address ing. The 16-bit address in this register takes part in the cal culation of effective addresses. This address may be used to point to data directly or may be modified by an optional con Carry stant or register offset. During some indexed modes, the Overflow contents of the index register are incremented and decre '-----Zero mented to point to the next item of tabular type data. All four '-------Negative pointer registers (X, V, U, SI may be used as index registers. '-----·---IRO Mask '---------Half Carry STACK POINTER (U, SI '-----------FIRO Mask '------------Entire Flag The hardware stack pointer (SI is used automatically by the processor during subroutine calls and interrupts. The user stack pointer (UI is controlled exclusively by the pro grammer. This allows arguments to be passed to and from subroutines with ease. The U register is frequently used as a stack marker. Both stack pointers have the same indexed mode addressing capabilities as the X and Y registers, but also support Push and Pull instructions. This allows the CONDITION CODE REGISTER MC6809E to be used efficiently as a stack processor, greatly DESCRIPTION enhancing its ability to support higher level languages and modular programming. BITO (CI Bit 0 is the carry flag and is usually the carry from the NOTE binary ALU. C is also used to represent a "borrow" from The stack pointers of the MC6809E point to the top of subtract like instructions (CMP, NEG, SUB, SBCI and is the the stack in contrast to the MC6800 stack pointer, complement of the carry from the binary ALU. which pointed to the next free location on stack. BIT 1 (VI PROGRAM COUNTER Bit 1 is the overflow flag and is set to a one by an operation The program counter is used by the processor to point to which causes a Signed twos complement arithmetic over the address of the next instruction to be executed by the pro flow. This overflow is detected in an operation in which the cessor. Relative addressing is provided allowing the program carry from the MSB in the ALU does not match the carry counter to be used like an index register in some situations. from the MSB-l. CONDITION CODE REGISTER BIT2(ZI The condition code register defines the state of the pro Bit 2 is the zero flag and is set to a one if the result of the cessor at any given time. See Figure 4. previous operation was identically zero. Me6S09E BIT3 (N) reset vectors are fetched from locations FFFE16 and FFFF16 Bit 3 is the negative flag, which contains exactly the value !Table 11 when interrupt acknowledge is true, IBAoBS= 11. of the MSB of the result of the preceding operation. Thus, a During initial power on, the reset line should be held low until negative twos complement result will leave N set to a one. the clock input Signals are fully operational. Because the MC6809E RESET pin has a Schmitt-trigger in BIT4 (I) put with a threshold voltage higher than that of standard Bit 4 is the TRCi mask bit. The processor will not recognize peripherals, a simple R/e network may be used to reset the interrupts from the TRCi line if this bit is set to a one. NliilT, entire system. This higher threshold voltage ensures that all FIRO, iRQ, RESET, and SWI all set I to a one. SWI2 and peripherals are out of the reset state before the processor. SWI3 do not affect I. HALT BIT 5 (H) A low level on this input pin will cause the MPU to stop Bit 5 is the half-carry bit. and is used to indicate a carry running at the end of the present instruction and remain from bit 3 in the ALU as a result of an 8-bit addition only halted indefinitely without loss of data. When halted, the BA IADC or ADDI. This bit is used by the DAA instruction to output is driven high indicating the buses are high im pedance. BS is also high which indicates the processor is in perform a BCD decimal add adjust operation. The state of this flag is undefined in all subtract-like instructions. the halt state. While halted, the M PU will not respond to ex | | | | | ternal real-time | requests IFIRO, | IROI although | NMI or | | --- | --- | --- | --- | ------------------ | ----------------- | --------------- | -------- | BIT6 (F) RESET will be latched for later response. During the halt state, 0 and E should continue to run normally. A halted | Bit 6 is | the FIRO mask bit. The | processor will | not | | | | | | ---------- | --------------------------- | --------------- | ---- | ------------------ | ------------------------------------ | --- | --- | | | | | | state IBAoBS = 11 | can be achieved by pulling HALT low | | | recognize interrupts from the FI RO line if this bit is a one. NMI, FIRO, SWI, and RESET all set F to a one. TRQ, SWI2, while RESET is still low. See Figure 7. and SWI3 do not affect F. BUS AVAILABLE, BUS STATUS (BA, BS) BIT7 (E) The bus available output is an indication of an internal control signal which makes the MOS buses of the M PU high Bit 7 is the entire flag, and when set to a one indicates that the complete machine state fall the registersl was stacked, impedance. When BA goes low, a dead cycle will elapse before the MPU acquires the bus. BA will not be asserted as opposed to the subset state I PC and CCI. The E bit of the when TSC is active, thus allowing dead cycle consistency. stacked CC is used on a return from interrupt I RTII to deter The bus status output signal, when decoded with BA, mine the extent of the unstacking. Therefore, the current E represents the MPU state Ivalid with leading edge of 01. left in the condition code register represents past action. | | PIN DESCRIPTIONS | | | MPU State | | | | | --- | ----------------- | --- | --- | ---------- | --- | --- | --- | MPU State Definition | | | | | BA | BS | | | | --- | --- | --- | --- | --- | --- | --- | --- | POWER IVSS, Vee) Two pins are used to supply power to the part: VSS is 0 0 Normal (Running) | | | | | 0 | 1 Interrupt or Reset Acknowledge | | | | --- | --- | --- | --- | --- | ---------------------------------- | --- | --- | ground or 0 volts, while Vce is +5.0 V ±5%. | | | | | 1 | 0 Sync Acknowledge | | | | --------------------- | --- | --- | --- | --- | -------------------- | --- | --- | | ADDRESS BUS (AO-A15) | | | | 1 | 1 Halt Acknowledge | | | Sixteen pins are used to output address information from the M PU onto the address bus. When the processor does Interrupt Acknowledge is indicated during both cycles of a not require the bus for a data transfer, it will output address | | | | | hardware vector fetch | IRESET, | NMI, FIRQ, | IRQ, SWI, | | --- | --- | --- | --- | ---------------------- | -------- | ------------ | ----------- | FFFF16, R/W= 1, and BS=O; this is a "dummy access" or SWI2, SW131. This signal, plus decoding of the lower four | VMA cycle. | All address bus drivers | are made | high | | | | | | ------------ | --------------------------- | ---------- | ----- | --- | --- | --- | --- | address lines, can provide the user with an indication of impedance when output bus available I BAI is high or when TSe is asserted. Each pin will drive one Schottky TTL load or which interrupt level is being serviced and allow vectoring by device. See Table 1. four LSTTL loads and 90 pF. DATA BUS (00-07) | | | | | TABLE 1 - | MEMORY MAP FOR INTERRUPT VECTORS | | | | ------------------------------------------------------- | --- | --- | --- | --------------- | --------------------------------- | --- | --- | | These eight pins provide communication with the system | | | | Memory Map For | | | | bidirectional data bus. Each pin will drive one Schottky TTL Interrupt Vector Vector Locations | load or four LSTTL loads and 130 pF. | | | | MS | LS | Description | | | ------------------------------------- | --- | --- | --- | ----- | ----- | ------------ | -------- | | | | | | FFFE | FFFF | | R ES ET | | READ/WRITE (R/W) | | | | | | | - - | | | | | | FFFC | FFFD | | NMI | This signal indicates the direction of data transfer on the | | | | | FFFA | FFFB | | SWI | | --- | --- | --- | --- | ----- | ----- | --- | ---- | data bus. A low indicates that the MPU is writing data onto FFF8 FFF9 IRO the data bus. R/W is made high impedance when BA is high | | | | | FFF6 | FFF7 | | Fi'R6 | | --- | --- | --- | --- | ----- | ----- | --- | ------ | or when TSe is asserted. | | | | | FFF4 | FFF5 | | SWI2 | | --- | --- | --- | --- | ----- | ----- | --- | ----- | RESET | | | | | FFF2 | FFF3 | | SWI3 | | --- | --- | --- | --- | ----- | ----- | --- | ----- | A low level on this Schmitt-trigger input for greater than | | | | | FFFO | FFFI | Reserved | | | --- | --- | --- | --- | ----- | ----- | --------- | --- | one bus cycle will reset the MPU, as shown in Figure 6. The s: en (") co <:) CD m FIGURE 6 - RESET TIMING I I m+1 I m+2 I m+31 m+41 m+5 I m+6 I m+7 I I I n + 1 I n + 2 I n + 3 I n + 4 I n + 5 I n + 6 I n + 7 I n + 8 I n + 9 I n + 10 I m n E Q RESET _____ | Address ==l.Y\._---"'---_..JL_~.L, _ | _"_ _ __"'____J'__ | __"'____J'__ _1.'__"_--"'--- | | | | | ------------------------------------- | --------------------- | ------------------------------ | --- | --- | --- | Data .ll.I.ll.I=l.Y\._~''---_J'-_--' = R/W~ S\\ill\\\ BA \~------------------~====~----- ill\\\\\\\ | B S | | \~--------~r_--------------------------~ | | | \ | | ---- | --- | ----------------------------------------- | --- | --- | --- | AVMA | | | ________ | ____________ | | ______ ___ | | -------------------------- | ------- | ---------------------------- | ------------- | -------- | ----------- | | BUSY~~w-________________~ | r---\~ | ~ | ~ | ~r---\~ | | | Lie | | r--""",,~--v----'.~-,r----' | | | | '---------------------~ NOTE: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted. 3: n 0» CO C) FIGURE 7 - HALT AND SINGLE INSTRUCTION EXECUTION TIMING FOR SYSTEM DEBUG CD m 2nd to Last Last Cycle Cycle 9f of Current Current Dead Halted Halted Q I ~ __________ \~ _____.. ~ t~tJC_f ________________ __ ~ ----2t-ltpcs Address ---,,--~v-- Bus Fetch Execute R/W ~!~----~\ \~ __________ ~/ BA ________________ BS ________________~ !~-----\~----------------~\ /~--------- Data -----,l,--__"r----. Bus ___. .J\_ Instruction Opcode ~ ~\,_--------------------~/ \'------ AVMA __________ ____ \--------------.~ ------------'/ L1C NOTE: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted. Me6S09E Sync Acknowledge is indicated while the MPU is waiting defer the rearbitration of the next bus cycle to insure the in for external synchronization on an interrupt line. tegrity of the above operations. This difference provides the Halt Acknowledge is indicated when the MC6809E is in a indivisible memory access required for a "test-and-set" halt condition. primitive, using anyone of several read-modify-write instruc tions. NON MASKABLE INTERRUPT (NMI)" BUSY does not become active during PSH or PUL opera A negative transition on this input requests that a non tions. A typical read-modify-write instruction IASLl is shown maskable interrupt sequence be generated. A non-maskable in Figure 11. Timing information is given in Figure 12. BUSY interrupt cannot be inhibited by the program and also has a is valid tCD after the rising edge of Q. higher priority than FIRQ, IRQ, or software interrupts. Dur ing recognition of an NMI, the entire machine state is saved AVMA on the hardware stack. After reset, an NMI will not be recog' nized until the first program load of the hardware stack AVMA is the advanced VMA signal and indicates that the pointer IS), The pulse width of NMIIow must be at least one MPU will use the bus in the following bus cycle. The predic E cycle. If the NMI input does not meet the minimum set up tive nature of the AVMA signal allows efficient shared-bus with respect to Q, the interrupt will not be recognized until multiprocessor systems. AVMA is low when the MPU is in the next cycle. See Figure 8. either a HALT or SYNC state. AVMA is valid tCD after the rising edge of Q. FAST-INTERRUPT REOUEST (FIRO)" A low level on this input pin will initiate a fast interrupt se quence, provided its mask bit IFI in the CC is clear. This se LlC quence has priority over the standard interrupt request IIRQI LlC lIast instruction cycle) is high during the last cycle of and ·is fast in the sense that it stacks only the contents of the every instruction, and its transition from high to low will indi condition code register and the program counter. The inter cate that the first byte of an opcode will be latched at the end rupt service routine should clear the source of the interrupt of the present bus cycle. LlC will be high when the MPU is before doing an RTI. See Figure 9. halted at the end of an instruction (i.e., not in CWAI or RESET), in sync state, or while stacking during interrupts. INTERRUPT REOUEST (IRO)" LlC is valid tCD after the rising edge of Q. A low level input on this pin will initiate an interrupt re quest sequence provided the mask bit (I) in the CC is clear. Since IRQ stacks the entire machine state, it provides a TSC slower response to interrupts than FIRQ. IRQ also has a TSC (three-state control) will cause MOS address, data, lower priority than FIRQ. Again, the interrupt service routine and R/IN buffers to assume a high-impedance state. The should clear the source of the interrupt before doing an RTI. control signals IBA, BS, BUSY, AVMA, and LlC) will not go See Figure 8. to the high-impedance state. TSC is intended to allow a single bus to be shared with other bus masters (processors CLOCK INPUTS E, 0 or DMA controllers). E and Q are the clock signals required by the MC6809E. Q While E is low, TSC controls the address buffers and R/IN must lead E; that is, a transition on Q must be followed by a directly. The data bus buffers during·a write operation are in similar transition on E after a minimum delay. Addresses will a high-impedance state until Q rises at which time, if TSC is be valid from the MPU, tAD after the falling edge of E, and true, they will remain in a high-impedance state. If TSC is data will be latched from the bus by the falling edge of E. held beyond the rising edge of E, then it will be internally While the Q input is fully TTL compatible, the E input directly latched, keeping the bus drivers in a high-impedance state drives internal MOS circuitry and, thus, requires a high level for the remainder of the bus cycle. See Figure 13. above normal TTL levels. This approach minimizes clock skew inherent with an internal buffer. Refer to BUS TIMING CHARACTERISTICS for E and Q and to Figure 10 which shows a simple clock generator for the MC6809E. MPU OPERATION BUSY During normal operation, the MPU fetches an instruction BUSY will be high for the read and modify cycles of a from memory and then executes the requested function. read-modify-write instruction and during the .access of the This sequence begins after RESET and is repeated indefinite first byte of a dbuble-byte operation (e.g., LDX, STD, ly unless altered by a special instruction or hardware occur ADDD)' BUSY is also high during the first byte of any in rence. Software instructions that alter normal MPU opera direct or other vector fetch (e.g., jump extended, SWI in- tion are: SWI, SWI2, SWI3, CWAI, RTI, and SYNC. An direct, etc.). . interrupt or HALT input can also alter the normal execution In a multiprocessor system, BUSY indicates the need to of instructions. Figure 14 is the flowchart for the MC6809E. rim "NMI. RRQ, and requests are sampled on the fallin~ edge of Q. One cycle is required for synchronization before these interrupts are recog nized. Th~ndlng Interru~t(sl Will not be serviced until completion of the current instruction unless a SYNC or CWAI condition is present. If IRQ and FIRQ do not remain low until completion of the current Instrucnan, they may not be reco~nSed. However, f\/1iiii is latched and need onlSEfmain low for one cycle. No interrupts are recognized or latched between the. falling edge of E ET and the rising edge of BS indicating RE acknowledge. See I'fEID sequence in the MPU flowchart in Figure 14. ~ o en co ~ m FIGUR~ 8 - IRO AND NMI INTERRUPT TIMING Last Cycle of Current Instruction Instruction Interrupt Stacking and Vector Fetch Sequence Fetch I ... )01 ... )01... .1 I m-2 I m-l I m I m+ 1 I m+21 m+31 m+41 m+5 I m+61 m+ 71 m+SI m+9Im+ 10 Im+ lllm+ 121m+ 131m+ 141m+ 151m+ 161m+ 171m+ lsi n n+ 1 I o Address I Bus -P~~~J~---1~-p-c~L-p-c~L-__J L_ _~ L-__J L_ _- fi~ __J L_ _- A_ ___J L_ _~ ____A -__- A~~~~~~~~~~~~~~~~~~~~~~~ -...r I 1RQ or PCS ~~-~--------------------------------------------------------------------------------~~~~~--------------- NMI Data __~ ____J L_ _- 1\_ ___J L_ _- A~~/L __- -'\~~/L~--'\~~'~~~~ __~ L-__J L_ _~ ~ __J L_ _~ ____J L_ _~ ~==A-__- A_ ___J ~==~ ____l L_ _- A R/W~ \ ______ ___ BA~~ ________________________________________________~ ====~ BS~~~~~================================~ ~~/ ___ ___- , \ AVMA __- A_ ___~ __- 1 BUSY~~~==================================================~r--\~~====~---c=== LlC ______~ * E clock shown for reference only. NOTE: Timing measurements are refererlced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted. | | | | FIGURE 9 - FIRQ INTERRUPT TIMING | | | | | | --- | --- | --- | --------------------------------- | --- | --- | --- | --- | last Cycle | | of Current | | | | | Instruction | | | --- | -------------------- | ------------- | --------------------------------------------- | --- | ------ | ------------- | --- | | | I I n structio n | | Interrupt Stacking and Vector Fetch Sequence | | | | .1 | | | 0 ( . , ... | | | | | ., ... Fetch | | | I | | I m+l 1 m+2 | | I | I m+7 | | | m-2 , m-l m , m+3 , m+4 m+5 , m+6 , m+8 m+9 n+1 n+ Q Address Bus f_r_ ~ t_pc_s_ ____________________________________________________________________________________ _ RRQ __ Data | | | | PCl | PCH CCR | VMA New PCH New PCl | VMA | | | --- | --- | --- | ---- | --------- | ---------------------- | ---- | --- | \'-____- --'J R/W~ BA~~ _____________________________________________________ _ ..J/ BS~ _____________ \'------- AVMA r-----\,.--- | BUSY ~ ____________________________________________ | | | | | ____ | | | | ---------------------------------------------------- | --- | --- | --- | --- | ------- | --- | --- | | ~ | | | | | ~f \~ | | ~~ | LlC --'-__- --J * E clock shown for reference only. NOTE: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted. Me6S09E FIGURE 10 - CLOCK GENERATOR r ------------------, I I | | +5V | I | | --- | ---- | --- | I I I I I I I Optional IMRDY MRDY fireuit I I I I I L ____ _ I _ __ ...1 ~--I----------~~Q to System and Processor I.!.!.+_------,--!:> E to System +5V 4 MHz NOTE: If optional circuit is not included the CLR and PRE inputs of U2 and U3 must be tied high. o MRDY Si'RE'i'CH ---------V/. FIGURE 11 - READ-M-ODI-FY-WRITE INSTRUCTION EXAMPLE IASL EXTENDED INDIRECT) | Memory | Memory | | | --------- | ------- | --------------------- | | Location | ~ | Contents Description | PC-$0200 | | $68 | ASL Indexed Opcode | | ------ | ---- | --------------------------- | | $0201 | $9F | Extended Indirect Postbyte | | $0202 | $63 | Indirect Address Hi-Byte | - | $0203 | $00 | Indirect Address La-Byte | | ------ | ---- | ------------------------- | | $0204 | | Next Main Instruction | L-- $6300~ Effective Address Hi-Byte $6301~ Effective Address La-Byte Target Data 3: | | Last Cycle of | | | FIGURE 12 - | BUSY TIMING | | | | | | | (') | | --- | --------------- | --- | --- | ----------- | ------------ | --- | --- | --- | --- | --- | --- | ---- | | | Current Instr. | | | | | | | | | | | en | m-l m I m+l m+2 I m+3 I m+4 I m+5 I m+6 m+7 m+S 1 m+9 I m+l0 I C O 0 CD m Q $0200 $0201 $0202 $0203 $FFFF $6300 $6301 $FFFF $E3D6 $FFFF $E3D6 $0204 | Data | X | ~ X | X | X | X | X | X | X | X | X | X | | | ----- | --- | --------- | ---- | --------- | --- | --------- | ------ | ---- | ------ | ---- | --- | --- | | | | $68 $9F | $63 | $00 VMA | | $E3 $D6 | VlVIA | $5C | VI'AA | $SS | | | r | R/W~ | | | | | | | | | | \ | / | | | ----- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | | | }, | | | | / | \ | | / | | \ | | | BUSY | | / | \ | | | | | | | | I | \ | | | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | LlC AVMA | | | | | FIGURE 13 - | TSC TIMING | | | | | | | | | --- | --- | ----- | --- | ----------- | ----------- | --- | --- | --------------- | --- | --- | --- | --- | | | | ~C-. | | | | | | 1~---...:ftPCS | | | | | ======-=-:Jf...!.-! __ | | | Q __''_'~ '_k | | | | | | | | | | | | --- | --- | --------------------- | --- | --- | ----- | ------- | --- | --- | --- | --- | --- | --- | | | | | | | | I | | I | | | | | | | | ==-~~_1-'--'-...J7_/ | | | .""~ | ~: ""~ | | | | | | | -.:..,J :"'" | | | TSC | | | | < | | <..... _ __ '---__ ;--!-lTSV_ | | | | | | --- | ------------- | ---- | --- | --- | --- | ----- | -------- | ------------------------------- | ----- | --- | --- | --- | | | | | | | | I | }-- | | | | | | | | R/w' Address | | | }- | | | | | | | | | | | | | | | | ---1 | | ~ ~;..-.tT.:...:Sc.:.V | | | | | | | | | | | | | \.-tDDW | | ___ | | | | ___ | | | MPUData ________ | | ----')---------<~ | | | | (~ | | | | | | --- | --- | ----------------- | --- | ------------------ | --- | --- | --- | --- | --- | --- | --- | --- | ~seeNotelJ NOTES: 1. Data will be asserted by the MPU only during the inte~val while R/W is low and (E or 0) is high. A composite bus cycle is shown to give most cases of timing. 2. Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted. Me6S09E ADDRESSING MODES | The basic instructions of any computer are greatly en | | | EXTENDED INDIRECT | | | | ------------------------------------------------------ | --- | --- | ------------------ | --- | --- | hanced by the presence of powerful addressing modes. The | | | | As a special | case of indexed | addressing (discussed | | --- | --- | --- | -------------- | ------------------ | ----------------------- | MC6809E has the most complete set of addressing modes below), one level of indirection may be added to extended available on any microcomputer today. For example, the addressing. In extended indirect, the two bytes following the MC6809E has 59 basic instructions; however, it recognizes postbyte of an indexed instruction contain the address of the | 1464 different variations | of instructions and | addressing | data. | | | | --------------------------- | -------------------- | ----------- | ------ | --- | --- | modes. The addressing modes support modern program LDA [CAT] ming techniques. The following addressing modes are avail | able on the M C6809E: | | | LDX [$FFFE] | | | | --------------------------------- | --- | --- | ------------- | --- | --- | | Inherent .!Includes Accumulator) | | | STU [DOG] | | | Immediate | Extended | | | DIRECT ADDRESSING | | | | --------- | --- | --- | ------------------ | --- | --- | Extended Indirect Direct addressing is similar to extended addressing except Direct that only one byte of address follows the opcode. This byte Register specifies the lower eight bits of the address to be used. The upper eight bits of the address are supplied by the direct Indexed page register. Since only one byte of address is required in Zero-Offset direct addressing, this mode requires less memory and exe Constant Offset cutes faster than extended addressing. Of course, only 256 Accumulator Offset locations (one page) can be accessed without redefining the Auto In crement/ Decrement contents of the DP register. Since the DP register is set to Indexed Indirect $00 on reset, direct addressing on the MC6809E is upward Relative compatible with direct addressing on the M6800. Indirection Short/Long Relative Branching is not allowed in direct addressing. Some examples of direct | Program Counter Relative Addressing | | | addressing are: | | | | ------------------------------------ | --- | --- | ---------------- | --- | --- | LDA where DP=$oo INHERENT (INCLUDES ACCUMULATOR) LDB where DP= $10 In this addressing mode, the opcode of the instruction | contains all the address information necessary. Examples of | | | LDD c======x=======x======J(======)---------------------~----------_1---------------------------1c======X======~C=====:J R/W~ ~--------------------~~~,-----------7-----------------------J SA ==:)_ ____- ----11 \.-------~----------~\~------------------------- __________________________, ,-____ _______________________________ __ | SS~~ | | | ~ | | | ----- | --- | --- | --- | --- | AVMA~_ ___________~ \ __________~ l~, _ _____~ ----------~/ _______ | | | .' | I | | | --------- | -------- | --- | --------- | -------------------------------- | | LlC ~ , | | | | x~ S_e_e_N_o_t_e_1_ _______ __ | | _---'I | '-----1 | | ~tiltPcf | | NIRMOI,, -----------------------------------------------------J.~,----------V-IL See Note 2 ~ FIRG ~tPcs NOTES: 1. If the associated mask bit is set when the interrupt is requested, Lie will go low and this cycle will be an instruction fetch from address location PC + 1. However, if the interrupt is accepted (N M loran unmasked Fl RQ or fRO) LIe will remain high and interrupt processing will start with this cycle as m on Figures 8 and 9 (Interrupt TimingJ. 2. If mask bits are clear, IRQ andFiRO must be held low for three cycles 10 guarantee that interrupt will be taken, although only one cycle is necessary to bring the processor out of SYNC. 3. Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted. MC6809E FIGURE 17 - CYCLE-BY-CYCLE PERFORMANCE ISheet 1 of 5) NOTES Data Bus Address Bus L-........' -'--=~ 2 Address NNNN is location of opcode 3 If opcode is a two byte opcode sUbSequent addresses are in parenthesis (-). 4. Two-byte opcodes are highlighted No Me6S0gE FIGURE 17 - CYCLE-BY-CYCLE PERFORMANCE (Sheet 2 of 5) ~ Inherer\tAddressmgModf' | ABxt | RTSI | | | RTll | | | | | ----- | -------- | --------------------------------- | --- | ----- | ------- | ------ | --- | | | :;~:;~ | ........,M,...U..JLL,! --,S~~"f4 | | | SYNC ~ | CWAlt | | | | ~?~~,B, | | | | | l | J | Don'teare DOr1'tCare Don't Care Don't Care Don'teare Don I Cilr~ CCMask co~~n~~~~;'er | NNN•N+ 1 | • | | | NNN N + 1 | NNN N+ 1 | | | | ---------- | --------- | --- | --- | ---------- | --------- | --- | ------ | | | DEC;A'_' | + | + | t | | + | Stack | ~ Don'teare PC High LSLA',~ 0011 1 Care Don't Care CCA Don tCare Don'teare | | St ack | FF FF | | | | NNN N +2 | | | --- | ---------- | ------ | --- | --- | --- | --------- | --- | | | + 0~~AB | + | + | | | i | | ~ ? , ~ i ' | | PC Low : ~ : M B | Don 'lea re | P C L o w | | | DOr1'tCare | | | --- | -------------------- | ------------ | ------------- | --- | --- | ----------- | --- | | | • | | S t •a c k | | | ~C""C"NO | | | | | • | | | | + | | Presentl | | Don't Care | Don'teare | PCH,gh | | | PC Low | | | --- | ----------- | ---------- | ------- | --- | --- | ------- | --- | | | | FFFF | Stack | | | Stack | y" | | | | + | + | | | + | | 3 State | | | Don'leare | Us€,StackLow | | | PC High | | | --- | --- | ---------- | ------------- | --- | --- | -------- | --- | | | | FFFF | Stack | | | Stack | | + BReglster | | | ~ | | Stack | | i l | J | | --- | --- | ----------- | --------------- | --------------- | --- | --------------------------- | --------- | | | | Don't Care | UserStackH,gh | | | User Stack Low v:~7~;~~ | | | | | FF FF | • | | | Sta ck | FFF X +l | | | | + | | | | t | t | | | | Don'teare | YReglsterLow | | | User Stack High Don tCare | | | | | FF•FF | St•ack | | | S t ack | | | | | | | £AeglsterHogh | | i | | | | | Don'teare | Y ReglsterH'gh | | | y Register Low | | | | | FFFF | Stack | | | Stack | | | | | + | + | X Register Low | | J | | Stack | | | Don'leare | X Aeg,ster Low | t | | y Register High | | | --- | --- | ---------- | ---------------- | --------------- | --- | ---------------- | --- | | | | | Stack | | | Stack | | | | | | i | Y AeglsterH'gh | | i | | | | | ~ | | Stack | | | | | | | | X Aeglster High | | | X Register Low | | | | | | Sl ack | | | Sta ck | | | | | | + | Y Register low | | + | | Stack | | | | | + | | X Register HLgh | | | --- | --- | --- | --- | --- | --- | ---------------- | --- | Stack | | | | • | User Stack High | | i | | | --- | --- | --- | --- | ---------------- | --- | --- | --- | | | | | | St a ck | | J | | L D'~~~t,~:;e | | | | BReglster | i - | | | | | --- | --- | --- | ---------- | --------------- | --- | ------ | --- | | | | | Stack | User Stack Low | | Stack | | + Stack | | | | A Register | | | BReglster | | | --- | --- | --- | ----------- | ------ | --- | ----------- | --- | | | | | St•ack | | | Stack | | | | | | | Stack | | t | | | | | | | + | | A Register | | Stack L- +- Stack | | | | Don't Care | ~ | | | | | --- | --- | --- | ----------- | --- | --- | --- | --- | FFFF t | | | | I v~n~t~;~~h | I | | | | | --- | --- | --- | ------------- | --- | --- | --- | --- | FF•FX I I v:~:;U~~ FFF•X+ l t MC6809E FIGURE 17 -CYCLE-BY-CYLE PERFORMANCE (Sheet 3 of 5) .-____ Direct ~~~----~~-------------L------~~~--~--------------~~~,A'?~:~:~;"~g~_, Except PSHU NNNN -!; 112) PSHS, PULS, HR, Don'fCare Address Low "'"G' NNNN+2131 Me6S09E FIGURE 17 - CYCLE-BY-CYCLE PERFORMANCE iSheet4of51 xxxx Constant Olfsetfrom A No Offset IndexA&glster 8·BilOffSP.t Index RegISter + Offset Byte 16-BIIOffset Index Register + Offset High Byte" Offset Low Bvte AccurnulalorOffsel from R A Regis\erOflset Index Register + A Register B Register Offset Index RegIster + B Register o RegisterOlfsel Index Register + 0 Register Auto Increme/II/Dec/ernen! R InCfementby2 InOeJ(Reglsler Decrement by2 Index Register -2 Constant Offsetlrom PC 8-8110115el Program Counter + Offset Byte 16-bltDllsel Program Counter + Offset High Byte Offset Low Byte Extendedlndirecl ~ Address High Bvte Addles Low Byte The ,ndel( register IS Incremented folloWII'lg the In(!exed access Me6S09E FIGURE 17 - CYCL.E-BY-CYClE PERFORMANCE (Sheet 5 of 5) ANDCC, DRce IAII Except ~STX. CLR, COM. (All Except (All Except (Immediate Immediatel _(All DEC,INC, Immediate) Immediate~ Only), Except LSL.LSR. • Immediate) NEG, ROL, RDA (All Except Immediatel Effective Address lEAl Conslartt Offset from A No 0ffset Index Aegls,ler 5-Bll0ffset Index Register 8-81t Ollset. Index Register + Post Byte 1&-811 Offset Index Register + Post Byte High: Post Byle Low Accumulator Offset from R A Register Oilse! Index Reglster'+ A Register S"Reglster Offset Index Register + B Reg~lster o Register Offset Index Register + 0 Register A-uto Increment/Decrement R Increment by 1 Index Register. Incrementby2 Index Register Decrement by 1 Index Reglster-1 Oecremer'ltby2 Index Reglster'-2 ConstantO/lsB! from PC 8-BltOffset Program Counter + Ollset Byte 16·BI\ Offset Program Counter + Ollset High Byte. Ollset Low Byte Direct Page Register: Address Low Address .Hlgh. Address Low Immediate NNNN+l *.:rhemdex register is Incremented followmg thelndElxedaccess Me6S09E | TABLE 4 - | B-BIT ACCUMULATOR AND MEMORY INSTRUCTIONS | | | ---------------- | --------------------------------------------------- | ---------- | | Mnemonic(s) | | Operation | | ADCA,ADCB | Add memory to accumulator with carry | | | ADDA,ADDB | Add memory to accumulator | | | ANDA,ANDB | And memory with accumulator | | | ASL, ASLA, ASLB | Arithmetic shift of accumulator or memory left | | | ASR,ASRA,ASRB | Arithmetic shift of accumulator or memory right | | | BITA, BITB | Bit test memory with accumulator | | | CLR, CLRA, CLRB | Clear accumulator or memory location | | | CMPA, CMPB | Compare memory from accumulator | | | COM, COMA, COMB | Complement accumulator or memory location | | | DAA | Decimal adjust A accumulator | | | DEC,DECA,DECB | Decrement accumulator or memory location | | | EORA, EORB | Exclusive or memory with accumulator | | | EXG Rl, R2 | Exchange Rl with R2 (Rl, R2 = A, B, CC, DP) | | | INC, INCA, INCB | Increment accumulator or memory location | | | LOA, LOB | Load accumulator from memory | | | LSL, LSLA, LSLB | Logical shift left accumulator or memory location | | | LSR, LSRA, LSRB | Logical shift right accumulator or memory location | | | MUL | Unsigned multiply (A x B - | D) | | NEG, NEGA, NEGB | Negate accumulator or memory | | | ORA,ORB | Or memory with accumulator | | | ROL, ROLA, ROLB | Rotate accumulator or memory left | | | ROR, RORA, RORB | Rotate accumulator or memory right | | | SBCA, SBCB | Subtract memory from accumulator with borrow | | | STA,STB | Store accumulator. to memory | | | SUBA,SUBB | Subtract memory from accumulator | | | TST,TSTA, TSTB | Test accumulator or memory location | | | TFR Rl, R2 | Transfer Rl to R2 (Rl, R2 = A, B, CC, DP) | | NOTE: A, B, CC or DP may be pushed to (pulled from) either stack with PSHS, PSHU (PULS, . PULU) instructions. | TABLE 5 - | l6-BIT ACCUMULATOR AND MEMORY INSTRUCTIONS | | | ------------ | ------------------------------------------- | --- | | Mnemonic(s) | Operation | | | ADDD | Add memory to 0 accumulator | | | CMPD | Compare memory from 0 accumulator | | | EXG 0, R | Exchange 0 with X, Y, S, U or PC | | | LDD | Load 0 accumulator from memory | | SEX Sign Extend B accumulator into A accumulator | STD | Store 0 accumulator to memory | | | --------- | ----------------------------------- | --- | | SUBD | Subtract memory from 0 accumulator | | | TFR 0, R | Transfer 0 to X, Y, S, U or PC | | | TFR R, 0 | Transfer X, Y, S, U or PC to 0 | | NOTE: 0 may be pushed (pulled) to either stack with PSH5., PSHU (PULS, PULU) instructions. | TABLE 6 - | INDEX REG)STERISTACKPOINTER INSTRUCTIONS | | | ------------ | --------------------------------------------------------- | --- | | Instruction | Description | | | CMPS, CMPU | Compare memory from stac~.· pointer | | | CMPX, CMPY | Compare memory from index register | | | EXG Rl, R2 | Exchange 0, X, Y, S, U or PC with D, X, Y, S, U or PC | | | LEAS, LEAU | Load effective ~ddress into stack pointer | | | LEAX, LEAY | Load effective address into index regtster | | | LOS, LOU | Load stack pointer from memOfY | | | LDX, LDY | Load index register from memory | | | PSHS | Push A, B, CC, DP, D, X, Y, U, or PC onto hardware stack | | | PSHU | Push A, B, CC, DP, 0, X, Y, S, or PC onto user stack | | | PULS | Pull A, B, CC, DP, D, X, Y, U or PC from hardware stack | | | PULU | Pull A, B, CC, DP, 0, X, Y, S or PC from hardware stack | | | STS, STU | Store stack pointer to memory | | | STX, STY | Store index register to memory | | | TFR Rl, R2 | Transfer 0, X, Y, S, U or PC to D, X, y, S, U or PC | | | ABX | Add B accumulator to ?< (unsigned) | | Me6S09E TABLE 7 - BRANCH INSTRUCTIONS Instruction Description SIMPLE BRANCHES BEQ, LBEQ Branch if equal BNE, LBNE Branch if not equal BMI, LBMI Branch if minus BPL, LBPL Branch if plus BCS, LBCS Branch if carry set. BCC, LBCC Branch if carry clear BVS, LBVS Branch if overflow set BVC, LBVC Branch if overflow clear SIGNED BRANCHES BGT, LBGT Branch if greater (signed) BVS, LBVS Branch if invalid 2'5 complement result BGE~ LBGE Branch if greater tha'n or equal (signed) BEQ, LBEQ Branch if equal BNE, LBNE Branch if not equal BLE, LBLE Branch if less than or equal (signed) BVC, LBVC Branch if valid 2's complement result BLT, LBLT Branch If less than (signed) UNSIGNED BRANCHES BHI, LBHI Branch if higher (unsigned) BCC, LBCC Branch if higher or same (unsigned) BHS, LBHS Branch if higher or same (unsigned) BEQ, LBEQ Branch if equal BNE, LBNE Branch if not equal BLS, LBLS Branch if lower or same' (:unsignedl BCS, LBCS Branch if lower (unsigned) BLO, LBLO Branch if lower (unsigned) OTHER BRANCHES BSR, LBSR Branch to subroutine BRA, LBRA Branch always BRN, LBRN Branch never TABLE 8 - MISCELLANEOUS INSTRUCTIONS Instruction Description ANDCC AND condition code regi,ster CWAI AND condition code register, then wait for interrupt NOP No operation ORCC OR condition code register JMP Jump JSR Jump to subroutine RTI Return from interrupt RTS Return from subroutine SWI, SWI2, SWI3 Software interrupt (absolute indirect) SYNC Synchronize with interrupt line Me6S0gE | | | | TABLE 9 - HEXADECIMAL VALUES OF MACHINE CODES | | | | | | | ------------- | ------- | ----- | ---------------------------------------------- | --------- | ----- | ------------- | -------- | ------- | | | | - | | | - | | | - | | OP Mnem | Mode | # | OP Mnem | Mode | # | OP Mnem | Mode | # | | ·NE G | | | | | | ·NE G | | | | ()() | Direct | 6 2 | 30 LEAX | | 4+ | 2+ 60 | Indexed | 6+ 2+ | | 01 · | | | 31 LEAY | :~:[: 4+ | | 2+ 61 · | | | | 02 | | | 32 LEAS | | 4+ | 2+ 62 | | | | 03 COM | | 6 2 | 33 LEAU | | 4+ | 2+ 63 COM | | 6+ 2+ | | ·LS R | | | | Immed | | ·LS R | | | | 04 | | 6 2 | 34 PSHS | | 5+ | 2 64 | | 6+ 2+ | | 05 | | | 35 PULS | Immed | 5+ | 2 65 | | | | | | | | Immed | | 2 ROR | | | | 06 ROR | | 6 2 | 36 PSHU | | 5+ | 66 | | 6+ 2+ | | 07 ASR | | 6 2 | 37 ·PU LU | Immed | 5+ | 2 67 ASH | | 6+ 2+ | | | | | | | - | 68 ASL, LSL | | | | 08 ASL, LSL | | 6 2 | 38 | | | | | 6+ 2+ | | 09 ROL | | 6 2 | 39 RTS | Inherent | 5 | 1 69 ROL | | 6+ 2+ | | ·DE C | | | ABX | | t 3 | 1 6A ·DE C | | 6+ 2+ | | OA | | 6 2 | 3A | | | | | | | OB | | | 3B RTI | | 6/15 | 1 6B | | | | | | | CWAI | | | 2 6C INC | | 6+ 2+ | | OC INC | | 6 2 | 3C | | ~20 | | | | | 00 TST | | 6 2 | 3D ·MU L | Inherent | 11 | 1 60 lST | | 6+ 2+ | | OE JMP | | | 3E | | - | 6E JMP | | 3+ 2+ | | | | 3 2 | | | | | | | OF CLR Direct 6 2 3F SWI Inherent 19 1 6F CLR Indexed 6+ 2+ 10 Page 2 - - - 40 NEGA Inherent 2 1 70 NEG Extended 7 3 | 11 Page 3 | | - - | 41 * | | | 71 * | | | | ----------- | --- | --- | ------ | --- | --- | ------ | --- | --- | - | 12 NOP | Inherent | 2 1 | 42 * | | | 72 * | | | | ----------- | ------------ | ----- | --------------- | --- | --- | ---------------- | --- | ----- | | 13 SYNC | Inherent ~4 | 1 | 43 COMA | | 2 | 1 73 COM | | 7 3 | | 14 * | | | 44 LSRA | | 2 | 1 74 LSR | | 7 3 | | 15 * | | | 45 * | | | 75 * | | | | 16 LBRA | Relative | 5 3 | 46 RORA | | 2 | 1 76 ROR | | 7 3 | | 17 ·LB SR | Relative | 9 3 | 47 ASRA | | 2 | 1 77 ASR | | 7 3 | | 18 | | | 48 ASLA, LSLA | | 2 | 1 78 ASL, LSL | | 7 3 | | 19 OAA | Inherent | 2 1 | 49 ROLA | | 2 | 1 79 ROL | | 7 3 | | 1A ORCC | Immed | 3 2 | 4A ·OE CA | | 2 | 1 7A OEC | | 7 3 | | 1B * | | | 4B | | | 7B * | | | - | 1C ANOCC | Immed | 3 2 | 4C INCA | | 2 | 1 7C INC | | 7 3 | | ---------- | --------- | ----- | --------- | --- | --- | ----------- | --- | ----- | | 10 SEX | Inherent | 2 1 | 40 TSTA | | 2 | 1 70 TST | | 7 3 | | 1E EXG | Immed | 8 2 | 4E * | | | 7E JMP | | 4 3 | 1F TFR Immed 6 2 4F CLRA Inherent 2 1 7F CLR Extended 7 3 20 BRA Relative 3 2 50 NEGB Inherent 2 1 80 SUBA Immed 2 2 | 21 BRN | | 3 2 | 51 * | | | 81 CMPA | | 2 2 | | ------------- | --------- | ----- | --------------- | --------- | --- | ------------- | --------- | ----- | | 22 BHI | | 3 2 | 52 * | | | 82 SBCA | | 2 2 | | 23 BLS | | 3 2 | 53 COMB | | 2 | 1 83 SUBO | | 4 3 | | 24 BHS, BCC | | 3 2 | 54 LSRB | | 2 | 1 84 ANOA | | 2 2 | | 25 BLD, BCS | | 3 2 | 55 * | | | 85 BITA | | 2 2 | | 26 BNE | | 3 2 | 56 RORB | | 2 | 1 86 ·LO A | | 2 2 | | 27 BEQ | | 3 2 | 57 ASRB | | 2 | 1 87 | | | | 28 BVC | | 3 2 | 68 ASLB, LSLB | | 2 | 1 68 EORA | | 2 2 | | | | | | | | 1 AOCA | | 2 | | 29 BVS | | 3 2 | 59 ROLB | | 2 | 89 | | 2 | | 2A BPL | | 3 2 | 5A OECB | | 2 | 1 8A ORA | | 2 2 | | | | | * | | | 8B AOOA | | 2 2 | | 2B BMI | | 3 2 | 5B | | | | | | | 2C BGE | | 3 2 | 5C INCB | | 2 | 1 8C CMPX | Immed | 4 3 | | 20 BLT | | | 50 TSTB | | 2 | 1 80 BSR | Relative | 7 2 | | | | 3 2 | | | | | | | | 2E BGT | | 3 2 | 5E * | | | 8E ·LO X | Immed | 3 3 | | | | | 5F CLRB | Inherent | 2 | 1 8F | | | | 2F BLE | Relative | 3 2 | | | | | | | LEGEND: - Number of MPU cycles (Jess possible push pull or indexed-mode cycles) # Number of program bytes * Denotes unused opcode Me6S09E | | | TABLE 9 - | HEXADECIMAL VALUES OF MACHINE CODES (CONTINUED) | | | | | | | | | ------------- | ------- | --------- | ------------------------------------------------ | --------------- | ------- | --------------- | ------------- | --------------------- | --------- | ------------- | | | | - | | | | - | | I | | I- I | | OP Mnem | Mode | | # | OP Mnem | Mode | | # OP | M nem | 1 Mode | # | | 90 SUBA | | 4 | | | | | | | | | | | Direct | | 2 | CO SUBB | Immed | 2 | 2 | | | | | 91 CMPA | | 4 | 2 | Cl CMPB | | 2 | 2 | | | | | 92 SBCA | | | | | | r | | Page 2 and 3 Machine | | | | | | 4 | 2 | C2 SBCB | | 2 | 2 | | Codes | | | 93 SUBD | | 6 | 2 | C3 ADDD | | 4 | 3 | | | | | 94 ANDA | | 4 | 2 | | | | | | | | | | | | | C4 ANDB | | 2 | 2 1021 | LBRN | Relative | 5 4 | | 95 BITA | | 4 | 2 | C5 BITB | Immed | 2 | 2 | LBHI | | | | 9 6 L D A | | 4 | 2 | | | | 1022 | | | 5161 4 | | | | | | C 6 L D B | ImImed | 2 | 2 1 0 2 3 | L B L S | | 5 1 6 1 4 | | 97 S T A | | 4 | 2 | C 7 * | | | | L B H S , LBCC | | | | 98 EORA | | 4 | 2 | | | | 1 0 2 4 | | | 5 1 6 1 4 | | | | | | C8 EORB | | 2 | 2 1025 | LBCS, LBLO | | 5(6) 4 | | 99 ADCA | | 4 | 2 | C9 ADCB | | 2 | 2 1026 | LBNE | | 5161 4 | | 9A ORA | | 4 | 2 | | | | | | | | | | | | | CA ORB | | 2 | 2 1027 | LBEQ | | 5161 4 | | 9B ADDA | | 4 | 2 | CB .AD DB" | | 2 | 2 1028 | LBVC | | 5161 4 | | 9C CMPX | | 6 | 2 | | | | | | | | | | | | | CC LDD | | 3 | 3 1029 | LBVS | | 5(6) 4 | | 9D JSR | | 7 | 2 | CD . | | | 102A | LBPL | | 5161 4 | | 9E LDX | | 5 | 2 | | | | | | | | | | | | | CE LDU | Immed | 3 | 3 102B | LBMI | | 5161 4 | | 9F STX | Direct | 5 | 2 | CF | | | 102C | LBGE | | 5(6) 4 | | | | | | D O S U B B | D | i r e c t 4 | 2 1 0 2 D | L B L T | | 5 1 6 1 4 | A O S U B A I n d e x e d 4 + 2 + 1 0 2 E L B G T 5 1 6 1 4 | A I C M P A | | 4 + | 2 + | D l C M P B | | 4 | 2 | | | | | -------------- | --- | --- | ------- | --------------- | --- | --- | ------------- | --------- | --- | ----------------------------- | | | | | | D 2 S B C B | | 4 | 2 1 0 2 F | L B L E | R | e l a t i v e 5 1 6 1 4 | A 2 S B C A 4 + 2 + I 0 3 F S W I 2 I n h e r e n t 2 0 2 | A 3 S U B D | | 6 + | 2 + | D 3 A D D D | | 6 | 2 | | | | | --------------- | --- | --- | ------- | --------------- | --- | --- | ------------- | --------- | --- | --------------- | | | | | | D 4 A N D B | | 4 | 2 1 0 8 3 | C M P b | I m | m e d 5 4 | | A 4 A N D A | | 4 + | 2 + | | | | 1 0 8 C | C M P Y | | I 5 4 | | A 5 B I T A | | 4 + | 2 + | D 5 B I T B | | 4 | 2 | | | | | | | | | D 6 L D B | | 4 | 2 1 0 8 E | L D Y | I m | m e d 4 4 | A 6 L D A 4 + 2 + 1 0 9 3 C M P D D i r t e c t 7 3 | A 7 S T A | | 4 + | 2 + | D 7 S T B | | 4 | 2 | | | | | --------------- | --- | --- | ------- | --------------- | --- | --- | ------------- | --------- | --- | ------------------- | | | | | | D 8 E O R B | | 4 | 2 I 0 9 C | C M P Y | | 7 3 | | A 8 E O R A | | 4 + | 2 + | | | | 1 0 9 E | L D Y | | 6 3 | | A 9 A D C A | | 4 + | 2 + | D 9 A D C B | | 4 | 2 | | | | | | | | | D A O R B | | 4 | 2 I 0 9 F | S T Y | D | i r e c t 6 3 | A A O R A 4 + 2 + 1 0 A 3 C M P D I n d e x e d 7 + 3 + | A B A D D A | | 4 + | 2 + | D B A D D B | | 4 | 2 | | | t | | --------------- | --- | --- | ------- | --------------- | --- | --- | ----------- | ----------- | --- | ----------- | | | | | | D C L D D | | 5 | 2 l O A C | C M P Y | | 7 + 3 + | | A C C M P X | | 6 + | 2 + | | | | 1 0 A E | L D Y | | 6 + 3 + | | A D J S R | | 7 + | 2 + | D D S T D | | 5 | 2 | | | | A E L D X D E L D U 5 2 lO A F S T Y I n d e x e d 6 + 3 + | | | 5 + | 2 + | | | | 1 0 B 3 | C M P D | E x | t e n d e d 8 4 | | ------------- | ----------- | ------------- | ------- | ------------- | -------- | --------------- | --------- | ----------- | ----------- | --------------------- | | A F S T X | I n d | e x e d 5 + | 2 + | D F S T U | D | i r e c t 5 | 2 | | | | | | | | | | | | 1 0 B C | C M P Y | | ~ 8 4 | | | | | | EO SUBB | Indexed | 4+ | 2+ lOBE | LDY | | 7 4 | | BO SUBA | Extended 5 | | 3 | El CMPB | | 4+ | 2+ | | | | | Bl CMPA | | | | | | | 10BF | STY | Extended 7 | 4 | | | | 5 | 3 | E2 SBCB | | 4+ | 2+ lOCE | LDS | Immed | 4 4 | | B2 SBCA | | 5 | 3 | E3 ADDD | | 6+ | 2+ | | | | | B3 SUBD | | 7 | 3 | | | | lODE | LDS | Direct | 6 3 | | | | | | E4 ANDB | | 4+ | 2+ 10DF | STS | Direct | 6 3 | | B4 ANDA | | 5 | 3 | E5 BITB | | 4+ | 2+ | | | | | B5 BITA | | 5 | 3 | | | | 10EE | LDS | Indexed | 6+ 3+ | | | | | | E6 LDB | | 4+ | 2+ 10EF | STS | Indexed | 6+ 3+ | | B6 LDA | | 5 | 3 | E7 STB | | 4+ | 2+ 10FE | LDS | Extended 7 | | | B7 STA | | 5 | 3 | | | | | | | 4 | | | | | | E8 EORB | | 4+ | 2+ 10FF | STS | Extended 7 | 4 | | B8 EORA | | 5 | 3 | E9 ADCB | | 4+ | 2+ 113F | SWI3 | | | | B9 ADCA | | 5 | 3 | | | | | | Inherent | 20 2 | | | | | | EA ORB | | 4+ | 2+ 1183 | CMPU | Immed | 5 4 | | BA ORA | | 5 | 3 | EB ADDB | | 4+ | 2+ 118C | CMPS | Immed | 5 4 | | BB ADDA | | 5 | 3 | | | | | | | | | | | | | EC LDD | | 5+ | 2+ 1193 | CMPU | Direct | 7 3 | B C C M P X 7 3 E D S TO 5 + 2 + 1 1 9C C M P S D ir e c t 7 3 | B D J S R | | 8 | a | | | | | | | | | ------------- | --- | --- | --- | ----------- | --- | ----- | ------------- | -------- | --- | --------------------- | | | | | | EE L O U | | 5 + | 2+ l1 A 3 | CM P U | In | d e x e d 7 + 3 + | BE LDX 6 3 EF STU Indexed 5+ 2+ llAC CMPS Indexed 7+ 3+ | BF STX | Extende d 6 | | 3 | | | | | | | | | -------- | ------------ | --- | --- | --------- | ----------- | ----- | ------------- | ----- | ----------- | --- | | | | | | FO SUBB | Extended 5 | | l1B3 | CMPU | Extended 8 | 4 | | | | | | | | | 3 11BC CMPS | | Extended 8 | 4 | | | | | | Fl CMPB | | ! 5 | 3 | | | | | | | | | F2 SBCB | | 5 | | | | | 3 | | | | | F3 ADDD | | 7 | 3 | | | | | --- | --- | --- | --- | ---------- | --- | --- | --- | --- | --- | --- | | | | | | F4 AN DB | | 5 | 3 | | | | | | | | | F5 BITB | | 5 | 3 | | | | | | | | | F6 LDB | | 5 | 3 | | | | | | | | | F7 STB | | 5 | 3 | | | | | | | | | F8 EORB | | 5 | 3 | | | | NOTE: All unused opcodes are both undefined | and illegal | | | | F9 ADCB | | 5 | 3 | | | | | ------------ | --- | --- | --- | --------- | ------------- | --- | --- | --- | --- | --- | | | | | | FA ORB | | 5 | 3 | | | | | | | | | FB AODB | Extended 5 | | 3 | | | | | | | | | FC LDD | Extetnd ed 6 | | 3 | | | | | | | | | FD STD | | 6 | 3 | | | | | | | | | FE LOU | | 6 | 3 | | | | | | | | | FF STU | Extende d 6 | | 3 | | | | Me6S09E | | | | | | FIGURE 18 - | PROGRAMMING AID | | | | | | | --- | --- | --- | --- | --- | ----------- | ---------------- | --- | --- | --- | --- | --- | Addressing Modes Imme-diate Dir-ect Indexed Exte-nded Inhe-rent 5 3 2 1 0 Instruction Forms Op # Op # Op # Op # Op # Description H· N· ·Z V· C· | ABX | | | | | | 3A | 3 1 B + X-X (Unsigned) | | | | | | ---- | --- | --- | --- | --- | --- | --- | ------------------------- | --- | --- | --- | --- | ADC ADCA 89 2 2 99 4 2 A9 B9 5 A+M+C-A I I I I I | | | | | | 4+ 2+ | 3 | | | | | | | --- | --- | --- | --- | --- | ------- | --- | --- | --- | --- | --- | --- | ADCB C9 2 2 D9 4 2 E9 4+ 2+ F9 5 3 B+M+C-B I I I I I ADD ADDA 8B 2 2 9B 4 2 AB 4+ 2+ BB 5 3 A+M-A I I I I I ADDB CB 2 2 DB 4 2 EB 4+ 2+ FB 5 3 B+M-B ·I I I I I ADDD C3 4 3 D3 6 2 E3 6+ 2+ F3 7 3 D+M:M+1-D · I I I ·I | AND | ANOA | 84 | | 94 4 | | | | | | · I | 0 · | | ---- | ----- | --- | ----- | ------ | ----------- | --------- | ----- | --- | --- | ---- | ----- | | | | | 2 2 | 2 | A4 4+ 2+ | B4 5 3 | AA M | A | | | I | ANOB C4 2 2 D4 4 2 E4 4+ 2+ F4 5 3 B A M-8 I I 0 | | ANOCC | 1C | 3 2 | | | | CC A IMM-CC | | | | 7 | | ---- | ------ | --- | ----- | --- | --- | --- | ------------ | ---------------- | --- | ----- | -------- | | ASL | ASLA | | | | | 48 | 2 1 | ~1[H I lim If-o | | B I | I I I | | | ASLB | | | | | 58 | 2 1 | | | B I | I I I | ASL 08 6 2 68 6+ 2+ 78 7 3 M c b7 bO 8 I I ·I I | ASR | A S R | A | | | | 4 7 | 2 1 | A ~ | - | 8 I | I · I | | ---- | ----- | --- | --- | --------- | ------- | ------ | ------- | ------- | ------- | ------- | ----------- | | | A S R | 8 | | | | 5 7 | 2 1 | ~ll lli | ll iHJ | 8 I | I · I | | | ASR | | | 07 6 2 | 67 | 7 | | | Eo | ·8 I | I ·I | | | | | | | 6+ 2+ | 77 3 | | 7 | | c | | 81T BITA 85 2 2 95 4 2 A5 4+ 2T B5 5 3 Bit Test A (M A AI · I I 0 · BITB C5 2 2 D5 4 2 E5 4+ 2+ F5 5 3 Bit Test B (M A BJ · I I 0 | CLR | CLRA | | | | | 4F | 2 1 O-A | | | · 0 | 1 0 0 | | ---- | ----- | --- | --- | --------- | ----------- | --------- | ---------- | --- | --- | ---- | -------- | | | CLR8 | | | | | 5F | 2 1 O-B | | | · 0 | 1 0 0 | | | CLR | | | OF 6 2 | 6F 6+ 2+ | 7F 7 3 | O-M | | | 0 | 1 0 0 | CMP CMPA 81 2 2 91 4 2 A1 4+ 2+ B1 5 3 Compare M from A 8 I I I I CMPB C1 2 2 D1 4 2 El 4+ 2+ F1 5 3 Compare M from B ·8 I I I I CMPO 10 5 4 10 7 3 10 7+ 3+ 10 8 4 Compare M:M + 1 from D I t I I | | | 83 | | 93 | A3 | B3 | | | | · | | | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | CMPS 11 5 4 11 7 3 11 7+ 3+ 11 8 4 Compare M: M + 1 from S I I I I | | | 8C | | 9C | AC | 8C | | | | · | | | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | CMPU 11 5 4 11 7 3 11 7+ 3+ 11 8 4 Compare M.M + 1 from U I I I I | | | 83 | | 93 | A3 | B3 | | | | · | | | --- | ----- | --- | ----- | --------- | ----------- | --------- | ----------------------- | --- | --- | ---- | -------- | | | | | | | | | Compare M M + 1 from X | | | · I | | | | CMPX | 8C | 4 3 | 9C 6 2 | AC 6+ 2+ | BC 7 3 | | | | | I I I | CMPY 10 5 4 10 7 3 10 7+ 3+ 10 8 4 Compare M.M + 1 from Y I I I I | | | 8C | | 9C | AC | BC | | | | · | | | ----- | ----- | --- | --------- | --------- | ----------- | --------- | ------------------------------- | --- | --- | ---- | -------- | | COM | COMA | | | | | 43 | 2 1 A-A | | | · I | I 0 1 | | | COMB | | | | | 53 | 2 1 B-B | | | · t | I 0 1 | | | COM | | | 03 6 2 | 63 6+ 2+ | 73 7 3 | liii-M | | | I | I 0 1 | | CWAI | | 3C | 2:l2C 2 | | | | CC A IMM-CC Walt for Interrupt | | | · | 7 | | | | | | | | | 1 DeCimal Adjust A | | | · I | 0 ·I | | DAA | | | | | | 19 | 2 | | | | I | | DEC | OECA | | | | | 4A | 2 1 A-1 | A | | · I | I t · | | | DECB | | | | | 5A | 2 1 B-1-B | | | · t | t t · | | | DEC | | | OA 6 2 | 6A 6+ 2+ | 7A 7 3 | M-1-M | | | · t | I t · | EOR EORA B8 2 2 98 4 2 A8 4+ 2+ B8 5 3 A-II-M-A · t I 0 · | | | | | | | | B¥M-B | | | · ·t ·t ·0 · | | | ---- | ------- | --- | ----- | --------- | ----------- | --------- | ------------------- | --- | --- | ---------------- | -------- | | | EORB | C8 | 2 2 | D8 4 2 | E8 4+ 2+ | F8 5 3 | | | | | | | EXG | R1, R2 | 1E | 8 2 | | | | R1-R22 | | | · | · | | INC | INCA | | | | | 4C | 2 1 A+ 1--A | | | · I | t t · | | | INCB | | | | | 5C | 2 1 B+ 1-B | | | · t | t t · | | | INC | | | DC 6 2 | 6C 6+ 2+ | 7C 7 3 | M+1-M | | | · ·t ·t ·t · | | | JMP | | | | OE 3 2 | 6E 3+ 2+ | 7E 4 3 | EA3_PC | | | · · · · · | | | JSR | | | | 90 7 2 | AD 7+ 2+ | BD 8 | Jump to Subroutine | | | | | | | | | | | | 3 | | | | · | · | LD LDA 86 2 2 96 4 2 A6 4+ 2+ B6 5 3 M-A · t I 0 · LDB C6 2 2 D6 4 2 E6 4+ 2+ F6 5 3 M-B · t t 0 · LDD CC 3 3 DC 5 2 EC 5+ 2+ FC 6 3 M M+1-D · t t 0 · LDS 10 4 4 10 6 3 10 6+ 3+ 10 7 4 MM+1-S t t 0 | | | CE | | DE | EE | FE | | | | · | · | | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---- | --- | | | | | | | | | | | | · t | · | LDU CE 3 3 DE 5 2 EE 5+ 2+ FE 6 3 M.M+1-U t 0 LDX 8E 3 3 9E 5 2 AE 5+ 2+ BE 6 3 M.M+1-X · t t 0 · LDY 10 4 4 10 6 3 10 6+ 3+ 10 7 4 MM+1-Y t t 0 | | | 8E | | 9E | AE | BE | | | | | | | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | · · · · · | LEA | LEAS | | | | 32 4+ 2+ | | EA3_S | | | · · · · · | | | ---- | ----- | --- | --- | --- | ----------- | --- | ------ | --- | --- | ---------- | ---- | | | LEAU | | | | 33 4+ 2+ | | EA3_U | | | · · | · · | | | LEAX | | | | 30 4+ 2+ | | EA3_X | | | · · t | · · | | | LEAY | | | | 31 4+ 2+ | | EA3_y | | | | I | LEGEND: liii Complement of M Test and set if true, cleared otherwise OP Operation Code (Hexadecimal) Transfer Into Not Affected Number of MPU Cycles H Half-carry (from bit 3) CC Condition Code Register Number of Program Bytes N Negative (sign bit) Concatenation | + Arithmetic Plus | | | | Z | Zero result | | | V Logical or | | | | | ------------------- | --- | --- | --- | --- | ------------ | --- | --- | -------------- | --- | --- | --- | Arithmetic Minus V Overflow, 2's complement A Logical and | Multiply | | | | C | | | | ¥ Logical Exclusive or | | | | | --------- | --- | --- | --- | --- | --- | --- | --- | ------------------------ | --- | --- | --- | Carry from ALU Me6S09E | | | | FIGURE 18 - | PilOGRAMMING AID (CONTINUED) | | | | | | | | --- | --- | --- | ----------- | ----------------------------- | --------- | --- | --- | --- | --- | --- | | | | | A d | dr e~ i n g · | M ~ e,s | , | , | | | | I m me-dtate Di-rect , I n d e- x e d 1 E xte-nded I nhe-rent 5 3 2 1 0 In~ruction Forms u p • up u p up Op Description H N , Z , V, C , · , , , | LSL | l S L | A | | | | 4 8 2 | 1 ~I[H liTIIIl f-o' · | | · | | | ---- | ------ | --- | ---------- | ------- | ------- | ------- | ------------------------- | ---- | ------ | ----------- | | | L S LB | | | | | 5 8 | 2 1 | | , j | , , , | | | | | | | | | | bQ | | , · , | | | LSL | | (1) 6 2 | 58 6+ | 2+ 78 | 7 3 | M | cb7 | · | | LSR 'L S R A 4 4 2 1 -.1 11 I 11111-0 · 0 , · , | | | | | | | | . ~A I | 0 | | , , | | ---- | ----- | --- | --------- | ------- | ------- | ------- | -------------------- | ------- | ------------- | ------------- | | | L SR | B | | | | 5 4 | 2 1 | | · Q | · | | | LSR | | 04 6 2 | 54 6+ | 2+ 74 | 7 3 | | b7 bQ | C · ·0 , · | | | MUL | | | | | | | A x B--D (UnsIgned) | | , , , 9, | | | | | | | | | 30 11 | 1 | | , | , , , | | NEG | N E G | A | | | | 4 0 | 2 1 A + | 1 - A | 8 | | | | NE G | B | | | | 5 0 | 2 1 8 + 1 | - B | 8 , | , , , | | | NEG | | 00 6 2 | 60 6+ | 2+ 70 | 7 3 | M+.1-M | | ·8 · · · · | | | NOP | | | | | | 12 | 2 1 No Operation | | · , , | · | · , , OR ORA 8A 2 2 9A 4 2 AA 4+ 2+ BA 5 3 AV M-A 0 · | | ORB | CA | 2 2 OA 4 2 | EA 4+ | 2+ FA | 5 3 | B V M-B | | | 0 | | --- | ----- | --- | --------------- | ------- | ------- | ----- | -------- | --- | ------------ | --- | | | ORCC | 1A | 3 2 | | | | | | · · · ·7 · | | CC V 'MM-CC | PSH | PSHS | 34 5+4 | 2 | | | | Push Registers on S .Stack | | · · · · · | | | ---- | ----- | ------- | --- | --- | --- | --- | --------------------------- | --- | ---------- | --- | | | PSHU | 36 5+4 | 2 | | | | Push ReQisters on U Stack | | | | · · · · · P\JL' PULS 35 5+ 2 Pull Registers from S Stack · · · · · PU L U 37 5+4 2 Pull Registers from U Stack · , , , , , , , , | ROl' | R O L | A | | | | 49 | 2 1 ~} ~ III 1111 ~ · , , , , | | · | | | ----- | ----- | --- | --------- | ------- | ------- | ----- | -------------------------------- | ---------- | ---------- | -------- | | | ROLB | | | | | 59 | 2 1 | | | | | | ROL | | 09 6 2 | 69 6+ | 2+ 79 | 7 3 | | | · , , · , | | | | | | | | | | | C b7 60 | , | , , | | ROR | R O R | A | | | | 4 6 | 2 1 ~}~IIIIIIIP · | | · | · | | | RO R | B | | | | 5 8 | 2 1 | | , | , · | bQ | | ROR | | 06 6 2 | 66 6+ | 2+ 76 | 7 3 | | C b7 | | 1 | | ---- | ---- | --- | --------- | ------- | ------- | -------- | ------------------------- | ------ | ------------ | --- | | RT' | | | | | | 3B 6115 | 1 Return From Interrupt | | · · · · ·7 | | , , , , | RTS | | | | | | 39 | 5 1 Return from Subroutine | | | | | ---- | --- | --- | --- | --- | --- | --- | ----------------------------- | --- | --- | --- | SBC SBCA 82 2 2 92 4 2 A2 4+ 2+ B2 5 3 A M C-A 8 , , , ·8 , ,j | | 'SBCB | C2 | 2 2 02 4 2 | E2 4+ | 2+ F2 | 5 3 | B-M-C-B | | | · | | ------ | ------ | --- | --------------- | ------- | ------- | ----- | ------------- | --------------- | --- | ---------- | | S E X | | | | | | 10 | 2 1 Sig n E | xtend B into A | , | , 0 · | • , , S T S T A 97 4 2 A 7 4 + 2 + B 7 5 3 A - M · , , o 0 ST B D 7 4 2 E 7 4 + 2 + F7 5 3 B -M · ' ·. | | STD | | DD 5 2 | ED 5+ | 2+ FD | 6 3 | D-M:M+1 | | · , | 0 · | | --- | ---- | --- | --------- | ------- | ------- | ----- | -------- | --- | ---- | ----- | STS 10 6 3 1 0 6+ 3+ 1 0 7 4 S-M:M+1 , , I 0 | | | | D F | E F | F F | | | | · | · | | --- | --- | --- | ----- | ----- | ----- | --- | --- | --- | --- | --- | S T U D F 5 2 E F 5 + 2 + FF 6 3 U - M : M + 1 · , , 0 · | | | | | | 2 + | | | | · , | , | | --- | --- | --- | --- | --- | ----- | --- | --- | --- | ----- | ---- | S T X 9F 5 2 A F 5 + B F 6 3 X- M : M + 1 O. · | | STY | | 10 6 3 | 10 | 10 | 7 4 | Y-M:M+1 | | | 0 | | --- | ---- | --- | --------- | ------- | -------- | ----- | -------- | --- | -------- | --- | | | | | 9F | AF 6+ | 3+. 8F | | | | , , , , | | , , , , SUB SUBA 80 2 2 90 4 2 AO 4+ 2+ BO 5 3 A-·M A 8 SUBB CO 2 2 DO 4 2 EO 4+ 2+ FO 5 3 B-M-B ·8 , , , , | | | | | 6+. '2+ | | 1 | | | · · · · · | | | ----- | ------- | --- | --------------- | -------- | --- | --------- | ------------------------- | --- | ---------- | --- | | | SUBD | 83 | 4 3 93 6 2 | A3 | B3 | 3 | D-M:M+1-D | | | | | SWI | SWlo | | | | | 3F 19 | 1 Software"·lnterrupf 1 | | · · · · · | | | | SWIz6 | | | | | 10 20 | 2 Software Interrupt 2 | | | | | | | | | | | 3F | | | · · · · · | | | | SWIJ6 | | | | | 11 20 | 1 Software Interrupt 3 | | | | | | | | | | | 3F | | | · · · · · | | | SYNC | | | | | | 13 ~4 1 | Synchronize to Interrupt | | · · · · · | | | TFR | R1, R2 | 1F | 6 2 | | | | R1-R2" | | · , | · | , | TSJ | T S T | A | | | | 4 D | 2 1 Te s t | A | · | ,j 0 · | | ---- | ----- | --- | ---------- | ------- | ------- | ----- | -------------- | ---- | ---- | -------------- | | | TS T | B | | | | 5 D | 2 1 T e st | 8 | · , | j 0 · | | | TST | | OD .6 2 | 6D 6+ | 2+ 70 | 7 3 | Test M | | | 0 | NOTES: 1. 'This column gives a basa cycle and byte count. To obtain total count, add the values obtained from the INDEXED ADDRESSING MODE table, Table 2 . . 2: Rl and R2 may be any pair of a bit or· any pair of 16 bit registers . .T he.a biuegisters are: A, B, CC, DP The 16 bit registers are: X, Y, U., S, D, PC . 3. EA is the effective address. 4. The PSH andPUL ·instr,uctions require 5 cycles plus 1 cycle for each byte pushed 'or pulled. 5. 5(61 means: 5 cycles if branch not taken, 6 cycles if taken !Branch instructions). SWI sets. I and F bits:··swi2 and SWI3 do not affect I imd F. 6. 7. Conditions Codes set as a direct result of the instruction. 8. Vaue of half-carry flag is undefined. | 9. | Special Casa - | Carry sat il b7 is SET. | | | | | | | | | | --- | -------------- | ------------------------ | --- | --- | --- | --- | --- | --- | --- | --- | Me6809E | | | . FIGURE 18 - | PROGRAMMING AID (CONTINUED) | | | | | | --- | --- | ------------- | ---------------------------- | --- | --- | --- | --- | Branch Instructions - | | AddreuOIg | | | | AdMdraB_li ng | | | | --- | ---------- | --- | -------------- | --- | -------------- | --- | -------- | | | | , | | | | , | | | | Relative | | 5 3 2 1 0 | | | | 2 I 0 | Il"IIItrUction Forms OP -5 Delcription ·H N• ·Z ·V ·e Instruction Form. OP -5 Desc:ription H· N· Z· V· C· .. Bee Bee 24 3 2 Branch C-O · · · · BlS BlS 23 3 2 Branch Lower | lBCC | 10 5161 | 4 Long Branch | | | | or Same | · · · · · | | ----- | -------- | --------------- | ---------- | ----- | --------- | --------------------- | ---------- | | | 24 | C=O | · · · · · | lBlS | 10 5161 | 4 Long Branch Lower | | BeS BeS 25 3 2 Branch C= 1 · · · · · 23 or· Same · · · · · · · · · · lBCS 10 5161 4 Long Branch BlT BlT 2D 3 2 8ranch Zero | | | | | | lBGT 10 5161 4 Long Branch> Zero BPl BPl 2A 3 2 Branch Plus · · · · · | | 2 E | | · · · · · | lBPl | 1 0 5161 | 4 Long Branch Plus | | | --- | ----- | --- | ------------------ | ----- | ---------- | -------------------- | --- | f-sHj-' BHI 2 2 3 2 Branch Higher · · · · · 2 A · · · · · · · · · · lBHI 10 5161 4 Long Branch Higher BRA BRA 20 3 2 Branch Always 22 · · · · · lBRA 16 5. 3 Long Branch Always · · · · · BHS BHS 24 3 2 Branch Higher BRN BRN 21 3 2 Branch Never · · · · · | | | or Same | · · · · · | LBRN | 10 | 5 4 Long Branch Never | | | ----- | -------- | ---------------------- | ---------- | ----- | --- | ------------------------ | --- | | lBHS | 10 5161 | 4 Long Branch Higher | | | 21 | | | · · · · · 24 or Same · · · · · BSR BSR aD 7 2 Branch to S·ubroutine · · · · · BlE BlE 2F 3 2 Branch:s Zero · · · · · lBSR 17 9 .3 Long Branch to lBlE 10 5161 4 Long Bran9h:s Zero Subroutine · · · · · | | 2F | | · · · · · | | | | | | --- | --- | --- | ---------- | --------- | --- | ----------------- | ---------- | | | | | | BVe BVC | 28 | 3 2 Branch V=O | · · · · · | BlO BlO 25 3 2 Branch lower · · · · · lBVC 10 5161 4 Long Branch | lBlO | 10 5161 | 4 Long Branch Lower | | | 2B | v=o | · · · · · | | ----- | --------- | --------------------- | --- | --------- | --------- | ---------------- | ---------- | | | 25 | | | | 29 | 3 | · · · | | | | | | BVS BVS | | 2 B.ranch V-1 | | | | | | | lBVS | 10 5161 | 4 Lc;mg Branch | .1. 1 | 29 V=I SIMPLE BRANCHES | | | OP | | SIMPLE CONDITIONAL BRANCHES (Notes 1-41 | | | | | ----- | --- | ----------- | --- | ---------------------------------------- | ----- | ----------- | -------- | | BRA | | 20 3 2 | | T8111 | True | OP F. ... | OP | | LBRA | | 16 5 3 | | N=1 | BMI | 2B | BPl 2A | | BRN | | 21 3 2 | | | | | | | | | | | Z=1 | BEQ | 27 | BNE 26 | | lBRN | | 1021 5 4 | | V=1 | BVS | 29 BVC | 28 | | BSA | | 80 7 2 | | C=1 | BCS | 25 BCC | 24 | | lBSR | | 17 9 3 | | | | | | SIGNED CONDITIONAL BRANCHES (Notes 1-4) UNSIGNED CONDmONAL BRANCHES (Notes 1-41 | T8111 | True | OP False | OP | T8111 | True | .OP False | OP | | ------ | ----- | ---------- | --- | ------ | ----- | ----------- | --- | | r>m | BGT | 2E BlE | 2F | r>m | BHI | 22 BlS | 23 | | | | | | | BHS | .24 BlO | 25 | | r~m | BGE | 2C BlT | 20 | r~m | | | | | .r=m | BEQ | 27 BNE | 26 | r=m | BEQ | 27 BNE | 26 | | rsm | BlE | 2F BGT | 2E | rsm | BLS | 23 BHI | 22 | | r