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systemc-code-database-new / file.txt
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 #include <systemc.h>
SC_MODULE (hello) { // module named hello
SC_CTOR (hello) { //constructor phase, which is empty in this case
}
void say_hello() {
std::cout << "Hello World!" << std::endl;
}
};
int sc_main(int argc, char* argv[]) {
hello h("hello");
h.say_hello();
return 0;
}
/*
* @ASCK
*/
#include <systemc.h>
SC_MODULE (ALU) {
sc_in <sc_int<8>> in1; // A
sc_in <sc_int<8>> in2; // B
sc_in <bool> c; // Carry Out // in this project, this signal is always 1
// ALUOP // has 5 bits by merging: opselect (4bits) and first LSB bit of opcode (1bit)
sc_in <sc_uint<5>> aluop;
sc_in <sc_uint<3>> sa; // Shift Amount
sc_out <sc_int<8>> out; // Output
/*
** module global variables
*/
//
SC_CTOR (ALU){
SC_METHOD (process);
sensitive << in1 << in2 << aluop;
}
void process () {
sc_int<8> a = in1.read();
sc_int<8> b = in2.read();
bool cin = c.read();
sc_uint<5> op = aluop.read();
sc_uint<3> sh = sa.read();
switch (op){
case 0b00000 :
out.write(a);
break;
case 0b00001 :
out.write(++a);
break;
case 0b00010 :
out.write(a+b);
break;
case 0b00011 :
out.write(a+b+cin);
break;
case 0b00100 :
out.write(a-b);
break;
case 0b00101 :
out.write(a-b-cin);
break;
case 0b00110 :
out.write(--a);
break;
case 0b00111 :
out.write(b);
break;
case 0b01000 :
case 0b01001 :
out.write(a&b);
break;
case 0b01010 :
case 0b01011 :
out.write(a|b);
break;
case 0b01100 :
case 0b01101 :
out.write(a^b);
break;
case 0b01110 :
case 0b01111 :
out.write(~a);
break;
case 0b10000 :
case 0b10001 :
case 0b10010 :
case 0b10011 :
case 0b10100 :
case 0b10101 :
case 0b10110 :
case 0b10111 :
out.write(a>>sh);
break;
default:
out.write(a<<sh);
break;
}
}
};
/*
* @ASCK
*/
#include <systemc.h>
SC_MODULE (Acc) {
sc_in <sc_int<8>> mem_data;
sc_in <bool> call;
sc_out <bool> read, write;
sc_out <sc_uint<13>> addr;
sc_out <sc_int<8>> data;
/*
** module global variables
*/
SC_CTOR (Acc){
SC_THREAD (process);
sensitive << call;
}
void process () {
while(true){
wait();
if(call.read()==1){
std::cout << "@@-_.|*^<!! STARTING ACCELERATOR !!>^*|._-@@" << endl;
operation();
}
}
}
void operation () {
// store value 10 to address 11
write_to_mem (11, 10);
// read from address 5 of memory : data=7 (this data has already stored by micro processor)
sc_int<8> a = read_from_mem(5);
// read from address 11 of memory : data=10
sc_int<8> b = read_from_mem(11);
// a + b
sc_int<8> c = a+b;
// store c to address 20 of memory
write_to_mem (20, c);
// end the acc task and begin the micro task
micro_notif();
}
/*
** notify micro processor that accelerator job is done and return back to the micro processor job
*/
void micro_notif (){
micro_acc_ev.notify();
now_is_call = false;
}
// read from memory
sc_int<8> read_from_mem (int ad) {
read.write(1);
write.write(0);
addr.write(ad);
wait(acc_mem_read_ev);
no_read_write();
wait(10, SC_NS);
return mem_data.read();
}
// write to memory
void write_to_mem (int ad, int dt) {
read.write(0);
write.write(1);
addr.write(ad);
data.write(dt);
wait(acc_mem_write_ev);
no_read_write();
wait(1, SC_NS);
}
// change the read and write signals not to read and not to write
void no_read_write () {
read.write(0);
write.write(0);
}
};
/*
* @ASCK
*/
#include <systemc.h>
SC_MODULE (Bus) {
sc_in_clk clk;
sc_in <bool> req; // X DIDN'T USED! X
sc_in <bool> read;
sc_in <bool> write;
sc_in <bool> call;
sc_in <sc_uint<13>> addr; // for both Mem. and Acc.
sc_in <sc_int<8>> data;
sc_out <bool> ack; // X DIDN'T USED! X
sc_out <bool> read_out;
sc_out <bool> write_out;
sc_out <bool> call_out;
sc_out <sc_uint<13>> addr_out; // for both Mem. and Acc.
sc_out <sc_int<8>> data_out;
/*
** module global variables
*/
SC_CTOR (Bus){
SC_METHOD (process);
sensitive << clk.pos();
}
void process () {
ack.write(req.read());
read_out.write(read.read());
write_out.write(write.read());
call_out.write(call.read());
addr_out.write(addr.read());
data_out.write(data.read());
}
};
/*
* @ASCK
*/
#include <systemc.h>
SC_MODULE (Controller) {
sc_in <sc_uint<4>> opcode, opselect;
sc_out <sc_uint<5>> aluOp;
sc_out <bool> regWrite, r, w, aluMux, regMux, wbMux, call;
/*
** module global variables
*/
sc_uint<4> opcd, opsel;
sc_uint<5> op;
//tmp
int c = 0;
SC_CTOR (Controller){
SC_METHOD (process);
sensitive << opcode << opselect;
}
void process () {
opcd = opcode.read();
opsel = opselect.read();
switch (opcd){
case 0b0000:
case 0b0001:
op = opsel;
op = opsel << 1;
op[0] = opcd[0];
aluOp.write(op); // concatinated to produce aluop
regWrite.write(1);
r.write(0);
w.write(0);
regMux.write(0); // r1 = rs
aluMux.write(0); // B = Rr2
wbMux.write(0); // use alu result
call.write(0);
break;
/*
** Transfer Imm to the Register rd
*/
case 0b0010:
aluOp.write(0b00111); // transfer B (rd = Imm)
regWrite.write(1);
r.write(0);
w.write(0);
regMux.write(0);
aluMux.write(1); // B = imm
wbMux.write(0);
call.write(0);
break;
/*
** Add Imm with register rd content and move it to the Register rd
*/
case 0b0011:
aluOp.write(0b00100); // Add A and B (rd += Imm)
regWrite.write(1);
r.write(0);
w.write(0);
regMux.write(1);
aluMux.write(1);
wbMux.write(0);
call.write(0);
break;
/*
** LOAD from Imm address of memory to rd
*/
case 0b0100:
aluOp.write(0);
regWrite.write(1);
r.write(1);
w.write(0);
regMux.write(0);
aluMux.write(0);
wbMux.write(1); // use memory result
call.write(0);
break;
/*
** STORE rd content to imm address of memory
*/
case 0b0101:
aluOp.write(0); // transfer A
regWrite.write(0); // don't write back to register
r.write(0);
w.write(1);
regMux.write(1); // r1 = reg (rd)
aluMux.write(0); // ignorable!
wbMux.write(0); // ignorable!
call.write(0);
break;
/*
** NOP
*/
case 0b1111:
aluOp.write(0);
regWrite.write(0);
r.write(0);
w.write(0);
regMux.write(0);
aluMux.write(0);
wbMux.write(0);
call.write(0);
break;
/*
** CALL Acc.
*/
default:
regWrite.write(0); // don't write back to register
r.write(0);
w.write(0);
call.write(1);
break;
}
}
};
/*
* @ASCK
*/
#include <systemc.h>
SC_MODULE (EXE) {
sc_in_clk clk;
sc_in <sc_int<8>> prev_result;
sc_in <sc_int<13>> prev_Imm;
sc_in <bool> prev_r;
sc_in <bool> prev_w;
sc_in <bool> prev_WbMux;
sc_in <bool> prev_call;
sc_in <bool> prev_regWrite;
sc_in <sc_uint<3>> prev_rd;
sc_out <sc_int<8>> next_result;
sc_out <sc_int<13>> next_Imm;
sc_out <bool> next_r;
sc_out <bool> next_w;
sc_out <bool> next_WbMux;
sc_out <bool> next_call;
sc_out <bool> next_regWrite;
sc_out <sc_uint<3>> next_rd;
/*
** module global variables
*/
SC_CTOR (EXE){
SC_THREAD (process);
sensitive << clk.pos();
}
void process () {
while(true){
wait();
if(now_is_call){
wait(micro_acc_ev);
}
next_result.write(prev_result.read());
next_Imm.write(prev_Imm.read());
next_r.write(prev_r.read());
next_w.write(prev_w.read());
next_WbMux.write(prev_WbMux.read());
next_call.write(prev_call.read());
next_regWrite.write(prev_regWrite);
next_rd.write(prev_rd.read());
}
}
};
/*
* @ASCK
*/
#include <systemc.h>
SC_MODULE (ID) {
sc_in_clk clk;
sc_in <sc_int<8>> prev_A;
sc_in <sc_int<8>> prev_B;
sc_in <sc_int<13>> prev_Imm;
sc_in <sc_uint<3>> prev_Sa;
sc_in <sc_uint<5>> prev_AluOp;
sc_in <bool> prev_r;
sc_in <bool> prev_w;
sc_in <bool> prev_AluMux;
sc_in <bool> prev_WbMux;
sc_in <bool> prev_call;
sc_in <bool> prev_regWrite;
sc_in <sc_uint<3>> prev_rd;
sc_out <sc_int<8>> next_A;
sc_out <sc_int<8>> next_B;
sc_out <sc_int<13>> next_Imm;
sc_out <sc_uint<3>> next_Sa;
sc_out <sc_uint<5>> next_AluOp;
sc_out <bool> next_r;
sc_out <bool> next_w;
sc_out <bool> next_AluMux;
sc_out <bool> next_WbMux;
sc_out <bool> next_call;
sc_out <bool> next_regWrite;
sc_out <sc_uint<3>> next_rd;
/*
** module global variables
*/
SC_CTOR (ID){
SC_THREAD (process);
sensitive << clk.pos();
}
void process () {
while(true){
wait();
if(now_is_call){
wait(micro_acc_ev);
}
next_A.write(prev_A.read());
next_B.write(prev_B.read());
next_Imm.write(prev_Imm.read());
next_Sa.write(prev_Sa.read());
next_AluOp.write(prev_AluOp.read());
next_AluMux.write(prev_AluMux.read());
next_r.write(prev_r.read());
next_w.write(prev_w.read());
next_WbMux.write(prev_WbMux.read());
next_call.write(prev_call.read());
next_regWrite.write(prev_regWrite);
next_rd.write(prev_rd.read());
}
}
};
/*
* @ASCK
*/
#include <systemc.h>
SC_MODULE (IF) {
sc_in_clk clk;
sc_in <sc_uint<20>> prev_data;
sc_out <sc_uint<20>> next_data;
/*
** module global variables
*/
SC_CTOR (IF){
SC_THREAD (process);
sensitive << clk.pos();
}
void process () {
while(true){
wait();
if(now_is_call){
cout<<"\t\t\t\t*******************" << endl;
wait(micro_acc_ev);
}
next_data.write(prev_data.read());
}
}
};
/*
* @ASCK
*/
#include <systemc.h>
SC_MODULE (IR) {
sc_in <sc_uint<14>> addr;
sc_out <sc_uint<20>> inst;
/*
** module global variables
*/
sc_uint<20> mem[819]; // 819 rows and 819*20=16380 bits = (16KB - 4bits) ~= 16KB
int instNum = 50;
sc_uint<20> instruction[50] = {
// 0b01234567890123456789
0b00000000000000000000,
0b00100000000000000111, // transfer (r0 <- 7): 7
0b00010010010000000000, // inc (r1++): 1
//stall for achieving the correct register data - sub
0b11110000000000000000, //stall
0b11110000000000000000, //stall
0b11110000000000000000, //stall
0b00000110000010000010, // sub (r3 <-r0 - r1): 6
0b11110000000000000000, //stall
0b11110000000000000000, //stall
0b11110000000000000000, //stall
0b00011000110010000001, // addc (r4 <- r3 + r1 + 1): 8
0b11110000000000000000, //stall
0b11110000000000000000, //stall
0b11110000000000000000, //stall
0b00001001000000101001, // shiftR (r4 >> 2): 2
0b01010000000000000101, // stroe (mem[5] <= r0) : 7
0b01001010000000000101, // load (r5 <= mem[5]) : 7
0b01100000000000000000, // do accelerator
0b01000100000000010100, // load (r2 <= mem[20]) : 17 => 0x11
0b11110000000000000000, //nop
0b11110000000000000000, //nop
0b11110000000000000000, //nop
0b11110000000000000000, //nop
0b11110000000000000000, //nop
0b11110000000000000000 //nop
};
SC_CTOR (IR){
SC_METHOD (process);
sensitive << addr;
for(int i=0; i<instNum; i++){
mem[i] = instruction[i];
}
// filling out other rows with a nop opcode
for(int i=instNum; i<819; i++){
mem[i] = 0b11110000000000000000;
}
}
void process () {
if(addr.read() < 819){
inst.write(mem[addr.read()]);
}
else{
inst.write(0);
}
}
};
/*
* @ASCK
*/
#include <systemc.h>
SC_MODULE (Memory) {
sc_in <bool> r_nw;
sc_in <sc_uint<13>> addr;
sc_in <sc_int<8>> data;
sc_out <sc_int<8>> out;
/*
** module global variables
*/
sc_int<8> mem[8192] = {0}; // 2^13 rows
bool done = false;
SC_CTOR (Memory){
SC_METHOD (process);
sensitive << r_nw << addr << data;
}
void process () {
if(done){
return;
}
if(addr.read() < 8192){
if(r_nw.read()){
out.write(mem[addr.read()]);
}
else{
mem[addr.read()] = data.read();
out.write(mem[addr.read()]);
}
}
else{
out.write(0);
}
}
};
/*
* @ASCK
*/
#include <systemc.h>
#include <./PC.cpp>
#include <./IR.cpp>
#include <./IF.cpp>
#include <./Mux3.cpp>
#include <./Mux8.cpp>
#include <./RegFile.cpp>
#include <./Controller.cpp>
#include <./ID.cpp>
#include <./ALU.cpp>
#include <./EXE.cpp>
#include <./WB.cpp>
#include <bitset>
SC_MODULE (Micro) {
sc_in_clk clk;
sc_in <sc_int<8>> mem_data;
sc_out <bool> read, write, call;
sc_out <sc_uint<13>> addr;
sc_out <sc_int<8>> data;
// testing wires
sc_out <sc_uint<5>> test_aluOp;
sc_out <sc_uint<14>> test_pc;
sc_out <sc_uint<20>> test_inst;
sc_out <sc_int<8>> reg_dump[8];
// sc_out <bool> test_regWrite, test_r_nw, test_aluMux, test_regMux, test_wbMux, test_call;
/*
** module global variables
*/
/*
** SIGNALS
*/
// -----
sc_uint<14> tmp_pc_prev_addr;
sc_signal<sc_uint<14>> pc_prev_addr;
sc_signal<sc_uint<14>> pc_next_addr;
sc_signal <sc_uint<20>> ir_inst;
sc_signal <sc_uint<20>> if_next_data;
sc_signal <sc_uint<4>> opcode;
sc_signal <sc_uint<3>> rd;
sc_signal <sc_uint<3>> rs;
sc_signal <sc_uint<3>> rt;
sc_signal <sc_uint<3>> sa;
sc_signal <sc_uint<4>> opselect;
sc_uint<20> tmp;
sc_signal <sc_int<13>> offset;
// controller output signal
sc_signal <sc_uint<5>> aluOp;
sc_signal <bool> regWrite, r, w, aluMux, regMux, wbMux, acc_call;
sc_signal <sc_uint<3>> mux_reg_res;
/*
** Register File signals
*/
sc_signal <sc_int<8>> Rr1;
sc_signal <sc_int<8>> Rr2;
sc_signal <sc_int<8>> regs[8];
sc_signal <sc_int<8>> id_next_A;
sc_signal <sc_int<8>> id_next_B;
sc_signal <sc_int<13>> id_next_Imm;
sc_signal <sc_uint<3>> id_next_Sa;
sc_signal <sc_uint<5>> id_next_AluOp;
sc_signal <bool> id_next_r;
sc_signal <bool> id_next_w;
sc_signal <bool> id_next_AluMux;
sc_signal <bool> id_next_WbMux;
sc_signal <bool> id_next_call;
sc_signal <bool> id_next_regWrite;
sc_signal <sc_uint<3>> id_next_rd;
sc_signal <sc_int<8>> alu_in_B;
sc_signal <sc_int<8>> id_nex_imm_8bits;
sc_signal <sc_int<8>> alu_out;
sc_signal<bool> carry;
sc_signal <sc_int<8>> exe_next_result;
sc_signal <sc_int<13>> exe_next_Imm;
sc_signal <bool> exe_next_r;
sc_signal <bool> exe_next_w;
sc_signal <bool> exe_next_WbMux;
sc_signal <bool> exe_next_call;
sc_signal <bool> exe_next_regWrite;
sc_signal <sc_uint<3>> exe_next_rd;
sc_signal <sc_int<8>> wb_next_result;
sc_signal <sc_int<8>> wb_prev_mem_data;
sc_signal <sc_int<8>> wb_next_mem_data;
sc_signal <bool> wb_next_WbMux;
sc_signal <bool> wb_next_regWrite;
sc_signal <sc_uint<3>> wb_next_rd;
sc_signal<sc_uint<13>> mem_addr;
sc_signal <sc_int<8>> regFileData;
sc_int<13> tmp_id_next_Imm;
sc_signal <sc_int<8>> sig_mem_data;
// -----
PC *pc;
IR *ir;
IF *iff;
Controller *ctl;
Mux3 *mux_reg;
ID *id;
Mux8 *alu_in_mux;
ALU *alu;
EXE *exe;
WB *wb;
Mux8 *wb_out_mux;
RegFile *reg_file;
SC_CTOR (Micro){
SC_THREAD (process);
sensitive << clk.pos();
pc = new PC("PC");
ir = new IR("IR");
iff = new IF ("IF");
ctl = new Controller ("Controller");
mux_reg = new Mux3 ("RegMux3bits");
id = new ID ("ID");
alu_in_mux = new Mux8 ("AluInputMux");
alu = new ALU ("ALU");
exe = new EXE ("EXE");
wb = new WB ("WB");
wb_out_mux = new Mux8 ("WBOutputMux");
reg_file = new RegFile ("RegisterFile");
pc->clk(clk);
pc->prev_addr(pc_prev_addr);
pc->next_addr(pc_next_addr);
ir->addr(pc_next_addr);
ir->inst(ir_inst);
iff->clk(clk);
iff->prev_data(ir_inst);
iff->next_data(if_next_data);
//ctl (opcode, opselect, aluOp, regWrite, r_nw, aluMux, regMux, wbMux, acc_call);
ctl->opcode(opcode);
ctl->opselect(opselect);
ctl->aluOp(aluOp);
ctl->regWrite(regWrite);
ctl->r(r);
ctl->w(w);
ctl->aluMux(aluMux);
ctl->regMux(regMux);
ctl->wbMux(wbMux);
ctl->call(acc_call);
//mux_reg (regMux, rs, rd, mux_reg_res);
mux_reg->sel(regMux);
mux_reg->in0(rs);
mux_reg->in1(rd);
mux_reg->out(mux_reg_res);
//id (clk, Rr1, id_next_A, Rr2, id_next_B, offset, id_next_Imm, sa, id_next_Sa, aluOp, id_next_AluOp, r_nw, id_next_MemOp, aluMux, id_next_AluMux, wbMux, id_next_WbMux, acc_call, id_next_call, rd, id_next_rd);
id->clk(clk);
id->prev_A(Rr1);
id->next_A(id_next_A);
id->prev_B(Rr2);
id->next_B(id_next_B);
id->prev_Imm(offset);
id->next_Imm(id_next_Imm);
id->prev_Sa(sa);
id->next_Sa(id_next_Sa);
id->prev_AluOp(aluOp);
id->next_AluOp(id_next_AluOp);
id->prev_r(r);
id->next_r(id_next_r);
id->prev_w(w);
id->next_w(id_next_w);
id->prev_AluMux(aluMux);
id->next_AluMux(id_next_AluMux);
id->prev_WbMux(wbMux);
id->next_WbMux(id_next_WbMux);
id->prev_call(acc_call);
id->next_call(id_next_call);
id->prev_regWrite(regWrite);
id->next_regWrite(id_next_regWrite);
id->prev_rd(rd);
id->next_rd(id_next_rd);
/*
** Mux 8 for immediate or B
*/
//alu_in_mux (id_next_AluMux, id_next_B, id_nex_imm_8bits, alu_in_B);
alu_in_mux->sel(id_next_AluMux);
alu_in_mux->in0(id_next_B);
alu_in_mux->in1(id_nex_imm_8bits);
alu_in_mux->out(alu_in_B);
/*
** ALU
*/
carry = 1;
//alu (id_next_A, alu_in_B, carry, id_next_AluOp, id_next_Sa, alu_out);
alu->in1(id_next_A);
alu->in2(alu_in_B);
alu->c(carry);
alu->aluop(id_next_AluOp);
alu->sa(id_next_Sa);
alu->out(alu_out);
/*
** EXE
*/
//exe (clk, alu_out, exe_next_result, id_next_Imm, exe_next_Imm, id_next_MemOp, exe_next_MemOp, id_next_WbMux, exe_next_WbMux, id_next_call, exe_next_call, id_next_rd, exe_next_rd);
exe->clk(clk);
exe->prev_result(alu_out);
exe->next_result(exe_next_result);
exe->prev_Imm(id_next_Imm);
exe->next_Imm(exe_next_Imm);
exe->prev_r(id_next_r);
exe->next_r(exe_next_r);
exe->prev_w(id_next_w);
exe->next_w(exe_next_w);
exe->prev_WbMux(id_next_WbMux);
exe->next_WbMux(exe_next_WbMux);
exe->prev_call(id_next_call);
exe->next_call(exe_next_call);
exe->prev_regWrite(id_next_regWrite);
exe->next_regWrite(exe_next_regWrite);
exe->prev_rd(id_next_rd);
exe->next_rd(exe_next_rd);
/*
** WB
*/
//wb (clk, exe_next_result, wb_next_result, wb_prev_mem_data, wb_next_mem_data, exe_next_WbMux, wb_next_WbMux, exe_next_rd, wb_next_rd);
wb->clk(clk);
wb->prev_alu_result(exe_next_result);
wb->next_alu_result(wb_next_result);
wb->prev_mem_result(mem_data);
wb->next_mem_result(wb_next_mem_data);
wb->prev_WbMux(exe_next_WbMux);
wb->next_WbMux(wb_next_WbMux);
wb->prev_regWrite(exe_next_regWrite);
wb->next_regWrite(wb_next_regWrite);
wb->prev_rd(exe_next_rd);
wb->next_rd(wb_next_rd);
/*
** Mux 8 bits for WB
*/
//wb_out_mux (wb_next_WbMux, wb_next_result, wb_next_mem_data, regFileData);
wb_out_mux->sel(wb_next_WbMux);
wb_out_mux->in0(wb_next_result);
wb_out_mux->in1(wb_next_mem_data);
wb_out_mux->out(regFileData);
/*
** Register File Module
*/
//reg_file (clk, regWrite, mux_reg_res, rt, wb_next_rd, regFileData, Rr1, Rr2);
reg_file->clk(clk);
reg_file->regWrite(wb_next_regWrite);
reg_file->r1(mux_reg_res);
reg_file->r2(rt);
reg_file->r3(wb_next_rd);
reg_file->data(regFileData);
reg_file->Rr1(Rr1);
reg_file->Rr2(Rr2);
for (int i=0; i<8; i++){
reg_file->r[i](regs[i]);
}
}
/*
** CLOCK THREAD FOR DOING PROCESSES
*/
void process(){
while(true){
if(id_next_call){
now_is_call = true;
}
wait();
///////////////
pcInc();
decode();
ImmTo8bits();
busAccess();
tester();
/////////////
/*
** HANDLE ACCELERATOR CALLS
*/
if(exe_next_call.read()){
call.write(1);
pc_prev_addr = (pc_prev_addr.read());
wait(micro_acc_ev);
pc_prev_addr = (pc_prev_addr.read()) + 1;
}
}
}
void pcInc (){
// increment the pc
tmp_pc_prev_addr = pc_prev_addr.read();
pc_prev_addr = ++tmp_pc_prev_addr;
}
void decode (){
/*
** split next instruction to the corresponding signals (Instruction Decode)
*/
tmp = ir_inst.read();
opcode = tmp.range(19, 16);
opselect = tmp.range(3, 0);
rd = tmp.range(15, 13);
rs = tmp.range(12, 10);
rt = tmp.range(9, 7);
sa = tmp.range(6, 4);
offset = (sc_int<13>) tmp.range(12, 0);
}
void ImmTo8bits (){
/*
** Mux 8 for immediate or B
*/
tmp_id_next_Imm = offset.read();
id_nex_imm_8bits = (tmp_id_next_Imm.range(7, 0));
}
void busAccess (){
/*
** ACCESS MEM. VIA BUS
*/
wb_prev_mem_data = mem_data.read();
mem_addr = (sc_uint<13>) id_next_Imm.read();
read.write(exe_next_r.read());
write.write(exe_next_w.read());
addr.write(mem_addr.read());
data.write(exe_next_result.read());
call.write(0); // setting of the value is also performs in process function
}
void tester () {
// testing wires
for(int i=0; i<8; i++){
reg_dump[i].write(regs[i].read());
}
test_aluOp.write(aluOp.read());
test_pc.write(pc_next_addr.read());
test_inst.write((sc_uint<20>)if_next_data.read());
print();
}
void print(){
cout << "pc addr ((FETCH)) :\t" << pc_next_addr << endl << endl;
cout << "IF inst ((DECODE)):\t" << std::hex << if_next_data << endl;
cout << "controller| opcode:\t" << opcode << endl;
cout << "regFile| regMux :\t" << regMux << endl;
cout << "regFile| r1 :\t" << mux_reg_res << endl;
cout << "regFile| r2 :\t" << rt << endl;
cout << "regFile| r3 :\t" << wb_next_rd << endl;
cout << "regFile| imm :\t" << offset << endl;
cout << "regFile| data :\t" << wb_next_rd << endl;
cout << "regFile| regWrite :\t" << wb_next_regWrite << endl << endl;
cout << "A ((EXE)) :\t" << id_next_A << endl;
cout << "B :\t" << alu_in_B << endl;
cout << "aluOp :\t" << id_next_AluOp << endl;
cout << "aluMux :\t" << id_next_AluMux << endl;
cout << "imm :\t" << id_next_Imm << endl;
cout << "aluOut :\t" << alu_out << endl << endl;
cout << "imm :\t" << exe_next_Imm << endl;
cout << "data_in ((MEM)) :\t" << exe_next_result << endl;
cout << "addr :\t" << exe_next_Imm << endl;
cout << "read :\t" << exe_next_r << endl;
cout << "write :\t" << exe_next_w << endl;
cout << "data_out :\t" << mem_data << endl << endl;
cout << "data ((WB)) :\t" << regFileData << endl;
cout << "rd :\t" << exe_next_rd << endl;
cout << "wbMux :\t" << wb_next_WbMux << endl << endl;
}
};
/*
* @ASCK
*/
#include <systemc.h>
SC_MODULE (Mux3) {
sc_in <bool> sel;
sc_in <sc_uint<3>> in0;
sc_in <sc_uint<3>> in1;
sc_out <sc_uint<3>> out;
/*
** module global variables
*/
SC_CTOR (Mux3){
SC_METHOD (process);
sensitive << in0 << in1 << sel;
}
void process () {
if(!sel.read()){
out.write(in0.read());
}
else{
out.write(in1.read());
}
}
};
/*
* @ASCK
*/
#include <systemc.h>
SC_MODULE (Mux8) {
sc_in <bool> sel;
sc_in <sc_int<8>> in0;
sc_in <sc_int<8>> in1;
sc_out <sc_int<8>> out;
/*
** module global variables
*/
SC_CTOR (Mux8){
SC_METHOD (process);
sensitive << in0 << in1 << sel;
}
void process () {
if(!sel.read()){
out.write(in0.read());
}
else{
out.write(in1.read());
}
}
};
/*
* @ASCK
*/
#include <systemc.h>
SC_MODULE (PC) {
sc_in <bool> clk;
sc_in <sc_uint<14>> prev_addr;
sc_out <sc_uint<14>> next_addr;
/*
** module global variables
*/
SC_CTOR (PC){
SC_METHOD (process);
sensitive << clk.pos();
}
void process () {
next_addr.write(prev_addr.read());
}
};
/*
* @ASCK
*/
#include <systemc.h>
SC_MODULE (RegFile) {
sc_in_clk clk;
sc_in <bool> regWrite;
sc_in <sc_uint<3>> r1;
sc_in <sc_uint<3>> r2;
sc_in <sc_uint<3>> r3;
sc_in <sc_int<8>> data;
sc_out <sc_int<8>> Rr1;
sc_out <sc_int<8>> Rr2;
//testing wires
sc_out <sc_int<8>> r[8];
/*
** module global variables
*/
sc_int<8> reg[8]; // 8 registers in register file
int c = 0;
SC_CTOR (RegFile){
SC_METHOD (process);
sensitive << regWrite << r1 << r2 << r3 << data;
}
void process () {
// whether the regWrite is 0 or not, the Rr1 and Rr2 have the corresponding output!
Rr1.write(reg[r1.read()]);
Rr2.write(reg[r2.read()]);
if(regWrite.read() == 1){
reg[r3.read()] = data.read();
}
for (int i=0; i< 8; i++){
r[i].write(reg[i]);
}
if (c++ == 32) {
reg[0] = 3;
}
}
};
/*
* @ASCK
*/
#include <systemc.h>
/*
** GLOBAL EVENT FOR MICRO-ACC
*/
//////////////////////////
sc_event micro_acc_ev;///
////////////////////////
/*
** GLOBAL EVENT FOR ACC-MEMORY -> READ MODE
*/
//////////////////////////
sc_event acc_mem_read_ev;///
////////////////////////
/*
** GLOBAL EVENT FOR ACC-MEMORY -> WRITE MODE
*/
//////////////////////////
sc_event acc_mem_write_ev;///
////////////////////////
/*
** variable for checking if IF/ID/EXE/WB should have been stopped after call=1 on memory-access stage or not!
*/
bool now_is_call = false;
#include <./Micro.cpp>
#include <./Bus.cpp>
#include <./Memory.cpp>
#include <./Acc.cpp>
SC_MODULE(System)
{
sc_in_clk clk;
sc_in_clk clk_bus;
// testing wires
sc_out<sc_uint<14>> pc;
sc_out<sc_uint<5>> test_aluop;
sc_out<sc_int<8>> reg_dump[8];
/*
** module global variables
*/
//
// SIGNALS
//
// MICRO
sc_signal<sc_int<8>> micro_data_in; // input
sc_signal<bool> micro_read, micro_write, micro_call;
sc_signal<sc_uint<13>> micro_addr;
sc_signal<sc_int<8>> micro_data_out; // output
// BUS
sc_signal<bool> req;
sc_signal<bool> read_in;
sc_signal<bool> write_in;
sc_signal<bool> call_in;
sc_signal<sc_uint<13>> addr_in; // for both Mem. and Acc.
sc_signal<sc_int<8>> data_in;
//// INPUTS -up- / -down- OUTPUTS
sc_signal<bool> ack;
sc_signal<bool> read_out;
sc_signal<bool> write_out;
sc_signal<bool> call_out;
sc_signal<sc_uint<13>> addr_out; // for both Mem. and Acc.
sc_signal<sc_int<8>> data_out;
// MEMORY
sc_signal<sc_int<8>> mem_data_in, mem_data_out;
sc_signal<sc_uint<13>> mem_addr;
sc_signal<bool> r_nw;
// ACC1
sc_signal <bool> acc_call_in, acc_read, acc_write;
sc_signal <sc_uint<13>> acc_addr_out;
sc_signal <sc_int<8>> acc_data_in, acc_data_out;
//TESTING SIGNALS
sc_signal<sc_uint<5>> test_aluOp;
sc_signal<sc_uint<14>> test_pc;
sc_signal<sc_uint<20>> test_inst;
/*
** CREATE POINTER TO COMPONENTS
*/
Micro *micro;
Bus *bus;
Memory *memory;
Acc *acc;
SC_CTOR(System)
{
SC_METHOD(process);
sensitive << clk_bus.pos();
micro = new Micro("Micro");
bus = new Bus("Bus");
memory = new Memory("MEMORY");
acc = new Acc("Acc1");
micro->clk(clk);
micro->mem_data(micro_data_in);
micro->read(micro_read);
micro->write(micro_write);
micro->call(micro_call);
micro->addr(micro_addr);
micro->data(micro_data_out);
micro->test_aluOp(test_aluOp);
micro->test_pc(test_pc);
micro->test_inst(test_inst);
for (int i = 0; i < 8; i++)
{
micro->reg_dump[i](reg_dump[i]);
}
req = 1;
bus->clk(clk_bus);
bus->req(req);
bus->read(read_in);
bus->write(write_in);
bus->call(micro_call);
bus->addr(addr_in);
bus->data(data_in);
bus->ack(ack);
bus->read_out(read_out);
bus->write_out(write_out);
bus->call_out(call_out);
bus->addr_out(addr_out);
bus->data_out(data_out);
r_nw = 1;
memory->r_nw(r_nw);
memory->addr(mem_addr);
memory->data(mem_data_in);
memory->out(mem_data_out);
acc->mem_data(acc_data_in);
acc->call(acc_call_in);
acc->read(acc_read);
acc->write(acc_write);
acc->addr(acc_addr_out);
acc->data(acc_data_out);
}
int c = 0; //clk counter for printing
/*
** FLAG: if the **acc_read** of accelerator is enabled then we know that after 2 clks
** we will have the memory data on the bus data_out!
**
** BRIEF: this flag acknowledge us whether we have to notify the acc_mem_read_ev or not!
*/
int notify_flag_read = 0;
int notify_flag_write = 0;
void process()
{
// testing wires
test_aluop.write(test_aluOp.read());
pc.write(test_pc.read());
cout << "-----------------------------------------------" << endl;
cout << "\t-___ " << "bus_clk: 0X" <<c++ << " ___-" << endl << endl;
/*
** Micro - MEMORY - ACC
*/
mem_addr = addr_out.read();
mem_data_in = data_out.read();
micro_data_in = data_out.read();
acc_data_in = data_out.read();
acc_call_in = call_out.read();
if (read_out.read() || write_out.read() || call_out.read()){
if (read_out.read()){
r_nw = read_out.read();
data_in = mem_data_out.read();
}
else if (write_out.read()){
r_nw = !(write_out.read());
}
}
////////////////////////HANDLE ACC READ/WRITE////////////////////////
if (notify_flag_write !=0 && notify_flag_write < 3){
// increment the flag to get to the intended clk count
notify_flag_write++;
return;
}
else if (notify_flag_write == 3){
// the write operation should have been done
notify_flag_write = 0;
acc_mem_write_ev.notify();
return;
}
if (notify_flag_read !=0 && notify_flag_read < 4){
// increment the flag to get to the intended clk count
notify_flag_read++;
return;
}
else if (notify_flag_read == 4){
// should we notify accelerator event? (two clocks have passed)
notify_flag_read = 0;
acc_mem_read_ev.notify();
return;
}
///////////////////////////////////////////////////////////////////MICRO
if (micro_read.read() || micro_write.read() || micro_call.read())
{
read_in = micro_read.read();
write_in = micro_write.read();
call_in = micro_call.read();
if (micro_read.read()){
addr_in = micro_addr.read();
}
else if (micro_write.read()){
data_in = micro_data_out.read();
addr_in = micro_addr.read();
}
}
///////////////////////////////////////////////////////////////////ACC
if (acc_read.read() || acc_write.read())
{
read_in = acc_read.read();
write_in = acc_write.read();
if (acc_read.read()){
// increment accelerator notify_flag_read
notify_flag_read++;
addr_in = acc_addr_out.read();
}
else if (acc_write.read()){
// increment accelerator notify_flag_write
notify_flag_write++;
data_in = acc_data_out.read();
addr_in = acc_addr_out.read();
}
}
}
};
/*
* @ASCK
*/
#include <systemc.h>
SC_MODULE (WB) {
sc_in_clk clk;
sc_in <sc_int<8>> prev_alu_result;
sc_in <sc_int<8>> prev_mem_result;
sc_in <bool> prev_WbMux;
sc_in <bool> prev_regWrite;
sc_in <sc_uint<3>> prev_rd;
sc_out <sc_int<8>> next_alu_result;
sc_out <sc_int<8>> next_mem_result;
sc_out <bool> next_WbMux;
sc_out <bool> next_regWrite;
sc_out <sc_uint<3>> next_rd;
/*
** module global variables
*/
SC_CTOR (WB){
SC_THREAD (process);
sensitive << clk.pos();
}
void process () {
while(true){
wait();
if(now_is_call){
wait(micro_acc_ev);
}
next_alu_result.write(prev_alu_result.read());
next_mem_result.write(prev_mem_result.read());
next_WbMux.write(prev_WbMux.read());
next_regWrite.write(prev_regWrite);
next_rd.write(prev_rd.read());
}
}
};
/*
* @ASCK
*/
#include <systemc.h>
#include <System.cpp>
using namespace std;
int sc_main(int argc, char* argv[]){
cout << "starting the complete project" << endl;
sc_trace_file *wf = sc_create_vcd_trace_file("project");
sc_signal <bool> clk;
sc_signal <bool> clk_bus;
sc_signal <sc_int<8>> reg_dump[8];
sc_signal <sc_uint<5>> aluop;
sc_signal <sc_uint<14>> pc;
System sys ("System");
sys (clk, clk_bus, pc, aluop);
for (int i=0; i<8; i++){
sys.reg_dump[i](reg_dump[i]);
}
sc_trace (wf, clk, "clk");
sc_trace (wf, clk_bus, "bus_clk");
sc_trace (wf, pc, "pc");
sc_trace (wf, aluop, "aluop");
for (int i=0; i<8; i++){
char str[3];
sprintf(str, "%d", i);
sc_trace (wf, reg_dump[i], "R" + string(str));
}
for (int i=0; i<40 ;i++){
clk_bus = 0;
clk = 1;
sc_start(1,SC_NS);
clk_bus = 1;
sc_start(1,SC_NS);
clk_bus = 0;
sc_start(1,SC_NS);
clk_bus = 1;
sc_start(1,SC_NS);
clk_bus = 0;
clk = 0;
sc_start(1,SC_NS);
clk_bus = 1;
sc_start(1,SC_NS);
clk_bus = 0;
sc_start(1,SC_NS);
clk_bus = 1;
sc_start(1,SC_NS);
}
sc_close_vcd_trace_file(wf);
cout << "vcd file completed" << endl;
return 0;
}
#include "systemc.h"
#include "tlm.h"
#include <string>
using namespace std;
using namespace tlm;
struct tr {
string message;
};
#include "uvmc.h"
using namespace uvmc;
UVMC_UTILS_1(tr, message)
SC_MODULE(refmod) {
sc_port<tlm_get_peek_if<tr> > in;
sc_port<tlm_put_if<tr> > out;
void p() {
tr tr;
while(1){
tr = in->get();
cout <<"refmod: " <<tr.message <<"\n";
out->put(tr);
}
}
SC_CTOR(refmod): in("in"), out("out") { SC_THREAD(p); }
};
SC_MODULE(refmod_low){
sc_port<tlm_get_peek_if<tr> > in;
sc_port<tlm_put_if<tr> > out;
void p() {
tr tr;
while(1){
tr = in->get();
cout <<"refmod_low: " <<tr.message <<"\n";
out->put(tr);
}
}
SC_CTOR(refmod_low): in("in"), out("out") { SC_THREAD(p); }
};
#include <octave/oct.h>
#include <octave/octave.h>
#include <octave/parse.h>
#include <octave/toplev.h>
SC_MODULE(refmod_oct) {
sc_port<tlm_get_peek_if<tr> > in;
sc_port<tlm_put_if<tr> > out;
void p() {
string_vector oct_argv (2);
oct_argv(0) = "embedded";
oct_argv(1) = "-q";
octave_function *oct_fcn;
octave_value_list oct_in, oct_out;
oct_fcn = load_fcn_from_file("reffunc.m");
if(oct_fcn) cout << "Info: SystemC: Octave function loaded." << endl;
else sc_stop();
tr tr;
while(1){
tr = in->get();
octave_idx_type i = 0;
oct_in(i) = octave_value (tr.message);
oct_out = feval(oct_fcn, oct_in);
tr.message = oct_out(0).string_value ();
cout <<"refmod_oct: " <<tr.message <<"\n";
out->put(tr);
}
}
SC_CTOR(refmod_oct): in("in"), out("out") { SC_THREAD(p); }
};
#include "refmod.cpp"
#include "refmod_low.cpp"
#include "refmod_oct.cpp"
int sc_main(int argc, char* argv[]) {
refmod refmod_i("refmod_i");
refmod_low refmod_low_i("refmod_low_i");
refmod_oct refmod_oct_i("refmod_oct_i");
uvmc_connect(refmod_i.in, "refmod_i.in");
uvmc_connect(refmod_low_i.in, "refmod_low_i.in");
uvmc_connect(refmod_i.out, "refmod_i.out");
uvmc_connect(refmod_low_i.out, "refmod_low_i.out");
uvmc_connect(refmod_oct_i.in, "refmod_oct_i.in");
uvmc_connect(refmod_oct_i.out, "refmod_oct_i.out");
sc_start();
return(0);
}
// Copyright (c) 2019 Group of Computer Architecture, university of Bremen. All Rights Reserved.
// Filename: Component.cpp
// Version 1 09-July-2019
#include "Component.h"
void Component::set_func (NT Func){
if (!Func.first.empty()){
string TypeName = Func.first+"+"+Func.second;
if (func_st.count(TypeName) == 0) {
vector<NT> temp;
func_st[TypeName] = temp;
}
}
}
//----------------------------------------------------------
void Component::set_func_with_local (string f_sig, vector<NT> vect){
if (func_st.count(f_sig) > 0) {
func_st[f_sig] = vect;
}
}
//----------------------------------------------------------
void Component::set_var (NT Var){
for (int i=0; i< var_st.size(); ++i){
if ((var_st[i].first == Var.first) && (var_st[i].second == Var.second))
return;
}
var_st.push_back(Var);
}
//----------------------------------------------------------
void Component::set_name (string module_name){
name = module_name;
}
//----------------------------------------------------------
string Component::get_name (){
return name;
}
//----------------------------------------------------------
string Component::get_name_XML (){
string temp;
if (name == "sc_main")
temp = "<Global_function name = \"" + name + "\">";
else
temp = "<Module name = \"" + name + "\">";
return temp;
}
//----------------------------------------------------------
string Component::get_var (){
string temp;
for (auto i: var_st){
if (!i.first.empty()){
temp = temp +"Name: "+i.first+"\tType: "+i.second+"\n";
}
}
if (temp.empty())
return "No Variable!\n";
else
return temp;
}
//----------------------------------------------------------
string Component::get_var_XML (){
string temp;
for (auto i: var_st){
if (!i.first.empty()){
temp = temp +"\t<Global_variable name = \""+i.first+"\"\ttype = \""+i.second+"\"></Global_variable>\n";
}
}
return temp;
}
//----------------------------------------------------------
string Component::get_func_XML (){
string temp, temp_local_var;
vector<string> vect_tp;
for (auto i: func_st){
if ((i.first != "") && (i.first != " ")){
vect_tp = split(i.first, '+');
temp_local_var = make_XML (i.second);
temp = temp + "\t<Function name = \""+vect_tp[0] + "\"\ttype = \"" + vect_tp[1]+"\">\n" + temp_local_var + "\t</Function>\n";
}
}
return temp;
}
//----------------------------------------------------------
string Component::get_func (){
string temp, temp_local_var;
vector<string> vect_tp;
for (auto i: func_st){
if ((i.first != "") && (i.first != " ")){
vect_tp = split(i.first, '+');
temp_local_var = make_string (i.second);
temp = temp +"Name: "+vect_tp[0]+"\tType: "+vect_tp[1]+"\n" + temp_local_var;
}
}
if (temp.empty())
return "No Function!\n";
else
return temp;
}
//----------------------------------------------------------
unordered_map<string, vector<NT>> Component::get_func_data (){
return func_st;
}
// Copyright (c) 2019 Group of Computer Architecture, university of Bremen. All Rights Reserved.
// Filename: Define.h
// Version 1 09-July-2019
#ifndef DEFINE_H_
#define DEFINE_H_
#include <iostream>
#include <string>
#include <sstream>
#include <vector>
#include <iterator>
using namespace std;
#include <limits>
#include <fstream>
#include <unordered_map>
#include <algorithm>
#define BLOCK "block #"
#define CLASS "class"
#define STRUCT "struct"
#define SCMODULE "sc_module"
#define DCSCMODULE "::sc_module"
#define SCMAIN "function sc_main"
#define SYMTAB "Symtab"
#define CAT "computed at runtime"
#define CONSTRUCT "construct"
#define TYPEDEF "typedef"
#define SCCORE "sc_core::"
#define CONST "const"
#define CT "const this;"
typedef pair<string, string> NT; //------N : name and T: type, which is for variable and function
const vector<string> CPlusPlus_type = {"char","char16_t","char32_t","wchar_t","signed char","short","int","long","long long","unsigned char","unsigned short","unsigned","unsigned long","unsigned long long","float","double","long double","bool","void"};
bool string_finder (string , string);
void GotoLine(ifstream& , unsigned int);
vector<string> split(const string &, char);
string replace_first_occurrence (string&, const string&, const string&);
bool findchar_exact (string, vector<string>);
void print_vector (vector<string>);
int find_in_vector (vector<string>, string);
void remove_element_vector(vector<string>&, string);
void set_NT_vector (vector<NT>&, NT);
void filter_element (string&, vector<string>);
string make_string (vector<NT>);
string make_XML (vector<NT>);
#endif
// Copyright (c) 2019 Group of Computer Architecture, university of Bremen. All Rights Reserved.
// Filename: SCmain.cpp
// Version 1 09-July-2019
#include "SCmain.h"
void ScMain::print_data(){
ofstream txtFile;
txtFile.open ("output.txt");
txtFile<<"--------------Extracted Static Information--------------"<<endl;
for (auto i: static_data_final){
txtFile<<"Module Name ----->\n"<<i.get_name()<<endl;
txtFile<<"Var List ----->\n"<<i.get_var()<<endl;
txtFile<<"Func List ----->\n"<<i.get_func()<<endl;
txtFile<<"----------------------------------------------------"<<endl;
}
}
//----------------------------------------------------------
void ScMain::print_data_XML(){
ofstream xmlFile;
xmlFile.open ("output.xml");
xmlFile<<"<ESL_ARCH>"<<endl;
for (auto i: static_data_final){
xmlFile<<i.get_name_XML()<<endl;
xmlFile<<i.get_var_XML()<<endl;
xmlFile<<i.get_func_XML()<<endl;
if (i.get_name() == "sc_main")
xmlFile<<"</Global_function>\n"<<endl;
else
xmlFile<<"</Module>\n"<<endl;
}
xmlFile<<"</ESL_ARCH>"<<endl;
xmlFile.close();
}
//----------------------------------------------------------
void ScMain::update_localVar (string m_name, string f_sig, vector<NT> local_var){
int index = find_element(m_name);
if (index != -1)
static_data_final[index].set_func_with_local(f_sig, local_var);
}
//----------------------------------------------------------
void ScMain::set_func_localVar(ifstream &debugSymbol){
unordered_map<string, vector<NT>> func_temp;
vector<string> vect_decod;
string temp, line;
vector<NT> Vect_NameType;
unsigned int lineNum = 0;
for (auto i: static_data_final){
func_temp = i.get_func_data();
for (auto j: func_temp){
lineNum = 0;
vect_decod = split(j.first,'+');
temp = "function " + i.get_name() + "::" + vect_decod[0];
GotoLine(debugSymbol, lineNum); //-------start from begining of file
if (debugSymbol.is_open()){
while (getline(debugSymbol, line)) {
lineNum++;
if (string_finder (line, temp)){
Vect_NameType = find_localVar_elements (debugSymbol, lineNum);
update_localVar(i.get_name(),j.first, Vect_NameType);
break;
}
}
}
else
cout << "\033[1;31mUnable to open Debug Symbol file\033[0m\n";
}
}
}
//----------------------------------------------------------
vector<NT> ScMain::find_localVar_elements (ifstream &debugSymbol, unsigned int lineNum){
vector<NT> Vect_NameType;
vector<string> split_line;
NT NameType;
string line;
GotoLine(debugSymbol, lineNum);
bool findComplexType = 0;
if (debugSymbol.is_open()){
while (getline(debugSymbol, line)) {
if ((!string_finder (line, DCSCMODULE)) && (!line.empty()) && (string_finder (line, CLASS) || string_finder (line, STRUCT))){ //--------- first step of extracting local var of systemC
split_line = split(line, ' ');
remove_element_vector(split_line, "");
if ((split_line.size() > 3) && string_finder (line, CLASS))
NameType.second = split_line[2];
else
NameType.second = split_line[1];
if (string_finder (NameType.second, SCCORE) && string_finder (NameType.second, "<"))
NameType.second = replace_first_occurrence(NameType.second,",",">");
findComplexType = 1;
}
else if (string_finder (line, CAT) && findComplexType && (!string_finder (line, CT)) && string_finder (line,"}")){ //--- second step of complex type
split_line = split(line, ' ');
remove_element_vector(split_line, "");
NameType.first = split_line[1];
NameType.first = replace_first_occurrence(NameType.first,";","");
set_NT_vector (Vect_NameType, NameType);
}
else if (string_finder (line, CAT) && (!string_finder (line, CT))){ //----------- extracting local var of c++ for each function
NameType = find_module_var(line);
set_NT_vector (Vect_NameType, NameType);
}
if (string_finder (line, BLOCK))
return Vect_NameType;
}
}
}
//----------------------------------------------------------
void ScMain::set_static_data_func (string m_name, NT f_name){
Component temp_struct;
int index = find_element(m_name);
if (index != -1){
static_data_final[index].set_func(f_name);
}
else{
temp_struct.set_name (m_name);
temp_struct.set_func(f_name);
static_data_final.push_back(temp_struct);
}
}
//----------------------------------------------------------
int ScMain::find_element (string str){
for (int i=0; i< static_data_final.size(); ++i){
if (static_data_final[i].get_name() == str)
return i;
}
return -1;
}
//----------------------------------------------------------
void ScMain::set_static_data_var (string m_name, NT v_name){
Component temp_struct;
int index = find_element(m_name);
if (index != -1){
static_data_final[index].set_var(v_name);
}
else{
temp_struct.set_name (m_name);
temp_struct.set_var(v_name);
static_data_final.push_back(temp_struct);
}
}
//----------------------------------------------------------
bool ScMain::find_scmain_elements (ifstream &debugSymbol, unsigned int lineNum){
string line, string_type, string_name;
NT name_type;
bool permission_flag = 0;
vector<string> split_line;
GotoLine(debugSymbol, lineNum);
if (debugSymbol.is_open()){
while (getline(debugSymbol, line)) {
if(!(string_finder(line, BLOCK))){
if (string_finder(line, CLASS)){
string_type = line;
split_line = split(string_type,' ');
string_type = split_line[6];
if((string_finder(string_type, SCCORE)) && (string_finder(string_type, "<"))){
string_type = replace_first_occurrence(string_type,",",">");
}
else if (string_finder(string_type, SCCORE)){
string_type = split_line[6];
}
permission_flag = 1;
}
else if ((string_finder(line, CAT)) && (permission_flag)){
string_name = line;
split_line = split(string_name,' ');
string_name = replace_first_occurrence(split_line[6],";","");
filter_element(string_name, {"*","&"});
name_type.first = string_name;
name_type.second = string_type;
permission_flag=0;
set_static_data_var ("sc_main", name_type);
}
}
else{
return 1;
}
}
}
else
cout << "\033[1;31mUnable to open Debug Symbol file\033[0m\n";
return 0;
}
//----------------------------------------------------------
bool ScMain::find_scmain (ifstream &debugSymbol){
string line;
bool finish = 0;
unsigned int line_num = 0;
if (debugSymbol.is_open()){
while (getline (debugSymbol,line)){
line_num++;
if (string_finder(line, BLOCK) && string_finder(line, SCMAIN)){
cout << "\033[1;32mStarting sc_main() variables extraction...\033[0m\n";
finish = find_scmain_elements (debugSymbol, line_num);
if (finish){
cout << "\033[1;32msc_main() variables extraction is dine!\033[0m\n";
cout << "\033[1;32mStarting module extraction...\033[0m\n";
find_module (debugSymbol, line_num);
cout << "\033[1;32mModule extraction is done!\033[0m\n";
GotoLine(debugSymbol, 0); //-------start from begining of file
cout << "\033[1;32mStarting local variables extraction...\033[0m\n";
set_func_localVar(debugSymbol);
cout << "\033[1;32mLocal variables extraction is done!\033[0m\n";
return 1;
}
else{
cout << "\033[1;31mCould not find sc_main() function\033[0m\n";
return 0;
}
}
}
}
else{
cout << "\033[1;31mUnable to open Debug Symbol file\033[0m\n";
return 0;
}
}
//----------------------------------------------------------
void ScMain::find_module (ifstream &debugSymbol, unsigned int lineNum){
GotoLine(debugSymbol, lineNum);
string line, module_name;
vector<string> split_line;
if (debugSymbol.is_open()){
while (getline(debugSymbol, line)) {
lineNum++;
if((string_finder(line, STRUCT)) && (string_finder(line, SCMODULE)) && (!string_finder(line, "::_")) && (!string_finder(line, BLOCK)) && (!string_finder(line, CONSTRUCT)) && (!string_finder(line, "*"))){
split_line = split(line,' ');
remove_element_vector(split_line, "");
if (string_finder(line, ">")) //--- for template type
module_name = split_line[1]+" "+split_line[2];
else
module_name = split_line[1];
if ((!string_finder(module_name, CLASS)) && (!string_finder(module_name, CONST)) && (!string_finder(module_name, SCCORE))){ //---ignoring pre-defined systemc module and function
find_module_elements(debugSymbol,lineNum, module_name);
GotoLine(debugSymbol, lineNum); //------------------return back to the line number where module defined
}
}
}
}
else
cout << "\033[1;31mUnable to open Debug Symbol file\033[0m\n";
}
//----------------------------------------------------------
void ScMain::find_module_elements (ifstream &debugSymbol, unsigned int lineNum, string m_name){
NT VarNameType;
NT FuncNameType;
GotoLine(debugSymbol, lineNum);
string line, string_type;
vector<string> split_line;
if (debugSymbol.is_open()){
while (getline(debugSymbol, line)) {
if((!string_finder(line, "}")) && (string_finder(line, ");")) && (!line.empty())){
FuncNameType = find_module_func(line);
set_static_data_func (m_name, FuncNameType);
}
else if ((string_finder(line, ";")) && (!string_finder(line, TYPEDEF)) && (!string_finder(line, "}"))){
VarNameType = find_module_var (line);
set_static_data_var (m_name, VarNameType);
}
else if (string_finder(line, "}"))
break;
}
}
else
cout << "\033[1;31mUnable to open Debug Symbol file\033[0m\n";
}
//----------------------------------------------------------
NT ScMain:: find_module_func (string line){
NT NameType;
vector<string> split_line = split(line, ' ');
remove_element_vector(split_line, "");
if ((split_line.size()>1) && (!string_finder(line, "~"))){ //------------------- ignore constractor and destrocture function
int index = find_in_vector(split_line, "(");
if (index>=0){
size_t pos = split_line[index].find("(");
NameType.first = split_line[index].substr(0,pos);
NameType.second = split_line[index-1];
}
}
return NameType;
}
//----------------------------------------------------------
NT ScMain:: find_module_var (string line){
NT NameType;
vector<string> split_line = split(line, ' ');
remove_element_vector(split_line, "");
int index_var = find_in_vector(split_line, ";");
if (index_var >=0)
NameType.first = replace_first_occurrence(split_line[index_var],";","");
else
NameType.first = replace_first_occurrence(split_line[1],";","");
NameType.second = split_line[0];
filter_element(NameType.first, {"*","&","["});
return NameType;
}
#include "systemc.h"
#include "tlm.h"
#include <string>
using namespace std;
using namespace tlm;
struct tr {
string message;
};
#include "uvmc.h"
using namespace uvmc;
UVMC_UTILS_1(tr, message)
SC_MODULE(refmod) {
sc_port<tlm_get_peek_if<tr> > in;
sc_port<tlm_put_if<tr> > out;
void p() {
tr tr;
while(1){
tr = in->get();
cout <<"refmod: " <<tr.message <<"\n";
out->put(tr);
}
}
SC_CTOR(refmod): in("in"), out("out") { SC_THREAD(p); }
};
SC_MODULE(refmod_low){
sc_port<tlm_get_peek_if<tr> > in;
sc_port<tlm_put_if<tr> > out;
void p() {
tr tr;
while(1){
tr = in->get();
cout <<"refmod_low: " <<tr.message <<"\n";
out->put(tr);
}
}
SC_CTOR(refmod_low): in("in"), out("out") { SC_THREAD(p); }
};
#include "refmod.cpp"
#include "refmod_low.cpp"
int sc_main(int argc, char* argv[]) {
refmod refmod_i("refmod_i");
refmod_low refmod_low_i("refmod_low_i");
uvmc_connect(refmod_i.in, "refmod_i.in");
uvmc_connect(refmod_low_i.in, "refmod_low_i.in");
uvmc_connect(refmod_i.out, "refmod_i.out");
uvmc_connect(refmod_low_i.out, "refmod_low_i.out");
sc_start();
return(0);
}
#ifndef KAHN_PROCESS_H
#define KAHN_PROCESS_H
/*
* kahn_process.h -- Base SystemC module for modeling applications using KPN
*
* System-Level Architecture and Modeling Lab
* Department of Electrical and Computer Engineering
* The University of Texas at Austin
*
* Author: Kamyar Mirzazad Barijough (kammirzazad@utexas.edu)
*/
#include <systemc.h>
class kahn_process : public sc_module
{
public:
SC_HAS_PROCESS(kahn_process);
kahn_process(sc_module_name name) : sc_module(name)
{
iter = 0;
SC_THREAD(main);
}
void main() { while(true) {process(); iter++;} }
protected:
int iter = 0;
virtual void process() = 0;
};
#endif
#include <systemc.h>
template <class T> SC_MODULE (driver){
// Modulo de acionamento
sc_fifo_out <T> acionamento;
// Constante para acionamento
T cte;
// Funcionamento do driver
void drive(){
int contador = 0;
// Geracao de 0s para o acionamento do sistema
while(contador < 3){
acionamento.write(cte);
cout << "Gerou um " << cte << endl;
contador++;
}
}
// Utilizando construtor de C++
SC_HAS_PROCESS(driver);
driver (sc_module_name n, const T& c):
sc_module(n), cte(c){
SC_THREAD (drive);
}
};
#include "sistema.cpp"
int sc_main (int arc, char * argv[]){
// Instanciacao do sistema, definindo o tipo da matriz e do vetor
sistema <int> sistema_instance("sistema_instance");
// Definindo a matriz
// Coluna 1
sistema_instance.mul1.matriz_in.write(1);
sistema_instance.mul1.matriz_in.write(4);
sistema_instance.mul1.matriz_in.write(7);
// Coluna 2
sistema_instance.mul2.matriz_in.write(2);
sistema_instance.mul2.matriz_in.write(5);
sistema_instance.mul2.matriz_in.write(8);
// Coluna 3
sistema_instance.mul3.matriz_in.write(3);
sistema_instance.mul3.matriz_in.write(6);
sistema_instance.mul3.matriz_in.write(9);
// |1 2 3|
// |4 5 6|
// |7 8 9|
// Definindo o vetor
sistema_instance.mul1.vetor_in.write(1);
sistema_instance.mul2.vetor_in.write(2);
sistema_instance.mul3.vetor_in.write(3);
// (1)
// (2)
// (3)
sc_start();
return 0;
}
#include "mul.cpp"
template <class T> SC_MODULE (monitor){
// Modulo de exibicao
sc_fifo_in <T> resultado;
// Funcionamento do Monitor
void monitora(){
int contador = 0;
cout << endl << "Resultado" << endl;
while(true){
// Imprime o vetor resultado
T elemento = resultado.read();
cout << "V" << contador << ": " << elemento << endl;
contador++;
}
}
SC_CTOR (monitor){
SC_THREAD (monitora);
}
};
#include "driver.cpp"
template <class T> SC_MODULE (mul){
// Entradas
sc_signal <T> vetor_in;
sc_fifo <T> matriz_in;
sc_fifo_in <T> soma_in;
// Saidas
sc_fifo_out <T> resultado_out;
// Funcionamento do modulo
void opera(){
while(true){
// Resultado = Soma + Vetor * Matriz
resultado_out.write((soma_in.read() + (vetor_in.read() * matriz_in.read())));
}
}
SC_CTOR (mul){
SC_THREAD(opera);
}
};
#include "monitor.cpp"
template <class T> SC_MODULE (sistema){
// Instanciacao dos modulos a serem utilizados
driver <T> driver_mul;
mul <T> mul1;
mul <T> mul2;
mul <T> mul3;
monitor <T> monitor_mul;
// FIFOs para conectar os modulos
sc_fifo <T> driver_mul1;
sc_fifo <T> mul1_mul2;
sc_fifo <T> mul2_mul3;
sc_fifo <T> mul3_monitor;
// Interconexao
SC_CTOR (sistema): driver_mul("driver_mul", 0),
mul1("mul1"),
mul2("mul2"),
mul3("mul3"),
monitor_mul("monitor_mul"){
// Conectando o driver ao 1 mul
driver_mul.acionamento(driver_mul1);
mul1.soma_in(driver_mul1);
// Conectando o 1 mul ao 2 mul
mul1.resultado_out(mul1_mul2);
mul2.soma_in(mul1_mul2);
// Conectando o 2 mul ao 3 mul
mul2.resultado_out(mul2_mul3);
mul3.soma_in(mul2_mul3);
// Conectando o 3 mul ao monitor
mul3.resultado_out(mul3_monitor);
monitor_mul.resultado(mul3_monitor);
}
};
#include <systemc.h>
#include "breg_if.h"
/*
* Banco de registradores que implementa a interface breg_if, eh
* utilizado na fase de EXECUTE.
*/
struct breg_risc: public sc_module, public breg_if {
// Leitura
int16_t read_breg(uint16_t reg);
// Escrita
void write_breg(uint16_t reg, int16_t dado);
// Impressao
void dump_breg();
SC_HAS_PROCESS(breg_risc);
// Declaracao do breg
breg_risc (sc_module_name n) :
sc_module(n){
breg = new int16_t[16];
}
private:
int16_t *breg;
};
#include <systemc.h>
// Interface do breg
struct breg_if: public sc_interface {
// Leitura
virtual
int16_t read_breg(uint16_t reg) = 0;
// Escrita
virtual
void write_breg(uint16_t reg, int16_t dado) = 0;
// Impressao
virtual
void dump_breg() = 0;
};
#include "fetch.h"
/*
* Decodificacao de uma funcao.
* - Acessa: contexto.
* - Saida: op, regs, regs2, regd, const4, const8.
*/
SC_MODULE(decode){
// Ponteiro para o contexto
Contexto_t *c_decode;
// Entradas
sc_fifo_in <Contexto_t*> decode_in;
// Saidas
sc_fifo_out <Contexto_t*> decode_out;
// Definicao do funcionamento do decode
void decoding();
SC_CTOR(decode){
SC_THREAD(decoding);
}
};
#include "decode.h"
// Enumeracao que define os opcodes das instrucoes
enum INSTRUCTIONS {
i_ADD = 0x2,
i_SUB = 0x3,
i_ADDi = 0x8,
i_SHIFT = 0x9,
i_AND = 0x4,
i_OR = 0x5,
i_NOT = 0xA,
i_XOR = 0x6,
i_SLT = 0x7,
i_LW = 0,
i_SW = 0x1,
i_LUI = 0xB,
i_BEQ = 0xC,
i_BLT = 0xD,
i_J = 0xE,
i_JAL = 0xF
};
/*
* Execucao de uma funcao.
* - Acessa: breg, mem e contexto.
* - Saida: breg, mem ou pc.
*/
SC_MODULE(execute){
// Ponteiro para o contexto
Contexto_t *c_execute;
// Entradas
sc_fifo_in <Contexto_t*> execute_in;
// Saidas
sc_fifo_out <Contexto_t*> execute_out;
// Memoria
sc_port<mem_if> p_mem_ex;
// BREG
sc_port<breg_if> p_breg_ex;
// Funcao para impressao do decode
void debug_decode();
// Definicao do funcionamento do execute
void executing();
SC_CTOR(execute){
SC_THREAD(executing);
}
};
#include "fetch.h"
// Definicao do funcionamento do fetch
void fetch::fetching(){
while(true){
// Pega o ponteiro do contexto
c_fetch = fetch_in.read();
//// Pega a instrucao e incrementa o PC
//ri = mem[pc];
c_fetch->ri = p_mem_fetch->read_mem(c_fetch->pc);
//pc++;
c_fetch->pc++;
// Se nao possui mais instrucoes
if(c_fetch->ri == 0){
cout << "Nao possui mais instrucoes!" << endl;
sc_stop();
exit(0);
}
// Passa o ponteiro do contexto para o decode
fetch_out.write(c_fetch);
}
}
#include <systemc.h>
#include "contexto.h"
#include "mem.h"
#include "breg.h"
/*
* Decodificacao de uma funcao.
* - Acessa: mem e contexto.
* - Saida: ri e pc.
*/
SC_MODULE(fetch){
// Contexto
Contexto_t *c_fetch;
// Entradas
sc_fifo_in <Contexto_t*> fetch_in;
// Saidas
sc_fifo_out <Contexto_t*> fetch_out;
// Memoria
sc_port<mem_if> p_mem_fetch;
// Definicao do funcionamento do fetch
void fetching();
SC_CTOR(fetch){
SC_THREAD(fetching);
}
};
// Variavel para definicao do modelo implementado, sendo:
// - 0 para Modelo com threads e eventos
// - 1 para Modelo com módulos interligados por filas bloqueantes
#define MODELO 1
#if MODELO == 0
#include "stdarg.h"
#include "risc16.h"
#else
#include "stdarg.h"
#include "top.h"
#endif
// Enumeracao que representa o formato da instrucao
enum i_FORMAT {
TIPO_R=4, TIPO_I=3, TIPO_J=2
};
// Funcao para geracao de instrucoes na memoria
short gerainst(int n, ...) {
short inst = 0;
va_list ap;
va_start(ap, n);
switch (n) {
case TIPO_R:
inst |= (va_arg(ap, int ) & 0xF) << 12;
inst |= (va_arg(ap, int ) & 0xF) << 8;
inst |= (va_arg(ap, int ) & 0xF) << 4;
inst |= (va_arg(ap, int ) & 0xF);
break;
case TIPO_I:
inst |= (va_arg(ap, int ) & 0xF) << 12;
inst |= (va_arg(ap, int ) & 0xF) << 8;
inst |= (va_arg(ap, int ) & 0xF) << 4;
inst |= (va_arg(ap, int ) & 0xF);
break;
case TIPO_J:
inst |= (va_arg(ap, int ) & 0xF) << 12;
inst |= (va_arg(ap, int ) & 0xF) << 8;
inst |= (va_arg(ap, int ) & 0xFF);
break;
default:
break;
}
return inst;
}
int sc_main (int arc, char * argv[]){
#if MODELO == 0
////// Instanciacao do risc16
risc16 risc16_instance("risc16_instance");
cout << "|||||||||||||Modelo com Eventos|||||||||||||" << endl;
////// Escrevendo instrucoes na memoria
//// Aritmeticas
/* addi $1, 0 */
// Resultado esperado => reg1 += 0
risc16_instance.write_mem(0,gerainst(TIPO_J, i_ADDi, 1, 0));
/* addi $1, 8 */
// Resultado esperado => reg1 += 8
risc16_instance.write_mem(1,gerainst(TIPO_J, i_ADDi, 1, 8));
/* addi $2, -12 */
// Resultado esperado => reg2 -= 12
risc16_instance.write_mem(2,gerainst(TIPO_J, i_ADDi, 2, -12));
/* add $3, $2, $1 */
// Resultado esperado => reg3 = reg2 + reg1
risc16_instance.write_mem(3,gerainst(TIPO_R, i_ADD, 1, 2, 3));
/* sub $4, $2, $3 */
// Resultado esperado => reg4 = reg2 - reg3
risc16_instance.write_mem(4,gerainst(TIPO_R, i_SUB, 2, 3, 4));
/* add $5, $0, $1 */
// Resultado esperado => reg5 = reg1
risc16_instance.write_mem(5,gerainst(TIPO_R, i_ADD, 1, 0, 5));
/* shift $5, 2 */
// Resultado esperado => reg5 >> 2
risc16_instance.write_mem(6,gerainst(TIPO_J, i_SHIFT, 5, 2));
/* add $6, $0, $1 */
// Resultado esperado => reg6 = reg1
risc16_instance.write_mem(7,gerainst(TIPO_R, i_ADD, 1, 0, 6));
/* shift $6, -4 */
// Resultado esperado => reg6 << 4
risc16_instance.write_mem(8,gerainst(TIPO_J, i_SHIFT, 6, -4));
//// Logicas
/* and $8, $7, $4 */
// Resultado esperado => reg8 = reg7 & reg4
risc16_instance.write_mem(9,gerainst(TIPO_R, i_AND, 4, 7, 8));
/* not $9 */
// Resultado esperado => reg9 = ~reg9
risc16_instance.write_mem(10,gerainst(TIPO_J, i_NOT, 9, 0, 0));
/* xor $10, $4, $7 */
// Resultado esperado => reg10 = reg4 ^ reg7
risc16_instance.write_mem(11,gerainst(TIPO_R, i_XOR, 4, 7, 10));
/* slt $11, $5, $1 */
// Resultado esperado => reg11 = reg5<reg1 ? 1 : 0
risc16_instance.write_mem(12,gerainst(TIPO_R, i_SLT, 5, 1, 11));
//// Transferencia
/* lui $7, FF */
// Resultado esperado => reg7 = const8 << 8
risc16_instance.write_mem(13,gerainst(TIPO_J, i_LUI, 7, 0xFF));
/* sw $5, $0, $6 */
// Resultado esperado => salva o que esta em $5 no endereco que esta em $6 da memoria
risc16_instance.write_mem(14,gerainst(TIPO_R, i_SW, 6, 0, 5));
/* lw $12, $0, $6 */
// Resultado esperado => carrega em $12 o que esta no endereco que esta em $6 da memoria
risc16_instance.write_mem(15,gerainst(TIPO_R, i_LW, 6, 0, 12));
//// Saltos
/* jal 20 */
// Resultado esperado => PC = 20
risc16_instance.write_mem(16,gerainst(TIPO_J, i_JAL, 0, 20));
/* j 30 */
// Resultado esperado => PC = 30
risc16_instance.write_mem(20,gerainst(TIPO_J, i_J, 0, 30));
/* beq $0, $8, 5 */
// Resultado esperado => reg8 == reg0 ? PC += 5 : PC += 1 => PC = 36
risc16_instance.write_mem(30,gerainst(TIPO_I, i_BEQ, 8, 0, 5));
/* blt $0, $1, 5 */
// Resultado esperado => reg0 < reg1 ? PC += 5 : PC += 1 => PC = 42
risc16_instance.write_mem(36,gerainst(TIPO_I, i_BLT, 0, 1, 5));
////// Execucao
sc_start();
risc16_instance.start();
#else
////// Instanciacao do top
top top_instance("top_instance");
cout << "|||||||||||||Modelo com Modulos e Filas Bloqueantes|||||||||||||" << endl;
////// Contexto inicial
Contexto_t *contexto = (Contexto_t*)malloc(sizeof(Contexto_t));
contexto->pc = 0;
top_instance.execute_fetch.write(contexto);
////// Escrevendo instrucoes na memoria (mesmas do caso risc16)
//// Aritmeticas
/* addi $1, 0 */
top_instance.memoria.write_mem(0, gerainst(TIPO_J, i_ADDi, 1, 0));
/* addi $1, 8 */
top_instance.memoria.write_mem(1,gerainst(TIPO_J, i_ADDi, 1, 8));
/* addi $2, -12 */
top_instance.memoria.write_mem(2,gerainst(TIPO_J, i_ADDi, 2, -12));
/* add $3, $2, $1 */
top_instance.memoria.write_mem(3,gerainst(TIPO_R, i_ADD, 1, 2, 3));
/* sub $4, $2, $3 */
top_instance.memoria.write_mem(4,gerainst(TIPO_R, i_SUB, 2, 3, 4));
/* add $5, $0, $1 */
top_instance.memoria.write_mem(5,gerainst(TIPO_R, i_ADD, 1, 0, 5));
/* shift $5, 2 */
top_instance.memoria.write_mem(6,gerainst(TIPO_J, i_SHIFT, 5, 2));
/* add $6, $0, $1 */
top_instance.memoria.write_mem(7,gerainst(TIPO_R, i_ADD, 1, 0, 6));
/* shift $6, -4 */
top_instance.memoria.write_mem(8,gerainst(TIPO_J, i_SHIFT, 6, -4));
//// Logicas
/* and $8, $7, $4 */
top_instance.memoria.write_mem(9,gerainst(TIPO_R, i_AND, 4, 7, 8));
/* not $9 */
top_instance.memoria.write_mem(10,gerainst(TIPO_J, i_NOT, 9, 0, 0));
/* xor $10, $4, $7 */
top_instance.memoria.write_mem(11,gerainst(TIPO_R, i_XOR, 4, 7, 10));
/* slt $11, $5, $1 */
top_instance.memoria.write_mem(12,gerainst(TIPO_R, i_SLT, 5, 1, 11));
//// Transferencia
/* lui $7, FF */
top_instance.memoria.write_mem(13,gerainst(TIPO_J, i_LUI, 7, 0xFF));
/* sw $5, $0, $6 */
top_instance.memoria.write_mem(14,gerainst(TIPO_R, i_SW, 6, 0, 5));
/* lw $12, $0, $6 */
top_instance.memoria.write_mem(15,gerainst(TIPO_R, i_LW, 6, 0, 12));
//// Saltos
/* jal 20 */
top_instance.memoria.write_mem(16,gerainst(TIPO_J, i_JAL, 0, 20));
/* j 30 */
top_instance.memoria.write_mem(20,gerainst(TIPO_J, i_J, 0, 30));
/* beq $0, $8, 5 */
top_instance.memoria.write_mem(30,gerainst(TIPO_I, i_BEQ, 8, 0, 5));
/* blt $0, $1, 5 */
top_instance.memoria.write_mem(36,gerainst(TIPO_I, i_BLT, 0, 1, 5));
////// Execucao
sc_start();
#endif
return 0;
}
#include <systemc.h>
#include "mem_if.h"
/*
* Memoria que implementa a interface mem_if, eh
* utilizada nas fases de FETCH e EXECUTE.
*/
struct mem_risc: public sc_module, public mem_if {
// Leitura
int16_t read_mem(uint16_t endereco);
// Escrita
void write_mem(uint16_t endereco, int16_t dado);
// Impressao
void dump_mem(uint16_t inicio, uint16_t fim, char formato);
SC_HAS_PROCESS(mem_risc);
// Declaracao da memoria
mem_risc (sc_module_name n, uint16_t tam) :
sc_module(n), tamanho(tam){
mem = new int16_t[tamanho];
}
private:
int16_t *mem;
uint16_t tamanho;
};
#include <systemc.h>
// Interface da memoria
struct mem_if: public sc_interface {
// Leitura
virtual
int16_t read_mem(uint16_t endereco) = 0;
// Escrita
virtual
void write_mem(uint16_t endereco, int16_t dado) = 0;
// Impressao
virtual
void dump_mem(uint16_t inicio, uint16_t fim, char formato) = 0;
};
#include "risc16.h"
// Funcao que inicializa o funcionamento do risc16
void risc16::start(){
wait(SC_ZERO_TIME);
pc = 0;
execute_ev.notify();
}
// Busca de uma instrucao
void risc16::fetch() {
while(true){
wait(execute_ev);
// Pega a instrucao e incrementa o PC
ri = mem[pc];
pc++;
// Se nao possui mais instrucoes
if(ri == 0){
cout << "Nao possui mais instrucoes!" << endl;
sc_stop();
exit(0);
}
fetch_ev.notify();
}
}
// Decodificacao de uma instrucao
void risc16::decode() {
while(true){
wait(fetch_ev);
// Preenchendo os campos de acordo com o RI
op = (ri >> 12) & 0xF;
regs = (ri >> 8) & 0xF;
regs2 = (ri >> 4) & 0xF;
regd = ri & 0xF;
const4 = (ri & 0x8)?(0xFFF0 | regd) : regd;
const8 = (char) (ri & 0xFF);
decode_ev.notify();
}
}
// Execucao de uma instrucao
void risc16::execute() {
while(true){
wait(decode_ev);
switch (op) {
//// Aritmeticas
// R
case i_ADD: breg[regd] = breg[regs] + breg[regs2];
break;
// R
case i_SUB: breg[regd] = breg[regs] - breg[regs2];
break;
// J
case i_ADDi: breg[regs] = breg[regs] + const8;
break;
// J
case i_SHIFT: if (const8 < 0)
breg[regs] = breg[regs] << (-const8);
else
breg[regs] = breg[regs] >> const8;
break;
//// Logicas
// R
case i_AND: breg[regd] = breg[regs] & breg[regs2];
break;
// R
case i_OR : breg[regd] = breg[regs] | breg[regs2];
break;
// R
case i_XOR: breg[regd] = breg[regs] ^ breg[regs2];
break;
// J
case i_NOT: breg[regs] = ~breg[regs];
break;
// R
case i_SLT: breg[regd] = breg[regs] < breg[regs2];
break;
//// Transferencia
// R
case i_LW: cout << "Mem:" << endl;
dump_mem(breg[regs]+breg[regs2],breg[regs]+breg[regs2],'H');
breg[regd] = mem[breg[regs] + breg[regs2]];
break;
// R
case i_SW: cout << "Mem antes:" << endl;
dump_mem(breg[regs]+breg[regs2],breg[regs]+breg[regs2],'H');
mem[breg[regs] + breg[regs2]] = breg[regd];
cout << "Mem depois:" << endl;
dump_mem(breg[regs]+breg[regs2],breg[regs]+breg[regs2],'H');
break;
// J
case i_LUI: breg[regs] = const8 << 8;
break;
//// Desvios
// I
case i_BEQ: if (breg[regs] == breg[regs2]){
debug_decode();
cout << endl;
pc = pc + const4;
}
break;
// I
case i_BLT: if (breg[regs] < breg[regs2]){
debug_decode();
cout << endl;
pc = pc + const4;
}
break;
// J
case i_J:
debug_decode();
cout << endl;
pc = breg[regs] + const8;
break;
// J
case i_JAL:
debug_decode();
cout << endl;
breg[16] = pc;
pc = breg[regs] + const8;
break;
}
// Endereco 0 do breg nao pode ser escrito
breg[0] = 0;
debug_decode();
dump_breg();
cout << endl;
execute_ev.notify();
}
}
// Impressao do breg
void risc16::dump_breg() {
for (int i=0; i<=16; i++) {
printf("BREG[%2d] = \t%4d \t\t\t%x\n", i, breg[i], breg[i]);
}
}
// Impressao apos a fase de decode
void risc16::debug_decode() {
cout << "MEM[" << pc-1 << "]" << endl;
cout << "PC = " << pc << endl;
cout << "op = " << op
<< " regs = " << regs
<< " regs2 = " << regs2
<< " regd = " << regd
<< " const4 = " << const4
<< " const8 = " << const8 << endl;
}
// Impressao da memoria
void risc16::dump_mem(uint16_t inicio, uint16_t fim, char formato) {
switch (formato) {
case 'h':
case 'H':
for (uint16_t i = inicio; i <= fim; i++)
printf("%x \t%x\n", i, mem[i]);
break;
case 'd':
case 'D':
for (uint16_t i = inicio; i <= fim; i++)
printf("%x \t%d\n", i, mem[i]);
break;
default:
break;
}
}
// Escrita na memoria
void risc16::write_mem(uint16_t endereco, int16_t dado) {
mem[endereco] = dado;
}
#include <stdlib.h>
#include <stdio.h>
#include <iostream>
#include <systemc.h>
// Tamanho maximo da memoria
const short MAX_MEM=1024;
// Enumeracao que define os opcodes das instrucoes
enum INSTRUCTIONS {
i_ADD = 0x2,
i_SUB = 0x3,
i_ADDi = 0x8,
i_SHIFT = 0x9,
i_AND = 0x4,
i_OR = 0x5,
i_NOT = 0xA,
i_XOR = 0x6,
i_SLT = 0x7,
i_LW = 0,
i_SW = 0x1,
i_LUI = 0xB,
i_BEQ = 0xC,
i_BLT = 0xD,
i_J = 0xE,
i_JAL = 0xF
};
// Definicao do risc16
SC_MODULE (risc16){
// Funcoes para o funcionamento
void start();
void fetch();
void decode();
void execute();
// Funcoes auxiliares para debug/impressao
void dump_breg();
void debug_decode();
void dump_mem(uint16_t inicio, uint16_t fim, char formato);
void write_mem(uint16_t endereco, int16_t dado);
// Threads utilizadas no funcionamento do risc16
SC_CTOR (risc16){
breg = new int16_t[16];
mem = new int16_t[MAX_MEM];
SC_THREAD(start);
SC_THREAD(fetch);
SC_THREAD(decode);
SC_THREAD(execute);
}
private:
// Componentes do risc16
uint16_t pc, ri;
uint16_t op, regs, regs2, regd;
int16_t const8, const4;
int16_t *breg;
int16_t *mem;
// Eventos para a sincronizacao
sc_event fetch_ev, decode_ev, execute_ev;
};
#include <systemc.h>
#include "execute.h"
/*
* Instanciacao do risc, interconectando os componentes.
*/
SC_MODULE(top){
//// Instanciacoes
// MEM
mem_risc memoria;
// BREG
breg_risc banco_registradores;
// Filas
sc_fifo <Contexto_t*> fetch_decode;
sc_fifo <Contexto_t*> decode_execute;
sc_fifo <Contexto_t*> execute_fetch;
// Componentes
fetch fetcher;
decode decoder;
execute executer;
SC_CTOR(top): memoria("memoria", 1024),
banco_registradores("banco_registradores"),
fetcher("fetcher"),
decoder("decoder"),
executer("executer"){
//// Conexoes
// Fetch -> Decode
fetcher.fetch_out(fetch_decode);
decoder.decode_in(fetch_decode);
// Decode -> Execute
decoder.decode_out(decode_execute);
executer.execute_in(decode_execute);
// Execute -> Fetch
executer.execute_out(execute_fetch);
fetcher.fetch_in(execute_fetch);
// Memoria
fetcher.p_mem_fetch(memoria);
executer.p_mem_ex(memoria);
// BREG
executer.p_breg_ex(banco_registradores);
}
};