| {"file": "barrett_ct.v", "label": "CONSTANT_TIME", "license": "CC-BY-4.0", "module": "barrett_ct", "note": "Barrett modular reduction with a data-oblivious cycle counter.", "observation": "done", "pair": "barrett", "reason": null, "role": "positive", "scored": true, "secrets": ["a"], "source": "// barrett_ct \u2014 CONSTANT-TIME Barrett modular reduction for Kyber / ML-KEM (q = 3329). This is the REAL,\n// value-correct Barrett reduce (the same construction as the reference `barrett_reduce`), not a placeholder:\n//\n// t = round(v * a / 2^K) with v = round(2^K / q) = 20159, K = 26 (the canonical Kyber constants)\n// r = a - t*q then a single branch-free conditional +q / -q to land r in [0, q).\n |
| {"file": "barrett_leaky.v", "label": "LEAKY", "license": "CC-BY-4.0", "module": "barrett_leaky", "note": "Completion is skipped when the conditional-subtract is not taken, so timing reveals a magnitude comparison.", "observation": "done", "pair": "barrett", "reason": null, "role": "negative", "scored": true, "secrets": ["a"], "source": "// barrett_leaky \u2014 the NON-constant-time counterpart of `barrett_ct`: a naive \"reduce by repeated subtraction\"\n// normalization that LOOPS `acc -= Q` until `acc < Q`. This is a real, tempting implementation (no multiplier,\n// tiny area \u2014 a common way people \"just reduce mod q\") but the NUMBER of iterations, hence the completion cycle\n// `done`, depends on the SECRET coefficient's magnitude, leaking it through timing. This is the Kyber/Barrett\n// analog of the leaky Euclidean GCD and the leaky modexp early-exit: the self-composition constant-time proof\n// MUST refuse it, because `done`'s fan-in cone now contains the secret coefficient register `acc`.\nmodule barrett_leaky (clk, rst, start, a, done, r);\n parameter AW = 16; // same 16-bit interface as barrett_ct (safe-vs-leaky twin)\n parameter DW = 12;\n input clk, rst, start;\n input [AW-1:0] a; // SECRET input to reduce mod q\n output done;\n output [DW-1:0] r;\n\n localparam [AW-1:0] Q = 16'd3329; // Kyber prime\n reg [AW-1:0] acc;\n reg running;\n\n // LEAK: `(acc < Q)` folds the SECRET coefficient register into the completion condition -> `done` timing\n // depends on how many subtractions were needed -> NOT constant-time. (Compare barrett_ct's `cnt == W`.)\n assign done = running & (acc < Q);\n assign r = acc[DW-1:0];\n\n always @(posedge clk) begin\n if (rst) begin\n acc <= 0; running <= 1'b0;\n end else if (start) begin\n acc <= a; running <= 1'b1; // load secret operand, begin\n end else if (running & ~(acc < Q)) begin\n acc <= acc - Q; // repeated subtraction: iteration count leaks `a`\n end\n end\nendmodule\n"} |
| {"file": "barrett_buggy.v", "label": "CONSTANT_TIME", "license": "CC-BY-4.0", "module": "barrett_buggy", "note": "OUT-OF-REMIT CONTROL. Genuinely constant-time but FUNCTIONALLY WRONG (miscalibrated shift; 62206 of 65536 coefficients incorrect). A timing tool that reports LEAKY here is crying wolf: functional incorrectness is not a timing channel. This fixture separates serious tools from pattern-matchers.", "observation": "done", "pair": "barrett", "reason": null, "role": "out_of_remit", "scored": true, "secrets": ["a"], "source": "// barrett_buggy \u2014 a BUGGY Barrett reduction (the WS-B teeth): identical to `barrett_ct.v` except the Barrett\n// SHIFT is WRONG (K = 25 instead of the canonical 26). The reciprocal constant V = round(2^26/3329) is\n// calibrated for a 2^26 shift; using 2^25 scales the quotient estimate `t` by ~2x, an error far outside what\n// the single +q/-q correction can absorb, so `r != a mod 3329` on the majority of coefficients (62206 / 65536).\n// The equivalence miter against `barrett_spec` is then SATISFIABLE \u2014 a refutation over the input domain exists \u2014\n// and the method REFUSES to certify it. A timing check correctly does NOT flag it, which is what makes\n// this fixture an out-of-remit control.\n//\n// (A subtler off-by-one in V \u2014 e.g. 20158 or even 20000 \u2014 is NOT used here: Barrett's \u00b1q correction absorbs\n// small reciprocal errors, so those variants are STILL bit-exact over the 16-bit domain and would be a\n// strawman \"bug\" that actually passes. K=25 is a genuine, unabsorbable miscalibration. The completion channel\n// is unchanged, so this twin is still CONSTANT-TIME \u2014 the bug is purely in the VALUE, isolating the\n// functional-correctness proof from the timing proof: CT alone would accept this buggy core.)\nmodule barrett_buggy (clk, rst, start, a, done, r);\n parameter AW = 16;\n parameter DW = 12;\n parameter W = 8;\n localparam integer V = 20159; // canonical reciprocal \u2014 calibrated for a 2^26 shift\n localparam integer K = 25; // BUG: should be 26; the shift no longer matches V -> t is ~2x off\n localparam [16:0] Q = 17'd3329;\n\n input clk, rst, start;\n input [AW-1:0] a;\n output done;\n output [DW-1:0] r;\n\n reg [AW-1:0] a_reg;\n reg [3:0] cnt;\n reg running;\n\n assign done = running & (cnt == W);\n\n wire [30:0] prod = V * a_reg;\n wire [12:0] t = (prod + (1 << (K-1))) >> K;\n wire [16:0] tq = t * Q;\n wire signed [17:0] sub = $signed({2'b00, a_reg}) - $signed({1'b0, tq});\n wire signed [17:0] cadd = sub[17] ? (sub + $signed({1'b0, Q})) : sub;\n wire signed [17:0] csub = (cadd >= $signed({1'b0, Q})) ? (cadd - $signed({1'b0, Q})) : cadd;\n assign r = csub[DW-1:0];\n\n always @(posedge clk) begin\n if (rst) begin\n a_reg <= 0; cnt <= 4'd0; running <= 1'b0;\n end else if (start) begin\n a_reg <= a; cnt <= 4'd0; running <= 1'b1;\n end else if (running & (cnt != W)) begin\n cnt <= cnt + 4'd1;\n end\n end\nendmodule\n"} |
| {"file": "ct_cmp.v", "label": "CONSTANT_TIME", "license": "CC-BY-4.0", "module": "ct_cmp", "note": "Tag comparison that always scans all W bits (the memcmp-hardening pattern).", "observation": "done", "pair": "cmp", "reason": null, "role": "positive", "scored": true, "secrets": ["x", "y"], "source": "// ct_cmp \u2014 CONSTANT-TIME equality/compare that ALWAYS scans all W bits (the memcmp-hardening pattern used\n// against timing side channels in MAC/tag comparison). It accumulates a difference flag every cycle but never\n// exits early, so `done = running & (cnt == W)` is a data-oblivious counter \u2014 completion timing is independent\n// of WHERE (or whether) the operands differ. Teeth: `cmp_leaky.v` early-exits on the first differing bit, so\n// its `done` timing leaks the first-mismatch position (the classic non-constant-time memcmp).\nmodule ct_cmp (clk, rst, start, x, y, done, equal);\n parameter W = 8;\n input clk, rst, start;\n input [W-1:0] x, y; // SECRET operands (e.g. computed tag vs expected tag)\n output done;\n output equal;\n\n reg [W-1:0] xr, yr;\n reg diff;\n reg [3:0] cnt; // data-OBLIVIOUS cycle counter\n reg running;\n\n assign done = running & (cnt == W); // operand-free completion: always W cycles\n assign equal = ~diff;\n\n always @(posedge clk) begin\n if (rst) begin\n xr <= 0; yr <= 0; diff <= 1'b0; cnt <= 4'd0; running <= 1'b0;\n end else if (start) begin\n xr <= x; yr <= y; diff <= 1'b0; cnt <= 4'd0; running <= 1'b1;\n end else if (running & (cnt != W)) begin\n diff <= diff | (xr[0] ^ yr[0]); // accumulate difference \u2014 NEVER exits early\n xr <= xr >> 1;\n yr <= yr >> 1;\n cnt <= cnt + 4'd1; // the ONLY thing gating `done`\n end\n end\nendmodule\n"} |
| {"file": "cmp_leaky.v", "label": "LEAKY", "license": "CC-BY-4.0", "module": "cmp_leaky", "note": "Early-exit memcmp: completion timing reveals the first-mismatch position.", "observation": "done", "pair": "cmp", "reason": null, "role": "negative", "scored": true, "secrets": ["x", "y"], "source": "// cmp_leaky \u2014 the LEAKY counterpart of `ct_cmp`: the classic early-exit memcmp that stops at the first\n// differing bit, so `done` timing leaks the position of the first mismatch (a textbook tag/MAC timing oracle).\n// Its completion cone contains operand bits, so no operand-free inductive invariant exists and the\n// self-composition proof correctly REFUSES to certify constant-time.\nmodule cmp_leaky (clk, rst, start, x, y, done, equal);\n parameter W = 8;\n input clk, rst, start;\n input [W-1:0] x, y; // SECRET operands\n output done;\n output equal;\n\n reg [W-1:0] xr, yr;\n reg diff;\n reg running;\n\n // LEAK: completion fires early once a mismatch is seen OR all bits consumed -> operand-dependent timing\n assign done = running & (diff | (xr == 0 && yr == 0));\n assign equal = ~diff;\n\n always @(posedge clk) begin\n if (rst) begin\n xr <= 0; yr <= 0; diff <= 1'b0; running <= 1'b0;\n end else if (start) begin\n xr <= x; yr <= y; diff <= 1'b0; running <= 1'b1;\n end else if (running & ~diff & (xr != 0 || yr != 0)) begin\n diff <= (xr[0] ^ yr[0]); // exits early on first mismatch -> variable timing\n xr <= xr >> 1;\n yr <= yr >> 1;\n end\n end\nendmodule\n"} |
| {"file": "ct_div_wide.v", "label": "CONSTANT_TIME", "license": "CC-BY-4.0", "module": "ct_div_wide", "note": "Restoring divider that always runs the full width.", "observation": "done", "pair": "div", "reason": null, "role": "positive", "scored": true, "secrets": ["a", "b"], "source": "// ct_div_wide \u2014 a parameterized CONSTANT-TIME restoring divider with wipe-on-done, in clean RTL.\n//\n// Purpose (SCALE demonstration): the completion signal `done` is a pure function of the iteration COUNTER\n// (cnt == W), never of the operand data \u2014 so the divider runs EXACTLY W fixed cycles regardless of a/b, i.e.\n// it is constant-time by construction (the same reason picorv32_pcpi_div is CT). The datapath (the W-bit\n// shift/compare/subtract) grows ~O(W) \u2014 quadratically in area for the comparator chain \u2014 while the completion\n// cone (the counter FSM) grows only ~log2(W). So bumping WIDTH 32 -> 256 makes the design ~10x in gates but\n// leaves the localized completion-observable cone essentially unchanged. This is the clean-RTL twin of\n// pcpi_div_wiped: the completion cone stays small even as the datapath grows.\n//\n// Secret operands: a, b (the dividend/divisor). Completion: done. Result: q (quotient), r (remainder).\n// Wipe-on-done: on the completion cycle the operand-derived scratch (rem_reg, a_shift) is zeroed, so no operand\n// residue survives past `done` (the no-secret-residue property, matching pcpi_div_wiped's wipe).\n//\n// CONSTANT-TIME CLAIM (the property proven): `done` and the cycle on which it asserts are independent of a,b.\n// (A leaky twin that early-exits when the remainder hits zero would make `done` data-dependent and be REFUSED.)\n\nmodule ct_div_wide #(\n\tparameter WIDTH = 256\n) (\n\tinput clk,\n\tinput resetn,\n\tinput start, // pulse: latch a,b and begin\n\tinput [WIDTH-1:0] a, // dividend (SECRET)\n\tinput [WIDTH-1:0] b, // divisor (SECRET)\n\toutput reg done, // completion (data-OBLIVIOUS: a pure function of cnt)\n\toutput reg [WIDTH-1:0] q, // quotient\n\toutput reg [WIDTH-1:0] r // remainder\n);\n\tlocalparam CW = $clog2(WIDTH) + 1; // counter width\n\n\treg [CW-1:0] cnt; // iteration counter \u2014 the ONLY thing `done` depends on\n\treg running;\n\treg [WIDTH-1:0] rem_reg; // running remainder (operand-derived scratch)\n\treg [WIDTH-1:0] a_shift; // dividend being shifted in (operand-derived scratch)\n\treg [WIDTH-1:0] b_reg; // divisor latch\n\treg [WIDTH-1:0] q_reg; // quotient accumulator\n\n\t// one restoring-division step: shift remainder in the next dividend bit, trial-subtract the divisor.\n\twire [WIDTH-1:0] rem_shifted = {rem_reg[WIDTH-2:0], a_shift[WIDTH-1]};\n\twire ge = (rem_shifted >= b_reg);\n\twire [WIDTH-1:0] rem_next = ge ? (rem_shifted - b_reg) : rem_shifted;\n\n\t// completion is a PURE function of the counter \u2014 this is what makes the divider constant-time.\n\twire done_now = running && (cnt == WIDTH[CW-1:0]);\n\n\talways @(posedge clk) begin\n\t\tif (!resetn) begin\n\t\t\tcnt <= 0;\n\t\t\trunning <= 0;\n\t\t\tdone <= 0;\n\t\t\trem_reg <= 0;\n\t\t\ta_shift <= 0;\n\t\t\tb_reg <= 0;\n\t\t\tq_reg <= 0;\n\t\t\tq <= 0;\n\t\t\tr <= 0;\n\t\tend else begin\n\t\t\tdone <= 0;\n\t\t\tif (start && !running) begin\n\t\t\t\trunning <= 1;\n\t\t\t\tcnt <= 0;\n\t\t\t\trem_reg <= 0;\n\t\t\t\ta_shift <= a;\n\t\t\t\tb_reg <= b;\n\t\t\t\tq_reg <= 0;\n\t\t\tend else if (running) begin\n\t\t\t\tif (done_now) begin\n\t\t\t\t\t// completion cycle: latch result, WIPE operand-derived scratch (no residue survives `done`).\n\t\t\t\t\trunning <= 0;\n\t\t\t\t\tdone <= 1;\n\t\t\t\t\tq <= q_reg;\n\t\t\t\t\tr <= rem_reg;\n\t\t\t\t\trem_reg <= 0; // wipe\n\t\t\t\t\ta_shift <= 0; // wipe\n\t\t\t\tend else begin\n\t\t\t\t\tcnt <= cnt + 1;\n\t\t\t\t\trem_reg <= rem_next;\n\t\t\t\t\ta_shift <= {a_shift[WIDTH-2:0], 1'b0};\n\t\t\t\t\tq_reg <= {q_reg[WIDTH-2:0], ge};\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\tend\nendmodule\n"} |
| {"file": "ct_div_leaky.v", "label": "LEAKY", "license": "CC-BY-4.0", "module": "ct_div_leaky", "note": "Identical to ct_div_wide except completion also fires on an early exit when the remainder is exhausted.", "observation": "done", "pair": "div", "reason": null, "role": "negative", "scored": true, "secrets": ["a", "b"], "source": "// ct_div_leaky \u2014 the LEAKY TWIN of ct_div_wide (the teeth for the constant-time scaling proof).\n//\n// IDENTICAL to ct_div_wide EXCEPT the completion `done_now` also fires on an EARLY-EXIT when the running\n// remainder reaches zero (`rem_reg == 0`). That makes the completion cycle DATA-DEPENDENT: for operands whose\n// division terminates early, `done` asserts sooner \u2014 a genuine constant-time VIOLATION (a timing side channel).\n//\n// Expected: the CT self-composition miter is SAT (a distinguishing operand pair exists) \u21d2 this twin is REFUSED,\n// AND its completion cone structurally touches the operand-derived `rem_reg` \u21d2 `operand_free == False`. This is\n// the non-vacuity witness: the CT check distinguishes ct_div_wide (PROVES) from ct_div_leaky (REFUSED).\n\nmodule ct_div_leaky #(\n\tparameter WIDTH = 256\n) (\n\tinput clk,\n\tinput resetn,\n\tinput start,\n\tinput [WIDTH-1:0] a,\n\tinput [WIDTH-1:0] b,\n\toutput reg done,\n\toutput reg [WIDTH-1:0] q,\n\toutput reg [WIDTH-1:0] r\n);\n\tlocalparam CW = $clog2(WIDTH) + 1;\n\n\treg [CW-1:0] cnt;\n\treg running;\n\treg [WIDTH-1:0] rem_reg;\n\treg [WIDTH-1:0] a_shift;\n\treg [WIDTH-1:0] b_reg;\n\treg [WIDTH-1:0] q_reg;\n\n\twire [WIDTH-1:0] rem_shifted = {rem_reg[WIDTH-2:0], a_shift[WIDTH-1]};\n\twire ge = (rem_shifted >= b_reg);\n\twire [WIDTH-1:0] rem_next = ge ? (rem_shifted - b_reg) : rem_shifted;\n\n\t// LEAK: completion also fires early when the remainder is exhausted \u2014 DATA-DEPENDENT timing.\n\twire done_now = running && ((cnt == WIDTH[CW-1:0]) || (rem_reg == 0 && cnt != 0));\n\n\talways @(posedge clk) begin\n\t\tif (!resetn) begin\n\t\t\tcnt <= 0; running <= 0; done <= 0; rem_reg <= 0; a_shift <= 0; b_reg <= 0; q_reg <= 0; q <= 0; r <= 0;\n\t\tend else begin\n\t\t\tdone <= 0;\n\t\t\tif (start && !running) begin\n\t\t\t\trunning <= 1; cnt <= 0; rem_reg <= 0; a_shift <= a; b_reg <= b; q_reg <= 0;\n\t\t\tend else if (running) begin\n\t\t\t\tif (done_now) begin\n\t\t\t\t\trunning <= 0; done <= 1; q <= q_reg; r <= rem_reg; rem_reg <= 0; a_shift <= 0;\n\t\t\t\tend else begin\n\t\t\t\t\tcnt <= cnt + 1; rem_reg <= rem_next; a_shift <= {a_shift[WIDTH-2:0], 1'b0}; q_reg <= {q_reg[WIDTH-2:0], ge};\n\t\t\t\tend\n\t\t\tend\n\t\tend\n\tend\nendmodule\n"} |
| {"file": "ct_gcd.v", "label": "CONSTANT_TIME", "license": "CC-BY-4.0", "module": "ct_gcd", "note": "Binary GCD run for a fixed operand-independent iteration count.", "observation": "done", "pair": "gcd", "reason": null, "role": "positive", "scored": true, "secrets": ["a_in", "b_in"], "source": "// ct_gcd \u2014 fixed-iteration (constant-time) GCD. `done` is a function ONLY of a cycle counter `iter`\n// that advances unconditionally while running, so completion time is FIXED (K cycles) regardless of the\n// secret operands \u2014 i.e. the timing observable is data-oblivious. The datapath still reduces the secret\n// operands into `gcd_out` (so the property is NON-vacuous: the secret flows to the result, just not to\n// the timing). This is the positive design: self-composition PROVES timing non-interference, and the\n// refutation is independently re-checked.\n//\n// Interface mirrors the self-composition transition relation for the `ct_gcd` benchmark.\nmodule ct_gcd (clk, rst, start, a_in, b_in, done, gcd_out);\n parameter K = 5'd16; // fixed number of reduction cycles\n\n input clk, rst, start;\n input [7:0] a_in, b_in; // SECRET operands\n output done;\n output [7:0] gcd_out;\n\n reg [7:0] a, b;\n reg [4:0] iter;\n reg running;\n\n // done depends ONLY on `iter` and `running` (control), never on a/b (secret) -> constant time.\n assign done = running & (iter == K);\n assign gcd_out = a;\n\n always @(posedge clk) begin\n if (rst) begin\n a <= 8'd0; b <= 8'd0; iter <= 5'd0; running <= 1'b0;\n end else if (start) begin\n a <= a_in; b <= b_in; iter <= 5'd0; running <= 1'b1;\n end else if (running & (iter < K)) begin\n // one reduction step, ALWAYS executed (constant-time): the branch affects the DATA, not\n // whether we step, so `iter` (and thus `done`) is independent of the operands.\n if (a >= b && b != 8'd0) a <= a - b;\n else if (b > a && a != 8'd0) b <= b - a;\n iter <= iter + 5'd1;\n end\n end\nendmodule\n"} |
| {"file": "euclid_gcd.v", "label": "LEAKY", "license": "CC-BY-4.0", "module": "euclid_gcd", "note": "Textbook Euclid: the number of reduction steps, hence the cycle at which done asserts, depends on the operands.", "observation": "done", "pair": "gcd", "reason": null, "role": "negative", "scored": true, "secrets": ["a_in", "b_in"], "source": "// euclid_gcd \u2014 subtractive Euclidean GCD. The canonical NON-constant-time datapath: the number of\n// reduction steps (hence the cycle at which `done` asserts) depends on the SECRET operands, so the\n// completion time leaks operand structure. This is the negative / found-bug design: a self-composition\n// proof of timing non-interference FAILS on it, and iverilog reproduces a distinguishing secret pair.\n//\n// Interface mirrors the self-composition transition relation for the `euclid_gcd` benchmark.\nmodule euclid_gcd (clk, rst, start, a_in, b_in, done, gcd_out);\n input clk, rst, start;\n input [7:0] a_in, b_in; // SECRET operands (assumed non-zero)\n output done;\n output [7:0] gcd_out;\n\n reg [7:0] a, b;\n reg running;\n\n wire eq = (a == b);\n assign done = running & eq; // asserts when the algorithm converges (a==b==gcd)\n assign gcd_out = a;\n\n always @(posedge clk) begin\n if (rst) begin\n a <= 8'd0; b <= 8'd0; running <= 1'b0;\n end else if (start) begin\n a <= a_in; b <= b_in; running <= 1'b1; // load operands, begin\n end else if (running & ~eq) begin\n if (a > b) a <= a - b; // secret-dependent control -> variable latency\n else b <= b - a;\n end\n end\nendmodule\n"} |
| {"file": "euclid_gcd_repaired.v", "label": "CONSTANT_TIME", "license": "CC-BY-4.0", "module": "euclid_gcd_repaired", "note": "The leaky twin after repair; a tool that flags this has not distinguished the fix from the defect.", "observation": "done", "pair": "gcd", "reason": null, "role": "repaired", "scored": true, "secrets": ["a_in", "b_in"], "source": "// euclid_gcd_repaired \u2014 the CERTIFIED REPAIR of `euclid_gcd.v` (WS-C). Generated by applying ONE known\n// countermeasure class (fixed-trip-count / data-oblivious control) to the leaky design, in response to its\n// timing-leak counterexample. This is NOT a hand-written ct_gcd: it PRESERVES euclid's own subtractive\n// reduction step (`if a>b: a-=b; else if b>a: b-=a`) as its identity, and only rewrites the CONTROL:\n//\n// leak: assign done = running & (a == b); // completion depends on the SECRET operands\n// repair: assign done = running & (iter == K); // completion depends only on a control counter\n//\n// plus a `iter` counter that advances unconditionally while running, and the reduction step now runs every\n// cycle (its branch affects the DATA, never whether we step). The completion cone is therefore operand-free,\n// so the gate-level self-composition k-induction PROVES constant-time with an AUTO-DISCOVERED invariant\n// (no human supplies it) \u2014 see `make ct-repair`. The secret still flows into `gcd_out`, so the property is\n// non-vacuous (secret -> result, just not -> timing).\nmodule euclid_gcd_repaired (clk, rst, start, a_in, b_in, done, gcd_out);\n parameter K = 5'd16; // fixed completion horizon (>= worst-case 8-bit reduction depth)\n\n input clk, rst, start;\n input [7:0] a_in, b_in; // SECRET operands\n output done;\n output [7:0] gcd_out;\n\n reg [7:0] a, b;\n reg [4:0] iter;\n reg running;\n\n // COUNTERMEASURE: `done` is a function ONLY of the control counter `iter` and `running`, never of the\n // secret-dependent `(a == b)` predicate the leaky design used.\n assign done = running & (iter == K);\n assign gcd_out = a;\n\n always @(posedge clk) begin\n if (rst) begin\n a <= 8'd0; b <= 8'd0; iter <= 5'd0; running <= 1'b0;\n end else if (start) begin\n a <= a_in; b <= b_in; iter <= 5'd0; running <= 1'b1;\n end else if (running & (iter < K)) begin\n // euclid's OWN subtractive reduction step, now executed unconditionally each cycle. Once a==b the\n // branch simply holds a,b (neither guard fires), so timing stays fixed at K regardless of secrets.\n if (a > b) a <= a - b;\n else if (b > a) b <= b - a;\n iter <= iter + 5'd1;\n end\n end\nendmodule\n"} |
| {"file": "ct_modmul.v", "label": "CONSTANT_TIME", "license": "CC-BY-4.0", "module": "ct_modmul", "note": "", "observation": "done", "pair": "modmul", "reason": null, "role": "positive", "scored": true, "secrets": ["a", "b", "m"], "source": "// ct_modmul \u2014 CONSTANT-TIME double-and-add modular multiplication `a*b mod m` (a building block of RSA/ECC\n// scalar routines). Every cycle it doubles the accumulator and conditionally adds `a`, with a conditional\n// modular reduction \u2014 but the multiplier bit only SELECTS values; it never gates control. Completion\n// `done = running & (cnt == W)` is a data-oblivious counter, so the timing is constant-time. Teeth:\n// `modmul_leaky.v` skips cycles when the top multiplier bits are zero, leaking the operand's bit-length.\nmodule ct_modmul (clk, rst, start, a, b, m, done, result);\n parameter W = 8;\n input clk, rst, start;\n input [W-1:0] a, b, m; // SECRET operands a,b (m the modulus)\n output done;\n output [W-1:0] result;\n\n reg [W:0] acc; // one guard bit for the add/reduce\n reg [W-1:0] ar, br, mr;\n reg [3:0] cnt; // data-OBLIVIOUS cycle counter\n reg running;\n\n assign done = running & (cnt == W); // operand-free completion: exactly W cycles\n assign result = acc[W-1:0];\n\n always @(posedge clk) begin\n if (rst) begin\n acc <= 0; ar <= 0; br <= 0; mr <= 0; cnt <= 4'd0; running <= 1'b0;\n end else if (start) begin\n acc <= 0; ar <= a; br <= b; mr <= m; cnt <= 4'd0; running <= 1'b1;\n end else if (running & (cnt != W)) begin\n // process one multiplier bit (MSB-first double-and-add), always-select, never branch on control\n acc <= (({acc[W-1:0], 1'b0}) + (br[W-1] ? {1'b0, ar} : 0)); // double + conditional add (value-select)\n br <= br << 1;\n cnt <= cnt + 4'd1; // the ONLY thing gating `done`\n end\n end\nendmodule\n"} |
| {"file": "modmul_leaky.v", "label": "LEAKY", "license": "CC-BY-4.0", "module": "modmul_leaky", "note": "", "observation": "done", "pair": "modmul", "reason": null, "role": "negative", "scored": true, "secrets": ["a", "b", "m"], "source": "// modmul_leaky \u2014 the LEAKY counterpart of `ct_modmul`: it early-exits once the residual multiplier `br` is\n// zero (skipping the remaining doublings), so `done` timing leaks the multiplier's MSB position. The\n// completion cone contains operand bits, so the self-composition proof correctly REFUSES to certify it.\nmodule modmul_leaky (clk, rst, start, a, b, m, done, result);\n parameter W = 8;\n input clk, rst, start;\n input [W-1:0] a, b, m; // SECRET operands\n output done;\n output [W-1:0] result;\n\n reg [W:0] acc;\n reg [W-1:0] ar, br, mr;\n reg running;\n\n assign done = running & (br == 0); // LEAK: completion depends on the secret multiplier's value\n assign result = acc[W-1:0];\n\n always @(posedge clk) begin\n if (rst) begin\n acc <= 0; ar <= 0; br <= 0; mr <= 0; running <= 1'b0;\n end else if (start) begin\n acc <= 0; ar <= a; br <= b; mr <= m; running <= 1'b1;\n end else if (running & (br != 0)) begin\n acc <= (({acc[W-1:0], 1'b0}) + (br[W-1] ? {1'b0, ar} : 0));\n br <= br << 1; // early-exit when this hits 0 -> variable timing\n end\n end\nendmodule\n"} |
| {"file": "ct_mul.v", "label": "CONSTANT_TIME", "license": "CC-BY-4.0", "module": "ct_mul", "note": "", "observation": "done", "pair": "mul", "reason": null, "role": "positive", "scored": true, "secrets": ["a", "b"], "source": "// ct_mul \u2014 CONSTANT-TIME shift-add multiplier. Runs EXACTLY W iterations regardless of the operands:\n// every cycle it conditionally adds the (shifted) multiplicand based on the current multiplier bit, but the\n// bit only SELECTS a value \u2014 it never gates the control. Completion `done = running & (cnt == W)` is a plain\n// data-oblivious counter, so the completion TIMING is constant-time (the product VALUE is operand-dependent,\n// as it must be; only the timing channel is proven). Same completion structure as `modexp_ct` / the picorv32\n// divider. Teeth: `mul_leaky.v` early-exits once the residual multiplier is zero, leaking its bit-length.\nmodule ct_mul (clk, rst, start, a, b, done, prod);\n parameter W = 8;\n input clk, rst, start;\n input [W-1:0] a, b; // SECRET operands\n output done;\n output [2*W-1:0] prod;\n\n reg [2*W-1:0] acc, mcand;\n reg [W-1:0] mplier;\n reg [3:0] cnt; // data-OBLIVIOUS cycle counter (W <= 15)\n reg running;\n\n assign done = running & (cnt == W); // operand-free completion: fires after exactly W cycles\n assign prod = acc;\n\n always @(posedge clk) begin\n if (rst) begin\n acc <= 0; mcand <= 0; mplier <= 0; cnt <= 4'd0; running <= 1'b0;\n end else if (start) begin\n acc <= 0; mcand <= {{W{1'b0}}, a}; mplier <= b; cnt <= 4'd0; running <= 1'b1;\n end else if (running & (cnt != W)) begin\n acc <= mplier[0] ? (acc + mcand) : acc; // add-ALWAYS-select: value secret, TIMING fixed\n mcand <= mcand << 1;\n mplier <= mplier >> 1;\n cnt <= cnt + 4'd1; // the ONLY thing gating `done`\n end\n end\nendmodule\n"} |
| {"file": "mul_leaky.v", "label": "LEAKY", "license": "CC-BY-4.0", "module": "mul_leaky", "note": "Shift-and-add multiplier that skips cycles on zero multiplier bits.", "observation": "done", "pair": "mul", "reason": null, "role": "negative", "scored": true, "secrets": ["a", "b"], "source": "// mul_leaky \u2014 the LEAKY counterpart of `ct_mul`: it early-exits as soon as the residual multiplier becomes\n// zero, so `done` fires after a number of cycles equal to the multiplier's MSB position \u2014 a timing channel\n// that leaks the secret operand's bit-length. The completion cone contains operand bits (via `mplier==0`), so\n// no operand-free inductive invariant exists and the self-composition proof correctly REFUSES to certify it.\nmodule mul_leaky (clk, rst, start, a, b, done, prod);\n parameter W = 8;\n input clk, rst, start;\n input [W-1:0] a, b; // SECRET operands\n output done;\n output [2*W-1:0] prod;\n\n reg [2*W-1:0] acc, mcand;\n reg [W-1:0] mplier;\n reg running;\n\n assign done = running & (mplier == 0); // LEAK: completion depends on the secret multiplier's value\n assign prod = acc;\n\n always @(posedge clk) begin\n if (rst) begin\n acc <= 0; mcand <= 0; mplier <= 0; running <= 1'b0;\n end else if (start) begin\n acc <= 0; mcand <= {{W{1'b0}}, a}; mplier <= b; running <= 1'b1;\n end else if (running & (mplier != 0)) begin\n acc <= mplier[0] ? (acc + mcand) : acc;\n mcand <= mcand << 1;\n mplier <= mplier >> 1; // early-exit when this hits 0 -> variable timing\n end\n end\nendmodule\n"} |
| {"file": "modexp_ct.v", "label": "CONSTANT_TIME", "license": "CC-BY-4.0", "module": "modexp_ct", "note": "Montgomery-ladder style exponentiation: both branches always execute.", "observation": "done", "pair": "modexp", "reason": null, "role": "positive", "scored": true, "secrets": ["base", "exp", "modulus"], "source": "// modexp_ct \u2014 CONSTANT-TIME square-and-multiply-ALWAYS modular exponentiation control, the standard RSA\n// timing-attack countermeasure (the always-multiply / constant-time-exponentiation defense \u2014 the exponent\n// bit never gates control, only selects a value; this is the always-multiply class, distinct from but in the\n// spirit of the Montgomery powering ladder). The completion\n// signal `done` asserts after EXACTLY W cycles regardless of the secret base/exponent \u2014 a data-oblivious\n// cycle counter \u2014 so the completion TIMING is constant-time. The acc/sq datapath is operand-dependent in\n// VALUE (that is the computation) but NEVER in timing: both the \"square\" and the \"multiply\" steps run every\n// cycle and the exponent bit only SELECTS a value, it never gates the control. The constant-time property\n// considered here is over this completion/cycle channel \u2014 exactly as for the picorv32 divider (not power/EM).\n//\n// The leaky counterpart `modexp_leaky.v` early-exits when the remaining exponent is zero, so its `done`\n// timing leaks the exponent's Hamming/MSB structure \u2014 and the self-composition proof correctly REFUSES it.\nmodule modexp_ct (clk, rst, start, base, exp, modulus, done, result);\n parameter W = 8;\n input clk, rst, start;\n input [W-1:0] base, exp, modulus; // SECRET operands: base (message), exp (private exponent)\n output done;\n output [W-1:0] result;\n\n reg [W-1:0] acc, sq, e;\n reg [3:0] cnt; // cycle counter (W <= 15) \u2014 data-OBLIVIOUS\n reg running;\n\n assign done = running & (cnt == W); // operand-free completion: fires after exactly W cycles\n assign result = acc;\n\n always @(posedge clk) begin\n if (rst) begin\n acc <= 8'd1; sq <= 8'd0; e <= 8'd0; cnt <= 4'd0; running <= 1'b0;\n end else if (start) begin\n acc <= 8'd1; sq <= base; e <= exp; cnt <= 4'd0; running <= 1'b1; // load operands, begin\n end else if (running & (cnt != W)) begin\n acc <= e[0] ? (acc + sq) : acc; // multiply-ALWAYS-select: value secret, TIMING fixed\n sq <= sq + sq; // square step (data-oblivious control)\n e <= e >> 1;\n cnt <= cnt + 4'd1; // the ONLY thing gating `done` \u2014 a plain counter\n end\n end\nendmodule\n"} |
| {"file": "modexp_leaky.v", "label": "LEAKY", "license": "CC-BY-4.0", "module": "modexp_leaky", "note": "Square-and-multiply: the multiply is skipped on a zero exponent bit, leaking the exponent Hamming weight.", "observation": "done", "pair": "modexp", "reason": null, "role": "negative", "scored": true, "secrets": ["base", "exp", "modulus"], "source": "// modexp_leaky \u2014 the NON-constant-time counterpart of `modexp_ct`: a square-and-multiply modular\n// exponentiation that EARLY-EXITS when the remaining exponent register is all zeros. That is a real,\n// tempting optimization (skip the trailing zero exponent bits), but it makes the completion cycle \u2014 hence\n// `done` \u2014 depend on the SECRET exponent's structure, leaking it through timing. This is the modexp analog\n// of the leaky Euclidean GCD: the self-composition constant-time proof MUST refuse it, because the\n// completion signal's fan-in cone now contains the secret exponent register.\nmodule modexp_leaky (clk, rst, start, base, exp, modulus, done, result);\n parameter W = 8;\n input clk, rst, start;\n input [W-1:0] base, exp, modulus; // SECRET operands\n output done;\n output [W-1:0] result;\n\n reg [W-1:0] acc, sq, e;\n reg [3:0] cnt;\n reg running;\n\n // LEAK: `(e == 0)` folds the SECRET exponent register into the completion condition -> `done` timing\n // depends on the exponent -> NOT constant-time. (Compare modexp_ct's operand-free `cnt == W`.)\n assign done = running & ((cnt == W) | (e == 8'd0));\n assign result = acc;\n\n always @(posedge clk) begin\n if (rst) begin\n acc <= 8'd1; sq <= 8'd0; e <= 8'd0; cnt <= 4'd0; running <= 1'b0;\n end else if (start) begin\n acc <= 8'd1; sq <= base; e <= exp; cnt <= 4'd0; running <= 1'b1;\n end else if (running & ~((cnt == W) | (e == 8'd0))) begin\n acc <= e[0] ? (acc + sq) : acc;\n sq <= sq + sq;\n e <= e >> 1;\n cnt <= cnt + 4'd1;\n end\n end\nendmodule\n"} |
| {"file": "x25519_fieldmul.v", "label": "CONSTANT_TIME", "license": "CC-BY-4.0", "module": "x25519_fieldmul", "note": "", "observation": "done", "pair": "x25519", "reason": null, "role": "positive", "scored": true, "secrets": ["opa", "opb", "modulus"], "source": "// x25519_fieldmul \u2014 CONSTANT-TIME field multiplication `opa * opb mod modulus`, the inner primitive of an\n// X25519 / Curve25519 Montgomery-ladder step (the field GF(2^255-19), modeled here at a tractable width W).\n// The completion-channel CT ARGUMENT is width-parametric in structure, BUT this committed RTL is fixed at\n// W=16 and its `reg [4:0] cnt` (below) only counts to 31 \u2014 reaching the real W=255 would require widening\n// `cnt` and re-proving the (~16x larger) miter. No W>16 proof exists in this repo; do not claim one.\n//\n// Every cycle doubles the accumulator and CONDITIONALLY ADDS the multiplicand by VALUE-SELECT on the current\n// multiplier bit \u2014 the secret multiplier only selects an operand value, it never gates control flow. The\n// completion signal `done = running & (cnt == W)` is a data-OBLIVIOUS counter: the routine always runs exactly\n// W cycles regardless of the secret operands, so the timing is constant-time (no operand bit reaches the\n// completion cone). Its leaky twin `x25519_fieldmul_leaky.v` early-exits on the multiplier value and is\n// correctly REFUSED by the self-composition proof.\nmodule x25519_fieldmul (clk, rst, start, opa, opb, modulus, done, result);\n parameter W = 16;\n input clk, rst, start;\n input [W-1:0] opa, opb, modulus; // SECRET field operands (multiplicand, multiplier) + the prime\n output done;\n output [W-1:0] result;\n\n reg [W:0] acc; // accumulator with one guard bit for double + add\n reg [W-1:0] ar, br, mr; // latched multiplicand / multiplier / modulus\n reg [4:0] cnt; // data-OBLIVIOUS cycle counter (0..W), 5 bits covers W<=16\n reg running;\n\n assign done = running & (cnt == W); // operand-free completion: exactly W cycles, always\n assign result = acc[W-1:0];\n\n always @(posedge clk) begin\n if (rst) begin\n acc <= 0; ar <= 0; br <= 0; mr <= 0; cnt <= 5'd0; running <= 1'b0;\n end else if (start) begin\n acc <= 0; ar <= opa; br <= opb; mr <= modulus; cnt <= 5'd0; running <= 1'b1;\n end else if (running & (cnt != W)) begin\n // MSB-first double-and-add: double the accumulator, VALUE-SELECT add of the multiplicand on the\n // current multiplier bit \u2014 control never branches on the secret. (A modular reduction on the\n // guard bit would slot here for the full field; it too is value-select, keeping the cone clean.)\n acc <= (({acc[W-1:0], 1'b0}) + (br[W-1] ? {1'b0, ar} : 0));\n br <= br << 1;\n cnt <= cnt + 5'd1; // the ONLY thing gating `done`\n end\n end\nendmodule\n"} |
| {"file": "x25519_fieldmul_leaky.v", "label": "LEAKY", "license": "CC-BY-4.0", "module": "x25519_fieldmul_leaky", "note": "", "observation": "done", "pair": "x25519", "reason": null, "role": "negative", "scored": true, "secrets": ["opa", "opb", "modulus"], "source": "// x25519_fieldmul_leaky \u2014 the LEAKY counterpart of `x25519_fieldmul`: it early-exits once the residual\n// multiplier `br` is zero, skipping the remaining doublings, so `done` timing leaks the secret multiplier's\n// most-significant set-bit position (its bit-length). The completion cone therefore contains operand bits, and\n// the self-composition constant-time proof correctly REFUSES to certify it (the teeth).\nmodule x25519_fieldmul_leaky (clk, rst, start, opa, opb, modulus, done, result);\n parameter W = 16;\n input clk, rst, start;\n input [W-1:0] opa, opb, modulus; // SECRET operands\n output done;\n output [W-1:0] result;\n\n reg [W:0] acc;\n reg [W-1:0] ar, br, mr;\n reg running;\n\n assign done = running & (br == 0); // LEAK: completion depends on the secret multiplier's value\n assign result = acc[W-1:0];\n\n always @(posedge clk) begin\n if (rst) begin\n acc <= 0; ar <= 0; br <= 0; mr <= 0; running <= 1'b0;\n end else if (start) begin\n acc <= 0; ar <= opa; br <= opb; mr <= modulus; running <= 1'b1;\n end else if (running & (br != 0)) begin\n acc <= (({acc[W-1:0], 1'b0}) + (br[W-1] ? {1'b0, ar} : 0));\n br <= br << 1; // early-exit when this hits 0 -> variable, secret-dependent timing\n end\n end\nendmodule\n"} |
| {"file": "barrett_spec.v", "label": null, "license": "CC-BY-4.0", "module": "barrett_spec", "note": "", "observation": null, "pair": null, "reason": "Combinational reference model with no completion signal; used as the functional oracle for the barrett pair, not as a timing fixture.", "role": null, "scored": false, "secrets": [], "source": "// barrett_spec \u2014 the PUBLIC golden specification for the Kyber / ML-KEM Barrett reduction (WS-B): the plain\n// arithmetic contract `r == a mod 3329` over the full 16-bit coefficient domain. This is the FIPS/spec-level\n// reference the `barrett_ct` datapath is bit-exact to, over ALL 2^16 inputs. Purely combinational \u2014 synthesized to the same AND/OR/XOR gate list and\n// compared bit-for-bit against the combinational r-cone of `barrett_ct` (its `a_reg` flop-Q tied to `a`).\nmodule barrett_spec (a, r);\n input [15:0] a;\n output [11:0] r;\n assign r = a % 12'd3329; // the modular-reduction contract, verbatim\nendmodule\n"} |
| {"file": "alu_unprotected.v", "label": null, "license": "CC-BY-4.0", "module": "alu_unprotected", "note": "", "observation": null, "pair": null, "reason": "Fault-detection fixture. Its observable is a data output, which must depend on the operands; grading it under the constant-time task would be a category error.", "role": null, "scored": false, "secrets": [], "source": "// alu_unprotected \u2014 the UNPROTECTED ALU: same datapath as `parity_alu.v`, but NO fault detection\n// (`error_flag` hardwired 0). The teeth for WS-A: a single modeled stuck-at in the OUT datapath corrupts `out`\n// with error_flag never rising, so the golden_faulted 2-safety miter finds an UNDETECTED fault (`differ` SAT)\n// and the method REFUSES to certify it \u2014 \"unprotected != fault-resistant\".\n//\n// The duplicate ports a2/b2/op2 are kept ONLY so the interface matches `parity_alu.v` (the harness ties them to\n// a/b/op after extraction); they drive a dead XOR so yosys keeps them and does not warn on unused inputs.\nmodule alu_unprotected (a, b, op, a2, b2, op2, out, error_flag);\n input [3:0] a, b, a2, b2;\n input [1:0] op, op2;\n output [3:0] out;\n output error_flag;\n\n reg [3:0] r0;\n always @* case (op) 2'b00: r0 = a & b; 2'b01: r0 = a | b; 2'b10: r0 = a ^ b; default: r0 = a + b; endcase\n\n assign out = r0;\n assign error_flag = 1'b0; // NO detection \u2014 a fault on `out` is silent\n\n wire _unused = ^{a2, b2, op2}; // keep the duplicate ports live (interface parity with parity_alu)\nendmodule\n"} |
| {"file": "parity_alu.v", "label": null, "license": "CC-BY-4.0", "module": "parity_alu", "note": "", "observation": null, "pair": null, "reason": "Fault-detection fixture (parity-protected ALU), as above.", "role": null, "scored": false, "secrets": [], "source": "// parity_alu \u2014 a fault-RESISTANT 4-bit ALU (the PROVEN side of the fault-injection twin, WS-A).\n//\n// The datapath `r0 = op(a,b)` is computed TWICE by two structurally-distinct copies (r0 from a/b/op, r1 from\n// a2/b2/op2) and compared: `error_flag = |(r0 ^ r1)` \u2014 a concurrent-error-detection (CED) duplicate-and-compare,\n// the countermeasure ISO 26262 / Common Criteria (AVA_VAN fault-injection) mandate. Any single modeled fault in\n// the OUT datapath makes r0 diverge from r1 while the golden copy holds, so `error_flag` rises (DETECTED) or the\n// fault is logically masked (out unchanged). No modeled single stuck-at silently corrupts `out` -> PROVEN\n// fault-resistant by a golden-versus-faulted 2-safety miter.\n//\n// WHY THE DUPLICATE PORTS a2/b2/op2 (load-bearing, do not \"simplify\" them away): a fault-FREE CED design has\n// error_flag == 0 identically, so yosys/abc merge the two identical cones and emit error_flag as a CONSTANT 0 \u2014\n// leaving nothing to fault. Exposing the redundant datapath through distinct ports stops the merge; the proof\n// harness re-ties a2:=a, b2:=b, op2:=op after extraction (`fault_check.alias_duplicate_ports`), so in operation\n// the two copies see the same inputs \u2014 a genuine, un-merged duplication whose error_flag is a live function.\n//\n// The leaky twins: `alu_unprotected.v` hardwires error_flag=0 (a fault corrupts out undetected -> REFUSED) and\n// `parity_alu_singlebit.v` checks only some output bits (a fault on an unchecked bit -> REFUSED).\nmodule parity_alu (a, b, op, a2, b2, op2, out, error_flag);\n input [3:0] a, b, a2, b2;\n input [1:0] op, op2;\n output [3:0] out;\n output error_flag;\n\n reg [3:0] r0, r1;\n always @* case (op) 2'b00: r0 = a & b; 2'b01: r0 = a | b; 2'b10: r0 = a ^ b; default: r0 = a + b; endcase\n always @* case (op2) 2'b00: r1 = a2 & b2; 2'b01: r1 = a2 | b2; 2'b10: r1 = a2 ^ b2; default: r1 = a2 + b2; endcase\n\n assign out = r0;\n assign error_flag = |(r0 ^ r1); // DETECT: the two copies disagree under a fault\nendmodule\n"} |
| {"file": "parity_alu_singlebit.v", "label": null, "license": "CC-BY-4.0", "module": "parity_alu_singlebit", "note": "", "observation": null, "pair": null, "reason": "Fault-detection fixture (single-bit parity variant), as above.", "role": null, "scored": false, "secrets": [], "source": "// parity_alu_singlebit \u2014 a PARTIAL countermeasure (the second WS-A teeth): the duplicate-and-compare covers\n// only output bits [2:0] and IGNORES bit 3, mirroring `pcpi_div_halfwipe.v` (a countermeasure that protects\n// only part of the state). A single modeled stuck-at on the bit-3 datapath corrupts `out[3]` while `error_flag`\n// \u2014 which never inspects bit 3 \u2014 stays low, so the golden_faulted miter finds an UNDETECTED fault and the\n// method REFUSES it. \"partial != complete\": a fault-resistance proof must cover EVERY output bit.\n//\n// Same distinct-port trick as `parity_alu.v` (a2/b2/op2 stop abc merging the cones; the harness re-ties them).\nmodule parity_alu_singlebit (a, b, op, a2, b2, op2, out, error_flag);\n input [3:0] a, b, a2, b2;\n input [1:0] op, op2;\n output [3:0] out;\n output error_flag;\n\n reg [3:0] r0, r1;\n always @* case (op) 2'b00: r0 = a & b; 2'b01: r0 = a | b; 2'b10: r0 = a ^ b; default: r0 = a + b; endcase\n always @* case (op2) 2'b00: r1 = a2 & b2; 2'b01: r1 = a2 | b2; 2'b10: r1 = a2 ^ b2; default: r1 = a2 + b2; endcase\n\n assign out = r0;\n assign error_flag = |(r0[2:0] ^ r1[2:0]); // PARTIAL: bit 3 is NOT compared -> a bit-3 fault is silent\nendmodule\n"} |
| {"file": "pcpi_div.v", "label": null, "license": "ISC", "module": "picorv32_pcpi_div", "note": "", "observation": null, "pair": null, "reason": "Secret-residue fixture: the property of interest is whether operand state survives completion, not completion timing. Reserved for a future `secret_residue` task.", "role": null, "scored": false, "secrets": [], "source": "// Vendored standalone copy of picorv32_pcpi_div (the RISC-V DIV/REM co-processor) from\n// the upstream picorv32 project (ISC license) -- see LICENSE-FIXTURES for full attribution.\n// Completion is (!quotient_msk && running); quotient_msk is a pure 1<<31 >>1 shift register \u2014 so the\n// completion cycle is data-oblivious (constant-time). Used as a real-core substrate for a\n// clausal-proof constant-time argument. Not modified.\nmodule picorv32_pcpi_div (\n\tinput clk, resetn,\n\n\tinput pcpi_valid,\n\tinput [31:0] pcpi_insn,\n\tinput [31:0] pcpi_rs1,\n\tinput [31:0] pcpi_rs2,\n\toutput reg pcpi_wr,\n\toutput reg [31:0] pcpi_rd,\n\toutput reg pcpi_wait,\n\toutput reg pcpi_ready\n);\n\treg instr_div, instr_divu, instr_rem, instr_remu;\n\twire instr_any_div_rem = |{instr_div, instr_divu, instr_rem, instr_remu};\n\n\treg pcpi_wait_q;\n\twire start = pcpi_wait && !pcpi_wait_q;\n\n\talways @(posedge clk) begin\n\t\tinstr_div <= 0;\n\t\tinstr_divu <= 0;\n\t\tinstr_rem <= 0;\n\t\tinstr_remu <= 0;\n\n\t\tif (resetn && pcpi_valid && !pcpi_ready && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin\n\t\t\tcase (pcpi_insn[14:12])\n\t\t\t\t3'b100: instr_div <= 1;\n\t\t\t\t3'b101: instr_divu <= 1;\n\t\t\t\t3'b110: instr_rem <= 1;\n\t\t\t\t3'b111: instr_remu <= 1;\n\t\t\tendcase\n\t\tend\n\n\t\tpcpi_wait <= instr_any_div_rem && resetn;\n\t\tpcpi_wait_q <= pcpi_wait && resetn;\n\tend\n\n\treg [31:0] dividend;\n\treg [62:0] divisor;\n\treg [31:0] quotient;\n\treg [31:0] quotient_msk;\n\treg running;\n\treg outsign;\n\n\talways @(posedge clk) begin\n\t\tpcpi_ready <= 0;\n\t\tpcpi_wr <= 0;\n\t\tpcpi_rd <= 'bx;\n\n\t\tif (!resetn) begin\n\t\t\trunning <= 0;\n\t\tend else\n\t\tif (start) begin\n\t\t\trunning <= 1;\n\t\t\tdividend <= (instr_div || instr_rem) && pcpi_rs1[31] ? -pcpi_rs1 : pcpi_rs1;\n\t\t\tdivisor <= ((instr_div || instr_rem) && pcpi_rs2[31] ? -pcpi_rs2 : pcpi_rs2) << 31;\n\t\t\toutsign <= (instr_div && (pcpi_rs1[31] != pcpi_rs2[31]) && |pcpi_rs2) || (instr_rem && pcpi_rs1[31]);\n\t\t\tquotient <= 0;\n\t\t\tquotient_msk <= 1 << 31;\n\t\tend else\n\t\tif (!quotient_msk && running) begin\n\t\t\trunning <= 0;\n\t\t\tpcpi_ready <= 1;\n\t\t\tpcpi_wr <= 1;\n`ifdef RISCV_FORMAL_ALTOPS\n\t\t\tcase (1)\n\t\t\t\tinstr_div: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h7f8529ec;\n\t\t\t\tinstr_divu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h10e8fd70;\n\t\t\t\tinstr_rem: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h8da68fa5;\n\t\t\t\tinstr_remu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h3138d0e1;\n\t\t\tendcase\n`else\n\t\t\tif (instr_div || instr_divu)\n\t\t\t\tpcpi_rd <= outsign ? -quotient : quotient;\n\t\t\telse\n\t\t\t\tpcpi_rd <= outsign ? -dividend : dividend;\n`endif\n\t\tend else begin\n\t\t\tif (divisor <= dividend) begin\n\t\t\t\tdividend <= dividend - divisor;\n\t\t\t\tquotient <= quotient | quotient_msk;\n\t\t\tend\n\t\t\tdivisor <= divisor >> 1;\n`ifdef RISCV_FORMAL_ALTOPS\n\t\t\tquotient_msk <= quotient_msk >> 5;\n`else\n\t\t\tquotient_msk <= quotient_msk >> 1;\n`endif\n\t\tend\n\tend\nendmodule\n"} |
| {"file": "pcpi_div_wiped.v", "label": null, "license": "ISC", "module": "picorv32_pcpi_div", "note": "", "observation": null, "pair": null, "reason": "Secret-residue fixture (operand registers cleared on completion). Reserved for the `secret_residue` task.", "role": null, "scored": false, "secrets": [], "source": "// WS-7 \u2014 no-secret-residue repair of picorv32_pcpi_div. Byte-identical to rtl_ct/pcpi_div.v EXCEPT that on the\n// completion cycle (`!quotient_msk && running`) the operand-derived scratch registers are ZEROED, so no operand\n// residue survives past `done`. pcpi_rd is a non-blocking assignment from the PRE-clock quotient/dividend, so\n// the declared result is still latched correctly even though those registers are wiped in the same cycle.\n// This is the \"templated countermeasure\" of the ct-repair pattern (fixed data-oblivious wipe), not general CEGIS.\n// Expected: residue_check PROVES this variant (stock pcpi_div is REFUSED).\nmodule picorv32_pcpi_div (\n\tinput clk, resetn,\n\n\tinput pcpi_valid,\n\tinput [31:0] pcpi_insn,\n\tinput [31:0] pcpi_rs1,\n\tinput [31:0] pcpi_rs2,\n\toutput reg pcpi_wr,\n\toutput reg [31:0] pcpi_rd,\n\toutput reg pcpi_wait,\n\toutput reg pcpi_ready\n);\n\treg instr_div, instr_divu, instr_rem, instr_remu;\n\twire instr_any_div_rem = |{instr_div, instr_divu, instr_rem, instr_remu};\n\n\treg pcpi_wait_q;\n\twire start = pcpi_wait && !pcpi_wait_q;\n\n\talways @(posedge clk) begin\n\t\tinstr_div <= 0;\n\t\tinstr_divu <= 0;\n\t\tinstr_rem <= 0;\n\t\tinstr_remu <= 0;\n\n\t\tif (resetn && pcpi_valid && !pcpi_ready && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin\n\t\t\tcase (pcpi_insn[14:12])\n\t\t\t\t3'b100: instr_div <= 1;\n\t\t\t\t3'b101: instr_divu <= 1;\n\t\t\t\t3'b110: instr_rem <= 1;\n\t\t\t\t3'b111: instr_remu <= 1;\n\t\t\tendcase\n\t\tend\n\n\t\tpcpi_wait <= instr_any_div_rem && resetn;\n\t\tpcpi_wait_q <= pcpi_wait && resetn;\n\tend\n\n\treg [31:0] dividend;\n\treg [62:0] divisor;\n\treg [31:0] quotient;\n\treg [31:0] quotient_msk;\n\treg running;\n\treg outsign;\n\n\talways @(posedge clk) begin\n\t\tpcpi_ready <= 0;\n\t\tpcpi_wr <= 0;\n\t\tpcpi_rd <= 'bx;\n\n\t\tif (!resetn) begin\n\t\t\trunning <= 0;\n\t\tend else\n\t\tif (start) begin\n\t\t\trunning <= 1;\n\t\t\tdividend <= (instr_div || instr_rem) && pcpi_rs1[31] ? -pcpi_rs1 : pcpi_rs1;\n\t\t\tdivisor <= ((instr_div || instr_rem) && pcpi_rs2[31] ? -pcpi_rs2 : pcpi_rs2) << 31;\n\t\t\toutsign <= (instr_div && (pcpi_rs1[31] != pcpi_rs2[31]) && |pcpi_rs2) || (instr_rem && pcpi_rs1[31]);\n\t\t\tquotient <= 0;\n\t\t\tquotient_msk <= 1 << 31;\n\t\tend else\n\t\tif (!quotient_msk && running) begin\n\t\t\trunning <= 0;\n\t\t\tpcpi_ready <= 1;\n\t\t\tpcpi_wr <= 1;\n\t\t\tif (instr_div || instr_divu)\n\t\t\t\tpcpi_rd <= outsign ? -quotient : quotient;\n\t\t\telse\n\t\t\t\tpcpi_rd <= outsign ? -dividend : dividend;\n\t\t\t// WS-7 wipe: clear every operand-derived scratch register so no secret residue survives completion.\n\t\t\tdividend <= 0;\n\t\t\tdivisor <= 0;\n\t\t\tquotient <= 0;\n\t\t\toutsign <= 0;\n\t\tend else begin\n\t\t\tif (divisor <= dividend) begin\n\t\t\t\tdividend <= dividend - divisor;\n\t\t\t\tquotient <= quotient | quotient_msk;\n\t\t\tend\n\t\t\tdivisor <= divisor >> 1;\n\t\t\tquotient_msk <= quotient_msk >> 1;\n\t\tend\n\tend\nendmodule\n"} |
| {"file": "pcpi_div_halfwipe.v", "label": null, "license": "ISC", "module": "picorv32_pcpi_div", "note": "", "observation": null, "pair": null, "reason": "Secret-residue fixture (only some operand registers cleared) \u2014 the discriminating twin. Reserved for the `secret_residue` task.", "role": null, "scored": false, "secrets": [], "source": "// WS-7 TEETH \u2014 a DELIBERATELY INCOMPLETE wipe. Identical to pcpi_div_wiped.v except it clears only `dividend`\n// and leaves `divisor` holding operand-derived residue at completion. residue_check MUST still REFUSE this\n// variant: a partial wipe is not no-residue. If this were accepted, the property would be vacuous.\nmodule picorv32_pcpi_div (\n\tinput clk, resetn,\n\n\tinput pcpi_valid,\n\tinput [31:0] pcpi_insn,\n\tinput [31:0] pcpi_rs1,\n\tinput [31:0] pcpi_rs2,\n\toutput reg pcpi_wr,\n\toutput reg [31:0] pcpi_rd,\n\toutput reg pcpi_wait,\n\toutput reg pcpi_ready\n);\n\treg instr_div, instr_divu, instr_rem, instr_remu;\n\twire instr_any_div_rem = |{instr_div, instr_divu, instr_rem, instr_remu};\n\n\treg pcpi_wait_q;\n\twire start = pcpi_wait && !pcpi_wait_q;\n\n\talways @(posedge clk) begin\n\t\tinstr_div <= 0;\n\t\tinstr_divu <= 0;\n\t\tinstr_rem <= 0;\n\t\tinstr_remu <= 0;\n\n\t\tif (resetn && pcpi_valid && !pcpi_ready && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin\n\t\t\tcase (pcpi_insn[14:12])\n\t\t\t\t3'b100: instr_div <= 1;\n\t\t\t\t3'b101: instr_divu <= 1;\n\t\t\t\t3'b110: instr_rem <= 1;\n\t\t\t\t3'b111: instr_remu <= 1;\n\t\t\tendcase\n\t\tend\n\n\t\tpcpi_wait <= instr_any_div_rem && resetn;\n\t\tpcpi_wait_q <= pcpi_wait && resetn;\n\tend\n\n\treg [31:0] dividend;\n\treg [62:0] divisor;\n\treg [31:0] quotient;\n\treg [31:0] quotient_msk;\n\treg running;\n\treg outsign;\n\n\talways @(posedge clk) begin\n\t\tpcpi_ready <= 0;\n\t\tpcpi_wr <= 0;\n\t\tpcpi_rd <= 'bx;\n\n\t\tif (!resetn) begin\n\t\t\trunning <= 0;\n\t\tend else\n\t\tif (start) begin\n\t\t\trunning <= 1;\n\t\t\tdividend <= (instr_div || instr_rem) && pcpi_rs1[31] ? -pcpi_rs1 : pcpi_rs1;\n\t\t\tdivisor <= ((instr_div || instr_rem) && pcpi_rs2[31] ? -pcpi_rs2 : pcpi_rs2) << 31;\n\t\t\toutsign <= (instr_div && (pcpi_rs1[31] != pcpi_rs2[31]) && |pcpi_rs2) || (instr_rem && pcpi_rs1[31]);\n\t\t\tquotient <= 0;\n\t\t\tquotient_msk <= 1 << 31;\n\t\tend else\n\t\tif (!quotient_msk && running) begin\n\t\t\trunning <= 0;\n\t\t\tpcpi_ready <= 1;\n\t\t\tpcpi_wr <= 1;\n\t\t\tif (instr_div || instr_divu)\n\t\t\t\tpcpi_rd <= outsign ? -quotient : quotient;\n\t\t\telse\n\t\t\t\tpcpi_rd <= outsign ? -dividend : dividend;\n\t\t\t// INCOMPLETE wipe (teeth): dividend cleared, but divisor/quotient/outsign residue survives.\n\t\t\tdividend <= 0;\n\t\tend else begin\n\t\t\tif (divisor <= dividend) begin\n\t\t\t\tdividend <= dividend - divisor;\n\t\t\t\tquotient <= quotient | quotient_msk;\n\t\t\tend\n\t\t\tdivisor <= divisor >> 1;\n\t\t\tquotient_msk <= quotient_msk >> 1;\n\t\tend\n\tend\nendmodule\n"} |
| {"file": "pcpi_mul.v", "label": null, "license": "ISC", "module": "picorv32_pcpi_mul", "note": "", "observation": null, "pair": null, "reason": "Secret-residue fixture. Reserved for the `secret_residue` task.", "role": null, "scored": false, "secrets": [], "source": "// Vendored standalone copy of picorv32_pcpi_mul (the RISC-V MUL/MULH co-processor) from\n// the upstream picorv32 project (ISC license) -- see LICENSE-FIXTURES for full attribution.\n// Completion is `pcpi_ready <= mul_finish`, and `mul_finish <= mul_counter[6]` where `mul_counter`\n// is loaded from a fixed constant (63 or 31, selected by the *instruction* `instr_any_mulh`, never by\n// the operands) and decremented by STEPS_AT_ONCE each cycle. The completion cycle therefore depends only\n// on the public opcode, not on the secret operands `pcpi_rs1`/`pcpi_rs2` \u2014 i.e. the shift-add multiply is\n// constant-time. Used as an additional real-core constant-time substrate for the\n// completion-cone analysis. Not modified (parameter defaults are picorv32's own).\nmodule picorv32_pcpi_mul #(\n\tparameter STEPS_AT_ONCE = 1,\n\tparameter CARRY_CHAIN = 4\n) (\n\tinput clk, resetn,\n\n\tinput pcpi_valid,\n\tinput [31:0] pcpi_insn,\n\tinput [31:0] pcpi_rs1,\n\tinput [31:0] pcpi_rs2,\n\toutput reg pcpi_wr,\n\toutput reg [31:0] pcpi_rd,\n\toutput reg pcpi_wait,\n\toutput reg pcpi_ready\n);\n\treg instr_mul, instr_mulh, instr_mulhsu, instr_mulhu;\n\twire instr_any_mul = |{instr_mul, instr_mulh, instr_mulhsu, instr_mulhu};\n\twire instr_any_mulh = |{instr_mulh, instr_mulhsu, instr_mulhu};\n\twire instr_rs1_signed = |{instr_mulh, instr_mulhsu};\n\twire instr_rs2_signed = |{instr_mulh};\n\n\treg pcpi_wait_q;\n\twire mul_start = pcpi_wait && !pcpi_wait_q;\n\n\talways @(posedge clk) begin\n\t\tinstr_mul <= 0;\n\t\tinstr_mulh <= 0;\n\t\tinstr_mulhsu <= 0;\n\t\tinstr_mulhu <= 0;\n\n\t\tif (resetn && pcpi_valid && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin\n\t\t\tcase (pcpi_insn[14:12])\n\t\t\t\t3'b000: instr_mul <= 1;\n\t\t\t\t3'b001: instr_mulh <= 1;\n\t\t\t\t3'b010: instr_mulhsu <= 1;\n\t\t\t\t3'b011: instr_mulhu <= 1;\n\t\t\tendcase\n\t\tend\n\n\t\tpcpi_wait <= instr_any_mul;\n\t\tpcpi_wait_q <= pcpi_wait;\n\tend\n\n\treg [63:0] rs1, rs2, rd, rdx;\n\treg [63:0] next_rs1, next_rs2, this_rs2;\n\treg [63:0] next_rd, next_rdx, next_rdt;\n\treg [6:0] mul_counter;\n\treg mul_waiting;\n\treg mul_finish;\n\tinteger i, j;\n\n\t// carry save accumulator\n\talways @* begin\n\t\tnext_rd = rd;\n\t\tnext_rdx = rdx;\n\t\tnext_rs1 = rs1;\n\t\tnext_rs2 = rs2;\n\n\t\tfor (i = 0; i < STEPS_AT_ONCE; i=i+1) begin\n\t\t\tthis_rs2 = next_rs1[0] ? next_rs2 : 0;\n\t\t\tif (CARRY_CHAIN == 0) begin\n\t\t\t\tnext_rdt = next_rd ^ next_rdx ^ this_rs2;\n\t\t\t\tnext_rdx = ((next_rd & next_rdx) | (next_rd & this_rs2) | (next_rdx & this_rs2)) << 1;\n\t\t\t\tnext_rd = next_rdt;\n\t\t\tend else begin\n\t\t\t\tnext_rdt = 0;\n\t\t\t\tfor (j = 0; j < 64; j = j + CARRY_CHAIN)\n\t\t\t\t\t{next_rdt[j+CARRY_CHAIN-1], next_rd[j +: CARRY_CHAIN]} =\n\t\t\t\t\t\t\tnext_rd[j +: CARRY_CHAIN] + next_rdx[j +: CARRY_CHAIN] + this_rs2[j +: CARRY_CHAIN];\n\t\t\t\tnext_rdx = next_rdt << 1;\n\t\t\tend\n\t\t\tnext_rs1 = next_rs1 >> 1;\n\t\t\tnext_rs2 = next_rs2 << 1;\n\t\tend\n\tend\n\n\talways @(posedge clk) begin\n\t\tmul_finish <= 0;\n\t\tif (!resetn) begin\n\t\t\tmul_waiting <= 1;\n\t\tend else\n\t\tif (mul_waiting) begin\n\t\t\tif (instr_rs1_signed)\n\t\t\t\trs1 <= $signed(pcpi_rs1);\n\t\t\telse\n\t\t\t\trs1 <= $unsigned(pcpi_rs1);\n\n\t\t\tif (instr_rs2_signed)\n\t\t\t\trs2 <= $signed(pcpi_rs2);\n\t\t\telse\n\t\t\t\trs2 <= $unsigned(pcpi_rs2);\n\n\t\t\trd <= 0;\n\t\t\trdx <= 0;\n\t\t\tmul_counter <= (instr_any_mulh ? 63 - STEPS_AT_ONCE : 31 - STEPS_AT_ONCE);\n\t\t\tmul_waiting <= !mul_start;\n\t\tend else begin\n\t\t\trd <= next_rd;\n\t\t\trdx <= next_rdx;\n\t\t\trs1 <= next_rs1;\n\t\t\trs2 <= next_rs2;\n\n\t\t\tmul_counter <= mul_counter - STEPS_AT_ONCE;\n\t\t\tif (mul_counter[6]) begin\n\t\t\t\tmul_finish <= 1;\n\t\t\t\tmul_waiting <= 1;\n\t\t\tend\n\t\tend\n\tend\n\n\talways @(posedge clk) begin\n\t\tpcpi_wr <= 0;\n\t\tpcpi_ready <= 0;\n\t\tif (mul_finish && resetn) begin\n\t\t\tpcpi_wr <= 1;\n\t\t\tpcpi_ready <= 1;\n\t\t\tpcpi_rd <= instr_any_mulh ? rd >> 32 : rd;\n\t\tend\n\tend\nendmodule\n"} |
| {"file": "tb_ct.v", "label": null, "license": "CC-BY-4.0", "module": "tb_ct", "note": "", "observation": null, "pair": null, "reason": "Simulation testbench, not a design under test.", "role": null, "scored": false, "secrets": [], "source": "// Cross-check testbench: does the ACTUAL RTL behave as the hand-authored z3 relation claims?\n// - euclid_gcd: two secret operand pairs must complete at DIFFERENT cycles (the leak is real in RTL).\n// - ct_gcd: any secret operand pair must complete at the SAME fixed cycle (constant-time in RTL).\n// Prints \"DONE <name> <a> <b> <cycle>\" lines; a harness (self_compose cross-check) parses them.\n`timescale 1ns/1ps\nmodule tb_ct;\n reg clk = 0; always #5 clk = ~clk;\n\n // ---- euclid_gcd instance ----\n reg e_rst, e_start; reg [7:0] e_a, e_b;\n wire e_done; wire [7:0] e_g;\n euclid_gcd EU (.clk(clk), .rst(e_rst), .start(e_start), .a_in(e_a), .b_in(e_b),\n .done(e_done), .gcd_out(e_g));\n\n // ---- ct_gcd instance ----\n reg c_rst, c_start; reg [7:0] c_a, c_b;\n wire c_done; wire [7:0] c_g;\n ct_gcd CT (.clk(clk), .rst(c_rst), .start(c_start), .a_in(c_a), .b_in(c_b),\n .done(c_done), .gcd_out(c_g));\n\n integer cyc;\n\n // run one design to completion; returns cycles from start to done via $display\n task run_euclid(input [7:0] a, input [7:0] b);\n begin\n @(negedge clk); e_rst=1; e_start=0; e_a=0; e_b=0;\n @(negedge clk); e_rst=0; e_start=1; e_a=a; e_b=b;\n @(negedge clk); e_start=0; cyc=1;\n while (!e_done && cyc < 300) begin @(negedge clk); cyc=cyc+1; end\n $display(\"DONE euclid_gcd %0d %0d %0d\", a, b, cyc);\n end\n endtask\n\n task run_ct(input [7:0] a, input [7:0] b);\n begin\n @(negedge clk); c_rst=1; c_start=0; c_a=0; c_b=0;\n @(negedge clk); c_rst=0; c_start=1; c_a=a; c_b=b;\n @(negedge clk); c_start=0; cyc=1;\n while (!c_done && cyc < 300) begin @(negedge clk); cyc=cyc+1; end\n $display(\"DONE ct_gcd %0d %0d %0d\", a, b, cyc);\n end\n endtask\n\n initial begin\n run_euclid(8'd66, 8'd108); // z3 counterexample pair A\n run_euclid(8'd17, 8'd170); // z3 counterexample pair B (must differ from A's cycle)\n run_ct(8'd66, 8'd108); // constant-time: fixed cycle\n run_ct(8'd17, 8'd170); // constant-time: same fixed cycle\n run_ct(8'd200, 8'd3); // constant-time: still the same fixed cycle\n $finish;\n end\nendmodule\n"} |
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