Update EDA Bench data card framing

DATA_CARD.md

@@ -47,11 +47,13 @@ plausibility.
 
 ## Contamination Policy
 
-The default benchmark should be reported as open-book hardware reconstruction.
-Agents may use web search and may discover public upstream projects. Claims
-should therefore be limited to research plus reconstruction under fixed prompts,
-fixed tooling, and recorded provenance. Do not use default leaderboard results as
-evidence of closed-book synthesis or memorization-resistant hidden answers.
+The default benchmark should be reported as open-book hardware task solving.
+Agents may use web search and may discover public upstream projects, just as
+public software-engineering benchmarks may expose code history, issue threads,
+or patches. Claims should therefore be limited to public-information EDA task
+solving under fixed prompts, fixed tooling, and recorded provenance. Do not use
+default leaderboard results as evidence of closed-book synthesis or
+memorization-resistant hidden answers.
 
 Repository build artifacts should contain runner and harness code, public
 documentation, the task-pack manifest, and loader/grader support code. Task
@@ -84,6 +86,19 @@ score-supported through explicit I/O simulation oracles:
 Full task packs include tests for the explicit I/O oracle. The reference project
 must score `1.0` through `score_components["io_simulation"]`, and the fail
 canary must score below the release threshold using the same simulation oracle.
+Fail canaries remove active internal circuitry when available, falling back to
+external boundary removal for passive boards, so validation covers plausible
+external shells that do not contain the circuit needed to work.
+
+The task-pack builder also stages generated mutation canaries for missing board
+outlines, unrouted external nets, isolated external pads, external power/signal
+pads tied to ground, and missing high-speed-like routes for high-speed carrier
+tasks. Four representative calibrated tasks currently add stricter task-family
+checks: USB-C breakout, RS-485 transceiver breakout, BQ24295 power path, and
+M.2/PCIe adapter.
+
+A full generated-mutation sweep on May 6, 2026 validated 40/40 tasks and 162
+generated mutation canaries below the release threshold.
 
 ## Evaluation Claims
 
@@ -92,31 +107,55 @@ plus behavioral transient I/O simulation oracle. Scores should not be interprete
 direct proof of electrical safety, regulatory compliance, manufacturability,
 production readiness, or high-speed protocol compliance.
 
+| Claim | Status |
+|---|---|
+| Open-book agent task solving under fixed prompts/tools/provenance | Supported |
+| External I/O behavior under the released oracle | Supported |
+| Closed-book PCB synthesis | Not supported |
+| Manufacturing, regulatory, thermal, EMC, or production readiness | Not supported |
+| Exact component inventory, reference designator, outline, or route-shape matching | Not a primary score |
+
 ## Known Limitations
 
 - The current oracle models realized copper, trace width/length/layer R/L/C
   parasitics, same-layer trace-intersection shorts, close-trace coupling,
   vias, zones, pad resistance, leakage, R/C/L/diode passives, deterministic
   generic IC coupling, task-required boundary-net interface families,
-  external-net electrical-health contracts, refdes-invariant external
+  task-required generic internal active-role realization,
+  broad component-function realization for active devices, passives,
+  decoupling, filters, and protection networks,
+  active-device power/ground integrity,
+  absolute fabrication geometry sanity for outlines, trace widths, and via
+  annular rings,
+  external-net and board-wide same-layer short electrical-health contracts,
+  refdes-invariant external
   connector pin/net semantic contracts, generic signal net-name tolerance,
+  KiCad DRC and schematic ERC errors relative to the reference when
+  `kicad-cli` is available,
   diagnostic exact reference-pad, role/topology, and route-shape checks, hard
   caps for wrong external pin/net mapping, missing routed copper, split or isolated external I/O,
   power/ground/signal shorts, missing simulated signal or I/O transfer
-  responses, grossly implausible impedance, and missing or implausible
-  differential-pair families. Many public hardware
+  responses, missing task-required internal active realization, missing
+  component-function realization, missing active-device power integrity,
+  DRC/ERC error violations, implausible trace/via/outline fabrication geometry,
+  grossly implausible impedance, and missing or implausible differential-pair
+  families. Many public hardware
   tasks still need richer calibrated models: device behavioral models,
   IBIS/SPICE/S-parameter data, field-solver stackups, power sequencing,
   differential-channel expectations, and task-specific tolerances.
 - The benchmark disables proxy grading based on component, footprint, routing,
   or outline similarity.
-- The built-in harness is web-enabled. Agents may be able to discover public
+- The built-in web harnesses are web-enabled. Agents may be able to discover public
   upstream projects through search, so results measure web-enabled agent
   performance rather than closed-book design synthesis. This is intentional for
   the default open-book track and should be disclosed in any leaderboard or
   paper claim.
 - Some upstream projects have restrictive or unclear redistribution terms. See
   `LICENSES.md` and per-source license notices before republishing subsets.
+- The current canary suite validates frozen references, structural fail canaries,
+  and generated mutation canaries. Additional mutation types should be added for
+  future releases, especially swapped pins, missing pull-ups, missing
+  decoupling, and active devices without power/ground.
 
 ## Maintenance