| { |
| "sleigh_data": [ |
| { |
| "id": "0", |
| "language": "Sleigh", |
| "instruction": "mov", |
| "sleigh_code": ":mov rm_04_07,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b0011 \n{\n rn_08_11 = rm_04_07;\n}", |
| "sleigh_comments": "", |
| "functionality": "", |
| "documentation": { |
| "official_documentation": "Renesas 32-Bit RISC Microcomputer SuperH", |
| "processor": "SuperH", |
| "instruction_details": "Transfers the source operand to the destination.", |
| "feature": "Data Transfer Instruction", |
| "opcode": "0110", |
| "example_usage": "void MOV (int m, int n)\n{\n R[n] = R[m];\n PC += 2;\n}", |
| "possible_exceptions": "" |
| }, |
| "annotations": { |
| "complexity": null, |
| "use_cases": "", |
| "known_issues": "" |
| } |
| }, |
| { |
| "id": "1", |
| "language": "Sleigh", |
| "instruction": "mov", |
| "sleigh_code": ":mov imm8,rn_08_11 is opcode_12_15=0b1110 & rn_08_11 & imm8 \n{\n rn_08_11 = imm8;\n}", |
| "sleigh_comments": "", |
| "functionality": "", |
| "documentation": { |
| "official_documentation": "Renesas 32-Bit RISC Microcomputer SuperH", |
| "processor": "SuperH", |
| "instruction_details": "Stores immediate data, sign-extended to longword, in general register Rn.", |
| "feature": "Data Transfer Instruction", |
| "opcode": "1110", |
| "example_usage": "void MOVI (int i, int n)\n{\n if ((i & 0x80) == 0)\n R[n] = (0x000000FF & i);\n else\n R[n] = (0xFFFFFF00 | i);\n\n PC += 2;\n}", |
| "possible_exceptions": "" |
| }, |
| "annotations": { |
| "complexity": null, |
| "use_cases": "", |
| "known_issues": "" |
| } |
| }, |
| { |
| "id": "2", |
| "language": "Sleigh", |
| "instruction": "movi20", |
| "sleigh_code": ":movi20 simm20, l_rn_24_27\n is l_opcode_28_31=0b0000 & l_rn_24_27 & l_opcode_16_19=0b0000 & simm20\n{\n l_rn_24_27 = simm20;\n}", |
| "sleigh_comments": "# MOVI20 #imm20, Rn 0000nnnniiii0000 iiiiiiiiiiiiiiii imm → sign extension → Rn", |
| "functionality": "", |
| "documentation": { |
| "official_documentation": "Renesas 32-Bit RISC Microcomputer SuperH", |
| "processor": "SuperH", |
| "instruction_details": "Stores immediate data that has been sign-extended to longword in general register Rn.", |
| "feature": "Data Transfer Instruction", |
| "opcode": "0b0000", |
| "example_usage": "void MOVI20 (int i, int n)\n{\n if (i & 0x00080000) == 0)\n R[n] = (0x000FFFFF & (long)i);\n else\n R[n] = (0xFFF00000 | (long)i);\n\n PC += 4;\n}\n", |
| "possible_exceptions": "" |
| }, |
| "annotations": { |
| "complexity": null, |
| "use_cases": "", |
| "known_issues": "" |
| } |
| }, |
| { |
| "id": "3", |
| "language": "Sleigh", |
| "instruction": "movi20s", |
| "sleigh_code": ":movi20s simm20s, l_rn_24_27\n is l_opcode_28_31=0b0000 & l_rn_24_27 & l_opcode_16_19=0b0001 & simm20s\n{\n l_rn_24_27 = simm20s;\n}", |
| "sleigh_comments": "# MOVI20S #imm20, Rn 0000nnnniiii0001 iiiiiiiiiiiiiiii imm<<8 → sign extension → Rn", |
| "functionality": "", |
| "documentation": { |
| "official_documentation": "Renesas 32-Bit RISC Microcomputer SuperH", |
| "processor": "SuperH", |
| "instruction_details": "Shifts immediate data 8 bits to the left and performs sign extension to longword, then stores the resulting data in general register Rn. Using an OR or ADD instruction as the next instruction enables a 28-bit absolute address to be generated.", |
| "feature": "Data Transfer Instruction", |
| "opcode": "0b0000", |
| "example_usage": "void MOVI20S (int i, int n)\n{\n if (i & 0x00080000) == 0)\n R[n] = (0x000FFFFF & (long)i);\n else\n R[n] = (0xFFF00000 | (long)i);\n\n R[n] <<= 8;\n PC += 4;\n}", |
| "possible_exceptions": "" |
| }, |
| "annotations": { |
| "complexity": null, |
| "use_cases": "", |
| "known_issues": "" |
| } |
| }, |
| { |
| "id": "4", |
| "language": "Sleigh", |
| "instruction": "mova", |
| "sleigh_code": ":mova disppc4,r0 is r0 & opcode_08_15=0b11000111 & disppc4\n{\n r0 = disppc4;\n}", |
| "sleigh_comments": "", |
| "functionality": "", |
| "documentation": { |
| "official_documentation": "Renesas 32-Bit RISC Microcomputer SuperH", |
| "processor": "SuperH", |
| "instruction_details": "Stores the effective address of the source operand into general register R0. The 8-bit displacement is zero-extended and quadrupled. Consequently, the relative interval from the operand is PC + 1020 bytes. The PC is the address four bytes after this instruction, but the lowest two bits of the PC are fixed at 00.\n\nNote\nSH1*, SH2*, SH3*:\nIf this instruction is placed immediately after a delayed branch instruction, the PC must point to an address specified by (the starting address of the branch destination) + 2.\n\nSH4*:\nIf this instruction is executed in a delay slot, a slot illegal instruction exception will be generated.", |
| "feature": "Data Transfer Instruction", |
| "opcode": "0b11000111", |
| "example_usage": "void MOVA (int d)\n{\n unsigned int disp;\n disp = (unsigned int)(0x000000FF & d);\n R[0] = (PC & 0xFFFFFFFC) + 4 + (disp << 2);\n PC += 2;\n}", |
| "possible_exceptions": "Slot illegal instruction" |
| }, |
| "annotations": { |
| "complexity": null, |
| "use_cases": "", |
| "known_issues": "" |
| } |
| }, |
| { |
| "id": "5", |
| "language": "Sleigh", |
| "instruction": "mov.w", |
| "sleigh_code": ":mov.w disppc2,rn_08_11 is opcode_12_15=0b1001 & rn_08_11 & disppc2\n{\n rn_08_11 = sext(*:2 disppc2);\n}", |
| "sleigh_comments": "", |
| "functionality": "", |
| "documentation": { |
| "official_documentation": "Renesas 32-Bit RISC Microcomputer SuperH", |
| "processor": "SuperH", |
| "instruction_details": "Stores immediate data, sign-extended to longword, in general register Rn. The data is stored from memory address (PC + 4 + displacement * 2). The 8-bit displacement is multiplied by two after zero-extension, and so the relative distance from the table is in the range up to PC + 4 + 510 bytes. The PC value is the address of this instruction.\n\nNote\nIf the following instruction is a branch instruction, it is identified as a slot illegal instruction.", |
| "feature": "Data Transfer Instruction", |
| "opcode": "0b1001", |
| "example_usage": "void MOVWI (int d, int n)\n{\n unsigned int disp = (0x000000FF & d);\n R[n] = Read_16 (PC + 4 + (disp << 1));\n if ((R[n] & 0x8000) == 0)\n R[n] &= 0x0000FFFF;\n else\n R[n] |= 0xFFFF0000;\n\n PC += 2;\n}", |
| "possible_exceptions": "Data TLB multiple-hit exception\nSlot illegal instruction exception\nData TLB miss exception\nData TLB protection violation exception" |
| }, |
| "annotations": { |
| "complexity": null, |
| "use_cases": "", |
| "known_issues": "" |
| } |
| }, |
| { |
| "id": "6", |
| "language": "Sleigh", |
| "instruction": "mov.l", |
| "sleigh_code": ":mov.l disppc4,rn_08_11 is opcode_12_15=0b1101 & rn_08_11 & disppc4\n{\n rn_08_11 = *:4 disppc4;\n}", |
| "sleigh_comments": "", |
| "functionality": "", |
| "documentation": { |
| "official_documentation": "Renesas 32-Bit RISC Microcomputer SuperH", |
| "processor": "SuperH", |
| "instruction_details": "Stores immediate data, sign-extended to longword, in general register Rn. The data is stored from memory address (PC + 4 + displacement * 4). The 8-bit displacement is multiplied by four after zero-extension, and so the relative distance from the operand is in the range up to PC + 4 + 1020 bytes. The PC value is the address of this instruction. A value with the lower 2 bits adjusted to 00 is used in address calculation.\n\nNote\nIf the following instruction is a branch instruction, it is identified as a slot illegal instruction.", |
| "feature": "Data Transfer Instruction", |
| "opcode": "0b1101", |
| "example_usage": "void MOVLI (int d, int n)\n{\n unsigned int disp = (0x000000FF & d);\n R[n] = Read_32 ((PC & 0xFFFFFFFC) + 4 + (disp << 2));\n PC += 2;\n}", |
| "possible_exceptions": "Data TLB multiple-hit exception\nSlot illegal instruction exception\nData TLB miss exception\nData TLB protection violation exception" |
| }, |
| "annotations": { |
| "complexity": null, |
| "use_cases": "", |
| "known_issues": "" |
| } |
| }, |
| { |
| "id": "7", |
| "language": "Sleigh", |
| "instruction": "mov.b", |
| "sleigh_code": ":mov.b @rm_04_07,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b0000 \n{\n rn_08_11 = sext(*:1 rm_04_07);\n}", |
| "sleigh_comments": "", |
| "functionality": "", |
| "documentation": { |
| "official_documentation": "Renesas 32-Bit RISC Microcomputer SuperH", |
| "processor": "SuperH", |
| "instruction_details": "Transfers the source operand to the destination. The loaded data is sign-extended to 32 bit before being stored in the destination register.", |
| "feature": "Data Transfer Instruction", |
| "opcode": "0b0110", |
| "example_usage": "void MOVBL (int m, int n)\n{\n R[n] = Read_8 (R[m]);\n if ((R[n] & 0x80) == 0)\n R[n] &= 0x000000FF;\n else\n R[n] |= 0xFFFFFF00;\n\n PC += 2;\n}", |
| "possible_exceptions": "Data TLB multiple-hit exception\nData TLB miss exception\nData TLB protection violation exception\nData address error" |
| }, |
| "annotations": { |
| "complexity": null, |
| "use_cases": "", |
| "known_issues": "" |
| } |
| }, |
| { |
| "id": "8", |
| "language": "Sleigh", |
| "instruction": "mov.w", |
| "sleigh_code": ":mov.w @rm_04_07,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b0001 \n{\n rn_08_11 = sext(*:2 rm_04_07);\n}", |
| "sleigh_comments": "", |
| "functionality": "", |
| "documentation": { |
| "official_documentation": "Renesas 32-Bit RISC Microcomputer SuperH", |
| "processor": "SuperH", |
| "instruction_details": "Transfers the source operand to the destination. The loaded data is sign-extended to 32 bit before being stored in the destination register.", |
| "feature": "Data Transfer Instruction", |
| "opcode": "0b0110", |
| "example_usage": "void MOVWL (int m, int n)\n{\n R[n] = Read_16 (R[m]);\n if ((R[n] & 0x8000) == 0)\n R[n] &= 0x0000FFFF;\n else\n R[n] |= 0xFFFF0000;\n\n PC += 2;\n}", |
| "possible_exceptions": "Data TLB multiple-hit exception\nData TLB miss exception\nData TLB protection violation exception\nData address error" |
| }, |
| "annotations": { |
| "complexity": null, |
| "use_cases": "", |
| "known_issues": "" |
| } |
| }, |
| { |
| "id": "9", |
| "language": "Sleigh", |
| "instruction": "mov.l", |
| "sleigh_code": ":mov.l @rm_04_07,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b0010 \n{\n rn_08_11 = *:4 rm_04_07;\n}", |
| "sleigh_comments": "", |
| "functionality": "", |
| "documentation": { |
| "official_documentation": "Renesas 32-Bit RISC Microcomputer SuperH", |
| "processor": "SuperH", |
| "instruction_details": "Transfers the source operand to the destination", |
| "feature": "Data Transfer Instruction", |
| "opcode": "0b0110", |
| "example_usage": "void MOVLL (int m, int n)\n{\n R[n] = Read_32 (R[m]);\n PC += 2;\n}", |
| "possible_exceptions": "Data TLB multiple-hit exception\nData TLB miss exception\nData TLB protection violation exception\nData address error" |
| }, |
| "annotations": { |
| "complexity": null, |
| "use_cases": "", |
| "known_issues": "" |
| } |
| }, |
| { |
| "id": "10", |
| "language": "Sleigh", |
| "instruction": "mov.b", |
| "sleigh_code": ":mov.b rm_04_07,@rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b0000 \n{\n *:1 rn_08_11 = rm_04_07:1;\n}", |
| "sleigh_comments": "", |
| "functionality": "", |
| "documentation": { |
| "official_documentation": "Renesas 32-Bit RISC Microcomputer SuperH", |
| "processor": "SuperH", |
| "instruction_details": "Transfers the source operand to the destination.", |
| "feature": "Data Transfer Instruction", |
| "opcode": "0010", |
| "example_usage": "void MOVBS (int m, int n)\n{\nWrite_8 (R[n], R[m]);\nPC += 2;\n}", |
| "possible_exceptions":"Data TLB multiple-hit exception\nData TLB miss exception\nData TLB protection violation exception\nData address error" |
| }, |
| "annotations": { |
| "complexity": null, |
| "use_cases": "", |
| "known_issues": "" |
| } |
| }, |
| { |
| "id": "11", |
| "language": "Sleigh", |
| "instruction": "mov.w", |
| "sleigh_code": ":mov.w rm_04_07,@rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b0001 \n{\n *:2 rn_08_11 = rm_04_07:2;\n}", |
| "sleigh_comments": "", |
| "functionality": "", |
| "documentation": { |
| "official_documentation": "Renesas 32-Bit RISC Microcomputer SuperH", |
| "processor": "SuperH", |
| "instruction_details": "Transfers the source operand to the destination.", |
| "feature": "Data Transfer Instruction", |
| "opcode": "0010", |
| "example_usage": "void MOVWS (int m, int n)\n{\n Write_16 (R[n], R[m]);\n PC += 2;\n}", |
| "possible_exceptions":"Data TLB multiple-hit exception\nData TLB miss exception\nData TLB protection violation exception\nData address error" |
| }, |
| "annotations": { |
| "complexity": null, |
| "use_cases": "", |
| "known_issues": "" |
| } |
| }, |
| { |
| "id": "12", |
| "language": "Sleigh", |
| "instruction": "mov.l", |
| "sleigh_code": ":mov.l rm_04_07,@rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b0010 \n{\n *:4 rn_08_11 = rm_04_07;\n}", |
| "sleigh_comments": "", |
| "functionality": "", |
| "documentation": { |
| "official_documentation": "Renesas 32-Bit RISC Microcomputer SuperH", |
| "processor": "SuperH", |
| "instruction_details": "Transfers the source operand to the destination.", |
| "feature": "Data Transfer Instruction", |
| "opcode": "0010", |
| "example_usage": "void MOVLS (int m, int n)\n{\n Write_32 (R[n], R[m]);\n PC += 2;\n}", |
| "possible_exceptions":"Data TLB multiple-hit exception\nData TLB miss exception\nData TLB protection violation exception\nData address error" |
| }, |
| "annotations": { |
| "complexity": null, |
| "use_cases": "", |
| "known_issues": "" |
| } |
| }, |
| { |
| "id": "13", |
| "language": "Sleigh", |
| "instruction": "mov.b", |
| "sleigh_code": ":mov.b @rm_04_07+,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b0100 & (opcode_04_07=opcode_08_11)\n{\n rn_08_11 = sext(*:1 rm_04_07);\n}", |
| "sleigh_comments": "the following two instructions share the same opcodes but differ if rm == rn", |
| "functionality": "", |
| "documentation": { |
| "official_documentation": "Renesas 32-Bit RISC Microcomputer SuperH", |
| "processor": "SuperH", |
| "instruction_details": "Transfers the source operand to the destination. The loaded data is sign-extended to 32 bit before being stored in the destination register.", |
| "feature": "Data Transfer Instruction", |
| "opcode": "0110", |
| "example_usage": "void MOVBP (int m, int n)\n{\n R[n] = Read_8 (R[m]);\n if ((R[n] & 0x80) == 0)\n R[n] &= 0x000000FF;\n else\n R[n] |= 0xFFFFFF00;\n if (n != m)\n R[m] += 1;\n PC += 2;\n}", |
| "possible_exceptions":"Data TLB multiple-hit exception\nData TLB miss exception\nData TLB protection violation exception\nData address error\nInitial page write exception" |
| }, |
| "annotations": { |
| "complexity": null, |
| "use_cases": "", |
| "known_issues": "" |
| } |
| }, |
| { |
| "id": "14", |
| "language": "Sleigh", |
| "instruction": "mov.w", |
| "sleigh_code": ":mov.w @rm_04_07+,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b0101 & (opcode_04_07=opcode_08_11)\n{\n rn_08_11 = sext(*:2 rm_04_07);\n}", |
| "sleigh_comments": "the following two instructions share the same opcodes but differ if rm == rn", |
| "functionality": "", |
| "documentation": { |
| "official_documentation": "Renesas 32-Bit RISC Microcomputer SuperH", |
| "processor": "SuperH", |
| "instruction_details": "Transfers the source operand to the destination.The loaded data is sign-extended to 32 bit before being stored in the destination register.", |
| "feature": "Data Transfer Instruction", |
| "opcode": "0110", |
| "example_usage": "void MOVWP (int m, int n)\n{\n R[n] = Read_16 (R[m]);\n if ((R[n] & 0x8000) == 0)\n R[n] &= 0x0000FFFF;\n else\n R[n] |= 0xFFFF0000;\n if (n != m)\n R[m] += 2;\n PC += 2;\n}", |
| "possible_exceptions":"Data TLB multiple-hit exception\nData TLB miss exception\nData TLB protection violation exception\nData address error\nInitial page write exception" |
| }, |
| "annotations": { |
| "complexity": null, |
| "use_cases": "", |
| "known_issues": "" |
| } |
| }, |
| { |
| "id": "15", |
| "language": "Sleigh", |
| "instruction": "mov.l", |
| "sleigh_code": ":mov.l @rm_04_07+,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b0110 & (opcode_04_07=opcode_08_11)\n{\n rn_08_11 = *:4 rm_04_07;\n}", |
| "sleigh_comments": "the following two instructions share the same opcodes but differ if rm == rn", |
| "functionality": "", |
| "documentation": { |
| "official_documentation": "Renesas 32-Bit RISC Microcomputer SuperH", |
| "processor": "SuperH", |
| "instruction_details": "Transfers the source operand to the destination.", |
| "feature": "Data Transfer Instruction", |
| "opcode": "0110", |
| "example_usage": "void MOVLP (int m, int n)\n{\n R[n] = Read_32 (R[m]);\n if (n != m)\n R[m] += 4;\n PC += 2;\n}", |
| "possible_exceptions":"Data TLB multiple-hit exception\nData TLB miss exception\nData TLB protection violation exception\n Data address error\nInitial page write exception" |
| }, |
| "annotations": { |
| "complexity": null, |
| "use_cases": "", |
| "known_issues": "" |
| } |
| }, |
| { |
| "id": "16", |
| "language": "Sleigh", |
| "instruction": "mov.b", |
| "sleigh_code": ":mov.b rm_04_07,@-rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b0100\n{\n rn_08_11 = rn_08_11 -1;\n *:1 rn_08_11 = rm_04_07;\n}", |
| "sleigh_comments": "", |
| "functionality": "", |
| "documentation": { |
| "official_documentation": "Renesas 32-Bit RISC Microcomputer SuperH", |
| "processor": "SuperH", |
| "instruction_details": "Transfers the source operand to the destination.", |
| "feature": "Data Transfer Instruction", |
| "opcode": "0010", |
| "example_usage": "void MOVBM (int m, int n)\n{\n Write_8 (R[n] - 1, R[m]);\n R[n] -= 1;\n PC += 2;\n}", |
| "possible_exceptions":"Data address error" |
| }, |
| "annotations": { |
| "complexity": null, |
| "use_cases": "", |
| "known_issues": "" |
| } |
| }, |
| { |
| "id": "17", |
| "language": "Sleigh", |
| "instruction": "mov.w", |
| "sleigh_code": ":mov.w rm_04_07,@-rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b0101\n{\n rn_08_11 = rn_08_11 -2;\n *:2 rn_08_11 = rm_04_07;\n}", |
| "sleigh_comments": "", |
| "functionality": "", |
| "documentation": { |
| "official_documentation": "Renesas 32-Bit RISC Microcomputer SuperH", |
| "processor": "SuperH", |
| "instruction_details": "Transfers the source operand to the destination.", |
| "feature": "Data Transfer Instruction", |
| "opcode": "0010", |
| "example_usage": "void MOVWM (int m, int n)\n{\n Write_16 (R[n] - 2, R[m]);\n R[n] -= 2;\n PC += 2;\n}", |
| "possible_exceptions":"Data TLB multiple-hit exception\nData TLB miss exception\nData TLB protection violation exception\nData address error\nInitial page write exception" |
| }, |
| "annotations": { |
| "complexity": null, |
| "use_cases": "", |
| "known_issues": "" |
| } |
| }, |
| { |
| "id": "18", |
| "language": "Sleigh", |
| "instruction": "mov.l", |
| "sleigh_code": ":mov.l rm_04_07,@-rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b0110\n{\n rn_08_11 = rn_08_11 -4;\n *:4 rn_08_11 = rm_04_07;\n}", |
| "sleigh_comments": "", |
| "functionality": "", |
| "documentation": { |
| "official_documentation": "Renesas 32-Bit RISC Microcomputer SuperH", |
| "processor": "SuperH", |
| "instruction_details": "Transfers the source operand to the destination.", |
| "feature": "Data Transfer Instruction", |
| "opcode": "0010", |
| "example_usage": "void MOVLM (int m, int n)\n{\n Write_32 (R[n] - 4, R[m]);\n R[n] -= 4;\n PC += 2;\n}", |
| "possible_exceptions":"Data TLB multiple-hit exception\nData TLB miss exception\nData TLB protection violation exception\nData address error\nInitial page write exception" |
| }, |
| "annotations": { |
| "complexity": null, |
| "use_cases": "", |
| "known_issues": "" |
| } |
| }, |
| { |
| "id": "19", |
| "language": "Sleigh", |
| "instruction": "mov.b", |
| "sleigh_code": ":mov.b @-rm_08_11, r0\n is r0 & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b11001011\n{\n rm_08_11 = rm_08_11 - 1;\n r0 = sext(*:1 (rm_08_11));\n}", |
| "sleigh_comments": "MOV.B @-Rm, R0 0100mmmm11001011 Rm - 1 → Rm, (Rm) → sign extension → R0", |
| "functionality": "", |
| "documentation": { |
| "official_documentation": "Renesas 32-Bit RISC Microcomputer SuperH", |
| "processor": "SuperH", |
| "instruction_details": "Transfers the source operand to the destination.", |
| "feature": "Data Transfer Instruction", |
| "opcode": "0100", |
| "example_usage": "void MOVRSBM (int m)\n{\n R[m] -= 1;\n R[0] = Read_16 (R[m]);\n if ((R[0] & 0x80) == 0)\n R[0] &= 0x000000FF;\n else\n R[0] |= 0xFFFFFF00;\n PC+=2;\n}", |
| "possible_exceptions":"Data address error" |
| }, |
| "annotations": { |
| "complexity": null, |
| "use_cases": "", |
| "known_issues": "" |
| } |
| }, |
| { |
| "id": "20", |
| "language": "Sleigh", |
| "instruction": "mov.w", |
| "sleigh_code": ":mov.w @-rm_08_11, r0 is r0 & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b11011011 \n{\n rm_08_11 = rm_08_11 - 2;\n r0 = sext(*:2 (rm_08_11));\n}", |
| "sleigh_comments": "MOV.W @-Rm, R0 0100mmmm11011011 Rm - 2 → Rm, (Rm) → sign extension → R0", |
| "functionality": "", |
| "documentation": { |
| "official_documentation": "Renesas 32-Bit RISC Microcomputer SuperH", |
| "processor": "SuperH", |
| "instruction_details": "Transfers the source operand to the destination. The loaded data is sign-extended to 32 bit before being stored in the destination register.", |
| "feature": "Data Transfer Instruction", |
| "opcode": "0100", |
| "example_usage": "void MOVRSWM (int m) \n{\n R[m]-= 2;\n R[0] = Read_16 (R[m]);\n if ((R[0] & 0x8000) == 0)\n R[0] &= 0x0000FFFF;\n else \n R[0] |= 0xFFFF0000; \n PC += 2;\n}", |
| "possible_exceptions": "Data address error" |
| }, |
| "annotations": { |
| "complexity": null, |
| "use_cases": "", |
| "known_issues": "" |
| } |
| }, |
| { |
| "id": "21", |
| "language": "Sleigh", |
| "instruction": "mov.l", |
| "sleigh_code": ":mov.l @-rm_08_11, r0\n is r0 & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b11101011\n{\n rm_08_11 = rm_08_11 - 4;\n r0 = *:4 (rm_08_11);\n}", |
| "sleigh_comments": "MOV.L @-Rm, R0 0100mmmm11101011 Rm - 4 → Rm, (Rm) → R0", |
| "functionality": "", |
| "documentation": { |
| "official_documentation": "Renesas 32-Bit RISC Microcomputer SuperH", |
| "processor": "SuperH", |
| "instruction_details": "Transfers the source operand to the destination..", |
| "feature": "Data Transfer Instruction", |
| "opcode": "0100", |
| "example_usage": "void MOVRSLM (int m)\n{\n R[m] -= 4;\n R[0] = Read_32 (R[m]);\n PC += 2;\n}", |
| "possible_exceptions": "Data address error" |
| }, |
| "annotations": { |
| "complexity": null, |
| "use_cases": "", |
| "known_issues": "" |
| } |
| }, |
| { |
| "id": "22", |
| "language": "Sleigh", |
| "instruction": "mov.b", |
| "sleigh_code": ":mov.b r0, @rn_08_11+\n is r0 & opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b10001011\n{\n *:1 (rn_08_11) = r0;\n rn_08_11 = rn_08_11 + 1;\n}", |
| "sleigh_comments": "MOV.B R0, @Rn+ 0100nnnn10001011 R0 → (Rn), Rn + 1 → Rn", |
| "functionality": "", |
| "documentation": { |
| "official_documentation": "Renesas 32-Bit RISC Microcomputer SuperH", |
| "processor": "SuperH", |
| "instruction_details": "Transfers the source operand to the destination.", |
| "feature": "Data Transfer Instruction", |
| "opcode": "0100", |
| "example_usage": "void MOVRSBP (int n)\n{\n Write_8 (R[n], R[0]);\n R[n] += 1;\n PC += 2;\n}", |
| "possible_exceptions": "Data address error" |
| }, |
| "annotations": { |
| "complexity": null, |
| "use_cases": "", |
| "known_issues": "" |
| } |
| }, |
| { |
| "id": "23", |
| "language": "Sleigh", |
| "instruction": "mov.w", |
| "sleigh_code": ":mov.w r0, @rn_08_11+\n is r0 & opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b10011011\n{\n *:2 (rn_08_11) = r0;\n rn_08_11 = rn_08_11 + 2;\n}", |
| "sleigh_comments": "MOV.W R0, @Rn+ 0100nnnn10011011 R0 → (Rn), Rn + 2 → Rn", |
| "functionality": "", |
| "documentation": { |
| "official_documentation": "Renesas 32-Bit RISC Microcomputer SuperH", |
| "processor": "SuperH", |
| "instruction_details": "Transfers the source operand to the destination.", |
| "feature": "Data Transfer Instruction", |
| "opcode": "0100", |
| "example_usage": "void MOVRSWP (int n)\n{\n Write_16 (R[n], R[0]);\n R[n] += 2;\n PC += 2;\n}", |
| "possible_exceptions": "Data address error" |
| }, |
| "annotations": { |
| "complexity": null, |
| "use_cases": "", |
| "known_issues": "" |
| } |
| }, |
| { |
| "id": "24", |
| "language": "Sleigh", |
| "instruction": "mov.l", |
| "sleigh_code": ":mov.l r0, @rn_08_11+\n is r0 & opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b10101011\n{\n *:4 (rn_08_11) = r0;\n rn_08_11 = rn_08_11 + 4;\n}", |
| "sleigh_comments": "MOV.L R0, @Rn+ 0100nnnn10101011 R0 → (Rn), Rn + 4 → Rn", |
| "functionality": "", |
| "documentation": { |
| "official_documentation": "Renesas 32-Bit RISC Microcomputer SuperH", |
| "processor": "SuperH", |
| "instruction_details": "Transfers the source operand to the destination.", |
| "feature": "Data Transfer Instruction", |
| "opcode": "0100", |
| "example_usage": "void MOVRSLP (int n)\n{\n Write_32 (R[n], R[0]);\n R[n] += 4;\n PC += 2;\n}", |
| "possible_exceptions": "Data address error" |
| }, |
| "annotations": { |
| "complexity": null, |
| "use_cases": "", |
| "known_issues": "" |
| } |
| }, |
| { |
| "id": "25", |
| "language": "Sleigh", |
| "instruction": "mov.b", |
| "sleigh_code": ":mov.b @(disp_00_03,rm_04_07),r0 is r0 & opcode_08_15=0b10000100 & rm_04_07 & disp_00_03\n{\n r0 = sext(*:1 (disp_00_03 + rm_04_07));\n}", |
| "sleigh_comments": "", |
| "functionality": "", |
| "documentation": { |
| "official_documentation": "Renesas 32-Bit RISC Microcomputer SuperH", |
| "processor": "SuperH", |
| "instruction_details": "Transfers the source operand to the destination. The 4-bit displacement is only zero-extended, so a range up to +15 bytes can be specified. If a memory operand cannot be reached, the @(R0,Rn) mode can be used instead. The loaded data is sign-extended to 32 bit before being stored in the destination register.", |
| "feature": "Data Transfer Instruction", |
| "opcode": "10000100", |
| "example_usage": "void MOVBL4 (int m, int d)\n{\n long disp = (0x0000000F & (long)d);\n R[0] = Read_8 (R[m] + disp);\n if ((R[0] & 0x80) == 0)\n R[0] &= 0x000000FF;\n else\n R[0] |= 0xFFFFFF00;\n PC += 2;\n}", |
| "possible_exceptions": "Data TLB multiple-hit exception\n Data TLB miss exception\n Data TLB protection violation exception\n Data address error" |
| }, |
| "annotations": { |
| "complexity": null, |
| "use_cases": "", |
| "known_issues": "" |
| } |
| }, |
| { |
| "id": "26", |
| "language": "Sleigh", |
| "instruction": "mov.b", |
| "sleigh_code": ":mov.b @(l_disp_00_11, l_rm_20_23), l_rn_24_27 is l_opcode_28_31=0b0011 & l_rn_24_27 & l_rm_20_23 & l_opcode_16_19=0b0001 & l_opcode_12_15=0b0100 & l_disp_00_11\n{\n l_rn_24_27 = sext(*:1 (l_rm_20_23 + l_disp_00_11));\n}", |
| "sleigh_comments": "MOV.B @(disp12, Rm), Rn 0011nnnnmmmm0001 0100dddddddddddd (disp+Rm) → sign extension → Rn", |
| "functionality": "", |
| "documentation": { |
| "official_documentation": "Renesas 32-Bit RISC Microcomputer SuperH", |
| "processor": "SuperH", |
| "instruction_details": "Transfers the source operand to the destination. This instruction is ideal for data access in a structure or the stack. The loaded data is sign-extended to 32 bit before being stored in the destination register.", |
| "feature": "Data Transfer Instruction", |
| "opcode": "0011", |
| "example_usage": "void MOVBL12 (int d, int m, int n)\n{\n long disp = (0x00000FFF & (long)d);\n R[n] = Read_8 (R[m] + disp);\n if ((R[n] & 0x80) == 0)\n R[n] &= 0x000000FF;\n else\n R[n] |= 0xFFFFFF00;\n PC += 4;\n}", |
| "possible_exceptions": "Data address error" |
| }, |
| "annotations": { |
| "complexity": null, |
| "use_cases": "", |
| "known_issues": "" |
| } |
| }, |
| { |
| "id": "27", |
| "language": "Sleigh", |
| "instruction": "movu.b", |
| "sleigh_code": ":movu.b @(l_disp_00_11, l_rm_20_23), l_rn_24_27\n is l_opcode_28_31=0b0011 & l_rn_24_27 & l_rm_20_23 & l_opcode_16_19=0b0001 & l_opcode_12_15=0b1000 & l_disp_00_11\n{\n l_rn_24_27 = zext(*:1 (l_disp_00_11 + l_rm_20_23));\n}", |
| "sleigh_comments": "MOVU.B @(disp12,Rm), Rn 0011nnnnmmmm0001 1000dddddddddddd (disp+Rm) → zero extension → Rn", |
| "functionality": "", |
| "documentation": { |
| "official_documentation": "Renesas 32-Bit RISC Microcomputer SuperH", |
| "processor": "SuperH", |
| "instruction_details": "Transfers the source operand to the destination. This instruction is ideal for data access in a structure or the stack. The loaded data is sign-extended to 32 bit before being stored in the destination register.", |
| "feature": "Data Transfer Instruction", |
| "opcode": "0011", |
| "example_usage": "void MOVBUL12 (int d, int m, int n)\n{\n long disp = (0x00000FFF & (long)d);\n R[n] = Read_8 (R[m] + disp);\n R[n] &= 0x000000FF;\n PC += 4;\n}", |
| "possible_exceptions": "" |
| }, |
| "annotations": { |
| "complexity": null, |
| "use_cases": "", |
| "known_issues": "" |
| } |
| }, |
| { |
| "id": "28", |
| "language": "Sleigh", |
| "instruction": "mov.w", |
| "sleigh_code": ":mov.w @(disp,rm_04_07),r0 is r0 & opcode_08_15=0b10000101 & rm_04_07 & disp_00_03 [ disp = disp_00_03 << 1; ]\n{\n r0 = sext(*:2 (disp + rm_04_07));\n}", |
| "sleigh_comments": "", |
| "functionality": "", |
| "documentation": { |
| "official_documentation": "Renesas 32-Bit RISC Microcomputer SuperH", |
| "processor": "SuperH", |
| "instruction_details": "Transfers the source operand to the destination. The 4-bit displacement is multiplied by two after zero-extension, enabling a range up to +30 bytes to be specified. If a memory operand cannot be reached, the @(R0,Rn) mode can be used instead. The loaded data is sign-extended to 32 bit before being stored in the destination register.", |
| "feature": "Data Transfer Instruction", |
| "opcode": "10000101", |
| "example_usage": "void MOVWL4 (int m, int d)\n long disp = (0x0000000F & (long)d);\n R[0] = Read_16 (R[m] + (disp << 1));\n if ((R[0] & 0x8000) == 0)\n R[0] &= 0x0000FFFF;\n else\n R[0] |= 0xFFFF0000;\n PC += 2;\n}", |
| "possible_exceptions": "Data TLB multiple-hit exception\n Data TLB miss exception\n Data TLB protection violation exception\n Data address error" |
| }, |
| "annotations": { |
| "complexity": null, |
| "use_cases": "", |
| "known_issues": "" |
| } |
| }, |
| { |
| "id": "29", |
| "language": "Sleigh", |
| "instruction": "mov.w", |
| "sleigh_code": ":mov.w @(disp, l_rm_20_23), l_rn_24_27\n is l_opcode_28_31=0b0011 & l_rn_24_27 & l_rm_20_23 & l_opcode_16_19=0b0001 & l_opcode_12_15=0b0101 & l_disp_00_11\n [ disp = 2*l_disp_00_11; ]\n{\n l_rn_24_27 = sext(*:2 (l_rm_20_23 + disp));\n}", |
| "sleigh_comments": "MOV.W @(disp12, Rm), Rn 0011nnnnmmmm0001 0101dddddddddddd (disp×2+Rm) → sign extension → Rn", |
| "functionality": "", |
| "documentation": { |
| "official_documentation": "Renesas 32-Bit RISC Microcomputer SuperH", |
| "processor": "SuperH", |
| "instruction_details": "Transfers the source operand to the destination. This instruction is ideal for data access in a structure or the stack. The loaded data is sign-extended to 32 bit before being stored in the destination register.", |
| "feature": "Data Transfer Instruction", |
| "opcode": "0011", |
| "example_usage": "void MOVWL12 (int d, int m, int n)\n{\n long disp = (0x00000FFF & (long)d);\n R[n] = Read_16 (R[m] + (disp << 1));\n if ((R[n] & 0x8000) == 0)\n R[n] &= 0x0000FFFF;\n else\n R[n] |= 0xFFFF0000;\n PC += 4;\n}", |
| "possible_exceptions": "Data address error" |
| }, |
| "annotations": { |
| "complexity": null, |
| "use_cases": "", |
| "known_issues": "" |
| } |
| } |
|
|
| ] |
| } |
|
|
