openAI-math-dataset / lean /OAI /Computability /BinPacking /Computation /PoweringMachineRowBody.lean
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| import OAI.Computability.BinPacking.Computation.MachineCanonicalOutput | |
| import OAI.Computability.BinPacking.Computation.PoweringGlobalEnumeration | |
| import OAI.Computability.BinPacking.PCP.PoweringFieldPlan | |
| import OAI.Computability.BinPacking.PCP.PoweringRowHeaderSemantics | |
| namespace OAI | |
| namespace BinPackingGames.Foundations.Complexity.PoweringMachineEqualityField | |
| open Turing | |
| open MachineComposition | |
| open PCP | |
| variable {K Λ A : Type} [DecidableEq K] | |
| variable {max l r n d : Nat} | |
| abbrev Alphabet (_ : K) := Bool | |
| abbrev Tape := PoweringMachineTapes.Tape | |
| abbrev State := MachineUnaryEqualityBit.State | |
| abbrev Label (l r : Nat) := | |
| PoweringMachineWord.Label l ⊕ PoweringMachineWord.Label r ⊕ MachineUnaryEqualityBit.Label | |
| def entry (l r : Nat) : Label l r := .inl (PoweringMachineWord.entry l) | |
| def instruction (hl : l ≤ max) (hr : r ≤ max) (placement : Tape max → K) | |
| (left : Fin l → Fin d) (right : Fin r → Fin d) | |
| (labels : Label l r → Λ) (exit : Option Λ) : | |
| Label l r → TM2.Stmt (Alphabet (K := K)) Λ (State A) | |
| | .inl q => PoweringMachineWord.instruction l | |
| (placement ∘ PoweringMachineTapes.wordPlacement hl false) left | |
| (fun z => labels (.inl z)) | |
| (some (labels (.inr (.inl (PoweringMachineWord.entry r))))) q | |
| | .inr (.inl q) => PoweringMachineWord.instruction r | |
| (placement ∘ PoweringMachineTapes.wordPlacement hr true) right | |
| (fun z => labels (.inr (.inl z))) | |
| (some (labels (.inr (.inr .seedLeft)))) q | |
| | .inr (.inr q) => MachineUnaryEqualityBit.instruction | |
| (placement ∘ PoweringMachineTapes.equalityPlacement max) | |
| (fun z => labels (.inr (.inr z))) exit q | |
| def endpoint (graph : PortTables.Table n d) {t : Nat} (vertex : Fin n) | |
| (ports : Fin t → Fin d) : Fin n := | |
| PoweringWalks.wordEnd (PortTables.portGraph graph) t vertex ports | |
| def resultBit (graph : PortTables.Table n d) (vertex : Fin n) | |
| (left : Fin l → Fin d) (right : Fin r → Fin d) : Bool := | |
| decide (endpoint graph vertex left = endpoint graph vertex right) | |
| def wordTapes (graph : PortTables.Table n d) {t : Nat} (h : t ≤ max) | |
| (placement : Tape max → K) (target : Bool) (vertex : Fin n) | |
| (ports : Fin t → Fin d) (base : K → List Bool) : K → List Bool := | |
| PoweringMachineWord.finalTapes graph t | |
| (placement ∘ PoweringMachineTapes.wordPlacement h target) vertex ports base | |
| def finalTapes (graph : PortTables.Table n d) (hl : l ≤ max) (hr : r ≤ max) | |
| (placement : Tape max → K) (vertex : Fin n) | |
| (left : Fin l → Fin d) (right : Fin r → Fin d) (base : K → List Bool) : | |
| K → List Bool := | |
| let afterLeft := wordTapes graph hl placement false vertex left base | |
| let afterBoth := wordTapes graph hr placement true vertex right afterLeft | |
| Function.update afterBoth (placement (.inl 10)) | |
| (MachineUnaryEqualityBit.bitEncoding (resultBit graph vertex left right) ++ | |
| afterBoth (placement (.inl 10))) | |
| def steps (graph : PortTables.Table n d) (vertex : Fin n) | |
| (left : Fin l → Fin d) (right : Fin r → Fin d) : Nat := | |
| PoweringMachineWord.steps graph l vertex left + | |
| PoweringMachineWord.steps graph r vertex right + | |
| MachineUnaryEqualityBit.steps (endpoint graph vertex left).val | |
| (endpoint graph vertex right).val | |
| theorem steps_le (graph : PortTables.Table n d) (vertex : Fin n) | |
| (left : Fin l → Fin d) (right : Fin r → Fin d) : | |
| steps graph vertex left right ≤ | |
| (14 * (l + r) + 10) * (PortTables.tableBits graph).length + 12 * (l + r) + 15 := by | |
| have hl := PoweringMachineWord.steps_le graph l vertex left | |
| have hr := PoweringMachineWord.steps_le graph r vertex right | |
| have he := MachineUnaryEqualityBit.steps_le | |
| (endpoint graph vertex left).val (endpoint graph vertex right).val | |
| have hleft := Nat.le_trans (Nat.le_of_lt (endpoint graph vertex left).isLt) | |
| (PortTables.vertices_le_tableBits_length graph) | |
| have hright := Nat.le_trans (Nat.le_of_lt (endpoint graph vertex right).isLt) | |
| (PortTables.vertices_le_tableBits_length graph) | |
| unfold steps | |
| simp only [Nat.mul_add, Nat.add_mul, Nat.mul_assoc] at hl hr ⊢ | |
| omega | |
| theorem wordTapes_other (graph : PortTables.Table n d) {t : Nat} (h : t ≤ max) | |
| (placement : Tape max → K) (target : Bool) (vertex : Fin n) | |
| (ports : Fin t → Fin d) (base : K → List Bool) (k : K) | |
| (hquery : k ≠ placement (.inl 2)) (hscan : k ≠ placement (.inl 3)) | |
| (hreverse : k ≠ placement (.inl 4)) | |
| (houtput : k ≠ placement (PoweringMachineTapes.endpoint max target)) | |
| (hpositions : ∀ i : Fin max, k ≠ placement (.inr i)) : | |
| wordTapes graph h placement target vertex ports base k = base k := by | |
| apply PoweringMachineWord.finalTapes_other | |
| · simpa only [Function.comp_apply, PoweringMachineTapes.wordPlacement_inl_one, | |
| PoweringMachineTapes.query] using hquery | |
| · simpa only [Function.comp_apply, PoweringMachineTapes.wordPlacement_inl_two, | |
| PoweringMachineTapes.scan] using hscan | |
| · simpa only [Function.comp_apply, PoweringMachineTapes.wordPlacement_inl_three, | |
| PoweringMachineTapes.reverse] using hreverse | |
| · simpa only [Function.comp_apply, PoweringMachineTapes.wordPlacement_inl_five] using houtput | |
| · intro i | |
| simpa only [Function.comp_apply, PoweringMachineTapes.wordPlacement_succ] using | |
| hpositions (Fin.castLE h i) | |
| theorem wordTapes_role (graph : PortTables.Table n d) {t : Nat} (h : t ≤ max) | |
| (placement : Tape max → K) (distinct : Function.Injective placement) | |
| (target : Bool) (vertex : Fin n) (ports : Fin t → Fin d) | |
| (base : K → List Bool) (j : Fin 11) | |
| (hquery : j ≠ 2) (hscan : j ≠ 3) (hreverse : j ≠ 4) | |
| (houtput : j ≠ if target then 7 else 6) : | |
| wordTapes graph h placement target vertex ports base (placement (.inl j)) = | |
| base (placement (.inl j)) := by | |
| apply wordTapes_other | |
| · intro he | |
| exact hquery (Sum.inl.inj (distinct he)) | |
| · intro he | |
| exact hscan (Sum.inl.inj (distinct he)) | |
| · intro he | |
| exact hreverse (Sum.inl.inj (distinct he)) | |
| · intro he | |
| apply houtput | |
| cases target <;> exact Sum.inl.inj (distinct he) | |
| · intro i he | |
| cases distinct he | |
| theorem finalTapes_other (graph : PortTables.Table n d) (hl : l ≤ max) (hr : r ≤ max) | |
| (placement : Tape max → K) (vertex : Fin n) | |
| (left : Fin l → Fin d) (right : Fin r → Fin d) (base : K → List Bool) (k : K) | |
| (hquery : k ≠ placement (.inl 2)) (hscan : k ≠ placement (.inl 3)) | |
| (hreverse : k ≠ placement (.inl 4)) (hleft : k ≠ placement (.inl 6)) | |
| (hright : k ≠ placement (.inl 7)) (hrow : k ≠ placement (.inl 10)) | |
| (hpositions : ∀ i : Fin max, k ≠ placement (.inr i)) : | |
| finalTapes graph hl hr placement vertex left right base k = base k := by | |
| unfold finalTapes | |
| rw [Function.update_of_ne hrow] | |
| rw [wordTapes_other graph hr placement true vertex right _ k | |
| hquery hscan hreverse hright hpositions] | |
| exact wordTapes_other graph hl placement false vertex left base k | |
| hquery hscan hreverse hleft hpositions | |
| theorem finalTapes_role (graph : PortTables.Table n d) (hl : l ≤ max) (hr : r ≤ max) | |
| (placement : Tape max → K) (distinct : Function.Injective placement) (vertex : Fin n) | |
| (left : Fin l → Fin d) (right : Fin r → Fin d) (base : K → List Bool) | |
| (j : Fin 11) (hrole : j = 0 ∨ j = 1 ∨ j = 5 ∨ j = 8 ∨ j = 9) : | |
| finalTapes graph hl hr placement vertex left right base (placement (.inl j)) = | |
| base (placement (.inl j)) := by | |
| apply finalTapes_other | |
| all_goals first | |
| | (intro he; have hij := Sum.inl.inj (distinct he); rcases hrole with rfl | rfl | rfl | rfl | rfl <;> simp at hij) | |
| | (intro i he; cases distinct he) | |
| theorem finalTapes_output (graph : PortTables.Table n d) (hl : l ≤ max) (hr : r ≤ max) | |
| (placement : Tape max → K) (distinct : Function.Injective placement) (vertex : Fin n) | |
| (left : Fin l → Fin d) (right : Fin r → Fin d) (base : K → List Bool) : | |
| finalTapes graph hl hr placement vertex left right base (placement (.inl 10)) = | |
| MachineUnaryEqualityBit.bitEncoding (resultBit graph vertex left right) ++ | |
| base (placement (.inl 10)) := by | |
| unfold finalTapes | |
| rw [Function.update_self, | |
| wordTapes_role graph hr placement distinct true vertex right _ 10 | |
| (by decide) (by decide) (by decide) (by decide), | |
| wordTapes_role graph hl placement distinct false vertex left base 10 | |
| (by decide) (by decide) (by decide) (by decide)] | |
| private theorem joinTrace {X : Type*} {f : X → X} {a b c : X} {u v : Nat} | |
| (first : f^[u] a = b) (second : f^[v] b = c) : f^[u + v] a = c := by | |
| rw [Nat.add_comm, Function.iterate_add_apply, first, second] | |
| theorem fieldTrace (graph : PortTables.Table n d) (hl : l ≤ max) (hr : r ≤ max) | |
| (placement : Tape max → K) (distinct : Function.Injective placement) | |
| (vertex : Fin n) (left : Fin l → Fin d) (right : Fin r → Fin d) | |
| (labels : Label l r → Λ) (exit : Option Λ) | |
| (program : Λ → TM2.Stmt (Alphabet (K := K)) Λ (State A)) | |
| (atLabels : ∀ q, program (labels q) = instruction hl hr placement left right labels exit q) | |
| (base : K → List Bool) | |
| (tableWord : base (placement (.inl 0)) = PortTables.tableBits graph) | |
| (scratchEmpty : base (placement (.inl 5)) = []) | |
| (leftCopyEmpty : base (placement (.inl 8)) = []) | |
| (rightCopyEmpty : base (placement (.inl 9)) = []) | |
| (suffix : List Bool) (sourceWord : base (placement (.inl 1)) = encodeWord vertex.val ++ suffix) | |
| (ambient : A) : | |
| (advance (TM2.step program))^[steps graph vertex left right] | |
| (some ⟨some (labels (entry l r)), MachineUnaryEqualityBit.clean ambient, base⟩) = | |
| some ⟨exit, MachineUnaryEqualityBit.clean ambient, | |
| finalTapes graph hl hr placement vertex left right base⟩ := by | |
| let afterLeft := wordTapes graph hl placement false vertex left base | |
| let afterBoth := wordTapes graph hr placement true vertex right afterLeft | |
| have leftFrame (j : Fin 11) (h2 : j ≠ 2) (h3 : j ≠ 3) (h4 : j ≠ 4) (h6 : j ≠ 6) : | |
| afterLeft (placement (.inl j)) = base (placement (.inl j)) := | |
| wordTapes_role graph hl placement distinct false vertex left base j h2 h3 h4 h6 | |
| have rightFrame (j : Fin 11) (h2 : j ≠ 2) (h3 : j ≠ 3) (h4 : j ≠ 4) (h7 : j ≠ 7) : | |
| afterBoth (placement (.inl j)) = afterLeft (placement (.inl j)) := | |
| wordTapes_role graph hr placement distinct true vertex right afterLeft j h2 h3 h4 h7 | |
| have bothFrame (j : Fin 11) (h2 : j ≠ 2) (h3 : j ≠ 3) (h4 : j ≠ 4) | |
| (h6 : j ≠ 6) (h7 : j ≠ 7) : | |
| afterBoth (placement (.inl j)) = base (placement (.inl j)) := | |
| (rightFrame j h2 h3 h4 h7).trans (leftFrame j h2 h3 h4 h6) | |
| have leftRun := PoweringMachineWord.wordTrace graph l | |
| (placement ∘ PoweringMachineTapes.wordPlacement hl false) | |
| (distinct.comp (PoweringMachineTapes.wordPlacement_injective hl false)) vertex left | |
| (fun q => labels (.inl q)) | |
| (some (labels (.inr (.inl (PoweringMachineWord.entry r))))) program | |
| (fun q => atLabels (.inl q)) base | |
| (by simpa only [Function.comp_apply, PoweringMachineTapes.wordPlacement_inl_zero, | |
| PoweringMachineTapes.table] using tableWord) | |
| (by simpa only [Function.comp_apply, PoweringMachineTapes.wordPlacement_inl_four, | |
| PoweringMachineTapes.scratch] using scratchEmpty) | |
| suffix (by simpa only [Function.comp_apply, PoweringMachineTapes.wordPlacement_first, | |
| PoweringMachineTapes.start] using sourceWord) | |
| (ambient, false, none) none | |
| have rightTable : afterLeft (placement (.inl 0)) = PortTables.tableBits graph := | |
| (leftFrame 0 (by decide) (by decide) (by decide) (by decide)).trans tableWord | |
| have rightScratch : afterLeft (placement (.inl 5)) = [] := | |
| (leftFrame 5 (by decide) (by decide) (by decide) (by decide)).trans scratchEmpty | |
| have rightSource : afterLeft (placement (.inl 1)) = encodeWord vertex.val ++ suffix := | |
| (leftFrame 1 (by decide) (by decide) (by decide) (by decide)).trans sourceWord | |
| have rightRun := PoweringMachineWord.wordTrace graph r | |
| (placement ∘ PoweringMachineTapes.wordPlacement hr true) | |
| (distinct.comp (PoweringMachineTapes.wordPlacement_injective hr true)) vertex right | |
| (fun q => labels (.inr (.inl q))) (some (labels (.inr (.inr .seedLeft)))) program | |
| (fun q => atLabels (.inr (.inl q))) afterLeft | |
| (by simpa only [Function.comp_apply, PoweringMachineTapes.wordPlacement_inl_zero, | |
| PoweringMachineTapes.table] using rightTable) | |
| (by simpa only [Function.comp_apply, PoweringMachineTapes.wordPlacement_inl_four, | |
| PoweringMachineTapes.scratch] using rightScratch) | |
| suffix (by simpa only [Function.comp_apply, PoweringMachineTapes.wordPlacement_first, | |
| PoweringMachineTapes.start] using rightSource) | |
| (ambient, false, none) none | |
| have leftEndpoint : afterBoth (placement (.inl 6)) = | |
| encodeWord (endpoint graph vertex left).val ++ base (placement (.inl 6)) := by | |
| rw [rightFrame 6 (by decide) (by decide) (by decide) (by decide)] | |
| dsimp only [afterLeft, wordTapes] | |
| simpa only [Function.comp_apply, PoweringMachineTapes.wordPlacement_inl_five, | |
| PoweringMachineTapes.endpoint_false, PoweringMachineTapes.leftEndpoint, | |
| wordTapes, endpoint] using leftRun.2 | |
| have rightEndpoint : afterBoth (placement (.inl 7)) = | |
| encodeWord (endpoint graph vertex right).val ++ afterLeft (placement (.inl 7)) := by | |
| dsimp only [afterBoth, wordTapes] | |
| simpa only [Function.comp_apply, PoweringMachineTapes.wordPlacement_inl_five, | |
| PoweringMachineTapes.endpoint_true, PoweringMachineTapes.rightEndpoint, | |
| wordTapes, endpoint] using rightRun.2 | |
| have copiesLeft : afterBoth (placement (.inl 8)) = [] := | |
| (bothFrame 8 (by decide) (by decide) (by decide) (by decide) (by decide)).trans leftCopyEmpty | |
| have copiesRight : afterBoth (placement (.inl 9)) = [] := | |
| (bothFrame 9 (by decide) (by decide) (by decide) (by decide) (by decide)).trans rightCopyEmpty | |
| have scratchBoth : afterBoth (placement (.inl 5)) = [] := | |
| (bothFrame 5 (by decide) (by decide) (by decide) (by decide) (by decide)).trans scratchEmpty | |
| have equalityRun := MachineUnaryEqualityBit.equalityTrace | |
| (placement ∘ PoweringMachineTapes.equalityPlacement max) | |
| (distinct.comp (PoweringMachineTapes.equalityPlacement_injective max)) | |
| (fun q => labels (.inr (.inr q))) exit program (fun q => atLabels (.inr (.inr q))) | |
| afterBoth (endpoint graph vertex left).val (endpoint graph vertex right).val | |
| (base (placement (.inl 6))) (afterLeft (placement (.inl 7))) | |
| (by simpa only [Function.comp_apply, PoweringMachineTapes.equalityPlacement_zero, | |
| PoweringMachineTapes.leftEndpoint] using leftEndpoint) | |
| (by simpa only [Function.comp_apply, PoweringMachineTapes.equalityPlacement_one, | |
| PoweringMachineTapes.rightEndpoint] using rightEndpoint) | |
| (by simpa only [Function.comp_apply, PoweringMachineTapes.equalityPlacement_two, | |
| PoweringMachineTapes.leftCopy] using copiesLeft) | |
| (by simpa only [Function.comp_apply, PoweringMachineTapes.equalityPlacement_three, | |
| PoweringMachineTapes.rightCopy] using copiesRight) | |
| (by simpa only [Function.comp_apply, PoweringMachineTapes.equalityPlacement_four, | |
| PoweringMachineTapes.scratch] using scratchBoth) | |
| ambient | |
| have joined := joinTrace (joinTrace leftRun.1 rightRun.1) equalityRun | |
| simpa only [steps, entry, MachineUnaryEqualityBit.clean, Function.comp_apply, | |
| PoweringMachineTapes.equalityPlacement_five, PoweringMachineTapes.rowOutput, | |
| finalTapes, resultBit, Fin.ext_iff, | |
| afterLeft, afterBoth, wordTapes] using joined | |
| def fieldInTime (graph : PortTables.Table n d) (hl : l ≤ max) (hr : r ≤ max) | |
| (placement : Tape max → K) (distinct : Function.Injective placement) | |
| (vertex : Fin n) (left : Fin l → Fin d) (right : Fin r → Fin d) | |
| (labels : Label l r → Λ) (exit : Option Λ) | |
| (program : Λ → TM2.Stmt (Alphabet (K := K)) Λ (State A)) | |
| (atLabels : ∀ q, program (labels q) = instruction hl hr placement left right labels exit q) | |
| (base : K → List Bool) | |
| (tableWord : base (placement (.inl 0)) = PortTables.tableBits graph) | |
| (scratchEmpty : base (placement (.inl 5)) = []) | |
| (leftCopyEmpty : base (placement (.inl 8)) = []) | |
| (rightCopyEmpty : base (placement (.inl 9)) = []) | |
| (suffix : List Bool) (sourceWord : base (placement (.inl 1)) = encodeWord vertex.val ++ suffix) | |
| (ambient : A) : | |
| StateTransition.EvalsToInTime (TM2.step program) | |
| ⟨some (labels (entry l r)), MachineUnaryEqualityBit.clean ambient, base⟩ | |
| (some ⟨exit, MachineUnaryEqualityBit.clean ambient, | |
| finalTapes graph hl hr placement vertex left right base⟩) | |
| ((14 * (l + r) + 10) * (PortTables.tableBits graph).length + 12 * (l + r) + 15) where | |
| steps := steps graph vertex left right | |
| evals_in_steps := fieldTrace graph hl hr placement distinct vertex left right labels exit program | |
| atLabels base tableWord scratchEmpty leftCopyEmpty rightCopyEmpty suffix sourceWord ambient | |
| steps_le_m := steps_le graph vertex left right | |
| def machine (degree : Nat) (hl : l ≤ max) (hr : r ≤ max) | |
| (left : Fin l → Fin degree) (right : Fin r → Fin degree) : FinTM2 where | |
| K := Tape max | |
| k₀ := .inl 0 | |
| k₁ := .inl 10 | |
| Γ _ := Bool | |
| Λ := Label l r | |
| main := entry l r | |
| σ := State Unit | |
| initialState := MachineUnaryEqualityBit.clean () | |
| m := instruction hl hr id left right id none | |
| end BinPackingGames.Foundations.Complexity.PoweringMachineEqualityField | |
| namespace BinPackingGames.Foundations.Complexity.PoweringMachineRowHeaders | |
| open Turing MachineComposition | |
| open PCP PoweringRowHeaderSemantics | |
| open PoweringMachineTapes | |
| variable {K Λ σ : Type} [DecidableEq K] | |
| variable {vertices d max : Nat} | |
| def headerPlacement {t max : Nat} (h : t ≤ max) : PoweringMachineWord.Tape t → Tape max := | |
| (Equiv.swap (leftEndpoint max) (rowOutput max)) ∘ wordPlacement h false | |
| theorem headerPlacement_injective {t max : Nat} (h : t ≤ max) : | |
| Function.Injective (headerPlacement h) := | |
| (Equiv.swap (leftEndpoint max) (rowOutput max)).injective.comp (wordPlacement_injective h false) | |
| @[simp] theorem headerPlacement_table {t max : Nat} (h : t ≤ max) : | |
| headerPlacement h (.inl 0) = table max := by | |
| simp [headerPlacement, table, leftEndpoint, rowOutput, Equiv.swap_apply_def] | |
| @[simp] theorem headerPlacement_query {t max : Nat} (h : t ≤ max) : | |
| headerPlacement h (.inl 1) = query max := by | |
| simp [headerPlacement, query, leftEndpoint, rowOutput, Equiv.swap_apply_def] | |
| @[simp] theorem headerPlacement_scan {t max : Nat} (h : t ≤ max) : | |
| headerPlacement h (.inl 2) = scan max := by | |
| simp [headerPlacement, scan, leftEndpoint, rowOutput, Equiv.swap_apply_def] | |
| @[simp] theorem headerPlacement_reverse {t max : Nat} (h : t ≤ max) : | |
| headerPlacement h (.inl 3) = reverse max := by | |
| simp [headerPlacement, reverse, leftEndpoint, rowOutput, Equiv.swap_apply_def] | |
| @[simp] theorem headerPlacement_scratch {t max : Nat} (h : t ≤ max) : | |
| headerPlacement h (.inl 4) = scratch max := by | |
| simp [headerPlacement, scratch, leftEndpoint, rowOutput, Equiv.swap_apply_def] | |
| @[simp] theorem headerPlacement_output {t max : Nat} (h : t ≤ max) : | |
| headerPlacement h (.inl 5) = rowOutput max := by | |
| simp [headerPlacement] | |
| @[simp] theorem headerPlacement_start {t max : Nat} (h : t ≤ max) : | |
| headerPlacement h (.inr (PoweringMachineWord.first t)) = start max := by | |
| simp [headerPlacement, start, leftEndpoint, rowOutput, Equiv.swap_apply_def] | |
| @[simp] theorem headerPlacement_succ {t max : Nat} (h : t ≤ max) (i : Fin t) : | |
| headerPlacement h (.inr i.succ) = .inr (Fin.castLE h i) := by | |
| simp [headerPlacement, leftEndpoint, rowOutput, Equiv.swap_apply_def] | |
| abbrev Label (n : Nat) := MachineUnaryAffineAt.Label ⊕ | |
| (MachineUnaryAffineAt.Label ⊕ PoweringMachineWord.Label (n + 1)) | |
| def entry (n : Nat) : Label n := .inl .seed | |
| def tailEntry (n : Nat) (direction : Bool) : Label n := | |
| if direction then .inr (.inr (PoweringMachineWord.entry (n + 1))) else .inr (.inl .seed) | |
| def affineInstruction (source work output : K) (coefficient offset : Nat) | |
| (labels : MachineUnaryAffineAt.Label → Λ) (exit : Option Λ) : | |
| MachineUnaryAffineAt.Label → TM2.Stmt (fun _ : K => Bool) Λ (σ × Option Bool) | |
| | .seed => MachineUnaryAffineAt.seed output offset (labels .scan) | |
| | .scan => MachineUnaryAffineAt.scan source work output coefficient (labels .scan) (labels .restore) | |
| | .restore => Reduction.MachineTransfer.loopAt work source id false (labels .restore) exit | |
| def instruction (n : Nat) (h : n + 1 ≤ max) (placement : Tape max → K) | |
| (ports : Fin (n + 1) → Fin d) (direction : Bool) | |
| (labels : Label n → Λ) (exit : Option Λ) : | |
| Label n → TM2.Stmt (fun _ : K => Bool) Λ (σ × Option Bool) | |
| | .inl q => affineInstruction (placement (start max)) (placement (scratch max)) | |
| (placement (rowOutput max)) (blockSize d n) (reverseOffset d n ports direction) | |
| (fun z => labels (.inl z)) (some (labels (tailEntry n direction))) q | |
| | .inr (.inl q) => PoweringMachineWord.copyInstruction | |
| (placement (start max)) (placement (scratch max)) (placement (rowOutput max)) | |
| (fun z => labels (.inr (.inl z))) exit q | |
| | .inr (.inr q) => PoweringMachineWord.instruction (n + 1) | |
| (placement ∘ headerPlacement h) ports (fun z => labels (.inr (.inr z))) exit q | |
| def afterReverse (n : Nat) (placement : Tape max → K) (vertex : Fin vertices) | |
| (ports : Fin (n + 1) → Fin d) (direction : Bool) (base : K → List Bool) : K → List Bool := | |
| Function.update base (placement (rowOutput max)) | |
| (encodeWord (reverseValue d n vertex ports direction) ++ base (placement (rowOutput max))) | |
| def finalTapes (input : PortTables.Table vertices d) (n : Nat) (h : n + 1 ≤ max) | |
| (placement : Tape max → K) (vertex : Fin vertices) (ports : Fin (n + 1) → Fin d) | |
| (direction : Bool) (base : K → List Bool) : K → List Bool := | |
| let mid := afterReverse n placement vertex ports direction base | |
| if direction then | |
| PoweringMachineWord.finalTapes input (n + 1) (placement ∘ headerPlacement h) vertex ports mid | |
| else Function.update mid (placement (rowOutput max)) | |
| (encodeWord vertex.val ++ mid (placement (rowOutput max))) | |
| def steps (input : PortTables.Table vertices d) (n : Nat) (vertex : Fin vertices) | |
| (ports : Fin (n + 1) → Fin d) (direction : Bool) : Nat := | |
| (2 * (vertex.val + 1) + 1) + | |
| if direction then PoweringMachineWord.steps input (n + 1) vertex ports | |
| else 2 * (vertex.val + 1) + 1 | |
| theorem headerTrace (input : PortTables.Table vertices d) (n : Nat) (h : n + 1 ≤ max) | |
| (placement : Tape max → K) (distinct : Function.Injective placement) | |
| (vertex : Fin vertices) (ports : Fin (n + 1) → Fin d) (direction : Bool) | |
| (labels : Label n → Λ) (exit : Option Λ) | |
| (program : Λ → TM2.Stmt (fun _ : K => Bool) Λ (σ × Option Bool)) | |
| (atLabels : ∀ l, program (labels l) = instruction n h placement ports direction labels exit l) | |
| (base : K → List Bool) (tableWord : base (placement (table max)) = PortTables.tableBits input) | |
| (scratchEmpty : base (placement (scratch max)) = []) (suffix : List Bool) | |
| (sourceWord : base (placement (start max)) = encodeWord vertex.val ++ suffix) | |
| (ambient : σ) (register : Option Bool) : | |
| (advance (TM2.step program))^[steps input n vertex ports direction] | |
| (some ⟨some (labels (entry n)), (ambient, register), base⟩) = | |
| some ⟨exit, (ambient, none), finalTapes input n h placement vertex ports direction base⟩ ∧ | |
| finalTapes input n h placement vertex ports direction base (placement (rowOutput max)) = | |
| encodeWords (headerWords input n vertex ports direction) ++ base (placement (rowOutput max)) := by | |
| have hd (i j : Tape max) (hne : i ≠ j) : placement i ≠ placement j := | |
| fun eq => hne (distinct eq) | |
| have hsourceOut : placement (start max) ≠ placement (rowOutput max) := | |
| hd _ _ (by simp [start, rowOutput]) | |
| have hscratchOut : placement (scratch max) ≠ placement (rowOutput max) := | |
| hd _ _ (by simp [scratch, rowOutput]) | |
| have htableOut : placement (table max) ≠ placement (rowOutput max) := | |
| hd _ _ (by simp [table, rowOutput]) | |
| let mid := afterReverse n placement vertex ports direction base | |
| have hrev := MachineUnaryAffineAt.seededAffineTrace | |
| (placement (start max)) (placement (scratch max)) (placement (rowOutput max)) | |
| (hd _ _ (by simp [start, scratch])) hsourceOut hscratchOut | |
| (blockSize d n) (reverseOffset d n ports direction) | |
| (labels (.inl .seed)) (labels (.inl .scan)) (labels (.inl .restore)) | |
| (some (labels (tailEntry n direction))) program | |
| (atLabels (.inl .seed)) (atLabels (.inl .scan)) (atLabels (.inl .restore)) | |
| base vertex.val suffix sourceWord scratchEmpty ambient register | |
| have hreverseTrace : (advance (TM2.step program))^[2 * (vertex.val + 1) + 1] | |
| (some ⟨some (labels (entry n)), (ambient, register), base⟩) = | |
| some ⟨some (labels (tailEntry n direction)), (ambient, none), mid⟩ := by | |
| simpa only [entry, mid, afterReverse, reverseValue] using hrev | |
| have hmidSource : mid (placement (start max)) = encodeWord vertex.val ++ suffix := by | |
| simpa only [mid, afterReverse, Function.update_of_ne hsourceOut] using sourceWord | |
| have hmidScratch : mid (placement (scratch max)) = [] := by | |
| simpa only [mid, afterReverse, Function.update_of_ne hscratchOut] using scratchEmpty | |
| have hmidTable : mid (placement (table max)) = PortTables.tableBits input := by | |
| simpa only [mid, afterReverse, Function.update_of_ne htableOut] using tableWord | |
| cases direction with | |
| | false => | |
| have hcopy := MachineUnaryAffineAt.seededAffineTrace | |
| (placement (start max)) (placement (scratch max)) (placement (rowOutput max)) | |
| (hd _ _ (by simp [start, scratch])) hsourceOut hscratchOut 1 0 | |
| (labels (.inr (.inl .seed))) (labels (.inr (.inl .scan))) | |
| (labels (.inr (.inl .restore))) exit program | |
| (atLabels (.inr (.inl .seed))) (atLabels (.inr (.inl .scan))) | |
| (atLabels (.inr (.inl .restore))) mid vertex.val suffix hmidSource hmidScratch ambient none | |
| constructor | |
| · rw [steps, ite_eq_right Bool.false_ne_true, Function.iterate_add_apply, hreverseTrace] | |
| simpa only [tailEntry, Bool.false_eq_true, ite_false, finalTapes, Nat.one_mul, | |
| Nat.add_zero] using hcopy | |
| · simp only [finalTapes, Bool.false_eq_true, ite_false, Function.update_self, | |
| afterReverse, headerWords, tailVertex, encodeWords, List.append_nil, List.append_assoc] | |
| | true => | |
| have hword := PoweringMachineWord.wordTrace input (n + 1) | |
| (placement ∘ headerPlacement h) (distinct.comp (headerPlacement_injective h)) vertex ports | |
| (fun z => labels (.inr (.inr z))) exit program (fun z => atLabels (.inr (.inr z))) mid | |
| (by simpa only [Function.comp_apply, headerPlacement_table] using hmidTable) | |
| (by simpa only [Function.comp_apply, headerPlacement_scratch] using hmidScratch) | |
| suffix (by simpa only [Function.comp_apply, headerPlacement_start] using hmidSource) ambient none | |
| constructor | |
| · rw [steps, ite_eq_left rfl, Nat.add_comm, Function.iterate_add_apply, hreverseTrace] | |
| simpa only [tailEntry, ite_true, finalTapes] using hword.1 | |
| · have hout := hword.2 | |
| simp only [Function.comp_apply, headerPlacement_output] at hout | |
| simpa only [finalTapes, ite_true, mid, afterReverse, Function.update_self, | |
| headerWords, tailVertex, encodeWords, List.append_nil, List.append_assoc] using hout | |
| theorem finalTapes_other (input : PortTables.Table vertices d) (n : Nat) (h : n + 1 ≤ max) | |
| (placement : Tape max → K) (vertex : Fin vertices) (ports : Fin (n + 1) → Fin d) | |
| (direction : Bool) (base : K → List Bool) (k : K) | |
| (hquery : k ≠ placement (query max)) (hscan : k ≠ placement (scan max)) | |
| (hreverse : k ≠ placement (reverse max)) (houtput : k ≠ placement (rowOutput max)) | |
| (hpositions : ∀ i : Fin (n + 1), k ≠ placement (.inr (Fin.castLE h i))) : | |
| finalTapes input n h placement vertex ports direction base k = base k := by | |
| cases direction with | |
| | false => simp only [finalTapes, Bool.false_eq_true, ite_false, | |
| Function.update_of_ne houtput, afterReverse] | |
| | true => | |
| let mid := afterReverse n placement vertex ports true base | |
| have hw := PoweringMachineWord.finalTapes_other input (n + 1) | |
| (placement ∘ headerPlacement h) vertex ports mid k | |
| (by simpa only [Function.comp_apply, headerPlacement_query] using hquery) | |
| (by simpa only [Function.comp_apply, headerPlacement_scan] using hscan) | |
| (by simpa only [Function.comp_apply, headerPlacement_reverse] using hreverse) | |
| (by simpa only [Function.comp_apply, headerPlacement_output] using houtput) | |
| (fun i => by simpa only [Function.comp_apply, headerPlacement_succ] using hpositions i) | |
| calc | |
| _ = mid k := hw | |
| _ = base k := by simp only [mid, afterReverse, Function.update_of_ne houtput] | |
| theorem finalTapes_shared (input : PortTables.Table vertices d) (n : Nat) (h : n + 1 ≤ max) | |
| (placement : Tape max → K) (distinct : Function.Injective placement) | |
| (vertex : Fin vertices) (ports : Fin (n + 1) → Fin d) | |
| (direction : Bool) (base : K → List Bool) (i : Fin 11) | |
| (hquery : i ≠ 2) (hscan : i ≠ 3) (hreverse : i ≠ 4) (houtput : i ≠ 10) : | |
| finalTapes input n h placement vertex ports direction base (placement (.inl i)) = | |
| base (placement (.inl i)) := by | |
| apply finalTapes_other input n h placement vertex ports direction base | |
| · intro heq; exact hquery (Sum.inl.inj (distinct heq)) | |
| · intro heq; exact hscan (Sum.inl.inj (distinct heq)) | |
| · intro heq; exact hreverse (Sum.inl.inj (distinct heq)) | |
| · intro heq; exact houtput (Sum.inl.inj (distinct heq)) | |
| · intro j heq; cases distinct heq | |
| theorem steps_le (input : PortTables.Table vertices d) (n : Nat) (vertex : Fin vertices) | |
| (ports : Fin (n + 1) → Fin d) (direction : Bool) : | |
| steps input n vertex ports direction ≤ | |
| (14 * (n + 1) + 4) * (PortTables.tableBits input).length + 12 * (n + 1) + 6 := by | |
| have hv : vertex.val ≤ (PortTables.tableBits input).length := | |
| Nat.le_trans (Nat.le_of_lt vertex.isLt) (PortTables.vertices_le_tableBits_length input) | |
| have hw := PoweringMachineWord.steps_le input (n + 1) vertex ports | |
| cases direction <;> simp only [steps, Bool.false_eq_true, ite_false, ite_true] | |
| · simp only [Nat.add_mul] | |
| omega | |
| · calc | |
| _ ≤ (2 * (PortTables.tableBits input).length + 3) + | |
| ((14 * (n + 1) + 2) * (PortTables.tableBits input).length + 12 * (n + 1) + 3) := | |
| Nat.add_le_add (by omega) hw | |
| _ = _ := by simp only [Nat.add_mul]; omega | |
| def machine (degree n : Nat) (ports : Fin (n + 1) → Fin degree) (direction : Bool) : FinTM2 where | |
| K := PoweringMachineTapes.Tape (n + 1) | |
| k₀ := table (n + 1) | |
| k₁ := rowOutput (n + 1) | |
| Γ _ := Bool | |
| Λ := Label n | |
| main := entry n | |
| σ := (Unit × Bool × Option Bool) × Option Bool | |
| initialState := (((), false, none), none) | |
| m := instruction n (Nat.le_refl (n + 1)) id ports direction id none | |
| end BinPackingGames.Foundations.Complexity.PoweringMachineRowHeaders | |
| namespace BinPackingGames.Foundations.Complexity.PoweringMachineField | |
| open Turing MachineComposition PCP PoweringFieldPlan | |
| variable {K Λ A : Type} [DecidableEq K] {n d max : Nat} | |
| abbrev Tape := PoweringMachineTapes.Tape | |
| abbrev State := MachineUnaryEqualityBit.State | |
| def Label : Instruction d → Type | |
| | .relation path _ _ _ => PoweringMachineRelationField.Label path | |
| | .equal left right => PoweringMachineEqualityField.Label left.length right.length | |
| instance labelFintype (op : Instruction d) : Fintype (Label op) := by | |
| cases op <;> dsimp only [Label] <;> infer_instance | |
| instance labelDecidableEq (op : Instruction d) : DecidableEq (Label op) := by | |
| cases op <;> dsimp only [Label] <;> infer_instance | |
| def entry : (op : Instruction d) → Label op | |
| | .relation path _ _ _ => .inl (PoweringMachineWord.entry path.length) | |
| | .equal left right => PoweringMachineEqualityField.entry left.length right.length | |
| def instruction (placement : Tape max → K) : (op : Instruction d) → op.radius ≤ max → | |
| (Label op → Λ) → Option Λ → Label op → TM2.Stmt (fun _ : K => Bool) Λ (State A) | |
| | .relation path port a b, bounded, labels, exit => | |
| PoweringMachineRelationField.instruction placement path bounded port a b labels exit | |
| | .equal left right, bounded, labels, exit => | |
| PoweringMachineEqualityField.instruction | |
| ((le_max_left _ _).trans bounded) ((le_max_right _ _).trans bounded) | |
| placement left.get right.get labels exit | |
| def finalTapes (graph : PortTables.Table n d) (placement : Tape max → K) | |
| (vertex : Fin n) : (op : Instruction d) → op.radius ≤ max → | |
| (K → List Bool) → K → List Bool | |
| | .relation path port a b, bounded, base => | |
| PoweringMachineRelationField.finalTapes placement path bounded port a b graph vertex base | |
| | .equal left right, bounded, base => | |
| PoweringMachineEqualityField.finalTapes graph | |
| ((le_max_left _ _).trans bounded) ((le_max_right _ _).trans bounded) | |
| placement vertex left.get right.get base | |
| def steps (graph : PortTables.Table n d) (vertex : Fin n) : Instruction d → Nat | |
| | .relation path port a b => PoweringMachineRelationField.steps path port a b graph vertex | |
| | .equal left right => PoweringMachineEqualityField.steps graph vertex left.get right.get | |
| structure Ready (graph : PortTables.Table n d) (placement : Tape max → K) | |
| (vertex : Fin n) (suffix : List Bool) (tapes : K → List Bool) : Prop where | |
| table : tapes (placement (.inl 0)) = PortTables.tableBits graph | |
| source : tapes (placement (.inl 1)) = encodeWord vertex.val ++ suffix | |
| scratch : tapes (placement (.inl 5)) = [] | |
| leftCopy : tapes (placement (.inl 8)) = [] | |
| rightCopy : tapes (placement (.inl 9)) = [] | |
| theorem finalTapes_role (graph : PortTables.Table n d) (placement : Tape max → K) | |
| (distinct : Function.Injective placement) (vertex : Fin n) | |
| (op : Instruction d) (bounded : op.radius ≤ max) (base : K → List Bool) | |
| (j : Fin 11) (role : j = 0 ∨ j = 1 ∨ j = 5 ∨ j = 8 ∨ j = 9) : | |
| finalTapes graph placement vertex op bounded base (placement (.inl j)) = | |
| base (placement (.inl j)) := by | |
| cases op with | |
| | relation path port a b => | |
| apply PoweringMachineRelationField.finalTapes_frame placement distinct path bounded | |
| port a b graph vertex base j | |
| all_goals rcases role with rfl | rfl | rfl | rfl | rfl <;> decide | |
| | equal left right => | |
| exact PoweringMachineEqualityField.finalTapes_role graph _ _ placement distinct | |
| vertex left.get right.get base j role | |
| theorem ready_finalTapes (graph : PortTables.Table n d) (placement : Tape max → K) | |
| (distinct : Function.Injective placement) (vertex : Fin n) | |
| (op : Instruction d) (bounded : op.radius ≤ max) (base : K → List Bool) | |
| (suffix : List Bool) (ready : Ready graph placement vertex suffix base) : | |
| Ready graph placement vertex suffix (finalTapes graph placement vertex op bounded base) := by | |
| constructor | |
| · rw [finalTapes_role graph placement distinct vertex op bounded base 0 (by simp)] | |
| exact ready.table | |
| · rw [finalTapes_role graph placement distinct vertex op bounded base 1 (by simp)] | |
| exact ready.source | |
| · rw [finalTapes_role graph placement distinct vertex op bounded base 5 (by simp)] | |
| exact ready.scratch | |
| · rw [finalTapes_role graph placement distinct vertex op bounded base 8 (by simp)] | |
| exact ready.leftCopy | |
| · rw [finalTapes_role graph placement distinct vertex op bounded base 9 (by simp)] | |
| exact ready.rightCopy | |
| theorem finalTapes_other (graph : PortTables.Table n d) (placement : Tape max → K) | |
| (vertex : Fin n) (op : Instruction d) (bounded : op.radius ≤ max) | |
| (base : K → List Bool) (k : K) (outside : ∀ i, k ≠ placement i) : | |
| finalTapes graph placement vertex op bounded base k = base k := by | |
| cases op with | |
| | relation path port a b => | |
| exact PoweringMachineRelationField.finalTapes_other placement path bounded port a b | |
| graph vertex base k outside | |
| | equal left right => | |
| exact PoweringMachineEqualityField.finalTapes_other graph _ _ placement vertex | |
| left.get right.get base k (outside _) (outside _) (outside _) (outside _) | |
| (outside _) (outside _) (fun i => outside _) | |
| theorem fieldTrace (graph : PortTables.Table n d) (placement : Tape max → K) | |
| (distinct : Function.Injective placement) (vertex : Fin n) | |
| (op : Instruction d) (bounded : op.radius ≤ max) | |
| (labels : Label op → Λ) (exit : Option Λ) | |
| (program : Λ → TM2.Stmt (fun _ : K => Bool) Λ (State A)) | |
| (atLabels : ∀ l, program (labels l) = instruction placement op bounded labels exit l) | |
| (base : K → List Bool) (suffix : List Bool) | |
| (ready : Ready graph placement vertex suffix base) (ambient : A) : | |
| (advance (TM2.step program))^[steps graph vertex op] | |
| (some ⟨some (labels (entry op)), MachineUnaryEqualityBit.clean ambient, base⟩) = | |
| some ⟨exit, MachineUnaryEqualityBit.clean ambient, | |
| finalTapes graph placement vertex op bounded base⟩ := by | |
| cases op with | |
| | relation path port a b => | |
| exact (PoweringMachineRelationField.fieldTrace placement distinct path bounded port a b | |
| labels exit program atLabels graph vertex base ready.table ready.scratch suffix | |
| ready.source ambient).1 | |
| | equal left right => | |
| exact PoweringMachineEqualityField.fieldTrace graph _ _ placement distinct | |
| vertex left.get right.get labels exit program atLabels base ready.table ready.scratch | |
| ready.leftCopy ready.rightCopy suffix ready.source ambient | |
| theorem finalTapes_output (graph : PortTables.Table n d) (placement : Tape max → K) | |
| (distinct : Function.Injective placement) (vertex : Fin n) | |
| (op : Instruction d) (bounded : op.radius ≤ max) (base : K → List Bool) | |
| (suffix : List Bool) (ready : Ready graph placement vertex suffix base) : | |
| finalTapes graph placement vertex op bounded base (placement (.inl 10)) = | |
| PoweringMachineRow.encodeBit (evaluate graph vertex op) ++ base (placement (.inl 10)) := by | |
| cases op with | |
| | relation path port a b => | |
| have h := (PoweringMachineRelationField.fieldTrace placement distinct path bounded port a b | |
| id none (PoweringMachineRelationField.instruction placement path bounded port a b id none) | |
| (fun _ => rfl) graph vertex base ready.table ready.scratch suffix ready.source ()).2 | |
| have he : ∀ bit : Bool, encodeWord (GraphTables.bitWord bit) = | |
| PoweringMachineRow.encodeBit bit := by intro bit; cases bit <;> rfl | |
| simpa only [finalTapes, PoweringMachineRelationField.bit, PoweringMachineRelationField.endpoint, | |
| evaluate, he] using h | |
| | equal left right => | |
| have h := PoweringMachineEqualityField.finalTapes_output graph | |
| ((le_max_left _ _).trans bounded) ((le_max_right _ _).trans bounded) placement distinct | |
| vertex left.get right.get base | |
| have he : ∀ bit : Bool, MachineUnaryEqualityBit.bitEncoding bit = | |
| PoweringMachineRow.encodeBit bit := by intro bit; cases bit <;> rfl | |
| simpa only [finalTapes, PoweringMachineEqualityField.resultBit, PoweringMachineEqualityField.endpoint, | |
| PoweringReach.wordEnd_eq_walkEnd_ofFn, List.ofFn_get, evaluate, he] using h | |
| end BinPackingGames.Foundations.Complexity.PoweringMachineField | |
| namespace BinPackingGames.Foundations.Complexity.PoweringMachinePlan | |
| open Turing MachineComposition PCP PoweringFieldPlan | |
| variable {K Λ A : Type} [DecidableEq K] {vertices d max : Nat} | |
| abbrev Command (d max : Nat) := {op : Instruction d // op.radius ≤ max} | |
| abbrev LocalLabel (op : Command d max) := PoweringMachineField.Label op.val | |
| abbrev Label (commands : List (Command d max)) := MachineFiniteSequence.Label LocalLabel commands | |
| def entry (commands : List (Command d max)) (labels : Label commands → Λ) (exit : Option Λ) : Option Λ := | |
| MachineFiniteSequence.entry LocalLabel (fun op => PoweringMachineField.entry op.val) | |
| commands labels exit | |
| def instruction (placement : PoweringMachineTapes.Tape max → K) | |
| (commands : List (Command d max)) (labels : Label commands → Λ) (exit : Option Λ) : | |
| Label commands → TM2.Stmt (fun _ : K => Bool) Λ (MachineUnaryEqualityBit.State A) := | |
| MachineFiniteSequence.instruction LocalLabel (fun op => PoweringMachineField.entry op.val) | |
| (fun op => PoweringMachineField.instruction placement op.val op.property) | |
| commands labels exit | |
| def result (graph : PortTables.Table vertices d) (placement : PoweringMachineTapes.Tape max → K) | |
| (vertex : Fin vertices) (op : Command d max) (base : K → List Bool) : K → List Bool := | |
| PoweringMachineField.finalTapes graph placement vertex op.val op.property base | |
| def finalTapes (graph : PortTables.Table vertices d) (placement : PoweringMachineTapes.Tape max → K) | |
| (vertex : Fin vertices) (commands : List (Command d max)) (base : K → List Bool) : K → List Bool := | |
| MachineFiniteSequence.resultOf (result graph placement vertex) commands base | |
| def steps (graph : PortTables.Table vertices d) (placement : PoweringMachineTapes.Tape max → K) | |
| (vertex : Fin vertices) (commands : List (Command d max)) (base : K → List Bool) : Nat := | |
| MachineFiniteSequence.steps (result graph placement vertex) | |
| (fun op _ => PoweringMachineField.steps graph vertex op.val) commands base | |
| theorem planTrace (graph : PortTables.Table vertices d) | |
| (placement : PoweringMachineTapes.Tape max → K) (distinct : Function.Injective placement) | |
| (vertex : Fin vertices) (commands : List (Command d max)) | |
| (labels : Label commands → Λ) (exit : Option Λ) | |
| (program : Λ → TM2.Stmt (fun _ : K => Bool) Λ (MachineUnaryEqualityBit.State A)) | |
| (atLabels : ∀ l, program (labels l) = instruction placement commands labels exit l) | |
| (base : K → List Bool) (suffix : List Bool) | |
| (ready : PoweringMachineField.Ready graph placement vertex suffix base) (ambient : A) : | |
| (advance (TM2.step program))^[steps graph placement vertex commands base] | |
| (some ⟨entry commands labels exit, MachineUnaryEqualityBit.clean ambient, base⟩) = | |
| some ⟨exit, MachineUnaryEqualityBit.clean ambient, | |
| finalTapes graph placement vertex commands base⟩ := by | |
| apply MachineFiniteSequence.trace LocalLabel (fun op => PoweringMachineField.entry op.val) | |
| (fun op => PoweringMachineField.instruction placement op.val op.property) | |
| (result graph placement vertex) (fun op _ => PoweringMachineField.steps graph vertex op.val) | |
| program (PoweringMachineField.Ready graph placement vertex suffix) | |
| (fun _ => MachineUnaryEqualityBit.clean ambient) id commands | |
| · intro op _ tapes good | |
| exact PoweringMachineField.ready_finalTapes graph placement distinct vertex op.val | |
| op.property tapes suffix good | |
| · intro op _ localLabels localExit atLocal tapes good | |
| exact PoweringMachineField.fieldTrace graph placement distinct vertex op.val op.property | |
| localLabels localExit program atLocal tapes suffix good ambient | |
| · exact atLabels | |
| · exact ready | |
| theorem ready_finalTapes (graph : PortTables.Table vertices d) | |
| (placement : PoweringMachineTapes.Tape max → K) (distinct : Function.Injective placement) | |
| (vertex : Fin vertices) (commands : List (Command d max)) (base : K → List Bool) | |
| (suffix : List Bool) (ready : PoweringMachineField.Ready graph placement vertex suffix base) : | |
| PoweringMachineField.Ready graph placement vertex suffix | |
| (finalTapes graph placement vertex commands base) := by | |
| induction commands generalizing base with | |
| | nil => exact ready | |
| | cons op commands ih => | |
| apply ih | |
| exact PoweringMachineField.ready_finalTapes graph placement distinct vertex op.val | |
| op.property base suffix ready | |
| theorem finalTapes_output (graph : PortTables.Table vertices d) | |
| (placement : PoweringMachineTapes.Tape max → K) (distinct : Function.Injective placement) | |
| (vertex : Fin vertices) (commands : List (Command d max)) (base : K → List Bool) | |
| (suffix : List Bool) (ready : PoweringMachineField.Ready graph placement vertex suffix base) : | |
| finalTapes graph placement vertex commands base (placement (.inl 10)) = | |
| PoweringMachineRow.encodeBits ((commands.map (fun op => evaluate graph vertex op.val)).reverse) ++ | |
| base (placement (.inl 10)) := by | |
| induction commands generalizing base with | |
| | nil => rfl | |
| | cons op commands ih => | |
| have nextReady := PoweringMachineField.ready_finalTapes graph placement distinct vertex | |
| op.val op.property base suffix ready | |
| change finalTapes graph placement vertex commands | |
| (result graph placement vertex op base) (placement (.inl 10)) = _ | |
| dsimp only [result] | |
| rw [ih _ nextReady, PoweringMachineField.finalTapes_output graph placement distinct vertex | |
| op.val op.property base suffix ready] | |
| simp only [List.map_cons, List.reverse_cons, PoweringMachineRow.encodeBits_append, | |
| PoweringMachineRow.encodeBits, List.append_nil, | |
| List.append_assoc] | |
| def boundedRowPlan (n : Nat) (ports : Fin (n + 1) → Fin d) (direction : Bool) : | |
| List (Command d (2 * (n + 1))) := | |
| List.ofFn fun i : Fin (PoweringMachineRow.inputSize (n + 1) (PoweringRowData.slotCount d n)) => | |
| let pair := (PoweringMachineRow.inputEquiv (n + 1) (PoweringRowData.slotCount d n)).symm i | |
| ⟨directedFieldPlan n ports direction pair.1 pair.2, | |
| directedFieldPlan_radius n ports direction pair.1 pair.2⟩ | |
| theorem boundedRowPlan_values (n : Nat) (ports : Fin (n + 1) → Fin d) (direction : Bool) : | |
| (boundedRowPlan n ports direction).map Subtype.val = rowPlan n ports direction := by | |
| rw [boundedRowPlan, rowPlan, List.map_ofFn] | |
| rfl | |
| theorem rowPlan_output (graph : PortTables.Table vertices d) | |
| (n : Nat) (ports : Fin (n + 1) → Fin d) (direction : Bool) | |
| (placement : PoweringMachineTapes.Tape (2 * (n + 1)) → K) | |
| (distinct : Function.Injective placement) (vertex : Fin vertices) (base : K → List Bool) | |
| (suffix : List Bool) (ready : PoweringMachineField.Ready graph placement vertex suffix base) : | |
| finalTapes graph placement vertex (boundedRowPlan n ports direction).reverse base | |
| (placement (.inl 10)) = | |
| PoweringRowData.dataTape graph n (direction, vertex, ports) ++ base (placement (.inl 10)) := by | |
| rw [finalTapes_output graph placement distinct vertex _ base suffix ready] | |
| rw [List.map_reverse, List.reverse_reverse, PoweringFieldPlan.dataTape_eq_plan] | |
| have h := congrArg (List.map (evaluate graph vertex)) (boundedRowPlan_values n ports direction) | |
| simpa only [List.map_map, Function.comp_def] using | |
| congrArg (fun bits => PoweringMachineRow.encodeBits bits ++ base (placement (.inl 10))) h | |
| end BinPackingGames.Foundations.Complexity.PoweringMachinePlan | |
| namespace BinPackingGames.Foundations.Complexity.PoweringPlanBudget | |
| open Turing MachineComposition PCP PoweringFieldPlan | |
| variable {K Λ A : Type} [DecidableEq K] {vertices d max : Nat} | |
| def fieldBudget (max inputLength : Nat) : Nat := | |
| (28 * max + 10) * inputLength + 24 * max + 15 | |
| theorem field_steps_le (graph : PortTables.Table vertices d) (vertex : Fin vertices) | |
| (op : Instruction d) (bounded : op.radius ≤ max) : | |
| PoweringMachineField.steps graph vertex op ≤ | |
| fieldBudget max (PortTables.tableBits graph).length := by | |
| cases op with | |
| | relation path port left right => | |
| change path.length ≤ max at bounded | |
| have h := PoweringMachineRelationField.steps_le path port left right graph vertex | |
| have coefficient : 14 * path.length + 9 ≤ 28 * max + 10 := by omega | |
| have product := Nat.mul_le_mul_right (PortTables.tableBits graph).length coefficient | |
| change PoweringMachineRelationField.steps path port left right graph vertex ≤ _ | |
| unfold fieldBudget | |
| omega | |
| | equal left right => | |
| change Nat.max left.length right.length ≤ max at bounded | |
| have hl : left.length ≤ max := (le_max_left _ _).trans bounded | |
| have hr : right.length ≤ max := (le_max_right _ _).trans bounded | |
| have h := PoweringMachineEqualityField.steps_le graph vertex left.get right.get | |
| have coefficient : 14 * (left.length + right.length) + 10 ≤ 28 * max + 10 := by | |
| omega | |
| have product := Nat.mul_le_mul_right (PortTables.tableBits graph).length coefficient | |
| change PoweringMachineEqualityField.steps graph vertex left.get right.get ≤ _ | |
| unfold fieldBudget | |
| omega | |
| theorem plan_steps_le (graph : PortTables.Table vertices d) | |
| (placement : PoweringMachineTapes.Tape max → K) (vertex : Fin vertices) | |
| (commands : List (PoweringMachinePlan.Command d max)) (base : K → List Bool) : | |
| PoweringMachinePlan.steps graph placement vertex commands base ≤ | |
| commands.length * fieldBudget max (PortTables.tableBits graph).length := by | |
| induction commands generalizing base with | |
| | nil => simp only [PoweringMachinePlan.steps, MachineFiniteSequence.steps, | |
| List.length_nil, Nat.zero_mul, Nat.le_refl] | |
| | cons op commands ih => | |
| have first := field_steps_le graph vertex op.val op.property | |
| have rest := ih (PoweringMachinePlan.result graph placement vertex op base) | |
| change PoweringMachineField.steps graph vertex op.val + | |
| PoweringMachinePlan.steps graph placement vertex commands | |
| (PoweringMachinePlan.result graph placement vertex op base) ≤ _ | |
| simpa only [List.length_cons, Nat.add_mul, Nat.one_mul, Nat.add_comm] using | |
| Nat.add_le_add first rest | |
| @[simp] theorem boundedRowPlan_length (n : Nat) | |
| (ports : Fin (n + 1) → Fin d) (direction : Bool) : | |
| (PoweringMachinePlan.boundedRowPlan n ports direction).length = | |
| PoweringMachineRow.inputSize (n + 1) (PoweringRowData.slotCount d n) := by | |
| simp only [PoweringMachinePlan.boundedRowPlan, List.length_ofFn] | |
| def rowBudget (d n inputLength : Nat) : Nat := | |
| PoweringMachineRow.inputSize (n + 1) (PoweringRowData.slotCount d n) * | |
| fieldBudget (2 * (n + 1)) inputLength | |
| theorem rowPlan_steps_le (graph : PortTables.Table vertices d) (n : Nat) | |
| (ports : Fin (n + 1) → Fin d) (direction : Bool) | |
| (placement : PoweringMachineTapes.Tape (2 * (n + 1)) → K) | |
| (vertex : Fin vertices) (base : K → List Bool) : | |
| PoweringMachinePlan.steps graph placement vertex | |
| (PoweringMachinePlan.boundedRowPlan n ports direction).reverse base ≤ | |
| PoweringMachineRow.inputSize (n + 1) (PoweringRowData.slotCount d n) * | |
| ((28 * (2 * (n + 1)) + 10) * (PortTables.tableBits graph).length + | |
| 24 * (2 * (n + 1)) + 15) := by | |
| have h := plan_steps_le graph placement vertex | |
| (PoweringMachinePlan.boundedRowPlan n ports direction).reverse base | |
| simpa only [List.length_reverse, boundedRowPlan_length, fieldBudget] using h | |
| def planInTime (graph : PortTables.Table vertices d) | |
| (placement : PoweringMachineTapes.Tape max → K) (distinct : Function.Injective placement) | |
| (vertex : Fin vertices) (commands : List (PoweringMachinePlan.Command d max)) | |
| (labels : PoweringMachinePlan.Label commands → Λ) (exit : Option Λ) | |
| (program : Λ → TM2.Stmt (fun _ : K => Bool) Λ (MachineUnaryEqualityBit.State A)) | |
| (atLabels : ∀ l, program (labels l) = | |
| PoweringMachinePlan.instruction placement commands labels exit l) | |
| (base : K → List Bool) (suffix : List Bool) | |
| (ready : PoweringMachineField.Ready graph placement vertex suffix base) (ambient : A) : | |
| StateTransition.EvalsToInTime (TM2.step program) | |
| ⟨PoweringMachinePlan.entry commands labels exit, MachineUnaryEqualityBit.clean ambient, base⟩ | |
| (some ⟨exit, MachineUnaryEqualityBit.clean ambient, | |
| PoweringMachinePlan.finalTapes graph placement vertex commands base⟩) | |
| (commands.length * fieldBudget max (PortTables.tableBits graph).length) where | |
| steps := PoweringMachinePlan.steps graph placement vertex commands base | |
| evals_in_steps := PoweringMachinePlan.planTrace graph placement distinct vertex commands | |
| labels exit program atLabels base suffix ready ambient | |
| steps_le_m := plan_steps_le graph placement vertex commands base | |
| def rowPlanInTime (graph : PortTables.Table vertices d) (n : Nat) | |
| (ports : Fin (n + 1) → Fin d) (direction : Bool) | |
| (placement : PoweringMachineTapes.Tape (2 * (n + 1)) → K) | |
| (distinct : Function.Injective placement) (vertex : Fin vertices) | |
| (labels : PoweringMachinePlan.Label | |
| (PoweringMachinePlan.boundedRowPlan n ports direction).reverse → Λ) | |
| (exit : Option Λ) | |
| (program : Λ → TM2.Stmt (fun _ : K => Bool) Λ (MachineUnaryEqualityBit.State A)) | |
| (atLabels : ∀ l, program (labels l) = PoweringMachinePlan.instruction placement | |
| (PoweringMachinePlan.boundedRowPlan n ports direction).reverse labels exit l) | |
| (base : K → List Bool) (suffix : List Bool) | |
| (ready : PoweringMachineField.Ready graph placement vertex suffix base) (ambient : A) : | |
| StateTransition.EvalsToInTime (TM2.step program) | |
| ⟨PoweringMachinePlan.entry (PoweringMachinePlan.boundedRowPlan n ports direction).reverse | |
| labels exit, MachineUnaryEqualityBit.clean ambient, base⟩ | |
| (some ⟨exit, MachineUnaryEqualityBit.clean ambient, | |
| PoweringMachinePlan.finalTapes graph placement vertex | |
| (PoweringMachinePlan.boundedRowPlan n ports direction).reverse base⟩) | |
| (rowBudget d n (PortTables.tableBits graph).length) where | |
| steps := PoweringMachinePlan.steps graph placement vertex | |
| (PoweringMachinePlan.boundedRowPlan n ports direction).reverse base | |
| evals_in_steps := PoweringMachinePlan.planTrace graph placement distinct vertex | |
| (PoweringMachinePlan.boundedRowPlan n ports direction).reverse | |
| labels exit program atLabels base suffix ready ambient | |
| steps_le_m := rowPlan_steps_le graph n ports direction placement vertex base | |
| end BinPackingGames.Foundations.Complexity.PoweringPlanBudget | |
| namespace BinPackingGames.Foundations.Complexity.PoweringMachineRowBody | |
| open Turing MachineComposition PCP | |
| open MachineFixedBlockMap | |
| variable {K Λ : Type} [DecidableEq K] {vertices d : Nat} | |
| abbrev capacity (n : Nat) := 2 * (n + 1) | |
| abbrev bufferSize (d n : Nat) := PoweringMachineRow.inputSize (n + 1) (PoweringRowData.slotCount d n) | |
| abbrev State (d n : Nat) := PoweringMasterState.Master (bufferSize d n) | |
| def commands (n : Nat) (ports : Fin (n + 1) → Fin d) (direction : Bool) := | |
| (PoweringMachinePlan.boundedRowPlan n ports direction).reverse | |
| abbrev Label (n : Nat) (ports : Fin (n + 1) → Fin d) (direction : Bool) := | |
| PoweringMachinePlan.Label (commands n ports direction) ⊕ | |
| (Unit ⊕ PoweringMachineRowHeaders.Label n) | |
| def planMain {max : Nat} {E : Type} | |
| (ops : List (PoweringMachinePlan.Command d max)) (fallback : E) : | |
| PoweringMachinePlan.Label ops ⊕ E := | |
| match ops with | |
| | [] => .inr fallback | |
| | op :: _ => .inl (.inl (PoweringMachineField.entry op.val)) | |
| theorem plan_entry_eq {max : Nat} {E : Type} | |
| (ops : List (PoweringMachinePlan.Command d max)) (fallback : E) | |
| (labels : PoweringMachinePlan.Label ops ⊕ E → Λ) : | |
| PoweringMachinePlan.entry ops (fun l => labels (.inl l)) | |
| (some (labels (.inr fallback))) = some (labels (planMain ops fallback)) := by | |
| cases ops <;> rfl | |
| def entry (n : Nat) (ports : Fin (n + 1) → Fin d) (direction : Bool) : Label n ports direction := | |
| planMain (commands n ports direction) (.inl ()) | |
| def headerPlacement {max : Nat} (placement : PoweringMachineTapes.Tape max → K) | |
| (output : K) (i : PoweringMachineTapes.Tape max) : K := | |
| if i = .inl 10 then output else placement i | |
| omit [DecidableEq K] in | |
| @[simp] theorem headerPlacement_output {max : Nat} | |
| (placement : PoweringMachineTapes.Tape max → K) (output : K) : | |
| headerPlacement placement output (.inl 10) = output := by simp [headerPlacement] | |
| omit [DecidableEq K] in | |
| theorem headerPlacement_other {max : Nat} | |
| (placement : PoweringMachineTapes.Tape max → K) (output : K) | |
| (i : PoweringMachineTapes.Tape max) (hi : i ≠ .inl 10) : | |
| headerPlacement placement output i = placement i := by simp [headerPlacement, hi] | |
| omit [DecidableEq K] in | |
| theorem headerPlacement_injective {max : Nat} | |
| (placement : PoweringMachineTapes.Tape max → K) (distinct : Function.Injective placement) | |
| (output : K) (outside : ∀ i, output ≠ placement i) : | |
| Function.Injective (headerPlacement placement output) := by | |
| intro i j h | |
| by_cases hi : i = .inl 10 | |
| · subst i | |
| by_cases hj : j = .inl 10 | |
| · exact hj.symm | |
| · exact False.elim (outside j (by simpa [headerPlacement, hj] using h)) | |
| · by_cases hj : j = .inl 10 | |
| · subst j | |
| exact False.elim (outside i (by simpa [headerPlacement, hi] using h.symm)) | |
| · exact distinct (by simpa [headerPlacement, hi, hj] using h) | |
| omit [DecidableEq K] in | |
| theorem headerPlacement_excludes_data {max : Nat} | |
| (placement : PoweringMachineTapes.Tape max → K) (distinct : Function.Injective placement) | |
| (output : K) (outside : ∀ i, output ≠ placement i) : | |
| ∀ i, placement (.inl 10) ≠ headerPlacement placement output i := by | |
| intro i h | |
| by_cases hi : i = .inl 10 | |
| · subst i | |
| exact outside _ (by simpa only [headerPlacement_output] using h.symm) | |
| · have heq : (.inl 10 : PoweringMachineTapes.Tape max) = i := | |
| distinct (by simpa [headerPlacement, hi] using h) | |
| exact hi heq.symm | |
| def instruction (n : Nat) (placement : PoweringMachineTapes.Tape (capacity n) → K) | |
| (output : K) (ports : Fin (n + 1) → Fin d) (direction : Bool) | |
| (labels : Label n ports direction → Λ) (exit : Option Λ) : | |
| Label n ports direction → TM2.Stmt (fun _ : K => Bool) Λ (State d n) | |
| | .inl q => PoweringMachinePlan.instruction placement (commands n ports direction) | |
| (fun z => labels (.inl z)) (some (labels (.inr (.inl ())))) q | |
| | .inr (.inl _) => PoweringMasterState.rowAt (t := n + 1) (placement (.inl 10)) output | |
| (PoweringRowData.fixedLabelAt d n) (some (labels (.inr (.inr (PoweringMachineRowHeaders.entry n))))) | |
| | .inr (.inr q) => PoweringMachineRowHeaders.instruction n (by unfold capacity; omega) | |
| (headerPlacement placement output) ports direction (fun z => labels (.inr (.inr z))) exit q | |
| def afterPlan (graph : PortTables.Table vertices d) (n : Nat) | |
| (placement : PoweringMachineTapes.Tape (capacity n) → K) (vertex : Fin vertices) (ports : Fin (n + 1) → Fin d) (direction : Bool) (base : K → List Bool) : K → List Bool := | |
| PoweringMachinePlan.finalTapes graph placement vertex (commands n ports direction) base | |
| def rowRelation (graph : PortTables.Table vertices d) (n : Nat) (vertex : Fin vertices) | |
| (ports : Fin (n + 1) → Fin d) (direction : Bool) : List Bool := | |
| encodeWords (GenericGraphTables.relationWords (PoweringTables.table graph n).rows[ | |
| PoweringEnumeration.encodeDart vertices d n (direction, vertex, ports)].relation) | |
| def rowWords (graph : PortTables.Table vertices d) (n : Nat) (vertex : Fin vertices) | |
| (ports : Fin (n + 1) → Fin d) (direction : Bool) : List Nat := | |
| GenericGraphTables.rowWords (PoweringTables.table graph n).rows[ | |
| PoweringEnumeration.encodeDart vertices d n (direction, vertex, ports)] | |
| def afterEmit (graph : PortTables.Table vertices d) (n : Nat) | |
| (placement : PoweringMachineTapes.Tape (capacity n) → K) (output : K) (vertex : Fin vertices) | |
| (ports : Fin (n + 1) → Fin d) (direction : Bool) (base : K → List Bool) : K → List Bool := | |
| let mid := afterPlan graph n placement vertex ports direction base | |
| Function.update (Function.update mid (placement (.inl 10)) []) output | |
| (rowRelation graph n vertex ports direction ++ mid output) | |
| def finalTapes (graph : PortTables.Table vertices d) | |
| (n : Nat) (placement : PoweringMachineTapes.Tape (capacity n) → K) (output : K) | |
| (vertex : Fin vertices) (ports : Fin (n + 1) → Fin d) (direction : Bool) | |
| (base : K → List Bool) : K → List Bool := | |
| PoweringMachineRowHeaders.finalTapes graph n (by unfold capacity; omega) | |
| (headerPlacement placement output) vertex ports direction | |
| (afterEmit graph n placement output vertex ports direction base) | |
| def planSteps {max : Nat} (graph : PortTables.Table vertices d) (vertex : Fin vertices) : | |
| List (PoweringMachinePlan.Command d max) → Nat | |
| | [] => 0 | |
| | op :: ops => PoweringMachineField.steps graph vertex op.val + planSteps graph vertex ops | |
| theorem planSteps_eq {max : Nat} (graph : PortTables.Table vertices d) | |
| (placement : PoweringMachineTapes.Tape max → K) (vertex : Fin vertices) | |
| (ops : List (PoweringMachinePlan.Command d max)) (base : K → List Bool) : | |
| PoweringMachinePlan.steps graph placement vertex ops base = planSteps graph vertex ops := by | |
| induction ops generalizing base with | |
| | nil => rfl | |
| | cons op ops ih => | |
| change PoweringMachineField.steps graph vertex op.val + | |
| PoweringMachinePlan.steps graph placement vertex ops | |
| (PoweringMachinePlan.result graph placement vertex op base) = _ | |
| rw [ih] | |
| rfl | |
| def steps (graph : PortTables.Table vertices d) (vertex : Fin vertices) | |
| (n : Nat) (ports : Fin (n + 1) → Fin d) (direction : Bool) : Nat := | |
| planSteps graph vertex (commands n ports direction) + 1 + | |
| PoweringMachineRowHeaders.steps graph n vertex ports direction | |
| def Ready (graph : PortTables.Table vertices d) (n : Nat) | |
| (placement : PoweringMachineTapes.Tape (capacity n) → K) (vertex : Fin vertices) | |
| (suffix : List Bool) (base : K → List Bool) : Prop := | |
| PoweringMachineField.Ready graph placement vertex suffix base ∧ base (placement (.inl 10)) = [] | |
| private theorem plan_other {max : Nat} (graph : PortTables.Table vertices d) | |
| (placement : PoweringMachineTapes.Tape max → K) (vertex : Fin vertices) | |
| (ops : List (PoweringMachinePlan.Command d max)) (base : K → List Bool) | |
| (k : K) (outside : ∀ i, k ≠ placement i) : | |
| PoweringMachinePlan.finalTapes graph placement vertex ops base k = base k := by | |
| induction ops generalizing base with | |
| | nil => rfl | |
| | cons op ops ih => | |
| change PoweringMachinePlan.finalTapes graph placement vertex ops | |
| (PoweringMachinePlan.result graph placement vertex op base) k = _ | |
| rw [ih] | |
| exact PoweringMachineField.finalTapes_other graph placement vertex op.val op.property base k outside | |
| theorem afterEmit_data (graph : PortTables.Table vertices d) (n : Nat) | |
| (placement : PoweringMachineTapes.Tape (capacity n) → K) (output : K) | |
| (outside : ∀ i, output ≠ placement i) (vertex : Fin vertices) | |
| (ports : Fin (n + 1) → Fin d) (direction : Bool) (base : K → List Bool) : | |
| afterEmit graph n placement output vertex ports direction base (placement (.inl 10)) = [] := by | |
| simp only [afterEmit, Function.update_of_ne (Ne.symm (outside _)), Function.update_self] | |
| theorem afterEmit_role (graph : PortTables.Table vertices d) (n : Nat) | |
| (placement : PoweringMachineTapes.Tape (capacity n) → K) (distinct : Function.Injective placement) | |
| (output : K) (outside : ∀ i, output ≠ placement i) (vertex : Fin vertices) | |
| (ports : Fin (n + 1) → Fin d) (direction : Bool) (base : K → List Bool) | |
| (j : Fin 11) (hj : j ≠ 10) : | |
| afterEmit graph n placement output vertex ports direction base (placement (.inl j)) = | |
| afterPlan graph n placement vertex ports direction base (placement (.inl j)) := by | |
| have hdata : placement (.inl j) ≠ placement (.inl 10) := fun h => hj (Sum.inl.inj (distinct h)) | |
| simp only [afterEmit, Function.update_of_ne (Ne.symm (outside _)), Function.update_of_ne hdata] | |
| theorem afterEmit_ready (graph : PortTables.Table vertices d) (n : Nat) | |
| (placement : PoweringMachineTapes.Tape (capacity n) → K) (distinct : Function.Injective placement) | |
| (output : K) (outside : ∀ i, output ≠ placement i) (vertex : Fin vertices) | |
| (ports : Fin (n + 1) → Fin d) (direction : Bool) (base : K → List Bool) | |
| (suffix : List Bool) (ready : Ready graph n placement vertex suffix base) : | |
| Ready graph n placement vertex suffix (afterEmit graph n placement output vertex ports direction base) := by | |
| have hp := PoweringMachinePlan.ready_finalTapes graph placement distinct vertex | |
| (commands n ports direction) base suffix ready.1 | |
| constructor | |
| · constructor | |
| · rw [afterEmit_role graph n placement distinct output outside vertex ports direction base 0 (by decide)] | |
| exact hp.table | |
| · rw [afterEmit_role graph n placement distinct output outside vertex ports direction base 1 (by decide)] | |
| exact hp.source | |
| · rw [afterEmit_role graph n placement distinct output outside vertex ports direction base 5 (by decide)] | |
| exact hp.scratch | |
| · rw [afterEmit_role graph n placement distinct output outside vertex ports direction base 8 (by decide)] | |
| exact hp.leftCopy | |
| · rw [afterEmit_role graph n placement distinct output outside vertex ports direction base 9 (by decide)] | |
| exact hp.rightCopy | |
| · exact afterEmit_data graph n placement output outside vertex ports direction base | |
| theorem finalTapes_data (graph : PortTables.Table vertices d) (n : Nat) | |
| (placement : PoweringMachineTapes.Tape (capacity n) → K) (distinct : Function.Injective placement) | |
| (output : K) (outside : ∀ i, output ≠ placement i) (vertex : Fin vertices) | |
| (ports : Fin (n + 1) → Fin d) (direction : Bool) (base : K → List Bool) : | |
| finalTapes graph n placement output vertex ports direction base (placement (.inl 10)) = [] := by | |
| have hother := headerPlacement_excludes_data placement distinct output outside | |
| calc | |
| finalTapes graph n placement output vertex ports direction base (placement (.inl 10)) = | |
| afterEmit graph n placement output vertex ports direction base (placement (.inl 10)) := | |
| PoweringMachineRowHeaders.finalTapes_other _ _ _ _ _ _ _ _ _ | |
| (hother _) (hother _) (hother _) (hother _) (fun i => hother _) | |
| _ = [] := afterEmit_data graph n placement output outside vertex ports direction base | |
| theorem finalTapes_ready (graph : PortTables.Table vertices d) (n : Nat) | |
| (placement : PoweringMachineTapes.Tape (capacity n) → K) (distinct : Function.Injective placement) | |
| (output : K) (outside : ∀ i, output ≠ placement i) (vertex : Fin vertices) | |
| (ports : Fin (n + 1) → Fin d) (direction : Bool) (base : K → List Bool) | |
| (suffix : List Bool) (ready : Ready graph n placement vertex suffix base) : | |
| Ready graph n placement vertex suffix (finalTapes graph n placement output vertex ports direction base) := by | |
| have hm := afterEmit_ready graph n placement distinct output outside vertex ports direction base suffix ready | |
| have hrole (j : Fin 11) (h₂ : j ≠ 2) (h₃ : j ≠ 3) (h₄ : j ≠ 4) (h₁₀ : j ≠ 10) : | |
| finalTapes graph n placement output vertex ports direction base (placement (.inl j)) = | |
| afterEmit graph n placement output vertex ports direction base (placement (.inl j)) := by | |
| have h := PoweringMachineRowHeaders.finalTapes_shared graph n (by unfold capacity; omega) | |
| (headerPlacement placement output) (headerPlacement_injective placement distinct output outside) | |
| vertex ports direction (afterEmit graph n placement output vertex ports direction base) j h₂ h₃ h₄ h₁₀ | |
| dsimp only [finalTapes] | |
| simpa only [headerPlacement, ite_eq_right (show (Sum.inl j : PoweringMachineTapes.Tape (capacity n)) ≠ .inl 10 from | |
| fun heq => h₁₀ (Sum.inl.inj heq))] using h | |
| constructor | |
| · constructor | |
| · rw [hrole 0 (by decide) (by decide) (by decide) (by decide)]; exact hm.1.table | |
| · rw [hrole 1 (by decide) (by decide) (by decide) (by decide)]; exact hm.1.source | |
| · rw [hrole 5 (by decide) (by decide) (by decide) (by decide)]; exact hm.1.scratch | |
| · rw [hrole 8 (by decide) (by decide) (by decide) (by decide)]; exact hm.1.leftCopy | |
| · rw [hrole 9 (by decide) (by decide) (by decide) (by decide)]; exact hm.1.rightCopy | |
| · exact finalTapes_data graph n placement distinct output outside vertex ports direction base | |
| theorem finalTapes_other (graph : PortTables.Table vertices d) (n : Nat) | |
| (placement : PoweringMachineTapes.Tape (capacity n) → K) (output : K) | |
| (vertex : Fin vertices) (ports : Fin (n + 1) → Fin d) (direction : Bool) | |
| (base : K → List Bool) (k : K) (hout : k ≠ output) (outside : ∀ i, k ≠ placement i) : | |
| finalTapes graph n placement output vertex ports direction base k = base k := by | |
| have hh : ∀ i, k ≠ headerPlacement placement output i := by | |
| intro i | |
| by_cases hi : i = .inl 10 | |
| · simpa [headerPlacement, hi] using hout | |
| · simpa [headerPlacement, hi] using outside i | |
| calc | |
| finalTapes graph n placement output vertex ports direction base k = | |
| afterEmit graph n placement output vertex ports direction base k := | |
| PoweringMachineRowHeaders.finalTapes_other _ _ _ _ _ _ _ _ _ | |
| (hh _) (hh _) (hh _) (hh _) (fun i => hh _) | |
| _ = afterPlan graph n placement vertex ports direction base k := by | |
| simp only [afterEmit, Function.update_of_ne hout, Function.update_of_ne (outside _)] | |
| _ = base k := plan_other graph placement vertex _ base k outside | |
| theorem rowBlock_eq_rowRelation (graph : PortTables.Table vertices d) (n : Nat) | |
| (vertex : Fin vertices) (ports : Fin (n + 1) → Fin d) (direction : Bool) : | |
| PoweringMachineRow.encodeBits (List.ofFn (PoweringMachineRow.rowBlock | |
| (PoweringRowData.fixedLabelAt d n) (PoweringRowData.rowBits graph n (direction, vertex, ports)))) = | |
| rowRelation graph n vertex ports direction := by | |
| calc | |
| _ = encodeWords (GenericGraphTables.relationWords | |
| (PoweringRowData.emittedRelation graph n (direction, vertex, ports))) := | |
| PoweringRowData.rowBlock_unary graph n (direction, vertex, ports) | |
| _ = _ := by | |
| have h := PoweringRowData.emittedRelation_table graph n | |
| (PoweringEnumeration.encodeDart vertices d n (direction, vertex, ports)) | |
| rw [PoweringEnumeration.decodeDart_encodeDart] at h | |
| exact congrArg (fun relation : GenericGraphTables.RelationTable (PoweringTables.labelCount d n) => | |
| encodeWords (GenericGraphTables.relationWords relation)) h | |
| theorem finalTapes_output (graph : PortTables.Table vertices d) (n : Nat) | |
| (placement : PoweringMachineTapes.Tape (capacity n) → K) (distinct : Function.Injective placement) | |
| (output : K) (outside : ∀ i, output ≠ placement i) (vertex : Fin vertices) | |
| (ports : Fin (n + 1) → Fin d) (direction : Bool) (base : K → List Bool) | |
| (suffix : List Bool) (ready : Ready graph n placement vertex suffix base) : | |
| finalTapes graph n placement output vertex ports direction base output = | |
| encodeWords (rowWords graph n vertex ports direction) ++ base output := by | |
| have hm := afterEmit_ready graph n placement distinct output outside vertex ports direction base suffix ready | |
| have hh := (PoweringMachineRowHeaders.headerTrace graph n (by unfold capacity; omega) | |
| (headerPlacement placement output) (headerPlacement_injective placement distinct output outside) | |
| vertex ports direction id none | |
| (PoweringMachineRowHeaders.instruction n (by unfold capacity; omega) | |
| (headerPlacement placement output) ports direction id none) (fun _ => rfl) | |
| (afterEmit graph n placement output vertex ports direction base) | |
| (by simpa [headerPlacement, PoweringMachineTapes.table] using hm.1.table) | |
| (by simpa [headerPlacement, PoweringMachineTapes.scratch] using hm.1.scratch) suffix | |
| (by simpa [headerPlacement, PoweringMachineTapes.start] using hm.1.source) () none).2 | |
| simp only [PoweringMachineTapes.rowOutput, headerPlacement_output] at hh | |
| calc | |
| finalTapes graph n placement output vertex ports direction base output = | |
| encodeWords (PoweringRowHeaderSemantics.headerWords graph n vertex ports direction) ++ | |
| afterEmit graph n placement output vertex ports direction base output := hh | |
| _ = encodeWords (PoweringRowHeaderSemantics.headerWords graph n vertex ports direction) ++ | |
| (rowRelation graph n vertex ports direction ++ base output) := by | |
| simp only [afterEmit, Function.update_self] | |
| rw [show afterPlan graph n placement vertex ports direction base output = base output from | |
| plan_other graph placement vertex _ base output outside] | |
| _ = _ := PoweringRowHeaderSemantics.header_relation_bits graph n vertex ports direction (base output) | |
| theorem rowTrace (graph : PortTables.Table vertices d) (n : Nat) | |
| (placement : PoweringMachineTapes.Tape (capacity n) → K) (distinct : Function.Injective placement) | |
| (output : K) (outside : ∀ i, output ≠ placement i) (vertex : Fin vertices) | |
| (ports : Fin (n + 1) → Fin d) (direction : Bool) | |
| (labels : Label n ports direction → Λ) (exit : Option Λ) | |
| (program : Λ → TM2.Stmt (fun _ : K => Bool) Λ (State d n)) | |
| (atLabels : ∀ l, program (labels l) = instruction n placement output ports direction labels exit l) | |
| (base : K → List Bool) (suffix : List Bool) (ready : Ready graph n placement vertex suffix base) : | |
| (advance (TM2.step program))^[steps graph vertex n ports direction] | |
| (some ⟨some (labels (entry n ports direction)), PoweringMasterState.clean (bufferSize d n), base⟩) = | |
| some ⟨exit, PoweringMasterState.clean (bufferSize d n), | |
| finalTapes graph n placement output vertex ports direction base⟩ := by | |
| have hp := PoweringMachinePlan.planTrace graph placement distinct vertex (commands n ports direction) | |
| (fun q => labels (.inl q)) (some (labels (.inr (.inl ())))) program | |
| (fun q => atLabels (.inl q)) base suffix ready.1 (emptyBuffer (bufferSize d n)) | |
| rw [planSteps_eq, plan_entry_eq] at hp | |
| let mid := afterPlan graph n placement vertex ports direction base | |
| have hinput : mid (placement (.inl 10)) = PoweringMachineRow.encodeBits | |
| (List.ofFn (PoweringRowData.rowBits graph n (direction, vertex, ports))) ++ [] := by | |
| dsimp only [mid, afterPlan, commands] | |
| have h := PoweringMachinePlan.rowPlan_output graph n ports direction placement distinct vertex base suffix ready.1 | |
| simpa only [ready.2, List.append_nil, PoweringRowData.dataTape_eq] using h | |
| have hr := PoweringMasterState.step_rowAt_clean (t := n + 1) (placement (.inl 10)) output | |
| (PoweringRowData.fixedLabelAt d n) | |
| (some (labels (.inr (.inr (PoweringMachineRowHeaders.entry n))))) program (labels (.inr (.inl ()))) | |
| (atLabels (.inr (.inl ()))) (Ne.symm (outside _)) | |
| (PoweringRowData.rowBits graph n (direction, vertex, ports)) | |
| (emptyBuffer (bufferSize d n)) [] mid hinput | |
| rw [rowBlock_eq_rowRelation] at hr | |
| have hm := afterEmit_ready graph n placement distinct output outside vertex ports direction base suffix ready | |
| have hh := (PoweringMachineRowHeaders.headerTrace graph n (by unfold capacity; omega) | |
| (headerPlacement placement output) (headerPlacement_injective placement distinct output outside) | |
| vertex ports direction (fun q => labels (.inr (.inr q))) exit program | |
| (fun q => atLabels (.inr (.inr q))) | |
| (afterEmit graph n placement output vertex ports direction base) | |
| (by simpa [headerPlacement, PoweringMachineTapes.table] using hm.1.table) | |
| (by simpa [headerPlacement, PoweringMachineTapes.scratch] using hm.1.scratch) suffix | |
| (by simpa [headerPlacement, PoweringMachineTapes.start] using hm.1.source) | |
| (emptyBuffer (bufferSize d n), false, none) none).1 | |
| rw [steps, Nat.add_comm, Function.iterate_add_apply, Function.iterate_succ_apply'] | |
| change (advance (TM2.step program))^[PoweringMachineRowHeaders.steps graph n vertex ports direction] | |
| (advance (TM2.step program) ((advance (TM2.step program))^[planSteps graph vertex (commands n ports direction)] | |
| (some ⟨some (labels (planMain (commands n ports direction) (.inl ()))), | |
| MachineUnaryEqualityBit.clean (emptyBuffer (bufferSize d n)), base⟩))) = _ | |
| rw [hp] | |
| simp only [advance_some] | |
| change (advance (TM2.step program))^[PoweringMachineRowHeaders.steps graph n vertex ports direction] | |
| (TM2.step program ⟨some (labels (.inr (.inl ()))), | |
| PoweringMasterState.withBuffer (emptyBuffer (bufferSize d n)), mid⟩) = _ | |
| rw [hr] | |
| exact hh | |
| def budget (d n inputLength : Nat) : Nat := | |
| PoweringPlanBudget.rowBudget d n inputLength + 1 + | |
| ((14 * (n + 1) + 4) * inputLength + 12 * (n + 1) + 6) | |
| theorem steps_le (graph : PortTables.Table vertices d) (vertex : Fin vertices) | |
| (n : Nat) (ports : Fin (n + 1) → Fin d) (direction : Bool) : | |
| steps graph vertex n ports direction ≤ budget d n (PortTables.tableBits graph).length := by | |
| have hp := PoweringPlanBudget.rowPlan_steps_le graph n ports direction id vertex (fun _ => []) | |
| rw [planSteps_eq] at hp | |
| have hh := PoweringMachineRowHeaders.steps_le graph n vertex ports direction | |
| change planSteps graph vertex (commands n ports direction) ≤ | |
| PoweringPlanBudget.rowBudget d n (PortTables.tableBits graph).length at hp | |
| unfold steps budget | |
| omega | |
| def rowInTime (graph : PortTables.Table vertices d) (n : Nat) | |
| (placement : PoweringMachineTapes.Tape (capacity n) → K) (distinct : Function.Injective placement) | |
| (output : K) (outside : ∀ i, output ≠ placement i) (vertex : Fin vertices) | |
| (ports : Fin (n + 1) → Fin d) (direction : Bool) | |
| (labels : Label n ports direction → Λ) (exit : Option Λ) | |
| (program : Λ → TM2.Stmt (fun _ : K => Bool) Λ (State d n)) | |
| (atLabels : ∀ l, program (labels l) = instruction n placement output ports direction labels exit l) | |
| (base : K → List Bool) (suffix : List Bool) (ready : Ready graph n placement vertex suffix base) : | |
| StateTransition.EvalsToInTime (TM2.step program) | |
| ⟨some (labels (entry n ports direction)), PoweringMasterState.clean (bufferSize d n), base⟩ | |
| (some ⟨exit, PoweringMasterState.clean (bufferSize d n), | |
| finalTapes graph n placement output vertex ports direction base⟩) | |
| (budget d n (PortTables.tableBits graph).length) where | |
| steps := steps graph vertex n ports direction | |
| evals_in_steps := rowTrace graph n placement distinct output outside vertex ports direction | |
| labels exit program atLabels base suffix ready | |
| steps_le_m := steps_le graph vertex n ports direction | |
| end BinPackingGames.Foundations.Complexity.PoweringMachineRowBody | |
| end OAI | |