content stringlengths 1 1.04M ⌀ |
|---|
-- $Id: sys_conf.vhd 351 2010-12-30 21:50:54Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, o... |
-- $Id: sys_conf.vhd 351 2010-12-30 21:50:54Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, o... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
package DW_Foundation_comp is
component DW_mult_pipe
generic (
a_width : positive; -- multiplier word width
b_width : positive; -- multiplicand word width
num_stages : posit... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
package DW_Foundation_comp is
component DW_mult_pipe
generic (
a_width : positive; -- multiplier word width
b_width : positive; -- multiplicand word width
num_stages : posit... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
package DW_Foundation_comp is
component DW_mult_pipe
generic (
a_width : positive; -- multiplier word width
b_width : positive; -- multiplicand word width
num_stages : posit... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
package DW_Foundation_comp is
component DW_mult_pipe
generic (
a_width : positive; -- multiplier word width
b_width : positive; -- multiplicand word width
num_stages : posit... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file co... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Entity Sync is
Port(
clk: in std_logic;
R_in, G_in, B_in : in std_logic_vector(3 downto 0);
x, y : out std_logic_vector(11 downto 0);
HSync, VSync: out std_logic;
R, G, B : out std_logic_vector(3 downto 0)
);
end Sync;
Architecture behavioral of Sy... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.mpu_pkg.all;
entity offset_correction is
port (
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
rd_fifo_count : in std_logic;
parameters : in param;
wr_en_flag : in std... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity I2C_TB is
end entity I2C_TB;
architecture RTL of I2C_TB is
component I2C is
generic(
CLOCKS_PER_SECOND : integer := 50000000;
SPEED : integer := 100000
);
port(
CLK : in std_logic;
RST : in std_logic;
SDA : inout... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Jun 05 10:58:36 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-------------------------------------------------------------------------------
--! @file lutFileRtl.vhd
--
--! @brief Look-up table file implementation
--
--! @details This look-up table file stores initialization values (generics)
--! in LUT resources.
-----------------------------------------------------------------... |
--
-----cell dp8ka----
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.all;
use ieee.vital_primitives.all;
--use ieee.std_logic_unsigned.all;
library ec;
use ec.global.gsrnet;
use ec.global.purnet;
use ec.mem3.all;
library grlib;
use grlib.stdlib.all;
-- entity declaration --
ENTITY dp8ka IS
... |
--
-----cell dp8ka----
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.all;
use ieee.vital_primitives.all;
--use ieee.std_logic_unsigned.all;
library ec;
use ec.global.gsrnet;
use ec.global.purnet;
use ec.mem3.all;
library grlib;
use grlib.stdlib.all;
-- entity declaration --
ENTITY dp8ka IS
... |
--
-----cell dp8ka----
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.all;
use ieee.vital_primitives.all;
--use ieee.std_logic_unsigned.all;
library ec;
use ec.global.gsrnet;
use ec.global.purnet;
use ec.mem3.all;
library grlib;
use grlib.stdlib.all;
-- entity declaration --
ENTITY dp8ka IS
... |
--
-----cell dp8ka----
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.all;
use ieee.vital_primitives.all;
--use ieee.std_logic_unsigned.all;
library ec;
use ec.global.gsrnet;
use ec.global.purnet;
use ec.mem3.all;
library grlib;
use grlib.stdlib.all;
-- entity declaration --
ENTITY dp8ka IS
... |
architecture RTL of FIFO is
type state_machine is (IDLE, WRITE, READ, DONE);
-- Violations below
type state_machine is (IDLE, WRITE, READ, DONE);
begin
end architecture RTL;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_misc.all;
-- ******************************************************************************
-- * License Agreement *
-- * ... |
-- This file is part of the Omega CPU Core
-- Copyright 2015 - 2016 Joseph Shetaye
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as
-- published by the Free Software Foundation, either version 3 of the
-- License, or (at your opti... |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.2 (lin64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
-- Date : Sun Oct 4 22:06:59 2015
-- Host : cascade.andrew.cmu.edu running 64-bi... |
-- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of ... |
architecture RTL of FIFO is
begin
FOR_LABEL : for i in 0 to 7 generate
end generate;
IF_LABEL : if a = '1' generate
end generate;
CASE_LABEL : case data generate
end generate;
-- Violations below
for_label : for i in 0 to 7 generate
end generate;
if_label : if a = '1' generate
end gen... |
entity repro is
end;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of repro is
-- AXI-Lite Interface signals
type t_axilite_write_address_channel is record
--DUT inputs
awaddr : std_logic_vector;
awvalid : std_logic;
awprot : std_logic_vector(2 downto 0); -- [0: '0' - unpriv... |
--
-- Taken from rtl/riverlib/core/stacktrbuf.vhd of https://github.com/sergeykhbr/riscv_vhdl
-- with modifications.
--
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2017 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@g... |
--
-- Taken from rtl/riverlib/core/stacktrbuf.vhd of https://github.com/sergeykhbr/riscv_vhdl
-- with modifications.
--
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2017 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@g... |
entity repro1 is
end entity;
architecture A of repro1 is
-- array with unconstrained array element type
type A is array(natural range <>) of bit_vector;
-- partially constrained array -> constrained outer array (vector)
subtype P2 is A(15 downto 0)(open);
signal S2 : P2(open)(7 downto 0); -- fully constrai... |
-------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
-- Testbench
--
-- $Id: tb.vhd,v 1.1 2005-02-08 21:09:20 arniml Exp $
--
-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved, see COPYING.
--
-- Redistribution and use in source and ... |
library verilog;
use verilog.vl_types.all;
entity ex_reg is
port(
clk : in vl_logic;
reset : in vl_logic;
alu_out : in vl_logic_vector(31 downto 0);
alu_of : in vl_logic;
stall : in vl_logic;
flush ... |
architecture RTL of FIFO is
begin
process
begin
a <= b;
end process;
-- Violations below
process
begin
a <= b;
end process;
end architecture RTL;
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.2 (win64) Build 932637 Wed Jun 11 13:33:10 MDT 2014
-- Date : Fri Sep 26 21:45:04 2014
-- Host : ECE-411-6 running 64-bit Service Pack... |
library verilog;
use verilog.vl_types.all;
entity usb_system_mm_interconnect_0_router is
port(
clk : in vl_logic;
reset : in vl_logic;
sink_valid : in vl_logic;
sink_data : in vl_logic_vector(104 downto 0);
sink_startofpacket: ... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue Jun 06 02:48:32 2017
-- Host : GILAMONSTER running 64-bit major rel... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity opcode... |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: clk_40.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
--... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MUX_wm is
Port ( RDin : in STD_LOGIC_VECTOR (5 downto 0);
o15 : in STD_LOGIC_VECTOR (5 downto 0);
RFDest : in STD_LOGIC;
nRD : out STD_LOGIC_VECTOR (5 downto 0)
);
end MUX_wm;
architecture Behavioral of MUX_wm is
be... |
architecture arch of entity1 is
begin
block_label : block is
type type1;
begin
end block block_label;
end architecture arch;
|
--------------------------------------------------------------------------------
-- Company: <Name>
--
-- File: testb_20_01.vhd
-- File history:
-- <Revision number>: <Date>: <Comments>
-- <Revision number>: <Date>: <Comments>
-- <Revision number>: <Date>: <Comments>
--
-- Description:
--
-- <Descriptio... |
-- megafunction wizard: %LPDDR2 SDRAM Controller with UniPHY v13.0%
-- GENERATION: XML
-- lpddr2ctrl1.vhd
-- Generated using ACDS version 13.0sp1 232 at 2013.09.05.17:05:47
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity lpddr2ctrl1 is
port (
pll_ref_clk : in std_logic... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity seatbelt is
port (k, p, s, t: in BIT; w: out BIT);
end entity seatbelt;
architecture arch1 of seatbelt is
begin
w <= k and p and not s or t;
end architecture arch1
|
-------------------------------------------------------------------------------
-- axi_sg_ftchq_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserv... |
-------------------------------------------------------------------------------
-- axi_sg_ftchq_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserv... |
-------------------------------------------------------------------------------
-- axi_sg_ftchq_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserv... |
-------------------------------------------------------------------------------
-- axi_sg_ftchq_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserv... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_t_e
--
-- Generated
-- by: wig
-- on: Mon Mar 5 07:51:26 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../../case.xls
--
-- !!! Do not edit this file! Autogenerated by ... |
--
-- A simulation model of VIC20 hardware - VIA implementation
-- Copyright (c) MikeJ - March 2003
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of sou... |
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Gener... |
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Gener... |
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core, asynchronous top level
--
-- Version : 0247
--
-- Copyri... |
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core, asynchronous top level
--
-- Version : 0247
--
-- Copyri... |
-- File: gray_counter_20.vhd
-- Generated by MyHDL 0.8dev
-- Date: Sun Feb 3 17:16:41 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity gray_counter_20 is
port (
gray_count: out unsigned(19 downto 0);
enable: in std_l... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IE... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IE... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IE... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SRAM_Controller IS
PORT
(
clk, reset : IN STD_LOGIC;
-- to/from main system
mem : IN STD_LOGIC;
rw : IN STD_LOGIC;
addr : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
data_f2s : IN STD_LOGIC_VECTOR(15 D... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library IEEE;
use IEEE.std_logic_1164.all;
use std.textio.all;
use IEEE.std_logic_textio.all;
use IEEE.numeric_std.all;
use ieee.math_real.all;
use work.sampling.all;
entity test_activation is
end test_activation;
architecture behave of test_activation is
constant clk_period : time := 10 ns;
constant num_sampl... |
-- -------------------------------------------------------------
--
-- Generated Configuration for ent_t
--
-- Generated
-- by: wig
-- on: Thu Mar 16 07:48:49 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -conf macro._MP_VHDL_USE_ENTY_MP_=Overwritten vhdl_enty from cmdline -conf macro._MP_VHDL_HOOK_ARCH_BODY_... |
--!
--! Copyright 2018 Sergey Khabarov, sergeykhbr@gmail.com
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless requ... |
entity test_ent is
port (
input: integer
);
end entity;
architecture test of test_ent is
begin
end architecture;
entity associate is
end entity;
architecture test of associate is
component test_ent is
port (
input: integer
);
end component;
begin
gen_labe... |
entity test_ent is
port (
input: integer
);
end entity;
architecture test of test_ent is
begin
end architecture;
entity associate is
end entity;
architecture test of associate is
component test_ent is
port (
input: integer
);
end component;
begin
gen_labe... |
entity test_ent is
port (
input: integer
);
end entity;
architecture test of test_ent is
begin
end architecture;
entity associate is
end entity;
architecture test of associate is
component test_ent is
port (
input: integer
);
end component;
begin
gen_labe... |
-- #####################################################################################
--
-- #### #### #####
-- ## ## ##
-- ## ## ##### ## ## ##### ## ###### ##### ##### ##### ## ##
-- ## ## ## ## ## ## ## ## #... |
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the ... |
architecture RTL of FIFO is
procedure proc1 is
constant c : integer;
variable v : integer;
file f : something;
alias a is name;
alias a : subtype_indicator is name;
begin
end procedure proc1;
procedure proc1 is
constant c : integer;
variable v : int... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- -------------------------------------------------------------
--
-- Generated Configuration for PORTLIST_i_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 18:36:52 2007
-- cmd: /home/wig/work/MIX/mix_0.pl -report portlist ../portlist.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $... |
entity tb_dff04 is
end tb_dff04;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff04 is
signal clk : std_logic;
signal din : std_logic_vector (7 downto 0);
signal dout : std_logic_vector (7 downto 0);
begin
dut: entity work.dff04
port map (
r => dout,
d => din,
clk ... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 27 15:47:02 2017
-- Host : GILAMONSTER running 64-bit major rel... |
library ieee;
use ieee.std_logic_1164.all;
entity Clk_div_2 is
port
(
clk_in,rst : in std_logic;
clk_out : out std_logic
);
end Clk_div_2;
architecture bhv of clk_div_2 is
signal clk : std_logic;
begin
process(clk_in,rst)
begin
if(rst = '1') then
clk <= '0';
elsif(rising_edge(clk_in)) then
clk <= not ... |
entity FIFO is
generic (
g_width : integer := 256;
g_depth : integer := 32;
PREFIX_generic_suffix : integer := 20
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
entity FIFO is
generic (
g_width : integer := 256;
g_depth : integer := 32;
PREFIX_g... |
architecture ARCH of ENTITY is
begin
CLK_PROC : process (reset, clk) is
begin
if (reset = '1') then
a <= '0';
b <= '1';
c <= '0';
d <= '1';
elsif (clk'event and clk = '1') then
a <= b after 1 ns;
b <= c after 1 ns;
c <= d after 1 ns;
d <= e after 1... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected unde... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Apr 18 23:15:16 2017
-- Host : DESKTOP-I9J3TQJ running 64-bit m... |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and ... |
constant TRFSM2Length : integer := 1020;
constant TRFSM2Cfg : std_logic_vector(TRFSM2Length-1 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000... |
constant TRFSM2Length : integer := 1020;
constant TRFSM2Cfg : std_logic_vector(TRFSM2Length-1 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000... |
constant TRFSM2Length : integer := 1020;
constant TRFSM2Cfg : std_logic_vector(TRFSM2Length-1 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 08:26:59 2017
-- Host : GILAMONSTER running 64-bit major rel... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:52:59 03/25/2016
-- Design Name:
-- Module Name: DC_CTL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
-... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.seven_seg_pkg.all;
entity seven_seg_controller is
generic (
-- The controller cycles through the seven segment displays
-- This variable controls how long (in clk cycles) every digit i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
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