content stringlengths 1 1.04M ⌀ |
|---|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
--
-- T420/421 ROM.
--
-- $Id: t420_rom-e.vhd,v 1.1 2006-05-14 22:29:01 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with ... |
--*****************************************************************************
-- @Copyright 2013 by SIAT_HFUS_TEAM, All rights reserved.
-- Module name : HUCB2P0_TOP
-- Call by :
-- Description : this module is the top module of HUCB2P0.
-- IC : 5CGXFC7D7F31C8N
-- Version... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc\hdlcodercpu_eml\Program_Counter.vhd
-- Created: 2014-08-26 11:41:14
--
-- Generated by MATLAB 8.3 and HDL Coder 3.4
--
-- -------------------------------------------------------------
-- ---------------------------------------... |
-- #################################################################################################
-- # << NEO430 - Watchdog Timer >> #
-- # ********************************************************************************************* #
-- # The internal... |
------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- for arch1
-- use ieee.std_logic_arith.all; -- for arch2, arch3
-- best to use arch2 using numeric_std
------------------------------
entity signed_multiplier is
--generic declarations
port (
a: i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 21:06:44 2017
-- Host : GILAMONSTER running 64-bit major rel... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
entity implicit is
end entity;
architecture test of implicit is
signal x : integer;
begin
process is
begin
assert x'delayed = 4; -- OK
assert x'delayed(1 ns) = 5; -- OK
assert x'delayed(5) = 1; -- Error
assert x'stable; -- OK
asse... |
----------------------------------------
-- Main Processor : IITB-RISC
-- Author : Titto Thomas, Sainath, Anakha
-- Date : 9/3/2014
----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pipeline_RISC is
port (
clock, reset : in std_logic; -- c... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity divider is
GENERIC (
N: positive := 60
);
Port ( clk : in STD_LOGIC;
tc : out STD_LOGIC);
end divider;
architecture divider_architecture of divider is
signal cpt : STD_LOGIC... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: GPU.vhd
-- // Date: 12/9/2004
-- // Description: Main GPU Module
-- // Class: CSE 378
-- ==================================================... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Martin Strasser, Ning Chen
--
-- Create Date: 20:59:47 06/19/2008
-- Design Name:
-- Module Name: idea_com_inner - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-... |
----- Libraries -----
library ieee;
use ieee.std_logic_1164.all;
entity Tester is
port( LEDR : out std_logic_vector(1 downto 0);
KEY : in std_logic_vector(1 downto 0);
SW : in std_logic_vector(1 downto 0)
);
end Tester;
architecture State of Tester is
begin
sm1 : entity work.Mee_Moo port map(moo_out => LE... |
library verilog;
use verilog.vl_types.all;
entity four_bit_adder_vlg_sample_tst is
port(
A : in vl_logic_vector(3 downto 0);
B : in vl_logic_vector(3 downto 0);
cin : in vl_logic;
sampler_tx : out vl_logic
);
end four_bi... |
----------------------------------------------------------------------------
----------------------------------------------------------------------------
--
-- Copyright 2017 International Business Machines
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in comp... |
-------------------------------------------------------------------------------
-- Title : ALU log_or
-- Project : Source files in two directories, custom library name, VHDL'87
-------------------------------------------------------------------------------
-- File : ALU_Log_Or.vhd
-- Author : Robert J... |
-- Testebench gerado via script.
-- Data: Sáb,31/12/2011-01:39:29
-- Autor: rogerio
-- Comentario: Teste da entidade unidadeLogica.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity unidadeLogica_tb is
end unidadeLogica_tb;
architecture estrutural of unidadeLogica_tb is
-- Declar... |
--------------------------------------------------------------------------------
-- Copyright (c) 2015, Przemyslaw Wegrzyn <pwegrzyn@codepainters.com>
-- This file is distributed under the Modified BSD License.
--
-- Testbench for teh HD44780 LCD interface.
--------------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:23:47 10/31/2013
-- Design Name:
-- Module Name: if_id_reg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revis... |
architecture RTL of FIFO is
begin
-- These are passing
a <= '0' when c = '0' else
'1';
a <= '0' when c = '0' else-- Comment
'1' when c = '1' else -- comment
'0' when d = '1' else
'1';
-- Violations below
a <= '0' when c = '0' else
'1' when c = '1' else
'0' when d = '1' else
'1... |
---------------------------------------------------------------------------
-- Copyright 2010 Lawrence Wilkinson lawrence@ljw.me.uk
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
entity repro is
end repro;
architecture behav of repro is
signal clk : bit;
signal cyc: bit;
signal wen : bit;
signal lw : bit;
begin
-- psl default clock is clk;
-- psl c1: assert always lw -> cyc and (next not(wen))
-- report "error";
end;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/TWDLROM_3_14.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------... |
--
-- \file conv_filter3x3.vhd
--
-- Implements a configurable 3x3 convolution kernel
--
-- \author Andreas Agne <agne@upb.de>
-- \date 21.11.2007
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.r... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY TB_RS232 IS
END TB_RS232;
ARCHITECTURE behavior OF TB_RS232 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT RS232
PORT(
clk : IN std_logic;
Entrada_8bits : IN std_logic_vector(7 downto 0);
... |
architecture RTL of FIFO is
begin
-- Test generate_statement_body
LABEL_1 : for i in 0 to 7 generate
signal blah : std_logic;
begin
a <= blah;
end;
end generate LABEL3;
-- Test generate_statement_body
LABEL_2 : for i in 0 to 7 generate
begin
a <= blah;
end;
end... |
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the ... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
entity TESTCASE is
end entity TESTCASE;
architecture PROBLEM of TESTCASE is
type ENUMERATION_TYPE is (VALUE1, VALUE2);
constant SOME_VAR : integer := ENUMERATION_TYPE'length;
begin
end architecture PROBLEM;
|
entity TESTCASE is
end entity TESTCASE;
architecture PROBLEM of TESTCASE is
type ENUMERATION_TYPE is (VALUE1, VALUE2);
constant SOME_VAR : integer := ENUMERATION_TYPE'length;
begin
end architecture PROBLEM;
|
entity TESTCASE is
end entity TESTCASE;
architecture PROBLEM of TESTCASE is
type ENUMERATION_TYPE is (VALUE1, VALUE2);
constant SOME_VAR : integer := ENUMERATION_TYPE'length;
begin
end architecture PROBLEM;
|
library ieee;
use ieee.std_logic_1164.all;
entity and6 is
port (i0, i1, i2, i3, i4, i5 : std_logic;
o : out std_logic);
end and6;
architecture behav of and6 is
signal t1, t2 : std_logic;
begin
a1: entity work.and3
port map (i0, i1, i2, t1);
a2: entity work.and3
port map (i3, i4, i5, t2);
o <... |
------------------------------------------------------------------------------
-- Copyright (C) 2007 Jonathon W. Donaldson
-- jwdonal a t opencores DOT org
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published... |
-------------------------------------------------------------------------------
-- Title : Input Conditioner
-- Project :
-------------------------------------------------------------------------------
-- File : input_conditioner.vhd
-- Author : Gustavo BM Bruno
-- Company :
-- Created : 2014-... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/TWDLROM_3_3.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- ------------------------------------------------... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Projeto MasterMind
-- Diogo Daniel Soares Ferreira e Eduardo Reis Silva
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Blink is
port( enable : in std_logic;
numberIn : in std_logic_vector(3 downto 0);
numberOut: out std_logic_vector(3 downto 0);
clock : in std_logic;
lo... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/IFFT_HDL_Optimized.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- ---------------------------... |
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.depp_pkg.all;
entity depp_slave_controller is
port (
clk : in std_logic;
rst : in std_logic;
-- Bus connection
slv2mst : in bus_slv2mst_type;
mst2slv : out bus... |
architecture RTL of ENTITY_NAME is
begin
process
begin
LABEL : assert TRUE
report "This is a string"
severity WARNING;
assert TRUE
report "This is a string"
severity WARNING;
LABEL : assert TRUE
report "This is a string";
LABEL : assert TRUE
severity WARNIN... |
library verilog;
use verilog.vl_types.all;
entity cpu is
port(
clk : in vl_logic;
reset : in vl_logic;
e1 : in vl_logic_vector(7 downto 0);
e2 : in vl_logic_vector(7 downto 0);
e3 : in vl_logic_v... |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: altpll0.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ===========================================... |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: altpll0.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ===========================================... |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: altpll0.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ===========================================... |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: altpll0.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ===========================================... |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: altpll0.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ===========================================... |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: altpll0.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ===========================================... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Mar 31 18:24:55 2017
-- Host : LAPTOP-IQ9G3D1I running 64-bit major... |
-------------------------------------------------------------------------------
--
-- File: ResetBridge.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 20 October 2014
-- Last modification date: 05 October 2022
--
--------------------------------------------------------------... |
-------------------------------------------------------------------------------
--
-- File: ResetBridge.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 20 October 2014
-- Last modification date: 05 October 2022
--
--------------------------------------------------------------... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
context c1;
context c2;
context my_lib.c1;
context my_lib.c2;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-... |
entity FIFO is
end entity fifo;
entity FIFO is
end entity fifo;
entity FIFO is
end entity fifo;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(A : in std_logic;
B : in std_logic;
carryIn : in std_logic;
carryOut : out std_logic;
fnord : out std_logic;
baz : out std_... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- highpass_filter_tb.vhd
-- Jan Viktorin <xvikto03@stud.fit.vutbr.cz>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity highpass_filter_tb is
end entity;
architecture testbench of highpass_filter_tb is
signal c... |
component Avalon_Test_Streaming is
end component Avalon_Test_Streaming;
u0 : component Avalon_Test_Streaming
port map (
);
|
entity test2 is
begin
end entity;
architecture arch of test2 is
begin
process(all)
begin
loop
exit;
end loop;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_562 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_562;
architecture augh of sub_562 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_562 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_562;
architecture augh of sub_562 is
signal carry_inA : std_l... |
--========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation fi... |
--========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation fi... |
--========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation fi... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This fil... |
-- SIMON 64/128
-- feistel round function operation gamma
-- gamma(x,y) = (x xor y)
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- x_in: half block 1
-- y_in: half block 2
-- x_out: xor of both inputs
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
... |
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