content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2017 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com
--
-- This source file is free software: you ... |
entity record10 is
end entity;
architecture test of record10 is
type rec1 is record
x, y : integer;
end record;
type rec2 is record
x : integer;
y : bit_vector(1 to 3);
end record;
begin
process is
variable r1 : rec1;
variable r2 : rec2;
varia... |
entity record10 is
end entity;
architecture test of record10 is
type rec1 is record
x, y : integer;
end record;
type rec2 is record
x : integer;
y : bit_vector(1 to 3);
end record;
begin
process is
variable r1 : rec1;
variable r2 : rec2;
varia... |
entity record10 is
end entity;
architecture test of record10 is
type rec1 is record
x, y : integer;
end record;
type rec2 is record
x : integer;
y : bit_vector(1 to 3);
end record;
begin
process is
variable r1 : rec1;
variable r2 : rec2;
varia... |
entity record10 is
end entity;
architecture test of record10 is
type rec1 is record
x, y : integer;
end record;
type rec2 is record
x : integer;
y : bit_vector(1 to 3);
end record;
begin
process is
variable r1 : rec1;
variable r2 : rec2;
varia... |
entity record10 is
end entity;
architecture test of record10 is
type rec1 is record
x, y : integer;
end record;
type rec2 is record
x : integer;
y : bit_vector(1 to 3);
end record;
begin
process is
variable r1 : rec1;
variable r2 : rec2;
varia... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue May 30 22:27:54 2017
-- Host : GILAMONSTER running 64-bit major rel... |
------------------------------------------------------------------------------
-- Testbench for reg_en.vhd
--
-- Project :
-- File : tb_reg_en.vhd
-- Author : Rolf Enzler <enzler@ife.ee.ethz.ch>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2002/06/26
-- Last changed:... |
-- describe what this circuit does
--
-- entity name: g23_Seconds_to_Days
--
-- Copyright (C) 2014 cadesalaberry, grahamludwinski
--
-- Version 1.0
--
-- Author:
-- Charles-Antoine de Salaberry; ca.desalaberry@mail.mcgill.ca,
-- Graham Ludwinski; graham.ludwinski@mail.mcgill.ca
--
-- Date: 21/01/2014
library ieee; -... |
-- describe what this circuit does
--
-- entity name: g23_Seconds_to_Days
--
-- Copyright (C) 2014 cadesalaberry, grahamludwinski
--
-- Version 1.0
--
-- Author:
-- Charles-Antoine de Salaberry; ca.desalaberry@mail.mcgill.ca,
-- Graham Ludwinski; graham.ludwinski@mail.mcgill.ca
--
-- Date: 21/01/2014
library ieee; -... |
-- describe what this circuit does
--
-- entity name: g23_Seconds_to_Days
--
-- Copyright (C) 2014 cadesalaberry, grahamludwinski
--
-- Version 1.0
--
-- Author:
-- Charles-Antoine de Salaberry; ca.desalaberry@mail.mcgill.ca,
-- Graham Ludwinski; graham.ludwinski@mail.mcgill.ca
--
-- Date: 21/01/2014
library ieee; -... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity font_generator is
port(
clock: in std_logic;
vramaddr : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
vramdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
video_on: in std_logic;
pixel_x, pixel_y: in std_logic_vector(9 downto 0);
rgb_text: out st... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
entity inverse_transform is
generic(
in_sample_width : integer := 16;
out_sample_width : integer := 8
);
port(
transform_block : in std_logic_vector((16*in_sample_width)-1 downto ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
entity inverse_transform is
generic(
in_sample_width : integer := 16;
out_sample_width : integer := 8
);
port(
transform_block : in std_logic_vector((16*in_sample_width)-1 downto ... |
library IEEE;
use IEEE.std_logic_1164.all;
entity unidade_controle is
port(
clock : in std_logic;
reset : in std_logic;
e_s_amostrada : in std_logic;
finaliza_recepcao : in std_logic;
finaliza_paridade : in std_logic;
recebendo ... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or ag... |
architecture RTL of FIFO is
begin
PROC_LABEL : process is
begin
end process;
-- Violations below
PROC_LABEL : process is
begin
end process;
end architecture RTL;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--This component normalizes the vector components according to the steps used in cordic algorithm
entity normalizer is
generic(TOTAL_BITS: integer := 32; FRACTIONAL_BITS: integer := 16);
port(
x_in: in std_logic_vector(TOTAL_BITS - 1 d... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confide... |
-- Author: Varun Nagpal
-- Net Id: vxn180010
-- Microprocessor Systems Project
-- December, 6th 2018
--
-- Design: Testbench for the Generic Nth order (L = N+1 taps) Transposed Direct-form FIR-filter
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use ieee.std_lo... |
-- NEED RESULT: ARCH00449 Assert allowed in a FOR generate statement Passed
-- NEED RESULT: ARCH00449: Block statement allowed in a FOR generate statement passed
-- NEED RESULT: ARCH00449: Generate statement allowed in a FOR generate statement passed
-- NEED RESULT: ARCH00449 Assert allowed in a IF generate statemen... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains co... |
-------------------------------------------------------------------------------
-- system_stub.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_stub is
port (
SWs_8Bits_TRI_IO ... |
--
-- Dual port RAM. Part of libstorage
--
-- Copyright (C) 2015 Olof Kindgren <olof.kindgren@gmail.com>
--
-- Permission to use, copy, modify, and/or distribute this software for any
-- purpose with or without fee is hereby granted, provided that the above
-- copyright notice and this permission notice appear in all ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
----------------------------------------------------------------------------------
-- Company: NTU ATHENS - BNL
-- Engineer: Christos Bakalis (christos.bakalis@cern.ch)
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Christos Bakalis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BN... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Package: Common functions and types
--
-- Authors: Thomas B. Pre... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Package: Common functions and types
--
-- Authors: Thomas B. Pre... |
--------------------------------------------------------------------------------
--
-- LAB #5 - Processor Elements
--
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SmallB... |
component soc_design is
port (
dram_addr : out std_logic_vector(12 downto 0); -- addr
dram_ba : out std_logic_vector(1 downto 0); -- ba
dram_cas_n : out std_logic; -- cas_n
dram_cke : out std_logic; ... |
component soc_design is
port (
dram_addr : out std_logic_vector(12 downto 0); -- addr
dram_ba : out std_logic_vector(1 downto 0); -- ba
dram_cas_n : out std_logic; -- cas_n
dram_cke : out std_logic; ... |
component soc_design is
port (
dram_addr : out std_logic_vector(12 downto 0); -- addr
dram_ba : out std_logic_vector(1 downto 0); -- ba
dram_cas_n : out std_logic; -- cas_n
dram_cke : out std_logic; ... |
-------------------------------------------------------------------------------
-- Clock domain crossing circuit for slowly changing signals
--
-- Author: Peter Würtz, TU Kaiserslautern (2016)
-- Distributed under the terms of the GNU General Public License Version 3.
-- The full license is in the file COPYING.txt, dis... |
-------------------------------------------------------------------------------
-- axi_interface.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprie... |
-------------------------------------------------------------------------------
-- axi_interface.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprie... |
-------------------------------------------------------------------------------
-- axi_interface.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprie... |
-------------------------------------------------------------------------------
-- axi_interface.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprie... |
library ieee;
use ieee.std_logic_1164.all;
entity fadd is
port ( a : in std_logic;
b : in std_logic;
cin : in std_logic;
s : out std_logic;
cout: out std_logic);
end entity fadd;
architecture Behavioral of fadd is
begin
s <= a xor b xor cin;
cout <= (a and b) or (a... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:42:09 02/09/2013
-- Design Name:
-- Module Name: Top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
... |
-------------------------------------------------------------------------------
-- $Id: mux_onehot_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot_f - arch and entity
-----------------------------------------------------------... |
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- ... |
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- ... |
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- video_system_onchip_memory_s1_translator.vhd
-- Generated using ACDS version 12.1sp1 243 at 2015.02.09.14:34:21
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity video_system_onchip_memory_s1_translator is
generic (
AV_ADDRESS_W : integer := 12;
AV_DATA_W ... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: ... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: ... |
----------------------------------------------------------------------------------
-- Company: Team 5
-- Engineer:
--
-- Create Date: 15:15:57 03/11/2016
-- Design Name:
-- Module Name: programCounter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_788 is
port (
eq : out std_logic;
in1 : in std_logic_vector(2 downto 0);
in0 : in std_logic_vector(2 downto 0)
);
end cmp_788;
architecture augh of cmp_788 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_788 is
port (
eq : out std_logic;
in1 : in std_logic_vector(2 downto 0);
in0 : in std_logic_vector(2 downto 0)
);
end cmp_788;
architecture augh of cmp_788 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'... |
library verilog;
use verilog.vl_types.all;
entity id_reg is
port(
clk : in vl_logic;
reset : in vl_logic;
alu_op : in vl_logic_vector(3 downto 0);
alu_in_0 : in vl_logic_vector(31 downto 0);
alu_in_1 : in vl_log... |
--
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This ... |
-- control signals for HF-RISCV
--
-- alu_op: alu_src1: mem_write: jump:
-- 0000 -> and 0 -> r[rs1] 00 -> no mem write 00 -> no jump
-- 0001 -> or 1 -> pc_last2 01 -> sb 01 -> don't care
-- 0010 -> xor 10 -> sh 10 -> jal
-- 0011 -> don't care alu_src2: 11 -> sw 11 -> jalr
-- 0100 -> add 000... |
-- control signals for HF-RISCV
--
-- alu_op: alu_src1: mem_write: jump:
-- 0000 -> and 0 -> r[rs1] 00 -> no mem write 00 -> no jump
-- 0001 -> or 1 -> pc_last2 01 -> sb 01 -> don't care
-- 0010 -> xor 10 -> sh 10 -> jal
-- 0011 -> don't care alu_src2: 11 -> sw 11 -> jalr
-- 0100 -> add 000... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
package fifo_pkg is
signal wr_en : std_logic; -- Comment
signal rd_en : std_logic; -- Comment
constant c_constant : integer; -- Comment
signal wr_en : std_logic; -- Comment
signal rd_en : std_logic; -- Comment
constant c_constant : integer; -- Comment
end package;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
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