content stringlengths 1 1.04M ⌀ |
|---|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
--use work.common.all;
ENTITY user_logic_hwtul IS
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_fun... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:49:45 06/05/2016
-- Design Name:
-- Module Name: RegistrosAbajo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- ... |
-- $Id: pdp11_sys70.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_sys70 - syn
-- Description: pdp11: 1... |
entity hintbug is
end entity;
architecture test of hintbug is
function func(x : bit) return bit_vector is
begin
return x & '1';
end function;
begin
process is
variable v : bit_vector(1 downto 0);
variable x : bit := '1';
begin
v := func(x); -- Will... |
---------------------------------------------------------------------
---- clock_divide_both.vhdl ----
---- ----
---- DOES NOT GIVE GOOD SYNTHESIS RESULTS: DUTYCYCLE != 50%
---- Divides ck_in by factor of divider.
----
--... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.BusMasters.all;
entity MAX6682_tb is
end MAX6682_tb;
architecture behavior of MAX6682_tb is
component MAX6682
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Enable_i : in std_logic;
CpuIn... |
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Mihaita Nagy
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Da... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
--
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/07 21:30:56 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: tx_ll_datapath_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.4 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gu... |
--
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/07 21:30:56 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: tx_ll_datapath_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.4 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gu... |
-- Copyright (C) 2014 Roland Dobai
--
-- This file is part of ZyEHW.
--
-- ZyEHW is free software: you can redistribute it and/or modify it under the
-- terms of the GNU General Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your option) any later
-- version.
--
... |
--------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information ... |
------------------------------------------------------
-- A four level, round-robin arbiter. This was
-- orginally coded by WD Peterson in VHDL.
-- Coder : Deepak Kumar Tala (Verilog)
-- Translator : Alexander H Pham (VHDL)
------------------------------------------------------
library ieee;
use i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- sewuence generator
-- note: cos,sin output on negative edge before pha, sync.
-- pha on positive edge, sync on positive edge
entity ram_lut is
port( nreset,clk,wstb,rstb: in std_logic;
cmd: in std_logic_vector(2 downto 0); -- contro... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- sewuence generator
-- note: cos,sin output on negative edge before pha, sync.
-- pha on positive edge, sync on positive edge
entity ram_lut is
port( nreset,clk,wstb,rstb: in std_logic;
cmd: in std_logic_vector(2 downto 0); -- contro... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 21:01:02 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 21:01:02 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 21:01:02 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee ;
use ieee.std_logic_1164.all ;
use std.textio.all ;
entity cond_assign_proc is
end entity cond_assign_proc ;
architecture doit of cond_assign_proc is
signal Clk : std_logic := '0' ;
signal Y : std_logic ;
begin
Clk <= not Clk after 10 ns ;
process (Clk)
variable A : std... |
library ieee ;
use ieee.std_logic_1164.all ;
use std.textio.all ;
entity cond_assign_proc is
end entity cond_assign_proc ;
architecture doit of cond_assign_proc is
signal Clk : std_logic := '0' ;
signal Y : std_logic ;
begin
Clk <= not Clk after 10 ns ;
process (Clk)
variable A : std... |
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
... |
-- ================================================================================
-- Legal Notice: Copyright (C) 1991-2006 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentat... |
--------------------------------------------------------------------------------
--
-- Design unit generated by Aldec IP Core Generator, version 8.2.
-- Copyright (c) 1997 - 2009 by Aldec, Inc. All rights reserved.
--
--------------------------------------------------------------------------------
--
-- Created ... |
entity tb_ram4 is
end tb_ram4;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_ram4 is
signal clk : std_logic;
signal en : std_logic;
signal we : std_logic;
signal addr : std_logic_vector(5 downto 0);
signal rdat : std_logic_vector(31 downto 0);
signal wdat : std_logic_vector(31 downto... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- T... |
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00510
--
-- AUTHOR:
--
-- D. Hyma... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
----------------------------------------------------------------------------------
-- Óñòðîéñòâî: êíîïêè
-- Êîä: 0x03
-- --------- ---------- ---------- --------- ------- ------- ------- -------
-- | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
-- |-----------------------------------------... |
architecture RTL of BLOCK_EXAMPLE is
begin
-- correct block format
BLK : block is
generic (
A : std_logic;
B : integer;
E, F : positive
);
generic map (
A => B,
B => C,
E => X,
F => Z
);
port (
A : std_logic;
B : integer;
E, F : po... |
library ieee;
use ieee.std_logic_1164.all,
ieee.numeric_std.all;
entity tdp_ram is
generic (
ADDRWIDTH_A : positive := 12;
WIDTH_A : positive := 8;
ADDRWIDTH_B : positive := 10;
WIDTH_B : positive := 32;
COL_WIDTH : positive := 8
);
port (
clk_a... |
--
-- 16-bit Timer for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistribut... |
-- NEED RESULT: ARCH00406.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00406.P2: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00406.P3: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity func08b is
port (v : std_ulogic_vector (3 downto 0);
r : out integer);
end func08b;
architecture behav of func08b is
function fls (val: std_ulogic_vector(3 downto 0)) return integer is
variable ret: integer;
begin
ret :=... |
-------------------------------------------------------------------------------
--! @file openmac-rtl-ea.vhd
--
--! @brief openMAC core
--
--! @details This is the openMAC core file implementing the MAC functionality.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2009... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity FIFO is
generic(
-- øèíà àäðåñà
m: integer := 2;
-- øèíà äàííûõ
n: integer := 2
);
port (
-- ñèíõðîíèçàöèÿ
CLK: in std_logic;
-- ñèãíàë óïðàâëåíèÿ ÷òåíèåì/çàïèñüþ
WR: in std_logic;
--... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:52:25 03/11/2014
-- Design Name:
-- Module Name: BaudRateGenerator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
... |
---------------------------------------------------------------------------------
-- TZX player
-- by György Szombathelyi
-- basic idea for the structure based on c1530 tap player by darfpga
--
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_11... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
----------------------------------------------------------------------------------
-- Author: Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com
--
-- Create Date: 01:21:32 06/30/2011
-- Design Name:
-- Module Name: spi_master_atlys_top
-- Project Name: spi_master_slave
-- Target Devices: Spar... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:10:22 11/17/2013
-- Design Name:
-- Module Name: C:/Users/etingi01/Mips32_948282/My_32bitAdder_tb_948282.vhd
-- Project Name: Mips32_948282
-- Target Device:
-- Tool versions:
-- ... |
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity test_xor_32_bits is
end test_xor_32_bits;
architecture behavior of test_xor_32_bits is
signal data_in: std_logic_vector(0 to 31);
signal key: std_logic_vector(0 to 31);
signal data_out: std_logic_vector(0 to 31);
begin
uut: entity xor_32_bits po... |
-- niosii_system_width_adapter_005.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:30
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_width_adapter_005 is
generic (
IN_PKT_ADDR_H : integer := 33;
IN_PKT_ADDR_L : intege... |
entity comp1_bot is
port (
x : in integer;
y : out integer );
end entity;
architecture rtl of comp1_bot is
begin
y <= x + 1;
end architecture;
-------------------------------------------------------------------------------
entity comp1 is
end entity;
architecture rtl of comp1 is
signal a... |
entity comp1_bot is
port (
x : in integer;
y : out integer );
end entity;
architecture rtl of comp1_bot is
begin
y <= x + 1;
end architecture;
-------------------------------------------------------------------------------
entity comp1 is
end entity;
architecture rtl of comp1 is
signal a... |
entity comp1_bot is
port (
x : in integer;
y : out integer );
end entity;
architecture rtl of comp1_bot is
begin
y <= x + 1;
end architecture;
-------------------------------------------------------------------------------
entity comp1 is
end entity;
architecture rtl of comp1 is
signal a... |
entity comp1_bot is
port (
x : in integer;
y : out integer );
end entity;
architecture rtl of comp1_bot is
begin
y <= x + 1;
end architecture;
-------------------------------------------------------------------------------
entity comp1 is
end entity;
architecture rtl of comp1 is
signal a... |
entity comp1_bot is
port (
x : in integer;
y : out integer );
end entity;
architecture rtl of comp1_bot is
begin
y <= x + 1;
end architecture;
-------------------------------------------------------------------------------
entity comp1 is
end entity;
architecture rtl of comp1 is
signal a... |
-------------------------------------------------------------------------------
-- Title : Finite Impulse Response Filter
-- Author : Steiger Martin <martin.steiger@students.fh-hagenberg.at>
-------------------------------------------------------------------------------
-- Description : Simple FIR filter str... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity threshold_process is
generic (
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic... |
------------------------------------------------------------------------------
-- add_sub_core - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2010 Xilinx,... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity test_logic is
port(sum:in std_logic_vector(3 downto 0);
d7,d711,d2312:out bit);
end test_logic;
architecture test of test_logic is
begin
process(sum)
begin
if sum="0111" then
d7<='1';
else d7<='0';
end if... |
-- Copyright 2018 Google LLC
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in w... |
-------------------------------------------------------------------------------
-- Title : UART package
-------------------------------------------------------------------------------
-- Standard : VHDL'x
-------------------------------------------------------------------------------
-- Description:
-----------... |
-------------------------------------------------------------------------------
-- $Id: pf_counter_bit.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- pf_counter_bit.vhd - entity/architecture pair
-----------------------------------------... |
-------------------------------------------------------------------------------
-- $Id: pf_counter_bit.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- pf_counter_bit.vhd - entity/architecture pair
-----------------------------------------... |
-- **********************************************************
-- Corso di Reti Logiche - Progetto Registratore Portatile
-- Andrea Carrer - 729101
-- Modulo Display.vhd
-- Versione 1.03 - 21.03.2013
-- **********************************************************
-- ****************************************... |
library ieee ;
use ieee.std_logic_1164.all;
package mypackage is
type myarray2dim is array(1 downto 0, 1 downto 0) of bit;
type myarray1 is array(1 downto 0) of bit_vector(1 downto 0);
end package;
library ieee ;
use ieee.std_logic_1164.all;
use work.mypackage.all;
entity myentity is
generic (
genarr2dim: ... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and pro... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:18:38 09/28/2017
-- Design Name:
-- Module Name: C:/Users/utp/Desktop/TEMPORAL/ALU/MUX_tb.vhd
-- Project Name: ALU
-- Target Device:
-- Tool versions:
-- Description: ... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:18:38 09/28/2017
-- Design Name:
-- Module Name: C:/Users/utp/Desktop/TEMPORAL/ALU/MUX_tb.vhd
-- Project Name: ALU
-- Target Device:
-- Tool versions:
-- Description: ... |
architecture RTL of ENTITY_NAME is
begin
process
begin
FORCE_LABEL : sig1 <= force in a + b - c after 10 ns, d + e after 25 ns;
FORCE_LABEL : sig1 <= force out a + b - c after 10 ns, d + e after 25 ns;
FORCE_LABEL : sig1 <= force a + b - c after 10 ns, d + e after 25 ns;
FORCE_LABEL : sig1 <=... |
-- file: nbit_register_pack.vhd
-- authors: Alexandre Medeiros and Gabriel Lopes
--
-- Solution to MC613 - Lab06.Q2.A
--
-- This package contains the following components:
--
-- * nbit_register:
-- A n bit register
library ieee ;
use ieee.std_logic_1164.all ;
package nbit_register_pack is
component nbit_register
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is
generic
(
NUM_STAGES : natural := 10
);
port
(
clk : in std_logic;
enable : in std_logic;
rst_n : in std_logic;
clear : in std_logic;
cnt_out: out std_logic_vector((NUM_STAGES-1) downto 0)
);
end entity;
archi... |
entity ent is
end entity;
architecture a of ent is
procedure proc(s : string) is
begin
report integer'image(s'left);
report integer'image(s'right);
report s;
end procedure;
begin
main : process
begin
proc(s(4 to 15) => "Hello world!");
wait;
end process;
end architecture;
|
entity ent is
end entity;
architecture a of ent is
procedure proc(s : string) is
begin
report integer'image(s'left);
report integer'image(s'right);
report s;
end procedure;
begin
main : process
begin
proc(s(4 to 15) => "Hello world!");
wait;
end process;
end architecture;
|
entity ent is
end entity;
architecture a of ent is
procedure proc(s : string) is
begin
report integer'image(s'left);
report integer'image(s'right);
report s;
end procedure;
begin
main : process
begin
proc(s(4 to 15) => "Hello world!");
wait;
end process;
end architecture;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_a_e
--
-- Generated
-- by: wig
-- on: Mon Mar 5 13:21:41 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -variant Calculate -nodelta ../../macro.xls
--
-- !!... |
entity logical3 is
end entity;
architecture test of logical3 is
signal v : bit_vector(1 to 3);
begin
process is
begin
v <= "110";
wait for 1 ns;
assert and v = '0';
assert nand v = '1';
assert or v = '1';
assert nor v = '0';
assert xor v = '0';
... |
library verilog;
use verilog.vl_types.all;
entity flexible_lvds_rx is
generic(
number_of_channels: integer := 1;
deserialization_factor: integer := 4;
use_extra_ddio_register: string := "YES";
use_extra_pll_clk: string := "NO";
buffer_implementation: string := "RAM";
... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package command_if_pkg is
constant c_cif_io_slot_base : unsigned(3 downto 0) := X"0";
constant c_cif_io_slot_enable : unsigned(3 downto 0) := X"1";
constant c_cif_io_handshake_out : unsigned(3 downto 0) := ... |
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: ieee754_fp_adder_subtractor - Structural
-- Description: Adds/subtracts two IEEE-754 floating point numbers
------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: ieee754_fp_adder_subtractor - Structural
-- Description: Adds/subtracts two IEEE-754 floating point numbers
------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: ieee754_fp_adder_subtractor - Structural
-- Description: Adds/subtracts two IEEE-754 floating point numbers
------------------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use work.exploration_pkg.all;
entity ExplorationGrid is port (
currentCellsInView: in gridArray;
grid : out gridArray);
end ExplorationGrid;
architecture explorationGrid of ExplorationGrid is
signal exploredGrid : gridArray;
begin
process(currentCellsInV... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity output_split2 is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(2 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
ra0_addr : in std_logic_vector(2 downto 0);
wa0_en : in ... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity output_split2 is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(2 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
ra0_addr : in std_logic_vector(2 downto 0);
wa0_en : in ... |
-- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_... |
--*****************************************************************************
-- (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- ... |
architecture rtl of fifo is
begin
procedure_call_label : postponed wr_en(a, b);
procedure_call_label : postponed wr_en(a, b);
end architecture rtl;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:03:30 06/04/2011
-- Design Name:
-- Module Name: tx_arbitrator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: arbitrate between ... |
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