# tiny-gpu on FPGA — Sizing, Requirements, and Board Options

All numbers below are **measured**, not estimated — produced by running Yosys
synthesis against `build/gpu.v` for each target family. Reproduction commands
are at the bottom.

---

## 1. Summary

| Question | Answer |
|---|---|
| How big is tiny-gpu? | **~5,500–7,300 logic cells** at the default `NUM_CORES=2` |
| Cost per core | **≈2,790 LUT4 + 1,060 flip-flops** |
| Smallest device that fits (2 cores) | iCE40 **LP8K** (7,680 LC) at ~72% |
| Does Cyclone II EP2C5 fit? | **No** — needs 7,343 LC, device has 4,608 (159%) |
| Does Spartan-6 XC6SLX9 fit? | **No** — needs 6,144 LUT, device has 5,720 (107%) |
| Biggest hidden task | Top level has **183 port bits**; needs an on-chip memory wrapper |

---

## 2. Resource scaling with `NUM_CORES`

Measured with `synth_ice40`. Scaling is clean and linear.

| `NUM_CORES` | LUT4 | Flip-flops | Device size needed (≤80% util) |
|---|---|---|---|
| 1 | 2,743 | 1,221 | ≥ 3,400 LC |
| **2** (default) | **5,547** | **2,284** | **≥ 6,900 LC** |
| 4 | 11,157 | 4,405 | ≥ 13,900 LC |

**Sizing constant: ≈2,790 LUT4 + 1,060 FF per core.**

Note `gpu.png` draws 4 cores but [`gpu.sv:17`](src/gpu.sv#L17) defaults to
`NUM_CORES = 2`. Building the diagram's version roughly doubles the requirement.

---

## 3. Mapped size per FPGA family (`NUM_CORES=2`)

The same design maps very differently depending on the target architecture.
LUT4 devices need more cells than LUT6 devices; Intel's flow absorbed the
multipliers into DSP blocks.

| Family | Combinational | Flip-flops | Carry / DSP |
|---|---|---|---|
| Lattice **ECP5** | **4,685** LUT4 | 2,284 | 476 CCU2C |
| Lattice **iCE40** | 5,547 LUT4 | 2,284 | 730 SB_CARRY |
| **Gowin** | 5,881 LUT | 2,284 | 976 ALU |
| **Xilinx** 7-series | 6,144 LUT (LUT1–LUT6) | 2,328 FDRE | 505 CARRY4 |
| **Intel** MAX 10 | 7,343 LCELL_COMB | 2,284 dffeas | **8 DSP multipliers** |

Worth noting: Intel's flow inferred **8 hardware multipliers** — exactly
2 cores × 4 threads = 8 ALUs, one `MUL` each. On the LUT4 families the
multipliers were built out of logic instead, which is part of why those
counts differ.

The flip-flop count is essentially **constant at ~2,284** across every family.
Sequential state is fixed by the RTL; only the combinational logic gets
restructured by the target architecture.

---

## 4. Device fit table (`NUM_CORES=2`)

| Device | Capacity | Needed | Util | Fits? |
|---|---|---|---|---|
| Intel Cyclone II **EP2C5** | 4,608 LE | 7,343 | **159%** | ❌ |
| Gowin **GW1N-4** (RUNBER) | 4,608 LUT | 5,881 | **128%** | ❌ |
| Lattice iCE40 **UP5K** | 5,280 LC | 5,547 | **105%** | ❌ |
| Xilinx Spartan-6 **XC6SLX9** | 5,720 LUT6 | 6,144 | **107%** | ❌ |
| Lattice iCE40 **LP8K/HX8K** | 7,680 LC | 5,547 | 72% | ✅ |
| Xilinx Spartan-7 **XC7S15** | 8,000 LUT6 | 6,144 | 77% | ✅ tight |
| Gowin **GW1NR-9** (Tang Nano 9K) | 8,640 LUT | 5,881 | 68% | ✅ |
| Gowin **GW2A-18** (Tang Nano 20K) | 20,736 LUT | 5,881 | 28% | ✅ |
| Xilinx Artix-7 **XC7A35T** | 20,800 LUT6 | 6,144 | 30% | ✅ |
| Lattice **ECP5-25F** | 24,000 LUT | 4,685 | 20% | ✅ |
| Xilinx Zynq **XC7Z020** (PYNQ-Z2) | 53,200 LUT6 | 6,144 | 12% | ✅ |
| Intel MAX 10 **10M50** (DECA) | 49,760 LE | 7,343 | 15% | ✅ |
| Xilinx Artix-7 **XC7A100T** (Nexys 4 DDR) | 63,400 LUT6 | 6,144 | 10% | ✅ |

### For 4 cores (what gpu.png draws)

Needs **~11,200–14,700** cells depending on family. That eliminates every
iCE40, the Spartan-7, the Tang Nano 9K, and the Spartan-6. Viable:
ECP5-25F+, Tang Nano 20K, Artix-7 35T+, MAX 10 10M50, Zynq 7020.

---

## 5. Requirements spec

| # | Requirement | Value | Rationale |
|---|---|---|---|
| 1 | Logic cells | ≥6,900 (2 cores) / ≥13,900 (4 cores) | measured, §2 |
| 2 | Block RAM | ≥6 Kbit | prog mem 256×16 = 4 Kbit; data mem 256×8 = 2 Kbit |
| 3 | Free I/O | ~10 pins *after wrapper* | 183 raw port bits otherwise — see §7 |
| 4 | Clock | any onboard oscillator | design is slow; ~20–50 MHz on iCE40 |
| 5 | Toolchain | see §6 | the practical filter |
| 6 | Programming | USB, ideally built-in bootloader | avoids buying a separate programmer |
| 7 | Observability | UART (2 pins) or ≥8 LEDs | must read results back out |

**Not required:** external DRAM, PCIe, high-speed transceivers, HDMI, Ethernet.
tiny-gpu is an undemanding design — don't pay for those.

Requirement #2 is satisfied by essentially every FPGA ever made; it exists only
to make the §7 wrapper possible.

Requirement #7 is the one that gets forgotten. Once memories move on-chip, the
Python testbench can no longer read the answer. Without a UART you have a design
that computes correctly and tells you nothing.

---

## 6. Toolchain matrix

| Family | Toolchain | macOS ARM | Windows/Linux |
|---|---|---|---|
| Lattice iCE40 | Yosys + nextpnr + **icestorm** (open) | ✅ native | ✅ |
| Lattice ECP5 | Yosys + nextpnr + **trellis** (open) | ✅ native | ✅ |
| Gowin | Yosys + **apicula** (open), or Gowin EDA | ✅ native | ✅ |
| Xilinx 7-series | **Vivado** | ❌ | ✅ |
| Xilinx Spartan-6 | **ISE 14.7** (2013, legacy) | ❌ | ✅ |
| Intel MAX 10 / Cyclone 10 | **Quartus Prime Lite** | ❌ | ✅ |
| Intel Cyclone II | **Quartus II 13.0sp1** (2013, legacy) | ❌ | ✅ x86 only |
| Efinix Trion | **Efinity** | ❌ | ✅ |
| Microchip PolarFire | **Libero** | ❌ | ✅ |

The open toolchains use **Yosys**, which is already installed and is the same
synthesizer that produced every number in this document.

---

## 7. The integration work (do not skip)

The top module exposes **183 port bits**, because program and data memory are
*external* in the current design — that is what `docs/images/gpu.png` shows,
with Global Memory drawn outside the GPU box. The cocotb testbench fakes both
memories in Python.

No small FPGA board has 183 free I/O pins.

**Required before bring-up:** a wrapper module that

1. instantiates program memory (256 × 16 bit) in BRAM, preloaded with the kernel
2. instantiates data memory (256 × 8 bit) in BRAM, preloaded with input data
3. connects both to the existing GPU memory interfaces
4. exposes only `clk`, `reset`, `start`, `done`, plus UART/LED debug

This drops the pin count from 183 to ~10 and uses ~6 Kbit of the device's BRAM.
It is a well-defined task, not a redesign — but it sits between "board arrives"
and "it runs."

---

## 8. Board options

### If using the Mac (open toolchain only)

| Board | Device | Cores | Notes |
|---|---|---|---|
| **TinyFPGA BX** | iCE40 LP8K | 2 | USB bootloader built in, no programmer needed |
| **Tang Nano 20K** | Gowin GW2A-18 | 4 | best headroom for the price |
| **ULX3S / OrangeCrab** | ECP5-25F/85F | 4+ | most capable open-toolchain option |
| iCEBreaker | iCE40 UP5K | ❌ 1 | **does not fit 2 cores** despite the price |

### If using the Windows/Linux PC (full field)

| Board | Device | Cores | Notes |
|---|---|---|---|
| **Arty A7-35T** | Artix-7 XC7A35T | 4 | best general-purpose value; Vivado |
| **DECA Dev Kit** | MAX 10 10M50 | 4 | huge headroom; Quartus Lite |
| **PYNQ-Z2** | Zynq XC7Z020 | 4 | has **hard ARM cores** — relevant for AURA-1 |
| **Nexys 4 DDR** | Artix-7 XC7A100T | 4+ | overkill and expensive |
| Spartan-6 XC6SLX9 | XC6SLX9 | ❌ 1 | **does not fit 2 cores**; legacy ISE |
| Cyclone II EP2C5T144 | EP2C5 | ❌ | **does not fit**; legacy Quartus II 13 |

**Verdict on the Cyclone II EP2C5T144 board:** it is a genuine FPGA board and a
fine part to learn on, but it cannot hold tiny-gpu at default settings —
159% utilization. It would fit a single-core build (2,743 LUT4 → ~60%). The
toolchain is also frozen at Quartus II 13.0sp1 from 2013, x86 Windows/Linux only.

---

## 9. Reproducing these numbers

```sh
cd tiny-gpu

# core-count scaling (iCE40)
for N in 1 2 4; do
  yosys -p "read_verilog build/gpu.v; chparam -set NUM_CORES $N gpu; \
            synth_ice40 -top gpu; stat"
done

# cross-family comparison
for FAM in ice40 ecp5 gowin xilinx; do
  yosys -p "read_verilog build/gpu.v; chparam -set NUM_CORES 2 gpu; \
            synth_$FAM -top gpu; stat"
done

# Intel requires an explicit family
yosys -p "read_verilog build/gpu.v; chparam -set NUM_CORES 2 gpu; \
          synth_intel -family max10 -top gpu; stat"
```

`build/gpu.v` is the sv2v output of `src/*.sv`; regenerate with `make compile`.

### Caveats

- These are **Yosys synthesis** results, not post-place-and-route. Vendor tools
  (Vivado, Quartus) pack differently and their reported utilization will vary,
  typically in the design's favour for LUT6 architectures.
- Routing congestion, not logic count, is what usually kills a design above ~80%
  utilization. The "≤80% util" targets in §2 account for this.
- Device capacities are from vendor datasheets and were not independently
  verified here.