conversations listlengths 2 3 | source stringclasses 1 value | stack stringclasses 1 value |
|---|---|---|
[
{
"from": "system",
"value": "Support Verilator simulation again, {PRINTF,STOP}_COND changed\n"
},
{
"from": "human",
"value": "`define CLOCK_PERIOD 1.0\n`define PRINTF_COND TestDriver.printf_cond\n`define STOP_COND !TestDriver.reset\n`define RANDOMIZE_MEM_INIT\n`define RANDOMIZE_REG_INIT\n`defi... | systemverilog | chosen |
[
{
"from": "system",
"value": "Add tests for `split_by_char` functions\n\nThe `FAIL` macros don't handle string very well, because it's not possible to quote text containing strings. This makes the tests look pretty awkward.\n"
},
{
"from": "human",
"value": "module string_utils_unit_test;\n\n i... | systemverilog | chosen |
[
{
"from": "system",
"value": "Fix null pointer exceptions in test\n\nThese weren't a problem before, because if a method call on a `null` object doesn't try to access any instance members, the call won't fail.\n"
},
{
"from": "human",
"value": "package queue_test;\n\n `include \"svunit.svh\"\n ... | systemverilog | chosen |
[
{
"from": "system",
"value": "test: Disable some weird broken tests\n"
},
{
"from": "human",
"value": "// 6.20 of svlog-2009\n\nmodule A1 #(int a = 5, localparam logic b = 1, type c = int, parameter n);\n\t// TODO: Check that parameter port is\n\t// - parameter int a = 5,\n\t// - localparam logi... | systemverilog | chosen |
[
{
"from": "system",
"value": "[dv/lc_ctrl] Modify lc tests to use post_start alert checking.\n\nSigned-off-by: Cindy Chen <399ad771a111eac8923348b1e2af093034e5d4f1@opentitan.org>\n"
},
{
"from": "human",
"value": "// Copyright lowRISC contributors.\n// Licensed under the Apache License, Version ... | systemverilog | chosen |
[
{
"from": "system",
"value": "Fix warning related to string comparison\n\n`s[i]` returns a `byte`, whereas `char` is a `string`. DVT and VCS complain about this comparison, while Xcelium and QuestaSim are fine with it. No idea who is in the right here, but we don't want warnings in any of the tools.\n"
},... | systemverilog | chosen |
[
{
"from": "system",
"value": "Revert \"Revert \"Changes to Output Controller Ram Access\"\"\n\nThis reverts commit 7aa9b68244bcd22dad3a1b46e23e69e6e8535e8f.\n"
},
{
"from": "human",
"value": "// $Id: $\n// File name: OutputControllerRAM.sv\n// Created: 4/21/2016\n// Author: Diego De L... | systemverilog | chosen |
[
{
"from": "system",
"value": "Fix access qualifier warnings when using experimental test macros\n"
},
{
"from": "human",
"value": "`define SVUNIT_INTERNAL_TEST_BEGIN(TEST_NAME, BASE_CLASS) \\\n class TEST_NAME extends BASE_CLASS; \\\n local static const bit is_test_builder_registerd \\\n ... | systemverilog | chosen |
[
{
"from": "system",
"value": "Update test to cover variable declaration inside for-loop header.\n\nissues #548\n\nPiperOrigin-RevId: 341669535\n"
},
{
"from": "human",
"value": "//- @my_module defines/binding _\nmodule my_module();\n //- @y defines/binding Y\n int y = 0;\n initial begin... | systemverilog | chosen |
[
{
"from": "system",
"value": "Implement enough production code to make one test pass\n"
},
{
"from": "human",
"value": "package factorial;\n\n function automatic int unsigned factorial(int unsigned n);\n return 0;\n endfunction\n\nendpackage\n"
},
{
"from": "gpt",
"value": "pack... | systemverilog | chosen |
[
{
"from": "system",
"value": "test: Update complex SV ports test\n"
},
{
"from": "human",
"value": "// RUN: moore %s -e foo\n// IGNORE\n\nmodule foo (\n .P1(x1[3:0]),\n .P2(x1[7:0]),\n .P3(x2),\n P4,\n .P5({x3, x4}),\n {x5, x6}\n);\n // This language needs to die.\n outpu... | systemverilog | chosen |
[
{
"from": "system",
"value": "[otbn,dv] Fix callstack flags in coverage\n\npop_stack_a (resp. pop_stack_b) is signalled if the instruction in\nquestion tries to read from x1 with operand a (resp b). pop_stack is\nonly true if, furthermore, rd_commit_i holds. This guarantees that the\ninstruction isn't stall... | systemverilog | chosen |
[
{
"from": "system",
"value": "Revert \"Changes to Output Controller Ram Access\"\n\nThis reverts commit d865033eed25767d82413f5213a9ee4eacf02ed8.\n"
},
{
"from": "human",
"value": "// $Id: $\n// File name: OutputControllerRAM.sv\n// Created: 4/21/2016\n// Author: Diego De La Fuente\n/... | systemverilog | chosen |
[
{
"from": "system",
"value": "[edn/dv] Fix ENUMERR in DV environment\n\nSigned-off-by: Michael Schaffner <a005a2d3342a687ea2d05360c953107acbe83e08@google.com>\n"
},
{
"from": "human",
"value": "// Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for... | systemverilog | chosen |
[
{
"from": "system",
"value": "Increase L2 cache size to 256k\n"
},
{
"from": "human",
"value": "// \n// Copyright 2011-2015 Jeff Bush\n// \n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain... | systemverilog | chosen |
[
{
"from": "system",
"value": "[prim_rom] Use localparam for derived parameters\n\nSigned-off-by: Philipp Wagner <5a4b10454c30419e54a1570be358a516ff84bb63@lowrisc.org>\n"
},
{
"from": "human",
"value": "// Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LIC... | systemverilog | chosen |
[
{
"from": "system",
"value": "[sysrst_ctrl,dv] Add flash_wp_l_o check in smoke test\n\nThis pull request will update the smoke test to check\nrandomizing flash_wp_l_in will not affect flash_wp_l_o output pin\n\nSigned-off-by: Madhuri Patel <11ca6de05d3d25e46f997d96738859192826ff1e@ensilica.com>\n"
},
{
... | systemverilog | chosen |
[
{
"from": "system",
"value": "[prim_pad_wrapper] Correct OE signal polarity for Xilinx version\n\nSigned-off-by: Michael Schaffner <a005a2d3342a687ea2d05360c953107acbe83e08@google.com>\n"
},
{
"from": "human",
"value": "// Copyright lowRISC contributors.\n// Licensed under the Apache License, Ve... | systemverilog | chosen |
[
{
"from": "system",
"value": "Make sure test code is elaborated\n\nIt's kind of annoying to have to force the user to write the extra import statement. Let's see if we can do better.\n"
},
{
"from": "human",
"value": "module svunit_main;\n\n initial\n svunit::run_all_tests();\n\nendmodule\n"... | systemverilog | chosen |
[
{
"from": "system",
"value": "[dv/edn] Increase edn genbit max size\n\nThis PR increases genbits max size to increase toggle and functional\ncoverage.\n\nSigned-off-by: Cindy Chen <399ad771a111eac8923348b1e2af093034e5d4f1@opentitan.org>\n"
},
{
"from": "human",
"value": "// Copyright lowRISC con... | systemverilog | chosen |
[
{
"from": "system",
"value": "Fix compile of code under test to work together with stable SVUnit\n\nThe file doesn't need any include guards, as it's not meant to be included by any other file than the package. They bust the compile now, because the define gets set when compiling the stable SVUnit.\n"
},
... | systemverilog | chosen |
[
{
"from": "system",
"value": "Work around compile error due to order of qualifiers\n\nQuestaSim doesn't like it when `pure virtual` is not the first qualifier.\n"
},
{
"from": "human",
"value": "typedef class global_test_registry;\n\n\nvirtual class test;\n\n typedef class builder;\n\n\n prote... | systemverilog | chosen |
[
{
"from": "system",
"value": "[aon_timer,dv] Set TL Outstanding Request Cap as 1\n\nSigned-off-by: Canberk Topal <e6b05429a51cc3258c31cb1f7836595b60921a29@lowrisc.org>\n"
},
{
"from": "human",
"value": "// Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LI... | systemverilog | chosen |
[
{
"from": "system",
"value": "Update unit test to use updated names for SVUnit version for testing\n"
},
{
"from": "human",
"value": "module string_utils_unit_test;\n\n import svunit_pkg::*;\n `include \"svunit_defines.svh\"\n\n string name = \"string_utils_ut\";\n svunit_testcase svunit_ut;... | systemverilog | chosen |
[
{
"from": "system",
"value": "Make dummy clock gating module compatible with latch-based reg file\n\nThe latch-based register file needs a clock gating cell that is\ntransparent for the clock enable signal only during the low clock\nphase.\n"
},
{
"from": "human",
"value": "// Copyright lowRISC ... | systemverilog | chosen |
[
{
"from": "system",
"value": "Use proper get_next_item()/item_done() calls in driver example.\n"
},
{
"from": "human",
"value": "class my_driver extends uvm_driver #(my_item);\n virtual my_interface vif;\n\n `uvm_component_utils(my_driver)\n function new(string name=\"my_driver\", uvm_c... | systemverilog | chosen |
[
{
"from": "system",
"value": "Add example with usage of `FAIL_IF_EQUAL`\n"
},
{
"from": "human",
"value": "\nmodule equals_macros_example_unit_test;\n\n import svunit_pkg::svunit_testcase;\n `include \"svunit_defines.svh\"\n\n string name = \"equals_macros_example_ut\";\n svunit_testcase svu... | systemverilog | chosen |
[
{
"from": "system",
"value": "[otbn] Add missing context keyword to DPI declaration\n\nOtbnMemUtilLoadElf uses svSetScope to do back-door DPI accesses, which\nisn't allowed unless the DPI declaration is marked \"context\" (and VCS\ncomplains!)\n\nSigned-off-by: Rupert Swarbrick <290093e2ad2515ed2f14d749293c... | systemverilog | chosen |
[
{
"from": "system",
"value": "[dv/kmac] Fix shadow reg error due to locked regwen\n\n1). This PR fixes shadow reg error because when there is fatal alert, design\nlocks `cfg_regwen` to 0.\nBecause this is not a common behavior, in `kmac_common_vseq.sv` I\noverride `predict_shadow_reg_status` to capture this... | systemverilog | chosen |
[
{
"from": "system",
"value": "[otbn] Fix typo in SVA bindings\n\nSigned-off-by: Rupert Swarbrick <290093e2ad2515ed2f14d749293c8cf8e02ca274@lowrisc.org>\n"
},
{
"from": "human",
"value": "// Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for detail... | systemverilog | chosen |
[
{
"from": "system",
"value": "Fix verbosity in ECC UVM driver\n\nThis should have been UVM_HIGH (which disables the messages most of\nthe time).\n"
},
{
"from": "human",
"value": "// Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// ... | systemverilog | chosen |
[
{
"from": "human",
"value": "Add examples with usage of `FAIL_UNLESS_EQUAL`\n"
},
{
"from": "gpt",
"value": "\nmodule equals_macros_example_unit_test;\n\n import svunit_pkg::svunit_testcase;\n `include \"svunit_defines.svh\"\n\n string name = \"equals_macros_example_ut\";\n svunit_testcase s... | systemverilog | chosen |
[
{
"from": "human",
"value": "Add dummy unit test for sequencer_stub\n\nsequencer_stub cannot be compiled with UVM 1.2 in its current form. The\nonly purpose of these \"unit tests\" currently is to make sure it can be\ncompiled with all required UVM versions.\n"
},
{
"from": "gpt",
"value": "// C... | systemverilog | chosen |
[
{
"from": "human",
"value": "test: Add worst-case svlog port test case\n"
},
{
"from": "gpt",
"value": "// RUN: moore %s -e foo\n// IGNORE\n\nmodule foo (\n .P1(x1[3:0]),\n .P2(x1[7:0]),\n .P3(x2),\n P4,\n .P5({x3, x4}),\n {x5, x6}\n);\n // This language needs to die.\n o... | systemverilog | chosen |
[
{
"from": "human",
"value": "Add test module which will contain tests for `string_utils`\n"
},
{
"from": "gpt",
"value": "module string_utils_unit_test;\n\n import svunit_pkg::*;\n `include \"svunit_defines.svh\"\n\n string name = \"string_utils_ut\";\n svunit_testcase svunit_ut;\n\n import... | systemverilog | chosen |
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