---
dataset_name: AIDE-Chip-15K-gem5-Sims
pretty_name: AIDE-Chip 15K gem5 Simulation Dataset
license: cc-by-nc-sa-4.0
task_categories:
- tabular-regression
language:
- en
tags:
- computer-architecture
- gem5
- cache
- design-space-exploration
- surrogate-modeling
- microarchitecture
- systems-ml
- explainable-ai
size_categories:
- 10K<n<100K
---

# AIDE-Chip 15K gem5 Simulation Dataset

AIDE-Chip-15K-gem5-Sims is a structured dataset of approximately 15,000 validated RISC-V gem5 simulations covering cache hierarchy design-space exploration (DSE) for single-core processors.

The dataset was generated using gem5's Syscall Emulation (SE) mode and six representative workloads, spanning compute-bound, memory-bound, and irregular access patterns. Each sample maps cache configuration parameters to IPC and L2 miss rate, enabling training of fast, physically consistent surrogate models.

This dataset accompanies the paper:

> Udayshankar Ravikumar . Fast, Explainable Surrogate Models for gem5 Cache Design Space Exploration. Authorea. January 14, 2026.
> <https://doi.org/10.22541/au.176843174.46109183/v1>

## Supported Tasks

* Cache performance regression (IPC)
* Cache miss-rate regression (L2 miss rate)

## Workloads

| Workload     | Description                        |
| ------------ | ---------------------------------- |
| `crc32`      | Streaming, low locality            |
| `dijkstra`   | Pointer-chasing, irregular         |
| `fft`        | Strided, cache-sensitive           |
| `matrix_mul` | Dense compute, high reuse          |
| `qsort`      | Branchy, mixed locality            |
| `sha`        | Compute-bound, near-zero miss rate |

The C code of the workloads can be found at: <https://github.com/Uralstech/AIDE-Chip-Surrogates/tree/main/15k-Sims/benchmarks>

## Dataset Structure

The dataset is released as sharded CSV files for scalability.

Each row contains:

| Column                         | Description               |
| ------------------------------ | ------------------------- |
| l1d_size, l1i_size, l2_size    | Cache sizes (KB)          |
| l1d_assoc, l1i_assoc, l2_assoc | Associativities           |
| workload                       | Benchmark name            |
| ipc                            | Instructions per cycle    |
| l2_miss_rate                   | L2 miss rate              |
| sim_duration_s                 | gem5 simulation wall time |
| error                          | Simulation success flag   |
| error_msg                      | Simulation error message  |

## Generation Details

* Simulator: gem5 (SE mode)
* Execution platform:
  * 4× AWS c6g + 4× AWS c7g
  * 64 vCPUs each
* Sampling strategy:
  * Constrained grid over cache sizes & associativities
  * Validity constraints enforced
  * Randomized execution order
* Recommended dataset split:
  * 70% train / 15% validation / 15% test (per workload)

The script used to generate the configuration set can be found at: <https://github.com/Uralstech/AIDE-Chip-Surrogates/blob/main/15k-Sims/config-gen/generate_configs.py>

## Intended Use

This dataset is intended for:

* Research on surrogate modeling for architecture simulation
* Cache design-space exploration
* Explainable ML for systems
* Educational and academic use

**Not intended for commercial use** (see License).

## Patent Notice

This dataset accompanies research describing surrogate-based techniques for
microarchitectural design-space exploration.

The author has filed a pending patent application that may cover broader
system-level methods beyond the specific data provided here.

This notice is informational only and does not alter the dataset’s
Creative Commons (CC BY-NC-SA 4.0) license.