[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Circadian-Friendly Led Light Sources

Technical Field and Background:
Identification of non-visual photoreceptors in the human eye (so-called intrinsically photosensitive retinal ganglion cells, or “ipRGCs”) linked to the circadian system has sparked considerable interest in the effects of various light spectra on health and amenity for human beings. High circadian stimulation may lead to positive effects such as resetting sleep patterns, boosting mood, increasing alertness and cognitive performance, and alleviating seasonal affective depression. However, mis-timed circadian stimulation can also be associated with disruption of the internal biological clock and melatonin suppression, and may be linked to illnesses such as cancer, heart disease, obesity and diabetes. Circadian stimulation is associated with glucocorticoid elevation and melatonin suppression and is most sensitive to light in the blue wavelength regime. With the preponderance of light-emitting diode (LED) illumination products being based on blue-primary phosphor-converted white-emitting LEDs, the situation has developed that most LED-based illumination sources have higher levels of circadian stimulation than the traditional sources they are intended to replace. Legacy techniques have been studied and in some cases techniques for dealing with circadian stimulation in lighting products have been published (e.g., see WO 2014165692 to Moore-Ede et al.), however such legacy techniques are deficient, at least in regards to uses of the herein-disclosed techniques to address lighting system design with respect to diurnal or circadian cycles In addition, illumination products are rarely tunable (other than mere dimming), and legacy illumination products fail to address the impact on humans with respect to diurnal or circadian cycles. Still worse, legacy illumination products that are ostensibly tunable fail to produce good color rendering throughout the tunable range. What is needed is a technique or techniques for constructing illumination products in which light emission (e.g., LED light emission) can be controlled to provide varying levels of circadian stimulation while providing desirable light quality aspects such as correlated color temperature (CCT) and color rendering index (CRI). Also needed is an illumination system in which a first ratio and a second ratio of light emission are such that changing from the first ratio to the second ratio varies relative circadian stimulation while maintaining a CRI above 80 and maintaining the CCT within a prescribed range. The aforementioned legacy technologies do not have the capabilities to implement a circadian-friendly LED light sources in an efficient manner. Therefore, there is a need for improved approaches.

Invention Disclosure:
Methods and apparatus for providing circadian-friendly LED light sources are disclosed. A light source is formed to include a first LED emission (e.g., one or more LEDs emitting a first spectrum) and a second LED emission (e.g., one or more LEDs emitting a second spectrum) wherein the first and second LED emissions are combined in a first ratio and in a second ratio such that while changing from the first ratio to the second ratio the relative circadian stimulation is varied while maintaining a color rendering index above 80.

[Assistant]
1. A light-emitting system comprising:
at least one solid-state lighting emitter emitting with a peak between 400 and 430 nm;
at least one first phosphor having a peak emission between 500 nm and 550 nm, and at least one second phosphor having a peak emission between 600 nm and 670 nm; and
wherein said lighting emitter and said first and second phosphors are configured such that the light-emitting system emits an emitted light having a spectral power distribution (SPD), wherein the SPD has a local minimum in a spectral region between 440 am and 480 am and wherein an area under the SPD in the range of 440 nm to 480 am is less than 2% of an area under the SPD in a range of 380 nm to 780 nm.

2. The system of claim 1, wherein said first and second phosphors are selected from silicates, fluorosilicates doped with Eu 2+, chalcogenides doped with Eu 2+, nitridosilicates, oxynitridosilicates, oxynitridoaluminosilicates, β-sialons doped with Eu 2+ carbidooxynitridosilicates doped with Eu 2+, nitridosilicates doped with Eu 2+; carbidonitridosilicates doped at least with Eu 2+; chalcogenides doped with Eu 2+, oxides, oxyfluorides, complex fluorides doped with Mn 4+, and combinations thereof.

3. The system of claim 1, wherein said emitted light has a certain correlated color temperature (CCT), is configured to produce a predetermined illuminance of about 50 lux to about 5000 lux, and a circadian stimulation no greater than about 50% of a reference circadian stimulation of a reference illuminant configured to produce an illuminance essentially the same as said predetermined illuminance and having a CCT the same as said certain CCT.

4. The system of claim 3, wherein said certain CCT is greater than or equal to 2700K.

5. The system of claim 1, wherein the area under the SPD within a range of 440 nm and 480 nm is less than 0.5% of the area under the SPD within a range of 380 nm to 780 nm.

6. The system of claim 1, wherein an absolute distance from the Planckian locus (Duv) is less than 0.006.

7. The system of claim 1, wherein the system comprises a general CRI index (Ra) is greater than or equal to 80.

8. The system of claim 1, wherein the system comprises a special CRI index #9 (R9) greater than or equal to 0.

9. The system of claim 1, further comprising a filter substantially absorbing or reflecting light having a wavelength within a range of 430 nm to 490 nm.

10. The system of claim 9, wherein the filter does not significantly affect a chromaticity of the emitted light.

11. The system of claim 1, wherein the first phosphor and the second phosphor are disposed in layers or in a pattern of small patches around the LED pump.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Semiconductor Device And A Manufacturing Method Thereof

Technical Field and Background:
The present invention relates to a semiconductor device and a manufacturing method thereof. The present invention is applicable to, for example, manufacturing of a semiconductor device having a nonvolatile memory and a capacitor element. As an electrically writable/erasable nonvolatile semiconductor storage device, an EEPROM (Electrically Erasable and Programmable Read Only Memory) has been widely used. Such a storage device has a conductive floating gate electrode surrounded by an oxide film, or a trapping insulation film under the gate electrode of a MISFET. The storage device uses the charge accumulation state at the floating gate or the trapping insulation film as stored information, and read out the information as a threshold value of the transistor. The trapping insulation film denotes an insulation film capable of accumulating electric charges. As one example thereof, mention may be made of a silicon nitride film. Implantation/discharge of electric charges into such a charge accumulation region causes each MISFET to be shifted in threshold value and to operate as a storage element. The nonvolatile storage devices using a trapping insulation film include a split gate type cell using a MONOS (Metal Oxide Nitride Oxide Semiconductor) film. Whereas, as the formation method of a gate electrode, a so-called gate-last process is known in which after forming a dummy gate electrode over a substrate, the dummy gate electrode is replaced with a metal gate electrode, or the like. When the gate-last process is used, it is difficult to form a capacitor element in which the lower electrode is formed at the same height as that of the gate electrode, and the upper electrode is formed over the lower electrode. In contrast, a capacitor element in which the semiconductor substrate is used as the lower electrode, and the upper electrode is formed at the same height as that of the gate electrode can be merged with a storage element, and the like formed using the gate-last process over the semiconductor substrate. In such a capacitor element, the upper electrode is partially embedded in the trenches formed in the main surface of the semiconductor substrate, so that the facing area of the upper electrode and the semiconductor substrate can be increased. This can increase the capacitance. Patent Document 1 (Japanese Unexamined Patent Application Publication No. 2001-85633) describes a capacitor element in which a capacitance is generated between a substrate and a first gate over the substrate, and further, a capacitance is generated between the first gate and a second gate over the first gate. Patent Document 2 (Japanese Unexamined Patent Application Publication No. 2003-309182) describes as follows: in a capacitor element for generating a capacitance between a substrate and an electrode over the substrate, the electrode is partially embedded in trenches in the top surface of the substrate. Patent Document 3 (Japanese Unexamined Patent Application Publication No. 2014-154790) describes that a memory cell is formed using the gate-last process. [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2001-85633 [Patent Document 2] Japanese Unexamined Patent Application Publication No. 2003-309182 [Patent Document 3] Japanese Unexamined Patent Application Publication No. 2014-154790

Invention Disclosure:
In a semiconductor device including a split gate type MONOS memory, and a trench capacitor element having an upper electrode partially embedded in trenches formed in the main surface of a semiconductor substrate, merged therein, the flatness of the top surface of the upper electrode embedded in the trench is improved. The polysilicon film formed over the semiconductor substrate to form a control gate electrode forming a memory cell of the MONOS memory is embedded in the trenches formed in the main surface of the semiconductor substrate in a capacitor element formation region, thereby to form the upper electrode including the polysilicon film in the trenches.

[Assistant]
1. A method for manufacturing a semiconductor device, comprising:
(a) providing a semiconductor substrate having a first region and a second region arranged along a main surface;
(b) forming a first trench in the main surface of the semiconductor substrate in the second region;
(c) covering a sidewall and a bottom surface of the first trench with a first insulation film;
(d) after (c), forming a first conductor film over the main surface of the semiconductor substrate in the first region and the second region, and thereby embedding the first conductor film in the first trench via the first insulation film;
(e) processing the first conductor film in the first region to form a control gate electrode comprised of the first conductor film;
(f) after (e), forming a memory gate electrode adjacent to a sidewall of the control gate electrode via a second insulation film, the second insulation film having a charge accumulation part therein;
(g) processing the first conductor film in the second region to form a first electrode comprised of the first conductor film embedded in the first trench; and
(h) after (f), forming a pair of first source/drain regions in the main surface of the semiconductor substrate in the first region,
wherein the control gate electrode, the memory gate electrode, and the pair of first source/drain regions form a memory cell of a nonvolatile memory, and
wherein the first electrode and the semiconductor substrate under the first electrode form a capacitor element.

2. The method for manufacturing a semiconductor device according to claim 1,
wherein (f) includes:
(f1) sequentially stacking the second insulation film and a second conductor film over the semiconductor substrate; and
(f2) processing the second insulation film and the second conductor film to form the memory gate electrode, which is comprised of the second conductor film, adjacent to the sidewall of the control gate electrode via the second insulation film,
wherein a film thickness of the second conductor film is smaller than a film thickness of the first conductor film.

3. The method for manufacturing a semiconductor device according to claim 1,
wherein in (b), a second trench is formed in the main surface of the semiconductor substrate in the first region,
the method further comprising:
(b1) after (b), embedding a third insulation film within the second trench and within the first trench, and thereby forming an element isolation region formed of the third insulation film in the second trench; and
(b2) before (c), removing at least a portion of the third insulation film in the first trench by etching.

4. The method for manufacturing a semiconductor device according to claim 3,
wherein a corner part of an upper end of the sidewall of the first trench is larger in radius of curvature than a corner part of an upper end of a sidewall of the second trench.

5. The method for manufacturing a semiconductor device according to claim 4,
wherein a corner part of an end of the bottom surface of the first trench is larger in radius of curvature than a corner part of an end of a bottom surface of the second trench.

6. The method for manufacturing a semiconductor device according to claim 3,
wherein after the removing of (b2), a portion of the third insulation film in contact with the bottom surface of the first trench remains,
wherein in (c), a fifth insulation film covering the sidewall of the first trench exposed from the third insulation film is formed, and the sidewall and the bottom surface of the first trench are covered with the first insulation film, which includes the fifth insulation film and the remaining portion of the third insulation film.

7. The method for manufacturing a semiconductor device according to claim 3,
wherein after (b2), a portion of a top surface of the semiconductor substrate adjacent to the first trench is lower than a portion of the top surface of the semiconductor substrate adjacent to the second trench.

8. The method for manufacturing a semiconductor device according to claim 3,
wherein after (b2), the bottom surface of the first trench is lower than a bottom surface of the second trench.

9. The method for manufacturing a semiconductor device according to claim 3,
wherein in (b), anisotropic etching is performed using a fourth insulation film including silicon nitride as a mask, thereby to form the second trench and the first trench, and
wherein in (b2), the fourth insulation film and the third insulation film in the second region are removed by anisotropic etching.

10. The method for manufacturing a semiconductor device according to claim 3,
wherein in (b), anisotropic etching to form the first and second trenches is performed using a fourth insulation film as a mask, the fourth insulation film being formed over the semiconductor substrate and including a first mask layer of silicon nitride and a second mask layer,
wherein prior to (b2), the first mask layer is removed by anisotropic etching, and
wherein in (b2), the second mask layer of the fourth insulation film and the third insulation film in the second region are removed by dry etching.

11. The method for manufacturing a semiconductor device according to claim 3,
wherein in (b), another second trench is formed in the main surface of the semiconductor substrate in the first region when the second trench and the first trench are formed in the main surface of the semiconductor substrate in the second region, and
wherein a portion of a top surface of the first electrode over the first trench is lower than a portion of the top surface of the first electrode over the element isolation region in the second region.

12. The method for manufacturing a semiconductor device according to claim 11, further comprising:
(i) forming a first interlayer insulation film covering the control gate electrode, the memory gate electrode, and the first electrode over the semiconductor substrate; and
(j) polishing a top surface of the first interlayer insulation film.

13. The method for manufacturing a semiconductor device according to claim 12,
wherein in (j), the top surface of the first interlayer insulation film is polished to expose a top surface of the first electrode over the element isolation region,
the method further comprising:
(k) after (j), forming a second interlayer insulation film covering the top surface of the first interlayer insulation film and the top surface of the first electrode,
wherein over the first trench, a portion of the first interlayer insulation film is interposed between the first electrode and the second interlayer insulation film.

14. The method for manufacturing a semiconductor device according to claim 13, further comprising:
(j1) after (j), and before (k), forming a silicide layer at the top surface of the first electrode exposed from the first interlayer insulation film; and
(l) forming a contact plug penetrating through the second interlayer insulation film, and coupled with the silicide layer.

15. The method for manufacturing a semiconductor device according to claim 1,
wherein (f) includes:
(f1) sequentially stacking the second insulation film and a second conductor film over the semiconductor substrate in the first region, and over the first conductor film in the second region; and
(f2) processing the second insulation film and the second conductor film, thereby to form the memory gate electrode, and to form a second electrode in the second region, the second electrode being formed of the second conductor film over the first conductor film via the second insulation film,
wherein the first electrode, the semiconductor substrate under the first electrode, and the second electrode form the capacitor element.

16. The method for manufacturing a semiconductor device according to claim 1,
wherein the main surface of the semiconductor substrate includes a third region arranged side by side with the first region and the second region, and
wherein in (d), the first conductor film is formed over the main surface of the semiconductor substrate in the first region, the second region, and the third region,
the method further comprising:
(e1) processing the first conductor film in the third region, and forming a pseudo gate electrode comprised of the first conductor film;
(h1) after (e1), forming a pair of second source/drain regions in the main surface of the semiconductor substrate in the third region;
(i) after (h) and (h1), forming a first interlayer insulation film covering the control gate electrode, the memory gate electrode, the pseudo gate electrode, and the first electrode over the semiconductor substrate;
(j) polishing the top surface of the first interlayer insulation film to expose the top surface of the pseudo gate electrode; and
(j1) after (j), removing the pseudo gate electrode to form a third trench in the first interlayer insulation film in the third region, and forming a metal gate electrode in the third trench,
wherein the metal gate electrode and the pair of second source/drain regions form a field effect transistor.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: High Caliber Target

Technical Field and Background:
In order to maintain proficiency in the use of firearms, it is common for law enforcement officers, members of the military and sportsmen to engage in target practice. While many perceive target practice as simply a method for improving accuracy, it is important for law enforcement officers, members of the military and the like to conduct target practice in scenarios which improve timing and the ability to make split-second decisions on whether or not to fire. Such split-second decisions can mean the difference between life and death both for the officer or soldier and those around them. For example, a police officer who fires too quickly may shoot an unarmed person. If he or she delays too long, however, a perpetrator may shoot a bystander. In the military context a sniper must often make a split second decision on whether to fire at a target. The person could be an enemy combatant holding a rocket-propelled grenade or simply a person carrying a pipe. To simulate different scenarios, it is often desirable to move one or more targets around. For example, target one may be an enemy combatant, and targets two and three are innocent civilians. Training is often improved by subjecting the shooter numerous different scenarios to prevent expectancy of the proper response. While there are a wide variety of targets which are useful with smaller caliber rounds, such as a 0.223 or similar round, there are a more limited number of targets which are useful with high caliber rounds when a much larger projectile is fired into the target. For example, some machine guns and many sniper rifles fire a .50 BMG round (12.7×99 mm NATO), in which the weight of the projectile is typically about 620-710 grains (40-46 grams). Thus, the weight of the projectile used in these high caliber rounds can easily be 10 times that of the common infantry rifle. Stopping a .50 BMG round presents a challenge at shooting ranges, especially where the targets are desired to be mobile. Most targets which will handle more common rounds, such as 30-06 and below, can be damaged by higher caliber rounds such as the .50 BMG. Thus, either the target is damaged by the impact of the projectile, or the target is so large and bulky as to be difficult to move. While attempts at portable targets that will withstand .50 BMG rounds have been made, some are prone to falling over when impacted by the projectile. Others leave exposed hardware or joints or edges which can create a ricochet risk which is of particular concern with such a high powered round. Thus there is a need for an improved target which can be used with high caliber rounds with little or no damage, provides little risk of ricochet, and remains transportable about a shooting range, etc.

Invention Disclosure:
A high caliber target includes a target plate and a stand. The target plate may be mounted on and removed from the stand. In accordance with one embodiment, the target plate can be mounted and removed without tools. In accordance with one embodiment, the target plate is presented to the shooter without joints or edges which could promote ricochets back toward the shooter. In accordance with another embodiment, the target plate can pivot on impact relative to the stand.

[Assistant]
1. A high caliber portable target comprising:
a target plate having a first mounting bracket and a second mounting bracket attached thereto; and
a stand having at least one mounting structure, the at least one mounting structure extending through the first mounting bracket and the second mounting bracket to attach the target plate to the stand, the first mounting bracket and the second mounting bracket being slidably mountable along the at least one mounting structure to allow the first mounting bracket and the second mounting bracket to be positioned on, retained and removed from the at least one mounting structure without tools; and
wherein at least one of the first mounting bracket and the second mounting bracket extends rearwardly beyond the at least one mounting structure so as to allow said mounting bracket to slide rearwardly on the at least one mounting structure such that the target plate can deflect between 5 and 15 degrees toward vertical when impacted.

2. The high caliber portable target of claim 1, wherein the first mounting bracket has a plurality of slots and wherein the second mounting bracket has a plurality of slots and wherein the mounting structure of the stand comprises a first arm which extends through one slot in the first mounting bracket and through one slot in the second mounting bracket and a second arm, spaced apart from the first arm, the second arm extending through one slot on the first mounting bracket and one slot on the second mounting bracket so that the first arm and the second arm slidably engage the first mounting bracket and the second mounting bracket, respectively, and thereby support the target plate above a surface from which the stand extends.

3. The high caliber portable target of claim 2, wherein the plurality of slots in the second mounting bracket are larger than the plurality of slots in the first mounting bracket.

4. The high caliber portable target of claim 1, wherein the first mounting bracket and the second mounting bracket are welded to the target plate.

5. The high caliber portable target of claim 1, wherein the target plate has opposing lateral sides, and wherein the stand includes a first support having a mounting structure at an upper end thereof, and a second support having a mounting structure at an upper end thereof, the first support and the second support being spaced apart from each other so as to be positioned adjacent the opposing lateral sides of the target plate.

6. The high caliber portable target of claim 5, further comprising a plurality of cross-members attaching the first support to the second support.

7. The high caliber portable target of claim 1, wherein the target plate has a front side for being impacted by bullet and a rear side, the first mounting bracket and the second mounting bracket being attached to the rear side and do not extend forwardly of the front side of the target plate.

8. A target comprising a target plate, a first mounting bracket having a plurality of slots formed therein and a second mounting bracket having a plurality of slots formed therein, the first mounting bracket and the second mounting bracket being welded to the target plate, wherein the plurality of slots in the first mounting bracket are disposed in alignment with and generally in parallel with the plurality of slots in the second mounting bracket to facilitate a stand being advanced through the slots, and wherein the plurality of slots on the second mounting bracket are larger than the plurality of slots in the first mounting bracket.

9. The target of claim 8, wherein the plurality of slots in the second mounting bracket are longer than the plurality of slots in the first mounting bracket.

10. The target of claim 8, wherein the first mounting bracket and the second mounting bracket are attached to one side of the target plate and do not extend beyond an opposing side of the target plate.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Semiconductor Device And Method For Manufacturing The Same

Technical Field and Background:
1. Field of the Invention The present invention relates to a semiconductor device including an oxide semiconductor and a method for manufacturing the semiconductor device. In this specification, a semiconductor device generally means a device which can function by utilizing semiconductor characteristics, and an electrooptic device, a semiconductor circuit, and an electronic appliance are all semiconductor devices. 2. Description of the Related Art In recent years, semiconductor devices have been developed to be used mainly for a CPU, or a memory. A CPU is an aggregation of semiconductor elements each provided with an electrode which is a connection terminal, which includes a semiconductor integrated circuit (including at least a transistor and a memory) separated from a semiconductor wafer. A semiconductor circuit (IC chip) of a CPU or a memory is mounted on a circuit board, for example, a printed wiring board, to be used as one of components of a variety of electronic appliances. A technique for manufacturing a transistor or the like using an oxide semiconductor film for a channel formation region and applying it to a display device has been attracting attention. Examples of such a transistor include a transistor in which zinc oxide (ZnO) is used as an oxide semiconductor film and a transistor in which InGaO 3 (ZnO) m is used as an oxide semiconductor film. A technique for manufacturing transistor including an oxide semiconductor film over a light-transmitting substrate and applying it to a switching element or the like of an image display device is disclosed in Patent Documents 1 and 2. Patent Document 3 discloses a semiconductor device in which a transistor including an oxide semiconductor is provided over a single crystal substrate.

Invention Disclosure:
A highly reliable semiconductor device exhibiting stable electrical characteristics is provided. Further, a highly reliable semiconductor device is provided. Oxide semiconductor films are stacked so that the conduction band has a well-shaped structure. A second oxide semiconductor film having a crystalline structure is provided over the first oxide semiconductor film and a third oxide semiconductor film is provided over the second oxide semiconductor film. The bottom of a conduction band in the second oxide semiconductor film is deeper from a vacuum level than the bottom of a conduction band in the first oxide semiconductor film and the bottom of a conduction band in the third oxide semiconductor film.

[Assistant]
1. A semiconductor device comprising:
a gate electrode;
a gate insulating film over the gate electrode;
a first oxide semiconductor film over the gate insulating film;
a second oxide semiconductor film having a crystalline structure over the first oxide semiconductor film; and
a third oxide semiconductor film over the second oxide semiconductor film,
a source electrode and a drain electrode which are in contact with the third oxide semiconductor film,
wherein a bottom of a conduction band in the second oxide semiconductor film is deeper from a vacuum level than a bottom of a conduction band in the first oxide semiconductor film and a bottom of a conduction band in the third oxide semiconductor film,
wherein each of the first oxide semiconductor film, the second oxide semiconductor film, and the third oxide semiconductor film includes indium, zinc, and gallium,
wherein the first oxide semiconductor film has a lower degree of crystallinity than the second oxide semiconductor film, and
wherein the third oxide semiconductor film has a lower degree of crystallinity than the second oxide semiconductor film.

2. The semiconductor device according to claim 1, wherein the second oxide semiconductor film includes a crystal region which is c-axis-aligned in a direction substantially perpendicular to a surface of the second oxide semiconductor film.

3. The semiconductor device according to claim 1, wherein the second oxide semiconductor film has a higher indium content than the first oxide semiconductor film and the third oxide semiconductor film.

4. The semiconductor device according to claim 1, wherein the first oxide semiconductor film and the third oxide semiconductor film each have an indium content of higher than or equal to 1×10 19 /cm 3.

5. The semiconductor device according to claim 1, wherein a portion of the source electrode and a portion of the drain electrode are overlapped with the gate electrode.

6. A display device comprising:
a gate electrode;
a gate insulating film over the gate electrode;
a first oxide semiconductor film over the gate insulating film;
a second oxide semiconductor film having a crystalline structure over the first oxide semiconductor film; and
a third oxide semiconductor film over the second oxide semiconductor film,
a source electrode and a drain electrode which are in contact with the third oxide semiconductor film,
an insulating film over the third oxide semiconductor film, the source electrode and the drain electrode, and
a pixel electrode over the insulating film,
wherein a bottom of a conduction band in the second oxide semiconductor film is deeper from a vacuum level than a bottom of a conduction band in the first oxide semiconductor film and a bottom of a conduction band in the third oxide semiconductor film,
wherein each of the first oxide semiconductor film, the second oxide semiconductor film, and the third oxide semiconductor film includes indium, zinc, and gallium,
wherein the first oxide semiconductor film has a lower degree of crystallinity than the second oxide semiconductor film, and
wherein the third oxide semiconductor film has a lower degree of crystallinity than the second oxide semiconductor film.

7. The display device according to claim 6, wherein the second oxide semiconductor film includes a crystal region which is c-axis-aligned in a direction substantially perpendicular to a surface of the second oxide semiconductor film.

8. The display device according to claim 6, wherein the second oxide semiconductor film has a higher indium content than the first oxide semiconductor film and the third oxide semiconductor film.

9. The display device according to claim 6, wherein the first oxide semiconductor film and the third oxide semiconductor film each have an indium content of higher than or equal to 1×10 19 /cm 3.

10. The display device according to claim 6, wherein a portion of the source electrode and a portion of the drain electrode are overlapped with the gate electrode.

11. A display device comprising:
a gate electrode;
a gate insulating film over the gate electrode;
a first oxide semiconductor film over the gate insulating film;
a second oxide semiconductor film having a crystalline structure over the first oxide semiconductor film; and
a third oxide semiconductor film over the second oxide semiconductor film,
a source electrode and a drain electrode which are in contact with the third oxide semiconductor film,
an insulating film over the third oxide semiconductor film, the source electrode and the drain electrode, and
a pixel electrode over the insulating film,
wherein a bottom of a conduction band in the second oxide semiconductor film is deeper from a vacuum level than a bottom of a conduction band in the first oxide semiconductor film and a bottom of a conduction band in the third oxide semiconductor film,
wherein each of the first oxide semiconductor film, the second oxide semiconductor film, and the third oxide semiconductor film includes indium, zinc, and gallium,
wherein the third oxide semiconductor film is in contact with a side surface of the first oxide semiconductor film and a side surface of the second oxide semiconductor film,
wherein the first oxide semiconductor film has a lower degree of crystallinity than the second oxide semiconductor film, and
wherein the third oxide semiconductor film has a lower degree of crystallinity than the second oxide semiconductor film.

12. The display device according to claim 11, wherein the second oxide semiconductor film includes a crystal region which is c-axis-aligned in a direction substantially perpendicular to a surface of the second oxide semiconductor film.

13. The display device according to claim 11, wherein the second oxide semiconductor film has a higher indium content than the first oxide semiconductor film and the third oxide semiconductor film.

14. The display device according to claim 11, wherein the first oxide semiconductor film and the third oxide semiconductor film each have an indium content of higher than or equal to 1×10 19 /cm 3.

15. The display device according to claim 11, wherein a portion of the source electrode and a portion of the drain electrode are overlapped with the gate electrode.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Tri-Chamber Nutating Pump

Technical Field and Background:
1. Technical Field Improved nutating pumps are disclosed with a third chamber added to the dual-chamber pump of U.S. Pat. No. 7,946,832, which is incorporated herewith. The third chamber is disposed adjacent to a compensating piston, or other actively driven displacement device, which provides a cyclic displacement (zero net flow through the cycle), which compensates for pulsations in output flow the dual-chamber pump of U.S. Pat. No. 7,946,832. The disclosed pumps also provide a more steady flow than the four chamber pump disclosed in U.S. Pat. No. 8,353,690, which is also incorporated herewith. The disclosed tri-chamber pumps provide an output flow, which for all practical purposes, is a steady flow resulting in the essentially the same flow output for each motor step. 2. Description of the Related Art Nutating pumps are pumps having a piston that both rotates about its axis and contemporaneously slides axially and reciprocally within a liner or casing. With a full pump chamber, as the piston is rotated 360° about its axis, the piston slides axially through a dispense stroke and returns to its initial position after an intake or “fill” stroke. The combined 360° rotation and reciprocating axial movement of the piston produces a sinusoidal dispense profile illustrated in FIG. 1 . The line 1 graphically illustrates the flow rate at varying points during one revolution of the piston. The portion of the curve 1 above the horizontal line 2 representing a zero flow rate represents the dispense or output stroke while the portion of the curve 1 disposed below the line 2 represents the intake or fill stroke. Further, because the output is not linear (see the line 1 of FIG. 1 ), some users limit the operation of conventional nutating pumps to complete 360° revolutions of the piston or at least one full dispense stroke. However, this methodology often requires a user to choose between a small pump that requires multiple revolutions of the piston to dispense the required volume and a large pump that requires a partial revolution of the piston to dispense the required volume. Further, the operator may also have to choose between running the motor of a small pump at high speeds to dispense larger volumes and running the motor of a large pump at slow or minimum speeds for smaller volumes. To avoid this dilemma, stepper motors have been used with nutating pumps to provide a partial revolution dispense. While using a partial revolution to accurately dispense fluid from a nutating pump is difficult due to the non-linear output of the nutating pump dispense profile (i.e., see FIG. 1 ), controllers, software algorithms and sensors can be used to monitor the angular position of the piston. Using this angular position, the controller can calculate the number of steps required to achieve the desired output as disclosed in U.S. Pat. No. 6,749,402, which is incorporated herewith. The sinusoidal profile illustrated in FIG. 1 is based upon a nutating pump operating at a constant motor speed. While operating the nutating pump at a constant motor speed has its benefits in terms of simplicity of controller design and pump operation, the use of a constant motor speed has inherent disadvantages. Specifically, in certain applications, the maximum output flow rate illustrated on the left side of FIG. 1 can be disadvantageous because the output fluid may splash or splatter as the fluid is pumped into the output receptacle at the higher flow rates. For example, in paint or cosmetics dispensing applications, any splashing of the colorant as it is being pumped into the output container results in an inaccurate dispense as well as colorant being splashed on the machine, which requires labor-intensive clean up and maintenance. This splashing problem will adversely affect any nutating pump application where precise amounts of output fluid are being delivered to small receptacles or to output receptacles that are either full or partially full of liquid. For example, the operation of a conventional nutating pump having the profile of FIG. 1 results in pulsed output flow as shown in FIGS. 2 and 3 . The pulsed flow shown at the left in FIGS. 2 and 3 , at speeds of 800 and 600 rpm respectively, results in pulsations 3 and 4 , which are a cause of unwanted splashing. FIGS. 2 and 3 are renderings of actual digital photographs of an actual nutating pump in operation.

Invention Disclosure:
A tri-chamber nutating pump is disclosed which includes two pump chambers disposed within a pump housing that accommodates a nutating piston. A reciprocating compensating piston is also provided with its own compensating housing that is connected to the outlet. As a cumulative output from the first two pump chambers reaches its maximum level, the compensating piston is pushed into the outlet or through a passage to reduce the output of the first two chambers and avoid splashing. As the output from the first two chambers reaches its minimum level, the compensating piston is withdrawn from the outlet or through a passage thereby increasing the output of the third chamber to its maximum level when the output from the first two pump chambers reaches its minimum level.

[Assistant]
1. A nutating pump, comprising:
a nutating piston disposed in a pump housing, the pump housing comprising an inlet and an outlet, the pump housing further comprising a middle passage extending through the pump housing and intersecting the inlet and the outlet, the middle passage including a middle section disposed between the inlet and the outlet and a distal section disposed opposite the inlet from the outlet and terminating at an enclosure,
the nutating piston comprising a proximal section and a distal end with a pump section disposed therebetween, the pump section at least partially and slidably accommodated in the middle section of the middle passage with the pump section extending at least partially across the inlet to the distal section of the middle passage, the proximal section of the nutating piston extending at least partially across the outlet, the pump section of the nutating piston comprising a recess extending across at least part of the pump section to the distal end of the nutating piston,
the proximal section of the nutating piston having a first maximum outer diameter, the pump section of the nutating piston having a second maximum outer diameter that is greater than the first maximum outer diameter, the proximal section connected to the pump section at a transition section, the proximal section of the nutating piston coupled to a drive shaft,
the pump housing and the nutating piston defining two pump chambers including a first pump chamber and a second pump chamber, the first pump chamber defined by the distal end and the recess of the nutating piston and the distal section of the middle passage,
the second pump chamber defined by the transition section and a portion of the proximal section of the nutating piston that extends across the outlet of the pump housing and between the outer passage and the outlet,
the outlet in communication with a through passage of a compensating housing, the through passage extending past a compensating piston at a third pump chamber disposed in the through passage, the compensating piston being slidably and sealably accommodated in the compensating housing, the compensating piston including a distal end directed towards the through passage and a proximal end engaging a bearing, the bearing engaging a cam, the cam coupled to the drive shaft,
wherein rotation of the drive shaft causing rotation of the cam, which imparts reciprocating movement to the bearing and the nutating piston thereby causing reciprocating movement of the distal end of the nutating piston into and out of the through passage.

2. The nutating pump of claim 1 wherein the middle passage of the pump housing extends at least substantially perpendicular to the inlet and the outlet and the outer passage of the pump housing extends at least substantially parallel to the middle passage.

3. The nutating pump of claim 1 wherein the outlet of the pump housing is connected to an outlet housing disposed between the outlet and the compensating housing, the outlet housing having an outlet passage providing communication between the outlet and the through passage.

4. The nutating pump of claim 1 wherein the compensating piston is slidably accommodated in a liner, the liner having a distal end facing the through passage of the compensating housing and a proximal end engaging a primary seal for inhibiting leakage between the compensating piston and the liner.

5. The nutating pump of claim 4 wherein the primary seal is annular and has an outer periphery, the outer periphery comprising a slot for accommodating an O-ring, the O-ring sandwiched between the outer periphery of the seal and a seal retainer, the seal retainer including a proximal end with an opening through which the compensating piston passes, the proximal end connected to a distal end by a continuous sidewall, the distal end of the seal retainer being biased against the compensating housing by a spring, the spring also biasing the proximal end of the compensating piston against the bearing.

6. The nutating pump of claim 1 wherein the cam, the compensating piston and the nutating piston are arranged so that when a cumulative output from the first and second pump chambers is at a maximum, a compensating output from the third pump chamber is at a minimum.

7. The nutating pump of claim 1 wherein the cam, the compensating piston and the nutating piston are arranged so that when a cumulative output from the first and second pump chambers is at a minimum, a compensating output from the third pump chamber is at a maximum.

8. The nutating pump of claim 1 wherein the drive shaft is coupled to a stepper motor.

9. The nutating pump of claim 1 wherein the pump housing and the compensating housing are molded from a plastic material.

10. A method for providing a steady state output flow from a nutating pump that is operating at a constant motor speed, the method comprising:
providing a nutating pump with a first pump chamber, a second pump chamber, and a nutating piston, the first pump chamber producing a first output in response to a first 180° of rotation of the nutating piston, the second pump chamber producing a second output in response to a second 180° of rotation of the nutating piston, the nutating pump including an outlet,
providing a compensating piston with a distal end that faces the outlet when the compensating piston is in a retracted position and that extends into the outlet when the compensating piston is in an extended position,
extending the compensating piston into the outlet when a cumulative output from the first and second pump chambers approaches a maximum level, and
retracting the compensating piston from the outlet when the cumulative output from the first and second pump chambers approaches a minimum level.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Semiconductor Device Having Reduced Drain-To-Source Capacitance

Technical Field and Background:
For various semiconductor devices, such as radio frequency (“RF”) switches in bulk silicon or semiconductor on insulator (“SOI”) structures, power loss and switching speed are two important parameters related to device performance. Power loss is determined, in part, by an on-state resistance (Ron) of the semiconductor device, while switching speed is determined, in part, by an off-state capacitance (Coff) of the semiconductor device. The on-state resistance includes the drain-to-source resistance of the semiconductor device in an on state, which partially depends on the resistance of the drain and source metals (e.g., source and drain electrodes) and the device layout area. The off-state capacitance includes the drain-to-source capacitance of the semiconductor device in an off state, which may be attributed to an off-state parasitic coupling between the drain and source metals. It is desirable for a semiconductor device, such as an RF switch, to have a low on-state resistance to reduce power loss, and a low off-state capacitance to improve switching speed. However, there is a trade-off between the two parameters. For example, the on-state resistance can be reduced by increasing the width of the source and drain metals, but the off-state capacitance can also be adversely increased due to the greater metalization width and device layout area. Accordingly, there is a need to provide a semiconductor device, such as an RF switch, with a reduced drain-to-source capacitance without substantially compromising the on-state resistance of the semiconductor device.

Invention Disclosure:
A semiconductor device includes a source finger electrode coupled to a source region in a semiconductor die, a drain finger electrode coupled to a drain region in the semiconductor die, where the source finger electrode includes at least one isolated segment and a main segment having a first portion and a second portion narrower than the first portion, whereby the source finger electrode reduces a drain-to-source capacitance of the semiconductor device. A common source rail is electrically coupled to the at least one isolated segment and the main segment of the source finger electrode. The drain fmger electrode includes at least one isolated segment and a main segment having a first portion and a second portion narrower than the first portion. A common drain rail is electrically coupled to the at least one isolated segment and the main segment of the drain finger electrode.

[Assistant]
1. A semiconductor device comprising:
a source region in a semiconductor die;
a drain region in said semiconductor die;
a source finger electrode located over the source region, wherein said source finger electrode comprises at least one isolated segment and a main segment having a first portion and a second portion that is narrower than said first portion, wherein the at least one isolated segment and the main segment of the source finger electrode are physically separated segments of a first metal layer; and
a plurality of source contacts that electrically couple the at least one isolated segment and the main segment of the source finger electrode to the source region.

2. The semiconductor device of claim 1 further comprising:
a common source rail located over the source finger electrode in a second metal layer; and
a plurality of conductive vias that electrically couple the at least one isolated segment and the main segment of the source finger electrode to the common source rail.

3. The semiconductor device of claim 2, wherein the common source rail extends over the isolated segments and the first portion of the main segment, but not the second portion of the main segment.

4. The semiconductor device of claim 3, wherein the common source rail extends approximately halfway across the source finger electrode.

5. The semiconductor device of claim 2, wherein the common source rail has the first width.

6. The semiconductor device of claim 1 further comprising:
a drain finger electrode located over the drain region, wherein said drain finger electrode comprises at least one isolated segment and a main segment having a first portion and a second portion that is narrower than said first portion, wherein the main segment of the drain finger electrode and the at least one isolated segment of the drain finger electrode are physically separated segments of the first metal layer; and
a plurality of drain contacts that electrically couple the at least one isolated segment of the drain finger electrode and the main segment of the drain finger electrode to the drain region.

7. The semiconductor device of claim 6 further comprising:
a common drain rail located over the drain finger electrode in a second metal layer; and
a plurality of conductive vias that electrically couple the at least one isolated segment of the drain finger electrode and the main segment of the drain finger electrode to the common drain rail.

8. The semiconductor device of claim 6 further comprising:
a gate located between the source region and the drain region;
wherein said second portion of said main segment of said drain finger electrode is laid out across the gate from said at least one isolated segment of said source finger electrode.

9. The semiconductor device of claim 8, wherein said second portion of the main segment of the source finger electrode is laid out across the gate from said at least one isolated segment of said drain finger electrode.

10. The semiconductor device of claim 1, wherein the at least one isolated segment has the first width.

11. The semiconductor device of claim 1, wherein the isolated segment has a first length, the first portion of the main segment has a second length and the second portion of the main segment has a third length, wherein the first, second and third lengths are approximately equal.

12. The semiconductor device of claim 1, wherein the first portion of the main segment is located between the second portion of the main segment and the at least one isolated segment.

13. A transistor comprising:
a plurality of source regions and a plurality of drain regions in a semiconductor die;
source finger electrodes electrically coupled to the source regions and interdigitated with drain finger electrodes electrically coupled to the source regions;
wherein at least one of said source finger electrodes includes at least one isolated source finger electrode segment and a main source finger electrode segment, which are physically separated segments of a first metal layer; and
wherein at least one of said drain finger electrodes includes at least one isolated drain finger electrode segment and a main drain finger electrode segment, which are physically separated segments of the first metal layer.

14. The transistor of claim 13, wherein said main source finger electrode segment comprises a first portion and a second portion narrower than said first portion.

15. The transistor of claim 13 wherein said main drain finger electrode segment comprises a first portion and a second portion narrower than said first portion.

16. The transistor of claim 15 wherein said second portion of said main drain finger electrode segment is laid out across from said at least one isolated source finger electrode segment.

17. The transistor of claim 13 wherein a common source rail is electrically coupled to said at least one isolated source finger electrode segment through conductive vias.

18. The transistor of claim 17 wherein the common source rail is formed in a metal two (M 2 ) layer.

19. The transistor of claim 17 wherein a common drain rail is electrically coupled to said at least one isolated drain finger electrode segment through conductive vias.

20. The transistor of claim 19 wherein the common source rail and the common drain rail are formed in a metal two (M 2 ) layer.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Method For Performing Adaptive Input Current Control In An Electronic Device With Aid Of Adaptor Management, And Associated Apparatus

Technical Field and Background:
The present invention relates to regulating control (e.g. charger control) in a portable electronic device, and more particularly, to a method for performing adaptive input current control in an electronic device, and an associated apparatus. According to the related art, a conventional regulating control circuit in a conventional portable electronic device may be designed to prevent some problems such as system crash caused by insufficient power of a conventional external power source (e.g. an alternating current (AC)-to-direct current (DC) adaptor). However, further problems such as some side effects may occur. For example, a conventional regulator of the conventional portable electronic device may be arranged for regulating the voltage and the current obtained from the conventional external power source, and in an initial time period (e.g. the conventional external power source is just connected to the conventional portable electronic device), the conventional charger control circuit may adjust the input current setting of the conventional regulator from low to high, to make the input current of the conventional regulator increase with various steps, which typically limits the power to a conventional system circuit of the conventional portable electronic device and limits the power to a battery of the conventional portable electronic device during the initial time period. Thus, the conventional portable electronic device may suffer from limited power-outputting capability during the initial time period. In addition, as this conventional charger control circuit may adjust the input current setting of the conventional regulator from low to high, to make the input voltage of the conventional regulator decrease and temporarily become lower than a power source collapse level before an optimized current level can be achieved, the conventional external power source may crash during operations of the conventional portable electronic device, which may cause unstable system power of the conventional portable electronic device. Thus, a novel architecture is required to improve regulating control of electronic devices, in order to guarantee the overall performance of the electronic devices.

Invention Disclosure:
A method and apparatus for performing adaptive input current control in an electronic device are provided, where the method may include the steps of: before limiting an input current of a regulator of the electronic device to a target current value, monitoring the input current of the regulator according to a reference current, and decreasing the reference current, to make the reference current change starting from one of a plurality of predetermined reference current values, wherein the input current is obtained from a power source; detecting an input voltage of the regulator to generate a detection signal, to selectively trigger limiting output power of the regulator; and at a time point when the reference current becomes smaller than the input current, limiting the input current of the regulator to the target current value with a latest reference current value of the reference current being utilized as the target current value.

[Assistant]
1. A method for performing adaptive input current control in an electronic device, the method comprising steps of:
in a first time period, monitoring the input current of the regulator according to a reference signal corresponding to a reference current, and decreasing the reference current by decreasing magnitude of the reference signal corresponding to the reference current, to make the reference current change starting from one of a plurality of predetermined reference current values, wherein the input current of the regulator is obtained from a power source, wherein the input current of the regulator is not limited to the reference current in the first time period;
detecting an input voltage of the regulator to generate a detection signal corresponding to the input voltage of the regulator, to selectively trigger limiting output power of the regulator, wherein limiting the output power of the regulator is selectively triggered according to the detection signal; and
at a time point when a monitoring result indicates that the reference current becomes smaller than the input current of the regulator, limiting the input current of the regulator in a second time period to the target current value with a latest reference current value of the reference current being utilized as the target current value, wherein the monitoring result is generated from monitoring the input current of the regulator, wherein the second time period is after the first time period.

2. The method of claim 1, wherein the one of the plurality of predetermined reference current values is greater than a maximum current available from the power source; and the method further comprises:
allowing, in the first time period, the input current of the regulator to reach the maximum current available from the power source.

3. The method of claim 1, wherein the step of detecting the input voltage of the regulator to generate the detection signal corresponding to the input voltage of the regulator to selectively trigger limiting the output power of the regulator further comprises:
detecting the input voltage of the regulator to generate the detection signal corresponding to the input voltage of the regulator, to selectively trigger limiting the output power of the regulator, in order to prevent collapse of the input voltage of the regulator that is obtained from the power source.

4. The method of claim 1, further comprising:
according to a digital version of the detection signal, selectively triggering limiting the input current of the regulator to the target current value.

5. The method of claim 4, wherein the step of selectively triggering limiting the input current of the regulator to the target current value further comprises:
before the digital version of the detection signal transits from a first logical state to a second logical state, preventing triggering limiting the input current of the regulator to the target current value.

6. The method of claim 5, wherein the step of selectively triggering limiting the input current of the regulator to the target current value further comprises:
when the digital version of the detection signal transits from the first logical state to the second logical state, triggering limiting the input current of the regulator to the target current value.

7. The method of claim 1, wherein the step of decreasing the reference current to make the reference current change starting from the one of the plurality of predetermined reference current values further comprises:
before the detection signal transits from a first state to a second state, keeping decreasing the reference current.

8. The method of claim 7, wherein the step of decreasing the reference current to make the reference current change starting from the one of the plurality of predetermined reference current values further comprises:
when the detection signal transits from the second state to the first state, stopping decreasing the reference current, to utilize the latest reference current value of the reference current as the target current value.

9. The method of claim 1, wherein an error control circuit is arranged for performing error control during limiting the input current of the regulator to the target current value, and comprises a first error amplifier; and the first error amplifier has a monitoring input terminal and a reference input terminal, wherein the monitoring input terminal of the first error amplifier is arranged for inputting a monitoring signal corresponding to the input current of the regulator, and the reference input terminal of the first error amplifier is arranged for inputting the reference signal corresponding to the reference current.

10. The method of claim 1, wherein a voltage monitoring circuit is arranged for detecting the input voltage of the regulator to generate the detection signal corresponding to the input voltage of the regulator, and comprises a second error amplifier; and the second error amplifier has a monitoring input terminal and a reference input terminal, wherein the monitoring input terminal of the second error amplifier is arranged for inputting the input voltage of the regulator or a derivative thereof, and the reference input terminal of the second error amplifier is arranged for inputting a reference signal corresponding to a predetermined voltage level.

11. An apparatus for performing adaptive input current control in an electronic device, the apparatus comprising:
a regulator, positioned in the electronic device, arranged for performing regulation for the electronic device;
an error control circuit, positioned in the electronic device and coupled to the regulator, arranged for performing error control during limiting an input current of the regulator to a target current value, wherein the input current of the regulator is obtained from a power source;
a voltage monitoring circuit, positioned in the electronic device and coupled to the regulator, arranged for detecting an input voltage of the regulator to generate a detection signal corresponding to the input voltage of the regulator; and
a management circuit, positioned in the electronic device and coupled to the regulator, the error control circuit, and the voltage monitoring circuit, arranged for managing the regulator, wherein the management circuit monitors, in a first time period, by utilizing the error control circuit, the input current of the regulator according to a reference signal corresponding to a reference current, and decreases the reference current by decreasing magnitude of the reference signal corresponding to the reference current, to make the reference current change starting from one of a plurality of predetermined reference current values, wherein the input current of the regulator is not limited to the reference current in the first time period, wherein according to the detection signal, the management circuit selectively triggers limiting output power of the regulator, and at a time point when a monitoring result indicates that the reference current becomes smaller than the input current of the regulator, the management circuit limits, in a second time period, by utilizing the error control circuit, the input current of the regulator to the target current value with a latest reference current value of the reference current being utilized as the target current value, wherein the monitoring result is generated from monitoring the input current of the regulator wherein the second time period is after the first time period.

12. The apparatus of claim 11, wherein the one of the plurality of predetermined reference current values is greater than a maximum current available from the power source; and the management circuit allows, in the first time period, the input current of the regulator to reach the maximum current available from the power source.

13. The apparatus of claim 11, wherein according to the detection signal, the management circuit selectively triggers limiting the output power of the regulator, in order to prevent collapse of the input voltage of the regulator that is obtained from the power source.

14. The apparatus of claim 11, wherein according to a digital version of the detection signal, the management circuit selectively triggers limiting the input current of the regulator to the target current value.

15. The apparatus of claim 14, wherein before the digital version of the detection signal transits from a first logical state to a second logical state, the management circuit prevents triggering limiting the input current of the regulator to the target current value.

16. The apparatus of claim 15, wherein when the digital version of the detection signal transits from the first logical state to the second logical state, the management circuit triggers limiting the input current of the regulator to the target current value.

17. The apparatus of claim 11, wherein before the detection signal transits from a first state to a second state, the management circuit keeps decreasing the reference current.

18. The apparatus of claim 17, wherein when the detection signal transits from the second state to the first state, the management circuit stops decreasing the reference current, to utilize the latest reference current value of the reference current as the target current value.

19. The apparatus of claim 11, wherein the error control circuit comprises a first error amplifier; and the first error amplifier has a monitoring input terminal and a reference input terminal, wherein the monitoring input terminal of the first error amplifier is arranged for inputting a monitoring signal corresponding to the input current of the regulator, and the reference input terminal of the first error amplifier is arranged for inputting the reference signal corresponding to the reference current.

20. The apparatus of claim 19, wherein the voltage monitoring circuit comprises a second error amplifier; and the second error amplifier has a monitoring input terminal and a reference input terminal, wherein the monitoring input terminal of the second error amplifier is arranged for inputting the input voltage of the regulator or a derivative thereof, and the reference input terminal of the second error amplifier is arranged for inputting a reference signal corresponding to a predetermined voltage level.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Modular Point-Of-Care Devices, Systems, And Uses Thereof

Technical Field and Background:
The discovery of a vast number of disease biomarkers and the establishment of miniaturized medical systems have opened up new avenues for the prediction, diagnosis and monitoring of treatment of diseases in a point-of-care setting. Point-of-care systems can rapidly deliver test results to medical personnel, other medical professionals and patients. Early diagnosis of a disease or disease progression can allow medical personnel to begin or modify therapy in a timely manner. Multiplexed biomarker measurement can provide additional knowledge of the condition of a patient. For example, when monitoring the effects of a drug, three or more biomarkers can be measured in parallel. Typically, microtiter plates and other similar apparatuses have been used to perform multiplexed separation-based assays. A microtiter plate (for example, a 384 well microtiter plate) can perform a large number of assays in parallel. In a Point-of-Care (POC) device, the number of assays that can be performed in parallel is often limited by the size of the device and the volume of the sample to be analyzed. In many POC devices, the number assays performed is about 2 to 10. A POC device capable of performing multiplexed assays on a small sample would be desirable. A shortcoming of many multiplexed POC assay devices is the high cost of manufacturing the components of the device. If the device is disposable, the high cost of the components can make the manufacturing of a POC device impractical. Further, for multiplexed POC devices that incorporate all of the necessary reagents onboard of the device, if any one of those reagents exhibit instability, an entire manufactured lot of devices may have to be discarded even if all the other reagents are still usable. When a customer is interested in a customizing a POC device to a particular set of analytes, manufacturers of multiplexed POC assay systems are often confronted with a need to mix-and-match the assays and reagents of the device. A multiplexed POC assay suitable to each customer can be very expensive, difficult to calibrate, and difficult to maintain quality control. POC methods have proven to be very valuable in monitoring disease and therapy (for example, blood glucose systems in diabetes therapy, Prothrombin Time measurement in anticoagulant therapy using Warfarin). By measuring multiple markers, it is believed that complex diseases (such as cancer) and therapies such as multi-drug therapy for cancer can be better monitored and controlled.

Invention Disclosure:
The present invention provides devices and systems for use at the point of care. The methods devices of the invention are directed toward automatic detection of analytes in a bodily fluid. The components of the device are modular to allow for flexibility and robustness of use with the disclosed methods for a variety of medical applications.

[Assistant]
1. A method of detecting at least two analytes present in a sample, the method comprising:
positioning a cartridge in an instrument, wherein the cartridge comprises:
a sample vessel, a plurality of reagent units, a plurality of assay units, and at least one pipette tip;
processing the sample to provide processed sample portions in selected assay units of the cartridge; and
removing at least one of said selected assay units from the cartridge and transporting said at least one of said selected assay units to a signal detector at a different location in the instrument;
wherein the cartridge contains all reagents and supplies for said detection of said at least two analytes.

2. The method of claim 1, wherein said cartridge is positioned in the instrument effective that an automated fluid transfer device of the instrument can engage at least one sample vessel, one of said reagent units, one of said assay units, or at least one pipette tip.

3. The method of claim 1, wherein at least one of said assay units comprises a pipette tip with a capture surface.

4. The method of claim 1, wherein at least one of said assay units comprises a pipette tip with a reaction site.

5. The method of claim 1, wherein the cartridge further comprises a housing for holding said reagent units and said assay units.

6. The method of claim 1, wherein the reagent units comprise instrument-operable containers that encapsulate liquid reagents.

7. The method of claim 1, wherein said reagents include liquid-phase and solid-phase reagents.

8. The method of claim 1 further comprising performing serial dilution on the sample, wherein a second diluted portion is formed from a first diluted portion.

9. The method of claim 1 further comprising using fingerstick blood from a single subject as the sample.

10. The method of claim 1 wherein the cartridge further comprises a housing, wherein a bottom of the housing is configured to collect waste liquids.

11. The method of claim 1 wherein the cartridge is configured to collect waste liquids after use that are transferred through a hole in a housing of the cartridge.

12. The method of claim 2, wherein said processing of the sample comprises transferring sample and diluent to one of the assay units using the fluid transfer device.

13. The method of claim 12, wherein the fluid transfer device is automated to follow a protocol associated with the cartridge to perform serial dilution of the sample.

14. The method of claim 12, wherein the fluid transfer device is automated to follow a protocol associated with a cartridge identifier that is associated with a subject.

15. The method of claim 1, further comprising expelling processed sample from the assay units and storing such expelled processed sample in the cartridge.

16. The method of claim 1, further comprising a touch-off absorber positioned on the cartridge in a plane different from at least some cavity openings on the cartridge.

17. The method of claim 14, further comprising using the fluid transfer device to perform an automated process carried out by a user-defined protocol.

18. The method of claim 14, wherein processing, diluting, removing, and detecting steps all occur within the instrument.

19. The method of claim 18, wherein the instrument is at a point-of-care (POC) location.

20. The method of claim 19, wherein said point-of-care (POC) location is a pharmacy.

21. The method of claim 19 further comprising sending data from the instrument in an encrypted format over a public network to a server comprising a network interface and a processor, wherein the server processes the data and then sends assay results over the public network to a user station display.

22. The method of claim 1, wherein said instrument comprises a translational stage for receiving said cartridge.

23. The method of claim 2, wherein said automated fluid transfer device comprises part of a bench-top instrument.

24. The method of claim 1, wherein said sample has a volume of between about 1 μL to about 100 μL.

25. The method of claim 1, further comprising obtaining said sample by lancing a subject to obtain a fingerstick blood sample.

26. The method of claim 2, wherein the automated fluid transfer device comprises a motor in communication with a programmable processor, wherein the motor can move a pipette head of the fluid transfer device based on a protocol from said programmable processor to change a sequence for transporting assay units and reagent units.

27. The method of claim 1, wherein the instrument is configured to automatically receive and process a whole blood sample to yield a plasma portion.

28. The method of claim 1, wherein cartridge identifier information is used to determine automated fluid transfer device movement.

29. The method of claim 1, wherein the cartridge further comprises a beads well.

30. The method of claim 1 wherein the sample vessel, the plurality of reagent units, the plurality of assay units, and the at least one pipette tip are all arranged in the cartridge in a two-dimensional configuration and not together in a single row.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Display Substrate And Driving Method Thereof As Well As Display Apparatus

Technical Field and Background:
A conventional display apparatus performs display by forming one pixel from sub-pixels of three colors: red, green and blue (RGB). In a practical application, a resolution of the display apparatus may be increased by increasing pixels per inch (abbreviated PPI) on the display apparatus. At present, RG/BG is a frequently-used pixel arrangement for realizing a high resolution by using fewer sub-pixels. However, with an increasing requirement for a resolution of the display apparatus, such a RG/BG sub-pixel arrangement faces a greater challenge. To increase the resolution of the display apparatus, it is necessary to increase the number of sub-pixels, which may cause problems such as large fabrication difficulty of the display apparatus, high cost and the like.

Invention Disclosure:
A display substrate and a driving method thereof as well as a display apparatus. The display substrate comprises pixel groups which are arranged repeatedly, each pixel group comprising a first sub-pixel group and a second sub-pixel group, each comprising four pixel columns. The present invention reduces the number of sub-pixels in the whole display apparatus. Therefore, on a premise of ensuring that the display apparatus achieves a relatively high resolution, the fabrication difficulty of the display apparatus is reduced, and the cost is lowered.

[Assistant]
1. A display substrate, comprising pixel groups which are arranged repeatedly, each pixel group comprising a first sub-pixel group and a second sub-pixel group, and said first sub-pixel group and said second sub-pixel ground both comprising four sub-pixel columns; wherein
two first sub-pixels which are sequentially arranged are disposed in a first sub-pixel column of said first sub-pixel group, one second sub-pixel is disposed in a second sub-pixel column of said first sub-pixel group, one third sub-pixel is disposed in a third sub-pixel column-in said first sub-pixel group, and two second sub-pixels which are sequentially arranged are disposed in a fourth sub-pixel column of said first sub-pixel group, wherein said second sub-pixel in said second sub-pixel column corresponds to said two first sub-pixels in said first pixel column, and said third sub-pixel in said third sub-pixel column corresponds to said two second sub-pixels in said fourth pixel column; and
one third sub-pixel is disposed in a first sub-pixel column of said second sub-pixel group, two second sub-pixels which are sequentially arranged are disposed in a second sub-pixel column of said second sub-pixel group, two first sub-pixels which are sequentially arranged are disposed in a third sub-pixel column of said second sub-pixel group, and one second sub-pixel is disposed in a fourth sub-pixel column of said second sub-pixel group, wherein said third sub-pixel in said first sub-pixel column corresponds to said two second sub-pixels in said second pixel column, and said second sub-pixel in said fourth sub-pixel column corresponds to said two first sub-pixels in said third pixel column
wherein in said first sub-pixel group, a light emitting center of said second sub-pixel in said second sub-pixel column and a midpoint of a connecting line between light emitting centers of said two first sub-pixels in said first sub-pixel column are located on the same straight line in a row direction, and a light emitting center of said third sub-pixel in said third sub-pixel column and a midpoint of a connecting line between light emitting centers of said two second sub-pixels in said fourth sub-pixel column are located on the same straight line in a row direction; and
wherein in said second sub-pixel group, a light emitting center of said third sub-pixel in said first sub-pixel column and a midpoint of a connecting line between light emitting centers of said two second sub-pixels in said second sub-pixel column are located on the same straight line in a row direction, and a light emitting center of said second sub-pixel in said fourth sub-pixel column and a midpoint of a connecting line between light emitting centers of said two first sub-pixels in said third sub-pixel column are located on the same straight line in a row direction.

2. The display substrate according to claim 1, wherein said first sub-pixel group and said second sub-pixel group are disposed in an overlying relation, and wherein individual sub-pixel columns in said first sub-pixel group are disposed corresponding to individual sub-pixel columns in said second sub-pixel group.

3. A display apparatus, comprising the display substrate according to claim 2.

4. The display substrate according to claim 1, wherein in said first sub-pixel group, said second sub-pixel in said second pixel column, and said third sub-pixel in said third sub-pixel column are located in the same pixel row.

5. A display apparatus, comprising the display substrate according to claim 4.

6. The display substrate according to claim 1, wherein in said second sub-pixel group, said third sub-pixel in said first sub-pixel column and said second sub-pixel in said fourth sub-pixel column are located in the same pixel row.

7. A display apparatus, comprising the display substrate according to claim 6.

8. A display apparatus, comprising the display substrate according to claim 1.

9. A method for driving the display substrate according to claim 1, comprising:
according to input values for corresponding sub-pixels in said first sub-pixel group, respectively generating output values for said two first sub-pixels in said first pixel column, an output value for said one second sub-pixel in said second pixel column, an output value for said one third sub-pixel in said third sub-pixel column and output values for said two second sub-pixels in said fourth pixel column;
respectively outputting said output values for said two first sub-pixels in said first pixel column, said output value for said one second sub-pixel in said second pixel column, said output value for said one third sub-pixel in said third sub-pixel column and said output values for said two second sub-pixels in said fourth pixel column, which are generated as above;
according to input values for corresponding sub-pixels in said second sub-pixel group, respectively generating an output value for said one third sub-pixel in said first pixel column, output values for said two second sub-pixels in said second pixel column, output values for said two first sub-pixels in said third pixel column, and an output value for said one second sub-pixel in said fourth pixel column; and
respectively outputting said output value for said one third sub-pixel in said first pixel column, said output values for said two second sub-pixels in said second pixel column, said output values for said two first sub-pixels in said third pixel column, and said output value for said one second sub-pixel in said fourth pixel column, which are generated as above.

10. The method according to claim 9, wherein the step of, according to input values for corresponding sub-pixels in said first sub-pixel group, respectively generating output values for said two first sub-pixels in said first pixel column, an output value for said one second sub-pixel in said second pixel column, an output value for said one third sub-pixel in said third sub-pixel column and output values for said two second sub-pixels in said fourth pixel column, comprises:
according to two first sub-pixel input values corresponding to each first sub-pixel in said first sub-pixel column of said first sub-pixel group, generating an output value for each first sub-pixel in said first pixel column;
according to two second sub-pixel input values corresponding to said second sub-pixel in said second sub-pixel column of said first sub-pixel group, generating an output value for said second sub-pixel in said second pixel column;
according to four third sub-pixel input values corresponding to said third sub-pixel in said third sub-pixel column of said first sub-pixel group, generating an output value for said third sub-pixel in said third pixel column; and
according to a second sub-pixel input value corresponding to each second sub-pixel in said fourth sub-pixel column of said first sub-pixel group, generating an output value for each second sub-pixel in said fourth pixel column.

11. The method according to claim 10, wherein
the step of, according to two first sub-pixel input values corresponding to each first sub-pixel in said first sub-pixel column of said first sub-pixel group, generating an output value for each first sub-pixel in said first pixel column, comprises: by dividing a sum of two first sub-pixel input values corresponding to each first sub-pixel in said first sub-pixel column of said first sub-pixel group by two, generating an output value for each first sub-pixel in said first pixel column;
the step of, according to two second sub-pixel input values corresponding to said second sub-pixel in said second sub-pixel column of said first sub-pixel group, generating an output value for said second sub-pixel in said second pixel column, comprises: by dividing a sum of two second sub-pixel input values corresponding to said second sub-pixel in said second sub-pixel column of said first sub-pixel group by two, generating an output value for said second sub-pixel in said second pixel column;
the step of, according to four third sub-pixel input values corresponding to said third sub-pixel in said third sub-pixel column of said first sub-pixel group, generating an output value for said third sub-pixel in said third pixel column, comprises: by dividing a sum of the four third sub-pixel input values corresponding to said third sub-pixel in said third sub-pixel column of said first sub-pixel group by four, generating an output value for said third sub-pixel in said third pixel column; and
the step of, according to a second sub-pixel input value corresponding to each second sub-pixel in said fourth sub-pixel column of said first sub-pixel group, generating an output value for each second sub-pixel in said fourth pixel column, comprises: setting a second sub-pixel input value corresponding to each second sub-pixel in said fourth sub-pixel column of said first sub-pixel group to an output value for each second sub-pixel in said fourth pixel column.

12. The method according to claim 9, wherein the step of, according to input values for corresponding sub-pixels in said second sub-pixel group, respectively generating an output value for said one third sub-pixel in said first pixel column, output values for said two second sub-pixels in said second pixel column, output values for said two first sub-pixels in said third pixel column, and an output value for said one second sub-pixel in said fourth pixel column, comprises:
according to four third sub-pixel input values corresponding to said third sub-pixel in said first sub-pixel column of said second sub-pixel group, generating an output value for said third sub-pixel in said first pixel column;
according to a second sub-pixel input value corresponding to each second sub-pixel in said second sub-pixel column of said second sub-pixel group, generating an output value for each second sub-pixel in said second pixel column;
according to two first sub-pixel input values corresponding to each first sub-pixel in said third sub-pixel column of said second sub-pixel group, generating an output value for each first sub-pixel in said third pixel column; and
according to two second sub-pixel input values corresponding to said second sub-pixel in said fourth sub-pixel column of said second sub-pixel group, generating an output value for said second sub-pixel in said fourth pixel column.

13. The method according to claim 12, wherein
the step of, according to four third sub-pixel input values corresponding to said third sub-pixel in said first sub-pixel column of said second sub-pixel group, generating an output value for said third sub-pixel in said first pixel column, comprises: by dividing a sum of four third sub-pixel input values corresponding to said third sub-pixel in said first sub-pixel column of said second sub-pixel group by four, generating an output value for said third sub-pixel in said first pixel column;
the step of, according to a second sub-pixel input value corresponding to each second sub-pixel in said second sub-pixel column of said second sub-pixel group, generating an output value for each second sub-pixel in said second pixel column, comprises: setting a second sub-pixel input value corresponding to each second sub-pixel in said second sub-pixel column of said second sub-pixel group to an output value for each second sub-pixel in said second pixel column;
the step of, according to two first sub-pixel input values corresponding to each first sub-pixel in said third sub-pixel column of said second sub-pixel group, generating an output value for each first sub-pixel in said third pixel column, comprises: by dividing a sum of two first sub-pixel input values corresponding to each first sub-pixel in said third of said second sub-pixel group by two, generating an output value for each first sub-pixel in said third pixel column; and
the step of, according to two second sub-pixel input values corresponding to said second sub-pixel in said fourth sub-pixel column of said second sub-pixel group, generating an output value for said second sub-pixel in said fourth pixel column, comprises: by dividing a sum of two second sub-pixel input values corresponding to said second sub-pixel in said fourth sub-pixel column of said second sub-pixel group by two, generating an output value for said second sub-pixel in said fourth pixel column.


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[User]
Title: Combat Medical Simulators And Associated Systems And Methods

Technical Field and Background:
As medical science has progressed, it has become increasingly important to provide non-human interactive formats for teaching patient care. Non-human interactive devices and systems can be used to teach the skills needed to successfully identify and treat various patient conditions without putting actual patients at risk. Such training devices and systems can be used by medical personnel and medical students to learn the techniques required for proper patient care, including those techniques used in war or combat zones where time is often of the essence in successful to both patient and medical personnel survival. In that regard, the training of medical personnel and patients is greatly enhanced through the use of realistic hands-on training with devices and systems, such as those of the present disclosure, that mimic characteristics of natural human and, in particular, allow training of procedures commonly performed in war and/or combat zones. In view of the foregoing, there remains a need for devices, systems, and methods appropriate for use in combat medical training.

Invention Disclosure:
Devices, systems, and methods appropriate for use in combat medical training are provided. In some instances, the combat medical simulators facilitate training of common field medical techniques including tracheostomy, wound care, tourniquet use, pneumothorax, cardiopulmonary resuscitation, and/or other medical treatments. Further, the combat medical simulators have joints that provide realistic ranges of motions to enhance the realism of the training experience.

[Assistant]
1. A combat medical simulation system, comprising:
a patient simulator including:
a wound formed on a limb of the patient simulator, the wound comprising a foam layer;
a fluid reservoir positioned within the patient simulator, the fluid reservoir in fluid communication with the foam layer of the wound via flexible tubing; and
a pump system in communication with the fluid reservoir for selectively simulating bleeding of the wound by pumping fluid from the fluid reservoir to the wound through the flexible tubing;
wherein proper application of a tourniquet around the limb of the patient simulator stops fluid flow through the flexible tubing to the wound.

2. The system of claim 1, wherein the patient simulator is operable without physical connection to an external device.

3. The system of claim 2, wherein the patient simulator is configured to wirelessly communicate with one or more external devices.

4. The system of claim 3, wherein the patient simulator receives control signals wirelessly from the one or more external devices.

5. The system of claim 2, wherein the patient simulator includes a rechargeable power supply.

6. The system of claim 1, wherein the wound is formed on an arm of the patient simulator.

7. The system of claim 1, wherein the wound is formed on a leg of the patient simulator.

8. The system of claim 1, wherein the wound is formed of a material having a hardness between 30 on the 00 scale and 10 on the A scale of the Rockwell hardness standard.

9. The system of claim 1, wherein the wound includes a porous layer adjacent to the foam layer to disperse fluid to simulate a hemorrhaging effect.

10. The system of claim 9, wherein the limb of the patient simulator has a cavity, in which the wound is housed, the wound further comprising a housing adjacent to the foam layer and opposite the porous layer, the housing being substantially non-porous so as to prevent or at least reduce fluid leakage into the limb of the patient simulator.

11. The system of claim 1, wherein proper application of a tourniquet around the limb of the patient simulator stops the flow of fluid through the flexible tubing to the wound by compressing the tubing to prevent fluid flow.

12. The system of claim 1, wherein proper application of a tourniquet around the limb of the patient simulator stops the flow of fluid through the flexible tubing to the wound by triggering a sensor that deactivates the pump.

13. The system of claim 1, wherein the wound is configured to accept packing material such that applying pressure to the wound with packing material stops the simulated bleeding of the wound.

14. The system of claim 13, further comprising a sensor that detects the application of pressure on the wound.

15. The system of claim 14, wherein the sensor sends a control signal to the pump to stop pumping fluid from the fluid reservoir to the wound when application of an appropriate amount of pressure is detected.

16. The system of claim 1, wherein, to simulate the bleeding of the wound, the fluid is pumped through the flexible tubing to the wound at a rate of approximately 0.25 liters per minute.

17. The system of claim 1, wherein the fluid reservoir is positioned within a leg of the patient simulator.

18. The system of claim 1, further comprising a sensor operably coupled to the fluid reservoir to monitor the amount of the fluid present in the fluid reservoir so that a user or instructor can replenish the fluid in the fluid reservoir as necessary.

19. The system of claim 18, wherein the sensor monitors the amount of the fluid present in the fluid reservoir by monitoring changes in weight and/or pressure imparted on the sensor by the fluid reservoir.

20. A combat medical simulation system, comprising:
a patient simulator sized and shaped to simulate an adult male, the patient simulator including:
a wound formed on a limb of the patient simulator;
a fluid reservoir positioned within the patient simulator, the fluid reservoir in fluid communication with the wound via flexible tubing; and
a pump system in communication with the fluid reservoir for selectively simulating bleeding of the wound by pumping fluid from the fluid reservoir to the wound through the flexible tubing; and
wherein proper application of a tourniquet around the limb of the patient simulator stops the flow of fluid through the flexible tubing to the wound; and
a pneumothorax simulation system positioned within a torso of the patient simulator, wherein the pneumothorax simulation system includes:
a moveable contact plate; and
a switch;
wherein a state of the switch is modified in response to movement of the contact plate resulting from a needle contacting the moveable contact plate.

21. The system of claim 20, wherein the moveable contact plate is pivotally mounted within the torso.

22. The system of claim 21, wherein a spring biases the movable contact plate towards an initial position.

23. The system of claim 20, wherein the pneumothorax simulation system is configured to selectively activate and deactivate a simulated left lung, a simulated right lung, or both simulated left and right lungs.