[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Generator Inspection Method

Technical Field and Background:
As one type of combined cycle power generation plant that drives a generator using a gas turbine and a steam turbine, there is a power generation plant in which a shaft of the gas turbine is connected to one end of a shaft of the generator and a shaft of the steam turbine is connected to the other end of the shaft of the generator. In this type of the combined cycle power generation plant, the shaft of the gas turbine, the shaft of the generator, and the shaft of the steam turbine are aligned in the same straight line. In this type of the combined cycle power generation plant, when an inspection of the shaft and the like is carried out after taking out the shaft of the generator from a casing of the generator, the inspection is sometimes carried out using the following method, for example. First, one of the gas turbine and the steam turbine that exist in an axial direction of the generator is disassembled. Next, after lifting up the generator, the shaft of the generator is pulled out from the casing of the generator toward a side, in the axial direction of the generator, on which an empty space has been created as a result of the disassembly. After that, the shaft is placed in a predetermined location, and the inspection of the shaft and the like is carried out. In the above-described method, when disassembling the generator, it becomes necessary to disassemble the gas turbine or the steam turbine. Thus, with the above-described method, even when only the generator needs inspection, it is necessary to disassemble the gas turbine or the steam turbine. Here, Patent Literature 1 described below discloses the following method in which it is not necessary to disassemble the gas turbine or the steam turbine when disassembling the generator. In this method, two platforms are prepared in advance, each of which has a floor face at a position higher than the highest point of the steam turbine. Then, of the two platforms, the first platform is installed so that the floor face of the first platform is positioned above the steam turbine. Next, the shaft of the generator is disconnected from the shaft of the gas turbine, and at the same time, the shaft of the generator is disconnected from the shaft of the steam turbine. Next, the generator is lifted up using a special lift-up device, until a bottom of the generator reaches a higher position than the floor face of the first platform. Next, the second platform is installed below the generator, and the generator is placed on the second platform. Next, the shaft of the generator is pulled out from the generator placed on the second platform toward the first platform side in the axial direction of the shaft. After that, the shaft is placed on the first platform, and the inspection of the shaft and the like is carried out.

Invention Disclosure:
In the present invention, the following are carried out: a shaft disconnecting step of disconnecting rotary machines that are respectively connected to both ends of a shaft of a generator; a gap forming step of forming a gap in a vertical direction between the generator and an installation stand; a pathway installing step of inserting into the gap a portion of a movement pathway member extending in a lateral direction which includes a horizontal direction component and a radial direction component of the shaft; a moving step of moving the generator in the lateral direction on the movement pathway member; and an inspecting step of inspecting the generator having undergone the moving step.

[Assistant]
1. A generator inspection method of inspecting a generator in which rotary machines are respectively connected to both ends of a shaft, the method comprising:
a shaft disconnecting step of disconnecting the rotary machines respectively connected to the ends of the shaft;
a gap forming step of forming a gap, in a vertical direction, between an installation stand of the generator and the generator;
a pathway installing step of inserting into the gap a portion of a movement pathway member extending in a lateral direction, the lateral direction including a horizontal direction component and a radial direction component of the shaft;
a moving step of moving the generator in the lateral direction on the movement pathway member; and
an inspecting step of inspecting the generator having undergone the moving step.

2. The generator inspection method according to claim 1, wherein
following the gap forming step and before the moving step, a roller arranging step is carried out to arrange a roller, which rolls in the lateral direction, between the movement pathway member and the generator.

3. The generator inspection method according to claim 2, wherein
in the roller arranging step, a roller carriage is arranged, the roller carriage being provided with at least one roller and a base which has a placement portion, on which an object is placed, above the at least one roller and which rotatably supports the at least one roller.

4. The generator inspection method according to claim 2, wherein
the movement pathway member has a roller guide member that regulates a movement of the roller in a horizontal direction perpendicular to the lateral direction.

5. The generator inspection method according claim 2, wherein
in the moving step, a rolling of the roller is restricted after moving the generator to an intended position in the lateral direction.

6. The generator inspection method according to claim 1, wherein
in the gap forming step, the generator is lifted upward using a jack, and a gap is formed in the vertical direction between the installation stand of the generator and the generator.

7. The generator inspection method according to claim 1, wherein
a structure that supports the movement pathway member is installed in advance at a position in the lateral direction of the generator, and
in the pathway installing step, the portion of the movement pathway member is inserted into the gap and then the movement pathway member is placed on the installation stand and the structure.

8. The generator inspection method according to claim 7, wherein
the structure has a floor board and a support structure that supports the floor board from below, and
a portion of the floor board is cut out along a section on which the movement pathway member is placed above the support structure.

9. The generator inspection method according to claim 8, wherein
the structure has a lid board that closes the cutout section of the floor board.

10. The generator inspection method according to claim 1, wherein
in the inspecting step, the shaft is pulled out, in an axial direction, from a casing that covers the shaft.

11. The generator inspection method according to claim 1, wherein,
after the inspecting step, the following steps are carried out:
a return moving step of returning the generator to an original position thereof above the installation stand in the horizontal direction by moving the generator in the lateral direction on the movement pathway member;
a gap forming step of forming a gap in the vertical direction between the movement pathway member and the generator;
a pathway removing step of removing the movement pathway member;
a placing step of placing the generator on the installation stand; and
a shaft connecting step of connecting the rotary machines respectively to the ends of the shaft.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Power Semiconductor Module And Power Conversion Device

Technical Field and Background:
In an insulated type power semiconductor module used for a power conversion device such as an inverter, a wiring pattern is formed over a metal plate, serving as a heat radiation plate, through an insulation layer, and a power semiconductor element that performs a switching operation is disposed on the wiring pattern. Such a power semiconductor element is connected to external terminals and is molded by resin. In a power conversion device in which a switching operation with large current and high voltage is performed, a surge voltage (ΔV=L·di/dt) is generated due to a time rate of current change di/dt when the power semiconductor element is switched off and a parasitic inductance L contained in the power conversion device, and the surge voltage is applied to the power semiconductor element. As the parasitic inductance L increases, a surge voltage larger than a breakdown voltage of the power semiconductor element may be generated and thus may cause destruction of the power semiconductor element. Therefore, reducing inductance is requested in power conversion devices and reducing inductance is requested also in power semiconductor modules. In a power conversion device, for the purpose of securing a necessary current capacity, a power semiconductor module having such a capacity is selected. Or, if a suitable candidate is not available, power semiconductor modules are used in parallel. However, when power semiconductor modules are used in parallel, it is necessary to keep a certain interval between the modules for securing an insulation distance, thereby inviting a problem of the increase in footprints. In order to solve the problem, a semiconductor device is proposed in which a plurality of power semiconductor elements are arranged in parallel in a package (e.g., see Patent Document 1). As shown in Patent Document 1, even if a plurality of external terminals are disposed for connecting to an external circuit, when terminals of the plurality of power semiconductor elements which are arranged in parallel in the package are collectively connected to the external terminal in the package, an effect of reducing the inductance is less likely to be obtained. Thus, since di/dt at switching off increases as the current capacity increases, the increase of the surge voltage occurs and may cause the destruction of the power semiconductor elements. A power semiconductor module is developed in which, similar to that in Patent Document 1, a plurality of power semiconductor elements are arranged in parallel in a package and a plurality of external terminals are disposed, and in which terminals of the plurality of power semiconductor elements are each separately connected to the external terminal in the package (e.g., see Patent Document 2). Also, in the module shown in Patent Document 2, the external terminals through which principal current flows are disposed in a vertically-stacked manner and bonding wires are disposed so as to cancel magnetic fluxes generated by the principal current, thereby reducing the inductance.

Invention Disclosure:
A power semiconductor module capable of reducing variation of inductance between upper/lower arms and reducing variation of current caused by the variation of inductance. The power semiconductor module includes circuit blocks (upper/lower arms) each of which is configured by connecting self-arc-extinguishing type semiconductor elements in series; first and second positive electrode terminals, first and second negative electrode terminals, and first and second AC terminals. Further, there are first and second wiring patterns that connect the self-arc-extinguishing type semiconductor elements to the DC and AC terminals. The outline of the power semiconductor module has a substantially quadrangular surface.

[Assistant]
1. A power semiconductor module, comprising:
a first set of an upper arm and a lower arm which includes a positive switching element and a negative switching element which are series-connected to each other, the positive switching element having a plurality of self-arc extinguishing type semiconductor elements parallel-connected to each other, the negative switching element having a plurality of self-arc extinguishing type semiconductor elements parallel-connected to each other;
a second set of an upper arm and a lower arm which includes a positive switching element and a negative switching element which are series-connected to each other, the positive switching element having a plurality of self-arc extinguishing type semiconductor elements parallel-connected to each other, the negative switching element having a plurality of self-arc extinguishing type semiconductor elements parallel-connected to each other, the second set of an upper arm and a lower arm being connected in parallel to the first set of an upper arm and a lower arm;
a first positive electrode side DC terminal connected to the positive switching element of the first set of an upper arm and a lower arm;
a second positive electrode side DC terminal connected to the positive switching element of the second set of an upper arm and a lower arm;
a first negative electrode side DC terminal connected to the negative switching element of the first set of an upper arm and a lower arm;
a second negative electrode side DC terminal connected to the negative switching element of the second set of an upper arm and a lower arm;
a first AC terminal connected to both of the positive switching element and the negative switching element of the first set of an upper arm and a lower arm;
a second AC terminal connected to both of the positive switching element and the negative switching element of the second set of an upper arm and a lower arm;
a first wiring pattern which connects the first set of an upper arm and a lower arm to the first positive electrode side DC terminal, the first negative electrode side DC terminal, and the first AC terminal; and
a second wiring pattern which connects the second set of an upper arm and a lower arm to the second positive electrode side DC terminal, the second negative electrode side DC terminal, and the second AC terminal, wherein
an outline of the power semiconductor module has a substantially quadrangular surface;
the first and second positive electrode side DC terminals and the first and second negative electrode side DC terminals are disposed at a side of the substantially quadrangular surface;
the first and second AC terminals are disposed at a side which is opposite to the side; and
the first positive electrode side DC terminal and the first negative electrode side DC terminal are disposed in mirror symmetry with the second positive electrode side DC terminal and the second negative electrode side DC terminal.

2. The power semiconductor module in claim 1, wherein
the first AC terminal is disposed in mirror symmetry with the second AC terminal based on a symmetrical axis; and
the first wiring pattern is disposed in mirror symmetry with the second wiring pattern based on the same symmetrical axis for the AC patterns.

3. The power semiconductor module in claim 1, wherein
the first positive electrode side DC terminal and the first negative electrode side DC terminal are disposed in mirror symmetry with the second positive electrode side DC terminal and the second negative electrode side DC terminal based on a right-angle axis with the side of the substantially quadrangular surface where the positive electrode side DC terminals and the negative electrode side DC terminals are disposed.

4. The power semiconductor module in claim 1, wherein
the first wiring pattern is disposed in mirror symmetry with the second wiring pattern based on a right-angle axis with the side of the substantially quadrangular surface where the positive electrode side DC terminals and the negative electrode side DC terminals are disposed.

5. The power semiconductor module in claim 1, wherein
the first wiring pattern has a first negative electrode terminal pattern portion which connects the first set of an upper arm and a lower arm to the first negative electrode side DC terminal;
the second wiring pattern has a second negative electrode terminal pattern portion which connects the second set of an upper arm and a lower arm to the second negative electrode side DC terminal; and
the first negative electrode terminal pattern portion is connected to the second negative electrode terminal pattern portion in the power semiconductor module.

6. The power semiconductor module in claim 1, wherein
the first wiring pattern has a first control wiring pattern portion connected to control electrodes of the self-arc-extinguishing type semiconductor elements of the first set of an upper arm and a lower arm;
the second wiring pattern has a second control wiring pattern portion connected to control electrodes of the self-arc-extinguishing type semiconductor elements of the second set of an upper arm and a lower arm; and
a relationship between a direction of gate charge/discharge current, flowing through the control wiring pattern portion, of the self-arc-extinguishing type semiconductor element and a direction of principal current flowing through the self-arc-extinguishing type semiconductor element is unified in the first and second set of an upper arm and a lower arms.

7. The power semiconductor module in claim 1, wherein
the first AC terminal and the second AC terminal are electrically connected each other at the same electric potential.

8. The power semiconductor module in claim 1, wherein
a distance between the first positive electrode side DC terminal and the first negative electrode side DC terminal is shorter than a distance between the first positive electrode side DC terminal and the first AC terminal.

9. The power semiconductor module in claim 1, wherein
a distance between the first positive electrode side DC terminal and the first negative electrode side DC terminal is shorter than a distance between the first negative electrode side DC terminal and the first AC terminal.

10. The power semiconductor module in claim 1, wherein
the first positive electrode side DC terminal and the first wiring pattern are connected at a first point;
the first negative electrode side DC terminal and the first wiring pattern are connected to at a second point;
the first AC terminal and the first wiring pattern are connected at a third point; and
a distance between the first point and the second point is shorter than a distance between the second point and the third point.

11. The power semiconductor module in claim 1, wherein
the first positive electrode side DC terminal and the first wiring pattern are connected at a first point;
the first negative electrode side DC terminal and the first wiring pattern are connected to at a second point;
the first AC terminal and the first wiring pattern are connected at a third point; and
a distance between the first point and the second point is shorter than a distance between the first point and the third point.

12. The power semiconductor module in claim 1, wherein
the self-arc-extinguishing type semiconductor elements include any one of silicon carbide, gallium nitride based material, and diamond that have a wider bandgap than silicon.

13. A power semiconductor module, comprising:
a first set of an upper arm and a lower arm which includes a positive switching element and a negative switching element which are series-connected to each other, the positive switching element having a plurality of self-arc extinguishing type semiconductor elements parallel-connected to each other, the negative switching element having a plurality of self-arc extinguishing type semiconductor elements parallel-connected to each other;
a second set of an upper arm and a lower arm which includes a positive switching element and a negative switching element which are series-connected to each other, the positive switching element having a plurality of self-arc extinguishing type semiconductor elements parallel-connected to each other, the negative switching element having a plurality of self-arc extinguishing type semiconductor elements parallel-connected to each other, the second set of an upper arm and a lower arm being connected in parallel to the first set of an upper arm and a lower arm;
a first positive electrode side DC terminal connected to the positive switching element of the first set of an upper arm and a lower arm;
a second positive electrode side DC terminal connected to the positive switching element of the second set of an upper arm and a lower arm;
a first negative electrode side DC terminal connected to the negative switching element of the first set of an upper arm and a lower arm;
a second negative electrode side DC terminal connected to the negative switching element of the second set of an upper arm and a lower arm;
a first AC terminal connected to both of the positive switching element and the negative switching element of the first set of an upper arm and a lower arm;
a second AC terminal connected to both of the positive switching element and the negative switching element of the second set of an upper arm and a lower arm;
a first wiring pattern which connects the first set of an upper arm and a lower arm to the first positive electrode side DC terminal, the first negative electrode side DC terminal, and the first AC terminal; and
a second wiring pattern which connects the second set of an upper arm and a lower arm to the second positive electrode side DC terminal, the second negative electrode side DC terminal, and the second AC terminal, wherein
an outline of the power semiconductor module has a substantially quadrangular surface;
the first and second positive electrode side DC terminals, the first and second negative electrode side DC terminals, and the first and second AC terminals are disposed within the substantially quadrangular surface in an order of the positive electrode side DC terminal, the negative electrode side DC terminal, and the AC terminal; and
the first positive electrode side DC terminal and the first negative electrode side DC terminal are disposed in mirror symmetry with the second positive electrode side DC terminal and the second negative electrode side DC terminal.

14. The power semiconductor module in claim 13, wherein
the first AC terminal is disposed in mirror symmetry with the second AC terminal based on a symmetrical axis; and
the first wiring pattern is disposed in mirror symmetry with the second wiring pattern based on the same symmetrical axis for the AC patterns.

15. The power semiconductor module in claim 13, wherein
the first AC terminal and the second AC terminal are electrically connected each other at the same electric potential.

16. The power semiconductor module in claim 13, wherein
a distance between the first positive electrode side DC terminal and the first negative electrode side DC terminal is shorter than a distance between the first positive electrode side DC terminal and the first AC terminal.

17. The power semiconductor module in claim 13, wherein
a distance between the first positive electrode side DC terminal and the first negative electrode side DC terminal is shorter than a distance between the first negative electrode side DC terminal and the first AC terminal.

18. The power semiconductor module in claim 13, wherein
the first positive electrode side DC terminal and the first wiring pattern are connected at a first point;
the first negative electrode side DC terminal and the first wiring pattern are connected to at a second point;
the first AC terminal and the first wiring pattern are connected at a third point; and
a distance between the first point and the second point is shorter than a distance between the second point and the third point.

19. The power semiconductor module in claim 13, wherein
the first positive electrode side DC terminal and the first wiring pattern are connected at a first point;
the first negative electrode side DC terminal and the first wiring pattern are connected to at a second point;
the first AC terminal and the first wiring pattern are connected at a third point; and
a distance between the first point and the second point is shorter than a distance between the first point and the third point.

20. The power semiconductor module in claim 13, wherein
the self-arc-extinguishing type semiconductor elements include any one of silicon carbide, gallium nitride based material, and diamond that have a wider bandgap than silicon.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Gate Valve For Controlling The Passage Of Liquid

Technical Field and Background:
1. Field of the Invention The present invention relates to a gate valve for controlling the passage of liquid, sludge and/or fecal matter through a fluid passage. The invention further relates to a vehicle, such as a mobile home, a trailer or a motor home, comprising the new gate valve. The invention even further relates to a slider for use in a gate valve according to the present invention. 2. Description of the Related Art Gate valves for controlling the passage of liquid, sludge and/or fecal matter are already known in the art. A known gate valve comprises a valve body having a fluid passage for the passage of liquid, sludge and/or fecal matter, and comprises a substantially flat slider which is slideable between an opened and a closed position in order to open or block the fluid passage, respectively, wherein the slider comprises two opposite straight edges via which the slider is slidably guided in the valve body surrounding it, and wherein the slider is substantially made from a plastic material. A drawback of the known gate valve is that the dimensions of the fluid passage, and thus also of the slider, are restricted as the slider is not sufficient rigid for relatively large fluid passages. As such, for relatively large fluid passages, there is an increased risk of the slider to flex and to destroy gate seals during sliding of the slider to the closed position.

Invention Disclosure:
A gate valve includes a valve body having a fluid passage for the passage of liquid, sludge and/or fecal matter and a substantially flat slider. The slider is slideable between an opened and a closed position in order to open or block the fluid passage, respectively. The slider includes two opposite straight edges via which the slider is slidably guided in the valve body surrounding it. The slider is substantially made from a plastic material. The slider includes flanges along each of the two opposite straight edges for providing rigidity to the slider.

[Assistant]
1. A gate valve, comprising:
a valve body defining a fluid passage for the passage of liquid, sludge, and/or fecal matter, the valve body, including:
first opposed protrusions located interior to the valve body at a first end of the valve body, wherein the first opposed protrusions define a first elongated channel at the first end of the valve body, and
second opposed protrusions located interior to the valve body at a second end of the valve body, wherein the second opposed protrusions define a second elongated channel at the second end of the valve body; and
a slider which is slideable between an opened position that opens the fluid passage and a closed position that blocks the fluid passage and facilitates a sealing of the gate valve, wherein:
the slider comprises a first straight edge opposite a second straight edge via which the slider is slidably guided in the valve body surrounding it,
the slider is substantially made from a plastic material, and
the slider comprises:
a first flange substantially orthogonal to and along the first straight edge for providing rigidity to the slider, wherein the first flange inserts into the first elongated channel such that the first opposed protrusions substantially encompass the first flange, further wherein the first elongated channel cooperates with the first flange for slideably guiding the slider in the valve body and for reducing slider flex thereby improving the sealing of the gate valve, and
a second flange substantially orthogonal to and along the second straight edge for providing rigidity to the slider, wherein the second flange inserts into the second elongated channel such that the second opposed protrusions substantially encompass the second flange, further wherein the second elongated channel cooperates with the second flange for slideably guiding the slider in the valve body and for reducing slider flex thereby improving the sealing of the gate valve.

2. The gate valve according to claim 1, wherein the slider is oriented in a plane, and the flanges extend from a respective edge in a direction substantially orthogonal to the plane.

3. The gate valve according to claim 2, wherein the flanges extend from a respective edge in both directions substantially orthogonal to the plane.

4. The gate valve according to claim 3, wherein a height of the flanges is between 2 mm-5 mm.

5. The gate valve according to claim 1, wherein a cross section of the fluid passage is substantially round, further wherein a diameter of the round cross section is between 90 mm-400 mm.

6. The gate valve according to claim 1, wherein the gate valve comprises a shaft fixedly connected to the slider for operating the slider between the opened and the closed position.

7. The gate valve according to claim 6, wherein the shaft is molded into the slider.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Method And Device For Bandwidth Assignment Of Optical Burst Ring

Technical Field and Background:
For meeting requirements on orientation to service traffic which will dynamically change in the future and efficient utilization of bandwidth resources, an industrial community proposes a concept of an OBRing based on all-optical packet transmission and switching. The OBRing may greatly reduce a cost of software and hardware of an existing network and a cost of operation administration and maintenance of the existing network, and the OBRing is particularly suitable for a network full-interconnection application scenario of establishing a connection between any two points. The OBRing may adopt a single-ring or double-ring topology. For example, as shown in FIG. 1 , four nodes A, B, C and D are connected together through a single ring. An OBRing consists of a control plane and a data plane, which respectively use different working wavelengths. For the control plane, a master node A controls bandwidth resources of whole network in a centralized manner. A control frame sent by the master node A is transmitted by one circle around the single ring to distribute bandwidth grants to nodes B, C and D, and returns to the master node A with bandwidth requests of the nodes B, C and D. The master node A updates the bandwidth grants according to the bandwidth requests. For the data plane, at least one Optical Burst (OB) with a fixed length of each OB is used to bear one or more services in the OBRing. A duration of each OB is defined as an OB timeslot. OBs which are sent by different nodes and have different wavelengths are temporally aligned, that is, OBs with different wavelengths may share the same OB timeslot. The OBs are all-optically and transparently transmitted through nodes through which the OBs pass without optic-electro-optic conversion. Each node broadcasts one or more OBs in at least one OB timeslot specified by the bandwidth grants by virtue of a fixed wavelength. The nodes update the bandwidth grants every one or more OB timeslots. An updating period of the bandwidth grants is defined as a Dynamic Bandwidth Assignment (DBA) period. After an OB arrives at a destination node, the destination node configures a tunable receiver according to a control frame, and receives the OB on a specified wavelength in a specified timeslot. The OB may be transmitted by an upstream node of the master node, and ends at a downstream node of the master node to establish an over-the-master-node connection or a not-over-the-master-node connection after being transparently transmitted over the master node, as shown in FIG. 2 . A data connection may be established between any two nodes by sending and receiving one or more OBs, and a bandwidth of the data connection may be dynamically regulated by regulating the number of the one or more OBs. From the above, characteristics of the OBRing may be summarized as follows: a ring topology and multiple working wavelengths are adopted, the master node is adopted for centralized control, all-optical burst transmission and switching is supported, and a dynamic network full-interconnection application scenario is supported. A method for bandwidth assignment is one of key technologies for implementing an OBRing. However, in the related art, above method for bandwidth assignment may not be directly applied to the OBRing. As shown in FIG. 3 , as an optical access network, a Passive Optical Network (PON) adopts a point-to-multipoint tree topology. An Optical Line Terminal (OLT) is connected with multiple Optical Network Units (ONUs) through an Optical Distribution Network (ODN). A direction from each ONU to the OLT is defined as an uplink direction. The OLT controls uplink bandwidth assignment of the PON in a centralized manner. The OLT periodically sends bandwidth grants to all the ONUs. The ONUs send uplink services to the OLT at different time with the same working wavelength according to the bandwidth grants, and report bandwidth requests. The OLT receives all the uplink services and bandwidth requests, and makes new bandwidth grants according to the bandwidth requests. Such a method for bandwidth assignment for the PON is inapplicable to the OBRing.

Invention Disclosure:
The disclosure provides a method for bandwidth assignment of an Optical Burst Ring (OBRing), which includes that: a master node acquires current bandwidth resources, and excludes bandwidth resources occupied by over-the-master-node connections from the current bandwidth resources to obtain bandwidth resources to be assigned; and the master node assigns the bandwidth resources to be assigned to each node according to bandwidth requests of each node in the OBRing. The disclosure also provides a device for bandwidth assignment of an OBRing. According to embodiments of the disclosure, the bandwidth resources occupied by the over-the-master-node connections are excluded before bandwidth assignment is started, so that the problem of receiving conflict caused by an over-the-master-node service data connection is solved.

[Assistant]
1. A method for bandwidth assignment of an Optical Burst Ring, OBRing, comprising:
acquiring, by a master node, current bandwidth resources, and excluding bandwidth resources occupied by over-the-master-node connections from the current bandwidth resources to obtain bandwidth resources to be assigned; and
assigning, by the master node, the bandwidth resources to be assigned to each node according to bandwidth requests of each node in the OBRing;
wherein the master node takes one Optical Burst, OB, timeslot as a unit and performs the bandwidth assignment on OB timeslots one by one when the bandwidth resources to be assigned are assigned to each node, and executes an operation of excluding the bandwidth resources occupied by the over-the-master-node connections from the current bandwidth resources before the bandwidth assignment is performed on each OB timeslot;
wherein the method further comprises: before the bandwidth assignment is performed on each OB timeslot, setting, by the master node, a logic destination node, called a first logic destination node, for the master node and an adjacent upstream node of the master node, setting, by the master node, two logic destination nodes, respectively called the first logic destination node and a second logic destination node, for the other nodes except for the master node and the adjacent upstream node of the master node, wherein the first logic destination node is configured to establish a not-over-the-master-node connection with an upstream node of the first logic destination node, and the second logic destination node is configured to establish an over-the-master-node connection with a downstream node of the second logic destination node, and setting, by the master node, one or more logic source nodes for each node;
acquiring, by the master node, the current bandwidth resources, and excluding the bandwidth resources occupied by the over-the-master-node connections from the current bandwidth resources comprises: before bandwidth assignment is performed on each OB timeslot, acquiring, by the master node, a destination node of an over-the-master-node connection in the current OB timeslot, and excluding the first logic destination node corresponding to the destination node of the over-the-master-node connection; and
assigning, by the master node, the bandwidth resources to be assigned to each node according to the bandwidth requests of each node in the OBRing comprises: in each OB timeslot, looking for and establishing, by the master node, connections between the rest of logic source nodes and logic destination nodes according to bandwidth requests existing in the current timeslot, wherein the bandwidth requests existing in the current timeslot are determined based on bandwidth requests according to which this round of bandwidth assignment is performed, bandwidth requests which are not met before this round of bandwidth assignment and bandwidth requests, which have been met in timeslots on which bandwidth assignment has been performed, in this round of bandwidth assignment.

2. The method as claimed in claim 1, wherein the method further comprises:
before the bandwidth assignment is performed, acquiring, by the master node, bandwidth requests in one Dynamic Bandwidth Assignment, DBA, period, classifying, by the master node, each bandwidth request of the bandwidth requests in the DBA period according to service levels to obtain one or more types of bandwidth requests, wherein, each type of bandwidth requests corresponds to one priority, and sequentially performing, by the master node, one or more rounds of bandwidth assignment on each type of bandwidth requests consistent with a preset condition according to priorities of the one or more types of bandwidth requests, wherein each round of bandwidth assignment corresponds to one type of bandwidth requests and bandwidth assignment being performed on OB timeslots one by one by taking one OB timeslot as a unit in each round of bandwidth assignment.

3. The method as claimed in claim 1, wherein
in each OB timeslot, looking for and establishing, by the master node, the connections between the rest of logic source nodes and logic destination nodes according to the bandwidth requests existing in the current timeslot comprises:
executing the following iteration process:
sending, by the logic source nodes with bandwidth requests existing in this iteration, virtual requests to logic destination nodes, and specifying, by the logic source nodes with bandwidth requests existing in this iteration, priorities of the virtual requests, wherein the bandwidth requests existing in this iteration are the bandwidth requests existing in the current timeslot during the first iteration;
selecting, by the logic destination nodes, virtual requests with the highest priorities, and sending, by the logic destination nodes, virtual grants to the corresponding logic source nodes, which sends the virtual requests with the highest priorities, wherein priorities of the virtual grants are consistent with the priorities of the virtual requests upon which the virtual grants are responded;
selecting, by the logic source nodes, the virtual grants with the highest priorities, and establishing connections with the corresponding logic destination nodes, which sends the virtual grants with the highest priorities; and
judging whether a specified number of iteration times has been reached or not, ending the iteration process if the specified number of iteration times has been reached, otherwise subtracting the bandwidth requests corresponding to which the connections have been established from the bandwidth requests existing in this iteration, excluding the logic source nodes and logic destination nodes between which the connections have been established, and restarting the iteration process.

4. The method as claimed in claim 3, wherein the priorities of the virtual requests are determined according to at least one of the following: magnitudes of the bandwidth requests between the logic source nodes and logic destination nodes corresponding to the virtual requests, caching queue head queuing time of cached data which is sent to the corresponding logic destination nodes by the logic source nodes initiating the virtual requests and a guaranteed bandwidth threshold for the connections between the logic source nodes and logic destination nodes corresponding to the virtual requests.

5. The method as claimed in claim 1, wherein the method further comprises: removing all the second logic destination nodes before bandwidth assignment is performed on a specified OB timeslot.

6. The method as claimed in claim 3, wherein setting the one or more logic source nodes for each node comprises: setting one logic source node for each node.

7. The method as claimed in claim 3, wherein setting the one or more logic source nodes for each node comprises:
setting two logic source nodes for each node, comprising a first logic source node and a second logic source node, wherein the first logic source node is configured to establish connections with the destination nodes in the current DBA period, and the second logic source node is configured to reserve bandwidth resources for not-over-the-master-node connections established with downstream nodes in the next DBA period;
when the iteration process is executed, sending, by the logic source nodes with the bandwidth requests existing in this iteration, the virtual requests to the logic destination nodes comprises: sending, by first logic source nodes with the bandwidth requests existing in this iteration, the virtual requests to the logic destination nodes, and sending, by the second logic source nodes with the bandwidth requests for the not-over-the-master-node connections existing in this iteration, the virtual requests to the second logic destination nodes; and
discarding connections established by the second logic source nodes.

8. A device for bandwidth assignment of an Optical Burst Ring, OBRing, comprising: a hardware processor, configured to perform programming components stored in a memory, wherein the programming components comprise:
an input component, configured to acquire current bandwidth resources, and exclude bandwidth resources occupied by over-the-master-node connections from the current bandwidth resources to obtain bandwidth resources to be assigned; and
a bandwidth assignment component, configured to assign the bandwidth resources to be assigned to each node according to bandwidth requests of each node in the OBRing;
wherein the bandwidth assignment component is configured to take one Optical Burst, OB, timeslot as a unit and perform the bandwidth assignment on OB timeslots one by one when the bandwidth resources to be assigned are assigned to each node; and the input component is configured to execute an operation of excluding the bandwidth resources occupied by the over-the-master-node connections from the current bandwidth resources before the bandwidth assignment is performed on each OB timeslot;
wherein the bandwidth assignment component comprises a control element and an iteration element, wherein the control element is configured to, before the bandwidth assignment is performed on each OB timeslot, by a master node, set a logic destination node, called a first logic destination node, for the master node and an adjacent upstream node of the master node, set two logic destination nodes, respectively called the first logic destination node and a second logic destination node, for the other nodes except for the master node and the adjacent upstream node of the master node, wherein the first logic destination node is configured to establish a not-over-the-master-node connection with an upstream node of the first logic destination node and the second logic destination node is configured to establish an over-the-master-node connection with a downstream node of the second logic destination node, and set one or more logic source nodes for each node;
the input component is further configured to, before bandwidth assignment is performed on each OB timeslot, acquire a destination node of an over-the-master-node connection in the current OB timeslot, and exclude the first logic destination node corresponding to the destination node of the over-the-master-node connection; and the iteration element is configured to, in each OB timeslot, look for and establish connections between the rest of logic source nodes and logic destination nodes according to bandwidth requests existing in the current timeslot, wherein the bandwidth requests existing in the current timeslot are determined based on the bandwidth requests according to which this round of bandwidth assignment is performed, bandwidth requests which are not met before this round of bandwidth assignment and bandwidth requests which have been met in timeslots on which bandwidth assignment has been performed in this round of bandwidth assignment.

9. The device as claimed in claim 8, wherein
the input component is further configured to, before bandwidth assignment is performed, acquire the bandwidth requests in one Dynamic Bandwidth Assignment, DBA, period, and classify each bandwidth request of the bandwidth requests in the DBA period according to service levels to obtain one or more types of bandwidth requests, wherein, each type of bandwidth requests corresponds to one priority; and
the bandwidth assignment component is further configured to sequentially perform one or more rounds of bandwidth assignment on each type of bandwidth requests consistent with a preset condition according to their priorities of the one or more types of bandwidth requests, wherein each round of bandwidth assignment corresponds to one type of bandwidth requests and bandwidth assignment being performed on OB timeslots one by one by taking one OB timeslot as a unit in each round of bandwidth assignment.

10. The device as claimed in claim 8, wherein
the iteration unit is configured to perform the operation of looking for and establishing the connections between the rest of logic source nodes and logic destination nodes according to the bandwidth requests existing in the current timeslot in each OB timeslot comprises that:
the following iteration process is executed:
the logic source nodes with the bandwidth requests existing in this iteration send virtual requests to logic destination nodes, and specify priorities of the virtual requests, wherein the bandwidth requests existing in this iteration are the bandwidth requests existing in the current timeslot during the first iteration;
the logic destination nodes select virtual requests with the highest priorities, and send virtual grants to the corresponding logic source nodes, which sends the virtual requests with the highest priorities, wherein priorities of the virtual grants are consistent with the priorities of the virtual requests upon which the virtual grants are responded;
the logic source nodes select the virtual grants with the highest priorities, and establish connections with the corresponding logic destination nodes, which sends the virtual grants with the highest priorities; and
whether a specified iteration number of times has been reached or not is judged, the iteration process ends if the specified number of iteration times has been reached, otherwise the bandwidth requests corresponding to which the connections have been established are subtracted from the bandwidth requests existing in this iteration, the logic source nodes and logic destination nodes between which the connections have been established are excluded, and the iteration process is restarted.

11. The device as claimed in claim 10, wherein the iteration unit determines the priorities of the virtual requests according to at least one of the following: magnitudes of the bandwidth requests between the logic source nodes and logic destination nodes corresponding to the virtual requests, caching queue head queuing time of cached data which is sent to the corresponding logic destination nodes by the logic source nodes initiating the virtual requests and a guaranteed bandwidth threshold for the connections between the logic source nodes and logic destination nodes corresponding to the virtual requests.

12. The device as claimed in claim 8, wherein the input component is further configured to remove all the second logic destination nodes before bandwidth assignment is performed on a specified OB timeslot.

13. The device as claimed in claim 10, wherein the control element is configured to perform the operation of setting the one or more logic source nodes for each node comprises that:
one logic source node is set for each node;
or,
two logic source nodes are set for each node, comprising a first logic source node and a second logic source node, wherein the first logic source node is configured to establish connections with the destination nodes in the current DBA period, and the second logic source node is configured to reserve bandwidth resources for not-over-the-master-node connections established with the downstream nodes in the next DBA period;
when the iteration element executes the iteration process, the operation that the logic source nodes with the bandwidth requests existing in this iteration send the virtual requests to the logic destination nodes comprises that: the first logic source nodes with the bandwidth requests existing in this iteration send the virtual requests to the logic destination nodes, and the second logic source nodes with the bandwidth requests for the not-over-the-master-node connections existing in this iteration send the virtual requests to the second logic destination nodes; and connections established by the second logic source nodes are discarded.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Systems And Methods For Adjusting Audio Based On Ambient Sounds

Technical Field and Background:
Ambient sounds can significantly affect the audio experience of listeners enjoying a song, a movie or a television program. Additionally, ambient sounds may continuously change while watching a movie or listening to a song. To cope with ambient sounds or background noise and their continuous changes, listeners are frequently forced to manually increase the volume, pause and/or rewind each time there is an ambient sound that interferes with their listening experience.

Invention Disclosure:
There is provided a system for use in an environment, the system comprising a microphone, a plurality of speakers, a memory storing an executable code, and a processor executing the executable code to receive a media content including an audio component, play the audio component of the media content over at least one of the plurality of speakers, detect, while playing the audio component, an ambient sound in the environment using the microphone, and adjust playing of the audio component of the media content for the at least one of the plurality of speakers based on the ambient sound in the environment.

[Assistant]
1. A system for use in an environment, the system comprising:
a microphone;
a plurality of speakers;
a non-transitory memory storing an executable code; and
a hardware processor executing the executable code to:
receive a media content including a plurality of surround sound audio components;
play the plurality of surround sound audio components of the media content over the plurality of speakers;
detect, while playing the plurality of surround sound audio components, an ambient sound in the environment using the microphone; and
adjust a volume of at least one of the plurality of surround sound audio components, but not all of the plurality of surround sound audio components, based on the ambient sound in the environment, for playing over at least one of the plurality of speakers.

2. The system of claim 1, wherein the hardware processor executes the executable code to further identify the ambient sound using a sound database stored in the non-transitory memory, and wherein detecting includes determining a volume of the ambient sound.

3. The system of claim 1, wherein the plurality of surround sound audio components have a plurality of sound tracks including a dialog sound track.

4. The system of claim 3, wherein adjusting the volume includes changing a volume of the dialog sound track.

5. The system of claim 1, wherein the plurality of speakers includes a speaker of a mobile device.

6. The system of claim 1, wherein adjusting the volume pauses the playing of the least one of the plurality of surround sound audio components on the at least one of the plurality of speakers.

7. The system of claim 1, wherein the media content includes metadata describing the plurality of surround sound audio components, and wherein the adjusting uses the metadata.

8. A method for use with a system having a non-transitory memory and a hardware processor in an environment, the method comprising:
receiving, using the hardware processor, a media content including a plurality of surround sound audio components;
playing, using the hardware processor, the plurality of surround sound audio components of the media content over a plurality of speakers;
detecting, using the hardware processor while playing the plurality of surround sound audio components, an ambient sound in the environment using a microphone; and
adjusting, using the hardware processor, a volume of at least one of the plurality of surround sound audio components, but not all of the plurality of surround sound audio components, based on the ambient sound in the environment, for playing over at least one of the plurality of speakers.

9. The method of claim 8, further comprising:
identify, using the hardware processor, the ambient sound using a sound database stored in the non-transitory memory, and wherein detecting includes determining a volume of the ambient sound.

10. The method of claim 8, wherein the plurality of surround sound audio components have a plurality of sound tracks including a dialog sound track.

11. The method of claim 10, wherein adjusting the volume includes changing a volume of the dialog sound track.

12. The method of claim 8, wherein the plurality of speakers includes a speaker of a mobile device.

13. The method of claim 8, wherein adjusting the volume pauses the playing of the least one of the plurality of surround sound audio components on the at least one of the plurality of speakers.

14. The method of claim 8, wherein the media content includes metadata describing the plurality of surround sound audio components, and wherein the adjusting uses the metadata.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Methods And Apparatuses For Estimating On-Wafer Oxide Layer Reduction Effectiveness Via Color Sensing

Technical Field and Background:
The fabrication of integrated circuits often involves one or more steps of electroplating a layer of conductive metal onto the surface of a semiconductor wafer. For example, in some IC fabrication procedures, an electroplating operation may be used to fill with metal the various features formed in the surface of a semiconductor wafer such as, for instance, the trenches and vias used as conductive paths between various circuit elements. The electroplated metal is oftentimes copper, but depending on the IC design, other metals may be appropriate and/or advantageous including ruthenium, palladium, iridium, rhodium, osmium, cobalt, nickel, gold, silver, and aluminum. In some embodiments, alloys of these metals may be appropriate and/or advantageous. In a typical electroplating operation, the surface of the wafer is exposed to an electroplating bath fluid which contains dissolved ions of the metal to be electroplated, and an electrical circuit is created between an electrode in the bath (which serves as an anode) and surface of the wafer (which serves as the cathode). Flow of current through this circuit upon application of an applied voltage causes electrons to flow to the cathode surface and reduce dissolved metal ions in its vicinity thereby resulting in the plating out of solution of neutral elemental metal onto the surface of the wafer. However, for this circuit to be completed and for electrochemical reduction of dissolved metal ions to occur, the surface of the wafer (serving as the circuit's cathode) must be, at least to a certain extent, relatively conductive. Accordingly, since the bare surface of a semiconductor wafer is not generally substantially conductive, the actual electroplating step in an electroplating operation is often preceded by the deposition of a conductive seed layer which provides the necessary conductive surface. Deposition of the seed layer may be accomplished by any feasible method of depositing the seed material. Suitable methods may include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), conformal film deposition (CFD), atomic layer deposition (ALD), and the like. Oftentimes, seed layer deposition and electroplating is followed by an edge bevel removal (EBR) operation that removes seed metal deposited at the edge of the wafer where its presence is not desired via the application of a thin viscous flow of etchant solution over the wafer's edge. However, oftentimes, after the seed layer is deposited, a wafer is removed from vacuum and exposed to clean room ambient air. In some instances, there could be a queue time ranging from a few minutes to several hours before the wafer is electroplated. Delay time and associated exposure to ambient air can cause oxidation of the seed layer—often referred to as “seed aging.” This oxide layer resulting from seed aging, being substantially non-conductive, may act to reduce electroplating efficiency or even prevent it from occurring. In addition, the surface wetting characteristics of the wafer may change also contributing to defects on the wafer. Post-electroplating voids and pits have been seen on pattern wafers as a result of too much pre-electroplating seed aging resulting in useless IC devices and thus negatively impacting overall wafer yields. Moreover, it is observed that seed aging effects are exacerbated in lower technology nodes—sub 22 nm, for example—where seed layers are generally very thin, for example, in some circumstances 50 Å or less. Seed dissolution and reduction in current density is also seen with thinner seed in localized spots deeper into the vias and trenches with higher denser pattern densities, also causing post-electroplating wafer defects. Accordingly, methods and apparatuses have been developed to deal with oxide layer reduction and/or removal, and further improvements on these methods and apparatuses are disclosed herein.

Invention Disclosure:
Disclosed are methods of preparing a semiconductor substrate having a metal seed layer for a subsequent electroplating operation. In some embodiments, the methods may include contacting the surface of the semiconductor substrate with a plasma to treat the surface by reducing metal oxides thereon and thereafter measuring a post-plasma-contact color signal from said surface, the color signal having one or more color components. The methods may then further include estimating the extent of the oxide reduction due to the plasma treatment based on the post-plasma contact color signal. In some embodiments, estimating the extent of the oxide reduction due to the plasma treatment is done based on the b* component of the post-plasma contact color signal. Also disclosed are plasma treatment apparatuses which may implement the foregoing methods.

[Assistant]
1. A method of preparing a semiconductor substrate having a metal seed layer for a subsequent electroplating operation, the method comprising:
contacting the surface of the semiconductor substrate with a plasma to treat the surface by reducing metal oxides thereon;
after contacting with the plasma, measuring a post-plasma-contact color signal from said surface, the color signal having one or more color components; and
estimating the extent of the oxide reduction due to the plasma treatment based, at least in part, on comparing the post-plasma contact color signal to one of: one or more reference color signals and a pre-plasma-contact color signal from said surface.

2. The method of claim 1, wherein estimating the extent of the oxide reduction due to the plasma treatment is done based on the b* component of the post-plasma contact color signal.

3. The method of claim 1, wherein estimating the extent of the oxide reduction due to the plasma treatment comprises:
comparing the post-plasma-contact color signal to one or more reference color signals.

4. The method of claim 3, wherein the comparing is done based on the b* component of the color signals.

5. The method of claim 1, wherein estimating the extent of the oxide reduction due to the plasma treatment comprises:
calculating one or more metrics, each of which is indicative of the difference between the post-plasma-contact color signal and a reference color signal from a set of one or more reference color signals.

6. The method of claim 5, wherein each metric is monotonically related to the absolute value of the difference between the b* component of the post-plasma-contact color signal and the b* component of a reference color signal.

7. The method of claim 1, further comprising:
before contacting with the plasma, measuring a pre-plasma-contact color signal from said surface, the color signal having one or more color components; and
wherein estimating the extent of the oxide reduction due to the plasma treatment comprises:
comparing the pre- and post-plasma-contact color signals.

8. The method of claim 7, wherein the comparing is done based on the b* component of the color signals.

9. The method of claim 7, wherein estimating the extent of the oxide reduction due to the plasma treatment comprises:
calculating a metric which is indicative of the difference between the pre- and post-plasma-contact color signals.

10. The method of claim 9, wherein the metric is monotonically related to the absolute value of the difference between the b* component of the pre- and post-plasma-contact color signals.

11. The method of claim 1, wherein the plasma contains hydrogen radicals.

12. The method of claim 1, wherein the metal is copper.

13. The method of claim 1, wherein the metal is cobalt.

14. The method of claim 1, wherein measuring the post-plasma-contact color signal is performed with a color sensor located about 0.1-5″ from the substrate surface during the measuring.

15. The method of claim 14, wherein measuring the post-plasma-contact color signal is performed with a color sensor located about 0.4-1″ from the substrate surface during the measuring.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Display Panel And Goa Circuit

Technical Field and Background:
The basic structure of a traditional TFT-LCD display panel using GOA (Gate Driver On Array) is shown in FIG. 1 . The display panel 1 includes a display area 10 , a fan-out area 11 , source-chip on films (S-COF) 12 , a printed circuit board (PCB) 13 , and a GOA circuit is disposed between the display area 10 and the fan-out area 11 . The gate driver of the traditional liquid crystal panel scans the thin film transistor (TFT), and charges a pixel electrode through a data line. A liquid crystal rotates under the influence of an electric field to guide light to display. The long charging time leads to a long liquid crystal response time, and makes more crosstalk between the pixel electrodes. Therefore, it is needed to provide a new display panel and a new GOA circuit, to increase the charging speed of the pixel.

Invention Disclosure:
The present invention relates to a display panel, having a display area and a fan-out area, and a GOA circuit. The GOA circuit includes a plurality of stage pre-charge modules, arranged for connecting output terminals of two adjacent gates in the GOA circuit in the fan-out area to two corresponding adjacent gate line outputs in the display area respectively. Each of the stage pre-charge modules includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor and a sixth thin film transistor.

[Assistant]
1. A display panel, having a display area and a fan-out area, and a GOA (Gate On Array, GOA) circuit, the display panel comprising:
a plurality of stage pre-charge modules, arranged for connecting output terminals of two adjacent gates in the GOA circuit in the fan-out area to two corresponding adjacent gate line outputs in the display area respectively, each of the stage pre-charge modules comprises:
a first thin film transistor, a source and a gate of the first thin film transistor being connected to a first output terminal at one of the two adjacent gates, a drain of the first thin film transistor being connected to a first gate line output;
a second thin film transistor, a gate of the second thin film transistor being connected to the first output terminal at the one gate, a drain of the second thin film transistor being connected to a previous stage pre-charge module;
a third thin film transistor, a gate of the third thin film transistor being connected to the first output terminal at the one gate, a drain of the third thin film transistor being connected to the first gate line output;
a fourth thin film transistor, a drain of the fourth thin film transistor being connected to a source of the third thin film transistor; a gate of the fourth thin film transistor being connected to a second output terminal at the other of the two adjacent gates, a source of the fourth thin film transistor being connected to a second gate line output;
a fifth thin film transistor, a gate of the fifth thin film transistor being connected to the second output terminal at the other gate, a source of the fifth thin film transistor being connected to the second output terminal, a drain of the fifth thin film transistor being connected to the second gate line output; and
a sixth thin film transistor, a gate of the sixth thin film transistor being connected to the second output terminal at the other gate, a drain of the sixth thin film transistor being connected to the second gate line output, a source of the sixth thin film transistor being connected to a next stage pre-charge module;
wherein charge waveforms of the first gate output terminal and the second gate output terminal partly overlap.

2. A display panel, having a display area and a fan-out area, and a GOA circuit, the display panel comprising:
a plurality of stage pre-charge modules, arranged for connecting output terminals of two adjacent gates in the GOA circuit in the fan-out area to two corresponding adjacent gate line outputs in the display area respectively, each of the stage pre-charge modules comprises:
a first thin film transistor, a source and a gate of the first thin film transistor being connected to a first output terminal at one of the two adjacent gates, a drain of the first thin film transistor being connected to a first gate line output;
a second thin film transistor, a gate of the second thin film transistor being connected to the first output terminal at the one gate, a drain of the second thin film transistor being connected to a previous stage pre-charge module;
a third thin film transistor, a gate of the third thin film transistor being connected to the first output terminal at the one gate, a drain of the third thin film transistor being connected to the first gate line output;
a fourth thin film transistor, a drain of the fourth thin film transistor being connected to a source of the third thin film transistor; a gate of the fourth thin film transistor being connected to a second output terminal at the other of the two adjacent gates, a source of the fourth thin film transistor being connected to a second gate line output;
a fifth thin film transistor, a gate of the fifth thin film transistor being connected to the second output terminal at the other gate, a source of the fifth thin film transistor being connected to the second output terminal, a drain of the fifth thin film transistor being connected to the second gate line output; and
a sixth thin film transistor, a gate of the sixth thin film transistor being connected to the second output terminal at the other gate, a drain of the sixth thin film transistor being connected to the second gate line output, a source of the sixth thin film transistor being connected to a next stage pre-charge module.

3. The display panel of claim 2, wherein when the first gate output terminal is a high voltage level bit, the second gate output terminal is a low voltage level bit, the first thin film transistor, the third thin film transistor, and the fourth thin film transistor are turned on, the second thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are turned off, and the first gate line output and the second gate line output are both high voltage level bits.

4. The display panel of claim 2, wherein when the first gate output terminal is a low voltage level bit, the second gate output terminal is a high voltage level bit, the first thin film transistor, the third thin film transistor, and the fourth thin film transistor are turned off, the second thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are turned on, and the first gate line output is a low voltage level bit, the second gate line output is a high voltage level bit.

5. The display panel of claim 2, wherein when the first gate output terminal and the second gate output terminal are both low voltage level bits, the first thin film transistor, the third thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are turned off, the second thin film transistor and the fourth thin film transistor are turned on, and the first gate line output and the second gate line output are both low voltage level bits.

6. A GOA circuit, used in a display device, the display device having a display area and a fan-out area, the GOA circuit comprising:
a plurality of stage pre-charge modules, arranged for connecting output terminals of two adjacent gates in the GOA circuit in the fan-out area to two corresponding adjacent gate line outputs in the display area respectively, each of the stage pre-charge modules comprises:
a first thin film transistor, a source and a gate of the first thin film transistor being connected to a first output terminal at one of the two adjacent gates, a drain of the first thin film transistor being connected to a first gate line output;
a second thin film transistor, a gate of the second thin film transistor being connected to the first output terminal at the one gate, a drain of the second thin film transistor being connected to a previous stage pre-charge module;
a third thin film transistor, a gate of the third thin film transistor being connected to the first output terminal at the one gate, a drain of the third thin film transistor being connected to the first gate line output;
a fourth thin film transistor, a drain of the fourth thin film transistor being connected to a source of the third thin film transistor; a gate of the fourth thin film transistor being connected to a second output terminal at the other of the two adjacent gates, a source of the fourth thin film transistor being connected to a second gate line output;
a fifth thin film transistor, a gate of the fifth thin film transistor being connected to the second output terminal at the other gate, a source of the fifth thin film transistor being connected to the second output terminal, a drain of the fifth thin film transistor being connected to the second gate line output; and
a sixth thin film transistor, a gate of the sixth thin film transistor being connected to the second output terminal at the other gate, a drain of the sixth thin film transistor being connected to the second gate line output, a source of the sixth thin film transistor being connected to a next stage pre-charge module.

7. The GOA circuit of claim 6, wherein when the first gate output terminal is a high voltage level bit, the second gate output terminal is a low voltage level bit, the first thin film transistor, the third thin film transistor, and the fourth thin film transistor are turned on, the second thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are turned off, and the first gate line output and the second gate line output are both high voltage level bits.

8. The GOA circuit of claim 6, wherein when the first gate output terminal is a low voltage level bit, the second gate output terminal is a high voltage level bit, the first thin film transistor, the third thin film transistor, and the fourth thin film transistor are turned off, the second thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are turned on, and the first gate line output is a low voltage level bit, the second gate line output is a high voltage level bit.

9. The GOA circuit of claim 6, wherein when the first gate output terminal and the second gate output terminal are both low voltage level bits, the first thin film transistor, the third thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are turned off, the second thin film transistor and the fourth thin film transistor are turned on, and the first gate line output and the second gate line output are both low voltage level bits.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Air Suspension

Technical Field and Background:
1. Field of the Invention An embodiment of the present invention relates to an air suspension. 2. Related Art A motorcycle is provided with a suspension for, for example, comfort riding. As the suspension of the motorcycle, there is an air suspension having an air spring structure including a damper main body, which includes, for example, a cylinder in which a piston slides, and a diaphragm structure, which includes a diaphragm in which air is filled. As the air suspension, for example, there is an air suspension of a so-called upright type in which a piston rod is present on a vehicle body side and a cylinder of a damper main body is present on an axle side. In the air suspension of the upright type, since the diaphragm structure is located on the vehicle body side, a valve section for filling the air in the diaphragm is provided in an upper part of the diaphragm structure. In recent years, for example, an air suspension of a so-called inverted type is often used in which a cylinder of a damper main body is present on a vehicle body side and a piston rod is present on an axle side. In the air suspension of the inverted type, since the diaphragm structure is located on the axle side, a valve section for filling the air in the diaphragm is provided in a lower part of the diaphragm structure.

Invention Disclosure:
An air suspension in an embodiment includes: a cylinder; a piston rod; a rod-side member disposed on the lower end side of the piston rod; a diaphragm; an axle-side attachment member having an upper end side of which is fixed to an opening at a lower end of the rod-side member, the axle-side attachment member including a fixing section for fixing the piston rod and an attachment hole joined to an axle; a gas passage formed in the axle-side attachment member, one end of the gas passage being opened to an upper end face of the axle-side attachment member and the other end of the gas passage being opened to a side section of the axle-side attachment member; and a valve section provided at the opening of the other end of the gas passage.

[Assistant]
1. An air suspension comprising:
a cylinder including, on an upper end side thereof, a vehicle-body-side attachment member joined to a vehicle body;
a piston rod including a piston on an upper end side thereof and inserted into the cylinder together with the piston;
a cylindrical rod-side member disposed on a lower end side of the piston rod and opened at an upper end of the rod-side member and a lower end thereof;
a diaphragm having an upper end of which is fixed to a side of the cylinder and a lower end of which is fixed to the rod-side member, the diaphragm forming an air chamber around the piston rod;
an axle-side attachment member having an upper end side of which is fixed to the opening at the lower end of the rod-side member, the axle-side attachment member which includes, on an upper end face thereof, a fixing section fixing a lower end of the piston rod and, on a lower end side thereof, an attachment hole joined to an axle;
a gas passage formed in the axle-side attachment member extending across an axis of the piston rod, one end of the gas passage being opened to the upper end face of the axle-side attachment member and the other end of the gas passage being opened to a side section of the axle-side attachment member;
a valve section provided at the opening of the other end of the gas passage; and
an annular groove that is provided at the side section of the axle-side attachment member so as to surround the gas passage and has a screw section formed on an outer periphery of the annular groove, wherein
the valve section includes:
a valve main body that is inserted into the gas passage and guides gas supplied from an outside to the gas passage; and
a valve cap that has a screw section on an inner periphery thereof that mates with the screw section of the annular groove so as to seal the valve main body.

2. The air suspension according to claim 1, wherein the other end of the gas passage is opened to the side section of the axle-side attachment member between the fixing section and the attachment hole.

3. The air suspension according to claim 2, wherein the gas passage is formed by an L-shaped through-hole including a bent section.

4. The air suspension according to claim 3, wherein
the valve cap is attached in a state where at least a part of the valve cap is inserted into the annular groove.

5. The air suspension according to claim 4, further comprising:
a cylindrical cover having a lower end of which is fixed to the rod-side member and an upper end of which is opened, the cylindrical cover covering an outer circumference of the diaphragm.

6. The air suspension according to claim 3, further comprising:
a cylindrical cover having a lower end of which is fixed to the rod-side member and an upper end of which is opened, the cylindrical cover covering an outer circumference of the diaphragm.

7. The air suspension according to claim 2, wherein
the valve cap is attached in a state where at least a part of the valve cap is inserted into the annular groove.

8. The air suspension according to claim 7, further comprising:
a cylindrical cover having a lower end of which is fixed to the rod-side member and an upper end of which is opened, the cylindrical cover covering an outer circumference of the diaphragm.

9. The air suspension according to claim 2, further comprising:
a cylindrical cover having a lower end of which is fixed to the rod-side member and an upper end of which is opened, the cylindrical cover covering an outer circumference of the diaphragm.

10. The air suspension according to claim 1, wherein the gas passage is formed by an L-shaped through-hole including a bent section.

11. The air suspension according to claim 10, wherein
the valve cap is attached in a state where at least a part of the valve cap is inserted into the annular groove.

12. The air suspension according to claim 11, further comprising:
a cylindrical cover having a lower end of which is fixed to the rod-side member and an upper end of which is opened, the cylindrical cover covering an outer circumference of the diaphragm.

13. The air suspension according to claim 10, further comprising:
a cylindrical cover having a lower end of which is fixed to the rod-side member and an upper end of which is opened, the cylindrical cover covering an outer circumference of the diaphragm.

14. The air suspension according to claim 1, wherein
the valve cap is attached in a state where at least a part of the valve cap is inserted into the annular groove.

15. The air suspension according to claim 14, further comprising:
a cylindrical cover having a lower end of which is fixed to the rod-side member and an upper end of which is opened, the cylindrical cover covering an outer circumference of the diaphragm.

16. The air suspension according to claim 1, further comprising:
a cylindrical cover having a lower end of which is fixed to the rod-side member and an upper end of which is opened, the cylindrical cover covering an outer circumference of the diaphragm.

17. The air suspension according to claim 1, wherein
the gas passage has a vertical portion extending in an axial direction of the piston rod and a horizontal portion extending in a direction perpendicular to the axial direction,
the vertical portion is longer than the fixing section in the axial direction.

18. The air suspension according to claim 17, wherein
the vertical portion extends parallel to the piston rod in the axial direction.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Semiconductor Device And Electronic Device

Technical Field and Background:
In the related art, semiconductor devices having a heat-dissipation structure have been known. With recent improvement in performance of semiconductor devices, with an increase in processing rate, for example, an amount of heat generated from a semiconductor chip tends to increase. Thus, it would be significant if a semiconductor device could have a heat-dissipation structure that is more efficient.

Invention Disclosure:
According to one embodiment, a semiconductor device includes a first substrate, a second substrate, a first electronic component, a heat-conducting layer, a covering portion, and a heat-transporting portion. The first substrate has a first face and the second substrate has a second face and a third face. The first electronic component has a fourth face and a fifth face. The heat-conducting layer covers the third face and the fifth face. The covering portion covers at least the heat-conducting layer. The heat-transporting portion thermally connects the heat-conducting layer and the first substrate, and is located outside the second substrate and outside the covering portion.

[Assistant]
1. A semiconductor device comprising:
a first substrate having a first face;
a second substrate disposed on the first face, the second substrate having a second face that faces the first face and a third face that is opposite to the second face;
a first electronic component disposed on the third face, the first electronic component having a fourth face that faces the third face and a fifth face that is opposite to the fourth face;
a heat-conducting layer covering the third face and the fifth face;
a covering portion on top of the heat-conducting layer, which is on the second substrate, the covering portion covering at least the heat-conducting layer; and
a heat-transporting portion thermally connecting the heat-conducting layer and the first substrate, the heat-transporting portion being located outside the second substrate and outside the covering portion.

2. The semiconductor device according to claim 1, wherein a second electronic component is disposed on the first face of the first substrate, and
the second substrate includes a first side facing the second electronic component and a second side different from the first side and the heat-transporting portion is disposed on the second side.

3. The semiconductor device according to claim 1, wherein the heat-conducting layer and the first substrate are thermally connected to each other by a plurality of the heat-transporting portions.

4. The semiconductor device according to claim 3, wherein the heat-transporting portions are arranged to be denser in the central portion of the side of the second substrate than in the end parts of the side thereof.

5. The semiconductor device according to claim 1, wherein an opening is formed in the heat-transporting portion.

6. The semiconductor device according to claim 1, wherein the covering portion includes a heat-dissipating portion on a surface of the covering portion, the heat-dissipating portion being thermally connected to the heat-conducting layer.

7. The semiconductor device according to claim 1, further comprising a connecting portion disposed in a state in which the connecting portion is thermally connected to the heat-conducting layer, the connecting portion being capable of being thermally connected to the plurality of heat-transporting portions,
wherein the heat-conducting layer and the heat-transporting portions are thermally connected to each other via at least one connecting portion.

8. The semiconductor device according to claim 1, wherein the second substrate includes a via penetrating the second face and the third face and the heat-conducting layer and the first substrate are thermally connected to each other through the via.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Semiconductor Devices Having Multiple Gate Structures And Methods Of Manufacturing Such Devices

Technical Field and Background:
Semiconductor devices are becoming more highly integrated in response to demand for smaller, lower power electronic devices. Fin field effect transistors (FinFET) that have a three-dimensional channel structure have been developed that may reduce short channel effects that can arise with increasingly high levels of device integration. In addition, research into techniques for increasing charge carrier mobility are currently in progress.

Invention Disclosure:
A semiconductor device includes a substrate having a first region and a second region, a plurality of first gate structures in the first region, the first gate structures being spaced apart from each other by a first distance, a plurality of second gate structures in the second region, the second gate structures being spaced apart from each other by a second distance, a first spacer on sidewalls of the first gate structures, a dielectric layer on the first spacer, a second spacer on sidewalls of the second gate structures, and a third spacer on the second spacer.

[Assistant]
1. A semiconductor device, comprising:
a substrate having a first region and a second region;
a plurality of first gate structures in the first region, the first gate structures being spaced apart from each other by a first distance;
a plurality of second gate structures in the second region, the second gate structures being spaced apart from each other by a second distance;
a plurality of first spacers on sidewalls of the respective first gate structures;
a dielectric layer on outer sidewalls of the respective first spacers;
a plurality of second spacers on sidewalls of the respective second gate structures; and
a plurality of third spacers on outer sidewalls of the respective second spacers,
wherein a sum of a first thickness of a first of the first spacers and a second thickness of the dielectric layer that are on a sidewall of a first of the first gate structures is substantially equal to a sum of a third thickness of a first of the second spacers and a fourth thickness of a first of the third spacers that are on a sidewall of a first of the second gate structures.

2. The semiconductor device of claim 1, wherein the first thickness of the first of the first spacers is substantially equal to the third thickness of the first of the second spacers; and
wherein the second thickness of the dielectric layer is substantially equal to the fourth thickness of the first of the third spacers.

3. The semiconductor device of claim 1, wherein the first distance is substantially equal to the second distance; and
wherein a first gap that is between portions of the dielectric layer that are on facing sidewalls of an adjacent pair of the first gate structures is substantially equal to a second gap between the third spacers that are on facing sidewalls of an adjacent pair of the second gate structures.

4. The semiconductor device of claim 3, further comprising an etch stop layer on sidewalls of the dielectric layer and the third spacers,
wherein a third gap between portions of the etch stop layer that axe on facing sidewalls of the adjacent pair of the first gate structures is substantially equal to a fourth gap between portions of the etch stop layer that are on facing sidewalls of the adjacent pair of the second gate structures.

5. The semiconductor device of claim 1, further comprising at least a first active fin that extends in a first direction in the first region to cross under the first gate structures;
wherein the first spacers have an L-shaped cross-section.

6. The semiconductor device of claim 5, wherein the first of the first spacers has a parallel portion and a perpendicular portion with respect to an upper surface of the substrate, a length of the parallel portion in the first direction being substantially equal to or greater than the sum of the first thickness and the second thickness.

7. The semiconductor device of claim 1, further comprising a plurality of first embedded source/drain regions on opposed sides of the first gate structures,
wherein the dielectric layer covers upper surfaces of the first embedded source/drain regions.

8. The semiconductor device of claim 5, further comprising at least a second active fin that extends in the first direction in the second region to cross under the second gate structures;
wherein the second spacers have an L-shaped cross-section.

9. The semiconductor device of claim 8, wherein the first of the second spacers has a parallel portion and a perpendicular portion with respect to an upper surface of the substrate, a length of the parallel portion in the first direction being greater than the sum of the third thickness and the fourth thickness.

10. The semiconductor device of claim 8, wherein the third spacers have an L-shaped cross-section.

11. The semiconductor device of claim 1, further comprising a plurality of second embedded source/drain regions on opposed sides of the second gate structures,
wherein the second embedded source/drain regions comprise silicon germanium (SiGe) doped with a P-type impurity.

12. The semiconductor device of claim 11, wherein the second embedded source/drain regions include a plurality of regions having different germanium (Ge) concentration from each other.

13. A semiconductor device, comprising:
a substrate having a first region and a second region, the first region including a plurality of first active fins and the second region including a plurality of second active fins;
a plurality of first gate structures that cross over the first active fins in the first region, the first gate structures being spaced apart from each other by a first distance;
a plurality of first embedded source/drain regions on opposed sides of the first gate structures;
a plurality of first spacers that have L-shaped cross-sections on sidewalls of the respective first gate structures;
a dielectric layer on outer sidewalls of the first spacers and on upper surfaces of the first embedded source/drain regions;
a plurality of second gate structures that cross over the second active fins in the second region, the second gate structures being spaced apart from each other by a second distance;
a plurality of second embedded source/drain regions on opposed sides of the second gate structures;
a plurality of second spacers that have L-shaped cross-sections on sidewalls of the respective second gate structures; and
a plurality of third spacers that have L-shaped cross-sections on outer sidewalls of the second spacers.

14. The semiconductor device of claim 13, wherein a sum of a first thickness of a first of the first spacers that is on a first of the first gate structures and a second thickness of the dielectric layer that is on a sidewall of the first of the first gate structures is substantially equal to a sum of a third thickness of a first of the second spacers that is on a first of the second gate structures and a fourth thickness of a first of the third spacers that is on a sidewall of the first of the second spacers.

15. A semiconductor device, comprising:
a substrate having an upper surface that extends in a first direction and in a second direction that is perpendicular to the first direction;
a first active fin extending in the first direction in a first region of the substrate;
a first gate structure that crosses over the first active fin in the first region of the substrate;
a first embedded source/drain region on a first side of the first gate structure;
a pair of first spacers having respective inner sidewalk that are directly on respective opposed sidewalls of the first gate structure, each of the first spacers including a first portion that extends in the first direction and a second portion that extends in a third direction that is perpendicular to both the first direction and the second direction;
a dielectric layer that comprises a material different from a material of the first spacers directly on outer sidewalls of the respective first spacers;
a second active fin extending in the first direction in a second region of the substrate;
a second gate structure that crosses over the second active fin in the second region of the substrate;
a second embedded source/drain region on a first side of the second gate structure;
a pair of second spacers having respective inner sidewalls that are directly on respective opposed sidewalls of the second gate structure, each of the second spacers including a first portion that extends in the first direction and a second portion that extends in the third direction;
a pair of third spacers that comprises a material different from a material of the second spacers directly on outer sidewalls of the respective second spacers; and
an etch stop layer,
wherein the dielectric layer extends across an upper surface of the first embedded source/drain region while the third spacer does not extend across an upper surface of the second embedded source/drain region, and
wherein the etch stop layer directly contacts an upper surface of the second embedded source/drain region and directly contacts a portion of the dielectric layer that is on an upper surface of the first embedded source/drain region.

16. The semiconductor device of claim 15, wherein each of the first spacers has a first thickness, the dielectric layer has a second thickness, each of the second spacers has a third thickness and each of the third spacers has a fourth thickness, and wherein a sum of the first thickness and the second thickness is substantially equal to a sum of the third thickness and the fourth thickness.

17. The semiconductor device of claim 16, wherein the first thickness is substantially equal to the third thickness and the second thickness is substantially equal to the fourth thickness.

18. The semiconductor device of claim 15, wherein the first embedded source/drain region has an upper surface that is above the upper surface of the substrate, and the second embedded source/drain region is coplanar with the upper surface of the substrate.

19. The semiconductor device of claim 15, wherein the third spacers each have a first portion that extends in the first direction and a second portion that extends in the third direction.

20. The semiconductor device of claim 14, wherein the first distance is substantially equal to the second distance; and
wherein a first gap that is between portions of the dielectric layer that are on facing sidewalls of an adjacent pair of the first gate structures is substantially equal to a second gap between the third spacers that are on facing sidewalls of an adjacent pair of the second gate structures.