[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Steering Device

Technical Field and Background:
In a steering device, in succession to a primary collision in which a vehicle collides with another vehicle, a secondary collision in which the driver collides with a steering wheel occurs. In order to absorb shock in the secondary collision, various structures in which a part of a steering column releases from the vehicle body, and is moved in the direction of the column shaft have been proposed. In FIG. 9 of Patent Reference 1, for example, a pair of engaging cutouts which extend parallel to the direction of a column shaft are disposed in a vehicle body-side bracket fixed to the vehicle body. A column-side bracket is supported through a pair of engaging capsules which are held by a plurality of engaging pins, by the engaging cutouts respectively. The engaging capsules are coupled and fixed to the column-side bracket through bolts which are passed through the engaging cutouts, respectively. In a secondary collision, the plurality of engaging pins holding the engaging capsules are broken, whereby the engaging capsules are caused to release from the corresponding engaging cutouts, and the bolts, the engaging capsules, and the column bracket are caused to co-move with one another in the column shaft direction.

Invention Disclosure:
A resin pin which is passed through a first resin-pin passing hole of a first plate, and a second resin-pin passing hole of a second plate to couple the second plate to a predetermined position of the first plate is sheared in a secondary collision, and causes the second plate to release from the predetermined position in a column movement direction. A slide plate which extends along the upper surface of the first plate has a resin-pin visual check hole. A highly hard collar is received by the second plate, placed in the first resin-pin passing hole, and fitted to a shaft portion of the resin pin. In the resin pin, axial elastic projections which apply a pressing and urging force to the slide plate are disposed at positions avoiding a range where, in a secondary collision, the resin-pin visual check hole is passed in the column movement direction.

[Assistant]
1. A steering device comprising:
a stationary bracket which is fixed to a vehicle body-side member, and which includes a first plate in which a first resin-pin passing hole, and a first bolt passing hole configured by a long hole that extends in a column movement direction in a secondary collision are formed;
a movable jacket which is configured to rotatably support a steering shaft in which a steering member is coupled to one end;
a movable bracket which is configured to support the movable jacket in a manner that, in a secondary collision, the movable bracket is moved together with the movable jacket in the column movement direction, and which includes a second plate that is opposed to a lower surface of the first plate, the second plate in which a second resin-pin passing hole and a second bolt passing hole are formed;
a suspension mechanism which includes: a slide plate in which a third bolt passing hole and a resin-pin visual check hole are formed along an upper surface of the first plate; and a suspension bolt which is passed sequentially through the third bolt passing hole, the first bolt passing hole, and the second bolt passing hole to couple the first plate and the second plate together, thereby suspending the movable jacket through the movable bracket, the suspension mechanism which is movable in a corresponding column movement direction in a secondary collision;
a resin pin which has an axial end surface opposed to the resin-pin visual check hole, which is passed through the first resin-pin passing hole and the second resin-pin passing hole to couple the second plate to a predetermined position of the first plate, and which, in a secondary collision, is configured to cause the second plate to release from the predetermined position in the column movement direction; and
a collar which is fitted to the resin pin in a state where the collar is received directly or indirectly by a member that is suspended by the suspension mechanism, and which is higher in hardness than the resin pin, wherein,
in one of the resin pin and the collar, an elastic projection which is configured to directly or indirectly urge the slide plate, and which projects in an axial direction is disposed at a position avoiding a range where, in a secondary collision, the resin-pin visual check hole is passed in the column movement direction.

2. The steering device according to claim 1, wherein
an inner circumference of the first resin-pin passing hole, and an outer circumference of the collar are formed into a laterally long shape which extends in a direction that is perpendicular to the column movement direction, thereby causing rotation of the collar to be restricted by the first resin-pin passing hole,
the resin pin includes: a shaft portion which is passed through the collar; and a head flange which is coupled to one end of the shaft portion,
the head flange has: a first surface which is opposed to the slide plate; and a second surface which is opposed to an end surface of the collar,
the elastic projection is placed at a position avoiding the resin-pin visual check hole in the first surface of the head flange, and
a rotation restricting convex portion which is disposed on at least one of the second surface of the head flange and the end surface of the collar is fitted to a rotation restricting concave portion which is disposed on the other surface, thereby restricting relative rotation of the resin pin and the collar.

3. The steering device according to claim 1, wherein
the resin pin includes: a shaft portion which is passed through the collar; and a head flange which is coupled to one end of the shaft portion,
an inner circumference of the first resin-pin passing hole includes a flat portion which is engaged with a flat portion disposed on an outer circumference of the head flange, thereby restricting rotation of the resin pin,
the head flange has: a first surface which is opposed to the slide plate; and a second surface which is opposed to an end surface of the collar, and
the elastic projection is placed at a position avoiding the resin-pin visual check hole in the first surface of the head flange.

4. The steering device according to claim 1, wherein
the resin pin includes: a shaft portion which is passed through the collar; and a head flange which is coupled to one end of the shaft portion,
the head flange has: a first surface which is opposed to the slide plate; and a second surface which is opposed to an end surface of the collar, and
the elastic projection is disposed on the second surface of the head flange.

5. The steering device according to claim 1, wherein
the collar includes: a first collar which is placed in the first resin-pin passing hole, and which is press-fitted to the resin pin; and a second collar which is placed in the second resin-pin passing hole, and which is loose-fitted to the resin pin, and
the elastic projection is disposed on at least one of opposing surfaces the first collar and the second collar.

6. The steering device according to claim 1, wherein
the resin-pin visual check hole includes a collar visual check region through which a part of the collar can be visually checked.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Multi-Mode Interference Coupler

Technical Field and Background:
Multimode interference (MMI) couplers are used for a wide variety of applications in photonic integrated circuits (PICs) such as splitters, combiners, and multiplexers. These applications take advantage of the variability of the refractive index of MIMI material, which can be heated as a means of controlling its behavior. As one of the basic MMI couplers, a 2×2 3 dB MMI coupler is a fundamental building block of photonic integrated circuits (PIC). FIG. 1A is a schematic diagram illustrating a conventional 3 dB 2×2 MMI coupler 100 having an MMI region 111 of a rectangular shape defined by a region length 112 equal to L MMI and a region width 114 equal to W MMI . The coupler 100 may be terminated by two pairs of ports at opposite ends of the MMI region 111 , one input pair of a first port 101 and a second port 102 at a first end 113 of the MMI region 111 , and another pair of third port 103 and fourth port 104 at a second end 115 of the MMI region 111 . The operating principle of such a coupler is defined by well-known MMI self-imaging theory. When a single-mode optical signal is launched at either the first port 101 or the second port 102 , the 2×2 coupler 100 behaves as a 3 dB power splitter, such as a Y-junction. Under such behavior, the single-mode optical signal propagates through the MMI region 111 , resulting in two imaging mode optical signals with a 90-degree phase difference to emerge, one at each of the third port 103 and the fourth port 104 . This 90-degree phase difference between the two output ports is an attractive feature in many applications such as broadband switches and coherent communications. The broadband wavelength response also makes the 2×2 MMI coupler 100 a better candidate for directional 3 dB couplers. Each pair of ports ( 101 and 102 ) or ( 103 and 104 ) at either end of the MMI region 111 is spaced apart by a port gap 117 equal to D gap . According to MMI self-imaging theory, D gap must at least be equal to ¼ W MMI . In conventional prior art practice, the region width W MMI and the region length L MMI are tuned when designing the 2×2 MMI coupler 100 by finding a self-imaging point that meets a specific desired performance FIG. 1B illustrates another configuration of a prior art rectangular K×M MMI coupler 200 with a rectangular MMI region 211 for applications requiring more than two ports at either a first end 213 or a second end 215 of the MMI region 211 . The coupler 200 is terminated by a first set of K ports 201 at the first end 213 , and a second set of M ports 202 at the second end 215 , where K and M are integers greater than 0. The K×M coupler 200 follows similar operating principles to those known for the 2×2 coupler 100 shown in FIG. 1A . With reference to FIG. 1C , trapezoidal coupler geometry is also conventionally used for the MMI region 311 . FIG. 1C illustrates a K×M MMI coupler 300 with a trapezoidal MMI region 311 terminated by a first set of K ports 301 at a first end 313 thereof, and by a second set of M ports 302 at a second end 315 thereof, where K and M are greater than 1. The port positioning in trapezoidal couplers is conventionally determined by the self-imaging theory disclosed by Soldano, Lucas B., and Erik Pennings, in a paper entitled “Optical multi-mode interference devices based on self-imaging: principles and applications” published in Lightwave Technology, Journal of 13.4, 1995, pages 615-627, which is incorporated herein by reference. Performance of the aforementioned prior art couplers, in terms of metrics, such as insertion losses, phase error and bandwidths, can be tuned only by modifying the width value W MMI and length value L MMI , thus leaving little room for design flexibility, in view of the fixed geometry of rectangular and trapezoidal MMI regions. Furthermore, rectangular and trapezoidal MMI region geometries disadvantageously introduce excess loss when coupling light out of the MMI region into a waveguide. In addition, the geometry and symmetry properties of the MMI region are susceptible to significant deviations from the intended dimensions as a result of variations in the fabrication process from run to run or even from wafer to wafer in lithography, etching, wafer thickness, and the like, thereby undermining the power balance and increasing the phase error of an optical signal propagating through the MMI region.

Invention Disclosure:
A multimode interference (MMI) coupler with an MMI region of curved edges, and a method of design and manufacturing by using a computerized optimization algorithm to determine a favorable set of segment widths for the MMI region for a predefined set of coupler design parameters.

[Assistant]
1. A multimode interference coupler comprising:
a multimode interference (MMI) region including:
first and second region ends separated by a region length along a longitudinal axis, and
first and second curved edges between the first and second region ends, defining the MMI region, which varies in width along the region length;
wherein each of the first and second curved edges includes a plurality of transitions, and varies in slope relative to the longitudinal axis on each side of each transition;
at least one port optically coupled to the first region end; and
at least one port optically coupled to the second region end;
wherein the plurality of transitions comprises a plurality of changes in curvature and at least four critical points with alternating changes in curvature and critical points in each of the first and second edges.

2. The coupler of claim 1, wherein the critical points comprise at least three peaks and at least two valleys in each of the first and second edges.

3. The coupler of claim 1, wherein the critical points comprise at least two peaks and at least three valleys in each of the first and second edges.

4. The coupler according to claim 1, wherein the MMI region includes a plurality of different widths, perpendicular to the longitudinal axis, each width corresponding to one of the plurality of transitions, spaced apart along the region length, defining adjacent segments; and wherein the first and second curved edges provide gradual transitions between the different widths.

5. The coupler according to claim 4, wherein the plurality of different widths correspond to 5 to 20 critical points comprising peaks and valleys spaced along each of the first and second edges.

6. The coupler of claim 5, wherein the plurality of different widths are equally spaced along the longitudinal axis.

7. The coupler of claim 6, wherein the plurality of different widths are symmetrical about a midpoint of the longitudinal axis.

8. The coupler of claim 4, wherein each of the at least one port optically coupled to the first and second region ends comprises two ports, wherein the first and second curved edges are symmetrical to each other about the longitudinal axis;
wherein the plurality of different widths corresponding to 5 to 20 peaks and valleys spaced along each of the first and second curved edges; and
wherein light entering one of the two ports optically coupled to the first region end is substantially equally split into the two ports optically coupled to the second region end, with a power unbalance of no more than 0.5 dB and an excess loss of no more than 0.5 dB.

9. The coupler of claim 8, wherein each of the plurality of different widths=1.5 μm+/−10%.

10. The coupler of claim 9, wherein the two ports coupled to the first region end are spaced apart by a first port gap;
wherein the two ports coupled to the second region end are spaced apart by a second port gap; and
wherein the first port gap=the second port gap=0.2 μm+/−50%.

11. The coupler of claim 10, wherein each of the ports coupled to the first and second region ends comprises:
a respective outer port side for optical coupling to an optical waveguide; and
a tapered section with a taper length equal to 1.0 μm+/−50%, a first taper width bordering the multimode interference region equal to 0.7 μm+/−20%, and a second taper width at the outer port side equal to 0.5 μm+/−20%.

12. A method of manufacturing a multimode interference (MMI) coupler comprising:
a multimode interference (MMI) region including:
first and second region ends separated by a region length along a longitudinal axis, and
first and second curved edges between the first and second region ends, defining the MIMI region, which varies in width along the region length, each of the first and second curved edges including a plurality of transitions and varying in slope relative to the longitudinal axis on each side of each transition;
at least one port optically coupled to the first region end; and
at least one port optically coupled to the second region end,
wherein the plurality of transitions comprises a plurality of changes in curvature and at least four critical points with alternating changes in curvature and critical points in each of the first and second edges;

13. The method of claim 12, wherein determining the first and second curved edges comprises:
a) generating a set of region widths, perpendicular to and spaced apart along the longitudinal axis, corresponding to the plurality of transitions, using the computerized optimization algorithm, thereby forming first and second interim edges; and
b) smoothing the first and second interim edges to generate the first and second curved edges forming critical points comprising at least two valleys and at least three peaks in each of the first and second curved edges.

14. The method of claim 13, further comprising setting the predefined widths range to between 80% and 120% of the predefined initial region width.

15. The method of claim 13, further comprising setting the set of region widths to between 8 to 20 region widths corresponding to critical points comprising between 5 and 20 peaks and valleys.

16. The method according to claim 12, wherein determining the first and second curved edges comprises:
i) randomly generating a set of interim region widths, perpendicular to and spaced apart along the longitudinal axis, corresponding to the plurality of transitions, within a predefined widths range approximate to a predefined initial region width, using the computerized optimization algorithm, thereby forming first and second interim edges;
ii) smoothing the first and second interim edges;
iii) determining output optical power at each of the ports optically coupled to the second region end relative to a predefined input optical power at one of the ports optically coupled to the first region end, by simulating the MMI coupler for the set of interim widths and the predefined set of design parameters;
iv) calculating a figure of merit from the output optical powers and the predefined input optical power;
v) repeating steps i) to iv) until the figure of merit exceeds a predefined performance limit for a working set of interim widths; and
vi) setting the working set of interim widths as the set of region widths.

17. The method of claim 16, wherein the step of smoothing the first and second interim edges comprises interpolating the working set of interim widths, using a computerized interpolation algorithm.

18. The method of claim 12, wherein the computerized optimization algorithm comprises one of a particle swarm optimization algorithm and a genetic optimization algorithm.

19. The method of claim 12, wherein the predefined set of design parameters comprises one or more parameters selected from the group consisting of: region length; numbers of ports; a semiconductor layer composition selected from the group consisting of SOI, SiN, Silicon on Saphire, InP, and GaAs; and an operational wavelength band selected from of the group consisting of O band, E band, S band, C band, L band, and U band.

20. The method of claim 12, further comprising measuring insertion loss of the MMI coupler by a test structure embedded within a large-scale integrated system, wherein the test structure comprises a cascade of a plurality of test couplers similar to the MMI coupler, optically coupled in a tandem arrangement.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Resonator Having Distributed Transconductance Elements

Technical Field and Background:
Resonators are used in various different circuits and integrated circuits (chips). Resonators can have a plurality of different resonant frequencies. Resonators include electrical circuits such as LC circuits which include an inductor and a capacitor. Some resonators include an array of capacitors, or more generally impedances, which are tuned by selectively switching capacitors in the array. Resonators are used to generate signals having a particular desired frequency. Filters may also use switched impedances to generate a desired narrowband passband function.

Invention Disclosure:
A method includes forming a resonator comprising a plurality of switched impedances spatially distributed within the resonator, selecting a resonant frequency for the resonator, and distributing two or more transconductance elements within the resonator based on the selected resonant frequency. Distributing the two or more transconductance elements may include non-uniformly distributing the two or more transconductance elements within the resonator.

[Assistant]
1. An apparatus comprising:
a resonator comprising:
a plurality of switched impedances spatially distributed within the resonator; and
a corresponding plurality of transconductance elements distributed within respective distances among the switched impedances;
wherein the resonator has a given desired resonant frequency and a given amplitude of response;
wherein combined pairs of the switched impedances and transconductance elements have respective parasitic resonant frequencies which are higher than the given desired resonant frequency and have respective amplitudes of response which are lower than the given amplitude of response; and
wherein a given distance between a given one of the switched impedances and a given one of the transconductance elements is controlled based on a relationship between an impedance value of the given switched impedance and a transconductance value of the given transconductance element.

2. The apparatus of claim 1 wherein the apparatus is a voltage controlled oscillator.

3. The apparatus of claim 2 wherein the voltage controlled oscillator comprises at least one of a wide-tuning range oscillator, a digitally controlled oscillator and a millimeter wave oscillator.

4. The apparatus of claim 1 wherein the apparatus is an active filter.

5. The apparatus of claim 4 wherein the active filter comprises at least one of a switched impedance filter, a switched capacitor transconductance filter and a programmable narrowband band select filter.

6. The apparatus of claim 1 wherein the switched impedances comprise a capacitor array.

7. The apparatus of claim 6 wherein:
one or more interconnects between capacitors in the capacitor array contribute respective parasitic inductances in the resonator; and
the transconductance elements are distributed within the capacitor array to reduce the parasitic inductances of the one or more interconnects.

8. The apparatus of claim 1 wherein:
the transconductance elements have associated therewith different transconductance values;
the switched impedances comprise capacitors having associated therewith different capacitance values; and
wherein the transconductance elements are distributed within the resonator such that the transconductance values are proportional to the capacitance values.

9. The apparatus of claim 8 wherein the given distance between the given switched impedance and the given transconductance element is controlled based on a relationship between the capacitance value of the given switched impedance and the transconductance value of the given transconductance element.

10. The apparatus of claim 1 wherein:
the transconductance elements have associated therewith different transconductance values;
the switched impedances comprise inductors having associated therewith different inductance values; and
wherein the transconductance elements are distributed within the resonator such that the transconductance values are proportional to the inductance values.

11. The apparatus of claim 10 wherein the given distance between the given switched impedance and the given transconductance element is controlled based on a relationship between the inductance value of the given switched impedance and the transconductance value of the given transconductance element.

12. The apparatus of claim 1 wherein the transconductance elements are distributed based on a target narrowband bandpass transfer function.

13. The apparatus of claim 1 wherein an operating frequency of the resonator is 20 gigahertz or greater.

14. The apparatus of claim 1 wherein physical dimensions of the apparatus are greater than 1/100 of a wavelength of the apparatus.

15. The apparatus of claim 1 wherein physical dimensions of the apparatus are greater than 1/1000 of a wavelength of the apparatus.

16. An integrated circuit comprising:
a resonator comprising:
a plurality of switched impedances spatially distributed within the resonator; and
a corresponding plurality of transconductance elements distributed within respective distances among the switched impedances;
wherein the resonator has a given desired resonant frequency and a given amplitude of response;
wherein combined pairs of the switched impedances and transconductance elements have respective parasitic resonant frequencies which are higher than the given desired resonant frequency and have respective amplitudes of response which are lower than the given amplitude of response; and
wherein a given distance between a given one of the switched impedances and a given one of the transconductance elements is controlled based on a relationship between an impedance value of the given switched impedance and a transconductance value of the given transconductance element.

17. A voltage controlled oscillator comprising the integrated circuit of claim 16.

18. An active filter comprising the integrated circuit of claim 16.

19. A method comprising:
forming a resonator comprising a plurality of switched impedances spatially distributed within the resonator; and
forming a plurality of transconductance elements within respective distances among the switched impedances;
wherein the resonator has a given desired resonant frequency and a given amplitude of response;
wherein combined pairs of the switched impedances and transconductance elements have respective parasitic resonant frequencies which are higher than the given desired resonant frequency and have respective amplitudes of response which are lower than the given amplitude of response; and
wherein a given distance between a given one of the switched impedances and a given one of the transconductance elements is controlled based on a relationship between an impedance value of the given switched impedance and a transconductance value of the given transconductance element.

20. The method of claim 19 further comprising forming at least one of a voltage controlled oscillator and a resonator comprising the resonator.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Semiconductor Circuit Device, Oscillator, Electronic Apparatus, And Moving Object

Technical Field and Background:
1. Technical Field The present invention relates to a semiconductor circuit device, an oscillator, an electronic apparatus, and a moving object. 2. Related Art In an AT cut quartz crystal resonator constituting a temperature compensated crystal oscillator (TCXO), a frequency fluctuates while drawing a curve approximated to a cubic curve which has an inflection point around 25° C. due to a change in ambient temperature. An oscillation circuit and the like constituting the oscillator also have temperature characteristics, and thus a frequency fluctuates due to influences thereof. In the TCXO, a voltage signal for compensating for the frequency fluctuation is generated by a temperature compensation circuit and is applied to a varicap diode provided in the oscillation circuit. Therefore, the frequency fluctuation due to the change in ambient temperature is minimized, and thus high frequency accuracy is realized. As an example of such a TCXO, JP-A-2007-67967 discloses a TCXO using a semiconductor substrate provided with an oscillation circuit, an output buffer circuit, and a temperature sensor circuit, in which the output buffer circuit and the temperature sensor circuit are disposed in diagonal corners or the same side corners of the semiconductor substrate. In JP-A-2007-67967, if the output buffer circuit which is one of heat generation sources is distant from the temperature sensor circuit, there is a possibility that a temperature of the vicinity of the output buffer circuit may not be accurately detected. For this reason, for example, in a case where temperature compensation is performed on the basis of an output signal from the temperature sensor circuit when the TCXO is activated, correction based on a temperature of the output buffer circuit vicinity cannot be performed due to delay of transfer of heat to the temperature sensor circuit, and thus there is a possibility that an output frequency may fluctuate.

Invention Disclosure:
A semiconductor circuit device includes an oscillation circuit, an output circuit that outputs a signal output from the oscillation circuit, a temperature sensing element, a characteristic adjustment circuit that adjusts characteristics of the oscillation circuit on the basis of a signal output from the temperature sensing element, a first wiring via which power is supplied to the output circuit, and a second wiring via which a reference voltage is supplied to the output circuit in which at least one of the first wiring and the second wiring overlaps the temperature sensing element in a plan view.

[Assistant]
1. A semiconductor circuit device comprising:
an oscillation circuit that is connected to a resonator and causes the resonator to oscillate;
an output circuit that receives a signal output from the oscillation circuit and outputs an oscillation signal;
a temperature sensing element;
a characteristic adjustment circuit that adjusts characteristics of the oscillation circuit on the basis of a signal output from the temperature sensing element;
a first wiring via which power for operating the output circuit is supplied to the output circuit;
a second wiring via which a reference voltage is supplied to the output circuit; and
a semiconductor substrate on which the circuits, the temperature sensing element, and the wirings are provided,
wherein at least one of the first wiring and the second wiring overlaps the temperature sensing element in a plan view.

2. The semiconductor circuit device according to claim 1, further comprising:
a connection terminal that is electrically connected to the oscillation circuit and is also electrically connected to the resonator,
wherein a distance between the connection terminal and the output circuit is shorter than a distance between the temperature sensing element and the output circuit in a plan view.

3. The semiconductor circuit device according to claim 1, further comprising:
a memory that stores data for controlling at least one of the oscillation circuit, the output circuit, and the characteristic adjustment circuit.

4. The semiconductor circuit device according to claim 1,
wherein the characteristic adjustment circuit is a temperature compensation circuit.

5. The semiconductor circuit device according to claim 1,
wherein the output circuit includes a frequency division circuit.

6. An oscillator comprising:
the semiconductor circuit device according to claim 1;
the resonator; and
a container that accommodates the semiconductor circuit device and the resonator.

7. An oscillator comprising:
the semiconductor circuit device according to claim 2;
the resonator; and
a container that accommodates the semiconductor circuit device and the resonator.

8. An oscillator comprising:
the semiconductor circuit device according to claim 3;
the resonator; and
a container that accommodates the semiconductor circuit device and the resonator.

9. An oscillator comprising:
the semiconductor circuit device according to claim 4;
the resonator; and
a container that accommodates the semiconductor circuit device and the resonator.

10. An oscillator comprising:
the semiconductor circuit device according to claim 5;
the resonator; and
a container that accommodates the semiconductor circuit device and the resonator.

11. An electronic apparatus comprising the semiconductor circuit device according to claim 1.

12. An electronic apparatus comprising the semiconductor circuit device according to claim 2.

13. An electronic apparatus comprising the semiconductor circuit device according to claim 3.

14. An electronic apparatus comprising the semiconductor circuit device according to claim 4.

15. An electronic apparatus comprising the semiconductor circuit device according to claim 5.

16. A moving object comprising the semiconductor circuit device according to claim 1.

17. A moving object comprising the semiconductor circuit device according to claim 2.

18. A moving object comprising the semiconductor circuit device according to claim 3.

19. A moving object comprising the semiconductor circuit device according to claim 4.

20. A moving object comprising the semiconductor circuit device according to claim 5.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Light-Emitting Device

Technical Field and Background:
The principle of light emission of a light-emitting diode (LED) is different from that of an incandescent light. Besides, the junction temperature of a light-emitting diode (LED) is much lower than the filament temperature of an incandescent light, and therefore an LED is a cold light source. Furthermore, the light-emitting diodes have advantages such as high durability, longer lifetime, lower power consumption, and small size. As a result, the lighting market has high expectation of the light-emitting diodes becoming a new generation of lighting sources to gradually replace the conventional light sources, while the light-emitting diodes are applied to various fields such as traffic lights, back light modules, street lighting, and medical equipment. FIG. 1A shows a conventional light-emitting device. As shown in FIG. 1A , the conventional light-emitting device 100 comprises a transparent substrate 11 , a semiconductor stack 12 on the transparent substrate 11 , and an electrode 14 on the semiconductor stack 12 , wherein the semiconductor stack 12 comprises a first conductive type semiconductor layer 120 , an active layer 122 and a second conductive type semiconductor layer 124 in sequence in a direction from the electrode 14 to the transparent substrate 11 . Besides, the light-emitting device 100 mentioned above is able to further combine with other elements to form a light-emitting apparatus as shown in FIG. 1B . FIG. 1B shows a conventional light-emitting apparatus 200 comprising a submount 15 comprising a circuit 150 , a solder 13 on the submount 15 , by which the above light-emitting device 100 can be fixed on the submount 15 , and by which the substrate 11 of the above light-emitting device 100 is electrically connected to the circuit 150 on the submount 15 ; and an electrical connection structure 16 for electrically connecting a pad 14 of the light-emitting device 100 to the circuit 150 on the submount 15 ; wherein the submount 15 can be a lead frame or a large mounting substrate for facilitating the design of the electrical circuit of the light-emitting apparatus 200 and increasing the heat dissipation efficiency.

Invention Disclosure:
A light-emitting device is provided. The light-emitting device comprises: a light-emitting stack having an active layer; an electrode structure on the light-emitting stack and comprising a first electrode and an extension electrode protruding from the first electrode toward an edge of the light-emitting device in a first extending direction; a transparent insulating layer between the light-emitting stack and the electrode structure, wherein the transparent insulating layer comprises a first part and an extension part protruding from the first part toward the edge of the light-emitting device in a second extending direction; wherein a surface area of a surface of the first electrode distal from the transparent insulating layer is smaller than a surface area of a surface of the transparent insulating layer distal from the light-emitting stack, the first electrode is right above the first part, and a part of the extension electrode is right above the extension part.

[Assistant]
1. A light-emitting device, comprising:
a light-emitting stack having an active layer;
an electrode structure on the light-emitting stack and comprising a first electrode and an extension electrode protruding from the first electrode toward an edge of the light-emitting device in a first extending direction;
a transparent insulating layer between the light-emitting stack and the electrode structure, wherein from a top view of the light-emitting device, the transparent insulating layer comprises a first part and an extension part extending from the first part, the first part aligned with and under the first electrode having a first maximum width, the extension part aligned with and under a part of the extension electrode having a second maximum width less than the first maximum width;
wherein the extension part comprises a first edge and the extension electrode comprises a second edge, and a part of the first edge of the extension part protrudes laterally outward from the second edge of the extension electrode.

2. The light-emitting device according to claim 1, further comprises an electrical contact layer on the light-emitting stack and in contact with the transparent insulating layer.

3. The light-emitting device according to claim 2, wherein a part of the transparent insulating layer overlays a part of the electrical contact layer.

4. The light-emitting device according to claim 2, wherein a part of a bottom surface of the transparent insulating layer and a bottom surface of the electrical contact layer are substantially coplanar on the light-emitting stack.

5. The light-emitting device according to claim 2, wherein the electrode structure overlays and in direct contact with a part of the electrical contact layer, and the transparent insulating layer separates the electrode structure from another part of the electrical contact layer.

6. The light-emitting device according to claim 2, wherein the electrical contact layer is between the extension electrode and the light-emitting stack.

7. The light-emitting device according to claim 2, wherein in a cross-sectional view of the light-emitting device, the transparent insulating layer overlays a part of an upper surface of the electrical contact layer, and the electrode structure overlays a part of the surface of the transparent insulating layer distal from the light-emitting stack.

8. The light-emitting device according to claim 1, further comprising an insulating layer under the light-emitting stack.

9. The light-emitting device according to claim 8, wherein the insulating layer comprises multiple discrete insulating regions.

10. The light-emitting device according to claim 9, wherein one of the insulating regions is right under the first part.

11. The light-emitting device according to claim 10, wherein in a cross-sectional view of the light-emitting device, the insulating region right under the first part has a width less than a maximum width of the transparent insulating layer.

12. The light-emitting device according to claim 1, wherein the transparent insulating layer comprises oxide material.

13. The light-emitting device according to claim 1, wherein the refractive index of the transparent insulating layer is between 1 and 3.4 both inclusive, the transmittance of the transparent insulating layer is greater than 80%.

14. The light-emitting device according to claim 1, wherein an exposed surface of the light-emitting stack is a rough surface.

15. The light-emitting device according to claim 1, wherein the transparent insulating layer has a thickness not less than 800 angstrom (Å).

16. The light-emitting device according to claim 1, wherein the extension electrode comprises a first extension and a second extension extending from the first extension, wherein a part of the first extension is right above the extension part of the transparent insulating layer.

17. The light-emitting device according to claim 1, wherein the extension electrode has a third maximum width substantially perpendicular to the first extending direction, and the first electrode has a fourth maximum width greater than the first maximum width.

18. The light-emitting device according to claim 1, wherein the second maximum width is substantially perpendicular to the first extending direction.

19. The light-emitting device according to claim 17, wherein the second maximum width is greater than the third maximum width.

20. The light-emitting device according to claim 1, wherein a surface area of a surface of the first electrode distal from the transparent insulating layer is smaller than a surface area of a surface of the transparent insulating layer distal from the light-emitting stack.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: System And Method For An Assembled Ring Shroud

Technical Field and Background:
Gas turbine engines typically comprise a compressor section and a turbine section, with each section including rotatable blades and stationary vanes. Blade outer air seals may be mounted within the engine casing, positioned in close proximity to the outermost tips of the rotatable blades. Blade outer air seals may comprise a variety of materials, including unidirectional Ceramic Matrix Composite (CMC) plies. The exclusive use of unidirectional CMC plies may limit the way in which structural rings are created. A full hoop CMC ring for a blade outer air seal is particularly challenging for unidirectional plies because the outer plies are subjected to tensile stress. Historical data shows that the end ply contains stress concentrations and may limit the allowable stress significantly.

Invention Disclosure:
An assembled ring shroud is provided. The assembled ring shroud may comprise a cover, a first ring layer, a key layer, and a second ring layer. The cover may operatively wrap around, contain, and secure the first ring layer, the key layer, and the second ring layer. The key layer may comprise a key that may act for position and anti-rotation. The key layer may comprise spacers to hold the keys in place. The first ring layer and the second ring layer may be configured to provide further strength and support to the assembled ring shroud.

[Assistant]
1. An assembled ring shroud having a circumferential axis, comprising:
a first ring layer having a top and a bottom, wherein the first ring layer is aligned in a direction at least one of tangent or substantially tangent to the circumferential axis;
a key layer having a key and a spacer and a top and a bottom, wherein the bottom of the key layer is coupled to the top of the first ring layer, and wherein the key layer is aligned in the direction at least one of tangent or substantially tangent to the circumferential axis;
a second ring layer having a top and a bottom, wherein the bottom of the second ring layer is coupled to the top of the key layer, and wherein the ring layer is aligned in the direction at least one of tangent or substantially tangent to the circumferential axis; and
a cover having a key slot, wherein the cover is configured to wrap around and secure the first ring layer, the key layer, and the second ring layer, and is aligned in the direction at least one of tangent or substantially tangent to the circumferential axis, and wherein the key slot comprises a void on an edge of cover, and is configured to fit the key.

2. The assembled ring shroud of claim 1, wherein the first ring layer, the key of the key layer, the second ring layer, and the cover are formed of a ceramic matrix composite (CMC) material.

3. The assembled ring shroud of claim 2, wherein the CMC material forming the first ring layer comprises unidirectionally aligned fibers oriented in a direction at least one of tangent or substantially tangent to the circumferential axis.

4. The assembled ring shroud of claim 2, wherein the CMC material forming the second ring layer comprises unidirectionally aligned fibers oriented in a direction at least one of tangent or substantially tangent to the circumferential axis.

5. The assembled ring shroud of claim 2, wherein the CMC material forming the key of the key layer comprises unidirectionally aligned fibers oriented in a direction at least one of perpendicular or substantially perpendicular to the circumferential axis.

6. The assembled ring shroud of claim 2, wherein the CMC material forming the cover comprises unidirectionally aligned fibers oriented in a direction at least one of perpendicular or substantially perpendicular to the circumferential axis.

7. The assembled ring shroud of claim 1, wherein the spacer of the key layer comprises a monolithic ceramic material.

8. A gas turbine engine comprising:
a blade stage; and
an assembled ring shroud in the blade stage, the assembled ring shroud having a circumferential axis, comprising:
a first ring layer having a top and a bottom, wherein the first ring layer is aligned in a direction at least one of tangent or substantially tangent to the circumferential axis;
a key layer having a key and a spacer and a top and a bottom, wherein the bottom of the key layer is coupled to the top of the first ring layer, and wherein the key layer is aligned in the direction at least one of tangent or substantially tangent to the circumferential axis;
a second ring layer having a top and a bottom, wherein the bottom of the second ring layer is coupled to the top of the key layer, and wherein the ring layer is aligned in the direction at least one of tangent or substantially tangent to the circumferential axis; and
a cover having a key slot, wherein the cover is configured to wrap around and secure the first ring layer, the key layer, and the second ring layer, and is aligned in the direction at least one of tangent or substantially tangent to the circumferential axis, and wherein the key slot comprises a void on an edge of cover, and is configured to fit the key.

9. The gas turbine engine of claim 8, wherein the first ring layer, the key of the key layer, the second ring layer, and the cover are formed of a ceramic matrix composite (CMC) material.

10. The gas turbine engine of claim 9, wherein the CMC material forming the first ring layer comprises unidirectionally aligned fibers oriented in a direction at least one of tangent or substantially tangent to the circumferential axis.

11. The gas turbine engine of claim 9, wherein the CMC material forming the second ring layer comprises unidirectionally aligned fibers oriented in a direction at least one of tangent or substantially tangent to the circumferential axis.

12. The gas turbine engine of claim 9, wherein the CMC material forming the key of the key layer comprises unidirectionally aligned fibers oriented in a direction at least one of perpendicular or substantially perpendicular to the circumferential axis.

13. The gas turbine engine of claim 9, wherein the CMC material forming the cover comprises unidirectionally aligned fibers oriented in a direction at least one of perpendicular or substantially perpendicular to the circumferential axis.

14. The gas turbine engine of claim 8, wherein the spacer of the key layer comprises a monolithic ceramic material.

15. A gas turbine engine comprising:
an engine case;
a turbine stage comprising a stator vane and a rotor blade; and
an assembled ring shroud attached to the engine case and facing the rotor blade to locally bind a radially outboard extreme of a core flow path through the gas turbine engine, the assembled ring shroud having a circumferential axis, comprising:
a first ring layer having a top and a bottom, wherein the first ring layer is aligned in a direction at least one of tangent or substantially tangent to the circumferential axis;
a key layer having a key and a spacer and a top and a bottom, wherein the bottom of the key layer is coupled to the top of the first ring layer, and wherein the key layer is aligned in the direction at least one of tangent or substantially tangent to the circumferential axis;
a second ring layer having a top and a bottom, wherein the bottom of the second ring layer is coupled to the top of the key layer, and wherein the ring layer is aligned in the direction at least one of tangent or substantially tangent to the circumferential axis; and
a cover having a key slot, wherein the cover is configured to wrap around and secure the first ring layer, the key layer, and the second ring layer, and is aligned in the direction at least one of tangent or substantially tangent to the circumferential axis, and wherein the key slot comprises a void on an edge of cover, and is configured to fit the key.

16. The gas turbine engine of claim 15, wherein the first ring layer, the key of the key layer, the second ring layer, and the cover are formed of a ceramic matrix composite (CMC) material.

17. The gas turbine engine of claim 16, wherein the CMC material forming the first ring layer comprises unidirectionally aligned fibers oriented in a direction at least one of tangent or substantially tangent to the circumferential axis.

18. The gas turbine engine of claim 16, wherein the CMC material forming the second ring layer comprises unidirectionally aligned fibers oriented in a direction at least one of tangent or substantially tangent to the circumferential axis.

19. The gas turbine engine of claim 16, wherein the CMC material forming the key of the key layer comprises unidirectionally aligned fibers oriented in a direction at least one of perpendicular or substantially perpendicular to the circumferential axis.

20. The gas turbine engine of claim 16, wherein the CMC material forming the cover comprises unidirectionally aligned fibers oriented in a direction at least one of perpendicular or substantially perpendicular to the circumferential axis.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Operating Panel Device

Technical Field and Background:
To control an air conditioner, an audio set, and the like of a vehicle, an operating panel device is used in general. A user can change a display on an operating panel of the device by using buttons provided on the operating panel. Such an operating panel device is required to be easily operated and to have high visibility. Conventional operating panel device 20 is described with reference to FIG. 9 . FIG. 9 is a plan view of operating panel device 20 . Operating panel device 20 includes operating ring 11 , push panels 12 A to 12 D, illumination part 13 , icons 14 A to 14 D, and display device 15 . Operating ring 11 can be operated by pushing and can also be operated by rotation. For example, when a user rotatably operates operating ring 11 , a set temperature of an air conditioner of a vehicle can be elevated or lowered. Push switches (not illustrated) are disposed below push panels 12 A to 12 D, and the push switches can determine which one of push panels 12 A to 12 D is pushed. Push panels 12 A to 12 D correspond to icons 14 A to 14 D provided on illumination part 13 . For example, when a user pushes any one of push panels 12 A to 12 D, a light emitting element (not illustrated) below any one of icons 14 A to 14 D which corresponds to the pushed push panel emits light. Accordingly, any one of icons 14 A to 14 D which corresponds to the pushed push panel is illuminated so that the user can easily visually recognize which icon is selected. In the example shown in FIG. 9 , when the user manipulates push panels 12 A to 12 D, an air conditioner of a vehicle is controlled. For example, when the user pushes push panel 12 A, a heater of a window of the vehicle is turned on (icon 14 A). When push panel 12 B is pushed, inside air/outside air switching in the vehicle is controlled (icon 14 B). When push panel 12 C is pushed, an automatic control of the air conditioner of the vehicle is turned on (icon 14 C). When push panel 12 D is pushed, the automatic control of the air conditioner of the vehicle is turned off (icon 14 D). Display device 15 is formed of a liquid crystal display or the like. In a normal state, display device 15 displays current setting of the air conditioner. When the user pushes operating ring 11 , the current display is changed to a screen display for changing a set temperature. When the user rotates operating ring 11 in a clockwise direction, the set temperature of the air conditioner is elevated, and when the user rotates operating ring 11 in a counterclockwise direction, the set temperature of the air conditioner is lowered (for example, PTL 1).

Invention Disclosure:
An operating panel device includes an operating ring, and a display device which is disposed to face a back surface of the operating ring. The display device includes a first portion, a second portion, and a third portion. The first portion is located inside the operating ring, and the second portion is located outside the operating ring. The third portion connects the first portion and the second portion. A display of the first portion changes in conjunction with a rotational operation applied to the operating ring.

[Assistant]
1. An operating panel device comprising:
an operating ring having an operable front surface and a back surface opposite to the front surface; and
a display device including a first portion located inside the operating ring, a second portion located outside the operating ring, and a third portion connecting the first portion and the second portion, the display device being disposed to face the back surface of the operating ring, wherein:
the third portion is an arcuate groove portion formed at a surface of the display device, the operating ring is disposed in the arcuate groove portion of the third portion, and
a display of the first portion changes in conjunction with a rotational operation applied to the operating ring.

2. The operating panel device according to claim 1, wherein the operating ring is one of a plurality of operating rings, and the operating panel device includes the plurality of operating rings.

3. The operating panel device according to claim 1, wherein the operating ring includes:
a rotary part having a ring shape and provided with a guide groove over a whole circumference on a surface facing the display device;
a fixed part having a ring-shaped flat plate portion, and a guide rail portion projecting from the flat plate portion and located inside the guide groove over the whole circumference of the flat plate portion;
a ball stored between an inner peripheral wall of the guide groove of the rotary part and an inner peripheral wall of the guide rail portion of the fixed part, the ball being in contact with the rotary part; and
an elastic body stored between the inner peripheral wall of the guide rail portion of the fixed part and the ball, the elastic body including a first end in contact with the fixed part and a second end in contact with the ball,
wherein click ridge portions having projections and depressions repeated over a whole circumference are formed on the inner peripheral wall of the guide groove of the rotary part, and the elastic body urges the ball against one of the click ridge portions.

4. The operating panel device according to claim 1, wherein:
the surface of the display is a cover lens, and
the arcuate groove portion is formed on the cover lens.

5. The operating panel device according to claim 1, further comprising a rotation detecting sensor for determining a rotational operation of the operating ring.

6. The operating panel device according to claim 5, wherein the rotation detecting sensor includes any one of a photo sensor, a magnetic field sensor, and an electrostatic sensor.

7. The operating panel device according to claim 5, wherein the rotation detecting sensor includes at least two magnetic field sensors, and a rotational operation of the operating ring is determined based on a difference between inputs of the magnetic field sensors.

8. The operating panel device according to claim 5, further comprising a control circuit for changing a display of the first portion based on an output from the rotation detecting sensor.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Isolation Of Magnetic Layers During Etch In A Magnetoresistive Device

Technical Field and Background:
Magnetoresistive memory devices store information by varying the resistance across the memory device such that a read current through a memory cell in the memory device will result in a voltage drop having a magnitude that is based on the information stored in the memory cell. For example, in certain magnetic memory devices, the voltage drop across a magnetic tunnel junction (MTJ) can be varied based on the relative magnetic states of the magnetic layers within the memory cell. In such memory devices, there is typically a portion of the memory cell that has a fixed magnetic state and another portion that has a free magnetic state that is controlled to be either parallel or antiparallel to the fixed magnetic state. Because the resistance through the memory cell changes based on whether the free portion is parallel or antiparallel to the fixed portion, information can be stored by setting the orientation of the free portion. The information is later retrieved by sensing the orientation of the free portion. Such magnetic memory devices are well known in the art. Writing magnetic memory cells can be accomplished by sending a spin-polarized write current through the memory device where the angular momentum carried by the spin-polarized current can change the magnetic state of the free portion. One of ordinary skill in the art understands that such a current can either be directly driven through the memory cell or can be the result of applying one or more voltages where the applied voltages result in the desired current. Depending on the direction of the current through the memory cell, the resulting magnetization of the free portion will either be parallel or antiparallel to the fixed portion. If the parallel orientation represents a logic “0”, the antiparallel orientation may represent a logic “1”, or vice versa. Thus, the direction of write current flow through the memory cell determines whether the memory cell is written to a first state or a second state. Such memory devices are often referred to as spin torque transfer memory devices. In such memories, the magnitude of the write current is typically greater than the magnitude of a read current used to sense the information stored in the memory cells. Manufacturing magnetoresistive devices, including MTJ devices, includes a sequence of processing steps during which many layers of materials are deposited and then patterned to form a magnetoresistive stack and the electrodes used to provide electrical connections to the magnetoresistive stack. The magnetoresistive stack includes the various layers that make up the free and fixed portions of the device as well as one or more dielectric layers that provide at least one the tunnel junction for the MTJ device. In many instances, the layers of material are very thin, on the order of a few or tens of angstroms. Similarly, the dimensions of such layers after patterning and etching are extremely small, and small deviations or imperfections during processing can have a significant impact on device performance. Because an MRAM device may include millions of MTJ elements, precise processing steps used in manufacturing the devices can contribute to increased densities by allowing devices to be placed in close proximity without unwanted interaction. Moreover, such accurate processing helps to minimize deviations in device characteristics, such as switching voltages, across devices included in the MRAM. Therefore, it is desirable to provide techniques for manufacturing such devices that support increased densities and promote minimizing the variance of certain characteristics amongst devices.

Invention Disclosure:
Methods for manufacturing magnetoresistive devices are presented in which isolation of magnetic layers in the magnetoresistive stack is achieved by oxidizing exposed sidewalls of the magnetic layers prior to subsequent etching steps. Etching the magnetic layers using a non-reactive gas further prevents degradation of the sidewalls.

[Assistant]
1. A method of manufacturing a magnetoresistive device that includes a magnetoresistive stack, comprising:
etching a first portion of the magnetoresistive stack to produce an etched first portion of the magnetoresistive stack having sidewalls, where the first portion of the magnetoresistive stack includes a first dielectric layer corresponding to a tunnel barrier layer for the device and at least one layer of magnetic material;
after etching the first portion of the magnetoresistive stack, oxidizing the sidewalls of the etched first portion of the magnetoresistive stack to encapsulate the sidewalls of the first portion of the magnetoresistive stack; and
after oxidizing the sidewalls of the etched first portion of the magnetoresistive stack, etching a second portion of the magnetoresistive stack to produce an etched second portion of the magnetoresistive stack, wherein the second portion of the magnetoresistive stack includes a layer of antiferromagnetic material, and where the first portion of the magnetoresistive stack is over the second portion of the magnetoresistive stack.

2. The method of claim 1, wherein etching the first portion of the magnetoresistive stack further comprises etching the first portion of the magnetoresistive stack using a non-reactive etch that prevents oxidation or other degradation of the tunnel barrier layer and the at least one layer of magnetic material during the etching of the first portion.

3. The method of claim 2, wherein the non-reactive etch is a non-oxidizing argon etch.

4. The method of claim 1, wherein etching the second portion of the magnetoresistive stack further comprises etching the second portion of the magnetoresistive stack using a reactive, corrosive etch.

5. The method of claim 4 wherein etching the second portion of the magnetoresistive stack includes etching the second portion using a mixture of at least one noble gas and at least one corrosive gas.

6. The method of claim 1, wherein the at least one layer of magnetic material includes a fixed layer, and wherein etching the first portion of the magnetoresistive stack further comprises etching at least a portion of the fixed layer.

7. The method of claim 6, wherein the fixed layer is over the layer of antiferromagnetic material, and wherein etching the first portion further comprises etching through the fixed layer until reaching the layer of antiferromagnetic material.

8. The method of claim 7, wherein etching the first portion of the magnetoresistive stack further comprises etching the first portion of the magnetoresistive stack using a non-reactive etch that prevents oxidation or other degradation of the tunnel barrier layer and the fixed layer during the etching of the first portion.

9. The method of claim 1 further comprising:
encapsulating sidewalls of the etched second portion of the magnetoresistive stack; and
after encapsulating the sidewalls of the etched second portion of the stack, etching a third portion of the magnetoresistive stack, where the second portion of the magnetoresistive stack is over the third portion of the magnetoresistive stack.

10. The method of claim 1 wherein etching the second portion of the magnetoresistive stack includes etching a lower layer of electrically conductive material to form a bottom electrode.

11. The method of claim 1, wherein etching the first portion of the magnetoresistive stack further comprises etching the first portion of the magnetoresistive stack using a reactive etch.

12. A method of manufacturing a magnetoresistive device, comprising:
etching an upper layer of electrically conductive material to form a top electrode;
etching an upper layer of magnetic material under the upper layer of electrically conductive material to form a first magnetic stack layer;
etching a dielectric layer under the upper layer of magnetic material to form a tunnel barrier;
etching at least a portion of a lower layer of magnetic material under the first dielectric layer to form a second magnetic stack layer;
oxidizing exposed sidewalls of at least the second magnetic stack layer to encapsulate at least the second magnetic stack layer; and
after oxidizing the exposed sidewalls, etching additional device layers under the lower layer of magnetic material using a reactive, corrosive etch chemistry.

13. The method of claim 12, wherein the additional device layers under the lower layer of magnetic material include a layer of antiferromagnetic material under the lower layer of magnetic material, and wherein etching the at least a portion of the lower layer of magnetic material includes etching the lower layer of magnetic material and stopping at the layer of antiferromagnetic material.

14. The method of claim 13, wherein etching the additional device layers under the lower layer of magnetic material includes etching a lower layer of electrically conductive material to form a bottom electrode.

15. The method of claim 12, wherein etching the lower layer of magnetic material includes etching the lower layer of magnetic material using a non-reactive etch that prevents oxidation or other degradation of the tunnel barrier and lower layer of magnetic material during the etching of the lower layer of magnetic material.

16. The method of claim 15, wherein oxidizing exposed sidewalls of at least the second magnetic stack layer includes oxidizing exposed sidewalls of the tunnel barrier.

17. A method of manufacturing a magnetoresistive device, comprising:
etching an upper layer of electrically conductive material to form a top electrode;
etching an upper layer of magnetic material under the upper layer of electrically conductive material to form a free layer;
etching a dielectric layer under the upper layer of magnetic material to form a tunnel barrier;
etching, using a non-reactive etch, a lower layer of magnetic material under the dielectric layer to form a fixed layer;
oxidizing exposed sidewalls of the fixed layer to form a protective layer on the exposed sidewalls; and
after oxidizing the exposed sidewalls of the fixed layer to form the protective layer, etching antiferromagnetic material under the lower layer of magnetic material using a reactive, corrosive etch chemistry.

18. The method of claim 17, wherein etching the lower layer of magnetic material includes etching the lower layer of magnetic material using a noble gas that prevents oxidation or other degradation of the tunnel barrier layer and the lower layer of magnetic material.

19. The method of claim 17, wherein etching the lower layer of magnetic material further comprises stopping etching of the lower layer of magnetic material when the antiferromagnetic material under the lower layer of magnetic material is reached.

20. The method of claim 17, wherein etching the lower layer of magnetic material further comprises etching the lower layer of magnetic material using a gas consisting of one of argon and xenon.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Solid-State Imaging Device And Imaging System

Technical Field and Background:
In a charge-coupled device (CCD) type or an amplification type solid-state imaging device used in a digital still camera, a cam coder or the like, there is a demand for finer pixels to obtain a high definition image. However, the finer the pixels, the smaller the light receiving area of a photoelectric conversion element for detecting light included in the pixels, resulting in a reduction in sensitivity. Japanese Patent Application Laid-Open No. 2006-191081 discusses complementary metal-oxide-semiconductor (CMOS) type, which is also an amplification type, solid-state imaging device of a construction in which a first substrate with a photoelectric conversion element and a transfer transistor arranged thereon and a second substrate with another circuit arranged thereon are bonded to each other to forma solid-state imaging device to secure the requisite light receiving area of the photoelectric conversion element. Further, Japanese Patent Application Laid-Open No. 2006-191081 discusses a solid-state imaging device in which a connection portion extending through a second substrate is connected to an input/output pad to effect connection of the input/output pad from the back-side of the second substrate. This input/output pad is formed after the connection portion is exposed by polishing of the second substrate. However, Japanese Patent Application Laid-Open No. 2006-191081 discusses a construction in which the input/output pad is directly connected to the circuit of the first substrate. In such a construction, external noise from an external terminal is imparted to the circuit of the first substrate, so that a malfunction of the circuit can be generated. Further, a photoelectric conversion element is arranged on the first substrate, and incorporation of external noise may affect the image signal.

Invention Disclosure:
A solid-state imaging device includes: a first semiconductor substrate including a photoelectric conversion element; and a second semiconductor substrate including at least a part of a peripheral circuit arranged in a main face of the second semiconductor substrate, the peripheral circuit generating a signal based on the charge of the photoelectric conversion element, a main face of the first semiconductor substrate and the main face of the second semiconductor substrate being opposed to each other with sandwiching a wiring structure therebetween; a pad to be connected to an external terminal; and a protection circuit electrically connected to the pad and to the peripheral circuit, wherein the protection circuit is arranged in the main face of the second semiconductor substrate.

[Assistant]
1. A method of manufacturing an imaging device, the method comprising:
providing a first member including a first semiconductor substrate and a first wiring structure on the first semiconductor substrate;
providing a second member including a second semiconductor substrate and a second wiring structure on the second semiconductor substrate;
bonding the first member and the second member such that the second wiring structure is arranged between the first semiconductor substrate and the second semiconductor substrate;
thinning the first semiconductor substrate after the bonding; and
forming an opening by etching the first substrate,
wherein the first member has a pixel part in which a plurality of photoelectric conversion elements is arranged, and a circuit part in which a circuit element is provided out of the pixel part,
wherein the second member has a protection circuit,
wherein a first wiring of the first wiring structure is electrically connected to the protection circuit via a second wiring of the second wiring structure before forming the opening, and
wherein the opening is formed above the first wiring of the first wiring structure.

2. The method according to claim 1, wherein, in the bonding, the first wiring structure is arranged between the first semiconductor substrate and the second semiconductor substrate, and
wherein the second wiring is arranged between the first wiring and the second semiconsductor substrate.

3. The method according to claim 2, wherein the first semiconductor substrate has, in the pixel part, a transfer transistor and an amplification transistor, and wherein the second semiconductor substrate has an n-type transistor and a p-type transistor.

4. The method according to claim 1, wherein a pad provides a connection between an external terminal and the protection circuit.

5. A method of manufacturing an imaging device, the method comprising:
providing a first member including a first semiconductor substrate and a first wiring structure on the first semiconductor substrate;
providing a second member including a second semiconductor substrate and a second wiring structure on the second semiconductor substrate;
bonding the first member and the second member such that the second wiring structure is arranged between the first semiconductor substrate and the second semiconductor substrate;
thinning the first semiconductor substrate after the bonding;
forming a lens layer on the first substrate after the thinning; and
forming an opening by etching the first substrate after forming the lens layer,
wherein the first member has a photoelectric conversion element, and the second member has a protection circuit, and,
wherein the first wiring structure has a first wiring for a connection between an external terminal and the protection circuit.

6. The method according to claim 5, wherein the second wiring structure is arranged between the first wiring structure and the second semiconductor substrate.

7. The method according to claim 5, wherein the opening is formed above the first wiring of the first wiring structure.

8. A method of manufacturing an imaging device, the method comprising:
providing a first member including a first semiconductor substrate and a first wiring structure on the first semiconductor substrate;
providing a second member including a second semiconductor substrate and a second wiring structure on the second semiconductor substrate;
bonding the first member and the second member such that the second wiring structure is arranged between the first semiconductor substrate and the second semiconductor substrate, and the second wiring structure is arranged between the first wiring structure and the second semiconductor substrate;
thinning the first semiconductor substrate after the bonding; and
forming an opening by etching the first substrate after the bonding,
wherein the first member has a photoelectric conversion element, and the second member has a protection circuit,
wherein the first wiring structure has a first wiring for a connection between an external terminal and the protection circuit, and
wherein the first wiring of the first wiring structure is electrically connected to the second wiring of the second wiring structure before forming the opening.

9. The method according to claim 8, further comprising thinning the second semiconductor substrate.

10. The method according to claim 9, wherein a thickness of the second semiconductor substrate is larger than a thickness of the first semiconductor substrate after the thinning of the second semiconductor substrate.

11. The method according to claim 8, wherein the second semiconductor substrate has a semiconductor region of the protection circuit.

12. The method according to claim 11, wherein the semiconductor region is surrounded by a shallow trench isolation structure.

13. The method according to claim 8, wherein the protection circuit includes a plurality of diodes.

14. The method according to claim 8, wherein the second member has a circuit to perform a signal processing.

15. The method according to claim 8, wherein the second member has a scanning circuit.

16. The method according to claim 8, further comprising forming a lens layer on the first substrate after the thinning.

17. The method according to claim 16, wherein the opening is formed after forming the lens layer.

18. The method according to claim 16, further comprising forming a film in the opening before forming the lens layer.

19. A method of manufacturing an imaging device, the method comprising:
providing a first member including a first semiconductor substrate and a first wiring structure on the first semiconductor substrate;
providing a second member including a second semiconductor substrate and a second wiring structure on the second semiconductor substrate;
bonding the first member and the second member such that the second wiring structure is arranged between the first semiconductor substrate and the second semiconductor substrate;
thinning the first semiconductor substrate after the bonding; and
forming an opening by etching the first substrate after the bonding,
wherein the first member has a photoelectric conversion element, the second member has a protection circuit and a pad for a connection between an external terminal and the protection circuit, and the opening is formed on the pad.

20. The method according to claim 19, wherein a first wiring of the first wiring structure is electrically connected to a second wiring of the second wiring structure before forming the opening.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Switching Circuit

Technical Field and Background:
Some transistors in integrated circuits are typical transistors. Some transistors switch slower than the typical transistors, and are called transistors in the slow corner. Some transistors switch faster than the typical transistors, and are called transistors in the fast corner. In a memory array, various power switches or transistors are placed at input-output (IO) circuits and at decoder circuits in the row or X direction of the memory array. During a wake up time of the memory array, particularly at high operational voltage values and/or when the transistors are in the fast corner, many transistors are turned on all together in a short period of time, which causes a large wake up current.

Invention Disclosure:
A circuit has an operational voltage supply node that carries an operational voltage having an operational voltage value, a reference voltage supply node that carries a reference voltage having a reference voltage value, and a sub-circuit and switching circuit between the operational voltage supply node and the reference voltage supply node. The switching circuit is in series with the sub-circuit and controls a current through the sub-circuit based on a difference between the operational voltage value and a nominal operational voltage value.

[Assistant]
1. A circuit comprising:
an operational voltage supply node configured to carry an operational voltage having an operational voltage value;
a reference voltage supply node configured to carry a reference voltage having a reference voltage value;
a sub-circuit between the operational voltage supply node and the reference voltage supply node; and
a switching circuit between the operational voltage supply node and the reference voltage supply node and in series with the sub-circuit, the switching circuit configured to control a current through the sub-circuit based on a difference between the operational voltage value and a nominal operational voltage value.

2. The circuit of claim 1, further comprising a control circuit configured to:
generate a control signal based on the operational voltage value; and
supply the control signal to the switching circuit.

3. The circuit of claim 2, wherein the control circuit is configured to change a logic state of the control signal after a delay if the operational voltage value is greater than a first value based on the nominal operational voltage value.

4. The circuit of claim 3, wherein the control circuit is configured to respond to a first signal having a logic state indicating a wake up mode by:
initiating the delay;
generating the control signal having a first logic state during the delay based on a stored logic value indicating the operational voltage value being greater than the first value based on the nominal operational voltage value; and
generating the control signal having a second logic state during the delay based on the stored logic value indicating the operational voltage value being less than a second value based on the nominal operational voltage value.

5. The circuit of claim 4, wherein the control circuit comprises a keeper circuit configured to store the stored logic value.

6. The circuit of claim 4, wherein the control circuit is configured to change the control signal from having the first logic state to the second logic state after the delay if the operational voltage value is greater than the first value based on the nominal operational voltage value.

7. The circuit of claim 3, wherein the switching circuit is configured to increase the current through the sub-circuit in response to the change in the logic state of the control signal.

8. The circuit of claim 3, further comprising a delay circuit configured to execute the delay in response to a first signal.

9. A method comprising:
carrying an operational voltage having an operational voltage value on an operational voltage supply node;
carrying a reference voltage having a reference voltage value on a reference voltage supply node;
receiving a current by a sub-circuit between the operational voltage supply node and the reference voltage supply node; and
controlling the current through the sub-circuit by a switching circuit between the operational voltage supply node and the reference voltage supply node and in series with the sub-circuit, controlling the current through the sub-circuit being based on a comparison of the operational voltage value to a nominal operational voltage value.

10. The method of claim 9, further comprising:
generating, by a control unit, a control signal based on the operational voltage value; and
supplying, by the control unit, the control signal to the switching circuit.

11. The method of claim 10, further comprising changing, by the control unit, a logic state of the control signal after a delay if the operational voltage value is greater than a first value based on the nominal operational voltage value.

12. The method of claim 11, further comprising the control unit responding to a first signal having a logic state indicating a wake up mode by:
initiating the delay;
generating the control signal having a first logic state during the delay based on a stored logic value indicating the operational voltage value being greater than the first value based on the nominal operational voltage value; and
generating the control signal having a second logic state during the delay based on the stored logic value indicating the operational voltage value being less than a second value based on the nominal operational voltage value.

13. The method of claim 12, further comprising storing the stored logic value with a keeper circuit of the control unit.

14. The circuit of claim 12, wherein the control unit responding to the first signal further comprises changing the control signal from having the first logic state to the second logic state after the delay if the operational voltage value is greater than the first value based on the nominal operational voltage value.

15. The method of claim 11, further comprising the switching circuit increasing the current through the sub-circuit in response to the change in the logic state of the control signal.

16. The method of claim 11, further comprising executing the delay by a delay circuit in response to a first signal.

17. A circuit comprising:
an operational voltage supply node configured to carry an operational voltage having an operational voltage value;
a reference voltage supply node configured to carry a reference voltage having a reference voltage value;
a plurality of sub-circuits between the operational voltage supply node and the reference voltage supply node;
a control circuit configured to generate a control signal based on the operational voltage value; and
a plurality of switching circuits between the operational voltage supply node and the reference voltage supply node, each switching circuit of the plurality of switching circuits being:
in series with a corresponding sub-circuit of the plurality of sub-circuits; and
configured to control a current through the corresponding sub-circuit based on the control signal.

18. The circuit of claim 17, wherein the control circuit is configured to:
initiate a delay;
generate the control signal having a first logic state during the delay based on a stored logic value indicating the operational voltage value being greater than a first value based on the nominal operational voltage value;
generate the control signal having a second logic state during the delay based on the stored logic value indicating the operational voltage value being less than a second value based on the nominal operational voltage value; and
supply the control signal to each switching circuit of the plurality of switching circuits.

19. The circuit of claim 18, wherein the control circuit is configured to change the control signal from having the first logic state to the second logic state after the delay if the operational voltage value is greater than the first value based on the nominal operational voltage value.

20. The circuit of claim 18, further comprising a plurality of delay elements configured to execute the delay, each delay element of the plurality of delay elements being associated with a corresponding sub-circuit of the plurality of sub-circuits.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Bolt Carrier Support System

Technical Field and Background:
AR-15 style rifles may be susceptible to buffer tube wear as a result of bolt cycling during operation. The bolt carrier may wear the buffer tube, which may in turn reduce the reliability of AR-15 style rifles. Generally, the buffer tube is a thin walled tube made from aluminum or another suitable material. The bolt carrier may be a harder material (e.g., steel) than the buffer tube. Moreover, the bolt carrier may be a denser material, have greater mass, and may be less susceptible to wear than the thin walls of the buffer tube.

Invention Disclosure:
In various embodiments, a buffer retention system may comprise a body, a retention tab and a spring. The body may comprise a generally cylindrical portion and a partially annular guide portion. The generally cylindrical portion may define a channel. The partially annular guide portion may be operatively coupled to the cylindrical portion. The retention tab may be installable in the channel. The retention tab may be configured to protrude through the partially annular guide portion. The spring may be installable within the channel. The spring may be configured to position the retention tab through the partially annular guide portion.

[Assistant]
1. A buffer retention system configured to be inserted within a lower receiver of a firearm, the buffer retention system comprising:
a body comprising:
a generally cylindrical portion defining a channel in an interior of the generally cylindrical portion;
a partially annular guide portion located forward of and adjacent to a lower portion of a buffer tube and integrally formed with the cylindrical portion, wherein the partially annular guide portion is coaxial with the buffer tube, wherein a support surface of the partially annular guide portion is configured to engage and support an aft portion of a bolt carrier, wherein the support surface is flush with the buffer tube, wherein the generally cylindrical portion and the partially annular guide portion are removable from the lower receiver;
a retaining pin located within the channel and protruding through an aperture in the partially annular guide portion, wherein the retaining pin is configured to translate within the channel, wherein the retaining pin is configured to contact a buffer located within the buffer tube and retain the buffer within the buffer tube; and
a spring located within the channel and configured to position the retaining pin through the aperture of the partially annular guide portion.

2. The buffer retention system of claim 1, wherein the buffer retention system is installable in a lower receiver of an AR-15 style rifle.

3. The buffer retention system of claim 1, wherein the buffer retention system is configured to engage and retain the buffer tube.

4. The buffer retention system of claim 1, wherein the buffer retention system is configured to support and guide a bolt carrier.

5. The buffer retention system of claim 1, wherein the partially annular guide portion is configured to remain stationary in response to the retaining pin compressing the spring.

6. The buffer retention system of claim 1, wherein the partially annular guide portion is configured to remain flush with the buffer tube in response to the retaining pin compressing the spring.

7. The buffer retention system of claim 1, wherein the generally cylindrical portion and the partially annular guide portion are a single integral piece.

8. A rotating bolt firearm, comprising:
an upper receiver comprising:
an operating system; and
a bolt rotatably moveable between a first position and a second position in response to an input from the operating system;
a barrel configured to receive the bolt;
a buffer system comprising a buffer located within a buffer tube; and
a lower receiver operatively coupled to the buffer tube, the lower receiver comprising,
a buffer retention system comprising:
a generally cylindrical portion defining a channel, the cylindrical portion removably installed within the lower receiver;
a partially annular guide portion located forward of and adjacent to a lower portion of the buffer tube and integrally formed with the cylindrical portion, wherein the partially annular guide portion is coaxial with the buffer tube, wherein a support surface of the partially annular guide portion is configured to engage and support an aft portion of a bolt carrier, wherein the support surface is flush with the buffer tube, wherein the support surface is perpendicular to the cylindrical portion, wherein the cylindrical portion is not coaxial with the buffer tube; and
a retaining pin located within the channel and protruding through an aperture in the support surface, wherein the retaining pin is configured to translate within the channel, wherein contact between the retaining pin and an interior of the cylindrical portion keeps the retaining pin within the cylindrical portion, wherein the retaining pin is coaxial with the cylindrical portion, wherein the retaining pin is in contact with the buffer and retains the buffer within the buffer tube;

9. The rotating bolt firearm of claim 8, wherein the partially annular guide portion is configured to remain stationary in response to the retaining pin compressing a spring in the channel.

10. The rotating bolt firearm of claim 8, wherein the partially annular guide portion is configured to remain flush with the buffer tube in response to the retaining pin compressing a spring in the channel.

11. The rotating bolt firearm of claim 8, wherein the generally cylindrical portion and the partially annular guide portion are a single integral piece.