[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Wireless Communications Assembly

Technical Field and Background:
The performance of wireless antennas (e.g. antenna, dielectric and via geometries in or on printed circuit board assemblies) is known to be dependent on the precision of these geometries. Particularly at higher frequencies—such as those employed by the IEEE 802.11ad standard (also referred to as WiGig), which employs the 60 GHz frequency band—sensitivity of antenna performance to geometry can be very pronounced. As a result, antennas for use in high-frequency applications are often produced with strict manufacturing tolerances. Adhering to such strict design tolerance requirements, however, increase the difficulty (and therefore the cost and time) of production. In addition to the challenges posed by strict manufacturing tolerances, the complexity required to successfully design, simulate, prototype, and validate high-frequency antennas into productions limits the number of viable antenna solutions that can be produced because of the cost and time associated with the above-mentioned design cycle, particularly when the cycle is repeated to refine the design. This cycle can limit the pace at which new antennas can be developed to meet different high-frequency antenna requirements. A further complicating factor in the production of wireless radio assemblies for high-frequency applications is the issue of signal attenuation between the antenna and processing circuitry: leads between antenna and processors are generally kept as short as possible to reduce signal losses. Together, the above-mentioned challenges tend to increase the complexity and cost of manufacturing high-frequency wireless communication assemblies.

Invention Disclosure:
A wireless communication assembly includes a first support member carrying a baseband processor and a radio processor, and defining a first mounting surface including a first pair of electrical contacts. The first support member has a first pair of electrical connections between the radio processor and the first electrical contacts. The assembly also includes a second support member carrying an antenna and defining a second mounting surface including a second pair of electrical contacts. The second support member has a second pair of electrical connections between the antenna and the second electrical contacts. The second mounting surface is configured to engage the first mounting surface to rigidly couple the first and second support members and to bring the first pair of electrical contacts into contact with the second pair of electrical contacts for electrically connecting the radio processor and the antenna via the first and second pairs of electrical connections.

[Assistant]
1. A wireless communication assembly, comprising:
a first support member having an outer surface; the first support member defining a first mounting surface opposite the outer surface, the first mounting surface including a first pair of electrical contacts;
a baseband processor surface-mounted to the outer surface;
a radio processor connected to the baseband processor and surface-mounted to the outer surface;
the first support member having a first pair of electrical connections extending from the outer surface through the first support member to the mounting surface, to electrically connect the radio processor and the first pair of electrical contacts; and
a second support member carrying an antenna and defining a second mounting surface on an opposite side of the second support member from the antenna, the second mounting surface including a second pair of electrical contacts; the second support member having a second pair of electrical connections between the antenna and the second pair of electrical contacts;
the second mounting surface configured to engage with the first mounting surface to rigidly couple the first and second support members and to bring the first pair of electrical contacts into contact with the second pair of electrical contacts for electrically connecting the radio processor and the antenna via the first and second pairs of electrical connections.

2. The wireless communication assembly of claim 1, the first pair of electrical connections comprising vias extending through the first support member, from the outer surface to the first mounting surface.

3. The wireless communication assembly of claim 2, wherein the vias are orthogonal to the outer surface.

4. The wireless communication assembly of claim 3, the second pair of electrical connections comprising vias extending through the second support member, from the side of the second support member carrying the antenna to the second mounting surface.

5. The wireless communication assembly of claim 4, wherein the vias are orthogonal to the side of the second support member carrying the antenna.

6. The wireless communication assembly of claim 5, the second pair of electrical contacts comprising solder bumps forming a ball grid array (BGA).

7. The wireless communication assembly of claim 1, the first support member comprising a multi-layer printed circuit board (PCB) and including:
a reserved internal layer for an integrated antenna; and
an additional electrical connection between the radio processor and the reserved internal layer.

8. An antenna component for a wireless communications assembly, comprising:
an antenna support member carrying an antenna and defining a mounting surface on an opposite side of the antenna support member from the antenna, the mounting surface including a pair of electrical contacts;
the antenna support member having a pair of electrical connections between the antenna and the pair of electrical contacts, the electrical connections comprising vias extending through the antenna support member, from a side of the antenna support member carrying the antenna to the mounting surface;
the mounting surface configured to engage with a corresponding mounting surface of a base component of the wireless communications assembly, to rigidly couple the antenna support member with the base component, and to bring the pair of electrical contacts into contact with a corresponding pair of electrical contacts on the base component for electrically connecting a radio processor surface-mounted on an opposite side of the base component from the corresponding pair of electrical contacts with the antenna via the pair of electrical connections.

9. The antenna component of claim 8, wherein the vias are orthogonal to the side of the antenna support member carrying the antenna.

10. The antenna component of claim 9, the pair of electrical contacts comprising solder bumps forming a ball grid array (BGA).

11. A base component for a wireless communications assembly, comprising:
a base support member having an outer surface; the base support member defining a mounting surface opposite the outer surface, the mounting surface including a pair of electrical contacts;
a baseband processor surface-mounted to the outer surface;
a radio processor connected to the baseband processor and surface-mounted to the outer surface;
the base support member having a pair of electrical connections extending from the outer surface through the first support member to the mounting surface, to electrically connect the radio processor and the pair of electrical contacts;
the mounting surface configured to engage with a corresponding mounting surface of an antenna component of the wireless communications assembly, to rigidly couple the antenna component with the base support member, and to bring the pair of electrical contacts into contact with a corresponding pair of electrical contacts on the corresponding mounting surface of the antenna component for electrically connecting the radio processor with an antenna carried by the antenna component on an opposite side of the antenna component from the corresponding pair of electrical contacts via the pair of electrical connections.

12. The base component of claim 11, the pair of electrical connections comprising vias extending through the base support member, from the outer surface to the mounting surface.

13. The base component of claim 12, wherein the vias are orthogonal to the outer surface.

14. The base component of claim 11, the base support member comprising a multi-layer printed circuit board (PCB) and including:
a reserved internal layer for an integrated antenna; and
an additional electrical connection between the radio processor and the reserved internal layer.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Downlink Signal Transceiving Method And Device, In Wireless Communication System, Taking Into Account Antenna Port Relationship

Technical Field and Background:
Multiple-Input Multiple-Output (MIMO) technology is a technology for improving efficiency of data transmission and reception using multiple transmit antennas and multiple receive antennas rather than using one transmit antenna and one receive antenna. If a single antenna is used, a receive entity receives data through a single antenna path. In contrast, if multiple antennas are used, the receive entity receives data through several paths, accordingly data transmission rate and throughput may be improved, and the coverage may be extended. To increase multiplexing gain of the MIMO operation, an MIMO transmit entity may use channel state information (CSI) fed back by the MIMO receive entity. The receive entity may determine the CSI by performing channel measurement using a predetermined reference signal (RS) from the transmit entity.

Invention Disclosure:
The present invention relates to a wireless communication system, and more particularly, to a downlink signal transmission and reception method and device taking into account antenna port relationship. A method for the reception of a physical downlink shared channel (PDSCH) signal by a terminal in a wireless communication system, according to one embodiment of the present invention, can comprise: a step for determining a start symbol index for the PDSCH in a downlink subframe; and a step for receiving the PDSCH signal on the basis of the start symbol index. The PDSCH start symbol index (k) when the downlink subframe belongs to a specific subframe set is determined according to k=min(KThreshold, K), KThreshold being a prescribed threshold, K being the PDSCH start symbol index when the downlink subframe does not belong to the specific subframe set, and min(KThreshold, K) being the minimum value among KThreshold and K.

[Assistant]
1. A method for transmitting a physical downlink shared channel (PDSCH) by a base station (BS) in a wireless communication system, the method comprising:
transmitting, to a user equipment (UE), at least one quasi co-location (QCL) parameter set including information on a specific subframe set; and
transmitting, to the UE, the PDSCH in a subframe based on a PDSCH start symbol index of the subframe,
wherein when the subframe belongs to the specific subframe set, the PDSCH start symbol index corresponds to an equation k=min (K Threshold, K),
wherein ‘k’ is the PDSCH start symbol index, ‘K Threshold ’ is a predetermined threshold, ‘K’ is one of given values including a first value from the at least one QCL parameter set and a second value from a physical control format indication channel (PCFICH), and ‘min (K Threshold, K)’ denotes a minimum value among ‘K Threshold ’ and ‘K’.

2. The method of claim 1, wherein when the subframe does not belong to the specific subframe set, the PDSCH start symbol index corresponds to ‘K’.

3. The method of claim 1, further comprising:
transmitting, to the UE, a physical downlink control channel (PDCCH) or an enhanced PDCCH (EPDCCH) for scheduling the PDSCH based on a predetermined downlink control channel (DCI) format.

4. The method of claim 3, wherein when the predetermined DCI format corresponds to a DCI format 2D for a coordinated multi-point (CoMP) operation, ‘K’ is determined according to a PDSCH start symbol value included in a QCL parameter set indicated by the DCI format 2D among the at least one QCL parameter set.

5. The method of claim 3, wherein when the predetermined DCI format corresponds to a DCI format 1A for a fallback operation, the value K is determined according to a PDSCH start symbol value included in a QCL parameter set having a lowest index among the at least one QCL parameter set.

6. The method of claim 1, the specific subframe set is a Multicast Broadcast Single Frequency Network (MBSFN) subframe set.

7. The method of claim 1, wherein ‘K Threshold ’ is 2.

8. The method of claim 1, wherein each of the at least one QCL parameter set further comprises at least one of a PDSCH start symbol value, number-of-cell-specific reference signal (CRS) ports information, CRS frequency shift information, Zero Power Channel State Information-Reference Signal (ZP CSI-RS) configuration information, and Non-Zero Power (NZP) CSI-RS configuration information.

9. The method of claim 1, wherein the UE is set to transmission mode 10 (TM10).

10. A base station (BS) comprising:
a transmitter configured to transmit a signal to a user equipment (UE); and
a processor configured to control the transmitter to:
transmit at least one quasi co-location (QCL) parameter set including information on a specific subframe set and information on a physical downlink shared channel (PDSCH) start symbol, and
transmit a PDSCH in a subframe based on a PDSCH start symbol index of the subframe,
wherein when the subframe belongs to the specific subframe set, the PDSCH start symbol index corresponds to an equation k=min (K Threshold, K),
wherein ‘k’ is the PDSCH start symbol index, ‘K Threshold ’ is a predetermined threshold, ‘K’ is one of given values including a first value from the at least one QCL parameter set and a second value from a physical control format indication channel (PCFICH), and ‘min (K Threshold, K)’ denotes a minimum value among ‘K Threshold ’ and ‘K’.

11. The BS of claim 10, wherein when the subframe does not belong to the specific subframe set, the PDSCH start symbol index corresponds to ‘K’.

12. The BS of claim 10, wherein the processor controls to transmitter to:
transmit a physical downlink control channel (PDCCH) or an enhanced PDCCH (EPDCCH) for scheduling the PDSCH based on a predetermined downlink control channel (DCI) format.

13. The BS of claim 12, wherein when the predetermined DCI format corresponds to a DCI format 2D for a coordinated multi-point (CoMP) operation, ‘K’ is determined according to a PDSCH start symbol value included in a QCL parameter set indicated by the DCI format 2D among the at least one QCL parameter set.

14. The BS of claim 12, wherein when the predetermined DCI format corresponds to a DCI format 1A for a fallback operation, the value K is determined according to a PDSCH start symbol value included in a QCL parameter set having a lowest index among the at least one QCL parameter set.

15. The BS of claim 10, the specific subframe set is a Multicast Broadcast Single Frequency Network (MBSFN) subframe set.

16. The BS of claim 10, wherein ‘K Threshold ’ is 2.

17. The BS of claim 10, wherein each of the at least one QCL parameter set further comprises at least one of number-of-cell-specific reference signal (CRS) ports information, CRS frequency shift information, Zero Power Channel State Information-Reference Signal (ZP CSI-RS) configuration information, and Non-Zero Power (NZP) CSI-RS configuration information.

18. The BS of claim 10, wherein the UE is set to transmission mode 10 (TM10).

19. A method for receiving a physical downlink shared channel (PDSCH) by a user equipment (UE) in a wireless communication system, the method comprising:
receiving, from a base station (BS), at least one quasi co-location (QCL) parameter set including information on a specific subframe set and information on a PDSCH start symbol; and
receiving, from the BS, the PDSCH in a subframe based on a PDSCH start symbol index of the subframe,
wherein when the subframe belongs to the specific subframe set, the PDSCH start symbol index corresponds to an equation k=min (K Threshold, K), and
wherein ‘k’ is the PDSCH start symbol index, ‘K Threshold ’ is a predetermined threshold, ‘K’ is one of given values including a firsts value from the at least one QCL parameter set and a second value from a physical control format indication channel (PCFICH), and ‘min (K Threshold, K)’ denotes a minimum value among ‘K Threshold ’ and ‘K’.

20. A user equipment (UE) comprising:
a receiver configured to receive a signal from a base station (BS); and
a processor configured to control the receiver to:
receive at least one quasi co-location (QCL) parameter set including information on a specific subframe set and information on a physical downlink shared channel (PDSCH) start symbol; and
receive a PDSCH in a subframe based on a PDSCH start symbol index of the subframe,
wherein when the subframe belongs to the specific subframe set, the PDSCH start symbol index corresponds to an equation k=min (K Threshold, K), and
wherein ‘k’ is the PDSCH start symbol index, ‘K Threshold ’ is a predetermined threshold, ‘K’ is one of given values including a firsts value from the at least one QCL parameter set and a second value from a physical control format indication channel (PCFICH), and ‘min (K Threshold, K)’ denotes a minimum value among ‘K Threshold ’ and ‘K’.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Semiconductor Device

Technical Field and Background:
SiC (silicon carbide) is superior in dielectric breakdown resistance and thermal conductivity etc. to Si (silicon). Therefore, SiC is watched with interest as a semiconductor suitable to a use for an inverter of a hybrid car or the like, for example. More specifically, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) employing SiC is expected as a high withstand voltage device suitable to an inverter of a hybrid car or the like. A MOSFET (Metal Oxide Semiconductor Field Effect Transistor) as an example of a MISFET employing SiC has an SiC-MOS structure obtained by stacking a gate electrode on an SiC substrate through a gate insulating film made of SiO 2 (silicon oxide). A well region is formed on a surface layer portion of the SiC substrate. A source region and a drain region are formed on a surface layer portion of the well region at an interval from each other. The gate insulating film is formed on a region between the source region and the drain region.

Invention Disclosure:
A semiconductor device includes a semiconductor layer made of first conductivity type semiconductor layer; a second conductivity type well region formed on the semiconductor layer and having a channel region; a first conductivity type source region formed on the well region and including a first region adjacent to the well region and a second region adjacent to the first region; a gate insulating film formed on the semiconductor layer and having a first portion that contacts the first region; a second portion that contacts the well region and that has a thickness that is the same as that of the first portion; and a third portion that contacts the second region and that has a thickness that is greater than that of the first portion; and a gate electrode formed on the gate insulating film and opposed to the channel region where a channel is formed through the gate insulating film.

[Assistant]
1. A semiconductor device, comprising:
a semiconductor layer that is a first conductivity type semiconductor layer;
a well region that is a second conductivity type well region formed on a surface layer portion of the semiconductor layer and that has a channel region defined therein;
a source region that is a first conductivity type source region formed on a surface layer portion of the well region and that includes a first region defined adjacent to the well region and a second region defined adjacent to the first region;
a gate insulating film formed on the semiconductor layer and having defined therein:
a first portion that contacts the first region of the source region;
a second portion that contacts the well region and that has a thickness that is the same as that of the first portion; and
a third portion that contacts the second region of the source region and that has a thickness that is greater than that of the first portion; and
a gate electrode formed on the gate insulating film and opposed to the channel region of the well region where a channel is formed through the gate insulating film,
wherein the interface between the semiconductor layer and the gate insulating film is hydrogen-terminated.

2. The semiconductor device according to claim 1, wherein the gate insulating film has a thickness which varies between the surface of the first region of the source region and the surface of the second region of the source region so that a step difference is formed and the third portion of the gate insulating film has a thickness that is greater than that of the first portion of the gate insulating film.

3. The semiconductor device according to claim 1, wherein the source region and the channel region are adjacently formed in a direction along the upper surface of the semiconductor layer, and the gate insulating film is formed on the upper surface of the semiconductor layer.

4. The semiconductor device according to claim 1, wherein the source region and the channel region are adjacently formed in a direction orthogonal to the upper surface of the semiconductor layer, wherein a trench is formed in the semiconductor layer that extends downwardly from the upper surface of the source region to pass through the source region and the well region, and wherein the gate insulating film is formed on the inner surface of the trench.

5. The semiconductor device according to claim 1, wherein the first region of the source region has an impurity concentration that is less than that of the second region of the source region.

6. The semiconductor device according to claim 1, further comprising a contact region that is a second conductivity type contact region formed to pass through both the first region and the second region of the source region.

7. A semiconductor device, comprising:
a semiconductor layer that is a first conductivity type semiconductor layer;
a well region that is a second conductivity type well region formed on a surface layer portion of the semiconductor layer and having a channel region defined therein;
a source region that is a first conductivity type source region formed on a surface layer portion of the well region and that includes a first region defined adjacent to the well region and a second region defined adjacent to the first region, the first region having an impurity concentration that is lower than that of the second region;
a gate insulating film formed on the semiconductor layer and having defined therein:
a first portion that contacts the first region of the source region;
a second portion that contacts the well region and that has a thickness that is the same as that of the first portion; and
a third portion that contacts the second region and that has a thickness that is greater than that of the first portion; and
a gate electrode formed on the gate insulating film and opposed to the channel region of the well region where a channel is formed through the gate insulating film,
wherein a drain metal is formed on the lower surface side of the semiconductor layer.

8. The semiconductor device according to claim 7, wherein the gate insulating film has a thickness which varies between the surface of the first region of the source region and the surface of the second region of the source region so that a step difference is formed and the third portion of the gate insulating film has a thickness that is greater than that of the first portion of the gate insulating film.

9. The semiconductor device according to claim 7, wherein the source region and the channel region are adjacently formed in a direction along the upper surface of the semiconductor layer, and wherein the gate insulating film is formed on the upper surface of the semiconductor layer.

10. The semiconductor device according to claim 7, wherein the source region and the channel region are adjacently formed in a direction orthogonal to the upper surface of the semiconductor layer, wherein a trench is formed in the semiconductor layer that extends downwardly from the upper surface of the source region to pass through the source region and the well region, and wherein the gate insulating film is formed on the inner surface of the trench.

11. The semiconductor device according to claim 7, further comprising a contact region that is a second conductivity type contact region formed to pass through both of the first region and the second region of the source region.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Network Service Access Control

Technical Field and Background:
Many computing devices configured for telecommunications, such as smartphones, are capable of processing various types and encodings of media and interacting with various network services in addition to, e.g., two-party voice telephone calls. Examples of such media or services can include video calling or multi-party conferencing. Cellular and other portable communications devices may connect with networks of varying capability either within a communication session or between communication sessions.

Invention Disclosure:
In some implementations, a telecommunications network can include an anchoring network device. The anchoring network device can receive, from a first party of a communication session, a service message including information of a first session attribute and associated with identification information of a party of the communication session. The anchoring network device can retrieve, from an authorization registry, authorization information corresponding to the identification information. In response to the authorization information indicating the first capability is not permitted, the anchoring network device can determine a status message based at least in part on the service message and transmit the status message via a communications interface. The status message can include a service-failure message or a second service message including information of a second, different session attribute.

[Assistant]
1. A telecommunications network, comprising:
a home subscriber server (HSS);
an authorization server that is different from the HSS; and
an anchoring network device communicatively connectable with user equipment, wherein the anchoring network device is configured to:
receive from the user equipment a first service message associated with a communication session, the first service message including information of a first session attribute;
determine identification information of the user equipment, wherein the user equipment is associated with a first party of one or more parties of the communication session and the identification information identifies a visited network in which the user equipment is roaming;
retrieve authorization information corresponding to the identification information from the authorization server;
in response to the authorization information indicating the first session attribute is not permitted, determine a second session attribute different from the first session attribute based at least in part on the first session attribute;
determine a second service message including information of the second session attribute; and
transmit the second service message to one or more parties of the telecommunication session via a communications interface of the anchoring network device.

2. The telecommunications network of claim 1, wherein the first session attribute and the second session attribute comprise respective capabilities.

3. The telecommunications network of claim 2, wherein the first session attribute is a video capability and the second session attribute is an audio capability.

4. The telecommunications network of claim 1, wherein the first session attribute comprises a first set of one or more parties, and the second session attribute comprises a second set of one or more parties including fewer than all of the parties in the first set of one or more parties.

5. The telecommunications network of claim 1, wherein the first session attribute and the second session attribute comprise respective protocols.

6. The telecommunications network of claim 1, wherein the user equipment is associated with the first party of the telecommunication session and the one or more parties includes a second party different from the first party.

7. The telecommunications network of claim 1, wherein the anchoring network device comprises a Rich Communication Suite (RCS) anchoring network device.

8. The telecommunications network of claim 5, wherein the first session attribute comprises a Rich Communication Suite (RCS) protocol and the second session attribute comprises at least one of a Short Message Service (SMS) protocol or a Multimedia Message Service (MIMS) protocol.

9. The telecommunications network of claim 1, wherein the anchoring network device is further configured to extract or derive the identification information from a P-Visited-Network-ID header of a Session Initiation Protocol (SIP) request.

10. The telecommunications network according to claim 9, wherein the anchoring network device is further configured to receive the identification information via Lightweight Directory Access Protocol (LDAP) or Simple Object Access Protocol (SOAP) over Hypertext Transfer Protocol (HTTP).

11. The telecommunications network according to claim 1, wherein the anchoring network device is further configured to, before retrieving the authorization information:
receive, from the HSS, service-access information associated with the first party; and
determine that the first service attribute is permitted in the communication session.

12. The telecommunications network according to claim 1, wherein the identification information further identifies a mobile virtual network operator (MVNO) associated with the user equipment.

13. The telecommunications network according to claim 1, wherein the authorization server comprises a computer-readable memory and is configured to:
receive a modification instruction via a communications interface of the authorization server; and
in response, modify a mapping between identification information and authorization information stored in the computer-readable memory.

14. A method comprising, by a processor of an anchoring network device of a telecommunications network:
receiving, from user equipment of a telecommunications network, a first service message associated with a communication session, the first service message including information of a first session attribute;
determining identification information of the user equipment, wherein the user equipment is associated with a first party of one or more parties of the communication session and the identification information identifies a visited network in which the user equipment is roaming;
retrieving authorization information corresponding to the identification information from the authorization server;
in response to the authorization information indicating the first session attribute is not permitted, determining a second session attribute different from the first session attribute based at least in part on the first session attribute;
determining a second service message including information of the second session attribute; and
transmitting the second service message to one or more parties of the telecommunication session via a communications interface of the anchoring network device.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Goa Circuit Of Reducing Feed-Through Voltage

Technical Field and Background:
The Liquid Crystal Display (LCD) possesses advantages of thin body, power saving and no radiation to be widely used in many application scope, such as LCD TV, mobile phone, personal digital assistant (PDA), digital camera, notebook, laptop, and dominates the flat panel display field. The GOA technology, i.e. the Gate Driver on Array technology utilizes the original array manufacture processes of the liquid crystal display panel to manufacture the driving circuit of the level scan lines on the substrate around the active area, to replace the external Integrated Circuit (IC) for accomplishing the driving of the level scan lines. The GOA technology can reduce the bonding procedure of the external IC and has potential to raise the productivity and lower the production cost. Meanwhile, it can make the liquid crystal display panel more suitable to the narrow frame or non frame design of display products. FIG. 1 shows a common GOA circuit according to prior art, comprising a plurality of GOA units which are cascade coupled. n is set to be a positive integer, and the GOA unit of the nth stage comprises: a first thin film transistor T 1 , and a gate of the first thin film transistor T 1 is electrically coupled to a forward scan control signal U 2 D, and a source is electrically coupled to an output end G(n−1) of a n−1th GOA unit of the former stage, and a drain is electrically coupled to a source of a third thin film transistor T 3 ; and a second thin film transistor T 2 , a gate of the second thin film transistor T 2 is electrically coupled to a backward scan control signal D 2 U, and a source is electrically coupled to an output end G(n+1) of a n+1th GOA unit of the latter stage, and a drain is electrically coupled to the source of the third thin film transistor T 3 ; the third thin film transistor T 3 , and a gate of the third thin film transistor T 3 is electrically coupled to a first clock signal CK( 1 ), and a drain is electrically coupled to a gate of a fourth thin film transistor T 4 ; the fourth thin film transistor T 4 , and a gate of the fourth thin film transistor T 4 is electrically coupled to a source of a seventh thin film transistor T 7 , and a drain is electrically coupled to a second node P(n), and a source is electrically coupled to the first clock signal CK( 1 ); a fifth thin film transistor T 5 , and a gate of the fifth thin film transistor T 5 is electrically coupled to the first clock signal CK( 1 ), and a drain is electrically coupled to the second node P(n), and a source is electrically coupled to a constant high voltage level VGH; a sixth thin film transistor T 6 , and a gate of the thin film transistor T 6 is electrically coupled to the second node P(n), and a source is electrically coupled to a drain of the seventh thin film transistor T 7 , and a drain is electrically coupled to a constant low voltage level VGL; the seventh thin film transistor T 7 , and a gate of the seventh thin film transistor T 7 is electrically coupled to a second clock signal CK( 2 ), and a source is electrically coupled to a source of an eighth thin film transistor T 8 ; the eighth thin film transistor T 8 , and a gate of the eighth thin film transistor T 8 is electrically coupled to the constant high voltage level VGH, and a drain is electrically coupled to a first node Q(n); a ninth thin film transistor T 9 , and a gate of the thin film transistor T 9 is electrically coupled to the first node Q(n), and a source is electrically coupled to the second clock signal CK(n), and a drain is electrically coupled to an output end G(n); a tenth thin film transistor T 10 , and a gate of the tenth thin film transistor T 10 is electrically coupled to the second node P(n), and a drain is electrically coupled to the output end G(n), and a source is electrically coupled to the constant low voltage level VGL; a first capacitor C 1 , and one end of the first capacitor C 1 is electrically coupled to the first node Q(n), and the other end is electrically coupled to the output end G(n); a second capacitor C 2 , and one end of the second capacitor C 2 is electrically coupled to the second node P(n), and the other end is electrically coupled to the constant low voltage level VGL.

Invention Disclosure:
The present invention provides a GOA circuit of reducing feed-through voltage. An eleventh thin film transistor (T11) and a first capacitor (R1) coupled to the eleventh thin film transistor (T11) in series are added in a pull-down output unit (400). In the output process of the GOA circuit, the eleventh thin film transistor (T11) is activated with the added output control signal (CKF). With the voltage division function of the first resistor (R1), one more falling edge is generated to the waveform outputted by the output end (G(n)). Namely, the waveform outputted by the output end (G(n)) comprises two falling edges. Thereby, the voltage difference before and after the gate of the TFT in the pixel can be decreased to reduce the feed-through voltage and raise the display uniformity of the liquid crystal panel.

[Assistant]
1. A GOA circuit of reducing feed-through voltage, comprising a plurality of GOA units, which are cascade coupled, and the GOA unit of each stage comprises: a forward-backward scan control unit, a pull-up output unit, a first node pull-down unit, a pull-down output unit and a third thin film transistor;
n is set to be a positive integer, and except the GOA unit of the first and last stages, in the GOA unit of the nth stage:
the forward-backward scan control unit comprises: a first thin film transistor, and a gate of the first thin film transistor is electrically coupled to a forward scan control signal, and a source is electrically coupled to an output end of a n−1th GOA unit of the former stage, and a drain is electrically coupled to a source of the third thin film transistor; and a second thin film transistor, a gate of the second thin film transistor is electrically coupled to a backward scan control signal, and a source is electrically coupled to an output end of a n+1th GOA unit of the latter stage, and a drain is electrically coupled to the source of the third thin film transistor;
a gate of the third thin film transistor is electrically coupled to a Mth clock signal, and the source is electrically coupled to the drain of the first thin film transistor and the drain of the second thin film transistor, and a drain is electrically coupled to a gate of a fourth thin film transistor;
the pull-up output unit comprises: a ninth thin film transistor, and a gate of the ninth thin film transistor is electrically coupled to a first node, and a source is electrically coupled to a M+1th clock signal, and a drain is electrically coupled to an output end; and a first capacitor, one end of the first capacitor is electrically coupled to the first node, and the other end is electrically coupled to the output end;
the pull-down output unit comprises: a fourth thin film transistor, and a gate of the fourth thin film transistor is electrically coupled to the drain of the third thin film transistor, and a drain is electrically coupled to a second node, and a source is electrically coupled to the Mth clock signal; a fifth thin film transistor, and a gate of the fifth thin film transistor is electrically coupled to the Mth clock signal, and a drain is electrically coupled to the second node, and a source is electrically coupled to a constant high voltage level; a tenth thin film transistor, and a gate of the tenth thin film transistor is electrically coupled to the second node, and a drain is electrically coupled to the output end, and a source is electrically coupled to a constant low voltage level; an eleventh thin film transistor, and a gate of the eleventh thin film transistor is electrically coupled to an output control signal, and a drain is electrically coupled to the output end, and a source is electrically coupled to one end of a first resistor; the first resistor, the other end of the first resistor is electrically coupled to the constant low voltage level, and a second capacitor, and one end of the second capacitor is electrically coupled to the second node, and the other end is electrically coupled to the constant low voltage level;
the first node pull-down unit comprises: a sixth thin film transistor, and a gate of the sixth thin film transistor is electrically coupled to the second node, and a source is electrically coupled to a drain of a seventh thin film transistor, and a drain is electrically coupled to the constant low voltage level; the seventh thin film transistor, and a gate of the seventh thin film transistor is electrically coupled to the M+1th clock signal, and a source is electrically coupled to the drain of the third thin film transistor, and a drain is electrically coupled to the source of the sixth thin film transistor; and an eighth thin film transistor, and a gate of the eighth thin film transistor is electrically coupled to the constant high voltage level, and a source is electrically coupled to the drain of the third thin film transistor, and a source is electrically coupled to the first node;
the output control signal is a pulse signal, of which a period is ½ of a clock signal period;
a signal waveform outputted by the output end comprises two falling edges.

2. The GOA circuit of reducing feed-through voltage according to claim 1, wherein in the GOA unit of the first stage, a source of the first thin film transistor is coupled to a circuit start signal.

3. The GOA circuit of reducing feed-through voltage according to claim 1, wherein in the GOA unit of the last stage, a source of the second thin film transistor is electrically coupled to a start signal.

4. The GOA circuit of reducing feed-through voltage according to claim 1, wherein as the forward scan control signal provides high voltage level, and the backward scan control signal provides low voltage level, the GOA circuit performs forward scan, and as the forward scan control signal provides low voltage level, and the backward scan control signal provides high voltage level, the GOA circuit performs backward scan.

5. The GOA circuit of reducing feed-through voltage according to claim 1, wherein the clock signal comprises two clock signals: a first clock signal and a second clock signal; as the Mth clock signal is the first clock signal, the M+1th clock signal is the second clock signal; as the Mth clock signal is the second clock signal, the M+1th clock signal is the first clock signal.

6. The GOA circuit of reducing feed-through voltage according to claim 1, wherein in one period of the output control signal, a rising edge of the output control signal is generated at a high voltage level phase of the M+1th clock signal, and a falling edge is generated simultaneously with a falling edge of the M+1th clock signal.

7. The GOA circuit of reducing feed-through voltage according to claim 1, wherein a high voltage level of the M+1th clock signal and a voltage level of the constant high voltage level are the same.

8. The GOA circuit of reducing feed-through voltage according to claim 7, wherein a voltage level of the first falling edge of a signal waveform outputted by the output end is dropped between the constant high voltage level and the constant low voltage level.

9. The GOA circuit of reducing feed-through voltage according to claim 8, wherein a channel width to length ratio of the eleventh thin film transistor and a resistance of the first resistor are adjusted to control a voltage level that the first falling edge of the signal waveform outputted by the output end drops to.

10. The GOA circuit of reducing feed-through voltage according to claim 1, wherein the thin film transistors are all N type LTPS semiconductor thin film transistors.

11. A GOA circuit of reducing feed-through voltage, comprising a plurality of GOA units, which are cascade coupled, and the GOA unit of each stage comprises: a forward-backward scan control unit, a pull-up output unit, a first node pull-down unit, a pull-down output unit and a third thin film transistor;
n is set to be a positive integer, and except the GOA unit of the first and last stages, in the GOA unit of the nth stage:
the forward-backward scan control unit comprises: a first thin film transistor, and a gate of the first thin film transistor is electrically coupled to a forward scan control signal, and a source is electrically coupled to an output end of a n−1th GOA unit of the former stage, and a drain is electrically coupled to a source of the third thin film transistor; and a second thin film transistor, a gate of the second thin film transistor is electrically coupled to a backward scan control signal, and a source is electrically coupled to an output end of a n+1th GOA unit of the latter stage, and a drain is electrically coupled to the source of the third thin film transistor;
a gate of the third thin film transistor is electrically coupled to a Mth clock signal, and the source is electrically coupled to the drain of the first thin film transistor and the drain of the second thin film transistor, and a drain is electrically coupled to a gate of a fourth thin film transistor;
the pull-up output unit comprises: a ninth thin film transistor, and a gate of the ninth thin film transistor is electrically coupled to a first node, and a source is electrically coupled to a M+1th clock signal, and a drain is electrically coupled to an output end; and a first capacitor, one end of the first capacitor is electrically coupled to the first node, and the other end is electrically coupled to the output end;
the pull-down output unit comprises: a fourth thin film transistor, and a gate of the fourth thin film transistor is electrically coupled to the drain of the third thin film transistor, and a drain is electrically coupled to a second node, and a source is electrically coupled to the Mth clock signal; a fifth thin film transistor, and a gate of the fifth thin film transistor is electrically coupled to the Mth clock signal, and a drain is electrically coupled to the second node, and a source is electrically coupled to a constant high voltage level; a tenth thin film transistor, and a gate of the tenth thin film transistor is electrically coupled to the second node, and a drain is electrically coupled to the output end, and a source is electrically coupled to a constant low voltage level; an eleventh thin film transistor, and a gate of the eleventh thin film transistor is electrically coupled to an output control signal, and a drain is electrically coupled to the output end, and a source is electrically coupled to one end of a first resistor; the first resistor, the other end of the first resistor is electrically coupled to the constant low voltage level, and a second capacitor, and one end of the second capacitor is electrically coupled to the second node, and the other end is electrically coupled to the constant low voltage level;
the first node pull-down unit comprises: a sixth thin film transistor, and a gate of the sixth thin film transistor is electrically coupled to the second node, and a source is electrically coupled to a drain of a seventh thin film transistor, and a drain is electrically coupled to the constant low voltage level; the seventh thin film transistor, and a gate of the seventh thin film transistor is electrically coupled to the M+1th clock signal, and a source is electrically coupled to the drain of the third thin film transistor, and a drain is electrically coupled to the source of the sixth thin film transistor; and an eighth thin film transistor, and a gate of the eighth thin film transistor is electrically coupled to the constant high voltage level, and a source is electrically coupled to the drain of the third thin film transistor, and a source is electrically coupled to the first node;
the output control signal is a pulse signal, of which a period is ½ of a clock signal period;
a signal waveform outputted by the output end comprises two falling edges;
wherein in the GOA unit of the first stage, the source of the first thin film transistor is electrically coupled to a start signal;
wherein in the GOA unit of the last stage, the source of the second thin film transistor is electrically coupled to a start signal;
wherein as the forward scan control signal provides high voltage level, and the backward scan control signal provides low voltage level, the GOA circuit performs forward scan, and as the forward scan control signal provides low voltage level, and the backward scan control signal provides high voltage level, the GOA circuit performs backward scan.

12. The GOA circuit of reducing feed-through voltage according to claim 11, wherein the clock signal comprises two clock signals: a first clock signal and a second clock signal; as the Mth clock signal is the first clock signal, the M+1th clock signal is the second clock signal; as the Mth clock signal is the second clock signal, the M+1th clock signal is the first clock signal.

13. The GOA circuit of reducing feed-through voltage according to claim 11, wherein in one period of the output control signal, a rising edge of the output control signal is generated at a high voltage level phase of the M+1th clock signal, and a falling edge is generated simultaneously with a falling edge of the M+1th clock signal.

14. The GOA circuit of reducing feed-through voltage according to claim 11, wherein a high voltage level of the M+1th clock signal and a voltage level of the constant high voltage level are the same.

15. The GOA circuit of reducing feed-through voltage according to claim 14, wherein a voltage level of the first falling edge of a signal waveform outputted by the output end is dropped between the constant high voltage level and the constant low voltage level.

16. The GOA circuit of reducing feed-through voltage according to claim 15, wherein a channel width to length ratio of the eleventh thin film transistor and a resistance of the first resistor are adjusted to control a voltage level that the first falling edge of the signal waveform outputted by the output end drops to.

17. The GOA circuit of reducing feed-through voltage according to claim 11, wherein the thin film transistors are all N type LTPS semiconductor thin film transistors.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Tactical-Gear Interconnection System Apparatus And Method

Technical Field and Background:
The present invention provides a tactical-gear interconnection system apparatus and method allowing for connection of a variety of tactical gear such as gun stocks, camera supports, sights and rangefinders, grips, and clamps, in field-interchangeable configurations. Apart from the Picatinny-rail and earlier Weaver-rail standards, there exists no standard for removable connection among different pieces of tactical gear. The Picatinny-rail system is designed for mounting relatively small things onto a gun, and is not meant to withstand the considerable strain that results from connecting large or heavy pieces together, or from connecting the various pieces in such a way that the connection acts as a part of the supporting structure of the whole. When the Picatinny-rail system is pressed into service for making structural connections, it is subject to failure. Such failure in the field is, at best, undesirable, and at worst may be life-threatening. In the field, people are called upon to make emergency repairs to tactical gear and to reconfigure gear in order to meet unexpected conditions. There is a need for a system of removable connections among various pieces of tactical gear that is standardized, with interchangeable parts; that is durable; and that is simple enough for the making and unmaking of connections to be done blindfolded or in otherwise challenging conditions.

Invention Disclosure:
A tactical-gear interconnection system apparatus and method allowing connection of a variety of tactical gear such as gun stocks, camera supports, sights, rangefinders, grips, and clamps, in field-interchangeable configurations responsive to changes in field conditions, by providing same-sized threaded plug units on all gear and same-sized interchangeable unions for removable connection of various pieces of gear.

[Assistant]
1. A tactical-gear interconnection system apparatus for removably connecting a variety of pieces of tactical gear, comprising:
(i) a plurality of plug units of the same size, affixed to tactical gear; and
(ii) a union having two sockets of the same size as said plug units, said union comprising:
(a) an internal-external threaded section, said internal-external threaded section having an interior surface and an exterior surface, having internal threads extending substantially along the entire interior surface and external threads extending substantially along the entire exterior surface, an open end, defining a socket sized to accommodate any said plug unit, and a closed end having a flat surface, the exterior surface of the internal-external threaded section defining a larger plug having a larger diameter;
(b) an internal-only threaded section having internal threads and an open end, defining a socket sized to accommodate any said plug unit, having an external body surface not larger than the larger diameter of said internal-external threaded section, and having a closed end having a flat surface extending beyond the external body surface and having a diameter larger than the larger diameter of said internal-external threaded section; and
(c) an internally threaded collar having internal threads and a first open end defining a larger socket sized to accommodate the larger plug of said internal-external threaded section, and a second open end having a central opening of the same size as the larger diameter of said internal-external threaded section, and a circumferential solid projection adapted to make contact with the flat surface extending beyond the external body surface of said internal-only threaded section;
where, in use, said internally threaded collar pushes said internal-only threaded section nominally downward while at the same time pulling said internal-external threaded section nominally upward, causing the two flat surfaces to be pressed together face to face; and
where two pieces of tactical gear affixed one each to said plug units, when connected to the respective socket of said internal-external threaded section and said internal-only threaded section, removably connect one piece of tactical gear to the other.

2. The tactical-gear interconnection system apparatus of claim 1, where said plug units are added to tactical gear during the manufacturing of the tactical gear.

3. The tactical-gear interconnection system apparatus of claim 1, where said plug units are added to tactical gear by retrofitting.

4. The tactical-gear interconnection system apparatus of claim 1, where components of said union are made of electrically conductive material.

5. The tactical-gear interconnection system apparatus of claim 1, where components of said union are made of electrically non-conductive material.

6. The tactical-gear interconnection system apparatus of claim 1, where the orientation of the socket in said internal-external threaded section in relation to the socket in said internal-only threaded section is essentially a straight line, with the sockets facing essentially 180-degree opposite directions.

7. The tactical-gear interconnection system apparatus of claim 1, said union further comprising said internal-external threaded section and said internal-only threaded section having sockets sized to accommodate different-sized plug units.

8. The tactical-gear interconnection system apparatus of claim 1, where size of said plug units is 1-inch diameter.

9. A tactical-gear interconnection system method for removably connecting a variety of pieces of tactical gear, comprising:
(i) providing a tactical-gear interconnection system apparatus, comprising:
(a) a plurality of plug units of the same size, affixed to tactical gear; and
(b) a union having two sockets of the same size as said plug units, said union comprising:
(1) an internal-external threaded section, said internal-external threaded section having an interior surface and an exterior surface, having internal threads extending substantially along the entire interior surface and external threads extending substantially along the entire exterior surface, an open end, defining a socket sized to accommodate any said plug unit, and a closed end having a flat surface, the exterior surface of the internal-external threaded section defining a larger plug having a larger diameter;
(2) an internal-only threaded section having internal threads and an open end, defining a socket sized to accommodate any said plug unit, having an external body surface not larger than the larger diameter of said internal-external threaded section, and having a closed end having a flat surface extending beyond the external body surface and having a diameter larger than the larger diameter of said internal-external threaded section; and
(3) an internally threaded collar having internal threads and a first open end defining a larger socket sized to accommodate the larger plug of said internal-external threaded section, and a second open end having a central opening of the same size as the larger diameter of said internal-external threaded section, and a circumferential solid projection adapted to make contact with the flat surface extending beyond the external body surface of said internal-only threaded section;

10. The tactical-gear interconnection system method of claim 9, where said plug units are added to tactical gear during the manufacturing of the tactical gear.

11. The tactical-gear interconnection system method of claim 9, where said plug units are added to tactical gear by retrofitting.

12. The tactical-gear interconnection system method of claim 9, where components of said union are made of electrically conductive material.

13. The tactical-gear interconnection system method of claim 9, where components of said union are made of electrically non-conductive material.

14. The tactical-gear interconnection system method of claim 9, where the orientation of the socket in said internal-external threaded section in relation to the socket in said internal-only threaded section is essentially a straight line, with the sockets facing essentially 180-degree opposite directions.

15. The tactical-gear interconnection system method of claim 9, said union further comprising said internal-external threaded section and said internal-only threaded section having sockets sized to accommodate different-sized plug units.

16. The tactical-gear interconnection system method of claim 9, where size of said plug unit is 1-inch diameter.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Speaker And Microphone Integrated Display Panel

Technical Field and Background:
1. Field The disclosure relates generally to a speaker and microphone integrated display panel, and more particularly, to a speaker and microphone integrated display panel in which a film type speaker serving both as a speaker and a microphone is integrated with a display panel to be drive-connected. 2. Description of the Related Art Recently, with the information age in full swing, display technology has advanced rapidly. Various flat panel displays having excellent performance in terms of reduction in thickness, weight, and power consumption have been correspondingly developed and are quickly replacing an existing cathode ray tube (CRT). Specific examples of such flat panel displays include a liquid crystal display (LCD), a plasma display panel (PDP) device, an field emission display (FED) device, an electro luminescence display (ELD) device, and the like, each of which commonly have a flat display panel for implementing an image. The flat display panel has a configuration in which a pair of transparent insulation substrates is bonded to each other while facing each other with a light emitting or polarization material layer therebetween. In particular, the liquid crystal display has a liquid crystal cell between the pair of transparent insulation substrates, in order to display an image by controlling light transmittance of a liquid crystal by using an electric field. The field emission display device may include a substrate providing a pixel area and a peripheral area, and a flexible thin film encapsulation (TFE) layer for encapsulation in which at least one inorganic layer and at least one organic layer are alternately stacked on the substrate to seal the substrate. These flat panel displays each include a display area displaying an image, and a non-display area located around the display area. In the non-display area, pads connected to a driver IC and wires connecting the display area and the pads are formed. Further, the pads are connected to an external flexible printed circuit board (FPCB) to receive a signal from an external source. In a speaker and microphone attached display device of the related art, separate PCBs, which are connected with wires of a display panel, a speaker, and a microphone, respectively, are formed and connected to a system driving circuit unit (not illustrated) within a system including each of the display panel, the speaker, and the microphone. Therefore, the wires of the display panel, the speaker and the microphone need to be connected to the separate PCBs, respectively, and individually connected in the driver IC, which makes circuit integration difficult and cumbersome. Further, since the speaker or the microphone is individually installed externally at a predetermined position with respect to the display panel, there are problems in that it is necessary to consider the orientation at the time of assembling a set and separately assemble the wires of the speaker or the microphone. This makes the assembly process complicated. Also, a plurality of substrates is required, which increases the total thickness and assembly time of the apparatus. The above information disclosed in this Background section is only for enhancement of understanding of the background of the described technology and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.

Invention Disclosure:
Provided is a speaker and microphone integrated display panel including: a display panel having a display area and a non-display area surrounding the display area; and a simultaneously convertible film type speaker or film type microphone which is mounted to correspond to an air hole in the non-display area, in which the display panel and the film type speaker or the film type microphone are at least partially integrated so as to be drive-connected.

[Assistant]
1. A speaker and microphone integrated display panel, comprising:
a display panel having a display area and a non-display area surrounding the display area; and
a simultaneously convertible film type speaker or film type microphone which is mounted to correspond to an air hole in the non-display area,
wherein the display panel and the film type speaker or the film type microphone at are at least partially integrated so as to be drive-connected, and
wherein the display panel includes:
upper and lower substrates arranged opposite to each other,
a window layer positioned so as to protect the upper and lower substrates and having the air hole formed therein,
a polarization layer positioned between the upper substrate and the window layer to polarize light emitted from the upper substrate, and
a synthetic resin passivation layer covering the polarization layer.

2. The speaker and microphone integrated display panel of claim 1, wherein the film type speaker or film type microphone includes:
a film type speaker or microphone substrate,
a protection cap mounted in the air hole to protect the film type speaker or microphone substrate, and
an upper film speaker electrode layer or upper film microphone electrode layer which is an upper electrode layer, and a lower film speaker electrode layer or a lower film microphone electrode layer which is a lower electrode layer, the upper and lower electrode layers being connected to at least one adhesive portion made of an anisotropic conductive material.

3. The speaker and microphone integrated display panel of claim 2, wherein:
the upper substrate and the lower substrate are offset from each other, so as to expose first and second pad portions to which a signal line of the display panel is connected, and
the exposed first and second pad portions are connected to first and second flexible printed circuit (FPC) units, the first and second FPC units also being connected to the lower film speaker electrode layer and the lower film microphone electrode layer.

4. The speaker and microphone integrated display panel of claim 2, wherein:
the upper substrate and the lower substrate are disposed so that at least one edge of the upper substrate is substantially coplanar with at least one edge of the lower substrate,
a common contact pad portion is formed within the synthetic resin passivation layer to be connected to a transparent electrode layer that is both disposed below the polarization layer and connected to first and second flexible printed circuit (FPC) units, and
the first and second FPC units are connected to the lower film speaker electrode layer and the lower film microphone electrode layer.

5. The speaker and microphone integrated display panel of claim 4, wherein:
the lower film speaker electrode layer or the lower film microphone electrode layer comprises a metal electrode layer having greater conductivity than that of the transparent electrode layer.

6. The speaker and microphone integrated display panel of claim 4, wherein:
the upper substrate is a thin film encapsulation (TFE) layer having a plurality of layers that include at least one organic encapsulation layer or inorganic encapsulation layer.

7. The speaker and microphone integrated display panel of claim 6, wherein:
the lower substrate is a flexible substrate comprising at least one of polymethyl methacrylate (PMMA), acryl, and polyester.

8. The speaker and microphone integrated display panel of claim 2, wherein:
the upper substrate and the lower substrate are disposed so that at least one edge of the upper substrate is substantially coplanar with at least one edge of the lower substrate, and
the lower film speaker electrode layer or the lower film microphone electrode layer extends to be connected to a transparent electrode layer disposed below the polarization layer, to thereby be drive-connected.

9. The speaker and microphone integrated display panel of claim 8, wherein:
the lower film speaker electrode layer or the lower film microphone electrode layer comprises a same material as that of the transparent electrode layer.

10. The speaker and microphone integrated display panel of claim 8, wherein:
the upper substrate is a thin film encapsulation (TFE) layer having a plurality of layers that include at least one organic encapsulation layer or inorganic encapsulation layer.

11. The speaker and microphone integrated display panel of claim 2, wherein:
the upper substrate and the lower substrate are disposed so that at least one edge of the upper substrate is substantially coplanar with at least one edge of the lower substrate,
a common contact pad portion is formed within the polarization layer to be connected to a transparent electrode layer that is both disposed within the polarization layer and connected to first and second flexible printed circuit (FPC) units, and
the first and second FPC units are connected to the lower film speaker electrode layer and the lower film microphone electrode layer.

12. The speaker and microphone integrated display panel of claim 11, wherein:
the polarization layer is a rigid polarizer.

13. The speaker and microphone integrated display panel of claim 11, wherein:
the upper substrate is a thin film encapsulation (TFE) layer having a plurality of layers that include at least one organic encapsulation layer or inorganic encapsulation layer, and
the polarization layer comprises a flexible substrate.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Oxide And Manufacturing Method Thereof

Technical Field and Background:
A technique for forming a transistor by using a semiconductor over a substrate having an insulating surface has attracted attention. The transistor is applied to a wide range of semiconductor devices such as an integrated circuit and a display device. Silicon is known as a semiconductor applicable to a transistor. As silicon which is used as a semiconductor of a transistor, either amorphous silicon or polycrystalline silicon is used depending on the purpose. For example, in the case of a transistor included in a large display device, it is preferable to use amorphous silicon, which can be used to form a film on a large substrate with the established technique. In the case of a transistor included in a high-performance display device where a driver circuit and a pixel circuit are formed over the same substrate, it is preferred to use polycrystalline silicon, which can form a transistor having high field-effect mobility. It is known that polycrystalline silicon can be formed as a result of heat treatment at high temperatures or laser light treatment on amorphous silicon. In recent years, transistors including oxide semiconductors (typified by an In—Ga—Zn oxide) have been actively developed. Oxide semiconductors have been researched since early times. In 1988, it was disclosed to use an In—Ga—Zn oxide crystal for a semiconductor element (see Patent Document 1). In 1995, a transistor including an oxide semiconductor was invented, and its electrical characteristics were disclosed (see Patent Document 2). In 2013, one group reported that an amorphous In—Ga—Zn oxide had an unstable structure in which crystallization is induced by irradiation with an electron beam (see Non-Patent Document 1). According to the report, no ordering was observed with a high-resolution transmission electron microscope in the amorphous In—Ga—Zn oxide formed by the group. In 2014, a transistor including a crystalline In—Ga—Zn oxide that has more excellent electrical characteristics and higher reliability than a transistor including an amorphous In—Ga—Zn oxide was reported (see Non-Patent Document 2, Non-Patent Document 3, and Non-Patent Document 4). These documents reported that a grain boundary was not clearly observed in an In—Ga—Zn oxide including a c-axis aligned crystalline oxide semiconductor (CAAC-OS). As a kind of polymer crystal structure, a concept of “paracrystal” is known. A paracrystal seemingly has a trace of crystal lattice; however, compared with an ideal single crystal, the paracrystal has a distorted crystal structure (see Non-Patent Document 5).

Invention Disclosure:
Provided is an oxide with a novel crystal structure, an oxide with high crystallinity, or an oxide with low impurity concentration. An oxide has a hexagonal atomic arrangement in the case of a single crystal. The oxide has a homologous structure of indium, an element M (aluminum, gallium, yttrium, or tin), and zinc. The oxide has a lattice point group observed through an analysis of a first region in a transmission electron microscopy image of a top surface of the oxide. In a Voronoi diagram having a plurality of Voronoi regions obtained through a Voronoi analysis of the lattice point group, a proportion of hexagonal Voronoi regions is higher than or equal to 78% and lower than or equal to 100%.

[Assistant]
1. An oxide comprising:
a homologous structure comprising indium, an element M, and zinc,
wherein the element M is one of aluminum, gallium, yttrium, and tin,
wherein the oxide includes a hexagonal atomic arrangement in the case of a single crystal,
wherein the oxide includes a lattice point group observed through an analysis of a first region in a transmission electron microscopy image of a top surface of the oxide, and
wherein a proportion of hexagonal Voronoi regions to all Voronoi regions in a Voronoi diagram obtained through a Voronoi analysis of the lattice point group is higher than or equal to 78% and lower than or equal to 100%.

2. The oxide according to claim 1,
wherein the first region is subjected to fast Fourier transform to obtain a first image,
wherein the first image is subjected to mask processing except for a range from 2.8 nm −1 to 5.0 nm −1 to obtain a second image,
wherein the second image is subjected to inverse fast Fourier transform to obtain a third image,
wherein noise is removed from the third image to obtain a fourth image, and
wherein lattice points included in the lattice point group are points with maximal luminance in the fourth image.

3. The oxide according to claim 2, wherein luminance within a 0.05-nm radius in the third image is averaged to remove the noise.

4. The oxide according to claim 3,
wherein a first step of extracting a second point with highest luminance within a 0.22-nm radius from a first point and a second step of extracting a third point with highest luminance within a 0.22-nm radius from the second point are repeated until a point with highest luminance is fixed as one of the points with maximal luminance, and
wherein the others of the points with maximal luminance are determined in a manner similar to that for the one of the points with maximal luminance using a point more than 0.22 nm away from the one of the points with maximal luminance as the first point.

5. An oxide comprising:
a homologous structure comprising indium, an element M, and zinc,
wherein the element M is one of aluminum, gallium, yttrium, and tin,
wherein the oxide includes a hexagonal atomic arrangement in the case of a single crystal,
wherein the oxide includes a lattice point group observed through an analysis of a first region in a transmission electron microscopy image of a top surface of the oxide,
wherein the lattice point group comprises lattice points comprising a first lattice point, and second to seventh lattice points adjacent to the first lattice point,
wherein to obtain a strain rate, a regular hexagon in which a distance between a center point and a vertex is an average distance between the first lattice point and each of the second to seventh lattice points is provided such that the center point overlaps with the first lattice point; the regular hexagon is rotated around the center point such that an average deviation amount between the vertex of the regular hexagon and each of the second to seventh lattice points becomes as small as possible; and the average deviation amount is divided by the distance between the center point and the vertex of the regular hexagon, and
wherein an average strain rate in the first region is less than 0.2.

6. The oxide according to claim 5,
wherein the first region is subjected to fast Fourier transform to obtain a first image,
wherein the first image is subjected to mask processing except for a range from 2.8 nm −1 to 5.0 nm −1 to obtain a second image,
wherein the second image is subjected to inverse fast Fourier transform to obtain a third image,
wherein noise is removed from the third image to obtain a fourth image, and
wherein the lattice points included in the lattice point group are points with maximal luminance in the fourth image.

7. The oxide according to claim 6, wherein luminance within a 0.05-nm radius in the third image is averaged to remove the noise.

8. The oxide according to claim 7,
wherein a first step of extracting a second point with highest luminance within a 0.22-nm radius from a first point and a second step of extracting a third point with highest luminance within a 0.22-nm radius from the second point are repeated until a point with highest luminance is fixed as one of the points with maximal luminance, and
wherein the others of the points with maximal luminance are determined in a manner similar to that for the one of the points with maximal luminance using a point more than 0.22 nm away from the one of the points with maximal luminance as the first point.

9. An oxide comprising:
indium, an element M, and zinc,
wherein the element M is one of aluminum, gallium, yttrium, and tin,
wherein a crystal structure in the oxide is capable of having a homologous structure,
wherein the oxide includes a plurality of flat-plate-like crystal regions,
wherein c-axes of the plurality of flat-plate-like crystal regions are approximately parallel to a normal vector of a top surface of the oxide,
wherein an average size of the plurality of flat-plate-like crystal regions in a direction parallel to the top surface of the oxide is larger than 3 nm in a transmission electron microscopy image of a cross section of the oxide taken along a plane perpendicular to the top surface, and
wherein no clear grain boundary is observed between the plurality of flat-plate-like crystal regions.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Method For Transmitting Signal For Mtc And Apparatus For Same

Technical Field and Background:
Recently, wireless communication systems are widely developed to provide various kinds of communication services including audio communications, data communications and the like. Generally, a wireless communication system is a kind of a multiple access system capable of supporting communications with multiple users by sharing available system resources (e.g., bandwidth, transmission power, etc.). For instance, multiple access systems include CDMA (code division multiple access) system, FDMA (frequency division multiple access) system, TDMA (time division multiple access) system, OFDMA (orthogonal frequency division multiple access) system, SC-FDMA (single carrier frequency division multiple access) system, MC-FDMA (multi carrier frequency division multiple access) and the like. In a wireless communication system, a user equipment (UE) may receive information from a base station in downlink (DL), and the user equipment may transmit information to the base station in uplink (UL). The information transmitted or received by the UE may include data and various control information. In addition, there are various physical channels according to the type or use of the information transmitted or received by the UE.

Invention Disclosure:
The present invention relates to a method for performing a random access procedure in a wireless communication system supporting repeated transmission of a same signal, and an apparatus for same, and more specifically, to a method and an apparatus for same, the method comprising: detecting a physical downlink control channel (PDCCH) signal; and transmitting a physical uplink shared channel (PUSCH) signal using an uplink grant, when the PDCCH signal includes the uplink grant, wherein the PUSCH signal is transmitted from a subframe having a first offset from among subframes from which the PDCCH signal has been detected, when user equipment is a first type of user equipment, wherein the PDCCH signal is repeatedly transmitted from a first plurality of subframe sections, when the user equipment is a second type of user equipment, wherein the transmission of the PUSCH signal begins from a subframe capable of starting repeated PUSCH transmission and closest to the last subframe in the first plurality of subframe sections, and wherein the subframe capable of starting repeated PUSCH transmission is determined in advanced through upper layer signaling.

[Assistant]
1. A method for transmitting and receiving a signal by a user equipment (UE) in a wireless communication system supporting coverage enhancement, the method comprising:
detecting a physical downlink control channel (PDCCH) signal; and
transmitting a physical uplink shared channel (PUSCH) signal based on the detected PDCCH signal,
wherein:
when the UE is a first type UE, the PUSCH signal is transmitted in a subframe obtained by applying a first offset to a subframe in which the PDCCH signal is detected,
when the UE is a second type UE, the PDCCH signal is repeatedly transmitted in a first plurality of subframes and the PUSCH signal begins to be repeatedly transmitted in a subframe which is obtained by applying the first offset to a last subframe of the first plurality of subframes within subframes in which PUSCH repeated transmission can be started, and
the subframes in which PUSCH repeated transmission can be started are preconfigured via radio resource control (RRC) layer signaling.

2. The method according to claim 1, further comprising:
receiving a physical hybrid automatic repeat request (HARD) indicator channel (PHICH) signal for the PUSCH signal,
wherein:
when the UE is the first type UE, the PHICH signal is received in a subframe obtained by applying a second offset to a subframe in which the PUSCH signal is transmitted,
when the UE is the second type UE, the PHICH signal begins to be repeatedly received in a subframe which is obtained by applying the second offset to a last subframe of repeatedly transmitting the PUSCH signal within subframes in which PHICH repeated transmission can be started, and
the subframes in which PHICH repeated transmission can be started are preconfigured via the RRC layer signaling.

3. The method according to claim 1, further comprising:
when the PDCCH signal contains downlink grant, receiving a physical downlink shared channel (PDSCH) signal scheduled by the downlink grant,
wherein:
when the UE is the first type UE, the PDSCH signal is received in a subframe in which the PDCCH signal is detected,
when the UE is the second type UE, the PDCCH signal is repeatedly transmitted in the first plurality of subframes, and the PDSCH signal begins to be repeatedly received in a subframe which is a last subframe of the first plurality of subframe intervals within subframes in which PDSCH repeated transmission can be started, and
the subframes in which PDSCH repeated transmission can be started are preconfigured via the RRC layer signaling.

4. The method according to claim 3, further comprising:
transmitting a physical uplink control channel (PUCCH) signal containing a hybrid automatic repeat request acknowledgement (HARQ-ACK) signal for the PDSCH signal,
wherein:
when the UE is the first type UE, the PUCCH signal is transmitted in a subframe obtained by applying a third offset to a subframe in which the PDSCH signal is received,
when the UE is the second type UE, the PUCCH signal begins to be repeatedly transmitted in a subframe which is a last subframe of repeatedly receiving the PDSCH signal within subframes in which PUCCH repeated transmission can be started, and
the subframes in which PUCCH repeated transmission can be started are preconfigured via the RRC layer signaling.

5. The method according to claim 1, wherein the second type UE supports a repeated transmission of a same signal for coverage enhancement and the first type UE does not support the repeated transmission of the same signal for coverage enhancement.

6. A user equipment (UE) for transmitting and receiving a signal in a wireless communication system supporting coverage enhancement, the UE comprising:
a radio frequency (RF) unit; and
a processor connected to the RF unit during an operation of the processor,
wherein the processor is configured to detect a physical downlink control channel (PDCCH) signal and transmit a physical uplink shared channel (PUSCH) signal based on the detected PDCCH signal, and
wherein:
when the UE is a first type UE, the PUSCH signal is transmitted in a subframe obtained by applying a first offset to a subframe, in which the PDCCH signal is detected,
when the UE is a second type UE, the PDCCH signal is repeatedly transmitted in a first plurality of subframes and the PUSCH signal begins to be repeatedly transmitted in a subframe which is obtained by applying the first offset to a last subframe of the first plurality of subframes within subframes in which PUSCH repeated transmission can be started, and
the subframes in which PUSCH repeated transmission can be started are preconfigured via radio resource control (RRC) layer signaling.

7. The UE according to claim 6, wherein the processor is further configured to receive a physical hybrid automatic repeat request (HARD) indicator channel (PHICH) signal for the PUSCH signal, and
wherein:
when the UE is the first type UE, the PHICH signal is received in a subframe obtained by applying a second offset to a subframe in which the PUSCH signal is transmitted,
when the UE is the second type UE, the PHICH signal begins to be repeatedly received in a subframe which is obtained by applying the second offset to a last subframe of repeatedly transmitting the PUSCH signal within subframes in which PHICH repeated transmission can be started, and
the subframes in which PHICH repeated transmission can be started are preconfigured via the RRC layer signaling.

8. The UE according to claim 6, wherein the processor is further configured to, when the PDCCH signal contains downlink grant, receive a physical downlink shared channel (PDSCH) signal scheduled by the downlink grant, and
wherein:
when the UE is the first type UE, the PDSCH signal is received in a subframe in which the PDCCH signal is detected,
when the UE is the second type UE, the PDCCH signal is repeatedly transmitted in the first plurality of subframe intervals, and the PDSCH signal begins to be repeatedly received in a subframe which is a last subframe of the first plurality of subframes within subframes in which PDSCH repeated transmission can be started, and
the subframes in which PDSCH repeated transmission can be started are preconfigured via the RRC layer signaling.

9. The UE according to claim 8, wherein the processor is further configured to transmit a physical uplink control channel (PUCCH) signal containing a hybrid automatic repeat request acknowledgement (HARQ-ACK) signal for the PDSCH signal, and
wherein:
when the UE is the first type UE, the PUCCH signal is transmitted in a subframe obtained by applying a third offset to a subframe in which the PDSCH signal is received,
when the UE is the second type UE, the PUCCH signal begins to be repeatedly transmitted in a subframe which is a last subframe of repeatedly receiving the PDSCH signal within subframes in which PUCCH repeated transmission can be started, and
the subframes in which PUCCH repeated transmission can be started are preconfigured via the RRC layer signaling.

10. The UE according to claim 6, wherein the second type UE supports a repeated transmission of a same signal for coverage enhancement and the first type UE does not support the repeated transmission of the same signal for coverage enhancement.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Brake Pad Retainer For A Disc Brake

Technical Field and Background:
DE 94 22 342 U1 discloses a brake pad mounting which has proven itself, in particular, even under the often rough operating conditions, to which disc brakes are subjected in commercial vehicles. In order to secure the position of the two brake pads, the latter are provided in each case with a pad mounting spring, which pad mounting springs are fastened to the respective brake pad in the upper edge region which faces an assembly opening of the brake caliper. The brake pads are pressed under prestress into the pad shaft of a stationary brake carrier or the brake caliper by a pad mounting bracket which extends transversely with respect thereto, that is to say in the axial direction of the brake disc, and is supported on the pad mounting springs. Here, the pad mounting bracket is fixed in two regions of the brake caliper which lie opposite one another and delimit the assembly opening. The mounting of the brake pads under spring prestress serves both for tolerance compensation and for reducing or preventing the generation of rattling noise, as would otherwise occur during driving operation of the vehicle. In order to assemble and dismantle the pad mounting bracket using simple means, it is plugged on one side into a pocket-shaped receptacle of the brake caliper and is fastened on the other side to the brake caliper by way of a securing bolt, a washer and a split pin. The securing bolt which is supported on the pad mounting bracket is guided by way of a fastening socket which is formed integrally on the brake caliper and passes through a window opening of the pad mounting bracket. The multiplicity of necessary individual parts, by way of which the pad mounting bracket is fastened to the brake caliper, is possible only with relatively great outlay on manufacturing and assembly, which leads to correspondingly high costs and opposes the constant requirement for cost optimization. This likewise applies to another known way of fastening the pad mounting bracket, in which the latter is screwed to the brake caliper. To this end, a threaded bore has to be made in the brake caliper, which can naturally be brought about only in a relatively complicated manner. Moreover, there is in principle the risk that the fastening element, specifically the split pin, becomes detached and is lost, in particular, during driving operation, just like the securing bolt which is then no longer secured, with the result that the pad mounting bracket can no longer fulfill its function, with the consequence of a failure of the disc brake. The invention is based on the object of developing a brake pad mounting of the generic type in such a way that it can be manufactured and assembled in a more simple and less expensive manner. This and other objects are achieved by a brake pad mounting of a disc brake for a commercial vehicle, having a pad mounting bracket which is supported on pad mounting springs of brake pads which are arranged on both sides of a brake disc in a brake caliper. The pad mounting bracket bridges an assembly opening of the brake caliper in the axial direction of the brake disc and is held in a fastening socket of the brake caliper at least on one side by a bolt-shaped securing element. The securing element is formed from an eccentric bolt, having a shank and at least one eccentric section which is positioned offset axially with respect to the shank. As a result of this structural configuration of the securing element, the use of further measures, in particular a split pin, can in principle be dispensed with, since the securing against displacement is then taken over by integrally formed stops of the securing element. This results in a whole series of advantages. In particular, the assembly of the pad mounting bracket and its securing are simplified substantially and therefore become less expensive especially since machining of the securing element is not required, as is required if a split pin is used as a result of the introduction of a bore into the securing bolt. Moreover, the functional reliability of the disc brake overall is improved, since a release of the securing element and therefore a release of the pad mounting bracket from its fastening position are practically ruled out as a result of the spring pressure of the pad mounting springs which acts on the pad mounting bracket and therefore on the securing element, even in the case of enduringly relatively pronounced, operation-induced vibrations of the commercial vehicle.

Invention Disclosure:
A brake pad retainer is provided for a disc brake for a commercial vehicle. A pad retaining bracket is supported by pad retaining springs on both sides of a brake disc on a brake pad arranged in a brake caliper. The pad retaining bracket tensions a mounting opening of the brake caliper in the direction of the axis of the brake disc and is maintained at least on one side by a bolt-shaped securing element in a securing eye of the brake caliper. The brake pad retainer is designed such that the securing element is formed from an eccentric bolt having a shaft and at least one eccentric section which is positioned so that it is axially offset with respect the shaft.

[Assistant]
1. A brake pad mount of a disc brake for a commercial vehicle, comprising:
a pad mounting bracket supportable on pad mounting springs of brake pads arranged on both sides of a brake disc in a brake caliper of the disc brake, wherein
the pad mounting bracket bridges an assembly opening of the brake caliper in an axial direction of the brake disc,
a bolt-shaped securing element that extends through a single transverse bore in a fastening socket of the brake caliper to hold the pad mounting bracket at least on one side, wherein
the bolt-shaped securing element comprises an eccentric bolt having a shank arranged in the single transverse bore, and at least one eccentric section positioned offset axially with respect to the shank,
a largest dimension between outer faces of the shank and the eccentric section is less than a diameter of the transverse bore of the fastening socket, and
the shank is pressed and automatically rotatable under spring pressure applied to the eccentric section via the pad mounting spring onto an upper inner surface of the transverse bore such that a longitudinal axis of the shank is below that of the eccentric section.

2. The brake pad mount according to claim 1, wherein
a respective eccentric section is connected on each side of the shank, at least one respective eccentric section having a head on a side facing away from the shank.

3. The brake pad mount according to claim 1, wherein the length of the shank corresponds to a length of a transverse bore through the fastening socket.

4. The brake pad mount according to claim 2, wherein the head bears against a side face of the pad mounting bracket.

5. The brake pad mount according to claim 2, wherein the respective eccentric sections lay in respective beads of the pad mounting bracket.

6. The brake pad mount according to claim 2, wherein the respective eccentric sections cover associated edge regions of a transverse bore through the fastening socket.

7. A brake pad mount of a disc brake for a commercial vehicle, comprising:
a caliper having an assembly opening through which brake pads are arranged on both sides of a brake disc, the caliper having a fastening socket through which a single transverse bore is arranged;
a pad mounting bracket configured to be supported on pad mounting springs of the arranged brake pads, the pad mounting bracket being configured to bridge the assembly opening in an axial direction of the brake disc, the pad mounting bracket having an opening at one end through which the fastening socket of the brake caliper extends;
a bolt-shaped securing element configured to extend through the single transverse bore of the fastening socket in order to hold the pad mounting bracket, the securing element comprising an eccentric bolt having a shank and at least one eccentric section positioned offset axially with respect to the shank at one end of the shank, wherein
a largest dimension between outer faces of the shank and the eccentric section is less than a diameter of the transverse bore of the fastening socket, and
the shank is pressed and automatically rotatable under spring pressure applied to the eccentric section via the pad mounting spring onto an upper inner surface of the transverse bore such that a longitudinal axis of the shank is below that of the eccentric section.

8. The brake pad mount according to claim 7, wherein the securing element comprises a second eccentric section connected to an opposite end of the shank and being position offset axially with respect to the shank.