[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Solid-State Imaging Device, Method Of Manufacturing A Solid-State Imaging Device, And Electronic Apparatus

Technical Field and Background:
The present disclosure relates to solid-state imaging devices, methods of manufacturing the solid-state imaging devices, and electronic apparatuses and, in particular, to a solid-state imaging device, a method of manufacturing the solid-state imaging device, and an electronic apparatus capable of preventing the degradation of color mixture. In recent years, CMOS type solid-state imaging devices (CMOS image sensors) have been installed in various electronic apparatuses such as digital cameras, video cameras, monitoring cameras, copiers, and facsimile machines. In solid-state imaging devices, on-chip lenses are formed over photodiodes serving as light receiving portions. However, the manufacturing of the on-chip lenses with a desired curvature has become difficult since it is requested to downsize the on-chip lenses to suit to finer pixels. Accordingly, there has been proposed the technology of achieving an improvement in sensitivity in a pixel structure in which on-chip lenses larger in size than pixels are formed for every other pixel to suit to finer pixels (see, for example, Japanese Patent Application Laid-open No. 2007-287891 (hereinafter, referred to as Patent Document 1).

Invention Disclosure:
Disclosed is a solid-state imaging device including a plurality of pixels and a plurality of on-chip lenses. The plurality of pixels are arranged in a matrix pattern. Each of the pixels has a photoelectric conversion portion configured to photoelectrically convert light incident from a rear surface side of a semiconductor substrate. The plurality of on-chip lenses are arranged for every other pixel. The on-chip lenses are larger in size than the pixels. Each of color filters at the pixels where the on-chip lenses are present has a cross-sectional shape whose upper side close to the on-chip lens is the same in width as the on-chip lens and whose lower side close to the photoelectric conversion portion is shorter than the upper side.

[Assistant]
1. An imaging device comprising:
green pixels including a first green pixel and a second green pixel disposed diagonally in a single line,
wherein the first green pixel is disposed between a first red pixel and a second red pixel in a horizontal direction,
wherein the second green pixel is disposed between a first blue pixel and a second blue pixel in the horizontal direction,
wherein a size of the first blue pixel is smaller than a size of the first green pixel, and
wherein a size of the second blue pixel is smaller than the size of the first green pixel.

2. The imaging device of claim 1, wherein a shape of the first green pixel is different than a shape of the first blue pixel.

3. The imaging device of claim 2, wherein a shape of the first green pixel is different than a shape of the second blue pixel.

4. The imaging device of claim 1, wherein a shape of the second green pixel is different than a shape of the first red pixel.

5. The imaging device of claim 4, wherein a shape of the second green pixel is different than a shape of the second red pixel.

6. The imaging device of claim 1, further comprising:
a third green pixel and a fourth green pixel disposed diagonally along the single line.

7. The imaging device of claim 6, further comprising:
a third red pixel and a fourth red pixel, wherein the third green pixel is disposed between the third red pixel and the fourth red pixel.

8. The imaging device of claim 7, further comprising:
a third blue pixel and a fourth blue pixel, and wherein the fourth green pixel is disposed between the third blue pixel and the fourth blue pixel.

9. An electronic apparatus comprising:
an imaging device including:
a plurality of green pixels, including a first green pixel and a second green pixel disposed diagonally in a single line;
a plurality of red pixels, including a first red pixel and a second red pixel; and
a plurality of blue pixels, including a first blue pixel and a second blue pixel,
wherein the first green pixel is disposed between the first red pixel and the second red pixel in a horizontal direction,
wherein the second green pixel is disposed between the first blue pixel and the second blue pixel in the horizontal direction,
wherein a size of the first blue pixel is smaller than a size of the first green pixel, and
wherein a size of the second blue pixel is smaller than the size of the first green pixel;
a plurality of on-chip lenses; and
a digital signal processor circuit.

10. The electronic apparatus of claim 9, wherein a shape of the first green pixel is different than a shape of the first blue pixel.

11. The electronic apparatus of claim 10, wherein a shape of the first green pixel is different than a shape of the second blue pixel.

12. The electronic apparatus of claim 9, wherein a shape of the second green pixel is different than a shape of the red blue pixel.

13. The electronic apparatus of claim 12, wherein a shape of the first green pixel is different than a shape of the second red pixel.

14. The electronic apparatus of claim 9, wherein the plurality of green pixels includes a third green pixel and a fourth green pixel disposed diagonally along the single line.

15. The electronic apparatus of claim 14, wherein the plurality of red pixels includes a third red pixel and a fourth red pixel, wherein the third green pixel is disposed between the third red pixel and the fourth red pixel.

16. The electronic apparatus of claim 15, wherein the plurality of blue pixels includes a third blue pixel and a fourth blue pixel, and wherein the fourth green pixel is disposed between the third blue pixel and the fourth blue pixel.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Recess-Mounted Hydraulic Pump Cartridge And Work Vehicle Drivetrain Therewith

Technical Field and Background:
Work vehicles used in various industries, such as agriculture, construction and forestry, may have onboard hydraulic systems for powering various vehicle and implement systems and tools. The hydraulic systems are pressurized by one or more hydraulic pumps powered by the main engine or one or more variable drives (e.g., electric motors). Depending on the work vehicle, numerous hydraulic pumps may be needed to supply the pressure necessary for proper operation of the varied vehicle and implement systems, thus increasing the space envelope required for the hydraulics and the complexity of arranging the associated plumbing lines and input power sources.

Invention Disclosure:
A hydraulic pump is configured to mount within an internal receptacle defined by a housing of a hydraulically-powered component of a work vehicle. The pump has a housing defining one or more pump chambers. Each pump chamber communicates with a suction port and an outlet pressure port. Each pump chamber contains a pump assembly having a drive member at a fluid interface between the suction port and the outlet pressure port. The drive member is arranged for co-rotation with at least one power input component extending into the housing through each pump chamber. Rotation of each drive member displaces and pressurizes hydraulic fluid through the pump housing, and, when the pump is mounted within the internal receptacle, through internally ported passages routed through walls of the hydraulically-powered component housing.

[Assistant]
1. A drivetrain assembly for a work vehicle, comprising:
a drivetrain housing containing a drivetrain component and defining an internal receptacle having an open end, the drivetrain housing having one or more walls defining internally ported suction and outlet pressure passages; and
a hydraulic pump mounted to the drivetrain housing, at least in part, within the open end of the internal receptacle, the pump having a housing defining one or more pump chambers, the one or more pump chambers communicating with an associated suction port and an associated outlet pressure port and containing an associated pump assembly, the associated pump assembly having a drive member between the associated suction port and the associated outlet pressure port, the associated suction port and the associated outlet pressure port communicating with associated ones of the suction and outlet pressure passages in the one or more walls of the drivetrain housing; and
an input shaft extending into the pump housing and engaging for co-rotation the drive member of the pump assembly for the associated one or more pump chambers;
wherein rotation of the input shaft drives the pump assembly of the associated one or more pump chambers to displace and pressurize hydraulic fluid between the associated ones of the suction and outlet pressure passages of the drivetrain housing to supply hydraulic fluid to the drivetrain component.

2. The drivetrain assembly of claim 1, wherein there are a plurality of pump chambers arranged in tandem along a reference axis.

3. The drivetrain assembly of claim 1, wherein the pump housing includes an end wall configured to fit within the internal receptacle of the drivetrain housing and a mounting flange configured to interface with an exterior surface of the drivetrain housing.

4. The drivetrain assembly of claim 3, wherein at least one of the end wall and the mounting flange has an opening therein receiving the input shaft.

5. The drivetrain assembly of claim 2, wherein each pump chamber has a dedicated set of suction and outlet pressure ports.

6. The drivetrain assembly of claim 1, wherein the associated pump assembly of the one or more pump chambers is a positive displacement pump assembly selected from the group consisting of an internal gear set, an external gear set, a rotary vane arrangement and an axial piston arrangement.

7. The drivetrain assembly of claim 2, wherein the pump housing defines at least three pump chambers.

8. The drivetrain assembly of claim 2, wherein the pump assembly in each pump chamber effects a different displacement.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Led Retrofit Lamp

Technical Field and Background:
WO2012127371A1 discloses an electric lamp having two pairs of external connection pins adapted for connecting the lamp to a voltage source for powering an internal lighting module. Each pair of pins is disconnected from the lighting module by an open switch unless a non-zero electric voltage is applied to the pair and causes the switch to close. The lamp may be fitted in a switch-start fixture, providing an ohmic connection between two pins in different pairs, as well as a rapid-start fixture, with a capacitive connection. Further measures might become necessary in order to meet increasing safety requirements for LED retrofit lamps.

Invention Disclosure:
The present invention relates to an LED retrofit lamp adapted for operation with an alternating current. The LED lamp comprises an LED unit, first and second switching devices (e.g., first and second relays), a startup voltage supply unit (1010) coupled in parallel to the first switching device, an ignition detection unit (1020) coupled in parallel to the second switching device, and a switch drive unit (1030) for setting the first and second switching devices to a conducting state. If one of the first and second switching devices is shorted either no startup supply voltage or no detection signal is provided, such that the failure is indicated externally to a user.

[Assistant]
1. An LED retrofit lamp adapted for operation with an alternating current, comprising:
an LED unit;
a first switching device, and a second switching device; said first switching device, said second switching device, and said LED unit being connected in series;
a startup voltage supply unit connected to a capacitor forming a parallel connection with said first switching device; said startup voltage supply unit adapted to generate a startup supply voltage if the first switching device is in a non-conducting state;
an ignition detection unit connected to a capacitor forming a parallel connection with said second switching device, said ignition detection unit adapted to generate a detection signal if the second switching device is in a non-conducting state; and
a switch drive unit adapted to provide said startup supply voltage to said first and second switching devices, in response to said detection signal, wherein said first and second switching devices are adapted to assume a conducting state upon receipt of said startup supply voltage.

2. The LED retrofit lamp according to claim 1, wherein said LED retrofit lamp further comprises a mains current line; said first switching device, said second switching device, and said LED unit being connected in series along said mains current line, said ignition detection unit adapted to generate said detection signal in response to detecting an ignition voltage on said mains current line.

3. The LED retrofit lamp according to claim 1, wherein said LED unit further comprises a steady-state voltage supply unit; said steady-state voltage supply unit being adapted to generate a steady-state supply voltage, wherein said steady-state voltage supply unit is further adapted to derive a steady-state supply voltage for said first and second switching devices from a mains current line of said LED retrofit lamp.

4. The LED retrofit lamp according to claim 3, wherein said steady-state voltage supply unit is further adapted to set said first and second switching devices at least temporarily to a non-conducting state in response to the power reduction on a mains current line of said LED lamp.

5. The LED retrofit lamp according to claim 3, said steady-state voltage supply unit being adapted to provide said steady-state supply voltage to the first and second switching devices, wherein said steady-state voltage supply unit is connected between said first and second switching devices.

6. The LED retrofit lamp according to claim 5, wherein said steady-state voltage supply unit comprises a shunt supply circuit adapted to tap energy from the mains current line of said LED retrofit lamp during a steady-state mode of operation.

7. The LED retrofit lamp according to claim 6, wherein said shunt supply circuit comprises at least one of:
a full diode bridge and a shunt switch;
an active full bridge comprising at least two diodes and at least two MOSFETs; and
an asymmetrical half-bridge.

8. The LED retrofit lamp according to claim 1, wherein said first switching device comprises a first relay, and wherein said second switching device comprises a second relay.

9. The LED retrofit lamp according to claim 8, wherein the first relay comprises a first coil, and wherein the second relay comprises a second coil; wherein the first and second coils are connected to receive said startup supply voltage from said switch drive unit, wherein said first and second relays change from a non-conducting state to a conducting state upon receipt of said startup supply voltage from said switch drive unit.

10. The LED retrofit lamp according to claim 1, wherein said first and second switching devices are adapted to assume said conducting state if said startup supply voltage is above a minimum threshold voltage.

11. The LED retrofit lamp according to claim 1, wherein the LED lamp is adapted for operation with an electrical ballast, and wherein said ignition voltage on said mains current line corresponds to an HF signal from said electrical ballast.

12. The LED retrofit lamp according to claim 11, wherein said ignition detection unit is adapted to detect the HF signal from said electrical ballast.

13. The LED retrofit lamp according to claim 1, wherein, if said first switching device is in a conducting state, said startup voltage supply unit is bypassed by the first switching device, and wherein, if said second switching device is in a conducting state, said ignition detection unit is bypassed by the second switching device.

14. A method of operating an LED retrofit lamp with an alternating current; said method comprises the steps of:
generating a startup supply voltage if a first switching device, which is included in the LED retrofit lamp, is in a non-conducting state;
generating a detection signal if a second switching device, which is included in the LED retrofit lamp, is in a non-conducting state, wherein the first and second switching devices are connected in series with an LED unit in the LED retrofit lamp; and
in response to said detection signal, providing said startup supply voltage to said first and second switching devices, wherein said first and second switching devices are adapted to assume a conducting state upon receipt of said startup supply voltage.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Rapid Optical Shutter, Chopper, Modulator And Deflector

Technical Field and Background:
There are numerous applications in which an optical source, e.g., laser or light beam, may be need to be shuttered (rapidly turned on and off), chopped, modulated (spatially or temporally), or deflected. One such example is consumer grade photography where rapid shutter speed prevents the camera from being over exposed and prevents blurring. In various other applications, shuttering needs to be done rapidly to improve signal to noise ratio or improve performance of the optical device being used. Current methods have limited speeds and are excessively large and/or expensive. Prior solutions for optical devices have not resolved the need for an approach to perform one or more of the above actions without drawbacks, e.g., optically and electrically inefficient, size constraints, and/or cost-prohibitive. Therefore, there is a need for optical device systems and methods that address one or more of the deficiencies described above amongst others.

Invention Disclosure:
An optical device with a light source and a detector is provided. A digital micromirror device positioned between the detector and the light source may deflect light beams projected from the light source. An aperture in front of the detector may block an incoming light beam from the detector when the incoming light beam is incident on the detector outside of a passable incident range and including an aperture opening configured to pass the incoming light beam to the detector when the incoming light beam is incident on the detector within a passable incident range. The digital micromirror device may rotate between a first position causing the light beam to pass through the aperture opening and a second position causing the light beam to be blocked by the aperture. The optical device may be configured to operate as a shutter, chopper, modulator and/or deflector.

[Assistant]
1. An optical device comprising:
a light source configured to project a light beam;
a detector configured to detect an incident light beam projected from the light source;
a mirrored device disposed at a position between the detector and the light source, such that it is configurable to deflect the light beam projected from the light source as it travels towards the detector; and
an aperture disposed in front of the detector and configured to block an incoming light beam from reaching the detector when the incoming light beam is incident on the detector outside of a passable incident range and including an aperture opening configured to pass the incoming light beam to the detector when the incoming light beam is incident on the detector within a passable incident range,
wherein the mirrored device is configured to rotate between a first position and a second position, the first position configured to cause the light beam to pass through the aperture opening to the detector, and the second position configured to cause the light beam to be blocked by the aperture; and
wherein the light beam comprises a continuous wave beam, and wherein the mirrored device is configured to oscillate such that the continuous wave beam is chopped into a series of laser pulses.

2. The optical device of claim 1, wherein the mirrored device includes an optical shutter to deflect the incoming light beam to the detector via the aperture at a repetition rate between 0.1 hertz and 32 kilohertz.

3. The optical device of claim 2, wherein the optical shutter is configured to reject ambient light.

4. The optical device of claim 1, wherein the light source includes a laser beam directed into a flame and a lens configured to collect scattered light from the laser beam passing through the flame and to direct the scattered light to the detector.

5. The optical device of claim 4, further comprising a mirror disposed between the mirrored device and the detector, the mirror being configured to deflect the scattered light collected by the lens toward the detector.

6. The optical device of claim 4, wherein, when the mirrored is positioned in the second position, luminosity from the flame is blocked from entering the detector.

7. The optical device of claim 1, wherein the light beam operates at a repetition rate between 0.1 Hz and 32 kilohertz.

8. The optical device of claim 1, further comprising a camera body housing each of the detector, the light source, the mirrored device and the aperture, and wherein the optical device is configured for imaging.

9. The optical device of claim 1, further comprising a laser beam safety system configured to selectively block the light source from the mirrored device.

10. The optical device of claim 1 wherein:
the digital micromirror device includes a plurality of mirrors arranged in an array;
era rotating the digital micromirror device between the first position and the second position, the plurality of mirrors are rotated at respective pivot points; and
the respective pivot points of the plurality of mirrors are located in a single fixed plane.

11. An optical device system comprising:
a plurality of optical devices including at least a first optical device and a second optical device, the plurality of optical devices connected in a series configuration, and each comprise:
a light source configured to project a light beam;
a detector configured to detect an incident light beam projected from the light source;
a mirrored device disposed at a position between the detector and the light source, such that it is configurable to deflect the light beam projected from the light source as it travels towards the detector; and
an aperture disposed in front of the detector and configured to block an incoming light beam from reaching the detector when the incoming light beam is incident on the detector outside of a passable incident range and including an aperture opening configured to pass the incoming light beam to the detector when the incoming light beam is incident on the detector within a passable incident range,
wherein the mirrored device is configured rotate between a first position and a second position, the first position configured to cause the light beam to pass through the aperture opening to the detector, and the second position configured to cause the light beam to be blocked by the aperture; and
wherein the light beam comprises a continuous wave beam, and wherein the mirrored device is configured to oscillate such that the continuous wave beam is chopped into a series of laser pulses.

12. An optical device comprising:
a detection system including a light beam receiving portion configured to detect a light beam;
a digital micromirror device configured to deflect a light beam toward the detection system; and
an aperture disposed proximate to the light beam receiving portion, the aperture including an aperture opening configured to allow passage of the light beam deflected from the digital micromirror device to the detection system and an aperture segment configured to block passage of the light beam deflected from the digital micromirror device from the detection system,
wherein the digital micromirror device is configured adjust between at least a first position and a second position, the first position configured to cause the light beam to pass through the aperture opening to the detection system, and the second position configured to cause the light beam to strike the aperture segment; and
wherein the light beam comprises a continuous wave beam, and wherein the digital micromirror device is configured to oscillate such that the continuous wave beam is chopped into a series of laser pulses.

13. The optical device of claim 12, wherein the digital micromirror device is configured temporally or spatially modulate the light beam.

14. The optical device of claim 13, wherein the digital micromirror device is configured to control a temporal or spatial mode of the light beam.

15. The optical device of claim 13, wherein a temporal or spatial modulation of the digital micromirror device corresponds to encoded information.

16. The optical device of claim 15, wherein the encoded information represents at least one of an image, an audio, a video, or an archival for data transmission and/or data storage.

17. The optical device of claim 12, further comprising a sample comprising at least one composition of matter, wherein the light beam passes through the sample before being passed to the detection system.

18. The optical device of claim 17, wherein detection system include a look-in electronics system to detect an oscillating signal passing through the sample.

19. The optical device of claim 17, further comprising at least one amplifier stage for amplifying the laser pulses.

20. The optical device of claim 17, wherein the digital micromirror device is configured to reduce amplified spontaneous emission (ASE) in a laser.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Hermetically Sealed Telecommunications Enclosure With Adapter Assembly

Technical Field and Background:
Fiber optic cables are widely used to transmit light signals for high speed data transmission. A fiber optic cable typically includes: (1) an optical fiber or optical fibers; (2) a buffer or buffers that surrounds the fiber or fibers; (3) a strength layer that surrounds the buffer or buffers; and (4) an outer jacket. Optical fibers function to carry optical signals. A typical optical fiber includes an inner core surrounded by a cladding that is covered by a coating. Buffers (e.g., loose or tight buffer tubes) typically function to surround and protect coated optical fibers. Strength layers add mechanical strength to fiber optic cables to protect the internal optical fibers against stresses applied to the cables during installation and thereafter. Example strength layers include aramid yarn, steel and epoxy reinforced glass roving. Outer jackets provide protection against damage caused by crushing, abrasions, and other physical damage. Outer jackets also provide protection against chemical damage (e.g., ozone, alkali, acids). Fiber optic cable connection systems are used to facilitate connecting and disconnecting fiber optic cables in the field without requiring a splice. A typical fiber optic cable connection system for interconnecting two fiber optic cables includes fiber optic connectors mounted at the ends of the fiber optic cables, and an adapter for mechanically and optically coupling the fiber optic connectors together. Fiber optic connectors generally include ferrules that support the ends of the optical fibers of the fiber optic cables. The end faces of the ferrules are typically polished and are often angled. The adapter includes co-axially aligned ports (i.e., receptacles) for receiving the fiber optic connectors desired to be interconnected. The adapter includes an internal sleeve that receives and aligns the ferrules of the fiber optic connectors when the connectors are inserted within the ports of the adapter. With the ferrules and their associated fibers aligned within the sleeve of the adapter, a fiber optic signal can pass from one fiber to the next. The adapter also typically has a mechanical fastening arrangement (e.g., a snap-fit arrangement) for mechanically retaining the fiber optic connectors within the adapter. One example of an existing fiber optic connection system is described in U.S. Pat. Nos. 6,579,014, 6,648,520, and 6,899,467. In certain examples, telecommunications enclosures or cable enclosures can typically be used to house telecommunications components in the field. The enclosures can provide interior space for receiving splice holders, optical splitters, wavelength division multiplexers, and other devices therein in a sealed manner. The enclosures can define cable ports for receiving cables of various types, such as a main cable and drop cables. Such cable ports can include sealed cable pass-through ports. Such cable ports can also include fiber optic adapters mounted to a wall of the enclosure for interfacing with the connectorized ends of fiber optic cables.

Invention Disclosure:
A fiber optic adapter assembly is provided that sealingly mounts to a telecommunications enclosure. The adapter assembly mounts to a communications enclosure such that one of two fiber optic connectors is received into the adapter assembly outside of the enclosure and the other fiber optic connector is engaged into the adapter assembly inside of the enclosure. The enclosure is pressurized at a predetermined level, and the adapter assembly is configured to maintain the pressure within the enclosure when the adapter assembly mounts to the enclosure.

[Assistant]
1. A fiber optic cable adapter assembly comprising:
an adapter housing defining a first port, a second port, and a through-passage extending between the first port and the second port, the adapter housing configured to mount to an opening formed in a mounting wall of a pressurized enclosure such that the first port is open to an exterior of the enclosure to receive a first fiber optic connector from the exterior of the enclosure and the second port is arranged in the interior of the enclosure;
an adapter module disposed within the through-passage and configured to couple the first fiber optic connector and a second fiber optic connector within the adapter housing, the second fiber optic connector being preassembled with the adapter module through the second port of the adapter housing before the adapter housing mounts to the opening of the mounting wall, the second fiber optic connector being fully received within the adapter housing;
a mounting flange formed on the adapter housing and configured to abut one of an inner surface and an outer surface of the mounting wall of the pressurized enclosure when the adapter housing mounts to the opening of the mounting wall;
a mounting nut engaging a portion of the adapter housing to sandwich the mounting wall of the pressurized enclosure between the mounting flange and the mounting nut;
an enclosure seal element disposed around the opening of the mounting wall between the mounting flange and the mounting nut to seal the adapter housing around the opening of the enclosure; and
a second port seal element disposed around a fiber optic cable of the second fiber optic connector at the second port to seal the adapter housing from the interior of the enclosure at the second port of the adapter housing,
wherein the enclosure seal element and the second port seal element are configured to maintain a positive or negative pressure within the pressurized enclosure relative to atmospheric pressure.

2. The fiber optic cable adapter assembly according to claim 1, wherein the adapter housing includes a housing end piece and an housing body, the housing end piece defining the first port and including the mounting flange, and the housing body sealingly engaging the housing end piece and defining the second port and the through-passage.

3. The fiber optic cable adapter assembly according to claim 2, wherein:
the mounting nut has internal threads; and
the housing end piece has external threads corresponding to the internal threads of the mounting nut such that the mounting nut is screwed onto the external threads of the housing end piece.

4. The fiber optic cable adapter assembly according to claim 1, wherein the enclosure seal element and the second port seal element are configured to maintain an air leak rate from the enclosure not to exceed 10 −6 cc/sec at one atmosphere of pressure differential.

5. The fiber optic cable adapter assembly according to claim 1, wherein the enclosure seal element is an elastomeric O-ring.

6. The fiber optic cable adapter assembly according to claim 1, wherein the second port seal element includes heat shrinkable materials.

7. The fiber optic cable adapter assembly according to claim 1, wherein the second port seal element includes adhesive materials.

8. The fiber optic cable adapter assembly according to claim 7, wherein the adhesive materials include an epoxy-based sealant.

9. A fiber optic connection system comprising:
a pressurized enclosure having a mounting wall, the mounting wall defining an opening;
a first fiber optic connector terminating a first fiber optic cable;
a second fiber optic connector terminating a second fiber optic cable; and
an adapter assembly comprising:
an adapter housing defining a first port, a second port, and a through-passage extending between the first port and the second port, the adapter housing configured to mount to the opening in the mounting wall of the enclosure such that the first port is open to an exterior of the enclosure to receive the first fiber optic connector from the exterior of the enclosure and the second port is arranged in the interior of the enclosure;
an adapter module disposed within the through-passage and configured to couple the first fiber optic connector and the second fiber optic connector within the adapter housing, the second fiber optic connector being preassembled with the adapter module through the second port of the adapter housing before the adapter housing mounts to the opening of the mounting wall, the second fiber optic connector being fully received with the adapter housing;
a mounting flange formed on the adapter housing and configured to abut one of an inner surface and an outer surface of the mounting wall of the pressurized enclosure when the adapter housing mounts to the opening of the mounting wall;
a mounting nut engaging a portion of the adapter housing to sandwich the mounting wall of the pressurized enclosure between the mounting flange and the mounting nut;
an enclosure seal element disposed around the opening of the mounting wall between the mounting flange and the mounting nut to seal the adapter housing around the opening of the enclosure; and
a second port seal element disposed around the second fiber optic cable of the second fiber optic connector at the second port to seal the adapter housing from the interior of the enclosure at the second port of the adapter housing,
wherein the enclosure seal element and the second port seal element are configured to maintain a positive or negative pressure within the pressurized enclosure relative to atmospheric pressure.

10. The fiber optic connection system according to claim 9, wherein the adapter housing includes a housing end piece and an housing body, the housing end piece defining the first port and including the mounting flange, and the housing body sealingly engaging the housing end piece and defining the second port and the through-passage.

11. The fiber optic connection system according to claim 10, wherein:
the mounting nut has internal threads; and
the housing end piece has external threads corresponding to the internal threads of the mounting nut such that the mounting nut is screwed onto the external threads of the housing end piece.

12. The fiber optic connection system according to claim 9, wherein the enclosure seal element and the second port seal element are configured to maintain an air leak rate from the enclosure not to exceed 10 −6 cc/sec at one atmosphere of pressure differential.

13. The fiber optic connection system according to claim 9, wherein the enclosure seal element is an elastomeric O-ring.

14. The fiber optic connection system according to claim 9, wherein the second port seal element includes heat shrinkable materials.

15. The fiber optic connection system according to claim 9, wherein the second port seal element includes adhesive materials.

16. The fiber optic connection system according to claim 15, wherein the adhesive materials include an epoxy-based sealant.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Locating A Mobile Device

Technical Field and Background:
Many computing devices are portable, and many mobile devices may be interactive with a user's surroundings. For example, a mapping application running on a user's mobile device (e.g., smartphone) may allow the user to identify their approximate location on a map displayed on the mobile device. Further, points of interest, retails establishments, entertainment venues, and more, can be indicated on such a map, for example, which can be searched for, and/or identified as the user moves through an area. Typically, mobile devices use global positioning systems (GPS), which utilize satellite triangulation, or some sort of signal triangulation (e.g., mobile phone signal) to identify the approximate location of the user. This location information can be used by various applications on the user's device (e.g., with the user's consent), such as to locate the user on a map, provide appropriate and relevant local information, identify the user's location for social networking, interact with local devices/services, and/or to provide a rich, interactive experience for the user.

Invention Disclosure:
Identifying a location of a mobile device is disclosed (e.g., presuming user consent to the same). One or more received signal strengths (RSSs), comprising a first RSS, may be received by a first access point (AP) from the mobile device. The RSSs may be used to identify a grid area, comprising a first grid space. A signal distance between the first grid space and the first AP may be identified using the first RSS, and combined with a first grid space distance, comprising a known distance between the first grid space and the first AP, to determine a first grid space likelihood score for the first grid space. A second grid space likelihood score may be determined for a second grid space (e.g., and a third, etc.), and the grid space comprising a desired grid space likelihood score (e.g., highest) may be selected as the mobile device location.

[Assistant]
1. A computer based method for identifying a location of a mobile device, comprising:
receiving a plurality of mobile device signal reports from a plurality of access points (AP);
filtering one or more reports, associated with unknown access points from the received mobile device signal reports;
indexing the filtered mobile device signal reports;
receiving a query from an application associated with the mobile device to identify the location of the mobile device;
retrieving data from the indexed filtered mobile device signal reports based on the query;
identifying a candidate area comprising the location of the mobile device using the retrieved data;
creating grid data for a plurality of grid spaces in the identified candidate area;
determining a grid space likelihood score for each of the plurality of grid spaces based on the grid data and the query; and
identifying the location of the mobile device based on the determined grid space likelihood scores, at least a portion of the method implemented at least in part via a processing unit.

2. A computer based method for identifying a location of a mobile device, comprising:
determining a first signal distance between a first grid space and a first access point (AP) using a first received signal strength (RSS), the first RSS comprising an indication of mobile device signal strength received by the first AP;
determining a first expected distance between the first AP and a second AP using a first AP RSS, the first AP RSS comprising an indication of signal strength for a signal transmitted from the second AP and received by the first AP;
determining a first AP difference based at least on a combination of the first expected distance and a first known AP distance, the first known AP distance comprising a known distance between the first AP and the second AP;
determining a first grid space likelihood score based on the first signal distance, the first AP difference, and a first grid space distance, the first grid space distance comprising a known distance between the first AP and the first grid space; and
identifying the location of the mobile device based at least on the first grid space likelihood score, at least a portion of the method implemented at least in part via a processing unit.

3. A computer based method for identifying a location of a mobile device, comprising:
identifying a candidate area comprising the location of the mobile device, the candidate area comprising a plurality of access points;
creating a plurality of grid spaces in the identified candidate area;
determining a grid space likelihood score for each of the plurality of grid spaces based on a signal distance and a grid space distance between each grid space and each of the plurality of access points, the grid space distance representing a known distance between an access point and a grid space, the signal distance representing an estimated distance between a grid space and an access point using a received signal strength (RSS), the RSS comprising an indication of mobile device signal strength received by the AP if the mobile device was located in the grid space; and
identifying the location of the mobile device as a grid space having highest grid space likelihood score, at least a portion of the method implemented at least in part via a processing unit.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Liquid Crystal Display And Gate Driver On Array Circuit

Technical Field and Background:
1. Field of the Invention The present invention relates to the field of liquid crystal displays (LCDs), and more particularly, to a gate driver on array (GOA) circuit applying to LCDs. 2. Description of the Prior Art The design of narrow bezels becomes very popular on the market. On the contrary, the border of the panel is gradually reduced. The height h of wiring layout of the GOA circuit at each stage is consistent with the size of a corresponding pixel for the conventional GOA circuit. Since products using display panels with 4 k or more pixel per inch (PPI) resolution become popular, the size of the pixel gets smaller. In other words, the room for wiring layout of the GOA circuit is decreased as well. The restriction of the height is compensated for the larger width, which is very disadvantageous to the design of the narrow bezel. The tri-gate structure is a common method of reducing cost. With respect to tri-gate structure, the number of scan lines is triple the number of the original design while the number of data lines is one third of the original design. The use of the data lines greatly reduces. In general, a source chip, i.e. source integrated circuit (IC) is more expensive than a gate chip, i.e. gate IC, so the goal to cost saving is achieved. The use of tri-gate structure with the GOA circuit makes it possible that no gate ICs and quite a few source ICs are used in the panel. Therefore, the cost of the panel is reduced, which is quite competitive on the market. However, the space for the GOA circuit at each stage gets smaller since the number of scan lines is triple the number of the original design after the structure of tri-gate is adopted. Based on the structure of the conventional circuit, the width of the GOA area is sacrificed, but it is not disadvantageous to the popular bezel design nowadays. Tri-gate is often used in a low-cost panel. Take a full high definition (FHD) panel for example. A standard panel comprises 1080 gate lines and 5760 data lines. Totally, 6840 signal lines are used. A panel with tri-gate comprises 3240 common gate lines and 1920 data lines. Totally, 5160 signal lines are used. It is obvious that the panel with tri-gate has fewer signals lines than the standard panel does. No gate lines are needed for the structure tri-gate integrated with GOA. Therefore, the cost of panels is reduced to the largest scale. The gate signal node Q(n) is a critical electric potential for the GOA circuit. When the gate signal node Q(n) is at high voltage level, the GOA circuit keeps opening and outputting. On the contrary, the GOA circuit keeps closed when the gate signal node Q(n) is at low voltage level. In the meantime, the gate signal output by the GOA circuit is also at low voltage level. Please refer to FIG. 1 . FIG. 1 is a circuit diagram of a conventional GOA circuit 10 . The GOA circuit 10 comprises a plurality of GOA units 15 . The plurality of GOA units 15 are connected in cascade. The GOA unit 15 at the nth stage charges a corresponding scan line G(n). The GOA unit 15 comprises a clock circuit 100 , a pull-down circuit 200 , a bootstrap capacitance circuit 300 , a pull-up circuit 400 , and a pull-down circuit 500 . The basic structure of GOA unit 15 comprises the clock circuit 100 , the pull-down circuit 200 , the bootstrap capacitance circuit 300 , and the pull-up circuit 400 . The GOA unit 15 comprises four thin-film transistors (TFTs) and a capacitor. Because amorphous silicon may be unstable and unreliable, the pull-down circuit 500 is also needed except for the basic structure. The main function of the pull-down circuit 500 is to pull-down voltage of the gate line G(n), that is, to ensure that the output of the GOA circuit and the gate signal node Q(n) keep at low voltage level and that the stability of the GOA circuit in operation is enhanced. Two auxiliary pull-down circuits are usually used in the conventional design. The function of the auxiliary pull-down circuits is pulling voltage of the gate signal node Q(n) down when the GOA circuit is closed so that the gate signal node Q(n) can keeps low voltage level. It ensures the normal working state of the panel and the increasing stability of the panel. The auxiliary pull-down circuit usually comprises more TFTs. These TFTs occupies larger space, which is disadvantageous when the narrow bezel is taken into consideration. With respect to the two auxiliary pull-down circuits, a detailed introduction is provided as follows.

Invention Disclosure:
A GOA circuit for an LCD includes GOA units connected in cascade and the plurality of GOA units at stages formed. The GOA unit at an nth stage corresponds to a scan line. The scan line includes a nth scan line, a (n+1)th scan line, and a (n+2)th scan line. The GOA unit at the an nth stage includes a first pull-down holding circuit, a pull-up circuit, a bootstrap capacitance circuit, a pull-down circuit, and a clock circuit. The improved GOA circuit at one stage corresponds to the output of three gate lines. So a number of the stages of the GOA circuit is reduced. Only ⅓ stage of the conventional GOA circuit is needed. Because of the decrease in the number of the stages, more flexibility of design is given to the GOA circuit at each stage. It is beneficiary for the design in narrow bezels.

[Assistant]
1. A gate driver on array (GOA) circuit for a liquid crystal display (LCD), comprising: a plurality of GOA units connected in cascade, each of the plurality of GOA units corresponding to a stage the GOA unit at an nth stage corresponds to at least one scan line, the at least one scan line comprising a nth scan line, a (n+1)th scan line, and a (n+2)th scan line, the GOA unit at the an nth stage comprising:
a first pull-down holding circuit, connected to a gate signal node;
a pull-up circuit, connected to the first pull-down holding circuit through the gate signal node;
a bootstrap capacitance circuit, connected to the pull-up circuit through the gate signal node;
a pull-down circuit, connected to the bootstrap capacitance circuit through the gate signal node and the first pull-down holding circuit; and
a clock circuit, connected to the bootstrap capacitance circuit through the gate signal node and receiving a first clock signal;
wherein the first pull-down holding circuit and the pull-down circuit are connected to a direct current low supply voltage;
the clock circuit comprises:
a first transistor, comprising a first control terminal connected to the gate signal node, a first input terminal connected to the first clock signal, and a first output terminal outputting a start pulse at an nth stage;
a second transistor, comprising a second control terminal connected to the gate signal node, a second input terminal connected to the first clock signal, and a second output terminal connected to the nth scan line;
a third transistor, comprising a third control terminal connected to the gate signal node, a third input terminal connected to the first clock signal, and a third output terminal connected to the (n+1)th scan line; and
a fourth transistor, comprising a fourth control terminal connected to the gate signal node, a fourth input terminal connected to the first clock signal, and a fourth output terminal connected to the (n+2)th scan line;
wherein the pull-down circuit comprises:
a thirteenth transistor, comprising a thirteenth control terminal connected to the first pull-down holding circuit, a thirteenth input terminal connected to the direct current low supply voltage, and a thirteenth output terminal connected to the nth scan line;
a fourteenth transistor, comprising a fourteenth control terminal connected to a second clock, a fourteenth input terminal connected to the direct current low supply voltage, and a fourteenth output terminal connected to the nth scan line;
a fifteenth transistor, comprising a fifteenth control terminal connected to a fourth clock signal, a fifteenth input terminal connected to the direct current low supply voltage, and a fifteenth output terminal connected to the nth scan line;
a sixteenth transistor, comprising a sixteenth control terminal connected to the first pull-down holding circuit, a sixteenth input terminal connected to the direct current low supply voltage, and a sixteenth output terminal connected to the (n+1)th scan line;
a seventeenth transistor, comprising a seventeenth control terminal connected to a third clock signal, a seventeenth input terminal connected to the direct current low supply voltage, and a seventeenth output terminal connected to the (n+1)th scan line;
an eighteenth transistor, comprising an eighteenth control terminal connected to a fifth clock signal, an eighteenth input terminal connected to the direct current low supply voltage, and an eighteenth output terminal connected to the (n+1)th scan line;
a nineteenth transistor, comprising a nineteenth control terminal connected to the first pull-down holding circuit, a nineteenth input terminal connected to the direct current low supply voltage, and a nineteenth output terminal connected to the (n+2)th scan line;
a twentieth transistor, comprising a twentieth control terminal connected to the fourth clock signal, a twentieth input terminal connected to the direct current low supply voltage, and a twentieth output terminal connected to the (n+2)th scan line;
a twentieth-first transistor, comprising a twenty-first control terminal connected to a sixth clock signal, a twenty-first input terminal connected to the direct current low supply voltage, and a twenty-first output terminal connected to the (n+2)th scan line; and
wherein the cycle of the first clock signal, the cycle of the second clock signal, and the cycle of the third clock signal are the same, and the first clock signal, the second clock signal, and the third clock signal are triggered subsequently based on the difference of a ⅓ cycle; the fourth clock signal is inversed to the first clock signal, the fifth clock signal is inversed to the second clock signal, and the sixth clock signal is inversed to the third clock signal.

2. A gate driver on array (GOA) circuit for a liquid crystal display (LCD), comprising: a plurality of GOA units connected in cascade, each of the plurality of GOA units corresponding to a stage, at stages formed the GOA unit at an nth stage corresponds to at least one scan line, the at least one scan line comprising a nth scan line, a (n+1)th scan line, and a (n+2)th scan line, the GOA unit at the an nth stage comprising:
a first pull-down holding circuit, connected to a gate signal node;
a pull-up circuit, connected to the first pull-down holding circuit through the gate signal node;
a bootstrap capacitance circuit, connected to the pull-up circuit through the gate signal node;
a pull-down circuit, connected to the bootstrap capacitance circuit through the gate signal node; and the first pull-down holding circuit; and
a clock circuit, connected to the bootstrap capacitance circuit through the gate signal node and receiving a first clock signal;
wherein the first pull-down holding circuit and the pull-down circuit are connected to a direct current low supply voltage;
the clock circuit comprises:
a first transistor, comprising a first control terminal connected to the gate signal node, a first input terminal connected to the first clock signal, and a first output terminal outputting a start pulse at an nth stage;
a second transistor, comprising a second control terminal connected to the gate signal node, a second input terminal connected to the first clock signal, and a second output terminal connected to the nth scan line;
a third transistor, comprising a third control terminal connected to the gate signal node, a third input terminal connected to the first clock signal, and a third output terminal connected to the (n+1)th scan line; and
a fourth transistor, comprising a fourth control terminal connected to the gate signal node, a fourth input terminal connected to the first clock signal, and a fourth output terminal connected to the (n+2)th scan line.

3. The GOA circuit of claim 2, wherein the bootstrap capacitance circuit comprises:
a first capacitor, comprising a first terminal connected to the gate signal node and a second terminal connected to the start pulse at the nth stage.

4. The GOA circuit of claim 2, wherein the pull-up circuit comprises:
a fifth transistor, comprising a fifth control terminal receiving a start pulse at an (n−3)th stage, a fifth input terminal connected to the fifth control terminal, and a fifth output terminal connected to the gate signal node.

5. The GOA circuit of claim 2, wherein the first pull-down holding circuit comprises:
a sixth transistor, comprising a sixth control terminal receiving a start pulse at the (n+3)th stage, a sixth input terminal connected to the direct current low supply voltage, and a sixth output terminal connected to the gate signal node;
a seventh transistor, comprising a seventh control terminal connected to the gate signal node, and a seventh input terminal connected to the direct current low supply voltage;
an eighth transistor, comprising an eighth control terminal connected to a direct current high supply voltage, an eighth output terminal connected to the eighth control terminal, and an eighth input terminal connected to a seventh output terminal;
a ninth transistor, comprising a ninth control terminal connected to the gate signal node, and a ninth input terminal connected to the direct current low supply voltage;
a tenth transistor, comprising a tenth control terminal connected to the seventh output terminal, a tenth input terminal connected to the ninth output terminal, and a tenth output terminal connected to the eighth output terminal;
an eleventh transistor, comprising an eleventh control terminal connected to the tenth input terminal, an eleventh input terminal connected to the direct current low supply voltage, and an eleventh output terminal connected to the gate signal node;
a twelfth transistor, comprising a twelfth control terminal connected to the tenth input terminal, a twelfth input terminal connected to the direct current low supply voltage, and a twelfth output terminal connected to the start pulse at the nth stage.

6. The GOA circuit of claim 2, wherein the pull-down circuit comprises:
a thirteenth transistor, comprising a thirteenth control terminal connected to the first pull-down holding circuit, a thirteenth input terminal connected to the direct current low supply voltage, and a thirteenth output terminal connected to the nth scan line;
a fourteenth transistor, comprising a fourteenth control terminal connected to a second clock, a fourteenth input terminal connected to the direct current low supply voltage, and a fourteenth output terminal connected to the nth scan line;
a fifteenth transistor, comprising a fifteenth control terminal connected to a fourth clock signal, a fifteenth input terminal connected to the direct current low supply voltage, and a fifteenth output terminal connected to the nth scan line;
a sixteenth transistor, comprising a sixteenth control terminal connected to the first pull-down holding circuit, a sixteenth input terminal connected to the direct current low supply voltage, and a sixteenth output terminal connected to the (n+1)th scan line;
a seventeenth transistor, comprising a seventeenth control terminal connected to a third clock signal, a seventeenth input terminal connected to the direct current low supply voltage, and a seventeenth output terminal connected to the (n+1)th scan line;
an eighteenth transistor, comprising an eighteenth control terminal connected to a fifth clock signal, an eighteenth input terminal connected to the direct current low supply voltage, and an eighteenth output terminal connected to the (n+1)th scan line;
a nineteenth transistor, comprising a nineteenth control terminal connected to the first pull-down holding circuit, a nineteenth input terminal connected to the direct current low supply voltage, and a nineteenth output terminal connected to the (n+2)th scan line;
a twentieth transistor, comprising a twentieth control terminal connected to the fourth clock signal, a twentieth input terminal connected to the direct current low supply voltage, and a twentieth output terminal connected to the (n+2)th scan line;
a twentieth-first transistor, comprising a twenty-first control terminal connected to a sixth clock signal, a twenty-first input terminal connected to the direct current low supply voltage, and a twenty-first output terminal connected to the (n+2)th scan line.

7. The GOA circuit of claim 6, wherein the cycle of the first clock signal, the cycle of the second clock signal, and the cycle of the third clock signal are the same, and the first clock signal, the second clock signal, and the third clock signal are triggered subsequently based on the difference of a ⅓ cycle.

8. The GOA circuit of claim 6, wherein the fourth clock signal is inversed to the first clock signal, the fifth clock signal is inversed to the second clock signal, and the sixth clock signal is inversed to the third clock signal.

9. The GOA circuit of claim 2, wherein the GOA circuit further comprises a second pull-down holding circuit, comprising:
a twentieth-second transistor, comprising a twenty-second control terminal connected to the fourth clock signal, a twenty-second input terminal connected to a direct current low supply voltage, and a twenty-second output terminal connected to the gate signal node;
a twentieth-third transistor, comprising a twenty-third control terminal connected to the fourth clock signal, a twenty-third input terminal connected to the direct current low supply voltage, and a twenty-third output terminal connected to the start pulse at the nth stage.

10. A gate driver on array (GOA) circuit for a liquid crystal display (LCD), comprising: a plurality of GOA units connected in cascade, each of the plurality of GOA units corresponding to a stage, at stages formed, the GOA unit at an nth stage corresponds to at least one scan line, the at least one scan line comprising a (n+3)th scan line, a (n+4)th scan line, and a (n+5)th scan line, the GOA unit at the an nth stage comprising:
a first pull-down holding circuit, connected to a gate signal node;
a pull-up circuit, connected to the first pull-down holding circuit through the gate signal node;
a bootstrap capacitance circuit, connected to the pull-up circuit through the gate signal node;
a pull-down circuit, connected to the bootstrap capacitance circuit through the gate signal node and the first pull-down holding circuit; and
a clock circuit, connected to the bootstrap capacitance circuit through the gate signal node and receiving a fourth clock signal;
wherein the first pull-down holding circuit and the pull-down circuit are connected to a direct current low supply voltage;
the clock circuit comprises:
a first transistor, comprising a first control terminal connected to the gate signal node, a first input terminal connected to the fourth clock signal, and a first output terminal outputting a start pulse at an (n+3)th stage;
a second transistor, comprising a second control terminal connected to the gate signal node, a second input terminal connected to the fourth clock signal, and a second output terminal connected to the (n+4)th scan line;
a third transistor, comprising a third control terminal connected to the gate signal node, a third input terminal connected to the fourth clock signal, and a third output terminal connected to the (n+5)th scan line; and
a fourth transistor, comprising a fourth control terminal connected to the gate signal node, a fourth input terminal connected to the fourth clock signal, and a fourth output terminal connected to the (n+5)th scan line.

11. The GOA circuit of claim 10, wherein the bootstrap capacitance circuit comprises:
a first capacitor comprising a first terminal connected to the gate signal node and a second terminal connected to the start pulse at the (n+3)th stage.

12. The GOA circuit of claim 10, wherein the pull-up circuit comprises:
a fifth transistor, comprising a fifth control terminal receiving a start pulse at an nth stage, a fifth input terminal connected to the fifth control terminal, and a fifth output terminal connected to the gate signal node.

13. The GOA circuit of claim 10, wherein the first pull-down holding circuit comprises:
a sixth transistor, comprising a sixth control terminal receiving a start pulse at the (n+6)th stage, a sixth input terminal connected to the direct current low supply voltage, and a sixth output terminal connected to the gate signal node;
a seventh transistor, comprising a seventh control terminal connected to the gate signal node, and a seventh input terminal connected to the direct current low supply voltage;
an eighth transistor, comprising an eighth control terminal connected to a direct current high supply voltage, an eighth output terminal connected to the eighth control terminal, and an eighth input terminal connected to a seventh output terminal;
a ninth transistor, comprising a ninth control terminal connected to the gate signal node, and a ninth input terminal connected to the direct current low supply voltage;
a tenth transistor, comprising a tenth control terminal connected to the seventh output terminal, a tenth input terminal connected to the ninth output terminal, and a tenth output terminal connected to the eighth output terminal;
an eleventh transistor, comprising an eleventh control terminal connected to the tenth input terminal, an eleventh input terminal connected to the direct current low supply voltage, and an eleventh output terminal connected to the gate signal node;
a twelfth transistor, comprising a twelfth control terminal connected to the tenth input terminal, a twelfth input terminal connected to the direct current low supply voltage, and a twelfth output terminal connected to the start pulse at the (n+3)th stage.

14. The GOA circuit of claim 10, wherein the pull-down circuit comprises:
a thirteenth transistor, comprising a thirteenth control terminal connected to the first pull-down holding circuit, a thirteenth input terminal connected to the direct current low supply voltage, and a thirteenth output terminal connected to the (n+3)th scan line;
a fourteenth transistor, comprising a fourteenth control terminal connected to a first clock, a fourteenth input terminal connected to the direct current low supply voltage, and a fourteenth output terminal connected to the (n+3)th scan line;
a fifteenth transistor, comprising a fifteenth control terminal connected to a third clock signal, a fifteenth input terminal connected to the direct current low supply voltage, and a fifteenth output terminal connected to the (n+3)th scan line;
a sixteenth transistor, comprising a sixteenth control terminal connected to the first pull-down holding circuit, a sixteenth input terminal connected to the direct current low supply voltage, and a sixteenth output terminal connected to the (n+4)th scan line;
a seventeenth transistor, comprising a seventeenth control terminal connected to a second clock signal, a seventeenth input terminal connected to the direct current low supply voltage, and a seventeenth output terminal connected to the (n+4)th scan line;
an eighteenth transistor, comprising an eighteenth control terminal connected to a fourth clock signal, an eighteenth input terminal connected to the direct current low supply voltage, and an eighteenth output terminal connected to the (n+4)th scan line;
a nineteenth transistor, comprising a nineteenth control terminal connected to the first pull-down holding circuit, a nineteenth input terminal connected to the direct current low supply voltage, and a nineteenth output terminal connected to the (n+5)th scan line;
a twentieth transistor, comprising a twentieth control terminal connected to the third clock signal, a twentieth input terminal connected to the direct current low supply voltage, and a twentieth output terminal connected to the (n+5)th scan line;
a twentieth-first transistor, comprising a twenty-first control terminal connected to a fifth clock signal, a twenty-first input terminal connected to the direct current low supply voltage, and a twenty-first output terminal connected to the (n+5)th scan line.

15. The GOA circuit of claim 14, wherein the cycle of the first clock signal, the cycle of the second clock signal, and the cycle of the third clock signal are the same, and the first clock signal, the second clock signal, and the third clock signal are triggered subsequently based on the difference of a ⅓ cycle.

16. The GOA circuit of claim 14, wherein the fourth clock signal is inversed to the first clock signal, the fifth clock signal is inversed to the second clock signal, and the sixth clock signal is inversed to the third clock signal.

17. The GOA circuit of claim 10, wherein the GOA circuit further comprises a second pull-down holding circuit, comprising:
a twentieth-second transistor, comprising a twenty-second control terminal connected to the first clock signal, a twenty-second input terminal connected to a direct current low supply voltage, and a twenty-second output terminal connected to the gate signal node;
a twentieth-third transistor, comprising a twenty-third control terminal connected to the first clock signal, a twenty-third input terminal connected to the direct current low supply voltage, and a twenty-third output terminal connected to the start pulse at the (n+3)th stage.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Magnetic Field Sensor With Skewed Sense Magnetization Of Sense Layer

Technical Field and Background:
Magnetic field sensors, also known as magnetometers, are widely used in a number of applications including in, for example, compass, security, and military applications, geophysics and space research, biomagnetism and medical applications, and non-destructive testing. Magnetic field sensors are typically based on semiconductor materials (e.g., Hall sensors, magnetoresistors, and so forth) and ferromagnetic materials (e.g., ferromagnetic magnetoresistors and flux guides). Other magnetic field sensors utilize optical, resonant, and superconducting properties. In many Earth's field magnetic sensing applications, especially those involving compassing or orientation, it is extremely desirable to have three-axis sensing capability. In order to achieve low cost of such sensors, it is also desirable that the solution be a single chip or even fully integrable onto the accompanying application specific integrated circuit (ASIC) die. In handheld and miniaturized applications it is also critical to minimize power consumption in order to extend battery life.

Invention Disclosure:
A magnetic field sensor comprises a sensor bridge having multiple sensor legs. Each sensor leg includes magnetoresistive sense elements, each comprising a pinned layer having a reference magnetization parallel to a plane of the sensor and a sense layer having a sense magnetization that is skewed away from three orthogonal axes. The sense magnetization of a portion of the sense elements is oriented in a first direction and the sense magnetization of a different portion of the sense elements is magnetically biased in a second direction by a permanent magnet layer. The second direction differs from the first direction by an opposing angular magnitude to yield a balanced sensor bridge that produces a zero-offset outcome in the absence of an external magnetic field.

[Assistant]
1. A magnetic field sensor comprising:
a sensor bridge having a first leg and a second leg;
a first magnetoresistive sense element formed in said first leg and located in a plane of said magnetic field sensor, said first magnetoresistive sense element including a first pinned layer and a first sense layer, said first sense layer having a first sense magnetization oriented in a first <hkl> direction, wherein h, k, and l are Miller indices all of which are non-zero and <hkl> represents a family of directions;
a second magnetoresistive sense element formed in said second leg and located in said plane of said magnetic field sensor, said second magnetoresistive sense element including a second pinned layer and a second sense layer, said first and second magnetoresistive sense elements being sensitive to an external magnetic field along a sensing direction, wherein each of said first and second pinned layers has a reference magnetization oriented substantially parallel to said plane and said second sense layer has a second sense magnetization; and
a permanent magnet layer positioned proximate said second magnetoresistive sense element, wherein in the absence of said external magnetic field, said permanent magnet layer magnetically biases said second sense magnetization in a second <hkl> direction relative to said first <hkl> direction, wherein one of said h, k, and l of said second <hkl> direction is a negative value of a corresponding one of said h, k, and l of said first <hkl> direction.

2. The magnetic field sensor of claim 1 wherein said permanent magnet layer is located away from said first magnetoresistive sense element to substantially prevent said permanent magnet layer from magnetically biasing said first sense magnetization of said first sense layer of said first magnetoresistive sense element.

3. The magnetic field sensor of claim 1 wherein:
said first <hkl> direction of said first sense magnetization of said first magnetoresistive sense element is characterized by said Miller indices of [111]; and
said second <hkl> direction of said second sense magnetization of said second magnetoresistive sense element is characterized by said Miller indices of [ 1 11].

4. The magnetic field sensor of claim 1 wherein:
said first <hkl> direction of said first sense magnetization of said first magnetoresistive sense element is characterized by said Miller indices of [111]; and
said second <hkl> direction of said second sense magnetization of said second magnetoresistive sense element is characterized by said Miller indices of [1 1 1].

5. The magnetic field sensor of claim 1 wherein:
said first <hkl> direction of said first sense magnetization of said first magnetoresistive sense element is characterized by said Miller indices of [111]; and
said second <hkl> direction of said second sense magnetization of said second magnetoresistive sense element is characterized by said Miller indices of [11 1 ].

6. The magnetic field sensor of claim 1 wherein said reference magnetization of each of said first and second pinned layers is oriented in the same direction substantially parallel said plane.

7. The magnetic field sensor of claim 6 wherein said reference magnetization of said each of said first and second pinned layers is oriented orthogonal to said sensing direction.

8. The magnetic field sensor of claim 1 wherein said sensor bridge further comprises:
a third leg having a third magnetoresistive sense element formed therein, said third magnetoresistive sense element including a third pinned layer and a third sense layer; and
a fourth leg having a fourth magnetoresistive sense element formed therein, said fourth magnetoresistive sense element including a fourth pinned layer and a fourth sense layer, wherein:
said first, second, third, and fourth legs are coupled as a Wheatstone bridge such that said first and fourth magnetoresistive sense elements are coupled in series to form a first half of said Wheatstone bridge, said second and third magnetoresistive sense elements are coupled in series to form a second half of said Wheatstone bridge, said first half of said Wheatstone bridge is coupled in parallel with said second half of said Wheatstone bridge such that a first junction of said first and second magnetoresistive sense elements forms a first input terminal and a second junction of said third and fourth magnetoresistive sense elements forms a second input terminal;
said reference magnetization of each of said first, second, third, and fourth pinned layers of each of said first and third magnetoresistive sense elements is oriented in the same direction substantially parallel to said plane;
said third sense layer of said third magnetoresistive sense element has a third sense magnetization oriented in said first <hkl> direction; and
said permanent magnet layer is positioned proximate said fourth magnetoresistive sense element, said permanent magnet layer magnetically biasing a fourth sense magnetization of said fourth sense layer in said second <hkl> direction.

9. The magnetic field sensor of claim 8 wherein said permanent magnet layer is located away from said third magnetoresistive sense element to substantially prevent said permanent magnet layer from magnetically biasing said sense magnetization of said third sense layer of said third magnetoresistive sense element.

10. The magnetic field sensor of claim 1 wherein said permanent magnet layer is characterized by a single magnetic orientation.

11. The magnetic field sensor of claim 1 wherein said permanent magnet layer is a first permanent magnet layer and said magnetic field sensor further comprises a second permanent magnet layer vertically displaced away from said first permanent magnet layer and positioned proximate said second magnetoresistive sense element, wherein said first and second permanent magnet layers function cooperatively to magnetically bias said second sense magnetization of said second magnetoresistive sense element in said second <hkl> direction.

12. The magnetic field sensor of claim 1 wherein said sensor bridge is a first sensor bridge, said sensing direction is a first sensing direction, and said magnetic field sensor further comprises:
a second sensor bridge having a third leg and a fourth leg;
a third magnetoresistive sense element formed in said third leg and located in said plane of said magnetic field sensor, said third magnetoresistive sense element including a third pinned layer and a third sense layer, said third sense layer having a third sense magnetization oriented in said first <hkl> direction;
a fourth magnetoresistive sense element formed in said fourth leg and located in said plane of said magnetic field sensor, said fourth magnetoresistive sense element including a fourth pinned layer and a fourth sense layer, said third and fourth magnetoresistive sense elements being sensitive to an external magnetic field along a second sensing direction that is orthogonal to said first sensing direction, wherein each of said third and fourth pinned layers has said reference magnetization oriented substantially parallel to said plane; and
said permanent magnet layer is positioned proximate said fourth magnetoresistive sense element, said permanent magnet layer magnetically biasing a fourth sense magnetization of said fourth sense layer in a third <hkl> direction.

13. The magnetic field sensor of claim 12 further comprising:
a third sensor bridge having a fifth leg and a sixth leg;
a fifth magnetoresistive sense element formed in said fifth leg and located in said plane of said magnetic field sensor, said fifth magnetoresistive sense element including a fifth pinned layer and a fifth sense layer, said fifth sense layer having a fifth sense magnetization oriented in said first <hkl> direction;
a sixth magnetoresistive sense element formed in said sixth leg and located in said plane of said magnetic field sensor, said sixth magnetoresistive sense element including a sixth pinned layer and a sixth sense layer, said fifth and sixth magnetoresistive sense elements being sensitive to an external magnetic field along a third sensing direction that is orthogonal to each of said first and second sensing directions, wherein each of said fifth and sixth pinned layers has said reference magnetization oriented substantially parallel to said plane; and
said permanent magnet layer is positioned proximate sixth magnetoresistive sense element, said permanent magnet layer magnetically biasing a sixth sense magnetization of said sixth sense layer in a fourth <hkl> direction.

14. The magnetic field sensor of claim 13 wherein:
said first <hkl> direction of said first, third, and fifth sense magnetizations of corresponding ones of said first, third, and fifth magnetoresistive sense elements is characterized by said Miller indices of [111];
said second <hkl> direction of said second sense magnetization of said second magnetoresistive sense element is characterized by said Miller indices of [ 1 11];
said fourth <hkl> direction of said fourth sense magnetization of said fourth magnetoresistive sense element is characterized by said Miller indices of [1 1 1]; and
said sixth <hkl> direction of said sixth sense magnetization of said sixth magnetoresistive sense element is characterized by said Miller indices of [11 1 ].

15. A magnetic field sensor comprising:
a sensor bridge having a first leg, a second leg, a third leg, and a fourth leg;
a first magnetoresistive sense element formed in said first leg and located in a plane of said magnetic field sensor, said first magnetoresistive sense element including a first pinned layer and a first sense layer, said first pinned layer having a reference magnetization, and said first sense layer having a first sense magnetization;
a second magnetoresistive sense element formed in said second leg and located in said plane of said magnetic field sensor, said second magnetoresistive sense element including a second pinned layer and a second sense layer, said second pinned layer having said reference magnetization, and said second sense layer having a second sense magnetization;
a third magnetoresistive sense element formed in said third leg and located in a plane of said magnetic field sensor, said third magnetoresistive sense element including a third pinned layer and a third sense layer, said third pinned layer having said reference magnetization, and said third sense layer having a third sense magnetization;
a fourth magnetoresistive sense element formed in said fourth leg and located in a plane of said magnetic field sensor, said fourth magnetoresistive sense element including a fourth pinned layer and a fourth sense layer, said fourth pinned layer having said reference magnetization, and said fourth sense layer having a fourth sense magnetization; and
a permanent magnet layer positioned proximate said second and fourth magnetoresistive sense elements and characterized by a single magnetic orientation, wherein:
said first, second, third, and fourth legs are coupled as a Wheatstone bridge such that said first and fourth magnetoresistive sense elements are coupled in series to form a first half of said Wheatstone bridge, said second and third magnetoresistive sense elements are coupled in series to form a second half of said Wheatstone bridge, said first half of said Wheatstone bridge is coupled in parallel with said second half of said Wheatstone bridge such that a first junction of said first and second magnetoresistive sense elements forms a first input terminal and a second junction of said third and fourth magnetoresistive sense elements forms a second input terminal;
said first, second, third, and fourth magnetoresistive sense elements being sensitive to an external magnetic field along a sensing direction;
said reference magnetization of each of said first, second, third, and fourth pinned layers is oriented substantially parallel to said plane;
said first sense magnetization and said third sense magnetization are oriented in a first <hkl> direction, wherein h, k, and l are Miller indices all of which are non-zero and <hkl> represents a family of directions; and
in the absence of said external magnetic field, said permanent magnet layer magnetically biases said second sense magnetization and said fourth sense magnetization in a second <hkl> direction relative to said first <hkl> direction, wherein one of said h, k, and l of said second <hkl> direction is a negative value of a corresponding one of said h, k, and l of said first <hkl> direction.

16. The magnetic field sensor of claim 15 wherein said reference magnetization of each of said first, second, third, and fourth pinned layers is oriented in the same direction substantially parallel said plane and orthogonal to said sensing direction.

17. A magnetic field sensor comprising:
a first sensor bridge having a first leg and a second leg;
a first magnetoresistive sense element formed in said first leg and located in a plane of said magnetic field sensor, said first magnetoresistive sense element including a first pinned layer and a first sense layer, said first sense layer having a first sense magnetization oriented in a first <hkl> direction, wherein h, k, and l are Miller indices all of which are non-zero and <hkl> represents a family of directions;
a second magnetoresistive sense element formed in said second leg and located in said plane of said magnetic field sensor, said second magnetoresistive sense element including a second pinned layer and a second sense layer, said first and second magnetoresistive sense elements being sensitive to a first external magnetic field along a first sensing direction, wherein each of said first and second pinned layers has a reference magnetization oriented substantially parallel to said plane and said second sense layer has a second sense magnetization
a second sensor bridge having a third leg and a fourth leg;
a third magnetoresistive sense element formed in said third leg and located in said plane of said magnetic field sensor, said third magnetoresistive sense element including a third pinned layer and a third sense layer, said third sense layer having a third sense magnetization oriented in said first <hkl> direction;
a fourth magnetoresistive sense element formed in said fourth leg and located in said plane of said magnetic field sensor, said fourth magnetoresistive sense element including a fourth pinned layer and a fourth sense layer, said third and fourth magnetoresistive sense elements being sensitive to a second external magnetic field along a second sensing direction that is orthogonal to said first sensing direction, wherein each of said third and fourth pinned layers has said reference magnetization oriented substantially parallel to said plane; and
a permanent magnet layer positioned proximate said second magnetoresistive sense element and said fourth magnetoresistive sense element, said permanent magnet layer being characterized by a single magnetic orientation, wherein:
in the absence of said first external magnetic field, said permanent magnet layer magnetically biases said second sense magnetization in a second <hkl> direction relative to said first <hkl> direction such that a first one of said h, k, and l of said second <hkl> direction is a negative value of a first corresponding one of said h, k, and l of said first <hkl> direction; and
in the absence of said second external magnetic field, said permanent magnet layer magnetically biases said fourth sense magnetization in a third <hkl> direction such that a second one of said h, k, and l of said third <hkl> direction is said negative value of a second corresponding one of said h, k, and l of said first <hkl> direction.

18. The magnetic field sensor of claim 17 further comprising:
a third sensor bridge having a fifth leg and a sixth leg;
a fifth magnetoresistive sense element formed in said fifth leg and located in said plane of said magnetic field sensor, said fifth magnetoresistive sense element including a fifth pinned layer and a fifth sense layer, said fifth sense layer having a fifth sense magnetization oriented in said first <hkl> direction;
a sixth magnetoresistive sense element formed in said sixth leg and located in said plane of said magnetic field sensor, said sixth magnetoresistive sense element including a sixth pinned layer and a sixth sense layer, said fifth and sixth magnetoresistive sense elements being sensitive to a third external magnetic field along a third sensing direction that is orthogonal to each of said first and second sensing directions, wherein each of said fifth and sixth pinned layers has said reference magnetization oriented substantially parallel to said plane; and
said permanent magnet layer is positioned proximate sixth magnetoresistive sense element, wherein in the absence of said third external magnetic field, said permanent magnet layer magnetically biases a sixth sense magnetization of said sixth sense layer in a fourth <hkl> direction such that a third one of said h, k, and l of said fourth <hkl> direction is said negative value of a third corresponding one of said h, k, and l of said first <hkl> direction.

19. The magnetic field sensor of claim 18 wherein:
said first <hkl> direction of said first, third, and fifth sense magnetizations of corresponding ones of said first, third, and fifth magnetoresistive sense elements is characterized by said Miller indices of [111];
said second <hkl> direction of said second sense magnetization of said second magnetoresistive sense element is characterized by said Miller indices of [ 1 11];
said fourth <hkl> direction of said fourth sense magnetization of said fourth magnetoresistive sense element is characterized by said Miller indices of [1 1 1]; and
said sixth <hkl> direction of said sixth sense magnetization of said sixth magnetoresistive sense element is characterized by said Miller indices of [11 1 ].

20. The magnetic field sensor of claim 18 wherein:
said reference magnetization of each of said first, second, third, and fourth pinned layers is oriented in a first planar direction substantially parallel said plane; and
said reference magnetization of each of said fifth and sixth pinned layers is oriented in a second planar direction perpendicular to said first planar direction and substantially parallel to said plane.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Systems And Methods For Attaching A Device To A Rotating Shaft

Technical Field and Background:
For testing, diagnostic, and/or health monitoring purposes, it may be desirable to acquire a measurement (such as strain, temperature, and/or pressure) on a rotating shaft. In many situations, a full-scale slip ring or telemetry system may not be feasible, both physically and economically. In such an instance, a strap-on telemetry system may provide the best solution. In a traditional strap-on telemetry system, the telemetry transmitter is placed on the outer diameter of the rotating shaft, and a strap is used to secure the telemetry transmitter. The strap is typically tensioned by a yoke assembly positioned on the opposite side of the rotating shaft. The strap is tensioned such that the downward force applied by the strap to the outer surface of the telemetry transmitter is greater than the forces generated by the rotating mass of the telemetry transmitter (due to centrifugal loading). In this manner, the greater the centrifugal loading, the more downward force is required in the strap. However, the greater the downward force in the strap, the more likely it is to damage the telemetry transmitter.

Invention Disclosure:
A system for attaching a device to a rotating shaft is provided herein. The system may include a rotating shaft, a telemetry transmitter positioned about the rotating shaft, and a housing positioned about the telemetry transmitter. The telemetry transmitter may be trapped by the housing. The system also may include a connector configured to connect the housing to the rotating shaft.

[Assistant]
1. A system for attaching a device to a shaft, the system comprising:
a rotating shaft;
a telemetry transmitter positioned about the rotating shaft;
a housing comprising a base member and a cap member positioned around the telemetry transmitter, wherein the telemetry transmitter is trapped within the housing between the base member and the cap member; and
a connector configured to connect the housing to the rotating shaft, wherein the connector comprises
a dovetail attached to the base member, and
a dovetail slot disposed within the rotating shaft.

2. The system of claim 1, wherein the rotating shaft comprises a rotor of a gas turbine engine assembly, a steam turbine, a wind turbine, load couplings, or drive shafts.

3. The system of claim 1, further comprising:
a cavity formed between the base member and the cap member, wherein the cavity is configured to receive and trap the telemetry transmitter therein.

4. The system of claim 1, wherein the dovetail extends from the base member.

5. The system of claim 1, wherein the dovetail is secured within the dovetail slot to secure the housing to the rotating shaft.

6. The system of claim 1, further comprising one or more bolts to secure the base member to the cap member.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Self-Captured Detent Mechanism

Technical Field and Background:
Revolvers having a swing-out cylinder have withstood the test of time because they permit ease of loading and ejecting cartridges without compromising the strength of the frame. Such revolvers present special design challenges, in particular, challenges concerning the use of detent mechanisms to maintain the revolver in a closed configuration. The mechanism must be robust and reliable; it must maintain the revolver closed during firing yet allow it to be readily opened manually for ejecting spent cartridges and reloading. It is also advantageous if the detent mechanism helps to maintain precise alignment between cylinder and barrel. Ideally, the detent mechanism would be simple to make and assemble on the revolver frame.

Invention Disclosure:
A revolver has a detent mechanism providing positive mechanical engagement between the cylinder yoke and the frame. A housing mounted on the frame has a spring biased plunger that transversely engages a pin. The pin projects from the housing and engages a recess on the yoke when the revolver cylinder is closed. The pin is biased into engagement with the recess by the plunger to maintain the revolver closed and the chambers of the cylinder in precise alignment with the barrel during firing. Manual force applied to the cylinder can overcome the biasing force and permit the revolver to be opened and closed.

[Assistant]
1. A revolver, comprising:
a frame;
a yoke mounted on said frame and movable about a pivot axis between an open and a closed position, a recess being positioned within said yoke;
a cylinder mounted on said yoke;
a detent mechanism, comprising:
a housing mounted on said frame adjacent to said yoke;
a pin bore positioned within said housing, said pin bore extending longitudinally along a pin bore axis;
a plunger cavity positioned within said housing and intersecting said pin bore, said plunger cavity extending longitudinally along a plunger cavity axis, said plunger cavity axis being oriented transversely to said pin bore axis;
a pin having a tip, said pin being positioned within said pin bore and movable along said pin bore axis between a first position, wherein said tip projects from said housing and engages said recess when said yoke is in said closed position, and a second position, wherein said tip is within said housing;
an action surface positioned on said pin, said action surface being oriented transversely to said pin bore axis;
a plunger having an end, said plunger being positioned within said plunger cavity and movable along said plunger cavity axis;
a spring positioned within said plunger cavity and biasing said end of said plunger into engagement with said action surface of said pin.

2. The revolver according to claim 1, wherein said plunger cavity comprises an open end terminating on a surface of said housing and a closed end terminating within said housing, said spring being positioned between said closed end and said plunger.

3. The revolver according to claim 2, wherein said open end faces said yoke when said yoke is in said closed position.

4. The revolver according to claim 1, wherein said pin bore axis is parallel to said pivot axis.

5. The revolver according to claim 1, wherein said tip comprises a conical surface.

6. The revolver according to claim 5, wherein said pin comprises an end oppositely disposed to said tip, said end comprising a conical surface.

7. The revolver according to claim 1, wherein said pin has a round cross section.

8. The revolver according to claim 1, wherein said action surface has an orientation angle relative to said pin bore axis from 30° to 60°.

9. The revolver according to claim 1, wherein said action surface has an orientation angle relative to said pin bore axis of 45°.

10. The revolver according to claim 1, wherein said pin comprises a cylindrical body.

11. The revolver according to claim 10, wherein said action surface comprises a surface of a notch formed in said cylindrical body.

12. The revolver according to claim 11, wherein said notch is V-shaped.

13. The revolver according to claim 1, wherein said plunger has a round cross section.

14. The revolver according to claim 1, wherein said plunger comprises a cylindrical body.

15. The revolver according to claim 1, wherein said end of said plunger comprises at least one surface oriented angularly with respect to said plunger cavity axis.

16. The revolver according to claim 15, wherein said at least one surface has an orientation angle relative to said plunger cavity axis from 30° to 60°.

17. The revolver according to claim 15, wherein said at least one surface has an orientation angle relative to said plunger cavity axis of 45°.

18. The revolver according to claim 1, wherein said end of said plunger comprises first and second surfaces oriented angularly with respect to said plunger cavity axis.