[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: System Of Architecture And Related Built-In Nanomembranes For The Emitter Of A Light-To-Electricity All-Silicon Converter For The Giant Photocnversion And The Method Of Its Manufacture

Technical Field and Background:
The invention concerns simultaneously physical effects, materials, and fabrication processing to significantly increase the efficiency of the light-to-electricity conversion. The one photon-one electron principle no longer applies when there is generation of additional electrons in a process involving a shallow extrinsic energy level and the conduction band. Here we show that a complementary converter will cool hot electrons (generated by energetic photons) via a specific silicon metamaterial membrane system buried within the emitter at the c-Si/a-Si interface. From the photoconversion viewpoint there are three modes of photon interaction with matter: transmission, conversion into electron flux (when the photon energy is close to the band gap) and conversion into both electron and phonon fluxes (when the photon energy is clearly above the band gap). Energetic photons produce two fluxes: electron flux→collectable current and phonon flux energy lost heat. For photon energies that results in carrier multiplication, where the multiplication cycle is characterized by the ratio of additional photon energy to specific segton energy E δ (the mean value of E δ is 0.274 eV). A multistage process allows conversion of energetic photons into a electron population. The unused kinetic energy of photogenerated hot carriers, reaching a buried substructure(s) with a nanoscale Si-layered system, is transferred to near-equilibrium electrons collectable in the external circuit. The multistage conversion cycle starts with the primary generation (photon absorption), then continues with secondary generations by multiple collisions of hot electrons with segtons (due to the specific low-energy mechanism). To ensure the permanent electric charge state of the segton a specific electron transport mechanism within seg-matter through its boarding nanomembranes (interfaces) is absolutely necessary. This charge resplenishment depends on the extremely short time constants of the segton dynamics (recharging). The multiplication cycle depends on the dynamics of the involved carrier population that has to be taken into account situating of the sag-matter within the converter, preferentially within the emitter. So one of the manageable ways is a superposition of desired effects within a limited and suitably localized volume, subvolumes, part(s) of the emitter to assume optimal conditions for the full and efficient cycle of the giant photoconversion. The modulation of the local material uses simultaneously several physical interactions, such as variation of the matter structure, heavy impurity doping, transition zones of semiconductor interfaces, local stress fields, local electric fields, local electron transport, effective electric screening and well-defined functionality of usefully arranged active components. The conceived material modulation preserves conventional-like behavior of the converter due to, for example, adapted ratios of geometrical factors, useful defect screening, unperturbed free-electron extraction as well as specific electron transport mechanisms. Using the quantum dots analogy, one can say that the silicon bandgap is controlled by confinement of carriers in artificial semiconductor nanoobjects, i.e., segtons, which behave like individual atoms or molecules. If they are close enough to allow large collision probability, atomic-like electron energy levels appears in the band model of a bulk semiconductor. This gives rise to a new version of the semiconductor material with electrical and optical properties that are tuned by adjusting the seg-matter size, segton density and seg-matter disposition within the converter. A membrane separates carriers of the same electric charge (electrons) but of different kinetic energy, i.e., hot electrons from near equilibrium electrons. Active substructure(s) is(are) embedded within a part(s) of the emitter that distinguishes by its higher doping density from its(their) neighborhood. This innovation presents a practical realization of the theoretically evoked prediction for the bright future of the highly efficient light-to-electricity conversion due to “semiconductor nanocrystals embedded in semiconductor matrix”. Nanostructured transformations of semiconductors, preferentially of Si, lead to optimized nanocrystal-like nanoobjects, called segtons and corresponding metamaterial, called seg-matter. This is an answer how to operate in practice.

Invention Disclosure:
Architecture of the light-to-electricity converter characterized in that the system of amorphized nanograms, preferentially nanograms of amorphized silicon, of any shape are optimally spread within the crystalline host material, preferentially crystalline silicon that are wrapped around with a metamaterial seg-matter nanolayer, characterized by secondary generation centers, called segtons, that are conditioned around divacancies and disposed entirely or only partly within the volume of the emitter, this volume being limited at each end by a nanomembrane assuming the appropriate exploitation of the low-energy secondary generation through the giant photoconversion involving hot electrons, segtons and seg-matter.

[Assistant]
1. An architectural system defined within an emitter space of a semiconductor light-to-electricity converter, comprising:
a front electrode;
a rear electrode;
a base portion disposed adjacent to said rear electrode;
an emitter, comprising crystalline silicon (c-Si), disposed adjacent to said front electrode and having a front face portion;
a PN junction interposed between said base portion and said emitter; and
at least one layer of amorphized silicon (a-Si) nanograins comprising a plurality of horizontally separated amorphized silicon (a-Si) nanograins disposed within an upper region of said emitter so as to be close to said front face portion of said emitter, each one of said plurality of horizontally separated amorphized silicon (a-Si) nanograins having a predetermined vertically elongated geometrical configuration such that a relatively small upper surface area is disposed toward said front face of said emitter while a relatively large body surface area of each one of said amorphized silicon (a-Si) nanograins is disposed within said emitter, and wherein each one of said plurality of horizontally separated amorphized silicon (a-Si) nanograins is enveloped within a coating of metamaterial such that when said light-to-electricity converter is exposed to incident light, only a small part of the incident light is absorbed within the amorphized matter comprising said plurality of amorphized silicon (a-Si) nanograins as a result of only said relatively small upper surface area being exposed to incoming photons, while hot electrons, generated by energetic photons entering said emitter and moving in all directions within said emitter, will massively collide with said plurality of horizontally separated, vertically elongated amorphized silicon (a-Si) nanograins so as to result in vastly multiplied secondary electron generation.

2. The architectural system as set forth in claim 1, wherein:
said predetermined vertically elongated geometrical configuration of each one of said plurality of horizontally separated amorphized silicon (a-Si) nano-grains is selected from the group comprising a rectangular cross section, with the longitudinal axis of the rectangle oriented vertically, a triangular cross section with an apex portion of the triangle disposed toward said front face of said emitter, an ovoid with the longitudinal ax-is of the ovoid oriented vertically, a T-shaped cross-sectional configuration, a D-shaped cross-sectional configuration, and a C-shaped cross-sectional configuration.

3. The architectural system as set forth in claim 1, wherein:
said at least one layer of amorphized silicon (a-Si) nanograins comprises a plurality of layers of amorphized silicon (a-Si) nanograins wherein said plurality of layers of amorphized silicon (a-Si) nanograins are vertically separated from each other and comprise an uppermost layer of amorphized silicon (a-Si) nanograins disposed closest to said front face portion of said emitter while other layers of said plurality of layers of amorphized silicon (a-Si) nanograins are disposed beneath said uppermost layer of amorphized silicon (a-Si) nanograins and are disposed throughout said emitter.

4. The architectural system as set forth in claim 3, wherein:
each one of said plurality of horizontally separated amorphized silicon (a-Si) nanograins disposed within said uppermost layer of amorphized silicon (a-Si) nanograins disposed closest to said front face portion of said emitter comprise a predetermined vertically elongated geometrical configuration selected from the group comprising a rectangular cross section, with the longitudinal axis of the rectangle oriented vertically, and a triangular cross section with an apex portion of the triangle disposed toward said front face of said emitter;
each one of said plurality of horizontally separated amorphized silicon (a-Si) nanograins disposed within said other ones of said plurality of layers of amorphized silicon (a-Si) nanograins disposed beneath said uppermost layer of amorphized silicon (a-Si) nanograins have a predetermined geometrical configuration selected from the group comprising a rectangular cross section, with the longitudinal axis of the rectangle oriented vertically, a rectangular cross-section, with the longitudinal axis of the rectangle oriented horizontally, a triangular cross section with an apex portion of the triangle disposed toward said front face of said emitter, a triangular cross-section with an apex portion of the triangle disposed away from said front face of said emitter, a circular cross-section, an ovoid cross-section, a T-shaped cross-sectional configuration, a D-shaped cross-sectional configuration, and a C-shaped cross-sectional configuration.

5. The architectural system as set forth in claim 3, wherein:
a particular layer of said plurality of layers of amorphized silicon (a-Si) nanograins has a different number of amorphized silicon (a-Si) nanograins comprising said particular layer of amorphized silicon (a-Si) nanograins as compared to the number of amorphized silicon (a-Si) nanograins comprising another one of said plurality of layers of amorphized silicon (a-Si) nanograins.

6. The architectural system as set forth in claim 3, wherein:
the plurality of amorphized silicon (a-Si) nanograins disposed within said plurality of layers of amorphized silicon (a-Si) nanograins are all vertically aligned with each other.

7. The architectural system as set forth in claim 3, wherein:
the plurality of amorphized silicon (a-Si) nanograins disposed within said plurality of layers of amorphized silicon (a-Si) nanograins are vertically misaligned with respect to each other.

8. The architectural system as set forth in claim 1, further comprising:
first nanomembranes separating said unstressed crystalline silicon (c-Si) regions of said emitter from stressed crystalline silicon (<c-Si>) regions of said emitter; and
second nanomembranes separating said amorphized silicon (a-Si) nano-grains from said stressed crystalline silicon (<c-Si>) regions of said emitter.

9. The architectural system as set forth in claim 1, wherein:
the entire emitter volume occupied by said amorphized silicon (a-Si) nanograins is delimited by two semiconductor interface nanomembranes resulting from a predetermined doping profile.

10. A method of forming an architectural system defined within an emitter space of a semiconductor light-to-electricity converter, comprising the steps of:
providing a front electrode;
providing a rear electrode;
providing a base portion disposed adjacent to said rear electrode;
providing an emitter, comprising crystalline silicon (c-Si), disposed adjacent to said front electrode and having a front face portion;
providing a PN junction interposed between said base portion and said emitter; and
providing at least one layer of amorphized silicon (a-Si) nanograins comprising a plurality of horizontally separated amorphized silicon (a-Si) nanograins disposed within an upper region of said emitter so as to be close to said front face portion of said emitter, each one of said plurality of horizontally separated amorphized silicon (a-Si) nanograins having a predetermined vertically elongated geometrical configuration such that a relatively small upper surface area is disposed toward said front face of said emitter while a relatively large body surface area of each one of said amorphized silicon (a-Si) nanograins is disposed within said emitter, and wherein each one of said plurality of horizontally separated amorphized silicon (a-Si) nanograins is enveloped within a coating of metamaterial such that when said light-to-electricity converter is exposed to incident light, only a small part of the incident light is absorbed within the amorphized matter comprising said plurality of amorphized silicon (a-Si) nanograins as a result of only said relatively small upper surface area being exposed to incoming photons, while hot electrons, generated by energetic photons entering said emitter and moving in all directions within said emitter, will massively collide with said plurality of horizontally separated, vertically elongated amorphized silicon (a-Si) nanograins so as to result in vastly multiplied secondary electron generation.

11. The method as set forth in claim 10, wherein:
said predetermined vertically elongated geometrical configuration of each one of said plurality of horizontally separated amorphized silicon (a-Si) nano-grains is selected from the group comprising a rectangular cross section, with the longitudinal axis of the rectangle oriented vertically, a triangular cross section with an apex portion of the triangle disposed toward said front face of said emitter, an ovoid with the longitudinal ax-is of the ovoid oriented vertically, a T-shaped cross-sectional configuration, a D-shaped cross-sectional configuration, and a C-shaped cross-sectional configuration.

12. The method as set forth in claim 10, wherein:
said at least one layer of amorphized silicon (a-Si) nanograins comprises a plurality of layers of amorphized silicon (a-Si) nanongrains wherein said plurality of layers of amorphized silicon (a-Si) nanograins are vertically separated from each other and comprise an uppermost layer of amorphized silicon (a-Si) nanograins disposed closest to said front face portion of said emitter while other layers of said plurality of layers of amorphized silicon (a-Si) nanongrains are dis-posed beneath said uppermost layer of amorphized silicon (a-Si) nanograins and are disposed throughout said emitter.

13. The method as set forth in claim 12, wherein:
each one of said plurality of horizontally separated amorphized silicon (a-Si) nanograins disposed within said uppermost layer of amorphized silicon (a-Si) nanograins disposed closest to said front face portion of said emitter comprise a predetermined vertically elongated geometrical configuration selected from the group comprising a rectangular cross section, with the longitudinal axis of the rec- tangle oriented vertically, and a triangular cross section with an apex portion of the triangle disposed toward said front face of said emitter; and
each one of said plurality of horizontally separated amorphized silicon (a-Si) nanograins disposed within said other ones of said plurality of layers of amorphized silicon (a-Si) nanograins disposed beneath said uppermost layer of amorphized silicon (a-Si) nanograins have a predetermined geometrical configuration selected from the group comprising a rectangular cross section, with the longitudinal axis of the rectangle oriented vertically, a rectangular cross-section, with the longitudinal axis of the rectangle oriented horizontally, a triangular cross section with an apex portion of the triangle disposed toward said front face of said emitter, a triangular cross-section with an apex portion of the triangle disposed away from said front face of said emitter, a circular cross-section, an ovoid cross-section, a T-shaped cross-sectional configuration, a D-shaped cross-sectional configuration, and a C-shaped cross-sectional configuration.

14. The method as set forth in claim 12, wherein:
a particular layer of said plurality of layers of amorphized silicon (a-Si) nanograins has a different number of amorphized silicon (a-Si) nanograins comprising said particular layer of amorphized silicon (a-Si) nanograins as compared to the number of amorphized silicon (a-Si) nanograins comprising another one of said plurality of layers of amorphized silicon (a-Si) nanograins.

15. The method as set forth in claim 12, wherein:
the plurality of amorphized silicon (a-Si) nanograins disposed within said plurality of layers of amorphized silicon (a-Si) nanograins are all vertically aligned with each other.

16. The method as set forth in claim 12, wherein:
the plurality of amorphized silicon (a-Si) nanograins disposed within said plurality of layers of amorphized silicon (a-Si) nanograins are vertically mis-aligned with respect to each other.

17. The method as set forth in claim 10, further comprising:
first nanomembranes separating said unstressed crystalline silicon (c- Si) regions of said emitter from stressed crystalline silicon (<c-Si>) regions of said emitter; and
second nanomembranes separating said amorphized silicon (a-Si) nano-grains from said stressed crystalline silicon (<c-Si>) regions of said emitter.

18. The method as set forth in claim 10, wherein:
the entire emitter volume occupied by said amorphized silicon (a-Si) nanograins is delimited by two semiconductor interface nanomembranes resulting from a predetermined doping profile.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Method For Preparation Of Purified Autoimmune Antigen Positive Serum

Technical Field and Background:
Under normal circumstances, the body recognizes and treats its own tissue components as “self”, without immune response, which is self-tolerance. Self-tolerance occurs because the lymphocyte clones that recognize its own tissues are destroyed or forbidden during the embryonic development, as stated in Burnet's forbidden clone theory. However, in some cases, self-tolerance is compromised and the forbidden clones are re-activated, so that the body's immune system initiates immune response against its own tissue components, which leads to autoimmune diseases. The key is that the organism produces autoantibodies or sensitized T lymphocytes that react with its own tissue components and lead to the damage of the tissue and cells. The mechanism on the production of autoantibodies and sensitized T cells is very complicated. The following factors may play a role, according to research findings. First, the Emergence of Autoantigen 1. Release of Sequestered Antigens Sequestered antigens refer to tissue components, such as sperm, intraocular soluble components, brain tissue, etc, that normally do not contact with immune cells. However, their corresponding immune cell clones exist and are immune-responsive. When the isolation barrier is damaged due to surgery, trauma, infection and other reasons, the sequestered antigens are released into the bloodstream or lymph. The immune system mistake them as “foreign agents”, trigger the autoimmune response, and result in the autoimmune disease. 2. Changes of Tissue Components The antigenicity of tissue components may change due to physical factors (such as cold, heat, ionizing radiation), chemical factors (such as drugs), or biological factors (such as bacteria, viruses, etc.). The changed tissue components can stimulate an autoimmune response, and result in autoimmune diseases. 3. Cross-Reactivity Some bacteria and viruses have similar epitopes as those on normal human tissue cells. The antibodies and sensitized lymphocytes produced against the foreign agents may cross react with the human epitopes, which finally result in autoimmune diseases. Second, Abnormal Immune Response 1. Bypass Activation of Lymphocyte Under normal circumstances, both autoantigen-specific T and B lymphocyte clones exist in the body. B lymphocytes can respond to autoantigens while the Th cells are irresponsive. With inactivated Th cells, B cells can't produce autoantibodies. Some foreign antigens have similar or identical determinants as those recognizable by B cells. Due to the difference of the carrier determinants recognized by various T cells, the Th cells that recognize autoantigens remain silent while those that recognize foreign agents are activated and in turn activate B cells to produce autoantibodies. Through this Th Bypass Activation, autoimmune response is initiated. 2. Bypass Activation of Polyclonal Stimulant Some polyclonal stimulants, such as epstein-barr virus and super-antigens, are capable of initiating polyclonal activation of B-cells, or even of T-cells, by directly binding to the p-subunit of T-cell receptors in a non-specific fashion. Through this bypass activation, autoantibodies are produced and lead to the autoimmune response. 3. Abnormal Expression of Auxiliary Stimulating Factor In the immune response, immune cell activation needs both the recognition by the immune active cells of the antigen peptide complex on the surface of the antigen presenting cells, and the interactions of auxiliary stimulating factors between the two cells. If the expression of the auxiliary stimulating factor on the surface of the antigen presenting cell is abnormal, this may activate the immune response of T cell and cause autoimmune diseases. In addition, the imbalance of the functions of Th1 and Th2 cells are also related to the initiation of autoimmune diseases. Third, Abnormal Expression of Fas/FasL The abnormal expression of Fas/FasL is related to the genesis of autoimmune diseases. Fas belongs to the family of TNFR/NGFR (or CD95). It is present on the surface of a variety of cells including lymphocytes. Its ligand, FasL (Fas ligand), is usually expressed on the cellular membrane of the activated T cells such as CTL and NK cells. It can also be secreted into the extracellular space. Both free and membrane-bound FasL, when bind to membrane Fas, induce cell apoptosis.

Invention Disclosure:
The present invention relates to a method for preparation of purified autoimmune antigen positive serum. The method comprises steps of: using autoimmune antigen to immunize healthy animals, obtaining antiserum after blood sampling, and purifying the antiserum for obtaining positive serum, the step of purifying the antiserum for obtaining positive serum are as follows: affining and purifying the antiserum for obtaining IgG antibody; coupling the IgG antibody and human IgG Fc or human IgM Fc or human IgA Fc at a ratio of 1:1˜2; separating and purifying the coupled solution for obtaining IgG-IgG Fc conjugates concentrated solution or IgG-IgM Fc conjugates concentrated solution or IgG-IgA Fc conjugates concentrated solution; and diluting the IgG-IgG Fc conjugates concentrated solution or the IgG-IgM Fc conjugates concentrated solution or the IgG-IgA Fc conjugates concentrated solution to a concentration of 0.5˜1 μg/ml for obtaining the positive serum.

[Assistant]
1. A method for preparation of purified autoimmune antigen positive serum, the method comprising the steps of immunizing a healthy animal with an autoimmune antigen, obtaining antiserum after blood sampling from the immunized animal, purifying the antiserum and obtaining positive serum, wherein the steps of purifying the antiserum and obtaining the positive serum are as follows:
Purifying IgG antibody from the antiserum obtained after the blood sampling by an affinity chromatography;
Preparing human IgG Fc, human IgM Fc or human IgA Fc fraction by digesting human IgG, human IgM or human IgA by papain followed by purification of human IgG Fc fraction, human IgM Fc fraction, or human IgA Fc fraction by protein A affinity chromatograph, and activating the purified Fc fraction by 4-(N-maleic imide methyl) cyclohexane-1-carboxylic acid succinimide ester;
coupling the purified IgG antibody with the activated human IgG Fc or the activated human IgM Fc or the activated human IgA Fc at a ratio of 1:1˜2 to form a first coupled solution comprising IgG-IgG Fc conjugates or a second coupled solution comprising IgG-IgM Fc conjugates or a third coupled solution comprising IgG-IgA Fc conjugates respectively;
separating and purifying the IgG-IgG Fc conjugates as a concentrated solution from the first coupled solution or the IgG-IgM Fc conjugates as a concentrated solution from the second coupled solution or the IgG-IgA Fc conjugates as a concentrated solution from the third coupled solution; and
diluting the IgG-IgG Fc conjugates concentrated solution or the IgG-IgM Fc conjugates concentrated solution or the IgG-IgA Fc conjugates concentrated solution to a concentration of 0.5˜1 ug/ml which forms the positive serum.

2. The method of claim 1, wherein the antiserum is purified by agarose affinity media, or immune affinity chromatography column.

3. The method of claim 2, wherein the agarose affinity media is Protein-A sepharose CL-4B.

4. The method of claim 2, wherein the immune affinity chromatography is prepared by coupling the autoimmune antigen to sepharose gel.

5. The method of claim 2, wherein the antiserum is purified by the immune affinity chromatography column after it is disposed by Ammonium sulfate.

6. The method of claim 1, wherein the human IgG Fc or the human IgM Fc or the human IgA Fc is prepared by the following steps:
firstly, dissolving the human IgG or the human IgM or the human IgA into a papain buffer;
secondly, adding the enzyme papain to the papain buffer to digest the human IgG or the human IgM or the human IgA and carrying out digestion reaction;
thirdly, after the digestion reaction, adding iodoacetamide to terminate the digestion reaction, and
finally, after the termination step, extracting the human IgG Fc or the human IgM Fc or the human IgA Fc with the protein A affinity chromatography.

7. The method of claim 1, wherein the IgG antibody and the human IgG Fc or the human IgM Fc or the human IgA Fc is activated by 4-(N-maleic imide methyl) cyclohexane-1-carboxylic acid succinimide ester, and coupled at pH 7.2-7.4.

8. The method of claim 7, wherein the concentration of 4-(N-maleic imide methyl) cyclohexane-1-carboxylic acid succinimide ester coupling agent is 4˜6 mg/ml.

9. The method of claim 1, wherein the first coupled solution or the second coupled solution or the third coupled solution is separated and purified using Sephadex 200 Gel purification column.

10. The method of claim 1, wherein the IgG-IgG Fc conjugates concentrated solution or the IgG-IgM Fc conjugates concentrated solution or the IgG-IgA Fc conjugates concentrated solution is diluted using a dilution buffer containing BSA 0.4˜0.6%, Tris buffer 0.09˜0.11 mol/L, and PH 7.5˜8.5.

11. The method of claim 4, wherein the antiserum is purified by the immune affinity chromatography column after it is disposed by Ammonium sulfate.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Thermally Compensated Valve Trim Component

Technical Field and Background:
Process control systems typically include various components for controlling various process parameters. For example, a fluid process control system may include a plurality of control valves for controlling flow rate, temperature, and/or pressure of a fluid flowing through the system. The end product is dependent on the accuracy of the control of these parameters, which is, in turn, dependent on the geometry and characteristics of the control valves. Control valves are, for example, specifically designed and selected to provide for particular flow capacities and pressure changes. When these characteristics are compromised, the quality of the end product may be affected. A control valve typically includes components such as a valve body, a valve trim assembly (e.g., a flow control member, a valve stem, a valve seat), and an actuator configured to operably position the flow control member within the valve body. In some cases, it may be desirable (e.g., for cost reasons) to manufacture some of these components, for example a valve trim component of the valve trim assembly, from two or more different materials. However, the valve trim component, by virtue of being made from different materials (which in turn have different thermal expansion coefficients), will have different portions having different thermal expansion coefficients, thereby producing differential expansion between the different portions of the valve trim component when the control valve is used at different temperatures (particularly at elevated temperatures). Such differential thermal expansion may undesirably compromise the characteristics of the control valve, thereby affecting the quality of the end product. Worse yet, differential thermal expansion may eventually cause the valve trim component to fail.

Invention Disclosure:
A thermally compensated valve trim component for a fluid flow control device is provided. The valve trim component includes a base and a sleeve coupled to the base. The base is formed of a first material having a first thermal expansion coefficient, while the sleeve is formed of a second material having a second thermal expansion coefficient different from the first thermal expansion coefficient. The valve trim component further includes a thermal compensating apparatus arranged within a gland defined between the base and the sleeve. The thermal compensating apparatus is formed of a third material having a third thermal expansion coefficient different from the first and second thermal expansion coefficients, such that the thermal compensating apparatus minimizes a resultant thermal expansion differential of the valve trim component.

[Assistant]
1. A thermally compensated valve trim component of a valve trim assembly for a fluid flow control device, the valve trim component comprising:
a base comprising a body and a stud each formed of a first material having a first thermal expansion coefficient, the stud extending outwardly from the body;
a sleeve coupled to the base and formed of a second material having a second thermal expansion coefficient different from the first thermal expansion coefficient, the sleeve axially disposed between the body and an end of the stud such that the stud extends beyond the sleeve; and
a thermal compensating apparatus arranged within a gland defined between the base and the sleeve, the thermal compensating apparatus being formed of a third material having a third thermal expansion coefficient different from the first and second thermal expansion coefficients such that the thermal compensating apparatus minimizes a resultant thermal expansion differential of the valve trim component.

2. The valve trim component of claim 1, further comprising a fastener secured to a portion of the base to couple the sleeve to the base.

3. The valve trim component of claim 2, wherein the stud extends through an interior bore formed in the sleeve.

4. The valve trim component of claim 3, wherein the thermal compensating apparatus surrounds a portion of the outwardly extending stud.

5. The valve trim component of claim 3, wherein the stud has a threaded portion configured to threadingly engage a mating threaded portion of the fastener.

6. The valve trim component of claim 1, wherein the sleeve is formed of Carbide.

7. The valve trim component of claim 1, wherein the first material is a superalloy material.

8. The valve trim component of claim 1, wherein the first thermal expansion coefficient is greater than the second thermal expansion coefficient, and wherein the third thermal expansion coefficient is greater than the second thermal expansion coefficient.

9. The valve trim component of claim 8, wherein the third thermal expansion coefficient is greater than the first thermal expansion coefficient.

10. A fluid flow control device, comprising:
a valve body defining an inlet, an outlet, and a fluid flow path extending between the inlet and the outlet; and
a valve trim assembly disposed within the valve body and comprising:
a valve seat disposed within the valve body and defining an orifice through which the fluid flow path passes;
a valve cage coupled to the valve seat within the valve body and defining an interior bore; and
a flow control member sized for insertion into the interior bore of the valve cage and movable along an axis between a closed position, in which the flow control member engages the valve seat, and an open position in which the flow control member is spaced from the valve seat, the flow control member comprising
a base formed of a first material having a first thermal expansion coefficient;
a sleeve coupled to the base and formed of a second material having a second thermal expansion coefficient different from the first thermal expansion coefficient;
a thermal compensating apparatus arranged within a gland defined between the base and the sleeve, the thermal compensating apparatus being formed of a third material having a third thermal expansion coefficient different from the first and second thermal expansion coefficients such that the thermal compensating apparatus minimizes a resultant thermal expansion differential of the flow control member; and
a fastener secured to a portion of the base to couple the sleeve to the base, the fastener defining a sealing surface arranged to sealingly engage the valve seat when the flow control member is in the closed position.

11. The fluid flow control device of claim 10, wherein the base comprises an outwardly extending stud, the stud being disposed in an interior bore formed in the sleeve.

12. The fluid flow control device of claim 11, wherein the thermal compensating apparatus surrounds a portion of the outwardly extending stud.

13. The fluid flow control device of claim 11, wherein the stud has a threaded portion configured to threadingly engage a mating threaded portion of the fastener.

14. The fluid flow control device of claim 10, wherein the sleeve is formed of Carbide.

15. The fluid flow control device of claim 10, wherein the base is formed of a superalloy material.

16. The fluid flow control device of claim 10, wherein the first thermal expansion coefficient is greater than the second thermal expansion coefficient, and wherein the third thermal expansion coefficient is greater than the second thermal expansion coefficient.

17. The fluid flow control device of claim 10, wherein the base comprises a body and a stud extending outwardly from the body, and wherein the sleeve is axially disposed between the body and an end of the stud.

18. A thermally compensated valve trim component of a valve trim assembly for a fluid flow control device, the valve trim component comprising:
a base comprising a body and a stud extending outwardly from the body, the base being formed of a first material having a first thermal expansion coefficient;
a sleeve coupled to the base and comprising a body and a circumferential wall extending upwardly from the body of the sleeve, the sleeve being formed of a second material having a second thermal expansion coefficient different from the first thermal expansion coefficient;
a thermal compensating apparatus arranged within a gland defined between the stud of the base and the circumferential wall of the sleeve, the thermal compensating apparatus being formed of a third material having a third thermal expansion coefficient different from the first and second thermal expansion coefficients such that the thermal compensating apparatus minimizes a resultant thermal expansion differential of the valve trim component; and
a fastener secured to a portion of the base to couple the sleeve to the base.

19. The valve trim component of claim 18, wherein the sleeve is axially disposed between the body of the base and the fastener.

20. The valve trim component of claim 18, wherein the stud of the base extends through the sleeve and has an end disposed in an aperture formed in the fastener.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Semiconductor Component With Dynamic Behavior

Technical Field and Background:
The present invention relates to a semiconductor component, in particular a transistor, such as a trench transistor, for example. A trench transistor has a gate electrode arranged in at least one trench of a semiconductor body and serving for controlling a conducting channel in a body zone arranged between a source zone doped complementarily to the body zone and a drift zone doped complementarily to the body zone. The drift zone is arranged between the source zone and a drain zone, wherein the doping and the dimensions of the drift zone crucially determine the dielectric strength of the component. In order to increase the dielectric strength a field electrode may be provided in the trench of the gate electrode, the field electrode being arranged adjacent to the drift zone and being at gate potential. When the component is turned off, the field electrode serves for compensation of part of the dopant charge present in the drift zone. In the known component, a plurality of trenches having gate electrode sections and field electrode sections arranged therein are present and arranged at a distance from the drain zone. In this case, a distance between the trench and the drain zone is intended to be approximately half as large as a mutual distance between two adjacent trenches. In “dense trench” transistors gate electrode sections and field electrode sections are spaced apart so closely that during static operation, when a reverse voltage is applied, a field strength maximum occurs at a lower end of the trenches in the drift zone, such that an avalanche breakdown occurs in this region when the dielectric strength limit is exceeded. Transistors of this type are also referred to as “dense trench” transistors. A further example of a trench transistor is described in DE 10 2004 052 678 B3. In components of this type, a distinction can be made between two breakdown regimes: the static breakdown explained above, in which only a current having a low current density flows after the breakdown and which is referred to hereinafter as breakdown with low current density; and a breakdown with high current density, in which a high current density is established rapidly in a drift zone section arranged between the trenches. In the case of such a breakdown with high current density, in dense trench transistors the field strength maximum may no longer occur at the lower end of the trenches, but rather at a pn junction between the body zone and the drift zone. This is unfavorable because the entire avalanche current flowing through the component is concentrated on the mesa region between two trenches in which the avalanche breakdown first commences. This can lead to local damage to the component, whereby the component becomes unusable. During an avalanche breakdown that occurs below the trenches in the drift zone, by contrast, the avalanche current is distributed between a plurality of mesa regions, which reduces the risk of destruction.

Invention Disclosure:
One embodiment provides a semiconductor component including a semiconductor body having a first side and a second side and a drift zone; a first semiconductor zone doped complementarily to the drift zone and adjacent to the drift zone in a direction of the first side; a second semiconductor zone of the same conduction type as the drift zone adjacent to the drift zone in a direction of the second side; at least two trenches arranged in the semiconductor body and extending into the semiconductor body and arranged at a distance from one another; and a field electrode arranged in the at least two trenches adjacent to the drift zone. The at least two trenches are arranged at a distance from the second semiconductor zone in the vertical direction, a distance between the trenches and the second semiconductor zone is greater than 1.5 times the mutual distance between the trenches, and a doping concentration of the drift zone in a section between the trenches and the second semiconductor zone differs by at most 35% from a minimum doping concentration in a section between the trenches.

[Assistant]
1. A semiconductor component comprising:
a semiconductor body;
a drift zone, a body zone, a source zone and a drain zone in the semiconductor body, wherein, in a vertical direction of the semiconductor body, the body zone is arranged between the source zone and the drift zone and the drift zone is arranged between the body zone and the drain zone;
a gate electrode dielectrically insulated from the body zone by a gate dielectric layer;
at least two trenches extending from a first side of the semiconductor body in the vertical direction into the semiconductor body, wherein the at least two trenches are arranged at a distance from one another in a lateral direction of the semiconductor body;
a field electrode arranged adjacent to the drift zone in the at least two trenches, wherein the field electrode is connected to the source zone; and
a field dielectric layer dielectrically insulating the field electrode from the drift zone and being thicker than the gate dielectric layer,
wherein the at least two trenches are arranged at a distance from the drain zone in the vertical direction;
wherein the distance between the trenches and the drain zone in the vertical direction is greater than 1.5 times the distance between the at least two trenches in the lateral direction,
wherein a doping concentration of a drift zone section arranged in the vertical direction between the at least two trenches and the drain zone differs by at most 35% from a minimum doping concentration of a drift zone section arranged in the lateral direction between the trenches.

2. The semiconductor component of claim 1, wherein the doping concentration of the drift zone section arranged in the lateral direction between the trenches is between 5·10 15 cm −3 and 1·10 17 cm −3.

3. The semiconductor component of claim 1,
wherein the vertical direction is substantially perpendicular to the first side, and
wherein the lateral direction is substantially parallel to the first side.

4. The semiconductor component of claim 1,
wherein a conduction type of the body zone is complementary to a conduction type of the source zone and the drift zone.

5. The semiconductor component of claim 4,
wherein a conduction type of the drain zone equals a conduction type of the drift zone.

6. The semiconductor component of claim 4,
wherein a conduction type of the drain zone is complementary to a conduction type of the drift zone.

7. The semiconductor component of claim 1, wherein the doping concentration of the drift zone section arranged in the vertical direction between the trenches and the drain zone differs by at most 20% from the minimum doping concentration of the drift zone section arranged in the lateral direction between the trenches.

8. The semiconductor component of claim 1, wherein the gate electrode and the field electrode are arranged in the at least two trenches.

9. The semiconductor component of claim 1,
wherein the drain zone is arranged between the drift zone and a semiconductor layer doped complementarily to the drain zone, and
wherein the semiconductor component further comprises a connecting zone of the same conduction type as the drain zone, wherein the connecting zone extends from the first side to the drain zone.

10. The semiconductor component of claim 1, wherein the dimensions and/or the doping concentration of the drift zone are chosen in such a way that when the component is turned off after the occurrence of a voltage breakdown, a depth over which an electric field extends in a direction of the second semiconductor zone proceeding from a semiconductor junction between the drift zone and the body zone is dependent on the current flowing through the component, wherein the depth in the case of a current corresponding to a rated current is 1.5 times as large as in the case of a current corresponding to at most a thousandth of the rated current.

11. A method, comprising:
forming a drift zone, a body, a source zone and a drain zone in the semiconductor body, such that, in a vertical direction of the semiconductor body, the body zone is arranged between the source zone and the drift zone and the drift zone is arranged between the body zone and the drain zone;
forming a gate electrode dielectrically insulated from the body zone by a gate dielectric layer;
forming at least two trenches extending from a first side of the semiconductor body in a vertical direction into the semiconductor body, wherein the at least two trenches are arranged at a distance from one another in a lateral direction of the semiconductor body;
forming a field electrode in the at least two trenches adjacent to the drift zone, the field electrode connected to the source zone;
forming a field dielectric layer dielectrically insulating the field electrode from the drift zone and being thicker than the gate dielectric layer;
wherein forming the at least two trenches comprises forming the at least two trenches at a distance from the drain zone in the vertical direction such that a distance between the at least two trenches and the drain zone in the vertical direction is greater than 1.5 times a distance between the at least two trenches in the lateral direction; and
wherein forming the drift zone comprises providing a doping concentration of a drift zone section arranged in the vertical direction between the trenches and the drain zone such that it differs by at most 35% from a minimum doping concentration of a drift zone section arranged in the lateral direction between the trenches.

12. The method of claim 11, wherein the doping concentration of the drift zone section arranged in the lateral direction between the trenches is between 5·10 15 cm −3 and 1·10 17 cm −3.

13. The method of claim 12,
wherein forming the drain zone comprises forming the drain zone such that a conduction type of the drain zone is complementary to a conduction type of the drift zone.

14. The method of claim 11,
wherein the vertical direction is substantially perpendicular to the first side, and
wherein the lateral direction is substantially parallel to the first side.

15. The method of claim 11,
wherein forming the drift zone, the body zone and the source zone comprises forming the drift zone, the body zone and the source zone such that a conduction type of the body zone is complementary to a conduction type of the source zone and the drift zone.

16. The method of claim 15,
wherein forming the drain zone comprises forming the drain zone such that a conduction type of the drain zone equals a conduction type of the drift zone.

17. The method of claim 11, wherein forming the drift zone comprises providing the doping concentration of the drift zone section arranged in the vertical direction between the at least two trenches and the drain zone such that it differs by at most 20% from the minimum doping concentration of the drift zone section arranged in the lateral direction between the trenches.

18. The method of claim 11, wherein a distance between the trenches and the second semiconductor zone and a doping concentration of the drift zone in the section between the trenches and the second semiconductor zone are coordinated with one another in such a way that an integral of the doping concentration of the drift zone in a vertical direction of the semiconductor body between the trenches and the second semiconductor zone is greater than or equal to 1.5 times the breakdown charge of the semiconductor material of the drift zone.

19. The method of claim 18, wherein the integral of the dopant charge of the drift zone in the vertical direction is greater than or equal to 2 times the breakdown charge of the semiconductor material of the drift zone.

20. The method of claim 19, wherein the integral of the dopant charge of the drift zone in the vertical direction is greater than or equal to 2.5 times the breakdown charge of the semiconductor material of the drift zone.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Interlock For Circuit Interrupting Device

Technical Field and Background:
Circuit-interrupting devices (i.e., switches) include load-breakers, such as vacuum interrupters, that are used to control the flow of electricity through the switch. For example, vacuum interrupters typically include a stationary contact, a moveable contact, and a mechanism for moving the movable contact. To open the electrical circuit defined by the switch, the movable contact is separated from the stationary contact.

Invention Disclosure:
A circuit-interrupting device includes a load-breaker operable between an open state and a closed state and a first interlock member operatively associated with the load-breaker. The first interlock member moves between a first position and a second position when the load-breaker moves between the closed state and the open state. The circuit-interrupting device further includes a disconnect switch that moves between an open state and a closed state. When the load-breaker is in the closed state, the first interlock member is in the first position and contacts the disconnect switch to prevent the disconnect switch from moving from the closed state to the open state.

[Assistant]
1. A circuit-interrupting device comprising:
a load-breaker operable between a load-breaker open state and a load-breaker closed state;
a first interlock member operatively associated with the load-breaker, wherein the first interlock member moves between a first position and a second position when the load-breaker moves between the load-breaker closed state and the load-breaker open state; and
a disconnect switch that moves between a disconnect switch open state and a disconnect switch closed state,
wherein when the load-breaker is in the load-breaker closed state, the first interlock member is in the first position relative to the disconnect switch to prevent the disconnect switch from moving from the disconnect switch closed state to the disconnect switch open state.

2. The circuit-interrupting device of claim 1, further comprising a second interlock member coupled to the disconnect switch and configured such that when the first interlock member is in the first position, the first interlock member contacts the second interlock member to prevent the disconnect switch from moving from the disconnect switch closed state to the disconnect switch open state.

3. The circuit-interrupting device of claim 1, wherein the disconnect switch is configured to rotate about a pivot point to move between the disconnect switch open state and the disconnect switch closed state.

4. The circuit-interrupting device of claim 3, further comprising a second interlock member coupled to the disconnect switch and configured to rotate about the pivot point when the disconnect switch moves between the disconnect switch open state and the disconnect switch closed state.

5. The circuit-interrupting device of claim 1, wherein the disconnect switch is movable by an operating mechanism and, when the first interlock member is in the first position, the first interlock member prevents the disconnect switch from moving from the disconnect switch closed state to the disconnect switch open state independent of the operating mechanism.

6. The circuit-interrupting device of claim 1, wherein the disconnect switch is enclosed within the circuit-interrupting device and is visible from an exterior of the circuit-interrupting device when the disconnect switch is in the disconnect switch open state.

7. The circuit-interrupting device of claim 1, wherein when the load-breaker is in the load-breaker open state and the disconnect switch is in the disconnect switch open state, the disconnect switch prevents the load-breaker from moving from the load-breaker open state to the load-breaker closed state.

8. The circuit-interrupting device of claim 1, further comprising a second interlock member coupled to the disconnect switch and configured such that when the load-breaker is in the load-breaker open state and the disconnect switch is in the disconnect switch open state, the second interlock member is positioned to block the first interlock member and prevent the load-breaker from moving from the load-breaker open state to the load-breaker closed state.

9. The circuit-interrupting device of claim 4, wherein when the load-breaker is in the load-breaker open state and the disconnect switch is in the disconnect switch open state, the disconnect switch is positioned to prevent the load-breaker from moving from the load-breaker open state to the load-breaker closed state.

10. The circuit-interrupting device of claim 1, wherein when the first interlock member is in the second position the disconnect switch is movable from the disconnect switch closed state to the disconnect switch open state.

11. An interlock system for a circuit-interrupting device, the circuit interrupting device including a load-breaker operable between a load-breaker open state and a load-breaker closed state and a disconnect switch in series with the load-breaker and having a blade movable between a blade open state and a blade closed state, the interlock system comprising:
a first interlock member operably associated with the load-breaker, the first interlock member having a first interlock state when the load-breaker is in the load-breaker closed state and a second interlock state when the load-breaker is in the load-breaker open state, wherein the first interlock member moves from the first interlock state to the second interlock state when the load-breaker moves to the load-breaker open state,
wherein, when the first interlock member is in the first interlock state, the first interlock member is positioned to prevent the disconnect switch blade from moving from the blade closed state to the blade open state.

12. The interlock system of claim 11, wherein when the first interlock member is in the second interlock state, the disconnect switch blade is only then movable from the blade closed state to the blade open state.

13. The interlock system of claim 11, wherein a portion of the disconnect switch comprises a second interlock member coupled to the disconnect switch blade for movement with the blade.

14. The interlock system of claim 11, wherein when the load-breaker is in the load-breaker open state and the disconnect switch blade is in the blade open state, the disconnect switch prevents the load-breaker from moving from the load-breaker open state to the load-breaker closed state.

15. A circuit-interrupting device comprising:
a load-breaker including a first contact and a second contact, wherein the second contact is movable relative to the first contact between a load-breaker closed state and a load-breaker open state;
a first operating mechanism for moving the second contact between the load-breaker closed state and the load-breaker open state;
a first actuating assembly for controlling movement of the first operating mechanism;
a disconnect switch having a blade pivotable between a disconnect switch closed state and a disconnect switch open state;
a second operating mechanism for moving the disconnect switch blade between the disconnect switch closed state and the disconnect switch open state;
a second actuating assembly for controlling movement of the second operating mechanism; and
a first interlock member coupled to the load-breaker for concurrent travel therewith to prevent, independently of the second actuating assembly, the disconnect switch blade from pivoting from the disconnect switch closed state to the disconnect switch open state when the second contact is in the load-breaker closed state.

16. The circuit interrupting device of claim 15, wherein when the second contact is in the load-breaker open state, the disconnect switch blade is pivotable from the disconnect switch closed state to the disconnect switch open state.

17. The circuit-interrupting device of claim 15, wherein when the second contact is in the load-breaker closed state, the first interlock member contacts a portion of the disconnect switch to prevent the disconnect switch blade from pivoting from the disconnect switch closed state to the disconnect switch open state.

18. The circuit-interrupting device of claim 17, wherein the portion of the disconnect switch comprises a second interlock member coupled to the disconnect switch blade for pivoting with the blade.

19. The circuit-interrupting device of claim 15, wherein when the second contact is in the load-breaker open state and the disconnect switch blade is in the disconnect switch open state, the disconnect switch prevents the second contact from moving from the load-breaker open state to the load-breaker closed state.

20. The circuit-interrupting device of claim 19, wherein the disconnect switch prevents the second contact from moving from the load-breaker open state to the load-breaker closed state independently of the first actuating assembly.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Method For Producing Light Emitting Device

Technical Field and Background:
1. Field of the Invention The present invention relates to a method for producing a light emitting device. 2. Description of Related Art In Patent Literature 1: JP 2003-133262A, for example, discloses a method for producing a semiconductor package comprising a step of forming dividing grooves on one surface of a ceramic wiring board, a step of mounting semiconductor elements on the other surface of the wiring board, a step of sealing the semiconductor elements with an epoxy sealing resin, a step of forming dividing recesses on the sealing resin surface at the positions corresponding to the dividing grooves of the wiring board, and a step of dividing an integrated body of the wiring board and sealing resin at the dividing grooves and dividing recesses. However, a silicone-based resin, for example, which has recently been widely used as a sealing resin for a light emitting diode (hereinafter abbreviated as “LED”), has a high rubber elasticity, unlike a hard epoxy-based resin, and is difficult to cut using a rotary blade or the like, so that a simultaneous cutting of both the resin and the hard ceramic wiring board may be complicated.

Invention Disclosure:
A method for producing a light emitting device includes providing a light emitting device array including a collective substrate, a plurality of light emitting elements, a covering member covering a region surrounding the plurality of light emitting elements, in which the plurality of light emitting elements and the covering member are arranged on an upper surface of the collective substrate, the collective substrate including a ceramic base member, and the covering member containing a silicone-based resin as a base material; making a cut into the covering member such that the cut has a depth such that an uncut portion remains in the covering member in a direction of the depth' and push-splitting the collective substrate, and splitting the uncut portion of the covering member after the making the cut into the covering member.

[Assistant]
1. A method for producing a light emitting device, the method comprising:
providing a light emitting device array including a collective substrate, a plurality of light emitting elements, and a covering member covering a region surrounding the plurality of light emitting elements, the plurality of light emitting elements and the covering member being arranged on an upper surface of the collective substrate, the collective substrate including a ceramic base member, and the covering member containing a silicone resin as a base material,
making a cut into the covering member such that the cut has a depth such that an uncut portion remains in the covering member in a direction of the depth, and
after making the cut into the covering member, pushing a push-splitting blade into the cut in the covering member from a covering member side of the light emitting device array, so as to split the uncut portion of the covering member and push-split the collective substrate.

2. The method for producing a light emitting device according to claim 1, wherein the splitting of the uncut portion of the covering member is performed simultaneously with the push-splitting the collective substrate.

3. The method for producing a light emitting device according to claim 1, wherein the splitting of the uncut portion of the covering member is performed by pulling apart the covering member after the push-splitting of the collective substrate.

4. The method for producing a light emitting device according to claim 1, wherein a thickness of the uncut portion of the covering member in the making the cut into the covering member is 50 μm or less.

5. The method for producing a light emitting device according to claim 1, wherein scribe lines are formed on a lower surface of the collective substrate prior to the step of push-splitting the collective substrate, the step of making the cut is performed along the scribe lines, and the collective substrate is push-split along the scribe lines in the step of push-splitting the collective substrate.

6. The method for producing a light emitting device according to claim 1, wherein ultrasonic waves are applied to the push-splitting blade in the step of push-splitting the collective substrate.

7. The method for producing a light emitting device according to claim 1, wherein the step of making the cut is performed using a non-rotating blade.

8. The method for producing a light emitting device according to claim 7, wherein ultrasonic waves are applied to the non-rotating blade.

9. The method for producing a light emitting device according to claim 7, wherein the covering member contains a white pigment and/or a fluorescent material.

10. The method for producing a light emitting device according to claim 9, wherein the covering member includes a lower layer containing the white pigment, and an upper layer containing the fluorescent material.

11. The method for producing a light emitting device according to claim 2, wherein a thickness of the uncut portion of the covering member in the step of making the cut into the covering member is 50 μm or less.

12. The method for producing a light emitting device according to claim 11, wherein the scribe lines are formed on the lower surface of the collective substrate prior to the step of push-splitting the collective substrate, the step of making the cut is performed along the scribe lines, and the collective substrate is push-split along the scribe lines in the step of push-splitting the collective substrate.

13. The method for producing a light emitting device according to claim 12, wherein ultrasonic waves are applied to the push-splitting blade in the step of push-splitting the collective substrate.

14. The method for producing a light emitting device according to claim 13, wherein the step of making the cut is performed using a non-rotating blade.

15. The method for producing a light emitting device according to claim 14, wherein ultrasonic waves are applied to the non-rotating blade.

16. The method for producing a light emitting device according to claim 3, wherein a thickness of the uncut portion of the covering member in the step of making the cut into the covering member is 50 μm or less.

17. The method for producing a light emitting device according to claim 16, wherein scribe lines are formed on the lower surface of the collective substrate prior to the step of push-splitting the collective substrate, the step of making the cut is performed along the scribe lines, and the collective substrate is push-split along the scribe lines in the step of push-splitting the collective substrate.

18. The method for producing a light emitting device according to claim 17, wherein ultrasonic waves are applied to the push-splitting blade in the step of push-splitting the collective substrate.

19. The method for producing a light emitting device according to claim 18, wherein the step of making the cut is performed using a non-rotating blade.

20. The method for producing a light emitting device according to claim 19, wherein ultrasonic waves are applied to the non-rotating blade.

21. The method for producing a light emitting device according to claim 1, wherein the cut in the covering member is made using a cutting blade.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Damping Force Generation Device For Vehicle

Technical Field and Background:
1. Field of the Invention The present invention relates to a damping force generation device for a vehicle, and more particularly, to a damping force generation device including a shock absorber. 2. Description of the Related Art When a vehicle such as an automobile travels, static electricity is generated in the vehicle due to the flow of air in a state in which the air is brought into friction contact with the vehicle. Static electricity is also generated when each portion of a tire is repeatedly brought into contact with a road surface and separated therefrom along with the rotation of a wheel, when components in an engine, a brake device, or the like move relatively under a contact state, and the like. The vehicle is substantially electrically insulated from the ground due to a tire having low conductivity, and hence electric charge (in general, positive electric charge) is charged to a vehicle body or the like when static electricity is generated in the vehicle. Radio noise is liable to be generated when the electric charge is charged to the vehicle body or the like. Therefore, a structure for reducing electric charge that is charged to a vehicle through the passage of an electric current has been investigated hitherto, and various structures have been proposed. For example, in Japanese Patent Application Laid-open No. 2009-181694, there is disclosed an electrostatic eliminator having such a configuration that charged silicon is filled into a case in which ceramic bodies are arranged densely in a radial fashion, and one of conductive wires connected to both sides of the case is connected to a minus terminal of a battery and the other conductive wire is connected to a vehicle body. In this type of the electrostatic eliminator, static electricity of the vehicle body is neutralized by grounding, and thus the electric charge that is charged to the vehicle body can be reduced. The related-art electrostatic eliminator as disclosed in Japanese Patent Application Laid-open No. 2009-181694 has a complicated structure, and hence the electrostatic eliminator is required to be connected to the minus terminal of the battery and the vehicle body through the conductive wires, with the result that an installation space for the electrostatic eliminator is also required. Incidentally, the vehicle includes damping force generation devices configured to damp vibrations of the vehicle body. Each of the damping force generation devices includes a shock absorber having a cylinder and a piston fitted to the cylinder in a reciprocally movable manner. The shock absorber is coupled to a sprung member and an unsprung member of the vehicle at a rod part of the piston and the cylinder, respectively, and generates the damping force due to a flow resistance when oil passes through orifices formed in the piston along with relative displacement between the sprung member and the unsprung member. Experimental research conducted by the inventors of the present invention has revealed that an adverse effect on the vehicle exerted by electric charge that is charged to the vehicle is not limited to the increase in the risk of generation of radio noise. In other words, when the electric charge is charged to the vehicle, the electric charge is also charged to the oil in the shock absorbers. As a result, the viscosity of the oil is increased so that damping forces are liable to become excessive. The related-art electrostatic eliminator as disclosed in Japanese Patent Application Laid-open No. 2009-181694 is restricted in terms of an installation location, and cannot thus be installed at a location for effectively reducing the electric charge that is charged to the oil in the shock absorbers. Therefore, the excessive damping force resulting from the increase in the viscosity of the oil caused by the charging of the electric charge cannot be effectively prevented by the related-art electrostatic eliminator.

Invention Disclosure:
A damping force generation device for a vehicle includes a shock absorber including a cylinder and a piston. The shock absorber is coupled to a vehicle body, a wheel carrier, and the like at a rod part of the piston and the cylinder, respectively, and is configured to generate a damping force due to a flow resistance when oil passes through an orifice formed in the piston. Each of self-discharge type charge eliminators is fixed to a surface of a specific member being at least one of a component of the shock absorber or an auxiliary member connected to the component. The charge eliminator reduces positive electric charge that is charged to the specific member, to thereby reduce a charge amount of the oil.

[Assistant]
1. A damping force generation device for a vehicle, comprising:
a shock absorber comprising:
a cylinder; and
a piston fitted into the cylinder in a reciprocally movable manner to form two cylinder chambers in cooperation with the cylinder,
the shock absorber being coupleable to one of a sprung member and an unsprung member of the vehicle at a rod part of the piston, and to another one of the sprung member and the unsprung member at the cylinder,
the shock absorber being configured to generate a damping force due to a flow resistance when a working liquid passes through an orifice formed in a main body part of the piston to move between the two cylinder chambers along with relative displacement between the sprung member and the unsprung member; and
a self-discharge type charge eliminator provided on a surface of a specific member comprising at least one of a member constructing the shock absorber or an auxiliary member connected to the shock absorber,
the self-discharge type charge eliminator comprising an air-ion conversion self-discharge type charge eliminator configured to reduce a charge amount of positive electric charge, which is charged to the specific member, through diselectrification carried out by changing air around the air-ion conversion self-discharge type charge eliminator into negative air ions depending on the charge amount of the specific member, and by causing the negative air ions to be attracted to the positive electric charge of the specific member to neutralize the positive electric charge, to thereby reduce a charge amount of the working liquid.

2. A damping force generation device for a vehicle according to claim 1, wherein:
the specific member is a dust boot made of a resin as the auxiliary member connected to the rod part;
the self-discharge type charge eliminator is provided on a surface of the dust boot; and
the rod part and the dust boot are connected to each other so that the positive electric charge is movable from the rod part to the dust boot.

3. A damping force generation device for a vehicle according to claim 1, wherein:
the shock absorber is a twin-tube shock absorber comprising:
an inner cylinder to which the piston is fitted; and
an outer cylinder surrounding the inner cylinder;
the specific member is the outer cylinder; and
the self-discharge type charge eliminator is provided on a surface of the outer cylinder below a liquid level of the working liquid between the inner cylinder and the outer cylinder when the vehicle is in a standard load state.

4. A damping force generation device for a vehicle according to claim 1, wherein:
the shock absorber is a twin-tube shock absorber comprising:
an inner cylinder to which the piston is fitted;
an outer cylinder surrounding the inner cylinder to form a reservoir chamber between the inner cylinder and the outer cylinder;
a base valve assembly; and
an end cap closing end portions of the inner cylinder and the outer cylinder to define a base valve chamber communicating with the reservoir chamber in cooperation with the base valve assembly;
the specific member is at least one of the outer cylinder or the end cap; and
the positive electric charge is movable from the inner cylinder to the specific member.

5. A damping force generation device for a vehicle according to claim 1, wherein:
the shock absorber is a mono-tube shock absorber;
the specific member is the cylinder; and
the self-discharge type charge eliminator is provided on a surface of the cylinder so that at least a part of the self-discharge type charge eliminator is positioned within a predetermined range corresponding to a range in a direction of the relative displacement, in which the main body part of the piston exists when the vehicle is in a standard load state.

6. A damping force generation device for a vehicle according to claim 1, wherein:
the shock absorber is a variable damping force shock absorber comprising:
a bypass passage for bypassing the main body part of the piston to connect the two cylinder chambers to each other;
a variable orifice formed in the bypass passage; and
an effective passage cross sectional area changing device configured to change an effective passage cross sectional area of the variable orifice,
the variable damping force shock absorber being configured such that, when the piston is displaced with respect to the cylinder, at least a part of the working liquid in one of the two cylinder chambers moves to another one of the two cylinder chambers through the bypass passage;
the specific member is the effective passage cross sectional area changing device; and
the positive electric charge is movable from the working liquid passing through the bypass passage to the effective passage cross sectional area changing device.

7. A damping force generation device for a vehicle according to claim 1, wherein:
the self-discharge type charge eliminator comprises:
a conductive metal foil having a large number of minute protrusions and recesses formed on a side surface on an outer periphery of the conductive metal foil; and
a layer of an adhesive applied to one surface of the conductive metal foil; and
the self-discharge type charge eliminator is fixed to the specific member by bonding with the layer of the adhesive.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Apparatus For Compensating For Temperature And Method Therefor

Technical Field and Background:
1. Field of the Disclosure The present disclosure relates generally to a temperature compensation apparatus and method and, more particularly, to a temperature compensation apparatus and method for supplying a bias to a power detector. 2. Description of the Related Art A Radio Frequency Integrated Circuit (RFIC) transceiver is widely used in modern wireless communication. The transceiver generally comprises a receiver (RX) path and a transmitter (TX) path. The RX path can down-convert a reception signal into a baseband signal, and the TX path modulates a signal and up-convert a baseband signal into a high frequency band signal (e.g. an RF signal). In the transceiver, the power detector detects transmission power from an output of the TX, and a modem controls a TX switch based on the information of the power detector, in order to optimize power consumption of a mobile terminal or improve the linearity of a Power Amplifier (PA). The power detector requires robustness against temperature variation for accurately detecting power. The performance of the power detector changes as temperature changes, but can be compensated for by a design of a suitable bias circuit, such as a Proportional To an Absolute Temperature (PTAT) circuit or a Band Gap Reference (BGR) circuit. The BGR circuit supplies a constant current (hereinafter, “BGR current”), which is constant regardless of a change in manufacturing processes or neighboring temperature, and the PTAT circuit supplies a current (hereinafter, “PTAT current”), which is linearly proportional to an absolute temperature. The PTAT circuit provides a bias current to a power amplifier together with the BGR circuit. The BGR circuit and the PTAT circuit offset temperature dependency, and compensate for an output voltage of a transconductance-dependent block through temperature variation. The output voltage of the power detector should be compensated for temperature variation to provide a modem with accurate transmission output power information regardless of the temperature variation. The PTAT circuit can compensate for a change of an analog circuit within the power detector by providing a compensated bias current. The conventional bias circuit only uses the BGR and PTAT circuits, and has approximately 15% of fixed and limited slope rate regarding temperature variation. FIG. 1 illustrates a PTAT current value according to temperature variation, according to the related art. In the graph of FIG. 1 , the x-axis indicates temperature, and the y-axis indicates a PTAT current value. Referring to FIG. 1 , when temperature changes from −30 degrees Celsius to 90 degrees Celsius, FIG. 1 illustrates that the PTAT current changes approximately from 10 [μA] to 14 [μA]. A slope of a PTAT current is approximately 15%, and indicates a rate of change in current according to temperature. However, the power detector may require a slope in which a rate of change in current according to temperature is greater than or equal to 45% for compensating for a change in gain and providing performance of the power detector which is insensitive to temperature. The performance of the power detector requires optimization throughout other operation bandwidths through a slope control ability of the current PTAT circuit. Accordingly, there is a need in the art for additional bias circuits to better control current, and a current slope for increasing compensation for performance degradation of the power detector due to temperature.

Invention Disclosure:
Disclosed are a temperature compensation apparatus and method. The apparatus includes a reference signal generator that supplies at least one of a first current which is constant regardless of temperature variation and a second current which is proportional to temperature variation, a slope amplifier that determines a first output current having a second temperature coefficient which is a multiple of a first temperature coefficient of the second current, based on the first current and the second current, and a slope controller that determines a second output current having a third temperature coefficient, using a weighted average of the first current and the second current.

[Assistant]
1. An apparatus for compensating for a temperature, the apparatus comprising:
a reference signal generator configured to supply a first current which is constant regardless of a temperature variation and a second current which is proportional to temperature variation;
a slope amplifier configured to determine a first output current based on a difference between a multiple of the first current and a multiple of the second current;
a slope controller comprising at least one transistor, the slope controller configured to determine a second output current using a weighted average of the first current and the second current, wherein a weight value for the weighted average being related to a characteristic of the at least one transistor; and
a bias distributor configured to supply a bias current to at least one other apparatus using at least one of the first output current and the second output current,
wherein a first temperature coefficient of the bias current is greater than a second temperature coefficient of the second current, and
wherein the first temperature coefficient and the second temperature coefficient is a rate of a temperature change with respect to the temperature variation.

2. The apparatus of claim 1, wherein the slope amplifier comprises at least one temperature coefficient double (TCDBL) configured to generate the first output current to be equal to (n×the second current)−((n−1)×the first current), where n is a number.

3. The apparatus of claim 2, wherein the slope amplifier further comprises a current mirror configured to copy the first output current.

4. The apparatus of claim 1, wherein the slope controller is further configured to increase the first current by a parameter α, which denotes the weight value, and increase the second current by 1−α, and adds the first current to the second current.

5. The apparatus of claim 1, wherein the slope controller comprises:
a first current mirror configured to mirror the first current which has been increased by a parameter α, which denotes the weight value:
a second current mirror configured to mirror the second current which has been increased by 1−α; and
a third current mirror configured to mirror a current obtained by adding the first current which has been increased by α to the second current which has been increased by 1−α.

6. The apparatus of claim 1, wherein the bias distributor comprises:
a first input unit configured to mirror a first input current; and
a first output unit configured to mirror the first output current and generate at least one third output current.

7. The apparatus of claim 1, wherein the bias distributer comprises:
a second input unit configured to mirror a second input current; and
a second output unit configured to mirror the second output current and generate at least one fourth output current.

8. The apparatus of claim 1, wherein the reference signal generator comprises:
a band gap reference (BGR) configured to generate the first current; and
a proportional to an absolute temperature (PTAT) circuit configured to generate the second current.

9. A method for compensating for a temperature in a device, the method comprising:
supplying a first current which is constant regardless of a temperature variation and a second current which is proportional to the temperature variation;
determining a first output current based on a difference between a multiple of the first current and a multiple of the second current;
determining a second output current using a weighted average of the first current and the second current, wherein a weight value for the weighted average being related to a characteristic of at least one transistor of the device; and
supplying a bias current to at least one other device using at least one of the first output current and the second output current,
wherein a first temperature coefficient of the bias current is greater than a second temperature coefficient of the second current, and
wherein the first temperature coefficient and the second temperature coefficient is a rate of a temperature change with respect to the temperature variation.

10. The method of claim 9, wherein determining the first output current comprises:
generating the first output current to be equal to (n×the second current)−((n−1)×the first current), where n is a number.

11. The method of claim 9, wherein determining the second output current comprises:
increasing the first current by a parameter α, which denotes the weight value; and
increasing the second current by 1−α, and adding the first current to the second current.

12. The method of claim 9, wherein supplying the bias current comprises:
mirroring the first output current; and
generating at least one third output current.

13. The method of claim 9, wherein supplying the bias current comprises:
mirroring the second output current; and
generating at least one fourth output current.

14. A method by a temperature compensation apparatus, the method comprising:
generating a first current which is constant regardless of a temperature variation and a second current which is proportional to the temperature variation;
determining a first output current based on a difference between a multiple of the first current and a multiple of the second current;
determining a second output current using a weighted average of the first current and the second current, wherein a weight value for the weighted average is related to a characteristic of at least one transistor of the temperature compensation apparatus; and
supplying a bias current to at least one other apparatus using at least one of the first output current and the second output current,
wherein a first temperature coefficient of the bias current is greater than a second temperature coefficient of the second current, and
wherein the first temperature coefficient and the second temperature coefficient is a rate of a temperature change with respect to the temperature variation.

15. The method of claim 14, wherein the first output current is equal to ((2×the second current)−the first current).

16. The method of claim 14, wherein the weighted average is determined by a sum of the first current multiplied by the weight value and the second reference signal multiplied by one minus the weight value.

17. The method of claim 14, further comprising:
supplying the bias current to the at least one other apparatus by distributing the first output current or the second output current to the at least one other apparatus, or by distributing a third output current obtained by multiplying the first output current and the second output current by parameters, to the at least one other apparatus.

18. The apparatus of claim 1, wherein the bias current is provided to the at least one other apparatus so that an output voltage of the at least one other apparatus is maintained regardless of the temperature variation.

19. The method of claim 9, wherein the bias current is provided to the at least one other device so that an output voltage of the at least one other device is maintained regardless of the temperature variation.

20. The method of claim 14, wherein the bias current is provided to the at least one other apparatus so that an output voltage of the at least one other apparatus is maintained regardless of the temperature variation.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Optimizing Operation Of Constrained User Equipment

Technical Field and Background:
As designs for wireless mobile devices (e.g., user equipment (UE)) evolve, there is a trend toward smaller devices and more streamlined housings. Some examples of these smaller devices or more streamlined designs include wearable devices such as watches that are worn on the wrist or glasses that are worn in the manner of traditional eyewear. Another example is pendants that may be attached to a strap and hung around a user's neck or wrist. A final example is a clip-on that may be clipped onto an article of clothing such as pockets or clipped onto an accessory such as a bag or purse. These smaller and streamlined designs generally result in less available space for components of the wireless mobile devices. For example, the batteries of such devices need to be smaller and therefore have a correspondingly smaller capacity. In another example, the designs generally require that all antennas be internal antennas so as not to change the form of the mobile device. This may result in shorter antennas because of the lack of availability of space within the housing of the mobile device. These constraints on the design of the wireless devices may result in a loss of performance for certain wireless functionalities. However, users expect these devices to operate and have similar performance characteristics as the standard wireless mobile devices to which the users are accustomed. Thus, if these smaller mobile devices have a loss of performance, the user experience will be degraded and users are less likely to adopt these new types of devices.

Invention Disclosure:
A base station and associated method transmits a page to a user equipment (UE) for a call establishment procedure, determines whether an acknowledgement is received in response to the page and when no acknowledgement has been received, determines a number of pages that have been transmitted to the UE for the call establishment procedure, transmits a further page to the UE for the call establishment procedure when the number of pages is less than a page threshold and performs a page failure procedure when the number of pages exceeds the page threshold. In another method the base station transmits a radio resource control (RRC) connection release message to the UE, maintains a context for the UE when an acknowledgement for the RRC connection release message is not received, transmits a first page and transmits a second page when a further acknowledgement for the first page is not received.

[Assistant]
1. A method, comprising:
at a network component of a network configured to establish a connection with a user equipment:
transmitting a page to the user equipment for a call establishment procedure;
determining whether an acknowledgement is received from the user equipment in response to the page; and
when the acknowledgement has been received from the user equipment in response to the page,
performing the call establishment procedure;
determining whether the call establishment procedure failed;
determining a number of times the call establishment procedure has failed when it is determined the call establishment procedure has failed; and
further performing the call establishment procedure without determining a page failure when the number of times is less than a call establishment threshold.

2. The method of claim 1, further comprising:
transmitting another page to the user equipment for the call establishment procedure when the number of times exceeds the call establishment threshold.

3. The method of claim 1, further comprising:
determining whether a timer for the call establishment procedure has expired; and
transmitting another page to the user equipment for the call establishment procedure when the timer for the call establishment procedure has expired.

4. The method of claim 1, further comprising:
completing the call establishment procedure to initiate a voice call with the user equipment,
determining that the voice call has failed; and
transmitting another page to the user equipment for the call establishment procedure.

5. A base station, comprising:
a transceiver;
a non-transitory memory having a program stored thereon; and
a processor executing the program, wherein the execution of the program causes the processor to perform operations comprising:
transmitting a page to the user equipment for a call establishment procedure;
determining whether an acknowledgement is received from the user equipment in response to the page; and
when the acknowledgement has been received from the user equipment in response to the page,
performing the call establishment procedure;
determining whether the call establishment procedure failed;
determining a number of times the call establishment procedure has failed when it is determined the call establishment procedure has failed; and
further performing the call establishment procedure without determining a page failure when the number of times is less than a call establishment threshold.

6. The base station of claim 5, wherein the operations further comprise:
transmitting another page to the user equipment for the call establishment procedure when the number of times exceeds the call establishment threshold.

7. The base station of claim 5, wherein the operations further comprise:
determining whether a timer for the call establishment procedure has expired; and
transmitting another page to the user equipment for the call establishment procedure when the timer for the call establishment procedure has expired.

8. The base station of claim 5, wherein the operations further comprise:
completing the call establishment procedure to initiate a voice call with the user equipment;
determining that the voice call has failed; and
transmitting another page to the user equipment for the call establishment procedure.

9. A method, comprising:
at a network component of a network configured to establish a connection with a user equipment:
transmitting a radio resource control (RRC) connection release message to the user equipment;
maintaining a context for the user equipment when an acknowledgement for the RRC connection release message is not received;
transmitting a first page; and
transmitting a second page when a further acknowledgement for the first page is not received.

10. The method of claim 9, wherein the first page includes a paging Radio Network Temporary Identifier (P-RNTI) as if the user equipment is in an RRC idle mode.

11. The method of claim 9, wherein the second page includes a cell Radio Network Temporary Identifier (C-RNTI) as if the user equipment is in an RRC connected mode.

12. The method of claim 9, further comprising:
determining whether an acknowledgement is received in response to the second page; and
determining whether a number of first and second page transmissions exceeds a threshold attempt value when the acknowledgment to the second page is not received.

13. The method of claim 12, further comprising:
when the number of first and second page transmissions does not exceeds the threshold attempt value;
maintain the context for the user equipment.

14. A base station, comprising:
a transceiver;
a non-transitory memory having a program stored thereon; and
a processor executing the program, wherein the execution of the program causes the processor to perform operations comprising:
transmitting a radio resource control (RRC) connection release message to a user equipment;
maintaining a context for the user equipment when an acknowledgement for the RRC connection release message is not received;
transmitting a first page; and
transmitting a second page when a further acknowledgement for the first page is not received.

15. The base station of claim 14, wherein the first page includes a paging Radio Network Temporary Identifier (P-RNTI) as if the user equipment is in an RRC idle mode.

16. The base station of claim 14, wherein the second page includes a cell Radio Network Temporary Identifier (C-RNTI) as if the user equipment is in an RRC connected mode.

17. The base station of claim 14, wherein the operations further comprise:
determining whether an acknowledgement is received in response to the second page; and
determining whether a number of first and second page transmissions exceeds a threshold attempt value when the acknowledgment to the second page is not received.

18. The base station of claim 17, wherein the operations further comprise:
when the number of first and second page transmissions does not exceeds the threshold attempt value;
maintain the context for the user equipment.

19. The method of claim 1, further comprising:
when no acknowledgement has been received in response to the page,
determining a number of pages that have been transmitted to the user equipment for the call establishment procedure;
transmitting a further page to the user equipment for the call establishment procedure when the number of pages is less than a page threshold; and
performing a page failure procedure when the number of pages exceeds the page threshold.

20. The base station of claim 5, wherein the operations further comprise:
when no acknowledgement has been received in response to the page,
determining a number of pages that have been transmitted to the user equipment for the call establishment procedure;
transmitting a further page to the user equipment for the call establishment procedure when the number of pages is less than a page threshold; and
performing a page failure procedure when the number of pages exceeds the page threshold.