[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Grease Gun Cartridge Construction

Technical Field and Background:
The present invention resides in the structure of a grease gun cartridge adapted for use on a grease gun having any of a wide variety of grease gun pump constructions, typical of which pump constructions are shown in the drawings herein and in U.S. Pat. Nos. 3,338,478; 3,344,084; 2,978,151; 1,368,840; 1,349,994; and 4,601,412, the disclosures of which are hereby incorporated herein by reference in their entireties. The typical mechanism in the gun head for operating these prior grease gun pumps consists of a grease loading and ejection cylinder in which a piston is slidably mounted for reciprocation between a grease loading stroke and a grease pressurizing (ejection) stroke, back and forth across a grease inlet port on the gun head, which port is in communication with the grease loading and ejection cylinder in the head. The inlet port is also in communication with a grease reservoir (cartridge) positioned in a metal barrel which is affixed to the gun head. In these mechanisms the grease in the loading operation is pressurized by a cartridge piston, a cartridge piston cocking rod, and a compression spring means having one end bearing against the lower inner end of the barrel (not shown) and having its other end bearing against the lower end of the piston within the filled cartridge and pressurizing the grease column within the cartridge toward and through the inlet port and into the grease loading cylinder. The piston in the gun head closes off the inlet port on its pressurizing (ejection) stroke and forces the grease, which was forced into the loading and ejection cylinder through the inlet port on the piston suction stroke by means of the cartridge spring, out of the gun head on the ejection (pressurizing stroke) and through a hose to a ZERK or equivalent fitting. One-way valving opens the loading and ejection cylinder to the hose on the piston ejection stroke and closes off the cylinder to the hose on the ejection piston suction stroke. Hand operated lever means or dual handle means operates the back and forth reciprocating action of the piston.

Invention Disclosure:
A grease gun cylinder walled cartridge adapted for direct attachment to any of a variety of grease gun head constructions and grease pumping systems, wherein the cartridge wall can be of any color or completely clear and see through, wherein the grease column within the cartridge is pressured toward and through an inlet port in the gun head, which port opens on the section stroke of a piston mounted in said cylinder into a loading portion of a cylinder of the grease pumping system, and wherein the grease column pressuring means is ambient air pressure.

[Assistant]
1. A grease cartridge construction comprising a cylindrical tubular cartridge wall having:
a top end portion which is closed off by a removable closure means and a closed bottom end portion and forming a grease reservoir chamber;
thread means on an outer surface of the cylindrical tubular cartridge wall adjacent to said top end and adapted to be screwed into a threaded mounting socket of a grease gun head;
a first removable closure means closing said top end of said wall;
a column of grease in said chamber and having a lower end surface and an upper end surface, said lower end surface of said column being spaced above said closed bottom end of said wall to provide an ambient air chamber;
a pumping means comprising a flexible, resilient bulb mounted on said bottom end portion of said cartridge wall, wherein an air inlet of said pumping means is in communication with the ambient atmosphere, and wherein an air outlet of said pumping means is in communication with said ambient air chamber, wherein said bulb is affixed to said bottom end portion of said cartridge wall which comprises a housing member containing said bulb, wherein the housing member itself is formed with a cylindrical side wall adapted to be tightly slid into a lower end portion of said cartridge wall; and
an air vent structure in said bottom end portion of said wall which lies below said lower end surface of said column for allowing a controlled flow of ambient air into said ambient air chamber to form a positive pressure in said chamber relative to a suction pressure which would exist in a grease gun on its suction stroke.

2. The cartridge construction of claim 1 wherein said cartridge wall is comprised of formed plastic material and wherein a wiper disc is in place against the proximal end of said column of grease.

3. The cartridge construction of claim 2 wherein said air vent structure comprises an aperture formed through said bottom end portion of said cartridge wall.

4. The cartridge construction of claim 3 wherein said aperture is an air passage through a one way valve.

5. The cartridge construction of claim 1 wherein said pumping means further comprises a one-way air valve structure having a body portion affixed to a distal end of said housing member, and wherein said air outlet of said bulb is in communication with said one-way air valve structure.

6. The cartridge construction of claim 5 wherein said valve structure comprises an air passage formed through said body portion, which passage is normally closed by a pair of opposing resilient lips which form a slit which opens under air pressure generated by squeezing said bulb.

7. A grease gun having:
a head section containing a grease pumping cylinder and piston mounted therein;
a grease inlet port in said head section communicating with said cylinder;
a grease outlet port in said head section communicating with a hose member affixed to said head;
a grease cartridge affixed to said head section and comprising a cylindrical tubular cartridge wall having an open top end portion and a closed bottom end portion and forming a grease reservoir chamber;
thread means on the outer surface of said wall adjacent to said top end and being screwed into a threaded mounting socket of said grease gun head section, whereby said inlet port is in communication with said chamber;
a second closure means closing said bottom end of said wall;
a column of grease in said chamber and having a lower end surface and an upper end surface, said lower end surface of said column being spaced above said closed bottom end of said cartridge wall to provide an ambient air chamber;
an air pumping means comprising a flexible, resilient bulb mounted on said bottom end portion of said cartridge wall, wherein an air inlet of said pumping means is in communication with the ambient atmosphere, and wherein an air outlet of said pumping means is in communication with said ambient air chamber, wherein said bulb is affixed to said bottom end portion of said cartridge wall which comprises a separate housing member, wherein the housing member itself is formed with a cylindrical side wall adapted to be tightly slid into a lower end portion of said cartridge wall;
an air vent structure in said bottom end portion of said wall which lies below said lower end surface of said column for allowing a controlled flow of ambient air into said ambient air chamber to form a positive pressure in said chamber relative to a suction pressure which would exist in said grease gun on its suction stroke.

8. The grease gun of claim 7 wherein said cartridge wall is comprise of formed plastic material a wiper disc is in place against the proximal end of said column of grease.

9. The cartridge construction of claim 8 wherein said air vent structure comprises an aperture formed through said bottom end portion of said cartridge wall.

10. The cartridge construction of claim 9 wherein said aperture is an air passage through a one way air valve.

11. The cartridge construction of claim 7, wherein said pumping means further comprises a one-way air valve structure having a body portion affixed to a distal side of said housing member, and wherein said air outlet of said bulb is in communication with said one-way air valve structure.

12. The cartridge construction of claim 11 wherein said valve structure comprises an air passage formed through said body portion, which passage is normally closed by a pair of opposing resilient lips which form a slit which opens under air pressure generated by sequeezing said bulb.

13. The cartridge construction of claim 12 wherein said air passage enters said body portion along a longitudinal axis of said body portion and along a coextensive longitudinal axis of said cartridge and exits said body portion at a substantially right angle to said longitudinal axes.

14. The cartridge construction of claim 6 wherein said side wall of said housing member is provided with an annular seal adapted to form a grease seal against the inner surface of said cartridge wall, and wherein said side wall of said housing member is provided with a plurality of flexible metal barbs which are affixed to the exterior surface of said side wall and extend outwardly therefrom at an acute angle toward said bottom end of said cartridge.

15. The cartridge construction of claim 14 wherein said barbs are portion of an annular rim which is nested in an annular groove in said side wall of said housing member.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Optoelectronic Filter

Technical Field and Background:
As is known in the art, noise degrades the spectral purity of oscillators, such as those commonly found radar systems, communication systems (e.g., including but not limited to cellular communication systems), metrology systems and the like. Due to feedback mechanics of oscillators and to inherent resistance of a saturated oscillator to amplitude fluctuations, noise (e.g., phase noise) can become a significant limitation (and in some cases a dominant limitation) to oscillator performance. Phase noise can, for example, result in spectral broadening of the oscillation line profile of an oscillator across a distribution of frequencies. For many systems (e.g., receiver systems in a communication system), the phase noise of a relatively strong signal (e.g., background noise) can obstruct the detection of comparatively weaker signals (e.g., signals of interest) at nearby frequencies. In essence, the weaker signal is buried beneath the phase noise of the stronger signal. Ideally, a system is capable of filtering out the stronger signal leaving behind the desired, weaker signal. However, such a filtering operation cannot typically be accomplished using conventional all-electronic filters for at least two reasons. First, the bandwidth of the pass band in such a conventional filter is insufficiently narrow to separate one signal from another (e.g., the stronger signal from the weaker signals). Second, even with an appropriate bandwidth, such conventional filters are unable to distinguish the weaker signals from phase noise.

Invention Disclosure:
An optoelectronic filter having at least one input and an output includes a modulator circuit having at least first and second inputs with a first one of the modulator circuit inputs adapted to couple to a respective one of the at least one input of the optoelectronic filter. The modulator circuit receives at least a first radio frequency (RF) signal having a first power level and a second RF signal having a second, different power level at the first one of the modulator circuit inputs and in response thereto generates a modulated signal at an output thereof. The first RF signal is suppressed relative to the second RF signal in the modulated signal. The optoelectronic filter additionally includes a light source adapted to couple to a second one of the modulator circuit inputs. A corresponding method is also provided.

[Assistant]
1. An optoelectronic filter for suppressing at least a first radio frequency (RF) signal relative to a second RF signal, the first RF signal having a first power level and the second RF signal having a second, different power level than the first RF signal, the optoelectronic filter having at least one input configured to receive the first and second RF signals and an output, and the optoelectronic filter comprising:
a signal level control circuit having an input coupled to the at least one optoelectronic filter input, said signal level control circuit configured to: receive the first and second RF signals at the input thereof, adjust a power level of the first RF signal and/or the power level of the second RF signal, and in response thereto provide a level-adjusted signal at an output thereof;
a modulator circuit having at least first and second inputs with a first one of the modulator circuit inputs coupled to the signal level control circuit output, said modulator circuit configured to receive the level-adjusted signal at the first one of the modulator circuit inputs and in response thereto generate a modulated signal at an output thereof; and
a light source coupled to a second one of the modulator circuit inputs, said light source configured to provide a beam having an optical intensity to the second one of the modulator circuit inputs,
wherein the signal level control circuit adjusts the power level of the first RF signal and/or the power level of the second RF signal such that the first RF signal transitions from constructive to destructive interference in said modulator circuit, wherein the first RF signal is suppressed relative to the second RF signal in the modulated signal.

2. The optoelectronic filter of claim 1 wherein an optical intensity of the beam is selected to provide gain to the modulated signal.

3. The optoelectronic filter of claim 1 wherein said modulator circuit is configured to generate the modulated signal upon detection of an optical envelope of the level-adjusted signal and propagation of the beam through said modulator circuit.

4. The optoelectronic filter of claim 1 wherein the signal level control circuit adjusts the power level of the first RF signal and/or the power level of the second RF signal using a respective plurality of attenuation or gain factors.

5. The optoelectronic filter of claim 1 wherein the signal level control circuit also an input coupled to the modulator circuit output, said signal level control circuit configured to: receive the modulated signal at the input thereof, attenuate one or more respective portions of the modulated signal representative of the first power level of the first RF signal and/or the power level of the second RF signal such that the first RF signal is further suppressed relative to the second RF signal, and in response thereto provide an attenuated signal at an output thereof.

6. The optoelectronic filter of claim 1 further comprising:
a detector circuit having an input coupled to the modulator circuit output, said detector circuit configured to receive the modulated signal at the input thereof and to provide a detected signal at an output thereof.

7. The optoelectronic filter of claim 1 wherein phase noise of the first RF signal is substantially suppressed from the modulated signal.

8. The optoelectronic filter of claim 1 wherein a ratio of the power level of the first RF signal to a voltage level required to transition the first RF signal from constructive to destructive interference in said modulator circuit is given by πv 1 /V π, where v 1 is the power level of the first RF signal and V π is the voltage level.

9. The optoelectronic filter of claim 8 wherein the ratio produces an interference pattern having a generally sinusoidal shape.

10. The optoelectronic filter of claim 8 wherein when the ratio is in the range of about 3.7 to about 3.9, the first RF signal is substantially suppressed and the second RF signal is proximate a local maximum.

11. The optoelectronic filter of claim 8 wherein when the ratio is about 3.83 the transmission characteristic of the first RF signal from the respective input of the optoelectronic filter to a respective output of the optoelectronic filter is about zero and the transmission characteristic of the second RF signal from the respective input of the optoelectronic filter to the respective output of the optoelectronic filter is proximate a local maximum.

12. The optoelectronic filter of claim 1 wherein the modulator circuit is a Mach-Zehnder modulator.

13. The optoelectronic filter of claim 1 wherein the light source comprises a light emitting diode (LED), and/or a laser diode.

14. A method of filtering received signals in an optoelectronic filter, the method comprising:
receiving first and second radio frequency (RF) signals at an input of the optoelectronic filter, wherein the first RF signal is provided having a first power level and the second RF signal is provided having a second, lower power level;
adjusting the power level of the first RF signal and/or the power level of the second RF signal to produce a level adjusted signal; and
generating a modulated signal from the level adjusted signal at an output of a modulator circuit, wherein the power level of the first RF signal and/or the power level of the second RF signal is adjusted such that the first RF signal transitions from constructive to destructive interference in the modulator circuit, and wherein the first RF signal is suppressed relative to the second RF signal in the modulated signal.

15. In a communication system, a receiver coupled to receive first and second radio frequency (RF) signals from one or more remote locations, wherein the first RF signal is provided having a first power level and the second RF signal is provided having a second, different power level, said receiver comprising:
an optoelectronic filter having at least one input configured to receive the first and second RF signals and an output, the optoelectronic filter comprising:
a signal level control circuit having an input coupled to the at least one optoelectronic filter input, said signal level control circuit configured to: receive the first and second RF signals at the input thereof, adjust a power level of the first RF signal and/or a power level of the second RF signal, and in response thereto provide a level-adjusted signal at an output thereof;
a modulator circuit having at least first and second inputs with a first one of the modulator circuit inputs coupled to the signal level control circuit output, said modulator circuit configured to receive the level-adjusted signal at the first one of the modulator circuit inputs and in response thereto generate a modulated signal at an output thereof; and
a light source coupled to a second one of the modulator circuit inputs, said light source configured to provide a beam having an optical intensity to the second one of the modulator circuit inputs,
wherein the signal level control circuit adjusts the power level of the first RF signal and/or a power level of the second RF signal such that the first RF signal transitions from constructive to destructive interference in said modulator circuit, wherein the first RF signal is suppressed relative to the second RF signal in the modulated signal.

16. The receiver of claim 15 wherein the optical intensity of the beam is selected to provide gain to the modulated signal.

17. The receiver circuit of claim 15 wherein said modulator circuit of the optoelectronic filter is configured to generate the modulated signal upon detection of an optical envelope of the level-adjusted signal and propagation of the beam through said modulator circuit.

18. The receiver of claim 15 wherein the signal level control circuit adjusts the power level of the first RF signal and/or the power level of the second RF signal using a respective plurality of attenuation or gain factors.

19. The receiver of claim 15 wherein the signal level control circuit also has an input coupled to the modulator circuit output, said signal level control circuit configured to: receive the modulated signal at the input thereof and adjust signal levels of one or more respective portions of the modulated signal representative of the power level of the first RF signal and/or the power level of the second RF signal.

20. The receiver of claim 15 wherein the optoelectronic filter further comprises:
a detector circuit having an input coupled to the modulator circuit output, said detector circuit configured to receive the modulated signal at the input thereof and to provide a detected signal at an output thereof.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Antenna Formed From Plates And Methods Useful In Conjunction Therewith

Technical Field and Background:
State of the art antenna technology includes that described in the following patent documents: US 20130120205; US 20130321229; U.S. Pat. No. 4,743,915; U.S. Pat. No. 4,783,663; U.S. Pat. No. 5,243,357; U.S. Pat. No. 5,568,160; U.S. Pat. No. 6,034,647; U.S. Pat. No. 6,563,398; U.S. Pat. No. 6,897,824; U.S. Pat. No. 7,564,421; U.S. Pat. No. 8,558,746; WO2013089456A1; and U.S. Pat. No. 4,743,915 to Rammos (Philips). The disclosures of all publications and patent documents mentioned in the specification, and of the publications and patent documents cited therein directly or indirectly, are hereby incorporated by reference. Materiality of such publications and patent documents to patentability is not conceded.

Invention Disclosure:
An antenna array configuration is provided with h-plane splitters between ends of a feeding network and radiating elements e.g. horns, thereby to reduce the distance between the centers of the horns to less than one wavelength which results in a better side lobe level. A method of manufacturing upper and lower plates together constituting an antenna is also provided, typically making each plate in a single operation, by dividing the feeding network's waveguides at the centre where there are no cross currents so as not to disturb propagation in the feeding network. The radiating elements, h-plane splitters and upper half of the feeding network may be fabricated in one plate without undercuts hence simplifying manufacture of the plate which may for example be formed using a simple molding machine or a 3 axis-CNC machine.

[Assistant]
1. Antenna apparatus for transmitting/receiving electromagnetic radiation defining a wavelength, the apparatus comprising:
at least one lower machined plate; and
at least one upper machined plate including:
a radiating element layer including an array of radiating elements each having a center, wherein the distance between the centers of adjacent elements in said array is less than one wavelength; and
an H-plane splitter layer below said radiating element layer and including H-plane splitters each having an H-plane splitter input facing said lower plate and a pair of H-plane splitter outputs which respectively connect the H-plane splitter to a pair of said radiating elements, and
an E-orientation feeding network layer having an input and comprising:
E-plane splitters receiving the wave from the feeding network input and defining multiple feeding network outputs, wherein an individual H-plane splitter input connects individual ones of said H-plane splitters to respective outputs from among said multiple feeding network outputs, thereby to enable the H-plane splitters to split the electromagnetic radiation travelling from the feeding network input to the radiating elements, and wherein each E-plane splitter is formed of first and second halves which are included in the upper and lower plates respectively; and
hollow waveguide sections interconnecting the E-plane splitters, and including first and second halves which are disposed on respective sides of a bisecting plane parallel to the waveguide's shorter cross-sectional dimension and which are included in the lower and upper plates respectively.

2. Antenna apparatus according to claim 1 wherein the radiating element layer, H-plane splitter layer and E-orientation feeding network layer are formed from only two machined plates.

3. Antenna apparatus according to claim 1 wherein the radiating element layer, H-plane splitter layer and E-orientation feeding network layer are formed by injection molding two machined plates.

4. Antenna apparatus according to claim 3 wherein the radiating element layer, H-plane splitter layer and E-orientation feeding network layer are formed by injection molding only two machined plates.

5. Antenna apparatus according to claim 1 wherein the E-plane splitters are arranged to form a parallel feeding network defining a binary tree comprising layers of splitters, each splitter in a layer n splitting an output of a splitter in layer (n−1) of said tree.

6. Antenna apparatus according to claim 1 wherein said at least one upper machined plate comprises a middle plate and a top-most plate, and wherein:
said radiating element layer is included in said top-most plate;
first and second portions of said H-plane splitter layer are included in said middle and top-most plates respectively; and
said hollow rectangular waveguide's first and second halves are included in the middle and lower plates respectively; and
each E-plane splitter's first and second halves are included in the middle and lower plates respectively.

7. Antenna apparatus according to claim 1 wherein there is no undercut in the lower plate.

8. Antenna apparatus according to claim 1 wherein at least one of said E-plane splitters has first and second outputs and is designed to split power unequally between said first and second outputs.

9. Antenna apparatus according to claim 1 wherein paths from the feeding network input to each of the outputs are equal in length so phases at all of said multiple feeding network outputs are identical.

10. Antenna apparatus according to claim 9 wherein said network layer comprises a full binary tree.

11. Antenna apparatus according to claim 1 wherein the upper machined plate is bonded to the lower machined plate.

12. Antenna apparatus according to claim 1 wherein there is no undercut in the upper plate.

13. Antenna apparatus according to claim 11 wherein said plates are screwed, rather than being soldered, to one another.

14. Antenna apparatus according to claim 1, wherein a connection point between a last-level E-plane splitter to a feeding network output is offset.

15. A method of manufacturing an antenna for transmitting/receiving electromagnetic radiation defining a wavelength and comprising:
providing a hollow waveguide made from first and second waveguide halves which are disposed on respective sides of a bisecting plane disposed parallel to the waveguide's shorter cross-sectional dimension, wherein said providing includes:
forming the first half of the hollow waveguide from at least one lower machined plate; and
forming the second half of the hollow waveguide from at least one upper machined plate;
wherein the method also comprises:
forming a radiating element layer including an array of radiating elements each having a center, wherein the distance between the centers of adjacent elements in said array is less than one wavelength;
forming an E-orientation feeding network layer comprising:
E-plane splitters operative to receive the electromagnetic wave from the antenna input and defining multiple feeding network outputs, wherein each E-plane splitter is made of first and second halves which are included in the upper and lower plates respectively; and
waveguide sections interconnecting said E-plane splitters; and

16. The method according to claim 15 wherein said forming is performed by a molding machine.

17. The method according to claim 15 wherein said forming is performed by a 3-axis CNC machine.

18. The method according to claim 15 wherein the upper machined plate is bonded to the lower machined plate.

19. The method according to claim 15, comprising offsetting a connection point between a last-level E-plane splitter to a feeding network output.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Display Device

Technical Field and Background:
1. Field of the Invention The present invention relates to a display device which includes a circuit configured using a transistor. The present invention particularly relates to a display device using a light emitting element, an electro-optical element such as a liquid crystal element, or the like as a display medium and to a method for driving the display device. 2. Description of the Related Art In recent years, with the increase of large-scale display devices such as liquid crystal televisions, display devices have been actively developed. In particular, a technique for forming a pixel circuit and a driver circuit including a shift register and the like (hereinafter also referred to as an internal circuit) over the same insulating substrate by using transistors formed of a non-crystalline semiconductor (hereinafter also referred to as amorphous silicon) has been actively developed because the technique greatly contributes to reductions in power consumption and cost. The internal circuit formed over the insulating substrate is connected to a controller IC or the like (hereinafter also referred to as an external circuit) through an FPC or the like, and thus its operation is controlled. Among the aforementioned internal circuits, a shift register using transistors formed of a non-crystalline semiconductor (hereinafter also referred to as amorphous silicon transistors) has been devised. FIG. 106A shows a structure of a flip-flop included in a conventional shift register (Reference 1: Japanese Published Patent Application No. 2004-157508). The flip-flop of FIG. 106A includes a transistor 11 , a transistor 12 , a transistor 13 , a transistor 14 , a transistor 15 , a transistor 16 , and a transistor 17 , and is connected to a signal line 21 , a signal line 22 , a wiring 23 , a signal line 24 , a power supply line 25 , and a power supply line 26 . A start signal, a reset signal, a clock signal, a power supply potential VDD, and a power supply potential VSS are input to the signal line 21 , the signal line 22 , the signal line 24 , the power supply line 25 , and the power supply line 26 , respectively. An operation period of the flip-flop of FIG. 106A is divided into a set period, a selection period, a reset period, and a non-selection period as shown in a timing chart of FIG. 106B , and most of the operation period is a non-selection period. Here, the transistor 12 and the transistor 16 are turned on in a non-selection period. Because amorphous silicon is used for semiconductor layers of the transistor 12 and the transistor 16 , fluctuation in threshold voltage (Vth) is caused due to deterioration or the like. Specifically, a threshold voltage is increased. In other words, a conventional shift register, in which the transistor 12 and the transistor 16 cannot be turned on due to an increase in threshold voltage, cannot supply VSS to a node 41 and the wiring 23 and causes malfunction. In order to solve this problem, shift registers which can suppress a shift in threshold voltage of the transistor 12 have been devised in References 2, 3, and 4 (Reference 2: Soo Young Yoon et al., “Highly Stable Integrated Gate Driver Circuit using a-Si TFT with Dual Pull-down Structure”, SOCIETY FOR INFORMATION DISPLAY 2005 INTERNATIONAL SYMPOSIUM DIGEST OF TECHNICAL PAPERS, Volume XXXVI, pp. 348-351, Reference 3: Bunn Kim et al., “a-Si Gate Driver Integration with Time Shared Data Driving”, Proceedings of The 12 th International Display Workshops in conjunction with Asia Display 2005, pp. 1073-1076, and Reference 4: Mindoo Chun et al., “Integrated Gate Driver Using Highly Stable a-Si TFT's”, Proceedings of The 12 th International Display Workshops in conjunction with Asia Display 2005, pp. 1077-1080). In References 2, 3, and 4, an additional transistor (called a first transistor) is arranged in parallel with the transistor 12 (called a second transistor), and signals inverted with respect to each other are input to gate electrodes of the first transistor and the second transistor in a non-selection period; thus, shifts in threshold voltage of the first transistor and the second transistor are suppressed.

Invention Disclosure:
By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an AC pulse. A shift in threshold voltage of a transistor which easily deteriorates and a shift in threshold voltage of a turned-on transistor are suppressed by signal input to a gate electrode of the transistor which easily deteriorates through the turned-on transistor. In other words, a structure for applying an AC pulse to a gate electrode of a transistor which easily deteriorates through a transistor to a gate electrode of which a high potential (VDD) is applied, is included.

[Assistant]
1. A semiconductor device comprising:
a first flip-flop; and
a second flip-flop,
wherein the first flip-flop comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a first capacitor,
wherein the second flip-flop comprises a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a second capacitor,
wherein a ratio of a channel width to a channel length of the first transistor is greater than a ratio of a channel width to a channel length of the third transistor,
wherein the ratio of the channel width to the channel length of the first transistor is greater than a ratio of a channel width to a channel length of the fifth transistor,
wherein the ratio of the channel width to the channel length of the first transistor is greater than a ratio of a channel width to a channel length of the sixth transistor,
wherein a ratio of a channel width to a channel length of the seventh transistor is greater than a ratio of a channel width to a channel length of the ninth transistor,
wherein the ratio of the channel width to the channel length of the seventh transistor is greater than a ratio of a channel width to a channel length of the eleventh transistor,
wherein the ratio of the channel width to the channel length of the seventh transistor is greater than a ratio of a channel width to a channel length of the twelfth transistor,
wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor,
wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein one of a source and a drain of the fifth transistor is directly connected to one of a source and a drain of the sixth transistor,
wherein a gate of the first transistor is electrically connected to the one of the source and the drain of the fifth transistor,
wherein a gate of the second transistor is directly connected to the one of the source and the drain of the fourth transistor,
wherein the gate of the second transistor is directly connected to a gate of the sixth transistor,
wherein a gate of the fourth transistor is directly connected to a gate of the fifth transistor,
wherein the gate of the fourth transistor is directly connected to the other of the source and the drain of the fifth transistor,
wherein a first electrode of the first capacitor is directly connected to the gate of the first transistor,
wherein a second electrode of the first capacitor is directly connected to the one of the source and the drain of the first transistor,
wherein one of a source and a drain of the seventh transistor is directly connected to one of a source and a drain of the eighth transistor,
wherein one of a source and a drain of the ninth transistor is electrically connected to one of a source and a drain of the tenth transistor,
wherein one of a source and a drain of the eleventh transistor is directly connected to one of a source and a drain of the twelfth transistor,
wherein a gate of the seventh transistor is electrically connected to the one of the source and the drain of the eleventh transistor,
wherein a gate of the eighth transistor is directly connected to the one of the source and the drain of the tenth transistor,
wherein the gate of the eighth transistor is directly connected to a gate of the twelfth transistor,
wherein a gate of the tenth transistor is directly connected to a gate of the eleventh transistor,
wherein the gate of the tenth transistor is directly connected to the other of the source and the drain of the eleventh transistor,
wherein a first electrode of the second capacitor is directly connected to the gate of the seventh transistor,
wherein a second electrode of the second capacitor is directly connected to the one of the source and the drain of the seventh transistor,
wherein the other of the source and the drain of the first transistor is directly connected to a first wiring,
wherein the other of the source and the drain of the third transistor is directly connected to a second wiring,
wherein the other of the source and the drain of the seventh transistor is directly connected to the second wiring,
wherein the other of the source and the drain of the ninth transistor is directly connected to the first wiring, and
wherein the one of the source and the drain of the first transistor is directly connected to the gate of the eleventh transistor.

2. The semiconductor device according to claim 1,
wherein a same voltage is supplied to the other of the source and the drain of the second transistor, the other of the source and the drain of the fourth transistor, the other of the source and the drain of the sixth transistor, the other of the source and the drain of the eighth transistor, the other of the source and the drain of the tenth transistor, and the other of the source and the drain of the twelfth transistor.

3. The semiconductor device according to claim 1,
wherein a first clock signal is input to the first wiring, and
wherein a second clock signal is input to the second wiring.

4. The semiconductor device according to claim 1,
wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor comprise a polycrystalline semiconductor.

5. A display device comprising:
a pixel portion;
a scan line driver circuit; and
a signal line driver circuit,
wherein the pixel portion and the scan line driver circuit are formed over a substrate,
wherein the scan line driver circuit comprises a first flip-flop and a second flip-flop,
wherein the first flip-flop comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a first capacitor,
wherein the second flip-flop comprises a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a second capacitor,
wherein a ratio of a channel width to a channel length of the first transistor is greater than a ratio of a channel width to a channel length of the third transistor,
wherein the ratio of the channel width to the channel length of the first transistor is greater than a ratio of a channel width to a channel length of the fifth transistor,
wherein the ratio of the channel width to the channel length of the first transistor is greater than a ratio of a channel width to a channel length of the sixth transistor,
wherein a ratio of a channel width to a channel length of the seventh transistor is greater than a ratio of a channel width to a channel length of the ninth transistor,
wherein the ratio of the channel width to the channel length of the seventh transistor is greater than a ratio of a channel width to a channel length of the eleventh transistor,
wherein the ratio of the channel width to the channel length of the seventh transistor is greater than a ratio of a channel width to a channel length of the twelfth transistor,
wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor,
wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein one of a source and a drain of the fifth transistor is directly connected to one of a source and a drain of the sixth transistor,
wherein a gate of the first transistor is electrically connected to the one of the source and the drain of the fifth transistor,
wherein a gate of the second transistor is directly connected to the one of the source and the drain of the fourth transistor,
wherein the gate of the second transistor is directly connected to a gate of the sixth transistor,
wherein a gate of the fourth transistor is directly connected to a gate of the fifth transistor,
wherein the gate of the fourth transistor is directly connected to the other of the source and the drain of the fifth transistor,
wherein a first electrode of the first capacitor is directly connected to the gate of the first transistor,
wherein a second electrode of the first capacitor is directly connected to the one of the source and the drain of the first transistor,
wherein one of a source and a drain of the seventh transistor is directly connected to one of a source and a drain of the eighth transistor,
wherein one of a source and a drain of the ninth transistor is electrically connected to one of a source and a drain of the tenth transistor,
wherein one of a source and a drain of the eleventh transistor is directly connected to one of a source and a drain of the twelfth transistor,
wherein a gate of the seventh transistor is electrically connected to the one of the source and the drain of the eleventh transistor,
wherein a gate of the eighth transistor is directly connected to the one of the source and the drain of the tenth transistor,
wherein the gate of the eighth transistor is directly connected to a gate of the twelfth transistor,
wherein a gate of the tenth transistor is directly connected to a gate of the eleventh transistor,
wherein the gate of the tenth transistor is directly connected to the other of the source and the drain of the eleventh transistor,
wherein a first electrode of the second capacitor is directly connected to the gate of the seventh transistor,
wherein a second electrode of the second capacitor is directly connected to the one of the source and the drain of the seventh transistor,
wherein the other of the source and the drain of the first transistor is directly connected to a first wiring,
wherein the other of the source and the drain of the third transistor is directly connected to a second wiring,
wherein the other of the source and the drain of the seventh transistor is directly connected to the second wiring,
wherein the other of the source and the drain of the ninth transistor is directly connected to the first wiring, and
wherein the one of the source and the drain of the first transistor is directly connected to the gate of the eleventh transistor.

6. The display device according to claim 5,
wherein a same voltage is supplied to the other of the source and the drain of the second transistor, the other of the source and the drain of the fourth transistor, the other of the source and the drain of the sixth transistor, the other of the source and the drain of the eighth transistor, the other of the source and the drain of the tenth transistor, and the other of the source and the drain of the twelfth transistor.

7. The display device according to claim 5,
wherein a first clock signal is input to the first wiring, and
wherein a second clock signal is input to the second wiring.

8. The display device according to claim 5,
wherein the signal line driver circuit comprises a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor,
wherein the thirteenth transistor, the fourteenth transistor, and the fifteenth transistor are formed over the substrate,
wherein one of a source and a drain of the thirteenth transistor is directly connected to a third wiring,
wherein one of a source and a drain of the fourteenth transistor is directly connected to the third wiring,
wherein one of a source and a drain of the fifteenth transistor is directly connected to the third wiring,
wherein a gate of the thirteenth transistor is directly connected to a fourth wiring,
wherein a gate of the fourteenth transistor is directly connected to a fifth wiring, and
wherein a gate of the fifteenth transistor is directly connected to a sixth wiring.

9. The display device according to claim 8,
wherein the pixel portion comprises a plurality of source signal lines, a plurality of scan lines, and a pixel,
wherein the pixel comprises a sixteenth transistor, a first insulating film over the sixteenth transistor, a common electrode over the first insulating film, a second insulating film over the common electrode, a pixel electrode over the second insulating film, and a liquid crystal over the pixel electrode,
wherein a first source signal line of the plurality of source signal lines is electrically connected to the other of the source and the drain of the thirteenth transistor,
wherein a second source signal line of the plurality of source signal lines is electrically connected to the other of the source and the drain of the fourteenth transistor,
wherein a third source signal line of the plurality of source signal lines is electrically connected to the other of the source and the drain of the fifteenth transistor,
wherein the plurality of scan lines are electrically connected to the scan line driver circuit,
wherein one of a source and a drain of the sixteenth transistor is electrically connected to one of the plurality of source signal lines,
wherein the other of the source and the drain of the sixteenth transistor is electrically connected to the pixel electrode, and
wherein a gate of the sixteenth transistor is electrically connected to one of the plurality of scan lines.

10. The display device according to claim 5,
wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor comprise a polycrystalline semiconductor.

11. The display device according to claim 9,
wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, the fifteenth transistor, and the sixteenth transistor comprise a polycrystalline semiconductor.

12. A display panel module comprising:
a display panel; and
a circuit board,
wherein the display panel comprises:
a pixel portion;
a scan line driver circuit; and
a signal line driver circuit,
wherein the pixel portion and the scan line driver circuit are formed over a substrate,
wherein the scan line driver circuit comprises a first flip-flop and a second flip-flop,
wherein the first flip-flop comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a first capacitor,
wherein the second flip-flop comprises a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a second capacitor,
wherein a ratio of a channel width to a channel length of the first transistor is greater than a ratio of a channel width to a channel length of the third transistor,
wherein the ratio of the channel width to the channel length of the first transistor is greater than a ratio of a channel width to a channel length of the fifth transistor,
wherein the ratio of the channel width to the channel length of the first transistor is greater than a ratio of a channel width to a channel length of the sixth transistor,
wherein a ratio of a channel width to a channel length of the seventh transistor is greater than a ratio of a channel width to a channel length of the ninth transistor,
wherein the ratio of the channel width to the channel length of the seventh transistor is greater than a ratio of a channel width to a channel length of the eleventh transistor,
wherein the ratio of the channel width to the channel length of the seventh transistor is greater than a ratio of a channel width to a channel length of the twelfth transistor,
wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor,
wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein one of a source and a drain of the fifth transistor is directly connected to one of a source and a drain of the sixth transistor,
wherein a gate of the first transistor is electrically connected to the one of the source and the drain of the fifth transistor,
wherein a gate of the second transistor is directly connected to the one of the source and the drain of the fourth transistor,
wherein the gate of the second transistor is directly connected to a gate of the sixth transistor,
wherein a gate of the fourth transistor is directly connected to a gate of the fifth transistor,
wherein the gate of the fourth transistor is directly connected to the other of the source and the drain of the fifth transistor,
wherein a first electrode of the first capacitor is directly connected to the gate of the first transistor,
wherein a second electrode of the first capacitor is directly connected to the one of the source and the drain of the first transistor,
wherein one of a source and a drain of the seventh transistor is directly connected to one of a source and a drain of the eighth transistor,
wherein one of a source and a drain of the ninth transistor is electrically connected to one of a source and a drain of the tenth transistor,
wherein one of a source and a drain of the eleventh transistor is directly connected to one of a source and a drain of the twelfth transistor,
wherein a gate of the seventh transistor is electrically connected to the one of the source and the drain of the eleventh transistor,
wherein a gate of the eighth transistor is directly connected to the one of the source and the drain of the tenth transistor,
wherein the gate of the eighth transistor is directly connected to a gate of the twelfth transistor,
wherein a gate of the tenth transistor is directly connected to a gate of the eleventh transistor,
wherein the gate of the tenth transistor is directly connected to the other of the source and the drain of the eleventh transistor,
wherein a first electrode of the second capacitor is directly connected to the gate of the seventh transistor,
wherein a second electrode of the second capacitor is directly connected to the one of the source and the drain of the seventh transistor,
wherein the other of the source and the drain of the first transistor is directly connected to a first wiring,
wherein the other of the source and the drain of the third transistor is directly connected to a second wiring,
wherein the other of the source and the drain of the seventh transistor is directly connected to the second wiring,
wherein the other of the source and the drain of the ninth transistor is directly connected to the first wiring,
wherein the one of the source and the drain of the first transistor is directly connected to the gate of the eleventh transistor, and
wherein the display panel and the circuit board are connected to each other by a connection wiring.

13. The display panel module according to claim 12,
wherein a same voltage is supplied to the other of the source and the drain of the second transistor, the other of the source and the drain of the fourth transistor, the other of the source and the drain of the sixth transistor, the other of the source and the drain of the eighth transistor, the other of the source and the drain of the tenth transistor, and the other of the source and the drain of the twelfth transistor.

14. The display panel module according to claim 12,
wherein a first clock signal is input to the first wiring, and
wherein a second clock signal is input to the second wiring.

15. The display panel module according to claim 12,
wherein the signal line driver circuit comprises a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor,
wherein the thirteenth transistor, the fourteenth transistor, and the fifteenth transistor are formed over the substrate,
wherein one of a source and a drain of the thirteenth transistor is directly connected to a third wiring,
wherein one of a source and a drain of the fourteenth transistor is directly connected to the third wiring,
wherein one of a source and a drain of the fifteenth transistor is directly connected to the third wiring,
wherein a gate of the thirteenth transistor is directly connected to a fourth wiring,
wherein a gate of the fourteenth transistor is directly connected to a fifth wiring, and
wherein a gate of the fifteenth transistor is directly connected to a sixth wiring.

16. The display panel module according to claim 15,
wherein the pixel portion comprises a plurality of source signal lines, a plurality of scan lines, and a pixel,
wherein the pixel comprises a sixteenth transistor, a first insulating film over the sixteenth transistor, a common electrode over the first insulating film, a second insulating film over the common electrode, a pixel electrode over the second insulating film, and a liquid crystal over the pixel electrode,
wherein a first source signal line of the plurality of source signal lines is electrically connected to the other of the source and the drain of the thirteenth transistor,
wherein a second source signal line of the plurality of source signal lines is electrically connected to the other of the source and the drain of the fourteenth transistor,
wherein a third source signal line of the plurality of source signal lines is electrically connected to the other of the source and the drain of the fifteenth transistor,
wherein the plurality of scan lines are electrically connected to the scan line driver circuit,
wherein one of a source and a drain of the sixteenth transistor is electrically connected to one of the plurality of source signal lines,
wherein the other of the source and the drain of the sixteenth transistor is electrically connected to the pixel electrode, and
wherein a gate of the sixteenth transistor is electrically connected to one of the plurality of scan lines.

17. The display panel module according to claim 12,
wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor comprise a polycrystalline semiconductor.

18. The display panel module according to claim 16,
wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, the fifteenth transistor, and the sixteenth transistor comprise a polycrystalline semiconductor.

19. The display panel module according to claim 12,
wherein the connection wiring is a flexible printed circuit.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Method And System For Communication In Multi-User Multiple-Input-Multiple Output Wireless Networks

Technical Field and Background:
In a typical wireless network utilizing a coordination function for coordinating transmissions among wireless stations, such a coordination function may be implemented in one of the wireless stations such as a wireless access point (AP) functioning as a coordinator. The wireless stations may communicate via directional transmissions using sector antennas and beam-forming antenna arrays. The coordinator may use omnidirectional transmissions for broadcasts to all wireless stations in all directions (e.g., 360 degrees range). Alternatively, the coordinator may use quasi-omnidirectional transmissions for broadcasts to a wide range, but not necessarily in all directions. In many wireless area networks (WLANs) such as those according to IEEE 802.11 standards, a coordinator is used in infrastructure mode for providing contention-free access to a wireless communication medium to support Quality of Service (QoS) for certain applications.

Invention Disclosure:
Wireless communication in a wireless system using a multiple user transmission opportunity is provided. The data blocks are organized in order of transmission priority based on access categories. Contention for access to the communication medium during a transmission opportunity period is based on a backoff timer of each access category and the transmission priority. Upon successful contention for a transmission opportunity period, during the transmission opportunity period, a data block of a primary access category is wirelessly transmitted from the wireless station to one or more primary destination wireless receivers. Simultaneously, a data block of a secondary access category is wirelessly transmitted from the wireless station to one or more secondary destination wireless receivers. Contending for the transmission opportunity period includes each access category contending for access to the wireless communication medium and a secondary access category selectively invoking communication medium access backoff based on one or more backoff events.

[Assistant]
1. A method of wireless communication in a wireless communication system, comprising:
receiving a data frame transmitted from an access point during a transmission opportunity (TXOP), wherein the data frame comprises data corresponding to primary access category or secondary access category of the access point; and
processing the data frame,
wherein when Enhanced Distributed Channel Access Function (EDCAF) of the secondary access category experiences an internal collision with EDCAF of the primary access category, backoff procedure is invoked.

2. The method of claim 1, wherein the primary access category is associated with EDCAF that gains channel access, and the secondary access category is not associated with EDCAF that gains channel access.

3. The method of claim 1, wherein a data of the primary access category and a data of the secondary access category are simultaneously transmitted during the TXOP by using TXOP sharing.

4. The method of claim 3, wherein the TXOP sharing is allowed when a data of the primary access category is transmitted in the data frame and resource permits a data from the secondary access category to be included in the data frame.

5. The method of claim 3, wherein duration of the TXOP is TXOP limit of the primary access category.

6. A terminal in a wireless communication system, comprising:
a receiver configured to receive a data frame transmitted from an access point during a transmission opportunity (TXOP), wherein the data frame comprises traffic corresponding to primary access category or secondary access category of the access point; and
a controller configured to process the data frame,
wherein when Enhanced Distributed Channel Access Function (EDCAF) of the secondary access category experiences an internal collision with EDCAF of the primary access category, backoff procedure is invoked.

7. The terminal of claim 6, wherein the primary access category is associated with EDCAF that gains channel access, and the secondary access category is not associated with EDCAF that gains channel access.

8. The terminal of claim 6, wherein a data frame of the primary access category and a data frame of the secondary access category are simultaneously transmitted during the TXOP by using TXOP sharing.

9. The terminal of claim 8, wherein the TXOP sharing is allowed when a data of the primary access category is transmitted in the data frame and resource permits a data from the secondary access category to be included in the data frame.

10. The terminal of claim 8, wherein duration of the TXOP is TXOP limit of the primary access category.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Led Having Vertical Contacts Redistributed For Flip Chip Mounting

Technical Field and Background:
Flip chip LEDs are desirable in many applications since they do not use wire bonding. Both electrodes are located on a bottom surface of the LED for direct bonding to metal pads on a submount. Bonding may be accomplished by ultrasonic bonding, solder, conductive adhesive, or other means. Light exits the surface of the LED opposite the electrodes. In a typical LED flip chip, the epitaxial p-type layer is the bottom layer and is contacted by the bottom anode electrode. A portion of the p-type layer and active layer must be etched away to expose the underside of the epitaxial n-type layer for being contacted by the bottom cathode electrode. This etching creates distributed vias through the p-type layer that expose the bottom surface of the n-type layer. The via openings are then insulated, and metal is deposited in the openings for contacting the n-type layer. Such topography is typically achieved by dry-etch of the semiconductor material in a plasma environment with active ionic species. The presence of such structure within a thin film device requires precise control of the plasma etch. Furthermore, the dry etched epitaxial surface, to be interfaced with contact metal, is sensitive to the damage caused by impingement of energetic ionic species in the plasma. From a thermal and mechanical point of view, the corners of such a step structure are prone to becoming failure initiation centers as a result of stress distribution within the sandwiched films. The film growth over the mesa or via structure typically requires a minimum step coverage, leading to higher equipment cost and the requirement of tighter in-line process control. Accordingly, it would be desirable to avoid such etching of vias to form the flip chip LEDs.

Invention Disclosure:
A light emitting diode (LED) structure has semiconductor layers, including a p-type layer, an active layer, and an n-type layer. The p-type layer has a bottom surface, and the n-type layer has a top surface though which light is emitted. A copper layer has a first portion electrically connected to and opposing the bottom surface of the p-type layer. A dielectric wall extends through the copper layer to isolate a second portion of the copper layer from the first portion. A metal shunt electrically connects the second portion of the copper layer to the top surface of the n-type layer. P-metal electrodes electrically connect to the first portion, and n-metal electrodes electrically connect to the second portion, wherein the LED structure forms a flip chip. Other embodiments of the methods and structures are also described.

[Assistant]
1. A method of forming a flip chip LED structure comprising:
providing a growth substrate;
epitaxially growing semiconductor layers on the growth substrate, including a first conductivity layer, an active layer, and a second conductivity layer, the first conductivity layer having an interior surface adjacent to the active layer and an exterior surface opposite the interior surface, and the second conductivity layer having an interior surface adjacent to the active layer and an exterior surface though which light is emitted;
forming a first dielectric portion at least underlying the exterior surface of the first conductivity layer;
forming a first metal portion and a second metal portion underlying the exterior surface of the first conductivity layer, the first metal portion being electrically connected to the exterior surface of the first conductivity layer, the second metal portion being electrically insulated from the first conductivity layer and the first metal portion by the first dielectric portion;
removing the growth substrate;
etching away at least the first conductivity layer, the active layer, and the second conductivity layer overlying the first dielectric portion such that the first dielectric portion electrically isolates the first metal portion from the second metal portion;
forming a first metal shunt portion integral with the LED structure and overlying a top portion of the exterior surface of the second conductivity layer;
forming a second metal shunt portion underlying the first metal shunt portion and electrically connected to the first metal shunt portion and the second metal portion such that the second metal portion is electrically connected to the top portion of the exterior surface of the second conductivity layer;
forming one or more first electrodes electrically connected to the first metal portion; and
forming one or more second electrodes electrically connected to the second metal portion such that the LED structure forms a flip chip, wherein at least some of the one or more second electrodes underlie the plurality of semiconductor layers and the first metal portion and are insulated from the first metal portion by the first dielectric portion.

2. The method of claim 1 wherein the growth substrate is a wafer that supports a plurality of LED structures, the method further comprising:
forming a second dielectric portion along areas which define singulation lines for separating out the plurality of LED structures from each other, the first dielectric portion and the second dielectric portion forming opposing walls with the second portion of the first metal layer in-between.

3. The method of claim 1 wherein a plurality of LED structures are formed on the growth substrate, the first metal shunt portion contacting the exterior surface of the second conductivity layer of one LED structure being in an electrical connection with the first metal portion of an adjacent LED structure so that the one LED structure and the adjacent LED structure are electrically connected in series.

4. The method of claim 1 further comprising forming a second dielectric portion extending from the first dielectric portion to at least the exterior surface of the second conductivity layer, the second dielectric portion isolating the first metal shunt portion from other than the top exterior surface of the second conductivity layer.

5. The method of claim 4 further comprising:
forming a third dielectric portion running along a section of the first metal portion; and
forming the one or more of the second electrodes over the third dielectric and in electrical contact with the second metal portion.

6. The method of claim 1 further comprising:
forming a second dielectric portion extending from the first dielectric portion to at least the exterior surface of the second conductivity layer, the second dielectric portion isolating the first metal shunt portion from other than the exterior surface of the second conductivity layer; and
wherein forming the first metal shunt portion comprises forming the first metal shunt portion over the second dielectric portion and around a periphery of the exterior surface of the second conductivity layer.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Extrusion-Type Connecting Rod, Extrusion Apparatus For Connecting Rod And Manufacturing Method For Extrusion-Type Connecting Rod

Technical Field and Background:
In general, a connecting rod is a mechanical element provided between a piston and a crank to convert reciprocating motion into rotary motion, and may include a big end connected to a crankshaft, a small end connected to a piston shaft, and a connection part for interconnecting the big and small ends. The connecting rod mostly uses an iron-based alloy having excellent toughness and fatigue resistance against repeated explosions of the piston, and is manufactured using casting, forging, or sintered powder molding. However, since the connecting rod manufactured using casting, forging, or sintered powder molding is not easily producible in a large quantity due to processing characteristics thereof, productivity is low, economic feasibility is low, and products are high-priced and heavy-weighted, and have a high defect rate due to structural detects, porosity defect, etc. thereof. To solve the above problem, KR 2001-0097861 discloses a method of manufacturing a connecting rod using an extrusion die. However, according to the connecting rod manufactured using the above conventional technology, a big end should be cut using a cutting device to interconnect a crankshaft and the big end. As such, manufacturing costs and manufacturing time of products are increased, productivity is lowered, and prices of the products are increased.

Invention Disclosure:
The present invention relates to an extrusion-type connecting rod which is installed between a piston and a crank and can convert the reciprocating motion of the piston into the rotary motion of a crank shaft, an extrusion apparatus for a connecting rod, and a manufacturing method for the extrusion-type connecting rod. The extrusion-type connecting rod may comprise: a first big end having a portion of a crank shaft hole formed on one side and having a seam-line divided surface, which comprises a seam line formed at the time of extrusion, formed on the other side; a second big end, being extrusion-molded simultaneously with the first big end, having the other portion of the crank shaft hole formed on one side, and having a seam-line divided surface, which comprises a seam line formed at the time of extrusion, formed so as to contact the seam-line divided surface of the first big end; a connection part which is extrusion-molded integrally with the second big end; and a small end which is extrusion-molded integrally with the connection part.

[Assistant]
1. A connecting rod extrusion apparatus comprising:
a front die having one final extrusion hole provided in an external shape of a connecting rod; and
a rear die assembled with the front die and comprising:
a crankshaft hole generator for generating a crankshaft hole of the connecting rod;
one or more bridges provided on the crankshaft hole generator to generate seam line splitting planes based on the crankshaft hole generator;
at least one first inlet hole provided in a first direction based on the bridges; and
at least one second inlet hole provided in a second direction based on the bridges.

2. The connecting rod extrusion apparatus of claim 1, wherein the crankshaft hole generator protrudes to be spaced apart from and partially inserted into the final extrusion hole of the front die.

3. The connecting rod extrusion apparatus of claim 1, further comprising:
a container assembled with the rear die and having one container hole; and
a ram for extruding a molding material accommodated in the container hole, toward the front die.

4. The connecting rod extrusion apparatus of claim 1, further comprising:
a container assembled with the rear die and comprising a first container hole connected to the first inlet hole and a second container hole connected to the second inlet hole;
a first ram for extruding a first molding material accommodated in the first container hole, toward the front die; and
a second ram for extruding a second molding material accommodated in the second container hole, toward the front die.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Four-Surface Narrow Field-Of-View Compound Lens

Technical Field and Background:
Digital camera modules are used in a variety of consumer, industrial and scientific imaging devices to produce still images and/or video. Applications of digital camera modules include image-based recognition applications such as barcode scanning and iris recognition. A camera for such applications may include an imaging lens with relatively large depth of field compared to conventional lenses. Such a large depth of field enables a device using the camera to recognize an object to be relatively insensitive to the object's distance from the imaging lens. For a fixed imaging lens focal length, the depth of field of the imaging lens is approximately linearly proportional to the lens's f-number N, where N is the ratio of the lens's effective length to its entrance pupil diameter D. See, for example, The Manual of Photography, 9 th ed. by Jacobson et al, Focal Press, 2000. The field of view 2α of a camera with an imaging lens having focal length f and an image sensor with diagonal length d is 2  α = 2  arctan  ( d 2  f ) . Expressed in terms of f-number N=f/D, α = 2  arctan  ( d 2  D · N ) , which illustrates that for a constant entrance pupil diameter D, field of view α decreases as f-number N increases. Since depth of field is approximately linearly proportional to the lens's f-number N, field of view 2α also decreases as depth of field increases. Image-based recognition devices require a camera module having a lens with a smaller field of view (FOV) than lenses in conventional camera modules, while producing images with line-width resolution minimally reduced compared to images formed by conventional camera modules. Conventional narrow-FOV camera modules achieve a small point of view while maintaining image quality of a larger FOV camera by employing telescope-like compound lenses that include several optical surfaces. A disadvantage of such camera modules is that the manufacturing cost of a compound lens increases with number of optical surfaces.

Invention Disclosure:
A four-surface narrow field-of-view compound lens includes a first biplanar substrate between a first lens and a second lens, the first lens being plano-convex and the second lens being plano-concave. The compound lens also includes a second biplanar substrate between a third lens and a fourth lens, the third lens being plano-convex and the fourth lens being plano-concave. The second lens and third lens are between the first biplanar substrate and the second biplanar substrate. The first lens, second lens, third lens, and fourth lens are coaxial and are formed of materials having a first, second, third, and fourth Abbe number respectively and focal lengths F1, F2, F3, and F4 respectively. The first Abbe number exceeds the second Abbe number and the third Abbe number exceeds the fourth Abbe number. Ratio F1/F2 may satisfy −0.32<F1/F2<−0.18 and ratio F4/F3 may satisfy −0.72<F4/F3<−0.48.

[Assistant]
1. A four-surface narrow field-of-view (FOV) compound lens for producing an image of an object at an image plane of an imaging system, the compound lens comprising:
a first biplanar substrate between a first lens and a second lens, the first lens being plano-convex and the second lens being plano-concave; and
a second biplanar substrate between a third lens and a fourth lens, the third lens being plano-convex and the fourth lens being plano-concave,
the first lens, the second lens, the third lens, and the fourth lens having a common optical axis,
the second lens and third lens being between the first biplanar substrate and the second biplanar substrate,
the first lens having a first planar surface on a first side of the first biplanar substrate and being formed of a material having a first Abbe number,
the second lens having a second planar surface on a second side of the first biplanar substrate opposite the first side and being formed of a material having a second Abbe number,
the third lens having a third planar surface on a first side of the second biplanar substrate and being formed of a material having a third Abbe number,
the fourth lens having a fourth planar surface on a second side of the second biplanar substrate opposite the first side and being formed of a material having a fourth Abbe number,
the first Abbe number exceeding the second Abbe number and the third Abbe number exceeding the fourth Abbe number.

2. The compound lens of claim 1, each of the first Abbe number and the third Abbe number exceeding 50, each of the second Abbe number and the fourth Abbe number being less than 35.

3. The compound lens of claim 1, the first lens having a focal length F1, the second lens having a focal length F2, the ratio F1/F2 satisfying 0.32<F1/F2<−0.18.

4. The compound lens of claim 1, the third lens having a focal length F3, the fourth lens having a focal length F4, the ratio F4/F3 satisfying 0.72<F4/F3<−0.48.

5. The compound lens of claim 1, the first lens, the first biplanar substrate, the second lens, the third lens, the second biplanar substrate, and the fourth lens collectively having an effective focal length f eff such that the image is formed at the image plane located a distance T from an intersection of the optical axis and an object-side convex surface of the first lens, and the ratio f eff /T satisfying 0.85<f eff /T<0.95 for limiting distance T.

6. The compound lens of claim 1, the second planar surface functioning as an aperture stop.

7. The compound lens of claim 1, the first biplanar substrate having a width exceeding a diameter of the second planar surface.

8. The compound lens of claim 1, at least one of the first lens, the second lens, the third lens, and the fourth lens being a singlet lens.

9. The compound lens of claim 1, the first lens, the first biplanar substrate, the second lens, the third lens, the second biplanar substrate, and the fourth lens collectively having an effective focal length between six millimeters and nine millimeters.

10. The compound lens of claim 1, having an f-number between 2.5 and 3.5.

11. A four-surface narrow field-of-view (FOV) compound lens for producing an image of an object at an image plane of an imaging system, the compound lens comprising:
a first biplanar substrate between a first lens and a second lens, the first lens being plano-convex and the second lens being plano-concave; and
a second biplanar substrate between a third lens and a fourth lens, the third lens being plano-convex and the fourth lens being plano-concave,
the first lens, the second lens, the third lens, and the fourth lens having a common optical axis,
the second lens and third lens being between the first biplanar substrate and the second biplanar substrate,
the first lens having a first planar surface on a first side of the first biplanar substrate, a focal length F1, and being formed of a material having a first Abbe number,
the second lens having a second planar surface on a second side of the first biplanar substrate opposite the first side, a focal length F2, and being formed of a material having a second Abbe number,
the third lens having a third planar surface on a first side of the second biplanar substrate, a focal length F3, and being formed of a material having a third Abbe number,
the fourth lens having a fourth planar surface on a second side of the second biplanar substrate opposite the first side, a focal length F4, and being formed of a material having a fourth Abbe number,
the ratio F1/F2 satisfying −0.32<F1/F2<−0.18,
the ratio F4/F3 satisfying −0.72<F4/F3<−0.48,
the first Abbe number and the third Abbe number each exceeding 50, the second Abbe number and the fourth Abbe number each being less than 35,
the first lens, the first biplanar substrate, the second lens, the third lens, the second biplanar substrate, and the fourth lens collectively having an effective focal length f eff such that the image is formed at the image plane located a distance T from an intersection of the optical axis and an object-side convex surface of the first lens, and the ratio f eff /T satisfying 0.85<f eff /T<0.95 for limiting distance T.

12. The compound lens of claim 11, the second planar surface functioning as an aperture stop.

13. The compound lens of claim 11, the first biplanar substrate having a width exceeding a diameter of the second planar surface.

14. The compound lens of claim 11, the first lens, the second lens, the third lens, and the fourth lens each being a singlet lens.

15. The compound lens of claim 11, the first lens, the first biplanar substrate, the second lens, the third lens, the second biplanar substrate, and the fourth lens collectively having an effective focal length between six millimeters and nine millimeters.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Image Processing Apparatus With Improved Slide Printout Based On Layout Data

Technical Field and Background:
Conventionally, a manufacturing process of a semiconductor device uses a CVD apparatus that forms a film by a CVD (Chemical Vapor Deposition) method. The CVD apparatus includes a diffusion plate that straightens a process gas for film deposition in a chamber. The diffusion plate has a plurality of through holes allowing the process gas to pass therethrough toward a wafer. The position and the opening area of each through hole and the number of the through holes are designed to provide a desired distribution of a film thickness in a plane of the wafer (hereinafter, also “in-plane distribution”). In recent years, a lamination deposition process has been developed in which plural types of films are laminated in the same chamber. In a case of applying the diffusion plate to the lamination deposition process, the through holes can be designed to provide a desired in-plane distribution of a film thickness for one type of film. However, an in-plane distribution of a film thickness for other types of films is degraded under such specialized design of through holes for the one type of film.

Invention Disclosure:
A semiconductor manufacturing method includes setting a relative position between first through holes of a first plate-shaped part and second through holes of a second plate-shaped part to a first relative position. The method includes supplying a first gas containing a component of the first film onto the semiconductor substrate in a reactor through the first through holes not closed with the second plate-shaped part, to form the first film on the semiconductor substrate. The method includes relatively moving the first plate-shaped part and the second plate-shaped part to change the relative position to a second relative position. The method includes supplying a second gas containing a component of the second film onto the semiconductor substrate through the first through holes not closed with the second plate-shaped part, to laminate the second film on the first film.

[Assistant]
1. A semiconductor manufacturing method using a semiconductor manufacturing apparatus comprising a reactor capable of accommodating a semiconductor substrate therein and allowing a gas used for film deposition on the semiconductor substrate to be introduced thereinto, a first plate part arranged in the reactor and comprising a plurality of first through holes each have a circular shape having the same inner diameter and are arranged radially to be concentric with the first plate part, and a second plate part arranged in the reactor on a gas-downstream side of the first plate part to be opposed to the first plate part and comprising a plurality of second through holes at least one of which is different from the first through holes in shape, the second through holes including arc-shaped through holes arranged around the center of the second plate part and elliptical through holes and circular through holes arranged in a peripheral portion of the second plate part, the method comprising:
setting a relative position between the first through holes and the second through holes to a first relative position corresponding to a target in-plane distribution of a film thickness of an oxide film;
supplying a first gas comprising a component of the oxide film and a diluent gas for the first gas onto the semiconductor substrate in the reactor through the first through holes not closed with the second plate part at the first relative position and supplying a first high-frequency electric power, to form the oxide film on the semiconductor substrate;
stopping the supply of the first high-frequency electric power based on a fact that a predetermined time has passed from the start of the supply of the first high-frequency electric power and stopping the supply of the first gas and the diluent gas for the first gas based on a fact that a predetermined time has passed from the start of the supply of the first gas and the diluent gas;
relatively rotating the first plate part and the second plate part to change the relative position to a second relative position corresponding to a target in-plane distribution of a film thickness of a nitride film, the second relative position being different from the first relative position in number, a cross-sectional area, or positions of the first through holes overlapping with the second through holes; and
supplying a second gas comprising a component of the nitride film and a diluent gas for the second gas onto the semiconductor substrate through the first through holes not closed with the second plate part at the second relative position and controlling flow rates of the second gas and the diluent gas for the second gas to be different from flow rates of the first gas and the diluent gas for the first gas, and supplying a second high-frequency electric power, to laminate the nitride film on the oxide film; and
stopping the supply of the second high-frequency electric power and stopping the supply of the second gas and the diluent gas for the second gas.

2. The method of claim 1, further comprising:
relatively moving the first plate part and the second plate part to change the relative position to the first relative position, after formation of the nitride film; and
supplying the first gas onto the semiconductor substrate through the first through holes not closed with the second plate part at the first relative position, to laminate the film on the nitride film.

3. The method of claim 1, wherein
supply of the first gas onto the semiconductor substrate is stopped and the first gas is discharged from the reactor, after formation of the oxide film, and
the first plate part and the second plate part are rotated relative to each other to change the relative position to the second relative position, after the stop of supply of the first gas and the discharge of the first gas before supply of the second gas onto the semiconductor substrate.

4. The method of claim 2, wherein
supply of the second gas onto the semiconductor substrate is stopped and the second gas is discharged from the reactor, after formation of the nitride film, and
the first plate part and the second plate part are rotated relative to each other to change the relative position to the first relative position, after the stop of supply of the second gas and the discharge of the second gas before supply of the first gas onto the semiconductor substrate.

5. The method of claim 3, wherein
the laminated film is formed by plasma CVD, and
stop of supply of the first gas, discharge of the first gas, and rotation of the first plate part and the second plate part relative to each other are performed, while plasma is generated after formation of the oxide film.

6. The method of claim 4, wherein
the laminated film is formed by plasma CVD, and
stop of supply of the second gas, discharge of the second gas, and rotation of the first plate part and the second plate part relative to each other are performed, while plasma is generated after formation of the nitride film.

7. The method of claim 3, wherein the second plate part is rotated.

8. The method of claim 4, wherein the second plate part is rotated.

9. The method of claim 1, wherein the second through holes are different from the first through holes in at least one of number, a cross-sectional area, and horizontal positions.

10. The method of claim 1, wherein at least one of the second through holes has a larger inner circumference than those of the first through holes.

11. The method of claim 1, wherein at least one of the second through holes has a smaller inner circumference than those of the first through holes.

12. A semiconductor manufacturing method using a semiconductor manufacturing apparatus comprising a reactor capable of accommodating a semiconductor substrate therein and allowing a gas used for film deposition on the semiconductor substrate to be introduced thereinto, a first plate part arranged in the reactor and comprising a plurality of first through holes each have a circular shape having the same inner diameter and are arranged radially to be concentric with the first plate part, and a second plate part arranged in the reactor on a gas-downstream side of the first plate part to be opposed to the first plate part and comprising a plurality of second through holes at least one of which is different from the first through holes in shape, the second through holes including arc-shaped through holes arranged around the center of the second plate part and elliptical through holes and circular through holes arranged in a peripheral portion of the second plate part, the method comprising:
setting a relative position between the first through holes and the second through holes to a first relative position corresponding to a target in-plane distribution of a film thickness of a first film;
supplying a first gas comprising a component of the first film and a diluent gas for the first gas onto the semiconductor substrate in the reactor through the first through holes not blocked with the second plate part at the first relative position and supplying high-frequency electric power into the reactor, to form the first film on the semiconductor substrate;
stopping the supply of the first gas onto the semiconductor substrate and discharging the first gas from the reactor;
relatively rotating the first plate part and the second plate part to change the relative position to a second relative position corresponding to a target in-plane distribution of a film thickness of a second film; and
supplying a second gas comprising a component of the second film and a diluent gas for the second gas onto the semiconductor substrate through the first through holes not closed with the second plate part at the second relative position and controlling flow rates of the second gas and the diluent gas for the second gas to be different from flow rates of the first gas and the diluent gas for the first gas, to laminate the second film on the first film;
stopping the supply of the second gas onto the semiconductor substrate and discharging the second gas from the reactor;
relatively moving the first plate part and the second plate part to change the relative position to the first relative position;
and supplying the first gas onto the semiconductor substrate through the first through holes not closed with the second plate part at the first relative position, to laminate the first film on the second film.

13. A semiconductor manufacturing method using a semiconductor manufacturing apparatus comprising a reactor capable of accommodating a semiconductor substrate therein and allowing a gas used for film deposition on the semiconductor substrate to be introduced thereinto, a first plate part arranged in the reactor and comprising a plurality of first through holes each have a circular shape having the same inner diameter and are arranged radially to be concentric with the first plate part, and a second plate part arranged in the reactor on a gas-downstream side of the first plate part to be opposed to the first plate part and comprising a plurality of second through holes at least one of which is different from the first through holes in shape, the second through holes including arc-shaped through holes arranged around the center of the second plate part and elliptical through holes and circular through holes arranged in a peripheral portion of the second plate part, the method comprising:
alternately supplying a first gas comprising a component of a first film and a diluent gas for the first gas, and a second gas comprising a component of a second film and the diluent gas for the second gas onto the semiconductor substrate in the reactor through the first through holes not blocked with the second plate part and supplying high-frequency electric power into the reactor, to form a laminated film comprising the first film and the second film alternately laminated on the semiconductor substrate; and
relatively rotating the first plate part and the second plate part to make a relative position between the first through holes and the second through holes different between when the first film is formed and when the second film is formed and controlling flow rates of the second gas and the diluent gas for the second gas to be different from flow rates of the first gas and the diluent gas for the first gas, wherein
the laminated film is formed by plasma CVD,
while plasma is generated after the first film is formed in a state that the relative position is set to a first relative position, supply of the first gas is stopped, the first gas is discharged from the reactor, and the relative position is changed from the first relative position to a second relative position, and
while the relative position is set to the second relative position and plasma is generated after formation of the second film, supply of the second gas is stopped, the second gas is discharged from the reactor, and the relative position is changed from the second relative position to the first relative position.


[System] You are an expert US patent attorney. Draft a set of independent and dependent claims based on the provided invention description. Use correct USPTO formatting.

[User]
Title: Steering Apparatus For Vehicle

Technical Field and Background:
The present disclosure relates to a steering apparatus for a vehicle, and more particularly, a steering apparatus for a vehicle, which is coupled to a subframe and transfers a driver's steering wheel operation to a wheel. A steering force of a vehicle through a steering wheel is transferred to a wheel through a steering apparatus having a rack-pinion structure, and then rotates the wheel. In particular, a motor driven steering apparatus for a vehicle assists a steering force through a motor, and enables a driver to more easily operate the steering wheel. The related technology is disclosed in Korean Patent Laid-open Publication No. 10-2013-0040104 published on Apr. 23, 2013 and titled “Rack bush of steering apparatus for vehicle”).

Invention Disclosure:
A steering apparatus for a vehicle may include: a pinion gear rotated in connection with a steering wheel; a rack housing for housing a rack bar which is rotated while engaged with the pinion gear; and a mounting member coupled to the rack housing, wherein the mounting member may be coupled to a subframe while the shape thereof is changed according to the position or shape of the subframe.

[Assistant]
1. A steering apparatus for use in a vehicle, the apparatus comprising:
a pinion gear configured to rotate according to operation of a steering wheel;
a rack housing configured to house a rack bar that is operably engaged with the pinion gear; and
a mounting member coupled to the rack housing, wherein the mounting member is coupled to a subframe while a configuration of the mounting member changes,
wherein the mounting member comprises:
a mounting coupled to the rack housing,
a sub-mounting part interposed between the mounting part and the subframe and rotatably coupled to the mounting part, and
a fastening part coupling the mounting part and the sub-mounting part to the subframe,
wherein the mounting part protrudes from the rack housing and includes a mounting hole through which the fastening part is passed and a sub-mounting seating part formed on a bottom surface thereof and having a shape corresponding to the shape of the sub-mounting part, and the sub-mounting part is seated on the sub-mounting seating part,
wherein the sub-mounting part is interposed between the mounting part and the subframe, and has a sub-mounting hole through which the fastening part is passed.

2. The steering apparatus of claim 1, wherein the fastening part comprises:
a fastening part body coupled to the subframe through the mounting part and the sub mounting part; and
a fastening part head coupled to the fastening part body, having a larger diameter than the fastening part body, and pressurizing the mounting part toward the sub mounting part.

3. The steering apparatus of claim 2, wherein the fastening part body is screwed to the subframe through a screw thread formed on an outer circumferential surface of the fastening part body.

4. The steering apparatus of claim 2, wherein the fastening part body and the fastening part head are integrated with each other.

5. The steering apparatus of claim 1, wherein the inner diameter of the sub-mounting hole is larger than the diameter of the fastening part.

6. The steering apparatus of claim 1, wherein the inner diameter of the sub-mounting hole is larger than the diameter of the mounting hole.

7. The steering apparatus of claim 1, wherein a surface of the sub-mounting part, facing the mounting part, is formed in a convex shape and contacted with the sub-mounting seating part.

8. The steering apparatus of claim 1, wherein the sub-mounting part is formed in a hemispherical shape, and has a convex surface contacted with the sub-mounting seating part.