| {"_id": "c361", "text": "eet\r\n| Bits | Description | Type | Reset |\r\n| 0 | ADC | RW | 0x1 |\r\n| Offset:0x4 | RESETS:WDSEL Register | | |\r\n| Bits | Description | Type | Reset |\r\n| 31:29 | Reserved. | | |\r\n| 28 | USBCTRL | RW | Ox0 |\r\n| 27 | UART1 | RW | Ox0 |\r\n| 26 | UARTO | RW | Ox0 |\r\n| 25 | TRNG | RW | 0x0 |\r\n| 24 | TIMER1 | RW | Ox0 |\r\n| 23 | TIMERO | RW | Ox0 |\r\n| 22 | TBMAN | RW | Ox0 |\r\n| 21 | SYSINFO | RW | Ox0 |\r\n| 20 | SYSCFG | RW | Ox0 |\r\n| 19 | SPI1 | RW | Ox0 |\r\n| 18 | SPIO | RW | Ox0 |\r\n| 17 | SHA256 | RW | Ox0 |\r\n| 16 | PWM | RW | Ox0 |\r\n| 15 | PLL_USB | RW | Ox0 |\r\n| 14 | PLL_SYS | RW | 0x0 |\r\n| 13 | PI02 | RW | Ox0 |\r\n| 12 | PI01 | RW | Ox0 |\r\n| 11 | PIO0 | RW | Ox0 |\r\n| 10 | PADS_QSPI | RW | Ox0 |\r\n| 9 | PADS_BANKO | RW | Ox0 |\r\n| 8 | JTAG | RW | Ox0 |\r\n| | IO_QSPI | RW | Ox0 |\r\n| 6 | IO_BANKO | RW | 0x0 |\r\n| 5 | I2C1 | RW | Ox0 |\r\n| 4 | I2C0 | RW | Ox0 |\r\n| 3 | HSTX | RW | Ox0 |\r\n| 2 | DMA | RW | 0x0 |\r\n| | BUSCTRL | RW | Ox0 |\r\n| 0 | ADC | RW | Ox0 |"} |
| {"_id": "c73", "text": "control register. Once the buffer control register has been written to, the device controller responds to the host with the\r\ndata. Before this point, the device replies with a NAK:\r\nPico Examples: https://github.com/raspberrypi/pico-examples/blob/master/usb/device/dev_lowlevel/dev_lowlevel.c Lines 238 - 260\r\n238 void usb_start_transfer(struct usb_endpoint_configuration *ep, uint8_t *buf, uint16_t len) {\r\n239 // We are asserting that the length is <= 64 bytes for simplicity of the example.\r\n240 // For multi packet transfers see the tinyusb port.\r\n241 assert(len <= 64);\r\n242 \r\n243 printf(\"Start transfer of len %d on ep addr 0x%x\\n\", len, ep->descriptor-\r\n\u00a0 >bEndpointAddress);\r\n244 \r\n245 // Prepare buffer control register value\r\n246 uint32_t val = len | USB_BUF_CTRL_AVAIL;\r\n247 \r\n248 if (ep_is_tx(ep)) {\r\n249 // Need to copy the data from the user buffer to the usb memory\r\n250 memcpy((void *) ep->data_buffer, (void *) buf, len);\r\n251 // Mark as full\r\n252 val |= USB_BUF_CTRL_FULL;\r\n253 }\r\n254 \r\n255 // Set pid and flip for next transfer\r\n256 val |= ep->next_pid ? USB_BUF_CTRL_DATA1_PID : USB_BUF_CTRL_DATA0_PID;\r\n257 ep->next_pid ^= 1u;\r\n258 \r\n259 *ep->buffer_control = val;\r\n260 }\r\n12.7.5. List of registers\r\nThe USB registers start at a base address of 0x50110000 (defined as USBCTRL_REGS_BASE in SDK).\r\nTable 1195. List of\r\nUSB registers\r\nOffset Name Info\r\n0x000 ADDR_ENDP Device address and endpoint control\r\n0x004 ADDR_ENDP1 Interrupt endpoint 1. Only valid for HOST mode.\r\n0x008 ADDR_ENDP2 Interrupt endpoint 2. Only valid for HOST mode.\r\n0x00c ADDR_ENDP3"} |
| {"_id": "c374", "text": "Description\r\n| | Returns the level of tracing that the trace unit can support | | |\r\n| Bits | Description | Type | Reset |\r\n| 31:8 | Reserved. | | |\r\n| 7:6 | SNID: Indicates whether the system enables the trace unit to support Secure non-invasive debug: | RO | 0x0 |\r\n| 5:4 | SID: Indicates whether the trace unit supports Secure invasive debug | RO | 0x0 |\r\n| 3:2 | NSNID:Indicates whether the system enables the trace unit to support Non- secure non-invasive debug: | RO | 0x0 |\r\n| 1:0 | NSID: Indicates whether the trace unit supports Non-secure invasive debug | RO | 0x0 |"} |
| {"_id": "c155", "text": ". . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1275\r\n13.5.3. Lock encoding in OTP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1276\r\n13.5.4. Special pages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1276\r\n13.5.5. Permissions of blank devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1276\r\n13.6. Error Correction Code (ECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1277\r\n13.6.1. Bit repair by polarity (BRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1277\r\n13.6.2. Modified Hamming ECC. . . . . . . . . . . . . . . . . . . . . . . . . . . ."} |
| {"_id": "c104", "text": "Bits Description Type Reset\r\n8 R5_X: Execute permission for region 5. Note R and X are transposed from the\r\nstandard bit order due to erratum RP2350-E6.\r\nRW 0x0\r\n7 R4_L: Lock region 4, and apply it to M-mode as well as U-mode. RW 0x0\r\n6:5 Reserved. - -\r\n4:3 R4_A: Address matching type for region 4. Writing an unsupported value (TOR)\r\nwill set the region to OFF.\r\nRW 0x0\r\nEnumerated values:\r\n0x0 \u2192 OFF: Disable region\r\n0x2 \u2192 NA4: Naturally aligned 4-byte\r\n0x3 \u2192 NAPOT: Naturally aligned power-of-two (8 bytes to 4 GiB)\r\n2 R4_R: Read permission for region 4. Note R and X are transposed from the\r\nstandard bit order due to erratum RP2350-E6.\r\nRW 0x0\r\n1 R4_W: Write permission for region 4 RW 0x0\r\n0 R4_X: Execute permission for region 4. Note R and X are transposed from the\r\nstandard bit order due to erratum RP2350-E6.\r\nRW 0x0\r\nRVCSR: PMPCFG2 Register\r\nOffset: 0x3a2\r\nDescription\r\nPhysical memory protection configuration for regions 8 through 11\r\nTable 387. PMPCFG2\r\nRegister\r\nBits Description Type Reset\r\n31 R11_L: Lock region 11, and apply it to M-mode as well as U-mode. RO 0x0\r\n30:29 Reserved. - -\r\n28:27 R11_A: Address matching type for region 11. Writing an unsupported value\r\n(TOR) will set the region to OFF.\r\nRO 0x0\r\nEnumerated values:\r\n0x0 \u2192 OFF: Disable region\r\n0x2 \u2192 NA4: Naturally aligned 4-byte\r\n0x3 \u2192 NAPOT: Naturally aligned power-of-two (8 bytes to 4 GiB)\r\n26 R11_R: Read permission for region 11. Note R and X are transposed from the\r\nstandard bit order due to erratum RP2350-E6.\r\nRO 0x0\r\n25 R11_W: Write permission for region 11 RO 0x0\r\n24 R11_X: Execute permission for region 11. Note R and X are transposed from\r\nthe standard bit order due to errat"} |
| {"_id": "c394", "text": "eet\r\n| Bits | Description | Type | Reset |\r\n| 22 | WHITE_LABEL_ADDR_VALID:valid flag for INFO_UF2_TXT_BOARD_ID_STRDEF entry of the USB_WHITE_LABEL struct (index 15) | RO | |\r\n| 21:16 | Reserved. | | |\r\n| 15 | WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID:valid flag for the USB_WHITE_LABEL_ADDR field | RO | |\r\n| 14 | WL_INFO_UF2_TXT_MODEL_STRDEF_VALID: valid flag for INFO_UF2_TXT_MODEL_STRDEF entry of the USB_WHITE_LABEL struct (index 14) | RO | |\r\n| 13 | WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID: valid flag for INDEX_HTM_REDIRECT_NAME_STRDEF entry of the USB_WHITE_LABEL struct (index 13) | RO | |\r\n| 12 | WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID: valid flag for INDEX_HTM_REDIRECT_URL_STRDEF entry of the USB_WHITE_LABEL struct (index 12) | RO | |\r\n| 11 | WL_SCSI_INQUIRY_VERSION_STRDEF_VALID: valid flag for SCSI_INQUIRY_VERSION_STRDEF entry of the USB_WHITE_LABEL struct (index 11) | RO | |\r\n| 10 | WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID: valid flag for SCSI_INQUIRY_PRODUCT_STRDEF entry of the USB_WHITE_LABEL struct (index 10) | RO | |\r\n| 9 | WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID: valid flag for SCSI_INQUIRY_VENDOR_STRDEF entry of the USB_WHITE_LABEL struct (index 9) | RO | |\r\n| 8 | WL_VOLUME_LABEL_STRDEF_VALID: valid flag for VOLUME_LABEL_STRDEF entry of the USB_WHITE_LABEL struct (index 8) | RO | |\r\n| | WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID: valid flag for USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES entry of the USB_WHITE_LABEL struct (index 7) | RO | |\r\n| 6 | WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID: valid flag for USB_DEVICE_SERIAL_NUMBER_STRDEF entry of the USB_WHITE_LABEL struct (index 6) | RO | |\r\n| 5 | WL_USB_DEVICE_PRODUCT_STRDEF_VALID: valid flag for USB_DEVICE_PRODUCT_STRDEF entry of the USB_WHITE_LABEL struct (index 5) | RO | |\r\n| 4 | WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID: valid flag for USB_DEVICE_MANUFACTURER_STRDEF entry of the USB_WHITE_LABEL struct (index 4) | RO | |\r\n| 3 | WL_USB_DEVICE_LANG_ID_VALUE_VALID: valid flag for USB_DEVICE_LANG_ID_VALUE entry of the USB_WHITE_LABEL struct (index 3) | RO | |\r\n| 2 | WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID: valid flag for USB_DEVICE_BCD_DEVICEVALUE entry of the USB_WHITE_LABEL struct (index 2) | RO | |\r\n| | WL_USB_DEVICE_PID_VALUE_VALID: valid flag for USB_DEVICE_PID_VALUE entry of the USB_wHITE_LABEL struct (index 1) | RO | |"} |
| {"_id": "c377", "text": "Bits Description Type Reset\r\n7 SM3_TXNFULL RO 0x0\r\n6 SM2_TXNFULL RO 0x0\r\n5 SM1_TXNFULL RO 0x0\r\n4 SM0_TXNFULL RO 0x0\r\n3 SM3_RXNEMPTY RO 0x0\r\n2 SM2_RXNEMPTY RO 0x0\r\n1 SM1_RXNEMPTY RO 0x0\r\n0 SM0_RXNEMPTY RO 0x0\r\nPIO: IRQ0_INTE Register\r\nOffset: 0x170\r\nDescription\r\nInterrupt Enable for irq0\r\nTable 1019.\r\nIRQ0_INTE Register\r\nBits Description Type Reset\r\n31:16 Reserved. - -\r\n15 SM7 RW 0x0\r\n14 SM6 RW 0x0\r\n13 SM5 RW 0x0\r\n12 SM4 RW 0x0\r\n11 SM3 RW 0x0\r\n10 SM2 RW 0x0\r\n9 SM1 RW 0x0\r\n8 SM0 RW 0x0\r\n7 SM3_TXNFULL RW 0x0\r\n6 SM2_TXNFULL RW 0x0\r\n5 SM1_TXNFULL RW 0x0\r\n4 SM0_TXNFULL RW 0x0\r\n3 SM3_RXNEMPTY RW 0x0\r\n2 SM2_RXNEMPTY RW 0x0\r\n1 SM1_RXNEMPTY RW 0x0\r\n0 SM0_RXNEMPTY RW 0x0\r\nPIO: IRQ0_INTF Register\r\nOffset: 0x174\r\nDescription\r\nInterrupt Force for irq0\r\nRP2350 Datasheet\r\n11.7. List of registers 95"} |
| {"_id": "c124", "text": "pio, uint sm, uint offset, uint pin_sda, uint\r\n\u00a0 pin_scl) {\r\n\u00a082 assert(pin_scl == pin_sda + 1);\r\n\u00a083 pio_sm_config c = i2c_program_get_default_config(offset);\r\nRP2350 Datasheet\r\n11.6. Examples 93"} |
| {"_id": "c68", "text": "| Mnemonic | Armv8-M Instruction | Operation |\r\n| gpioc_hi_oe_set | mcrp0.=2.Rtc0c5 | sio_hw+gpio_hi_oe_set = Rt |\r\n| gpioc_hi_oe_c1r | mcr p0.=3,Rtc0c5 | sio_hwgpio_hi_oe_clr = Rt; |\r\n| gpioc_hilo_oe_put | mcrr p0.#0.Rt.Rt2.c4 | Simultaneously:sio_hwgpio_oe =Rt;sio_hwgpio_hi_oe =Rt2; |\r\n| gpioc_hilo_oe_xor | mcrr p0.=1Rt.Rt2.c4 | Simultaneously:sio_hwgpio_oe_togl =Rt;sio_hw+gpio_hi_oe_togl= Rt2; |\r\n| gpioc_hilo_oe_set | mcrr p0#2,Rt,Rt2c4 | Simultaneously:sio_hwgpio_oe_set = Rt;sio_hwgpio_hi_ce_set = Rt2; |\r\n| gpioc_hilo_oe_clr | mcrr p0#3.Rt,Rt2c4 | Simultaneously:sio_hw+gpio_oe_clr =Rt;sio_hwgpio_hi_oe_clr= Rt2; |"} |
| {"_id": "c450", "text": "clock frequency divided by this number.\r\nFractional division uses simple 1st-order sigma-delta.\r\n0x008 CH0_CTR Direct access to the PWM counter\r\n0x00c CH0_CC Counter compare values\r\n0x010 CH0_TOP Counter wrap value\r\n0x014 CH1_CSR Control and status register\r\n0x018 CH1_DIV INT and FRAC form a fixed-point fractional number.\r\nCounting rate is system clock frequency divided by this number.\r\nFractional division uses simple 1st-order sigma-delta.\r\n0x01c CH1_CTR Direct access to the PWM counter\r\n0x020 CH1_CC Counter compare values\r\n0x024 CH1_TOP Counter wrap value\r\n0x028 CH2_CSR Control and status register\r\n0x02c CH2_DIV INT and FRAC form a fixed-point fractional number.\r\nCounting rate is system clock frequency divided by this number.\r\nFractional division uses simple 1st-order sigma-delta.\r\nRP2350 Datasheet\r\n12.5. PWM"} |
| {"_id": "c9", "text": "| 3.8.1.3.1.Register conventions | | |\r\n| | | The following ABl names are synonymous with x through x31: |\r\n| Register | ABI Name | Description |\r\n| x0 | zero | Hardwired to zero; ignores writes |\r\n| x1 | ra | Return address (link register) |\r\n| x2 | Sp | Stack pointer |\r\n| x3 | gp | Global pointer |\r\n| x4 | tp | Thread pointer |\r\n| x5-x7 | t0-t2 | Temporaries |\r\n| x8 | s0or fp | Saved register or frame pointer |\r\n| x9 | $1 | Saved register |\r\n| x10- x11 | a0-a1 | Function arquments and return values |\r\n| x12-x17 | a2-a7 | Function arguments |\r\n| x18 - x27 | s2-511 | Saved registers |\r\n| x28 - x31 | t3-t6 | Temporaries |"} |
| {"_id": "c194", "text": "eet\r\n| Bits | Description | Type | Reset |\r\n| 7 | R12_L: Lock region 12, and apply it to M-mode as well as U-mode | RO | 0x0 |\r\n| 6:5 | Reserved. | | |\r\n| 4:3 | R12_A:Address matching type for region 12.Writing an unsupported value (TOR) will set the region to OFF. | RO | 0x0 |\r\n| | Enumerated values: | | |\r\n| | Ox0OFF:Disable region | | |\r\n| | Ox2NA4: Naturally aligned 4-byte | | |\r\n| | Ox3 NAPOT:Naturally aligned power-of-two 8 bytes to 4 GiB | | |\r\n| 2 | R12_R:Read permission for region 12.Note R and X are transposed from the standard bit order due to erratum RP2350-E6 | RO | 0x0 |\r\n| 1 | R12_W: Write permission for region 12 | RO | 0x0 |\r\n| 0 | R12_X:Execute permission for region 12.Note R and X are transposed from the standard bit order due toerratum RP2350-E6 | RO | 0x0 |"} |
| {"_id": "c406", "text": "| Instruction | Cycles | Note |\r\n| Atomic Memory Operations | | |\r\n| amoswap.wrd.rs2,rs1) | 4+ | 4 per attempt.Multiple attempts if reservation is lost.4 |\r\n| amoadd.w rd,rs2.rs1) | 4+ | 4 per attempt.Multiple attempts if reservation is lost.4 |\r\n| amoxor.wrdrs2rs1) | 4+ | 4 per attempt.Multiple attempts if reservation is lost. |\r\n| amoand.w rdrs2rs1) | 4+ | 4 per attempt. Multiple attempts if reservation is lost. |\r\n| amoor.rd,rs2rs1 | 4+ | 4 per attempt.Multiple attempts if reservation is lost. |\r\n| amomin.w rd.rs2.rs1 | 4+ | 4 per attempt.Multiple attempts if reservation is lost.4 |\r\n| amomax.rd.rs2.rs1) | 4+ | 4 per attempt.Multiple attempts if reservation is lost.4 |\r\n| amominu.w rd,rs2,rs1) | 4+ | 4 per attempt.Multiple attempts if reservation is lost.4 |\r\n| amomaxu.wrd,rs2,rs1) | 4+ | 4 per attempt.Multiple attempts if reservation is lost.4 |"} |
| {"_id": "c84", "text": "3.135V to 3.63V supply\r\n1.1V supply\r\n100nF\r\nGND\r\n100nF\r\nGND\r\n100nF\r\nGND\r\n4.7\u00b5F\r\nGND\r\nGND DVDD\r\nDVDD DVDD VREG_PGND VREG_LX VREG_AVDD VREG_VIN VREG_FB\r\nFigure 21. External\r\ncore supply with on\u0002chip regulator\r\ndisabled.\r\nThe on-chip regulator will still power on as soon as VREG_VIN and VREG_AVDD are available, but can be shut down under\r\nsoftware control after the chip is out of reset. This is a safe mode of operation, though the regulator will consume\r\napproximately 400 \u00b5A until it\u2019s shut down. The regulator should be shut down by writing a 1 to the VREG register\u2019s HIZ\r\nfield.\r\n6.3.8. External components and PCB layout requirements\r\nThe most critical part of an RP2350 PCB layout is the core voltage regulator. This should be placed first on any board\r\ndesign and these guidelines must be strictly followed.\r\nRP2350 Datasheet\r\n6.3. Core voltage regulator 45"} |
| {"_id": "c371", "text": "| | | Machine-mode instruction retire counter, low half | | |\r\n| 414. STRETH Register | Bits | Description | Type | Reset |\r\n| | 31:0 | Counts up once per 1 << 32 instructions, when mcountinhibit.ir is 0.Disabled by default to save power. | RW | 0x00000000 |"} |
| {"_id": "c388", "text": "| | | 12.6.3.1.Aliases and triggers | | | |\r\n| Table 1745. Control egister aliases. Each | Offset | +0x0 | +0x4 | +0x8 | +0xc (Trigger) |\r\n| channel has four control/status | ex (Alias 0) | READ_ADDR | WRITE_ADOR | TRANS_COUNT | CTRL_TRIG |\r\n| egisters. Each egister can be | 0x10 (Alias 1) | CTRL | READ_ADOR | WRITE_ACOR | TRANS_COUNT_TRIG |\r\n| sccessed at multiple fifferent addresses. In | 0x20 (Alias 2) | CTRL | TRANS_COUNT | READ_ADOR | WRITE_ADDR TRIG |\r\n| Nach naturally-aligned group of four, all four | 0x30 Alias3 | CTRL | WRITE_ADOR | TRANS_COUNT | READ_ADO_TRIG |\r\negisters appear, in"} |
| {"_id": "c495", "text": "4.\r\n| ESTART_DET | Bits | Description | Type | Reset |\r\n| | 31:1 | Reserved. | | |\r\n| | 0 | CLR_RESTART_DET:Read this register to clear the RESTART_DET interrupt bit 12) of IC_RAW_INTR_STAT register. Reset value:Ox0 | RO | 0x0 |"} |
| {"_id": "c30", "text": "(Return to index)\r\n3.8.1.15. Zba: bit manipulation (address generation)\r\nThese instructions accelerate address generation for arrays of 2, 4 and 8-byte elements. They can also multiply by\r\nconstant values 3, 5 and 9 if that is more your style.\r\nsh1add\r\nAdd, with the first addend shifted left by 1.\r\nUsage:\r\nsh1add rd, rs1, rs2\r\nOperation:\r\nrd <= (rs1 << 1) + rs2;\r\nsh2add\r\nAdd, with the first addend shifted left by 2.\r\nUsage:\r\nsh2add rd, rs1, rs2\r\nOperation:\r\nrd <= (rs1 << 2) + rs2;\r\nsh3add\r\nAdd, with the first addend shifted left by 3.\r\nUsage:\r\nsh3add rd, rs1, rs2\r\nOperation:\r\nrd <= (rs1 << 3) + rs2;\r\n3.8.1.16. Zbb: bit manipulation (basic)\r\nThese instructions are useful for bitfield manipulation, and complex integer arithmetic, such as in soft floating point\r\nroutines. Many of them substitute directly for common pairs of RV32I instructions, like zext.h \u2192 sll, srl.\r\nRP2350 Datasheet\r\n3.8. Hazard3 processor"} |
| {"_id": "c316", "text": ". . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919\r\n11.6.3. UART TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921\r\n11.6.4. UART RX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923\r\n11.6.5. Manchester serial TX and RX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926\r\n11.6.6. Differential Manchester (BMC) TX and RX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929\r\n11.6.7. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932\r\n11.6.8. PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ."} |
| {"_id": "c408", "text": ".\r\n\u2022 DMA channels below the least-set effective permission bit (ignoring SU when SP is clear, and ignoring NSU when NSP\r\nis clear) are disconnected from that peripheral\u2019s DREQ signals.\r\n10.6.2.3. Blocks without bus access control\r\nThere are four memory-mapped blocks which do not have bus access control registers in ACCESSCTRL:\r\n\u2022 The Cortex-M PPB is internal to the processors, and is banked internally over Secure/Non-secure.\r\n\u2022 The SIO is also banked internally over Secure/Non-secure access.\r\n\u2022 ACCESSCTRL itself is always world-readable and has its own internal filtering for writes.\r\n\u2022 Boot RAM is hardwired for Secure access only.\r\n10.6.3. List of registers\r\nThe ACCESSCTRL registers start at a base address of 0x40060000 (defined as ACCESSCTRL_BASE in the SDK).\r\nRP2350 Datasheet\r\n10.6. Access control 82"} |
| {"_id": "c490", "text": "GPIO17_LEVEL_HIGH RW 0x0\r\n4 GPIO17_LEVEL_LOW RW 0x0\r\n3 GPIO16_EDGE_HIGH RW 0x0\r\n2 GPIO16_EDGE_LOW RW 0x0\r\n1 GPIO16_LEVEL_HIGH RW 0x0\r\n0 GPIO16_LEVEL_LOW RW 0x0\r\nIO_BANK0: DORMANT_WAKE_INTF3 Register\r\nOffset: 0x2fc\r\nRP2350 Datasheet\r\n9.11. List of registers"} |
| {"_id": "c491", "text": "0 HOST_CONN_DIS: Host: raised when a device is connected or disconnected\r\n(i.e. when SIE_STATUS.SPEED changes). Cleared by writing to\r\nSIE_STATUS.SPEED\r\nRO 0x0\r\nUSB: INTE Register\r\nOffset: 0x090\r\nDescription\r\nInterrupt Enable\r\nTable 1218. INTE\r\nRegister\r\nBits Description Type Reset\r\n31:24 Reserved. - -\r\n23 EPX_STOPPED_ON_NAK: Source: NAK_POLL.EPX_STOPPED_ON_NAK RW 0x0\r\n22 DEV_SM_WATCHDOG_FIRED: Source: DEV_SM_WATCHDOG.FIRED RW 0x0\r\n21 ENDPOINT_ERROR: Source: SIE_STATUS.ENDPOINT_ERROR RW 0x0\r\n20 RX_SHORT_PACKET: Source: SIE_STATUS.RX_SHORT_PACKET RW 0x0\r\n19 EP_STALL_NAK: Raised when any bit in EP_STATUS_STALL_NAK is set. Clear\r\nby clearing all bits in EP_STATUS_STALL_NAK.\r\nRW 0x0\r\n18 ABORT_DONE: Raised when any bit in ABORT_DONE is set. Clear by clearing\r\nall bits in ABORT_DONE.\r\nRW 0x0\r\n17 DEV_SOF: Set every time the device receives a SOF (Start of Frame) packet.\r\nCleared by reading SOF_RD\r\nRW 0x0\r\nRP2350 Datasheet\r\n12.7. USB 117"} |
| {"_id": "c280", "text": "To make the programming model of Secure and Non-secure software consistent, and to avoid overhead in Non-secure\r\ncode, RP2350 extends Secure/Non-secure separation throughout the system. For example, DMA channels can be\r\nassigned for Secure or Non-secure use. Using this extended separation, Non-secure code can use DMA transfers to\r\naccelerate peripheral accesses without endangering security model invariants (such as Non-secure code using the DMA\r\nto read Secure memory).\r\nThe key hardware features that enable Secure/Non-secure separation throughout the system are:\r\n\u2022 The Cortex-M33\u2019s implementation of the Secure and Non-secure states (Section 10.2)\r\n\u2022 The DMA\u2019s implementation of matching per-channel security states (Section 10.7)\r\n\u2022 The system-level bus access filtering implemented by ACCESSCTRL (Section 10.6)\r\n\u2022 Peripheral-level filtering, such as the per-GPIO access filtering of the SIO GPIO registers (Section 3.1.1)\r\n10.2. Processor security features (Arm)\r\nThe Cortex-M33 processors on RP2350 are configured with the following standard Arm security features:\r\n\u2022 Support for the Armv8-M Security extension\r\n\u2022 8\u00d7 security attribution unit (SAU) regions\r\n\u2022 8\u00d7 Secure and 8\u00d7 Non-secure memory protection unit (MPU) regions\r\nThese features are covered exhaustively in the Armv8-M Architecture Reference Manual, the Cortex-M33 Technical\r\nReference Manual, and the Cortex-M33 section of this datasheet (Section 3.7). This section gives a high-level overview\r\nof these features, as well as a description of the implementation-defined attribution unit included in RP2350.\r\n10.2.1. Background\r\nThe Cortex-M33 processors on RP2350 support the Armv8-M Security Extension. Hardware in the processor maintains\r\ntwo separate execution contexts, called the Secure and Non-secure domains. Access to important data, such as\r\ncryptographic keys, or hardware, such as the system voltage regulator, can be limited to the Secure domain. Separating\r\nexecution into these domains prevents Non-secure execution from interfering with Secure execution. When this\r\ndatasheet uses the (capitalised) terms Secure and Non-secure, we refer to these two Arm security domains and the\r\nassociated bus attributes.\r\nCode running in the Non-secure domain is not necessarily malicious. Consider complex protocols and stacks like USB,\r\nwhose implementation is expected to be"} |
| {"_id": "c356", "text": "0 DIV_FRAC\r\nCounter enable\r\n3 DIV_INT\r\nCounter enable\r\n.5 DIV_FRAC\r\nCounter enable\r\n2 DIV_INT\r\nFigure 119. The clock\r\ndivider generates an\r\nenable signal. The\r\ncounter only counts on\r\ncycles where this\r\nsignal is high. A clock\r\ndivisor of 1 causes the\r\nenable to be asserted\r\non every cycle, so the\r\ncounter counts by one\r\non every system clock\r\ncycle. Higher divisors\r\ncause the count\r\nenable to be asserted\r\nless frequently.\r\nFractional division\r\nachieves an average\r\nfractional counting\r\nrate by spacing some\r\nenable pulses further\r\napart than others.\r\nThe fractional divider is a first-order delta-sigma type.\r\nThe clock divider also extends the effective count range when using level-sensitive or edge-sensitive modes to take duty\r\ncycle or frequency measurements.\r\n12.5.2.5. Level-sensitive and edge-sensitive triggering\r\nThe PWM provides the following counter modes:\r\n\u2022 Default free-running, counting continuously whenever the slice is enabled (free-running)\r\n\u2022 Count continuously when a high level is detected on the B pin (level sensitive)\r\n\u2022 Count once with each rising edge detected on the B pin (rising edge-sensitive)\r\n\u2022 Count once with each falling edge detected on the B pin (falling edge-sensitive)\r\nRP2350 Datasheet\r\n12.5. PWM 108"} |
| {"_id": "c76", "text": "| Description | If ECC row programming is interrupted, an ECC row may contain a value that fails ECC validation. Because any ECC could potentially contain an invalid,partially written value, the bootrom uses a separate enable flag in OTP to indicate whether a particular ECC row is expected to contain a valid value.The user is expected to only set this flag after a particular ECC row is known to have been written correctly. |\r\n| | For FLASH_PARTITION_SLOT_SIZE the \"enable\" flag is BOOT_FLAGSO.OVERRIDE_FLASH_PARTITION_SLOT_SIZE |\r\n| | In the case of FLASH_PARTITION_SLOT_SIZE,the bootrom reads the row value and asserts the value is valid before checking the enable flag, and thus the boot process will hang if the BOOT_FLAGS0.OVERRIDE_FLASH_PARTITION_SLOT_SIZE row in OTP contains an invalid ECC value |\r\n| Workaround | Don't program FLASH_PARTITiON_SLOT_SIZE or at least be aware that doing so may brick your device if the programming operation is interrupted or fails. |\r\n| Fixed by | RP2350A4 bootrom,Documentation |"} |
| {"_id": "c461", "text": "Description\r\nInterrupt status after masking & forcing for dormant_wake\r\nTable 816.\r\nDORMANT_WAKE_INT\r\nS4 Register\r\nBits Description Type Reset\r\n31 GPIO39_EDGE_HIGH RO 0x0\r\n30 GPIO39_EDGE_LOW RO 0x0\r\n29 GPIO39_LEVEL_HIGH RO 0x0\r\n28 GPIO39_LEVEL_LOW RO 0x0\r\n27 GPIO38_EDGE_HIGH RO 0x0\r\n26 GPIO38_EDGE_LOW RO 0x0\r\n25 GPIO38_LEVEL_HIGH RO 0x0\r\n24 GPIO38_LEVEL_LOW RO 0x0\r\n23 GPIO37_EDGE_HIGH RO 0x0\r\n22 GPIO37_EDGE_LOW RO 0x0\r\n21 GPIO37_LEVEL_HIGH RO 0x0\r\n20 GPIO37_LEVEL_LOW RO 0x0\r\n19 GPIO36_EDGE_HIGH RO 0x0\r\n18 GPIO36_EDGE_LOW RO 0x0\r\n17 GPIO36_LEVEL_HIGH RO 0x0\r\n16 GPIO36_LEVEL_LOW RO 0x0\r\n15 GPIO35_EDGE_HIGH RO 0x0\r\n14 GPIO35_EDGE_LOW RO 0x0\r\n13 GPIO35_LEVEL_HIGH RO 0x0\r\n12 GPIO35_LEVEL_LOW RO 0x0\r\n11 GPIO34_EDGE_HIGH RO 0x0\r\n10 GPIO34_EDGE_LOW RO 0x0\r\n9 GPIO34_LEVEL_HIGH RO 0x0\r\n8 GPIO34_LEVEL_LOW RO 0x0\r\n7 GPIO33_EDGE_HIGH RO 0x0\r\n6 GPIO33_EDGE_LOW RO 0x0\r\n5 GPIO33_LEVEL_HIGH RO 0x0\r\n4 GPIO33_LEVEL_LOW RO 0x0\r\n3 GPIO32_EDGE_HIGH RO 0x0\r\n2 GPIO32_EDGE_LOW RO 0x0\r\n1 GPIO32_LEVEL_HIGH RO 0x0\r\n0 GPIO32_LEVEL_LOW RO 0x0\r\nIO_BANK0: DORMANT_WAKE_INTS5 Register\r\nOffset: 0x31c\r\nRP2350 Datasheet\r\n9.11. List of registers 75"} |
| {"_id": "c497", "text": "and at what security/privilege levels they can\r\ndo so.\r\nDefaults to Secure, Privileged processor or debug access only.\r\nThis register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which\r\nbecomes Non-secure-Privileged-writable when the NSP bit is set.\r\nTable 957. TRNG\r\nRegister\r\nBits Description Type Reset\r\n31:8 Reserved. - -\r\n7 DBG: If 1, TRNG can be accessed by the debugger, at security/privilege levels\r\npermitted by SP/NSP/SU/NSU in this register.\r\nRW 0x1\r\n6 DMA: If 1, TRNG can be accessed by the DMA, at security/privilege levels\r\npermitted by SP/NSP/SU/NSU in this register.\r\nRW 0x0\r\n5 CORE1: If 1, TRNG can be accessed by core 1, at security/privilege levels\r\npermitted by SP/NSP/SU/NSU in this register.\r\nRW 0x1\r\n4 CORE0: If 1, TRNG can be accessed by core 0, at security/privilege levels\r\npermitted by SP/NSP/SU/NSU in this register.\r\nRW 0x1\r\n3 SP: If 1, TRNG can be accessed from a Secure, Privileged context. RW 0x1\r\n2 SU: If 1, and SP is also set, TRNG can be accessed from a Secure, Unprivileged\r\ncontext.\r\nRW 0x0\r\n1 NSP: If 1, TRNG can be accessed from a Non-secure, Privileged context. RW 0x0\r\nRP2350 Datasheet\r\n10.6. Access control 85"} |
| {"_id": "c211", "text": "\u2022 ITM: DWT and ITM trace\r\n\u2022 ETM: ETM trace\r\n\u2022 MTB: no MTB trace\r\n\u2022 WIC: Wake up interrupt controller\r\n\u2022 WICLINES: 55: All external interrupts and 3 internal events: NMI, RVEX, Debug\r\n\u2022 CTI: Cross trigger interface\r\n\u2022 RAR: reset all registers on power up\r\n\u2022 UNCROSS_I_D: Modify internal address map\r\n\u2022 SBIST: no SBIST features\r\n\u2022 CDE modules not used\r\n\u2022 CDERTLID: RTL ID for system with multi Cortex-M33: 16\r\nArchitectural clock gating allows the processor core to support SLEEP and DEEPSLEEP power states by disabling the\r\nclock to parts of the processor core. Power gating is not supported.\r\nEach Cortex-M33 core has its own interrupt controller that can individually mask out interrupt sources as required. The\r\nsame interrupts route to both Cortex-M33 cores.\r\nThe processor supports the following interfaces:\r\n\u2022 Code AHB (C-AHB) interface\r\n\u2022 System AHB (S-AHB) interface\r\n\u2022 External PPB (EPPB) APB interface\r\n\u2022 Debug AHB (D-AHB) interface\r\nThe processor implements the following optional interfaces:\r\n\u2022 Arm TrustZone technology, using the Armv8-M Security Extension supporting Secure and Non-secure states\r\n\u2022 Memory Protection Units (MPUs), which you can configure to protect regions of memory\r\n\u2022 Floating-point arithmetic functionality with support for single precision arithmetic\r\n\u2022 Support for ETM trace\r\n3.7.2.1. Modifications by Raspberry Pi\r\n3.7.2.1.1. UNCROSS_I_D\r\nThe original Cortex-M33 processor design routes the following operations to either the Code or System port:\r\n\u2022 instruction fetch\r\n\u2022 load/stores\r\n\u2022 debugger accesses\r\nAccesses below address 0x20000000 route to the Code port. All other accesses route to the System port.\r\nThis routing strategy makes contention possible on both the internal bus matrix and the main system AHB5 crossbar.\r\nThe Cortex-M33 Technical Reference Manual describes this strategy in detail.\r\nIn RP2350, Raspberry Pi modified the Cortex-M33 bus matrix to:\r\n\u2022 route all instruction fetch operations to the Code port\r\nRP2350 Datasheet\r\n3.7. Cortex-M33 processor"} |
| {"_id": "c101", "text": "| 168. INTE1 | Bits | Description | Type | Reset |\r\n| | 31:16 | Reserved. | | |\r\n| | | Set bit n to pass interrupts from channel n to DMA IRQ 1. | | |\r\n| | 15:0 | Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ1. | RW | Ox0000 |"} |
| {"_id": "c334", "text": "O uls Tegister is nardwired to oxI..\r\n| | CLOCKS:CLK_GPOUT2_CTRLRegister | | |\r\n| | Offset:0x18 Description | | |\r\n| | Clock control,can be changed on-the-fly (except for auxsrc) | | |\r\n| Bits | Description | Type | Reset |\r\n| 31:29 | Reserved. | | |\r\n| 28 | ENABLED:clock generator is enabled | RO | 0x0 |\r\n| 27:21 | Reserved. | | |\r\n| 20 | NUDGE: An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time | RW | 0x0 |\r\n| 19:18 | Reserved. | | |\r\n| 17:16 | PHASE: This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect | RW | 0x0 |\r\n| 15:13 | Reserved. | | |\r\n| 12 | DC50: Enables duty cycle correction for odd divisors,can be changed on-the- fly | RW | 0x0 |\r\n| 11 | ENABLE: Starts and stops the clock generator cleanly | RW | 0x0 |\r\n| 10 | KILL: Asynchronously kills the clock generator,enable must be set low before deasserting kill | RW | 0x0 |\r\n| 9 | Reserved. | | |\r\n| 8:5 | AUxsRc: Selects the auxiliary clock source,will glitch when switching | RW | 0x0 |\r\n| | Enumerated values: | | |\r\n| | Ox0CLKSRC_PLL_SYS | | |\r\n| | 0x1CLKSRC_GPINO | | |\r\n| | 0x2CLKSRC_GPIN1 | | |\r\n| | Ox3CLKSRC_PLL_USB | | |\r\n| | 0x4-CLKSRC_PLL_USB_PRIMARY_REF_OPCG | | |"} |
| {"_id": "c475", "text": "RT0 can be accessed from a Secure, Privileged context. RW 0x1\r\n2 SU: If 1, and SP is also set, UART0 can be accessed from a Secure,\r\nUnprivileged context.\r\nRW 0x1\r\n1 NSP: If 1, UART0 can be accessed from a Non-secure, Privileged context. RW 0x0\r\n0 NSU: If 1, and NSP is also set, UART0 can be accessed from a Non-secure,\r\nUnprivileged context.\r\nThis bit is writable from a Non-secure, Privileged context, if and only if the NSP\r\nbit is set.\r\nRW 0x0\r\nACCESSCTRL: UART1 Register\r\nOffset: 0xa4\r\nDescription\r\nControl whether debugger, DMA, core 0 and core 1 can access UART1, and at what security/privilege levels they can\r\ndo so.\r\nDefaults to Secure access from any master.\r\nThis register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which\r\nbecomes Non-secure-Privileged-writable when the NSP bit is set.\r\nRP2350 Datasheet\r\n10.6. Access control 85"} |
| {"_id": "c336", "text": "R1,R2,R0\r\nMLA R0,R1,R2,R3\r\nMLA R3,R1,R2,R0\r\n...\r\nUMLAL R0,R1,R4,R5\r\nUMLAL R2,R3,R6,R7\r\nUMLAL R0,R1,R4,R5\r\nUMLAL R2,R3,R6,R7\r\n...\r\nThe multiplier requires its multiply operands on cycle n, requires its accumulate operand (if any) on cycle n+1, and\r\nmakes its result available on cycle n+2.\r\nAs a further example, the following sequence completes in 4 cycles:\r\nRP2350 Datasheet\r\n3.7. Cortex-M33 processor"} |
| {"_id": "c440", "text": "| Bits | Description | Type | Reset |\r\n| | NSU: If 1, and NSP is also set, SRAM5 can be accessed from a Non-secure Unprivileged context. | | |\r\n| | This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. | RW | 0x1 |"} |
| {"_id": "c173", "text": "| | IO_BANK0:IRQSUMMARY_PROC1_NONSECURE1 Register Offset:0x21c | | |\r\n| Bits | Description | Type | Reset |\r\n| 31:16 | Reserved. | | |\r\n| 15 | GPIO47 | RO | 0x0 |\r\n| 14 | GPI046 | RO | 0x0 |\r\n| 13 | GPI045 | RO | 0x0 |\r\n| 12 | GPI044 | RO | 0x0 |\r\n| 11 | GPI043 | RO | 0x0 |\r\n| 10 | GPI042 | RO | 0x0 |\r\n| 9 | GPIO41 | RO | 0x0 |\r\n| 8 | GPIO40 | RO | 0x0 |\r\n| 7 | GPI039 | RO | 0x0 |"} |
| {"_id": "c2", "text": "| | Note that when an Arm core is deselected, its cold reset domain is also held in reset, since in particular the SYSRESETREQ bit becomes inaccessible once the core is deselected.Note also the RiSC-V cores do not have a cold reset domain, since their corresponding controls are located in the Debug Module | | |\r\n| Bits | Description | Type | Reset |\r\n| 31:2 | Reserved. | | |\r\n| 1 | CORE1:Select architecture for core 1. | RW | 0x0 |\r\n| | Enumerated values: | | |\r\n| | Ox0ARM:Switch core1 to ArmCortex-M33 | | |\r\n| | Ox1RISCV:Switch core 1 to RISC-V Hazard3) | | |\r\n| 0 | COREo:Select architecture for core 0 | RW | 0x0 |\r\n| | Enumerated values: | | |\r\n| | Ox0ARM:Switch core 0 to ArmCortex-M33 | | |\r\n| | Ox1RISCV:Switch core O to RISC-V Hazard3) | | |"} |
| {"_id": "c333", "text": "X R14 (but not BX to any other register or MOV R15,R14)\r\n\u2022 PrevInst is 16 bits long\r\n\u2022 PrevInst was executed sequentially (i.e., not itself branched to), or PrevInst is word-aligned\r\n\u2022 PrevInst itself was not itself folded with a previous instruction\r\nIf any of the above conditions are not true, F is 0.\r\nK\r\n1 when it is known that the branch will execute prior to executing PrevInst; 0 otherwise. In other words, K is 1 unless\r\nthe branch is conditional and PrevInst sets the flags.\r\nFor example, the following delay loop takes 299 cycles:\r\n10000002: MOVS R5,#100\r\n10000004: SUBS R5,R5,#1\r\n10000006: BNE 0x10000004\r\nThose cycles come from the following timings:\r\n\u2022 1 cycle for MOVS R5,#100\r\n\u2022 1 cycle for each SUBS R5,R5,#1\r\n\u2022 2 cycles each for the first 99 BNE instructions (L=U=0, F=1, K=0)\r\n\u2022 0 cycles for the last, non-taken, BNE (L=U=0, F=1, K=0, using the formula 1-F)\r\nAt a different alignment, the same delay loop takes 300 cycles:\r\nRP2350 Datasheet\r\n3.7. Cortex-M33 processor"} |
| {"_id": "c409", "text": "1 D0 Nak\r\nFigure 78. Master S\r\nReceiver - TX FIFO\r\nEmpties/STOP\r\nGeneration\r\nFigure 79 and Figure 80 illustrate configurations where the user can control the generation of RESTART conditions on\r\nthe I2C bus. If bit 10 (Restart) of the IC_DATA_CMD register is set and the restart capability is enabled (IC_RESTART_EN=1),\r\na RESTART is generated before the data byte is written to or read from the slave. If the restart capability is not enabled,\r\na STOP followed by a START is generated in place of the RESTART. Figure 79 illustrates this situation during operation\r\nas a master transmitter.\r\nRP2350 Datasheet\r\n12.2. I2C 99"} |
| {"_id": "c70", "text": "Clock Description Nominal Frequency\r\nclk_sys System clock that is always running\r\nunless in DORMANT mode. Runs from\r\nclk_ref at power-up, but is typically\r\nswitched to a PLL.\r\n150MHz\r\nclk_peri Peripheral clock. Typically runs from\r\nclk_sys but allows peripherals to run at\r\na consistent speed if clk_sys is\r\nchanged by software.\r\n12 - 150MHz\r\nclk_usb USB reference clock. Must be 48MHz. 48MHz\r\nclk_adc ADC reference clock. Must be 48MHz. 48MHz\r\nclk_hstx HSTX clock. 150MHz\r\nFor a full list of clock sources for each clock generator, see the appropriate CTRL register. For example, CLK_SYS_CTRL.\r\n8.1.3.2. Multiplexers\r\nAll clock generators have a multiplexer referred to as the auxiliary (aux) mux. This mux has a conventional design\r\nwhose output will glitch when changing the select control. The reference clock (clk_ref) and the system clock (clk_sys)\r\nhave an additional multiplexer referred to as the glitchless mux. The glitchless mux can switch between clock sources\r\nwithout generating a glitch on the output.\r\nBefore switching the clock source of an auxiliary mux you must either:\r\n\u2022 Temporarily switch the glitchless mux away from aux (if a glitchless mux is available).\r\n\u2022 Temporarily disable the clock generator using its CTRL_ENABLE bit.\r\n\u2022 Hold the destination in reset so that a potential clock glitch doesn\u2019t cause undefined operation.\r\nFailure to do at least one of the above can cause a glitch on the clock input of all hardware currently clocked by this\r\nclock generator. Avoid clock glitches at all costs; they can corrupt the logic running from the clock.\r\nClock generators require two cycles of the source clock to stop the output and two cycles of the new source to restart\r\nthe output. Wait for the generator to stop before changing the auxiliary mux. When the destination clock is much slower\r\nthan the system clock, there is a danger that software changes the aux mux source before the clock generator has\r\ncome to a safe halt. Avoid this by polling the clock generator\u2019s CTRL_ENABLED status until it matches the value of\r\nCTRL_ENABLE.\r\nThe glitchless mu"} |
| {"_id": "c209", "text": "Write transfer format configuration for memory address window 0/1.\r\n| | Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases.Only 24-bit addresses are supported. | | |\r\n| | The reset value of the Mx_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_wRITABLE_Mx bit for this window, as XIP memory is read-only by default. | | |\r\n| Bits | Description | Type | Reset |\r\n| 31:29 | Reserved. | | |\r\n| | DTR: Enable double transfer rate (DTR) for write commands: address,suffix and write data phases are active on both edges of SCK.SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch | | |\r\n| 28 | If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even. number of SCK edges DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. | RW | 0x0 |\r\n| 27:19 | Reserved. | | |\r\n| 18:16 | DUMMy_LEN: Length of dummy phase between command suffix and data phase, in units of 4 bits.(i.e.1 cycle for quad width,2 for dual, 4 for single) | RW | 0x0 |\r\n| | Enumerated values: | | |\r\n| | Ox0NONE:No dummy phase | | |\r\n| | 0x14:4 dummy bits | | |\r\n| | 0x2-8:8 dummy bits | | |\r\n| | 0x3-12:12 dummy bits | | |\r\n| | 0x416:16 dummy bits | | |\r\n| | 0x520:20 dummy bits | | |\r\n| | 0x6 24:24 dummy bits | | |\r\n| | 0x728:28 dummy bits | | |\r\n| 15:14 | SUFFIX_LEN:Length of post-address command suffix, in units of 4 bits.(i.e.1 cycle for quad width,2 for dual, 4 for single Only values of 0 and 8 bits are supported | RW | 0x0 |"} |
| {"_id": "c63", "text": "Table 18. CPUID\r\nRegister\r\nBits Description Type Reset\r\n31:0 Value is 0 when read from processor core 0, and 1 when read from processor\r\ncore 1.\r\nRO -\r\nSIO: GPIO_IN Register\r\nOffset: 0x004\r\nTable 19. GPIO_IN\r\nRegister\r\nBits Description Type Reset\r\n31:0 Input value for GPIO0\u202631.\r\nIn the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as\r\nzero.\r\nRO 0x00000000\r\nSIO: GPIO_HI_IN Register\r\nOffset: 0x008\r\nDescription\r\nInput value on GPIO32\u202647, QSPI IOs and USB pins\r\nIn the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero.\r\nTable 20. GPIO_HI_IN\r\nRegister\r\nBits Description Type Reset\r\n31:28 QSPI_SD: Input value on QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins RO 0x0\r\n27 QSPI_CSN: Input value on QSPI CSn pin RO 0x0\r\n26 QSPI_SCK: Input value on QSPI SCK pin RO 0x0\r\n25 USB_DM: Input value on USB D- pin RO 0x0\r\n24 USB_DP: Input value on USB D+ pin RO 0x0\r\n23:16 Reserved. - -\r\n15:0 GPIO: Input value on GPIO32\u202647 RO 0x0000\r\nSIO: GPIO_OUT Register\r\nOffset: 0x010\r\nDescription\r\nGPIO0\u202631 output value\r\nRP2350 Datasheet\r\n3.1. SIO"} |
| {"_id": "c384", "text": "a delay of SPKLEN + 2 ic_clk cycles, where SPKLEN is\r\nIC_FS_SPKLEN if the component is operating in SS or FS.\r\n\u25e6 Whenever SCL is driven one to zero by the DW_apb_i2c (completing the SCL high time) an internal logic latency of\r\nthree ic_clk cycles is incurred. Consequently, the minimum SCL low time of which the DW_apb_i2c is capable is\r\nnine ic_clk periods (7 + 1 + 1), while the minimum SCL high time is thirteen ic_clk periods (6 + 1 + 3 + 3).\r\nRP2350 Datasheet\r\n12.2. I2C 100"} |
| {"_id": "c93", "text": "X data is sampled at 48MHz, giving 4\r\nclock cycles to capture and filter the bus state. The line state detection module distributes the filtered RX data to the\r\nSerial RX Engine.\r\n12.7.3.5. Serial RX engine\r\nThe serial receive (RX) engine decodes receive data captured by the line state detection module. It produces the\r\nfollowing information:\r\n\u2022 The PID of the incoming data packet\r\n\u2022 The device address for the incoming data\r\n\u2022 The device endpoint for the incoming data\r\n\u2022 Data bytes\r\nThe serial receive engine also detects errors in RX data by performing a CRC check on the incoming data. Any errors are\r\nsignalled to the other hardware blocks and can raise an interrupt.\r\nRP2350 Datasheet\r\n12.7. USB 114"} |
| {"_id": "c485", "text": ". . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888\r\n11.3.6. Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888\r\n11.3.7. Pseudo-instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889\r\n11.4. Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889\r\n11.4.1. Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889\r\n11.4.2. JMP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890\r\n11.4.3. WAIT . . . . . . . . . . ."} |
| {"_id": "c185", "text": "ROSC and stop the PLLs.\r\n2. Choose an oscillator (XOSC or ROSC). Write a specific 32-bit value to the DORMANT register of the chosen oscillator to\r\nstop it.\r\nWhen exiting DORMANT mode, the chosen oscillator will restart. If you chose XOSC, the frequency will be more precise,\r\nbut the restart will take more time due to startup delay (>1ms on the RP2350 reference design (see Hardware design\r\nwith RP2350, Minimal Design Example)). If you chose ROSC, the frequency will be less precise, but the start-up time is\r\nvery short (approximately 1\u03bcs). See Section 6.5.3.1, \u201cWaking from the DORMANT state\u201d for the events which cause the\r\nsystem to exit DORMANT mode.\r\n\uf05a NOTE\r\nYou must stop the PLLs before entering DORMANT mode.\r\nPico Extras: https://github.com/raspberrypi/pico-extras/blob/master/src/rp2_common/hardware_rosc/rosc.c Lines 56 - 61\r\n56 void rosc_set_dormant(void) {\r\n57 // WARNING: This stops the rosc until woken up by an irq\r\n58 rosc_write(&rosc_hw->dormant, ROSC_DORMANT_VALUE_DORMANT);\r\n59 // Wait for it to become stable once woken up\r\n60 while(!(rosc_hw->status & ROSC_STATUS_STABLE_BITS));\r\n61 }\r\nRP2350 Datasheet\r\n8.3. Ring oscillator (ROSC) 56"} |
| {"_id": "c33", "text": "RVCSR:MSTATOSRegister\r\n| Description | Offset0x300 Machine status register | | |\r\n| Bits | Description | Type | Reset |\r\n| 31:22 | Reserved. | | |\r\n| 21 | TW: Timeout wait.When 1, attempting to execute a WFl instruction in U-mode will instantly cause an illegal instruction exception.. | RW | 0x0 |\r\n| 20:18 | Reserved | | |\r\n| 17 | MPRV: Modify privilege.If 1, loads and stores behave as though the current privilege level were epp.This includes physical memory protection checks,and the privilege level asserted on the system bus alongside the load/store address. | RW | 0x0 |\r\n| 16:13 | Reserved. | | |\r\n| 12:11 | MPP:Previous privilege level.Can store the values 3 (M-mode) or 0 (U-mode) If another value is written,hardware rounds to the nearest supported mode | RW | 0x3 |\r\n| 10:8 | Reserved, | | |\r\n| 7 | MPIE:Previous interrupt enable.Readable and writable.Is set to the current value of mstatus.nie on trap entry.Is set to 1 on trap return. | RW | 0x0 |\r\n| 6:4 | Reserved. | | |\r\n| 3 | MIE:Interrupt enable.Readable and writable.Is set to O on trap entry.Is set to the current value of mstatus.mpie on trap return | RW | 0x0 |\r\n| 2:0 | Reserved. | | |"} |
| {"_id": "c77", "text": "Bits Description Type Reset\r\n27 CLK_SYS_ROM RW 0x1\r\n26 CLK_SYS_RESETS RW 0x1\r\n25 CLK_SYS_PWM RW 0x1\r\n24 CLK_SYS_POWMAN RW 0x1\r\n23 CLK_REF_POWMAN RW 0x1\r\n22 CLK_SYS_PLL_USB RW 0x1\r\n21 CLK_SYS_PLL_SYS RW 0x1\r\n20 CLK_SYS_PIO2 RW 0x1\r\n19 CLK_SYS_PIO1 RW 0x1\r\n18 CLK_SYS_PIO0 RW 0x1\r\n17 CLK_SYS_PADS RW 0x1\r\n16 CLK_SYS_OTP RW 0x1\r\n15 CLK_REF_OTP RW 0x1\r\n14 CLK_SYS_JTAG RW 0x1\r\n13 CLK_SYS_IO RW 0x1\r\n12 CLK_SYS_I2C1 RW 0x1\r\n11 CLK_SYS_I2C0 RW 0x1\r\n10 CLK_SYS_HSTX RW 0x1\r\n9 CLK_HSTX RW 0x1\r\n8 CLK_SYS_GLITCH_DETECTOR RW 0x1\r\n7 CLK_SYS_DMA RW 0x1\r\n6 CLK_SYS_BUSFABRIC RW 0x1\r\n5 CLK_SYS_BUSCTRL RW 0x1\r\n4 CLK_SYS_BOOTRAM RW 0x1\r\n3 CLK_SYS_ADC RW 0x1\r\n2 CLK_ADC_ADC RW 0x1\r\n1 CLK_SYS_ACCESSCTRL RW 0x1\r\n0 CLK_SYS_CLOCKS RW 0x1\r\nCLOCKS: WAKE_EN1 Register\r\nOffset: 0xb0\r\nDescription\r\nenable clock in wake mode\r\nTable 588. WAKE_EN1\r\nRegister\r\nBits Description Type Reset\r\n31 Reserved. - -\r\n30 CLK_SYS_XOSC RW 0x1\r\nRP2350 Datasheet\r\n8.1. Overview 54"} |
| {"_id": "c0", "text": "skilled users with suitable levels of design knowledge. Users are solely responsible for\r\ntheir selection and use of the RESOURCES and any application of the products described in them. User agrees to\r\nindemnify and hold RPL harmless against all liabilities, costs, damages or other losses arising out of their use of the\r\nRESOURCES.\r\nRPL grants users permission to use the RESOURCES solely in conjunction with the Raspberry Pi products. All other use\r\nof the RESOURCES is prohibited. No licence is granted to any other RPL or other third party intellectual property right.\r\nHIGH RISK ACTIVITIES. Raspberry Pi products are not designed, manufactured or intended for use in hazardous\r\nenvironments requiring fail safe performance, such as in the operation of nuclear facilities, aircraft navigation or\r\ncommunication systems, air traffic control, weapons systems or safety-critical applications (including life support\r\nsystems and other medical devices), in which the failure of the products could lead directly to death, personal injury or\r\nsevere physical or environmental damage (\"High Risk Activities\"). RPL specifically disclaims any express or implied\r\nwarranty of fitness for High Risk Activities and accepts no liability for use or inclusions of Raspberry Pi products in High\r\nRisk Activities.\r\nRaspberry Pi products are provided subject to RPL\u2019s Standard Terms. RPL\u2019s provision of the RESOURCES does not\r\nexpand or otherwise modify RPL\u2019s Standard Terms including but not limited to the disclaimers and warranties\r\nexpressed in them.\r\nRP2350 Datasheet\r\nLegal disclaimer notice"} |
| {"_id": "c11", "text": "| | | Provides CoreSight discovery information for the FP | | |\r\n| Ne 177. FP_PIDR6 ister | Bits | Description | Type | Reset |\r\n| | 31:0 | Reserved. | | - |"} |
| {"_id": "c415", "text": "| | | OTP_DATA:DEFAULT_BOOT_VERSIONORegister Offset:0x04e | | |\r\n| Table 1388. DEFAULT_BOOT_VERS | Bits | Description | Type | Reset |\r\n| IONO Register | 31:24 | Reserved. | | |\r\n| | 23:0 | Default boot version thermometer counter,bits 23:0 (RBIT-3) | RO | |"} |
| {"_id": "c22", "text": "| | CoreSight Component ID2 | | |\r\n| Bits | Description | Type | Reset |\r\n| 31:8 | Reserved. | | |\r\n| 7:0 | PRMBL_2:Preamble[2].Contains bits[23:16] of the component identification code. | RO | 0x05 |"} |
| {"_id": "c72", "text": "ECT\r\n| 0x18 | GPIO_QSPI_SS | | |\r\n| | PADS_QSPI:VOLTAGE_SELECT Register Offset:0x00 | | |\r\n| Bits | Description | Type | Reset |\r\n| 31:1 | Reserved. | | |\r\n| 0 | Voltage select.Per bank control | RW | 0x0 |\r\n| | Enumerated values: | | |\r\n| | 0x03V3:Set voltage to 3.3V (DVDD>=2V5 | | |\r\n| | Ox11V8:Set voltage to 1.8V DVDD1V8) | | |"} |
| {"_id": "c182", "text": "scnmnnt.cnaorescmtuigger\r\nUXI\r\n| 0 | SLEWFAST:Slew rate control.1 = Fast,0 = Slow RW | RW | RW | 0x0 |\r\n| Offset:0x10 | PADS_QSPI:GPIO_QSPI_SD2 Register | | | |\r\n| Bits | Description | | Type | Reset |\r\n| 31:9 | Reserved. | | | |\r\n| 8 | ISO:Pad isolation control.Remove this once the pad is configured by software. | | RW | 0x1 |\r\n| 7 | OD:Output disable.Has priority over output enable from peripherals | | RW | 0x0 |\r\n| 6 | IE: Input enable | | RW | 0x1 |\r\n| 5:4 | DRIVE:Drive strength. | | RW | 0x1 |\r\n| | Enumerated values: | | | |\r\n| | 0x02MA | | | |\r\n| | 0x1 4MA | | | |\r\n| | 0x28MA | | | |\r\n| | 0x312MA | | | |\r\n| 3 | PUE: Pull up enable | | RW | 0x1 |\r\n| 2 | PDE: Pull down enable | | RW | 0x0 |\r\n| 1 | SCHMITT:Enable schmitt trigger | | RW | 0x1 |\r\n| 0 | SLEwFAST:Slew rate control.1 = Fast,0 = Slow | | RW | 0x0 |"} |
| {"_id": "c131", "text": "0x0\r\nPADS_BANK0: GPIO39 Register\r\nOffset: 0xa0\r\nRP2350 Datasheet\r\n9.11. List of registers 80"} |
| {"_id": "c410", "text": "Table 1407. KEY1_2,\r\nKEY2_2, \u2026, KEY5_2,\r\nKEY6_2 Registers\r\nBits Description Type Reset\r\n31:16 Reserved. - -\r\n15:0 Bits 47:32 of OTP access key n (ECC) RO -\r\nOTP_DATA: KEY1_3, KEY2_3, \u2026, KEY5_3, KEY6_3 Registers\r\nOffsets: 0xf4b, 0xf53, \u2026, 0xf6b, 0xf73\r\nTable 1408. KEY1_3,\r\nKEY2_3, \u2026, KEY5_3,\r\nKEY6_3 Registers\r\nBits Description Type Reset\r\n31:16 Reserved. - -\r\n15:0 Bits 63:48 of OTP access key n (ECC) RO -\r\nOTP_DATA: KEY1_4, KEY2_4, \u2026, KEY5_4, KEY6_4 Registers\r\nOffsets: 0xf4c, 0xf54, \u2026, 0xf6c, 0xf74\r\nTable 1409. KEY1_4,\r\nKEY2_4, \u2026, KEY5_4,\r\nKEY6_4 Registers\r\nBits Description Type Reset\r\n31:16 Reserved. - -\r\n15:0 Bits 79:64 of OTP access key n (ECC) RO -\r\nOTP_DATA: KEY1_5, KEY2_5, \u2026, KEY5_5, KEY6_5 Registers\r\nOffsets: 0xf4d, 0xf55, \u2026, 0xf6d, 0xf75\r\nTable 1410. KEY1_5,\r\nKEY2_5, \u2026, KEY5_5,\r\nKEY6_5 Registers\r\nBits Description Type Reset\r\n31:16 Reserved. - -\r\n15:0 Bits 95:80 of OTP access key n (ECC) RO -\r\nOTP_DATA: KEY1_6, KEY2_6, \u2026, KEY5_6, KEY6_6 Registers\r\nOffsets: 0xf4e, 0xf56, \u2026, 0xf6e, 0xf76\r\nTable 1411. KEY1_6,\r\nKEY2_6, \u2026, KEY5_6,\r\nKEY6_6 Registers\r\nBits Description Type Reset\r\n31:16 Reserved. - -\r\n15:0 Bits 111:96 of OTP access key n (ECC) RO -\r\nOTP_DATA: KEY1_7, KEY2_7, \u2026"} |
| {"_id": "c193", "text": "Description\r\nInterrupt Enable for dormant_wake\r\nTable 802.\r\nDORMANT_WAKE_INT\r\nE2 Register\r\nBits Description Type Reset\r\n31 GPIO23_EDGE_HIGH RW 0x0\r\n30 GPIO23_EDGE_LOW RW 0x0\r\n29 GPIO23_LEVEL_HIGH RW 0x0\r\n28 GPIO23_LEVEL_LOW RW 0x0\r\n27 GPIO22_EDGE_HIGH RW 0x0\r\n26 GPIO22_EDGE_LOW RW 0x0\r\n25 GPIO22_LEVEL_HIGH RW 0x0\r\n24 GPIO22_LEVEL_LOW RW 0x0\r\n23 GPIO21_EDGE_HIGH RW 0x0\r\n22 GPIO21_EDGE_LOW RW 0x0\r\n21 GPIO21_LEVEL_HIGH RW 0x0\r\n20 GPIO21_LEVEL_LOW RW 0x0\r\n19 GPIO20_EDGE_HIGH RW 0x0\r\n18 GPIO20_EDGE_LOW RW 0x0\r\n17 GPIO20_LEVEL_HIGH RW 0x0\r\n16 GPIO20_LEVEL_LOW RW 0x0\r\n15 GPIO19_EDGE_HIGH RW 0x0\r\n14 GPIO19_EDGE_LOW RW 0x0\r\n13 GPIO19_LEVEL_HIGH RW 0x0\r\n12 GPIO19_LEVEL_LOW RW 0x0\r\n11 GPIO18_EDGE_HIGH RW 0x0\r\n10 GPIO18_EDGE_LOW RW 0x0\r\n9 GPIO18_LEVEL_HIGH RW 0x0\r\n8 GPIO18_LEVEL_LOW RW 0x0\r\n7 GPIO17_EDGE_HIGH RW 0x0\r\n6 GPIO17_EDGE_LOW RW 0x0\r\n5 GPIO17_LEVEL_HIGH RW 0x0\r\n4 GPIO17_LEVEL_LOW RW 0x0\r\n3 GPIO16_EDGE_HIGH RW 0x0\r\n2 GPIO16_EDGE_LOW RW 0x0\r\n1 GPIO16_LEVEL_HIGH RW 0x0\r\n0 GPIO16_LEVEL_LOW RW 0x0\r\nIO_BANK0: DORMANT_WAKE_INTE3 Register\r\nOffset: 0x2e4\r\nRP2350 Datasheet\r\n9.11. List of registers 74"} |
| {"_id": "c55", "text": "\u25e6\r\nSet: Write 0x10 to MEICONTEXT.PREEMPT (greater than any interrupt priority in MEIPRA)\r\nMEICONTEXT.IRQ and NOIRQ help code determine in which interrupt handler it is running. MEICONTEXT should be\r\nsaved/restored by interrupts which pre-empt the current one, so is safe to check these fields during the handler.\r\nThe update to MEICONTEXT.PREEMPT upon writing MEINEXT.UPDATE ensures the core will be pre-empted by\r\ninterrupts higher-priority than the one it is about to enter. Equally important, it ensures the core is not pre-empted by\r\nlower or equal priority interrupts, including the one whose handler it is about to enter.\r\nTo avoid awkward interactions between the MIP.MEIP handler, which should be aware of the Xh3irq extension, and the\r\nMTIP/MSIP handlers, which may not be, it\u2019s best to avoid pre-emption of the former by the latter.\r\nMEICONTEXT.CLEARTS, MTIESAVE and MSIESAVE support disabling and restoring the timer/software interrupt\r\nenables as part of the MEICONTEXT CSR accesses that take place during context save/restore in the MEIP handler.\r\n3.8.6.1.6. Minimal handler example\r\nThis example demonstrates a minimal meip handler which dispatches to an array of C-function interrupt handlers,\r\nwithout enabling pre-emption. In this case the priorities configured in MEIPRA still determine the order in which\r\ninterrupts are entered when multiple are asserted, but when an interrupt handler starts running, no other interrupts are\r\nserviced until that handler completes.\r\n#include \"hardware/regs/rvcsr.h\"\r\nisr_riscv_machine_external_irq:\r\n\u00a0 // Save all caller saves and temporaries before entering a C ABI function.\r\n\u00a0 // Note mstatus.mie is cleared by hardware on interrupt entry, and\r\n\u00a0 // we're going to leave it clear.\r\n\u00a0 addi sp, sp, -64\r\n\u00a0 sw ra, 0(sp)\r\n\u00a0 sw t0, 4(sp)\r\n\u00a0 sw t1, 8(sp)\r\n\u00a0 sw t2, 12(sp)\r\n\u00a0 sw a0, 16(sp)\r\n\u00a0 sw a1, 20(sp)\r\n\u00a0 sw a2, 24(sp)\r\n\u00a0 sw a3, 28(sp)\r\n\u00a0 sw a4, 32(sp)\r\n\u00a0 sw a5, 36(sp)\r\n\u00a0 sw a6,"} |
| {"_id": "c148", "text": "/U-mode code to\r\nread/write its assigned PADS_BANK0 registers.\r\nFixed by RP2350 A3, Documentation, Software\r\nBootrom\r\nRP2350-E10\r\nReference RP2350-E10\r\nSummary UF2 drag-and-drop doesn\u2019t work with partition tables\r\nAffects RP2350 A2\r\nDescription When dragging and dropping a UF2 onto the USB Mass Storage Device, the bootrom on chip revision A2\r\ndoesn\u2019t set up the flash before checking the partition table. This causes the UF2 download to fail if there\r\nis a partition table present.\r\nRP2350 Datasheet\r\nACCESSCTRL 135"} |
| {"_id": "c18", "text": "| | Controls the tick generator | | |\r\n| Bits | Description | Type | Reset |\r\n| 31:2 | Reserved. | | |\r\n| | RUNNING:Is the tick generator running? | RO | |\r\n| 0 | ENABLE:start/stop tick generation | RW | 0x0 |"} |
| {"_id": "c204", "text": "Bits Description Type Reset\r\n0x41 \u2192 ROM_STALL_DOWNSTREAM\r\n0x42 \u2192 ROM_ACCESS_CONTESTED\r\n0x43 \u2192 ROM_ACCESS\r\nBUSCTRL: PERFCTR3 Register\r\nOffset: 0x24\r\nDescription\r\nBus fabric performance counter 3\r\nTable 1330.\r\nPERFCTR3 Register\r\nBits Description Type Reset\r\n31:24 Reserved. - -\r\n23:0 Busfabric saturating performance counter 3\r\nCount some event signal from the busfabric arbiters, if PERFCTR_EN is set.\r\nWrite any value to clear. Select an event to count using PERFSEL3\r\nWC 0x000000\r\nBUSCTRL: PERFSEL3 Register\r\nOffset: 0x28\r\nDescription\r\nBus fabric performance event select for PERFCTR3\r\nTable 1331. PERFSEL3\r\nRegister\r\nBits Description Type Reset\r\n31:7 Reserved. - -\r\n6:0 Select an event for PERFCTR3. For each downstream port of the main\r\ncrossbar, four events are available: ACCESS, an access took place;\r\nACCESS_CONTESTED, an access took place that previously stalled due to\r\ncontention from other masters; STALL_DOWNSTREAM, count cycles where\r\nany master stalled due to a stall on the downstream bus; STALL_UPSTREAM,\r\ncount cycles where any master stalled for any reason, including contention\r\nfrom other masters.\r\nRW 0x1f\r\nEnumerated values:\r\n0x00 \u2192 SIOB_PROC1_STALL_UPSTREAM\r\n0x01 \u2192 SIOB_PROC1_STALL_DOWNSTREAM\r\n0x02 \u2192 SIOB_PROC1_ACCESS_CONTESTED\r\n0x03 \u2192 SIOB_PROC1_ACCESS\r\n0x04 \u2192 SIOB_PROC0_STALL_UPSTREAM\r\n0x05 \u2192 SIOB_PROC0_STALL_DOWNSTREAM\r\n0x06 \u2192 SIOB_PROC0_ACCESS_CONTESTED\r\n0x07 \u2192 SIOB_PROC0_ACCESS\r\n0x08 \u2192 APB_STALL_UPSTREAM\r\n0x09 \u2192 APB_STALL_DOWNSTREAM\r\n0x0a \u2192 APB_ACCESS_CONTESTED\r\nRP2350 Datasheet\r\n12.15. System Control Registers 126"} |
| {"_id": "c78", "text": "| | Offset:0x343 | | |\r\n| Bits | Description | Type | Reset |\r\n| 31:0 | Machine bad address or instruction.Hardwired to zero | RO | 0x00000000 |"} |
| {"_id": "c494", "text": ");\r\n46 if (events & mask) {\r\n47 // Copy this event string into the user string\r\n48 const char *event_str = gpio_irq_str[i];\r\n49 while (*event_str != '\\0') {\r\n50 *buf++ = *event_str++;\r\n51 }\r\n52 events &= ~mask;\r\n53 \r\n54 // If more events add \", \"\r\n55 if (events) {\r\n56 *buf++ = ',';\r\n57 *buf++ = ' ';\r\n58 }\r\n59 }\r\n60 }\r\n61 *buf++ = '\\0';\r\n62 }\r\n9.11. List of registers\r\n9.11.1. IO - User Bank\r\nThe User Bank IO registers start at a base address of 0x40028000 (defined as IO_BANK0_BASE in SDK).\r\nRP2350 Datasheet\r\n9.11. List of registers 60"} |
| {"_id": "c262", "text": "actions if it is disabled by MATCH\r\nRW 0x2\r\n3:0 MATCH: Controls the type of match generated by this comparator RW 0x8\r\nM33: DWT_COMP2 Register\r\nOffset: 0x01040\r\nRP2350 Datasheet\r\n3.7. Cortex-M33 processor"} |
| {"_id": "c323", "text": "naturally aligned span of bytes (the base address modulo the size is zero) whose size is\r\na power of two.\r\nThe number of trailing 1s in the PMP address value encodes the size of an NAPOT region. This is the number of\r\nconsecutive 1s counted from the LSB without reaching a 0. A PMP address value with no trailing ones (ending in a 0)\r\nmatches a region eight bytes in size, and the region size is doubled with each additional 1 bit.\r\nThe PMP region matches on the address bits to the left of the least-significant 0 bit. Because the PMP address registers\r\nare right-shifted by two, you must apply the same shift to the addresses being compared. The following examples\r\ndemonstrate how to match addresses based on PMPADDRx values:\r\n\u2022 The 30-bit all-ones bit pattern 0x3fffffff has the maximum possible size, and matches all addresses.\r\n\u2022 The all-zeroes bit pattern 0x00000000 has the minimum possible size.\r\n\u25e6\r\nSince there are no trailing 1s, this matches starting from bit 1 of the PMP address register.\r\n\u25e6\r\nDue to addresses being right-shifted by two, this is a region of eight bytes starting from address 0x0.\r\n\u2022 The bit pattern 0x???????7 (where ? is any digit) matches any 64-byte region.\r\n\u25e6\r\nShift the base address of this 64-byte region by two to get bits 29:4 of the PMPADDRx value.\r\n\u2022 The bit pattern 0x0800000f matches byte addresses between 0x20000000 and 0x2000007f, the first 128 bytes of SRAM.\r\n\u25e6\r\nRight-shift the base address (0x20000000) by two to get 0x08000000.\r\n\u25e6\r\nAdd trailing ones to increase the region size and get the final value of 0x0800000f.\r\n\u25e6\r\nThe size of the region is eight bytes times two to the power of the number of trailing 1 bits, which in this case\r\n(four 1s) works out to 8 \u00d7 2\r\n4\r\n = 128 bytes.\r\nFor more examples of PMP address match patterns, see the hardwired PMP region values in Section 3.8.8.1.\r\nRP2350 configures Hazard3 with a granule of 32 bytes. This means the two least-significant bits of each PMP address\r\nregister are hardwired to all-ones when the"} |
| {"_id": "c483", "text": "Description\r\n| | Receive FIFO for direct mode | | |\r\n| Bits | Description | Type | Reset |\r\n| 31:16 | Reserved. | | |\r\n| | With each byte clocked out on the serial interface, one byte will simultaneously be clocked in, and will appear in this FiFO.The serial interface will stall when this FIFO is full, to avoid dropping data | | |\r\n| 15:0 | When 16-bit data is pushed into the TX FIFO,the corresponding RX FIFO push will also contain 16 bits of data.The least-significant byte is the first one received. | RF | 0x0000 |"} |
| {"_id": "c79", "text": "eet\r\n| | Description Interrupt Force for dormant_wake | | |\r\n| Bits | Description | Type | Reset |\r\n| 31 | GPI039_EDGE_HIGH | RW | Ox0 |\r\n| 30 | GPI039_EDGE_LOW | RW | Ox0 |\r\n| 29 | GPIO39_LEVEL_HIGH | RW | Ox0 |\r\n| 28 | GPIO39_LEVEL_LOW | RW | Ox0 |\r\n| 27 | GPIO38_EDGE_HIGH | RW | Ox0 |\r\n| 26 | GPIO38_EDGE_LOW | RW | 0x0 |\r\n| 25 | GPIO38_LEVEL_HIGH | RW | Ox0 |\r\n| 24 | GPIO38_LEVEL_LOW | RW | 0x0 |\r\n| 23 | GPIO37_EDGE_HIGH | RW | Ox0 |\r\n| 22 | GPIO37_EDGE_LOW | RW | 0x0 |\r\n| 21 | GPIO37_LEVEL_HIGH | RW | Ox0 |\r\n| 20 | GPIO37_LEVEL_LOW | RW | Ox0 |\r\n| 19 | GPIO36_EDGE_HIGH | RW | Ox0 |\r\n| 18 | GPI036_EDGE_LOW | RW | 0x0 |\r\n| 17 | GPIO36_LEVEL_HIGH | RW | 0x0 |\r\n| 16 | GPIO36_LEVEL_LOW | RW | Ox0 |\r\n| 15 | GPIO35_EDGE_HIGH | RW | Ox0 |\r\n| 14 | GPIO35_EDGE_LOW | RW | Ox0 |\r\n| 13 | GPIO35_LEVEL_HIGH | RW | 0x0 |\r\n| 12 | GPIO35_LEVEL_LOW | RW | Ox0 |\r\n| 11 | GPIO34_EDGE_HIGH | RW | 0x0 |\r\n| 10 | GPIO34_EDGE_LOW | RW | Ox0 |\r\n| 9 | GPIO34_LEVEL_HIGH | RW | 0x0 |\r\n| 8 | GPIO34_LEVEL_LOW | RW | 0x0 |\r\n| 7 | GPIO33_EDGE_HIGH | RW | 0x0 |\r\n| 6 | GPIO33_EDGE_LOW | RW | Ox0 |\r\n| S | GPIO33_LEVEL_HIGH | RW | Ox0 |\r\n| 4 | GPIO33_LEVEL_LOW | RW | Ox0 |\r\n| 3 | GPIO32_EDGE_HIGH | RW | Ox0 |\r\n| 2 | GPIO32_EDGE_LOW | RW | Ox0 |\r\n| - | GPIO32_LEVEL_HIGH | RW | Ox0 |\r\n0\r\nGPIO32_LEVEL_LOW\r\nRW\r\n0x0"} |
| {"_id": "c39", "text": "reset, or explicitly resetting just processor core 1).\r\nThe following C code describes the procedure:\r\n// values to be sent in order over the FIFO from core 0 to core 1\r\n//\r\n// vector_table is value for VTOR register\r\n// sp is initial stack pointer (SP)\r\n// entry is the initial program counter (PC) (don't forget to set the thumb bit!)\r\nconst uint32_t cmd_sequence[] =\r\n\u00a0 {0, 0, 1, (uintptr_t) vector_table, (uintptr_t) sp, (uintptr_t) entry};\r\nuint seq = 0;\r\ndo {\r\n\u00a0 uint cmd = cmd_sequence[seq];\r\n\u00a0 // always drain the READ FIFO (from core 1) before sending a 0\r\n\u00a0 if (!cmd) {\r\n\u00a0 // discard data from read FIFO until empty\r\n\u00a0 multicore_fifo_drain();\r\n\u00a0 // execute a SEV as core 1 may be waiting for FIFO space\r\n\u00a0 __sev();\r\n\u00a0 }\r\n\u00a0 // write 32 bit value to write FIFO\r\n\u00a0 multicore_fifo_push_blocking(cmd);\r\n\u00a0 // read 32 bit value from read FIFO once available\r\n\u00a0 uint32_t response = multicore_fifo_pop_blocking();\r\n\u00a0 // move to next state on correct response (echo-d value) otherwise start over\r\n\u00a0 seq = cmd == response ? seq + 1 : 0;\r\n} while (seq < count_of(cmd_sequence));\r\n5.4. Bootrom APIs\r\nWhilst some ROM space is dedicated to the implementation of the boot sequence and USB/UART boot interfaces, the\r\nbootrom also contains public functions that provide useful RP2350 functionality that may be useful for any code or\r\nruntime running on the device.\r\nA categorised list is available in Section 5.4.6.\r\nThe full alphabetical list is available in Section 5.4.7.\r\n5.4.1. Locating the API functions\r\nThe API functions are normally made available to the user by wrappers in the SDK. However, a lower level method is\r\nprovided to locate them (since their locations may change with each bootrom release) for other runtimes, or those who\r\nwish to locate them directly.\r\nTable 453 shows the fixed memory layout of certain words in the bootrom used to locate these"} |
| {"_id": "c451", "text": "xosc_hw->ctrl = XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ;\r\n32 \r\n33 // Set xosc startup delay\r\n34 xosc_hw->startup = STARTUP_DELAY;\r\n35 \r\n36 // Set the enable bit now that we have set freq range and startup delay\r\n37 hw_set_bits(&xosc_hw->ctrl, XOSC_CTRL_ENABLE_VALUE_ENABLE << XOSC_CTRL_ENABLE_LSB);\r\n38 \r\nRP2350 Datasheet\r\n8.2. Crystal oscillator (XOSC) 55"} |
| {"_id": "c46", "text": "sheet\r\n12.11. HSTX 120"} |
| {"_id": "c238", "text": "WARNING\r\nIf you do not configure IRQ before entering DORMANT mode, neither oscillator will restart.\r\nSee Section 6.5.6.2, \u201cDORMANT\u201d for a complete example of DORMANT mode using the XOSC.\r\n8.2.7. Programmer\u2019s model\r\nSDK: https://github.com/raspberrypi/pico-sdk/blob/master/src/rp2350/hardware_structs/include/hardware/structs/xosc.h Lines 27 - 57\r\n27 typedef struct {\r\n28 _REG_(XOSC_CTRL_OFFSET) // XOSC_CTRL\r\n29 // Crystal Oscillator Control\r\n30 // 0x00fff000 [23:12] ENABLE (-) On power-up this field is initialised to DISABLE and\r\n\u00a0 the...\r\n31 // 0x00000fff [11:0] FREQ_RANGE (-) The 12-bit code is intended to give some\r\n\u00a0 protection...\r\n32 io_rw_32 ctrl;\r\n33 \r\n34 _REG_(XOSC_STATUS_OFFSET) // XOSC_STATUS\r\n35 // Crystal Oscillator Status\r\n36 // 0x80000000 [31] STABLE (0) Oscillator is running and stable\r\n37 // 0x01000000 [24] BADWRITE (0) An invalid value has been written to CTRL_ENABLE\r\n\u00a0 or...\r\n38 // 0x00001000 [12] ENABLED (-) Oscillator is enabled but not necessarily running\r\n\u00a0 and...\r\n39 // 0x00000003 [1:0] FREQ_RANGE (-) The current frequency range setting\r\n40 io_rw_32 status;\r\n41 \r\n42 _REG_(XOSC_DORMANT_OFFSET) // XOSC_DORMANT\r\n43 // Crystal Oscillator pause control\r\n44 // 0xffffffff [31:0] DORMANT (-) This is used to save power by pausing the XOSC +\r\n45 io_rw_32 dormant;\r\n46 \r\n47 _REG_(XOSC_STARTUP_OFFSET) // XOSC_STARTUP\r\n48 // Controls the startup delay\r\n49 // 0x00100000 [20] X4 (-)"} |
| {"_id": "c391", "text": "0 (CPOL=0 CPHA=0) is\r\nsupported.\r\n0x04 DIRECT_TX Transmit FIFO for direct mode\r\nRP2350 Datasheet\r\n12.14. QSPI memory interface (QMI) 123"} |
| {"_id": "c352", "text": "modes are not supported:\r\n\u2022 High-speed mode (with data rates up to 3.4Mb/s),\r\n\u2022 Ultra-Fast Speed Mode (with data rates up to 5Mb/s).\r\n\uf05a NOTE\r\nReferences to fast mode also apply to fast mode plus, unless specifically stated otherwise.\r\nThe I2C block can communicate with devices in one of these modes as long as they are attached to the bus.\r\nAdditionally, fast mode devices are downward compatible. For instance, fast mode devices can communicate with\r\nstandard mode devices at up to 100\u00a0kb/s over the I2C bus system. However, standard mode devices are not upward\r\ncompatible and should not be incorporated in a fast-mode I2C bus system as they cannot follow the higher transfer\r\nrate; unpredictable states would occur.\r\nRP2350 Datasheet\r\n12.2. I2C 98"} |
| {"_id": "c341", "text": "| | | The two bulk endpoints are used for sending commands and retrieved successful command results. All commands are exactly 32 bytes (see Table 458) and sent to the BuLk_0UT endpoint |\r\n| Offset | Name | Description |\r\n| 0x00 | dMagic | The value0x431fd10b |\r\n| 0x04 | dToken | A user provided token to identify this request by. |\r\n| 0x08 | bCmdId | The ID of the command.Note that the top bit indicates data transfer direction 0x80=IN |\r\n| 0x09 | bCmdSize | Number of bytes of valid data in the args field |\r\n| 0x0a | reserved | exeee |\r\n| 0x0c | dTransferLength | The number of bytes the host expects to send or receive over the bulk channel |\r\n| 0x10 | args | 16 bytes of command-specific data padded with zeros |"} |
| {"_id": "c277", "text": "| Bits | Description | Type | Reset |\r\n| 5:4 | EP2 | WC | 0x0 |\r\n| 3:2 | EP1 | WC | 0x0 |\r\n| 1:0 | EPO | WC | 0x0 |"} |
| {"_id": "c290", "text": "| able 629. MER1_COUNT | Bits | Description | Type | Reset |\r\n| egister | 31:9 | Reserved | | |\r\n| | 8:0 | Count down timer:the remaining number clk_tick cycles before the next tick is generated. | RO | |"} |
| {"_id": "c317", "text": "| Bits | Description | Type | Reset |\r\n| 0 | EPO_IN | RO | 0x0 |"} |
| {"_id": "c304", "text": "\u2022 Page 0, which contains chip information, is read-only for all accesses.\r\n\u2022 Pages 1 and 2, which contain boot config and boot key fingerprints, are read-only for Non-secure access, read\u0002write for Secure access, and read-write for bootloader access.\r\n\u2022 Page 62, which contains only the page 62 lock word, is read-only for Non-secure access, read-write for Secure\r\naccess, and read-write for bootloader access (as a partial workaround for RP2350-E28).\r\n\u2022 Page 63, which contains the RMA flag, is read-only for Non-secure and bootloader access, and read-write for\r\nSecure access.\r\nThis minimal set of default permissions on blank devices avoids certain classes of security model violation, like Non\u0002secure code being able to brick the chip by overwriting the boot key fingerprints with invalid data. In this context, the\r\nterm blank device refers to a device that has gone through manufacturing test programming, but has not had any other\r\nOTP bits programmed by the user.\r\nYou can add additional soft or hard locks to these default permissions, with the exception of page 0. Page 0 cannot be\r\nhard-locked, since the secure read-only permission prevents a user from altering its lock word.\r\nLock words 2 through 61, covering all pages with user-defined contents, are left unprogrammed. On a blank device,\r\nthese pages are fully accessible from all domains. Before launching any Non-secure application, you should apply at\r\nleast a soft read-only lock to all pages that are not explicitly allocated for Non-secure use. To do this, write to\r\nSW_LOCK2 through SW_LOCK61. For devices that you don\u2019t expect to RMA, such as those that have passed board-level\r\nmanufacturing tests, you should lock secure writes to the RMA flag.\r\n13.6. Error Correction Code (ECC)\r\nECC-protected rows store data in the following structure, accessible through a raw alias:\r\n\u2022 Bits 23:22: bit repair by polarity (BRP) flag\r\n\u2022 Bits 21:16: modified Hamming ECC code\r\n\u2022 Bits 15:0 (the 16 LSBs): data\r\nRP2350 stores the following error correction data in the 8 MSBs of each 24-bit row:\r\n\u2022 a 6-bit modified Hamming code ECC, providing single-error-correct and double-error-detect capabilities\r\n\u2022 2 bits of"} |
| {"_id": "c268", "text": "GPIO41_LEVEL_HIGH RW 0x0\r\n4 GPIO41_LEVEL_LOW RW 0x0\r\n3 GPIO40_EDGE_HIGH RW 0x0\r\n2 GPIO40_EDGE_LOW RW 0x0\r\n1 GPIO40_LEVEL_HIGH RW 0x0\r\n0 GPIO40_LEVEL_LOW RW 0x0\r\nIO_BANK0: PROC0_INTS0 Register\r\nOffset: 0x278\r\nRP2350 Datasheet\r\n9.11. List of registers 71"} |
| {"_id": "c69", "text": "Bits Description Type Reset\r\n7:5 L0_NBITS: Number of valid data bits for the lane 0 TMDS encoder, starting\r\nfrom bit 7 of the rotated data. Field values of 0 \u2192 7 encode counts of 1 \u2192 8\r\nbits.\r\nRW 0x0\r\n4:0 L0_ROT: Right-rotate applied to the current shifter data before the lane 0\r\nTMDS encoder.\r\nRW 0x00\r\n12.11.8. List of FIFO registers\r\nThe FIFO registers start at a base address of 0x50600000 (defined as HSTX_FIFO_BASE in the SDK).\r\nTable 1258. List of\r\nHSTX_FIFO registers\r\nOffset Name Info\r\n0x0 STAT FIFO status\r\n0x4 FIFO Write access to FIFO\r\nHSTX_FIFO: STAT Register\r\nOffset: 0x0\r\nDescription\r\nFIFO status\r\nTable 1259. STAT\r\nRegister\r\nBits Description Type Reset\r\n31:11 Reserved. - -\r\n10 WOF: FIFO was written when full. Write 1 to clear. WC 0x0\r\n9 EMPTY RO -\r\n8 FULL RO -\r\n7:0 LEVEL RO 0x00\r\nHSTX_FIFO: FIFO Register\r\nOffset: 0x4\r\nTable 1260. FIFO\r\nRegister\r\nBits Description Type Reset\r\n31:0 Write access to FIFO WF 0x00000000\r\n12.12. TRNG\r\n12.12.1. Overview\r\nRP2350 contains an Arm IP-based True Random Number Generator block. It supports the following features:\r\n\u2022 Compliance with FIPS Publication 140-2, BSI AIS-31, and NIST SP 800-90B\r\n\u2022 Produces approximately 7.5\u00a0kb/s of entropy when the core runs at 150\u00a0MHz\r\nOn request, the TRNG block generates a block of 192 entropy bits generated by automatically processing a series of\r\nperiodic samples from the TRNG block\u2019s internal Ring Oscillator (ROSC).\r\nRP2350 Datasheet\r\n12.12. TRNG 121"} |
| {"_id": "c455", "text": "| | | sys_cik cycres andtnererore can ony generate TREqs at a rate orT per'sys_cik (I.e. permanent TREq)or less | | |\r\n| | Bits | Description | Type | Reset |\r\n| ble 1177. TIMER0, MER1, TIMER2, MER3Registers | 31:16 | X: Pacing Timer Dividend.Specifies the X value for the (X/Y) fractional timer. | RW | 0x0000 |\r\n| | 15:0 | Y: Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. | RW | 0x0000 |"} |
| {"_id": "c465", "text": "| | connect_internal_flashQfunction.Alternatively,connect CS1 to pin 0 |\r\n| Fixed by | RP2350A3 bootrom,Documentation,Software |\r\n| RP2350-E15 | |\r\n| Reference | RP2350-E15 |\r\n| Summary | The bootrom otp_access() function applies incorrect access permission to pages 62 &63 |\r\n| Affects | RP2350A2 |\r\n| Description | The bootrom otp_access function incorrectly applies the access permissions specified in OTP rows PAGE62_L0CK1 and PAGE63_L0CK1 to the entirety of their respective OTP pages 62 and 63).This is incorrect, as pages 62 and 63 contain lock words for other pages: each lock word is instead protected by the permissions of the corresponding page. |\r\n| | The ATE programming then locks down write access from non-Secure software and the bootloader to the page 63 lock word (to prevent non-Secure setting of the RMA flag). and write access from non-Secure software to the page 62 lock word.This prevents non-Secure software from modifying any of the OTP page locks, and the bootloader from modifying the locks for pages 32-63. |\r\n| | When running code on the device, dont use the non-Secure otp_access() function to set locks for OTP pages. To set OTP page locks from non-Secure code, implement your own Secure APl to do this that can be called from non-Secure code. |\r\n| Workaround | Page locks for OTP pages 32-63 can be set by picotool using the picotool otp permissions command. This command loads a Secure binary into XIP SRAM on the device to change the permissions before rebooting back into the USB bootloader. |\r\n| Fixed by | RP2350A3 bootrom,Documentation,Software |"} |
| {"_id": "c154", "text": "Bits Description Type Reset\r\n15:0 FRAC: Fractional component of the divisor, can be changed on-the-fly RW 0x0000\r\nCLOCKS: CLK_GPOUT1_SELECTED Register\r\nOffset: 0x14\r\nDescription\r\nIndicates which src is currently selected (one-hot)\r\nTable 549.\r\nCLK_GPOUT1_SELECT\r\nED Register\r\nBits Description Type Reset\r\n31:1 Reserved. - -\r\n0 This slice does not have a glitchless mux (only the AUX_SRC field is present,\r\nnot SRC) so this register is hardwired to 0x1.\r\nRO 0x1\r\nCLOCKS: CLK_GPOUT2_CTRL Register\r\nOffset: 0x18\r\nDescription\r\nClock control, can be changed on-the-fly (except for auxsrc)\r\nTable 550.\r\nCLK_GPOUT2_CTRL\r\nRegister\r\nBits Description Type Reset\r\n31:29 Reserved. - -\r\n28 ENABLED: clock generator is enabled RO 0x0\r\n27:21 Reserved. - -\r\n20 NUDGE: An edge on this signal shifts the phase of the output by 1 cycle of the\r\ninput clock\r\nThis can be done at any time\r\nRW 0x0\r\n19:18 Reserved. - -\r\n17:16 PHASE: This delays the enable signal by up to 3 cycles of the input clock\r\nThis must be set before the clock is enabled to have any effect\r\nRW 0x0\r\n15:13 Reserved. - -\r\n12 DC50: Enables duty cycle correction for odd divisors, can be changed on-the\u0002flyRW 0x0\r\n11 ENABLE: Starts and stops the clock generator cleanly RW 0x0\r\n10 KILL: Asynchronously kills the clock generator, enable must be set low before\r\ndeasserting kill\r\nRW 0x0\r\n9 Reserved. - -\r\n8:5 AUXSRC: Selects the auxiliary clock source, will glitch when switching RW 0x0\r\nEnumerated values:\r\n0x0 \u2192 CLKSRC_PLL_SYS\r\n0x1 \u2192 CLKSRC_GPIN0\r\n0x2 \u2192 CLKSRC_GPIN1\r\n0x3 \u2192 CLKSRC_PLL_USB\r\n0x4 \u2192 CLKSRC_PLL_USB_PRIMARY_REF_OPCG\r\nRP2350 Datasheet\r\n8.1. Overview 53"} |
| {"_id": "c82", "text": "104 dma_start_channel_mask(1u << ctrl_chan);\r\n105 \r\n106 // The data channel will assert its IRQ flag when it gets a null trigger,\r\n107 // indicating the end of the control block list. We're just going to wait\r\n108 // for the IRQ flag instead of setting up an interrupt handler.\r\n109 while (!(dma_hw->intr & 1u << data_chan))\r\n110 tight_loop_contents();\r\n111 dma_hw->ints0 = 1u << data_chan;\r\n112 \r\n113 puts(\"DMA finished.\");\r\n114 #endif\r\n115 }\r\n12.6.10. List of Registers\r\nThe DMA registers start at a base address of 0x50000000 (defined as DMA_BASE in SDK).\r\nTable 1147. List of\r\nDMA registers\r\nOffset Name Info\r\n0x000 CH0_READ_ADDR DMA Channel 0 Read Address pointer\r\n0x004 CH0_WRITE_ADDR DMA Channel 0 Write Address pointer\r\n0x008 CH0_TRANS_COUNT DMA Channel 0 Transfer Count\r\n0x00c CH0_CTRL_TRIG DMA Channel 0 Control and Status\r\n0x010 CH0_AL1_CTRL Alias for channel 0 CTRL register\r\n0x014 CH0_AL1_READ_ADDR Alias for channel 0 READ_ADDR register\r\n0x018 CH0_AL1_WRITE_ADDR Alias for channel 0 WRITE_ADDR register\r\n0x01c CH0_AL1_TRANS_COUNT_TRIG Alias for channel 0 TRANS_COUNT register\r\nThis is a trigger register (0xc). Writing a nonzero value will\r\nreload the channel counter and start the channel.\r\n0x020 CH0_AL2_CTRL Alias for channel 0 CTRL register\r\n0x024 CH0_AL2_TRANS_COUNT Alias for channel 0 TRANS_COUNT register\r\n0x028 CH0_AL2_READ_ADDR Alias for channel 0 READ_ADDR register\r\n0x02c CH0_AL2_WRITE_ADDR_TRIG Alias for channel 0 WRITE_ADDR register\r\nThis is a trigger register (0xc). Writing a nonzero value will\r\nreload the channel counter and start the channel.\r\n0x030 CH0_AL3_"} |
| {"_id": "c477", "text": "Bits Description Type Reset\r\n0 NSU: If 1, and NSP is also set, TRNG can be accessed from a Non-secure,\r\nUnprivileged context.\r\nThis bit is writable from a Non-secure, Privileged context, if and only if the NSP\r\nbit is set.\r\nRW 0x0\r\nACCESSCTRL: SHA256 Register\r\nOffset: 0xb8\r\nDescription\r\nControl whether debugger, DMA, core 0 and core 1 can access SHA256, and at what security/privilege levels they\r\ncan do so.\r\nDefaults to Secure, Privileged access only.\r\nThis register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which\r\nbecomes Non-secure-Privileged-writable when the NSP bit is set.\r\nTable 958. SHA256\r\nRegister\r\nBits Description Type Reset\r\n31:8 Reserved. - -\r\n7 DBG: If 1, SHA256 can be accessed by the debugger, at security/privilege\r\nlevels permitted by SP/NSP/SU/NSU in this register.\r\nRW 0x1\r\n6 DMA: If 1, SHA256 can be accessed by the DMA, at security/privilege levels\r\npermitted by SP/NSP/SU/NSU in this register.\r\nRW 0x1\r\n5 CORE1: If 1, SHA256 can be accessed by core 1, at security/privilege levels\r\npermitted by SP/NSP/SU/NSU in this register.\r\nRW 0x1\r\n4 CORE0: If 1, SHA256 can be accessed by core 0, at security/privilege levels\r\npermitted by SP/NSP/SU/NSU in this register.\r\nRW 0x1\r\n3 SP: If 1, SHA256 can be accessed from a Secure, Privileged context. RW 0x1\r\n2 SU: If 1, and SP is also set, SHA256 can be accessed from a Secure,\r\nUnprivileged context.\r\nRW 0x0\r\n1 NSP: If 1, SHA256 can be accessed from a Non-secure, Privileged context. RW 0x0\r\n0 NSU: If 1, and NSP is also set, SHA256 can be accessed from a Non-secure,\r\nUnprivileged context.\r\nThis bit is writable from a Non-secure, Privileged context, if and only if the NSP\r\nbit is set.\r\nRW 0x0\r\nACCESSCTRL: SYSCF"} |
| {"_id": "c172", "text": ". Power management (POWMAN) registers 45"} |
| {"_id": "c321", "text": "1.1. The chip\r\nDual Cortex-M33 or Hazard3 processors access RP2350\u2019s memory and peripherals via AHB and APB bus fabric.\r\nIOs\r\nPIO Memory\r\nCrystal\r\nClock\r\ngeneration Processor subsystem\r\nPeripherals\r\nBus Fabric\r\nInternal \r\noscillator\r\nUSB\r\nProc0\r\nROM\r\nSRAM\r\nDMA\r\nCore Supply Regulator\r\n(Switcher and low \r\npower LDO)\r\nXIP / \r\nCache\r\nSPI \u00d72\r\nPWM\r\nUART \u00d72\r\nTimer\r\nAON Timer\r\nI2C \u00d72\r\nADC & TS\r\nReset control\r\nPower control\r\nSysctrl\r\nSysinfo\r\nWatchdog\r\nSecurity\r\nHSTX\r\nPLL\r\nPLL Interrupts\r\nSWD\r\nQSPI\r\nRP2350\r\nSRAM\r\nSRAM SRAM\r\nSRAM\r\nOTP\r\nSRAM SRAM\r\nSRAM SRAM\r\nSRAM\r\nProc1\r\nPIO0 PIO1 PIO2\r\nSIO\r\nGPIO\r\nFigure 1. A system\r\noverview of the\r\nRP2350 chip\r\nCode may execute directly from external memory through a dedicated QSPI memory interface in the execute-in-place\r\nsubsystem (XIP). The cache improves XIP performance significantly. Both flash and RAM can attach via this interface.\r\nDebug is available via the SWD interface. This allows an external host to load, run, halt and inspect software running on\r\nthe system, or configure the execution trace output.\r\nInternal SRAM can contain code or data. It is addressed as a single 520\u00a0kB region, but physically partitioned into 10\r\nbanks to allow simultaneous parallel access from different managers. All SRAM supports single-cycle access.\r\nA high-bandwidth system DMA offloads repetitive data transfer tasks from the processors.\r\nGPIO pins can be driven directly via single-cycle IO (SIO), or from a variety of dedicated logic functions such as the\r\nhardware SPI, I2C, UART and PWM. Programmable IO controllers (PIO) can provide a wider variety of IO functions, or\r\nsupplement the number of fixed-function peripherals.\r\nA USB controller with embedded PHY provides FS/LS Host or Device connectivity under software control.\r\nFour or eight ADC inputs (depending on package size) are shared with GPIO pins.\r\nTwo PLLs provide a fixed 48\u00a0MHz clock for USB or ADC, and a flexible system clock up to 150\u00a0MHz. A crystal oscillator\r\nprovides a precise reference for the PLLs.\r\nAn internal voltage regulator supplies the core voltage, so you need generally only supply the IO voltage. It operates as a"} |
| {"_id": "c90", "text": "eet\r\n| Offset | Name | Info |\r\n| Ox0a4 | CH8_DIV | INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta.. |\r\n| 0x0a8 | CH8_CTR | Direct access to the PwM counter |\r\n| Ox0ac | CH8_CC | Counter compare values |\r\n| 0x0b0 | CH8_TOP | Counter wrap value |\r\n| Ox0b4 | CH9_CSR | Control and status register |\r\n| 0x0b8 | CH9_DIV | INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta.. |\r\n| Ox0bc | CH9_CTR | Direct access to the PwM counter |\r\n| Ox0c0 | CH9_CC | Counter compare values |\r\n| 0x0c4 | CH9_TOP | Counter wrap value |\r\n| 0x0c8 | CH10_CSR | Control and status register |\r\n| Ox0cc | CH10_DIV | INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta. |\r\n| Ox0d0 | CH10_CTR | Direct access to the PwM counter |\r\n| 0x0d4 | CH10_CC | Counter compare values |\r\n| 0x0d8 | CH10_TOP | Counter wrap value |\r\n| Ox0dc | CH11_CSR | Control and status register |\r\n| Ox0e0 | CH11_DIV | INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta.. |\r\n| Ox0e4 | CH11_CTR | Direct access to the PwM counter |\r\n| 0x0e8 | CH11_CC | Counter compare values |\r\n| Ox0ec | CH11_TOP | Counter wrap value |\r\n| OxOfo | EN | This register aliases the CSR_EN bits for all channels.. Writing to this register allows multiple channels to be enabled or disabled simultaneously, so they can run in perfect sync. For each channel, there is only one physical EN register bit, which can be accessed through here or CHx_CSR. |\r\n| Ox0f4 | INTR | Raw Interrupts |\r\n| Ox0f8 | IRQO_INTE | Interrupt Enable for irq0 |\r\n| OxOfc | IRQO_INTF | Interrupt Force for irq0 |\r\n| 0x100 | IRQO_INTS | Interrupt status after masking & forcing for irq0 |\r\n| 0x104 | IRQ1_INTE | Interrupt Enable for irq1 |\r\n| 0x108 | IRQ1_INTF | Interrupt Force for irq1 |\r\n| 0x10c | IRQ1_INTS | Interrupt status after masking & forcing for irq1 |"} |
| {"_id": "c180", "text": "| Bits | Description | Type | Reset |\r\n| 15:0 | BAUD_DIvINT: The integer baud rate divisor.These bits are cleared to O on reset. | RW | Ox0000 |"} |
| {"_id": "c414", "text": "driving to the GPIOs. On RP2040 there are 30 GPIOs, so\r\nthe two most significant bits are hardwired to 0.\r\nRP2350 Datasheet\r\n11.7. List of registers 94"} |
| {"_id": "c312", "text": "Description\r\n| | I2CReceive FIFO Threshold Register | | |\r\n| Bits | Description | Type | Reset |\r\n| 31:8 | Reserved. | | |\r\n| | RX_TL: Receive FIFO Threshold Level | | |\r\n| 7:0 | Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register).The valid range is 0-255,with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer.If an attempt is made to do that, the actual value set will be the maximum depth of the buffer.A value of O sets the threshold for 1 entry,and a value of 255 sets the threshold for 256 entries | RW | 0x00 |"} |
| {"_id": "c278", "text": "\u2022 TX Shift: Presents data supplied by CPU for transfer on the I2C bus.\r\n\u2022 RX Filter: Detects the events in the bus; for example, start, stop and arbitration lost.\r\n\u2022 Toggle: Generates pulses on both sides and toggles to transfer signals across clock domains.\r\n\u2022 Synchronizer: Transfers signals from one clock domain to another.\r\n\u2022 DMA Interface: Generates the handshaking signals to the central DMA controller in order to automate the data\r\ntransfer without CPU intervention.\r\n\u2022 Interrupt Controller: Generates the raw interrupt and interrupt flags, allowing them to be set and cleared.\r\n\u2022 RX FIFO/TX FIFO: Holds the RX FIFO and TX FIFO register banks and controllers, along with their status levels.\r\n12.2.4. I2C terminology\r\nThis section defines key terms used in various parts of the I2C.\r\n12.2.4.1. I2C bus terms\r\nThe following terms relate to how the role of the I2C device and how it interacts with other I2C devices on the bus.\r\nTransmitter\r\nthe device that sends data to the bus. A transmitter can either be a device that initiates the data transmission to the\r\nbus (a master-transmitter) or the device that responds to a request from the master to send data to the bus (a\r\nslave-transmitter).\r\nReceiver\r\nthe device that receives data from the bus. A receiver can either be a device that receives data on its own request (a\r\nmaster-receiver) or a device that receives data in response to a request from the master (a slave-receiver).\r\nMaster\r\nthe component that initializes a transfer (START command), generates the clock SCL signal and terminates the\r\ntransfer (STOP command). A master can be either a transmitter or a receiver.\r\nSlave\r\nthe device addressed by the master. A slave can be either receiver or transmitter.\r\nMulti-master\r\nthe ability for more than one master to co-exist on the bus at the same time without collision or data loss.\r\nArbitration\r\nthe predefined procedure that authorizes only one master at a time to take control of the bus. For more information\r\nabout this behaviour, refer to Section 12.2.8.\r\nSynchronization\r\nthe predefined procedure that synchronizes the clock signals provided by two or more masters. For more\r\ninformation about this feature, refer to Section 12.2.9.\r\nSDA\r\nthe data signal line (Serial Data).\r\nSCL\r\nthe clock signal line (Serial"} |
| {"_id": "c381", "text": "| Offset:Ox0c | | | |\r\n| Bits | Description | Type | Reset |\r\n| 31:8 | Reserved. | | |\r\n| 7:0 | Write any nonzero value to disable writes to ARM, DISARM, SENSITIVITY and LOCK.This register is Secure read/write only | RW | 0x00 |"} |
| {"_id": "c472", "text": "\u25e6\r\nFor a multi-layer board (4 or more layers) please cut away any copper immediately underneath LX/VREG_LX\r\nnode. For example, Figure 24 illustrates this.\r\n\u2022 The GND via placement is critical.\r\n\u25e6\r\nThere must be a short-as-possible, low impedance GND path back to the Raspberry Pi Pico 2 QFN GND pad\r\nfrom the high-current GND at one single point (using 2 adjacent vias to reduce the impedance).\r\n\u25e6\r\nCFILT must also have a low impedance and short-as-possible path back to the QFN GND pad (don\u2019t share any\r\nGND vias with the CIN/COUT high current GND).\r\n\u2022 The VREG_FB pin should be fed from the output of COUT, avoiding routing directly underneath LX.\r\n\u2022 COUT is critical for regulator performance and EMI. It must be placed between VREG_VIN and VREG_PGND as close to the\r\npins as practically possible.\r\n\u25e6\r\nIn addition to COUT, for best performance we recommend a second 4.7\u03bcF capacitor is used on the VOUT net,\r\nlocated on the bottom edge of the package (DVDD pin 23 on the QFN-60). Don\u2019t place this near LX/COUT.\r\nLayer 2\r\nFigure 24. Cut-out\r\nbeneath LX/VREG_LX\r\nnet on layer 2 of 4 (or\r\nmore) layer PCBs\r\n6.3.8.2. Component values\r\n\u2022 CIN should be at least 4.7\u03bcF and have a maximum parasitic resistance of 50m\u03a9.\r\n\u2022 COUT must be 4.7\u03bcF \u00b120% with a maximum parasitic resistance of 250m\u03a9 and a maximum inductance of 6nH.\r\n\u2022 LX must be fully shielded, 3.3\u03bcH \u00b120% and with a maximum DC resistance of 250m\u03a9. Saturation current should be\r\nat least 1.5A. The inductor must be marked for polarity (see Figure 25) and placed on the layout as indicated in\r\nFigure 23. As discussed below, we recommend the AOTA-B201610S3R3-101-T.\r\nRP2350 Datasheet\r\n6.3. Core voltage regulator 45"} |
| {"_id": "c362", "text": "All predefined data fields have some form of redundancy. Where ECC is not viable, for instance because a location is\r\nexpected to have individual bits programmed at different times, best-of-three majority vote is used instead. The only\r\nexception to this is the critical hardware flags in CRIT0 and CRIT1. These flags use a three-of-eight vote encoding for\r\neach individual flag: the flag is considered set when at least three bits are set out of the eight redundant bit locations.\r\nThe description for each row indicates the type of redundancy.\r\nPages 3 through 60 (rows 0x0c0 through 0xf3f) are free for arbitrary user content such as OTP-resident bootloaders, and\r\nRaspberry Pi will avoid allocating any of these locations for bootrom configuration if possible. This is a total of 7424\r\nbytes of ECC-protected content.\r\nPage 2 (rows 0x080 through 0x0bf) is also available for user content if secure boot is disabled. It is partially available if\r\nsecure boot is enabled and fewer than four boot key fingerprints are registered. This is an additional 128 ECC bytes\r\npotentially available for user content.\r\nPages 0, 1, and 61 through 63 are reserved for future use by Raspberry Pi. Software should avoid allocating content in\r\nthese regions, even if they currently have no defined use in this data listing.\r\nTable 1362. List of\r\nOTP_DATA registers\r\nOffset Name Info\r\n0x000 CHIPID0 Bits 15:0 of public device ID. (ECC)\r\nThe CHIPID0..3 rows contain a 64-bit random identifier for this\r\nchip, which can be read from the USB bootloader PICOBOOT\r\ninterface or from the get_sys_info ROM API.\r\nThe number of random bits makes the occurrence of twins\r\nexceedingly unlikely: for example, a fleet of a hundred million\r\ndevices has a 99.97% probability of no twinned IDs. This is\r\nestimated to be lower than the occurrence of process errors in\r\nthe assignment of sequential random IDs, and for practical\r\npurposes CHIPID may be treated as unique.\r\n0x001 CHIPID1 Bits 31:16 of public device ID (ECC)\r\n0x002 CHIPID2 Bits 47:32 of public device ID (ECC)\r\n0x003 CHIPID3 Bits 63:48 of public device ID (ECC)\r\n0x004 RANDID0 Bits 15:0 of private per-"} |
| {"_id": "c324", "text": "Table 139. ITM_CIDR0\r\nRegister\r\nBits Description Type Reset\r\n31:8 Reserved. - -\r\n7:0 PRMBL_0: See CoreSight Architecture Specification RO 0x0d\r\nM33: ITM_CIDR1 Register\r\nOffset: 0x00ff4\r\nDescription\r\nProvides CoreSight discovery information for the ITM\r\nTable 140. ITM_CIDR1\r\nRegister\r\nBits Description Type Reset\r\n31:8 Reserved. - -\r\n7:4 CLASS: See CoreSight Architecture Specification RO 0x9\r\n3:0 PRMBL_1: See CoreSight Architecture Specification RO 0x0\r\nM33: ITM_CIDR2 Register\r\nOffset: 0x00ff8\r\nDescription\r\nProvides CoreSight discovery information for the ITM\r\nTable 141. ITM_CIDR2\r\nRegister\r\nBits Description Type Reset\r\n31:8 Reserved. - -\r\n7:0 PRMBL_2: See CoreSight Architecture Specification RO 0x05\r\nM33: ITM_CIDR3 Register\r\nOffset: 0x00ffc\r\nDescription\r\nProvides CoreSight discovery information for the ITM\r\nTable 142. ITM_CIDR3\r\nRegister\r\nBits Description Type Reset\r\n31:8 Reserved. - -\r\n7:0 PRMBL_3: See CoreSight Architecture Specification RO 0xb1\r\nM33: DWT_CTRL Register\r\nOffset: 0x01000\r\nDescription\r\nProvides configuration and status information for the DWT unit, and used to control features of the unit\r\nTable 143. DWT_CTRL\r\nRegister\r\nBits Description Type Reset\r\n31:28 NUMCOMP: Number of DWT comparators implemented RO 0x7\r\n27 NOTRCPKT: Indicates whether the implementation does not support trace RO 0x0\r\n26 NOEXTTRIG: Reserved, RAZ RO 0x0\r\n25 NOCYCCNT: Indicates whether the implementation does not include a cycle\r\ncounter\r\nRO 0x1\r\nRP2350 Datasheet\r\n3.7. Cortex-M33 processor"} |
| {"_id": "c431", "text": "RL_PULL_THRESH and\r\nSHIFTCTRL_PUSH_THRESH to decide whether action is required. Autopull and autopush are individually enabled by the\r\nSHIFTCTRL_AUTOPULL and SHIFTCTRL_AUTOPUSH fields.\r\n11.5.4.1. Autopush details\r\nPseudocode for an IN with autopush enabled:\r\n\u00a01 isr = shift_in(isr, input())\r\n\u00a02 isr count = saturate(isr count + in count)\r\n\u00a03 \r\n\u00a04 if rx count >= threshold:\r\n\u00a05 if rx fifo is full:\r\n\u00a06 stall\r\n\u00a07 else:\r\n\u00a08 push(isr)\r\n\u00a09 isr = 0\r\n10 isr count = 0\r\nThe hardware performs the above steps in a single machine clock cycle, unless there is a stall.\r\nThreshold is configurable from 1 to 32.\r\nRP2350 Datasheet\r\n11.5. Functional details 90"} |
| {"_id": "c347", "text": "HIGH RW 0x0\r\n0 GPIO8_LEVEL_LOW RW 0x0\r\nIO_BANK0: PROC0_INTE2 Register\r\nOffset: 0x250\r\nDescription\r\nInterrupt Enable for proc0\r\nTable 766.\r\nPROC0_INTE2 Register\r\nBits Description Type Reset\r\n31 GPIO23_EDGE_HIGH RW 0x0\r\nRP2350 Datasheet\r\n9.11. List of registers 70"} |
| {"_id": "c86", "text": "Table 888. GPIO35\r\nRegister\r\nBits Description Type Reset\r\n31:9 Reserved. - -\r\n8 ISO: Pad isolation control. Remove this once the pad is configured by\r\nsoftware.\r\nRW 0x1\r\n7 OD: Output disable. Has priority over output enable from peripherals RW 0x0\r\n6 IE: Input enable RW 0x0\r\n5:4 DRIVE: Drive strength. RW 0x1\r\nEnumerated values:\r\n0x0 \u2192 2MA\r\n0x1 \u2192 4MA\r\n0x2 \u2192 8MA\r\n0x3 \u2192 12MA\r\n3 PUE: Pull up enable RW 0x0\r\n2 PDE: Pull down enable RW 0x1\r\n1 SCHMITT: Enable schmitt trigger RW 0x1\r\n0 SLEWFAST: Slew rate control. 1 = Fast, 0 = Slow RW 0x0\r\nPADS_BANK0: GPIO36 Register\r\nOffset: 0x94\r\nTable 889. GPIO36\r\nRegister\r\nBits Description Type Reset\r\n31:9 Reserved. - -\r\n8 ISO: Pad isolation control. Remove this once the pad is configured by\r\nsoftware.\r\nRW 0x1\r\n7 OD: Output disable. Has priority over output enable from peripherals RW 0x0\r\n6 IE: Input enable RW 0x0\r\n5:4 DRIVE: Drive strength. RW 0x1\r\nEnumerated values:\r\n0x0 \u2192 2MA\r\n0x1 \u2192 4MA\r\n0x2 \u2192 8MA\r\n0x3 \u2192 12MA\r\n3 PUE: Pull up enable RW 0x0\r\n2 PDE: Pull down enable RW 0x1\r\n1 SCHMITT: Enable schmitt trigger RW 0x1\r\n0 SLEWFAST: Slew rate control. 1 = Fast, 0 = Slow RW 0x0\r\nPADS_BANK0: GPIO37 Register\r\nOffset: 0x98\r\nRP2350 Datasheet\r\n9.11. List of registers 80"} |
| {"_id": "c75", "text": "these FIFOs.\r\nTable 447. List of\r\nXIP_AUX registers\r\nOffset Name Info\r\n0x0 STREAM Read the XIP stream FIFO (fast bus access to\r\nXIP_CTRL_STREAM_FIFO)\r\n0x4 QMI_DIRECT_TX Write to the QMI direct-mode TX FIFO (fast bus access to\r\nQMI_DIRECT_TX)\r\nRP2350 Datasheet\r\n4.4. External flash and PSRAM (XIP)"} |
| {"_id": "c438", "text": "| | | be disarmed early using the ARMED status register | | |\r\n| | Offset:Ox1c | TIMER:ALARM3Register | | |\r\n| 1235. ALARM3 ter | Bits | Description | Type | Reset |\r\n| | 31:0 | Arm alarm 3,and confiqure the time it will fire be disarmed early using the ARMED status register. Once armed,the alarm fires when TIMER_ALARM3 == TIMELR The alarm will disarm itself once it fires, and can | RW | 0x00000000 |"} |
| {"_id": "c15", "text": "x0\r\n3 GPIO24_EDGE_HIGH RO 0x0\r\n2 GPIO24_EDGE_LOW RO 0x0\r\n1 GPIO24_LEVEL_HIGH RO 0x0\r\n0 GPIO24_LEVEL_LOW RO 0x0\r\nIO_BANK0: PROC0_INTS4 Register\r\nOffset: 0x288\r\nRP2350 Datasheet\r\n9.11. List of registers 72"} |
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