[ { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 1 $ $Author: rio1rt $ $Date: 2024/01/25 15:35:15 GMT $')\nsav('VDD', 0.0, sim_ignore=True)\nsav('VDDIO', 0.0, sim_ignore=True)\ndly(1e-3)\nsav('VDD', 1.8, v_range=2.0, i_comp=40e-3)\nsav('VDDIO', 3.0, v_range=4.0, i_comp=40e-3)\ndly(3e-3)\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T01_01_power_cycle_V1: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n static double v_VDDIO, v_VDD;\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n v_VDDIO = Primary.getLevelSpec().getSpecValue(\"VDDIO\");\n v_VDD = Primary.getLevelSpec().getSpecValue(\"VDD\");\n\n rdi.dc().pin(\"All_AVI64\").disconnect().execute();\n rdi.hwRelay().pin(\"ALL_PS1600\").setOff(\"ALL\").execute();\n rdi.hwRelay().pin(\"SPI_Pins\").setOn(\"AC\").setOff(\"DC,PPMU\").execute();\n rdi.util().pin(\"K1_K2\").setOn().execute();\n rdi.util().pin(\"K6,K7\").setOff().execute();\n// rdi.dc().pin(\"VDD_AVI64\").vForce(v_VDD).iMeasRange(40 mA).execute();\n// rdi.dc().pin(\"VDDIO_AVI64\").vForce(v_VDDIO).iMeasRange(40 mA).execute();\n RDI_BEGIN(mode);\n rdi.burstId(\"T01_01_power_cycle_V1_PAT_id\");\n rdi.dc(\"T01_01_power_cycle_V1DC_id0\").label(s_label_name)\n .insertSub(i_comment_line0[0]).pin(\"VDD\").vForce(0.0)\n .insertSub(i_comment_line0[0]).pin(\"VDDIO\").vForce(0.0)\n .insertSub(i_comment_line0[1]).pin(\"VDD\").vForce(v_VDD).iRange(40 mA)\n .insertSub(i_comment_line0[1]).pin(\"VDDIO\").vForce(v_VDDIO).iRange(40 mA)\n .execute();\n RDI_END();\n ON_FIRST_INVOCATION_END();\n \n int Func_result = rdi.id(\"T01_01_power_cycle_V1_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T01_01_power_cycle_V1\", T01_01_power_cycle_V1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 1 $ $Author: hmf1rt $ $Date: 2024/03/13 13:36:52 GMT $')\nrac('CHIP_ID', 0x0000, 0x0000) # Dummy read to init SPI protocol\ndly(50e-6)\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T01_02_IF_setup_SPI_V1: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n// i_comment_line0 = search_comment_line(s_label_name);\n// print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T01_02_IF_setup_SPI_V1_PAT_id\");\n rdi.func().label(s_label_name).execute();\n RDI_END();\n\n ON_FIRST_INVOCATION_END();\n \n int Func_result = rdi.id(\"T01_02_IF_setup_SPI_V1_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T01_02_IF_setup_SPI_V1\", T01_02_IF_setup_SPI_V1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: bai430aa_rel/1 $ $Author: hmf1rt $ $Date: 2024/07/18 13:10:23 GMT $')\nbw('CSB', 1) # Pre-condition inputs: CSB high to keep I2C enabled\nbw('SCX', 1) # Pre-condition inputs: SCX high I2C clock\nbw('SDX', 1) # Pre-condition inputs: SDX high I2C data\nbw('SDO', 0) # Pre-condition inputs: SDO low to use I2C device ID 0x68\ndly(10e-6)\nsav('VDD', 0.0, sim_ignore=True)\nsav('VDDIO', 0.0, sim_ignore=True)\ndly(1e-3)\nsav('VDD', 1.8, v_range=2.0, i_comp=40e-3)\nsav('VDDIO', 3.0, v_range=4.0, i_comp=40e-3)\ndly(3e-3)\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T01_03_IF_setup_I2C_devID68_R1: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n static double v_VDDIO, v_VDD;\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n v_VDDIO = Primary.getLevelSpec().getSpecValue(\"VDDIO\");\n v_VDD = Primary.getLevelSpec().getSpecValue(\"VDD\");\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T01_03_IF_setup_I2C_devID68_R1_PAT_id\");\n rdi.dc(\"T01_03_IF_setup_I2C_devID68_R1DC_id0\").label(s_label_name)\n .insertSub(i_comment_line0[0]).pin(\"VDD\").vForce(0.0)\n .insertSub(i_comment_line0[0]).pin(\"VDDIO\").vForce(0.0)\n .insertSub(i_comment_line0[1]).pin(\"VDD\").vForce(v_VDD).iRange(40 mA)\n .insertSub(i_comment_line0[1]).pin(\"VDDIO\").vForce(v_VDDIO).iRange(40 mA)\n .execute();\n RDI_END();\n ON_FIRST_INVOCATION_END();\n \n int Func_result = rdi.id(\"T01_03_IF_setup_I2C_devID68_R1_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T01_03_IF_setup_I2C_devID68_R1\", T01_03_IF_setup_I2C_devID68_R1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: bai430aa_rel/1 $ $Author: hmf1rt $ $Date: 2024/07/18 13:21:04 GMT $')\nbw('CSB', 1) # Pre-condition inputs: CSB high to keep I2C enabled\nbw('SCX', 1) # Pre-condition inputs: SCX high I2C clock\nbw('SDX', 1) # Pre-condition inputs: SDX high I2C data\nbw('SDO', 1) # Pre-condition inputs: SDO low to use I2C device ID 0x69\ndly(10e-6)\nsav('VDD', 0.0, sim_ignore=True)\nsav('VDDIO', 0.0, sim_ignore=True)\ndly(1e-3)\nsav('VDD', 1.8, v_range=2.0, i_comp=40e-3)\nsav('VDDIO', 3.0, v_range=4.0, i_comp=40e-3)\ndly(3e-3)\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T01_04_IF_setup_I2C_devID69_R1: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n static double v_VDDIO, v_VDD;\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n v_VDDIO = Primary.getLevelSpec().getSpecValue(\"VDDIO\");\n v_VDD = Primary.getLevelSpec().getSpecValue(\"VDD\");\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T01_04_IF_setup_I2C_devID69_R1_PAT_id\");\n rdi.dc(\"T01_04_IF_setup_I2C_devID69_R1DC_id0\").label(s_label_name)\n .insertSub(i_comment_line0[0]).pin(\"VDD\").vForce(0.0)\n .insertSub(i_comment_line0[0]).pin(\"VDDIO\").vForce(0.0)\n .insertSub(i_comment_line0[1]).pin(\"VDD\").vForce(v_VDD).iRange(40 mA)\n .insertSub(i_comment_line0[1]).pin(\"VDDIO\").vForce(v_VDDIO).iRange(40 mA)\n .execute();\n RDI_END();\n ON_FIRST_INVOCATION_END();\n\n int Func_result = rdi.id(\"T01_04_IF_setup_I2C_devID69_R1_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T01_04_IF_setup_I2C_devID69_R1\", T01_04_IF_setup_I2C_devID69_R1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "# Warning, AA workaround applied, pri.sec pad drive strength set to 1\ncmt('Version info: $Revision: bai430aa_rel/4 $ $Author: hmf1rt $ $Date: 2024/09/25 12:30:22 GMT $')\nwr('EXT_MODE', 0x0000) # User page\nwac('IO_PAD_STRENGTH', 0x0049) # Set pad drive strength to 1 for prim/sec IF\nrac('CHIP_ID', 0x00af, 0x00ff) # Check chip access\nwac('PWR_CONF', 0x0000) # Keep advanced power save off (default is 0x0)\ndly(10e-6)\nwr('CMD', 0xBB3A) # 1st command for enabling the extended mode\nwr('CMD', 0x2C62) # 2nd command for enabling the extended mode\nwr('CMD', 0xA576) # 1st command for enabling the super privilege mode\nwr('CMD', 0x34D6) # 2nd command for enabling the super privilege mode\ndly(200e-6)\nwac('ACC_CONF', 0xe24c) # Enable ACC in HPM; set AFS=32g; set ODR=1600; set BW=200\ndly(400e-6)\nrac('ERR_REG', 0x0000) # Check error register\nwac('EXT_MODE', 0xc00d) # Enable super privilege mode; switch to ANA register page\nrac('STATUS_PMOD0', 0x0003, 0x0003) # Check ACC AFE PMU status\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T01_10_set_device_config_STC_ACC_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n ARRAY_LL IO_PAD_STRENGTH_rtv(xNSitES);\n const int Wri_Bit_Length = 33;\n const int Wri_Bit_Position = 415;\n int IO_PAD_STRENGTH = 1;\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n// i_comment_line0 = search_comment_line(s_label_name);\n// print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T01_10_set_device_config_STC_ACC_V2_PAT_id\");\n rdi.func().label(s_label_name).execute();\n RDI_END();\n\n// FOR_EACH_SITE_BEGIN();\n// \t IO_PAD_STRENGTH_rtv[CURRENT_SITE_NUMBER()-1] = extend_Pmode_Herschel(IO_PAD_STRENGTH, 2);\n// FOR_EACH_SITE_END();\n\n// rdi.runTimeVal(\"IO_PAD_STRENGTH_rtv\", IO_PAD_STRENGTH_rtv);\n//\n// RDI_BEGIN(mode);\n// rdi.burstId(\"id2\");\n// rdi.digCap(\"pad_drv_digcap\").vecVarOnly().pin(\"SDO\").capMode(TA::SER).samples(16*1).bitPerWord(16).execute();\n// rdi.smartVec().label(\"T08_99_Pad_Drive_setting_R1\").pin(\"SDX\").writeData(\"IO_PAD_STRENGTH_rtv\", Wri_Bit_Length, Wri_Bit_Position).execute();\n// RDI_END();\n ON_FIRST_INVOCATION_END();\n \n int Func_result = rdi.id(\"T01_10_set_device_config_STC_ACC_V2_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n// int Func_result2 = rdi.id(\"id2\").getBurstPassFail();\n// FuncPrint(\"Func_result2\", Func_result2);\n//\n// ARRAY_I Vec=rdi.id(\"pad_drv_digcap\").getVector();\n// FuncPrint(\"IO_PAD_STRENGTH_RD\", reverse_ras_result(Vec[0])&0x7);\n// FuncPrint(\"IO_PAD_STRENGTH\", IO_PAD_STRENGTH);\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T01_10_set_device_config_STC_ACC_V2\", T01_10_set_device_config_STC_ACC_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 2 $ $Author: rio1rt $ $Date: 2024/03/14 13:05:55 GMT $')\nrac('CHIP_ID', 0x00af, 0x00ff) # Check chip access\nwac('PWR_CONF', 0x0000) # Keep advanced power save off (default is 0x0)\ndly(10e-6)\nwr('CMD', 0xBB3A) # 1st command for enabling the extended mode\nwr('CMD', 0x2C62) # 2nd command for enabling the extended mode\nwr('CMD', 0xA576) # 1st command for enabling the super privilege mode\nwr('CMD', 0x34D6) # 2nd command for enabling the super privilege mode\ndly(10e-6)\nwac('ACC_CONF', 0xe24c) # Enable ACC in HPM; set AFS=32g; set ODR=1600; set BW=200\nwac('GYR_CONF', 0xe25c) # Enable GYR in HPM; set GFS=4K; set ODR=1600; set BW=200\ndly(50e-3)\nrac('ERR_REG', 0x0000) # Check error register\nwac('EXT_MODE', 0xc00d) # Enable super privilege mode; switch to ANA register page\nrac('STATUS_PMOD0', 0x0003, 0x0003) # Check ACC AFE PMU status\nrac('STATUS_PMOD1', 0x003c, 0x003c) # Check GYR drive and rate PMU status\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T01_11_set_device_config_STC_COMBO_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n// i_comment_line0 = search_comment_line(s_label_name);\n// print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T01_11_set_device_config_STC_COMBO_V2_PAT_id\");\n rdi.func().label(s_label_name).execute();\n RDI_END();\n\n ON_FIRST_INVOCATION_END();\n \n int Func_result = rdi.id(\"T01_11_set_device_config_STC_COMBO_V2_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T01_11_set_device_config_STC_COMBO_V2\", T01_11_set_device_config_STC_COMBO_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: bai430aa_rel/3 $ $Author: hmf1rt $ $Date: 2024/08/06 09:19:58 GMT $')\nwac('EXT_MODE', 0xc006) # Switch to the FCU register page\nwac('OCP_MASK', 0x1000) # Set masking register\nwr('FILTER_CONF',0x1000) # Bypass GYR notch filter\nrac('FILTER_CONF',0x1000, 0x1000) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('OCP_MASK', 0x0040) # Set masking register\nwr('FCU_TEST_CONF',0x0040) # Disable gyro self-test\nrac('FCU_TEST_CONF',0x0040) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('EXT_MODE', 0xc00d) # Switch to ANA/PMU register page\nwac('GYR_TEST_AA_AI', 0x0003) # Power down AA/AI\nwac('EXT_MODE', 0xc00e) # Switch to AFE register page\nwac('OCP_MASK', 0x0030) # Set masking register\nwr('DRV_ST_TRM', 0x0020) # Disable GYR startup BITE\nrac('DRV_ST_TRM', 0x0020, 0x0020) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('OCP_MASK', 0x0004) # Set masking register\nwr('GYR_TEST_EN', 0x0004) # Enable VCO free-running frequency\nrac('GYR_TEST_EN', 0x0004, 0x0004) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('EXT_MODE', 0xc000) # Switch to USR register page\nwac('GYR_CONF', 0xe25e) # Enable GYR in HPM; set GFS=4K; set ODR=6400; set BW=200\ndly(5e-3) # Delay for PMU power-up; no data ready (~10ms)\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nrac('STATUS_PMOD1', 0x003c, 0x003c) # Check GYR drive and rate PMU status\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T01_20_switch_on_GYR_wo_drive_V3: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n// i_comment_line0 = search_comment_line(s_label_name);\n// print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T01_20_switch_on_GYR_wo_drive_V3_PAT_id\");\n rdi.func().label(s_label_name).execute();\n RDI_END();\n// rdi.func().label(\"T11_21_VCO_reference_measurement_V2_AVC2_PY2\").execute();\n ON_FIRST_INVOCATION_END();\n \n int Func_result = rdi.id(\"T01_20_switch_on_GYR_wo_drive_V3_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T01_20_switch_on_GYR_wo_drive_V3\", T01_20_switch_on_GYR_wo_drive_V3);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: bai430aa_rel/1 $ $Author: hmf1rt $ $Date: 2024/07/18 13:21:04 GMT $')\nwac('EXT_MODE', 0xc000) # Switch to USR register page\nwac('GYR_CONF', 0x0058) # Disable GYR; set default configuration\ndly(100e-6) \nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('OCP_MASK', 0x0004) # Set masking register\nwr('GYR_TEST_EN', 0x0000) # Disable VCO free-running frequency\nrac('GYR_TEST_EN', 0x0000, 0x0004) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('EXT_MODE', 0xc00e) # Switch to AFE register page\nwac('OCP_MASK', 0x0020) # Set masking register\nwr('DRV_ST_TRM', 0x0000) # Enable GYR startup BITE\nrac('DRV_ST_TRM', 0x0000, 0x0020) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('EXT_MODE', 0xc00d) # Switch to ANA/PMU register page\nwac('GYR_TEST_AA_AI', 0x0000) # Enable power up of AA/AI\nwac('EXT_MODE', 0xc006) # Switch to the FCU register page\nwac('OCP_MASK', 0x0040) # Set masking register\nwr('FCU_TEST_CONF',0x0000) # Enable gyro self-test\nrac('FCU_TEST_CONF',0x0000) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('OCP_MASK', 0x1000) # Set masking register\nwr('FILTER_CONF',0x0000) # Disable GYR notch filter bypass\nrac('FILTER_CONF',0x0000, 0x1000) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('EXT_MODE', 0xc00d) # Switch to ANA/PMU register page\nrac('STATUS_PMOD1', 0x0000, 0x003c) # Check GYR drive and rate PMU status\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T01_21_switch_off_GYR_wo_drive_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n// i_comment_line0 = search_comment_line(s_label_name);\n// print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T01_21_switch_off_GYR_wo_drive_V2_PAT_id\");\n rdi.func().label(s_label_name).execute();\n RDI_END();\n\n ON_FIRST_INVOCATION_END();\n \n int Func_result = rdi.id(\"T01_21_switch_off_GYR_wo_drive_V2_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T01_21_switch_off_GYR_wo_drive_V2\", T01_21_switch_off_GYR_wo_drive_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 3 $ $Author: luz3sgh $ $Date: 2024/05/20 08:35:37 GMT $')\n\nwac('EXT_MODE',0xc000) # User page\nwac('ACC_CONF', 0x004e) # e24c->004e, odr to max 6.4K, bandwidth change to auto, Disable ACC\n\nwac('EXT_MODE',0xc00e) \t\t\t# AFE(acc afe) page\nwac('ACC_TRM_CTRL',0x01af) # Default value for gmboost, slow chopper, settling count\nwac('ACC_TEST_CTRL',0x00c7) # Disable sensor drive, disconnect MEMS, enable all 3 channels\n\nwac('EXT_MODE',0xc00b) # AFE(acc_dp) page\nwac('ACC_COMP_CONF', 0x0003)\t\t\t\t# Disable offset and gain correction\n\nwac('EXT_MODE',0xc000) # User page\nwac('FILTER_CONF', 0x0000)\t\t\t\t# Bypass IIR, reset value 0303\nwac('ACC_CONF', 0xe04e) # Enable ACC in HPM; set AFS=32g; set ODR=3200; set BW=AUTO\ndly(400e-6) # wait for the internal clock (25kHz), multiple clocks in the PMU\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T01_24_enable_ACC_high_odr_mode_V3: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n// i_comment_line0 = search_comment_line(s_label_name);\n// print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T01_24_enable_ACC_high_odr_mode_V3_PAT_id\");\n rdi.func().label(s_label_name).execute();\n RDI_END();\n\n ON_FIRST_INVOCATION_END();\n \n int Func_result = rdi.id(\"T01_24_enable_ACC_high_odr_mode_V3_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T01_24_enable_ACC_high_odr_mode_V3\", T01_24_enable_ACC_high_odr_mode_V3);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 2 $ $Author: luz3sgh $ $Date: 2024/06/11 07:02:03 GMT $')\nwac('EXT_MODE',0xc000) # AFE(acc afe) page\nwac('ACC_CONF', 0x004e) # Disable ACC\n\n# Restore to default value\nwac('EXT_MODE',0xc00e) # AFE(acc afe) page\nwac('ACC_TEST_CTRL',0x0007) # Restore default\n\nwac('EXT_MODE',0xc00b) # AFE(acc_dp) page\nwac('ACC_COMP_CONF', 0x0000)\t # Restore default\n\nwac('EXT_MODE',0xc000) # User page\nwac('FILTER_CONF', 0x0303)\t # Restore default\n\nwac('ACC_CONF', 0xe24c) # Enable ACC in HPM; set AFS=32g; set ODR=1600; set BW=200\ndly(500e-6) # as in T01_10_set_device_config_STC, +100microseconds for rac(),wac()\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T01_25_disable_ACC_high_odr_mode_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n// i_comment_line0 = search_comment_line(s_label_name);\n// print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"01_25_disable_ACC_high_odr_mode_V2_PAT_id\");\n rdi.func().label(s_label_name).execute();\n RDI_END();\n\n ON_FIRST_INVOCATION_END();\n \n int Func_result = rdi.id(\"01_25_disable_ACC_high_odr_mode_V2_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T01_25_disable_ACC_high_odr_mode_V2\", T01_25_disable_ACC_high_odr_mode_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: bai430aa_rel/1 $ $Author: hmf1rt $ $Date: 2024/07/18 13:21:04 GMT $')\nwac('EXT_MODE', 0xc006) # Switch to the FCU register page\nwac('OCP_MASK', 0x1000) # Set masking register\nwr('FILTER_CONF',0x1000) # Bypass GYR notch filter\nrac('FILTER_CONF',0x1000, 0x1000) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('OCP_MASK', 0x0040) # Set masking register\nwr('FCU_TEST_CONF',0x0040) # Disable gyro self-test\nrac('FCU_TEST_CONF',0x0040) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('EXT_MODE', 0xc00d) # Switch to ANA/PMU register page\nwac('GYR_TEST_AA_AI', 0x0003) # Power down AA/AI\nwac('OCP_MASK', 0x1000) # Set masking register\nwr('ANA_TRM_CAP_PROG_DRV', 0x1000) # Enable realignment of GYR clk to FOSC\nrac('ANA_TRM_CAP_PROG_DRV', 0x1000, 0x1000) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('EXT_MODE', 0xc00e) # Switch to AFE register page\nwac('OCP_MASK', 0x0030) # Set masking register\nwr('DRV_ST_TRM', 0x0020) # Disable GYR startup BITE\nrac('DRV_ST_TRM', 0x0020, 0x0020) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('OCP_MASK', 0x0004) # Set masking register\nwr('GYR_TEST_EN', 0x0004) # Enable VCO free-running frequency\nrac('GYR_TEST_EN', 0x0004, 0x0004) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('EXT_MODE', 0xc000) # Switch to USR register page\nwac('GYR_CONF', 0xe25e) # Enable GYR in HPM; set GFS=4K; set ODR=6400; set BW=200\ndly(5e-3) # Delay for PMU power-up; no data ready (~10ms)\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nrac('STATUS_PMOD1', 0x003c, 0x003c) # Check GYR drive and rate PMU status\n", "output": "/*****************************************************\n * T01_30_switch_on_GYR_wo_drive_econ_V3, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T01_30_switch_on_GYR_wo_drive_econ_V3: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static int i_funcRes0[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T01_30_switch_on_GYR_wo_drive_econ}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 1] @ avcline 3973: {Test End: T01_30_switch_on_GYR_wo_drive_econ}\n */\n// rdi.util().pin(\"K1_K2,K6,K7\").setOn().execute();\n// rdi.dc().pin(\"VDD_AVI64\").vForce(0).iMeasRange(40 mA).execute();\n// rdi.dc().pin(\"VDDIO_AVI64\").vForce(0).iMeasRange(40 mA).execute();\n\n// RDI_BEGIN(mode);\n// \t rdi.dc().pin(\"VDDIO_AVI64\").vForce(0).execute();\n// \t rdi.dc().pin(\"VDD_AVI64\").vForce(0).execute();\n// \t rdi.wait(1 ms);\n// \t rdi.dc().pin(\"VDDIO_AVI64\").vForce(3).execute();\n// \t rdi.dc().pin(\"VDD_AVI64\").vForce(1.8).execute();\n// \t rdi.wait(1 ms);\n// \t rdi.func().label(\"T01_02_IF_setup_SPI_V1_AVC1_PY1\").execute();\n// \t rdi.func().label(\"T01_10_set_device_config_STC_ACC_R1\").execute();\n// \t rdi.func().label(s_splited_pat_name[0]).execute();\n// RDI_END();\n\n//\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.func().label(s_splited_pat_name[0]).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n FuncPrint(\"i_funcRes0\", i_funcRes0[curSite]);\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n//rdi.func().label(\"T11_20_VCO_reference_trimming_V2_AVC2_PY2\").execute();\n ON_FIRST_INVOCATION_END();\n\n i_funcRes[curSite] = i_funcRes0[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T01_30_switch_on_GYR_wo_drive_econ_V3\", T01_30_switch_on_GYR_wo_drive_econ_V3);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: bai430aa_rel/1 $ $Author: hmf1rt $ $Date: 2024/07/18 13:21:04 GMT $')\nwac('EXT_MODE', 0xc000) # Switch to USR register page\nwac('GYR_CONF', 0x0058) # Disable GYR; set default configuration\ndly(100e-6) \nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('OCP_MASK', 0x0004) # Set masking register\nwr('GYR_TEST_EN', 0x0000) # Disable VCO free-running frequency\nrac('GYR_TEST_EN', 0x0000, 0x0004) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('EXT_MODE', 0xc00e) # Switch to AFE register page\nwac('OCP_MASK', 0x0020) # Set masking register\nwr('DRV_ST_TRM', 0x0000) # Enable GYR startup BITE\nrac('DRV_ST_TRM', 0x0000, 0x0020) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('EXT_MODE', 0xc00d) # Switch to ANA/PMU register page\nwac('OCP_MASK', 0x1000) # Set masking register\nwr('ANA_TRM_CAP_PROG_DRV', 0x0000) # Disable realignment of GYR clk to FOSC\nrac('ANA_TRM_CAP_PROG_DRV', 0x0000, 0x1000) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('GYR_TEST_AA_AI', 0x0000) # Enable power up of AA/AI\nwac('EXT_MODE', 0xc006) # Switch to the FCU register page\nwac('OCP_MASK', 0x0040) # Set masking register\nwr('FCU_TEST_CONF',0x0000) # Enable gyro self-test\nrac('FCU_TEST_CONF',0x0000) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('OCP_MASK', 0x1000) # Set masking register\nwr('FILTER_CONF',0x0000) # Disable GYR notch filter bypass\nrac('FILTER_CONF',0x0000, 0x1000) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('EXT_MODE', 0xc00d) # Switch to ANA/PMU register page\nrac('STATUS_PMOD1', 0x0000, 0x003c) # Check GYR drive and rate PMU status\n", "output": "/*****************************************************\n * T01_31_switch_off_GYR_wo_drive_econ_V4, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T01_31_switch_off_GYR_wo_drive_econ_V4: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static int i_funcRes0[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T01_31_switch_off_GYR_wo_drive_econ}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 1] @ avcline 3973: {Test End: T01_31_switch_off_GYR_wo_drive_econ}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.func().label(s_splited_pat_name[0]).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n FuncPrint(\"i_funcRes0\", i_funcRes0[curSite]);\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n\n ON_FIRST_INVOCATION_END();\n\n i_funcRes[curSite] = i_funcRes0[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T01_31_switch_off_GYR_wo_drive_econ_V4\", T01_31_switch_off_GYR_wo_drive_econ_V4);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 2 $ $Author: luz3sgh $ $Date: 2024/04/12 06:49:43 GMT $')\ncmt(\"py $Revision: 2 $\")\nwac(\"EXT_MODE\", 0xc009) # change to page 9,IO\nbw(\"ASCX\", 1) # Set pad ASCX to \"1\"\n#IO page\nwac('OCP_MASK', 0x0018) # Set masking register\nwr('IO_TEST_IF', 0x0018) # Enable external clock; select ASCX as clk source\ndly(10.064e-6) # Delay to fit the 74ns grid\nubw('ASCX')\nclk(\"ASCX\", 1/148e-9) # Start to apply ext clk (6.757 MHz) on DTM3\ndly(20.128e-6) # Delay to fit the 74ns grid\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nrac(\"IO_TEST_IF\", 0x0018, 0x0018) # Check register setting\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T02_02_enable_external_clock_on_ascx_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n// i_comment_line0 = search_comment_line(s_label_name);\n// print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T02_02_enable_external_clock_on_ascx_V2_PAT_id\");\n rdi.func().label(s_label_name).execute();\n RDI_END();\n\n ON_FIRST_INVOCATION_END();\n \n int Func_result = rdi.id(\"T02_02_enable_external_clock_on_ascx_V2_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T02_02_enable_external_clock_on_ascx_V2\", T02_02_enable_external_clock_on_ascx_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description:\n# Part1- VDDA bypass\n# - swith off ACC\n# - switch off VDDA_LDO\n# - disable pullup on ANAIO 2\n# - set ext. voltage\n# - enable bypass--connect VDDA to OCSB Pad\n# Part2- VDDDC bypass\n# - set INT1 to 1.15V\n# - enable bypass--connect VDDDC to INT1 pad\n# - switch off VDD_DC LDO\n# - set INT1 to 1.1V\n#############################################################################################################\ncmt('Version info: $Revision: 2 $ $Author: laj1mu23 $ $Date: 2024/03/25 19:45:00 GMT $')\n# Part1,vdda bypass\n# switch off ACC\nwac('EXT_MODE', 0xc000) # Switch to USR page\nwac('ACC_CONF',0x024c) # Disable ACC \n# power down VDDA_LDO (to prevent power request in other test items) \nwac('EXT_MODE', 0xc00d) # Switch to PMU page\nwac(\"OCP_MASK\", 0x000a) \nwr(\"PMU_TEST_OWR\",0x0008) # bit3 acc_vdda_owr_en 1, bit 1, owr_vdda_acc_en 0\nrac(\"PMU_TEST_OWR\",0x0008,0x000a) \nwr(\"OCP_MASK\", 0x0000) \nrac(\"OCP_MASK\", 0xffff) \n# set vdda ext. voltage\nsav(\"OCSB\", 1.5, v_range=2.0, i_comp=10e-3) \ndly(100.048e-6)\n# enable bypass\nwac(\"EXT_MODE\", 0xc00d) # change to page D, ANA/PMU page ++ \nwac(\"OCP_MASK\", 0x0001) # Set masking register\nwr(\"ANA_TEST_PWR\",0x0001) # vdda_ext_en to 1, VDDA to OCSB\nrac(\"ANA_TEST_PWR\", 0x0001, 0x0001) # Check register setting\nwr(\"OCP_MASK\", 0x0000) # Reset masking register\nrac(\"OCP_MASK\", 0xffff) # Check masking register reset\n# Part2, vddd_dc bypass\nsav('INT1', 1.15, v_range=2.0, i_comp=10e-3) \ndly(100.048e-6)\nwac('OCP_MASK', 0x0042) # Set masking register\nwr('ANA_TEST_PWR', 0x0002) # Bypass VDDD_DC to external pad\nrac('ANA_TEST_PWR', 0x0002,0x0042) # Bypass VDDD_DC to external pad\ndly(10.064e-6)\nwr('ANA_TEST_PWR', 0x0042) # Disable VDDD_DC LDO; keep external pad bypass\nrac('ANA_TEST_PWR', 0x0042,0x0042) # Disable VDDD_DC LDO; keep external pad bypass\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n# Set vddd_dc ext. voltage\nsav('INT1', 1.1, v_range=2.0, i_comp=10e-3)\ndly(100.048e-6)\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T02_10_enable_VDDD_DC_and_VDDA_external_bypass_ECon_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n double d_V_INT1, d_V_OCSB;\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n d_V_INT1 = Primary.getLevelSpec().getSpecValue(\"INT1\");\n d_V_OCSB = Primary.getLevelSpec().getSpecValue(\"OCSB\");\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T02_10_enable_VDDD_DC_and_VDDA_external_bypass_ECon_V2_PAT_id\");\n rdi.dc(\"T02_10_enable_VDDD_DC_and_VDDA_external_bypass_ECon_V2DC_id0\").label(s_label_name)\n .insertSub(i_comment_line0[0]).pin(\"OCSB\").vForce(d_V_OCSB)\n .insertSub(i_comment_line0[1]).pin(\"INT1\").vForce(1.15)\n .insertSub(i_comment_line0[2]).pin(\"INT1\").vForce(d_V_INT1)\n .execute();\n RDI_END();\n\n ON_FIRST_INVOCATION_END();\n \n int Func_result = rdi.id(\"T02_10_enable_VDDD_DC_and_VDDA_external_bypass_ECon_V2_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T02_10_enable_VDDD_DC_and_VDDA_external_bypass_ECon_V2\", T02_10_enable_VDDD_DC_and_VDDA_external_bypass_ECon_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 2 $ $Author: laj1mu23 $ $Date: 2024/03/25 19:45:00 GMT $')\n# Part1 disable vdddc bypass\nsav('INT1', 1.15) # Increase supply voltage to 1.15V on pad INT1\ndly(100.048e-6)\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('OCP_MASK', 0x0042) # Set masking register\nwr('ANA_TEST_PWR', 0x0002) # Enable VDDD_DC_LDO; keep external bypass\nrac('ANA_TEST_PWR', 0x0002, 0x0042) # Check register setting\ndly(100.048e-6)\nwr('ANA_TEST_PWR', 0x0000) # Disable VDDD_DC extnernal bypass\nrac('ANA_TEST_PWR', 0x0000, 0x0042) # Check register setting\ndly(100.048e-6)\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nuav('INT1') # Unset voltage stimuli on INT1\ndly(100.048e-6)\n# Part2 disable vdda bypass\n# disable bypass VDDA_LDO with ext voltage\nwac(\"OCP_MASK\", 0x0001) # Set masking register\nwr(\"ANA_TEST_PWR\",0x0000) # vdda_ext_en to 0, disconnect VDDA to OCSB\nrac(\"ANA_TEST_PWR\", 0x0000, 0x0001) # Check register setting\nwr(\"OCP_MASK\", 0x0000) # Reset masking register\nrac(\"OCP_MASK\", 0xffff) # Check masking register reset\n# unset ext voltage\nuav(\"OCSB\")\ndly(100.048e-6)\n# disable VDDA_LDO power overwrite\nwac('EXT_MODE',0xc00d) # to PMU page \nwac(\"OCP_MASK\", 0x000a) \nwr(\"PMU_TEST_OWR\",0x0000) # bit3 acc_vdda_owr_en 0, bit 1, owr_vdda_acc_en 0\nrac(\"PMU_TEST_OWR\",0x0000,0x000a) \nwr(\"OCP_MASK\", 0x0000) \nrac(\"OCP_MASK\", 0xffff) \n# switch on ACC\nwac('EXT_MODE', 0xc000)\nwac('ACC_CONF', 0xe24c) # Enable ACC in HPM; set AFS=32g; set ODR=1600; set BW=200\ndly(3000.256e-6) \n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T02_11_disable_VDDD_DC_and_VDDA_external_bypass_ECon_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T02_11_disable_VDDD_DC_and_VDDA_external_bypass_ECon_V2_PAT_id\");\n rdi.dc(\"T02_11_disable_VDDD_DC_and_VDDA_external_bypass_ECon_V2DC_id0\").label(s_label_name)\n .insertSub(i_comment_line0[0]).pin(\"INT1\").vForce(1.15)\n .insertSub(i_comment_line0[1]).pin(\"INT1\").relay(TA::ppmuRly_offALL)\n .insertSub(i_comment_line0[2]).pin(\"OCSB\").relay(TA::ppmuRly_offALL)\n .execute();\n RDI_END();\n\n ON_FIRST_INVOCATION_END();\n \n int Func_result = rdi.id(\"T02_11_disable_VDDD_DC_and_VDDA_external_bypass_ECon_V2_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T02_11_disable_VDDD_DC_and_VDDA_external_bypass_ECon_V2\", T02_11_disable_VDDD_DC_and_VDDA_external_bypass_ECon_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description:\n# - swith off ACC\n# - switch off VDDA_LDO\n# - disable pullup on ANAIO 2\n# - set ext. voltage\n# - enable bypass--connect VDDA to external Pad\n#############################################################################################################\ncmt('Version info: $Revision: 3 $ $Author: hmf1rt $ $Date: 2024/04/19 12:11:59 GMT $')\n# switch off ACC\nwac('EXT_MODE', 0xc000) # Switch to USR page\nwac('ACC_CONF',0x024c) # Disable ACC \n# power down VDDA_LDO (to prevent power request in other test items) \nwac('EXT_MODE', 0xc00d) # Switch to PMU page\nwac(\"OCP_MASK\", 0x000a) \nwr(\"PMU_TEST_OWR\",0x0008) # bit3 acc_vdda_owr_en 1, bit 1, owr_vdda_acc_en 0\nrac(\"PMU_TEST_OWR\",0x0008,0x000a) \nwr(\"OCP_MASK\", 0x0000) \nrac(\"OCP_MASK\", 0xffff) \n# set ext. voltage\nsav(\"OCSB\", 1.5, v_range=2.0, i_comp=10e-3) \ndly(100e-6)\n# enable bypass\nwac(\"EXT_MODE\", 0xc00d) # change to page D, ANA/PMU page ++ \nwac(\"OCP_MASK\", 0x0001) # Set masking register\nwr(\"ANA_TEST_PWR\",0x0001) # vdda_ext_en to 1, VDDA to OCSB\nrac(\"ANA_TEST_PWR\", 0x0001, 0x0001) # Check register setting\nwr(\"OCP_MASK\", 0x0000) # Reset masking register\nrac(\"OCP_MASK\", 0xffff) # Check masking register reset\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T02_14_enable_vdda_external_bypass_V3: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T02_14_enable_vdda_external_bypass_V3_PAT_id\");\n rdi.dc(\"T02_14_enable_vdda_external_bypass_V3DC_id0\").label(s_label_name)\n .insertSub(i_comment_line0[0]).pin(\"OCSB\").vForce(1.5)\n .execute();\n RDI_END();\n\n ON_FIRST_INVOCATION_END();\n\n int Func_result = rdi.id(\"T02_14_enable_vdda_external_bypass_V3_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T02_14_enable_vdda_external_bypass_V3\", T02_14_enable_vdda_external_bypass_V3);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description:\n# - disable bypass VDDA_LDO with ext. voltage\n# - unset ext. voltage\n# - enable pullup on ANAIO2\n# - disable VDDA pwr overwrite\n# - switch on ACC\n#############################################################################################################\ncmt('Version info: $Revision: bai430aa_rel/1 $ $Author: hmf1rt $ $Date: 2024/08/07 15:17:16 GMT $') \n# disable bypass VDDA_LDO with ext voltage\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac(\"OCP_MASK\", 0x0001) # Set masking register\nwr(\"ANA_TEST_PWR\",0x0000) # vdda_ext_en to 0, disconnect VDDA to OCSB\nrac(\"ANA_TEST_PWR\", 0x0000, 0x0001) # Check register setting\nwr(\"OCP_MASK\", 0x0000) # Reset masking register\nrac(\"OCP_MASK\", 0xffff) # Check masking register reset\n# unset ext voltage\nuav(\"OCSB\")\ndly(100e-6)\n# disable VDDA_LDO power overwrite\nwac('EXT_MODE',0xc00d) # to PMU page \nwac(\"OCP_MASK\", 0x000a) \nwr(\"PMU_TEST_OWR\",0x0000) # bit3 acc_vdda_owr_en 0, bit 1, owr_vdda_acc_en 0\nrac(\"PMU_TEST_OWR\",0x0000,0x000a) \nwr(\"OCP_MASK\", 0x0000) \nrac(\"OCP_MASK\", 0xffff) \n# switch on ACC\nwac('EXT_MODE', 0xc000)\nwac('ACC_CONF', 0xe24c) # Enable ACC in HPM; set AFS=32g; set ODR=1600; set BW=200\ndly(3e-3) \n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T02_15_disable_vdda_external_bypass_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T02_15_disable_vdda_external_bypass_V2_PAT_id\");\n rdi.dc(\"T02_15_disable_vdda_external_bypass_V2DC_id0\").label(s_label_name)\n .insertSub(i_comment_line0[0]).pin(\"OCSB\").relay(TA::ppmuRly_offALL)\n .execute();\n RDI_END();\n\n ON_FIRST_INVOCATION_END();\n \n int Func_result = rdi.id(\"T02_15_disable_vdda_external_bypass_V2_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T02_15_disable_vdda_external_bypass_V2\", T02_15_disable_vdda_external_bypass_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description:\n# - swith off ACC\n# - switch off VDDA_LDO\n# - disable pullup on ANAIO 2\n# - set ext. voltage\n# - enable bypass--connect VDDA to external Pad\n#############################################################################################################\ncmt('Version info: $Revision: 1 $ $Author: hmf1rt $ $Date: 2024/04/19 12:28:38 GMT $')\n# switch off ACC\nwac('EXT_MODE', 0xc000) # Switch to USR page\nwac('ACC_CONF',0x024c) # Disable ACC \n# power down VDDA_LDO (to prevent power request in other test items) \nwac('EXT_MODE', 0xc00d) # Switch to PMU page\nwac(\"OCP_MASK\", 0x000a) \nwr(\"PMU_TEST_OWR\",0x0008) # bit3 acc_vdda_owr_en 1, bit 1, owr_vdda_acc_en 0\nrac(\"PMU_TEST_OWR\",0x0008,0x000a) \nwr(\"OCP_MASK\", 0x0000) \nrac(\"OCP_MASK\", 0xffff) \n# set ext. voltage\nsav(\"OCSB\", 1.5, v_range=2.0, i_comp=10e-3) \ndly(100e-6)\n# enable bypass\nwac(\"EXT_MODE\", 0xc00d) # change to page D, ANA/PMU page ++ \nwac(\"OCP_MASK\", 0x0001) # Set masking register\nwr(\"ANA_TEST_PWR\",0x0001) # vdda_ext_en to 1, VDDA to OCSB\nrac(\"ANA_TEST_PWR\", 0x0001, 0x0001) # Check register setting\nwr(\"OCP_MASK\", 0x0000) # Reset masking register\nrac(\"OCP_MASK\", 0xffff) # Check masking register reset\n", "output": "/*****************************************************\n * T02_16_enable_vdda_external_bypass_econ_V1, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T02_16_enable_vdda_external_bypass_econ_V1: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static int i_funcRes0[xNSitES];\n double d_V_OCSB;\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n d_V_OCSB = Primary.getLevelSpec().getSpecValue(\"OCSB\");\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T02_16_enable_vdda_external_bypass_econ}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 1] @ avcline 1162: {sav('OCSB', 1.5, 2, 0.01, False, False)}\n valid comment[ 2] @ avcline 1940: {Test End: T02_16_enable_vdda_external_bypass_econ}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][1]).pin(\"OCSB\").vForce(d_V_OCSB)//{sav('OCSB', 1.5, 2, 0.01, False, False)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n\n ON_FIRST_INVOCATION_END();\n\n i_funcRes[curSite] = i_funcRes0[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T02_16_enable_vdda_external_bypass_econ_V1\", T02_16_enable_vdda_external_bypass_econ_V1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description:\n# - disable bypass VDDA_LDO with ext. voltage\n# - unset ext. voltage\n# - enable pullup on ANAIO2\n# - disable VDDA pwr overwrite\n# - switch on ACC\n#############################################################################################################\ncmt('Version info: $Revision: bai430aa_rel/1 $ $Author: hmf1rt $ $Date: 2024/08/07 15:17:16 GMT $') \n# disable bypass VDDA_LDO with ext voltage\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac(\"OCP_MASK\", 0x0001) # Set masking register\nwr(\"ANA_TEST_PWR\",0x0000) # vdda_ext_en to 0, disconnect VDDA to OCSB\nrac(\"ANA_TEST_PWR\", 0x0000, 0x0001) # Check register setting\nwr(\"OCP_MASK\", 0x0000) # Reset masking register\nrac(\"OCP_MASK\", 0xffff) # Check masking register reset\n# unset ext voltage\nuav(\"OCSB\")\ndly(100e-6)\n# disable VDDA_LDO power overwrite\nwac('EXT_MODE',0xc00d) # to PMU page \nwac(\"OCP_MASK\", 0x000a) \nwr(\"PMU_TEST_OWR\",0x0000) # bit3 acc_vdda_owr_en 0, bit 1, owr_vdda_acc_en 0\nrac(\"PMU_TEST_OWR\",0x0000,0x000a) \nwr(\"OCP_MASK\", 0x0000) \nrac(\"OCP_MASK\", 0xffff) \n# switch on ACC\nwac('EXT_MODE', 0xc000)\nwac('ACC_CONF', 0xe24c) # Enable ACC in HPM; set AFS=32g; set ODR=1600; set BW=200\ndly(3e-3) \n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T02_17_disable_vdda_external_bypass_econ_R1: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T02_17_disable_vdda_external_bypass_econ_R1_PAT_id\");\n rdi.dc(\"T02_17_disable_vdda_external_bypass_econ_R1DC_id0\").label(s_label_name)\n .insertSub(i_comment_line0[0]).pin(\"OCSB\").relay(TA::ppmuRly_offALL)\n .execute();\n RDI_END();\n\n ON_FIRST_INVOCATION_END();\n \n int Func_result = rdi.id(\"T02_17_disable_vdda_external_bypass_econ_R1_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T02_17_disable_vdda_external_bypass_econ_R1\", T02_17_disable_vdda_external_bypass_econ_R1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description:\n# Part1- VDDA bypass\n# - swith off ACC\n# - switch off VDDA_LDO\n# - disable pullup on ANAIO 2\n# - set ext. voltage\n# - enable bypass--connect VDDA to OCSB Pad\n# Part2- VDDDC bypass\n# - set INT1 to 1.15V\n# - enable bypass--connect VDDDC to INT1 pad\n# - switch off VDD_DC LDO\n# - set INT1 to 1.1V\n# - enable ACC in HPM\n#############################################################################################################\ncmt('Version info: $Revision: 4 $ $Author: hmf1rt $ $Date: 2024/04/23 14:41:28 GMT $')\n# Part1,vdda bypass\n# switch off ACC\nwac('EXT_MODE', 0xc000) # Switch to USR page\nwac('ACC_CONF',0x024c) # Disable ACC \n# power down VDDA_LDO (to prevent power request in other test items) \nwac('EXT_MODE', 0xc00d) # Switch to PMU page\nwac(\"OCP_MASK\", 0x000a) \nwr(\"PMU_TEST_OWR\",0x0008) # bit3 acc_vdda_owr_en 1, bit 1, owr_vdda_acc_en 0\nrac(\"PMU_TEST_OWR\",0x0008,0x000a) \nwr(\"OCP_MASK\", 0x0000) \nrac(\"OCP_MASK\", 0xffff) \n# set vdda ext. voltage\nsav(\"OCSB\", 1.5, v_range=2.0, i_comp=10e-3) \ndly(100e-6)\n# enable bypass\nwac(\"EXT_MODE\", 0xc00d) # change to page D, ANA/PMU page ++ \nwac(\"OCP_MASK\", 0x0001) # Set masking register\nwr(\"ANA_TEST_PWR\",0x0001) # vdda_ext_en to 1, VDDA to OCSB\nrac(\"ANA_TEST_PWR\", 0x0001, 0x0001) # Check register setting\nwr(\"OCP_MASK\", 0x0000) # Reset masking register\nrac(\"OCP_MASK\", 0xffff) # Check masking register reset\n# Part2, vddd_dc bypass\nsav('INT1', 1.15, v_range=2.0, i_comp=10e-3) \ndly(100e-6)\nwac('OCP_MASK', 0x0042) # Set masking register\nwr('ANA_TEST_PWR', 0x0002) # Bypass VDDD_DC to external pad\nrac('ANA_TEST_PWR', 0x0002,0x0042) # Bypass VDDD_DC to external pad\ndly(10e-6)\nwr('ANA_TEST_PWR', 0x0042) # Disable VDDD_DC LDO; keep external pad bypass\nrac('ANA_TEST_PWR', 0x0042,0x0042) # Disable VDDD_DC LDO; keep external pad bypass\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n# Set vddd_dc ext. voltage\nsav('INT1', 1.1, v_range=2.0, i_comp=10e-3)\ndly(100e-6)\n# switch on ACC\nwac('EXT_MODE', 0xc000) # Switch to USR page\nwac('ACC_CONF', 0xe24c) # Enable ACC in HPM\ndly(400e-6)\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T02_18_enable_vddd_dc_and_vdda_external_bypass_V4: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n double d_V_INT1, d_V_OCSB;\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n d_V_INT1 = Primary.getLevelSpec().getSpecValue(\"INT1\");\n d_V_OCSB = Primary.getLevelSpec().getSpecValue(\"OCSB\");\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T02_18_enable_vddd_dc_and_vdda_external_bypass_V4_PAT_id\");\n rdi.dc(\"T02_18_enable_vddd_dc_and_vdda_external_bypass_V4DC_id0\").label(s_label_name)\n .insertSub(i_comment_line0[0]).pin(\"OCSB\").vForce(d_V_OCSB)\n .insertSub(i_comment_line0[1]).pin(\"INT1\").vForce(1.15)\n .insertSub(i_comment_line0[2]).pin(\"INT1\").vForce(d_V_INT1)\n .execute();\n RDI_END();\n\n ON_FIRST_INVOCATION_END();\n \n int Func_result = rdi.id(\"T02_18_enable_vddd_dc_and_vdda_external_bypass_V4_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T02_18_enable_vddd_dc_and_vdda_external_bypass_V4\", T02_18_enable_vddd_dc_and_vdda_external_bypass_V4);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 3 $ $Author: hmf1rt $ $Date: 2024/04/23 14:41:28 GMT $')\n# switch off ACC\nwac('EXT_MODE', 0xc000) # Switch to USR page\nwac('ACC_CONF',0x024c) # Disable ACC \n# Part1 disable vdddc bypass\nsav('INT1', 1.15) # Increase supply voltage to 1.15V on pad INT1\ndly(100e-6)\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('OCP_MASK', 0x0042) # Set masking register\nwr('ANA_TEST_PWR', 0x0002) # Enable VDDD_DC_LDO; keep external bypass\nrac('ANA_TEST_PWR', 0x0002, 0x0042) # Check register setting\ndly(100e-6)\nwr('ANA_TEST_PWR', 0x0000) # Disable VDDD_DC extnernal bypass\nrac('ANA_TEST_PWR', 0x0000, 0x0042) # Check register setting\ndly(100e-6)\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nuav('INT1') # Unset voltage stimuli on INT1\ndly(100e-6)\n# Part2 disable vdda bypass\n# disable bypass VDDA_LDO with ext voltage\nwac(\"OCP_MASK\", 0x0001) # Set masking register\nwr(\"ANA_TEST_PWR\",0x0000) # vdda_ext_en to 0, disconnect VDDA to OCSB\nrac(\"ANA_TEST_PWR\", 0x0000, 0x0001) # Check register setting\nwr(\"OCP_MASK\", 0x0000) # Reset masking register\nrac(\"OCP_MASK\", 0xffff) # Check masking register reset\n# unset ext voltage\nuav(\"OCSB\")\ndly(100e-6)\n# disable VDDA_LDO power overwrite\nwac('EXT_MODE',0xc00d) # to PMU page \nwac(\"OCP_MASK\", 0x000a) \nwr(\"PMU_TEST_OWR\",0x0000) # bit3 acc_vdda_owr_en 0, bit 1, owr_vdda_acc_en 0\nrac(\"PMU_TEST_OWR\",0x0000,0x000a) \nwr(\"OCP_MASK\", 0x0000) \nrac(\"OCP_MASK\", 0xffff) \n# switch on ACC\nwac('EXT_MODE', 0xc000)\nwac('ACC_CONF', 0xe24c) # Enable ACC in HPM; set AFS=32g; set ODR=1600; set BW=200\ndly(400e-6) \n", "output": "/*****************************************************\n * T02_19_disable_vddd_dc_and_vdda_external_bypass_V3, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T02_19_disable_vddd_dc_and_vdda_external_bypass_V3: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static int i_funcRes0[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T02_19_disable_vddd_dc_and_vdda_external_bypass}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 1] @ avcline 394: {sav('INT1', 1.15, 2, 0.01, False, False)}\n valid comment[ 2] @ avcline 1384: {uav('INT1', False)}\n valid comment[ 3] @ avcline 1970: {uav('OCSB', False)}\n valid comment[ 4] @ avcline 3140: {Test End: T02_19_disable_vddd_dc_and_vdda_external_bypass}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][1]).pin(\"INT1\").vForce(1.15 V)//{sav('INT1', 1.15, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][2]).pin(\"INT1\").relay(TA::ppmuRly_offALL)////{uav('INT1', False)}\n .insertSub(i_comment_line[0][3]).pin(\"OCSB\").relay(TA::ppmuRly_offALL)////{uav('OCSB', False)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n\n ON_FIRST_INVOCATION_END();\n\n i_funcRes[curSite] = i_funcRes0[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T02_19_disable_vddd_dc_and_vdda_external_bypass_V3\", T02_19_disable_vddd_dc_and_vdda_external_bypass_V3);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: supply VDDG externally via IO_OCSB_LOWRES pin\n#############################################################################################################\nfrom test_sub_functions import *\ncmt('Version info: $Revision: 2 $ $Author: laj1mu23 $ $Date: 2024/03/25 19:45:00 GMT $')\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_ADDR', 0x0003) # Enable ATM loop back test\nwac('TM_PIN', 0x1100) # Set ATM ANAIO 4,3 => highZ\nwac('TM_CONF', 0x0000) # Disable TBs\n\nwac('EXT_MODE', 0xc00d) # Switch to PMU page\nwac(\"PMU_TEST_OWR\",0x0030) # enable VDDT (required for Gyro BG and Bias)\n\nwac(\"EXT_MODE\", 0xc00d) # change to page D, ANA/PMU page ++ \nwac(\"OCP_MASK\", 0x0010) # Set masking register\nwr(\"ANA_TEST_PWR\",0x0010) # vddg_ext_en to 1: connecting VDDG to IO_OCSB_LOWRES\nrac(\"ANA_TEST_PWR\", 0x0010, 0x0010) # Check register setting\nwr(\"OCP_MASK\", 0x0000) # Reset masking register\nrac(\"OCP_MASK\", 0xffff) # Check masking register reset\ndly(100e-6)\nsav('OCSB', 1.5) # Set voltage on OCSB\n\n", "output": "/*****************************************************\n * T02_21_enable_vddg_external_bypass_V2, description file version Notfound, avc file version Notfound\n * First Editor : jsh5sgh\n * Code generated with autocoding tool V2.9.1, in TOI2 standard way by module write_standard\n * Change History:\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T02_21_enable_vddg_external_bypass_V2: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static int i_funcRes0[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T02_21_enable_vddg_external_bypass}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 1] @ avcline 1940: {sav('OCSB', 1.5, 2, 0.01, False, False)}\n valid comment[ 1] @ avcline 1940: {Test End: T02_21_enable_vddg_external_bypass}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][1]).pin(\"OCSB\").vForce(1.5 V)//{sav('OCSB', 1.5, 2, 0.01, False, False)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n\n ON_FIRST_INVOCATION_END();\n\n i_funcRes[curSite] = i_funcRes0[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T02_21_enable_vddg_external_bypass_V2\", T02_21_enable_vddg_external_bypass_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# Description: SCAN test\n# Preamble: T03_10_scan_entry, T03_11_scan_reset\n#############################################################################################################\ncmt('Version info: $Revision: 1 $ $Author: hmf1rt $ $Date: 2024/03/13 13:36:52 GMT $')\ncmt('Execute the scan pattern file: T03_01_scan_test_V1.stil')\ncmt('The pattern timing is included in this file')\ncmt('This test item is a functional fail if any of the compare vectors in the scan patttern fails')\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T03_01_scan_test: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n static double v_VDDIO, v_VDD;\n// vector i_comment_line0;\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n// i_comment_line0 = search_comment_line(s_label_name);\n// print_key_comment(s_label_name, i_comment_line0, printFlag);\n// v_VDDIO = Primary.getLevelSpec().getSpecValue(\"VDDIO\");\n// v_VDD = Primary.getLevelSpec().getSpecValue(\"VDD\");\n//\n// rdi.dc().pin(\"VDD\").vForce(v_VDD).iRange(40 mA).execute();\n// rdi.hwRelay().pin(\"INT1,INT2\").setOff(\"ALL\").execute();\n\n\n rdi.dc().pin(\"VDDIO\").vForce(1.8).iRange(40 mA).execute();\n// rdi.dc().pin(\"SCX\").vForce(1.8).iRange(40 mA).execute();\n// Primary.getLevelSpec().change(\"VDDIO\", 1.8);\n RDI_BEGIN(mode);\n rdi.burstId(\"T03_01_scan_test_PAT_id\");\n rdi.func().label(s_label_name).execute();\n RDI_END();\n// rdi.emapLocation(TA::RAM);\n// RDI_BEGIN();\n// \trdi.emap(\"a\").label(s_label_name).pin(\"SDO\")\n// \t\t\t.failCount()\n// // \t\t\t.pfMap()\n//// \t\t\t.FFC()\n// \t\t\t.failCyc()\n// \t\t\t.execute();\n //\t\t\t\t\t\t.pin(\"pC\").failCyc(5).execute();\n // \t rdi.emap(\"b\").label(s_label_name).pin(\"MISO\").FFC().execute();\n// \tRDI_END();\n rdi.util().pin(\"K4,K8\").setOff().execute();\n ON_FIRST_INVOCATION_END();\n \n int Func_result = rdi.id(\"T03_01_scan_test_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n// int fcount=rdi.id(\"a\").getFailCount(\"SDO\");\n//\n// ARRAY_LL FailCycles = rdi.id(\"a\").getFailCyc(\"SDO\");\n//\n// cout << \"FailCycles=\" << FailCycles < i_comment_line0;\n static double IDDQ_VDD_LV[xNSitES][30];\n static double IDDQ_VDDIO_LV[xNSitES][30];\n static double IDDQ_VDDD_DC_LV[xNSitES][30];\n\n static double IDDQ_VDD_HV[xNSitES][30];\n static double IDDQ_VDDIO_HV[xNSitES][30];\n static double IDDQ_VDDD_DC_HV[xNSitES][30];\n\n static double DELTA_IDDQ_VDD[xNSitES][30];\n static double DELTA_IDDQ_VDDIO[xNSitES][30];\n static double DELTA_IDDQ_VDDD_DC[xNSitES][30];\n\n const int NUM_STEPS = 30;\n RDI_INIT();\n double d_V_VDD, d_V_VDDIO, d_V_INT1;\n\n const double stress_voltage = 1.68; // V\n\n ON_FIRST_INVOCATION_BEGIN();\n \t GET_TESTSUITE_NAME(test_name);\n d_V_VDD = Primary.getLevelSpec().getSpecValue(\"VDD\");\n d_V_VDDIO = Primary.getLevelSpec().getSpecValue(\"VDDIO\");\n d_V_INT1 = Primary.getLevelSpec().getSpecValue(\"INT1\");\n\t\t i_comment_line0 = search_comment_line(s_label_name,\"IddqTestPoint\");\t\t//key word: \"IddqTestPoint\"\n\t\t print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n\t\t rdi.enableOre(oreFlag);\n\t\t rdi.oreFile(\"./ORE_Files/rdi_ore_T03_02_IDDQ_TEST.xml\");\n\n\t\t RDI_BEGIN(mode);\n\t\t\t rdi.burstId(\"burst_id1\");\n\t\t\t rdi.dc(\"t0302_iddq_test_ID\").label(s_label_name).cont();\n\t\t\t for(int i=0;i i_comment_line0;\n\n // Auto_Code_Variable_define\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T03_03_scan_test_transitional_PAT_id\");\n rdi.func().label(s_label_name).execute();\n RDI_END();\n // Auto_Code_Execution_Part\n\n\n\n ON_FIRST_INVOCATION_END();\n // Auto_Code_Retrieve_Data\n \n int Func_result = rdi.id(\"T03_03_scan_test_transitional_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n // Auto_Code_Judge_and_log\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T03_03_scan_test_transitional\", T03_03_scan_test_transitional);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "from test_sub_functions import *\n\nCRC = get_rom_crc()\n\ncmt('Version info: $Revision: 3 $ $Author: rio1rt $ $Date: 2024/06/11 10:33:47 GMT $')\n# Setup prerequisites for MBIST\nwac('EXT_MODE',0xc00d) # Switch to PMU register page\nwcb('force_ds_pwr_on', 0x1) # Force DS power\nwac('EXT_MODE',0xc000) # Switch to USR register page\nwcb('mem_conf_ram', 0x0) # Assign 4kB RAM to MCU\n# Configure interrupt\nwac('IO_INT_CTRL', 0x0005) # Enable INT1 as output and active high\nwac('INT_MAP_MCU', 0x4000) # Map command execution interrupt to INT1\nwac('INT_CONF', 0x0001) # Use latched interrupt mode for INT1\n# Execute MBIST FW\nwr('MCU_GP_1', 0x007b) # MCU boot ASIC test; select MBIST\nwr('MCU_GP_STATUS', 0x0001) # Sync GP register\nwcb('mcu_mode', 0x3) # Power on MCU\ndly(2e-3)\nrac('MCU_GP_0', 0x0003, 0x0003) # Check MBIST is running\nras('MCU_GP_0_WITHINMBIST','MCU_GP_0') # log real value\ncalc('FEAT_ENG_STATE_WITHINMBIST', 'MCU_GP_0_WITHINMBIST', '&', '0x0003')\nlog('FEAT_ENG_STATE_WITHINMBIST') # Expect 0x3\ndly(120e-3)\n# Check MBIST result\nbc('INT1', 1) # Check FW ready interrupt\ncmt('TOI, please log INT1 status as STATUS_INT1, set function to fail if not logic one')\nlog('STATUS_INT1') # Expect 0x1\nrac('MCU_GP_0', 0x017B) # Check MBIST test result\nras('MCU_GP_0_AFTERMBIST','MCU_GP_0') # log real value, expect 0x017B\nlog('MCU_GP_0_AFTERMBIST')\ncmt(f'Reading ROM-CRC: 0x{CRC:04X}')\nrac('MCU_SW_STATUS3', CRC) # Check ROM CRC\nras('ROM_CRC_AFTERMBIST','MCU_SW_STATUS3') # log real value\nlog('ROM_CRC_AFTERMBIST') # Expect CRC\n# Clean-up\nwcb('mcu_mode', 0x0) # Power off MCU\nwac('IO_INT_CTRL', 0x0000) # Reset IO configuration\nwac('INT_MAP_MCU', 0x0000) # Reset interrupt mapping\nwac('INT_CONF', 0x0000) # Reset interrupt configuration\nwcb('mem_conf_ram', 0x2) # Set RAM config to default\nwac('EXT_MODE',0xc00d) # Switch to PMU register page\nwcb('force_ds_pwr_on', 0x0) # Disable DS power force\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T03_05_MBIST_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n// vector i_comment_line0;\n\n static int MCU_GP_0_WITHINMBIST[xNSitES];\n static int MCU_GP_0_AFTERMBIST[xNSitES];\n static int ROM_CRC_AFTERMBIST[xNSitES];\n static int FEAT_ENG_STATE_WITHINMBIST[xNSitES];\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n// i_comment_line0 = search_comment_line(s_label_name);\n// print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T03_05_MBIST_V2_PAT_id\");\n rdi.digCap(\"T03_05_MBIST_V2_Digcap_id\").label(s_label_name).pin(\"SDO\").capMode(TA::SER).samples(16*3).bitPerWord(16).execute();\n RDI_END();\n\n ON_FIRST_INVOCATION_END();\n \n ARRAY_I Vec=rdi.id(\"T03_05_MBIST_V2_Digcap_id\").getVector();\n MCU_GP_0_WITHINMBIST[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[0]);\n MCU_GP_0_AFTERMBIST[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[1]);\n ROM_CRC_AFTERMBIST[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[2]);\n FEAT_ENG_STATE_WITHINMBIST[CURRENT_SITE_NUMBER()-1] = MCU_GP_0_WITHINMBIST[CURRENT_SITE_NUMBER()-1] & 0x0003;\n\n int Func_result = rdi.id(\"T03_05_MBIST_V2_PAT_id\").getBurstPassFail();\n int STATUS_INT1 = rdi.getBurstPassFail(\"INT1\");\n FuncPrint(\"Func_result\", Func_result);\n FuncPrint(\"FEAT_ENG_STATE_WITHINMBIST\", FEAT_ENG_STATE_WITHINMBIST[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"MCU_GP_0_AFTERMBIST\", MCU_GP_0_AFTERMBIST[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"ROM_CRC_AFTERMBIST\", ROM_CRC_AFTERMBIST[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"STATUS_INT1\", STATUS_INT1);\n\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"FEAT_ENG_STATE_WITHINMBIST\", FEAT_ENG_STATE_WITHINMBIST[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"MCU_GP_0_AFTERMBIST\", MCU_GP_0_AFTERMBIST[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"ROM_CRC_AFTERMBIST\", ROM_CRC_AFTERMBIST[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"STATUS_INT1\", STATUS_INT1);\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T03_05_MBIST_V2\", T03_05_MBIST_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 2 $ $Author: laj1mu23 $ $Date: 2024/03/25 21:19:50 GMT $')\nwac('EXT_MODE', 0xc000) # Switch to USR register page\nrac('REV_ID', 0x0000, 0x00ff) # Read and check revision id\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T03_08_check_revision_ID_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n// vector i_comment_line0;\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n// i_comment_line0 = search_comment_line(s_label_name);\n// print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T03_08_check_revision_ID_V2_PAT_id\");\n// for (int i=0; i<100; i++)\n// {\n rdi.func().label(s_label_name).execute();\n// }\n RDI_END();\n\n ON_FIRST_INVOCATION_END();\n \n int Func_result = rdi.id(\"T03_08_check_revision_ID_V2_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T03_08_check_revision_ID_V2\", T03_08_check_revision_ID_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: bai430aa_rel/1 $ $Author: hmf1rt $ $Date: 2024/07/18 13:22:20 GMT $')\nwr('CMD', 0xBB3A) # 1st command for enabling the extended mode\nwr('CMD', 0x2C62) # 2nd command for enabling the extended mode\nwr('CMD', 0xA576) # 1st command for enabling the super privilege mode\nwr('CMD', 0x34D6) # 2nd command for enabling the super privilege mode\ndly(10e-6)\ndly(100e-6)\nsav('INT1', 1.1) # Apply a voltage of 1.1V on pad INT1 (VDDD_DC/DS)\nsav('OCSB', 1.1) # Apply a voltage of 1.1V on pad OCSB (VDDD_MEM)\ndly(100e-6)\nbw('ASCX', 0) # Pre-condition inputs: scan_clk = Low\nbw('ASDX', 0) # Pre-condition inputs: scan_in2 = Low\nwr('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('ANA_TEST_PWR', 0x0002) # Bypass VDDD_DC to external pad\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwr('TEST_SCAN', 0x0006) # Enable ext supply for scan; set compressed mode\ndly(100e-6)\nwr('TEST_SCAN', 0x000e) # Enter compressed scan mode\ndly(10e-6)\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T03_09_scan_entry_compressed_V1: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n static double v_INT1, v_OCSB;\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n v_INT1 = Primary.getLevelSpec().getSpecValue(\"INT1\");\n v_OCSB = Primary.getLevelSpec().getSpecValue(\"OCSB\");\n rdi.util().pin(\"K4\").setOn().execute();\n RDI_BEGIN(mode);\n rdi.burstId(\"T03_09_scan_entry_compressed_V1_PAT_id\");\n rdi.dc(\"T03_09_scan_entry_compressed_V1DC_id0\").label(s_label_name)\n .insertSub(i_comment_line0[0]).pin(\"INT1\").vForce(v_INT1)\n .insertSub(i_comment_line0[0]).pin(\"OCSB\").vForce(v_OCSB)\n .execute();\n RDI_END();\n\n ON_FIRST_INVOCATION_END();\n\n int Func_result = rdi.id(\"T03_09_scan_entry_compressed_V1_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T03_09_scan_entry_compressed_V1\", T03_09_scan_entry_compressed_V1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 4 $ $Author: hmf1rt $ $Date: 2024/06/12 11:58:00 GMT $')\nwr('CMD', 0xBB3A) # 1st command for enabling the extended mode\nwr('CMD', 0x2C62) # 2nd command for enabling the extended mode\nwr('CMD', 0xA576) # 1st command for enabling the super privilege mode\nwr('CMD', 0x34D6) # 2nd command for enabling the super privilege mode\ndly(10e-6)\ndly(100e-6)\nsav('INT1', 1.1) # Apply a voltage of 1.1V on pad INT1 (VDDD_DC/DS)\nsav('OCSB', 1.1) # Apply a voltage of 1.1V on pad OCSB (VDDD_MEM)\ndly(100e-6)\nbw('ASCX', 0) # Pre-condition inputs: scan_clk = Low\nbw('ASDX', 0) # Pre-condition inputs: scan_in2 = Low\nwr('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('ANA_TEST_PWR', 0x0002) # Bypass VDDD_DC to external pad\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwr('TEST_SCAN', 0x0002) # Enable ext supply for scan mode\ndly(100e-6)\nwr('TEST_SCAN', 0x000a) # Enter scan mode\ndly(10e-6)\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T03_10_scan_entry_V3: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n static double v_INT1, v_OCSB;\n // Auto_Code_Variable_define\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n v_INT1 = Primary.getLevelSpec().getSpecValue(\"INT1\");\n v_OCSB = Primary.getLevelSpec().getSpecValue(\"OCSB\");\n\n// rdi.util().pin(\"K4\").setOn().execute();\n// rdi.util().pin(\"K8\").setOn().execute();\n// rdi.dc().pin(\"INT1_AVI64\").vForce(0.8).iClamp(2 mA).iMeasRange(10 mA).execute();\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T03_10_scan_entry_V3_PAT_id\");\n rdi.dc(\"T03_10_scan_entry_V3DC_id0\").label(s_label_name)\n .insertSub(i_comment_line0[0]).pin(\"INT1\").vForce(v_INT1)\n .insertSub(i_comment_line0[0]).pin(\"OCSB\").vForce(v_OCSB)\n .execute();\n RDI_END();\n\n // Auto_Code_Execution_Part\n\n\n\n ON_FIRST_INVOCATION_END();\n\n\n // Auto_Code_Retrieve_Data\n \n int Func_result = rdi.id(\"T03_10_scan_entry_V3_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n // Auto_Code_Judge_and_log\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T03_10_scan_entry_V3\", T03_10_scan_entry_V3);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 1 $ $Author: hmf1rt $ $Date: 2024/03/13 13:36:52 GMT $')\n# Execute scan reset sequence\ndly(5e-6)\nbw('CSB', 0)\nbw('SCX', 1)\ndly(5e-6)\nbw('SCX', 0)\ndly(5e-6)\nbw('SCX', 1)\ndly(5e-6)\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T03_11_scan_reset_V1: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n// vector i_comment_line0;\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n// i_comment_line0 = search_comment_line(s_label_name);\n// print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T03_11_scan_reset_V1_PAT_id\");\n rdi.func().label(s_label_name).execute();\n RDI_END();\n ON_FIRST_INVOCATION_END();\n \n int Func_result = rdi.id(\"T03_11_scan_reset_V1_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T03_11_scan_reset_V1\", T03_11_scan_reset_V1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: SPI4 communication at max speed 10 MHz\n# - Entry condition STC_ACC\n# - Execute single write, single read, burst write, burst read\n#############################################################################################################\ncmt('Version info: $Revision: 4 $ $Author: luz3sgh $ $Date: 2024/05/06 05:53:19 GMT $')\ncmt('Use signal and timing conventions compliant with SPI4 mode 0')\ncmt('Use the following parameters: F_sck = 10.0 MHz')\nwac('EXT_MODE', 0xc007) # Switch to MCU register page\n# single write single read\nwr('MCU_SW_STATUS0', 0x55aa) # Write signature to register\nrac('MCU_SW_STATUS0', 0x55aa) # Read signature from register\nwr('MCU_SW_STATUS1', 0x81cc) # Write signature to register\nrac('MCU_SW_STATUS1', 0x81cc) # Read signature from register\nwr('MCU_SW_STATUS2', 0xf00f) # Write signature to register\nrac('MCU_SW_STATUS2', 0xf00f) # Read signature from register\nwr('MCU_SW_STATUS3', 0xaa55) # Write signature to register\nrac('MCU_SW_STATUS3', 0xaa55) # Read signature from register\n# burst read\nbrac('MCU_SW_STATUS0', [0x55aa,0x81cc,0xf00f,0xaa55]) # Burst read and compare\n# burst write burst read \nbwr('MCU_SW_STATUS0', [0xaa55,0xcc81,0x0ff0,0x55aa]) # Burst write\nbrac('MCU_SW_STATUS0', [0xaa55,0xcc81,0x0ff0,0x55aa]) # Burst read and compare\n# register reset\nwac('MCU_SW_STATUS0', 0x0000) # Reset register value\nwac('MCU_SW_STATUS1', 0x0000) # Reset register value\nwac('MCU_SW_STATUS2', 0x0000) # Reset register value\nwac('MCU_SW_STATUS3', 0x0000) # Reset register value\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T04_01_SPI4_test_V4: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n// vector i_comment_line0;\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n// i_comment_line0 = search_comment_line(s_label_name);\n// print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T04_01_SPI4_test_V4_PAT_id\");\n rdi.func().label(s_label_name).execute();\n RDI_END();\n ON_FIRST_INVOCATION_END();\n \n int Func_result = rdi.id(\"T04_01_SPI4_test_V4_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T04_01_SPI4_test_V4\", T04_01_SPI4_test_V4);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description:\n# - SPI4 mode 0, 10.0MHz\n#############################################################################################################\ncmt('Version info: $Revision: 2 $ $Author: luz3sgh $ $Date: 2024/05/06 05:53:19 GMT $')\n\ndef register_set():\n wac('MCU_SW_STATUS0', 0xaa55) # Write signature to register\n wac('MCU_SW_STATUS1', 0x82cc) # Write signature to register\n wac('MCU_SW_STATUS2', 0xd0ee) # Write signature to register\n wac('MCU_SW_STATUS3', 0xf00f) # Write signature to register\n brac('MCU_SW_STATUS0', [0xaa55, 0x82cc, 0xd0ee, 0xf00f]) # Burst read access and compare\n wac('MCU_SW_STATUS0', 0x0f01) # Write signature to register\n wac('MCU_SW_STATUS1', 0x1800) # Write signature to register\n brac('MCU_SW_STATUS0', [0x0f01, 0x1800])# Burst read access and compare\n \ndef register_reset():\n wac('MCU_SW_STATUS0', 0x0000) # Write reset to register\n wac('MCU_SW_STATUS1', 0x0000) # Write reset to register\n wac('MCU_SW_STATUS2', 0x0000) # Write reset to register\n wac('MCU_SW_STATUS3', 0x0000) # Write reset to register\n\nwac('EXT_MODE', 0xc007) # Switch to MCU register page\n# -- CSB Setup Time SPI4 mode 0 --\n# Test CSB Setup Time in SPI4 mode 0 (CPOL = 0 and CPHA = 0)\n# Use signal and timing conventions compliant with SPI4 mode 0 according test spec\n# Execute the 2 sequences \"register_reset\" + \"register_set\"\n# If pattern pass: In \"register_set\" shift all falling edges of CSB signal to the right\n# relative to SCX rising edges in 1 ns steps and repeat \"register_reset\"+\"register_set\"\n# If pattern fail: Record the time T_SPI4_SETUP_CSB_M0 at which \"register_set\" passed\n# for the last time\ncmt('Start sequence \"register_reset\"')\nregister_reset()\ncmt('Stop sequence \"register_reset\"')\ncmt('Start sequence \"register_set\"')\nregister_set()\ncmt('Stop sequence \"register_set\"')\ndly(100e-6)\n# -- CSB Hold Time SPI4 mode 0 --\n# Test CSB Hold Time in SPI4 mode 0 (CPOL = 0 and CPHA = 0)\n# Use signal and timing conventions compliant with SPI4 mode 0 according test spec\n# Execute the 2 sequences \"register_reset\" + \"register_set\"\n# If pattern pass: In \"register_set\" shift all rising edges of CSB signal to the left\n# relative to SCX rising edges in 1 ns steps and repeat \"register_reset\"+\"register_set\"\n# If pattern fail: Record the time T_SPI4_HOLD_CSB_M0 at which \"register_set\" passed\n# for the last time\ncmt('Start sequence \"register_reset\"')\nregister_reset()\ncmt('Stop sequence \"register_reset\"')\ncmt('Start sequence \"register_set\"')\nregister_set()\ncmt('Stop sequence \"register_set\"')\ndly(100e-6)\n# -- SDX Setup Time SPI4 mode 0 --\n# Test SDX Setup Time in SPI4 mode 0 (CPOL = 0 and CPHA = 0)\n# Use signal and timing conventions compliant with SPI4 mode 0 according test spec\n# Execute the 2 sequences \"register_reset\" + \"register_set\"\n# If pattern pass: In \"register_set\" shift all edges of SDX signal to the right\n# relative to SCX edges in 1 ns steps and repeat \"register_reset\"+\"register_set\"\n# If pattern fail: Record the time T_SPI4_SETUP_SDX_M0 at which \"register_set\" passed\n# for the last time\ncmt('Start sequence \"register_reset\"')\nregister_reset()\ncmt('Stop sequence \"register_reset\"')\ncmt('Start sequence \"register_set\"')\nregister_set()\ncmt('Stop sequence \"register_set\"')\ndly(100e-6)\n# -- SDX Hold Time SPI4 mode 0 --\n# Test SDX Hold Time in SPI4 mode 0 (CPOL = 0 and CPHA = 0)\n# Use signal and timing conventions compliant with SPI4 mode 0 according test spec\n# Execute the 2 sequences \"register_reset\" + \"register_set\"\n# If pattern pass: In \"register_set\" shift all edges of SDX signal to the left\n# relative to SCX edges in 1 ns steps and repeat \"register_reset\"+\"register_set\"\n# If pattern fail: Record the time T_SPI4_HOLD_SDX_M0 at which \"register_set\" passed \n# for the last time\ncmt('Start sequence \"register_reset\"')\nregister_reset()\ncmt('Stop sequence \"register_reset\"')\ncmt('Start sequence \"register_set\"')\nregister_set()\ncmt('Stop sequence \"register_set\"')\ndly(100e-6)\n# -- SDO Delay Time SPI4 mode 0 --\n# Test SDO Delay Time in SPI4 mode 0 (CPOL = 0 and CPHA = 0)\n# Use signal and timing conventions compliant with SPI4 mode 0 according test spec\n# Set default SDO strobe point in ATE\n# Execute the sequence \"register_set\"\n# If pattern pass: In \"register_set\" shift all SDO strobe points to the left\n# relative to SCX falling edges in 1 ns steps and repeat \"register_set\"\n# If pattern fail: Record the time T_SPI4_DELAY_SDO_M0 at which \"register_set\" passed\n# for the last time\ncmt('Start sequence \"register_set\"')\nregister_set()\ncmt('Stop sequence \"register_set\"')\ndly(100e-6)\n# -- SCX Frequency SPI4 mode 0 --\n# Test SCX frequency in SPI4 mode 0 (CPOL = 0 and CPHA = 0)\n# Use signal and timing conventions compliant with SPI4 mode 0 according test spec\n# Execute the 2 sequences \"register_reset\" + \"register_set\"\n# If pattern pass: In \"register_set\" decrease T_LOW and T_HIGH for signal SCX and the\n# timing of signal SDX and the strobe points related to signal SDO by 1.0 ns each and\n# repeat \"register_reset\"+\"register_set\"\n# If pattern fail: Record the frequency F_SPI4_SCX_M0 = 1/(T_LOW + T_HIGH)\n# at which \"register_set\" passed for the last time\ncmt('Start sequence \"register_reset\"')\nregister_reset()\ncmt('Stop sequence \"register_reset\"')\ncmt('Start sequence \"register_set\"')\nregister_set()\ncmt('Stop sequence \"register_set\"')\ndly(100e-6)\n# clean-up\nwac('MCU_SW_STATUS0', 0x0000) # Write reset to register\nwac('MCU_SW_STATUS1', 0x0000) # Write reset to register\nwac('MCU_SW_STATUS2', 0x0000) # Write reset to register\nwac('MCU_SW_STATUS3', 0x0000) # Write reset to register\n", "output": "#include \"testmethod.hpp\"\n\n//for test method API interfaces (any system include should be added above this line)\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\n//for MTP test method API interfaces\n\nusing namespace std;\n\n/**\n * Test method class.\n *\n * For each testsuite using this test method, one object of this\n * class is created.\n */\nclass T04_02_SPI4_Char_M0: public testmethod::TestMethod {\n\nprotected:\n\t int\t\tmSPI_mode;\t//M0 - M3\n\t int \t\tmSPI3_flag;\t//0 for SPI4, 1 for SPI3\n\t int\t\ti_funcRes[xNSitES];\n\t double\td_T_SETUP_CSB_M0[xNSitES];\n\t double \td_T_HOLD_CSB_M0[xNSitES];\n\t double \td_T_SETUP_SDI_M0[xNSitES];\n\t double \td_T_HOLD_SDI_M0[xNSitES];\n\t double \td_T_DELAY_SDO_M0[xNSitES];\n\t double \td_F_SCK_M0[xNSitES];\n//\t double \td_T_LOW_SCX_M0[xNSitES];\n//\t double \td_T_HIGH_SCX_M0[xNSitES];\n\t double d_T_SCK_M0[xNSitES];\n\t string mMOSIpin;\n\t string mMISOpin;\n /**\n *Initialize the parameter interface to the testflow.\n *This method is called just once after a testsuite is created.\n */\n virtual void initialize()\n {\n //Add your initialization code here\n //Note: Test Method API should not be used in this method!\n\t\taddParameter(\"SPI_mode\",\n\t\t\t\t\t \"int\",\n\t\t\t\t\t &mSPI_mode,\n\t\t\t\t\t testmethod::TM_PARAMETER_INPUT)\n\t\t .setDefault(\"0\");\n\n\t\taddParameter(\"SPI3_flag\",\n\t\t\t\t\t \"int\",\n\t\t\t\t\t &mSPI3_flag,\n\t\t\t\t\t testmethod::TM_PARAMETER_INPUT)\n\t\t .setDefault(\"0\");\n\n\t\taddParameter(\"MOSIpin\",\n\t\t\t\t\t \"string\",\n\t\t\t\t\t &mMOSIpin,\n\t\t\t\t\t testmethod::TM_PARAMETER_INPUT)\n\t\t .setDefault(\"SDX\");\n\n\t\taddParameter(\"MISOpin\",\n\t\t\t\t\t \"string\",\n\t\t\t\t\t &mMISOpin,\n\t\t\t\t\t testmethod::TM_PARAMETER_INPUT)\n\t\t .setDefault(\"SDO\");\n }\n\n /**\n *This test is invoked per site.\n */\n virtual void run()\n {\n\t string pat_name[2][4] = {{\"T04_02_SPI4_Char_M0\", \"\", \"\", \"T04_12_SPI4_Char_M3\"},\n\t\t\t \t \t \t \t {\"T04_04_SPI3_Char_M0\", \"\", \"\", \"T04_14_SPI3_Char_M3\"}};\n\n\t const string s_Label_Init \t\t= pat_name[mSPI3_flag][mSPI_mode]+\"_Init\";\n\t const string s_Label_Set \t\t= pat_name[mSPI3_flag][mSPI_mode]+\"_Set\";\n\t const string s_Label_Reset \t\t= pat_name[mSPI3_flag][mSPI_mode]+\"_Reset\";\n\n\n\t static int i_func_results[xNSitES][8];\n//\t int i_func_results[xNSitES][8];\n\t static double d_TransitionTime1[xNSitES], d_TransitionTime2[xNSitES], d_TransitionTime3[xNSitES], d_TransitionTime4[xNSitES], d_TransitionTime5[xNSitES], d_TransitionTime6[xNSitES], d_TransitionTime7[xNSitES];\n// static double d_TransitionTime1[xNSitES], d_TransitionTime2[xNSitES], d_TransitionTime3[xNSitES], d_TransitionTime4[xNSitES], d_TransitionTime5[xNSitES];\n\n\t SEARCH_FUNC_TASK TASK_spec1, TASK_spec2, TASK_spec3, TASK_spec4, TASK_spec5, TASK_spec6, TASK_spec7, TASK_spec8;\n\n\t int i_PassFail;\n\n ON_FIRST_INVOCATION_BEGIN();\n\n\t Func_Init_Var(i_funcRes, 0, xNSitES);\n\t Func_Init_Var(d_T_SETUP_CSB_M0, -999.0, xNSitES);\n\t Func_Init_Var(d_T_HOLD_CSB_M0, -999.0, xNSitES);\n\t Func_Init_Var(d_T_SETUP_SDI_M0, -999.0, xNSitES);\n\t Func_Init_Var(d_T_HOLD_SDI_M0, -999.0, xNSitES);\n\t Func_Init_Var(d_T_DELAY_SDO_M0, -999.0, xNSitES);\n\t Func_Init_Var(d_F_SCK_M0, -999.0, xNSitES);\n//\t Func_Init_Var(d_T_LOW_SCX_M0, -999.0, xNSitES);\n//\t Func_Init_Var(d_T_HIGH_SCX_M0, -999.0, xNSitES);\n\t Func_Init_Var(d_T_SCK_M0, -999.0, xNSitES);\n\n\t Func_Init_Var((int**)i_func_results, -999, xNSitES, 10);\n\t Func_Init_Var(d_TransitionTime1, -999.0, xNSitES);\n\t Func_Init_Var(d_TransitionTime2, -999.0, xNSitES);\n\t Func_Init_Var(d_TransitionTime3, -999.0, xNSitES);\n\t Func_Init_Var(d_TransitionTime4, -999.0, xNSitES);\n\t Func_Init_Var(d_TransitionTime5, -999.0, xNSitES);\n\t Func_Init_Var(d_TransitionTime6, -999.0, xNSitES);\n\t Func_Init_Var(d_TransitionTime7, -999.0, xNSitES);\n\n\t Primary.label(s_Label_Init);\n\t FLUSH();\n\t FUNCTIONAL_TEST();\n\t FOR_EACH_SITE_BEGIN();\n\t\t i_func_results[curSite][0] = GET_FUNCTIONAL_RESULT();\n\t\t Func_Print(i_func_results[curSite][0], \"i_func_results[0]\");\n\t FOR_EACH_SITE_END();\n\n Primary.timing(TIMING_SPEC(44,1));\n FLUSH(TM::APRM);\n\n\t Primary.label(s_Label_Reset);\n\t FUNCTIONAL_TEST();\n\t FOR_EACH_SITE_BEGIN();\n\t\t i_func_results[curSite][1] = GET_FUNCTIONAL_RESULT();\n\t\t Func_Print(i_func_results[curSite][1], \"i_func_results[1]\");\n\t FOR_EACH_SITE_END();\n\n //*************************CSB Setup Time SPI4 mode 0*************************\n\t Primary.label(s_Label_Set);\n\t FLUSH();\n//\t\t TASK_spec1.pin(\"CSB\").spec(\"delay1\",TM::TIM).method(TM::Binary).start(0).stop(82).resolution(0.5);\n\t TASK_spec1.pin(\"CSB\").spec(\"delay1\",TM::TIM).method(TM::Linear).start(0).stop(90).stepWidth(0.1);\n\t TASK_spec1.execute();\n\n\t FOR_EACH_SITE_BEGIN();\n\t\t i_PassFail = TASK_spec1.getPassFail(\"CSB\");\n\t\t //if find the transition point, get value\n\n\t\t if(i_PassFail)\n\t\t {\n\t\t\t d_TransitionTime1[curSite] = TASK_spec1.getPassValue(\"CSB\");\n\t\t\t d_T_SETUP_CSB_M0[curSite] = 50 - d_TransitionTime1[curSite]; //unit s\n\n\t\t\t Func_Print(d_TransitionTime1[curSite], \"Org TransitionTime1\");\n\t\t\t Func_Print(d_T_SETUP_CSB_M0[curSite], \"d_T_SETUP_CSB_M0\");\n\t\t }\n\t FOR_EACH_SITE_END();\n\n\t //*************************CSB Hold Time SPI4 mode 0*************************\n\n\t Primary.label(s_Label_Reset);\n\t FUNCTIONAL_TEST();\n\t FOR_EACH_SITE_BEGIN();\n\t\t i_func_results[curSite][2] = GET_FUNCTIONAL_RESULT();\n\t\t Func_Print(i_func_results[curSite][2], \"i_func_results[2]\");\n\t FOR_EACH_SITE_END();\n\n\t Primary.label(s_Label_Set);\n\t FLUSH();\n//\t\t TASK_spec2.pin(\"CSB\").spec(\"delay2\",TM::TIM).method(TM::Binary).start(0).stop(-70).resolution(0.5);\n\t TASK_spec2.pin(\"CSB\").spec(\"delay2\",TM::TIM).method(TM::Linear).start(0).stop(-90).stepWidth(0.1);\n\n\t TASK_spec2.execute();\n\n\t FOR_EACH_SITE_BEGIN();\n\t\t i_PassFail = TASK_spec2.getPassFail(\"CSB\");\n\t\t //if find the transition point, get value\n\t\t if(i_PassFail)\n\t\t {\n\t\t\t d_TransitionTime2[curSite] = TASK_spec2.getPassValue(\"CSB\");\n\t\t\t d_T_HOLD_CSB_M0[curSite] = ( 50 + d_TransitionTime2[curSite]) ; //unit s\n\n\t\t\t Func_Print(d_TransitionTime2[curSite], \"Org TransitionTime2\");\n\t\t\t Func_Print(d_T_HOLD_CSB_M0[curSite], \"d_T_HOLD_CSB_M0\");\n\t\t }\n\t FOR_EACH_SITE_END();\n\n //*************************SDI Setup Time SPI4 mode 0*************************\n\n\t Primary.label(s_Label_Reset);\n\t FUNCTIONAL_TEST();\n\t FOR_EACH_SITE_BEGIN();\n\t\t i_func_results[curSite][3] = GET_FUNCTIONAL_RESULT();\n\t\t Func_Print(i_func_results[curSite][3], \"i_func_results[3]\");\n\t FOR_EACH_SITE_END();\n\n\t Primary.label(s_Label_Set);\n\t FLUSH();\n//\t\t TASK_spec3.pin(mMOSIpin).spec(\"delay3\",TM::TIM).method(TM::Binary).start(0).stop(82).resolution(0.5);\n\t TASK_spec3.pin(mMOSIpin).spec(\"delay3\",TM::TIM).method(TM::Linear).start(0).stop(80).stepWidth(0.1);\n\n\t TASK_spec3.execute();\n\n\t FOR_EACH_SITE_BEGIN();\n\t\t i_PassFail = TASK_spec3.getPassFail(mMOSIpin);\n\t\t //if find the transition point, get value\n\t\t if(i_PassFail)\n\t\t {\n\t\t\t d_TransitionTime3[curSite] = TASK_spec3.getPassValue(mMOSIpin);\n\t\t\t d_T_SETUP_SDI_M0[curSite] = ( 50 - d_TransitionTime3[curSite]) ; //unit s\n\n\t\t\t Func_Print(d_TransitionTime3[curSite], \"Org TransitionTime3\");\n\t\t\t Func_Print(d_T_SETUP_SDI_M0[curSite], \"d_T_SETUP_SDI_M0\");\n\t\t }\n\t FOR_EACH_SITE_END();\n\n\n //*************************SDI Hold Time SPI4 mode 0*************************\n\t Primary.label(s_Label_Reset);\n\t FUNCTIONAL_TEST();\n\t FOR_EACH_SITE_BEGIN();\n\t\t i_func_results[curSite][4] = GET_FUNCTIONAL_RESULT();\n\t\t Func_Print(i_func_results[curSite][4], \"i_func_results[4]\");\n\t FOR_EACH_SITE_END();\n\n\t Primary.label(s_Label_Set);\n\t FLUSH();\n//\t\t TASK_spec4.pin(mMOSIpin).spec(\"delay3\",TM::TIM).method(TM::Binary).start(0).stop(-82).resolution(0.5);\n\t TASK_spec4.pin(mMOSIpin).spec(\"delay3\",TM::TIM).method(TM::Linear).start(0).stop(-90).stepWidth(0.1);\n\t TASK_spec4.execute();\n\n\t FOR_EACH_SITE_BEGIN();\n\t\t i_PassFail = TASK_spec4.getPassFail(mMOSIpin);\n\t\t //if find the transition point, get value\n\t\t if(i_PassFail)\n\t\t {\n\t\t\t d_TransitionTime4[curSite] = TASK_spec4.getPassValue(mMOSIpin);\n\t\t\t d_T_HOLD_SDI_M0[curSite] = ( 50 + d_TransitionTime4[curSite]) ; //unit s\n\n\t\t\t Func_Print(d_TransitionTime4[curSite], \"Org TransitionTime4\");\n\t\t\t Func_Print(d_T_HOLD_SDI_M0[curSite], \"d_T_HOLD_SDI_M0\");\n\t\t }\n\t FOR_EACH_SITE_END();\n\n\n //*************************SDO Delay Time SPI4 mode 0*************************\n\t Primary.label(s_Label_Reset);\n\t FUNCTIONAL_TEST();\n\t FOR_EACH_SITE_BEGIN();\n\t\t i_func_results[curSite][5] = GET_FUNCTIONAL_RESULT();\n\t\t Func_Print(i_func_results[curSite][5], \"i_func_results[5]\");\n\t FOR_EACH_SITE_END();\n\n//\t\t Primary.label(s_Label_Set_Sdo_Dly);\n\n\t Primary.label(s_Label_Set);\n\n\t FLUSH();\n//\t\t TASK_spec5.pin(mMISOpin).spec(\"delay5\",TM::TIM).method(TM::Binary).start(0).stop(-82).resolution(0.5);\n\t\tTASK_spec5.pin(mMISOpin).spec(\"delay5\",TM::TIM).method(TM::Linear).start(-80).stop(20).stepWidth(0.1);\n\t TASK_spec5.execute();\n\n\t FOR_EACH_SITE_BEGIN();\n\t\t i_PassFail = TASK_spec5.getPassFail(mMISOpin);\n\t\t //if find the transition point, get value\n\t\t if(i_PassFail)\n\t\t {\n\t\t\t d_TransitionTime5[curSite] = TASK_spec5.getPassValue(mMISOpin);\n\t\t\t d_T_DELAY_SDO_M0[curSite] = (0.8*100 + d_TransitionTime5[curSite]) ; //unit s\n\n\t\t\t Func_Print(d_TransitionTime5[curSite], \"Org TransitionTime5\");\n\t\t\t Func_Print(d_T_DELAY_SDO_M0[curSite], \"d_T_DELAY_SDO_M0\");\n\t\t }\n\t FOR_EACH_SITE_END();\n\n\n\t\t //*************************T_HIGH_SCK_MIN SPI4 mode 0*************************\n//\t\t Primary.label(s_Label_Reset);\n//\t\t FUNCTIONAL_TEST();\n//\t\t FOR_EACH_SITE_BEGIN();\n//\t\t\t i_func_results[curSite][6] = GET_FUNCTIONAL_RESULT();\n//\t\t\t Func_Print(i_func_results[curSite][6], \"i_func_results[6]\");\n//\t\t FOR_EACH_SITE_END();\n//\n//\t\t Primary.label(s_Label_Set);\n////\t\t Primary.label(\"T_10_25_SPI4_Timing_Char_M0_register_set_t_high\");\n//\t\t FLUSH();\n////\t\t TASK_spec6.spec(\"per_ns\",TM::TIM).method(TM::Binary).start(20).stop(82).resolution(1);\n//\t\t TASK_spec6.pin(\"SCX\").spec(\"delay6\",TM::TIM).method(TM::Linear).start(1).stop(40).stepWidth(1);\n//\t\t TASK_spec6.execute();\n//\n//\t\t FOR_EACH_SITE_BEGIN();\n//\t\t\t i_PassFail = TASK_spec6.getPassFail(\"SCX\");\n//\t\t\t //if find the transition point, get value\n//\t\t\t if(i_PassFail)\n//\t\t\t {\n//\n//\t\t\t\t d_TransitionTime6[curSite] = TASK_spec6.getPassValue(\"SCX\");\n//\t\t\t\t d_T_HIGH_SCX_M0[curSite] = (41 - d_TransitionTime6[curSite]) ; //unit s\n//\n//\t\t\t\t Func_Print(d_TransitionTime6[curSite], \"Org TransitionTime6\");\n//\t\t\t\t Func_Print(d_T_HIGH_SCX_M0[curSite], \"d_T_HIGH_SCX_M0\");\n//\n//\n//\t\t\t }\n//\t\t FOR_EACH_SITE_END();\n\n\t\t //*************************T_LOW_SCK_MIN SPI4 mode 0*************************\n//\t\t Primary.label(s_Label_Reset);\n//\t\t FUNCTIONAL_TEST();\n//\t\t FOR_EACH_SITE_BEGIN();\n//\t\t\t i_func_results[curSite][7] = GET_FUNCTIONAL_RESULT();\n//\t\t\t Func_Print(i_func_results[curSite][7], \"i_func_results[7]\");\n//\t\t FOR_EACH_SITE_END();\n//\n//\t\t Primary.label(s_Label_Set);\n////\t\t Primary.label(\"T_10_25_SPI4_Timing_Char_M0_register_set_t_low\");\n//\t\t FLUSH();\n////\t\t TASK_spec6.spec(\"per_ns\",TM::TIM).method(TM::Binary).start(20).stop(82).resolution(1);\n//\t\t TASK_spec7.pin(\"SCX\").spec(\"delay6\",TM::TIM).method(TM::Linear).start(-1).stop(-40).stepWidth(1);\n//\t\t TASK_spec7.execute();\n//\n//\t\t FOR_EACH_SITE_BEGIN();\n//\t\t\t i_PassFail = TASK_spec7.getPassFail(\"SCX\");\n//\t\t\t //if find the transition point, get value\n//\t\t\t if(i_PassFail)\n//\t\t\t {\n//\n//\t\t\t\t d_TransitionTime7[curSite] = TASK_spec7.getPassValue(\"SCX\");\n//\t\t\t\t d_T_LOW_SCX_M0[curSite] = (41 + d_TransitionTime7[curSite]) ; //unit s\n//\n//\t\t\t\t Func_Print(d_TransitionTime7[curSite], \"Org TransitionTime7\");\n//\t\t\t\t Func_Print(d_T_LOW_SCX_M0[curSite], \"d_T_LOW_SCX_M0\");\n//\n//\n//\t\t\t }\n//\t\t FOR_EACH_SITE_END();\n\n\n\t //*************************SCK Frequency SPI4 mode 0*************************\n\t Primary.label(s_Label_Reset);\n\t FUNCTIONAL_TEST();\n\t FOR_EACH_SITE_BEGIN();\n\t\t i_func_results[curSite][8] = GET_FUNCTIONAL_RESULT();\n\t\t Func_Print(i_func_results[curSite][8], \"i_func_results[8]\");\n\t FOR_EACH_SITE_END();\n\n\t Primary.label(s_Label_Set);\n Primary.timing(TIMING_SPEC(45,1));\n FLUSH(TM::APRM);\n//\t\t TASK_spec6.spec(\"per_ns\",TM::TIM).method(TM::Binary).start(20).stop(82).resolution(1);\n\t TASK_spec8.spec(\"f_scx\",TM::TIM).method(TM::Linear).start(10).stop(90).stepWidth(1);\n\t TASK_spec8.execute();\n\n\t FOR_EACH_SITE_BEGIN();\n\t\t i_PassFail = TASK_spec8.getPassFail();\n\t\t //if find the transition point, get value\n\t\t if(i_PassFail)\n\t\t {\n\t\t\t d_TransitionTime7[curSite] = TASK_spec8.getPassValue();\n\t\t\t d_F_SCK_M0[curSite] = d_TransitionTime7[curSite]*1e6;\t//Hz\n//\t\t\t d_F_SCK_M0[curSite] = 1000000000/TASK_spec8.getPassValue();\n//\t\t\t d_T_SCK_M0[curSite] = TASK_spec8.getPassValue();\n\n\t\t\t Func_Print(d_TransitionTime7[curSite], \"Org TransitionTime7\");\n\t\t\t Func_Print(d_F_SCK_M0[curSite], \"d_F_SCK_M0\");\n//\t\t\t Func_Print(d_T_SCK_M0[curSite], \"d_T_SCK_M0\");\n\t\t }\n\t FOR_EACH_SITE_END();\n\n\t FOR_EACH_SITE_BEGIN();\n\t\t i_funcRes[curSite] = i_func_results[curSite][0] & i_func_results[curSite][1] & i_func_results[curSite][2] &\n\t\t\t\t\t\t\t i_func_results[curSite][3] & i_func_results[curSite][4] & i_func_results[curSite][5] &\n\t\t\t\t\t\t\t i_func_results[curSite][8];\n\t FOR_EACH_SITE_END();\n\n\t ON_FIRST_INVOCATION_END();\n\n\t string spi;\n\t if (mSPI3_flag)\n\t\t spi = \"3\";\n\t else\n\t\t spi = \"4\";\n\n\t Func_Print(i_funcRes[curSite], \"i_funcRes\");\n\t TestLog(\"FUNCTIONAL_TEST\", \ti_funcRes[curSite]);\n\t TestLog(\"T_SPI\"+spi+\"_SETUP_CSB_M\"+rdi.itos(mSPI_mode), \t\t\t\td_T_SETUP_CSB_M0[curSite]*1e-9);\n\t TestLog(\"T_SPI\"+spi+\"_HOLD_CSB_M\"+rdi.itos(mSPI_mode), \t\t\t\td_T_HOLD_CSB_M0[curSite]*1e-9);\n\t TestLog(\"T_SPI\"+spi+\"_SETUP_SDX_M\"+rdi.itos(mSPI_mode), \t\t\t\td_T_SETUP_SDI_M0[curSite]*1e-9);\n\t TestLog(\"T_SPI\"+spi+\"_HOLD_SDX_M\"+rdi.itos(mSPI_mode), \t\t\t\td_T_HOLD_SDI_M0[curSite]*1e-9);\n\t TestLog(\"T_SPI\"+spi+\"_DELAY_\"+mMISOpin+\"_M\"+rdi.itos(mSPI_mode), \t\td_T_DELAY_SDO_M0[curSite]*1e-9);\n//\t TestLog(\"T_HIGH_SCX_SPI\"+spi+\"m0\", \t\td_T_HIGH_SCX_M0[curSite]*1e-9);\n//\t TestLog(\"T_LOW_SCX_SPI\"+spi+\"m0\", \t\td_T_LOW_SCX_M0[curSite]*1e-9);\n\t TestLog(\"F_SPI\"+spi+\"_SCX_M\"+rdi.itos(mSPI_mode), \t\t\td_F_SCK_M0[curSite]);\n\n return;\n }\n\n /**\n *This function will be invoked once the specified parameter's value is changed.\n *@param parameterIdentifier\n */\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n //Add your code\n //Note: Test Method API should not be used in this method!\n return;\n }\n\n /**\n *This function will be invoked once the Select Test Method Dialog is opened.\n */\n virtual const string getComment() const \n {\n string comment = \" please add your comment for this method.\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T04_02_SPI4_Char_M0\", T04_02_SPI4_Char_M0);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: SPI3 communication at max speed 10 MHz\n# - Entry condition STC_ACC\n# - Execute single write, single read, burst write, burst read\n#############################################################################################################\ncmt('Version info: $Revision: 4 $ $Author: luz3sgh $ $Date: 2024/05/06 06:30:36 GMT $')\ncmt('Use signal and timing conventions compliant with SPI3 mode 0')\ncmt('Use the following parameters: F_sck = 10.0 MHz')\nwac('EXT_MODE', 0xc007) # Switch to MCU register page\n# single write single read\nwr('MCU_SW_STATUS0', 0x55aa) # Write signature to register\nrac('MCU_SW_STATUS0', 0x55aa) # Read signature from register\nwr('MCU_SW_STATUS1', 0x81cc) # Write signature to register\nrac('MCU_SW_STATUS1', 0x81cc) # Read signature from register\nwr('MCU_SW_STATUS2', 0xf00f) # Write signature to register\nrac('MCU_SW_STATUS2', 0xf00f) # Read signature from register\nwr('MCU_SW_STATUS3', 0xaa55) # Write signature to register\nrac('MCU_SW_STATUS3', 0xaa55) # Read signature from register\n# burst read\nbrac('MCU_SW_STATUS0', [0x55aa,0x81cc,0xf00f,0xaa55]) # Burst read and compare\n# burst write burst read \nbwr('MCU_SW_STATUS0', [0xaa55,0xcc81,0x0ff0,0x55aa]) # Burst write\nbrac('MCU_SW_STATUS0', [0xaa55,0xcc81,0x0ff0,0x55aa]) # Burst read and compare\n# register reset\nwac('MCU_SW_STATUS0', 0x0000) # Reset register value\nwac('MCU_SW_STATUS1', 0x0000) # Reset register value\nwac('MCU_SW_STATUS2', 0x0000) # Reset register value\nwac('MCU_SW_STATUS3', 0x0000) # Reset register value\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T04_03_SPI3_test_V4: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n// vector i_comment_line0;\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n// i_comment_line0 = search_comment_line(s_label_name);\n// print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T04_03_SPI3_test_V4_PAT_id\");\n rdi.func().label(s_label_name).execute();\n RDI_END();\n ON_FIRST_INVOCATION_END();\n \n int Func_result = rdi.id(\"T04_03_SPI3_test_V4_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T04_03_SPI3_test_V4\", T04_03_SPI3_test_V4);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: I2C delay trimming\n# steps: 1.Enable I2C delay test\n# 2.Measure SCX rise, fall delay refernce, within loop\n# 3.Measure SCX rise, fall delay, within loop\n# 4.Find best index\n#############################################################################################################\ncmt('Version info: $Revision: 3 $ $Author: luz3sgh $ $Date: 2024/05/20 08:10:02 GMT $')\nwac('EXT_MODE',0xc00f) # Test PAGE\nwac('TEST_I2C_DEL',0x0001) # Enable bit for I2C delay test\nwac('EXT_MODE',0xc009) # IO PAGE\nfor n in range(8): \n cmt(f'Set I2C delay trimming to {n} in given range') \n wac('OCP_MASK', 0xe000) # Mask setting for IO_PAD_TRM<15:13> \n wr('IO_PAD_TRM', n*2**13) # Set I2C delay trimming\n rac('IO_PAD_TRM', n*2**13, 0xe000) # Check register setting\n wr('OCP_MASK', 0x0000) # Reset masking register\n rac('OCP_MASK', 0xffff) # Check masking register reset\n wac('EXT_MODE', 0xc00f) # Switch to TST register page\n # Reference measurement SCX RISE \n wr('DTB3', 0x002c) # scl_dl_topad on both ASDX & OOSDO\n dly(2e-6)\n bw('CSB', 0)\n bw('SCX', 0)\n dly(2e-6)\n bw('SCX', 1)\n cmt('Wait for 0 to 1 transition on OSDO and record time T_RISE_OSDO_REF')\n cmt('Wait for 0 to 1 transition on ASDX and record time T_RISE_ASDX_REF')\t \n dly(1e-6)\n cmt(f'Calc T_DLY_RISE_REF_{n} = T_RISE_ASDX_REF - T_RISE_OSDO_REF') \n # Reference measurement SCX FALL \n dly(2e-6)\n bw('SCX', 0)\n cmt('Wait for 1 to 0 transition on OSDO and record time T_FALL_OSDO_REF')\n cmt('Wait for 1 to 0 transition on ASDX and record time T_FALL_ASDX_REF')\t \n dly(1e-6)\n cmt(f'Calc T_DLY_FALL_REF_{n} = T_FALL_ASDX_REF - T_FALL_OSDO_REF')\n bw('CSB', 1)\n dly(2e-6)\n # Delay measurement SCX RISE\n wr('DTB3', 0x0027) # sck_dl_frompad@ASDX, sck_dl_topad@OSDO\n dly(2e-6)\n bw('CSB', 0)\n bw('SCX', 0)\n dly(2e-6)\n bw('SCX', 1) \n cmt('Wait for 0 to 1 transition on OSDO and record time T_RISE_OSDO_MEAS')\n cmt('Wait for 0 to 1 transition on ASDX and record time T_RISE_ASDX_MEAS')\t \n dly(1e-6)\n cmt(f'Calc T_DLY_RISE_MEAS_{n} = T_RISE_ASDX_MEAS - T_RISE_OSDO_MEAS') \n log(f'T_DLY_RISE_MEAS_{n}') \n # Delay measurement SCX FALL\n dly(2e-6) \n bw('SCX', 0)\n cmt('Wait for 1 to 0 transition on OSDO and record time T_FALL_OSDO_MEAS')\n cmt('Wait for 1 to 0 transition on ASDX and record time T_FALL_ASDX_MEAS')\t \n dly(1e-6)\n cmt(f'Calc T_DLY_FALL_MEAS_{n} = T_FALL_ASDX_MEAS - T_FALL_OSDO_MEAS') \n log(f'T_DLY_FALL_MEAS_{n}') \n bw('CSB', 1)\n dly(2e-6)\n wac('DTB3', 0x0000) # Disable DTB3X\n cmt(f'Caculate T_DLY_RISE_{n} = T_DLY_RISE_MEAS_{n} - T_DLY_RISE_REF_{n}')\n cmt(f'Caculate T_DLY_FALL_{n} = T_DLY_FALL_MEAS_{n} - T_DLY_FALL_REF_{n}')\n wac('EXT_MODE', 0xc009) # !!!Back to IO page for next loop\ncmt('Select index n = N_OPT_I2C with T_DLY_RISE_N_OPT_I2C <= target value')\ncmt('and with min. difference of T_DLY_RISE_N_OPT_I2C to target value')\ncalc('N_OPT_I2C',2) # Warning, placeholder !! Only for simulation \nlog('T_DLY_RISE_N_OPT_I2C')\nlog('N_OPT_I2C')\ncalc('N_IO_PAD_TRM_WR','N_OPT_I2C','<<',13) \nwac('OCP_MASK', 0xe000) # Mask setting for IO_PAD_TRM<15:13> \nwri('IO_PAD_TRM', 'N_IO_PAD_TRM_WR')\nras('N_IO_PAD_TRM_RD','IO_PAD_TRM')\ncalc('N_OPT_I2C_RD','N_IO_PAD_TRM_RD','>>',13)\ncmt('The test item is a functional fail if (N_OPT_I2C_RD != N_OPT_I2C')\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n# Clean\nwac('EXT_MODE',0xc00f) # Test PAGE\nwac('TEST_I2C_DEL',0x0000) \n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T04_06_i2c_delay_trimming_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n INT split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &split_pat_flag);\n vector s_splited_pat_name;\n const int split_count = 2; // Alarm:: split_count need manual confirm.\n s_splited_pat_name.resize(split_count);\n vector i_comment_line[split_count];\n\n static int N_IO_PAD_TRM_RD[xNSitES], N_OPT_I2C[xNSitES], N_IO_PAD_TRM_WR[xNSitES], N_OPT_I2C_RD[xNSitES];\n // Auto_Code_Variable_define\n ARRAY_LL N_IO_PAD_TRM_WR_rtv;\n const int Wri_Bit_Length = 33;\n const int Wri_Bit_Position = 31;\n \n double main_port_period, ASDX_port_period, OSDO_port_period;\n const int Cap_Cyc_Main_Port = 6;\n const int Cap_Cyc_Offset = 0;\n\n static double T_RISE_OSDO_REF[xNSitES][8], T_RISE_ASDX_REF[xNSitES][8], T_FALL_OSDO_REF[xNSitES][8], T_FALL_ASDX_REF[xNSitES][8];\n static double T_RISE_OSDO_MEAS[xNSitES][8], T_RISE_ASDX_MEAS[xNSitES][8], T_FALL_OSDO_MEAS[xNSitES][8], T_FALL_ASDX_MEAS[xNSitES][8];\n static double T_DLY_RISE_REF[xNSitES][8], T_DLY_FALL_REF[xNSitES][8], T_DLY_RISE_MEAS[xNSitES][8], T_DLY_FALL_MEAS[xNSitES][8];\n static double T_DLY_RISE[xNSitES][8], T_DLY_FALL[xNSitES][8];\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n\t rdi.enableOre(oreFlag);\n\t rdi.oreFile(\"./ORE_Files/rdi_ore_T04_06_I2C_DELAY_TRIMMING.xml\");\n\n GET_TESTSUITE_NAME(test_name);\n N_IO_PAD_TRM_WR_rtv.resize(xNSitES);\n\n if (split_pat_flag)\n {\n split_pattern(s_label_name,\"wri\",split_pat_flag,s_splited_pat_name);\n }\n else\n {\n for (int i = 0; i> 13;\n// \t\tcmt('Select index n = N_OPT_I2C with T_DLY_RISE_N_OPT_I2C <= target value')\n// \t\tcmt('and with min. difference of T_DLY_RISE_N_OPT_I2C to target value')\n// \t\tcalc('N_OPT_I2C',2) # Warning, placeholder !! Only for simulation\n// \t\tcalc('N_IO_PAD_TRM_WR','N_OPT_I2C','<<',13)\n// \t\twac('OCP_MASK', 0xe000) # Mask setting for IO_PAD_TRM<15:13>\n// \t\twri('IO_PAD_TRM', 'N_IO_PAD_TRM_WR')\n// \t\tras('N_IO_PAD_TRM_RD','IO_PAD_TRM')\n// \t\tcalc('N_OPT_I2C_RD','N_IO_PAD_TRM_RD','>>',13)\n// \t\tcmt('The test item is a functional fail if (N_OPT_I2C_RD != N_OPT_I2C')\n\n FOR_EACH_SITE_END();\n\n// double try_array1[5] = {5, 3.5, 0.5, 1.5, 2.49};\n// cout << \"i_Func_Optimal_Pos_Trim_Val=\" << i_Func_Optimal_Pos_Trim_Val(try_array1, 2, 5) << \"||||\" << try_array1[i_Func_Optimal_Pos_Trim_Val(try_array1, 2, 5)] << endl;\n// cout << \"i_Func_Optimal_Neg_Trim_Val=\" << i_Func_Optimal_Neg_Trim_Val(try_array1, 2, 5) << \"||||\" << try_array1[i_Func_Optimal_Neg_Trim_Val(try_array1, 2, 5)] << endl;\n// cout << \"i_Func_Optimal_Trim_Val=\" << i_Func_Optimal_Trim_Val(try_array1, 2, 5) << \"||||\" << try_array1[i_Func_Optimal_Trim_Val(try_array1, 2, 5)] << endl;\n\n rdi.runTimeVal(\"N_IO_PAD_TRM_WR_rtv\", N_IO_PAD_TRM_WR_rtv);\n\n TIMING_SPEC spi_std(1, 1);\n Primary.timing(spi_std);\n Primary.timing(1);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T04_06_i2c_delay_trimming_V2_PAT_id1\");\n rdi.digCap(\"T04_06_i2c_delay_trimming_V2_Digcap_id\").vecVarOnly().pin(\"SDO\").capMode(TA::SER).samples(16*1).bitPerWord(16).execute();\n rdi.smartVec().label(s_splited_pat_name[1]).pin(\"SDX\").writeData(\"N_IO_PAD_TRM_WR_rtv\", Wri_Bit_Length, Wri_Bit_Position).execute();\n RDI_END();\n\n rdi.dc().pin(\"VDDIO\").vForce(3 V).execute();\n Primary.getLevelSpec().change(\"VDDIO\",3);\n FLUSH(TM::APRM);\n }\n ON_FIRST_INVOCATION_END();\n\n ARRAY_I Vec=rdi.id(\"T04_06_i2c_delay_trimming_V2_Digcap_id\").getVector();\n N_IO_PAD_TRM_RD[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[0]);\n FuncPrint(\"N_IO_PAD_TRM_RD\", N_IO_PAD_TRM_RD[CURRENT_SITE_NUMBER()-1]);\n int Func_result0 = rdi.id(\"T04_06_i2c_delay_trimming_V2_PAT_id0\").getBurstPassFail();\n int Func_result1 = rdi.id(\"T04_06_i2c_delay_trimming_V2_PAT_id1\").getBurstPassFail();\n\t FuncPrint(\"Func_result0\", Func_result0);\n\t FuncPrint(\"Func_result1\", Func_result1);\n\t int Func_result = 1 * Func_result0 * Func_result1;\n\t if ((N_IO_PAD_TRM_RD[CURRENT_SITE_NUMBER()-1] >> 13 ) != N_OPT_I2C[CURRENT_SITE_NUMBER()-1]) Func_result=99;\n\t FuncPrint(\"Func_result\", Func_result);\n\n\t for (int i = 0; i<8; i++) TestLog(\"T_DLY_RISE_MEAS_\"+rdi.itos(i), T_DLY_RISE[CURRENT_SITE_NUMBER()-1][i]*1e-9);\n\t for (int i = 0; i<8; i++) TestLog(\"T_DLY_FALL_MEAS_\"+rdi.itos(i), T_DLY_FALL[CURRENT_SITE_NUMBER()-1][i]*1e-9);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"N_OPT_I2C\", N_OPT_I2C[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"T_DLY_RISE_N_OPT_I2C\", T_DLY_RISE[CURRENT_SITE_NUMBER()-1][N_OPT_I2C[CURRENT_SITE_NUMBER()-1]]*1e-9);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T04_06_i2c_delay_trimming_V2\", T04_06_i2c_delay_trimming_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: I2C delay Char\n# steps: 1.Enable I2C delay test\n# 2.Measure SCX rise, fall delay refernce, within loop\n# 3.Measure SCX rise, fall delay, within loop\n#############################################################################################################\ncmt('Version info: $Revision: 2 $ $Author: laj1mu23 $ $Date: 2024/03/25 21:13:42 GMT $')\nwac('EXT_MODE',0xc00f) # Test PAGE\nwac('TEST_I2C_DEL',0x0001) # Enable bit for I2C delay test\nwac('EXT_MODE',0xc009) # IO PAGE\nras('REG_VALUE', 'IO_PAD_TRM') # Store the current value\nfor n in range(8): \n cmt(f'Set I2C delay trimming to {n} in given range') \n wac('OCP_MASK', 0xe000) # Mask setting for IO_PAD_TRM<15:13> \n wr('IO_PAD_TRM', n*2**13) # Set I2C delay trimming\n rac('IO_PAD_TRM', n*2**13, 0xe000) # Check register setting\n wr('OCP_MASK', 0x0000) # Reset masking register\n rac('OCP_MASK', 0xffff) # Check masking register reset\n wac('EXT_MODE', 0xc00f) # Switch to TST register page\n # Reference measurement SCX RISE \n wr('DTB3', 0x002c) # scl_dl_topad on both ASDX & OOSDO\n dly(2e-6)\n bw('CSB', 0)\n bw('SCX', 0)\n dly(2e-6)\n bw('SCX', 1)\n cmt('Wait for 0 to 1 transition on OSDO and record time T_RISE_OSDO_REF')\n cmt('Wait for 0 to 1 transition on ASDX and record time T_RISE_ASDX_REF')\t \n dly(1e-6)\n cmt(f'Calc T_DLY_RISE_REF_{n} = T_RISE_ASDX_REF - T_RISE_OSDO_REF') \n # Reference measurement SCX FALL \n dly(2e-6)\n bw('SCX', 0)\n cmt('Wait for 1 to 0 transition on OSDO and record time T_FALL_OSDO_REF')\n cmt('Wait for 1 to 0 transition on ASDX and record time T_FALL_ASDX_REF')\t \n dly(1e-6)\n cmt(f'Calc T_DLY_FALL_REF_{n} = T_FALL_ASDX_REF - T_FALL_OSDO_REF')\n bw('CSB', 1)\n dly(2e-6)\n # Delay measurement SCX RISE\n wr('DTB3', 0x0027) # sck_dl_frompad@ASDX, sck_dl_topad@OSDO\n dly(2e-6)\n bw('CSB', 0)\n bw('SCX', 0)\n dly(2e-6)\n bw('SCX', 1) \n cmt('Wait for 0 to 1 transition on OSDO and record time T_RISE_OSDO_MEAS')\n cmt('Wait for 0 to 1 transition on ASDX and record time T_RISE_ASDX_MEAS')\t \n dly(1e-6)\n cmt(f'Calc T_DLY_RISE_MEAS_{n} = T_RISE_ASDX_MEAS - T_RISE_OSDO_MEAS') \n # Delay measurement SCX FALL\n dly(2e-6) \n bw('SCX', 0)\n cmt('Wait for 1 to 0 transition on OSDO and record time T_FALL_OSDO_MEAS')\n cmt('Wait for 1 to 0 transition on ASDX and record time T_FALL_ASDX_MEAS')\t \n dly(1e-6)\n cmt(f'Calc T_DLY_FALL_MEAS_{n} = T_FALL_ASDX_MEAS - T_FALL_OSDO_MEAS') \n bw('CSB', 1)\n dly(2e-6)\n wac('DTB3', 0x0000) # Disable DTB3X\n cmt(f'Caculate T_DLY_RISE_C_{n} = T_DLY_RISE_MEAS_{n} - T_DLY_RISE_REF_{n}')\n cmt(f'Caculate T_DLY_FALL_C_{n} = T_DLY_FALL_MEAS_{n} - T_DLY_FALL_REF_{n}')\n log(f'T_DLY_RISE_C_{n}')\n log(f'T_DLY_FALL_C_{n}')\n wac('EXT_MODE', 0xc009) # !!!Back to IO page for next loop\nwac('OCP_MASK', 0xe000) # Mask setting for IO_PAD_TRM<15:13> \nwri('IO_PAD_TRM', 'REG_VALUE')\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n# Clean\nwac('EXT_MODE',0xc00f) # Test PAGE\nwac('TEST_I2C_DEL',0x0000) \n", "output": "/*****************************************************\n * T04_07_I2C_Delay_Char_V2, description file version Notfound, avc file version Notfound\n * First Editor : jsh5sgh\n * Code generated with autocoding tool V2.9.1, in TOI2 standard way by module write_standard\n * Change History:\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T04_07_I2C_Delay_Char_V2: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 3;\n vector i_comment_line[i_split_count];\n\n ARRAY_I aI_Captured_0;\n static int i_REG_VALUE[xNSitES];\n static int i_WRITE_BACK[xNSitES];\n static int i_vec_Num1[32] = {0};\n static int i_funcRes0[xNSitES], i_funcRes1[xNSitES], i_funcRes2[xNSitES];\n static int i_pat_p0_len = 689;\n double main_port_period, ASDX_port_period, OSDO_port_period;\n static double T_DLY_RISE_REF[xNSitES][8], T_DLY_FALL_REF[xNSitES][8], T_DLY_RISE_MEAS[xNSitES][8], T_DLY_FALL_MEAS[xNSitES][8];\n static double T_DLY_RISE_C[xNSitES][8], T_DLY_FALL_C[xNSitES][8];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(i_REG_VALUE, 9, xNSitES);\n Func_Init_Var(i_REG_VALUE, 9, xNSitES);\n \n //!\"CTmsg: cut pattern to 2 parts @ oriAVCvecline [13563]\n //!\"CTmsg: cut pattern to 2 parts @ binarypatline [13553]\n if (i_split_pat_flag)\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n }\n else\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n for(int i=0; i }\n valid comment[ 1] @ avcline 586: {ras('REG_VALUE', 'IO_PAD_TRM')}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.port(\"Non_OSDO_ASDX_Port\").digCap(\"digcapid_0\").vecVarOnly().pin(\"SDO\").capMode(TA::SER).bitPerWord(16).samples(1*16).execute();\n rdi.port(\"Non_OSDO_ASDX_Port\").func().label(s_splited_pat_name[0]).execute();\n rdi.port(\"ASDX_Port\").waitCycle(i_pat_p0_len*Port_factor_ASDX);\n rdi.port(\"OSDO_Port\").waitCycle(i_pat_p0_len*Port_factor_ASDX);\n RDI_END();\n\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n aI_Captured_0 = rdi.id(\"digcapid_0\").getVector(\"SDO\");\n aI_Captured_0[0] = Switch_High_Low_Bits_16Bits(aI_Captured_0[0]);\n i_REG_VALUE[curSite] = aI_Captured_0[0];\n FuncPrint(\"REG_VALUE\",i_REG_VALUE[curSite]);\n FOR_EACH_SITE_END();\n\n /* Ori key coments in subpat1 ~~~~~~~~~~~~~~\n\t\t\t===========Pattern T04_07_I2C_Delay_Char_V2_AVC2_PY2_part1=============\n\t\t\tkey comment[0]is || TCMT 0,\" cut_here search_here {cmt: Set I2C delay trimming to 0 in given range} {wac('OCP_MASK', 0xe000, 0)}\"\n\t\t\tkey comment[1]is || TCMT 902,\" search_here {bw('SCX', 1)} {cmt: Wait for 0 to 1 transition on OSDO and record time T_RISE_OSDO_REF} {cmt: Wait for 0 to 1 transition on ASDX and record time T_RISE_ASDX_REF} {dly(1e-06, 0)}\"\n\t\t\tkey comment[2]is || TCMT 915,\" search_here {cmt: Calc T_DLY_RISE_REF_0 = T_RISE_ASDX_REF - T_RISE_OSDO_REF} {dly(2e-06, 0)}\"\n\t\t\tkey comment[3]is || TCMT 942,\" search_here {bw('SCX', 0)} {cmt: Wait for 1 to 0 transition on OSDO and record time T_FALL_OSDO_REF} {cmt: Wait for 1 to 0 transition on ASDX and record time T_FALL_ASDX_REF} {dly(1e-06, 0)}\"\n\t\t\tkey comment[4]is || TCMT 956,\" search_here {cmt: Calc T_DLY_FALL_REF_0 = T_FALL_ASDX_REF - T_FALL_OSDO_REF} {bw('CSB', 1)} {dly(2e-06, 0)}\"\n\t\t\tkey comment[5]is || TCMT 1117,\" search_here {bw('SCX', 1)} {cmt: Wait for 0 to 1 transition on OSDO and record time T_RISE_OSDO_MEAS} {cmt: Wait for 0 to 1 transition on ASDX and record time T_RISE_ASDX_MEAS} {dly(1e-06, 0)}\"\n\t\t\tkey comment[6]is || TCMT 1130,\" search_here {cmt: Calc T_DLY_RISE_MEAS_0 = T_RISE_ASDX_MEAS - T_RISE_OSDO_MEAS} {dly(2e-06, 0)}\"\n\t\t\tkey comment[7]is || TCMT 1157,\" search_here {bw('SCX', 0)} {cmt: Wait for 1 to 0 transition on OSDO and record time T_FALL_OSDO_MEAS} {cmt: Wait for 1 to 0 transition on ASDX and record time T_FALL_ASDX_MEAS} {dly(1e-06, 0)}\"\n\t\t\tkey comment[8]is || TCMT 1171,\" search_here {cmt: Calc T_DLY_FALL_MEAS_0 = T_FALL_ASDX_MEAS - T_FALL_OSDO_MEAS} {bw('CSB', 1)} {dly(2e-06, 0)}\"\n\t\t\tkey comment[9]is || TCMT 1390,\" search_here {cmt: Caculate T_DLY_RISE_C_0 = T_DLY_RISE_MEAS_0 - T_DLY_RISE_REF_0} {cmt: Caculate T_DLY_FALL_C_0 = T_DLY_FALL_MEAS_0 - T_DLY_FALL_REF_0} {log('T_DLY_RISE_C_0', '', '', 0, 0)}\"\n\t\t\tkey comment[10]is || TCMT 1391,\" search_here {log('T_DLY_FALL_C_0', '', '', 0, 0)}\"\n\n\t\t\tkey comment[11]is || TCMT 1584,\" search_here {cmt: Set I2C delay trimming to 1 in given range} {wac('OCP_MASK', 0xe000, 0)}\"\n\t\t\tkey comment[12]is || TCMT 2486,\" search_here {bw('SCX', 1)} {cmt: Wait for 0 to 1 transition on OSDO and record time T_RISE_OSDO_REF} {cmt: Wait for 0 to 1 transition on ASDX and record time T_RISE_ASDX_REF} {dly(1e-06, 0)}\"\n\t\t\tkey comment[13]is || TCMT 2499,\" search_here {cmt: Calc T_DLY_RISE_REF_1 = T_RISE_ASDX_REF - T_RISE_OSDO_REF} {dly(2e-06, 0)}\"\n\t\t\tkey comment[14]is || TCMT 2526,\" search_here {bw('SCX', 0)} {cmt: Wait for 1 to 0 transition on OSDO and record time T_FALL_OSDO_REF} {cmt: Wait for 1 to 0 transition on ASDX and record time T_FALL_ASDX_REF} {dly(1e-06, 0)}\"\n\t\t\tkey comment[15]is || TCMT 2540,\" search_here {cmt: Calc T_DLY_FALL_REF_1 = T_FALL_ASDX_REF - T_FALL_OSDO_REF} {bw('CSB', 1)} {dly(2e-06, 0)}\"\n\t\t\tkey comment[16]is || TCMT 2701,\" search_here {bw('SCX', 1)} {cmt: Wait for 0 to 1 transition on OSDO and record time T_RISE_OSDO_MEAS} {cmt: Wait for 0 to 1 transition on ASDX and record time T_RISE_ASDX_MEAS} {dly(1e-06, 0)}\"\n\t\t\tkey comment[17]is || TCMT 2714,\" search_here {cmt: Calc T_DLY_RISE_MEAS_1 = T_RISE_ASDX_MEAS - T_RISE_OSDO_MEAS} {dly(2e-06, 0)}\"\n\t\t\tkey comment[18]is || TCMT 2741,\" search_here {bw('SCX', 0)} {cmt: Wait for 1 to 0 transition on OSDO and record time T_FALL_OSDO_MEAS} {cmt: Wait for 1 to 0 transition on ASDX and record time T_FALL_ASDX_MEAS} {dly(1e-06, 0)}\"\n\t\t\tkey comment[19]is || TCMT 2755,\" search_here {cmt: Calc T_DLY_FALL_MEAS_1 = T_FALL_ASDX_MEAS - T_FALL_OSDO_MEAS} {bw('CSB', 1)} {dly(2e-06, 0)}\"\n\t\t\tkey comment[20]is || TCMT 2974,\" search_here {cmt: Caculate T_DLY_RISE_C_1 = T_DLY_RISE_MEAS_1 - T_DLY_RISE_REF_1} {cmt: Caculate T_DLY_FALL_C_1 = T_DLY_FALL_MEAS_1 - T_DLY_FALL_REF_1} {log('T_DLY_RISE_C_1', '', '', 0, 0)}\"\n\t\t\tkey comment[21]is || TCMT 2975,\" search_here {log('T_DLY_FALL_C_1', '', '', 0, 0)}\"\n\n\t\t\tkey comment[22]is || TCMT 3168,\" search_here {cmt: Set I2C delay trimming to 2 in given range} {wac('OCP_MASK', 0xe000, 0)}\"\n\t\t\tkey comment[23]is || TCMT 4070,\" search_here {bw('SCX', 1)} {cmt: Wait for 0 to 1 transition on OSDO and record time T_RISE_OSDO_REF} {cmt: Wait for 0 to 1 transition on ASDX and record time T_RISE_ASDX_REF} {dly(1e-06, 0)}\"\n\t\t\tkey comment[24]is || TCMT 4083,\" search_here {cmt: Calc T_DLY_RISE_REF_2 = T_RISE_ASDX_REF - T_RISE_OSDO_REF} {dly(2e-06, 0)}\"\n\t\t\tkey comment[25]is || TCMT 4110,\" search_here {bw('SCX', 0)} {cmt: Wait for 1 to 0 transition on OSDO and record time T_FALL_OSDO_REF} {cmt: Wait for 1 to 0 transition on ASDX and record time T_FALL_ASDX_REF} {dly(1e-06, 0)}\"\n\t\t\tkey comment[26]is || TCMT 4124,\" search_here {cmt: Calc T_DLY_FALL_REF_2 = T_FALL_ASDX_REF - T_FALL_OSDO_REF} {bw('CSB', 1)} {dly(2e-06, 0)}\"\n\t\t\tkey comment[27]is || TCMT 4285,\" search_here {bw('SCX', 1)} {cmt: Wait for 0 to 1 transition on OSDO and record time T_RISE_OSDO_MEAS} {cmt: Wait for 0 to 1 transition on ASDX and record time T_RISE_ASDX_MEAS} {dly(1e-06, 0)}\"\n\t\t\tkey comment[28]is || TCMT 4298,\" search_here {cmt: Calc T_DLY_RISE_MEAS_2 = T_RISE_ASDX_MEAS - T_RISE_OSDO_MEAS} {dly(2e-06, 0)}\"\n\t\t\tkey comment[29]is || TCMT 4325,\" search_here {bw('SCX', 0)} {cmt: Wait for 1 to 0 transition on OSDO and record time T_FALL_OSDO_MEAS} {cmt: Wait for 1 to 0 transition on ASDX and record time T_FALL_ASDX_MEAS} {dly(1e-06, 0)}\"\n\t\t\tkey comment[30]is || TCMT 4339,\" search_here {cmt: Calc T_DLY_FALL_MEAS_2 = T_FALL_ASDX_MEAS - T_FALL_OSDO_MEAS} {bw('CSB', 1)} {dly(2e-06, 0)}\"\n\t\t\tkey comment[31]is || TCMT 4558,\" search_here {cmt: Caculate T_DLY_RISE_C_2 = T_DLY_RISE_MEAS_2 - T_DLY_RISE_REF_2} {cmt: Caculate T_DLY_FALL_C_2 = T_DLY_FALL_MEAS_2 - T_DLY_FALL_REF_2} {log('T_DLY_RISE_C_2', '', '', 0, 0)}\"\n\t\t\tkey comment[32]is || TCMT 4559,\" search_here {log('T_DLY_FALL_C_2', '', '', 0, 0)}\"\n\t\t\tkey comment[33]is || TCMT 4752,\" search_here {cmt: Set I2C delay trimming to 3 in given range} {wac('OCP_MASK', 0xe000, 0)}\"\n\t\t\tkey comment[34]is || TCMT 5654,\" search_here {bw('SCX', 1)} {cmt: Wait for 0 to 1 transition on OSDO and record time T_RISE_OSDO_REF} {cmt: Wait for 0 to 1 transition on ASDX and record time T_RISE_ASDX_REF} {dly(1e-06, 0)}\"\n\t\t\tkey comment[35]is || TCMT 5667,\" search_here {cmt: Calc T_DLY_RISE_REF_3 = T_RISE_ASDX_REF - T_RISE_OSDO_REF} {dly(2e-06, 0)}\"\n\t\t\tkey comment[36]is || TCMT 5694,\" search_here {bw('SCX', 0)} {cmt: Wait for 1 to 0 transition on OSDO and record time T_FALL_OSDO_REF} {cmt: Wait for 1 to 0 transition on ASDX and record time T_FALL_ASDX_REF} {dly(1e-06, 0)}\"\n\t\t\tkey comment[37]is || TCMT 5708,\" search_here {cmt: Calc T_DLY_FALL_REF_3 = T_FALL_ASDX_REF - T_FALL_OSDO_REF} {bw('CSB', 1)} {dly(2e-06, 0)}\"\n\t\t\tkey comment[38]is || TCMT 5869,\" search_here {bw('SCX', 1)} {cmt: Wait for 0 to 1 transition on OSDO and record time T_RISE_OSDO_MEAS} {cmt: Wait for 0 to 1 transition on ASDX and record time T_RISE_ASDX_MEAS} {dly(1e-06, 0)}\"\n\t\t\tkey comment[39]is || TCMT 5882,\" search_here {cmt: Calc T_DLY_RISE_MEAS_3 = T_RISE_ASDX_MEAS - T_RISE_OSDO_MEAS} {dly(2e-06, 0)}\"\n\t\t\tkey comment[40]is || TCMT 5909,\" search_here {bw('SCX', 0)} {cmt: Wait for 1 to 0 transition on OSDO and record time T_FALL_OSDO_MEAS} {cmt: Wait for 1 to 0 transition on ASDX and record time T_FALL_ASDX_MEAS} {dly(1e-06, 0)}\"\n\t\t\tkey comment[41]is || TCMT 5923,\" search_here {cmt: Calc T_DLY_FALL_MEAS_3 = T_FALL_ASDX_MEAS - T_FALL_OSDO_MEAS} {bw('CSB', 1)} {dly(2e-06, 0)}\"\n\t\t\tkey comment[42]is || TCMT 6142,\" search_here {cmt: Caculate T_DLY_RISE_C_3 = T_DLY_RISE_MEAS_3 - T_DLY_RISE_REF_3} {cmt: Caculate T_DLY_FALL_C_3 = T_DLY_FALL_MEAS_3 - T_DLY_FALL_REF_3} {log('T_DLY_RISE_C_3', '', '', 0, 0)}\"\n\t\t\tkey comment[43]is || TCMT 6143,\" search_here {log('T_DLY_FALL_C_3', '', '', 0, 0)}\"\n\t\t\tkey comment[44]is || TCMT 6336,\" search_here {cmt: Set I2C delay trimming to 4 in given range} {wac('OCP_MASK', 0xe000, 0)}\"\n\t\t\tkey comment[45]is || TCMT 7238,\" search_here {bw('SCX', 1)} {cmt: Wait for 0 to 1 transition on OSDO and record time T_RISE_OSDO_REF} {cmt: Wait for 0 to 1 transition on ASDX and record time T_RISE_ASDX_REF} {dly(1e-06, 0)}\"\n\t\t\tkey comment[46]is || TCMT 7251,\" search_here {cmt: Calc T_DLY_RISE_REF_4 = T_RISE_ASDX_REF - T_RISE_OSDO_REF} {dly(2e-06, 0)}\"\n\t\t\tkey comment[47]is || TCMT 7278,\" search_here {bw('SCX', 0)} {cmt: Wait for 1 to 0 transition on OSDO and record time T_FALL_OSDO_REF} {cmt: Wait for 1 to 0 transition on ASDX and record time T_FALL_ASDX_REF} {dly(1e-06, 0)}\"\n\t\t\tkey comment[48]is || TCMT 7292,\" search_here {cmt: Calc T_DLY_FALL_REF_4 = T_FALL_ASDX_REF - T_FALL_OSDO_REF} {bw('CSB', 1)} {dly(2e-06, 0)}\"\n\t\t\tkey comment[49]is || TCMT 7453,\" search_here {bw('SCX', 1)} {cmt: Wait for 0 to 1 transition on OSDO and record time T_RISE_OSDO_MEAS} {cmt: Wait for 0 to 1 transition on ASDX and record time T_RISE_ASDX_MEAS} {dly(1e-06, 0)}\"\n\t\t\tkey comment[50]is || TCMT 7466,\" search_here {cmt: Calc T_DLY_RISE_MEAS_4 = T_RISE_ASDX_MEAS - T_RISE_OSDO_MEAS} {dly(2e-06, 0)}\"\n\t\t\tkey comment[51]is || TCMT 7493,\" search_here {bw('SCX', 0)} {cmt: Wait for 1 to 0 transition on OSDO and record time T_FALL_OSDO_MEAS} {cmt: Wait for 1 to 0 transition on ASDX and record time T_FALL_ASDX_MEAS} {dly(1e-06, 0)}\"\n\t\t\tkey comment[52]is || TCMT 7507,\" search_here {cmt: Calc T_DLY_FALL_MEAS_4 = T_FALL_ASDX_MEAS - T_FALL_OSDO_MEAS} {bw('CSB', 1)} {dly(2e-06, 0)}\"\n\t\t\tkey comment[53]is || TCMT 7726,\" search_here {cmt: Caculate T_DLY_RISE_C_4 = T_DLY_RISE_MEAS_4 - T_DLY_RISE_REF_4} {cmt: Caculate T_DLY_FALL_C_4 = T_DLY_FALL_MEAS_4 - T_DLY_FALL_REF_4} {log('T_DLY_RISE_C_4', '', '', 0, 0)}\"\n\t\t\tkey comment[54]is || TCMT 7727,\" search_here {log('T_DLY_FALL_C_4', '', '', 0, 0)}\"\n\t\t\tkey comment[55]is || TCMT 7920,\" search_here {cmt: Set I2C delay trimming to 5 in given range} {wac('OCP_MASK', 0xe000, 0)}\"\n\t\t\tkey comment[56]is || TCMT 8822,\" search_here {bw('SCX', 1)} {cmt: Wait for 0 to 1 transition on OSDO and record time T_RISE_OSDO_REF} {cmt: Wait for 0 to 1 transition on ASDX and record time T_RISE_ASDX_REF} {dly(1e-06, 0)}\"\n\t\t\tkey comment[57]is || TCMT 8835,\" search_here {cmt: Calc T_DLY_RISE_REF_5 = T_RISE_ASDX_REF - T_RISE_OSDO_REF} {dly(2e-06, 0)}\"\n\t\t\tkey comment[58]is || TCMT 8862,\" search_here {bw('SCX', 0)} {cmt: Wait for 1 to 0 transition on OSDO and record time T_FALL_OSDO_REF} {cmt: Wait for 1 to 0 transition on ASDX and record time T_FALL_ASDX_REF} {dly(1e-06, 0)}\"\n\t\t\tkey comment[59]is || TCMT 8876,\" search_here {cmt: Calc T_DLY_FALL_REF_5 = T_FALL_ASDX_REF - T_FALL_OSDO_REF} {bw('CSB', 1)} {dly(2e-06, 0)}\"\n\t\t\tkey comment[60]is || TCMT 9037,\" search_here {bw('SCX', 1)} {cmt: Wait for 0 to 1 transition on OSDO and record time T_RISE_OSDO_MEAS} {cmt: Wait for 0 to 1 transition on ASDX and record time T_RISE_ASDX_MEAS} {dly(1e-06, 0)}\"\n\t\t\tkey comment[61]is || TCMT 9050,\" search_here {cmt: Calc T_DLY_RISE_MEAS_5 = T_RISE_ASDX_MEAS - T_RISE_OSDO_MEAS} {dly(2e-06, 0)}\"\n\t\t\tkey comment[62]is || TCMT 9077,\" search_here {bw('SCX', 0)} {cmt: Wait for 1 to 0 transition on OSDO and record time T_FALL_OSDO_MEAS} {cmt: Wait for 1 to 0 transition on ASDX and record time T_FALL_ASDX_MEAS} {dly(1e-06, 0)}\"\n\t\t\tkey comment[63]is || TCMT 9091,\" search_here {cmt: Calc T_DLY_FALL_MEAS_5 = T_FALL_ASDX_MEAS - T_FALL_OSDO_MEAS} {bw('CSB', 1)} {dly(2e-06, 0)}\"\n\t\t\tkey comment[64]is || TCMT 9310,\" search_here {cmt: Caculate T_DLY_RISE_C_5 = T_DLY_RISE_MEAS_5 - T_DLY_RISE_REF_5} {cmt: Caculate T_DLY_FALL_C_5 = T_DLY_FALL_MEAS_5 - T_DLY_FALL_REF_5} {log('T_DLY_RISE_C_5', '', '', 0, 0)}\"\n\t\t\tkey comment[65]is || TCMT 9311,\" search_here {log('T_DLY_FALL_C_5', '', '', 0, 0)}\"\n\t\t\tkey comment[66]is || TCMT 9504,\" search_here {cmt: Set I2C delay trimming to 6 in given range} {wac('OCP_MASK', 0xe000, 0)}\"\n\t\t\tkey comment[67]is || TCMT 10406,\" search_here {bw('SCX', 1)} {cmt: Wait for 0 to 1 transition on OSDO and record time T_RISE_OSDO_REF} {cmt: Wait for 0 to 1 transition on ASDX and record time T_RISE_ASDX_REF} {dly(1e-06, 0)}\"\n\t\t\tkey comment[68]is || TCMT 10419,\" search_here {cmt: Calc T_DLY_RISE_REF_6 = T_RISE_ASDX_REF - T_RISE_OSDO_REF} {dly(2e-06, 0)}\"\n\t\t\tkey comment[69]is || TCMT 10446,\" search_here {bw('SCX', 0)} {cmt: Wait for 1 to 0 transition on OSDO and record time T_FALL_OSDO_REF} {cmt: Wait for 1 to 0 transition on ASDX and record time T_FALL_ASDX_REF} {dly(1e-06, 0)}\"\n\t\t\tkey comment[70]is || TCMT 10460,\" search_here {cmt: Calc T_DLY_FALL_REF_6 = T_FALL_ASDX_REF - T_FALL_OSDO_REF} {bw('CSB', 1)} {dly(2e-06, 0)}\"\n\t\t\tkey comment[71]is || TCMT 10621,\" search_here {bw('SCX', 1)} {cmt: Wait for 0 to 1 transition on OSDO and record time T_RISE_OSDO_MEAS} {cmt: Wait for 0 to 1 transition on ASDX and record time T_RISE_ASDX_MEAS} {dly(1e-06, 0)}\"\n\t\t\tkey comment[72]is || TCMT 10634,\" search_here {cmt: Calc T_DLY_RISE_MEAS_6 = T_RISE_ASDX_MEAS - T_RISE_OSDO_MEAS} {dly(2e-06, 0)}\"\n\t\t\tkey comment[73]is || TCMT 10661,\" search_here {bw('SCX', 0)} {cmt: Wait for 1 to 0 transition on OSDO and record time T_FALL_OSDO_MEAS} {cmt: Wait for 1 to 0 transition on ASDX and record time T_FALL_ASDX_MEAS} {dly(1e-06, 0)}\"\n\t\t\tkey comment[74]is || TCMT 10675,\" search_here {cmt: Calc T_DLY_FALL_MEAS_6 = T_FALL_ASDX_MEAS - T_FALL_OSDO_MEAS} {bw('CSB', 1)} {dly(2e-06, 0)}\"\n\t\t\tkey comment[75]is || TCMT 10894,\" search_here {cmt: Caculate T_DLY_RISE_C_6 = T_DLY_RISE_MEAS_6 - T_DLY_RISE_REF_6} {cmt: Caculate T_DLY_FALL_C_6 = T_DLY_FALL_MEAS_6 - T_DLY_FALL_REF_6} {log('T_DLY_RISE_C_6', '', '', 0, 0)}\"\n\t\t\tkey comment[76]is || TCMT 10895,\" search_here {log('T_DLY_FALL_C_6', '', '', 0, 0)}\"\n\t\t\tkey comment[77]is || TCMT 11088,\" search_here {cmt: Set I2C delay trimming to 7 in given range} {wac('OCP_MASK', 0xe000, 0)}\"\n\t\t\tkey comment[78]is || TCMT 11990,\" search_here {bw('SCX', 1)} {cmt: Wait for 0 to 1 transition on OSDO and record time T_RISE_OSDO_REF} {cmt: Wait for 0 to 1 transition on ASDX and record time T_RISE_ASDX_REF} {dly(1e-06, 0)}\"\n\t\t\tkey comment[79]is || TCMT 12003,\" search_here {cmt: Calc T_DLY_RISE_REF_7 = T_RISE_ASDX_REF - T_RISE_OSDO_REF} {dly(2e-06, 0)}\"\n\t\t\tkey comment[80]is || TCMT 12030,\" search_here {bw('SCX', 0)} {cmt: Wait for 1 to 0 transition on OSDO and record time T_FALL_OSDO_REF} {cmt: Wait for 1 to 0 transition on ASDX and record time T_FALL_ASDX_REF} {dly(1e-06, 0)}\"\n\t\t\tkey comment[81]is || TCMT 12044,\" search_here {cmt: Calc T_DLY_FALL_REF_7 = T_FALL_ASDX_REF - T_FALL_OSDO_REF} {bw('CSB', 1)} {dly(2e-06, 0)}\"\n\t\t\tkey comment[82]is || TCMT 12205,\" search_here {bw('SCX', 1)} {cmt: Wait for 0 to 1 transition on OSDO and record time T_RISE_OSDO_MEAS} {cmt: Wait for 0 to 1 transition on ASDX and record time T_RISE_ASDX_MEAS} {dly(1e-06, 0)}\"\n\t\t\tkey comment[83]is || TCMT 12218,\" search_here {cmt: Calc T_DLY_RISE_MEAS_7 = T_RISE_ASDX_MEAS - T_RISE_OSDO_MEAS} {dly(2e-06, 0)}\"\n\t\t\tkey comment[84]is || TCMT 12245,\" search_here {bw('SCX', 0)} {cmt: Wait for 1 to 0 transition on OSDO and record time T_FALL_OSDO_MEAS} {cmt: Wait for 1 to 0 transition on ASDX and record time T_FALL_ASDX_MEAS} {dly(1e-06, 0)}\"\n\t\t\tkey comment[85]is || TCMT 12259,\" search_here {cmt: Calc T_DLY_FALL_MEAS_7 = T_FALL_ASDX_MEAS - T_FALL_OSDO_MEAS} {bw('CSB', 1)} {dly(2e-06, 0)}\"\n\t\t\tkey comment[86]is || TCMT 12478,\" search_here {cmt: Caculate T_DLY_RISE_C_7 = T_DLY_RISE_MEAS_7 - T_DLY_RISE_REF_7} {cmt: Caculate T_DLY_FALL_C_7 = T_DLY_FALL_MEAS_7 - T_DLY_FALL_REF_7} {log('T_DLY_RISE_C_7', '', '', 0, 0)}\"\n\t\t\tkey comment[87]is || TCMT 12479,\" search_here {log('T_DLY_FALL_C_7', '', '', 0, 0)}\"\n\t\t\t*/\n int index[4*8];\n int i_cnt=0;\n for(int i=0; i<8; i++) {\n \t for(int j=0; j<4; j++) {\n \t\t index[i_cnt] = i*11 + j*2 + 1;\n \t\t i_cnt++;\n \t }\n }\n\n RDI_BEGIN(mode);\n\t\t\t rdi.burstId(\"burst_id1\");\n\t\t\t rdi.port(\"Non_OSDO_ASDX_Port\").func().label(s_splited_pat_name[1]).startVec(0).stopVec(i_comment_line[1][index[0]]-1).execute();\n\t\t\t rdi.portSync();\n\t\t\t for(int i=0; i<31; i++)\n\t\t\t {\n\t\t\t\t rdi.port(\"ASDX_Port\").digCap(\"T04_07_ASDX\"+rdi.itos(i)).pin(\"ASDX\").capMode(TA::SER).samples(800).bitPerWord(1).execute();\n\t\t\t\t rdi.port(\"OSDO_Port\").digCap(\"T04_07_OSDO\"+rdi.itos(i)).pin(\"OSDO\").capMode(TA::SER).samples(800).bitPerWord(1).execute();\n\t\t\t\t rdi.port(\"Non_OSDO_ASDX_Port\").func().label(s_splited_pat_name[1]).startVec(i_comment_line[1][index[i]]).stopVec(i_comment_line[1][index[i+1]]-1).execute();\n\t\t\t\t rdi.portSync();\n\t\t\t }\n\t\t\t rdi.port(\"ASDX_Port\").digCap(\"T04_07_ASDX\"+rdi.itos(31)).pin(\"ASDX\").capMode(TA::SER).samples(800).bitPerWord(1).execute();\n\t\t\t rdi.port(\"OSDO_Port\").digCap(\"T04_07_OSDO\"+rdi.itos(31)).pin(\"OSDO\").capMode(TA::SER).samples(800).bitPerWord(1).execute();\n\t\t\t rdi.port(\"Non_OSDO_ASDX_Port\").func().label(s_splited_pat_name[1]).startVec(i_comment_line[1][index[31]]-1).execute();\n\t\t\t rdi.portSync();\n RDI_END();\n\n FOR_EACH_SITE_BEGIN();\n i_funcRes1[curSite] = rdi.id(\"burst_id1\").getBurstPassFail();\n for(int i=0; i<8; i++)\n {\n \t double d_ASDX_RISE, d_ASDX_FALL;\n \t double d_OSDO_RISE, d_OSDO_FALL;\n \t ARRAY_I aI_Data_ASDX, aI_Data_OSDO;\n\n \t aI_Data_ASDX = rdi.id(\"T04_07_ASDX\"+rdi.itos(4*i+0)).getVector(\"ASDX\");\n \t aI_Data_OSDO = rdi.id(\"T04_07_OSDO\"+rdi.itos(4*i+0)).getVector(\"OSDO\");\n \t d_ASDX_RISE = ASDX_port_period/8 * (Find_first_Switch_point_index(aI_Data_ASDX, 0.5)) * 1e-9; //second\n \t d_OSDO_RISE = OSDO_port_period/8 * (Find_first_Switch_point_index(aI_Data_OSDO, 0.5)) * 1e-9; //second\n \t\t FuncPrint(\"T_RISE_ASDX_REF\"+rdi.itos(i), d_ASDX_RISE);\n \t\t FuncPrint(\"T_RISE_OSDO_REF\"+rdi.itos(i), d_OSDO_RISE);\n \t\t T_DLY_RISE_REF[curSite][i] = d_ASDX_RISE - d_OSDO_RISE;\n \t\t FuncPrint(\"T_DLY_RISE_REF_\"+rdi.itos(i), T_DLY_RISE_REF[curSite][i]);\n\n \t aI_Data_ASDX = rdi.id(\"T04_07_ASDX\"+rdi.itos(4*i+1)).getVector(\"ASDX\");\n \t aI_Data_OSDO = rdi.id(\"T04_07_OSDO\"+rdi.itos(4*i+1)).getVector(\"OSDO\");\n \t d_ASDX_FALL = ASDX_port_period/8 * (Find_first_Switch_point_index(aI_Data_ASDX, 0.5)) * 1e-9; //second\n \t d_OSDO_FALL = OSDO_port_period/8 * (Find_first_Switch_point_index(aI_Data_OSDO, 0.5)) * 1e-9; //second\n \t\t FuncPrint(\"T_FALL_ASDX_REF\"+rdi.itos(i), d_ASDX_FALL);\n \t\t FuncPrint(\"T_FALL_OSDO_REF\"+rdi.itos(i), d_OSDO_FALL);\n \t\t T_DLY_FALL_REF[curSite][i] = d_ASDX_FALL - d_OSDO_FALL;\n \t\t FuncPrint(\"T_DLY_FALL_REF_\"+rdi.itos(i), T_DLY_FALL_REF[curSite][i]);\n\n \t aI_Data_ASDX = rdi.id(\"T04_07_ASDX\"+rdi.itos(4*i+2)).getVector(\"ASDX\");\n \t aI_Data_OSDO = rdi.id(\"T04_07_OSDO\"+rdi.itos(4*i+2)).getVector(\"OSDO\");\n \t d_ASDX_RISE = ASDX_port_period/8 * (Find_first_Switch_point_index(aI_Data_ASDX, 0.5)) * 1e-9; //second\n \t d_OSDO_RISE = OSDO_port_period/8 * (Find_first_Switch_point_index(aI_Data_OSDO, 0.5)) * 1e-9; //second\n \t\t FuncPrint(\"T_RISE_ASDX_MEAS\"+rdi.itos(i), d_ASDX_RISE);\n \t\t FuncPrint(\"T_RISE_OSDO_MEAS\"+rdi.itos(i), d_OSDO_RISE);\n \t\t T_DLY_RISE_MEAS[curSite][i] = d_ASDX_RISE - d_OSDO_RISE;\n \t\t FuncPrint(\"T_DLY_RISE_MEAS_\"+rdi.itos(i), T_DLY_RISE_MEAS[curSite][i]);\n\n \t aI_Data_ASDX = rdi.id(\"T04_07_ASDX\"+rdi.itos(4*i+3)).getVector(\"ASDX\");\n \t aI_Data_OSDO = rdi.id(\"T04_07_OSDO\"+rdi.itos(4*i+3)).getVector(\"OSDO\");\n \t d_ASDX_FALL = ASDX_port_period/8 * (Find_first_Switch_point_index(aI_Data_ASDX, 0.5)) * 1e-9; //second\n \t d_OSDO_FALL = OSDO_port_period/8 * (Find_first_Switch_point_index(aI_Data_OSDO, 0.5)) * 1e-9; //second\n \t\t FuncPrint(\"T_FALL_ASDX_MEAS\"+rdi.itos(i), d_ASDX_FALL);\n \t\t FuncPrint(\"T_FALL_OSDO_MEAS\"+rdi.itos(i), d_OSDO_FALL);\n \t\t T_DLY_FALL_MEAS[curSite][i] = d_ASDX_FALL - d_OSDO_FALL;\n \t\t FuncPrint(\"T_DLY_FALL_MEAS_\"+rdi.itos(i), T_DLY_FALL_MEAS[curSite][i]);\n\n \t\t T_DLY_RISE_C[curSite][i] = T_DLY_RISE_MEAS[curSite][i] - T_DLY_RISE_REF[curSite][i];\n \t\t FuncPrint(\"T_DLY_RISE_C_\"+rdi.itos(i), T_DLY_RISE_C[curSite][i]);\n \t\t T_DLY_FALL_C[curSite][i] = T_DLY_FALL_MEAS[curSite][i] - T_DLY_FALL_REF[curSite][i];\n \t\t FuncPrint(\"T_DLY_FALL_C_\"+rdi.itos(i), T_DLY_FALL_C[curSite][i]);\n }\n FOR_EACH_SITE_END();\n\n /* Ori key coments in subpat2 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 13563: {wri('IO_PAD_TRM', 'REG_VALUE')}\n valid comment[ 1] @ avcline 14218: {Test End: T04_07_I2C_Delay_Char}\n */\n TIMING_SPEC spi_std(1, 1);\n Primary.timing(spi_std);\n Primary.timing(1);\n\n static int i_vec_iposition1[32] = {\n 31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,\n 48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63\n };\n for (int i = 0; i < 32; i++)\n {\n i_vec_Num1[i] = i_vec_iposition1[i];\n }\n FOR_EACH_SITE_BEGIN();\n i_WRITE_BACK[curSite] = Switch_High_Low_Bits_16Bits(i_REG_VALUE[curSite]);\n Func_Vector_Dynamic_Write(s_splited_pat_name[2], \"SDX\", i_vec_Num1, 32, i_WRITE_BACK[curSite], 0, 2); //Notes. TEI check per project\n FOR_EACH_SITE_END();\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id2\");\n rdi.func().label(s_splited_pat_name[2]).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes2[curSite] = rdi.id(\"burst_id2\").getBurstPassFail();\n FOR_EACH_SITE_END();\n }\n\n ON_FIRST_INVOCATION_END();\n\n i_funcRes[curSite] = i_funcRes0[curSite] && i_funcRes1[curSite] && i_funcRes2[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n for(int i=0; i<8; i++) {\n \t TestLog(\"T_DLY_RISE_C_\"+rdi.itos(i), T_DLY_RISE_C[curSite][i]);\n \t TestLog(\"T_DLY_FALL_C_\"+rdi.itos(i), T_DLY_FALL_C[curSite][i]);\n }\n\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T04_07_I2C_Delay_Char_V2\", T04_07_I2C_Delay_Char_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 3 $ $Author: luz3sgh $ $Date: 2024/05/06 05:53:19 GMT $')\n# Use signal and timing conventions compliant with I2C fast mode plus acc. test spec (i2c_std)\n# Enable active load into SDX pad during compare cycles\n# The ATE threshold voltage shall be 70% of VDDIO for the detection of logic 1\n# and 30% of VDDIO for logic 0')\n# The I2C device ID is set to 0x68 for pattern generation of this test excetp VD_ACK_RISE measrement.\n# For VD_ACK_RISE, salve ID in pattern is set to 0x69 by TEA.\nubw('SDO') # Release SDO pad\ndly(10e-6)\nrac('CHIP_ID', 0x00af, 0x00ff) # Check chip access\nwac('PWR_CONF', 0x0000) # Keep advanced power save off (default is 0x0)\ndly(10e-6)\nwr('CMD', 0xBB3A) # 1st command for enabling the extended mode\nwr('CMD', 0x2C62) # 2nd command for enabling the extended mode\nwr('CMD', 0xA576) # 1st command for enabling the super privilege mode\nwr('CMD', 0x34D6) # 2nd command for enabling the super privilege mode\ndly(10e-6)\nwac('ACC_CONF', 0xe24c) # Enable ACC in HPM; set AFS=32g; set ODR=1600; set BW=200\ndly(400e-6)\nrac('ERR_REG', 0x0000) # Check error register\nwac('EXT_MODE', 0xc00d) # Enable super privilege mode; switch to ANA register page\nrac('STATUS_PMOD0', 0x0003, 0x0003) # Check ACC AFE PMU status\nwac('EXT_MODE', 0xc007) # Switch to MCU register page\n# -- Hold time start condition HD_STA --\ncmt('Execute following sequence until exit condition is reached')\ncmt('--Sequence Start--')\nwr('MCU_SW_STATUS0', 0x0000) # Clear register\nwr('MCU_SW_STATUS0', 0x006a) # Write signature to register; change signal timing here\nrac('MCU_SW_STATUS0', 0x006a) # Check register with nominal signal timing\n# If previous rd operation pass: In the previous wr operation shift the falling edge of\n# SDX write transition in steps of 5 ns and repeat the entire sequence\n# If previous rd operation fail: Record T_I2C_HD_STA at which the previous rd operation\n# passed for the last time and exit the sequence\ncmt('--Sequence Stop--')\ndly(10e-6)\n# -- Data setup time SU_DAT --\ncmt('Execute following sequence until exit condition is reached')\ncmt('--Sequence Start--')\nwr('MCU_SW_STATUS0', 0x0000) # Clear register\nwr('MCU_SW_STATUS0', 0x006a) # Write signature to register; change signal timing here\nrac('MCU_SW_STATUS0', 0x006a) # Check register with nominal signal timing\n# If previous rd operation pass: In the previous wr operation shorten the pulse duration\n# 5 ns of the register data write phase and repeat the entire sequence\n# If previous rd operation fail: Record T_I2C_SU_DAT at which the previous rd operation\n# passed for the last time and exit the sequence\ncmt('--Sequence Stop--')\ndly(10e-6)\n# -- Data hold time HD_DAT --\ncmt('Execute following sequence until exit condition is reached')\ncmt('--Sequence Start--')\nwr('MCU_SW_STATUS0', 0x0000) # Clear register\nwr('MCU_SW_STATUS0', 0x006a) # Write signature to register; change signal timing here\nrac('MCU_SW_STATUS0', 0x006a) # Check register with nominal signal timing\n# If previous rd operation pass: In the previous wr operation shorten the pulse duration\n# 5 ns of the register data write phase and repeat the entire sequence\n# If previous rd operation fail: Record T_I2C_HD_DAT at which the previous rd operation\n# passed for the last time and exit the sequence\ncmt('--Sequence Stop--')\ndly(10e-6)\n# -- Data valid time VD_DAT --\n# Hardware setup for this measurement: Adjust 30% to 70% rise time of open drain low to\n# high transition to match timing requirements shown in the figure at end of this test\n# description. This timing is valid for the logic 1 output of the DUT and must be\n# independent of temperature\nwr('MCU_SW_STATUS0', 0x006a) # Write signature to register\nrac('MCU_SW_STATUS0', 0x006a) # Read out register; check timing here\n# During the read out in the previous rd operation measure the times T_I2C_VD_DAT_RISE\n# and T_I2C_VD_DAT_FALL when the slave transmits data to the master\ndly(10e-6)\n# -- Data valid acknowledge time for low state VD_ACK_FALL --\nwr('MCU_SW_STATUS0', 0x006a) # Write signature to register; check timing here\n# During the previous write operation measure the time T_I2C_VD_ACK_FALL\ndly(10e-6)\n# -- Data valid acknowledge time for high state VD_ACK_RISE --\ncmt('Use wrong I2C slave address 0x69 in following test')\ndly(10e-6)\nwr('MCU_SW_STATUS0', 0x006a) # Write operation with 0x69 as slave id in pattern\n# During the previous write operation measure the time T_I2C_VD_ACK_RISE\ndly(10e-6) \n# -- Setup time for repeated start condition SU_STA --\nwr('MCU_SW_STATUS0', 0x006a) # Write signature to register\ncmt('Execute following sequence until exit condition is reached')\ncmt('--Sequence Start--')\nrac('MCU_SW_STATUS0', 0x006a) # Read out register; change signal timing here\n# If previous rd operation pass: In the previous rd operation shift the rising edge of\n# SCX signal for the repeated strt conditing 5 ns to the right and repeat the sequence\n# If previous rd operation fail: Record T_I2C_SU_STA at which the previous rd operation\n# passed for the last time and exit the sequence\ncmt('--Sequence Stop--')\ndly(10e-6)\n# -- Bus free time between stop and start condition T_BUF --\nwac('MCU_SW_STATUS0', 0x0015) # Write signature to register\nwac('MCU_SW_STATUS1', 0x002a) # Write signature to register\ncmt('Set variable T_I2C_BUF = 2000 ns')\ncmt('Execute following sequence until exit condition is reached')\ncmt('--Sequence Start--')\n# For following 2 read operations substitute I2C idle timing after the I2C operation,\n# extracted from patttern simulation, by the timing given in the test description here\nrac('MCU_SW_STATUS0', 0x0015) # Read signature from register\ncmt('DLY = T_I2C_BUF')\nrac('MCU_SW_STATUS1', 0x002a) # Read signature from register\ndly(2e-6)\n# If previous rd operation pass: Decrease T_I2C_BUF by 50 ns and repeat the sequence\n# If previous rd operation fail: Record T_I2C_BUF at which the previous rd operation\n# passed for the last time and exit the sequence\ncmt('--Sequence Stop--')\ndly(10e-6)\n# -- High period of SCX clock T_HIGH --\ncmt('Execute following sequence until exit condition is reached')\ncmt('--Sequence Start--')\nwr('MCU_SW_STATUS0', 0x0000) # Clear register\nwr('MCU_SW_STATUS0', 0x006a) # Write signature to register; change signal timing here\nrac('MCU_SW_STATUS0', 0x006a) # Check register with nominal signal timing\n# If previous rd operation pass: In the previous wr operation decr T_I2C_HIGH by 5 ns\n# If previous rd operation fail: Record T_I2C_HIGH at which the previous rd operation\n# passed for the last time and exit the sequence\ncmt('--Sequence Stop--')\ndly(10e-6)\n# -- Low period of SCX clock T_LOW --\ncmt('Execute following sequence until exit condition is reached')\ncmt('--Sequence Start--')\nwr('MCU_SW_STATUS0', 0x0000) # Clear register\nwr('MCU_SW_STATUS0', 0x0023) # Write signature to register; change signal timing here\nrac('MCU_SW_STATUS0', 0x0023) # Check register with nominal signal timing\n# If previous rd operation pass: In the previous wr operation decr T_I2C_LOW by 5 ns\n# If previous rd operation fail: Record T_I2C_LOW at which the previous rd operation\n# passed for the last time and exit the sequence\ncmt('--Sequence Stop--')\ndly(10e-6)\n# -- SDX negative spike suppression time T_SP_SDX_NEG --\ncmt('Set variable T_I2C_SP_SDX_NEG = 0 ns')\ncmt('Execute following sequence until exit condition is reached')\ncmt('--Sequence Start--')\nwr('MCU_SW_STATUS0', 0x00f0) # Write signature to register; change signal timing here\nrac('MCU_SW_STATUS0', 0x00f0) # Read out register\n# If previous rd operation pass: Incr T_I2C_SP_SDX_NEG by 1 ns in previous wr operation\n# and repeat the entire sequence\n# If previous rd operation fail: Record T_I2C_SP_SDX_NEG at which the previous rd\n# operation passed for the last time and exit the sequence\ncmt('--Sequence Stop--')\ndly(10e-6)\n# -- SDX positive spike suppression time T_SP_SDX_POS --\ncmt('Set variable T_I2C_SP_SDX_POS = 0 ns')\ncmt('Execute following sequence until exit condition is reached')\ncmt('--Sequence Start--')\nwr('MCU_SW_STATUS0', 0x00f0) # Write signature to register; change signal timing here\nrac('MCU_SW_STATUS0', 0x00f0) # Read out register\n# If previous rd operation pass: Incr T_I2C_SP_SDX_POS by 1 ns in previous wr operation\n# and repeat the entire sequence\n# If previous rd operation fail: Record T_I2C_SP_SDX_POS at which the previous rd\n# operation passed for the last time and exit the sequence\ncmt('--Sequence Stop--')\ndly(10e-6)\n# -- SCX negative spike suppression time T_SP_SCX_NEG --\ncmt('Set variable T_I2C_SP_SCX_NEG = 0 ns')\ncmt('Execute following sequence until exit condition is reached')\ncmt('--Sequence Start--')\nwr('MCU_SW_STATUS0', 0x00f0) # Write signature to register; change signal timing here\nrac('MCU_SW_STATUS0', 0x00f0) # Read out register\n# If previous rd operation pass: Incr T_I2C_SP_SCX_NEG by 1 ns in previous wr operation\n# and repeat the entire sequence\n# If previous rd operation fail: Record T_I2C_SP_SCX_NEG at which the previous rd\n# operation passed for the last time and exit the sequence\ncmt('--Sequence Stop--')\ndly(10e-6)\n# -- SCX positive spike suppression time T_SP_SCX_POS --\ncmt('Set variable T_I2C_SP_SCX_POS = 0 ns')\ncmt('Execute following sequence until exit condition is reached')\ncmt('--Sequence Start--')\nwr('MCU_SW_STATUS0', 0x00f0) # Write signature to register; change signal timing here\nrac('MCU_SW_STATUS0', 0x00f0) # Read out register\n# If previous rd operation pass: Incr T_I2C_SP_SCX_POS by 1 ns in previous wr operation\n# and repeat the entire sequence\n# If previous rd operation fail: Record T_I2C_SP_SCX_POS at which the previous rd\n# operation passed for the last time and exit the sequence\ncmt('--Sequence Stop--')\ndly(10e-6)\n# -- Setup time for stop condition SU_STO --\ncmt('Execute following sequence until exit condition is reached')\ncmt('--Sequence Start--')\nwr('MCU_SW_STATUS0', 0x0000) # Clear register\nwr('MCU_SW_STATUS0', 0x006a) # Write signature to register; change signal timing here\nrac('MCU_SW_STATUS0', 0x006a) # Check register with nominal signal timing\n# If previous rd operation pass: In the previous wr operation decrease T_I2C_SU_STO by\n# 5 ns and repeat the entire sequence\n# If previous rd operation fail: Record T_I2C_SU_STO at which the previous rd operation\n# passed for the last time and exit the sequence\ncmt('--Sequence Stop--')\ndly(10e-6)\n#Clean-up\nwac('MCU_SW_STATUS0', 0x0000) # Reset register setting\nwac('MCU_SW_STATUS1', 0x0000) # Reset register setting\n", "output": "#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\n/**\n * Test method class.\n *\n * For each testsuite using this test method, one object of this\n * class is created.\n */\nclass T04_08_I2C_characterization_V1: public testmethod::TestMethod {\n\nprotected:\n\t int i_funcRes[xNSitES];\n\t double d_I2C_T_HD_STA[xNSitES];\n\t double d_I2C_T_SU_DAT[xNSitES];\n\t double d_I2C_T_HD_DAT[xNSitES];\n\t double d_I2C_T_SU_STA[xNSitES];\n\t double d_I2C_T_SU_STO[xNSitES];\n\t double d_I2C_T_BUF[xNSitES];\n\t double d_I2C_T_LOW[xNSitES];\n\t double d_I2C_T_HIGH[xNSitES];\n\t double d_I2C_T_SP_SDX_NEG[xNSitES];\n\t double d_I2C_T_SP_SDX_POS[xNSitES];\n\t double d_I2C_T_SP_SCX_NEG[xNSitES];\n\t double d_I2C_T_SP_SCX_POS[xNSitES];\n\t double d_I2C_T_VD_DAT_RISE[xNSitES];\n\t double d_I2C_T_VD_DAT_FALL[xNSitES];\n\t double d_I2C_T_VD_ACK_RISE[xNSitES];\n\t double d_I2C_T_VD_ACK_FALL[xNSitES];\n\n /**\n *Initialize the parameter interface to the testflow.\n *This method is called just once after a testsuite is created.\n */\n virtual void initialize()\n {\n //Add your initialization code here\n //Note: Test Method API should not be used in this method!\n }\n\n /**\n *This test is invoked per site.\n */\n virtual void run()\n {\n //Add your test code here.\n\t const string s_Label_Init = \"T04_08_I2C_characterization_V3_AVC3_PY3_Init\";\n\t const string s_Label_Seq1 = \"T04_08_i2c_timing_V1_seq1\";\n\t const string s_Label_Seq2 = \"T04_08_i2c_timing_V1_seq2\";\n\t const string s_Label_Seq3 = \"T04_08_i2c_timing_V1_seq3\";\n\t const string s_Label_Seq4 = \"T04_08_i2c_timing_V1_seq4\";\n\t const string s_Label_Seq5 = \"T04_08_i2c_timing_V1_seq5\";\n\t const string s_Label_Seq6 = \"T04_08_i2c_timing_V1_seq6\";\n\t const string s_Label_Cleanup = \"T04_08_i2c_timing_V1_cleanup\";\n\t const string s_Label_Wac1 = \"T04_08_i2c_timing_V1_wac1\";\n\t const string s_Label_Wac2 = \"T04_08_i2c_timing_V1_wac2\";\n\n\n\t SEARCH_FUNC_TASK TASK_spec1, TASK_spec2, TASK_spec3, TASK_spec4, TASK_spec5, TASK_spec6, TASK_spec7, TASK_spec8,\n\t \t \t \t \t TASK_spec9, TASK_spec10, TASK_spec11, TASK_spec12, TASK_spec13, TASK_spec14, TASK_spec15, TASK_spec16, TASK_spec17;\n\n\t int i_PassFail;\n\t TIMING_SPEC spec_i2c_sp_scl(41,1);\n\t TIMING_SPEC spec_i2c_char(40,1);\n\t TIMING_SPEC spec_i2c_timing(3,1); //TODO check if match with current timing\n\n\t ON_FIRST_INVOCATION_BEGIN();\n\n\n\t\t int i_funcRes1[xNSitES], i_funcRes2[xNSitES], i_funcRes3[xNSitES], i_funcRes4[xNSitES], i_funcRes5[xNSitES]\n\t\t , i_funcRes6[xNSitES], i_funcRes7[xNSitES], i_funcRes8[xNSitES], i_funcRes9[xNSitES], i_funcRes10[xNSitES]\n\t\t , i_funcRes11[xNSitES], i_funcRes12[xNSitES], i_funcRes13[xNSitES], i_funcRes14[xNSitES], i_funcRes15[xNSitES]\n\t\t , i_funcRes16[xNSitES], i_funcRes17[xNSitES], i_funcRes18[xNSitES], i_funcRes7_1[xNSitES], i_funcRes8_1[xNSitES];\n\n\t\t double d_TransitionTime1[xNSitES], d_TransitionTime2[xNSitES], d_TransitionTime3[xNSitES], d_TransitionTime4[xNSitES], d_TransitionTime5[xNSitES]\n\t\t , d_TransitionTime6[xNSitES], d_TransitionTime7[xNSitES], d_TransitionTime8[xNSitES], d_TransitionTime9[xNSitES], d_TransitionTime10[xNSitES]\n\t\t , d_TransitionTime11[xNSitES], d_TransitionTime12[xNSitES], d_TransitionTime13[xNSitES], d_TransitionTime14[xNSitES], d_TransitionTime15[xNSitES]\n\t\t , d_TransitionTime16[xNSitES];\n//\t\t , d_TransitionTime17[xNSitES], d_TransitionTime18[xNSitES];\n\n\n\t\t Primary.timing(spec_i2c_timing);\n\t\t FLUSH();\n\n\t\t //initial, goto page0\t//TODO to get Init pattern of py.\n\t\t Primary.label(s_Label_Init);\n\t\t FUNCTIONAL_TEST();\n \t FOR_EACH_SITE_BEGIN();\n \t \t i_funcRes1[curSite] = GET_FUNCTIONAL_RESULT();\n \t Func_Print(i_funcRes1[curSite], \"i_funcRes1\");\n \t FOR_EACH_SITE_END();\n\n\t\t Primary.timing(spec_i2c_char);\n\n\t\t //***********************************I2C_T_HD_STA*************************************************************\n\t\t Primary.label(s_Label_Seq1);\n\t\t FUNCTIONAL_TEST();\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t \t i_funcRes2[curSite] = GET_FUNCTIONAL_RESULT();\n\t\t\t Func_Print(i_funcRes2[curSite], \"i_funcRes2\");\n\t\t FOR_EACH_SITE_END();\n\n\t\t Primary.label(s_Label_Seq1+\"_hd_sta\");\n\t\t FLUSH();\n\t\t TASK_spec1.pin(\"SDX\").spec(\"t_hd_sta\",TM::TIM).method(TM::Binary).start(10).stop(750).resolution(1);\n\t\t TASK_spec1.execute();\n\n\t\t FOR_EACH_SITE_BEGIN();\n\t \t i_PassFail = TASK_spec1.getPassFail(\"SDX\");\n\t\t\t //if find the transition point, get value\n\t\t\t if(i_PassFail)\n\t\t\t {\n\t\t\t\t d_TransitionTime1[curSite] = TASK_spec1.getPassValue(\"SDX\");\n\t\t\t\t d_I2C_T_HD_STA[curSite] = (750 - d_TransitionTime1[curSite]) ; //unit s\n\n\t\t \t\t Func_Print(d_TransitionTime1[curSite], \"Org TransitionTime1\");\n\t\t \t\t Func_Print(d_I2C_T_HD_STA[curSite], \"d_I2C_T_HD_STA\");\n\t\t\t }\n\t\t FOR_EACH_SITE_END();\n\n\n\t\t //***********************************I2C_T_SU_DAT*************************************************************\n\t\t Primary.label(s_Label_Seq1);\n\t\t FUNCTIONAL_TEST();\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t \t i_funcRes3[curSite] = GET_FUNCTIONAL_RESULT();\n\t\t \t Func_Print(i_funcRes3[curSite], \"i_funcRes3\");\n\t\t FOR_EACH_SITE_END();\n\n\t\t Primary.label(s_Label_Seq1+\"_su_dat\");\n\t\t FLUSH();\n\t\t TASK_spec2.pin(\"SDX\").spec(\"t_su_dat\",TM::TIM).method(TM::Binary).start(10).stop(450).resolution(1);\n\t\t TASK_spec2.execute();\n\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t\t i_PassFail = TASK_spec2.getPassFail(\"SDX\");\n\t\t\t //if find the transition point, get value\n\t\t\t if(i_PassFail)\n\t\t\t {\n\t\t\t\t d_TransitionTime2[curSite] = TASK_spec2.getPassValue(\"SDX\");\n\t\t\t\t d_I2C_T_SU_DAT[curSite] = (250 - d_TransitionTime2[curSite]) ; //unit s\n\n\t\t \t\t Func_Print(d_TransitionTime2[curSite], \"Org TransitionTime2\");\n\t\t \t\t Func_Print(d_I2C_T_SU_DAT[curSite], \"d_I2C_T_SU_DAT\");\n\t\t\t }\n\t\t FOR_EACH_SITE_END();\n\n\n\n\t\t //***********************************I2C_T_HD_DAT*************************************************************\n\t\t Primary.label(s_Label_Seq1);\n\t\t FUNCTIONAL_TEST();\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t \t i_funcRes4[curSite] = GET_FUNCTIONAL_RESULT();\n\t\t \t Func_Print(i_funcRes4[curSite], \"i_funcRes4\");\n\t\t FOR_EACH_SITE_END();\n\n\t\t Primary.label(s_Label_Seq1+\"_hd_dat\");\n\t\t FLUSH();\n\t\t TASK_spec3.pin(\"SDX\").spec(\"t_hd_dat\",TM::TIM).method(TM::Binary).start(0).stop(500).resolution(1);\n\t\t TASK_spec3.execute();\n\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t\t i_PassFail = TASK_spec3.getPassFail(\"SDX\");\n\t\t\t //if find the transition point, get value\n\t\t\t if(i_PassFail)\n\t\t\t {\n\t\t\t\t d_TransitionTime3[curSite] = TASK_spec3.getPassValue(\"SDX\");\n\t\t\t\t d_I2C_T_HD_DAT[curSite] = (250 - d_TransitionTime3[curSite]) ; //unit s\n\n\t\t \t\t Func_Print(d_TransitionTime3[curSite], \"Org TransitionTime3\");\n\t\t \t\t Func_Print(d_I2C_T_HD_DAT[curSite], \"d_I2C_T_HD_DAT\");\n\t\t\t }\n\t\t FOR_EACH_SITE_END();\n\n\n\t\t //***********************************I2C_T_VD_DAT_RISE*************************************************************\n\t\t Primary.label(s_Label_Seq1);\n\t\t FUNCTIONAL_TEST();\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t \t i_funcRes5[curSite] = GET_FUNCTIONAL_RESULT();\n\t\t \t Func_Print(i_funcRes5[curSite], \"i_funcRes5\");\n\t\t FOR_EACH_SITE_END();\n\n\t\t Primary.label(s_Label_Seq1+\"_vd_dat_rise\");\n\t\t FLUSH();\n\t\t TASK_spec4.pin(\"SDX\").spec(\"t_vd_dat\",TM::TIM).method(TM::Binary).start(0).stop(-800).resolution(1);\n\t\t TASK_spec4.execute();\n\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t\t i_PassFail = TASK_spec4.getPassFail(\"SDX\");\n\t\t\t //if find the transition point, get value\n\t\t\t if(i_PassFail)\n\t\t\t {\n\t\t\t\t d_TransitionTime4[curSite] = TASK_spec4.getPassValue(\"SDX\");\n\t\t\t\t d_I2C_T_VD_DAT_RISE[curSite] = (250 + 500 + d_TransitionTime4[curSite]) ; //unit s\n\n\t\t \t\t Func_Print(d_TransitionTime4[curSite], \"Org TransitionTime4\");\n\t\t \t\t Func_Print(d_I2C_T_VD_DAT_RISE[curSite], \"d_I2C_T_VD_DAT_RISE\");\n\t\t\t }\n\t\t FOR_EACH_SITE_END();\n\n\n\t\t //***********************************I2C_T_VD_DAT_FALL*************************************************************\n\t\t Primary.label(s_Label_Seq1);\n\t\t FUNCTIONAL_TEST();\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t \t i_funcRes6[curSite] = GET_FUNCTIONAL_RESULT();\n\t\t \t Func_Print(i_funcRes6[curSite], \"i_funcRes6\");\n\t\t FOR_EACH_SITE_END();\n\n\t\t Primary.label(s_Label_Seq1+\"_vd_dat_fall\");\n\t\t FLUSH();\n\t\t TASK_spec5.pin(\"SDX\").spec(\"t_vd_dat\",TM::TIM).method(TM::Binary).start(0).stop(-800).resolution(1);\n\t\t TASK_spec5.execute();\n\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t\t i_PassFail = TASK_spec5.getPassFail(\"SDX\");\n\t\t\t //if find the transition point, get value\n\t\t\t if(i_PassFail)\n\t\t\t {\n\t\t\t\t d_TransitionTime5[curSite] = TASK_spec5.getPassValue(\"SDX\");\n\t\t\t\t d_I2C_T_VD_DAT_FALL[curSite] = (250 + 500 + d_TransitionTime5[curSite]) ; //unit s\n\n\t\t \t\t Func_Print(d_TransitionTime5[curSite], \"Org TransitionTime5\");\n\t\t \t\t Func_Print(d_I2C_T_VD_DAT_FALL[curSite], \"d_I2C_T_VD_DAT_FALL\");\n\t\t\t }\n\t\t FOR_EACH_SITE_END();\n\n\n\t\t //***********************************I2C_T_VD_ACK_RISE*************************************************************\n\t\t Primary.label(s_Label_Seq6);\n\t\t FUNCTIONAL_TEST();\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t \t i_funcRes18[curSite] = GET_FUNCTIONAL_RESULT();\n\t\t \t Func_Print(i_funcRes18[curSite], \"i_funcRes18\");\n\t\t FOR_EACH_SITE_END();\n\n\t\t Primary.label(s_Label_Seq6+\"_vd_ack_rise\");\n\t\t FLUSH();\n\t\t TASK_spec17.pin(\"SDX\").spec(\"t_vd_dat\",TM::TIM).method(TM::Binary).start(0).stop(-800).resolution(1);\n\t\t TASK_spec17.execute();\n\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t\t i_PassFail = TASK_spec17.getPassFail(\"SDX\");\n\t\t\t //if find the transition point, get value\n\t\t\t if(i_PassFail)\n\t\t\t {\n\t\t\t\t d_TransitionTime16[curSite] = TASK_spec17.getPassValue(\"SDX\");\n\t\t\t\t d_I2C_T_VD_ACK_RISE[curSite] = (250 + 500 + d_TransitionTime16[curSite]) ; //unit s\n\n\t\t \t\t Func_Print(d_TransitionTime16[curSite], \"Org TransitionTime16\");\n\t\t \t\t Func_Print(d_I2C_T_VD_ACK_RISE[curSite], \"d_I2C_T_VD_ACK_RISE\");\n\t\t\t }\n\t\t FOR_EACH_SITE_END();\n\n\t\t //***********************************I2C_T_VD_ACK_FALL*************************************************************\n\t\t Primary.label(s_Label_Seq6);\n\t\t FUNCTIONAL_TEST();\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t \t i_funcRes17[curSite] = GET_FUNCTIONAL_RESULT();\n\t\t \t Func_Print(i_funcRes17[curSite], \"i_funcRes17\");\n\t\t FOR_EACH_SITE_END();\n\n\t\t Primary.label(s_Label_Seq6+\"_vd_ack_fall\");\n\t\t FLUSH();\n\t\t TASK_spec16.pin(\"SDX\").spec(\"t_vd_dat\",TM::TIM).method(TM::Binary).start(0).stop(-800).resolution(1);\n\t\t TASK_spec16.execute();\n\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t\t i_PassFail = TASK_spec16.getPassFail(\"SDX\");\n\t\t\t //if find the transition point, get value\n\t\t\t if(i_PassFail)\n\t\t\t {\n\t\t\t\t d_TransitionTime15[curSite] = TASK_spec16.getPassValue(\"SDX\");\n\t\t\t\t d_I2C_T_VD_ACK_FALL[curSite] = (250 + 500 + d_TransitionTime15[curSite]) ; //unit s\n\n\t\t \t\t Func_Print(d_TransitionTime15[curSite], \"Org TransitionTime15\");\n\t\t \t\t Func_Print(d_I2C_T_VD_ACK_FALL[curSite], \"d_I2C_T_VD_ACK_FALL\");\n\t\t\t }\n\t\t FOR_EACH_SITE_END();\n\n\n\t\t //***********************************I2C_T_SU_STA*************************************************************\n\t\t Primary.label(s_Label_Wac1);\n\t\t FUNCTIONAL_TEST();\n\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t \t i_funcRes7_1[curSite] = GET_FUNCTIONAL_RESULT();\n\t\t \t Func_Print(i_funcRes7_1[curSite], \"i_funcRes7_1\");\n\t\t FOR_EACH_SITE_END();\n\n\n\t\t Primary.getTimingSpec().change(\"t_su_sta\", 250);\n\t\t FLUSH();\n\n//\t\t Primary.label(\"T04_08_i2c_timing_V1_seq2_t_su_sta\");\n\t\t Primary.label(s_Label_Seq2+\"_su_sta\");\n\t\t FUNCTIONAL_TEST();\n\n\n\n\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t \t i_funcRes7[curSite] = GET_FUNCTIONAL_RESULT();\n\t\t \t Func_Print(i_funcRes7[curSite], \"i_funcRes7\");\n\t\t FOR_EACH_SITE_END();\n\n\t\t Primary.label(s_Label_Seq2+\"_su_sta\");\n//\t\t Primary.label(\"T04_08_i2c_timing_V1_seq2_t_su_sta\");\n\t\t FLUSH();\n\t\t TASK_spec6.pin(\"SCX\").spec(\"t_su_sta\",TM::TIM).method(TM::Binary).start(250).stop(740).resolution(0.1);\n\t\t TASK_spec6.execute();\n\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t\t i_PassFail = TASK_spec6.getPassFail(\"SCX\");\n\t\t\t //if find the transition point, get value\n\t\t\t if(i_PassFail)\n\t\t\t {\n\t\t\t\t d_TransitionTime6[curSite] = TASK_spec6.getPassValue(\"SCX\");\n\t\t\t\t d_I2C_T_SU_STA[curSite] = (500- d_TransitionTime6[curSite]) ; //unit s\n\n\t\t \t\t Func_Print(d_TransitionTime6[curSite], \"Org TransitionTime6\");\n\t\t \t\t Func_Print(d_I2C_T_SU_STA[curSite], \"d_I2C_T_SU_STA\");\n\n\t\t\t }\n\t\t FOR_EACH_SITE_END();\n\n\n\t\t //***********************************I2C_T_BUF*************************************************************\n\t\t Primary.label(s_Label_Wac2);\n\t\t FUNCTIONAL_TEST();\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t \t i_funcRes8_1[curSite] = GET_FUNCTIONAL_RESULT();\n\t\t \t Func_Print(i_funcRes8_1[curSite], \"i_funcRes8_1\");\n\t\t FOR_EACH_SITE_END();\n\n\t\t Primary.getTimingSpec().change(\"t_su_dat\", 500);\n\t\t FLUSH();\n\n\t\t Primary.label(s_Label_Seq3+\"_buf\");\n//\t\t Primary.label(s_Label_Seq3);\n\t\t FUNCTIONAL_TEST();\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t \t i_funcRes8[curSite] = GET_FUNCTIONAL_RESULT();\n\t\t \t Func_Print(i_funcRes8[curSite], \"i_funcRes8\");\n\t\t FOR_EACH_SITE_END();\n\n//\t\t Primary.label(\"T04_08_i2c_timing_V1_seq3_buf_test\");\n\n\t\t Primary.label(s_Label_Seq3+\"_buf\");\n\t\t FLUSH();\n\t\t TASK_spec7.pin(\"SDX\").spec(\"t_su_dat\",TM::TIM).method(TM::Linear).start(500).stop(1000).stepWidth(10);\n\t\t TASK_spec7.execute();\n\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t\t i_PassFail = TASK_spec7.getPassFail(\"SDX\");\n\t\t\t //if find the transition point, get value\n\t\t\t if(i_PassFail)\n\t\t\t {\n\t\t\t\t d_TransitionTime7[curSite] = TASK_spec7.getPassValue(\"SDX\");\n\t\t\t\t d_I2C_T_BUF[curSite] = (1000 - d_TransitionTime7[curSite]) * 2 ;\n\n\t\t \t\t Func_Print(d_TransitionTime7[curSite], \"Org TransitionTime7\");\n\t\t \t\t Func_Print(d_I2C_T_BUF[curSite], \"d_I2C_T_BUF\");\n\t\t\t }\n\t\t FOR_EACH_SITE_END();\n\n\n\t\t //***********************************I2C_T_HIGH*************************************************************\n\t\t Primary.label(s_Label_Seq1);\n\t\t FUNCTIONAL_TEST();\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t\t i_funcRes9[curSite] = GET_FUNCTIONAL_RESULT();\n\t\t\t Func_Print(i_funcRes9[curSite], \"i_funcRes9\");\n\t\t FOR_EACH_SITE_END();\n\n\t\t Primary.label(s_Label_Seq1+\"_high\");\n\t\t FLUSH();\n\t\t TASK_spec8.pin(\"SCX\").spec(\"t_high\",TM::TIM).method(TM::Binary).start(0).stop(-500).resolution(1);\n\t\t TASK_spec8.execute();\n\n\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t \t i_PassFail = TASK_spec8.getPassFail(\"SCX\");\n\t\t\t //if find the transition point, get value\n\t\t\t if(i_PassFail)\n\t\t\t {\n\t\t\t\t d_TransitionTime8[curSite] = TASK_spec8.getPassValue(\"SCX\");\n\t\t\t\t d_I2C_T_HIGH[curSite] = (500 + d_TransitionTime8[curSite]) ; //unit s\n\n\t\t\t\t Func_Print(d_TransitionTime8[curSite], \"Org TransitionTime8\");\n\t\t \t\t Func_Print(d_I2C_T_HIGH[curSite], \"d_I2C_T_HIGH\");\n\t\t\t }\n\t\t FOR_EACH_SITE_END();\n\n\n\t\t //***********************************I2C_T_LOW*************************************************************\n\t\t Primary.label(s_Label_Seq4);\n\t\t FUNCTIONAL_TEST();\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t\t i_funcRes10[curSite] = GET_FUNCTIONAL_RESULT();\n\t\t \t Func_Print(i_funcRes10[curSite], \"i_funcRes10\");\n\t\t FOR_EACH_SITE_END();\n\n\t\t Primary.label(s_Label_Seq4+\"_low\");\n\t\t FLUSH();\n//\t\t TASK_spec9.pin(\"SCX\").spec(\"t_low\",TM::TIM).method(TM::Binary).start(0).stop(500).resolution(5);\n\t\t TASK_spec9.pin(\"SCX\").spec(\"t_high\",TM::TIM).method(TM::Binary).start(0).stop(500).resolution(1);\n\t\t TASK_spec9.execute();\n\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t\t i_PassFail = TASK_spec9.getPassFail(\"SCX\");\n\t\t\t //if find the transition point, get value\n\t\t\t if(i_PassFail)\n\t\t\t {\n\t\t\t d_TransitionTime9[curSite] = TASK_spec9.getPassValue(\"SCX\");\n\t\t\t d_I2C_T_LOW[curSite] = (500 - d_TransitionTime9[curSite]) ; //unit s\n\n\t\t\t\t Func_Print(d_TransitionTime9[curSite], \"Org TransitionTime9\");\n\t\t \t\t Func_Print(d_I2C_T_LOW[curSite], \"d_I2C_T_LOW\");\n\t\t\t }\n\t\t FOR_EACH_SITE_END();\n\n\n\t\t //***********************************I2C_T_SP_SDX_NEG*************************************************************\n\t\t Primary.label(s_Label_Seq5);\n\t\t FUNCTIONAL_TEST();\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t\t i_funcRes11[curSite] = GET_FUNCTIONAL_RESULT();\n\t\t\t Func_Print(i_funcRes11[curSite], \"i_funcRes11\");\n\t\t FOR_EACH_SITE_END();\n\n\t\t Primary.label(s_Label_Seq5+\"_sp_sda_neg\");\n\t\t FLUSH();\n\t\t TASK_spec10.pin(\"SDX\").spec(\"t_sp\",TM::TIM).method(TM::Binary).start(0).stop(1000).resolution(1); //modify the time to 200ns based on shmoo data on 0526\n\t\t TASK_spec10.execute();\n\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t\t i_PassFail = TASK_spec10.getPassFail(\"SDX\");\n\t\t\t //if find the transition point, get value\n\t\t\t if(i_PassFail)\n\t\t\t {\n\t\t\t\t d_TransitionTime10[curSite] = TASK_spec10.getPassValue(\"SDX\");\n\t\t\t\t d_I2C_T_SP_SDX_NEG[curSite] = (d_TransitionTime10[curSite] + 5); //unit s\n\n\t\t\t\t Func_Print(d_TransitionTime10[curSite], \"Org TransitionTime10\");\n\t\t \t\t Func_Print(d_I2C_T_SP_SDX_NEG[curSite], \"d_I2C_T_SP_SDX_NEG\");\n\t\t\t }\n\t\t FOR_EACH_SITE_END();\n\n\n\t\t //***********************************I2C_T_SP_SDX_POS*************************************************************\n\t\t Primary.label(s_Label_Seq5);\n\t\t FUNCTIONAL_TEST();\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t \t i_funcRes12[curSite] = GET_FUNCTIONAL_RESULT();\n\t\t \t Func_Print(i_funcRes12[curSite], \"i_funcRes12\");\n\t\t FOR_EACH_SITE_END();\n\n\t\t Primary.label(s_Label_Seq5+\"_sp_sda_pos\");\n\t\t FLUSH();\n\t\t TASK_spec11.pin(\"SDX\").spec(\"t_sp\",TM::TIM).method(TM::Binary).start(0).stop(1000).resolution(1); //modify the time to 200ns based on shmoo data on 0526\n\t\t TASK_spec11.execute();\n\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t\t i_PassFail = TASK_spec11.getPassFail(\"SDX\");\n\t\t\t //if find the transition point, get value\n\t\t\t if(i_PassFail)\n\t\t\t {\n\t\t\t\t d_TransitionTime11[curSite] = TASK_spec11.getPassValue(\"SDX\");\n\t\t\t\t d_I2C_T_SP_SDX_POS[curSite] = (d_TransitionTime11[curSite]+5) ; //unit s\n\n\t\t\t\t Func_Print(d_TransitionTime11[curSite], \"Org TransitionTime11\");\n\t\t \t\t Func_Print(d_I2C_T_SP_SDX_POS[curSite], \"d_I2C_T_SP_SDX_POS\");\n\t\t\t }\n\t\t FOR_EACH_SITE_END();\n\n\n\t\t //***********************************I2C_T_SP_SCX_NEG*************************************************************\n\t\t Primary.timing(spec_i2c_sp_scl);\n\t\t FLUSH();\n\n\t\t Primary.label(s_Label_Seq5);\n\t\t FUNCTIONAL_TEST();\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t\t i_funcRes13[curSite] = GET_FUNCTIONAL_RESULT();\n\t\t\t Func_Print(i_funcRes13[curSite], \"i_funcRes13\");\n\t\t FOR_EACH_SITE_END();\n\n\t\t Primary.label(s_Label_Seq5+\"_sp_scl_neg\");\n\t\t FLUSH();\n\t\t TASK_spec12.pin(\"SCX\").spec(\"t_sp_scl_neg\",TM::TIM).method(TM::Linear).start(10).stop(490).stepWidth(1);//resolution(5); //modify Linear, and the time to 150ns based on shmoo data on 0526\n\t\t TASK_spec12.execute();\n\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t\t i_PassFail = TASK_spec12.getPassFail(\"SCX\");\n\t\t\t //if find the transition point, get value\n\t\t\t if(i_PassFail)\n\t\t\t {\n\t\t\t\t d_TransitionTime12[curSite] = TASK_spec12.getPassValue(\"SCX\");\n\t\t\t\t d_I2C_T_SP_SCX_NEG[curSite] = (d_TransitionTime12[curSite]); //unit s\n\n\t\t\t\t Func_Print(d_TransitionTime12[curSite], \"Org TransitionTime12\");\n\t\t \t\t Func_Print(d_I2C_T_SP_SCX_NEG[curSite], \"d_I2C_T_SP_SCX_NEG\");\n\t\t\t }\n\t\t FOR_EACH_SITE_END();\n\n\n\t\t //***********************************I2C_T_SP_SCX_POS*************************************************************\n//\t\t TIMING_SPEC spec_i2c_sp_scl(33,1);\n//\t\t Primary.timing(spec_i2c_sp_scl);\n\t\t FLUSH();\n\n\t\t Primary.label(s_Label_Seq5);\n\t\t FUNCTIONAL_TEST();\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t\t i_funcRes14[curSite] = GET_FUNCTIONAL_RESULT();\n\t\t\t Func_Print(i_funcRes14[curSite], \"i_funcRes14\");\n\t\t FOR_EACH_SITE_END();\n\n\t\t Primary.label(s_Label_Seq5+\"_sp_scl_pos\");\n\t\t FLUSH();\n\t\t TASK_spec13.pin(\"SCX\").spec(\"t_sp_scl_pos\",TM::TIM).method(TM::Linear).start(0).stop(500).stepWidth(1);//resolution(5); //modify Linear, and the time to 200ns based on shmoo data on 0526\n\t\t TASK_spec13.execute();\n\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t\t i_PassFail = TASK_spec13.getPassFail(\"SCX\");\n\t\t\t //if find the transition point, get value\n\t\t\t if(i_PassFail)\n\t\t\t {\n\t\t\t\t d_TransitionTime13[curSite] = TASK_spec13.getPassValue(\"SCX\");\n\t\t\t\t d_I2C_T_SP_SCX_POS[curSite] = (d_TransitionTime13[curSite] ); //unit s\n\n\t\t\t\t Func_Print(d_TransitionTime13[curSite], \"Org TransitionTime13\");\n\t\t \t\t Func_Print(d_I2C_T_SP_SCX_POS[curSite], \"d_I2C_T_SP_SCX_POS\");\n\t\t\t }\n\t\t FOR_EACH_SITE_END();\n\n\t\t //***********************************I2C_T_SU_STO*************************************************************\n\t\t Primary.timing(spec_i2c_char);\n\t\t FLUSH();\n\n\t\t Primary.label(s_Label_Seq1);\n\t\t FUNCTIONAL_TEST();\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t \t i_funcRes15[curSite] = GET_FUNCTIONAL_RESULT();\n\t\t \t Func_Print(i_funcRes15[curSite], \"i_funcRes15\");\n\t\t FOR_EACH_SITE_END();\n\n\t\t Primary.label(s_Label_Seq1+\"_su_sto\");\n\t\t FLUSH();\n\t\t TASK_spec14.pin(\"SDX\").spec(\"t_su_dat\",TM::TIM).method(TM::Linear).start(600).stop(0).stepWidth(1);\n\t\t TASK_spec14.execute();\n\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t\t i_PassFail = TASK_spec14.getPassFail(\"SDX\");\n\t\t\t //if find the transition point, get value\n\t\t\t if(i_PassFail)\n\t\t\t {\n\t\t\t\t d_TransitionTime14[curSite] = TASK_spec14.getPassValue(\"SDX\");\n\t\t\t\t d_I2C_T_SU_STO[curSite] = (d_TransitionTime14[curSite]-250); //unit s\n\n\t\t\t\t Func_Print(d_TransitionTime14[curSite], \"Org TransitionTime14\");\n\t\t \t\t Func_Print(d_I2C_T_SU_STO[curSite], \"d_I2C_T_SU_STO\");\n\t\t\t }\n\t\t FOR_EACH_SITE_END();\n\n\n\t\t //clean up\t//TODO clean up pattern need to be get from py.\n\n\t\t Primary.label(s_Label_Cleanup);\n//\t\t Primary.label(\"T04_08_I2C_characterization_cleanup\");\n\t\t FUNCTIONAL_TEST();\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t\t i_funcRes16[curSite] = GET_FUNCTIONAL_RESULT();\n\t\t\t Func_Print(i_funcRes16[curSite], \"i_funcRes16\");\n\n\t\t\t i_funcRes[curSite] = i_funcRes1[curSite] & i_funcRes2[curSite] & i_funcRes3[curSite] & i_funcRes4[curSite]\n\t\t\t\t\t\t\t\t & i_funcRes5[curSite] & i_funcRes6[curSite] & i_funcRes7[curSite] & i_funcRes8[curSite]\n\t\t\t\t\t\t\t\t & i_funcRes9[curSite] & i_funcRes10[curSite]& i_funcRes11[curSite]& i_funcRes12[curSite]\n\t\t\t\t\t\t\t\t & i_funcRes13[curSite]& i_funcRes14[curSite]& i_funcRes15[curSite]& i_funcRes16[curSite]\n\t\t\t\t\t\t\t\t & i_funcRes17[curSite]& i_funcRes18[curSite];\n\t\t\t Func_Print(i_funcRes[curSite], \"i_funcRes\");\n\n\t\t FOR_EACH_SITE_END();\n\n ON_FIRST_INVOCATION_END();\n\n\n //test and judge\n\t TestLog(\"T_I2C_HD_STA\", d_I2C_T_HD_STA[curSite] * 1e-9);\n\t TestLog(\"T_I2C_SU_DAT\", d_I2C_T_SU_DAT[curSite] * 1e-9);\n\t TestLog(\"T_I2C_HD_DAT\", d_I2C_T_HD_DAT[curSite] * 1e-9);\n\t TestLog(\"T_I2C_VD_DAT_RISE\", d_I2C_T_VD_DAT_RISE[curSite] * 1e-9);\n\t TestLog(\"T_I2C_VD_DAT_FALL\", d_I2C_T_VD_DAT_FALL[curSite] * 1e-9);\n\t TestLog(\"T_I2C_SU_STA\", d_I2C_T_SU_STA[curSite] * 1e-9);\n\t TestLog(\"T_I2C_BUF\", d_I2C_T_BUF[curSite] * 1e-9);\n\t TestLog(\"T_I2C_HIGH\", d_I2C_T_HIGH[curSite] * 1e-9);\n\t TestLog(\"T_I2C_LOW\", d_I2C_T_LOW[curSite] * 1e-9);\n\t TestLog(\"T_I2C_SP_SDX_NEG\", d_I2C_T_SP_SDX_NEG[curSite] * 1e-9);\n\t TestLog(\"T_I2C_SP_SDX_POS\", d_I2C_T_SP_SDX_POS[curSite] * 1e-9);\n\t TestLog(\"T_I2C_SP_SCX_NEG\", d_I2C_T_SP_SCX_NEG[curSite] * 1e-9);\n\t TestLog(\"T_I2C_SP_SCX_POS\", d_I2C_T_SP_SCX_POS[curSite] * 1e-9);\n\t TestLog(\"T_I2C_SU_STO\", d_I2C_T_SU_STO[curSite] * 1e-9);\n\t TestLog(\"T_I2C_VD_ACK_RISE\", d_I2C_T_VD_ACK_RISE[curSite] * 1e-9);\n\t TestLog(\"T_I2C_VD_ACK_FALL\", d_I2C_T_VD_ACK_FALL[curSite] * 1e-9);\n\t TestLog(\"FUNCTIONAL_TEST\", \t\t\ti_funcRes[curSite]);\n\n return;\n }\n\n /**\n *This function will be invoked once the specified parameter's value is changed.\n *@param parameterIdentifier\n */\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n //Add your code\n //Note: Test Method API should not be used in this method!\n return;\n }\n\n /**\n *This function will be invoked once the Select Test Method Dialog is opened.\n */\n virtual const string getComment() const \n {\n string comment = \" please add your comment for this method.\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T04_08_I2C_characterization_V1\", T04_08_I2C_characterization_V1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 3 $ $Author: rio1rt $ $Date: 2024/05/03 08:07:32 GMT $')\ndly(10e-6)\nubw('SDO') # Release SDO pad\ndly(10e-6)\ncmt('Execute I3C init pattern to enter I3C mode(included in pattern)')\nscmd('do SETDASA_DIRECT_CCC i3c_seq keeping {'\n '.target == BST;'\n '.dev_addr == 0x42;'\n '};')\ndly(10e-6)\nwac('EXT_MODE',0x0000)\nrac('CHIP_ID', 0x00af, 0x00ff) # Check chip access\nwr('FIFO_WATERMARK', 0x02a5) # Write signature to register\nrac('FIFO_WATERMARK', 0x02a5) # Read signature from register\nwac('FIFO_WATERMARK', 0x0000) # Clear register\nwac('PWR_CONF', 0x0000) # Keep advanced power save off (default is 0x0)\ndly(10e-6)\nwr('CMD', 0xBB3A) # 1st command for enabling the extended mode\nwr('CMD', 0x2C62) # 2nd command for enabling the extended mode\nwr('CMD', 0xA576) # 1st command for enabling the super privilege mode\nwr('CMD', 0x34D6) # 2nd command for enabling the super privilege mode\ndly(10e-6)\nwac('ACC_CONF', 0xe24c) # Enable ACC in HPM; set AFS=32g; set ODR=1600; set BW=200\ndly(400e-6)\nrac('ERR_REG', 0x0000) # Check error register\nwac('EXT_MODE', 0xc00d) # Enable super privilege mode; switch to ANA register page\nrac('STATUS_PMOD0', 0x0003, 0x0003) # Check ACC AFE PMU status\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T04_09_I3C_test_V3: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n// vector i_comment_line0;\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n// i_comment_line0 = search_comment_line(s_label_name);\n// print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T04_09_I3C_test_V3_PAT_id\");\n rdi.func().label(s_label_name).execute();\n RDI_END();\n ON_FIRST_INVOCATION_END();\n \n int Func_result = rdi.id(\"T04_09_I3C_test_V3_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T04_09_I3C_test_V3\", T04_09_I3C_test_V3);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "# Warning, AA workaround applied, TE3 not executed\ncmt('Version info: $Revision: bai430aa_rel/2 $ $Author: luz3sgh $ $Date: 2024/09/26 08:47:02 GMT $')\n# ---I3C Protocol check---\ncmt('Check chip already in I3C state, and dev_addr assigned to 0x42)')\ndly(10e-6)\nwr('EXT_MODE', 0x0000) # Switch to USR mode\nwr('FIFO_WATERMARK', 0x02a5) # Write signature to register\nrac('FIFO_WATERMARK', 0x02a5) # Read signature from register\ndly(10e-6)\n\n# ---HDR EXIT---\ncmt('Switch to HDR_DDR mode (included in pattern)')\nscmd('do ENTHDR0_BROADCAST_CCC i3c_seq keeping {'\n '.do_stop == FALSE;'\n '};')\ndly(10e-6)\ncmt('Drive HDR_DDR traffic to enter HDR_DDR mode (included in pattern)')\nscmd('do PRIVATE_DDR i3c_seq keeping {'\n '.target == BST;'\n '.do_enthdr0_seq == FALSE;'\n '.do_hdr_exit == FALSE;'\n '};')\ndly(10e-6)\ncmt('Drive HDR_DDR EXIT pattern to exist HDR_DDR mode (included in pattern)')\nscmd('do START_STOP i3c_seq keeping {'\n '.i3c_bus_mode == HDR_DDR;'\n '.do_hdr_exit == TRUE;'\n '};')\ndly(10e-6)\nwr('FIFO_WATERMARK', 0x025a) # Write signature to register\nrac('FIFO_WATERMARK', 0x025a) # Read signature from register\ndly(10e-6)\n\n# ---TRIGGER TE0 ERROR---\ncmt('Trigger TE0 error (included in pattern)')\nscmd(\"do TE0'error_type SDR_ERROR CONTROLLER i3c_seq;\")\n#error_recovery is enabled by default in i3c_target eVC\n\ndly(10e-6)\nrac('FIFO_WATERMARK', 0x025a) # Check I3C target recovery\nrac('ERR_REG', 0x0100) # Check I3C te0 error has been triggered\nrac('ERR_REG', 0x0000) # Check reset of error register\ndly(10e-6)\n\n# ---TRIGGER TE1 ERROR---\ncmt('Trigger TE1 error (included in pattern)')\nscmd(\"do TE1'error_type SDR_ERROR CONTROLLER i3c_seq;\")\n#error_recovery is enabled by default in i3c_target eVC\ndly(10e-6)\nrac('FIFO_WATERMARK', 0x025a) # Check I3C target recovery\nrac('ERR_REG', 0x0200) # Check I3C te1 error has been triggered\nrac('ERR_REG', 0x0000) # Check reset of error register\ndly(10e-6)\n\n# ---TRIGGER TE2 ERROR---\ncmt('Trigger TE2 error (included in pattern)')\nscmd(\"do TE2'error_type SDR_ERROR CONTROLLER i3c_seq;\")\n#error_recovery is enabled by default in i3c_target eVC\n\ndly(10e-6)\nrac('FIFO_WATERMARK', 0x025a) # Check I3C target recovery\nrac('ERR_REG', 0x0400) # Check I3C te2 error has been triggered\nrac('ERR_REG', 0x0000) # Check reset of error register\ndly(10e-6)\n\n# ---TRIGGER TE3 ERROR---\n#cmt('Trigger TE3 error (included in pattern)')\n#scmd(\"do TE3'error_type SDR_ERROR CONTROLLER i3c_seq;\")\n#error_recovery is enabled by default in i3c_target eVC\n\n#dly(10e-6)\n#rac('FIFO_WATERMARK', 0x025a) # Check I3C target recovery\n#rac('ERR_REG', 0x0800) # Check I3C te3 error has been triggered\n#rac('ERR_REG', 0x0000) # Check reset of error register\n#dly(10e-6)\n\n# ---TRIGGER TE4 ERROR---\ncmt('Trigger TE4 error (included in pattern)')\nscmd(\"do TE4'error_type SDR_ERROR CONTROLLER i3c_seq;\")\n#error_recovery is enabled by default in i3c_target eVC\n\ndly(10e-6)\nrac('FIFO_WATERMARK', 0x025a) # Check I3C target recovery\nrac('ERR_REG', 0x1000) # Check I3C te4 error has been triggered\nrac('ERR_REG', 0x0000) # Check reset of error register\ndly(10e-6)\n\n# ---RESET DAA---\ncmt('Send the RST DAA CC to reset the dynamic address (included in pattern)')\nscmd('do RSTDAA_BROADCAST_CCC i3c_seq;')\ndly(10e-6)\nrac('FIFO_WATERMARK', 0x0000) # Read access expeced to fail and target does not ACK\nwr('FIFO_WATERMARK', 0x0000) # Write access expeced to fail and target does not ACK\ndly(10e-6)\ncmt('Re-assign the dynamic address (included in pattern)')\nscmd('do SETDASA_DIRECT_CCC i3c_seq keeping {'\n '.target == BST;'\n '.dev_addr == 0x42;'\n '};')\ncmt('Re-enable target interrupts IBI (included in pattern)')\nscmd('do ENEC_DIRECT_CCC i3c_seq keeping {'\n '.target == BST;'\n '.enint;'\n '};')\ndly(10e-6)\nrac('FIFO_WATERMARK', 0x025a) # Check read works after DAA re-assignment\nwr('FIFO_WATERMARK', 0x0255) # Write signature to register\nrac('FIFO_WATERMARK', 0x0255) # Read signature from register and check wr/rd access pass\nwac('FIFO_WATERMARK', 0x0000) # Set register to reset value\ndly(10e-6)\n\n# ---IBI---\nwac('INT_MAP_MCU', 0x0003) # Map interrrupt to MCU A (IBI)\nwr('CMD', 0xBB3A) # 1st command for enabling the extended mode\nwr('CMD', 0x2C62) # 2nd command for enabling the extended mode\nwac('EXT_MODE', 0x8000) # Enter extended mode\nwac('EXT_MODE', 0x8004) # Switch to HWINT register page\nwr('INT_MCU_SET', 0x0001) # Trigger MCU interrupt A\n# The following SCX mask signal is used in the pattern generation flow to mask SCX to '1'.\n# The ASIC is driving SDX to '0'. Since the master clock is masked and not toggling, the ASIC is keeping SDX at '0'\n# This mechanism is used to verify the ASIC has triggered the IBI interrupt.\nbm('SCX') # Set SCX mask to mask I3C master response to IBI\ndly(10e-6)\nubm('SCX') # Unset SCX mask; Note: for pattern gen SCX mask falling edge is used for the SDX bit compare\n# Note: The following bit compare SDX=0 is masked out becase it will be implemented with the pattern generaton flow\n# bc('SDX', 0) # Check IBI has been triggered and drives SDX to '0'\ndly(10e-6)\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T04_11_I3C_feature_test_V4: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n// vector i_comment_line0;\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n// i_comment_line0 = search_comment_line(s_label_name);\n// print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T04_11_I3C_feature_test_V4_PAT_id\");\n rdi.func().label(s_label_name).execute();\n RDI_END();\n ON_FIRST_INVOCATION_END();\n \n int Func_result = rdi.id(\"T04_11_I3C_feature_test_V4_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T04_11_I3C_feature_test_V4\", T04_11_I3C_feature_test_V4);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: I2C communication at max speed 1 MHz\n# - Use I2C device ID 0x68\n# - Entry condition PU_I2C\n# - Device init and unlock super privilege mode\n# - Execute single write, single read, burst read\n#############################################################################################################\ncmt('Version info: $Revision: 5 $ $Author: luz3sgh $ $Date: 2024/05/06 07:27:57 GMT $')\ncmt('Use signal and timing conventions compliant with I2C')\ncmt('Enable pull-up (active load) on pad SDX')\ncmt('Use the following parameters: F_sck = 1.0 MHz')\nubw('SDO') # Release SDO pad\ndly(10e-6)\nrac('CHIP_ID', 0x00af, 0x00ff) # Check chip access\nwac('PWR_CONF', 0x0000) # Keep advanced power save off (default is 0x0)\ndly(10e-6)\nwr('CMD', 0xBB3A) # 1st command for enabling the extended mode\nwr('CMD', 0x2C62) # 2nd command for enabling the extended mode\nwr('CMD', 0xA576) # 1st command for enabling the super privilege mode\nwr('CMD', 0x34D6) # 2nd command for enabling the super privilege mode\ndly(10e-6)\nwac('ACC_CONF', 0xe24c) # Enable ACC in HPM; set AFS=32g; set ODR=1600; set BW=200\ndly(400e-6)\nrac('ERR_REG', 0x0000) # Check error register\nwac('EXT_MODE', 0xc00d) # Enable super privilege mode; switch to ANA register page\nrac('STATUS_PMOD0', 0x0003, 0x0003) # Check ACC AFE PMU status\nwac('EXT_MODE', 0xc007) # Switch to MCU register page\n# single write single read\nwr('MCU_SW_STATUS0', 0x55aa) # Write signature to register\nrac('MCU_SW_STATUS0', 0x55aa) # Read signature from register\nwr('MCU_SW_STATUS1', 0x81cc) # Write signature to register\nrac('MCU_SW_STATUS1', 0x81cc) # Read signature from register\nwr('MCU_SW_STATUS2', 0xf00f) # Write signature to register\nrac('MCU_SW_STATUS2', 0xf00f) # Read signature from register\nwr('MCU_SW_STATUS3', 0xaa55) # Write signature to register\nrac('MCU_SW_STATUS3', 0xaa55) # Read signature from register\n# burst read\nbrac('MCU_SW_STATUS0', [0x55aa,0x81cc,0xf00f,0xaa55]) # Burst read and compare\n# register reset\nwac('MCU_SW_STATUS0', 0x0000) # Reset register value\nwac('MCU_SW_STATUS1', 0x0000) # Reset register value\nwac('MCU_SW_STATUS2', 0x0000) # Reset register value\nwac('MCU_SW_STATUS3', 0x0000) # Reset register value\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T04_16_I2C_test_devID68_V5: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n// vector i_comment_line0;\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n// i_comment_line0 = search_comment_line(s_label_name);\n// print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T04_16_I2C_test_devID68_V5_PAT_id\");\n rdi.func().label(s_label_name).execute();\n RDI_END();\n ON_FIRST_INVOCATION_END();\n \n int Func_result = rdi.id(\"T04_16_I2C_test_devID68_V5_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T04_16_I2C_test_devID68_V5\", T04_16_I2C_test_devID68_V5);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: I2C communication at max speed 1 MHz\n# - Use I2C device ID 0x69\n# - Entry condition PU_I2C\n# - Device init and unlock super privilege mode\n# - Execute single write, single read, burst read\n#############################################################################################################\ncmt('Version info: $Revision: 5 $ $Author: luz3sgh $ $Date: 2024/05/06 07:27:55 GMT $')\ncmt('Use signal and timing conventions compliant with I2C')\ncmt('Enable pull-up (active load) on pad SDX')\ncmt('Use the following parameters: F_sck = 1.0 MHz')\nubw('SDO') # Release SDO pad\ndly(10e-6)\nrac('CHIP_ID', 0x00af, 0x00ff) # Check chip access\nwac('PWR_CONF', 0x0000) # Keep advanced power save off (default is 0x0)\ndly(10e-6)\nwr('CMD', 0xBB3A) # 1st command for enabling the extended mode\nwr('CMD', 0x2C62) # 2nd command for enabling the extended mode\nwr('CMD', 0xA576) # 1st command for enabling the super privilege mode\nwr('CMD', 0x34D6) # 2nd command for enabling the super privilege mode\ndly(10e-6)\nwac('ACC_CONF', 0xe24c) # Enable ACC in HPM; set AFS=32g; set ODR=1600; set BW=200\ndly(400e-6)\nrac('ERR_REG', 0x0000) # Check error register\nwac('EXT_MODE', 0xc00d) # Enable super privilege mode; switch to ANA register page\nrac('STATUS_PMOD0', 0x0003, 0x0003) # Check ACC AFE PMU status\nwac('EXT_MODE', 0xc007) # Switch to MCU register page\n# single write single read\nwr('MCU_SW_STATUS0', 0x55aa) # Write signature to register\nrac('MCU_SW_STATUS0', 0x55aa) # Read signature from register\nwr('MCU_SW_STATUS1', 0x81cc) # Write signature to register\nrac('MCU_SW_STATUS1', 0x81cc) # Read signature from register\nwr('MCU_SW_STATUS2', 0xf00f) # Write signature to register\nrac('MCU_SW_STATUS2', 0xf00f) # Read signature from register\nwr('MCU_SW_STATUS3', 0xaa55) # Write signature to register\nrac('MCU_SW_STATUS3', 0xaa55) # Read signature from register\n# burst read\nbrac('MCU_SW_STATUS0', [0x55aa,0x81cc,0xf00f,0xaa55]) # Burst read and compare\n# register reset\nwac('MCU_SW_STATUS0', 0x0000) # Reset register value\nwac('MCU_SW_STATUS1', 0x0000) # Reset register value\nwac('MCU_SW_STATUS2', 0x0000) # Reset register value\nwac('MCU_SW_STATUS3', 0x0000) # Reset register value\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T04_17_I2C_test_devID69_V5: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n// vector i_comment_line0;\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n// i_comment_line0 = search_comment_line(s_label_name);\n// print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T04_17_I2C_test_devID69_V5_PAT_id\");\n rdi.func().label(s_label_name).execute();\n RDI_END();\n ON_FIRST_INVOCATION_END();\n \n int Func_result = rdi.id(\"T04_17_I2C_test_devID69_V5_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T04_17_I2C_test_devID69_V5\", T04_17_I2C_test_devID69_V5);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# Description:\n# - Enable secondary interface OIS\n# - Read OIS test register via secondary interface\n# - Disable secondary interface\n#############################################################################################################\ncmt('Version info: $Revision: 2 $ $Author: luz3sgh $ $Date: 2024/05/21 05:45:06 GMT $')\n\nwac('EXT_MODE', 0xc009) # Switch to IO register page\nwcb('disable_sec_if', 0x0) # Ensure secondary IF is not disabled (default=0x0)\nwac('IO_IF_CONF', 0x0008) # Enable OIS SPI4 interface\nwac('EXT_MODE', 0xc000) # Switch to USR register page\ncmt('Read address 0x00 via OIS interface and compare read-out to 0xaf (included in pattern)')\nscmd('var OIS_CHIP_ID : OIS_CHIP_ID vr_ad_reg;'\n 'read_reg {'\n '.driver == driver.rsd_ois;'\n '.byte_enable == 0xFF;' # Read mask\n '} OIS_CHIP_ID;')\ncmt('Read address 0x5a via OIS interface and compare read-out to 0xaa (included in pattern)')\nscmd('var OIS_TEST_L : OIS_TEST_L vr_ad_reg;'\n 'read_reg {'\n '.driver == driver.rsd_ois;'\n '.byte_enable == 0xFF;' # Read mask\n '} OIS_TEST_L;')\ncmt('Read address 0x5b via OIS interface and compare read-out to 0x55 (included in pattern)')\nscmd('var OIS_TEST_H : OIS_TEST_H vr_ad_reg;'\n 'read_reg {'\n '.driver == driver.rsd_ois;'\n '.byte_enable == 0xFF;' # Read mask\n '} OIS_TEST_H;')\t \nwac('EXT_MODE', 0xc009) # Switch to IO register page\nwac('IO_IF_CONF', 0x0000) # Disable OIS SPI4 interface\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T04_20_OIS_test_V1: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n// vector i_comment_line0;\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n// i_comment_line0 = search_comment_line(s_label_name);\n// print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n rdi.hwRelay().pin(\"ASDX\").setOn(\"AC\").setOff(\"DC,PPMU\").execute();\n RDI_BEGIN(mode);\n rdi.burstId(\"T04_20_OIS_test_V1_PAT_id\");\n rdi.func().label(s_label_name).execute();\n RDI_END();\n ON_FIRST_INVOCATION_END();\n \n int Func_result = rdi.id(\"T04_20_OIS_test_V1_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T04_20_OIS_test_V1\", T04_20_OIS_test_V1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# Description:\n# - Enable secondary interface OIS, SPI4 mode 0 @10MHz\n# - Read OIS test register via secondary interface\n# - Disable secondary interface\n#############################################################################################################\ncmt('Version info: $Revision: 4 $ $Author: luz3sgh $ $Date: 2024/06/24 06:54:38 GMT $')\ndef register_read():\n CMT('Read through OIS interface from OIS_TEST_L/H using SPI4 protocol')\n scmd('var OIS_TEST_L : OIS_TEST_L vr_ad_reg;'\n 'var OIS_TEST_H : OIS_TEST_H vr_ad_reg;'\n 'read_reg {'\n '.driver == driver.rsd_ois;'\n '.byte_enable == 0xFFFF;' # Read mask\n '} OIS_TEST_L;'\n 'read_reg {'\n '.driver == driver.rsd_ois;'\n '.byte_enable == 0xFFFF;' # Read mask\n '} OIS_TEST_H;')\n\nwac('EXT_MODE', 0xc009) # Switch to IO register page\nwcb('disable_sec_if', 0x0) # Ensure secondary IF is not disabled (default=0x0)\nwac('IO_IF_CONF', 0x0008) # Enable OIS SPI4 interface\nwac('EXT_MODE', 0xc000) # Switch to USR register page\ncmt('There are two OIS read operations in register_read sequence,expect 0xAA & 0x55')\n# OCSB Setup Time SPI4 mode 0\nCMT('Test OCSB Setup Time in SPI4 mode 0 (CPOL = 0 and CPHA = 0)')\nCMT('Use signal and timing conventions compliant with SPI4 mode 0 according test spec')\nCMT('Execute the sequences \"register_read\"')\nCMT('If pattern pass: In \"register_read\" shift falling edges of OCSB signal to the right')\nCMT('relative to ASCX rising edges in 1 ns steps and repeat \"register_read\"')\nCMT('If pattern fail: Record the time T_SETUP_OCSB_M0 at which \"register_read\" passed')\nCMT('for the last time')\nCMT('Start sequence \"register_read\"')\nregister_read()\nCMT('Stop sequence \"register_read\"')\n# OCSB Hold Time SPI4 mode 0\nCMT('Test OCSB Hold Time in SPI4 mode 0 (CPOL = 0 and CPHA = 0)')\nCMT('Use signal and timing conventions compliant with SPI4 mode 0 according test spec')\nCMT('Execute the sequences \"register_read\"')\nCMT('If pattern pass: In \"register_read\" shift rising edges of OCSB signal to the left')\nCMT('relative to ASCX rising edges in 1 ns steps and repeat \"register_read\"')\nCMT('If pattern fail: Record the time T_HOLD_OCSB_M0 at which \"register_read\" passed')\nCMT('for the last time')\nCMT('Start sequence \"register_read\"')\nregister_read()\nCMT('Stop sequence \"register_read\"')\n# ASDX Setup Time SPI4 mode 0\nCMT('Test ASDX Setup Time in SPI4 mode 0 (CPOL = 0 and CPHA = 0)')\nCMT('Use signal and timing conventions compliant with SPI4 mode 0 according test spec')\nCMT('Execute the sequences \"register_read\"')\nCMT('If pattern pass: In \"register_read\" shift all edges of ASDX signal to the right')\nCMT('relative to ASCX edges in 1 ns steps and repeat \"register_read\"')\nCMT('If pattern fail: Record the time T_SETUP_ASDX_M0 at which \"register_read\" passed')\nCMT('for the last time')\nCMT('Start sequence \"register_read\"')\nregister_read()\nCMT('Stop sequence \"register_read\"')\n# ASDX Hold Time SPI4 mode 0\nCMT('Test ASDX Hold Time in SPI4 mode 0 (CPOL = 0 and CPHA = 0)')\nCMT('Use signal and timing conventions compliant with SPI4 mode 0 according test spec')\nCMT('Execute the sequences \"register_read\"')\nCMT('If pattern pass: In \"register_read\" shift all edges of ASDX signal to the left')\nCMT('relative to ASCX edges in 1 ns steps and repeat \"register_read\"')\nCMT('If pattern fail: Record the time T_HOLD_ASDX_M0 at which \"register_read\" passed')\nCMT('for the last time')\nCMT('Start sequence \"register_read\"')\nregister_read()\nCMT('Stop sequence \"register_read\"')\n# OSDO Delay Time SPI4 mode 0\nCMT('Test OSDO Delay Time in SPI4 mode 0 (CPOL = 0 and CPHA = 0)')\nCMT('Use signal and timing conventions compliant with SPI4 mode 0 according test spec')\nCMT('Set default OSDO strobe point in ATE')\nCMT('Execute the sequence \"register_read\"')\nCMT('If pattern pass: In \"register_read\" shift all OSDO strobe points to the left')\nCMT('relative to ASCX falling edges in 1 ns steps and repeat \"register_read\"')\nCMT('If pattern fail: Record the time T_DELAY_OSDO_M0 at which \"register_read\" passed')\nCMT('for the last time')\nCMT('Start sequence \"register_read\"')\nregister_read()\nCMT('Stop sequence \"register_read\"')\n# clean -up\nwac('EXT_MODE', 0xc009) # Switch to IO register page\nwac('IO_IF_CONF', 0x0000) # Disable OIS SPI4 interface\n", "output": "#include \"testmethod.hpp\"\n\n//for test method API interfaces (any system include should be added above this line)\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\n//for MTP test method API interfaces\n\nusing namespace std;\n\n/**\n * Test method class.\n *\n * For each testsuite using this test method, one object of this\n * class is created.\n */\nclass T04_21_OIS_Char_M0: public testmethod::TestMethod {\n\nprotected:\n\t int \t mSPI_mode;\n\t int i_funcRes[xNSitES];\n\t double d_T_SETUP_CSB[xNSitES];\n\t double d_T_HOLD_CSB[xNSitES];\n\t double d_T_SETUP_SDI[xNSitES];\n\t double d_T_HOLD_SDI[xNSitES];\n\t double d_T_DELAY_SDO[xNSitES];\n\t double d_T_HOLD_SDO[xNSitES];\n\t double d_F_SCK[xNSitES];\n\t double d_T_LOW_SCX[xNSitES];\n\t double d_T_HIGH_SCX[xNSitES];\n\t string mCSBpin;\n\t string mSCLKpin;\n\t string mMOSIpin;\n\t string mMISOpin;\n /**\n *Initialize the parameter interface to the testflow.\n *This method is called just once after a testsuite is created.\n */\n virtual void initialize()\n {\n //Add your initialization code here\n //Note: Test Method API should not be used in this method!\n\taddParameter(\"SPI_mode\",\n\t\t\t\t \"int\",\n\t\t\t\t &mSPI_mode,\n\t\t\t\t testmethod::TM_PARAMETER_INPUT)\n\t .setDefault(\"0\");\n\n\taddParameter(\"CSBpin\",\n\t\t\t\t \"string\",\n\t\t\t\t &mCSBpin,\n\t\t\t\t testmethod::TM_PARAMETER_INPUT)\n\t .setDefault(\"OCSB\");\n\n\taddParameter(\"SCLKpin\",\n\t\t\t\t \"string\",\n\t\t\t\t &mSCLKpin,\n\t\t\t\t testmethod::TM_PARAMETER_INPUT)\n\t .setDefault(\"ASCX\");\n\n\taddParameter(\"MOSIpin\",\n\t\t\t\t \"string\",\n\t\t\t\t &mMOSIpin,\n\t\t\t\t testmethod::TM_PARAMETER_INPUT)\n\t .setDefault(\"ASDX\");\n\n\taddParameter(\"MISOpin\",\n\t\t\t\t \"string\",\n\t\t\t\t &mMISOpin,\n\t\t\t\t testmethod::TM_PARAMETER_INPUT)\n\t .setDefault(\"OSDO\");\n }\n\n /**\n *This test is invoked per site.\n */\n virtual void run()\n {\n\t const string pat_name[4] = {\"T04_21_OIS_Char_M0\", \"\", \"\", \"T04_22_OIS_Char_M3\" };\n\t const string s_Label_Init \t\t= pat_name[mSPI_mode]+\"_Init\";\n\t const string s_Label_Set \t\t= pat_name[mSPI_mode]+\"_register_read\";\n\n\t static int i_func_results[xNSitES][5];\n\n\t static double d_TransitionTime1[xNSitES], d_TransitionTime2[xNSitES], d_TransitionTime3[xNSitES], d_TransitionTime4[xNSitES], d_TransitionTime5[xNSitES];\n\n\t SEARCH_FUNC_TASK TASK_spec1, TASK_spec2, TASK_spec3, TASK_spec4, TASK_spec5;\n\n\t int i_PassFail;\n\n ON_FIRST_INVOCATION_BEGIN();\n\n\t Func_Init_Var(i_funcRes, 0, xNSitES);\n\t Func_Init_Var(d_T_SETUP_CSB, -999.0, xNSitES);\n\t Func_Init_Var(d_T_HOLD_CSB, -999.0, xNSitES);\n\t Func_Init_Var(d_T_SETUP_SDI, -999.0, xNSitES);\n\t Func_Init_Var(d_T_HOLD_SDI, -999.0, xNSitES);\n\n\n\t Func_Init_Var((int**)i_func_results, -999, xNSitES, 5);\n\t Func_Init_Var(d_TransitionTime1, -999.0, xNSitES);\n\t Func_Init_Var(d_TransitionTime2, -999.0, xNSitES);\n\t Func_Init_Var(d_TransitionTime3, -999.0, xNSitES);\n\t Func_Init_Var(d_TransitionTime4, -999.0, xNSitES);\n\t Func_Init_Var(d_TransitionTime5, -999.0, xNSitES);\n\n\n\t Primary.label(s_Label_Init);\n\t FLUSH();\n\t FUNCTIONAL_TEST();\n\t FOR_EACH_SITE_BEGIN();\n\t\t i_func_results[curSite][0] = GET_FUNCTIONAL_RESULT();\n\t\t Func_Print(i_func_results[curSite][0], \"i_func_results[0]\");\n\t FOR_EACH_SITE_END();\n\n Primary.timing(TIMING_SPEC(43,1));\n FLUSH(TM::APRM);\n\n\n\t //*************************CSB Setup Time OIS*************************\n\t Primary.label(s_Label_Set);\n\t FLUSH(TM::APRM);\n\t TASK_spec1.pin(mCSBpin).spec(\"delay1\",TM::TIM).method(TM::Linear).start(0).stop(100).stepWidth(1);\n\t TASK_spec1.execute();\n\n\t FOR_EACH_SITE_BEGIN();\n\t\t i_PassFail = TASK_spec1.getPassFail(mCSBpin);\n\n\t\t if(i_PassFail)\n\t\t {\n\t\t\t d_TransitionTime1[curSite] = TASK_spec1.getPassValue(mCSBpin);\n\t\t\t d_T_SETUP_CSB[curSite] = (50 - d_TransitionTime1[curSite]) ; //unit ns\n\t\t\t Func_Print(d_TransitionTime1[curSite], \"Org TransitionTime1\");\n\t\t\t Func_Print(d_T_SETUP_CSB[curSite], \"d_T_SETUP_CSB\");\n\t\t }\n\t FOR_EACH_SITE_END();\n\n\t\t //*************************CSB Hold Time OIS*************************\n//\t\t Primary.getTimingSpec().change(\"delay5\", -50);\n\t\t Primary.label(s_Label_Set);\n\t\t Primary.getTimingSpec().restore();\n\t\t FLUSH(TM::APRM);\n\t\t TASK_spec2.pin(mCSBpin).spec(\"delay2\",TM::TIM).method(TM::Linear).start(0).stop(-100).stepWidth(1);\n\n\t\t TASK_spec2.execute();\n\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t\t i_PassFail = TASK_spec2.getPassFail(mCSBpin);\n\t\t\t //if find the transition point, get value\n\t\t\t if(i_PassFail)\n\t\t\t {\n\t\t\t\t d_TransitionTime2[curSite] = TASK_spec2.getPassValue(mCSBpin);\n\t\t\t\t d_T_HOLD_CSB[curSite] = (50 + d_TransitionTime2[curSite]) ; //unit s\n\n\t\t\t\t Func_Print(d_TransitionTime2[curSite], \"Org TransitionTime2\");\n\t\t\t\t Func_Print(d_T_HOLD_CSB[curSite], \"d_T_HOLD_CSB\");\n\t\t\t }\n\t\t FOR_EACH_SITE_END();\n\n\n\t\t //*************************SDI Setup Time OIS*************************\n\n\t\t Primary.label(s_Label_Set);\n\t\t Primary.getTimingSpec().restore();\n\t\t FLUSH(TM::APRM);\n\t\t TASK_spec3.pin(mMOSIpin).spec(\"delay3\",TM::TIM).method(TM::Linear).start(0).stop(100).stepWidth(1);\n\n\t\t TASK_spec3.execute();\n\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t\t i_PassFail = TASK_spec3.getPassFail(mMOSIpin);\n\t\t\t //if find the transition point, get value\n\t\t\t if(i_PassFail)\n\t\t\t {\n\t\t\t\t d_TransitionTime3[curSite] = TASK_spec3.getPassValue(mMOSIpin);\n\t\t\t\t d_T_SETUP_SDI[curSite] = (50 - d_TransitionTime3[curSite]) ; //unit s\n\n\t\t\t\t Func_Print(d_TransitionTime3[curSite], \"Org TransitionTime3\");\n\t\t\t\t Func_Print(d_T_SETUP_SDI[curSite], \"d_T_SETUP_SDI\");\n\t\t\t }\n\t\t FOR_EACH_SITE_END();\n\n\n\t\t //*************************SDI Hold Time OIS*************************\n\t\t Primary.label(s_Label_Set);\n\t\t Primary.getTimingSpec().restore();\n\t\t FLUSH();\n\t\t TASK_spec4.pin(mMOSIpin).spec(\"delay3\",TM::TIM).method(TM::Linear).start(0).stop(-100).stepWidth(1);\n\t\t TASK_spec4.execute();\n\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t\t i_PassFail = TASK_spec4.getPassFail(mMOSIpin);\n\t\t\t //if find the transition point, get value\n\t\t\t if(i_PassFail)\n\t\t\t {\n\t\t\t\t d_TransitionTime4[curSite] = TASK_spec4.getPassValue(mMOSIpin);\n\t\t\t\t d_T_HOLD_SDI[curSite] = (50 + d_TransitionTime4[curSite]) ; //unit s\n\n\t\t\t\t Func_Print(d_TransitionTime4[curSite], \"Org TransitionTime4\");\n\t\t\t\t Func_Print(d_T_HOLD_SDI[curSite], \"d_T_HOLD_SDI\");\n\t\t\t }\n\t\t FOR_EACH_SITE_END();\n\n\n\t\t //*************************SDO Delay Time OIS*************************\n\n\t\t Primary.getTimingSpec().restore();\n\t\t Primary.label(s_Label_Set);\n\n\t\t FLUSH();\n//\t\t TASK_spec5.pin(\"SDO\").spec(\"delay5\",TM::TIM).method(TM::Binary).start(0).stop(-82).resolution(0.5);\n\t\t TASK_spec5.pin(mMISOpin).spec(\"delay5\",TM::TIM).method(TM::Linear).start(0).stop(-100).stepWidth(1);\n\t\t TASK_spec5.execute();\n\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t\t i_PassFail = TASK_spec5.getPassFail(mMISOpin);\n\t\t\t //if find the transition point, get value\n\t\t\t if(i_PassFail)\n\t\t\t {\n\t\t\t\t d_TransitionTime5[curSite] = TASK_spec5.getPassValue(mMISOpin);\n\t\t\t\t d_T_DELAY_SDO[curSite] = (0.5*100 + d_TransitionTime5[curSite]) ; //unit s\n\n\t\t\t\t Func_Print(d_TransitionTime5[curSite], \"Org TransitionTime5\");\n\t\t\t\t Func_Print(d_T_DELAY_SDO[curSite], \"d_T_DELAY_SDO\");\n\t\t\t }\n\t\t FOR_EACH_SITE_END();\n\n\n\t\t FOR_EACH_SITE_BEGIN();\n\t\t \t i_funcRes[curSite] = i_func_results[curSite][0];\n\n\t\t FOR_EACH_SITE_END();\n\n\n\t ON_FIRST_INVOCATION_END();\n\n\t Func_Print(i_funcRes[curSite], \"i_funcRes\");\n\n\t TestLog(\"FUNCTIONAL_TEST\", \t\t\t\t\t\ti_funcRes[curSite]);\n\t TestLog(\"T_SETUP_\"+mCSBpin+\"_M\"+rdi.itos(mSPI_mode), \td_T_SETUP_CSB[curSite]*1e-9);\n\t TestLog(\"T_HOLD_\"+mCSBpin+\"_M\"+rdi.itos(mSPI_mode), \td_T_HOLD_CSB[curSite]*1e-9);\n\t TestLog(\"T_SETUP_\"+mMOSIpin+\"_M\"+rdi.itos(mSPI_mode), \td_T_SETUP_SDI[curSite]*1e-9);\n\t TestLog(\"T_HOLD_\"+mMOSIpin+\"_M\"+rdi.itos(mSPI_mode), \td_T_HOLD_SDI[curSite]*1e-9);\n\t TestLog(\"T_DELAY_\"+mMISOpin+\"_M\"+rdi.itos(mSPI_mode), \td_T_DELAY_SDO[curSite]*1e-9);\n\n\n\n\n return;\n }\n\n /**\n *This function will be invoked once the specified parameter's value is changed.\n *@param parameterIdentifier\n */\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n //Add your code\n //Note: Test Method API should not be used in this method!\n return;\n }\n\n /**\n *This function will be invoked once the Select Test Method Dialog is opened.\n */\n virtual const string getComment() const \n {\n string comment = \" please add your comment for this method.\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T04_21_OIS_Char_M0\", T04_21_OIS_Char_M0);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: bai430aa_rel/1 $ $Author: luz3sgh $ $Date: 2024/08/13 06:12:21 GMT $')\nwr('EXT_MODE', 0xc000) # Switch to USR register page\nwr('OCP_MASK', 0x0001) # Set masking register\nwr('IO_IF_CONF', 0x0001) # Enable SPI3 mode\ndly(10e-6)\nrac('IO_IF_CONF', 0x0001, 0x0001) # Check setting of SPI3 mode\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T04_30_switch_SPI4_to_SPI3_V1: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n// vector i_comment_line0;\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n// i_comment_line0 = search_comment_line(s_label_name);\n// print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T04_30_switch_SPI4_to_SPI3_V1_PAT_id\");\n rdi.func().label(s_label_name).execute();\n RDI_END();\n ON_FIRST_INVOCATION_END();\n \n int Func_result = rdi.id(\"T04_30_switch_SPI4_to_SPI3_V1_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T04_30_switch_SPI4_to_SPI3_V1\", T04_30_switch_SPI4_to_SPI3_V1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 1 $ $Author: hmf1rt $ $Date: 2024/03/13 13:36:52 GMT $')\nwr('EXT_MODE', 0xc000) # Switch to USR register page\nwr('OCP_MASK', 0x0001) # Set masking register\nwr('IO_IF_CONF', 0x0000) # Enable SPI4 mode\ndly(10e-6)\nrac('IO_IF_CONF', 0x0000, 0x0001) # Check setting of SPI4 mode\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T04_31_switch_SPI3_to_SPI4_V1: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n// vector i_comment_line0;\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n// i_comment_line0 = search_comment_line(s_label_name);\n// print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T04_31_switch_SPI3_to_SPI4_V1_PAT_id\");\n rdi.func().label(s_label_name).execute();\n RDI_END();\n ON_FIRST_INVOCATION_END();\n \n int Func_result = rdi.id(\"T04_31_switch_SPI3_to_SPI4_V1_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T04_31_switch_SPI3_to_SPI4_V1\", T04_31_switch_SPI3_to_SPI4_V1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 3 $ $Author: luz3sgh $ $Date: 2024/06/09 06:02:00 GMT $')\nsav('VDD', 0.0)\nsav('VDDIO', 0.0)\ndly(1e-3)\nfor p in ['CSB','SCX','SDX','SDO','INT1','INT2','OCSB','ASCX','ASDX','OSDO']:\n sac('{}'.format(p), 100e-6, i_range = 200e-6, v_comp_p=1.0, v_comp_n=0.0)\n dly(100e-6)\n gav('V_CONT_{}'.format(p), '{}'.format(p))\n uac('{}'.format(p))\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: LSN3SGH, py 4\n * Update: LSN3SGH, py 7--20230328\n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T06_01_Continuity_test: public testmethod::TestMethod {\n\nprotected:\n\n\tstring OD_Pads;\n\tstring supply_Pads;\n\n virtual void initialize()\n {\n\t addParameter(\"supply_Pads_string\",\n\t\t\t \t \"PinString\",\n\t\t\t \t &supply_Pads,\n\t\t\t \t testmethod::TM_PARAMETER_INPUT)\n\t\t\t \t .setDefault(\"VDDIO,VDD\");\n\t addParameter(\"OD_Pads_string\",\n\t\t\t \"PinString\",\n\t\t\t &OD_Pads,\n\t\t\t testmethod::TM_PARAMETER_INPUT)\n\t\t\t .setDefault(\"CSB,SCX,SDX,SDO,INT1,INT2,OCSB,ASCX,ASDX,OSDO\");\n }\n virtual void run()\n {\n\n\t static STRING test_name;\n\t const string s_label_name = Primary.getLabel();\n//\t vector i_comment_line0;\n\n\t string rly={\"K1_K2\"};\n\t string rly_all={\"K1_K2,K3,K4,K5,K6,K7,K8,K9\"};\n\n\t STRING_VECTOR supply_str,od_str;\n\t supply_str=PinUtility.getDigitalPinNamesFromPinList(supply_Pads, TM::ALL_DIGITAL, TRUE, TRUE, PIN_UTILITY::DEFINITION_ORDER);\n\t od_str=PinUtility.getDigitalPinNamesFromPinList(OD_Pads, TM::ALL_DIGITAL, TRUE, TRUE, PIN_UTILITY::DEFINITION_ORDER);\n\n\t RDI_INIT();\n\n\t ON_FIRST_INVOCATION_BEGIN();\n\n\t\t rdi.enableOre(oreFlag);\n\t\t rdi.oreFile(\"./ORE_Files/rdi_ore_T06_01_Continuity_test.xml\");\n\n\t\t rdi.util().pin(rly_all).setOff().execute();\n\t\t rdi.util().pin(rly).setOn().execute();\n\t\t rdi.wait(2 ms);\n\t\t rdi.dc().pin(\"All_AVI64\").disconnect().execute();\n\n\t\t RDI_BEGIN(mode);\n\t\t rdi.dc().pin(OD_Pads).vForce(0 V).iRange(40 mA).execute();\n\t\t rdi.dc().pin(supply_Pads).vForce(0 V).clamp(-0.1 mA, 0.1 mA).execute();\n\t\t rdi.wait(20 us);\n\n\t\t for(unsigned int i=0; i i_comment_line0;\n\n\t string rly={\"K1_K2\"};\n\t string rly_all={\"K1_K2,K3,K4,K5,K6,K7,K8,K9\"};\n\n\t STRING_VECTOR supply_str,od_str;\n\t supply_str=PinUtility.getDigitalPinNamesFromPinList(supply_Pads, TM::ALL_DIGITAL, TRUE, TRUE, PIN_UTILITY::DEFINITION_ORDER);\n\t od_str=PinUtility.getDigitalPinNamesFromPinList(OD_Pads, TM::ALL_DIGITAL, TRUE, TRUE, PIN_UTILITY::DEFINITION_ORDER);\n\n\t RDI_INIT();\n\n\t const double force_current1 = -10e-3;\n\t const double force_current2 = -20e-3;\n\n\t ON_FIRST_INVOCATION_BEGIN();\n\n\t\t rdi.util().pin(rly_all).setOff().execute();\n\t\t rdi.util().pin(rly).setOn().execute();\n\t\t rdi.wait(2 ms);\n\t\t rdi.dc().pin(\"All_AVI64\").disconnect().execute();\n\t\t rdi.hwRelay().pin(\"ALL_PS1600\").setOff(\"ALL\").execute();\n\t\t rdi.dc().pin(supply_Pads).vForce(0 V).clamp(-40 mA, 40 mA).execute();\n\n//\t\t RDI_BEGIN(mode);\n\t\t rdi.dc(\"V_CONT_SDO_force1\").pin(\"SDO\").iForce(force_current1).clamp(-2 V, 2 V).vMeas().average(256).measWait(10 ms).execute();\n\t\t rdi.wait(1 ms);\n\t\t rdi.dc().pin(\"CSB,SCX,SDX,ASCX,ASDX,SDO\").iForce(force_current1).execute();\n\t\t rdi.dc(\"V_CONT_SDO_force1_X6\").pin(\"SDO\").iForce(force_current1).clamp(-2 V, 2 V).vMeas().average(256).measWait(10 ms).execute();\n\n\t\t rdi.hwRelay().pin(\"ALL_PS1600\").setOff(\"ALL\").execute();\n\n\t\t rdi.dc().pin(supply_Pads).vForce(0 V).clamp(-40 mA, 40 mA).execute();\n\t\t rdi.dc(\"V_CONT_SDO_force2\").pin(\"SDO\").iForce(force_current2).clamp(-2 V, 2 V).vMeas().average(256).measWait(10 ms).execute();\n\t\t rdi.wait(1 ms);\n\t\t rdi.dc().pin(\"CSB,SCX,SDX,ASCX,ASDX,SDO\").iForce(force_current2).execute();\n\t\t rdi.dc(\"V_CONT_SDO_force2_X6\").pin(\"SDO\").iForce(force_current2).clamp(-2 V, 2 V).vMeas().average(256).measWait(10 ms).execute();\n\n\t\t rdi.hwRelay().pin(\"ALL_PS1600\").setOff(\"ALL\").execute();\n//\t\t RDI_END();\n//\t\t rdi.dc().pin(\"All_AVI64\").disconnect().execute();\n\t ON_FIRST_INVOCATION_END();\n\n\t\t double V_CONT_SDO_force1 = rdi.id(\"V_CONT_SDO_force1\").getValue();\n\t\t double V_CONT_SDO_force1_X6 = rdi.id(\"V_CONT_SDO_force1_X6\").getValue();\n\t\t double v_delta_force1 = V_CONT_SDO_force1_X6 - V_CONT_SDO_force1;\n\t\t double r_gnd_force1 = v_delta_force1 / (force_current1 * 5);\n\n\t\t double V_CONT_SDO_force2 = rdi.id(\"V_CONT_SDO_force2\").getValue();\n\t\t double V_CONT_SDO_force2_X6 = rdi.id(\"V_CONT_SDO_force2_X6\").getValue();\n\t\t double v_delta_force2 = V_CONT_SDO_force2_X6 - V_CONT_SDO_force2;\n\t\t double r_gnd_force2 = v_delta_force2 / (force_current2 * 5);\n\n\n\n\t\t FuncPrint(\"force_current1\", force_current1);\n\t\t FuncPrint(\"V_CONT_SDO_force1\", V_CONT_SDO_force1);\n\t\t FuncPrint(\"V_CONT_SDO_force1_X6\", V_CONT_SDO_force1_X6);\n\t\t FuncPrint(\"v_delta_force1\", v_delta_force1);\n\t\t FuncPrint(\"r_gnd_force1\", r_gnd_force1);\n\n\t\t FuncPrint(\"force_current2\", force_current2);\n\t\t FuncPrint(\"V_CONT_SDO_force2\", V_CONT_SDO_force2);\n\t\t FuncPrint(\"V_CONT_SDO_force2_X6\", V_CONT_SDO_force2_X6);\n\t\t FuncPrint(\"v_delta_force2\", v_delta_force2);\n\t\t FuncPrint(\"r_gnd_force2\", r_gnd_force2);\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T06_01_Continuity_test_rgnd_measure\", T06_01_Continuity_test_rgnd_measure);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: bai430aa_rel/2 $ $Author: luz3sgh $ $Date: 2024/08/19 06:26:50 GMT $')\nwac('EXT_MODE', 0xc009) # Switch to IO register page\nwac('IO_INT_CTRL', 0x0808) # int2_conf=1 int2_input_en=1 int1_input_en=1 \n \nfor pad in ['CSB','SCX','SDX']: # SPI inputs\n ubw('{}'.format(pad)) # dig_out_en= 0\nfor pad in ['CSB','SCX','SDX','INT1','INT2']:\n sav('{}'.format(pad), 0.0)\ndly(100e-6) # one time for all PADs\ncmt('Check if parallel measurements possible')\nfor pad in ['CSB','SCX','SDX','INT1','INT2']:\n gac('I_LEAK_PU_{}'.format(pad), '{}'.format(pad), i_range=2e-6)\n log('I_LEAK_PU_{}'.format(pad))\nfor pad in ['CSB','SCX','SDX','INT1','INT2']:\n sav('{}'.format(pad), 1.8)\ndly(100e-6) # one time for all PADs\nfor pad in ['CSB','SCX','SDX','INT1','INT2']:\n gac('I_LEAK_PD_{}'.format(pad), '{}'.format(pad), i_range=2e-6)\n log('I_LEAK_PD_{}'.format(pad))\nfor pad in ['CSB','SCX','SDX','INT1','INT2']:\n uav('{}'.format(pad))\nbw('CSB',1) # dig_out_en= 1\nbw('SCX',0) # dig_out_en= 1\nbw('SDX',0) # dig_out_en= 1\nwr('IO_IF_CONF', 0x000A) # sec_if_conf 2, ois eanbled, sec_spi_mode 1, ois spi 3 wire, pri_spi 0, spi4\ndly(2e-3)\nwr('IO_IF_CONF', 0x000A) # sec_if_conf 2, ois eanbled, sec_spi_mode 1, ois spi 3 wire, pri_spi 0, spi4\ndly(2e-3)\nrac('IO_IF_CONF', 0x000A) # sec_if_conf 2, ois eanbled, sec_spi_mode 1, ois spi 3 wire, pri_spi 0, spi4\nwr('IO_TEST_IF', 0x0001) # force_mode=1 (SPI_OIS) configure ASCX, ASDX, OCSB as inputs\n # read back not possible (due to force_mode=1 (SPI_OIS))\nfor pad in ['OCSB','ASCX','ASDX']: \n sav('{}'.format(pad), 0.0)\ndly(100e-6) # one time for all PADs\ncmt('Check if parallel measurements possible')\nfor pad in ['OCSB','ASCX','ASDX']:\n gac('I_LEAK_PU_{}'.format(pad), '{}'.format(pad), i_range=2e-6)\n log('I_LEAK_PU_{}'.format(pad))\nfor pad in ['OCSB','ASCX','ASDX']:\n sav('{}'.format(pad), 1.8)\ndly(100e-6) # one time for all PADs\nfor pad in ['OCSB','ASCX','ASDX']:\n gac('I_LEAK_PD_{}'.format(pad), '{}'.format(pad), i_range=2e-6)\n log('I_LEAK_PD_{}'.format(pad))\nfor pad in ['OCSB','ASCX','ASDX']:\n uav('{}'.format(pad))\nwac('IO_IF_CONF', 0x0000) # reset values\nwac('IO_INT_CTRL', 0x0000) # reset values\nwac('IO_TEST_IF', 0x0000) # reset values\n\n# switch to I2C\n# Note: SDO is not configured as input during this measurement\n# Note: There is no possibility to configure SDO as input permanently\nwr('EXT_MODE', 0xc00d) # Switch to ANA register page\ndly(2e-3)\nrac('EXT_MODE', 0xc00d) # Switch to ANA register page\nrac('STATUS_PMOD0', 0x0003, 0x0003) # Check ACC AFE PMU status\nwr('CMD', 0xdeaf) # Trigger soft reset\ndly(3e-3)\nsav('SDO', 0.0)\ndly(100e-6)\ngac('I_LEAK_PU_SDO', 'SDO', i_range=2e-6)\nsav('SDO', 1.8)\ndly(100e-6)\ngac('I_LEAK_PD_SDO', 'SDO', i_range=2e-6)\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T06_02_Input_Leakage_Test_V7: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n static double I_LEAK_PU_CSB[xNSitES];\n static double I_LEAK_PU_SCX[xNSitES];\n static double I_LEAK_PU_SDX[xNSitES];\n static double I_LEAK_PU_INT1[xNSitES];\n static double I_LEAK_PU_INT2[xNSitES];\n static double I_LEAK_PD_CSB[xNSitES];\n static double I_LEAK_PD_SCX[xNSitES];\n static double I_LEAK_PD_SDX[xNSitES];\n static double I_LEAK_PD_INT1[xNSitES];\n static double I_LEAK_PD_INT2[xNSitES];\n static double I_LEAK_PU_OCSB[xNSitES];\n static double I_LEAK_PU_ASCX[xNSitES];\n static double I_LEAK_PU_ASDX[xNSitES];\n static double I_LEAK_PD_OCSB[xNSitES];\n static double I_LEAK_PD_ASCX[xNSitES];\n static double I_LEAK_PD_ASDX[xNSitES];\n static double I_LEAK_PU_SDO[xNSitES];\n static double I_LEAK_PD_SDO[xNSitES];\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T06_02_Input_Leakage_Test_V7_PAT_id\");\n rdi.dc(\"T06_02_Input_Leakage_Test_V7DC_id0\").label(s_label_name)\n .insertSub(i_comment_line0[0]).pin(\"CSB,SCX,SDX,INT1,INT2\").vForce(0.0)\n .insertSub(i_comment_line0[1]).pin(\"CSB,SCX,SDX,INT1,INT2\").vForce(0 V).iMeas().valueMode(TA::BADC).iRange(2e-06 A).average(16).measWait(0.1 ms) //I_LEAK_PU_CSB\n .insertSub(i_comment_line0[6]).pin(\"CSB,SCX,SDX,INT1,INT2\").vForce(1.8)\n .insertSub(i_comment_line0[7]).pin(\"CSB,SCX,SDX,INT1,INT2\").vForce(1.8 V).iMeas().valueMode(TA::BADC).iRange(2e-06 A).average(16).measWait(0.1 ms) //I_LEAK_PD_CSB\n .insertSub(i_comment_line0[12]).pin(\"CSB,SCX,SDX,INT1,INT2\").relay(TA::ppmuRly_onAC_offDCPPMU)\n .insertSub(i_comment_line0[13]).pin(\"OCSB,ASCX,ASDX\").vForce(0.0)\n .insertSub(i_comment_line0[14]).pin(\"OCSB,ASCX,ASDX\").vForce(0 V).iMeas().valueMode(TA::BADC).iRange(2e-06 A).average(16).measWait(0.1 ms) //I_LEAK_PU_OCSB\n .insertSub(i_comment_line0[17]).pin(\"OCSB,ASCX,ASDX\").vForce(1.8)\n .insertSub(i_comment_line0[18]).pin(\"OCSB,ASCX,ASDX\").vForce(1.8 V).iMeas().valueMode(TA::BADC).iRange(2e-06 A).average(16).measWait(0.1 ms) //I_LEAK_PD_OCSB\n .insertSub(i_comment_line0[21]).pin(\"OCSB,ASCX,ASDX\").relay(TA::ppmuRly_offALL)\n .insertSub(i_comment_line0[22]).pin(\"SDO\").vForce(0.0)\n .insertSub(i_comment_line0[23]).pin(\"SDO\").vForce(0 V).iMeas().valueMode(TA::BADC).iRange(2e-06 A).average(16).measWait(0.1 ms) //I_LEAK_PU_SDO\n .insertSub(i_comment_line0[23]).pin(\"SDO\").vForce(1.8)\n .insertSub(i_comment_line0[24]).pin(\"SDO\").vForce(1.8 V).iMeas().valueMode(TA::BADC).iRange(2e-06 A).average(16).measWait(0.1 ms) //I_LEAK_PD_SDO\n .insertSub(i_comment_line0[24]).pin(\"SDO\").relay(TA::ppmuRly_onAC_offDCPPMU)\n .execute();\n RDI_END();\n ON_FIRST_INVOCATION_END();\n\n ARRAY_D JSUB_results_ASCX;\n JSUB_results_ASCX = rdi.id(\"T06_02_Input_Leakage_Test_V7DC_id0\").getMultiValue(\"ASCX\");\n ARRAY_D JSUB_results_CSB;\n JSUB_results_CSB = rdi.id(\"T06_02_Input_Leakage_Test_V7DC_id0\").getMultiValue(\"CSB\");\n ARRAY_D JSUB_results_ASDX;\n JSUB_results_ASDX = rdi.id(\"T06_02_Input_Leakage_Test_V7DC_id0\").getMultiValue(\"ASDX\");\n ARRAY_D JSUB_results_SDO;\n JSUB_results_SDO = rdi.id(\"T06_02_Input_Leakage_Test_V7DC_id0\").getMultiValue(\"SDO\");\n ARRAY_D JSUB_results_SCX;\n JSUB_results_SCX = rdi.id(\"T06_02_Input_Leakage_Test_V7DC_id0\").getMultiValue(\"SCX\");\n ARRAY_D JSUB_results_SDX;\n JSUB_results_SDX = rdi.id(\"T06_02_Input_Leakage_Test_V7DC_id0\").getMultiValue(\"SDX\");\n ARRAY_D JSUB_results_OCSB;\n JSUB_results_OCSB = rdi.id(\"T06_02_Input_Leakage_Test_V7DC_id0\").getMultiValue(\"OCSB\");\n ARRAY_D JSUB_results_INT1;\n JSUB_results_INT1 = rdi.id(\"T06_02_Input_Leakage_Test_V7DC_id0\").getMultiValue(\"INT1\");\n ARRAY_D JSUB_results_INT2;\n JSUB_results_INT2 = rdi.id(\"T06_02_Input_Leakage_Test_V7DC_id0\").getMultiValue(\"INT2\");\n I_LEAK_PU_CSB[CURRENT_SITE_NUMBER()-1] = JSUB_results_CSB[0];\n I_LEAK_PU_SCX[CURRENT_SITE_NUMBER()-1] = JSUB_results_SCX[0];\n I_LEAK_PU_SDX[CURRENT_SITE_NUMBER()-1] = JSUB_results_SDX[0];\n I_LEAK_PU_INT1[CURRENT_SITE_NUMBER()-1] = JSUB_results_INT1[0];\n I_LEAK_PU_INT2[CURRENT_SITE_NUMBER()-1] = JSUB_results_INT2[0];\n I_LEAK_PD_CSB[CURRENT_SITE_NUMBER()-1] = JSUB_results_CSB[1];\n I_LEAK_PD_SCX[CURRENT_SITE_NUMBER()-1] = JSUB_results_SCX[1];\n I_LEAK_PD_SDX[CURRENT_SITE_NUMBER()-1] = JSUB_results_SDX[1];\n I_LEAK_PD_INT1[CURRENT_SITE_NUMBER()-1] = JSUB_results_INT1[1];\n I_LEAK_PD_INT2[CURRENT_SITE_NUMBER()-1] = JSUB_results_INT2[1];\n I_LEAK_PU_OCSB[CURRENT_SITE_NUMBER()-1] = JSUB_results_OCSB[0];\n I_LEAK_PU_ASCX[CURRENT_SITE_NUMBER()-1] = JSUB_results_ASCX[0];\n I_LEAK_PU_ASDX[CURRENT_SITE_NUMBER()-1] = JSUB_results_ASDX[0];\n I_LEAK_PD_OCSB[CURRENT_SITE_NUMBER()-1] = JSUB_results_OCSB[1];\n I_LEAK_PD_ASCX[CURRENT_SITE_NUMBER()-1] = JSUB_results_ASCX[1];\n I_LEAK_PD_ASDX[CURRENT_SITE_NUMBER()-1] = JSUB_results_ASDX[1];\n I_LEAK_PU_SDO[CURRENT_SITE_NUMBER()-1] = JSUB_results_SDO[0];\n I_LEAK_PD_SDO[CURRENT_SITE_NUMBER()-1] = JSUB_results_SDO[1];\n \n int Func_result = rdi.id(\"T06_02_Input_Leakage_Test_V7_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n FuncPrint(\"I_LEAK_PU_CSB\", I_LEAK_PU_CSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"I_LEAK_PU_SCX\", I_LEAK_PU_SCX[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"I_LEAK_PU_SDX\", I_LEAK_PU_SDX[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"I_LEAK_PU_INT1\", I_LEAK_PU_INT1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"I_LEAK_PU_INT2\", I_LEAK_PU_INT2[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"I_LEAK_PD_CSB\", I_LEAK_PD_CSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"I_LEAK_PD_SCX\", I_LEAK_PD_SCX[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"I_LEAK_PD_SDX\", I_LEAK_PD_SDX[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"I_LEAK_PD_INT1\", I_LEAK_PD_INT1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"I_LEAK_PD_INT2\", I_LEAK_PD_INT2[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"I_LEAK_PU_OCSB\", I_LEAK_PU_OCSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"I_LEAK_PU_ASCX\", I_LEAK_PU_ASCX[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"I_LEAK_PU_ASDX\", I_LEAK_PU_ASDX[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"I_LEAK_PD_OCSB\", I_LEAK_PD_OCSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"I_LEAK_PD_ASCX\", I_LEAK_PD_ASCX[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"I_LEAK_PD_ASDX\", I_LEAK_PD_ASDX[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"I_LEAK_PU_SDO\", I_LEAK_PU_SDO[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"I_LEAK_PD_SDO\", I_LEAK_PD_SDO[CURRENT_SITE_NUMBER()-1]);\n\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"I_LEAK_PU_CSB\", I_LEAK_PU_CSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"I_LEAK_PU_SCX\", I_LEAK_PU_SCX[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"I_LEAK_PU_SDX\", I_LEAK_PU_SDX[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"I_LEAK_PU_INT1\", I_LEAK_PU_INT1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"I_LEAK_PU_INT2\", I_LEAK_PU_INT2[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"I_LEAK_PD_CSB\", I_LEAK_PD_CSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"I_LEAK_PD_SCX\", I_LEAK_PD_SCX[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"I_LEAK_PD_SDX\", I_LEAK_PD_SDX[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"I_LEAK_PD_INT1\", I_LEAK_PD_INT1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"I_LEAK_PD_INT2\", I_LEAK_PD_INT2[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"I_LEAK_PU_OCSB\", I_LEAK_PU_OCSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"I_LEAK_PU_ASCX\", I_LEAK_PU_ASCX[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"I_LEAK_PU_ASDX\", I_LEAK_PU_ASDX[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"I_LEAK_PD_OCSB\", I_LEAK_PD_OCSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"I_LEAK_PD_ASCX\", I_LEAK_PD_ASCX[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"I_LEAK_PD_ASDX\", I_LEAK_PD_ASDX[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"I_LEAK_PU_SDO\", I_LEAK_PU_SDO[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"I_LEAK_PD_SDO\", I_LEAK_PD_SDO[CURRENT_SITE_NUMBER()-1]);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T06_02_Input_Leakage_Test_V7\", T06_02_Input_Leakage_Test_V7);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 3 $ $Author: hmf1rt $ $Date: 2024/04/19 13:50:33 GMT $')\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_CONF', 0x0001) # Enable TB1\nwac('TM_PIN', 0xf0b5) # Enable ANAIO1/2/4; TB1_OUT on ANAIO1; TB1_INP on ANAIO2; DEV_TIOP on ANAIO4\nwac('TM_ADDR', 0x0003) # Enable ATM loop back test\nsav('OCSB', 1.0) # Set voltage stimuli of 1V on OCSB\ndly(1352*74e-9)\nuclk('ASCX')\nbw('ASCX', 1)\ncmt('Note: the absolute votage on both INT2/ASDX is ~1V, the differential voltage is close to 0V')\ncmt('TOI: The measurement needs to be done with an accuracy of +/- 1mV')\ndly(100e-6)\ngav('V_OFF1_ECON', 'INT2', 'ASDX', v_range=0.1)\nlog('V_OFF1_ECON')\ndly(48e-9)\nubw('ASCX')\nclk('ASCX', 1/148e-9)\nuav('OCSB') # Disable voltage stimuli and set to highZ configuration\ndly(1352*74e-9)\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_CONF', 0x0012) # Enable TB2 + BUS_INV\nwac('TM_PIN', 0xf05b) # Enable ANAIO1/2/4; TB2_OUT on ANAIO2; TB2_INP on ANAIO1; DEV_TIOP on ANAIO3\nwac('TM_ADDR', 0x0003) # Enable ATM loop back test\nsav('OCSB', 1.0) # Set voltage stimuli of 1V on OCSB\ndly(1352*74e-9)\nuclk('ASCX')\nbw('ASCX', 1)\ncmt('Note: the absolute votage on both INT2/ASDX is ~1V, the differential voltage is close to 0V')\ncmt('TOI: The measurement needs to be done with an accuracy of +/- 1mV')\ndly(1352*74e-9)\ngav('V_OFF2_ECON', 'ASDX', 'INT2', v_range=0.1)\nlog('V_OFF2_ECON')\nubw('ASCX')\nclk('ASCX', 1/148e-9)\nuav('OCSB') # Disable voltage stimuli and set to highZ configuration\ndly(1352*74e-9)\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T07_01_testbuffer_offset_measurement_econ_V3: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n\t rdi.enableOre(oreFlag);\n\t rdi.oreFile(\"./ORE_Files/rdi_ore_T07_01_TESTBUFFER_OFFSET_MEASUREMENT_ECON.xml\");\n\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T07_01_testbuffer_offset_measurement_econ_V3_PAT_id\");\n rdi.dc(\"T07_01_testbuffer_offset_measurement_econ_V3DC_id0\").label(s_label_name)\n .insertSub(i_comment_line0[0]).pin(\"OCSB\").vForce(1.0)\n .insertSub(i_comment_line0[1]).pin(\"INT2,ASDX\",TA::BADC).vMeas().average(128).measWait(1 ms) //V_OFF1_ECON\n .insertSub(i_comment_line0[2]).pin(\"OCSB\").relay(TA::ppmuRly_offALL)\n .insertSub(i_comment_line0[3]).pin(\"OCSB\").vForce(1.0)\n .insertSub(i_comment_line0[4]).pin(\"ASDX,INT2\",TA::BADC).vMeas().average(128).measWait(1 ms) //V_OFF2_ECON\n .insertSub(i_comment_line0[5]).pin(\"OCSB\").relay(TA::ppmuRly_offALL)\n .execute();\n RDI_END();\n ON_FIRST_INVOCATION_END();\n\n ARRAY_D JSUB_results_ASDX;\n JSUB_results_ASDX = rdi.id(\"T07_01_testbuffer_offset_measurement_econ_V3DC_id0\").getMultiValue(\"ASDX\");\n ARRAY_D JSUB_results_INT2;\n JSUB_results_INT2 = rdi.id(\"T07_01_testbuffer_offset_measurement_econ_V3DC_id0\").getMultiValue(\"INT2\");\n V_OFF1_ECON[CURRENT_SITE_NUMBER()-1] = JSUB_results_INT2[0] - JSUB_results_ASDX[0];\n V_OFF2_ECON[CURRENT_SITE_NUMBER()-1] = JSUB_results_ASDX[1] - JSUB_results_INT2[1];\n\n int Func_result = rdi.id(\"T07_01_testbuffer_offset_measurement_econ_V3_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n\n FuncPrint(\"JSUB_results_ASDX_0\", JSUB_results_ASDX[0]);\n FuncPrint(\"JSUB_results_ASDX_1\", JSUB_results_ASDX[1]);\n FuncPrint(\"JSUB_results_INT2_0\", JSUB_results_INT2[0]);\n FuncPrint(\"JSUB_results_INT2_1\", JSUB_results_INT2[1]);\n\n FuncPrint(\"V_OFF1_ECON\", V_OFF1_ECON[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"V_OFF2_ECON\", V_OFF2_ECON[CURRENT_SITE_NUMBER()-1]);\n\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"V_OFF1_ECON\", V_OFF1_ECON[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"V_OFF2_ECON\", V_OFF2_ECON[CURRENT_SITE_NUMBER()-1]);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T07_01_testbuffer_offset_measurement_econ_V3\", T07_01_testbuffer_offset_measurement_econ_V3);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 2 $ $Author: laj1mu23 $ $Date: 2024/03/25 20:27:19 GMT $')\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_CONF', 0x0001) # Enable TB1\nwac('TM_PIN', 0x0db5) # Enable ANAIO1/2/3; TB1_OUT on ANAIO1; TB1_INP on ANAIO2; DEV_TM on ANAIO3\nwac('TM_ADDR', 0x0003) # Enable ATM loop back test\nsav('ASCX', 1.0) # Set voltage stimuli of 1V on ASCX\ncmt('Note: the absolute votage on both INT2/ASDX is ~1V, the differential voltage is close to 0V')\ncmt('TOI: The measurement needs to be done with an accuracy of +/- 1mV')\ndly(100e-6)\ngav('V_OFF1_ECOFF', 'INT2', 'ASDX', v_range=0.1)\nlog('V_OFF1_ECOFF')\nuav('ASCX') # Disable voltage stimuli and set to highZ configuration\ndly(100e-6)\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_CONF', 0x0012) # Enable TB2 + BUS_INV\nwac('TM_PIN', 0x0d5b) # Enable ANAIO1/2/3; TB2_OUT on ANAIO2; TB2_INP on ANAIO1; DEV_TM on ANAIO3\nwac('TM_ADDR', 0x0003) # Enable ATM loop back test\nsav('ASCX', 1.0) # Set voltage stimuli of 1V on ASCX\ncmt('Note: the absolute votage on both INT2/ASDX is ~1V, the differential voltage is close to 0V')\ncmt('TOI: The measurement needs to be done with an accuracy of +/- 1mV')\ndly(100e-6)\ngav('V_OFF2_ECOFF', 'ASDX', 'INT2', v_range=0.1)\nlog('V_OFF2_ECOFF')\nuav('ASCX') # Disable voltage stimuli and set to highZ configuration\ndly(100e-6)\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\n", "output": "/*****************************************************\n * T07_02_testbuffer_offset_measurement_ecoff_V2, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T07_02_testbuffer_offset_measurement_ecoff_V2: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static double d_V_OFF1_ECOFF[xNSitES];\n static double d_V_OFF2_ECOFF[xNSitES];\n static int i_funcRes0[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n rdi.enableOre(oreFlag);\n rdi.oreFile(\"./ORE_Files/rdi_ore_T07_02_TESTBUFFER_OFFSET_MEASUREMENT_ECOFF.xml\");\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(d_V_OFF1_ECOFF, 9.9, xNSitES);\n Func_Init_Var(d_V_OFF2_ECOFF, 9.9, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T07_02_testbuffer_offset_measurement_ecoff}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 1] @ avcline 778: {sav('ASCX', 1, 2, 0.01, False, False)}\n valid comment[ 1] @ avcline 778: {cmt: Note: the absolute votage on both INT2/ASDX is ~1V, the differential voltage is close to 0V}\n valid comment[ 1] @ avcline 778: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 2] @ avcline 788: {gav('V_OFF1_ECOFF', 'INT2', 'ASDX', 0.1, 0.0001, True)}\n valid comment[ 2] @ avcline 788: {log('V_OFF1_ECOFF', '', '', 0, 0)}\n valid comment[ 3] @ avcline 789: {uav('ASCX', False)}\n valid comment[ 4] @ avcline 1566: {sav('ASCX', 1, 2, 0.01, False, False)}\n valid comment[ 4] @ avcline 1566: {cmt: Note: the absolute votage on both INT2/ASDX is ~1V, the differential voltage is close to 0V}\n valid comment[ 4] @ avcline 1566: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 5] @ avcline 1576: {gav('V_OFF2_ECOFF', 'ASDX', 'INT2', 0.1, 0.0001, True)}\n valid comment[ 5] @ avcline 1576: {log('V_OFF2_ECOFF', '', '', 0, 0)}\n valid comment[ 6] @ avcline 1577: {uav('ASCX', False)}\n valid comment[ 7] @ avcline 2162: {Test End: T07_02_testbuffer_offset_measurement_ecoff}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][1]).pin(\"ASCX\").vForce(1 V)//{sav('ASCX', 1, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][2]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_OFF1_ECOFF//{gav('V_OFF1_ECOFF', 'INT2', 'ASDX', 0.1, 0.0001, True)}\n .insertSub(i_comment_line[0][3]).pin(\"ASCX\").relay(TA::ppmuRly_offALL)////{uav('ASCX', False)}\n .insertSub(i_comment_line[0][4]).pin(\"ASCX\").vForce(1 V)//{sav('ASCX', 1, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][5]).pin(\"ASDX,INT2\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_OFF2_ECOFF//{gav('V_OFF2_ECOFF', 'ASDX', 'INT2', 0.1, 0.0001, True)}\n .insertSub(i_comment_line[0][6]).pin(\"ASCX\").relay(TA::ppmuRly_offALL)////{uav('ASCX', False)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n ARRAY_D ad_jsubresults_ASDX; ad_jsubresults_ASDX.resize(2); ad_jsubresults_ASDX.init(-9.9);\n ARRAY_D ad_jsubresults_INT2; ad_jsubresults_INT2.resize(2); ad_jsubresults_INT2.init(-9.9);\n\n ad_jsubresults_ASDX = rdi.id(\"dcid_0\").getMultiValue(\"ASDX\");\n ad_jsubresults_INT2 = rdi.id(\"dcid_0\").getMultiValue(\"INT2\");\n\n V_OFF1_ECOFF[curSite] = ad_jsubresults_INT2[0] - ad_jsubresults_ASDX[0];\n V_OFF2_ECOFF[curSite] = ad_jsubresults_ASDX[1] - ad_jsubresults_INT2[1];\n\n FuncPrint(\"ad_jsubresults_INT2[0]\",ad_jsubresults_INT2[0]);\n FuncPrint(\"ad_jsubresults_ASDX[0]\",ad_jsubresults_ASDX[0]);\n\n FuncPrint(\"ad_jsubresults_ASDX[1]\",ad_jsubresults_ASDX[1]);\n FuncPrint(\"ad_jsubresults_INT2[1]\",ad_jsubresults_INT2[1]);\n\n FuncPrint(\"V_OFF1_ECOFF\",V_OFF1_ECOFF[curSite]);\n FuncPrint(\"V_OFF2_ECOFF\",V_OFF2_ECOFF[curSite]);\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n\n ON_FIRST_INVOCATION_END();\n\n TestLog(\"V_OFF1_ECOFF\",V_OFF1_ECOFF[curSite]);\n TestLog(\"V_OFF2_ECOFF\",V_OFF2_ECOFF[curSite]);\n i_funcRes[curSite] = i_funcRes0[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T07_02_testbuffer_offset_measurement_ecoff_V2\", T07_02_testbuffer_offset_measurement_ecoff_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# Description: \n# Verify that the 2 testbuffer offset measurements in the test flow have the same result\n#############################################################################################################\ncmt('Version info: $Revision: 1 $ $Author: hmf1rt $ $Date: 2024/03/13 13:36:52 GMT $')\ncmt('Get the 2 result parameters \"V_OFF1_ECON\" and \"V_OFF2_ECON\" from test item T07.01')\ncmt('Get the 2 result parameters \"V_OFF1_ECOFF\" and \"V_OFF2_ECOFF\" from test item T07.02')\ncmt('Calculate V_OFF1_DELTA = V_OFF1_ECON - V_OFF1_ECOFF')\nlog('V_OFF1_DELTA')\ncmt('Calculate V_OFF2_DELTA = V_OFF2_ECON - V_OFF2_ECOFF')\nlog('V_OFF2_DELTA')\n", "output": "/*****************************************************\n * T07_02_testbuffer_offset_measurement_ecoff_V2, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T07_03_testbuffer_offset_validation: public testmethod::TestMethod {\n\n protected:\n// int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n\n\t double V_OFF1_DELTA = V_OFF1_ECON[CURRENT_SITE_NUMBER()-1] - V_OFF1_ECOFF[CURRENT_SITE_NUMBER()-1];\n\t double V_OFF2_DELTA = V_OFF2_ECON[CURRENT_SITE_NUMBER()-1] - V_OFF2_ECOFF[CURRENT_SITE_NUMBER()-1];\n TestLog(\"V_OFF1_DELTA\",V_OFF1_DELTA);\n TestLog(\"V_OFF2_DELTA\",V_OFF2_DELTA);\n\n FuncPrint(\"V_OFF1_DELTA\",V_OFF1_DELTA);\n FuncPrint(\"V_OFF2_DELTA\",V_OFF2_DELTA);\n FuncPrint(\"V_OFF1_ECON\",V_OFF1_ECON[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"V_OFF1_ECOFF\",V_OFF1_ECOFF[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"V_OFF2_ECON\",V_OFF2_ECON[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"V_OFF2_ECOFF\",V_OFF2_ECOFF[CURRENT_SITE_NUMBER()-1]);\n\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T07_03_testbuffer_offset_validation\", T07_03_testbuffer_offset_validation);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 2 $ $Author: laj1mu23 $ $Date: 2024/03/25 20:27:19 GMT $')\nsav('ASCX', 0.5) # Set voltage on ASCX\ndly(100e-6)\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_ADDR', 0x0003) # Enable ATM loop back test\nwac('TM_PIN', 0x0db5) # Enable ANAIO1/2/3; TB1_OUT on ANAIO1; TB1_INP on ANAIO2; DEV_TM on ANAIO3\nwac('TM_CONF', 0x0001) # Enable TB1\ncmt('Note: the absolute voltage on both INT2/ASDX is ~0.5V .. 1.7V, the differential voltage is close to 0V')\ncmt('TOI: The measurement needs to be done with an accuracy of +/- 1mV')\nfor n in range (0, 7, 1):\n sav('ASCX', 0.5+n*0.2)\n dly(100e-6)\n gav('V_OFF1_C[{:02d}]'.format(n), 'INT2', 'ASDX', v_range=0.1)\n log('V_OFF1_C[{:02d}]'.format(n))\nwac('TM_PIN', 0x0111) # Set ATM ANAIO 4 => off, 3:1 => highZ\ndly(100e-6)\n#sav('ASCX', 0.5) # Set voltage on ASCX\nwac('TM_PIN', 0x0d5b) # Enable ANAIO1/2/3; TB2_OUT on ANAIO2; TB2_INP on ANAIO1; DEV_TM on ANAIO3\nwac('TM_CONF', 0x0012) # Enable TB2 + BUS_INV\ncmt('Note: the absolute voltage on both INT2/ASDX is ~0.5V .. 1.7V, the differential voltage is close to 0V')\ncmt('TOI: The measurement needs to be done with an accuracy of +/- 1mV')\nfor n in range (0, 7, 1):\n sav('ASCX', 0.5+n*0.2)\n dly(100e-6)\n gav('V_OFF2_C[{:02d}]'.format(n), 'ASDX', 'INT2', v_range=0.1)\n log('V_OFF2_C[{:02d}]'.format(n))\nuav('ASCX') # Disable voltage stimuli and set to highZ configuration\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\ndly(100e-6)\n", "output": "/*****************************************************\n * T07_04_Testbuffer_Voltage_Char_V2, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n * JSH5SGH: fix some bugs.\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T07_04_Testbuffer_Voltage_Char_V2: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static double d_V_OFF1_C_00[xNSitES];\n static double d_V_OFF1_C_01[xNSitES];\n static double d_V_OFF1_C_02[xNSitES];\n static double d_V_OFF1_C_03[xNSitES];\n static double d_V_OFF1_C_04[xNSitES];\n static double d_V_OFF1_C_05[xNSitES];\n static double d_V_OFF1_C_06[xNSitES];\n static double d_V_OFF2_C_00[xNSitES];\n static double d_V_OFF2_C_01[xNSitES];\n static double d_V_OFF2_C_02[xNSitES];\n static double d_V_OFF2_C_03[xNSitES];\n static double d_V_OFF2_C_04[xNSitES];\n static double d_V_OFF2_C_05[xNSitES];\n static double d_V_OFF2_C_06[xNSitES];\n static int i_funcRes0[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(d_V_OFF1_C_00, 9.9, xNSitES);\n Func_Init_Var(d_V_OFF1_C_01, 9.9, xNSitES);\n Func_Init_Var(d_V_OFF1_C_02, 9.9, xNSitES);\n Func_Init_Var(d_V_OFF1_C_03, 9.9, xNSitES);\n Func_Init_Var(d_V_OFF1_C_04, 9.9, xNSitES);\n Func_Init_Var(d_V_OFF1_C_05, 9.9, xNSitES);\n Func_Init_Var(d_V_OFF1_C_06, 9.9, xNSitES);\n Func_Init_Var(d_V_OFF2_C_00, 9.9, xNSitES);\n Func_Init_Var(d_V_OFF2_C_01, 9.9, xNSitES);\n Func_Init_Var(d_V_OFF2_C_02, 9.9, xNSitES);\n Func_Init_Var(d_V_OFF2_C_03, 9.9, xNSitES);\n Func_Init_Var(d_V_OFF2_C_04, 9.9, xNSitES);\n Func_Init_Var(d_V_OFF2_C_05, 9.9, xNSitES);\n Func_Init_Var(d_V_OFF2_C_06, 9.9, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T07_04_Testbuffer_Voltage_Char}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 0] @ avcline 10: {sav('ASCX', 0.5, 2, 0.01, False, False)}\n valid comment[ 1] @ avcline 788: {cmt: Note: the absolute voltage on both INT2/ASDX is ~0.5V .. 1.7V, the differential voltage is close to 0V}\n valid comment[ 1] @ avcline 788: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 1] @ avcline 788: {sav('ASCX', 0.5, 2, 0.01, False, False)}\n valid comment[ 2] @ avcline 798: {gav('V_OFF1_C[00]', 'INT2', 'ASDX', 0.1, 0.0001, True)}\n valid comment[ 2] @ avcline 798: {log('V_OFF1_C[00]', '', '', 0, 0)}\n valid comment[ 3] @ avcline 799: {sav('ASCX', 0.7, 2, 0.01, False, False)}\n valid comment[ 4] @ avcline 808: {gav('V_OFF1_C[01]', 'INT2', 'ASDX', 0.1, 0.0001, True)}\n valid comment[ 4] @ avcline 808: {log('V_OFF1_C[01]', '', '', 0, 0)}\n valid comment[ 5] @ avcline 809: {sav('ASCX', 0.9, 2, 0.01, False, False)}\n valid comment[ 6] @ avcline 819: {gav('V_OFF1_C[02]', 'INT2', 'ASDX', 0.1, 0.0001, True)}\n valid comment[ 6] @ avcline 819: {log('V_OFF1_C[02]', '', '', 0, 0)}\n valid comment[ 7] @ avcline 820: {sav('ASCX', 1.1, 2, 0.01, False, False)}\n valid comment[ 8] @ avcline 829: {gav('V_OFF1_C[03]', 'INT2', 'ASDX', 0.1, 0.0001, True)}\n valid comment[ 8] @ avcline 829: {log('V_OFF1_C[03]', '', '', 0, 0)}\n valid comment[ 9] @ avcline 830: {sav('ASCX', 1.3, 2, 0.01, False, False)}\n valid comment[ 10] @ avcline 839: {gav('V_OFF1_C[04]', 'INT2', 'ASDX', 0.1, 0.0001, True)}\n valid comment[ 10] @ avcline 839: {log('V_OFF1_C[04]', '', '', 0, 0)}\n valid comment[ 11] @ avcline 840: {sav('ASCX', 1.5, 2, 0.01, False, False)}\n valid comment[ 12] @ avcline 850: {gav('V_OFF1_C[05]', 'INT2', 'ASDX', 0.1, 0.0001, True)}\n valid comment[ 12] @ avcline 850: {log('V_OFF1_C[05]', '', '', 0, 0)}\n valid comment[ 13] @ avcline 851: {sav('ASCX', 1.7, 2, 0.01, False, False)}\n valid comment[ 14] @ avcline 860: {gav('V_OFF1_C[06]', 'INT2', 'ASDX', 0.1, 0.0001, True)}\n valid comment[ 14] @ avcline 860: {log('V_OFF1_C[06]', '', '', 0, 0)}\n valid comment[ 15] @ avcline 1447: {cmt: Note: the absolute voltage on both INT2/ASDX is ~0.5V .. 1.7V, the differential voltage is close to 0V}\n valid comment[ 15] @ avcline 1447: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 15] @ avcline 1447: {sav('ASCX', 0.5, 2, 0.01, False, False)}\n valid comment[ 16] @ avcline 1457: {gav('V_OFF2_C[00]', 'ASDX', 'INT2', 0.1, 0.0001, True)}\n valid comment[ 16] @ avcline 1457: {log('V_OFF2_C[00]', '', '', 0, 0)}\n valid comment[ 17] @ avcline 1458: {sav('ASCX', 0.7, 2, 0.01, False, False)}\n valid comment[ 18] @ avcline 1467: {gav('V_OFF2_C[01]', 'ASDX', 'INT2', 0.1, 0.0001, True)}\n valid comment[ 18] @ avcline 1467: {log('V_OFF2_C[01]', '', '', 0, 0)}\n valid comment[ 19] @ avcline 1468: {sav('ASCX', 0.9, 2, 0.01, False, False)}\n valid comment[ 20] @ avcline 1478: {gav('V_OFF2_C[02]', 'ASDX', 'INT2', 0.1, 0.0001, True)}\n valid comment[ 20] @ avcline 1478: {log('V_OFF2_C[02]', '', '', 0, 0)}\n valid comment[ 21] @ avcline 1479: {sav('ASCX', 1.1, 2, 0.01, False, False)}\n valid comment[ 22] @ avcline 1488: {gav('V_OFF2_C[03]', 'ASDX', 'INT2', 0.1, 0.0001, True)}\n valid comment[ 22] @ avcline 1488: {log('V_OFF2_C[03]', '', '', 0, 0)}\n valid comment[ 23] @ avcline 1489: {sav('ASCX', 1.3, 2, 0.01, False, False)}\n valid comment[ 24] @ avcline 1498: {gav('V_OFF2_C[04]', 'ASDX', 'INT2', 0.1, 0.0001, True)}\n valid comment[ 24] @ avcline 1498: {log('V_OFF2_C[04]', '', '', 0, 0)}\n valid comment[ 25] @ avcline 1499: {sav('ASCX', 1.5, 2, 0.01, False, False)}\n valid comment[ 26] @ avcline 1509: {gav('V_OFF2_C[05]', 'ASDX', 'INT2', 0.1, 0.0001, True)}\n valid comment[ 26] @ avcline 1509: {log('V_OFF2_C[05]', '', '', 0, 0)}\n valid comment[ 27] @ avcline 1510: {sav('ASCX', 1.7, 2, 0.01, False, False)}\n valid comment[ 28] @ avcline 1519: {gav('V_OFF2_C[06]', 'ASDX', 'INT2', 0.1, 0.0001, True)}\n valid comment[ 28] @ avcline 1519: {log('V_OFF2_C[06]', '', '', 0, 0)}\n valid comment[ 29] @ avcline 1520: {uav('ASCX', False)}\n valid comment[ 30] @ avcline 2106: {Test End: T07_04_Testbuffer_Voltage_Char}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][0]).pin(\"ASCX\").vForce(0.5 V)//{sav('ASCX', 0.5, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][1]).pin(\"ASCX\").vForce(0.5 V)//{sav('ASCX', 0.5, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][2]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_OFF1_C_00//{gav('V_OFF1_C[00]', 'INT2', 'ASDX', 0.1, 0.0001, True)}\n .insertSub(i_comment_line[0][3]).pin(\"ASCX\").vForce(0.7 V)//{sav('ASCX', 0.7, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][4]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_OFF1_C_01//{gav('V_OFF1_C[01]', 'INT2', 'ASDX', 0.1, 0.0001, True)}\n .insertSub(i_comment_line[0][5]).pin(\"ASCX\").vForce(0.9 V)//{sav('ASCX', 0.9, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][6]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_OFF1_C_02//{gav('V_OFF1_C[02]', 'INT2', 'ASDX', 0.1, 0.0001, True)}\n .insertSub(i_comment_line[0][7]).pin(\"ASCX\").vForce(1.1 V)//{sav('ASCX', 1.1, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][8]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_OFF1_C_03//{gav('V_OFF1_C[03]', 'INT2', 'ASDX', 0.1, 0.0001, True)}\n .insertSub(i_comment_line[0][9]).pin(\"ASCX\").vForce(1.3 V)//{sav('ASCX', 1.3, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][10]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_OFF1_C_04//{gav('V_OFF1_C[04]', 'INT2', 'ASDX', 0.1, 0.0001, True)}\n .insertSub(i_comment_line[0][11]).pin(\"ASCX\").vForce(1.5 V)//{sav('ASCX', 1.5, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][12]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_OFF1_C_05//{gav('V_OFF1_C[05]', 'INT2', 'ASDX', 0.1, 0.0001, True)}\n .insertSub(i_comment_line[0][13]).pin(\"ASCX\").vForce(1.7 V)//{sav('ASCX', 1.7, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][14]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_OFF1_C_06//{gav('V_OFF1_C[06]', 'INT2', 'ASDX', 0.1, 0.0001, True)}\n .insertSub(i_comment_line[0][15]).pin(\"ASCX\").vForce(0.5 V)//{sav('ASCX', 0.5, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][16]).pin(\"ASDX,INT2\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_OFF2_C_00//{gav('V_OFF2_C[00]', 'ASDX', 'INT2', 0.1, 0.0001, True)}\n .insertSub(i_comment_line[0][17]).pin(\"ASCX\").vForce(0.7 V)//{sav('ASCX', 0.7, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][18]).pin(\"ASDX,INT2\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_OFF2_C_01//{gav('V_OFF2_C[01]', 'ASDX', 'INT2', 0.1, 0.0001, True)}\n .insertSub(i_comment_line[0][19]).pin(\"ASCX\").vForce(0.9 V)//{sav('ASCX', 0.9, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][20]).pin(\"ASDX,INT2\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_OFF2_C_02//{gav('V_OFF2_C[02]', 'ASDX', 'INT2', 0.1, 0.0001, True)}\n .insertSub(i_comment_line[0][21]).pin(\"ASCX\").vForce(1.1 V)//{sav('ASCX', 1.1, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][22]).pin(\"ASDX,INT2\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_OFF2_C_03//{gav('V_OFF2_C[03]', 'ASDX', 'INT2', 0.1, 0.0001, True)}\n .insertSub(i_comment_line[0][23]).pin(\"ASCX\").vForce(1.3 V)//{sav('ASCX', 1.3, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][24]).pin(\"ASDX,INT2\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_OFF2_C_04//{gav('V_OFF2_C[04]', 'ASDX', 'INT2', 0.1, 0.0001, True)}\n .insertSub(i_comment_line[0][25]).pin(\"ASCX\").vForce(1.5 V)//{sav('ASCX', 1.5, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][26]).pin(\"ASDX,INT2\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_OFF2_C_05//{gav('V_OFF2_C[05]', 'ASDX', 'INT2', 0.1, 0.0001, True)}\n .insertSub(i_comment_line[0][27]).pin(\"ASCX\").vForce(1.7 V)//{sav('ASCX', 1.7, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][28]).pin(\"ASDX,INT2\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_OFF2_C_06//{gav('V_OFF2_C[06]', 'ASDX', 'INT2', 0.1, 0.0001, True)}\n .insertSub(i_comment_line[0][29]).pin(\"ASCX\").relay(TA::ppmuRly_offALL)////{uav('ASCX', False)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n ARRAY_D ad_jsubresults_ASDX; ad_jsubresults_ASDX.resize(14); ad_jsubresults_ASDX.init(-9.9);\n ARRAY_D ad_jsubresults_INT2; ad_jsubresults_INT2.resize(14); ad_jsubresults_INT2.init(-9.9);\n \n ad_jsubresults_INT2 = rdi.id(\"dcid_0\").getMultiValue(\"INT2\");\n ad_jsubresults_ASDX = rdi.id(\"dcid_0\").getMultiValue(\"ASDX\");\n \n d_V_OFF1_C_00[curSite] = ad_jsubresults_INT2[0] - ad_jsubresults_ASDX[0];\n d_V_OFF1_C_01[curSite] = ad_jsubresults_INT2[1] - ad_jsubresults_ASDX[1];\n d_V_OFF1_C_02[curSite] = ad_jsubresults_INT2[2] - ad_jsubresults_ASDX[2];\n d_V_OFF1_C_03[curSite] = ad_jsubresults_INT2[3] - ad_jsubresults_ASDX[3];\n d_V_OFF1_C_04[curSite] = ad_jsubresults_INT2[4] - ad_jsubresults_ASDX[4];\n d_V_OFF1_C_05[curSite] = ad_jsubresults_INT2[5] - ad_jsubresults_ASDX[5];\n d_V_OFF1_C_06[curSite] = ad_jsubresults_INT2[6] - ad_jsubresults_ASDX[6];\n d_V_OFF2_C_00[curSite] = ad_jsubresults_ASDX[7] - ad_jsubresults_INT2[7];\n d_V_OFF2_C_01[curSite] = ad_jsubresults_ASDX[8] - ad_jsubresults_INT2[8];\n d_V_OFF2_C_02[curSite] = ad_jsubresults_ASDX[9] - ad_jsubresults_INT2[9];\n d_V_OFF2_C_03[curSite] = ad_jsubresults_ASDX[10] - ad_jsubresults_INT2[10];\n d_V_OFF2_C_04[curSite] = ad_jsubresults_ASDX[11] - ad_jsubresults_INT2[11];\n d_V_OFF2_C_05[curSite] = ad_jsubresults_ASDX[12] - ad_jsubresults_INT2[12];\n d_V_OFF2_C_06[curSite] = ad_jsubresults_ASDX[13] - ad_jsubresults_INT2[13];\n FuncPrint(\"V_OFF1_C_00\",d_V_OFF1_C_00[curSite]);\n FuncPrint(\"V_OFF1_C_01\",d_V_OFF1_C_01[curSite]);\n FuncPrint(\"V_OFF1_C_02\",d_V_OFF1_C_02[curSite]);\n FuncPrint(\"V_OFF1_C_03\",d_V_OFF1_C_03[curSite]);\n FuncPrint(\"V_OFF1_C_04\",d_V_OFF1_C_04[curSite]);\n FuncPrint(\"V_OFF1_C_05\",d_V_OFF1_C_05[curSite]);\n FuncPrint(\"V_OFF1_C_06\",d_V_OFF1_C_06[curSite]);\n FuncPrint(\"V_OFF2_C_00\",d_V_OFF2_C_00[curSite]);\n FuncPrint(\"V_OFF2_C_01\",d_V_OFF2_C_01[curSite]);\n FuncPrint(\"V_OFF2_C_02\",d_V_OFF2_C_02[curSite]);\n FuncPrint(\"V_OFF2_C_03\",d_V_OFF2_C_03[curSite]);\n FuncPrint(\"V_OFF2_C_04\",d_V_OFF2_C_04[curSite]);\n FuncPrint(\"V_OFF2_C_05\",d_V_OFF2_C_05[curSite]);\n FuncPrint(\"V_OFF2_C_06\",d_V_OFF2_C_06[curSite]);\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n\n ON_FIRST_INVOCATION_END();\n\n TestLog(\"V_OFF1_C_00\",d_V_OFF1_C_00[curSite]);\n TestLog(\"V_OFF1_C_01\",d_V_OFF1_C_01[curSite]);\n TestLog(\"V_OFF1_C_02\",d_V_OFF1_C_02[curSite]);\n TestLog(\"V_OFF1_C_03\",d_V_OFF1_C_03[curSite]);\n TestLog(\"V_OFF1_C_04\",d_V_OFF1_C_04[curSite]);\n TestLog(\"V_OFF1_C_05\",d_V_OFF1_C_05[curSite]);\n TestLog(\"V_OFF1_C_06\",d_V_OFF1_C_06[curSite]);\n TestLog(\"V_OFF2_C_00\",d_V_OFF2_C_00[curSite]);\n TestLog(\"V_OFF2_C_01\",d_V_OFF2_C_01[curSite]);\n TestLog(\"V_OFF2_C_02\",d_V_OFF2_C_02[curSite]);\n TestLog(\"V_OFF2_C_03\",d_V_OFF2_C_03[curSite]);\n TestLog(\"V_OFF2_C_04\",d_V_OFF2_C_04[curSite]);\n TestLog(\"V_OFF2_C_05\",d_V_OFF2_C_05[curSite]);\n TestLog(\"V_OFF2_C_06\",d_V_OFF2_C_06[curSite]);\n i_funcRes[curSite] = i_funcRes0[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T07_04_Testbuffer_Voltage_Char_V2\", T07_04_Testbuffer_Voltage_Char_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: Internal ground measure\n# VSS on CTB_P\n#############################################################################################################\ncmt('Version info: $Revision: 2 $ $Author: laj1mu23 $ $Date: 2024/03/25 20:27:19 GMT $')\n# Config Ana pin\nwac('EXT_MODE', 0xc00f) # Test page, TM_PIN\nwcb('tm_int2_en',0x1)\nwcb('tm_int2_sel',0x4) # TB1_INP\ndly(100e-6)\n# Config ATM addr & cfg\nwcb('tm_cfg' , 0x8) # TM_ADDR, VSS to CTB_P\nwcb('tm_addr', 0xd) # COM_TIO_PWR, Signal :TM_PWRBLOCK_EN\n# Measure\ndly(100e-6)\ncmt('The measurement needs to be done with an accuracy of +/- 1mV')\ngav('V_GND', 'INT2', v_range=0.1) # target value close to 0\nlog('V_GND')\n# Clean\nwac('TM_ADDR',0x0000) # Reset tm_addr, tm_cfg \nwac('TM_PIN',0x0000) # Reset tm__sel/en \n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T07_05_internal_gnd_measurement_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n static double V_GND[xNSitES];\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T07_05_internal_gnd_measurement_V2_PAT_id\");\n rdi.dc(\"T07_05_internal_gnd_measurement_V2DC_id0\").label(s_label_name)\n .insertSub(i_comment_line0[0]).pin(\"INT2\",TA::BADC).vMeas().average(128).measWait(1 ms) //V_GND\n .execute();\n RDI_END();\n ON_FIRST_INVOCATION_END();\n\n ARRAY_D JSUB_results_INT2;\n JSUB_results_INT2 = rdi.id(\"T07_05_internal_gnd_measurement_V2DC_id0\").getMultiValue(\"INT2\");\n V_GND[CURRENT_SITE_NUMBER()-1] = JSUB_results_INT2[0];\n\n int Func_result = rdi.id(\"T07_05_internal_gnd_measurement_V2_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n FuncPrint(\"V_GND\", V_GND[CURRENT_SITE_NUMBER()-1]);\n\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"V_GND\", V_GND[CURRENT_SITE_NUMBER()-1]);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T07_05_internal_gnd_measurement_V2\", T07_05_internal_gnd_measurement_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 2 $ $Author: laj1mu23 $ $Date: 2024/03/25 20:22:06 GMT $')\nwac('EXT_MODE', 0xc00f) # Switch to the TEST register page\nwac('TM_CONF', 0x0003) # tm_se_meas=0 tm_bus_inv=0 tm_buf_pwrup=3 (tbuf_tb1_tb2_on)\n # bus_inv. because the power_ana_test_multiplexor_2 provides VSS_A/VDDA\nwac('TM_PIN', 0x0055) # tm_asdx_sel=2 (BUF2_OUT) tm_asdx_en=1 tm_int2_sel=2 (BUF1_OUT) tm_int2_en=1\nwac('TM_ADDR', 0x0c0d) # tm_cfg=c (COM_TB2= VDDA, COM_TB1= VDDA) tm_addr=d (COM_TIO_PWR;\n # enable the power_ana_test_multiplexor_2 for power supplies)\ndly(100e-6)\nsac('INT2', 0.0, i_range=-100e-6, sim_ignore=True)\ndly(100e-6)\ngav('V_BUFFER1_ZERO', 'INT2')\nsac('INT2', -20e-6, i_range=-100e-6, sim_ignore=True)\ndly(100e-6)\ngav('V_BUFFER1_20microA', 'INT2')\nuac('INT2')\ncalc(\"V_BUFFER1\", \"V_BUFFER1_ZERO\", \"-\", \"V_BUFFER1_20microA\")\ncalc(\"R_BUFFER1\", \"V_BUFFER1\", \"/\", \"20e-6\")\nlog(\"R_BUFFER1\")\ndly(100e-6)\nsac('ASDX', 0.0, i_range=-100e-6, sim_ignore=True)\ndly(100e-6)\ngav('V_BUFFER2_ZERO', 'ASDX')\nsac('ASDX', -20e-6, i_range=-100e-6, sim_ignore=True)\ndly(100e-6)\ngav('V_BUFFER2_20microA', 'ASDX')\nuac('ASDX')\ncalc(\"V_BUFFER2\", \"V_BUFFER2_ZERO\", \"-\", \"V_BUFFER2_20microA\")\ncalc(\"R_BUFFER2\", \"V_BUFFER2\", \"/\", \"20e-6\")\nlog(\"R_BUFFER2\")\n# EXT_MODE selects the TEST register page already\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\n", "output": "/*****************************************************\n * T07_06_Testbuffer_Output_Impedance_Char_V2, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n * JSH5SGH: fix some bugs.\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T07_06_Testbuffer_Output_Impedance_Char_V2: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static double d_V_BUFFER1_20microA[xNSitES];\n static double d_V_BUFFER1_ZERO[xNSitES];\n static double d_V_BUFFER2_20microA[xNSitES];\n static double d_V_BUFFER2_ZERO[xNSitES];\n static int i_funcRes0[xNSitES];\n static double V_BUFFER1[xNSitES], R_BUFFER1[xNSitES];\n static double V_BUFFER2[xNSitES], R_BUFFER2[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(d_V_BUFFER1_20microA, 9.9, xNSitES);\n Func_Init_Var(d_V_BUFFER1_ZERO, 9.9, xNSitES);\n Func_Init_Var(d_V_BUFFER2_20microA, 9.9, xNSitES);\n Func_Init_Var(d_V_BUFFER2_ZERO, 9.9, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T07_06_Testbuffer_Output_Impedance_Char}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 1] @ avcline 788: {sac('INT2', 0, -0.0001, 2, 0, False, True)}\n valid comment[ 2] @ avcline 797: {gav('V_BUFFER1_ZERO', 'INT2', '', 2, 0.0001, True)}\n valid comment[ 2] @ avcline 797: {sac('INT2', -2e-05, -0.0001, 2, 0, False, True)}\n valid comment[ 3] @ avcline 807: {gav('V_BUFFER1_20microA', 'INT2', '', 2, 0.0001, True)}\n valid comment[ 3] @ avcline 807: {uac('INT2', False)}\n valid comment[ 3] @ avcline 807: {calc('V_BUFFER1', 'V_BUFFER1_ZERO', '-', 'V_BUFFER1_20microA')}\n valid comment[ 3] @ avcline 807: {calc('R_BUFFER1', 'V_BUFFER1', '/', '20e-6')}\n valid comment[ 3] @ avcline 807: {log('R_BUFFER1', '', '', 0, 0)}\n valid comment[ 4] @ avcline 817: {sac('ASDX', 0, -0.0001, 2, 0, False, True)}\n valid comment[ 5] @ avcline 826: {gav('V_BUFFER2_ZERO', 'ASDX', '', 2, 0.0001, True)}\n valid comment[ 5] @ avcline 826: {sac('ASDX', -2e-05, -0.0001, 2, 0, False, True)}\n valid comment[ 6] @ avcline 836: {gav('V_BUFFER2_20microA', 'ASDX', '', 2, 0.0001, True)}\n valid comment[ 6] @ avcline 836: {uac('ASDX', False)}\n valid comment[ 6] @ avcline 836: {calc('V_BUFFER2', 'V_BUFFER2_ZERO', '-', 'V_BUFFER2_20microA')}\n valid comment[ 6] @ avcline 836: {calc('R_BUFFER2', 'V_BUFFER2', '/', '20e-6')}\n valid comment[ 6] @ avcline 836: {log('R_BUFFER2', '', '', 0, 0)}\n valid comment[ 7] @ avcline 1413: {Test End: T07_06_Testbuffer_Output_Impedance_Char}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][1]).pin(\"INT2\").iForce(0 uA).iRange(100 uA)//{sac('INT2', 0, -0.0001, 2, 0, False, True)}\n .insertSub(i_comment_line[0][2]).pin(\"INT2\").iForce(0 uA).vMeas().valueMode(TA::BADC).average(128).measWait(1 ms)//V_BUFFER1_ZERO//{gav('V_BUFFER1_ZERO', 'INT2', '', 2, 0.0001, True)}\n// .insertSub(i_comment_line[0][2]).pin(\"INT2\", TA::BADC).iForce(0 uA).vMeas().average(32).measWait(1 ms)//V_BUFFER1_ZERO//{gav('V_BUFFER1_ZERO', 'INT2', '', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][2]).pin(\"INT2\").iForce(-20 uA).iRange(100 uA)//{sac('INT2', -2e-05, -0.0001, 2, 0, False, True)}\n .insertSub(i_comment_line[0][3]).pin(\"INT2\").iForce(-20 uA).valueMode(TA::BADC).vMeas().average(128).measWait(1 ms)//V_BUFFER1_20microA//{gav('V_BUFFER1_20microA', 'INT2', '', 2, 0.0001, True)}\n// .insertSub(i_comment_line[0][3]).pin(\"INT2\", TA::BADC).iForce(-20 uA).vMeas().average(32).measWait(1 ms)//V_BUFFER1_20microA//{gav('V_BUFFER1_20microA', 'INT2', '', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][3]).pin(\"INT2\").relay(TA::ppmuRly_onAC_offDCPPMU)////{uac('INT2', False)}\n\n .insertSub(i_comment_line[0][4]).pin(\"ASDX\").iForce(0 uA).iRange(100 uA)//{sac('ASDX', 0, -0.0001, 2, 0, False, True)}\n .insertSub(i_comment_line[0][5]).pin(\"ASDX\").iForce(0 uA).vMeas().valueMode(TA::BADC).average(128).measWait(1 ms)//V_BUFFER2_ZERO//{gav('V_BUFFER2_ZERO', 'ASDX', '', 2, 0.0001, True)}\n// .insertSub(i_comment_line[0][5]).pin(\"ASDX\", TA::BADC).iForce(0 uA).vMeas().average(32).measWait(1 ms)//V_BUFFER2_ZERO//{gav('V_BUFFER2_ZERO', 'ASDX', '', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][5]).pin(\"ASDX\").iForce(-20 uA).iRange(100 uA)//{sac('ASDX', -2e-05, -0.0001, 2, 0, False, True)}\n .insertSub(i_comment_line[0][6]).pin(\"ASDX\").iForce(-20 uA).vMeas().valueMode(TA::BADC).average(128).measWait(1 ms)//V_BUFFER2_20microA//{gav('V_BUFFER2_20microA', 'ASDX', '', 2, 0.0001, True)}\n// .insertSub(i_comment_line[0][6]).pin(\"ASDX\", TA::BADC).iForce(-20 uA).vMeas().average(32).measWait(1 ms)//V_BUFFER2_20microA//{gav('V_BUFFER2_20microA', 'ASDX', '', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][6]).pin(\"ASDX\").relay(TA::ppmuRly_onAC_offDCPPMU)////{uac('ASDX', False)}\n .execute();\n RDI_END();\n\n// RDI_BEGIN(mode);\n// rdi.burstId(\"burst_id0\");\n// rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n// .insertSub(i_comment_line[0][1]).pin(\"OSDO\").iForce(0 uA).iRange(100 uA)//{sac('OSDO', 0, -0.0001, 2, 0, False, True)}\n// .insertSub(i_comment_line[0][2]).pin(\"OSDO\").iForce(0 uA).vMeas().valueMode(TA::BADC).average(512).measWait(1 ms)//V_BUFFER1_ZERO//{gav('V_BUFFER1_ZERO', 'OSDO', '', 2, 0.0001, True)}\n// .insertSub(i_comment_line[0][2]).pin(\"OSDO\").iForce(-20 uA).iRange(100 uA)//{sac('OSDO', -2e-05, -0.0001, 2, 0, False, True)}\n// .insertSub(i_comment_line[0][3]).pin(\"OSDO\").iForce(-20 uA).vMeas().valueMode(TA::BADC).average(512).measWait(1 ms)//V_BUFFER1_20microA//{gav('V_BUFFER1_20microA', 'OSDO', '', 2, 0.0001, True)}\n// .insertSub(i_comment_line[0][3]).pin(\"OSDO\").relay(TA::ppmuRly_onAC_offDCPPMU,TA::ppmuRly_offALL)////{uac('OSDO', False)}\n// .insertSub(i_comment_line[0][4]).pin(\"ASDX\").iForce(0 uA).iRange(100 uA)//{sac('ASDX', 0, -0.0001, 2, 0, False, True)}\n// .insertSub(i_comment_line[0][5]).pin(\"ASDX\").iForce(0 uA).vMeas().valueMode(TA::BADC).average(512).measWait(1 ms)//V_BUFFER2_ZERO//{gav('V_BUFFER2_ZERO', 'ASDX', '', 2, 0.0001, True)}\n// .insertSub(i_comment_line[0][5]).pin(\"ASDX\").iForce(-20 uA).iRange(100 uA)//{sac('ASDX', -2e-05, -0.0001, 2, 0, False, True)}\n// .insertSub(i_comment_line[0][6]).pin(\"ASDX\").iForce(-20 uA).vMeas().valueMode(TA::BADC).average(512).measWait(1 ms)//V_BUFFER2_20microA//{gav('V_BUFFER2_20microA', 'ASDX', '', 2, 0.0001, True)}\n//// .insertSub(i_comment_line[0][6]).pin(\"ASDX\").relay(TA::ppmuRly_onAC_offDCPPMU)////{uac('ASDX', False)}\n// .execute();\n// RDI_END();\n\n\n\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n ARRAY_D ad_jsubresults_ASDX; ad_jsubresults_ASDX.resize(2); ad_jsubresults_ASDX.init(-9.9);\n ARRAY_D ad_jsubresults_INT2; ad_jsubresults_INT2.resize(2); ad_jsubresults_INT2.init(-9.9);\n ad_jsubresults_ASDX = rdi.id(\"dcid_0\").getMultiValue(\"ASDX\");\n \n ad_jsubresults_INT2 = rdi.id(\"dcid_0\").getMultiValue(\"INT2\");\n \n d_V_BUFFER1_ZERO[curSite] = ad_jsubresults_INT2[0];\n FuncPrint(\"V_BUFFER1_ZERO\",d_V_BUFFER1_ZERO[curSite]);\n d_V_BUFFER1_20microA[curSite] = ad_jsubresults_INT2[1];\n FuncPrint(\"V_BUFFER1_20microA\",d_V_BUFFER1_20microA[curSite]);\n d_V_BUFFER2_ZERO[curSite] = ad_jsubresults_ASDX[0];\n FuncPrint(\"V_BUFFER2_ZERO\",d_V_BUFFER2_ZERO[curSite]);\n d_V_BUFFER2_20microA[curSite] = ad_jsubresults_ASDX[1];\n FuncPrint(\"V_BUFFER2_20microA\",d_V_BUFFER2_20microA[curSite]);\n\n V_BUFFER1[curSite] = d_V_BUFFER1_ZERO[curSite] - d_V_BUFFER1_20microA[curSite];\n FuncPrint(\"V_BUFFER1\",V_BUFFER1[curSite]);\n R_BUFFER1[curSite] = V_BUFFER1[curSite] / 20e-6;\n FuncPrint(\"R_BUFFER1\",R_BUFFER1[curSite]);\n\n V_BUFFER2[curSite] = d_V_BUFFER2_ZERO[curSite] - d_V_BUFFER2_20microA[curSite];\n FuncPrint(\"V_BUFFER2\",V_BUFFER2[curSite]);\n R_BUFFER2[curSite] = V_BUFFER2[curSite] / 20e-6;\n FuncPrint(\"R_BUFFER2\",R_BUFFER2[curSite]);\n\n FOR_EACH_SITE_END();\n\n\n ON_FIRST_INVOCATION_END();\n\n TestLog(\"R_BUFFER1\",R_BUFFER1[curSite]);\n TestLog(\"R_BUFFER2\",R_BUFFER2[curSite]);\n i_funcRes[curSite] = i_funcRes0[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T07_06_Testbuffer_Output_Impedance_Char_V2\", T07_06_Testbuffer_Output_Impedance_Char_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "######################################################################################################################\n# description: Write TB offset measurements to dark OTP\n# Step1: Calcualtion of V_OFF1/2 measurement into integer value\n# Step2: Program value in dark OTP regID 0xDA\n# - Bits 0..5 used to store the TB1 offset (-32..31)\n# - Bits 8..12 used to store the TB2 offset (-32..31)\n######################################################################################################################\ncmt('Version info: $Revision: 1 $ $Author: hmf1rt $ $Date: 2024/03/13 13:36:52 GMT $')\n# Convert TB offset measurements to integer values\ncmt('Get result parameter V_OFF1_ECOFF from test item T07.02 (unit V) and convert to unit mV')\ncalc('V_OFF1_MV', 'V_OFF1_ECOFF', '*', 1000) # Get V_OFF1_ECOFF from test item T07.02\ncalc('NS_OFF1', 'V_OFF1_MV', 'round') # Round TB1 offset in (mV) to nearest integer\ncmt('This test item is a functional fail if NS_OFF1 > 31 or NS_OFF1 < -32')\ncalc('NU_OFF1', 'NS_OFF1', 'csu', 6) # Convert 6-bit signed to unsigend\ndly(296e-9)\ncmt('Get result parameter V_OFF2_ECOFF from test item T07.02 (unit V) and convert to unit mV')\ncalc('V_OFF2_MV', 'V_OFF2_ECOFF', '*', 1000) # Get V_OFF2_ECOFF from test item T07.02\ncalc('NS_OFF2', 'V_OFF2_MV', 'round') # Round TB2 offset in (mV) to nearest integer\ncmt('This test item is a functional fail if NS_OFF2 > 31 or NS_OFF2 < -32')\ncalc('NU_OFF2', 'NS_OFF2', 'csu', 6) # Convert 6-bit signed to unsigend\ndly(296e-9)\ncalc('NU_OFF2_LS', 'NU_OFF2', '<<', 8) # Left shift NU_OFF2 to bit 8\ncalc('NU_OFF_OTP', 'NU_OFF2_LS', '+', 'NU_OFF1')# Calc OTP program data\n# Program data to OTP\nwac('EXT_MODE', 0xc00d) # Switch to PMU register page\nwcb('nvmotp_power_en',0x1) # Request OTP power\ndly(300e-6) \nwac('EXT_MODE', 0xc00f) # Switch to OTPCTRL register page\nwac('OTP_PROG_EN', 0x0002) # Enable OTP program\nwcb('vddp_sw', 0x1) # Connect VDDP to VDD\nsav('VDD', 3.6, v_range=4.0, i_comp=40e-3)\ndly(1e-3)\nwri('OTP_DATA', 'NU_OFF_OTP') # Write measurement result to OTP data register\nrac('OTP_STATUS', 0x0001) # Check OTP ready\nwr('OTP_CMD', 0x0005) # Trigger OTP data program\ndly(200e-6) # OTP spec, pgm speed 10us per bit\nwac('OTP_DATA',0xda) # Set regID for dark OTP \nrac('OTP_STATUS', 0x0001) # Check OTP ready\nwr('OTP_CMD', 0x0006) # Trigger OTP reg_id program\ndly(200e-6) \nrac('OTP_STATUS', 0x0001) # Check OTP ready\nsav('VDD', 1.8, v_range=4.0, i_comp=40e-3)\ndly(1e-3)\nwac('OTP_PROG_EN', 0x0000) # Disable OTP program\nwcb('vddp_sw', 0x0) # Connect VDDP to VDDD_DC\nwac('OTP_DATA', 0x0000) # Reset OTP data register\n# Read data from OTP \nwac('BOOT_RANGE', 0xdada) # Set register ID for dark OTP load\nrac('BOOT_STATUS', 0x0001) # Check boot controller ready and error bits\nwr('BOOT_CMD', 0x0001) # Trigger OTP load\ndly(1.2e-3)\nras('NU_OFF_OTP_RD', 'BOOT_LAST_DATA') # Read and save OTP data\ncmt('This test item is a functional fail if NU_OFF_OTP_RD != NU_OFF_OTP')\n# Clean-up \nwac('BOOT_RANGE', 0x0000)\nwac('EXT_MODE', 0xc00d) # Switch to PMU register page\nwcb('nvmotp_power_en',0x0) # Disable OTP power\ndly(100e-6)\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T07_10_testbuffer_offset_dark_OTP_write_V1: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n INT split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &split_pat_flag);\n vector s_splited_pat_name;\n const int split_count = 5; // Alarm:: split_count need manual confirm.\n s_splited_pat_name.resize(split_count);\n vector i_comment_line[split_count];\n static int NU_OFF_OTP_RD[xNSitES];\n static double V_OFF1_MV[xNSitES], V_OFF2_MV[xNSitES];\n static int NS_OFF1[xNSitES], NU_OFF1[xNSitES], NS_OFF2[xNSitES], NU_OFF2[xNSitES], NU_OFF2_LS[xNSitES], NU_OFF_OTP[xNSitES];\n ARRAY_LL NU_OFF_OTP_rtv(xNSitES);\n\n const int Wri_Bit_Length = 33;\n const int Wri_Bit_Position = 31;\n // Auto_Code_Variable_define\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n GET_TESTSUITE_NAME(test_name);\n if (split_pat_flag)\n {\n \t split_pattern(s_label_name,\"wri\",\"sav\",split_pat_flag,s_splited_pat_name);\n }\n else\n {\n for (int i = 0; i_sel/en \n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T07_15_r_gnd_measurement: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n static double V_GND[xNSitES];\n static double V_10ma[xNSitES],V_40ma[xNSitES];\n static double V_0ma[xNSitES],V_delta[xNSitES],R_gnd[xNSitES];\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n rdi.dc().pin(\"INT1_AVI64\").vMeasRange(3 V).connectState(TA::HIZ).execute();\n rdi.util().pin(\"K8\").setOn().execute();\n rdi.util().pin(\"K4\").setOff().execute();\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T07_15_r_gnd_measurement_PAT_id\");\n rdi.dc(\"T07_15_r_gnd_measurementDC_id0\").label(s_label_name)\n .insertSub(i_comment_line0[0]).pin(\"INT1_AVI64\").vMeas().average(256).measWait(1 ms) //V_GND\n .insertSub(i_comment_line0[1]).pin(\"INT1\").iForce(10 mA)\n .insertSub(i_comment_line0[2]).pin(\"INT1_AVI64\").vMeas().average(256).measWait(1 ms) //V_10ma\n .insertSub(i_comment_line0[2]).pin(\"INT1\").iForce(40 mA)\n .insertSub(i_comment_line0[2]).wait(1 ms)\n .insertSub(i_comment_line0[2]).pin(\"INT1_AVI64\").vMeas().average(256).measWait(1 ms) //V_40ma\n .insertSub(i_comment_line0[2]).pin(\"INT1\").relay(TA::ppmuRly_offALL)\n .insertSub(i_comment_line0[3]).pin(\"INT1_AVI64\").vMeas().average(256).measWait(1 ms) //V_0ma\n// .insertSub(i_comment_line0[3]).pin(\"INT2\").relay(TA::ppmuRly_offALL)\n .execute();\n RDI_END();\n rdi.util().pin(\"K8\").setOff().execute();\n ON_FIRST_INVOCATION_END();\n ARRAY_D JSUB_results_INT2;\n JSUB_results_INT2 = rdi.id(\"T07_15_r_gnd_measurementDC_id0\").getMultiValue(\"INT1_AVI64\");\n V_GND[CURRENT_SITE_NUMBER()-1] = JSUB_results_INT2[0];\n V_10ma[CURRENT_SITE_NUMBER()-1] = JSUB_results_INT2[1];\n V_40ma[CURRENT_SITE_NUMBER()-1] = JSUB_results_INT2[2];\n V_0ma[CURRENT_SITE_NUMBER()-1] = JSUB_results_INT2[3];\n\n V_delta[CURRENT_SITE_NUMBER()-1] = V_40ma[CURRENT_SITE_NUMBER()-1] - V_10ma[CURRENT_SITE_NUMBER()-1];\n R_gnd[CURRENT_SITE_NUMBER()-1] = V_delta[CURRENT_SITE_NUMBER()-1] / (40e-3 - 10e-3);\n\n // Auto_Code_Retrieve_Data\n \n int Func_result = rdi.id(\"T07_15_r_gnd_measurement_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n FuncPrint(\"FUNCTIONAL_TEST\", Func_result);\n FuncPrint(\"V_GND\", V_GND[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"V_10ma\", V_10ma[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"V_40ma\", V_40ma[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"V_0ma\", V_0ma[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"V_delta\", V_delta[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"R_gnd\", R_gnd[CURRENT_SITE_NUMBER()-1]);\n\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"V_GND\", V_GND[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"V_10ma\", V_10ma[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"V_40ma\", V_40ma[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"V_0ma\", V_0ma[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"V_delta\", V_delta[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"R_gnd\", R_gnd[CURRENT_SITE_NUMBER()-1]);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T07_15_r_gnd_measurement\", T07_15_r_gnd_measurement);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 1 $ $Author: hmf1rt $ $Date: 2024/03/13 13:36:52 GMT $')\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nrac('STATUS_PMOD0', 0x0003, 0x0003) # Check ACC AFE PMU status\nwr('CMD', 0xdeaf) # Trigger soft reset\ndly(3e-3)\nrac('CHIP_ID', 0x0000, 0x0000) # Dummy read to init SPI protocol\ndly(10e-6)\nrac('CHIP_ID', 0x00af, 0x00ff) # Read chip ID (proof for the reset)\nrac('ACC_CONF', 0x0028) # Check reset of ACC config regiser (proof for the reset)\n\n", "output": "/*****************************************************\n * T08_01_soft_reset, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T08_01_soft_reset: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n static double v_VDDIO, v_VDD;\n\n static int i_funcRes0[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T08_01_soft_reset}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 1] @ avcline 750: {Test End: T08_01_soft_reset}\n */\n v_VDDIO = Primary.getLevelSpec().getSpecValue(\"VDDIO\");\n v_VDD = Primary.getLevelSpec().getSpecValue(\"VDD\");\n\n rdi.dc().pin(\"VDDIO\").vForce(v_VDDIO V).execute();\n rdi.dc().pin(\"VDD\").vForce(v_VDD V).execute();\n// Primary.getLevelSpec().change(\"VDDIO\",1.8);\n// FLUSH(TM::APRM);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.func().label(s_splited_pat_name[0]).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n FuncPrint(\"i_funcRes0\", i_funcRes0[curSite]);\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n// rdi.dc().pin(\"VDDIO\").vForce(1.8 V).execute();\n// Primary.getLevelSpec().change(\"VDDIO\",1.8);\n// FLUSH(TM::APRM);\n\n ON_FIRST_INVOCATION_END();\n\n i_funcRes[curSite] = i_funcRes0[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T08_01_soft_reset\", T08_01_soft_reset);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description:\n# - soft reset; delay of 200us; recovery check with ras() operations of reg CHIP_ID; store the result to an array\n# - recovery, when 0x00AF read back from the register (read back zero otherwise)\n# - the lowest entry greater than 0x00AF marks the first entry when recovered from reset (loop index is added)\n# - for ras(): (70+71)*0,5 bit cycles before/after the transfer\n# (see pre_delay, post_delay in setups/spi_fast.e)\n# - for ras() transfer: 8bit addr, 8bit data[4], 4x0,5 breaks (iot_delay=1) => 5x8+4x0,5=42\n# (see sot_delay, eot_delay, iot_delay in setups/spi_std.e)\n# - 42+70,5=112,5, spi_fast 100ns per clock cycle\n# - The same procedure is applied for the ACC mode (after T01_10_set_device_config_STC_ACC)\n# and for the suspend mode (after reset)\n#############################################################################################################\ncmt('Version info: $Revision: bai430aa_rel/1 $ $Author: hmf1rt $ $Date: 2024/07/18 13:24:08 GMT $')\ncmt('This test must run with 10MHz')\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nrac('STATUS_PMOD0', 0x0003, 0x0003) # Check ACC AFE PMU status\nwr('CMD', 0xdeaf) # Trigger soft reset\ndly(200e-6)\t # 200us to avoid any SPI read/simulation issues after reset\nfor n in range(0, 170, 1):\n ras('WATERMARK', 'CHIP_ID') # 112,5 cycles\n calc('WATERMARK_CHIPID_ONLY', 'WATERMARK', \"&\", 0x00FF) #remove asic version ifno \n calc('WATERMARK_IDX[{:02d}]'.format(n), 'WATERMARK_CHIPID_ONLY', \"+\", n)\noti('N_RECOVERY_RST_ACC', 'WATERMARK_IDX', 0x00AF, criteria='gt') # calculate the first index when back from reset\ncalc('T_RECOVERY',112.5e-7,'*','N_RECOVERY_RST_ACC')\ncalc('T_RECOVERY_ACC_C',200e-6,'+','T_RECOVERY')\nlog('T_RECOVERY_ACC_C')\n######## same again for suspend mode\nwr('CMD', 0xBB3A) # 1st command for enabling the extended mode\nwr('CMD', 0x2C62) # 2nd command for enabling the extended mode\nwr('CMD', 0xA576) # 1st command for enabling the super privilege mode\nwr('CMD', 0x34D6) # 2nd command for enabling the super privilege mode\ndly(10e-6)\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nrac('STATUS_PMOD0', 0x0000, 0x0003) # Check ACC AFE PMU status (now for suspend)\nwr('CMD', 0xdeaf) # Trigger soft reset\ndly(200e-6)\t # 200us to avoid any SPI read/simulation issues after reset\nfor n in range(0, 170, 1):\n ras('WATERMARK', 'CHIP_ID')\n calc('WATERMARK_CHIPID_ONLY', 'WATERMARK', \"&\", 0x00FF) #remove asic version ifno \n calc('WATERMARK_IDX_SUSP[{:02d}]'.format(n), 'WATERMARK_CHIPID_ONLY', \"+\", n)\noti('N_RECOVERY_RST_SUSP', 'WATERMARK_IDX_SUSP', 0x00AF, criteria='gt') # calculate the first index when back from reset\ncalc('T_RECOVERY',112.5e-7,'*','N_RECOVERY_RST_SUSP')\ncalc('T_RECOVERY_SUSP_C',200e-6,'+','T_RECOVERY')\nlog('T_RECOVERY_SUSP_C')\n", "output": "/*****************************************************\n * T08_02_Soft_Reset_Recovery_Time_R1, description file version Notfound, avc file version Notfound\n * First Editor : jsh5sgh\n * Code generated with autocoding tool V2.9.1, in TOI2 standard way by module write_standard\n * Change History:\n * JSH5SGH V5: description update\n * JSH5SGH R1: version update.\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T08_02_Soft_Reset_Recovery_Time_R1: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 4;\n vector i_comment_line[i_split_count];\n\n// static int WATERMARK[xNSitES][170];\n ARRAY_I aI_Captured_0, aI_Captured_2;\n static int WATERMARK[xNSitES][170], WATERMARK_CHIPID_ONLY[xNSitES][170], WATERMARK_IDX[xNSitES][170], WATERMARK_IDX_SUSP[xNSitES][170];\n static int N_RECOVERY_RST_ACC[xNSitES], N_RECOVERY_RST_SUSP[xNSitES];\n static double T_RECOVERY[xNSitES], T_RECOVERY_ACC_C[xNSitES], T_RECOVERY_SUSP_C[xNSitES];\n static int i_funcRes0[xNSitES], i_funcRes1[xNSitES], i_funcRes2[xNSitES], i_funcRes3[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(WATERMARK[170], 9, xNSitES);\n Func_Init_Var(WATERMARK[170], 9, xNSitES);\n \n //!\"CTmsg: cut pattern to 4 parts @ oriAVCvecline [17516, 18132, 35302]\n //!\"CTmsg: cut pattern to 4 parts @ binarypatline [17506, 18122, 35292]\n if (i_split_pat_flag)\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n }\n else\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n for(int i=0; i }\n valid comment[ 0] @ avcline 10: {cmt: This test must run with 10MHz}\n valid comment[ 1] @ avcline 346: {ras('WATERMARK', 'CHIP_ID')}\n valid comment[ 2] @ avcline 447: {calc('WATERMARK_CHIPID_ONLY', 'WATERMARK', '&', '255')}\n valid comment[ 2] @ avcline 447: {calc('WATERMARK_IDX[00]', 'WATERMARK_CHIPID_ONLY', '+', '0')}\n valid comment[ 2] @ avcline 447: {ras('WATERMARK', 'CHIP_ID')}\n valid comment[ 3] @ avcline 548: {calc('WATERMARK_CHIPID_ONLY', 'WATERMARK', '&', '255')}\n valid comment[ 3] @ avcline 548: {calc('WATERMARK_IDX[01]', 'WATERMARK_CHIPID_ONLY', '+', '1')}\n ...\n valid comment[170] @ avcline 17415: {ras('WATERMARK', 'CHIP_ID')}\n valid comment[171] @ avcline 17516: {calc('WATERMARK_CHIPID_ONLY', 'WATERMARK', '&', '255')}\n valid comment[171] @ avcline 17516: {calc('WATERMARK_IDX[169]', 'WATERMARK_CHIPID_ONLY', '+', '169')}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.digCap(\"digcapid_0\").label(s_splited_pat_name[0]).pin(\"SDO\").capMode(TA::SER).bitPerWord(16).samples(170*16).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n aI_Captured_0 = rdi.id(\"digcapid_0\").getVector(\"SDO\");\n for (int i=0; i < 170; i++) \n\t\t\t {\n\t\t\t\t aI_Captured_0[i+0] = Switch_High_Low_Bits_16Bits(aI_Captured_0[i+0]);\n\t\t\t\t WATERMARK[curSite][i] = aI_Captured_0[i+0];\n\t\t\t\t FuncPrint(\"WATERMARK\" ,WATERMARK[curSite][i]);\n\n\t\t\t\t WATERMARK_CHIPID_ONLY[curSite][i] = WATERMARK[curSite][i] & 0xFF;\n\t\t\t\t FuncPrint(\"WATERMARK_CHIPID_ONLY\" ,WATERMARK_CHIPID_ONLY[curSite][i]);\n\n\t\t\t\t WATERMARK_IDX[curSite][i] = WATERMARK_CHIPID_ONLY[curSite][i] + i;\n\t\t\t\t FuncPrint(\"WATERMARK_IDX\" ,WATERMARK_IDX[curSite][i]);\n\t\t\t }\n\n N_RECOVERY_RST_ACC[curSite] = i_Func_Optimal_Trim_Val(WATERMARK_IDX[curSite], 0xAF, 170); //todo criteria='gt'\n FuncPrint(\"N_RECOVERY_RST_ACC\" ,N_RECOVERY_RST_ACC[curSite]);\n\n T_RECOVERY[curSite] = 112.5e-7 * N_RECOVERY_RST_ACC[curSite];\n FuncPrint(\"T_RECOVERY\" ,T_RECOVERY[curSite]);\n\n T_RECOVERY_ACC_C[curSite] = 200e-6 + T_RECOVERY[curSite];\n FuncPrint(\"T_RECOVERY_ACC_C\" ,T_RECOVERY_ACC_C[curSite]);\n\n FOR_EACH_SITE_END();\n\n\n /* Ori key coments in subpat1 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 17516: {oti('N_RECOVERY_RST_ACC', 'WATERMARK_IDX', '175', 'gt')}\n valid comment[ 0] @ avcline 17516: {calc('T_RECOVERY', '0.00001125', '*', 'N_RECOVERY_RST_ACC')}\n valid comment[ 0] @ avcline 17516: {calc('T_RECOVERY_ACC_C', '0.0002', '+', 'T_RECOVERY')}\n valid comment[ 0] @ avcline 17516: {log('T_RECOVERY_ACC_C', '', '', 0, 0)}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id1\");\n rdi.func().label(s_splited_pat_name[1]).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes1[curSite] = rdi.id(\"burst_id1\").getBurstPassFail();\n FuncPrint(\"i_funcRes1\", i_funcRes1[curSite]);\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n\n /* Ori key coments in subpat2 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 18132: {ras('WATERMARK', 'CHIP_ID')}\n valid comment[ 1] @ avcline 18233: {calc('WATERMARK_CHIPID_ONLY', 'WATERMARK', '&', '255')}\n valid comment[ 1] @ avcline 18233: {calc('WATERMARK_IDX_SUSP[00]', 'WATERMARK_CHIPID_ONLY', '+', '0')}\n valid comment[ 1] @ avcline 18233: {ras('WATERMARK', 'CHIP_ID')}\n valid comment[ 2] @ avcline 18334: {calc('WATERMARK_CHIPID_ONLY', 'WATERMARK', '&', '255')}\n valid comment[ 2] @ avcline 18334: {calc('WATERMARK_IDX_SUSP[01]', 'WATERMARK_CHIPID_ONLY', '+', '1')}\n ...\n valid comment[169] @ avcline 35201: {ras('WATERMARK', 'CHIP_ID')}\n valid comment[170] @ avcline 35302: {calc('WATERMARK_CHIPID_ONLY', 'WATERMARK', '&', '255')}\n valid comment[170] @ avcline 35302: {calc('WATERMARK_IDX_SUSP[169]', 'WATERMARK_CHIPID_ONLY', '+', '169')}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id2\");\n rdi.digCap(\"digcapid_2\").label(s_splited_pat_name[2]).pin(\"SDO\").capMode(TA::SER).bitPerWord(16).samples(170*16).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes2[curSite] = rdi.id(\"burst_id2\").getBurstPassFail();\n aI_Captured_2 = rdi.id(\"digcapid_2\").getVector(\"SDO\");\n for (int i=0; i < 170; i++) \n\t\t\t {\n \t aI_Captured_2[i+0] = Switch_High_Low_Bits_16Bits(aI_Captured_2[i+0]);\n\t\t\t\t WATERMARK[curSite][i] = aI_Captured_2[i+0];\n\t\t\t\t FuncPrint(\"WATERMARK\" ,WATERMARK[curSite][i]);\n\n\t\t\t\t WATERMARK_CHIPID_ONLY[curSite][i] = WATERMARK[curSite][i] & 0xFF;\n\t\t\t\t FuncPrint(\"WATERMARK_CHIPID_ONLY\" ,WATERMARK_CHIPID_ONLY[curSite][i]);\n\n\t\t\t\t WATERMARK_IDX_SUSP[curSite][i] = WATERMARK_CHIPID_ONLY[curSite][i] + i;\n\t\t\t\t FuncPrint(\"WATERMARK_IDX\" ,WATERMARK_IDX_SUSP[curSite][i]);\n\t\t\t }\n\n N_RECOVERY_RST_SUSP[curSite] = i_Func_Optimal_Trim_Val(WATERMARK_IDX_SUSP[curSite], 0xAF, 170); //todo criteria='gt'\n FuncPrint(\"N_RECOVERY_RST_SUSP\" ,N_RECOVERY_RST_SUSP[curSite]);\n\n T_RECOVERY[curSite] = 112.5e-7 * N_RECOVERY_RST_SUSP[curSite];\n FuncPrint(\"T_RECOVERY\" ,T_RECOVERY[curSite]);\n\n T_RECOVERY_SUSP_C[curSite] = 200e-6 + T_RECOVERY[curSite];\n FuncPrint(\"T_RECOVERY_SUSP_C\" ,T_RECOVERY_SUSP_C[curSite]);\n\n FOR_EACH_SITE_END();\n\n\n\n /* Ori key coments in subpat3 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 35302: {oti('N_RECOVERY_RST_SUSP', 'WATERMARK_IDX_SUSP', '175', 'gt')}\n valid comment[ 0] @ avcline 35302: {calc('T_RECOVERY', '0.00001125', '*', 'N_RECOVERY_RST_SUSP')}\n valid comment[ 0] @ avcline 35302: {calc('T_RECOVERY_SUSP_C', '0.0002', '+', 'T_RECOVERY')}\n valid comment[ 0] @ avcline 35302: {log('T_RECOVERY_SUSP_C', '', '', 0, 0)}\n valid comment[ 1] @ avcline 35304: {Test End: T08_02_Soft_Reset_Recovery_Time}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id3\");\n rdi.func().label(s_splited_pat_name[3]).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes3[curSite] = rdi.id(\"burst_id3\").getBurstPassFail();\n FuncPrint(\"i_funcRes3\", i_funcRes3[curSite]);\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n\n }\n\n ON_FIRST_INVOCATION_END();\n\n TestLog(\"T_RECOVERY_ACC_C\" ,T_RECOVERY_ACC_C[curSite]);\n TestLog(\"T_RECOVERY_SUSP_C\" ,T_RECOVERY_SUSP_C[curSite]);\n\n i_funcRes[curSite] = i_funcRes0[curSite] && i_funcRes1[curSite] && i_funcRes2[curSite] && i_funcRes3[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T08_02_Soft_Reset_Recovery_Time_R1\", T08_02_Soft_Reset_Recovery_Time_R1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 1 $ $Author: hmf1rt $ $Date: 2024/03/13 13:36:52 GMT $')\nrac('CHIP_ID', 0x0000, 0x0000) # Dummy read to init SPI protocol\nwac('FIFO_WATERMARK', 0x02a5) # Write signature to register\nsav('VDD', 1.6) # don't trigger a BOR\ndly(1e-3)\nrac('FIFO_WATERMARK', 0x02a5) # Check signature\nsav('VDD', 1.2) # trigger a BOR\ndly(1e-3)\nsav('VDD', 1.7) # deactivate POR\ndly(3e-3) # specified BOOT time\nrac('CHIP_ID', 0x0000, 0x0000) # Dummy read to init SPI protocol\ndly(10e-6)\nrac('FIFO_WATERMARK', 0x0000) # Check that register reset has occurred\nsav('VDD', 1.8)\ndly(100e-6)\n", "output": "/*****************************************************\n * T08_03_POR_BOR_VDD_test_V1, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T08_03_POR_BOR_VDD_test_V1: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static int i_funcRes0[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T08_03_POR_BOR_VDD_test}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 1] @ avcline 315: {sav('VDD', 1.6, 2, 0.01, False, False)}\n valid comment[ 2] @ avcline 436: {sav('VDD', 1.2, 2, 0.01, False, False)}\n valid comment[ 3] @ avcline 444: {sav('VDD', 1.7, 2, 0.01, False, False)}\n valid comment[ 4] @ avcline 687: {sav('VDD', 1.8, 2, 0.01, False, False)}\n valid comment[ 5] @ avcline 697: {Test End: T08_03_POR_BOR_VDD_test}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][1]).pin(\"VDD\").vForce(1.6 V).iRange(40 mA)//{sav('VDD', 1.6, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][2]).pin(\"VDD\").vForce(1.2 V).iRange(40 mA)//{sav('VDD', 1.2, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][3]).pin(\"VDD\").vForce(1.7 V).iRange(40 mA)//{sav('VDD', 1.7, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][4]).pin(\"VDD\").vForce(1.8 V).iRange(40 mA)//{sav('VDD', 1.8, 2, 0.01, False, False)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n\n ON_FIRST_INVOCATION_END();\n\n i_funcRes[curSite] = i_funcRes0[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T08_03_POR_BOR_VDD_test_V1\", T08_03_POR_BOR_VDD_test_V1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description:\n# - ramping down the VDD pulse and measure current on VDD (ACC on); detect the POR\n# - ramping up VDD and measure current on VDD; detect the POR\n# - ramping down the VDD pulse and measure current on VDD (sensors off/STANDBY); detect the POR\n#############################################################################################################\ncmt('Version info: $Revision: 1 $ $Author: hmf1rt $ $Date: 2024/03/13 13:36:52 GMT $')\n\nwac('EXT_MODE', 0xc006) # Switch to FCU register page\nwcb('FCU_TEST_CONF.temp_test_force_dis',0x1) # temp off\ndly(3e-3) # make sure that TEMP is switched off\nwac('EXT_MODE', 0xc000) # Switch to USR register page\nwac('FIFO_WATERMARK', 0x02a5) # Write signature to register\n# Ramp down VDD pulse from 1.70 V to 1.00 V in 10 mV steps and measure supply current\n# Use optimal current measurement range covering 300 uA for full ramp down\nfor n in range(0, 71, 1):\n cmt('Set voltage at pad VDD to {:.2f}V'.format(1.7-0.01*n))\n sav(\"VDD\", (170-n)/100.0)\n dly(300e-6)\t # good for any probecard/tester\n gac('I_VDD_BOR[{:02d}]'.format(n), 'VDD', i_range=300e-6)\n dly(296e-9)\n log('I_VDD_BOR[{:02d}]'.format(n))\n dly(10e-6)\n sav(\"VDD\", 1.6)\n dly(3e-3) # specified BOOT time\n rac('CHIP_ID', 0x0000, 0x0000) # Dummy read to init SPI protocol\n ras('WATERMARK', 'FIFO_WATERMARK')\n calc('WATERMARK_IDX_DWN[{:02d}]'.format(n), 'WATERMARK', \"+\", n)\n calc('V_SUPPLY_VDD_DWN[{:02d}]'.format(n), (170-n)/100.0)\n wac('FIFO_WATERMARK', 0x02a5) # Write signature to register\noti('N_OPT_RESET_DWN', 'WATERMARK_IDX_DWN', 0) # the first index with a reset is calculated\ngvi('V_VDD_BOR', 'V_SUPPLY_VDD_DWN', 'N_OPT_RESET_DWN')\nlog('V_VDD_BOR')\ndly(100e-6)\t\n\n# Ramp up VDD voltage from 1.00 V to 1.70 V in 10 mV steps and measure supply current\n# Use optimal current measurement range covering 100 uA for full ramp up\nfor n in range(0, 71, 1):\n cmt('Set voltage at pad VDD to {:.2f}V'.format(1.0+0.01*n))\n sav(\"VDD\", (100+n)/100.0)\n dly(3e-3)\t\n # Measure current I_VDD_POR_{n} at pad VDD\n gac('I_VDD_POR[{:02d}]'.format(n), 'VDD', i_range=300e-6)\n dly(296e-9)\n log('I_VDD_POR[{:02d}]'.format(n))\n rac('CHIP_ID', 0x0000, 0x0000) # Dummy read to init SPI protocol\n wr('FIFO_WATERMARK', 0x02a5) # Write signature to register\n ras('WATERMARK', 'FIFO_WATERMARK')\n calc('WATERMARK_IDX_UP[{:02d}]'.format(n), 'WATERMARK', \"+\", n)\n calc('V_SUPPLY_VDD_UP[{:02d}]'.format(n), (100+n)/100.0)\noti('N_OPT_RESET_UP', 'WATERMARK_IDX_UP', 0x02a5) # the first index with an activation is calculated\ngvi('V_VDD_POR', 'V_SUPPLY_VDD_UP', 'N_OPT_RESET_UP')\nlog('V_VDD_POR')\ndly(100e-6)\n\nsav(\"VDD\", 1.8) # VDD back to original voltage, T01_10 CONFIG_STC_ACC\ndly(100e-6)\n", "output": "/*****************************************************\n * T08_04_POR_BOR_VDD_Char_V1, description file version Notfound, avc file version Notfound\n * First Editor : jsh5sgh\n * Code generated with autocoding tool V2.9.1, in TOI2 standard way by module write_standard\n * Change History:\n * JSH5SGH: fix some bugs.\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T08_04_POR_BOR_VDD_Char_V1: public testmethod::TestMethod {\n\n protected:\n int\t\ti_funcRes[xNSitES];\n double\tV_VDD;\n double\tV_VDDIO;\n\nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n\t static int iVDD_Spec;\n\t GET_USER_FLAG(\"VDD_Spec\",\t\t\t&iVDD_Spec);\n\t if (iVDD_Spec >1)\n\t\t return;\n\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 5;\n vector i_comment_line[i_split_count];\n\n ARRAY_I aI_Captured_0, aI_Captured_2;\n static int WATERMARK[xNSitES][71], WATERMARK_IDX_DWN[xNSitES][71], WATERMARK_IDX_UP[xNSitES][71];\n static int i_funcRes0[xNSitES], i_funcRes1[xNSitES], i_funcRes2[xNSitES], i_funcRes3[xNSitES];\n static int i_funcRes4[xNSitES];\n static double V_SUPPLY_VDD_DWN[xNSitES][71], I_VDD_BOR[xNSitES][71];\n static double V_SUPPLY_VDD_UP[xNSitES][71], I_VDD_POR[xNSitES][71];\n static int N_OPT_RESET_DWN[xNSitES], N_OPT_RESET_UP[xNSitES];\n static double V_VDD_BOR[xNSitES], V_VDD_POR[xNSitES];\n\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n\t Func_Init_Var(i_funcRes, 0, xNSitES);\n\n\t //!\"CTmsg: cut pattern to 5 parts @ oriAVCvecline [32964, 32975, 55485, 55496]\n\t //!\"CTmsg: cut pattern to 5 parts @ binarypatline [32954, 32965, 55475, 55486]\n\t if (i_split_pat_flag)\n\t {\n\t split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n\t }\n\t else\n\t {\n\t\t split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n\t\t for(int i=0; i }\n\n\t valid comment[ 1] @ avcline 943: {cmt: Set voltage at pad VDD to 1.70V}\n\t valid comment[ 1] @ avcline 943: {sav('VDD', 1.7, 2, 0.01, False, False)}\n\t valid comment[ 2] @ avcline 952: {gac('I_VDD_BOR[00]', 'VDD', 0.0003, 0.0001, True)}\n\t valid comment[ 3] @ avcline 956: {log('I_VDD_BOR[00]', '', '', 0, 0)}\n\t valid comment[ 4] @ avcline 966: {sav('VDD', 1.6, 2, 0.01, False, False)}\n\t valid comment[ 5] @ avcline 1089: {ras('WATERMARK', 'FIFO_WATERMARK')}\n\t valid comment[ 6] @ avcline 1202: {calc('WATERMARK_IDX_DWN[00]', 'WATERMARK', '+', '0')}\n\t valid comment[ 6] @ avcline 1202: {calc('V_SUPPLY_VDD_DWN[00]', '1.7', '', '')}\n\n\t valid comment[ 7] @ avcline 1394: {cmt: Set voltage at pad VDD to 1.69V}\n\t valid comment[ 7] @ avcline 1394: {sav('VDD', 1.69, 2, 0.01, False, False)}\n\t valid comment[ 8] @ avcline 1403: {gac('I_VDD_BOR[01]', 'VDD', 0.0003, 0.0001, True)}\n\t valid comment[ 9] @ avcline 1407: {log('I_VDD_BOR[01]', '', '', 0, 0)}\n\t valid comment[ 10] @ avcline 1417: {sav('VDD', 1.6, 2, 0.01, False, False)}\n\t valid comment[ 11] @ avcline 1540: {ras('WATERMARK', 'FIFO_WATERMARK')}\n\t valid comment[ 12] @ avcline 1653: {calc('WATERMARK_IDX_DWN[01]', 'WATERMARK', '+', '1')}\n\t valid comment[ 12] @ avcline 1653: {calc('V_SUPPLY_VDD_DWN[01]', '1.69', '', '')}\n\t ...\n\t valid comment[421] @ avcline 32513: {cmt: Set voltage at pad VDD to 1.00V}\n\t valid comment[421] @ avcline 32513: {sav('VDD', 1, 2, 0.01, False, False)}\n\t valid comment[422] @ avcline 32522: {gac('I_VDD_BOR[70]', 'VDD', 0.0003, 0.0001, True)}\n\t valid comment[423] @ avcline 32526: {log('I_VDD_BOR[70]', '', '', 0, 0)}\n\t valid comment[424] @ avcline 32536: {sav('VDD', 1.6, 2, 0.01, False, False)}\n\t valid comment[425] @ avcline 32659: {ras('WATERMARK', 'FIFO_WATERMARK')}\n\t valid comment[426] @ avcline 32772: {calc('WATERMARK_IDX_DWN[70]', 'WATERMARK', '+', '70')}\n\t valid comment[426] @ avcline 32772: {calc('V_SUPPLY_VDD_DWN[70]', '1.0', '', '')}\n\t */\n string s_rdi_unit, s_rdi_burstid, s_rdi_dcid;\n SWITCH_VDD(s_rdi_unit, s_rdi_burstid, s_rdi_dcid, 0);\n RDI_UNIT_INIT(s_rdi_unit);\n\n\t RDI_BEGIN(mode);\n\t\t rdi.burstId(s_rdi_burstid);\n\t\t rdi.digCap(\"digcapid_0\").vecVarOnly().pin(\"SDO\").capMode(TA::SER).bitPerWord(16).samples(71*16).execute();\n\t\t for(int i=0; i<71; i++) {\n\t\t\t double v_bor = 1.70 - 0.01*i;\n\t\t\t rdi.dc(s_rdi_dcid).label(s_splited_pat_name[0])\n\t\t\t\t\t .insertSub(i_comment_line[0][i*6+1]).pin(\"VDD\").vForce(v_bor V)//{sav('VDD', 1.7, 2, 0.01, False, False)}\n\t\t\t\t\t\t.insertSub(i_comment_line[0][i*6+2]).pin(\"VDD\").vForce(v_bor V).iMeas().iRange(1000 uA).average(32).measWait(1 ms)//{gac('I_VDD_BOR[00]', 'VDD', 0.0003, 0.0001, True)}\n\t\t\t\t\t\t.insertSub(i_comment_line[0][i*6+4]).pin(\"VDD\").vForce(1.6 V).iRange(40 mA)//{sav('VDD', 1.6, 2, 0.01, False, False)}\n\t\t\t\t\t\t.cont();\n\t\t }\n\t\t rdi.dc(s_rdi_dcid).label(s_splited_pat_name[0]).execute();\n\n\t RDI_END();\n\t FOR_EACH_SITE_BEGIN();\n\t\t i_funcRes0[curSite] = rdi.id(s_rdi_burstid).getBurstPassFail();\n\t\t aI_Captured_0 = rdi.id(\"digcapid_0\").getVector(\"SDO\");\n\t\t ARRAY_D ad_jsubresults_VDD; ad_jsubresults_VDD.resize(71); ad_jsubresults_VDD.init(-9.9);\n\t\t ad_jsubresults_VDD = rdi.id(s_rdi_dcid).getMultiValue(\"VDD\");\n\n\t\t for (int i=0; i < 71; i++)\n\t\t {\n\t\t\t aI_Captured_0[i+0] = Switch_High_Low_Bits_16Bits(aI_Captured_0[i+0]);\n\t\t\t I_VDD_BOR[curSite][i] = ad_jsubresults_VDD[i];\n\t\t\t FuncPrint(\"I_VDD_BOR\" ,I_VDD_BOR[curSite][i]);\n\n\t\t\t WATERMARK[curSite][i] = aI_Captured_0[i+0];\n\t\t\t FuncPrint(\"WATERMARK\" ,WATERMARK[curSite][i]);\n\n\t\t\t WATERMARK_IDX_DWN[curSite][i] = WATERMARK[curSite][i] + i;\n\t\t\t FuncPrint(\"WATERMARK_IDX_DWN\" ,WATERMARK_IDX_DWN[curSite][i]);\n\n\t\t\t V_SUPPLY_VDD_DWN[curSite][i] = (170-i)/100.0;\n\t\t\t FuncPrint(\"V_SUPPLY_VDD_DWN\" ,V_SUPPLY_VDD_DWN[curSite][i]);\n\t\t }\n\t\t N_OPT_RESET_DWN[curSite] = i_Func_Optimal_Trim_Val(WATERMARK_IDX_DWN[curSite], 0, 71);\n\t\t FuncPrint(\"N_OPT_RESET_DWN\" ,N_OPT_RESET_DWN[curSite]);\n\t\t V_VDD_BOR[curSite] = V_SUPPLY_VDD_DWN[curSite][N_OPT_RESET_DWN[curSite]];\n\t\t FuncPrint(\"V_VDD_BOR\" ,V_VDD_BOR[curSite]);\n\n\t FOR_EACH_SITE_END();\n\n\n\t /* Ori key coments in subpat1 ~~~~~~~~~~~~~~\n\t valid comment[ 0] @ avcline 32964: {oti('N_OPT_RESET_DWN', 'WATERMARK_IDX_DWN', '0', '')}\n\t valid comment[ 0] @ avcline 32964: {log('V_VDD_BOR', '', '', 0, 0)}\n\t valid comment[ 1] @ avcline 32975: {cmt: Set voltage at pad VDD to 1.00V}\n\t */\n\t RDI_BEGIN(mode);\n\t\t rdi.burstId(\"burst_id1\");\n\t\t rdi.func().label(s_splited_pat_name[1]).execute();\n\t RDI_END();\n\t FOR_EACH_SITE_BEGIN();\n\t\t i_funcRes1[curSite] = rdi.id(\"burst_id1\").getBurstPassFail();\n\t\t FuncPrint(\"i_funcRes1\", i_funcRes1[curSite]);\n\t\t //Add calc code if necessary\n\t FOR_EACH_SITE_END();\n\n\n\t /* Ori key coments in subpat2 ~~~~~~~~~~~~~~\n\t valid comment[ 0] @ avcline 32975: {sav('VDD', 1, 2, 0.01, False, False)}\n\t valid comment[ 1] @ avcline 32985: {gac('I_VDD_POR[00]', 'VDD', 0.0003, 0.0001, True)}\n\t valid comment[ 2] @ avcline 32989: {log('I_VDD_POR[00]', '', '', 0, 0)}\n\t valid comment[ 3] @ avcline 33182: {ras('WATERMARK', 'FIFO_WATERMARK')}\n\t valid comment[ 4] @ avcline 33295: {calc('WATERMARK_IDX_UP[00]', 'WATERMARK', '+', '0')}\n\t valid comment[ 4] @ avcline 33295: {calc('V_SUPPLY_VDD_UP[00]', '1.0', '', '')}\n\t valid comment[ 4] @ avcline 33295: {cmt: Set voltage at pad VDD to 1.01V}\n\n\t valid comment[ 4] @ avcline 33295: {sav('VDD', 1.01, 2, 0.01, False, False)}\n\t valid comment[ 5] @ avcline 33302: {gac('I_VDD_POR[01]', 'VDD', 0.0003, 0.0001, True)}\n\t valid comment[ 6] @ avcline 33306: {log('I_VDD_POR[01]', '', '', 0, 0)}\n\t valid comment[ 7] @ avcline 33499: {ras('WATERMARK', 'FIFO_WATERMARK')}\n\t valid comment[ 8] @ avcline 33612: {calc('WATERMARK_IDX_UP[01]', 'WATERMARK', '+', '1')}\n\t valid comment[ 8] @ avcline 33612: {calc('V_SUPPLY_VDD_UP[01]', '1.01', '', '')}\n\t valid comment[ 8] @ avcline 33612: {cmt: Set voltage at pad VDD to 1.02V}\n\t ...\n\t valid comment[280] @ avcline 55168: {sav('VDD', 1.7, 2, 0.01, False, False)}\n\t valid comment[281] @ avcline 55175: {gac('I_VDD_POR[70]', 'VDD', 0.0003, 0.0001, True)}\n\t valid comment[282] @ avcline 55179: {log('I_VDD_POR[70]', '', '', 0, 0)}\n\t valid comment[283] @ avcline 55372: {ras('WATERMARK', 'FIFO_WATERMARK')}\n\t valid comment[284] @ avcline 55485: {calc('WATERMARK_IDX_UP[70]', 'WATERMARK', '+', '70')}\n\t valid comment[284] @ avcline 55485: {calc('V_SUPPLY_VDD_UP[70]', '1.7', '', '')}\n\t */\n SWITCH_VDD(s_rdi_unit, s_rdi_burstid, s_rdi_dcid, 2);\n\n\t RDI_BEGIN(mode);\n\t\t rdi.burstId(s_rdi_burstid);\n\t\t rdi.digCap(\"digcapid_2\").vecVarOnly().pin(\"SDO\").capMode(TA::SER).bitPerWord(16).samples(71*16).execute();\n\t\t for(int i=0; i<71; i++) {\n\t\t\t double v_por = 1.00 + 0.01*i;\n\t\t\t rdi.dc(s_rdi_dcid).label(s_splited_pat_name[2])\n\t\t\t\t\t\t.insertSub(i_comment_line[2][i*4]) .pin(\"VDD\").vForce(v_por V)//{sav('VDD', 1, 2, 0.01, False, False)}\n\t\t\t\t\t\t.insertSub(i_comment_line[2][i*4+2]).pin(\"VDD\").vForce(v_por V).iRange(100 uA).iMeas().average(128).measWait(1 ms)//{gac('I_VDD_BOR[00]', 'VDD', 0.0003, 0.0001, True)}\n\t\t\t\t\t\t.cont();\n\t\t }\n\t\t rdi.dc(s_rdi_dcid).label(s_splited_pat_name[2]).execute();\n\n\t RDI_END();\n\t FOR_EACH_SITE_BEGIN();\n\t\t i_funcRes2[curSite] = rdi.id(s_rdi_burstid).getBurstPassFail();\n\t\t aI_Captured_2 = rdi.id(\"digcapid_2\").getVector(\"SDO\");\n\t\t ARRAY_D ad_jsubresults_VDD; ad_jsubresults_VDD.resize(71); ad_jsubresults_VDD.init(-9.9);\n\t\t ad_jsubresults_VDD = rdi.id(s_rdi_dcid).getMultiValue(\"VDD\");\n\n\t\t for (int i=0; i < 71; i++)\n\t\t {\n\t\t\t aI_Captured_2[i+0] = Switch_High_Low_Bits_16Bits(aI_Captured_2[i+0]);\n\t\t\t I_VDD_POR[curSite][i] = ad_jsubresults_VDD[i];\n\t\t\t FuncPrint(\"I_VDD_POR\" ,I_VDD_POR[curSite][i]);\n\n\t\t\t WATERMARK[curSite][i] = aI_Captured_2[i+0];\n\t\t\t FuncPrint(\"WATERMARK\" ,WATERMARK[curSite][i]);\n\n\t\t\t WATERMARK_IDX_UP[curSite][i] = WATERMARK[curSite][i] + i;\n\t\t\t FuncPrint(\"WATERMARK_IDX_UP\" ,WATERMARK_IDX_UP[curSite][i]);\n\n\t\t\t V_SUPPLY_VDD_UP[curSite][i] = (100+i)/100.0;\n\t\t\t FuncPrint(\"V_SUPPLY_VDD_UP\" ,V_SUPPLY_VDD_UP[curSite][i]);\n\t\t }\n\t\t N_OPT_RESET_UP[curSite] = i_Func_Optimal_Trim_Val(WATERMARK_IDX_UP[curSite], 0x2a5, 71); //todo confirm if: criteria='gt'\n\t\t FuncPrint(\"N_OPT_RESET_UP\" ,N_OPT_RESET_UP[curSite]);\n\t\t V_VDD_POR[curSite] = V_SUPPLY_VDD_UP[curSite][N_OPT_RESET_UP[curSite]];\n\t\t FuncPrint(\"V_VDD_POR\" ,V_VDD_POR[curSite]);\n\n\t FOR_EACH_SITE_END();\n\n\n\n\t /* Ori key coments in subpat3 ~~~~~~~~~~~~~~\n\t valid comment[ 0] @ avcline 55485: {oti('N_OPT_RESET_UP', 'WATERMARK_IDX_UP', '677', '')}\n\t valid comment[ 0] @ avcline 55485: {log('V_VDD_POR', '', '', 0, 0)}\n\t */\n\t RDI_BEGIN(mode);\n\t\t rdi.burstId(\"burst_id3\");\n\t\t rdi.func().label(s_splited_pat_name[3]).execute();\n\t RDI_END();\n\t FOR_EACH_SITE_BEGIN();\n\t\t i_funcRes3[curSite] = rdi.id(\"burst_id3\").getBurstPassFail();\n\t\t FuncPrint(\"i_funcRes3\", i_funcRes3[curSite]);\n\t\t //Add calc code if necessary\n\t FOR_EACH_SITE_END();\n\n\n\t /* Ori key coments in subpat4 ~~~~~~~~~~~~~~\n\t valid comment[ 0] @ avcline 55496: {sav('VDD', 1.8, 2, 0.01, False, False)}\n\t valid comment[ 1] @ avcline 55505: {Test End: T08_04_POR_BOR_VDD_Char}\n\t */\n SWITCH_VDD(s_rdi_unit, s_rdi_burstid, s_rdi_dcid, 4);\n\n\t RDI_BEGIN(mode);\n\t\t rdi.burstId(s_rdi_burstid);\n\t\t rdi.dc(s_rdi_dcid).label(s_splited_pat_name[4])\n\t\t\t\t\t.insertSub(i_comment_line[4][0]).pin(\"VDD\").vForce(V_VDD V).iRange(40 mA)//{sav('VDD', 1.8, 2, 0.01, False, False)}\n\t\t\t\t\t.execute();\n\t RDI_END();\n\t FOR_EACH_SITE_BEGIN();\n\t\t i_funcRes4[curSite] = rdi.id(s_rdi_burstid).getBurstPassFail();\n\t\t //Add calc code if necessary\n\t FOR_EACH_SITE_END();\n\n\n }\n\n ON_FIRST_INVOCATION_END();\n\n for (int i=0; i < 71; i++) \n\t {\n \t TestLog(s_Func_Test_Name_Add_2Num(\"I_VDD_POR_\", i), I_VDD_POR[curSite][i]);\n \t TestLog(s_Func_Test_Name_Add_2Num(\"I_VDD_BOR_\", i), I_VDD_BOR[curSite][i]);\n\n\t }\n TestLog(\"V_VDD_POR\" ,V_VDD_POR[curSite]);\n TestLog(\"V_VDD_BOR\" ,V_VDD_BOR[curSite]);\n\n i_funcRes[curSite] = i_funcRes0[curSite] && i_funcRes1[curSite] && i_funcRes2[curSite] && i_funcRes3[curSite] && i_funcRes4[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T08_04_POR_BOR_VDD_Char_V1\", T08_04_POR_BOR_VDD_Char_V1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 1 $ $Author: hmf1rt $ $Date: 2024/03/13 13:36:52 GMT $')\nrac('CHIP_ID', 0x0000, 0x0000) # Dummy read to init SPI protocol\nwac('FIFO_WATERMARK', 0x025a) # Write signature to register\nsav('VDDIO', 1.15, v_range=4.0) # some margin for the real device\ndly(1e-3)\nrac('FIFO_WATERMARK', 0x025a) # Check signature\nsav('VDDIO', 0.8, v_range=4.0) # some margin for the real device\ndly(1e-3)\nsav('VDDIO', 1.15, v_range=4.0) # some margin for the real device\ndly(3e-3) # specified BOOT time\nrac('CHIP_ID', 0x0000, 0x0000) # Dummy read to init SPI protocol\ndly(10e-6)\nrac('FIFO_WATERMARK', 0x0000) # Check that register reset has occurred\nsav('VDDIO', 3.0, v_range=4.0)\ndly(100e-6)\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T08_05_POR_BOR_VDDIO_test_V1: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n static double v_VDDIO, v_VDD;\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n v_VDDIO = Primary.getLevelSpec().getSpecValue(\"VDDIO\");\n v_VDD = Primary.getLevelSpec().getSpecValue(\"VDD\");\n// ===========Pattern T08_05_POR_BOR_VDDIO_test_V1_AVC1_PY1=============\n// key comment[0]is || TCMT 305,\" {sav('VDDIO', 1.15, 4, 0.01, False, False)} {dly(0.001, 0)}\"\n// key comment[1]is || TCMT 424,\" {sav('VDDIO', 0.8, 4, 0.01, False, False)} {dly(0.001, 0)}\"\n// key comment[2]is || TCMT 466,\" {sav('VDDIO', 1.15, 4, 0.01, False, False)} {dly(0.003, 0)}\"\n// key comment[3]is || TCMT 721,\" {sav('VDDIO', 3, 4, 0.01, False, False)} {dly(0.0001, 0)}\"\n// ==============================================================\n\n rdi.dc().pin(\"VDDIO\").vForce(v_VDDIO).execute();\n rdi.func(\"id0\").label(s_label_name).stopVec(i_comment_line0[0]-1).execute();\n\n Primary.getLevelSpec().change(\"VDDIO\",1.15);\n FLUSH(TM::APRM);\n rdi.dc().pin(\"VDDIO\").vForce(1.02 V).execute();\n rdi.func(\"id1\").label(s_label_name).startVec(i_comment_line0[0]).stopVec(i_comment_line0[1]-1).execute();\n\n Primary.getLevelSpec().change(\"VDDIO\",0.8);\n FLUSH(TM::APRM);\n rdi.dc().pin(\"VDDIO\").vForce(0.55 V).execute();\n rdi.func(\"id2\").label(s_label_name).startVec(i_comment_line0[1]).stopVec(i_comment_line0[2]-1).execute();\n\n Primary.getLevelSpec().change(\"VDDIO\",1.15);\n FLUSH(TM::APRM);\n rdi.dc().pin(\"VDDIO\").vForce(1.08 V).execute();\n rdi.func(\"id3\").label(s_label_name).startVec(i_comment_line0[2]).stopVec(i_comment_line0[3]-1).execute();\n\n Primary.getLevelSpec().change(\"VDDIO\",3);\n FLUSH(TM::APRM);\n rdi.dc().pin(\"VDDIO\").vForce(1.8 V).execute();\n rdi.func(\"id4\").label(s_label_name).startVec(i_comment_line0[3]).execute();\n\n ON_FIRST_INVOCATION_END();\n\n int Func_result = 1;\n for (int i=0; i<5; i++)\n {\n \t Func_result = Func_result * rdi.id(\"id\"+rdi.itos(i)).getPassFail();\n }\n for (int i=0; i<5; i++)\n {\n \t FuncPrint(\"Func_result\"+rdi.itos(i), rdi.id(\"id\"+rdi.itos(i)).getPassFail());\n }\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T08_05_POR_BOR_VDDIO_test_V1\", T08_05_POR_BOR_VDDIO_test_V1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description:\n# - ramping down the VDDIO pulse and measure current on VDD (ACC on); detect the power on reset\n# - ramping up VDDIO and measure current on VDD(sensors off); detect the power on reset\n#############################################################################################################\ncmt('Version info: $Revision: bai430aa_rel/2 $ $Author: luz3sgh $ $Date: 2024/07/24 02:06:55 GMT $')\n\nwac('EXT_MODE', 0xc006) # Switch to FCU register page\nwcb('FCU_TEST_CONF.temp_test_force_dis',0x1) # temp off\ndly(3e-3) # make sure that TEMP is switched off\n\nwac('EXT_MODE', 0xc000) # Switch to USR register page\nwac('FIFO_WATERMARK', 0x02a5) # Write signature to register\n\n# Ramp down VDDIO pulse from 1.20 V to 0.60 V in 10 mV steps and measure supply current\n# Use optimal current measurement range covering 300 uA for full ramp down\nfor n in range(0, 61, 1):\n cmt('Set voltage at pad VDDIO to {:.2f}V'.format(1.2-0.01*n))\n sav(\"VDDIO\", (120-n)/100.0, sim_ignore=True)\n dly(300e-6)\t # good for any probecard/tester\n gac('I_VDDIO_BOR[{:02d}]'.format(n), 'VDD', i_range=300e-6)\n dly(296e-9)\n log('I_VDDIO_BOR[{:02d}]'.format(n))\n dly(10e-6)\n sav(\"VDDIO\", 1.6)\n dly(3e-3) # specified BOOT time\n rac('CHIP_ID', 0x0000, 0x0000) # Dummy read to init SPI protocol\n ras('WATERMARK', 'FIFO_WATERMARK')\n calc('WATERMARK_IDX_DWN[{:02d}]'.format(n), 'WATERMARK', \"+\", n)\n calc('V_SUPPLY_VDDIO_DWN[{:02d}]'.format(n), (120-n)/100.0)\n wac('FIFO_WATERMARK', 0x02a5) # Write signature to register\noti('N_OPT_RESET_DWN', 'WATERMARK_IDX_DWN', 0) # the first index with a reset is calculated\ngvi('V_VDDIO_BOR', 'V_SUPPLY_VDDIO_DWN', 'N_OPT_RESET_DWN')\nlog('V_VDDIO_BOR')\ndly(100e-6)\t\n\n# Ramp up VDDIO voltage from 0.60 V to 1.20 V in 10 mV steps and measure supply current\n# Use optimal current measurement range covering 100 uA for full ramp up\nfor n in range(0, 61, 1):\n cmt('Set voltage at pad VDDIO to {:.2f}V'.format(0.6+0.01*n))\n sav(\"VDDIO\", (60+n)/100.0, sim_ignore=True) # force 0.6V ras() will face issue during pattern gen\n dly(3e-3)\t\n gac('I_VDDIO_POR[{:02d}]'.format(n), 'VDD', i_range=100e-6)\n dly(296e-9)\n log('I_VDDIO_POR[{:02d}]'.format(n))\n rac('CHIP_ID', 0x0000, 0x0000) # Dummy read to init SPI protocol\n wr('FIFO_WATERMARK', 0x02a5) # Write signature to register\n ras('WATERMARK', 'FIFO_WATERMARK')\n calc('WATERMARK_IDX_UP[{:02d}]'.format(n), 'WATERMARK', \"+\", n)\n calc('V_SUPPLY_VDDIO_UP[{:02d}]'.format(n), (60+n)/100.0)\noti('N_OPT_RESET_UP', 'WATERMARK_IDX_UP', 0x02a5) # the first index with an activation is calculated\ngvi('V_VDDIO_POR', 'V_SUPPLY_VDDIO_UP', 'N_OPT_RESET_UP')\nlog('V_VDDIO_POR')\ndly(100e-6)\nsav(\"VDDIO\", 3.0, v_range=3.0) # VDDIO back to original voltage, T01_10 CONFIG_STC_ACC\ndly(100e-6)\t\n", "output": "/*****************************************************\n * T08_06_POR_BOR_VDDIO_Char_R1, description file version Notfound, avc file version Notfound\n * First Editor : jsh5sgh\n * Code generated with autocoding tool V2.9.1, in TOI2 standard way by module write_standard\n * Change History:\n * JSH5SGH V2: VDDIO force back to 3.0V\n * JSH5SGH: fix some bugs.\n * JSH5SGH: version update.\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T08_06_POR_BOR_VDDIO_Char_R1: public testmethod::TestMethod {\n\n protected:\n int\t\ti_funcRes[xNSitES];\n double\tV_VDD;\n double\tV_VDDIO;\n\nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n\t static int iVDD_Spec;\n\t GET_USER_FLAG(\"VDD_Spec\",\t\t\t&iVDD_Spec);\n\t if (iVDD_Spec >1)\n\t\t return;\n\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 5;\n vector i_comment_line[i_split_count];\n\n ARRAY_I aI_Captured_0, aI_Captured_2;\n static int WATERMARK[xNSitES][61], WATERMARK_IDX_DWN[xNSitES][61], WATERMARK_IDX_UP[xNSitES][61];\n static double V_SUPPLY_VDDIO_DWN[xNSitES][61], I_VDDIO_BOR[xNSitES][61];\n static double V_SUPPLY_VDDIO_UP[xNSitES][61], I_VDDIO_POR[xNSitES][61];\n static int N_OPT_RESET_DWN[xNSitES], N_OPT_RESET_UP[xNSitES];\n static double V_VDDIO_BOR[xNSitES], V_VDDIO_POR[xNSitES];\n static int i_funcRes0[xNSitES], i_funcRes1[xNSitES], i_funcRes2[xNSitES], i_funcRes3[xNSitES];\n static int i_funcRes4[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n \n //!\"CTmsg: cut pattern to 5 parts @ oriAVCvecline [28454, 28465, 47805, 47816]\n //!\"CTmsg: cut pattern to 5 parts @ binarypatline [28444, 28455, 47795, 47806]\n if (i_split_pat_flag)\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n }\n else\n {\n\t\t\t split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n\t\t\t for(int i=0; i }\n\n valid comment[ 1] @ avcline 943: {cmt: Set voltage at pad VDDIO to 1.20V}\n valid comment[ 1] @ avcline 943: {sav('VDDIO', 1.2, 2, 0.01, False, True)}\n valid comment[ 2] @ avcline 952: {gac('I_VDDIO_BOR[00]', 'VDD', 0.0003, 0.0001, True)}\n valid comment[ 3] @ avcline 956: {log('I_VDDIO_BOR[00]', '', '', 0, 0)}\n valid comment[ 4] @ avcline 966: {sav('VDDIO', 1.6, 2, 0.01, False, False)}\n valid comment[ 5] @ avcline 1089: {ras('WATERMARK', 'FIFO_WATERMARK')}\n valid comment[ 6] @ avcline 1202: {calc('WATERMARK_IDX_DWN[00]', 'WATERMARK', '+', '0')}\n valid comment[ 6] @ avcline 1202: {calc('V_SUPPLY_VDDIO_DWN[00]', '1.2', '', '')}\n\n valid comment[ 7] @ avcline 1394: {cmt: Set voltage at pad VDDIO to 1.19V}\n valid comment[ 7] @ avcline 1394: {sav('VDDIO', 1.19, 2, 0.01, False, True)}\n valid comment[ 8] @ avcline 1403: {gac('I_VDDIO_BOR[01]', 'VDD', 0.0003, 0.0001, True)}\n valid comment[ 9] @ avcline 1407: {log('I_VDDIO_BOR[01]', '', '', 0, 0)}\n valid comment[ 10] @ avcline 1417: {sav('VDDIO', 1.6, 2, 0.01, False, False)}\n valid comment[ 11] @ avcline 1540: {ras('WATERMARK', 'FIFO_WATERMARK')}\n valid comment[ 12] @ avcline 1653: {calc('WATERMARK_IDX_DWN[01]', 'WATERMARK', '+', '1')}\n valid comment[ 12] @ avcline 1653: {calc('V_SUPPLY_VDDIO_DWN[01]', '1.19', '', '')}\n ...\n valid comment[361] @ avcline 28003: {cmt: Set voltage at pad VDDIO to 0.60V}\n valid comment[361] @ avcline 28003: {sav('VDDIO', 0.6, 2, 0.01, False, True)}\n valid comment[362] @ avcline 28012: {gac('I_VDDIO_BOR[60]', 'VDD', 0.0003, 0.0001, True)}\n valid comment[363] @ avcline 28016: {log('I_VDDIO_BOR[60]', '', '', 0, 0)}\n valid comment[364] @ avcline 28026: {sav('VDDIO', 1.6, 2, 0.01, False, False)}\n valid comment[365] @ avcline 28149: {ras('WATERMARK', 'FIFO_WATERMARK')}\n valid comment[366] @ avcline 28262: {calc('WATERMARK_IDX_DWN[60]', 'WATERMARK', '+', '60')}\n valid comment[366] @ avcline 28262: {calc('V_SUPPLY_VDDIO_DWN[60]', '0.6', '', '')}\n */\n string s_rdi_unit, s_rdi_burstid, s_rdi_dcid;\n SWITCH_VDD(s_rdi_unit, s_rdi_burstid, s_rdi_dcid, 0);\n RDI_UNIT_INIT(s_rdi_unit);\n\n RDI_BEGIN(mode);\n rdi.burstId(s_rdi_burstid);\n rdi.digCap(\"digcapid_0\").vecVarOnly().pin(\"SDO\").capMode(TA::SER).bitPerWord(16).samples(61*16).execute();\n for(int i=0; i<61; i++) {\n \t double v_vddio_bor = 1.20 - 0.01*i;\n\t\t\t\t rdi.dc(s_rdi_dcid).label(s_splited_pat_name[0])\n\t\t\t\t\t\t\t.insertSub(i_comment_line[0][6*i+1]).pin(\"VDDIO\").vForce(v_vddio_bor V)//{sav('VDDIO', 1.2, 2, 0.01, False, True)}\n\t\t\t\t\t\t\t.insertSub(i_comment_line[0][6*i+2]).pin(\"VDD\").vForce(V_VDDIO).iRange(1 mA).iMeas().average(128).measWait(1 ms)//{gac('I_VDDIO_BOR[00]', 'VDD', 0.0003, 0.0001, True)}\n\t\t\t\t\t\t\t.insertSub(i_comment_line[0][6*i+4]).pin(\"VDDIO\").vForce(1.6 V)//{sav('VDDIO', 1.6, 2, 0.01, False, False)}\n\t\t\t\t\t\t\t.cont();\n }\n rdi.dc(s_rdi_dcid).label(s_splited_pat_name[0]).execute();\n RDI_END();\n\n \t FOR_EACH_SITE_BEGIN();\n \t\t i_funcRes0[curSite] = rdi.id(s_rdi_burstid).getBurstPassFail();\n \t\t aI_Captured_0 = rdi.id(\"digcapid_0\").getVector(\"SDO\");\n \t\t ARRAY_D ad_jsubresults_VDDIO = rdi.id(s_rdi_dcid).getMultiValue(\"VDD\");\n\n \t\t for (int i=0; i < 61; i++)\n \t\t {\n \t\t\t aI_Captured_0[i+0] = Switch_High_Low_Bits_16Bits(aI_Captured_0[i+0]);\n \t\t\t I_VDDIO_BOR[curSite][i] = ad_jsubresults_VDDIO[i];\n \t\t\t FuncPrint(\"I_VDDIO_BOR\" ,I_VDDIO_BOR[curSite][i]);\n\n \t\t\t WATERMARK[curSite][i] = aI_Captured_0[i+0];\n \t\t\t FuncPrint(\"WATERMARK\" ,WATERMARK[curSite][i]);\n\n \t\t\t WATERMARK_IDX_DWN[curSite][i] = WATERMARK[curSite][i] + i;\n \t\t\t FuncPrint(\"WATERMARK_IDX_DWN\" ,WATERMARK_IDX_DWN[curSite][i]);\n\n \t\t\t V_SUPPLY_VDDIO_DWN[curSite][i] = (120-i)/100.0;\n \t\t\t FuncPrint(\"V_SUPPLY_VDDIO_DWN\" ,V_SUPPLY_VDDIO_DWN[curSite][i]);\n \t\t }\n \t\t N_OPT_RESET_DWN[curSite] = i_Func_Optimal_Trim_Val(WATERMARK_IDX_DWN[curSite], 0, 61);\n \t\t FuncPrint(\"N_OPT_RESET_DWN\" ,N_OPT_RESET_DWN[curSite]);\n \t\t V_VDDIO_BOR[curSite] = V_SUPPLY_VDDIO_DWN[curSite][N_OPT_RESET_DWN[curSite]];\n \t\t FuncPrint(\"V_VDDIO_BOR\" ,V_VDDIO_BOR[curSite]);\n\n \t FOR_EACH_SITE_END();\n\n /* Ori key coments in subpat1 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 28454: {oti('N_OPT_RESET_DWN', 'WATERMARK_IDX_DWN', '0', '')}\n valid comment[ 0] @ avcline 28454: {log('V_VDDIO_BOR', '', '', 0, 0)}\n valid comment[ 1] @ avcline 28465: {cmt: Set voltage at pad VDDIO to 0.60V}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id1\");\n rdi.func().label(s_splited_pat_name[1]).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes1[curSite] = rdi.id(\"burst_id1\").getBurstPassFail();\n FuncPrint(\"i_funcRes1\", i_funcRes1[curSite]);\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n /* Ori key coments in subpat2 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 28465: {sav('VDDIO', 0.6, 2, 0.01, False, True)}\n valid comment[ 1] @ avcline 28475: {gac('I_VDDIO_POR[00]', 'VDD', 0.0001, 0.0001, True)}\n valid comment[ 2] @ avcline 28479: {log('I_VDDIO_POR[00]', '', '', 0, 0)}\n valid comment[ 3] @ avcline 28672: {ras('WATERMARK', 'FIFO_WATERMARK')}\n valid comment[ 4] @ avcline 28785: {calc('WATERMARK_IDX_UP[00]', 'WATERMARK', '+', '0')}\n valid comment[ 4] @ avcline 28785: {calc('V_SUPPLY_VDDIO_UP[00]', '0.6', '', '')}\n\n valid comment[ 4] @ avcline 28785: {cmt: Set voltage at pad VDDIO to 0.61V}\n valid comment[ 4] @ avcline 28785: {sav('VDDIO', 0.61, 2, 0.01, False, True)}\n valid comment[ 5] @ avcline 28792: {gac('I_VDDIO_POR[01]', 'VDD', 0.0001, 0.0001, True)}\n valid comment[ 6] @ avcline 28796: {log('I_VDDIO_POR[01]', '', '', 0, 0)}\n valid comment[ 7] @ avcline 28989: {ras('WATERMARK', 'FIFO_WATERMARK')}\n valid comment[ 8] @ avcline 29102: {calc('WATERMARK_IDX_UP[01]', 'WATERMARK', '+', '1')}\n valid comment[ 8] @ avcline 29102: {calc('V_SUPPLY_VDDIO_UP[01]', '0.61', '', '')}\n\t\t ...\n valid comment[240] @ avcline 47488: {cmt: Set voltage at pad VDDIO to 1.20V}\n valid comment[240] @ avcline 47488: {sav('VDDIO', 1.2, 2, 0.01, False, True)}\n valid comment[241] @ avcline 47495: {gac('I_VDDIO_POR[60]', 'VDD', 0.0001, 0.0001, True)}\n valid comment[242] @ avcline 47499: {log('I_VDDIO_POR[60]', '', '', 0, 0)}\n valid comment[243] @ avcline 47692: {ras('WATERMARK', 'FIFO_WATERMARK')}\n valid comment[244] @ avcline 47805: {calc('WATERMARK_IDX_UP[60]', 'WATERMARK', '+', '60')}\n valid comment[244] @ avcline 47805: {calc('V_SUPPLY_VDDIO_UP[60]', '1.2', '', '')}\n */\n SWITCH_VDD(s_rdi_unit, s_rdi_burstid, s_rdi_dcid, 2);\n\n RDI_BEGIN(mode);\n rdi.burstId(s_rdi_burstid);\n rdi.digCap(\"digcapid_2\").vecVarOnly().pin(\"SDO\").capMode(TA::SER).bitPerWord(16).samples(61*16).execute();\n for(int i=0; i<61; i++) {\n \t double v_vddio_por = 0.60 + 0.01*i;\n\t\t\t\t rdi.dc(s_rdi_dcid).label(s_splited_pat_name[2])\n\t\t\t\t\t\t\t.insertSub(i_comment_line[2][4*i+0]).pin(\"VDDIO\").vForce(v_vddio_por V)//{sav('VDDIO', 0.6, 2, 0.01, False, True)}\n\t\t\t\t\t\t\t.insertSub(i_comment_line[2][4*i+1]+1).pin(\"VDD\").vForce(V_VDDIO).iRange(1000 uA).iMeas().average(128).measWait(1 ms)//{gac('I_VDDIO_POR[00]', 'VDD', 0.0001, 0.0001, True)}\n\t\t\t\t\t\t\t.cont();\n }\n rdi.dc(s_rdi_dcid).label(s_splited_pat_name[2]).execute();\n RDI_END();\n \t FOR_EACH_SITE_BEGIN();\n \t\t i_funcRes2[curSite] = rdi.id(s_rdi_burstid).getBurstPassFail();\n \t\t aI_Captured_2 = rdi.id(\"digcapid_2\").getVector(\"SDO\");\n \t\t ARRAY_D ad_jsubresults_VDDIO = rdi.id(s_rdi_dcid).getMultiValue(\"VDD\");\n\n \t\t for (int i=0; i < 61; i++)\n \t\t {\n \t\t\t aI_Captured_2[i+0] = Switch_High_Low_Bits_16Bits(aI_Captured_2[i+0]);\n \t\t\t I_VDDIO_POR[curSite][i] = ad_jsubresults_VDDIO[i];\n \t\t\t FuncPrint(\"I_VDDIO_POR\" ,I_VDDIO_POR[curSite][i]);\n\n \t\t\t WATERMARK[curSite][i] = aI_Captured_2[i+0];\n \t\t\t FuncPrint(\"WATERMARK\" ,WATERMARK[curSite][i]);\n\n \t\t\t WATERMARK_IDX_UP[curSite][i] = WATERMARK[curSite][i] + i;\n \t\t\t FuncPrint(\"WATERMARK_IDX_UP\" ,WATERMARK_IDX_UP[curSite][i]);\n\n \t\t\t V_SUPPLY_VDDIO_UP[curSite][i] = (60+i)/100.0;\n \t\t\t FuncPrint(\"V_SUPPLY_VDDIO_UP\" ,V_SUPPLY_VDDIO_UP[curSite][i]);\n \t\t }\n \t\t N_OPT_RESET_UP[curSite] = i_Func_Optimal_Trim_Val(WATERMARK_IDX_UP[curSite], 0x2a5, 61); //todo confirm if: criteria='gt'\n \t\t FuncPrint(\"N_OPT_RESET_UP\" ,N_OPT_RESET_UP[curSite]);\n \t\t V_VDDIO_POR[curSite] = V_SUPPLY_VDDIO_UP[curSite][N_OPT_RESET_UP[curSite]];\n \t\t FuncPrint(\"V_VDDIO_POR\" ,V_VDDIO_POR[curSite]);\n\n \t FOR_EACH_SITE_END();\n\n /* Ori key coments in subpat3 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 47805: {oti('N_OPT_RESET_UP', 'WATERMARK_IDX_UP', '677', '')}\n valid comment[ 0] @ avcline 47805: {log('V_VDDIO_POR', '', '', 0, 0)}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id3\");\n rdi.func().label(s_splited_pat_name[3]).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes3[curSite] = rdi.id(\"burst_id3\").getBurstPassFail();\n FuncPrint(\"i_funcRes3\", i_funcRes3[curSite]);\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n\n /* Ori key coments in subpat4 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 47816: {sav('VDDIO', 3.0, 2, 0.01, False, False)}\n valid comment[ 1] @ avcline 47825: {Test End: T08_06_POR_BOR_VDDIO_Char}\n */\n SWITCH_VDD(s_rdi_unit, s_rdi_burstid, s_rdi_dcid, 4);\n\n \t RDI_BEGIN(mode);\n \t\t rdi.burstId(s_rdi_burstid);\n \t\t rdi.dc(s_rdi_dcid).label(s_splited_pat_name[4])\n \t\t\t\t\t.insertSub(i_comment_line[4][0]).pin(\"VDDIO\").vForce(V_VDDIO V).iRange(40 mA)//{sav('VDDIO', TODO ?1.8, 2, 0.01, False, False)}\n \t\t\t\t\t.insertSub(i_comment_line[4][0]).pin(\"VDD\").vForce(V_VDD V).iRange(40 mA)//{sav('VDDIO', TODO ?1.8, 2, 0.01, False, False)}\n\t\t\t\t\t\t.execute();\n \t RDI_END();\n \t FOR_EACH_SITE_BEGIN();\n \t\t i_funcRes4[curSite] = rdi.id(s_rdi_burstid).getBurstPassFail();\n \t\t //Add calc code if necessary\n \t FOR_EACH_SITE_END();\n\n\n }\n\n ON_FIRST_INVOCATION_END();\n\n for (int i=0; i < 61; i++)\n\t {\n \t TestLog(s_Func_Test_Name_Add_2Num(\"I_VDDIO_POR_\", i), I_VDDIO_POR[curSite][i]);\n \t TestLog(s_Func_Test_Name_Add_2Num(\"I_VDDIO_BOR_\", i), I_VDDIO_BOR[curSite][i]);\n\n\t }\n TestLog(\"V_VDDIO_POR\" ,V_VDDIO_POR[curSite]);\n TestLog(\"V_VDDIO_BOR\" ,V_VDDIO_BOR[curSite]);\n\n i_funcRes[curSite] = i_funcRes0[curSite] && i_funcRes1[curSite] && i_funcRes2[curSite] && i_funcRes3[curSite] && i_funcRes4[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T08_06_POR_BOR_VDDIO_Char_R1\", T08_06_POR_BOR_VDDIO_Char_R1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 1 $ $Author: hmf1rt $ $Date: 2024/03/13 13:36:52 GMT $')\nwac('EXT_MODE', 0xc009) # Switch to IO register page\n# Measure sink capability\nwac('OCP_MASK', 0x000f) # Set masking register\nwr('IO_INT_CTRL', 0x0004) # Enable INT1 output; Set active low, INT1 in high state\nrac('IO_INT_CTRL', 0x0004, 0x000f) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\ncmt('Configure tester to sink 3 mA current from pad INT1')\nsac('INT1', -3e-3, i_range=-10e-3, sim_ignore=True)\ndly(100e-6)\ngav('V_PAD_SINK', 'INT1', v_range=4.0) \ncmt('Calculate REL_V_PAD_SINK = V_PAD_SINK / VDDIO')\nlog('REL_V_PAD_SINK')\n# Measure source capability\nwac('OCP_MASK', 0x000f) # Set masking register\nwr('IO_INT_CTRL', 0x0005) # Enable INT1 output; Set active high, INT1 in low state\nrac('IO_INT_CTRL', 0x0005, 0x000f) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\ncmt('Configure tester to source 3 mA current into pad INT1')\nsac('INT1', 3e-3, i_range=10e-3, sim_ignore=True)\ndly(100e-6)\ngav('V_PAD_SOURCE', 'INT1', v_range=4.0) \nuac('INT1')\ncmt('Calculate REL_V_PAD_SOURCE = V_PAD_SOURCE / VDDIO')\nlog('REL_V_PAD_SOURCE')\n# Clean\nwac('OCP_MASK', 0x000f) \nwr('IO_INT_CTRL', 0x0000) \nrac('IO_INT_CTRL', 0x0000, 0x000f) \nwr('OCP_MASK', 0x0000) \nrac('OCP_MASK', 0xffff) \n", "output": "/*****************************************************\n * T08_08_Pad_Current_Sink_Source_Capability_V1, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n * JSH5SGH: fix some bugs.\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T08_08_Pad_Current_Sink_Source_Capability_V1: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n double V_VDDIO;\n\nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static double d_V_PAD_SINK[xNSitES];\n static double d_V_PAD_SOURCE[xNSitES];\n static double REL_V_PAD_SINK[xNSitES], REL_V_PAD_SOURCE[xNSitES];\n static int i_funcRes0[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(d_V_PAD_SINK, 9.9, xNSitES);\n Func_Init_Var(d_V_PAD_SOURCE, 9.9, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n \t V_VDDIO = Primary.getLevelSpec().getSpecValue(\"VDDIO\");\n \t Func_Print(V_VDDIO,\t\"V_VDDIO\");\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T08_08_Pad_Current_Sink_Source_Capability}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 1] @ avcline 778: {cmt: Configure tester to sink 3 mA current from pad INT1}\n valid comment[ 1] @ avcline 778: {sac('INT1', -0.003, -0.01, 2, 0, False, True)}\n valid comment[ 2] @ avcline 788: {gav('V_PAD_SINK', 'INT1', '', 4, 0.0001, True)}\n valid comment[ 2] @ avcline 788: {cmt: Calculate REL_V_PAD_SINK = V_PAD_SINK / VDDIO}\n valid comment[ 2] @ avcline 788: {log('REL_V_PAD_SINK', '', '', 0, 0)}\n valid comment[ 3] @ avcline 1365: {cmt: Configure tester to source 3 mA current into pad INT1}\n valid comment[ 3] @ avcline 1365: {sac('INT1', 0.003, 0.01, 2, 0, False, True)}\n valid comment[ 4] @ avcline 1375: {gav('V_PAD_SOURCE', 'INT1', '', 4, 0.0001, True)}\n valid comment[ 4] @ avcline 1375: {uac('INT1', False)}\n valid comment[ 4] @ avcline 1375: {cmt: Calculate REL_V_PAD_SOURCE = V_PAD_SOURCE / VDDIO}\n valid comment[ 4] @ avcline 1375: {log('REL_V_PAD_SOURCE', '', '', 0, 0)}\n valid comment[ 5] @ avcline 1952: {Test End: T08_08_Pad_Current_Sink_Source_Capability}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][1]).pin(\"INT1\").iForce(-3 mA).iRange(40 mA)//{sac('INT1', -0.003, -0.01, 2, 0, False, True)}\n .insertSub(i_comment_line[0][2]).pin(\"INT1\").iForce(-3 mA).iRange(40 mA).valueMode(TA::BADC).vMeas().average(128).measWait(1 ms)//V_PAD_SINK//{gav('V_PAD_SINK', 'INT1', '', 4, 0.0001, True)}\n .insertSub(i_comment_line[0][3]).pin(\"INT1\").iForce(3 mA).iRange(40 mA)//{sac('INT1', 0.003, 0.01, 2, 0, False, True)}\n .insertSub(i_comment_line[0][4]).pin(\"INT1\").iForce(3 mA).iRange(40 mA).valueMode(TA::BADC).vMeas().average(128).measWait(1 ms)//V_PAD_SOURCE//{gav('V_PAD_SOURCE', 'INT1', '', 4, 0.0001, True)}\n .insertSub(i_comment_line[0][4]).pin(\"INT1\").relay(TA::ppmuRly_onAC_offDCPPMU)////{uac('INT1', False)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n ARRAY_D ad_jsubresults_INT1; ad_jsubresults_INT1.resize(2); ad_jsubresults_INT1.init(-9.9);\n ad_jsubresults_INT1 = rdi.id(\"dcid_0\").getMultiValue(\"INT1\");\n \n d_V_PAD_SINK[curSite] = ad_jsubresults_INT1[0];\n FuncPrint(\"V_PAD_SINK\",d_V_PAD_SINK[curSite]);\n d_V_PAD_SOURCE[curSite] = ad_jsubresults_INT1[1];\n FuncPrint(\"V_PAD_SOURCE\",d_V_PAD_SOURCE[curSite]);\n\n REL_V_PAD_SINK[curSite] = d_V_PAD_SINK[curSite] / V_VDDIO;\n FuncPrint(\"REL_V_PAD_SINK\",REL_V_PAD_SINK[curSite]);\n\n REL_V_PAD_SOURCE[curSite] = d_V_PAD_SOURCE[curSite] / V_VDDIO;\n FuncPrint(\"REL_V_PAD_SOURCE\",REL_V_PAD_SOURCE[curSite]);\n\n FOR_EACH_SITE_END();\n\n\n ON_FIRST_INVOCATION_END();\n\n TestLog(\"REL_V_PAD_SINK\",\t\tREL_V_PAD_SINK[curSite]);\n TestLog(\"REL_V_PAD_SOURCE\",\tREL_V_PAD_SOURCE[curSite]);\n i_funcRes[curSite] = i_funcRes0[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T08_08_Pad_Current_Sink_Source_Capability_V1\", T08_08_Pad_Current_Sink_Source_Capability_V1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: bai430aa_rel/1 $ $Author: hmf1rt $ $Date: 2024/07/18 13:25:06 GMT $')\nwac('EXT_MODE', 0xc009) # Switch to IO register page\nwac('OCP_MASK', 0x000f) # Set masking register\nwr('IO_INT_CTRL', 0x0005) # Enable INT1 output; Set active high\nrac('IO_INT_CTRL', 0x0005, 0x000f) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwr('EXT_MODE', 0xc00f) # Switch to TEST page\nwac('DTB1',0x0037) # Route \"sdxfrompad\" to INT1\ncmt('Disconnect pad SDX from digital stimuli and switch to analog resource')\nscmd(\"set_stim SDX.dig_out_en(0)\") \nfor n in range(0, 301, 1): \n cmt('Set stimuli voltage on pad SDX to V_STIM_{} = {}/300*VDDIO'.format(n,n))\n sav('SDX', n/100, v_range=4.0) # Note: the sav() values are only valid for VDDIO=3V (simulated), for other suppies the sav()-ramp needs to be adapted in the pattern\n dly(100e-6)\n cmt('Following is a dummy delay for pattern post processing on ATE')\n dly(592e-9)\t\n gav('V_INT1_{}'.format(n), 'INT1', v_range=4.0)\ncmt('Record V_PAD_UP = V_STIM_n when V_INT_n_ > 0.8*VDDIO the first time')\ncmt('Calculate R_V_PAD_UP = V_PAD_UP / VDDIO')\nlog('R_V_PAD_UP')\nfor n in range(300, -1, -1):\n cmt('Set stimuli voltage on pad SDX to V_STIM[{}] = {}/300*VDDIO'.format(n,n))\n sav('SDX', n/100, v_range=4.0) # Note: the sav() values are only valid for VDDIO=3V (simulated), for other suppies the sav()-ramp needs to be adapted in the pattern\n dly(100e-6)\n cmt('Following is a dummy delay for pattern post processing on ATE')\n dly(592e-9)\t\n gav('V_INT1_{}'.format(n), 'INT1', v_range=4.0)\ncmt('Record V_PAD_DN = V_STIM_n when V_INT1_n < 0.2*VDDIO the first time')\ncmt('Calculate R_V_PAD_DN = V_PAD_DN / VDDIO')\nlog('R_V_PAD_DN')\nuav('SDX')\ndly(100e-6)\ncmt('Calculate R_V_PAD_HYST = R_V_PAD_UP - R_V_PAD_DN')\ncmt('Connect pad SDX to digital SPI driver resource')\nlog('R_V_PAD_HYST')\nscmd(\"set_stim SDX.dig_out_en(1)\") \nwac('DTB1', 0x0000) # Disable DTB1X\nwac('EXT_MODE', 0xc009) # Switch to IO register page\nwac('OCP_MASK', 0x000f) # Set masking register\nwr('IO_INT_CTRL', 0x0000) # Reset INT1 configuration\nrac('IO_INT_CTRL', 0x0000, 0x000f) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n", "output": "/*****************************************************\n * T08_11_Pad_Input_Receiver_Char_R1, description file version Notfound, avc file version Notfound\n * First Editor : jsh5sgh\n * Code generated with autocoding tool V2.9.1, in TOI2 standard way by module write_standard\n * Change History:\n * JSH5SGH V2: add missing log info.\n * JSH5SGH: add VDD/VDDIO swap.\n * JSH5SGH R1: version update\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T08_11_Pad_Input_Receiver_Char_R1: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n double\tV_VDD;\n double\tV_VDDIO;\n\nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n static int i_funcRes0[xNSitES];\n static double V_PAD_UP[xNSitES], R_V_PAD_UP[xNSitES];\n static double V_PAD_DN[xNSitES], R_V_PAD_DN[xNSitES];\n// double V_STIM_UP[301], V_STIM_DN[301];\n static double R_V_PAD_HYST[xNSitES];\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n \t V_VDD = Primary.getLevelSpec().getSpecValue(\"VDD\");\n \t Func_Print(V_VDD,\t\t\"V_VDD\");\n \t V_VDDIO = Primary.getLevelSpec().getSpecValue(\"VDDIO\");\n \t Func_Print(V_VDDIO,\t\"V_VDDIO\");\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T08_11_Pad_Input_Receiver_Char}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 1] @ avcline 1049: {cmt: Disconnect pad SDX from digital stimuli and switch to analog resource}\n\n valid comment[ 1] @ avcline 1049: {cmt: Set stimuli voltage on pad SDX to V_STIM_0 = 0/300*VDDIO}\n valid comment[ 1] @ avcline 1049: {sav('SDX', 0, 4, 0.01, False, False)}\n valid comment[ 2] @ avcline 1059: {cmt: Following is a dummy delay for pattern post processing on ATE}\n valid comment[ 3] @ avcline 1067: {gav('V_INT1_0', 'INT1', '', 4, 0.0001, True)}\n\n valid comment[ 3] @ avcline 1067: {cmt: Set stimuli voltage on pad SDX to V_STIM_1 = 1/300*VDDIO}\n valid comment[ 3] @ avcline 1067: {sav('SDX', 0.01, 4, 0.01, False, False)}\n valid comment[ 4] @ avcline 1076: {cmt: Following is a dummy delay for pattern post processing on ATE}\n valid comment[601] @ avcline 6255: {gav('V_INT1_299', 'INT1', '', 4, 0.0001, True)}\n\n valid comment[601] @ avcline 6255: {cmt: Set stimuli voltage on pad SDX to V_STIM_300 = 300/300*VDDIO}\n valid comment[601] @ avcline 6255: {sav('SDX', 3, 4, 0.01, False, False)}\n valid comment[602] @ avcline 6264: {cmt: Following is a dummy delay for pattern post processing on ATE}\n valid comment[603] @ avcline 6272: {gav('V_INT1_300', 'INT1', '', 4, 0.0001, True)}\n\n valid comment[603] @ avcline 6272: {cmt: Record V_PAD_UP = V_STIM_n when V_INT_n_ > 0.8*VDDIO the first time}\n valid comment[603] @ avcline 6272: {cmt: Calculate R_V_PAD_UP = V_PAD_UP / VDDIO}\n\n valid comment[603] @ avcline 6272: {cmt: Set stimuli voltage on pad SDX to V_STIM[300] = 300/300*VDDIO}\n valid comment[603] @ avcline 6272: {sav('SDX', 3, 4, 0.01, False, False)}\n valid comment[604] @ avcline 6282: {cmt: Following is a dummy delay for pattern post processing on ATE}\n valid comment[605] @ avcline 6290: {gav('V_INT1_300', 'INT1', '', 4, 0.0001, True)}\n\n valid comment[605] @ avcline 6290: {cmt: Set stimuli voltage on pad SDX to V_STIM[299] = 299/300*VDDIO}\n valid comment[605] @ avcline 6290: {sav('SDX', 2.99, 4, 0.01, False, False)}\n valid comment[606] @ avcline 6299: {cmt: Following is a dummy delay for pattern post processing on ATE}\n valid comment[607] @ avcline 6307: {gav('V_INT1_299', 'INT1', '', 4, 0.0001, True)}\n\n valid comment[1203] @ avcline 11478: {cmt: Set stimuli voltage on pad SDX to V_STIM[0] = 0/300*VDDIO}\n valid comment[1203] @ avcline 11478: {sav('SDX', 0, 4, 0.01, False, False)}\n valid comment[1204] @ avcline 11487: {cmt: Following is a dummy delay for pattern post processing on ATE}\n valid comment[1205] @ avcline 11495: {gav('V_INT1_0', 'INT1', '', 4, 0.0001, True)}\n\n valid comment[1205] @ avcline 11495: {cmt: Record V_PAD_DN = V_STIM_n when V_INT1_n < 0.2*VDDIO the first time}\n valid comment[1205] @ avcline 11495: {cmt: Calculate R_V_PAD_DN = V_PAD_DN / VDDIO}\n valid comment[1205] @ avcline 11495: {uav('SDX', False)}\n valid comment[1206] @ avcline 11504: {cmt: Calculate R_V_PAD_HYST = R_V_PAD_UP - R_V_PAD_DN}\n valid comment[1206] @ avcline 11504: {cmt: Connect pad SDX to digital SPI driver resource}\n valid comment[1207] @ avcline 12464: {Test End: T08_11_Pad_Input_Receiver_Char}\n */\n string s_rdi_unit, s_rdi_burstid, s_rdi_dcid;\n SWITCH_VDD(s_rdi_unit, s_rdi_burstid, s_rdi_dcid, 0);\n RDI_UNIT_INIT(s_rdi_unit);\n\n RDI_BEGIN(mode);\n rdi.burstId(s_rdi_burstid);\n for(int i=0; i<301; i++) {\n \t double V_STIM_UP = 1.0 * i/300*V_VDDIO;\n rdi.dc(s_rdi_dcid).label(s_splited_pat_name[0])\n\t\t\t\t\t\t.insertSub(i_comment_line[0][2*i+1]).pin(\"SDX\").vForce(V_STIM_UP V)\n\t\t\t\t\t\t.insertSub(i_comment_line[0][2*i+3]).pin(\"INT1\",TA::BADC).vMeas().average(128).measWait(1 ms)\n\t\t\t\t\t\t.cont();\n }\n for(int i=0; i<301; i++) {\n \t double V_STIM_DN = 1.0 * (300-i)/300*V_VDDIO;\n rdi.dc(s_rdi_dcid).label(s_splited_pat_name[0])\n\t\t\t\t\t\t.insertSub(i_comment_line[0][600+2*i+1]).pin(\"SDX\").vForce(V_STIM_DN V)\n\t\t\t\t\t\t.insertSub(i_comment_line[0][600+2*i+3]).pin(\"INT1\",TA::BADC).vMeas().average(128).measWait(1 ms)\n\t\t\t\t\t\t.cont();\n }\n rdi.dc(s_rdi_dcid).label(s_splited_pat_name[0]).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(s_rdi_burstid).getBurstPassFail();\n ARRAY_D V_INT1; V_INT1.resize(301); V_INT1.init(-9.9);\n ARRAY_D ad_jsubresults_INT1 = rdi.id(s_rdi_dcid).getMultiValue(\"INT1\");\n for(int i=0; i<301; i++) {\n V_INT1[i] = ad_jsubresults_INT1[i];\n// FuncPrint(\"V_INT1_UP_\"+rdi.itos(i), V_INT1[i]);\n }\n int n = Find_first_L2H_Switch_point_index(V_INT1, 0.8*V_VDDIO);\n FuncPrint(\"n\", n);\n\n V_PAD_UP[curSite] = 1.0 * n/300*V_VDDIO;\n FuncPrint(\"V_PAD_UP\", V_PAD_UP[curSite]);\n\n R_V_PAD_UP[curSite] = V_PAD_UP[curSite] / V_VDDIO;\n FuncPrint(\"R_V_PAD_UP\", R_V_PAD_UP[curSite]);\n\n for(int i=0; i<301; i++) {\n\t\t\t\t V_INT1[i] = ad_jsubresults_INT1[i+301];\n// FuncPrint(\"V_INT1_DN_\"+rdi.itos(300-i), V_INT1[i]);\n\n\t\t\t }\n n = Find_first_H2L_Switch_point_index(V_INT1, 0.2*V_VDDIO);\n FuncPrint(\"n\", n);\n\n V_PAD_DN[curSite] = 1.0 * (300-n)/300*V_VDDIO;\n FuncPrint(\"V_PAD_DN\", V_PAD_DN[curSite]);\n\n R_V_PAD_DN[curSite] = V_PAD_DN[curSite] / V_VDDIO;\n FuncPrint(\"R_V_PAD_DN\", R_V_PAD_DN[curSite]);\n\n R_V_PAD_HYST[curSite] = R_V_PAD_UP[curSite] - R_V_PAD_DN[curSite];\n FuncPrint(\"R_V_PAD_HYST\", R_V_PAD_HYST[curSite]);\n\n FOR_EACH_SITE_END();\n\n ON_FIRST_INVOCATION_END();\n\n TestLog(\"R_V_PAD_UP\",\t\tR_V_PAD_UP[curSite]);\n TestLog(\"R_V_PAD_DN\",\t\tR_V_PAD_DN[curSite]);\n TestLog(\"R_V_PAD_HYST\", R_V_PAD_HYST[curSite]);\n\n i_funcRes[curSite] = i_funcRes0[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n// TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T08_11_Pad_Input_Receiver_Char_R1\", T08_11_Pad_Input_Receiver_Char_R1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: bai430aa_rel/1 $ $Author: hmf1rt $ $Date: 2024/07/18 13:25:06 GMT $')\ncmt('Test 1: set external voltage to check pad drive capability')\nwac('EXT_MODE', 0xc009) # Switch to IO register page\nwac('OCP_MASK',0x0007)\n### Pad drive strength test: pad driving vs external voltage, Hi side vs 80% of VDDIO (VDDIO set to 3.0V (see T01_01_power_cycle)) ###\nwr('IO_INT_CTRL',0x0004)\nrac('IO_INT_CTRL',0x0004,0x0007) # Enable INT1 output, push-pull, active low \nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('OCP_MASK',0x0007)\nscmd('set_tb_global ASIC_PAD_TEST_IMPEDANCE_1(100.0);') # Set impedance of external voltage at pad INT1 (backdoor model) in DMS Testbench\nscmd('set_tb_global ASIC_PAD_TEST_VOLTAGE_1(2.4);') # Apply external voltage of 2.4V at pad INT1 (backdoor model) in DMS Testbench, the pad needs to drive against the external voltage\ndly(100e-6)\nfor n in range(8):\n wr('INT_IO_PAD_STRENGTH0', n) # Set pad drive strength, if_pri_drv\n rac('INT_IO_PAD_STRENGTH0',n, 0x0007)\n sav('INT1', 0.96, i_comp=-40e-3, sim_ignore=True) \n dly(1e-3)\n cmt('Following is a dummy delay for pattern post processing on ATE')\n dly(156e-9)\n gac('I_INT1_SINK_DRV_{}'.format(n), 'INT1', i_range=-10e-3)\n\nuav('INT1')\nscmd('set_tb_global ASIC_PAD_TEST_VOLTAGE_1(`wrealZState);') # reset external voltage to high impedance\ndly(100e-6)\nscmd('set_tb_global ASIC_PAD_TEST_VOLTAGE_1(`wrealZState);') # reset external voltage to high impedance\nwr('INT_IO_PAD_STRENGTH0', 0x0004) # Reset pad drive strength\nrac('INT_IO_PAD_STRENGTH0', 0x0004, 0x0007) # Check register setting\n### Pad drive strength test: pad driving vs external voltage, Lo side vs 20% of VDDIO (VDDIO set to 3.0V (see T01_01_power_cycle)) ###\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('IO_INT_CTRL', 0x0005) # Enable INT1 output; Set active high\nwac('OCP_MASK', 0x0007) # Set masking register\n\nscmd('set_tb_global ASIC_PAD_TEST_VOLTAGE_1(0.6);') # Apply external voltage of 0.6V at pad INT1 (backdoor model) in DMS Testbench, the pad needs to drive against the external voltage\nfor n in range(0, 8, 1): \n wr('INT_IO_PAD_STRENGTH0', n) # Set pad drive strength\n sav('INT1', 0.24, i_comp=40e-3, sim_ignore=True) \n dly(1e-3)\n cmt('Following is a dummy delay for pattern post processing on ATE')\n dly(156e-9)\n gac('I_INT1_SOURCE_DRV_{}'.format(n), 'INT1', i_range=10e-3)\n\nuav('INT1')\nscmd('set_tb_global ASIC_PAD_TEST_CURRENT_1(0.00);') # Apply 0A at pad INT1 in DMS Testbench \nscmd('set_tb_global ASIC_PAD_TEST_VOLTAGE_1(`wrealZState);') # reset external voltage to high impedance \ndly(100e-6)\n\n### Reset settings at end of test\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n", "output": "/*****************************************************\n * T08_12_Pad_Drive_Char_R1, description file version Notfound, avc file version Notfound\n * First Editor : jsh5sgh\n * Code generated with autocoding tool V2.9.1, in TOI2 standard way by module write_standard\n * Change History:\n * JSH5SGH R1: version update.\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T08_12_Pad_Drive_Char_R1: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n double\tV_VDD;\n double\tV_VDDIO;\n\nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n\t static int iVDD_Spec;\n\t GET_USER_FLAG(\"VDD_Spec\",\t\t\t&iVDD_Spec);\n\t if (iVDD_Spec >1)\n\t\t return;\n\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static double I_INT1_SINK_DRV[xNSitES][8];\n static double I_INT1_SOURCE_DRV[xNSitES][8];\n static int i_funcRes0[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n \t V_VDD = Primary.getLevelSpec().getSpecValue(\"VDD\");\n \t Func_Print(V_VDD,\t\t\"V_VDD\");\n \t V_VDDIO = Primary.getLevelSpec().getSpecValue(\"VDDIO\");\n \t Func_Print(V_VDDIO,\t\"V_VDDIO\");\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T08_12_Pad_Drive_Char}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 0] @ avcline 10: {cmt: Test 1: set external voltage to check pad drive capability}\n\n valid comment[ 1] @ avcline 1172: {sav('INT1', 0.96, 2, -0.04, False, True)}\n valid comment[ 2] @ avcline 1180: {cmt: Following is a dummy delay for pattern post processing on ATE}\n valid comment[ 3] @ avcline 1182: {gac('I_INT1_SINK_DRV_0', 'INT1', -0.01, 0.0001, True)}\n\n valid comment[ 4] @ avcline 1374: {sav('INT1', 0.96, 2, -0.04, False, True)}\n valid comment[ 5] @ avcline 1382: {cmt: Following is a dummy delay for pattern post processing on ATE}\n valid comment[ 6] @ avcline 1384: {gac('I_INT1_SINK_DRV_1', 'INT1', -0.01, 0.0001, True)}\n ...\n valid comment[ 22] @ avcline 2586: {sav('INT1', 0.96, 2, -0.04, False, True)}\n valid comment[ 23] @ avcline 2594: {cmt: Following is a dummy delay for pattern post processing on ATE}\n valid comment[ 24] @ avcline 2596: {gac('I_INT1_SINK_DRV_7', 'INT1', -0.01, 0.0001, True)}\n\n valid comment[ 24] @ avcline 2596: {uav('INT1', False)}\n\n valid comment[ 25] @ avcline 3452: {sav('INT1', 0.24, 2, 0.04, False, True)}\n valid comment[ 26] @ avcline 3460: {cmt: Following is a dummy delay for pattern post processing on ATE}\n valid comment[ 27] @ avcline 3462: {gac('I_INT1_SOURCE_DRV_0', 'INT1', 0.01, 0.0001, True)}\n\n valid comment[ 28] @ avcline 3541: {sav('INT1', 0.24, 2, 0.04, False, True)}\n valid comment[ 29] @ avcline 3549: {cmt: Following is a dummy delay for pattern post processing on ATE}\n valid comment[ 30] @ avcline 3551: {gac('I_INT1_SOURCE_DRV_1', 'INT1', 0.01, 0.0001, True)}\n\n valid comment[ 46] @ avcline 4075: {sav('INT1', 0.24, 2, 0.04, False, True)}\n valid comment[ 47] @ avcline 4083: {cmt: Following is a dummy delay for pattern post processing on ATE}\n valid comment[ 48] @ avcline 4085: {gac('I_INT1_SOURCE_DRV_7', 'INT1', 0.01, 0.0001, True)}\n\n valid comment[ 48] @ avcline 4085: {uav('INT1', False)}\n valid comment[ 49] @ avcline 4286: {Test End: T08_12_Pad_Drive_Char}\n */\n \t double v_INT1_high = 0.8 * V_VDDIO;\n \t double v_INT1_low = 0.2 * V_VDDIO;\n\n \t RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n for(int i=0; i<8; i++) {\n\t\t\t\t rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n\t\t\t\t\t\t\t.insertSub(i_comment_line[0][3*i+1]).pin(\"INT1\").vForce(v_INT1_high V).iRange(40 mA)//{sav('INT1', 0.96, 2, -0.04, False, True)}\n\t\t\t\t\t\t\t.insertSub(i_comment_line[0][3*i+3]).pin(\"INT1\").vForce(v_INT1_high V).iMeas().valueMode(TA::BADC).iRange(40 mA).average(128).measWait(1 ms)\n\t\t\t\t\t\t\t.cont();\n }\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][24]).pin(\"INT1\").relay(TA::ppmuRly_offALL)////{uav('INT1', False)}\n .cont();\n for(int i=0; i<8; i++) {\n\t\t\t\t rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n\t\t\t\t\t\t\t.insertSub(i_comment_line[0][24+3*i+1]).pin(\"INT1\").vForce(v_INT1_low V).iRange(40 mA)//{sav('INT1', 0.96, 2, -0.04, False, True)}\n\t\t\t\t\t\t\t.insertSub(i_comment_line[0][24+3*i+3]).pin(\"INT1\").vForce(v_INT1_low V).iMeas().valueMode(TA::BADC).iRange(40 mA).average(128).measWait(1 ms)\n\t\t\t\t\t\t\t.cont();\n }\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][48]).pin(\"INT1\").relay(TA::ppmuRly_offALL)////{uav('INT1', False)}\n .cont();\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0]).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n ARRAY_D ad_jsubresults_INT1; ad_jsubresults_INT1.resize(16); ad_jsubresults_INT1.init(-9.9);\n ad_jsubresults_INT1 = rdi.id(\"dcid_0\").getMultiValue(\"INT1\");\n\n for(int i=0; i<8; i++) {\n I_INT1_SINK_DRV[curSite][i] = ad_jsubresults_INT1[i];\n FuncPrint(\"I_INT1_SINK_DRV_\"+rdi.itos(i),\t\tI_INT1_SINK_DRV[curSite][i]);\n\n I_INT1_SOURCE_DRV[curSite][i] = ad_jsubresults_INT1[i+8];\n FuncPrint(\"I_INT1_SOURCE_DRV_\"+rdi.itos(i),\tI_INT1_SOURCE_DRV[curSite][i]);\n }\n FOR_EACH_SITE_END();\n\n\n ON_FIRST_INVOCATION_END();\n\n for(int i=0; i<8; i++) {\n \t TestLog(\"I_INT1_SINK_DRV_\"+rdi.itos(i), \tI_INT1_SINK_DRV[curSite][i]);\n TestLog(\"I_INT1_SOURCE_DRV_\"+rdi.itos(i),\t\tI_INT1_SOURCE_DRV[curSite][i]);\n }\n\n i_funcRes[curSite] = i_funcRes0[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T08_12_Pad_Drive_Char_R1\", T08_12_Pad_Drive_Char_R1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description:\n# - measure pull-up resistance of CSB\n# -Entry condtion PU; Exit codition Extendpage enabled\n#############################################################################################################\ncmt('Version info: $Revision: 4 $ $Author: luz3sgh $ $Date: 2024/07/04 02:14:57 GMT $')\n# CSB pull up measure, SPI protocol not enabled yet\nscmd(\"set_stim CSB.dig_out_en(0)\") # Disable digital driver on CSB \nVDDIO = 3.0 # change VDDIO value base on corrsponding char flow\nsav(\"CSB\", 0.8*VDDIO, v_range=4.0) # Pull CSB to 0.8 * VDDIO\ndly(100e-6)\ngac(\"I_PU_CSB\", \"CSB\", i_range=10e-6)\ncmt(\"Calculate R_PU_CSB = abs(0.2*VDDIO/I_PU_CSB)\")\nlog(\"R_PU_CSB\")\nuav(\"CSB\")\nscmd(\"set_stim CSB.dig_out_en(1)\") # Enable digital driver on CSB\n", "output": "/*****************************************************\n * T08_13_PU_Resistors_Measurement_V4, description file version Notfound, avc file version Notfound\n * First Editor : jsh5sgh\n * Code generated with autocoding tool V2.9.1, in TOI2 standard way by module write_standard\n * Change History:\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T08_13_PU_Resistors_Measurement_V4: public testmethod::TestMethod {\n\n protected:\n int\t\ti_funcRes[xNSitES];\n double\tV_VDD;\n double\tV_VDDIO;\n\nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static double I_PU_CSB[xNSitES];\n static double R_PU_CSB[xNSitES];\n static int i_funcRes0[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n \t V_VDD = Primary.getLevelSpec().getSpecValue(\"VDD\");\n \t Func_Print(V_VDD,\t\t\"V_VDD\");\n \t V_VDDIO = Primary.getLevelSpec().getSpecValue(\"VDDIO\");\n \t Func_Print(V_VDDIO,\t\"V_VDDIO\");\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T08_13_PU_Resistors_Measurement}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 0] @ avcline 10: {sav('CSB', 2.4, 4, 0.01, False, False)}\n valid comment[ 1] @ avcline 20: {gac('I_PU_CSB', 'CSB', 1e-05, 0.0001, True)}\n valid comment[ 1] @ avcline 20: {cmt: Calculate R_PU_CSB = abs(0.2*VDDIO/I_PU_CSB)}\n valid comment[ 1] @ avcline 20: {log('R_PU_CSB', '', '', 0, 0)}\n valid comment[ 2] @ avcline 21: {uav('CSB', False)}\n valid comment[ 2] @ avcline 21: {Test End: T08_13_PU_Resistors_Measurement}\n */\n string s_rdi_unit, s_rdi_burstid, s_rdi_dcid;\n SWITCH_VDD(s_rdi_unit, s_rdi_burstid, s_rdi_dcid, 0);\n RDI_UNIT_INIT(s_rdi_unit);\n\n RDI_BEGIN(mode);\n rdi.burstId(s_rdi_burstid);\n rdi.dc(s_rdi_dcid).label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][0]).pin(\"CSB\").vForce(0.8*V_VDDIO V)//{sav('CSB', 2.4, 4, 0.01, False, False)}\n .insertSub(i_comment_line[0][1]).pin(\"CSB\").vForce(0.8*V_VDDIO V).iMeas().valueMode(TA::BADC).iRange(10 uA).average(512).measWait(1 ms)\n .insertSub(i_comment_line[0][2]).pin(\"CSB\").relay(TA::ppmuRly_offALL)////{uav('CSB', False)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(s_rdi_burstid).getBurstPassFail();\n ARRAY_D ad_jsubresults_CSB; ad_jsubresults_CSB.resize(1); ad_jsubresults_CSB.init(-9.9);\n ad_jsubresults_CSB = rdi.id(s_rdi_dcid).getMultiValue(\"CSB\");\n \n I_PU_CSB[curSite] = ad_jsubresults_CSB[0];\n FuncPrint(\"I_PU_CSB\",I_PU_CSB[curSite]);\n\n R_PU_CSB[curSite] = abs(0.2*V_VDDIO/I_PU_CSB[curSite]);\n FuncPrint(\"R_PU_CSB\",R_PU_CSB[curSite]);\n\n FOR_EACH_SITE_END();\n\n\n ON_FIRST_INVOCATION_END();\n\n TestLog(\"R_PU_CSB\",R_PU_CSB[curSite]);\n i_funcRes[curSite] = i_funcRes0[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T08_13_PU_Resistors_Measurement_V4\", T08_13_PU_Resistors_Measurement_V4);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#####################################################################\n# Measure VDD/VDDIO current under different ramp up combinations\n# C1 C2 C3 C4A C4B\n# _ _ _ _ _ _ _ _ _ _ _ _ _ _\n#VDD _ _| |_ _ _ _ _ _ _ _ _| |_ _ _| \n# C1 C2 C3A C3B C4 \n# _ _ _ _ _ _ _ _ _ _ _ _ _ _\n#VDDIO _ _ _ _ _ _ _| |_ _| |_ _| |_ _ _\n#\n\n# C5 C6 \n# _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ \n#VDD _ _| |_ _| |_ _ _| |_ _ _ \n# C5 C6 \n# _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ \n#VDDIO _ _| |_ _ _| |_ _| |_ _ _\n#\n#####################################################################\ncmt('Version info: $Revision: bai430aa_rel/1 $ $Author: hmf1rt $ $Date: 2024/07/18 13:25:06 GMT $')\ncmt(\"SCX, SDX keep low during entier test sequence to avoid I2C atuto detect and current leakage\")\ncmt(\"CSB keel same level as VDDIO druing entire test sequence to avoid current leakage\")\ncmt(\"TOI: make sure to adapt the CSB VIH level to the VDDIO supply setting\")\n# Define VDD, VDDIO supply for sim only\nsupply = {\"VDD\":1.8, \"VDDIO\":3.0}\n# Pre-setting\n#sav('VDD', value=0.0, v_range=3, i_comp=500e-6, sim_ignore=True)\nsav('VDD', value=0.0, v_range=3, i_comp=500e-6)\n#sav('VDDIO', value=0.0, v_range=3, i_comp=500e-6, sim_ignore=True)\nsav('VDDIO', value=0.0, v_range=3, i_comp=500e-6)\nsav('CSB', 0.0)\nsav('SCX', 0.0)\nsav('SDX', 0.0)\ndly(1.000036e-3) # (4x3378 + 2) *74ns to have extra 2 vec lines in pattern \n# Measure\ncmt('Measure C1, ramp up VDD, keep VDDIO low')\nsav('VDD', supply[\"VDD\"], 3, 500e-6, sim_ignore=True)\nsav('VDDIO', 0.0, 3, 500e-6, sim_ignore=True)\nsav('CSB', 0.0)\ndly(1.000036e-3)\ngac('I_C1_VDD', 'VDD', 50e-6, 1e-3) \ngac('I_C1_VDDIO', 'VDDIO', 50e-6, 1e-3)\n\ncmt('Measure C2, VDD low, ramp up VDDIO')\nsav('VDD', 0.0, sim_ignore=True)\ndly(1.000036e-3)\nsav('VDDIO',supply[\"VDDIO\"], 3, 500e-6, sim_ignore=True)\nsav('CSB', supply[\"VDDIO\"])\ndly(1.000036e-3)\ngac('I_C2_VDD', 'VDD', 50e-6, 1e-3)\ngac('I_C2_VDDIO', 'VDDIO',50e-6, 1e-3)\nsav('VDD', 0.0, sim_ignore=True)\nsav('VDDIO', 0.0, sim_ignore=True)\nsav('CSB', 0.0)\ndly(1.000036e-3)\n\ncmt('Measure C3, VDDIO ramp first, then ramp VDD and power down VDD ')\nsav('VDDIO',supply[\"VDDIO\"], 3, 500e-6, sim_ignore=True)\nsav('CSB', supply[\"VDDIO\"])\ndly(1.000036e-3)\ncmt('Set VDD to value given in the supply voltage table')\nsav('VDD',supply[\"VDD\"],3,500e-6,sim_ignore=True)\ndly(1.000036e-3)\ngac('I_C3_VDD', 'VDD', 50e-6, 1e-3)\ngac('I_C3A_VDDIO', 'VDDIO',50e-6, 1e-3)\ndly(1.000036e-3)\nsav('VDD', 0.0,sim_ignore=True)\ndly(1.000036e-3)\ngac('I_C3B_VDDIO', 'VDDIO',50e-6, 1e-3)\nsav('VDD', 0.0,sim_ignore=True)\nsav('VDDIO', 0.0,sim_ignore=True)\nsav('CSB', 0.0)\ndly(1.000036e-3)\n\ncmt('Measure C4, VDD ramp first, then ramp VDDIO and power down VDD ')\nsav('VDD',supply[\"VDD\"],3,500e-6,sim_ignore=True)\ndly(1.000036e-3)\ncmt('Set VDDIO to value given in the supply voltage table')\nsav('VDDIO',supply[\"VDDIO\"], 3, 500e-6, sim_ignore=True)\nsav('CSB', supply[\"VDDIO\"])\ndly(1.000036e-3)\ngac('I_C4A_VDD', 'VDD', 50e-6, 1e-3)\ngac('I_C4_VDDIO', 'VDDIO',50e-6, 1e-3)\ndly(1.000036e-3)\nsav('VDDIO', 0.0,sim_ignore=True)\nsav('CSB', 0.0)\ndly(1.000036e-3)\ngac('I_C4B_VDD', 'VDD', 50e-6, 1e-3)\n# C5 C6 \n# _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ \n#VDD _ _| |_ _| |_ _ _| |_ _ _ \n# C5 C6 \n# _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ \n#VDDIO _ _| |_ _ _| |_ _| |_ _ _\nsav('VDD', 0.0,sim_ignore=True)\nsav('VDDIO', 0.0,sim_ignore=True)\nsav('CSB', 0.0)\ndly(1.000036e-3)\ncmt('Measure C5')\nsav('VDD', supply[\"VDD\"], 3, 500e-6, sim_ignore=True)\nsav('VDDIO',supply[\"VDDIO\"], 3, 500e-6, sim_ignore=True)\nsav('CSB', supply[\"VDDIO\"])\ndly(1.000036e-3)\nsav('VDDIO', 0.0,sim_ignore=True)\nsav('CSB', 0.0)\n\ndly(1.000036e-3)\nsav('VDDIO',supply[\"VDDIO\"], 3, 500e-6, sim_ignore=True)\nsav('CSB', supply[\"VDDIO\"])\ndly(1.000036e-3)\ngac('I_C5_VDD', 'VDD', 50e-6, 1e-3)\ngac('I_C5_VDDIO', 'VDDIO',50e-6, 1e-3)\nsav('VDD', 0.0,sim_ignore=True)\nsav('VDDIO', 0.0,sim_ignore=True)\nsav('CSB', 0.0)\ndly(1.000036e-3)\n\ncmt('Measure C6')\nsav('VDD', supply[\"VDD\"], 3, 500e-6, sim_ignore=True)\nsav('VDDIO',supply[\"VDDIO\"], 3, 500e-6, sim_ignore=True)\nsav('CSB', supply[\"VDDIO\"])\ndly(1.000036e-3)\nsav('VDD', 0.0,sim_ignore=True)\ndly(1.000036e-3)\nsav('VDD', supply[\"VDD\"], 3, 500e-6, sim_ignore=True)\ndly(1.000036e-3)\ngac('I_C6_VDD', 'VDD', 50e-6, 1e-3)\ngac('I_C6_VDDIO', 'VDDIO',50e-6, 1e-3)\nsav('VDD', 0.0,sim_ignore=True)\nsav('VDDIO', 0.0,sim_ignore=True)\nsav('CSB', 0.0)\n", "output": "/*****************************************************\n * T08_15_Power_Supply_Ramping_Test_R1, description file version Notfound, avc file version Notfound\n * First Editor : jsh5sgh\n * Code generated with autocoding tool V2.9.1, in TOI2 standard way by module write_standard\n * Change History:\n * JSH5SGH V2: add dummy line between RPTV and gac\n * JSH5SGH R1: version update.\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T08_15_Power_Supply_Ramping_Test_R1: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n double\tV_VDD;\n double\tV_VDDIO;\n\nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static double I_C1_VDD[xNSitES];\n static double I_C1_VDDIO[xNSitES];\n static double I_C2_VDD[xNSitES];\n static double I_C2_VDDIO[xNSitES];\n static double I_C3A_VDDIO[xNSitES];\n static double I_C3B_VDDIO[xNSitES];\n static double I_C3_VDD[xNSitES];\n static double I_C4A_VDD[xNSitES];\n static double I_C4B_VDD[xNSitES];\n static double I_C4_VDDIO[xNSitES];\n static double I_C5_VDD[xNSitES];\n static double I_C5_VDDIO[xNSitES];\n static double I_C6_VDD[xNSitES];\n static double I_C6_VDDIO[xNSitES];\n static int i_funcRes0[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n \t V_VDD = Primary.getLevelSpec().getSpecValue(\"VDD\");\n \t Func_Print(V_VDD,\t\t\"V_VDD\");\n \t V_VDDIO = Primary.getLevelSpec().getSpecValue(\"VDDIO\");\n \t Func_Print(V_VDDIO,\t\"V_VDDIO\");\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T08_15_Power_Supply_Ramping_Test}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 0] @ avcline 10: {cmt: SCX, SDX keep low during entier test sequence to avoid I2C atuto detect and current leakage}\n valid comment[ 0] @ avcline 10: {cmt: CSB keel same level as VDDIO druing entire test sequence to avoid current leakage}\n valid comment[ 0] @ avcline 10: {cmt: TOI: make sure to adapt the CSB VIH level to the VDDIO supply setting}\n\n valid comment[ 0] @ avcline 10: {sav('VDD', 0, 3, 0.0005, False, False)}\n valid comment[ 0] @ avcline 10: {sav('VDDIO', 0, 3, 0.0005, False, False)}\n valid comment[ 0] @ avcline 10: {sav('CSB', 0, 2, 0.01, False, False)}\n valid comment[ 0] @ avcline 10: {sav('SCX', 0, 2, 0.01, False, False)}\n valid comment[ 0] @ avcline 10: {sav('SDX', 0, 2, 0.01, False, False)}\n\n valid comment[ 1] @ avcline 18: {cmt: Measure C1, ramp up VDD, keep VDDIO low}\n valid comment[ 1] @ avcline 18: {sav('VDD', 1.8, 3, 0.0005, False, True)}\n valid comment[ 1] @ avcline 18: {sav('VDDIO', 0, 3, 0.0005, False, True)}\n valid comment[ 1] @ avcline 18: {sav('CSB', 0, 2, 0.01, False, False)}\n valid comment[ 2] @ avcline 25: {gac('I_C1_VDD', 'VDD', 5e-05, 0.001, True)}\n valid comment[ 2] @ avcline 25: {gac('I_C1_VDDIO', 'VDDIO', 5e-05, 0.001, True)}\n\n valid comment[ 2] @ avcline 25: {cmt: Measure C2, VDD low, ramp up VDDIO}\n valid comment[ 2] @ avcline 25: {sav('VDD', 0, 2, 0.01, False, True)}\n valid comment[ 3] @ avcline 33: {sav('VDDIO', 3, 3, 0.0005, False, True)}\n valid comment[ 3] @ avcline 33: {sav('CSB', 3, 2, 0.01, False, False)}\n valid comment[ 4] @ avcline 40: {gac('I_C2_VDD', 'VDD', 5e-05, 0.001, True)}\n valid comment[ 4] @ avcline 40: {gac('I_C2_VDDIO', 'VDDIO', 5e-05, 0.001, True)}\n valid comment[ 4] @ avcline 40: {sav('VDD', 0, 2, 0.01, False, True)}\n valid comment[ 4] @ avcline 40: {sav('VDDIO', 0, 2, 0.01, False, True)}\n valid comment[ 4] @ avcline 40: {sav('CSB', 0, 2, 0.01, False, False)}\n\n valid comment[ 5] @ avcline 48: {cmt: Measure C3, VDDIO ramp first, then ramp VDD and power down VDD }\n valid comment[ 5] @ avcline 48: {sav('VDDIO', 3, 3, 0.0005, False, True)}\n valid comment[ 5] @ avcline 48: {sav('CSB', 3, 2, 0.01, False, False)}\n valid comment[ 6] @ avcline 55: {cmt: Set VDD to value given in the supply voltage table}\n valid comment[ 6] @ avcline 55: {sav('VDD', 1.8, 3, 0.0005, False, True)}\n valid comment[ 7] @ avcline 63: {gac('I_C3_VDD', 'VDD', 5e-05, 0.001, True)}\n valid comment[ 7] @ avcline 63: {gac('I_C3A_VDDIO', 'VDDIO', 5e-05, 0.001, True)}\n valid comment[ 8] @ avcline 70: {sav('VDD', 0, 2, 0.01, False, True)}\n valid comment[ 9] @ avcline 78: {gac('I_C3B_VDDIO', 'VDDIO', 5e-05, 0.001, True)}\n valid comment[ 9] @ avcline 78: {sav('VDD', 0, 2, 0.01, False, True)}\n valid comment[ 9] @ avcline 78: {sav('VDDIO', 0, 2, 0.01, False, True)}\n valid comment[ 9] @ avcline 78: {sav('CSB', 0, 2, 0.01, False, False)}\n\n valid comment[ 10] @ avcline 85: {cmt: Measure C4, VDD ramp first, then ramp VDDIO and power down VDD }\n valid comment[ 10] @ avcline 85: {sav('VDD', 1.8, 3, 0.0005, False, True)}\n valid comment[ 11] @ avcline 93: {cmt: Set VDDIO to value given in the supply voltage table}\n valid comment[ 11] @ avcline 93: {sav('VDDIO', 3, 3, 0.0005, False, True)}\n valid comment[ 11] @ avcline 93: {sav('CSB', 3, 2, 0.01, False, False)}\n valid comment[ 12] @ avcline 100: {gac('I_C4A_VDD', 'VDD', 5e-05, 0.001, True)}\n valid comment[ 12] @ avcline 100: {gac('I_C4_VDDIO', 'VDDIO', 5e-05, 0.001, True)}\n valid comment[ 13] @ avcline 108: {sav('VDDIO', 0, 2, 0.01, False, True)}\n valid comment[ 13] @ avcline 108: {sav('CSB', 0, 2, 0.01, False, False)}\n valid comment[ 14] @ avcline 115: {gac('I_C4B_VDD', 'VDD', 5e-05, 0.001, True)}\n valid comment[ 14] @ avcline 115: {sav('VDD', 0, 2, 0.01, False, True)}\n valid comment[ 14] @ avcline 115: {sav('VDDIO', 0, 2, 0.01, False, True)}\n valid comment[ 14] @ avcline 115: {sav('CSB', 0, 2, 0.01, False, False)}\n\n valid comment[ 15] @ avcline 123: {cmt: Measure C5}\n valid comment[ 15] @ avcline 123: {sav('VDD', 1.8, 3, 0.0005, False, True)}\n valid comment[ 15] @ avcline 123: {sav('VDDIO', 3, 3, 0.0005, False, True)}\n valid comment[ 15] @ avcline 123: {sav('CSB', 3, 2, 0.01, False, False)}\n valid comment[ 16] @ avcline 130: {sav('VDDIO', 0, 2, 0.01, False, True)}\n valid comment[ 16] @ avcline 130: {sav('CSB', 0, 2, 0.01, False, False)}\n valid comment[ 17] @ avcline 138: {sav('VDDIO', 3, 3, 0.0005, False, True)}\n valid comment[ 17] @ avcline 138: {sav('CSB', 3, 2, 0.01, False, False)}\n valid comment[ 18] @ avcline 145: {gac('I_C5_VDD', 'VDD', 5e-05, 0.001, True)}\n valid comment[ 18] @ avcline 145: {gac('I_C5_VDDIO', 'VDDIO', 5e-05, 0.001, True)}\n valid comment[ 18] @ avcline 145: {sav('VDD', 0, 2, 0.01, False, True)}\n valid comment[ 18] @ avcline 145: {sav('VDDIO', 0, 2, 0.01, False, True)}\n valid comment[ 18] @ avcline 145: {sav('CSB', 0, 2, 0.01, False, False)}\n\n valid comment[ 19] @ avcline 153: {cmt: Measure C6}\n valid comment[ 19] @ avcline 153: {sav('VDD', 1.8, 3, 0.0005, False, True)}\n valid comment[ 19] @ avcline 153: {sav('VDDIO', 3, 3, 0.0005, False, True)}\n valid comment[ 19] @ avcline 153: {sav('CSB', 3, 2, 0.01, False, False)}\n valid comment[ 20] @ avcline 160: {sav('VDD', 0, 2, 0.01, False, True)}\n valid comment[ 21] @ avcline 168: {sav('VDD', 1.8, 3, 0.0005, False, True)}\n valid comment[ 22] @ avcline 175: {gac('I_C6_VDD', 'VDD', 5e-05, 0.001, True)}\n valid comment[ 22] @ avcline 175: {gac('I_C6_VDDIO', 'VDDIO', 5e-05, 0.001, True)}\n valid comment[ 22] @ avcline 175: {sav('VDD', 0, 2, 0.01, False, True)}\n valid comment[ 22] @ avcline 175: {sav('VDDIO', 0, 2, 0.01, False, True)}\n valid comment[ 22] @ avcline 175: {sav('CSB', 0, 2, 0.01, False, False)}\n valid comment[ 22] @ avcline 175: {Test End: T08_15_Power_Supply_Ramping_Test}\n */\n string s_rdi_unit, s_rdi_burstid, s_rdi_dcid;\n SWITCH_VDD(s_rdi_unit, s_rdi_burstid, s_rdi_dcid, 0);\n RDI_UNIT_INIT(s_rdi_unit);\n\n RDI_BEGIN(mode);\n rdi.burstId(s_rdi_burstid);\n rdi.dc(s_rdi_dcid).label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][0]).pin(\"VDD,VDDIO,CSB,SCX,SDX\").vForce(0 V).iRange(40 mA)//{sav('VDD', 0, 3, 0.0005, False, False)}\n .insertSub(i_comment_line[0][1]).pin(\"VDD\")\t\t.vForce(V_VDD V).iRange(40 mA)//{sav('VDD', 1.8, 3, 0.0005, False, True)}\n .insertSub(i_comment_line[0][1]).pin(\"VDDIO\")\t.vForce(0 V).iRange(40 mA)//{sav('VDDIO', 0, 3, 0.0005, False, True)}\n .insertSub(i_comment_line[0][1]).pin(\"CSB\")\t\t.vForce(0 V).iRange(40 mA)//{sav('CSB', 0, 2, 0.01, False, False)}\n //C1\n .insertSub(i_comment_line[0][2]).pin(\"VDD\")\t\t.vForce(V_VDD V).iRange(100 uA).iMeas().valueMode(TA::BADC).average(512).measWait(1.0 ms)//{gac('I_C1_VDD', 'VDD', 5e-05, 0.001, True)}\n .insertSub(i_comment_line[0][2]).pin(\"VDDIO\")\t.vForce(0 V).iRange(10 uA).iMeas().valueMode(TA::BADC).average(512).measWait(1.0 ms)//{gac('I_C1_VDDIO', 'VDDIO', 5e-05, 0.001, True)}\n //C2\n .insertSub(i_comment_line[0][2]).pin(\"VDD\")\t\t.vForce(0 V).iRange(40 mA)//{sav('VDD', 0, 2, 0.01, False, True)}\n .insertSub(i_comment_line[0][3]).pin(\"VDDIO\")\t.vForce(V_VDDIO V).iRange(40 mA)//{sav('VDDIO', 3, 3, 0.0005, False, True)}\n .insertSub(i_comment_line[0][3]).pin(\"CSB\")\t\t.vForce(V_VDDIO V).iRange(40 mA)//{sav('CSB', 3, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][4]).pin(\"VDD\")\t\t.vForce(0 V).iRange(10 uA).iMeas().valueMode(TA::BADC).average(512).measWait(1.0 ms)//{gac('I_C1_VDD', 'VDD', 5e-05, 0.001, True)}\n .insertSub(i_comment_line[0][4]).pin(\"VDDIO\")\t.vForce(V_VDDIO V).iRange(10 uA).iMeas().valueMode(TA::BADC).average(512).measWait(1.0 ms)//{gac('I_C1_VDDIO', 'VDDIO', 5e-05, 0.001, True)}\n .insertSub(i_comment_line[0][4]).pin(\"VDD\")\t\t.vForce(0 V).iRange(40 mA)//{sav('VDD', 0, 2, 0.01, False, True)}\n .insertSub(i_comment_line[0][4]).pin(\"VDDIO\")\t.vForce(0 V).iRange(40 mA)//{sav('VDDIO', 0, 2, 0.01, False, True)}\n .insertSub(i_comment_line[0][4]).pin(\"CSB\")\t\t.vForce(0 V).iRange(40 mA)//{sav('CSB', 0, 2, 0.01, False, False)}\n //C3\n .insertSub(i_comment_line[0][5]).pin(\"VDDIO\")\t.vForce(V_VDDIO V).iRange(40 mA)//{sav('VDDIO', 3, 3, 0.0005, False, True)}\n .insertSub(i_comment_line[0][5]).pin(\"CSB\")\t\t.vForce(V_VDDIO V).iRange(40 mA)//{sav('CSB', 3, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][6]).pin(\"VDD\")\t\t.vForce(V_VDD V).iRange(40 mA)//{sav('VDD', 1.8, 3, 0.0005, False, True)}\n .insertSub(i_comment_line[0][7]).pin(\"VDD\")\t\t.vForce(V_VDD V).iRange(100 uA).iMeas().valueMode(TA::BADC).average(512).measWait(1.0 ms)//{gac('I_C1_VDD', 'VDD', 5e-05, 0.001, True)}\n .insertSub(i_comment_line[0][7]).pin(\"VDDIO\")\t.vForce(V_VDDIO V).iRange(10 uA).iMeas().valueMode(TA::BADC).average(512).measWait(1.0 ms)//{gac('I_C1_VDDIO', 'VDDIO', 5e-05, 0.001, True)}\n .insertSub(i_comment_line[0][8]).pin(\"VDD\")\t\t.vForce(0 V).iRange(40 mA)//{sav('VDD', 0, 2, 0.01, False, True)}\n .insertSub(i_comment_line[0][9]).pin(\"VDDIO\")\t.vForce(V_VDDIO V).iRange(10 uA).iMeas().valueMode(TA::BADC).average(512).measWait(1.0 ms)//{gac('I_C1_VDDIO', 'VDDIO', 5e-05, 0.001, True)}\n .insertSub(i_comment_line[0][9]).pin(\"VDD\")\t\t.vForce(0 V).iRange(40 mA)//{sav('VDD', 0, 2, 0.01, False, True)}\n .insertSub(i_comment_line[0][9]).pin(\"VDDIO\")\t.vForce(0 V).iRange(40 mA)//{sav('VDDIO', 0, 2, 0.01, False, True)}\n .insertSub(i_comment_line[0][9]).pin(\"CSB\")\t\t.vForce(0 V).iRange(40 mA)//{sav('CSB', 0, 2, 0.01, False, False)}\n //C4\n .insertSub(i_comment_line[0][10]).pin(\"VDD\")\t.vForce(V_VDD V)//{sav('VDD', 1.8, 3, 0.0005, False, True)}\n .insertSub(i_comment_line[0][11]).pin(\"VDDIO\")\t.vForce(V_VDDIO V)//{sav('VDDIO', 3, 3, 0.0005, False, True)}\n .insertSub(i_comment_line[0][11]).pin(\"CSB\")\t.vForce(V_VDDIO V)//{sav('CSB', 3, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][12]).pin(\"VDD\")\t.vForce(V_VDD V).iRange(100 uA).iMeas().valueMode(TA::BADC).average(512).measWait(1.0 ms)//{gac('I_C1_VDD', 'VDD', 5e-05, 0.001, True)}\n .insertSub(i_comment_line[0][12]).pin(\"VDDIO\")\t.vForce(V_VDDIO V).iRange(10 uA).iMeas().valueMode(TA::BADC).average(512).measWait(1.0 ms)//{gac('I_C1_VDDIO', 'VDDIO', 5e-05, 0.001, True)}\n .insertSub(i_comment_line[0][13]).pin(\"VDDIO\")\t.vForce(0 V).iRange(40 mA)//{sav('VDDIO', 0, 2, 0.01, False, True)}\n .insertSub(i_comment_line[0][13]).pin(\"CSB\")\t.vForce(0 V).iRange(40 mA)//{sav('CSB', 0, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][14]).pin(\"VDD\")\t.vForce(V_VDD V).iRange(10 uA).iMeas().valueMode(TA::BADC).average(512).measWait(1.0 ms)//{gac('I_C1_VDD', 'VDD', 5e-05, 0.001, True)}\n .insertSub(i_comment_line[0][14]).pin(\"VDD\")\t.vForce(0 V).iRange(40 mA)//{sav('VDD', 0, 2, 0.01, False, True)}\n .insertSub(i_comment_line[0][14]).pin(\"VDDIO\")\t.vForce(0 V).iRange(40 mA)//{sav('VDDIO', 0, 2, 0.01, False, True)}\n .insertSub(i_comment_line[0][14]).pin(\"CSB\")\t.vForce(0 V).iRange(40 mA)//{sav('CSB', 0, 2, 0.01, False, False)}\n //C5\n .insertSub(i_comment_line[0][15]).pin(\"VDD\")\t.vForce(V_VDD V).iRange(40 mA)//{sav('VDD', 1.8, 3, 0.0005, False, True)}\n .insertSub(i_comment_line[0][15]).pin(\"VDDIO\")\t.vForce(V_VDDIO V).iRange(40 mA)//{sav('VDDIO', 3, 3, 0.0005, False, True)}\n .insertSub(i_comment_line[0][15]).pin(\"CSB\")\t.vForce(V_VDDIO V).iRange(40 mA)//{sav('CSB', 3, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][16]).pin(\"VDDIO\")\t.vForce(0 V).iRange(40 mA)//{sav('VDDIO', 0, 2, 0.01, False, True)}\n .insertSub(i_comment_line[0][16]).pin(\"CSB\")\t.vForce(0 V).iRange(40 mA)//{sav('CSB', 0, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][17]).pin(\"VDDIO\")\t.vForce(V_VDDIO V).iRange(40 mA)//{sav('VDDIO', 3, 3, 0.0005, False, True)}\n .insertSub(i_comment_line[0][17]).pin(\"CSB\")\t.vForce(V_VDDIO V).iRange(40 mA)//{sav('CSB', 3, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][18]).pin(\"VDD\")\t.vForce(V_VDD V).iRange(100 uA).iMeas().valueMode(TA::BADC).average(512).measWait(1.0 ms)//{gac('I_C1_VDD', 'VDD', 5e-05, 0.001, True)}\n .insertSub(i_comment_line[0][18]).pin(\"VDDIO\")\t.vForce(V_VDDIO V).iRange(10 uA).iMeas().valueMode(TA::BADC).average(512).measWait(1.0 ms)//{gac('I_C1_VDDIO', 'VDDIO', 5e-05, 0.001, True)}\n .insertSub(i_comment_line[0][18]).pin(\"VDD\")\t.vForce(0 V).iRange(40 mA)//{sav('VDD', 0, 2, 0.01, False, True)}\n .insertSub(i_comment_line[0][18]).pin(\"VDDIO\")\t.vForce(0 V).iRange(40 mA)//{sav('VDDIO', 0, 2, 0.01, False, True)}\n .insertSub(i_comment_line[0][18]).pin(\"CSB\")\t.vForce(0 V).iRange(40 mA)//{sav('CSB', 0, 2, 0.01, False, False)}\n //c6\n .insertSub(i_comment_line[0][19]).pin(\"VDD\")\t.vForce(V_VDD V).iRange(40 mA)//{sav('VDD', 1.8, 3, 0.0005, False, True)}\n .insertSub(i_comment_line[0][19]).pin(\"VDDIO\")\t.vForce(V_VDDIO V).iRange(40 mA)//{sav('VDDIO', 3, 3, 0.0005, False, True)}\n .insertSub(i_comment_line[0][19]).pin(\"CSB\")\t.vForce(V_VDDIO V).iRange(40 mA)//{sav('CSB', 3, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][20]).pin(\"VDD\")\t.vForce(0 V).iRange(40 mA)//{sav('VDD', 0, 2, 0.01, False, True)}\n .insertSub(i_comment_line[0][21]).pin(\"VDD\")\t.vForce(V_VDD V)//{sav('VDD', 1.8, 3, 0.0005, False, True)}\n .insertSub(i_comment_line[0][22]).pin(\"VDD\")\t.vForce(V_VDD V).iRange(100 uA).iMeas().valueMode(TA::BADC).average(512).measWait(1.0 ms)//{gac('I_C1_VDD', 'VDD', 5e-05, 0.001, True)}\n .insertSub(i_comment_line[0][22]).pin(\"VDDIO\")\t.vForce(V_VDDIO V).iRange(10 uA).iMeas().valueMode(TA::BADC).average(512).measWait(1.0 ms)//{gac('I_C1_VDDIO', 'VDDIO', 5e-05, 0.001, True)}\n .insertSub(i_comment_line[0][22]).pin(\"VDD\")\t.vForce(0 V).iRange(40 mA)\n .insertSub(i_comment_line[0][22]).pin(\"VDDIO\")\t.vForce(0 V).iRange(40 mA)\n .insertSub(i_comment_line[0][22]).pin(\"CSB\")\t.vForce(0 V).iRange(40 mA)//{sav('CSB', 0, 2, 0.01, False, False)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(s_rdi_burstid).getBurstPassFail();\n ARRAY_D ad_jsubresults_VDD; ad_jsubresults_VDD.resize(7); ad_jsubresults_VDD.init(-9.9);\n ARRAY_D ad_jsubresults_VDDIO; ad_jsubresults_VDDIO.resize(7); ad_jsubresults_VDDIO.init(-9.9);\n ad_jsubresults_VDD = rdi.id(s_rdi_dcid).getMultiValue(\"VDD\");\n ad_jsubresults_VDDIO = rdi.id(s_rdi_dcid).getMultiValue(\"VDDIO\");\n \n I_C1_VDD[curSite] = ad_jsubresults_VDD[0];\n I_C2_VDD[curSite] = ad_jsubresults_VDD[1];\n I_C3_VDD[curSite] = ad_jsubresults_VDD[2];\n I_C4A_VDD[curSite] = ad_jsubresults_VDD[3];\n I_C4B_VDD[curSite] = ad_jsubresults_VDD[4];\n I_C5_VDD[curSite] = ad_jsubresults_VDD[5];\n I_C6_VDD[curSite] = ad_jsubresults_VDD[6];\n I_C1_VDDIO[curSite] = ad_jsubresults_VDDIO[0];\n I_C2_VDDIO[curSite] = ad_jsubresults_VDDIO[1];\n I_C3A_VDDIO[curSite] = ad_jsubresults_VDDIO[2];\n I_C3B_VDDIO[curSite] = ad_jsubresults_VDDIO[3];\n I_C4_VDDIO[curSite] = ad_jsubresults_VDDIO[4];\n I_C5_VDDIO[curSite] = ad_jsubresults_VDDIO[5];\n I_C6_VDDIO[curSite] = ad_jsubresults_VDDIO[6];\n FuncPrint(\"I_C1_VDD\",I_C1_VDD[curSite]);\n FuncPrint(\"I_C1_VDDIO\",I_C1_VDDIO[curSite]);\n FuncPrint(\"I_C2_VDD\",I_C2_VDD[curSite]);\n FuncPrint(\"I_C2_VDDIO\",I_C2_VDDIO[curSite]);\n FuncPrint(\"I_C3A_VDDIO\",I_C3A_VDDIO[curSite]);\n FuncPrint(\"I_C3B_VDDIO\",I_C3B_VDDIO[curSite]);\n FuncPrint(\"I_C3_VDD\",I_C3_VDD[curSite]);\n FuncPrint(\"I_C4A_VDD\",I_C4A_VDD[curSite]);\n FuncPrint(\"I_C4B_VDD\",I_C4B_VDD[curSite]);\n FuncPrint(\"I_C4_VDDIO\",I_C4_VDDIO[curSite]);\n FuncPrint(\"I_C5_VDD\",I_C5_VDD[curSite]);\n FuncPrint(\"I_C5_VDDIO\",I_C5_VDDIO[curSite]);\n FuncPrint(\"I_C6_VDD\",I_C6_VDD[curSite]);\n FuncPrint(\"I_C6_VDDIO\",I_C6_VDDIO[curSite]);\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n\n ON_FIRST_INVOCATION_END();\n\n TestLog(\"I_C1_VDD\",I_C1_VDD[curSite]);\n TestLog(\"I_C1_VDDIO\",I_C1_VDDIO[curSite]);\n TestLog(\"I_C2_VDD\",I_C2_VDD[curSite]);\n TestLog(\"I_C2_VDDIO\",I_C2_VDDIO[curSite]);\n TestLog(\"I_C3A_VDDIO\",I_C3A_VDDIO[curSite]);\n TestLog(\"I_C3B_VDDIO\",I_C3B_VDDIO[curSite]);\n TestLog(\"I_C3_VDD\",I_C3_VDD[curSite]);\n TestLog(\"I_C4A_VDD\",I_C4A_VDD[curSite]);\n TestLog(\"I_C4B_VDD\",I_C4B_VDD[curSite]);\n TestLog(\"I_C4_VDDIO\",I_C4_VDDIO[curSite]);\n TestLog(\"I_C5_VDD\",I_C5_VDD[curSite]);\n TestLog(\"I_C5_VDDIO\",I_C5_VDDIO[curSite]);\n TestLog(\"I_C6_VDD\",I_C6_VDD[curSite]);\n TestLog(\"I_C6_VDDIO\",I_C6_VDDIO[curSite]);\n i_funcRes[curSite] = i_funcRes0[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T08_15_Power_Supply_Ramping_Test_R1\", T08_15_Power_Supply_Ramping_Test_R1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: Power skew test\n# - assume chip in STC_ACC status\n#############################################################################################################\ncmt('Version info: $Revision: 1 $ $Author: hmf1rt $ $Date: 2024/03/13 13:36:52 GMT $')\nsupply = {\"VDDmin\": 1.62, \"VDDtyp\":1.80, \"VDDmax\":3.60,\n \"VDDIOmin\":1.08,\"VDDIOtyp\":1.80,\"VDDIOmax\":3.60 \n }\nsav('VDD', supply[\"VDDtyp\"], v_range=4.0, i_comp=40e-3)\nsav('VDDIO', supply[\"VDDIOtyp\"], v_range=4.0, i_comp=40e-3)\ndly(4e-3)\ngac('I_SKEW_ACT0_VDD', 'VDD')\ngac('I_SKEW_ACT0_VDDIO', 'VDDIO')\nsav('VDD', supply[\"VDDmin\"], v_range=4.0, i_comp=40e-3)\nsav('VDDIO', supply[\"VDDIOmax\"], v_range=4.0, i_comp=40e-3)\ndly(4e-3)\ngac('I_SKEW_ACT1_VDD', 'VDD')\ngac('I_SKEW_ACT1_VDDIO', 'VDDIO')\nsav('VDD', supply[\"VDDmax\"], v_range=4.0, i_comp=40e-3)\nsav('VDDIO', supply[\"VDDIOmin\"], v_range=4.0, i_comp=40e-3)\ndly(4e-3)\ngac('I_SKEW_ACT2_VDD', 'VDD')\ngac('I_SKEW_ACT2_VDDIO', 'VDDIO')\n\nsav('VDD', supply[\"VDDtyp\"], v_range=4.0, i_comp=40e-3)\nsav('VDDIO', supply[\"VDDIOtyp\"], v_range=4.0, i_comp=40e-3)\ndly(1e-3)\nwac('EXT_MODE', 0xc000) # Switch to USR register page\nwac('ACC_CONF', 0x024C) # Switch ACC off\ndly(200e-6)\nwac('EXT_MODE', 0xc00d) # Switch to PMU register page\nrac('STATUS_PMOD0', 0x0000, 0x0003) # Check ACC PMU status\ndly(4e-3)\ngac('I_SKEW_STBY0_VDD', 'VDD')\ngac('I_SKEW_STBY0_VDDIO', 'VDDIO')\nsav('VDD', supply[\"VDDmin\"], v_range=4.0, i_comp=40e-3)\nsav('VDDIO', supply[\"VDDIOmax\"], v_range=4.0, i_comp=40e-3)\ndly(4e-3)\ngac('I_SKEW_STBY1_VDD', 'VDD')\ngac('I_SKEW_STBY1_VDDIO', 'VDDIO')\nsav('VDD', supply[\"VDDmax\"], v_range=4.0, i_comp=40e-3)\nsav('VDDIO', supply[\"VDDIOmin\"], v_range=4.0, i_comp=40e-3)\ndly(4e-3)\ngac('I_SKEW_STBY2_VDD', 'VDD')\ngac('I_SKEW_STBY2_VDDIO', 'VDDIO')\n\nsav('VDD', supply[\"VDDtyp\"], v_range=4.0, i_comp=40e-3)\nsav('VDDIO', supply[\"VDDIOtyp\"], v_range=4.0, i_comp=40e-3)\ndly(1e-3)\nwac('EXT_MODE', 0xc000) # Switch to USR register page\nwac('ACC_CONF', 0xe24c) # Switch ACC on\ndly(400e-6)\nwac('EXT_MODE', 0xc00d) # Switch to PMU register page\nrac('STATUS_PMOD0', 0x0003, 0x0003) # Check ACC AFE PMU status\n", "output": "/*****************************************************\n * T08_16_Power_Skew_Test_V1, description file version Notfound, avc file version Notfound\n * First Editor : jsh5sgh\n * Code generated with autocoding tool V2.9.1, in TOI2 standard way by module write_standard\n * Change History:\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T08_16_Power_Skew_Test_V1: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n const double VDDmin = 1.62, VDDtyp = 1.80, VDDmax = 3.60;\n const double VDDIOmin = 1.08, VDDIOtyp = 1.80, VDDIOmax = 3.60;\n static double I_SKEW_ACT0_VDD[xNSitES];\n static double I_SKEW_ACT0_VDDIO[xNSitES];\n static double I_SKEW_ACT1_VDD[xNSitES];\n static double I_SKEW_ACT1_VDDIO[xNSitES];\n static double I_SKEW_ACT2_VDD[xNSitES];\n static double I_SKEW_ACT2_VDDIO[xNSitES];\n static double I_SKEW_STBY0_VDD[xNSitES];\n static double I_SKEW_STBY0_VDDIO[xNSitES];\n static double I_SKEW_STBY1_VDD[xNSitES];\n static double I_SKEW_STBY1_VDDIO[xNSitES];\n static double I_SKEW_STBY2_VDD[xNSitES];\n static double I_SKEW_STBY2_VDDIO[xNSitES];\n static int i_funcRes0[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T08_16_Power_Skew_Test}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 0] @ avcline 10: {sav('VDD', 1.8, 4, 0.04, False, False)}\n valid comment[ 0] @ avcline 10: {sav('VDDIO', 1.8, 4, 0.04, False, False)}\n valid comment[ 1] @ avcline 19: {gac('I_SKEW_ACT0_VDD', 'VDD', 1e-05, 0.0001, True)}\n valid comment[ 1] @ avcline 19: {gac('I_SKEW_ACT0_VDDIO', 'VDDIO', 1e-05, 0.0001, True)}\n valid comment[ 1] @ avcline 19: {sav('VDD', 1.62, 4, 0.04, False, False)}\n valid comment[ 1] @ avcline 19: {sav('VDDIO', 3.6, 4, 0.04, False, False)}\n valid comment[ 2] @ avcline 27: {gac('I_SKEW_ACT1_VDD', 'VDD', 1e-05, 0.0001, True)}\n valid comment[ 2] @ avcline 27: {gac('I_SKEW_ACT1_VDDIO', 'VDDIO', 1e-05, 0.0001, True)}\n valid comment[ 2] @ avcline 27: {sav('VDD', 3.6, 4, 0.04, False, False)}\n valid comment[ 2] @ avcline 27: {sav('VDDIO', 1.08, 4, 0.04, False, False)}\n valid comment[ 3] @ avcline 35: {gac('I_SKEW_ACT2_VDD', 'VDD', 1e-05, 0.0001, True)}\n valid comment[ 3] @ avcline 35: {gac('I_SKEW_ACT2_VDDIO', 'VDDIO', 1e-05, 0.0001, True)}\n valid comment[ 3] @ avcline 35: {sav('VDD', 1.8, 4, 0.04, False, False)}\n valid comment[ 3] @ avcline 35: {sav('VDDIO', 1.8, 4, 0.04, False, False)}\n valid comment[ 4] @ avcline 749: {gac('I_SKEW_STBY0_VDD', 'VDD', 1e-05, 0.0001, True)}\n valid comment[ 4] @ avcline 749: {gac('I_SKEW_STBY0_VDDIO', 'VDDIO', 1e-05, 0.0001, True)}\n valid comment[ 4] @ avcline 749: {sav('VDD', 1.62, 4, 0.04, False, False)}\n valid comment[ 4] @ avcline 749: {sav('VDDIO', 3.6, 4, 0.04, False, False)}\n valid comment[ 5] @ avcline 757: {gac('I_SKEW_STBY1_VDD', 'VDD', 1e-05, 0.0001, True)}\n valid comment[ 5] @ avcline 757: {gac('I_SKEW_STBY1_VDDIO', 'VDDIO', 1e-05, 0.0001, True)}\n valid comment[ 5] @ avcline 757: {sav('VDD', 3.6, 4, 0.04, False, False)}\n valid comment[ 5] @ avcline 757: {sav('VDDIO', 1.08, 4, 0.04, False, False)}\n valid comment[ 6] @ avcline 765: {gac('I_SKEW_STBY2_VDD', 'VDD', 1e-05, 0.0001, True)}\n valid comment[ 6] @ avcline 765: {gac('I_SKEW_STBY2_VDDIO', 'VDDIO', 1e-05, 0.0001, True)}\n valid comment[ 6] @ avcline 765: {sav('VDD', 1.8, 4, 0.04, False, False)}\n valid comment[ 6] @ avcline 765: {sav('VDDIO', 1.8, 4, 0.04, False, False)}\n valid comment[ 7] @ avcline 1469: {Test End: T08_16_Power_Skew_Test}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][0]).pin(\"VDD\").vForce(VDDtyp V)//{sav('VDD', 1.8, 4, 0.04, False, False)}\n .insertSub(i_comment_line[0][0]).pin(\"VDDIO,CSB\").vForce(VDDIOtyp V)//{sav('VDDIO', 1.8, 4, 0.04, False, False)}\n .insertSub(i_comment_line[0][1]).pin(\"VDD\").vForce(VDDtyp V).iRange(1 mA).iMeas().valueMode(TA::BADC).average(512).measWait(1.0 ms)//{gac('I_C1_VDD', 'VDD', 5e-05, 0.001, True)}\n .insertSub(i_comment_line[0][1]).pin(\"VDDIO\").vForce(VDDIOtyp V).iRange(100 uA).iMeas().valueMode(TA::BADC).average(512).measWait(1.0 ms)//{gac('I_C1_VDDIO', 'VDDIO', 5e-05, 0.001, True)}\n\n .insertSub(i_comment_line[0][1]).pin(\"VDD\").vForce(VDDmin V)//{sav('VDD', 1.62, 4, 0.04, False, False)}\n .insertSub(i_comment_line[0][1]).pin(\"VDDIO,CSB\").vForce(VDDIOmax V)//{sav('VDDIO', 3.6, 4, 0.04, False, False)}\n .insertSub(i_comment_line[0][2]).pin(\"VDD\").vForce(VDDmin V).iRange(1 mA).iMeas().valueMode(TA::BADC).average(512).measWait(1.0 ms)//{gac('I_C1_VDD', 'VDD', 5e-05, 0.001, True)}\n .insertSub(i_comment_line[0][2]).pin(\"VDDIO\").vForce(VDDIOmax V).iRange(100 uA).iMeas().valueMode(TA::BADC).average(512).measWait(1.0 ms)//{gac('I_C1_VDDIO', 'VDDIO', 5e-05, 0.001, True)}\n\n .insertSub(i_comment_line[0][2]).pin(\"VDD\").vForce(VDDmax V)//{sav('VDD', 3.6, 4, 0.04, False, False)}\n .insertSub(i_comment_line[0][2]).pin(\"VDDIO,CSB\").vForce(VDDIOmin V)//{sav('VDDIO', 1.08, 4, 0.04, False, False)}\n .insertSub(i_comment_line[0][3]).pin(\"VDD\").vForce(VDDmax V).iRange(1 mA).iMeas().valueMode(TA::BADC).average(512).measWait(1.0 ms)//{gac('I_C1_VDD', 'VDD', 5e-05, 0.001, True)}\n .insertSub(i_comment_line[0][3]).pin(\"VDDIO\").vForce(VDDIOmin V).iRange(100 uA).iMeas().valueMode(TA::BADC).average(512).measWait(1.0 ms)//{gac('I_C1_VDDIO', 'VDDIO', 5e-05, 0.001, True)}\n\n .insertSub(i_comment_line[0][3]).pin(\"VDD\").vForce(VDDtyp V)//{sav('VDD', 1.8, 4, 0.04, False, False)}\n .insertSub(i_comment_line[0][3]).pin(\"VDDIO,CSB\").vForce(VDDIOtyp V)//{sav('VDDIO', 1.8, 4, 0.04, False, False)}\n .insertSub(i_comment_line[0][3]).pin(\"CSB\").relay(TA::ppmuRly_onAC_offDCPPMU)\n\n .insertSub(i_comment_line[0][4]).pin(\"VDD\").vForce(VDDtyp V).iRange(1 mA).iMeas().valueMode(TA::BADC).average(512).measWait(1.0 ms)//{gac('I_C1_VDD', 'VDD', 5e-05, 0.001, True)}\n .insertSub(i_comment_line[0][4]).pin(\"VDDIO\").vForce(VDDIOtyp V).iRange(100 uA).iMeas().valueMode(TA::BADC).average(512).measWait(1.0 ms)//{gac('I_C1_VDDIO', 'VDDIO', 5e-05, 0.001, True)}\n\n .insertSub(i_comment_line[0][4]).pin(\"VDD\").vForce(VDDmin V)//{sav('VDD', 1.62, 4, 0.04, False, False)}\n .insertSub(i_comment_line[0][4]).pin(\"VDDIO,CSB\").vForce(VDDIOmax V)//{sav('VDDIO', 3.6, 4, 0.04, False, False)}\n .insertSub(i_comment_line[0][5]).pin(\"VDD\").vForce(VDDmin V).iRange(1 mA).iMeas().valueMode(TA::BADC).average(512).measWait(1.0 ms)//{gac('I_C1_VDD', 'VDD', 5e-05, 0.001, True)}\n .insertSub(i_comment_line[0][5]).pin(\"VDDIO\").vForce(VDDIOmax V).iRange(100 uA).iMeas().valueMode(TA::BADC).average(512).measWait(1.0 ms)//{gac('I_C1_VDDIO', 'VDDIO', 5e-05, 0.001, True)}\n\n .insertSub(i_comment_line[0][5]).pin(\"VDD\").vForce(VDDmax V)//{sav('VDD', 3.6, 4, 0.04, False, False)}\n .insertSub(i_comment_line[0][5]).pin(\"VDDIO,CSB\").vForce(VDDIOmin V)//{sav('VDDIO', 1.08, 4, 0.04, False, False)}\n .insertSub(i_comment_line[0][6]).pin(\"VDD\").vForce(VDDmax V).iRange(1 mA).iMeas().valueMode(TA::BADC).average(512).measWait(1.0 ms)//{gac('I_C1_VDD', 'VDD', 5e-05, 0.001, True)}\n .insertSub(i_comment_line[0][6]).pin(\"VDDIO\").vForce(VDDIOmin V).iRange(100 uA).iMeas().valueMode(TA::BADC).average(512).measWait(1.0 ms)//{gac('I_C1_VDDIO', 'VDDIO', 5e-05, 0.001, True)}\n\n .insertSub(i_comment_line[0][6]).pin(\"VDD\").vForce(VDDtyp V).iRange(40 mA)//{sav('VDD', 1.8, 4, 0.04, False, False)}\n .insertSub(i_comment_line[0][6]).pin(\"VDDIO,CSB\").vForce(VDDIOtyp V).iRange(40 mA)//{sav('VDDIO', 1.8, 4, 0.04, False, False)}\n .insertSub(i_comment_line[0][6]).pin(\"CSB\").relay(TA::ppmuRly_onAC_offDCPPMU)\n\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n ARRAY_D ad_jsubresults_VDD; ad_jsubresults_VDD.resize(6); ad_jsubresults_VDD.init(-9.9);\n ARRAY_D ad_jsubresults_VDDIO; ad_jsubresults_VDDIO.resize(6); ad_jsubresults_VDDIO.init(-9.9);\n ad_jsubresults_VDD = rdi.id(\"dcid_0\").getMultiValue(\"VDD\");\n ad_jsubresults_VDDIO = rdi.id(\"dcid_0\").getMultiValue(\"VDDIO\");\n \n I_SKEW_ACT0_VDD[curSite] = ad_jsubresults_VDD[0];\n I_SKEW_ACT1_VDD[curSite] = ad_jsubresults_VDD[1];\n I_SKEW_ACT2_VDD[curSite] = ad_jsubresults_VDD[2];\n I_SKEW_STBY0_VDD[curSite] = ad_jsubresults_VDD[3];\n I_SKEW_STBY1_VDD[curSite] = ad_jsubresults_VDD[4];\n I_SKEW_STBY2_VDD[curSite] = ad_jsubresults_VDD[5];\n I_SKEW_ACT0_VDDIO[curSite] = ad_jsubresults_VDDIO[0];\n I_SKEW_ACT1_VDDIO[curSite] = ad_jsubresults_VDDIO[1];\n I_SKEW_ACT2_VDDIO[curSite] = ad_jsubresults_VDDIO[2];\n I_SKEW_STBY0_VDDIO[curSite] = ad_jsubresults_VDDIO[3];\n I_SKEW_STBY1_VDDIO[curSite] = ad_jsubresults_VDDIO[4];\n I_SKEW_STBY2_VDDIO[curSite] = ad_jsubresults_VDDIO[5];\n FuncPrint(\"I_SKEW_ACT0_VDD\",I_SKEW_ACT0_VDD[curSite]);\n FuncPrint(\"I_SKEW_ACT0_VDDIO\",I_SKEW_ACT0_VDDIO[curSite]);\n FuncPrint(\"I_SKEW_ACT1_VDD\",I_SKEW_ACT1_VDD[curSite]);\n FuncPrint(\"I_SKEW_ACT1_VDDIO\",I_SKEW_ACT1_VDDIO[curSite]);\n FuncPrint(\"I_SKEW_ACT2_VDD\",I_SKEW_ACT2_VDD[curSite]);\n FuncPrint(\"I_SKEW_ACT2_VDDIO\",I_SKEW_ACT2_VDDIO[curSite]);\n FuncPrint(\"I_SKEW_STBY0_VDD\",I_SKEW_STBY0_VDD[curSite]);\n FuncPrint(\"I_SKEW_STBY0_VDDIO\",I_SKEW_STBY0_VDDIO[curSite]);\n FuncPrint(\"I_SKEW_STBY1_VDD\",I_SKEW_STBY1_VDD[curSite]);\n FuncPrint(\"I_SKEW_STBY1_VDDIO\",I_SKEW_STBY1_VDDIO[curSite]);\n FuncPrint(\"I_SKEW_STBY2_VDD\",I_SKEW_STBY2_VDD[curSite]);\n FuncPrint(\"I_SKEW_STBY2_VDDIO\",I_SKEW_STBY2_VDDIO[curSite]);\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n\n ON_FIRST_INVOCATION_END();\n\n TestLog(\"I_SKEW_ACT0_VDD\",I_SKEW_ACT0_VDD[curSite]);\n TestLog(\"I_SKEW_ACT0_VDDIO\",I_SKEW_ACT0_VDDIO[curSite]);\n TestLog(\"I_SKEW_ACT1_VDD\",I_SKEW_ACT1_VDD[curSite]);\n TestLog(\"I_SKEW_ACT1_VDDIO\",I_SKEW_ACT1_VDDIO[curSite]);\n TestLog(\"I_SKEW_ACT2_VDD\",I_SKEW_ACT2_VDD[curSite]);\n TestLog(\"I_SKEW_ACT2_VDDIO\",I_SKEW_ACT2_VDDIO[curSite]);\n TestLog(\"I_SKEW_STBY0_VDD\",I_SKEW_STBY0_VDD[curSite]);\n TestLog(\"I_SKEW_STBY0_VDDIO\",I_SKEW_STBY0_VDDIO[curSite]);\n TestLog(\"I_SKEW_STBY1_VDD\",I_SKEW_STBY1_VDD[curSite]);\n TestLog(\"I_SKEW_STBY1_VDDIO\",I_SKEW_STBY1_VDDIO[curSite]);\n TestLog(\"I_SKEW_STBY2_VDD\",I_SKEW_STBY2_VDD[curSite]);\n TestLog(\"I_SKEW_STBY2_VDDIO\",I_SKEW_STBY2_VDDIO[curSite]);\n i_funcRes[curSite] = i_funcRes0[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T08_16_Power_Skew_Test_V1\", T08_16_Power_Skew_Test_V1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 3 $ $Author: hmf1rt $ $Date: 2024/04/19 14:25:16 GMT $')\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_CONF', 0x0011) # Enable TB1; invert test bus\nwac('TM_PIN', 0x0095) # Enable ANAIO1/2; TB1_OUT on ANAIO1; TB2_INP on ANAIO2\nwac('TM_ADDR', 0x070e) # Enable reference block on ATM; Connect VREFD/VSS\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('OCP_MASK', 0x000f) # Set masking register\nfor n in range (0, 16, 1):\n cmt('Set trim index to value {} in range (0..15)'.format(n))\n wr('ANA_TRM_PMU', n) # Set trim value\n rac('ANA_TRM_PMU', n, 0x000f) # Check register setting\n uclk('ASCX')\n bw('ASCX', 1)\n dly(1352*74e-9)\n gav('V_REF_D_RAW[{:02d}]'.format(n), 'INT2', 'ASDX')\n calc('V_REF_D[{:02d}]'.format(n), 'V_REF_D_RAW[{:02d}]'.format(n), '-', 'V_OFF1_ECON')\n log('V_REF_D[{:02d}]'.format(n))\n ubw('ASCX')\n clk('ASCX', 1/148e-9)\t\ndly(296e-9)\notv('V_OPT_VREFD', 'V_REF_D', 1.1) # Select optimum trim value\nlog('V_OPT_VREFD')\noti('N_OPT_VREFD', 'V_REF_D', 1.1) # Select optimum trim index\nlog('N_OPT_VREFD')\ndly(296e-9)\nwri('ANA_TRM_PMU', 'N_OPT_VREFD') # Write opt trim index N_OPT_VREFD back to DUT\nras('N_OPT_VREFD_RD', 'ANA_TRM_PMU') # Read and save register setting\ncmt('The test item is a functional fail if (N_OPT_VREFD_RD & 0x000f) != N_OPT_VREFD')\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T10_01_standby_regulator_trimming_V3: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n INT split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &split_pat_flag);\n vector s_splited_pat_name;\n const int split_count = 2; // Alarm:: split_count need manual confirm.\n s_splited_pat_name.resize(split_count);\n vector i_comment_line[split_count];\n\n static int N_OPT_VREFD_RD[xNSitES];\n static int N_OPT_VREFD_WR[xNSitES];\n static double V_REF_D_RAW[xNSitES][16];\n static double V_REF_D[xNSitES][16];\n static double V_OPT_VREFD[xNSitES];\n\n ARRAY_LL N_OPT_VREFD_WR_rtv(xNSitES);\n const int Wri_Bit_Length = 33;\n const int Wri_Bit_Position = 31;\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n GET_TESTSUITE_NAME(test_name);\n\n if (split_pat_flag)\n {\n split_pattern(s_label_name,\"wri\",split_pat_flag,s_splited_pat_name);\n }\n else\n {\n for (int i = 0; i s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static double d_V_REF_D_M[xNSitES];\n static int i_funcRes0[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n// Func_Init_Var(i_funcRes, 0, xNSitES);\n// Func_Init_Var(d_V_REF_D_M_RAW, 9.9, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T10_02_standby_regulator_measurement}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 1] @ avcline 788: {gav('V_REF_D_M_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 1] @ avcline 788: {calc('V_REF_D_M', 'V_REF_D_M_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 1] @ avcline 788: {log('V_REF_D_M', '', '', 0, 0)}\n valid comment[ 2] @ avcline 1365: {Test End: T10_02_standby_regulator_measurement}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][1]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_REF_D_M_RAW//{gav('V_REF_D_M_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n ARRAY_D ad_jsubresults_INT2; ad_jsubresults_INT2.resize(1); ad_jsubresults_INT2.init(-9.9);\n ARRAY_D ad_jsubresults_ASDX; ad_jsubresults_ASDX.resize(1); ad_jsubresults_ASDX.init(-9.9);\n ad_jsubresults_INT2 = rdi.id(\"dcid_0\").getMultiValue(\"INT2\");\n ad_jsubresults_ASDX = rdi.id(\"dcid_0\").getMultiValue(\"ASDX\");\n \n d_V_REF_D_M[curSite] = ad_jsubresults_INT2[0] - ad_jsubresults_ASDX[0] - V_OFF1_ECOFF[curSite];\n\n \t\t FuncPrint(\"ad_jsubresults_ASDX\", ad_jsubresults_ASDX[0]);\n \t\t FuncPrint(\"ad_jsubresults_INT2\", ad_jsubresults_INT2[0]);\n\n FuncPrint(\"V_REF_D_M\",d_V_REF_D_M[curSite]);\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n\n ON_FIRST_INVOCATION_END();\n\n\n int Func_result = rdi.id(\"burst_id0\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"V_REF_D_M\",d_V_REF_D_M[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T10_02_standby_regulator_measurement_V2\", T10_02_standby_regulator_measurement_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 2 $ $Author: laj1mu23 $ $Date: 2024/03/25 20:34:28 GMT $')\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_CONF', 0x0011) # Enable TB1; invert test bus\nwac('TM_PIN', 0x0095) # Enable ANAIO1/2; TB1_OUT on ANAIO1; TB2_INP on ANAIO2\nwac('TM_ADDR', 0x070e) # Enable reference block on ATM; Connect VREFD/VSS\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('OCP_MASK', 0x000f) # Set masking register\nras('REG_VALUE', 'ANA_TRM_PMU') # Store the current value\nfor n in range (0, 16, 1):\n cmt('Set trim index to value {} in range (0..15)'.format(n))\n wr('ANA_TRM_PMU', n) # pc_trm_vref_dc\n rac('ANA_TRM_PMU', n, 0x000f) # Check register setting\n dly(100e-6)\n gav('V_REF_D_C_RAW[{:02d}]'.format(n), 'INT2', 'ASDX')\n calc('V_REF_D_C[{:02d}]'.format(n), 'V_REF_D_C_RAW[{:02d}]'.format(n), '-', 'V_OFF1_ECOFF')\n log('V_REF_D_C[{:02d}]'.format(n))\ndly(592e-9)\nwri('ANA_TRM_PMU', 'REG_VALUE') # Write back the stored value\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\n", "output": "/*****************************************************\n * T10_03_Standby_Regulator_Char_V2, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n * JSH5SGH: fix some bugs.\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T10_03_Standby_Regulator_Char_V2: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 2;\n vector i_comment_line[i_split_count];\n\n static int i_REG_VALUE[xNSitES];\n ARRAY_I aI_Captured_0;\n static double d_V_REF_D_C_RAW[xNSitES][16];\n static double V_REF_D_C[xNSitES][16];\n ARRAY_D ad_V_REF_D_C_RAW;\n\n static int i_WRITE_BACK[xNSitES];\n static int i_vec_Num1[32] = {0};\n static int i_funcRes0[xNSitES], i_funcRes1[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(i_REG_VALUE, 9, xNSitES);\n \n //!\"CTmsg: cut pattern to 2 parts @ oriAVCvecline [4531]\n //!\"CTmsg: cut pattern to 2 parts @ binarypatline [4521]\n if (i_split_pat_flag)\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n }\n else\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n for(int i=0; i }\n valid comment[ 1] @ avcline 1162: {ras('REG_VALUE', 'ANA_TRM_PMU')}\n valid comment[ 2] @ avcline 1275: {cmt: Set trim index to value 0 in range (0..15)}\n valid comment[ 3] @ avcline 1477: {gav('V_REF_D_C_RAW[00]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 3] @ avcline 1477: {calc('V_REF_D_C[00]', 'V_REF_D_C_RAW[00]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 3] @ avcline 1477: {log('V_REF_D_C[00]', '', '', 0, 0)}\n valid comment[ 4] @ avcline 1478: {cmt: Set trim index to value 1 in range (0..15)}\n valid comment[ 5] @ avcline 1680: {gav('V_REF_D_C_RAW[01]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 5] @ avcline 1680: {calc('V_REF_D_C[01]', 'V_REF_D_C_RAW[01]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 5] @ avcline 1680: {log('V_REF_D_C[01]', '', '', 0, 0)}\n valid comment[ 6] @ avcline 1681: {cmt: Set trim index to value 2 in range (0..15)}\n valid comment[ 7] @ avcline 1883: {gav('V_REF_D_C_RAW[02]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 7] @ avcline 1883: {calc('V_REF_D_C[02]', 'V_REF_D_C_RAW[02]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 7] @ avcline 1883: {log('V_REF_D_C[02]', '', '', 0, 0)}\n valid comment[ 8] @ avcline 1884: {cmt: Set trim index to value 3 in range (0..15)}\n valid comment[ 9] @ avcline 2086: {gav('V_REF_D_C_RAW[03]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 9] @ avcline 2086: {calc('V_REF_D_C[03]', 'V_REF_D_C_RAW[03]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 9] @ avcline 2086: {log('V_REF_D_C[03]', '', '', 0, 0)}\n valid comment[ 10] @ avcline 2087: {cmt: Set trim index to value 4 in range (0..15)}\n valid comment[ 11] @ avcline 2289: {gav('V_REF_D_C_RAW[04]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 11] @ avcline 2289: {calc('V_REF_D_C[04]', 'V_REF_D_C_RAW[04]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 11] @ avcline 2289: {log('V_REF_D_C[04]', '', '', 0, 0)}\n valid comment[ 12] @ avcline 2290: {cmt: Set trim index to value 5 in range (0..15)}\n valid comment[ 13] @ avcline 2492: {gav('V_REF_D_C_RAW[05]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 13] @ avcline 2492: {calc('V_REF_D_C[05]', 'V_REF_D_C_RAW[05]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 13] @ avcline 2492: {log('V_REF_D_C[05]', '', '', 0, 0)}\n valid comment[ 14] @ avcline 2493: {cmt: Set trim index to value 6 in range (0..15)}\n valid comment[ 15] @ avcline 2695: {gav('V_REF_D_C_RAW[06]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 15] @ avcline 2695: {calc('V_REF_D_C[06]', 'V_REF_D_C_RAW[06]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 15] @ avcline 2695: {log('V_REF_D_C[06]', '', '', 0, 0)}\n valid comment[ 16] @ avcline 2696: {cmt: Set trim index to value 7 in range (0..15)}\n valid comment[ 17] @ avcline 2898: {gav('V_REF_D_C_RAW[07]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 17] @ avcline 2898: {calc('V_REF_D_C[07]', 'V_REF_D_C_RAW[07]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 17] @ avcline 2898: {log('V_REF_D_C[07]', '', '', 0, 0)}\n valid comment[ 18] @ avcline 2899: {cmt: Set trim index to value 8 in range (0..15)}\n valid comment[ 19] @ avcline 3101: {gav('V_REF_D_C_RAW[08]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 19] @ avcline 3101: {calc('V_REF_D_C[08]', 'V_REF_D_C_RAW[08]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 19] @ avcline 3101: {log('V_REF_D_C[08]', '', '', 0, 0)}\n valid comment[ 20] @ avcline 3102: {cmt: Set trim index to value 9 in range (0..15)}\n valid comment[ 21] @ avcline 3304: {gav('V_REF_D_C_RAW[09]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 21] @ avcline 3304: {calc('V_REF_D_C[09]', 'V_REF_D_C_RAW[09]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 21] @ avcline 3304: {log('V_REF_D_C[09]', '', '', 0, 0)}\n valid comment[ 22] @ avcline 3305: {cmt: Set trim index to value 10 in range (0..15)}\n valid comment[ 23] @ avcline 3507: {gav('V_REF_D_C_RAW[10]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 23] @ avcline 3507: {calc('V_REF_D_C[10]', 'V_REF_D_C_RAW[10]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 23] @ avcline 3507: {log('V_REF_D_C[10]', '', '', 0, 0)}\n valid comment[ 24] @ avcline 3508: {cmt: Set trim index to value 11 in range (0..15)}\n valid comment[ 25] @ avcline 3710: {gav('V_REF_D_C_RAW[11]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 25] @ avcline 3710: {calc('V_REF_D_C[11]', 'V_REF_D_C_RAW[11]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 25] @ avcline 3710: {log('V_REF_D_C[11]', '', '', 0, 0)}\n valid comment[ 26] @ avcline 3711: {cmt: Set trim index to value 12 in range (0..15)}\n valid comment[ 27] @ avcline 3913: {gav('V_REF_D_C_RAW[12]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 27] @ avcline 3913: {calc('V_REF_D_C[12]', 'V_REF_D_C_RAW[12]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 27] @ avcline 3913: {log('V_REF_D_C[12]', '', '', 0, 0)}\n valid comment[ 28] @ avcline 3914: {cmt: Set trim index to value 13 in range (0..15)}\n valid comment[ 29] @ avcline 4116: {gav('V_REF_D_C_RAW[13]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 29] @ avcline 4116: {calc('V_REF_D_C[13]', 'V_REF_D_C_RAW[13]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 29] @ avcline 4116: {log('V_REF_D_C[13]', '', '', 0, 0)}\n valid comment[ 30] @ avcline 4117: {cmt: Set trim index to value 14 in range (0..15)}\n valid comment[ 31] @ avcline 4319: {gav('V_REF_D_C_RAW[14]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 31] @ avcline 4319: {calc('V_REF_D_C[14]', 'V_REF_D_C_RAW[14]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 31] @ avcline 4319: {log('V_REF_D_C[14]', '', '', 0, 0)}\n valid comment[ 32] @ avcline 4320: {cmt: Set trim index to value 15 in range (0..15)}\n valid comment[ 33] @ avcline 4522: {gav('V_REF_D_C_RAW[15]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 33] @ avcline 4522: {calc('V_REF_D_C[15]', 'V_REF_D_C_RAW[15]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 33] @ avcline 4522: {log('V_REF_D_C[15]', '', '', 0, 0)}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.digCap(\"digcapid_0\").vecVarOnly().pin(\"SDO\").capMode(TA::SER).bitPerWord(16).samples(1*16).execute();\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][3]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_REF_D_C_RAW_00//{gav('V_REF_D_C_RAW[00]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][5]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_REF_D_C_RAW_01//{gav('V_REF_D_C_RAW[01]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][7]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_REF_D_C_RAW_02//{gav('V_REF_D_C_RAW[02]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][9]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_REF_D_C_RAW_03//{gav('V_REF_D_C_RAW[03]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][11]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_REF_D_C_RAW_04//{gav('V_REF_D_C_RAW[04]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][13]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_REF_D_C_RAW_05//{gav('V_REF_D_C_RAW[05]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][15]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_REF_D_C_RAW_06//{gav('V_REF_D_C_RAW[06]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][17]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_REF_D_C_RAW_07//{gav('V_REF_D_C_RAW[07]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][19]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_REF_D_C_RAW_08//{gav('V_REF_D_C_RAW[08]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][21]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_REF_D_C_RAW_09//{gav('V_REF_D_C_RAW[09]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][23]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_REF_D_C_RAW_10//{gav('V_REF_D_C_RAW[10]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][25]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_REF_D_C_RAW_11//{gav('V_REF_D_C_RAW[11]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][27]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_REF_D_C_RAW_12//{gav('V_REF_D_C_RAW[12]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][29]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_REF_D_C_RAW_13//{gav('V_REF_D_C_RAW[13]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][31]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_REF_D_C_RAW_14//{gav('V_REF_D_C_RAW[14]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][33]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_REF_D_C_RAW_15//{gav('V_REF_D_C_RAW[15]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n aI_Captured_0 = rdi.id(\"digcapid_0\").getVector(\"SDO\");\n ARRAY_D ad_jsubresults_INT2; ad_jsubresults_INT2.resize(16); ad_jsubresults_INT2.init(-9.9);\n ARRAY_D ad_jsubresults_ASDX; ad_jsubresults_ASDX.resize(16); ad_jsubresults_ASDX.init(-9.9);\n ad_jsubresults_INT2 = rdi.id(\"dcid_0\").getMultiValue(\"INT2\");\n ad_jsubresults_ASDX = rdi.id(\"dcid_0\").getMultiValue(\"ASDX\");\n \n aI_Captured_0[0] = Switch_High_Low_Bits_16Bits(aI_Captured_0[0]);\n\n i_REG_VALUE[curSite] = aI_Captured_0[0];\n FuncPrint(\"REG_VALUE\",i_REG_VALUE[curSite]);\n\n for(int i=0; i<16; i++){\n d_V_REF_D_C_RAW[curSite][i] = ad_jsubresults_INT2[0 + i] - ad_jsubresults_ASDX[0 + i];\n FuncPrint(\"V_REF_D_C_RAW_\" + rdi.itos(curSite) + \"_\"+ rdi.itos(i) ,d_V_REF_D_C_RAW[curSite][i]);\n\n V_REF_D_C[curSite][i] = d_V_REF_D_C_RAW[curSite][i] - V_OFF1_ECOFF[curSite];\n FuncPrint(\"V_REF_D_C\"+rdi.itos(i) ,V_REF_D_C[curSite][i]);\n\n }\n\n for(int i=0; i < 16; i++){ \n }\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n\n /* Ori key coments in subpat1 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 4531: {wri('ANA_TRM_PMU', 'REG_VALUE')}\n valid comment[ 1] @ avcline 5570: {Test End: T10_03_Standby_Regulator_Char}\n */\n static int i_vec_iposition1[32] = {\n 31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,\n 48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63\n };\n for (int i = 0; i < 32; i++)\n {\n i_vec_Num1[i] = i_vec_iposition1[i];\n }\n FOR_EACH_SITE_BEGIN();\n i_WRITE_BACK[curSite] = Switch_High_Low_Bits_16Bits(i_REG_VALUE[curSite]);\n Func_Vector_Dynamic_Write(s_splited_pat_name[1], \"SDX\", i_vec_Num1, 32, i_WRITE_BACK[curSite], 0, 2); //Notes. TEI check per project\n //TODO pl.TEI check position & mask\n FOR_EACH_SITE_END();\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id1\");\n rdi.func().label(s_splited_pat_name[1]).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes1[curSite] = rdi.id(\"burst_id1\").getBurstPassFail();\n FuncPrint(\"REG_VALUE\", i_REG_VALUE[curSite]);\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n\n }\n\n ON_FIRST_INVOCATION_END();\n\n// TestLog(\"REG_VALUE\",i_REG_VALUE[curSite]);\n for(int i=0; i < 16; i++) {\n TestLog(s_Func_Test_Name_Add_2Num(\"V_REF_D_C_\", i), V_REF_D_C[curSite][i]);\n }\n i_funcRes[curSite] = i_funcRes0[curSite] && i_funcRes1[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T10_03_Standby_Regulator_Char_V2\", T10_03_Standby_Regulator_Char_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 2 $ $Author: laj1mu23 $ $Date: 2024/03/25 20:34:28 GMT $')\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_CONF', 0x0001) # Enable TB1\nwac('TM_PIN', 0x0095) # Enable ANAIO1/2; TB1_OUT on ANAIO1; TB2_INP on ANAIO2\nwac('TM_ADDR', 0x010d) # Enable power block on ATM; Connect VDDD_DC/VSS\ndly(100e-6)\ngav('V_DDD_DC_T_RAW', 'INT2', 'ASDX')\ncalc('V_DDD_DC_T', 'V_DDD_DC_T_RAW', '-', 'V_OFF1_ECOFF')\nlog('V_DDD_DC_T')\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T10_04_VDDD_DC_LDO_measurement_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n static double V_DDD_DC_T_RAW[xNSitES];\n static double V_DDD_DC_T[xNSitES];\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T10_04_VDDD_DC_LDO_measurement_V2_PAT_id\");\n rdi.dc(\"T10_04_VDDD_DC_LDO_measurement_V2DC_id0\").label(s_label_name)\n .insertSub(i_comment_line0[0]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms) //V_DDD_DC_T_RAW\n .execute();\n RDI_END();\n ON_FIRST_INVOCATION_END();\n\n ARRAY_D JSUB_results_ASDX;\n JSUB_results_ASDX = rdi.id(\"T10_04_VDDD_DC_LDO_measurement_V2DC_id0\").getMultiValue(\"ASDX\");\n ARRAY_D JSUB_results_INT2;\n JSUB_results_INT2 = rdi.id(\"T10_04_VDDD_DC_LDO_measurement_V2DC_id0\").getMultiValue(\"INT2\");\n V_DDD_DC_T_RAW[CURRENT_SITE_NUMBER()-1] = JSUB_results_INT2[0] - JSUB_results_ASDX[0];\n V_DDD_DC_T[CURRENT_SITE_NUMBER()-1] = V_DDD_DC_T_RAW[CURRENT_SITE_NUMBER()-1] - V_OFF1_ECOFF[CURRENT_SITE_NUMBER()-1];\n\n FuncPrint(\"JSUB_results_ASDX\", JSUB_results_ASDX[0]);\n FuncPrint(\"JSUB_results_INT2\", JSUB_results_INT2[0]);\n FuncPrint(\"V_DDD_DC_T_RAW\", V_DDD_DC_T_RAW[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"V_DDD_DC_T\", V_DDD_DC_T[CURRENT_SITE_NUMBER()-1]);\n \n int Func_result = rdi.id(\"T10_04_VDDD_DC_LDO_measurement_V2_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"V_DDD_DC_T\", V_DDD_DC_T[CURRENT_SITE_NUMBER()-1]);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T10_04_VDDD_DC_LDO_measurement_V2\", T10_04_VDDD_DC_LDO_measurement_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 2 $ $Author: laj1mu23 $ $Date: 2024/03/25 20:34:28 GMT $')\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_CONF', 0x0001) # Enable TB1\nwac('TM_PIN', 0x0095) # Enable ANAIO1/2; TB1_OUT on ANAIO1; TB2_INP on ANAIO2\nwac('TM_ADDR', 0x030d) # Enable power block on ATM; Connect VDDD_DS/VSS\ndly(100e-6)\ngav('V_DDD_DS_T_RAW', 'INT2', 'ASDX')\ncalc('V_DDD_DS_T', 'V_DDD_DS_T_RAW', '-', 'V_OFF1_ECOFF')\nlog('V_DDD_DS_T')\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\n", "output": "/*****************************************************\n * T10_05_VDDD_DS_LDO_measurement_V2, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T10_05_VDDD_DS_LDO_measurement_V2: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static double d_V_DDD_DS_T_RAW[xNSitES], d_V_DDD_DS_T[xNSitES];\n static int i_funcRes0[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(d_V_DDD_DS_T_RAW, 9.9, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T10_05_VDDD_DS_LDO_measurement}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 1] @ avcline 788: {gav('V_DDD_DS_T_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 1] @ avcline 788: {calc('V_DDD_DS_T', 'V_DDD_DS_T_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 1] @ avcline 788: {log('V_DDD_DS_T', '', '', 0, 0)}\n valid comment[ 2] @ avcline 1365: {Test End: T10_05_VDDD_DS_LDO_measurement}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][1]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_DDD_DS_T_RAW//{gav('V_DDD_DS_T_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n ARRAY_D ad_jsubresults_INT2; ad_jsubresults_INT2.resize(1); ad_jsubresults_INT2.init(-9.9);\n ARRAY_D ad_jsubresults_ASDX; ad_jsubresults_ASDX.resize(1); ad_jsubresults_ASDX.init(-9.9);\n ad_jsubresults_INT2 = rdi.id(\"dcid_0\").getMultiValue(\"INT2\");\n ad_jsubresults_ASDX = rdi.id(\"dcid_0\").getMultiValue(\"ASDX\");\n \n d_V_DDD_DS_T[curSite] = ad_jsubresults_INT2[0] - ad_jsubresults_ASDX[0] - V_OFF1_ECOFF[curSite];\n \t\t FuncPrint(\"ad_jsubresults_INT2\", ad_jsubresults_INT2[0]);\n \t\t FuncPrint(\"ad_jsubresults_ASDX\", ad_jsubresults_ASDX[0]);\n// \t\t FuncPrint(\"d_V_DDD_DS_T_RAW\", d_V_DDD_DS_T_RAW[CURRENT_SITE_NUMBER()-1]);\n \t\t FuncPrint(\"d_V_DDD_DS_T\", d_V_DDD_DS_T[CURRENT_SITE_NUMBER()-1]);\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n\n ON_FIRST_INVOCATION_END();\n\n int Func_result = rdi.id(\"burst_id0\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"V_DDD_DS_T\", d_V_DDD_DS_T[CURRENT_SITE_NUMBER()-1]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T10_05_VDDD_DS_LDO_measurement_V2\", T10_05_VDDD_DS_LDO_measurement_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: bai430aa_rel/1 $ $Author: hmf1rt $ $Date: 2024/08/07 15:18:41 GMT $')\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_CONF', 0x0001) # Enable TB1\nwac('TM_PIN', 0x0095) # Enable ANAIO1/2; TB1_OUT on ANAIO1; TB2_INP on ANAIO2\nwac('TM_ADDR', 0x010d) # Enable power block on ATM; Connect VDDD_DC/VSS\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('OCP_MASK', 0x000f) # Set masking register\nras('REG_VALUE', 'ANA_TRM_PMU') # Store the current value\nfor n in range (0, 16, 1):\n cmt('Set trim index to value {} in range (0..15)'.format(n))\n wr('ANA_TRM_PMU', n) # pc_trm_vref_dc\n rac('ANA_TRM_PMU', n, 0x000f) # Check register setting\n dly(100e-6)\n gav('V_DDD_DC_C_RAW[{:02d}]'.format(n), 'INT2', 'ASDX')\n calc('V_DDD_DC_C[{:02d}]'.format(n), 'V_DDD_DC_C_RAW[{:02d}]'.format(n), '-', 'V_OFF1_ECOFF')\n log('V_DDD_DC_C[{:02d}]'.format(n))\ndly(592e-9)\nwri('ANA_TRM_PMU', 'REG_VALUE') # Write back the stored value\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\n", "output": "/*****************************************************\n * T10_06_VDDD_DC_LDO_Char_R1, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n * JSH5SGH: fix some bugs.\n * JSH5SGH: pattern update to R1.\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T10_06_VDDD_DC_LDO_Char_R1: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 2;\n vector i_comment_line[i_split_count];\n\n static int i_REG_VALUE[xNSitES];\n ARRAY_I aI_Captured_0;\n static double d_V_DDD_DC_C_RAW[xNSitES][16];\n static double V_DDD_DC_C[xNSitES][16];\n ARRAY_D ad_V_DDD_DC_C_RAW;\n\n static int i_WRITE_BACK[xNSitES];\n static int i_vec_Num1[32] = {0};\n static int i_funcRes0[xNSitES], i_funcRes1[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(i_REG_VALUE, 9, xNSitES);\n \n //!\"CTmsg: cut pattern to 2 parts @ oriAVCvecline [4531]\n //!\"CTmsg: cut pattern to 2 parts @ binarypatline [4521]\n if (i_split_pat_flag)\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n }\n else\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n for(int i=0; i }\n valid comment[ 1] @ avcline 1162: {ras('REG_VALUE', 'ANA_TRM_PMU')}\n valid comment[ 2] @ avcline 1275: {cmt: Set trim index to value 0 in range (0..15)}\n valid comment[ 3] @ avcline 1477: {gav('V_DDD_DC_C_RAW[00]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 3] @ avcline 1477: {calc('V_DDD_DC_C[00]', 'V_DDD_DC_C_RAW[00]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 3] @ avcline 1477: {log('V_DDD_DC_C[00]', '', '', 0, 0)}\n valid comment[ 4] @ avcline 1478: {cmt: Set trim index to value 1 in range (0..15)}\n valid comment[ 5] @ avcline 1680: {gav('V_DDD_DC_C_RAW[01]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 5] @ avcline 1680: {calc('V_DDD_DC_C[01]', 'V_DDD_DC_C_RAW[01]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 5] @ avcline 1680: {log('V_DDD_DC_C[01]', '', '', 0, 0)}\n valid comment[ 6] @ avcline 1681: {cmt: Set trim index to value 2 in range (0..15)}\n valid comment[ 7] @ avcline 1883: {gav('V_DDD_DC_C_RAW[02]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 7] @ avcline 1883: {calc('V_DDD_DC_C[02]', 'V_DDD_DC_C_RAW[02]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 7] @ avcline 1883: {log('V_DDD_DC_C[02]', '', '', 0, 0)}\n valid comment[ 8] @ avcline 1884: {cmt: Set trim index to value 3 in range (0..15)}\n valid comment[ 9] @ avcline 2086: {gav('V_DDD_DC_C_RAW[03]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 9] @ avcline 2086: {calc('V_DDD_DC_C[03]', 'V_DDD_DC_C_RAW[03]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 9] @ avcline 2086: {log('V_DDD_DC_C[03]', '', '', 0, 0)}\n valid comment[ 10] @ avcline 2087: {cmt: Set trim index to value 4 in range (0..15)}\n valid comment[ 11] @ avcline 2289: {gav('V_DDD_DC_C_RAW[04]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 11] @ avcline 2289: {calc('V_DDD_DC_C[04]', 'V_DDD_DC_C_RAW[04]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 11] @ avcline 2289: {log('V_DDD_DC_C[04]', '', '', 0, 0)}\n valid comment[ 12] @ avcline 2290: {cmt: Set trim index to value 5 in range (0..15)}\n valid comment[ 13] @ avcline 2492: {gav('V_DDD_DC_C_RAW[05]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 13] @ avcline 2492: {calc('V_DDD_DC_C[05]', 'V_DDD_DC_C_RAW[05]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 13] @ avcline 2492: {log('V_DDD_DC_C[05]', '', '', 0, 0)}\n valid comment[ 14] @ avcline 2493: {cmt: Set trim index to value 6 in range (0..15)}\n valid comment[ 15] @ avcline 2695: {gav('V_DDD_DC_C_RAW[06]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 15] @ avcline 2695: {calc('V_DDD_DC_C[06]', 'V_DDD_DC_C_RAW[06]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 15] @ avcline 2695: {log('V_DDD_DC_C[06]', '', '', 0, 0)}\n valid comment[ 16] @ avcline 2696: {cmt: Set trim index to value 7 in range (0..15)}\n valid comment[ 17] @ avcline 2898: {gav('V_DDD_DC_C_RAW[07]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 17] @ avcline 2898: {calc('V_DDD_DC_C[07]', 'V_DDD_DC_C_RAW[07]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 17] @ avcline 2898: {log('V_DDD_DC_C[07]', '', '', 0, 0)}\n valid comment[ 18] @ avcline 2899: {cmt: Set trim index to value 8 in range (0..15)}\n valid comment[ 19] @ avcline 3101: {gav('V_DDD_DC_C_RAW[08]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 19] @ avcline 3101: {calc('V_DDD_DC_C[08]', 'V_DDD_DC_C_RAW[08]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 19] @ avcline 3101: {log('V_DDD_DC_C[08]', '', '', 0, 0)}\n valid comment[ 20] @ avcline 3102: {cmt: Set trim index to value 9 in range (0..15)}\n valid comment[ 21] @ avcline 3304: {gav('V_DDD_DC_C_RAW[09]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 21] @ avcline 3304: {calc('V_DDD_DC_C[09]', 'V_DDD_DC_C_RAW[09]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 21] @ avcline 3304: {log('V_DDD_DC_C[09]', '', '', 0, 0)}\n valid comment[ 22] @ avcline 3305: {cmt: Set trim index to value 10 in range (0..15)}\n valid comment[ 23] @ avcline 3507: {gav('V_DDD_DC_C_RAW[10]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 23] @ avcline 3507: {calc('V_DDD_DC_C[10]', 'V_DDD_DC_C_RAW[10]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 23] @ avcline 3507: {log('V_DDD_DC_C[10]', '', '', 0, 0)}\n valid comment[ 24] @ avcline 3508: {cmt: Set trim index to value 11 in range (0..15)}\n valid comment[ 25] @ avcline 3710: {gav('V_DDD_DC_C_RAW[11]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 25] @ avcline 3710: {calc('V_DDD_DC_C[11]', 'V_DDD_DC_C_RAW[11]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 25] @ avcline 3710: {log('V_DDD_DC_C[11]', '', '', 0, 0)}\n valid comment[ 26] @ avcline 3711: {cmt: Set trim index to value 12 in range (0..15)}\n valid comment[ 27] @ avcline 3913: {gav('V_DDD_DC_C_RAW[12]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 27] @ avcline 3913: {calc('V_DDD_DC_C[12]', 'V_DDD_DC_C_RAW[12]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 27] @ avcline 3913: {log('V_DDD_DC_C[12]', '', '', 0, 0)}\n valid comment[ 28] @ avcline 3914: {cmt: Set trim index to value 13 in range (0..15)}\n valid comment[ 29] @ avcline 4116: {gav('V_DDD_DC_C_RAW[13]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 29] @ avcline 4116: {calc('V_DDD_DC_C[13]', 'V_DDD_DC_C_RAW[13]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 29] @ avcline 4116: {log('V_DDD_DC_C[13]', '', '', 0, 0)}\n valid comment[ 30] @ avcline 4117: {cmt: Set trim index to value 14 in range (0..15)}\n valid comment[ 31] @ avcline 4319: {gav('V_DDD_DC_C_RAW[14]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 31] @ avcline 4319: {calc('V_DDD_DC_C[14]', 'V_DDD_DC_C_RAW[14]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 31] @ avcline 4319: {log('V_DDD_DC_C[14]', '', '', 0, 0)}\n valid comment[ 32] @ avcline 4320: {cmt: Set trim index to value 15 in range (0..15)}\n valid comment[ 33] @ avcline 4522: {gav('V_DDD_DC_C_RAW[15]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 33] @ avcline 4522: {calc('V_DDD_DC_C[15]', 'V_DDD_DC_C_RAW[15]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 33] @ avcline 4522: {log('V_DDD_DC_C[15]', '', '', 0, 0)}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.digCap(\"digcapid_0\").vecVarOnly().pin(\"SDO\").capMode(TA::SER).bitPerWord(16).samples(1*16).execute();\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][3]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_DDD_DC_C_RAW_00//{gav('V_DDD_DC_C_RAW[00]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][5]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_DDD_DC_C_RAW_01//{gav('V_DDD_DC_C_RAW[01]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][7]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_DDD_DC_C_RAW_02//{gav('V_DDD_DC_C_RAW[02]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][9]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_DDD_DC_C_RAW_03//{gav('V_DDD_DC_C_RAW[03]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][11]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_DDD_DC_C_RAW_04//{gav('V_DDD_DC_C_RAW[04]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][13]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_DDD_DC_C_RAW_05//{gav('V_DDD_DC_C_RAW[05]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][15]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_DDD_DC_C_RAW_06//{gav('V_DDD_DC_C_RAW[06]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][17]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_DDD_DC_C_RAW_07//{gav('V_DDD_DC_C_RAW[07]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][19]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_DDD_DC_C_RAW_08//{gav('V_DDD_DC_C_RAW[08]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][21]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_DDD_DC_C_RAW_09//{gav('V_DDD_DC_C_RAW[09]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][23]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_DDD_DC_C_RAW_10//{gav('V_DDD_DC_C_RAW[10]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][25]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_DDD_DC_C_RAW_11//{gav('V_DDD_DC_C_RAW[11]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][27]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_DDD_DC_C_RAW_12//{gav('V_DDD_DC_C_RAW[12]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][29]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_DDD_DC_C_RAW_13//{gav('V_DDD_DC_C_RAW[13]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][31]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_DDD_DC_C_RAW_14//{gav('V_DDD_DC_C_RAW[14]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][33]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_DDD_DC_C_RAW_15//{gav('V_DDD_DC_C_RAW[15]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n aI_Captured_0 = rdi.id(\"digcapid_0\").getVector(\"SDO\");\n ARRAY_D ad_jsubresults_INT2; ad_jsubresults_INT2.resize(16); ad_jsubresults_INT2.init(-9.9);\n ARRAY_D ad_jsubresults_ASDX; ad_jsubresults_ASDX.resize(16); ad_jsubresults_ASDX.init(-9.9);\n ad_jsubresults_INT2 = rdi.id(\"dcid_0\").getMultiValue(\"INT2\");\n ad_jsubresults_ASDX = rdi.id(\"dcid_0\").getMultiValue(\"ASDX\");\n \n aI_Captured_0[0] = Switch_High_Low_Bits_16Bits(aI_Captured_0[0]);\n i_REG_VALUE[curSite] = aI_Captured_0[0];\n FuncPrint(\"REG_VALUE\",i_REG_VALUE[curSite]);\n\n for(int i=0; i<16; i++){\n d_V_DDD_DC_C_RAW[curSite][i] = ad_jsubresults_INT2[0 + i] - ad_jsubresults_ASDX[0 + i];\n FuncPrint(\"V_DDD_DC_C_RAW_\" + rdi.itos(curSite) + \"_\"+ rdi.itos(i) ,d_V_DDD_DC_C_RAW[curSite][i]);\n V_DDD_DC_C[curSite][i] = d_V_DDD_DC_C_RAW[curSite][i] - V_OFF1_ECOFF[curSite];\n FuncPrint(\"V_DDD_DC_C_\"+rdi.itos(i) ,V_DDD_DC_C[curSite][i]);\n\t\t\t }\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n\n /* Ori key coments in subpat1 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 4531: {wri('ANA_TRM_PMU', 'REG_VALUE')}\n valid comment[ 1] @ avcline 5378: {Test End: T10_06_VDDD_DC_LDO_Char}\n */\n static int i_vec_iposition1[32] = {\n\t\t\t 31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,\n\t\t\t 48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63\n };\n for (int i = 0; i < 32; i++)\n\t\t {\n\t\t\t i_vec_Num1[i] = i_vec_iposition1[i];\n\t\t }\n FOR_EACH_SITE_BEGIN();\n i_WRITE_BACK[curSite] = Switch_High_Low_Bits_16Bits(i_REG_VALUE[curSite]);\n Func_Vector_Dynamic_Write(s_splited_pat_name[1], \"SDX\", i_vec_Num1, 32, i_WRITE_BACK[curSite], 0, 2); //Notes. TEI check per project\n\n FOR_EACH_SITE_END();\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id1\");\n rdi.func().label(s_splited_pat_name[1]).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes1[curSite] = rdi.id(\"burst_id1\").getBurstPassFail();\n FuncPrint(\"REG_VALUE\", i_REG_VALUE[curSite]);\n\n FOR_EACH_SITE_END();\n\n\n }\n\n ON_FIRST_INVOCATION_END();\n\n for(int i=0; i < 16; i++){ \n TestLog(s_Func_Test_Name_Add_2Num(\"V_DDD_DC_C_\", i), V_DDD_DC_C[curSite][i]);\n\t }\n\n i_funcRes[curSite] = i_funcRes0[curSite] && i_funcRes1[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T10_06_VDDD_DC_LDO_Char_R1\", T10_06_VDDD_DC_LDO_Char_R1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: bai430aa_rel/1 $ $Author: hmf1rt $ $Date: 2024/08/07 15:18:41 GMT $')\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_CONF', 0x0001) # Enable TB1\nwac('TM_PIN', 0x0095) # Enable ANAIO1/2; TB1_OUT on ANAIO1; TB2_INP on ANAIO2\nwac('TM_ADDR', 0x030d) # Enable power block on ATM; Connect VDDD_DS/VSS\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('OCP_MASK', 0x000f) # Set masking register\nras('REG_VALUE', 'ANA_TRM_PMU') # Store the current value\nfor n in range (0, 16, 1):\n cmt('Set trim index to value {} in range (0..15)'.format(n))\n wr('ANA_TRM_PMU', n) # pc_trm_vref_dc\n rac('ANA_TRM_PMU', n, 0x000f) # Check register setting\n dly(100e-6)\n gav('V_DDD_DS_C_RAW[{:02d}]'.format(n), 'INT2', 'ASDX')\n calc('V_DDD_DS_C[{:02d}]'.format(n), 'V_DDD_DS_C_RAW[{:02d}]'.format(n), '-', 'V_OFF1_ECOFF')\n log('V_DDD_DS_C[{:02d}]'.format(n))\ndly(592e-9)\nwri('ANA_TRM_PMU', 'REG_VALUE') # Write back the stored value\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\n", "output": "/*****************************************************\n * T10_07_VDDD_DS_LDO_Char_R1, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n * JSH5SGH: fix some bugs.\n * JSH5SGH: pattern update to R1.\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T10_07_VDDD_DS_LDO_Char_R1: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 2;\n vector i_comment_line[i_split_count];\n\n static int i_REG_VALUE[xNSitES];\n ARRAY_I aI_Captured_0;\n static double d_V_DDD_DS_C_RAW[xNSitES][16];\n static double V_DDD_DS_C[xNSitES][16];\n ARRAY_D ad_V_DDD_DS_C_RAW;\n\n static int i_WRITE_BACK[xNSitES];\n static int i_vec_Num1[32] = {0};\n static int i_funcRes0[xNSitES], i_funcRes1[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(i_REG_VALUE, 9, xNSitES);\n \n //!\"CTmsg: cut pattern to 2 parts @ oriAVCvecline [4531]\n //!\"CTmsg: cut pattern to 2 parts @ binarypatline [4521]\n if (i_split_pat_flag)\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n }\n else\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n for(int i=0; i }\n valid comment[ 1] @ avcline 1162: {ras('REG_VALUE', 'ANA_TRM_PMU')}\n valid comment[ 2] @ avcline 1275: {cmt: Set trim index to value 0 in range (0..15)}\n valid comment[ 3] @ avcline 1477: {gav('V_DDD_DS_C_RAW[00]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 3] @ avcline 1477: {calc('V_DDD_DS_C[00]', 'V_DDD_DS_C_RAW[00]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 3] @ avcline 1477: {log('V_DDD_DS_C[00]', '', '', 0, 0)}\n valid comment[ 4] @ avcline 1478: {cmt: Set trim index to value 1 in range (0..15)}\n valid comment[ 5] @ avcline 1680: {gav('V_DDD_DS_C_RAW[01]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 5] @ avcline 1680: {calc('V_DDD_DS_C[01]', 'V_DDD_DS_C_RAW[01]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 5] @ avcline 1680: {log('V_DDD_DS_C[01]', '', '', 0, 0)}\n valid comment[ 6] @ avcline 1681: {cmt: Set trim index to value 2 in range (0..15)}\n valid comment[ 7] @ avcline 1883: {gav('V_DDD_DS_C_RAW[02]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 7] @ avcline 1883: {calc('V_DDD_DS_C[02]', 'V_DDD_DS_C_RAW[02]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 7] @ avcline 1883: {log('V_DDD_DS_C[02]', '', '', 0, 0)}\n valid comment[ 8] @ avcline 1884: {cmt: Set trim index to value 3 in range (0..15)}\n valid comment[ 9] @ avcline 2086: {gav('V_DDD_DS_C_RAW[03]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 9] @ avcline 2086: {calc('V_DDD_DS_C[03]', 'V_DDD_DS_C_RAW[03]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 9] @ avcline 2086: {log('V_DDD_DS_C[03]', '', '', 0, 0)}\n valid comment[ 10] @ avcline 2087: {cmt: Set trim index to value 4 in range (0..15)}\n valid comment[ 11] @ avcline 2289: {gav('V_DDD_DS_C_RAW[04]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 11] @ avcline 2289: {calc('V_DDD_DS_C[04]', 'V_DDD_DS_C_RAW[04]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 11] @ avcline 2289: {log('V_DDD_DS_C[04]', '', '', 0, 0)}\n valid comment[ 12] @ avcline 2290: {cmt: Set trim index to value 5 in range (0..15)}\n valid comment[ 13] @ avcline 2492: {gav('V_DDD_DS_C_RAW[05]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 13] @ avcline 2492: {calc('V_DDD_DS_C[05]', 'V_DDD_DS_C_RAW[05]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 13] @ avcline 2492: {log('V_DDD_DS_C[05]', '', '', 0, 0)}\n valid comment[ 14] @ avcline 2493: {cmt: Set trim index to value 6 in range (0..15)}\n valid comment[ 15] @ avcline 2695: {gav('V_DDD_DS_C_RAW[06]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 15] @ avcline 2695: {calc('V_DDD_DS_C[06]', 'V_DDD_DS_C_RAW[06]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 15] @ avcline 2695: {log('V_DDD_DS_C[06]', '', '', 0, 0)}\n valid comment[ 16] @ avcline 2696: {cmt: Set trim index to value 7 in range (0..15)}\n valid comment[ 17] @ avcline 2898: {gav('V_DDD_DS_C_RAW[07]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 17] @ avcline 2898: {calc('V_DDD_DS_C[07]', 'V_DDD_DS_C_RAW[07]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 17] @ avcline 2898: {log('V_DDD_DS_C[07]', '', '', 0, 0)}\n valid comment[ 18] @ avcline 2899: {cmt: Set trim index to value 8 in range (0..15)}\n valid comment[ 19] @ avcline 3101: {gav('V_DDD_DS_C_RAW[08]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 19] @ avcline 3101: {calc('V_DDD_DS_C[08]', 'V_DDD_DS_C_RAW[08]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 19] @ avcline 3101: {log('V_DDD_DS_C[08]', '', '', 0, 0)}\n valid comment[ 20] @ avcline 3102: {cmt: Set trim index to value 9 in range (0..15)}\n valid comment[ 21] @ avcline 3304: {gav('V_DDD_DS_C_RAW[09]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 21] @ avcline 3304: {calc('V_DDD_DS_C[09]', 'V_DDD_DS_C_RAW[09]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 21] @ avcline 3304: {log('V_DDD_DS_C[09]', '', '', 0, 0)}\n valid comment[ 22] @ avcline 3305: {cmt: Set trim index to value 10 in range (0..15)}\n valid comment[ 23] @ avcline 3507: {gav('V_DDD_DS_C_RAW[10]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 23] @ avcline 3507: {calc('V_DDD_DS_C[10]', 'V_DDD_DS_C_RAW[10]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 23] @ avcline 3507: {log('V_DDD_DS_C[10]', '', '', 0, 0)}\n valid comment[ 24] @ avcline 3508: {cmt: Set trim index to value 11 in range (0..15)}\n valid comment[ 25] @ avcline 3710: {gav('V_DDD_DS_C_RAW[11]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 25] @ avcline 3710: {calc('V_DDD_DS_C[11]', 'V_DDD_DS_C_RAW[11]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 25] @ avcline 3710: {log('V_DDD_DS_C[11]', '', '', 0, 0)}\n valid comment[ 26] @ avcline 3711: {cmt: Set trim index to value 12 in range (0..15)}\n valid comment[ 27] @ avcline 3913: {gav('V_DDD_DS_C_RAW[12]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 27] @ avcline 3913: {calc('V_DDD_DS_C[12]', 'V_DDD_DS_C_RAW[12]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 27] @ avcline 3913: {log('V_DDD_DS_C[12]', '', '', 0, 0)}\n valid comment[ 28] @ avcline 3914: {cmt: Set trim index to value 13 in range (0..15)}\n valid comment[ 29] @ avcline 4116: {gav('V_DDD_DS_C_RAW[13]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 29] @ avcline 4116: {calc('V_DDD_DS_C[13]', 'V_DDD_DS_C_RAW[13]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 29] @ avcline 4116: {log('V_DDD_DS_C[13]', '', '', 0, 0)}\n valid comment[ 30] @ avcline 4117: {cmt: Set trim index to value 14 in range (0..15)}\n valid comment[ 31] @ avcline 4319: {gav('V_DDD_DS_C_RAW[14]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 31] @ avcline 4319: {calc('V_DDD_DS_C[14]', 'V_DDD_DS_C_RAW[14]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 31] @ avcline 4319: {log('V_DDD_DS_C[14]', '', '', 0, 0)}\n valid comment[ 32] @ avcline 4320: {cmt: Set trim index to value 15 in range (0..15)}\n valid comment[ 33] @ avcline 4522: {gav('V_DDD_DS_C_RAW[15]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 33] @ avcline 4522: {calc('V_DDD_DS_C[15]', 'V_DDD_DS_C_RAW[15]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 33] @ avcline 4522: {log('V_DDD_DS_C[15]', '', '', 0, 0)}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.digCap(\"digcapid_0\").vecVarOnly().pin(\"SDO\").capMode(TA::SER).bitPerWord(16).samples(1*16).execute();\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][3]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_DDD_DS_C_RAW_00//{gav('V_DDD_DS_C_RAW[00]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][5]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_DDD_DS_C_RAW_01//{gav('V_DDD_DS_C_RAW[01]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][7]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_DDD_DS_C_RAW_02//{gav('V_DDD_DS_C_RAW[02]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][9]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_DDD_DS_C_RAW_03//{gav('V_DDD_DS_C_RAW[03]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][11]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_DDD_DS_C_RAW_04//{gav('V_DDD_DS_C_RAW[04]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][13]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_DDD_DS_C_RAW_05//{gav('V_DDD_DS_C_RAW[05]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][15]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_DDD_DS_C_RAW_06//{gav('V_DDD_DS_C_RAW[06]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][17]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_DDD_DS_C_RAW_07//{gav('V_DDD_DS_C_RAW[07]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][19]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_DDD_DS_C_RAW_08//{gav('V_DDD_DS_C_RAW[08]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][21]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_DDD_DS_C_RAW_09//{gav('V_DDD_DS_C_RAW[09]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][23]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_DDD_DS_C_RAW_10//{gav('V_DDD_DS_C_RAW[10]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][25]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_DDD_DS_C_RAW_11//{gav('V_DDD_DS_C_RAW[11]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][27]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_DDD_DS_C_RAW_12//{gav('V_DDD_DS_C_RAW[12]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][29]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_DDD_DS_C_RAW_13//{gav('V_DDD_DS_C_RAW[13]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][31]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_DDD_DS_C_RAW_14//{gav('V_DDD_DS_C_RAW[14]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][33]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_DDD_DS_C_RAW_15//{gav('V_DDD_DS_C_RAW[15]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n aI_Captured_0 = rdi.id(\"digcapid_0\").getVector(\"SDO\");\n ARRAY_D ad_jsubresults_INT2; ad_jsubresults_INT2.resize(16); ad_jsubresults_INT2.init(-9.9);\n ARRAY_D ad_jsubresults_ASDX; ad_jsubresults_ASDX.resize(16); ad_jsubresults_ASDX.init(-9.9);\n ad_jsubresults_INT2 = rdi.id(\"dcid_0\").getMultiValue(\"INT2\");\n ad_jsubresults_ASDX = rdi.id(\"dcid_0\").getMultiValue(\"ASDX\");\n \n aI_Captured_0[0] = Switch_High_Low_Bits_16Bits(aI_Captured_0[0]);\n i_REG_VALUE[curSite] = aI_Captured_0[0];\n FuncPrint(\"REG_VALUE\",i_REG_VALUE[curSite]);\n\n for(int i=0; i<16; i++){\n d_V_DDD_DS_C_RAW[curSite][i] = ad_jsubresults_INT2[0 + i] - ad_jsubresults_ASDX[0 + i];\n FuncPrint(\"V_DDD_DS_C_RAW_\" + rdi.itos(curSite) + \"_\"+ rdi.itos(i) ,d_V_DDD_DS_C_RAW[curSite][i]);\n V_DDD_DS_C[curSite][i] = d_V_DDD_DS_C_RAW[curSite][i] - V_OFF1_ECOFF[curSite];\n FuncPrint(\"V_DDD_DS_C_\"+ rdi.itos(i) ,V_DDD_DS_C[curSite][i]);\n \t\t\t }\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n\n /* Ori key coments in subpat1 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 4531: {wri('ANA_TRM_PMU', 'REG_VALUE')}\n valid comment[ 1] @ avcline 5378: {Test End: T10_07_VDDD_DS_LDO_Char}\n */\n static int i_vec_iposition1[32] = {\n\t\t\t 31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,\n\t\t\t 48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63\n };\n for (int i = 0; i < 32; i++)\n\t\t {\n\t\t\t i_vec_Num1[i] = i_vec_iposition1[i];\n\t\t }\n FOR_EACH_SITE_BEGIN();\n i_WRITE_BACK[curSite] = Switch_High_Low_Bits_16Bits(i_REG_VALUE[curSite]);\n Func_Vector_Dynamic_Write(s_splited_pat_name[1], \"SDX\", i_vec_Num1, 32, i_WRITE_BACK[curSite], 0, 2); //Notes. TEI check per project\n\n FOR_EACH_SITE_END();\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id1\");\n rdi.func().label(s_splited_pat_name[1]).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes1[curSite] = rdi.id(\"burst_id1\").getBurstPassFail();\n FOR_EACH_SITE_END();\n\n\n }\n\n ON_FIRST_INVOCATION_END();\n\n for(int i=0; i < 16; i++){\n TestLog(s_Func_Test_Name_Add_2Num(\"V_DDD_DS_C_\", i), V_DDD_DS_C[curSite][i]);\n\t }\n\n i_funcRes[curSite] = i_funcRes0[curSite] && i_funcRes1[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T10_07_VDDD_DS_LDO_Char_R1\", T10_07_VDDD_DS_LDO_Char_R1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: ACC bandgap trimming\n# - VSS_A to ANAIO1, VERF_AA to ANAIO2 with buffer 2 enabled only\n#############################################################################################################\nfrom test_sub_functions import *\ncmt('Version info: $Revision: 4 $ $Author: hmf1rt $ $Date: 2024/04/19 15:13:09 GMT $')\n# Config Buffer, TM_CONF\nwac('EXT_MODE', 0xc00f) # Page Test, Reg TM_CONF \nwcb('tm_buf_pwrup',0x1) # Enable TB1 only\nwcb('tm_bus_inv',0x1) # Invert tset bus\n# Config ANAIO pad, TM_PIN\nwcb('tm_int2_en',0x1)\nwcb('tm_int2_sel',0x2) # TB1OUT on anaio1\nwcb('tm_asdx_en',0x1)\nwcb('tm_asdx_sel',0x4) # TB2IN on anaio2\n# Config CTB_P/N, TM_ADDR\nwcb('tm_cfg', 0x6) # CTB_P is VSS_A, CTP_N is VREF_AA\nwcb('tm_addr', 0xe) \n# Trim loop\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('OCP_MASK', 0x01f0) # Set masking register\nfor n in range (0, 32, 1):\n cmt('Set trim index to value {} in range (0..31)'.format(n))\n wr('ANA_TRM_BG', n*16) # ANA_TRM_BG<8:4> pc_trm_bgp_vra\n rac('ANA_TRM_BG', n*16, 0x01f0)\n uclk('ASCX')\n bw('ASCX', 1)\n dly(1352*74e-9)\n gav('V_VBG_ACC_RAW[{:02d}]'.format(n), 'INT2', 'ASDX') \n calc('V_VBG_ACC[{:02d}]'.format(n), 'V_VBG_ACC_RAW[{:02d}]'.format(n), '-', 'V_OFF1_ECON')\n log(f'V_VBG_ACC[{n:02}]')\n ubw('ASCX')\n clk('ASCX', 1/148e-9)\t\noti('N_OPT_VBG_ACC', 'V_VBG_ACC', 0.75) # Select optimum trim index\nlog('N_OPT_VBG_ACC')\notv('V_OPT_VBG_ACC', 'V_VBG_ACC', 0.75) # Select optimum trim value\nlog('V_OPT_VBG_ACC')\ncalc('N_ANA_TRM_BG_WR','N_OPT_VBG_ACC','<<',4)\nwri('ANA_TRM_BG','N_ANA_TRM_BG_WR')\nras('N_ANA_TRM_BG_RD','ANA_TRM_BG')\ncalc('N_ANA_TRM_BG_RD_8_4','N_ANA_TRM_BG_RD','&',0x01f0)\ncalc('N_OPT_VBG_ACC_RD','N_ANA_TRM_BG_RD_8_4','>>',4)\nlog('N_OPT_VBG_ACC_RD')\ncmt('The test item is a functional fail if N_OPT_VBG_ACC_RD != N_OPT_VBG_ACC')\n# Clean\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T10_11_acc_bandgap_trimming_V4: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n INT split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &split_pat_flag);\n vector s_splited_pat_name;\n const int split_count = 2; // Alarm:: split_count need manual confirm.\n s_splited_pat_name.resize(split_count);\n vector i_comment_line[split_count];\n\n static int N_OPT_VBG_ACC[xNSitES];\n static double V_OPT_VBG_ACC[xNSitES];\n static int N_ANA_TRM_BG_RD[xNSitES];\n static double V_VBG_ACC_RAW[xNSitES][32];\n static double V_VBG_ACC[xNSitES][32];\n static int N_ANA_TRM_BG_WR[xNSitES], N_ANA_TRM_BG_RD_8_4[xNSitES], N_OPT_VBG_ACC_RD[xNSitES];\n\n ARRAY_LL N_ANA_TRM_BG_WR_rtv(xNSitES);\n const int Wri_Bit_Length = 33;\n const int Wri_Bit_Position = 31;\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n cout.precision(3);\n rdi.enableOre(oreFlag);\n rdi.oreFile(\"./ORE_Files/rdi_ore_T10_11_ACC_BANDGAP_TRIMMING.xml\");\n\n\t GET_TESTSUITE_NAME(test_name);\n\n\t if (split_pat_flag)\n\t {\n\t\t split_pattern(s_label_name,\"wri\",split_pat_flag,s_splited_pat_name);\n\t }\n\t else\n\t {\n\t\t for (int i = 0; i> 4;\n//\n int Func_result0 = rdi.id(\"T10_11_acc_bandgap_trimming_V4_PAT_id0\").getBurstPassFail();\n int Func_result1 = rdi.id(\"T10_11_acc_bandgap_trimming_V4_PAT_id1\").getBurstPassFail();\n FuncPrint(\"Func_result0\", Func_result0);\n FuncPrint(\"Func_result1\", Func_result1);\n int Func_result = 1 * Func_result0 * Func_result1;\n if ((N_OPT_VBG_ACC_RD[CURRENT_SITE_NUMBER()-1] & 0x1F) != N_OPT_VBG_ACC[CURRENT_SITE_NUMBER()-1]) Func_result=99;\n FuncPrint(\"N_OPT_VBG_ACC_RD\", N_OPT_VBG_ACC_RD[CURRENT_SITE_NUMBER()-1]& 0x1F);\n FuncPrint(\"N_OPT_VBG_ACC\", N_OPT_VBG_ACC[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n for (int i = 0; i<10; i++)\n {\n \t TestLog(\"V_VBG_ACC_0\"+rdi.itos(i), V_VBG_ACC[CURRENT_SITE_NUMBER()-1][i]);\n }\n for (int i = 10; i<32; i++)\n {\n \t TestLog(\"V_VBG_ACC_\"+rdi.itos(i), V_VBG_ACC[CURRENT_SITE_NUMBER()-1][i]);\n }\n\n TestLog(\"V_OPT_VBG_ACC\", V_OPT_VBG_ACC[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"N_OPT_VBG_ACC_RD\", N_OPT_VBG_ACC_RD[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"N_OPT_VBG_ACC\", N_OPT_VBG_ACC[CURRENT_SITE_NUMBER()-1]);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T10_11_acc_bandgap_trimming_V4\", T10_11_acc_bandgap_trimming_V4);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 2 $ $Author: laj1mu23 $ $Date: 2024/03/25 20:34:28 GMT $')\nwac('EXT_MODE', 0xc00f) # Switch to the TEST register page\nwac('TM_CONF', 0x0011) # tm_se_meas=0 tm_bus_inv=1 tm_buf_pwrup=1 (tbuf_tb1_on)\n # bus_inv. because the power_ana_test_multiplexor_refs provides VSS_A/VREF_AA\nwac('TM_PIN', 0x0095) # tm_asdx_sel=4 (BUF2_INP) tm_asdx_en=1 tm_int2_sel=2 (BUF1_OUT) tm_int2_en=1\nwac('TM_ADDR', 0x060e) # tm_cfg=6 (COM_TB2= VREF_AA, COM_TB1= VSS_A) tm_addr=e (tm_bus_sel=tm_addr(3:2)=3 (COM_TION/P) COM_TIO_REF;\n # enable the power_ana_test_multiplexor); any tm_addr value except off/0 enables the test module\ndly(100e-6)\ngav('V_VBG_ACC_M_RAW', 'INT2', 'ASDX')\ncalc('V_VBG_ACC_M', 'V_VBG_ACC_M_RAW', '-', 'V_OFF1_ECOFF')\nlog('V_VBG_ACC_M')\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\n", "output": "/*****************************************************\n * T10_12_ACC_bandgap_measurement_V2, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T10_12_ACC_bandgap_measurement_V2: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static double d_V_VBG_ACC_M_RAW[xNSitES],d_V_VBG_ACC_M[xNSitES];\n static int i_funcRes0[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(d_V_VBG_ACC_M_RAW, 9.9, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T10_12_ACC_bandgap_measurement}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 1] @ avcline 788: {gav('V_VBG_ACC_M_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 1] @ avcline 788: {calc('V_VBG_ACC_M', 'V_VBG_ACC_M_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 1] @ avcline 788: {log('V_VBG_ACC_M', '', '', 0, 0)}\n valid comment[ 2] @ avcline 1365: {Test End: T10_12_ACC_bandgap_measurement}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][1]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_M_RAW//{gav('V_VBG_ACC_M_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n ARRAY_D ad_jsubresults_INT2; ad_jsubresults_INT2.resize(1); ad_jsubresults_INT2.init(-9.9);\n ARRAY_D ad_jsubresults_ASDX; ad_jsubresults_ASDX.resize(1); ad_jsubresults_ASDX.init(-9.9);\n ad_jsubresults_INT2 = rdi.id(\"dcid_0\").getMultiValue(\"INT2\");\n ad_jsubresults_ASDX = rdi.id(\"dcid_0\").getMultiValue(\"ASDX\");\n \n d_V_VBG_ACC_M_RAW[curSite] = ad_jsubresults_INT2[0] - ad_jsubresults_ASDX[0];\n d_V_VBG_ACC_M[curSite] = d_V_VBG_ACC_M_RAW[curSite] - V_OFF1_ECOFF[curSite];\n\n \t\t FuncPrint(\"ad_jsubresults_INT2\", ad_jsubresults_INT2[0]);\n \t\t FuncPrint(\"ad_jsubresults_ASDX\", ad_jsubresults_ASDX[0]);\n FuncPrint(\"d_V_VBG_ACC_M_RAW\",d_V_VBG_ACC_M_RAW[curSite]);\n FuncPrint(\"V_VBG_ACC_M\",d_V_VBG_ACC_M[curSite]);\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n\n ON_FIRST_INVOCATION_END();\n\n int Func_result = rdi.id(\"burst_id0\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"V_VBG_ACC_M\", d_V_VBG_ACC_M[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T10_12_ACC_bandgap_measurement_V2\", T10_12_ACC_bandgap_measurement_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: ACC bandgap characterization\n# Characterization loop derived from T10_11_acc_bandgap_trimming\n# - VSS_A to ANAIO2, VREF_AA to ANAIO1 with buffer 1 enabled only\n#############################################################################################################\nfrom test_sub_functions import *\ncmt('Version info: $Revision: 2 $ $Author: laj1mu23 $ $Date: 2024/03/25 20:34:28 GMT $')\nwac('EXT_MODE', 0xc00f) # Switch to the TEST register page\nwac('TM_CONF', 0x0011) # tm_se_meas=0 tm_bus_inv=1 tm_buf_pwrup=1 (tbuf_tb1_on)\n # bus_inv. because the power_ana_test_multiplexor_refs provides VSS_A/VREF_AA\nwac('TM_PIN', 0x0095) # tm_asdx_sel=4 (BUF2_INP) tm_asdx_en=1 tm_int2_sel=2 (BUF1_OUT) tm_int2_en=1\nwac('TM_ADDR', 0x060e) # tm_cfg=6 (COM_TB2= VREF_AA, COM_TB1= VSS_A) tm_addr=e (tm_bus_sel=tm_addr(3:2)=3 (COM_TION/P) COM_TIO_REF;\n # enable the power_ana_test_multiplexor); any tm_addr value except off/0 enables the test module\n# Characterization loop\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('OCP_MASK', 0x01f0) # Set masking register\nras('REG_VALUE', 'ANA_TRM_BG') # Store the current value\nfor n in range (0, 32, 1):\n cmt('Set trim index to value {} in range (0..31)'.format(n))\n wr('ANA_TRM_BG', n*16) # ANA_TRM_BG<8:4> pc_trm_bgp_vra\n rac('ANA_TRM_BG', n*16, 0x01f0)\n dly(100e-6)\n gav('V_VBG_ACC_C_RAW[{:02d}]'.format(n), 'INT2', 'ASDX') \n calc('V_VBG_ACC_C[{:02d}]'.format(n), 'V_VBG_ACC_C_RAW[{:02d}]'.format(n), '-', 'V_OFF1_ECOFF')\n log(f'V_VBG_ACC_C[{n:02}]')\ndly(592e-9)\nwri('ANA_TRM_BG','REG_VALUE')\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n# Clean\nwac('EXT_MODE', 0xc00f) # Switch to the TEST register page\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\n", "output": "/*****************************************************\n * T10_13_ACC_Bandgap_Char_V2, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n * JSH5SGH: fix some bugs.\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T10_13_ACC_Bandgap_Char_V2: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 2;\n vector i_comment_line[i_split_count];\n\n static int i_REG_VALUE[xNSitES];\n ARRAY_I aI_Captured_0;\n static double d_V_VBG_ACC_C_RAW[xNSitES][32];\n static double V_VBG_ACC_C[xNSitES][32];\n ARRAY_D ad_V_VBG_ACC_C_RAW;\n\n static int i_WRITE_BACK[xNSitES];\n static int i_vec_Num1[32] = {0};\n static int i_funcRes0[xNSitES], i_funcRes1[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(i_REG_VALUE, 9, xNSitES);\n \n //!\"CTmsg: cut pattern to 2 parts @ oriAVCvecline [7779]\n //!\"CTmsg: cut pattern to 2 parts @ binarypatline [7769]\n if (i_split_pat_flag)\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n }\n else\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n for(int i=0; i }\n valid comment[ 1] @ avcline 1162: {ras('REG_VALUE', 'ANA_TRM_BG')}\n valid comment[ 2] @ avcline 1275: {cmt: Set trim index to value 0 in range (0..31)}\n valid comment[ 3] @ avcline 1477: {gav('V_VBG_ACC_C_RAW[00]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 3] @ avcline 1477: {calc('V_VBG_ACC_C[00]', 'V_VBG_ACC_C_RAW[00]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 3] @ avcline 1477: {log('V_VBG_ACC_C[00]', '', '', 0, 0)}\n valid comment[ 4] @ avcline 1478: {cmt: Set trim index to value 1 in range (0..31)}\n valid comment[ 5] @ avcline 1680: {gav('V_VBG_ACC_C_RAW[01]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 5] @ avcline 1680: {calc('V_VBG_ACC_C[01]', 'V_VBG_ACC_C_RAW[01]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 5] @ avcline 1680: {log('V_VBG_ACC_C[01]', '', '', 0, 0)}\n valid comment[ 6] @ avcline 1681: {cmt: Set trim index to value 2 in range (0..31)}\n valid comment[ 7] @ avcline 1883: {gav('V_VBG_ACC_C_RAW[02]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 7] @ avcline 1883: {calc('V_VBG_ACC_C[02]', 'V_VBG_ACC_C_RAW[02]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 7] @ avcline 1883: {log('V_VBG_ACC_C[02]', '', '', 0, 0)}\n valid comment[ 8] @ avcline 1884: {cmt: Set trim index to value 3 in range (0..31)}\n valid comment[ 9] @ avcline 2086: {gav('V_VBG_ACC_C_RAW[03]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 9] @ avcline 2086: {calc('V_VBG_ACC_C[03]', 'V_VBG_ACC_C_RAW[03]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 9] @ avcline 2086: {log('V_VBG_ACC_C[03]', '', '', 0, 0)}\n valid comment[ 10] @ avcline 2087: {cmt: Set trim index to value 4 in range (0..31)}\n valid comment[ 11] @ avcline 2289: {gav('V_VBG_ACC_C_RAW[04]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 11] @ avcline 2289: {calc('V_VBG_ACC_C[04]', 'V_VBG_ACC_C_RAW[04]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 11] @ avcline 2289: {log('V_VBG_ACC_C[04]', '', '', 0, 0)}\n valid comment[ 12] @ avcline 2290: {cmt: Set trim index to value 5 in range (0..31)}\n valid comment[ 13] @ avcline 2492: {gav('V_VBG_ACC_C_RAW[05]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 13] @ avcline 2492: {calc('V_VBG_ACC_C[05]', 'V_VBG_ACC_C_RAW[05]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 13] @ avcline 2492: {log('V_VBG_ACC_C[05]', '', '', 0, 0)}\n valid comment[ 14] @ avcline 2493: {cmt: Set trim index to value 6 in range (0..31)}\n valid comment[ 15] @ avcline 2695: {gav('V_VBG_ACC_C_RAW[06]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 15] @ avcline 2695: {calc('V_VBG_ACC_C[06]', 'V_VBG_ACC_C_RAW[06]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 15] @ avcline 2695: {log('V_VBG_ACC_C[06]', '', '', 0, 0)}\n valid comment[ 16] @ avcline 2696: {cmt: Set trim index to value 7 in range (0..31)}\n valid comment[ 17] @ avcline 2898: {gav('V_VBG_ACC_C_RAW[07]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 17] @ avcline 2898: {calc('V_VBG_ACC_C[07]', 'V_VBG_ACC_C_RAW[07]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 17] @ avcline 2898: {log('V_VBG_ACC_C[07]', '', '', 0, 0)}\n valid comment[ 18] @ avcline 2899: {cmt: Set trim index to value 8 in range (0..31)}\n valid comment[ 19] @ avcline 3101: {gav('V_VBG_ACC_C_RAW[08]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 19] @ avcline 3101: {calc('V_VBG_ACC_C[08]', 'V_VBG_ACC_C_RAW[08]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 19] @ avcline 3101: {log('V_VBG_ACC_C[08]', '', '', 0, 0)}\n valid comment[ 20] @ avcline 3102: {cmt: Set trim index to value 9 in range (0..31)}\n valid comment[ 21] @ avcline 3304: {gav('V_VBG_ACC_C_RAW[09]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 21] @ avcline 3304: {calc('V_VBG_ACC_C[09]', 'V_VBG_ACC_C_RAW[09]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 21] @ avcline 3304: {log('V_VBG_ACC_C[09]', '', '', 0, 0)}\n valid comment[ 22] @ avcline 3305: {cmt: Set trim index to value 10 in range (0..31)}\n valid comment[ 23] @ avcline 3507: {gav('V_VBG_ACC_C_RAW[10]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 23] @ avcline 3507: {calc('V_VBG_ACC_C[10]', 'V_VBG_ACC_C_RAW[10]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 23] @ avcline 3507: {log('V_VBG_ACC_C[10]', '', '', 0, 0)}\n valid comment[ 24] @ avcline 3508: {cmt: Set trim index to value 11 in range (0..31)}\n valid comment[ 25] @ avcline 3710: {gav('V_VBG_ACC_C_RAW[11]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 25] @ avcline 3710: {calc('V_VBG_ACC_C[11]', 'V_VBG_ACC_C_RAW[11]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 25] @ avcline 3710: {log('V_VBG_ACC_C[11]', '', '', 0, 0)}\n valid comment[ 26] @ avcline 3711: {cmt: Set trim index to value 12 in range (0..31)}\n valid comment[ 27] @ avcline 3913: {gav('V_VBG_ACC_C_RAW[12]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 27] @ avcline 3913: {calc('V_VBG_ACC_C[12]', 'V_VBG_ACC_C_RAW[12]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 27] @ avcline 3913: {log('V_VBG_ACC_C[12]', '', '', 0, 0)}\n valid comment[ 28] @ avcline 3914: {cmt: Set trim index to value 13 in range (0..31)}\n valid comment[ 29] @ avcline 4116: {gav('V_VBG_ACC_C_RAW[13]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 29] @ avcline 4116: {calc('V_VBG_ACC_C[13]', 'V_VBG_ACC_C_RAW[13]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 29] @ avcline 4116: {log('V_VBG_ACC_C[13]', '', '', 0, 0)}\n valid comment[ 30] @ avcline 4117: {cmt: Set trim index to value 14 in range (0..31)}\n valid comment[ 31] @ avcline 4319: {gav('V_VBG_ACC_C_RAW[14]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 31] @ avcline 4319: {calc('V_VBG_ACC_C[14]', 'V_VBG_ACC_C_RAW[14]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 31] @ avcline 4319: {log('V_VBG_ACC_C[14]', '', '', 0, 0)}\n valid comment[ 32] @ avcline 4320: {cmt: Set trim index to value 15 in range (0..31)}\n valid comment[ 33] @ avcline 4522: {gav('V_VBG_ACC_C_RAW[15]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 33] @ avcline 4522: {calc('V_VBG_ACC_C[15]', 'V_VBG_ACC_C_RAW[15]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 33] @ avcline 4522: {log('V_VBG_ACC_C[15]', '', '', 0, 0)}\n valid comment[ 34] @ avcline 4523: {cmt: Set trim index to value 16 in range (0..31)}\n valid comment[ 35] @ avcline 4725: {gav('V_VBG_ACC_C_RAW[16]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 35] @ avcline 4725: {calc('V_VBG_ACC_C[16]', 'V_VBG_ACC_C_RAW[16]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 35] @ avcline 4725: {log('V_VBG_ACC_C[16]', '', '', 0, 0)}\n valid comment[ 36] @ avcline 4726: {cmt: Set trim index to value 17 in range (0..31)}\n valid comment[ 37] @ avcline 4928: {gav('V_VBG_ACC_C_RAW[17]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 37] @ avcline 4928: {calc('V_VBG_ACC_C[17]', 'V_VBG_ACC_C_RAW[17]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 37] @ avcline 4928: {log('V_VBG_ACC_C[17]', '', '', 0, 0)}\n valid comment[ 38] @ avcline 4929: {cmt: Set trim index to value 18 in range (0..31)}\n valid comment[ 39] @ avcline 5131: {gav('V_VBG_ACC_C_RAW[18]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 39] @ avcline 5131: {calc('V_VBG_ACC_C[18]', 'V_VBG_ACC_C_RAW[18]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 39] @ avcline 5131: {log('V_VBG_ACC_C[18]', '', '', 0, 0)}\n valid comment[ 40] @ avcline 5132: {cmt: Set trim index to value 19 in range (0..31)}\n valid comment[ 41] @ avcline 5334: {gav('V_VBG_ACC_C_RAW[19]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 41] @ avcline 5334: {calc('V_VBG_ACC_C[19]', 'V_VBG_ACC_C_RAW[19]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 41] @ avcline 5334: {log('V_VBG_ACC_C[19]', '', '', 0, 0)}\n valid comment[ 42] @ avcline 5335: {cmt: Set trim index to value 20 in range (0..31)}\n valid comment[ 43] @ avcline 5537: {gav('V_VBG_ACC_C_RAW[20]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 43] @ avcline 5537: {calc('V_VBG_ACC_C[20]', 'V_VBG_ACC_C_RAW[20]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 43] @ avcline 5537: {log('V_VBG_ACC_C[20]', '', '', 0, 0)}\n valid comment[ 44] @ avcline 5538: {cmt: Set trim index to value 21 in range (0..31)}\n valid comment[ 45] @ avcline 5740: {gav('V_VBG_ACC_C_RAW[21]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 45] @ avcline 5740: {calc('V_VBG_ACC_C[21]', 'V_VBG_ACC_C_RAW[21]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 45] @ avcline 5740: {log('V_VBG_ACC_C[21]', '', '', 0, 0)}\n valid comment[ 46] @ avcline 5741: {cmt: Set trim index to value 22 in range (0..31)}\n valid comment[ 47] @ avcline 5943: {gav('V_VBG_ACC_C_RAW[22]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 47] @ avcline 5943: {calc('V_VBG_ACC_C[22]', 'V_VBG_ACC_C_RAW[22]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 47] @ avcline 5943: {log('V_VBG_ACC_C[22]', '', '', 0, 0)}\n valid comment[ 48] @ avcline 5944: {cmt: Set trim index to value 23 in range (0..31)}\n valid comment[ 49] @ avcline 6146: {gav('V_VBG_ACC_C_RAW[23]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 49] @ avcline 6146: {calc('V_VBG_ACC_C[23]', 'V_VBG_ACC_C_RAW[23]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 49] @ avcline 6146: {log('V_VBG_ACC_C[23]', '', '', 0, 0)}\n valid comment[ 50] @ avcline 6147: {cmt: Set trim index to value 24 in range (0..31)}\n valid comment[ 51] @ avcline 6349: {gav('V_VBG_ACC_C_RAW[24]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 51] @ avcline 6349: {calc('V_VBG_ACC_C[24]', 'V_VBG_ACC_C_RAW[24]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 51] @ avcline 6349: {log('V_VBG_ACC_C[24]', '', '', 0, 0)}\n valid comment[ 52] @ avcline 6350: {cmt: Set trim index to value 25 in range (0..31)}\n valid comment[ 53] @ avcline 6552: {gav('V_VBG_ACC_C_RAW[25]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 53] @ avcline 6552: {calc('V_VBG_ACC_C[25]', 'V_VBG_ACC_C_RAW[25]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 53] @ avcline 6552: {log('V_VBG_ACC_C[25]', '', '', 0, 0)}\n valid comment[ 54] @ avcline 6553: {cmt: Set trim index to value 26 in range (0..31)}\n valid comment[ 55] @ avcline 6755: {gav('V_VBG_ACC_C_RAW[26]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 55] @ avcline 6755: {calc('V_VBG_ACC_C[26]', 'V_VBG_ACC_C_RAW[26]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 55] @ avcline 6755: {log('V_VBG_ACC_C[26]', '', '', 0, 0)}\n valid comment[ 56] @ avcline 6756: {cmt: Set trim index to value 27 in range (0..31)}\n valid comment[ 57] @ avcline 6958: {gav('V_VBG_ACC_C_RAW[27]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 57] @ avcline 6958: {calc('V_VBG_ACC_C[27]', 'V_VBG_ACC_C_RAW[27]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 57] @ avcline 6958: {log('V_VBG_ACC_C[27]', '', '', 0, 0)}\n valid comment[ 58] @ avcline 6959: {cmt: Set trim index to value 28 in range (0..31)}\n valid comment[ 59] @ avcline 7161: {gav('V_VBG_ACC_C_RAW[28]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 59] @ avcline 7161: {calc('V_VBG_ACC_C[28]', 'V_VBG_ACC_C_RAW[28]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 59] @ avcline 7161: {log('V_VBG_ACC_C[28]', '', '', 0, 0)}\n valid comment[ 60] @ avcline 7162: {cmt: Set trim index to value 29 in range (0..31)}\n valid comment[ 61] @ avcline 7364: {gav('V_VBG_ACC_C_RAW[29]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 61] @ avcline 7364: {calc('V_VBG_ACC_C[29]', 'V_VBG_ACC_C_RAW[29]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 61] @ avcline 7364: {log('V_VBG_ACC_C[29]', '', '', 0, 0)}\n valid comment[ 62] @ avcline 7365: {cmt: Set trim index to value 30 in range (0..31)}\n valid comment[ 63] @ avcline 7567: {gav('V_VBG_ACC_C_RAW[30]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 63] @ avcline 7567: {calc('V_VBG_ACC_C[30]', 'V_VBG_ACC_C_RAW[30]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 63] @ avcline 7567: {log('V_VBG_ACC_C[30]', '', '', 0, 0)}\n valid comment[ 64] @ avcline 7568: {cmt: Set trim index to value 31 in range (0..31)}\n valid comment[ 65] @ avcline 7770: {gav('V_VBG_ACC_C_RAW[31]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 65] @ avcline 7770: {calc('V_VBG_ACC_C[31]', 'V_VBG_ACC_C_RAW[31]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 65] @ avcline 7770: {log('V_VBG_ACC_C[31]', '', '', 0, 0)}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.digCap(\"digcapid_0\").vecVarOnly().pin(\"SDO\").capMode(TA::SER).bitPerWord(16).samples(1*16).execute();\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][3]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_C_RAW_00//{gav('V_VBG_ACC_C_RAW[00]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][5]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_C_RAW_01//{gav('V_VBG_ACC_C_RAW[01]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][7]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_C_RAW_02//{gav('V_VBG_ACC_C_RAW[02]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][9]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_C_RAW_03//{gav('V_VBG_ACC_C_RAW[03]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][11]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_C_RAW_04//{gav('V_VBG_ACC_C_RAW[04]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][13]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_C_RAW_05//{gav('V_VBG_ACC_C_RAW[05]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][15]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_C_RAW_06//{gav('V_VBG_ACC_C_RAW[06]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][17]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_C_RAW_07//{gav('V_VBG_ACC_C_RAW[07]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][19]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_C_RAW_08//{gav('V_VBG_ACC_C_RAW[08]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][21]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_C_RAW_09//{gav('V_VBG_ACC_C_RAW[09]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][23]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_C_RAW_10//{gav('V_VBG_ACC_C_RAW[10]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][25]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_C_RAW_11//{gav('V_VBG_ACC_C_RAW[11]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][27]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_C_RAW_12//{gav('V_VBG_ACC_C_RAW[12]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][29]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_C_RAW_13//{gav('V_VBG_ACC_C_RAW[13]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][31]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_C_RAW_14//{gav('V_VBG_ACC_C_RAW[14]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][33]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_C_RAW_15//{gav('V_VBG_ACC_C_RAW[15]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][35]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_C_RAW_16//{gav('V_VBG_ACC_C_RAW[16]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][37]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_C_RAW_17//{gav('V_VBG_ACC_C_RAW[17]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][39]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_C_RAW_18//{gav('V_VBG_ACC_C_RAW[18]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][41]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_C_RAW_19//{gav('V_VBG_ACC_C_RAW[19]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][43]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_C_RAW_20//{gav('V_VBG_ACC_C_RAW[20]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][45]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_C_RAW_21//{gav('V_VBG_ACC_C_RAW[21]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][47]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_C_RAW_22//{gav('V_VBG_ACC_C_RAW[22]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][49]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_C_RAW_23//{gav('V_VBG_ACC_C_RAW[23]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][51]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_C_RAW_24//{gav('V_VBG_ACC_C_RAW[24]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][53]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_C_RAW_25//{gav('V_VBG_ACC_C_RAW[25]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][55]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_C_RAW_26//{gav('V_VBG_ACC_C_RAW[26]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][57]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_C_RAW_27//{gav('V_VBG_ACC_C_RAW[27]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][59]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_C_RAW_28//{gav('V_VBG_ACC_C_RAW[28]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][61]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_C_RAW_29//{gav('V_VBG_ACC_C_RAW[29]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][63]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_C_RAW_30//{gav('V_VBG_ACC_C_RAW[30]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][65]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_C_RAW_31//{gav('V_VBG_ACC_C_RAW[31]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n aI_Captured_0 = rdi.id(\"digcapid_0\").getVector(\"SDO\");\n ARRAY_D ad_jsubresults_INT2; ad_jsubresults_INT2.resize(32); ad_jsubresults_INT2.init(-9.9);\n ARRAY_D ad_jsubresults_ASDX; ad_jsubresults_ASDX.resize(32); ad_jsubresults_ASDX.init(-9.9);\n ad_jsubresults_INT2 = rdi.id(\"dcid_0\").getMultiValue(\"INT2\");\n ad_jsubresults_ASDX = rdi.id(\"dcid_0\").getMultiValue(\"ASDX\");\n \n aI_Captured_0[0] = Switch_High_Low_Bits_16Bits(aI_Captured_0[0]);\n i_REG_VALUE[curSite] = aI_Captured_0[0];\n FuncPrint(\"REG_VALUE\",i_REG_VALUE[curSite]);\n\n for(int i=0; i<32; i++){\n d_V_VBG_ACC_C_RAW[curSite][i] = ad_jsubresults_INT2[0 + i] - ad_jsubresults_ASDX[0 + i];\n FuncPrint(\"V_VBG_ACC_C_RAW_\" + rdi.itos(curSite) + \"_\"+ rdi.itos(i) ,d_V_VBG_ACC_C_RAW[curSite][i]);\n V_VBG_ACC_C[curSite][i] = d_V_VBG_ACC_C_RAW[curSite][i] - V_OFF1_ECOFF[curSite];\n FuncPrint(\"V_VBG_ACC_C_\"+ rdi.itos(i) ,V_VBG_ACC_C[curSite][i]);\n\t\t\t }\n FOR_EACH_SITE_END();\n\n\n /* Ori key coments in subpat1 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 7779: {wri('ANA_TRM_BG', 'REG_VALUE')}\n valid comment[ 1] @ avcline 8818: {Test End: T10_13_ACC_Bandgap_Char}\n */\n static int i_vec_iposition1[32] = {\n 31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,\n 48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63\n };\n for (int i = 0; i < 32; i++)\n\t\t {\n\t\t\t i_vec_Num1[i] = i_vec_iposition1[i];\n\t\t }\n FOR_EACH_SITE_BEGIN();\n i_WRITE_BACK[curSite] = Switch_High_Low_Bits_16Bits(i_REG_VALUE[curSite]);\n Func_Vector_Dynamic_Write(s_splited_pat_name[1], \"SDX\", i_vec_Num1, 32, i_WRITE_BACK[curSite], 0, 2); //Notes. TEI check per project\n\n FOR_EACH_SITE_END();\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id1\");\n rdi.func().label(s_splited_pat_name[1]).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes1[curSite] = rdi.id(\"burst_id1\").getBurstPassFail();\n\n FOR_EACH_SITE_END();\n\n\n }\n\n ON_FIRST_INVOCATION_END();\n\n for(int i=0; i < 32; i++){ \n TestLog(s_Func_Test_Name_Add_2Num(\"V_VBG_ACC_C_\", i), V_VBG_ACC_C[curSite][i]);\n }\n i_funcRes[curSite] = i_funcRes0[curSite] && i_funcRes1[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T10_13_ACC_Bandgap_Char_V2\", T10_13_ACC_Bandgap_Char_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 2 $ $Author: laj1mu23 $ $Date: 2024/03/25 20:34:28 GMT $')\nwac('EXT_MODE', 0xc00f) # Switch to the TEST register page\nwac('TM_CONF', 0x0011) # tm_se_meas=0 tm_bus_inv=1 tm_buf_pwrup=1 (tbuf_tb1_on)\n # bus_inv. because the power_ana_test_multiplexor_2 provides VSS_A/VDDA\nwac('TM_PIN', 0x0095) # tm_asdx_sel=4 (BUF2_INP) tm_asdx_en=1 tm_int2_sel=2 (BUF1_OUT) tm_int2_en=1\nwac('TM_ADDR', 0x090d) # tm_cfg=9 (COM_TB2= VDDA, COM_TB1= VSS_A) tm_addr=d (COM_TIO_PWR;\n # enable the power_ana_test_multiplexor_2 for power supplies); any tm_addr value except off/0 enables the test module\ndly(100e-6)\ngav('V_VDDAA_M_RAW', 'INT2', 'ASDX') # no check (V_OFF2_ECON)\ncalc('V_VDDAA', 'V_VDDAA_M_RAW', '-', 'V_OFF1_ECOFF')\nlog('V_VDDAA')\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T10_14_VDDA_LDO_measurement_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n static double V_VDDAA_M_RAW[xNSitES];\n static double V_VDDAA[xNSitES];\n // Auto_Code_Variable_define\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T10_14_VDDA_LDO_measurement_V2_PAT_id\");\n rdi.dc(\"T10_14_VDDA_LDO_measurement_V2DC_id0\").label(s_label_name)\n .insertSub(i_comment_line0[0]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms) //V_VDDAA_M_RAW\n .execute();\n RDI_END();\n ON_FIRST_INVOCATION_END();\n\n ARRAY_D JSUB_results_ASDX;\n JSUB_results_ASDX = rdi.id(\"T10_14_VDDA_LDO_measurement_V2DC_id0\").getMultiValue(\"ASDX\");\n ARRAY_D JSUB_results_INT2;\n JSUB_results_INT2 = rdi.id(\"T10_14_VDDA_LDO_measurement_V2DC_id0\").getMultiValue(\"INT2\");\n V_VDDAA_M_RAW[CURRENT_SITE_NUMBER()-1] = JSUB_results_INT2[0] - JSUB_results_ASDX[0];\n V_VDDAA[CURRENT_SITE_NUMBER()-1] = V_VDDAA_M_RAW[CURRENT_SITE_NUMBER()-1] - V_OFF1_ECOFF[CURRENT_SITE_NUMBER()-1];\n\n FuncPrint(\"JSUB_results_ASDX\", JSUB_results_ASDX[0]);\n FuncPrint(\"JSUB_results_INT2\", JSUB_results_INT2[0]);\n FuncPrint(\"V_VDDAA_M_RAW\", V_VDDAA_M_RAW[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"V_VDDAA\", V_VDDAA[CURRENT_SITE_NUMBER()-1]);\n \n int Func_result = rdi.id(\"T10_14_VDDA_LDO_measurement_V2_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"V_VDDAA\", V_VDDAA[CURRENT_SITE_NUMBER()-1]);\n // Auto_Code_Judge_and_log\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T10_14_VDDA_LDO_measurement_V2\", T10_14_VDDA_LDO_measurement_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: ACC bandgap characterization\n# similar to T10_13_ACC_Bandgap_Char.py\n# - VDDA to ANAIO1, VSS_A to ANAIO2 with buffer 1 enabled only\n#############################################################################################################\nfrom test_sub_functions import *\ncmt('Version info: $Revision: 2 $ $Author: laj1mu23 $ $Date: 2024/03/25 20:34:28 GMT $')\nwac('EXT_MODE', 0xc00f) # Switch to the TEST register page\nwac('TM_CONF', 0x0011) # tm_se_meas=0 tm_bus_inv=1 tm_buf_pwrup=1 (tbuf_tb1_on)\n # bus_inv. because the power_ana_test_multiplexor_2 provides VSS_A/VDDA\nwac('TM_PIN', 0x0095) # tm_asdx_sel=4 (BUF2_INP) tm_asdx_en=1 tm_int2_sel=2 (BUF1_OUT) tm_int2_en=1\nwac('TM_ADDR', 0x090d) # tm_cfg=9 (COM_TB2= VDDA, COM_TB1= VSS_A) tm_addr=d (COM_TIO_PWR;\n # enable the power_ana_test_multiplexor_2 for power supplies); any tm_addr value except off/0 enables the test module\n# Characterization loop\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('OCP_MASK', 0x01f0) # Set masking register\nras('REG_VALUE', 'ANA_TRM_BG') # Store the current value\nfor n in range (0, 32, 1):\n cmt('Set trim index to value {} in range (0..31)'.format(n))\n wr('ANA_TRM_BG', n*16) # ANA_TRM_BG<8:4> pc_trm_bgp_vra\n rac('ANA_TRM_BG', n*16, 0x01f0)\n dly(100e-6)\n gav('V_VDDA_C_RAW[{:02d}]'.format(n), 'INT2', 'ASDX') \n calc('V_VDDA_C[{:02d}]'.format(n), 'V_VDDA_C_RAW[{:02d}]'.format(n), '-', 'V_OFF1_ECOFF')\n log(f'V_VDDA_C[{n:02}]')\ndly(592e-9)\nwri('ANA_TRM_BG','REG_VALUE')\n# Clean\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n# Clean\nwac('EXT_MODE', 0xc00f) # Switch to the TEST register page\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\n", "output": "/*****************************************************\n * T10_15_VDDA_LDO_Char_V2, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n * JSH5SGH: fix some bugs.\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T10_15_VDDA_LDO_Char_V2: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 2;\n vector i_comment_line[i_split_count];\n\n static int i_REG_VALUE[xNSitES];\n ARRAY_I aI_Captured_0;\n static double d_V_VDDA_C_RAW[xNSitES][32];\n static double V_VDDA_C[xNSitES][32];\n ARRAY_D ad_V_VDDA_C_RAW;\n\n static int i_WRITE_BACK[xNSitES];\n static int i_vec_Num1[32] = {0};\n static int i_funcRes0[xNSitES], i_funcRes1[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(i_REG_VALUE, 9, xNSitES);\n \n //!\"CTmsg: cut pattern to 2 parts @ oriAVCvecline [7779]\n //!\"CTmsg: cut pattern to 2 parts @ binarypatline [7769]\n if (i_split_pat_flag)\n {\n \t split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n }\n else\n {\n\t\t\t split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n\t\t\t for(int i=0; i }\n valid comment[ 1] @ avcline 1162: {ras('REG_VALUE', 'ANA_TRM_BG')}\n valid comment[ 2] @ avcline 1275: {cmt: Set trim index to value 0 in range (0..31)}\n valid comment[ 3] @ avcline 1477: {gav('V_VDDA_C_RAW[00]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 3] @ avcline 1477: {calc('V_VDDA_C[00]', 'V_VDDA_C_RAW[00]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 3] @ avcline 1477: {log('V_VDDA_C[00]', '', '', 0, 0)}\n valid comment[ 4] @ avcline 1478: {cmt: Set trim index to value 1 in range (0..31)}\n valid comment[ 5] @ avcline 1680: {gav('V_VDDA_C_RAW[01]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 5] @ avcline 1680: {calc('V_VDDA_C[01]', 'V_VDDA_C_RAW[01]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 5] @ avcline 1680: {log('V_VDDA_C[01]', '', '', 0, 0)}\n valid comment[ 6] @ avcline 1681: {cmt: Set trim index to value 2 in range (0..31)}\n valid comment[ 7] @ avcline 1883: {gav('V_VDDA_C_RAW[02]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 7] @ avcline 1883: {calc('V_VDDA_C[02]', 'V_VDDA_C_RAW[02]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 7] @ avcline 1883: {log('V_VDDA_C[02]', '', '', 0, 0)}\n valid comment[ 8] @ avcline 1884: {cmt: Set trim index to value 3 in range (0..31)}\n valid comment[ 9] @ avcline 2086: {gav('V_VDDA_C_RAW[03]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 9] @ avcline 2086: {calc('V_VDDA_C[03]', 'V_VDDA_C_RAW[03]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 9] @ avcline 2086: {log('V_VDDA_C[03]', '', '', 0, 0)}\n valid comment[ 10] @ avcline 2087: {cmt: Set trim index to value 4 in range (0..31)}\n valid comment[ 11] @ avcline 2289: {gav('V_VDDA_C_RAW[04]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 11] @ avcline 2289: {calc('V_VDDA_C[04]', 'V_VDDA_C_RAW[04]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 11] @ avcline 2289: {log('V_VDDA_C[04]', '', '', 0, 0)}\n valid comment[ 12] @ avcline 2290: {cmt: Set trim index to value 5 in range (0..31)}\n valid comment[ 13] @ avcline 2492: {gav('V_VDDA_C_RAW[05]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 13] @ avcline 2492: {calc('V_VDDA_C[05]', 'V_VDDA_C_RAW[05]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 13] @ avcline 2492: {log('V_VDDA_C[05]', '', '', 0, 0)}\n valid comment[ 14] @ avcline 2493: {cmt: Set trim index to value 6 in range (0..31)}\n valid comment[ 15] @ avcline 2695: {gav('V_VDDA_C_RAW[06]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 15] @ avcline 2695: {calc('V_VDDA_C[06]', 'V_VDDA_C_RAW[06]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 15] @ avcline 2695: {log('V_VDDA_C[06]', '', '', 0, 0)}\n valid comment[ 16] @ avcline 2696: {cmt: Set trim index to value 7 in range (0..31)}\n valid comment[ 17] @ avcline 2898: {gav('V_VDDA_C_RAW[07]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 17] @ avcline 2898: {calc('V_VDDA_C[07]', 'V_VDDA_C_RAW[07]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 17] @ avcline 2898: {log('V_VDDA_C[07]', '', '', 0, 0)}\n valid comment[ 18] @ avcline 2899: {cmt: Set trim index to value 8 in range (0..31)}\n valid comment[ 19] @ avcline 3101: {gav('V_VDDA_C_RAW[08]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 19] @ avcline 3101: {calc('V_VDDA_C[08]', 'V_VDDA_C_RAW[08]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 19] @ avcline 3101: {log('V_VDDA_C[08]', '', '', 0, 0)}\n valid comment[ 20] @ avcline 3102: {cmt: Set trim index to value 9 in range (0..31)}\n valid comment[ 21] @ avcline 3304: {gav('V_VDDA_C_RAW[09]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 21] @ avcline 3304: {calc('V_VDDA_C[09]', 'V_VDDA_C_RAW[09]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 21] @ avcline 3304: {log('V_VDDA_C[09]', '', '', 0, 0)}\n valid comment[ 22] @ avcline 3305: {cmt: Set trim index to value 10 in range (0..31)}\n valid comment[ 23] @ avcline 3507: {gav('V_VDDA_C_RAW[10]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 23] @ avcline 3507: {calc('V_VDDA_C[10]', 'V_VDDA_C_RAW[10]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 23] @ avcline 3507: {log('V_VDDA_C[10]', '', '', 0, 0)}\n valid comment[ 24] @ avcline 3508: {cmt: Set trim index to value 11 in range (0..31)}\n valid comment[ 25] @ avcline 3710: {gav('V_VDDA_C_RAW[11]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 25] @ avcline 3710: {calc('V_VDDA_C[11]', 'V_VDDA_C_RAW[11]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 25] @ avcline 3710: {log('V_VDDA_C[11]', '', '', 0, 0)}\n valid comment[ 26] @ avcline 3711: {cmt: Set trim index to value 12 in range (0..31)}\n valid comment[ 27] @ avcline 3913: {gav('V_VDDA_C_RAW[12]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 27] @ avcline 3913: {calc('V_VDDA_C[12]', 'V_VDDA_C_RAW[12]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 27] @ avcline 3913: {log('V_VDDA_C[12]', '', '', 0, 0)}\n valid comment[ 28] @ avcline 3914: {cmt: Set trim index to value 13 in range (0..31)}\n valid comment[ 29] @ avcline 4116: {gav('V_VDDA_C_RAW[13]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 29] @ avcline 4116: {calc('V_VDDA_C[13]', 'V_VDDA_C_RAW[13]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 29] @ avcline 4116: {log('V_VDDA_C[13]', '', '', 0, 0)}\n valid comment[ 30] @ avcline 4117: {cmt: Set trim index to value 14 in range (0..31)}\n valid comment[ 31] @ avcline 4319: {gav('V_VDDA_C_RAW[14]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 31] @ avcline 4319: {calc('V_VDDA_C[14]', 'V_VDDA_C_RAW[14]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 31] @ avcline 4319: {log('V_VDDA_C[14]', '', '', 0, 0)}\n valid comment[ 32] @ avcline 4320: {cmt: Set trim index to value 15 in range (0..31)}\n valid comment[ 33] @ avcline 4522: {gav('V_VDDA_C_RAW[15]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 33] @ avcline 4522: {calc('V_VDDA_C[15]', 'V_VDDA_C_RAW[15]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 33] @ avcline 4522: {log('V_VDDA_C[15]', '', '', 0, 0)}\n valid comment[ 34] @ avcline 4523: {cmt: Set trim index to value 16 in range (0..31)}\n valid comment[ 35] @ avcline 4725: {gav('V_VDDA_C_RAW[16]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 35] @ avcline 4725: {calc('V_VDDA_C[16]', 'V_VDDA_C_RAW[16]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 35] @ avcline 4725: {log('V_VDDA_C[16]', '', '', 0, 0)}\n valid comment[ 36] @ avcline 4726: {cmt: Set trim index to value 17 in range (0..31)}\n valid comment[ 37] @ avcline 4928: {gav('V_VDDA_C_RAW[17]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 37] @ avcline 4928: {calc('V_VDDA_C[17]', 'V_VDDA_C_RAW[17]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 37] @ avcline 4928: {log('V_VDDA_C[17]', '', '', 0, 0)}\n valid comment[ 38] @ avcline 4929: {cmt: Set trim index to value 18 in range (0..31)}\n valid comment[ 39] @ avcline 5131: {gav('V_VDDA_C_RAW[18]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 39] @ avcline 5131: {calc('V_VDDA_C[18]', 'V_VDDA_C_RAW[18]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 39] @ avcline 5131: {log('V_VDDA_C[18]', '', '', 0, 0)}\n valid comment[ 40] @ avcline 5132: {cmt: Set trim index to value 19 in range (0..31)}\n valid comment[ 41] @ avcline 5334: {gav('V_VDDA_C_RAW[19]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 41] @ avcline 5334: {calc('V_VDDA_C[19]', 'V_VDDA_C_RAW[19]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 41] @ avcline 5334: {log('V_VDDA_C[19]', '', '', 0, 0)}\n valid comment[ 42] @ avcline 5335: {cmt: Set trim index to value 20 in range (0..31)}\n valid comment[ 43] @ avcline 5537: {gav('V_VDDA_C_RAW[20]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 43] @ avcline 5537: {calc('V_VDDA_C[20]', 'V_VDDA_C_RAW[20]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 43] @ avcline 5537: {log('V_VDDA_C[20]', '', '', 0, 0)}\n valid comment[ 44] @ avcline 5538: {cmt: Set trim index to value 21 in range (0..31)}\n valid comment[ 45] @ avcline 5740: {gav('V_VDDA_C_RAW[21]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 45] @ avcline 5740: {calc('V_VDDA_C[21]', 'V_VDDA_C_RAW[21]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 45] @ avcline 5740: {log('V_VDDA_C[21]', '', '', 0, 0)}\n valid comment[ 46] @ avcline 5741: {cmt: Set trim index to value 22 in range (0..31)}\n valid comment[ 47] @ avcline 5943: {gav('V_VDDA_C_RAW[22]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 47] @ avcline 5943: {calc('V_VDDA_C[22]', 'V_VDDA_C_RAW[22]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 47] @ avcline 5943: {log('V_VDDA_C[22]', '', '', 0, 0)}\n valid comment[ 48] @ avcline 5944: {cmt: Set trim index to value 23 in range (0..31)}\n valid comment[ 49] @ avcline 6146: {gav('V_VDDA_C_RAW[23]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 49] @ avcline 6146: {calc('V_VDDA_C[23]', 'V_VDDA_C_RAW[23]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 49] @ avcline 6146: {log('V_VDDA_C[23]', '', '', 0, 0)}\n valid comment[ 50] @ avcline 6147: {cmt: Set trim index to value 24 in range (0..31)}\n valid comment[ 51] @ avcline 6349: {gav('V_VDDA_C_RAW[24]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 51] @ avcline 6349: {calc('V_VDDA_C[24]', 'V_VDDA_C_RAW[24]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 51] @ avcline 6349: {log('V_VDDA_C[24]', '', '', 0, 0)}\n valid comment[ 52] @ avcline 6350: {cmt: Set trim index to value 25 in range (0..31)}\n valid comment[ 53] @ avcline 6552: {gav('V_VDDA_C_RAW[25]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 53] @ avcline 6552: {calc('V_VDDA_C[25]', 'V_VDDA_C_RAW[25]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 53] @ avcline 6552: {log('V_VDDA_C[25]', '', '', 0, 0)}\n valid comment[ 54] @ avcline 6553: {cmt: Set trim index to value 26 in range (0..31)}\n valid comment[ 55] @ avcline 6755: {gav('V_VDDA_C_RAW[26]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 55] @ avcline 6755: {calc('V_VDDA_C[26]', 'V_VDDA_C_RAW[26]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 55] @ avcline 6755: {log('V_VDDA_C[26]', '', '', 0, 0)}\n valid comment[ 56] @ avcline 6756: {cmt: Set trim index to value 27 in range (0..31)}\n valid comment[ 57] @ avcline 6958: {gav('V_VDDA_C_RAW[27]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 57] @ avcline 6958: {calc('V_VDDA_C[27]', 'V_VDDA_C_RAW[27]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 57] @ avcline 6958: {log('V_VDDA_C[27]', '', '', 0, 0)}\n valid comment[ 58] @ avcline 6959: {cmt: Set trim index to value 28 in range (0..31)}\n valid comment[ 59] @ avcline 7161: {gav('V_VDDA_C_RAW[28]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 59] @ avcline 7161: {calc('V_VDDA_C[28]', 'V_VDDA_C_RAW[28]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 59] @ avcline 7161: {log('V_VDDA_C[28]', '', '', 0, 0)}\n valid comment[ 60] @ avcline 7162: {cmt: Set trim index to value 29 in range (0..31)}\n valid comment[ 61] @ avcline 7364: {gav('V_VDDA_C_RAW[29]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 61] @ avcline 7364: {calc('V_VDDA_C[29]', 'V_VDDA_C_RAW[29]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 61] @ avcline 7364: {log('V_VDDA_C[29]', '', '', 0, 0)}\n valid comment[ 62] @ avcline 7365: {cmt: Set trim index to value 30 in range (0..31)}\n valid comment[ 63] @ avcline 7567: {gav('V_VDDA_C_RAW[30]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 63] @ avcline 7567: {calc('V_VDDA_C[30]', 'V_VDDA_C_RAW[30]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 63] @ avcline 7567: {log('V_VDDA_C[30]', '', '', 0, 0)}\n valid comment[ 64] @ avcline 7568: {cmt: Set trim index to value 31 in range (0..31)}\n valid comment[ 65] @ avcline 7770: {gav('V_VDDA_C_RAW[31]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 65] @ avcline 7770: {calc('V_VDDA_C[31]', 'V_VDDA_C_RAW[31]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 65] @ avcline 7770: {log('V_VDDA_C[31]', '', '', 0, 0)}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.digCap(\"digcapid_0\").vecVarOnly().pin(\"SDO\").capMode(TA::SER).bitPerWord(16).samples(1*16).execute();\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][3]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDA_C_RAW_00//{gav('V_VDDA_C_RAW[00]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][5]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDA_C_RAW_01//{gav('V_VDDA_C_RAW[01]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][7]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDA_C_RAW_02//{gav('V_VDDA_C_RAW[02]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][9]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDA_C_RAW_03//{gav('V_VDDA_C_RAW[03]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][11]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDA_C_RAW_04//{gav('V_VDDA_C_RAW[04]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][13]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDA_C_RAW_05//{gav('V_VDDA_C_RAW[05]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][15]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDA_C_RAW_06//{gav('V_VDDA_C_RAW[06]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][17]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDA_C_RAW_07//{gav('V_VDDA_C_RAW[07]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][19]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDA_C_RAW_08//{gav('V_VDDA_C_RAW[08]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][21]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDA_C_RAW_09//{gav('V_VDDA_C_RAW[09]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][23]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDA_C_RAW_10//{gav('V_VDDA_C_RAW[10]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][25]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDA_C_RAW_11//{gav('V_VDDA_C_RAW[11]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][27]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDA_C_RAW_12//{gav('V_VDDA_C_RAW[12]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][29]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDA_C_RAW_13//{gav('V_VDDA_C_RAW[13]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][31]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDA_C_RAW_14//{gav('V_VDDA_C_RAW[14]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][33]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDA_C_RAW_15//{gav('V_VDDA_C_RAW[15]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][35]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDA_C_RAW_16//{gav('V_VDDA_C_RAW[16]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][37]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDA_C_RAW_17//{gav('V_VDDA_C_RAW[17]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][39]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDA_C_RAW_18//{gav('V_VDDA_C_RAW[18]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][41]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDA_C_RAW_19//{gav('V_VDDA_C_RAW[19]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][43]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDA_C_RAW_20//{gav('V_VDDA_C_RAW[20]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][45]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDA_C_RAW_21//{gav('V_VDDA_C_RAW[21]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][47]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDA_C_RAW_22//{gav('V_VDDA_C_RAW[22]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][49]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDA_C_RAW_23//{gav('V_VDDA_C_RAW[23]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][51]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDA_C_RAW_24//{gav('V_VDDA_C_RAW[24]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][53]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDA_C_RAW_25//{gav('V_VDDA_C_RAW[25]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][55]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDA_C_RAW_26//{gav('V_VDDA_C_RAW[26]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][57]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDA_C_RAW_27//{gav('V_VDDA_C_RAW[27]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][59]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDA_C_RAW_28//{gav('V_VDDA_C_RAW[28]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][61]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDA_C_RAW_29//{gav('V_VDDA_C_RAW[29]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][63]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDA_C_RAW_30//{gav('V_VDDA_C_RAW[30]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][65]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDA_C_RAW_31//{gav('V_VDDA_C_RAW[31]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n aI_Captured_0 = rdi.id(\"digcapid_0\").getVector(\"SDO\");\n ARRAY_D ad_jsubresults_INT2; ad_jsubresults_INT2.resize(32); ad_jsubresults_INT2.init(-9.9);\n ARRAY_D ad_jsubresults_ASDX; ad_jsubresults_ASDX.resize(32); ad_jsubresults_ASDX.init(-9.9);\n ad_jsubresults_INT2 = rdi.id(\"dcid_0\").getMultiValue(\"INT2\");\n ad_jsubresults_ASDX = rdi.id(\"dcid_0\").getMultiValue(\"ASDX\");\n \n aI_Captured_0[0] = Switch_High_Low_Bits_16Bits(aI_Captured_0[0]);\n i_REG_VALUE[curSite] = aI_Captured_0[0];\n FuncPrint(\"REG_VALUE\",i_REG_VALUE[curSite]);\n\n for(int i=0; i<32; i++){\n d_V_VDDA_C_RAW[curSite][i] = ad_jsubresults_INT2[0 + i] - ad_jsubresults_ASDX[0 + i];\n FuncPrint(\"V_VDDA_C_RAW_\" + rdi.itos(curSite) + \"_\"+ rdi.itos(i) ,d_V_VDDA_C_RAW[curSite][i]);\n\n V_VDDA_C[curSite][i] = d_V_VDDA_C_RAW[curSite][i] - V_OFF1_ECOFF[curSite];\n FuncPrint(s_Func_Test_Name_Add_2Num(\"V_VDDA_C_\", i) ,V_VDDA_C[curSite][i]);\n\t\t\t }\n FOR_EACH_SITE_END();\n\n\n /* Ori key coments in subpat1 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 7779: {wri('ANA_TRM_BG', 'REG_VALUE')}\n valid comment[ 1] @ avcline 8818: {Test End: T10_15_VDDA_LDO_Char}\n */\n static int i_vec_iposition1[32] = {\n 31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,\n 48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63\n };\n for (int i = 0; i < 32; i++)\n\t\t {\n\t\t\t i_vec_Num1[i] = i_vec_iposition1[i];\n\t\t }\n FOR_EACH_SITE_BEGIN();\n i_WRITE_BACK[curSite] = Switch_High_Low_Bits_16Bits(i_REG_VALUE[curSite]);\n Func_Vector_Dynamic_Write(s_splited_pat_name[1], \"SDX\", i_vec_Num1, 32, i_WRITE_BACK[curSite], 0, 2); //Notes. TEI check per project\n\n FOR_EACH_SITE_END();\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id1\");\n rdi.func().label(s_splited_pat_name[1]).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes1[curSite] = rdi.id(\"burst_id1\").getBurstPassFail();\n\n FOR_EACH_SITE_END();\n }\n\n ON_FIRST_INVOCATION_END();\n\n for(int i=0; i < 32; i++){ \n TestLog(s_Func_Test_Name_Add_2Num(\"V_VDDA_C_\", i) ,V_VDDA_C[curSite][i]);\n }\n i_funcRes[curSite] = i_funcRes0[curSite] && i_funcRes1[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T10_15_VDDA_LDO_Char_V2\", T10_15_VDDA_LDO_Char_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: ACC bias current trimming\n# - ibias_acc@ANAIO2 by default, invert to anaio1 \n#############################################################################################################\ncmt('Version info: $Revision: 3 $ $Author: hmf1rt $ $Date: 2024/04/23 15:35:23 GMT $')\n# Swap tareget singal to ANAIO1 \nwac('EXT_MODE', 0xc00f) # Switch to the TEST register page\nwcb('tm_se_meas',1)\nwcb('tm_bus_inv',1) # invert ibias_acc to anaio1\n# Config ANAIO pad, TM_PIN\nwcb('tm_int2_en',0x1)\nwcb('tm_int2_sel',0x4) # TB1INP on anaio1\n# Config CTB_P/N, TM_ADDR\nwcb('tm_cfg', 0x1) # CTP_N is IB_ACC\nwcb('tm_addr', 0xe) # COM_TIO_PWR, Signal :TM_PWRBLOCK_EN\n# Trim loop\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('OCP_MASK', 0xf000) # Set masking register\nfor n in range (0, 16, 1):\n cmt('Set trim index to value {} in range (0..15)'.format(n))\n wr('ANA_TRM_BG', n*2**12) # ANA_TRM_BG<15:12> pc_trm_ib_acc\n rac('ANA_TRM_BG', n*2**12, 0xf000)\n uclk('ASCX')\n bw('ASCX', 1)\n dly(271*74e-9)\t # Delay ~20us\n gac(f'I_BIAS_ACC[{n:02d}]', 'INT2', i_range=2e-6)\n log(f'I_BIAS_ACC[{n:02d}]')\n ubw('ASCX')\n clk('ASCX', 1/148e-9)\t\noti('N_OPT_IBIAS_ACC', 'I_BIAS_ACC', -0.9e-6) \nlog('N_OPT_IBIAS_ACC')\notv('I_OPT_IBIAS_ACC', 'I_BIAS_ACC', -0.9e-6) \nlog('I_OPT_IBIAS_ACC')\ncalc('N_ANA_TRM_BG_WR','N_OPT_IBIAS_ACC','<<',12) \nwri('ANA_TRM_BG','N_ANA_TRM_BG_WR')\nras('N_ANA_TRM_BG_RD','ANA_TRM_BG')\ncalc('N_ANA_TRM_BG_RD_15_12','N_ANA_TRM_BG_RD','&',0xf000)\ncalc('N_OPT_IBIAS_ACC_RD','N_ANA_TRM_BG_RD_15_12','>>',12)\ncmt('The test item is a functional fail if N_OPT_IBIAS_ACC_RD != N_OPT_IBIAS_ACC')\n# Clean\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Clean TM_CONF\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T10_16_acc_bias_current_trimming_V3: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n INT split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &split_pat_flag);\n vector s_splited_pat_name;\n const int split_count = 2; // Alarm:: split_count need manual confirm.\n s_splited_pat_name.resize(split_count);\n vector i_comment_line[split_count];\n\n static int N_ANA_TRM_BG_RD[xNSitES];\n static double I_BIAS_ACC[xNSitES][16];\n static int N_OPT_IBIAS_ACC[xNSitES], N_ANA_TRM_BG_WR[xNSitES], N_ANA_TRM_BG_RD_15_12[xNSitES], N_OPT_IBIAS_ACC_RD[xNSitES];\n static double I_OPT_IBIAS_ACC[xNSitES];\n\n ARRAY_LL N_ANA_TRM_BG_WR_rtv(xNSitES);\n const int Wri_Bit_Length = 33;\n const int Wri_Bit_Position = 31;\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n\t rdi.enableOre(oreFlag);\n\t rdi.oreFile(\"./ORE_Files/rdi_ore_T10_16_ACC_BIAS_CURRENT_TRIMMING.xml\");\n\n\t GET_TESTSUITE_NAME(test_name);\n\n\t if (split_pat_flag)\n\t {\n\t\t split_pattern(s_label_name,\"wri\",split_pat_flag,s_splited_pat_name);\n\t }\n\t else\n\t {\n\t\t for (int i = 0; i> 12;\n\n int Func_result0 = rdi.id(\"T10_16_acc_bias_current_trimming_V3_PAT_id0\").getBurstPassFail();\n int Func_result1 = rdi.id(\"T10_16_acc_bias_current_trimming_V3_PAT_id1\").getBurstPassFail();\n FuncPrint(\"Func_result0\", Func_result0);\n FuncPrint(\"Func_result1\", Func_result1);\n int Func_result = 1 * Func_result0 * Func_result1;\n if ((N_OPT_IBIAS_ACC_RD[CURRENT_SITE_NUMBER()-1]) != N_OPT_IBIAS_ACC[CURRENT_SITE_NUMBER()-1]) Func_result=99;\n FuncPrint(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n for (int i = 0; i<10; i++)\n {\n \t TestLog(\"I_BIAS_ACC_0\"+rdi.itos(i), I_BIAS_ACC[CURRENT_SITE_NUMBER()-1][i]);\n }\n for (int i = 10; i<16; i++)\n {\n \t TestLog(\"I_BIAS_ACC_\"+rdi.itos(i), I_BIAS_ACC[CURRENT_SITE_NUMBER()-1][i]);\n }\n TestLog(\"I_OPT_IBIAS_ACC\", I_OPT_IBIAS_ACC[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"N_OPT_IBIAS_ACC\", N_OPT_IBIAS_ACC[CURRENT_SITE_NUMBER()-1]);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T10_16_acc_bias_current_trimming_V3\", T10_16_acc_bias_current_trimming_V3);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 2 $ $Author: laj1mu23 $ $Date: 2024/03/25 20:34:28 GMT $')\nwac('EXT_MODE', 0xc00f) # Switch to the TEST register page\nwac('TM_CONF', 0x0110) # tm_se_meas=1 tm_bus_inv=1 (COM_TION instead of COM_TIOP for BUF1_INP)\nwac('TM_PIN', 0x0009) # tm_int2_sel=4 (BUF1_INP) tm_int2_en=1\nwac('TM_ADDR', 0x010e) # tm_cfg=1 (COM_TB2= IB_ACC, COM_TB1= IB_GYR) tm_addr=e (tm_bus_sel=tm_addr(3:2)=3 (COM_TION/P) COM_TIO_REF;\n # enable the power_ana_test_multiplexor); any tm_addr value except off/0 enables the test module\ndly(100e-6)\ngac('I_BIAS_ACC_M', 'INT2', i_range=2e-6)\n\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T10_17_ACC_bias_current_measurement_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n static double I_BIAS_ACC_M[xNSitES];\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T10_17_ACC_bias_current_measurement_V2_PAT_id\");\n rdi.dc(\"T10_17_ACC_bias_current_measurement_V2DC_id0\").label(s_label_name)\n// Alarm::vForce value had not been assigned in TOI, need manual check\n .insertSub(i_comment_line0[0]).pin(\"INT2\").vForce(0 V).iMeas().valueMode(TA::BADC).iRange(2e-06 A).average(16).measWait(1 ms) //I_BIAS_ACC_M\n .execute();\n RDI_END();\n ON_FIRST_INVOCATION_END();\n \n ARRAY_D JSUB_results_INT2;\n JSUB_results_INT2 = rdi.id(\"T10_17_ACC_bias_current_measurement_V2DC_id0\").getMultiValue(\"INT2\");\n I_BIAS_ACC_M[CURRENT_SITE_NUMBER()-1] = JSUB_results_INT2[0];\n FuncPrint(\"I_BIAS_ACC_M\", I_BIAS_ACC_M[CURRENT_SITE_NUMBER()-1]);\n\n int Func_result = rdi.id(\"T10_17_ACC_bias_current_measurement_V2_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"I_BIAS_ACC_M\", I_BIAS_ACC_M[CURRENT_SITE_NUMBER()-1]);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T10_17_ACC_bias_current_measurement_V2\", T10_17_ACC_bias_current_measurement_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: ACC bias current characterization\n# Characterization loop derived from T10_16_acc_bias_current_trimming\n# - ibias_acc@ANAIO1\n#############################################################################################################\ncmt('Version info: $Revision: 3 $ $Author: luz3sgh $ $Date: 2024/07/02 01:03:26 GMT $')\nwac('EXT_MODE', 0xc00f) # Switch to the TEST register page\nwac('TM_CONF', 0x0110) # tm_se_meas=1 tm_bus_inv=1 (COM_TION instead of COM_TIOP for BUF1_INP)\nwac('TM_PIN', 0x0009) # tm_int2_sel=4 (BUF1_INP) tm_int2_en=1\nwac('TM_ADDR', 0x010e) # tm_cfg=1 (COM_TB2= IB_ACC, COM_TB1= IB_GYR) tm_addr=e (tm_bus_sel=tm_addr(3:2)=3 (COM_TION/P) COM_TIO_REF;\n # enable the power_ana_test_multiplexor); any tm_addr value except off/0 enables the test module\n# Characterization loop\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('OCP_MASK', 0xf000) # Set masking register\nras('REG_VALUE', 'ANA_TRM_BG') # Store the current value\nfor n in range (0, 16, 1):\n cmt('Set trim index to value {} in range (0..15)'.format(n))\n wr('ANA_TRM_BG', n*2**12) # ANA_TRM_BG<15:12> pc_trm_ib_acc\n rac('ANA_TRM_BG', n*2**12, 0xf000)\n dly(271*74e-9) # delay ~20us \n gac(f'I_BIAS_ACC_C[{n:02d}]', 'INT2', i_range=2e-6)\n log(f'I_BIAS_ACC_C[{n:02d}]')\ndly(148e-9)\nwri('ANA_TRM_BG','REG_VALUE')\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n# Clean\nwac('EXT_MODE', 0xc00f) # Switch to the TEST register page\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\n", "output": "/*****************************************************\n * T10_18_ACC_Bias_Current_Char_V3, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n * JSH5SGH: fix some bugs.\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T10_18_ACC_Bias_Current_Char_V3: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 2;\n vector i_comment_line[i_split_count];\n\n static int i_REG_VALUE[xNSitES];\n ARRAY_I aI_Captured_0;\n static double d_I_BIAS_ACC_C[xNSitES][16];\n ARRAY_D ad_I_BIAS_ACC_C;\n\n static int i_WRITE_BACK[xNSitES];\n static int i_vec_Num1[32] = {0};\n static int i_funcRes0[xNSitES], i_funcRes1[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(i_REG_VALUE, 9, xNSitES);\n \n //!\"CTmsg: cut pattern to 2 parts @ oriAVCvecline [4509]\n //!\"CTmsg: cut pattern to 2 parts @ binarypatline [4499]\n if (i_split_pat_flag)\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n }\n else\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n for(int i=0; i }\n valid comment[ 1] @ avcline 1162: {ras('REG_VALUE', 'ANA_TRM_BG')}\n valid comment[ 2] @ avcline 1275: {cmt: Set trim index to value 0 in range (0..15)}\n valid comment[ 3] @ avcline 1476: {gac('I_BIAS_ACC_C[00]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 3] @ avcline 1476: {log('I_BIAS_ACC_C[00]', '', '', 0, 0)}\n valid comment[ 4] @ avcline 1477: {cmt: Set trim index to value 1 in range (0..15)}\n valid comment[ 5] @ avcline 1678: {gac('I_BIAS_ACC_C[01]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 5] @ avcline 1678: {log('I_BIAS_ACC_C[01]', '', '', 0, 0)}\n valid comment[ 6] @ avcline 1679: {cmt: Set trim index to value 2 in range (0..15)}\n valid comment[ 7] @ avcline 1880: {gac('I_BIAS_ACC_C[02]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 7] @ avcline 1880: {log('I_BIAS_ACC_C[02]', '', '', 0, 0)}\n valid comment[ 8] @ avcline 1881: {cmt: Set trim index to value 3 in range (0..15)}\n valid comment[ 9] @ avcline 2082: {gac('I_BIAS_ACC_C[03]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 9] @ avcline 2082: {log('I_BIAS_ACC_C[03]', '', '', 0, 0)}\n valid comment[ 10] @ avcline 2083: {cmt: Set trim index to value 4 in range (0..15)}\n valid comment[ 11] @ avcline 2284: {gac('I_BIAS_ACC_C[04]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 11] @ avcline 2284: {log('I_BIAS_ACC_C[04]', '', '', 0, 0)}\n valid comment[ 12] @ avcline 2285: {cmt: Set trim index to value 5 in range (0..15)}\n valid comment[ 13] @ avcline 2486: {gac('I_BIAS_ACC_C[05]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 13] @ avcline 2486: {log('I_BIAS_ACC_C[05]', '', '', 0, 0)}\n valid comment[ 14] @ avcline 2487: {cmt: Set trim index to value 6 in range (0..15)}\n valid comment[ 15] @ avcline 2688: {gac('I_BIAS_ACC_C[06]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 15] @ avcline 2688: {log('I_BIAS_ACC_C[06]', '', '', 0, 0)}\n valid comment[ 16] @ avcline 2689: {cmt: Set trim index to value 7 in range (0..15)}\n valid comment[ 17] @ avcline 2890: {gac('I_BIAS_ACC_C[07]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 17] @ avcline 2890: {log('I_BIAS_ACC_C[07]', '', '', 0, 0)}\n valid comment[ 18] @ avcline 2891: {cmt: Set trim index to value 8 in range (0..15)}\n valid comment[ 19] @ avcline 3092: {gac('I_BIAS_ACC_C[08]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 19] @ avcline 3092: {log('I_BIAS_ACC_C[08]', '', '', 0, 0)}\n valid comment[ 20] @ avcline 3093: {cmt: Set trim index to value 9 in range (0..15)}\n valid comment[ 21] @ avcline 3294: {gac('I_BIAS_ACC_C[09]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 21] @ avcline 3294: {log('I_BIAS_ACC_C[09]', '', '', 0, 0)}\n valid comment[ 22] @ avcline 3295: {cmt: Set trim index to value 10 in range (0..15)}\n valid comment[ 23] @ avcline 3496: {gac('I_BIAS_ACC_C[10]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 23] @ avcline 3496: {log('I_BIAS_ACC_C[10]', '', '', 0, 0)}\n valid comment[ 24] @ avcline 3497: {cmt: Set trim index to value 11 in range (0..15)}\n valid comment[ 25] @ avcline 3698: {gac('I_BIAS_ACC_C[11]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 25] @ avcline 3698: {log('I_BIAS_ACC_C[11]', '', '', 0, 0)}\n valid comment[ 26] @ avcline 3699: {cmt: Set trim index to value 12 in range (0..15)}\n valid comment[ 27] @ avcline 3900: {gac('I_BIAS_ACC_C[12]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 27] @ avcline 3900: {log('I_BIAS_ACC_C[12]', '', '', 0, 0)}\n valid comment[ 28] @ avcline 3901: {cmt: Set trim index to value 13 in range (0..15)}\n valid comment[ 29] @ avcline 4102: {gac('I_BIAS_ACC_C[13]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 29] @ avcline 4102: {log('I_BIAS_ACC_C[13]', '', '', 0, 0)}\n valid comment[ 30] @ avcline 4103: {cmt: Set trim index to value 14 in range (0..15)}\n valid comment[ 31] @ avcline 4304: {gac('I_BIAS_ACC_C[14]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 31] @ avcline 4304: {log('I_BIAS_ACC_C[14]', '', '', 0, 0)}\n valid comment[ 32] @ avcline 4305: {cmt: Set trim index to value 15 in range (0..15)}\n valid comment[ 33] @ avcline 4506: {gac('I_BIAS_ACC_C[15]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 33] @ avcline 4506: {log('I_BIAS_ACC_C[15]', '', '', 0, 0)}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.digCap(\"digcapid_0\").vecVarOnly().pin(\"SDO\").capMode(TA::SER).bitPerWord(16).samples(1*16).execute();\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][3]).pin(\"INT2\").iMeas().iRange(2 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_ACC_C[00]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][5]).pin(\"INT2\").iMeas().iRange(2 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_ACC_C[01]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][7]).pin(\"INT2\").iMeas().iRange(2 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_ACC_C[02]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][9]).pin(\"INT2\").iMeas().iRange(2 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_ACC_C[03]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][11]).pin(\"INT2\").iMeas().iRange(2 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_ACC_C[04]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][13]).pin(\"INT2\").iMeas().iRange(2 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_ACC_C[05]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][15]).pin(\"INT2\").iMeas().iRange(2 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_ACC_C[06]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][17]).pin(\"INT2\").iMeas().iRange(2 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_ACC_C[07]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][19]).pin(\"INT2\").iMeas().iRange(2 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_ACC_C[08]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][21]).pin(\"INT2\").iMeas().iRange(2 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_ACC_C[09]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][23]).pin(\"INT2\").iMeas().iRange(2 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_ACC_C[10]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][25]).pin(\"INT2\").iMeas().iRange(2 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_ACC_C[11]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][27]).pin(\"INT2\").iMeas().iRange(2 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_ACC_C[12]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][29]).pin(\"INT2\").iMeas().iRange(2 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_ACC_C[13]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][31]).pin(\"INT2\").iMeas().iRange(2 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_ACC_C[14]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][33]).pin(\"INT2\").iMeas().iRange(2 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_ACC_C[15]', 'INT2', 2e-06, 0.0001, True)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n aI_Captured_0 = rdi.id(\"digcapid_0\").getVector(\"SDO\");\n ARRAY_D ad_jsubresults_INT2; ad_jsubresults_INT2.resize(16); ad_jsubresults_INT2.init(-9.9);\n ad_jsubresults_INT2 = rdi.id(\"dcid_0\").getMultiValue(\"INT2\");\n \n aI_Captured_0[0] = Switch_High_Low_Bits_16Bits(aI_Captured_0[0]);\n i_REG_VALUE[curSite] = aI_Captured_0[0];\n FuncPrint(\"REG_VALUE\",i_REG_VALUE[curSite]);\n\n for(int i=0; i<16; i++){\n d_I_BIAS_ACC_C[curSite][i] = ad_jsubresults_INT2[0 + i];\n FuncPrint(\"I_BIAS_ACC_C_\" + rdi.itos(curSite) + \"_\"+ rdi.itos(i) ,d_I_BIAS_ACC_C[curSite][i]);\n }\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n\n /* Ori key coments in subpat1 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 4509: {wri('ANA_TRM_BG', 'REG_VALUE')}\n valid comment[ 1] @ avcline 5548: {Test End: T10_18_ACC_Bias_Current_Char}\n */\n static int i_vec_iposition1[32] = {\n 31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,\n 48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63\n };\n for (int i = 0; i < 32; i++)\n {\n i_vec_Num1[i] = i_vec_iposition1[i];\n }\n FOR_EACH_SITE_BEGIN();\n i_WRITE_BACK[curSite] = Switch_High_Low_Bits_16Bits(i_REG_VALUE[curSite]);\n Func_Vector_Dynamic_Write(s_splited_pat_name[1], \"SDX\", i_vec_Num1, 32, i_WRITE_BACK[curSite], 0, 2); //Notes. TEI check per project\n FOR_EACH_SITE_END();\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id1\");\n rdi.func().label(s_splited_pat_name[1]).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes1[curSite] = rdi.id(\"burst_id1\").getBurstPassFail();\n\n FOR_EACH_SITE_END();\n\n\n }\n\n ON_FIRST_INVOCATION_END();\n\n for(int i=0; i < 16; i++){ \n TestLog(s_Func_Test_Name_Add_2Num(\"I_BIAS_ACC_C_\", i) ,d_I_BIAS_ACC_C[curSite][i]);\n\t }\n i_funcRes[curSite] = i_funcRes0[curSite] && i_funcRes1[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T10_18_ACC_Bias_Current_Char_V3\", T10_18_ACC_Bias_Current_Char_V3);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: GRY bandgap trimming\n# Steps: 1. enable temp adc test mode\n# 2. set ATM, measure VBGP1V21 refer to BGP_REFN\n# 3. trim loop\n#############################################################################################################\nfrom test_sub_functions import *\ncmt('Version info: $Revision: 4 $ $Author: hmf1rt $ $Date: 2024/04/24 07:06:10 GMT $')\nwac('EXT_MODE', 0xc006) # Fcu page.\nwcb('temp_mode',0x1) # FCU_TEST_CONF, temp always on\nwcb('temp_test_odr',0x4) # FCU_TEST_CONF, set temp test ODR to 800\ndly(320e-6) \n# Config Buffer, TM_CONF\nwac('EXT_MODE', 0xc00f) # Page Test, Reg TM_CONF \nwcb('tm_buf_pwrup',0x1) # Enable TB1 only\nwcb('tm_bus_inv',0x1) # Invert tset bus\n# Config ANAIO pad, TM_PIN \nwcb('tm_int2_en',0x1)\nwcb('tm_int2_sel',0x2) # TB1OUT on anaio1\nwcb('tm_asdx_en',0x1)\nwcb('tm_asdx_sel',0x4) # TB2IN on anaio2\n# Config CTB_P/N, TM_ADDR\nwcb('tm_cfg', 0x8) # CTB_P is VBGP_REFN(local gnd), CTP_N is VBGP_1V21\nwcb('tm_addr', 0xe) \n# Trim loop\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('OCP_MASK', 0x003f) # Set masking register\nfor n in range (0, 64, 1):\n cmt('Set trim index to value {} in range (0..64)'.format(n))\n wr('ANA_TRM_OSC', n) # ANA_TRM_OSC<7:0> gyr_trm_res_prog_bg \n rac('ANA_TRM_OSC', n, 0x003f) # only <5:0> used for trimmming\n uclk('ASCX')\n bw('ASCX', 1)\n dly(1352*74e-9)\n cmt(\"TOI: The measurement needs to be done with an accuracy of +/- 1mV\")\n gav(f'V_BGP_G_RAW[{n:03d}]', 'INT2','ASDX')\n calc(f'V_BGP_G[{n:03d}]', f'V_BGP_G_RAW[{n:03d}]','-', 'V_OFF1_ECON')\n log(f'V_BGP_G[{n:03d}]')\n ubw('ASCX')\n clk('ASCX', 1/148e-9)\t\noti('N_OPT_VBGP_G', 'V_BGP_G', 1.21) # Select optimum trim index\nlog('N_OPT_VBGP_G')\notv('V_OPT_VBGP_G', 'V_BGP_G', 1.21) # Select optimum trim value\nlog('V_OPT_VBGP_G')\nwri('ANA_TRM_OSC','N_OPT_VBGP_G')\nras('N_ANA_TRM_OSC_RD','ANA_TRM_OSC')\ncalc('N_OPT_VBGP_G_RD','N_ANA_TRM_OSC_RD','&',0x003f)\nlog('N_OPT_VBGP_G_RD')\ncmt('The test item is a functional fail if N_OPT_VBGP_G_RD != N_OPT_VBGP_G')\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n# Clean\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\nwac('EXT_MODE', 0xc006) # FCU page\nwcb('temp_mode',0x0) # FCU_TEST_CONF\nwcb('temp_test_odr',0x0) # FCU_TEST_CONF \n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T10_21_gyr_bandgap_trimming_V4: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n INT split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &split_pat_flag);\n vector s_splited_pat_name;\n const int split_count = 2; // Alarm:: split_count need manual confirm.\n s_splited_pat_name.resize(split_count);\n vector i_comment_line[split_count];\n\n static int N_OPT_VBGP_G_RD[xNSitES], N_OPT_VBGP_G[xNSitES];\n static double V_BGP_G_RAW[xNSitES][64], V_BGP_G[xNSitES][64], V_OPT_VBGP_G[xNSitES];\n\n ARRAY_LL N_OPT_VBGP_G_rtv(xNSitES);\n const int Wri_Bit_Length = 33;\n const int Wri_Bit_Position = 31;\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n\t\t rdi.enableOre(oreFlag);\n\t\t rdi.oreFile(\"./ORE_Files/rdi_ore_T10_21_GYR_BANDGAP_TRIMMING.xml\");\n\n GET_TESTSUITE_NAME(test_name);\n\n if (split_pat_flag)\n {\n split_pattern(s_label_name,\"wri\",split_pat_flag,s_splited_pat_name);\n }\n else\n {\n for (int i = 0; i i_comment_line0;\n\n static double V_BGP_G_M_RAW[xNSitES], V_BGP_G_M[xNSitES];\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T10_22_GYR_bandgap_measurement_V2_PAT_id\");\n rdi.dc(\"T10_22_GYR_bandgap_measurement_V2DC_id0\").label(s_label_name)\n .insertSub(i_comment_line0[0]).pin(\"INT2,ASDX\",TA::BADC).vMeas().average(128).measWait(1 ms) //V_BGP_G_M_RAW\n .execute();\n RDI_END();\n ON_FIRST_INVOCATION_END();\n\n ARRAY_D JSUB_results_ASDX;\n JSUB_results_ASDX = rdi.id(\"T10_22_GYR_bandgap_measurement_V2DC_id0\").getMultiValue(\"ASDX\");\n ARRAY_D JSUB_results_INT2;\n JSUB_results_INT2 = rdi.id(\"T10_22_GYR_bandgap_measurement_V2DC_id0\").getMultiValue(\"INT2\");\n V_BGP_G_M_RAW[CURRENT_SITE_NUMBER()-1] = JSUB_results_INT2[0] - JSUB_results_ASDX[0];\n V_BGP_G_M[CURRENT_SITE_NUMBER()-1] = V_BGP_G_M_RAW[CURRENT_SITE_NUMBER()-1] - V_OFF1_ECOFF[CURRENT_SITE_NUMBER()-1];\n\n FuncPrint(\"JSUB_results_INT2\", JSUB_results_INT2[0]);\n FuncPrint(\"JSUB_results_ASDX\", JSUB_results_ASDX[0]);\n FuncPrint(\"V_BGP_G_M_RAW\", V_BGP_G_M_RAW[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"V_BGP_G_M\", V_BGP_G_M[CURRENT_SITE_NUMBER()-1]);\n \n int Func_result = rdi.id(\"T10_22_GYR_bandgap_measurement_V2_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"V_BGP_G_M\", V_BGP_G_M[CURRENT_SITE_NUMBER()-1]);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T10_22_GYR_bandgap_measurement_V2\", T10_22_GYR_bandgap_measurement_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: GYR bandgap characterization\n# Characterization loop derived from T10_21_gyr_bandgap_trimming\n# Steps: 1. enable temp adc test mode\n# 2. set ATM, measure VBGP1V21 refer to BGP_REFN\n# 3. Characterization loop\n#############################################################################################################\n#from test_sub_functions import *\ncmt('Version info: $Revision: 3 $ $Author: luz3sgh $ $Date: 2024/07/02 01:44:18 GMT $')\n# Config Buffer, TM_CONF\nwac('EXT_MODE', 0xc00f) # Page Test, Reg TM_CONF \nwcb('tm_buf_pwrup',0x1) # Enable TB1 only\nwcb('tm_bus_inv',0x1) # Invert tset bus\n# Config ANAIO pad, TM_PIN \nwcb('tm_int2_en',0x1)\nwcb('tm_int2_sel',0x2) # TB1OUT on anaio1\nwcb('tm_asdx_en',0x1)\nwcb('tm_asdx_sel',0x4) # TB2IN on anaio2\n# Config CTB_P/N, TM_ADDR\nwcb('tm_cfg', 0x8) # CTB_P is VBGP_REFN(local gnd), CTP_N is VBGP_1V21\nwcb('tm_addr', 0xe) \n# Characterization loop\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('OCP_MASK', 0x003f) # Set masking register\nras('REG_VALUE', 'ANA_TRM_OSC') # Store the current value\nfor n in range (0, 64, 1):\n cmt('Set trim index to value {} in range (0..64)'.format(n))\n wr('ANA_TRM_OSC', n) # ANA_TRM_OSC<7:0> gyr_trm_res_prog_bg \n rac('ANA_TRM_OSC', n, 0x003f) # loop only bits <5:0> \n dly(100e-6)\n cmt(\"TOI: The measurement needs to be done with an accuracy of +/- 1mV\")\n gav(f'V_BGP_G_C_RAW[{n:03d}]', 'INT2','ASDX')\n calc(f'V_BGP_G_C[{n:03d}]', f'V_BGP_G_C_RAW[{n:03d}]','-', 'V_OFF1_ECOFF')\n log(f'V_BGP_G_C[{n:03d}]')\ndly(592e-9)\nwri('ANA_TRM_OSC','REG_VALUE')\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n# Clean\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\nwac('EXT_MODE', 0xc00a) # Page TEMP_DP,Reg TEMP_TEST_TADC, bit<0>\n", "output": "/*****************************************************\n * T10_23_GYR_Bandgap_Char_V3, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n * JSH5SGH: fix some bugs.\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T10_23_GYR_Bandgap_Char_V3: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 2;\n vector i_comment_line[i_split_count];\n\n static int i_REG_VALUE[xNSitES];\n ARRAY_I aI_Captured_0;\n static double d_V_BGP_G_C_RAW[xNSitES][64];\n static double V_BGP_G_C[xNSitES][64];\n ARRAY_D ad_V_BGP_G_C_RAW;\n\n static int i_WRITE_BACK[xNSitES];\n static int i_vec_Num1[32] = {0};\n static int i_funcRes0[xNSitES], i_funcRes1[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(i_REG_VALUE, 9, xNSitES);\n \n //!\"CTmsg: cut pattern to 2 parts @ oriAVCvecline [16499]\n //!\"CTmsg: cut pattern to 2 parts @ binarypatline [16489]\n if (i_split_pat_flag)\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n }\n else\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n for(int i=0; i }\n valid comment[ 1] @ avcline 3386: {ras('REG_VALUE', 'ANA_TRM_OSC')}\n valid comment[ 2] @ avcline 3499: {cmt: Set trim index to value 0 in range (0..64)}\n valid comment[ 3] @ avcline 3701: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 3] @ avcline 3701: {gav('V_BGP_G_C_RAW[000]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 3] @ avcline 3701: {calc('V_BGP_G_C[000]', 'V_BGP_G_C_RAW[000]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 3] @ avcline 3701: {log('V_BGP_G_C[000]', '', '', 0, 0)}\n valid comment[ 4] @ avcline 3702: {cmt: Set trim index to value 1 in range (0..64)}\n valid comment[ 5] @ avcline 3904: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 5] @ avcline 3904: {gav('V_BGP_G_C_RAW[001]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 5] @ avcline 3904: {calc('V_BGP_G_C[001]', 'V_BGP_G_C_RAW[001]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 5] @ avcline 3904: {log('V_BGP_G_C[001]', '', '', 0, 0)}\n valid comment[ 6] @ avcline 3905: {cmt: Set trim index to value 2 in range (0..64)}\n valid comment[ 7] @ avcline 4107: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 7] @ avcline 4107: {gav('V_BGP_G_C_RAW[002]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 7] @ avcline 4107: {calc('V_BGP_G_C[002]', 'V_BGP_G_C_RAW[002]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 7] @ avcline 4107: {log('V_BGP_G_C[002]', '', '', 0, 0)}\n valid comment[ 8] @ avcline 4108: {cmt: Set trim index to value 3 in range (0..64)}\n valid comment[ 9] @ avcline 4310: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 9] @ avcline 4310: {gav('V_BGP_G_C_RAW[003]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 9] @ avcline 4310: {calc('V_BGP_G_C[003]', 'V_BGP_G_C_RAW[003]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 9] @ avcline 4310: {log('V_BGP_G_C[003]', '', '', 0, 0)}\n valid comment[ 10] @ avcline 4311: {cmt: Set trim index to value 4 in range (0..64)}\n valid comment[ 11] @ avcline 4513: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 11] @ avcline 4513: {gav('V_BGP_G_C_RAW[004]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 11] @ avcline 4513: {calc('V_BGP_G_C[004]', 'V_BGP_G_C_RAW[004]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 11] @ avcline 4513: {log('V_BGP_G_C[004]', '', '', 0, 0)}\n valid comment[ 12] @ avcline 4514: {cmt: Set trim index to value 5 in range (0..64)}\n valid comment[ 13] @ avcline 4716: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 13] @ avcline 4716: {gav('V_BGP_G_C_RAW[005]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 13] @ avcline 4716: {calc('V_BGP_G_C[005]', 'V_BGP_G_C_RAW[005]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 13] @ avcline 4716: {log('V_BGP_G_C[005]', '', '', 0, 0)}\n valid comment[ 14] @ avcline 4717: {cmt: Set trim index to value 6 in range (0..64)}\n valid comment[ 15] @ avcline 4919: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 15] @ avcline 4919: {gav('V_BGP_G_C_RAW[006]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 15] @ avcline 4919: {calc('V_BGP_G_C[006]', 'V_BGP_G_C_RAW[006]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 15] @ avcline 4919: {log('V_BGP_G_C[006]', '', '', 0, 0)}\n valid comment[ 16] @ avcline 4920: {cmt: Set trim index to value 7 in range (0..64)}\n valid comment[ 17] @ avcline 5122: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 17] @ avcline 5122: {gav('V_BGP_G_C_RAW[007]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 17] @ avcline 5122: {calc('V_BGP_G_C[007]', 'V_BGP_G_C_RAW[007]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 17] @ avcline 5122: {log('V_BGP_G_C[007]', '', '', 0, 0)}\n valid comment[ 18] @ avcline 5123: {cmt: Set trim index to value 8 in range (0..64)}\n valid comment[ 19] @ avcline 5325: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 19] @ avcline 5325: {gav('V_BGP_G_C_RAW[008]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 19] @ avcline 5325: {calc('V_BGP_G_C[008]', 'V_BGP_G_C_RAW[008]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 19] @ avcline 5325: {log('V_BGP_G_C[008]', '', '', 0, 0)}\n valid comment[ 20] @ avcline 5326: {cmt: Set trim index to value 9 in range (0..64)}\n valid comment[ 21] @ avcline 5528: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 21] @ avcline 5528: {gav('V_BGP_G_C_RAW[009]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 21] @ avcline 5528: {calc('V_BGP_G_C[009]', 'V_BGP_G_C_RAW[009]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 21] @ avcline 5528: {log('V_BGP_G_C[009]', '', '', 0, 0)}\n valid comment[ 22] @ avcline 5529: {cmt: Set trim index to value 10 in range (0..64)}\n valid comment[ 23] @ avcline 5731: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 23] @ avcline 5731: {gav('V_BGP_G_C_RAW[010]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 23] @ avcline 5731: {calc('V_BGP_G_C[010]', 'V_BGP_G_C_RAW[010]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 23] @ avcline 5731: {log('V_BGP_G_C[010]', '', '', 0, 0)}\n valid comment[ 24] @ avcline 5732: {cmt: Set trim index to value 11 in range (0..64)}\n valid comment[ 25] @ avcline 5934: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 25] @ avcline 5934: {gav('V_BGP_G_C_RAW[011]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 25] @ avcline 5934: {calc('V_BGP_G_C[011]', 'V_BGP_G_C_RAW[011]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 25] @ avcline 5934: {log('V_BGP_G_C[011]', '', '', 0, 0)}\n valid comment[ 26] @ avcline 5935: {cmt: Set trim index to value 12 in range (0..64)}\n valid comment[ 27] @ avcline 6137: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 27] @ avcline 6137: {gav('V_BGP_G_C_RAW[012]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 27] @ avcline 6137: {calc('V_BGP_G_C[012]', 'V_BGP_G_C_RAW[012]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 27] @ avcline 6137: {log('V_BGP_G_C[012]', '', '', 0, 0)}\n valid comment[ 28] @ avcline 6138: {cmt: Set trim index to value 13 in range (0..64)}\n valid comment[ 29] @ avcline 6340: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 29] @ avcline 6340: {gav('V_BGP_G_C_RAW[013]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 29] @ avcline 6340: {calc('V_BGP_G_C[013]', 'V_BGP_G_C_RAW[013]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 29] @ avcline 6340: {log('V_BGP_G_C[013]', '', '', 0, 0)}\n valid comment[ 30] @ avcline 6341: {cmt: Set trim index to value 14 in range (0..64)}\n valid comment[ 31] @ avcline 6543: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 31] @ avcline 6543: {gav('V_BGP_G_C_RAW[014]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 31] @ avcline 6543: {calc('V_BGP_G_C[014]', 'V_BGP_G_C_RAW[014]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 31] @ avcline 6543: {log('V_BGP_G_C[014]', '', '', 0, 0)}\n valid comment[ 32] @ avcline 6544: {cmt: Set trim index to value 15 in range (0..64)}\n valid comment[ 33] @ avcline 6746: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 33] @ avcline 6746: {gav('V_BGP_G_C_RAW[015]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 33] @ avcline 6746: {calc('V_BGP_G_C[015]', 'V_BGP_G_C_RAW[015]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 33] @ avcline 6746: {log('V_BGP_G_C[015]', '', '', 0, 0)}\n valid comment[ 34] @ avcline 6747: {cmt: Set trim index to value 16 in range (0..64)}\n valid comment[ 35] @ avcline 6949: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 35] @ avcline 6949: {gav('V_BGP_G_C_RAW[016]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 35] @ avcline 6949: {calc('V_BGP_G_C[016]', 'V_BGP_G_C_RAW[016]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 35] @ avcline 6949: {log('V_BGP_G_C[016]', '', '', 0, 0)}\n valid comment[ 36] @ avcline 6950: {cmt: Set trim index to value 17 in range (0..64)}\n valid comment[ 37] @ avcline 7152: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 37] @ avcline 7152: {gav('V_BGP_G_C_RAW[017]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 37] @ avcline 7152: {calc('V_BGP_G_C[017]', 'V_BGP_G_C_RAW[017]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 37] @ avcline 7152: {log('V_BGP_G_C[017]', '', '', 0, 0)}\n valid comment[ 38] @ avcline 7153: {cmt: Set trim index to value 18 in range (0..64)}\n valid comment[ 39] @ avcline 7355: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 39] @ avcline 7355: {gav('V_BGP_G_C_RAW[018]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 39] @ avcline 7355: {calc('V_BGP_G_C[018]', 'V_BGP_G_C_RAW[018]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 39] @ avcline 7355: {log('V_BGP_G_C[018]', '', '', 0, 0)}\n valid comment[ 40] @ avcline 7356: {cmt: Set trim index to value 19 in range (0..64)}\n valid comment[ 41] @ avcline 7558: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 41] @ avcline 7558: {gav('V_BGP_G_C_RAW[019]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 41] @ avcline 7558: {calc('V_BGP_G_C[019]', 'V_BGP_G_C_RAW[019]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 41] @ avcline 7558: {log('V_BGP_G_C[019]', '', '', 0, 0)}\n valid comment[ 42] @ avcline 7559: {cmt: Set trim index to value 20 in range (0..64)}\n valid comment[ 43] @ avcline 7761: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 43] @ avcline 7761: {gav('V_BGP_G_C_RAW[020]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 43] @ avcline 7761: {calc('V_BGP_G_C[020]', 'V_BGP_G_C_RAW[020]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 43] @ avcline 7761: {log('V_BGP_G_C[020]', '', '', 0, 0)}\n valid comment[ 44] @ avcline 7762: {cmt: Set trim index to value 21 in range (0..64)}\n valid comment[ 45] @ avcline 7964: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 45] @ avcline 7964: {gav('V_BGP_G_C_RAW[021]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 45] @ avcline 7964: {calc('V_BGP_G_C[021]', 'V_BGP_G_C_RAW[021]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 45] @ avcline 7964: {log('V_BGP_G_C[021]', '', '', 0, 0)}\n valid comment[ 46] @ avcline 7965: {cmt: Set trim index to value 22 in range (0..64)}\n valid comment[ 47] @ avcline 8167: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 47] @ avcline 8167: {gav('V_BGP_G_C_RAW[022]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 47] @ avcline 8167: {calc('V_BGP_G_C[022]', 'V_BGP_G_C_RAW[022]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 47] @ avcline 8167: {log('V_BGP_G_C[022]', '', '', 0, 0)}\n valid comment[ 48] @ avcline 8168: {cmt: Set trim index to value 23 in range (0..64)}\n valid comment[ 49] @ avcline 8370: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 49] @ avcline 8370: {gav('V_BGP_G_C_RAW[023]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 49] @ avcline 8370: {calc('V_BGP_G_C[023]', 'V_BGP_G_C_RAW[023]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 49] @ avcline 8370: {log('V_BGP_G_C[023]', '', '', 0, 0)}\n valid comment[ 50] @ avcline 8371: {cmt: Set trim index to value 24 in range (0..64)}\n valid comment[ 51] @ avcline 8573: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 51] @ avcline 8573: {gav('V_BGP_G_C_RAW[024]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 51] @ avcline 8573: {calc('V_BGP_G_C[024]', 'V_BGP_G_C_RAW[024]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 51] @ avcline 8573: {log('V_BGP_G_C[024]', '', '', 0, 0)}\n valid comment[ 52] @ avcline 8574: {cmt: Set trim index to value 25 in range (0..64)}\n valid comment[ 53] @ avcline 8776: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 53] @ avcline 8776: {gav('V_BGP_G_C_RAW[025]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 53] @ avcline 8776: {calc('V_BGP_G_C[025]', 'V_BGP_G_C_RAW[025]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 53] @ avcline 8776: {log('V_BGP_G_C[025]', '', '', 0, 0)}\n valid comment[ 54] @ avcline 8777: {cmt: Set trim index to value 26 in range (0..64)}\n valid comment[ 55] @ avcline 8979: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 55] @ avcline 8979: {gav('V_BGP_G_C_RAW[026]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 55] @ avcline 8979: {calc('V_BGP_G_C[026]', 'V_BGP_G_C_RAW[026]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 55] @ avcline 8979: {log('V_BGP_G_C[026]', '', '', 0, 0)}\n valid comment[ 56] @ avcline 8980: {cmt: Set trim index to value 27 in range (0..64)}\n valid comment[ 57] @ avcline 9182: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 57] @ avcline 9182: {gav('V_BGP_G_C_RAW[027]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 57] @ avcline 9182: {calc('V_BGP_G_C[027]', 'V_BGP_G_C_RAW[027]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 57] @ avcline 9182: {log('V_BGP_G_C[027]', '', '', 0, 0)}\n valid comment[ 58] @ avcline 9183: {cmt: Set trim index to value 28 in range (0..64)}\n valid comment[ 59] @ avcline 9385: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 59] @ avcline 9385: {gav('V_BGP_G_C_RAW[028]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 59] @ avcline 9385: {calc('V_BGP_G_C[028]', 'V_BGP_G_C_RAW[028]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 59] @ avcline 9385: {log('V_BGP_G_C[028]', '', '', 0, 0)}\n valid comment[ 60] @ avcline 9386: {cmt: Set trim index to value 29 in range (0..64)}\n valid comment[ 61] @ avcline 9588: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 61] @ avcline 9588: {gav('V_BGP_G_C_RAW[029]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 61] @ avcline 9588: {calc('V_BGP_G_C[029]', 'V_BGP_G_C_RAW[029]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 61] @ avcline 9588: {log('V_BGP_G_C[029]', '', '', 0, 0)}\n valid comment[ 62] @ avcline 9589: {cmt: Set trim index to value 30 in range (0..64)}\n valid comment[ 63] @ avcline 9791: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 63] @ avcline 9791: {gav('V_BGP_G_C_RAW[030]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 63] @ avcline 9791: {calc('V_BGP_G_C[030]', 'V_BGP_G_C_RAW[030]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 63] @ avcline 9791: {log('V_BGP_G_C[030]', '', '', 0, 0)}\n valid comment[ 64] @ avcline 9792: {cmt: Set trim index to value 31 in range (0..64)}\n valid comment[ 65] @ avcline 9994: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 65] @ avcline 9994: {gav('V_BGP_G_C_RAW[031]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 65] @ avcline 9994: {calc('V_BGP_G_C[031]', 'V_BGP_G_C_RAW[031]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 65] @ avcline 9994: {log('V_BGP_G_C[031]', '', '', 0, 0)}\n valid comment[ 66] @ avcline 9995: {cmt: Set trim index to value 32 in range (0..64)}\n valid comment[ 67] @ avcline 10197: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 67] @ avcline 10197: {gav('V_BGP_G_C_RAW[032]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 67] @ avcline 10197: {calc('V_BGP_G_C[032]', 'V_BGP_G_C_RAW[032]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 67] @ avcline 10197: {log('V_BGP_G_C[032]', '', '', 0, 0)}\n valid comment[ 68] @ avcline 10198: {cmt: Set trim index to value 33 in range (0..64)}\n valid comment[ 69] @ avcline 10400: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 69] @ avcline 10400: {gav('V_BGP_G_C_RAW[033]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 69] @ avcline 10400: {calc('V_BGP_G_C[033]', 'V_BGP_G_C_RAW[033]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 69] @ avcline 10400: {log('V_BGP_G_C[033]', '', '', 0, 0)}\n valid comment[ 70] @ avcline 10401: {cmt: Set trim index to value 34 in range (0..64)}\n valid comment[ 71] @ avcline 10603: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 71] @ avcline 10603: {gav('V_BGP_G_C_RAW[034]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 71] @ avcline 10603: {calc('V_BGP_G_C[034]', 'V_BGP_G_C_RAW[034]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 71] @ avcline 10603: {log('V_BGP_G_C[034]', '', '', 0, 0)}\n valid comment[ 72] @ avcline 10604: {cmt: Set trim index to value 35 in range (0..64)}\n valid comment[ 73] @ avcline 10806: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 73] @ avcline 10806: {gav('V_BGP_G_C_RAW[035]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 73] @ avcline 10806: {calc('V_BGP_G_C[035]', 'V_BGP_G_C_RAW[035]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 73] @ avcline 10806: {log('V_BGP_G_C[035]', '', '', 0, 0)}\n valid comment[ 74] @ avcline 10807: {cmt: Set trim index to value 36 in range (0..64)}\n valid comment[ 75] @ avcline 11009: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 75] @ avcline 11009: {gav('V_BGP_G_C_RAW[036]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 75] @ avcline 11009: {calc('V_BGP_G_C[036]', 'V_BGP_G_C_RAW[036]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 75] @ avcline 11009: {log('V_BGP_G_C[036]', '', '', 0, 0)}\n valid comment[ 76] @ avcline 11010: {cmt: Set trim index to value 37 in range (0..64)}\n valid comment[ 77] @ avcline 11212: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 77] @ avcline 11212: {gav('V_BGP_G_C_RAW[037]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 77] @ avcline 11212: {calc('V_BGP_G_C[037]', 'V_BGP_G_C_RAW[037]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 77] @ avcline 11212: {log('V_BGP_G_C[037]', '', '', 0, 0)}\n valid comment[ 78] @ avcline 11213: {cmt: Set trim index to value 38 in range (0..64)}\n valid comment[ 79] @ avcline 11415: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 79] @ avcline 11415: {gav('V_BGP_G_C_RAW[038]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 79] @ avcline 11415: {calc('V_BGP_G_C[038]', 'V_BGP_G_C_RAW[038]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 79] @ avcline 11415: {log('V_BGP_G_C[038]', '', '', 0, 0)}\n valid comment[ 80] @ avcline 11416: {cmt: Set trim index to value 39 in range (0..64)}\n valid comment[ 81] @ avcline 11618: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 81] @ avcline 11618: {gav('V_BGP_G_C_RAW[039]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 81] @ avcline 11618: {calc('V_BGP_G_C[039]', 'V_BGP_G_C_RAW[039]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 81] @ avcline 11618: {log('V_BGP_G_C[039]', '', '', 0, 0)}\n valid comment[ 82] @ avcline 11619: {cmt: Set trim index to value 40 in range (0..64)}\n valid comment[ 83] @ avcline 11821: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 83] @ avcline 11821: {gav('V_BGP_G_C_RAW[040]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 83] @ avcline 11821: {calc('V_BGP_G_C[040]', 'V_BGP_G_C_RAW[040]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 83] @ avcline 11821: {log('V_BGP_G_C[040]', '', '', 0, 0)}\n valid comment[ 84] @ avcline 11822: {cmt: Set trim index to value 41 in range (0..64)}\n valid comment[ 85] @ avcline 12024: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 85] @ avcline 12024: {gav('V_BGP_G_C_RAW[041]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 85] @ avcline 12024: {calc('V_BGP_G_C[041]', 'V_BGP_G_C_RAW[041]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 85] @ avcline 12024: {log('V_BGP_G_C[041]', '', '', 0, 0)}\n valid comment[ 86] @ avcline 12025: {cmt: Set trim index to value 42 in range (0..64)}\n valid comment[ 87] @ avcline 12227: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 87] @ avcline 12227: {gav('V_BGP_G_C_RAW[042]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 87] @ avcline 12227: {calc('V_BGP_G_C[042]', 'V_BGP_G_C_RAW[042]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 87] @ avcline 12227: {log('V_BGP_G_C[042]', '', '', 0, 0)}\n valid comment[ 88] @ avcline 12228: {cmt: Set trim index to value 43 in range (0..64)}\n valid comment[ 89] @ avcline 12430: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 89] @ avcline 12430: {gav('V_BGP_G_C_RAW[043]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 89] @ avcline 12430: {calc('V_BGP_G_C[043]', 'V_BGP_G_C_RAW[043]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 89] @ avcline 12430: {log('V_BGP_G_C[043]', '', '', 0, 0)}\n valid comment[ 90] @ avcline 12431: {cmt: Set trim index to value 44 in range (0..64)}\n valid comment[ 91] @ avcline 12633: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 91] @ avcline 12633: {gav('V_BGP_G_C_RAW[044]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 91] @ avcline 12633: {calc('V_BGP_G_C[044]', 'V_BGP_G_C_RAW[044]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 91] @ avcline 12633: {log('V_BGP_G_C[044]', '', '', 0, 0)}\n valid comment[ 92] @ avcline 12634: {cmt: Set trim index to value 45 in range (0..64)}\n valid comment[ 93] @ avcline 12836: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 93] @ avcline 12836: {gav('V_BGP_G_C_RAW[045]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 93] @ avcline 12836: {calc('V_BGP_G_C[045]', 'V_BGP_G_C_RAW[045]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 93] @ avcline 12836: {log('V_BGP_G_C[045]', '', '', 0, 0)}\n valid comment[ 94] @ avcline 12837: {cmt: Set trim index to value 46 in range (0..64)}\n valid comment[ 95] @ avcline 13039: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 95] @ avcline 13039: {gav('V_BGP_G_C_RAW[046]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 95] @ avcline 13039: {calc('V_BGP_G_C[046]', 'V_BGP_G_C_RAW[046]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 95] @ avcline 13039: {log('V_BGP_G_C[046]', '', '', 0, 0)}\n valid comment[ 96] @ avcline 13040: {cmt: Set trim index to value 47 in range (0..64)}\n valid comment[ 97] @ avcline 13242: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 97] @ avcline 13242: {gav('V_BGP_G_C_RAW[047]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 97] @ avcline 13242: {calc('V_BGP_G_C[047]', 'V_BGP_G_C_RAW[047]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 97] @ avcline 13242: {log('V_BGP_G_C[047]', '', '', 0, 0)}\n valid comment[ 98] @ avcline 13243: {cmt: Set trim index to value 48 in range (0..64)}\n valid comment[ 99] @ avcline 13445: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[ 99] @ avcline 13445: {gav('V_BGP_G_C_RAW[048]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 99] @ avcline 13445: {calc('V_BGP_G_C[048]', 'V_BGP_G_C_RAW[048]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 99] @ avcline 13445: {log('V_BGP_G_C[048]', '', '', 0, 0)}\n valid comment[100] @ avcline 13446: {cmt: Set trim index to value 49 in range (0..64)}\n valid comment[101] @ avcline 13648: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[101] @ avcline 13648: {gav('V_BGP_G_C_RAW[049]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[101] @ avcline 13648: {calc('V_BGP_G_C[049]', 'V_BGP_G_C_RAW[049]', '-', 'V_OFF1_ECOFF')}\n valid comment[101] @ avcline 13648: {log('V_BGP_G_C[049]', '', '', 0, 0)}\n valid comment[102] @ avcline 13649: {cmt: Set trim index to value 50 in range (0..64)}\n valid comment[103] @ avcline 13851: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[103] @ avcline 13851: {gav('V_BGP_G_C_RAW[050]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[103] @ avcline 13851: {calc('V_BGP_G_C[050]', 'V_BGP_G_C_RAW[050]', '-', 'V_OFF1_ECOFF')}\n valid comment[103] @ avcline 13851: {log('V_BGP_G_C[050]', '', '', 0, 0)}\n valid comment[104] @ avcline 13852: {cmt: Set trim index to value 51 in range (0..64)}\n valid comment[105] @ avcline 14054: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[105] @ avcline 14054: {gav('V_BGP_G_C_RAW[051]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[105] @ avcline 14054: {calc('V_BGP_G_C[051]', 'V_BGP_G_C_RAW[051]', '-', 'V_OFF1_ECOFF')}\n valid comment[105] @ avcline 14054: {log('V_BGP_G_C[051]', '', '', 0, 0)}\n valid comment[106] @ avcline 14055: {cmt: Set trim index to value 52 in range (0..64)}\n valid comment[107] @ avcline 14257: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[107] @ avcline 14257: {gav('V_BGP_G_C_RAW[052]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[107] @ avcline 14257: {calc('V_BGP_G_C[052]', 'V_BGP_G_C_RAW[052]', '-', 'V_OFF1_ECOFF')}\n valid comment[107] @ avcline 14257: {log('V_BGP_G_C[052]', '', '', 0, 0)}\n valid comment[108] @ avcline 14258: {cmt: Set trim index to value 53 in range (0..64)}\n valid comment[109] @ avcline 14460: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[109] @ avcline 14460: {gav('V_BGP_G_C_RAW[053]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[109] @ avcline 14460: {calc('V_BGP_G_C[053]', 'V_BGP_G_C_RAW[053]', '-', 'V_OFF1_ECOFF')}\n valid comment[109] @ avcline 14460: {log('V_BGP_G_C[053]', '', '', 0, 0)}\n valid comment[110] @ avcline 14461: {cmt: Set trim index to value 54 in range (0..64)}\n valid comment[111] @ avcline 14663: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[111] @ avcline 14663: {gav('V_BGP_G_C_RAW[054]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[111] @ avcline 14663: {calc('V_BGP_G_C[054]', 'V_BGP_G_C_RAW[054]', '-', 'V_OFF1_ECOFF')}\n valid comment[111] @ avcline 14663: {log('V_BGP_G_C[054]', '', '', 0, 0)}\n valid comment[112] @ avcline 14664: {cmt: Set trim index to value 55 in range (0..64)}\n valid comment[113] @ avcline 14866: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[113] @ avcline 14866: {gav('V_BGP_G_C_RAW[055]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[113] @ avcline 14866: {calc('V_BGP_G_C[055]', 'V_BGP_G_C_RAW[055]', '-', 'V_OFF1_ECOFF')}\n valid comment[113] @ avcline 14866: {log('V_BGP_G_C[055]', '', '', 0, 0)}\n valid comment[114] @ avcline 14867: {cmt: Set trim index to value 56 in range (0..64)}\n valid comment[115] @ avcline 15069: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[115] @ avcline 15069: {gav('V_BGP_G_C_RAW[056]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[115] @ avcline 15069: {calc('V_BGP_G_C[056]', 'V_BGP_G_C_RAW[056]', '-', 'V_OFF1_ECOFF')}\n valid comment[115] @ avcline 15069: {log('V_BGP_G_C[056]', '', '', 0, 0)}\n valid comment[116] @ avcline 15070: {cmt: Set trim index to value 57 in range (0..64)}\n valid comment[117] @ avcline 15272: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[117] @ avcline 15272: {gav('V_BGP_G_C_RAW[057]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[117] @ avcline 15272: {calc('V_BGP_G_C[057]', 'V_BGP_G_C_RAW[057]', '-', 'V_OFF1_ECOFF')}\n valid comment[117] @ avcline 15272: {log('V_BGP_G_C[057]', '', '', 0, 0)}\n valid comment[118] @ avcline 15273: {cmt: Set trim index to value 58 in range (0..64)}\n valid comment[119] @ avcline 15475: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[119] @ avcline 15475: {gav('V_BGP_G_C_RAW[058]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[119] @ avcline 15475: {calc('V_BGP_G_C[058]', 'V_BGP_G_C_RAW[058]', '-', 'V_OFF1_ECOFF')}\n valid comment[119] @ avcline 15475: {log('V_BGP_G_C[058]', '', '', 0, 0)}\n valid comment[120] @ avcline 15476: {cmt: Set trim index to value 59 in range (0..64)}\n valid comment[121] @ avcline 15678: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[121] @ avcline 15678: {gav('V_BGP_G_C_RAW[059]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[121] @ avcline 15678: {calc('V_BGP_G_C[059]', 'V_BGP_G_C_RAW[059]', '-', 'V_OFF1_ECOFF')}\n valid comment[121] @ avcline 15678: {log('V_BGP_G_C[059]', '', '', 0, 0)}\n valid comment[122] @ avcline 15679: {cmt: Set trim index to value 60 in range (0..64)}\n valid comment[123] @ avcline 15881: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[123] @ avcline 15881: {gav('V_BGP_G_C_RAW[060]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[123] @ avcline 15881: {calc('V_BGP_G_C[060]', 'V_BGP_G_C_RAW[060]', '-', 'V_OFF1_ECOFF')}\n valid comment[123] @ avcline 15881: {log('V_BGP_G_C[060]', '', '', 0, 0)}\n valid comment[124] @ avcline 15882: {cmt: Set trim index to value 61 in range (0..64)}\n valid comment[125] @ avcline 16084: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[125] @ avcline 16084: {gav('V_BGP_G_C_RAW[061]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[125] @ avcline 16084: {calc('V_BGP_G_C[061]', 'V_BGP_G_C_RAW[061]', '-', 'V_OFF1_ECOFF')}\n valid comment[125] @ avcline 16084: {log('V_BGP_G_C[061]', '', '', 0, 0)}\n valid comment[126] @ avcline 16085: {cmt: Set trim index to value 62 in range (0..64)}\n valid comment[127] @ avcline 16287: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[127] @ avcline 16287: {gav('V_BGP_G_C_RAW[062]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[127] @ avcline 16287: {calc('V_BGP_G_C[062]', 'V_BGP_G_C_RAW[062]', '-', 'V_OFF1_ECOFF')}\n valid comment[127] @ avcline 16287: {log('V_BGP_G_C[062]', '', '', 0, 0)}\n valid comment[128] @ avcline 16288: {cmt: Set trim index to value 63 in range (0..64)}\n valid comment[129] @ avcline 16490: {cmt: TOI: The measurement needs to be done with an accuracy of +/- 1mV}\n valid comment[129] @ avcline 16490: {gav('V_BGP_G_C_RAW[063]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[129] @ avcline 16490: {calc('V_BGP_G_C[063]', 'V_BGP_G_C_RAW[063]', '-', 'V_OFF1_ECOFF')}\n valid comment[129] @ avcline 16490: {log('V_BGP_G_C[063]', '', '', 0, 0)}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.digCap(\"digcapid_0\").vecVarOnly().pin(\"SDO\").capMode(TA::SER).bitPerWord(16).samples(1*16).execute();\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][3]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_000//{gav('V_BGP_G_C_RAW[000]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][5]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_001//{gav('V_BGP_G_C_RAW[001]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][7]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_002//{gav('V_BGP_G_C_RAW[002]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][9]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_003//{gav('V_BGP_G_C_RAW[003]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][11]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_004//{gav('V_BGP_G_C_RAW[004]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][13]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_005//{gav('V_BGP_G_C_RAW[005]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][15]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_006//{gav('V_BGP_G_C_RAW[006]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][17]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_007//{gav('V_BGP_G_C_RAW[007]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][19]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_008//{gav('V_BGP_G_C_RAW[008]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][21]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_009//{gav('V_BGP_G_C_RAW[009]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][23]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_010//{gav('V_BGP_G_C_RAW[010]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][25]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_011//{gav('V_BGP_G_C_RAW[011]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][27]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_012//{gav('V_BGP_G_C_RAW[012]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][29]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_013//{gav('V_BGP_G_C_RAW[013]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][31]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_014//{gav('V_BGP_G_C_RAW[014]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][33]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_015//{gav('V_BGP_G_C_RAW[015]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][35]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_016//{gav('V_BGP_G_C_RAW[016]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][37]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_017//{gav('V_BGP_G_C_RAW[017]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][39]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_018//{gav('V_BGP_G_C_RAW[018]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][41]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_019//{gav('V_BGP_G_C_RAW[019]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][43]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_020//{gav('V_BGP_G_C_RAW[020]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][45]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_021//{gav('V_BGP_G_C_RAW[021]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][47]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_022//{gav('V_BGP_G_C_RAW[022]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][49]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_023//{gav('V_BGP_G_C_RAW[023]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][51]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_024//{gav('V_BGP_G_C_RAW[024]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][53]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_025//{gav('V_BGP_G_C_RAW[025]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][55]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_026//{gav('V_BGP_G_C_RAW[026]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][57]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_027//{gav('V_BGP_G_C_RAW[027]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][59]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_028//{gav('V_BGP_G_C_RAW[028]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][61]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_029//{gav('V_BGP_G_C_RAW[029]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][63]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_030//{gav('V_BGP_G_C_RAW[030]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][65]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_031//{gav('V_BGP_G_C_RAW[031]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][67]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_032//{gav('V_BGP_G_C_RAW[032]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][69]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_033//{gav('V_BGP_G_C_RAW[033]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][71]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_034//{gav('V_BGP_G_C_RAW[034]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][73]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_035//{gav('V_BGP_G_C_RAW[035]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][75]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_036//{gav('V_BGP_G_C_RAW[036]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][77]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_037//{gav('V_BGP_G_C_RAW[037]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][79]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_038//{gav('V_BGP_G_C_RAW[038]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][81]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_039//{gav('V_BGP_G_C_RAW[039]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][83]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_040//{gav('V_BGP_G_C_RAW[040]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][85]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_041//{gav('V_BGP_G_C_RAW[041]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][87]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_042//{gav('V_BGP_G_C_RAW[042]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][89]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_043//{gav('V_BGP_G_C_RAW[043]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][91]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_044//{gav('V_BGP_G_C_RAW[044]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][93]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_045//{gav('V_BGP_G_C_RAW[045]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][95]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_046//{gav('V_BGP_G_C_RAW[046]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][97]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_047//{gav('V_BGP_G_C_RAW[047]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][99]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_048//{gav('V_BGP_G_C_RAW[048]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][101]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_049//{gav('V_BGP_G_C_RAW[049]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][103]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_050//{gav('V_BGP_G_C_RAW[050]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][105]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_051//{gav('V_BGP_G_C_RAW[051]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][107]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_052//{gav('V_BGP_G_C_RAW[052]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][109]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_053//{gav('V_BGP_G_C_RAW[053]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][111]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_054//{gav('V_BGP_G_C_RAW[054]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][113]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_055//{gav('V_BGP_G_C_RAW[055]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][115]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_056//{gav('V_BGP_G_C_RAW[056]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][117]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_057//{gav('V_BGP_G_C_RAW[057]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][119]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_058//{gav('V_BGP_G_C_RAW[058]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][121]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_059//{gav('V_BGP_G_C_RAW[059]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][123]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_060//{gav('V_BGP_G_C_RAW[060]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][125]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_061//{gav('V_BGP_G_C_RAW[061]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][127]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_062//{gav('V_BGP_G_C_RAW[062]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][129]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_BGP_G_C_RAW_063//{gav('V_BGP_G_C_RAW[063]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n aI_Captured_0 = rdi.id(\"digcapid_0\").getVector(\"SDO\");\n ARRAY_D ad_jsubresults_INT2; ad_jsubresults_INT2.resize(64); ad_jsubresults_INT2.init(-9.9);\n ARRAY_D ad_jsubresults_ASDX; ad_jsubresults_ASDX.resize(64); ad_jsubresults_ASDX.init(-9.9);\n ad_jsubresults_INT2 = rdi.id(\"dcid_0\").getMultiValue(\"INT2\");\n ad_jsubresults_ASDX = rdi.id(\"dcid_0\").getMultiValue(\"ASDX\");\n \n aI_Captured_0[0] = Switch_High_Low_Bits_16Bits(aI_Captured_0[0]);\n i_REG_VALUE[curSite] = aI_Captured_0[0];\n FuncPrint(\"REG_VALUE\",i_REG_VALUE[curSite]);\n\n for(int i=0; i<64; i++){\n d_V_BGP_G_C_RAW[curSite][i] = ad_jsubresults_INT2[0 + i] - ad_jsubresults_ASDX[0 + i];\n FuncPrint(\"V_BGP_G_C_RAW_\" + rdi.itos(curSite) + \"_\"+ rdi.itos(i) ,d_V_BGP_G_C_RAW[curSite][i]);\n\n V_BGP_G_C[curSite][i] = d_V_BGP_G_C_RAW[curSite][i] - V_OFF1_ECOFF[curSite];\n FuncPrint(s_Func_Test_Name_Add_2Num(\"V_BGP_G_C_\",i), V_BGP_G_C[curSite][i]);\n\t\t\t }\n FOR_EACH_SITE_END();\n\n\n /* Ori key coments in subpat1 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 16499: {wri('ANA_TRM_OSC', 'REG_VALUE')}\n valid comment[ 1] @ avcline 17730: {Test End: T10_23_GYR_Bandgap_Char}\n */\n static int i_vec_iposition1[32] = {\n 31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,\n 48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63\n };\n for (int i = 0; i < 32; i++)\n {\n i_vec_Num1[i] = i_vec_iposition1[i];\n }\n FOR_EACH_SITE_BEGIN();\n i_WRITE_BACK[curSite] = Switch_High_Low_Bits_16Bits(i_REG_VALUE[curSite]);\n Func_Vector_Dynamic_Write(s_splited_pat_name[1], \"SDX\", i_vec_Num1, 32, i_WRITE_BACK[curSite], 0, 2); //Notes. TEI check per project\n //TODO pl.TEI check position & mask\n FOR_EACH_SITE_END();\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id1\");\n rdi.func().label(s_splited_pat_name[1]).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes1[curSite] = rdi.id(\"burst_id1\").getBurstPassFail();\n FuncPrint(\"REG_VALUE\", i_REG_VALUE[curSite]);\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n\n }\n\n ON_FIRST_INVOCATION_END();\n\n for(int i=0; i < 64; i++){ \n \t TestLog(s_Func_Test_Name_Add_2Num(\"V_BGP_G_C_\",i), V_BGP_G_C[curSite][i]);\n }\n// TestLog(\"REG_VALUE\", i_REG_VALUE[curSite]);\n i_funcRes[curSite] = i_funcRes0[curSite] && i_funcRes1[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T10_23_GYR_Bandgap_Char_V3\", T10_23_GYR_Bandgap_Char_V3);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: VDDG LDO trimming, VDDG, typ 1.5V\n#############################################################################################################\nfrom test_sub_functions import *\ncmt('Version info: $Revision: 4 $ $Author: hmf1rt $ $Date: 2024/04/24 11:24:19 GMT $')\nwac('EXT_MODE', 0xc006) # Fcu page.\nwcb('temp_mode',0x1) # FCU_TEST_CONF, temp always on\nwcb('temp_test_odr',0x4) # FCU_TEST_CONF, set temp test ODR to 800\ndly(320e-6) \n# Overwrite power up signal\nwac('EXT_MODE',0xc00d) # Page Test, Reg PMU\nwcb('owr_vddg_en',0x1)\nwcb('gyr_owr_en',0x1)\ndly(100e-6)\n# Config Buffer, TM_CONF\nwac('EXT_MODE', 0xc00f) # Page Test, Reg TM_CONF \nwcb('tm_buf_pwrup',0x1) # Enable TB1 only\nwcb('tm_bus_inv',0x1) # Invert tset bus\n# Config ANAIO pad, TM_PIN\nwcb('tm_int2_en',0x1)\nwcb('tm_int2_sel',0x2) # TB1OUT on anaio1\nwcb('tm_asdx_en',0x1)\nwcb('tm_asdx_sel',0x4) # TB2IN on anaio2\n# Config CTB_P/N, TM_ADDR\nwcb('tm_cfg', 0xb) # VSSG(local gnd)@CTP_P, VDDG@CTP_N\nwcb('tm_addr', 0xd) # COM_TIO_PWR, Signal :TM_PWRBLOCK_EN\n# Trim loop\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('OCP_MASK', 0x07c0) # Set masking register\nfor n in range (0, 32, 1):\n cmt('Set trim index to value {} in range (0..31)'.format(n))\n wr('ANA_TRM_RES_PROG0', n*2**6) # ANA_TRM_RES_PROG0<10:6> gyr_trm_res_prog_ldo_a\n rac('ANA_TRM_RES_PROG0', n*2**6, 0x07c0)\n uclk('ASCX')\n bw('ASCX', 1)\n dly(1352*74e-9)\n gav(f'V_VDDG_LDO_RAW[{n:03d}]', 'INT2','ASDX')\n calc(f'V_VDDG_LDO[{n:03d}]', f'V_VDDG_LDO_RAW[{n:03d}]','-', 'V_OFF1_ECON')\n log(f'V_VDDG_LDO[{n:03d}]')\n ubw('ASCX')\n clk('ASCX', 1/148e-9)\t\noti('N_OPT_VDDG_LDO', 'V_VDDG_LDO', 1.52, criteria='gt') # Select optimum trim index\nlog('N_OPT_VDDG_LDO')\notv('V_OPT_VDDG_LDO', 'V_VDDG_LDO', 1.52, criteria='gt') # Select optimum trim value\nlog('V_OPT_VDDG_LDO')\ncalc('N_ANA_TRM_RES_PROG0_WR','N_OPT_VDDG_LDO','<<',6)\nwri('ANA_TRM_RES_PROG0', 'N_ANA_TRM_RES_PROG0_WR')\nras('N_ANA_TRM_RES_PROG0_RD', 'ANA_TRM_RES_PROG0')\ncalc('N_ANA_TRM_RES_PROG0_10_6','N_ANA_TRM_RES_PROG0_RD','&',0x07c0)\ncalc('N_OPT_VDDG_LDO_RD','N_ANA_TRM_RES_PROG0_10_6','>>',6)\ncmt('The test item is a functional fail if N_OPT_VDDG_LDO_RD != N_OPT_VDDG_LDO')\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n# Clean\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\nwac('EXT_MODE',0xc00d) # Page Test, Reg PMU\nwcb('owr_vddg_en',0x0) # GYR_TEST_OWR1 bit10\nwcb('gyr_owr_en',0x0) # GYR_TEST_OWR1 bit0\nwac('EXT_MODE', 0xc006)\nwcb('temp_mode',0x0) # FCU page, FCU_TEST_CONF\nwcb('temp_test_odr',0x0) # FCU page, FCU_TEST_CONF\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T10_24_vddg_ldo_trimming_V4: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n INT split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &split_pat_flag);\n vector s_splited_pat_name;\n const int split_count = 2; // Alarm:: split_count need manual confirm.\n s_splited_pat_name.resize(split_count);\n vector i_comment_line[split_count];\n\n static int N_ANA_TRM_RES_PROG0_RD[xNSitES], N_OPT_VDDG_LDO[xNSitES], N_ANA_TRM_RES_PROG0_WR[xNSitES], N_ANA_TRM_RES_PROG0_10_6[xNSitES], N_OPT_VDDG_LDO_RD[xNSitES];\n static double V_VDDG_LDO_RAW[xNSitES][32], V_VDDG_LDO[xNSitES][32], V_OPT_VDDG_LDO[xNSitES];\n ARRAY_LL N_ANA_TRM_RES_PROG0_WR_rtv(xNSitES);\n const int Wri_Bit_Length = 33;\n const int Wri_Bit_Position = 31;\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n\t\t rdi.enableOre(oreFlag);\n\t\t rdi.oreFile(\"./ORE_Files/rdi_ore_T10_24_VDDG_LDO_TRIMMING.xml\");\n\n GET_TESTSUITE_NAME(test_name);\n if (split_pat_flag)\n {\n split_pattern(s_label_name,\"wri\",split_pat_flag,s_splited_pat_name);\n }\n else\n {\n for (int i = 0; i>',6)\n// cmt('The test item is a functional fail if N_OPT_VDDG_LDO_RD != N_OPT_VDDG_LDO')\n N_ANA_TRM_RES_PROG0_WR[CURRENT_SITE_NUMBER()-1] = N_OPT_VDDG_LDO[CURRENT_SITE_NUMBER()-1] << 6;\n\n \t FuncPrint(\"N_OPT_VDDG_LDO\", N_OPT_VDDG_LDO[CURRENT_SITE_NUMBER()-1]);\n \t FuncPrint(\"V_OPT_VDDG_LDO\", V_OPT_VDDG_LDO[CURRENT_SITE_NUMBER()-1]);\n \t FuncPrint(\"N_ANA_TRM_RES_PROG0_WR\", N_ANA_TRM_RES_PROG0_WR[CURRENT_SITE_NUMBER()-1]);\n\n \t N_ANA_TRM_RES_PROG0_WR_rtv[CURRENT_SITE_NUMBER()-1] = extend_Pmode_Herschel(N_ANA_TRM_RES_PROG0_WR[CURRENT_SITE_NUMBER()-1], 2);\n \t FuncPrint(\"N_ANA_TRM_RES_PROG0_WR_rtv\", N_ANA_TRM_RES_PROG0_WR_rtv[CURRENT_SITE_NUMBER()-1]);\n FOR_EACH_SITE_END();\n\n rdi.runTimeVal(\"N_ANA_TRM_RES_PROG0_WR_rtv\", N_ANA_TRM_RES_PROG0_WR_rtv);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T10_24_vddg_ldo_trimming_V4_PAT_id1\");\n rdi.digCap(\"T10_24_vddg_ldo_trimming_V4_Digcap_id\").vecVarOnly().pin(\"SDO\").capMode(TA::SER).samples(16*1).bitPerWord(16).execute();\n rdi.smartVec().label(s_splited_pat_name[1]).pin(\"SDX\").writeData(\"N_ANA_TRM_RES_PROG0_WR_rtv\", Wri_Bit_Length, Wri_Bit_Position).execute();\n RDI_END();\n\n }\n ON_FIRST_INVOCATION_END();\n ARRAY_I Vec=rdi.id(\"T10_24_vddg_ldo_trimming_V4_Digcap_id\").getVector();\n N_ANA_TRM_RES_PROG0_RD[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[0]);\n\n N_ANA_TRM_RES_PROG0_10_6[CURRENT_SITE_NUMBER()-1] = N_ANA_TRM_RES_PROG0_RD[CURRENT_SITE_NUMBER()-1] & 1984;\n N_OPT_VDDG_LDO_RD[CURRENT_SITE_NUMBER()-1] = N_ANA_TRM_RES_PROG0_10_6[CURRENT_SITE_NUMBER()-1] >> 6;\n \n int Func_result0 = rdi.id(\"T10_24_vddg_ldo_trimming_V4_PAT_id0\").getBurstPassFail();\n int Func_result1 = rdi.id(\"T10_24_vddg_ldo_trimming_V4_PAT_id1\").getBurstPassFail();\n FuncPrint(\"Func_result0\", Func_result0);\n FuncPrint(\"Func_result1\", Func_result1);\n int Func_result = 1 * Func_result0 * Func_result1;\n if (N_OPT_VDDG_LDO_RD[CURRENT_SITE_NUMBER()-1] != N_OPT_VDDG_LDO[CURRENT_SITE_NUMBER()-1]) Func_result=99;\n FuncPrint(\"Func_result1\", Func_result1);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n for (int i = 0; i<10; i++)\n {\n \t TestLog(\"V_VDDG_LDO_0\"+rdi.itos(i), V_VDDG_LDO[CURRENT_SITE_NUMBER()-1][i]);\n }\n for (int i = 10; i<32; i++)\n {\n \t TestLog(\"V_VDDG_LDO_\"+rdi.itos(i), V_VDDG_LDO[CURRENT_SITE_NUMBER()-1][i]);\n }\n TestLog(\"N_OPT_VDDG_LDO\", N_OPT_VDDG_LDO[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"V_OPT_VDDG_LDO\", V_OPT_VDDG_LDO[CURRENT_SITE_NUMBER()-1]);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T10_24_vddg_ldo_trimming_V4\", T10_24_vddg_ldo_trimming_V4);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 2 $ $Author: laj1mu23 $ $Date: 2024/03/25 20:34:28 GMT $')\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_CONF', 0x0011) # Enable TB1; invert test bus\nwac('TM_PIN', 0x0095) # Enable ANAIO1/2; TB1_OUT on ANAIO1; TB2_INP on ANAIO2\nwac('TM_ADDR', 0x0b0d) # Enable power block on ATM; Connect VDDG/VSSG\ndly(100e-6)\ngav('V_VDDG_LDO_M_RAW', 'INT2','ASDX')\ncalc('V_VDDG_LDO_M', 'V_VDDG_LDO_M_RAW', '-', 'V_OFF1_ECOFF')\nlog('V_VDDG_LDO_M')\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T10_25_VDDG_LDO_measurement_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n static double V_VDDG_LDO_M_RAW[xNSitES],V_VDDG_LDO_M[xNSitES];\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T10_25_VDDG_LDO_measurement_V2_PAT_id\");\n rdi.dc(\"T10_25_VDDG_LDO_measurement_V2DC_id0\").label(s_label_name)\n .insertSub(i_comment_line0[0]).pin(\"INT2,ASDX\",TA::BADC).vMeas().average(128).measWait(1 ms) //V_VDDG_LDO_M_RAW\n .execute();\n RDI_END();\n\n ON_FIRST_INVOCATION_END();\n\n ARRAY_D JSUB_results_ASDX;\n JSUB_results_ASDX = rdi.id(\"T10_25_VDDG_LDO_measurement_V2DC_id0\").getMultiValue(\"ASDX\");\n ARRAY_D JSUB_results_INT2;\n JSUB_results_INT2 = rdi.id(\"T10_25_VDDG_LDO_measurement_V2DC_id0\").getMultiValue(\"INT2\");\n V_VDDG_LDO_M_RAW[CURRENT_SITE_NUMBER()-1] = JSUB_results_INT2[0] - JSUB_results_ASDX[0];\n V_VDDG_LDO_M[CURRENT_SITE_NUMBER()-1] = V_VDDG_LDO_M_RAW[CURRENT_SITE_NUMBER()-1] - V_OFF1_ECOFF[CURRENT_SITE_NUMBER()-1];\n\n FuncPrint(\"JSUB_results_INT2\", JSUB_results_INT2[0]);\n FuncPrint(\"JSUB_results_ASDX\", JSUB_results_ASDX[0]);\n FuncPrint(\"V_VDDG_LDO_M_RAW\", V_VDDG_LDO_M_RAW[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"V_VDDG_LDO_M\", V_VDDG_LDO_M[CURRENT_SITE_NUMBER()-1]);\n \n int Func_result = rdi.id(\"T10_25_VDDG_LDO_measurement_V2_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"V_VDDG_LDO_M\", V_VDDG_LDO_M[CURRENT_SITE_NUMBER()-1]);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T10_25_VDDG_LDO_measurement_V2\", T10_25_VDDG_LDO_measurement_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: VDDG LDO characterization, VDDG, typ 1.5V\n# Characterization loop derived from T10_24_vddg_ldo_trimming\n#############################################################################################################\nfrom test_sub_functions import *\ncmt('Version info: $Revision: 2 $ $Author: laj1mu23 $ $Date: 2024/03/25 20:34:28 GMT $')\n# Config Buffer, TM_CONF\nwac('EXT_MODE', 0xc00f) # Page Test, Reg TM_CONF \nwcb('tm_buf_pwrup',0x1) # Enable TB1 only\nwcb('tm_bus_inv',0x1) # Invert tset bus\n# Config ANAIO pad, TM_PIN\nwcb('tm_int2_en',0x1)\nwcb('tm_int2_sel',0x2) # TB1OUT on anaio1\nwcb('tm_asdx_en',0x1)\nwcb('tm_asdx_sel',0x4) # TB2IN on anaio2\n# Config CTB_P/N, TM_ADDR\nwcb('tm_cfg', 0xb) # VSSG(local gnd)@CTP_P, VDDG@CTP_N\nwcb('tm_addr', 0xd) # COM_TIO_PWR, Signal :TM_PWRBLOCK_EN\n# Characterization loop\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('OCP_MASK', 0x07c0) # Set masking register\nras('REG_VALUE', 'ANA_TRM_RES_PROG0') # Store the current value\nfor n in range (0, 32, 1):\n cmt('Set trim index to value {} in range (0..31)'.format(n))\n wr('ANA_TRM_RES_PROG0', n*2**6) # ANA_TRM_RES_PROG0<10:6> gyr_trm_res_prog_ldo_a\n rac('ANA_TRM_RES_PROG0', n*2**6, 0x07c0)\n dly(100e-6)\n gav(f'V_VDDG_LDO_C_RAW[{n:03d}]', 'INT2','ASDX')\n calc(f'V_VDDG_LDO_C[{n:03d}]', f'V_VDDG_LDO_C_RAW[{n:03d}]','-', 'V_OFF1_ECOFF')\n log(f'V_VDDG_LDO_C[{n:03d}]')\ndly(592e-9)\nwri('ANA_TRM_RES_PROG0', 'REG_VALUE')\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n# Clean\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\n", "output": "/*****************************************************\n * T10_26_VDDG_LDO_Char_V2, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n * JSH5SGH: fix some bugs.\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T10_26_VDDG_LDO_Char_V2: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 2;\n vector i_comment_line[i_split_count];\n\n static int i_REG_VALUE[xNSitES];\n ARRAY_I aI_Captured_0;\n static double d_V_VDDG_LDO_C_RAW[xNSitES][32];\n static double V_VDDG_LDO_C[xNSitES][32];\n ARRAY_D ad_V_VDDG_LDO_C_RAW;\n\n static int i_WRITE_BACK[xNSitES];\n static int i_vec_Num1[32] = {0};\n static int i_funcRes0[xNSitES], i_funcRes1[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(i_REG_VALUE, 9, xNSitES);\n \n //!\"CTmsg: cut pattern to 2 parts @ oriAVCvecline [10003]\n //!\"CTmsg: cut pattern to 2 parts @ binarypatline [9993]\n if (i_split_pat_flag)\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n }\n else\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n for(int i=0; i }\n valid comment[ 1] @ avcline 3386: {ras('REG_VALUE', 'ANA_TRM_RES_PROG0')}\n valid comment[ 2] @ avcline 3499: {cmt: Set trim index to value 0 in range (0..31)}\n valid comment[ 3] @ avcline 3701: {gav('V_VDDG_LDO_C_RAW[000]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 3] @ avcline 3701: {calc('V_VDDG_LDO_C[000]', 'V_VDDG_LDO_C_RAW[000]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 3] @ avcline 3701: {log('V_VDDG_LDO_C[000]', '', '', 0, 0)}\n valid comment[ 4] @ avcline 3702: {cmt: Set trim index to value 1 in range (0..31)}\n valid comment[ 5] @ avcline 3904: {gav('V_VDDG_LDO_C_RAW[001]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 5] @ avcline 3904: {calc('V_VDDG_LDO_C[001]', 'V_VDDG_LDO_C_RAW[001]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 5] @ avcline 3904: {log('V_VDDG_LDO_C[001]', '', '', 0, 0)}\n valid comment[ 6] @ avcline 3905: {cmt: Set trim index to value 2 in range (0..31)}\n valid comment[ 7] @ avcline 4107: {gav('V_VDDG_LDO_C_RAW[002]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 7] @ avcline 4107: {calc('V_VDDG_LDO_C[002]', 'V_VDDG_LDO_C_RAW[002]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 7] @ avcline 4107: {log('V_VDDG_LDO_C[002]', '', '', 0, 0)}\n valid comment[ 8] @ avcline 4108: {cmt: Set trim index to value 3 in range (0..31)}\n valid comment[ 9] @ avcline 4310: {gav('V_VDDG_LDO_C_RAW[003]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 9] @ avcline 4310: {calc('V_VDDG_LDO_C[003]', 'V_VDDG_LDO_C_RAW[003]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 9] @ avcline 4310: {log('V_VDDG_LDO_C[003]', '', '', 0, 0)}\n valid comment[ 10] @ avcline 4311: {cmt: Set trim index to value 4 in range (0..31)}\n valid comment[ 11] @ avcline 4513: {gav('V_VDDG_LDO_C_RAW[004]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 11] @ avcline 4513: {calc('V_VDDG_LDO_C[004]', 'V_VDDG_LDO_C_RAW[004]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 11] @ avcline 4513: {log('V_VDDG_LDO_C[004]', '', '', 0, 0)}\n valid comment[ 12] @ avcline 4514: {cmt: Set trim index to value 5 in range (0..31)}\n valid comment[ 13] @ avcline 4716: {gav('V_VDDG_LDO_C_RAW[005]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 13] @ avcline 4716: {calc('V_VDDG_LDO_C[005]', 'V_VDDG_LDO_C_RAW[005]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 13] @ avcline 4716: {log('V_VDDG_LDO_C[005]', '', '', 0, 0)}\n valid comment[ 14] @ avcline 4717: {cmt: Set trim index to value 6 in range (0..31)}\n valid comment[ 15] @ avcline 4919: {gav('V_VDDG_LDO_C_RAW[006]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 15] @ avcline 4919: {calc('V_VDDG_LDO_C[006]', 'V_VDDG_LDO_C_RAW[006]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 15] @ avcline 4919: {log('V_VDDG_LDO_C[006]', '', '', 0, 0)}\n valid comment[ 16] @ avcline 4920: {cmt: Set trim index to value 7 in range (0..31)}\n valid comment[ 17] @ avcline 5122: {gav('V_VDDG_LDO_C_RAW[007]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 17] @ avcline 5122: {calc('V_VDDG_LDO_C[007]', 'V_VDDG_LDO_C_RAW[007]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 17] @ avcline 5122: {log('V_VDDG_LDO_C[007]', '', '', 0, 0)}\n valid comment[ 18] @ avcline 5123: {cmt: Set trim index to value 8 in range (0..31)}\n valid comment[ 19] @ avcline 5325: {gav('V_VDDG_LDO_C_RAW[008]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 19] @ avcline 5325: {calc('V_VDDG_LDO_C[008]', 'V_VDDG_LDO_C_RAW[008]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 19] @ avcline 5325: {log('V_VDDG_LDO_C[008]', '', '', 0, 0)}\n valid comment[ 20] @ avcline 5326: {cmt: Set trim index to value 9 in range (0..31)}\n valid comment[ 21] @ avcline 5528: {gav('V_VDDG_LDO_C_RAW[009]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 21] @ avcline 5528: {calc('V_VDDG_LDO_C[009]', 'V_VDDG_LDO_C_RAW[009]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 21] @ avcline 5528: {log('V_VDDG_LDO_C[009]', '', '', 0, 0)}\n valid comment[ 22] @ avcline 5529: {cmt: Set trim index to value 10 in range (0..31)}\n valid comment[ 23] @ avcline 5731: {gav('V_VDDG_LDO_C_RAW[010]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 23] @ avcline 5731: {calc('V_VDDG_LDO_C[010]', 'V_VDDG_LDO_C_RAW[010]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 23] @ avcline 5731: {log('V_VDDG_LDO_C[010]', '', '', 0, 0)}\n valid comment[ 24] @ avcline 5732: {cmt: Set trim index to value 11 in range (0..31)}\n valid comment[ 25] @ avcline 5934: {gav('V_VDDG_LDO_C_RAW[011]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 25] @ avcline 5934: {calc('V_VDDG_LDO_C[011]', 'V_VDDG_LDO_C_RAW[011]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 25] @ avcline 5934: {log('V_VDDG_LDO_C[011]', '', '', 0, 0)}\n valid comment[ 26] @ avcline 5935: {cmt: Set trim index to value 12 in range (0..31)}\n valid comment[ 27] @ avcline 6137: {gav('V_VDDG_LDO_C_RAW[012]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 27] @ avcline 6137: {calc('V_VDDG_LDO_C[012]', 'V_VDDG_LDO_C_RAW[012]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 27] @ avcline 6137: {log('V_VDDG_LDO_C[012]', '', '', 0, 0)}\n valid comment[ 28] @ avcline 6138: {cmt: Set trim index to value 13 in range (0..31)}\n valid comment[ 29] @ avcline 6340: {gav('V_VDDG_LDO_C_RAW[013]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 29] @ avcline 6340: {calc('V_VDDG_LDO_C[013]', 'V_VDDG_LDO_C_RAW[013]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 29] @ avcline 6340: {log('V_VDDG_LDO_C[013]', '', '', 0, 0)}\n valid comment[ 30] @ avcline 6341: {cmt: Set trim index to value 14 in range (0..31)}\n valid comment[ 31] @ avcline 6543: {gav('V_VDDG_LDO_C_RAW[014]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 31] @ avcline 6543: {calc('V_VDDG_LDO_C[014]', 'V_VDDG_LDO_C_RAW[014]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 31] @ avcline 6543: {log('V_VDDG_LDO_C[014]', '', '', 0, 0)}\n valid comment[ 32] @ avcline 6544: {cmt: Set trim index to value 15 in range (0..31)}\n valid comment[ 33] @ avcline 6746: {gav('V_VDDG_LDO_C_RAW[015]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 33] @ avcline 6746: {calc('V_VDDG_LDO_C[015]', 'V_VDDG_LDO_C_RAW[015]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 33] @ avcline 6746: {log('V_VDDG_LDO_C[015]', '', '', 0, 0)}\n valid comment[ 34] @ avcline 6747: {cmt: Set trim index to value 16 in range (0..31)}\n valid comment[ 35] @ avcline 6949: {gav('V_VDDG_LDO_C_RAW[016]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 35] @ avcline 6949: {calc('V_VDDG_LDO_C[016]', 'V_VDDG_LDO_C_RAW[016]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 35] @ avcline 6949: {log('V_VDDG_LDO_C[016]', '', '', 0, 0)}\n valid comment[ 36] @ avcline 6950: {cmt: Set trim index to value 17 in range (0..31)}\n valid comment[ 37] @ avcline 7152: {gav('V_VDDG_LDO_C_RAW[017]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 37] @ avcline 7152: {calc('V_VDDG_LDO_C[017]', 'V_VDDG_LDO_C_RAW[017]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 37] @ avcline 7152: {log('V_VDDG_LDO_C[017]', '', '', 0, 0)}\n valid comment[ 38] @ avcline 7153: {cmt: Set trim index to value 18 in range (0..31)}\n valid comment[ 39] @ avcline 7355: {gav('V_VDDG_LDO_C_RAW[018]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 39] @ avcline 7355: {calc('V_VDDG_LDO_C[018]', 'V_VDDG_LDO_C_RAW[018]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 39] @ avcline 7355: {log('V_VDDG_LDO_C[018]', '', '', 0, 0)}\n valid comment[ 40] @ avcline 7356: {cmt: Set trim index to value 19 in range (0..31)}\n valid comment[ 41] @ avcline 7558: {gav('V_VDDG_LDO_C_RAW[019]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 41] @ avcline 7558: {calc('V_VDDG_LDO_C[019]', 'V_VDDG_LDO_C_RAW[019]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 41] @ avcline 7558: {log('V_VDDG_LDO_C[019]', '', '', 0, 0)}\n valid comment[ 42] @ avcline 7559: {cmt: Set trim index to value 20 in range (0..31)}\n valid comment[ 43] @ avcline 7761: {gav('V_VDDG_LDO_C_RAW[020]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 43] @ avcline 7761: {calc('V_VDDG_LDO_C[020]', 'V_VDDG_LDO_C_RAW[020]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 43] @ avcline 7761: {log('V_VDDG_LDO_C[020]', '', '', 0, 0)}\n valid comment[ 44] @ avcline 7762: {cmt: Set trim index to value 21 in range (0..31)}\n valid comment[ 45] @ avcline 7964: {gav('V_VDDG_LDO_C_RAW[021]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 45] @ avcline 7964: {calc('V_VDDG_LDO_C[021]', 'V_VDDG_LDO_C_RAW[021]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 45] @ avcline 7964: {log('V_VDDG_LDO_C[021]', '', '', 0, 0)}\n valid comment[ 46] @ avcline 7965: {cmt: Set trim index to value 22 in range (0..31)}\n valid comment[ 47] @ avcline 8167: {gav('V_VDDG_LDO_C_RAW[022]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 47] @ avcline 8167: {calc('V_VDDG_LDO_C[022]', 'V_VDDG_LDO_C_RAW[022]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 47] @ avcline 8167: {log('V_VDDG_LDO_C[022]', '', '', 0, 0)}\n valid comment[ 48] @ avcline 8168: {cmt: Set trim index to value 23 in range (0..31)}\n valid comment[ 49] @ avcline 8370: {gav('V_VDDG_LDO_C_RAW[023]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 49] @ avcline 8370: {calc('V_VDDG_LDO_C[023]', 'V_VDDG_LDO_C_RAW[023]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 49] @ avcline 8370: {log('V_VDDG_LDO_C[023]', '', '', 0, 0)}\n valid comment[ 50] @ avcline 8371: {cmt: Set trim index to value 24 in range (0..31)}\n valid comment[ 51] @ avcline 8573: {gav('V_VDDG_LDO_C_RAW[024]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 51] @ avcline 8573: {calc('V_VDDG_LDO_C[024]', 'V_VDDG_LDO_C_RAW[024]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 51] @ avcline 8573: {log('V_VDDG_LDO_C[024]', '', '', 0, 0)}\n valid comment[ 52] @ avcline 8574: {cmt: Set trim index to value 25 in range (0..31)}\n valid comment[ 53] @ avcline 8776: {gav('V_VDDG_LDO_C_RAW[025]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 53] @ avcline 8776: {calc('V_VDDG_LDO_C[025]', 'V_VDDG_LDO_C_RAW[025]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 53] @ avcline 8776: {log('V_VDDG_LDO_C[025]', '', '', 0, 0)}\n valid comment[ 54] @ avcline 8777: {cmt: Set trim index to value 26 in range (0..31)}\n valid comment[ 55] @ avcline 8979: {gav('V_VDDG_LDO_C_RAW[026]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 55] @ avcline 8979: {calc('V_VDDG_LDO_C[026]', 'V_VDDG_LDO_C_RAW[026]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 55] @ avcline 8979: {log('V_VDDG_LDO_C[026]', '', '', 0, 0)}\n valid comment[ 56] @ avcline 8980: {cmt: Set trim index to value 27 in range (0..31)}\n valid comment[ 57] @ avcline 9182: {gav('V_VDDG_LDO_C_RAW[027]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 57] @ avcline 9182: {calc('V_VDDG_LDO_C[027]', 'V_VDDG_LDO_C_RAW[027]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 57] @ avcline 9182: {log('V_VDDG_LDO_C[027]', '', '', 0, 0)}\n valid comment[ 58] @ avcline 9183: {cmt: Set trim index to value 28 in range (0..31)}\n valid comment[ 59] @ avcline 9385: {gav('V_VDDG_LDO_C_RAW[028]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 59] @ avcline 9385: {calc('V_VDDG_LDO_C[028]', 'V_VDDG_LDO_C_RAW[028]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 59] @ avcline 9385: {log('V_VDDG_LDO_C[028]', '', '', 0, 0)}\n valid comment[ 60] @ avcline 9386: {cmt: Set trim index to value 29 in range (0..31)}\n valid comment[ 61] @ avcline 9588: {gav('V_VDDG_LDO_C_RAW[029]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 61] @ avcline 9588: {calc('V_VDDG_LDO_C[029]', 'V_VDDG_LDO_C_RAW[029]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 61] @ avcline 9588: {log('V_VDDG_LDO_C[029]', '', '', 0, 0)}\n valid comment[ 62] @ avcline 9589: {cmt: Set trim index to value 30 in range (0..31)}\n valid comment[ 63] @ avcline 9791: {gav('V_VDDG_LDO_C_RAW[030]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 63] @ avcline 9791: {calc('V_VDDG_LDO_C[030]', 'V_VDDG_LDO_C_RAW[030]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 63] @ avcline 9791: {log('V_VDDG_LDO_C[030]', '', '', 0, 0)}\n valid comment[ 64] @ avcline 9792: {cmt: Set trim index to value 31 in range (0..31)}\n valid comment[ 65] @ avcline 9994: {gav('V_VDDG_LDO_C_RAW[031]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 65] @ avcline 9994: {calc('V_VDDG_LDO_C[031]', 'V_VDDG_LDO_C_RAW[031]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 65] @ avcline 9994: {log('V_VDDG_LDO_C[031]', '', '', 0, 0)}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.digCap(\"digcapid_0\").vecVarOnly().pin(\"SDO\").capMode(TA::SER).bitPerWord(16).samples(1*16).execute();\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][3]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDG_LDO_C_RAW_000//{gav('V_VDDG_LDO_C_RAW[000]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][5]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDG_LDO_C_RAW_001//{gav('V_VDDG_LDO_C_RAW[001]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][7]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDG_LDO_C_RAW_002//{gav('V_VDDG_LDO_C_RAW[002]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][9]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDG_LDO_C_RAW_003//{gav('V_VDDG_LDO_C_RAW[003]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][11]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDG_LDO_C_RAW_004//{gav('V_VDDG_LDO_C_RAW[004]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][13]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDG_LDO_C_RAW_005//{gav('V_VDDG_LDO_C_RAW[005]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][15]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDG_LDO_C_RAW_006//{gav('V_VDDG_LDO_C_RAW[006]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][17]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDG_LDO_C_RAW_007//{gav('V_VDDG_LDO_C_RAW[007]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][19]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDG_LDO_C_RAW_008//{gav('V_VDDG_LDO_C_RAW[008]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][21]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDG_LDO_C_RAW_009//{gav('V_VDDG_LDO_C_RAW[009]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][23]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDG_LDO_C_RAW_010//{gav('V_VDDG_LDO_C_RAW[010]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][25]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDG_LDO_C_RAW_011//{gav('V_VDDG_LDO_C_RAW[011]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][27]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDG_LDO_C_RAW_012//{gav('V_VDDG_LDO_C_RAW[012]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][29]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDG_LDO_C_RAW_013//{gav('V_VDDG_LDO_C_RAW[013]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][31]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDG_LDO_C_RAW_014//{gav('V_VDDG_LDO_C_RAW[014]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][33]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDG_LDO_C_RAW_015//{gav('V_VDDG_LDO_C_RAW[015]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][35]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDG_LDO_C_RAW_016//{gav('V_VDDG_LDO_C_RAW[016]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][37]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDG_LDO_C_RAW_017//{gav('V_VDDG_LDO_C_RAW[017]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][39]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDG_LDO_C_RAW_018//{gav('V_VDDG_LDO_C_RAW[018]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][41]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDG_LDO_C_RAW_019//{gav('V_VDDG_LDO_C_RAW[019]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][43]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDG_LDO_C_RAW_020//{gav('V_VDDG_LDO_C_RAW[020]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][45]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDG_LDO_C_RAW_021//{gav('V_VDDG_LDO_C_RAW[021]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][47]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDG_LDO_C_RAW_022//{gav('V_VDDG_LDO_C_RAW[022]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][49]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDG_LDO_C_RAW_023//{gav('V_VDDG_LDO_C_RAW[023]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][51]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDG_LDO_C_RAW_024//{gav('V_VDDG_LDO_C_RAW[024]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][53]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDG_LDO_C_RAW_025//{gav('V_VDDG_LDO_C_RAW[025]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][55]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDG_LDO_C_RAW_026//{gav('V_VDDG_LDO_C_RAW[026]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][57]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDG_LDO_C_RAW_027//{gav('V_VDDG_LDO_C_RAW[027]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][59]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDG_LDO_C_RAW_028//{gav('V_VDDG_LDO_C_RAW[028]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][61]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDG_LDO_C_RAW_029//{gav('V_VDDG_LDO_C_RAW[029]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][63]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDG_LDO_C_RAW_030//{gav('V_VDDG_LDO_C_RAW[030]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][65]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VDDG_LDO_C_RAW_031//{gav('V_VDDG_LDO_C_RAW[031]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n aI_Captured_0 = rdi.id(\"digcapid_0\").getVector(\"SDO\");\n ARRAY_D ad_jsubresults_INT2; ad_jsubresults_INT2.resize(32); ad_jsubresults_INT2.init(-9.9);\n ARRAY_D ad_jsubresults_ASDX; ad_jsubresults_ASDX.resize(32); ad_jsubresults_ASDX.init(-9.9);\n ad_jsubresults_INT2 = rdi.id(\"dcid_0\").getMultiValue(\"INT2\");\n ad_jsubresults_ASDX = rdi.id(\"dcid_0\").getMultiValue(\"ASDX\");\n \n aI_Captured_0[0] = Switch_High_Low_Bits_16Bits(aI_Captured_0[0]);\n i_REG_VALUE[curSite] = aI_Captured_0[0];\n FuncPrint(\"REG_VALUE\",i_REG_VALUE[curSite]);\n\n for(int i=0; i<32; i++){\n d_V_VDDG_LDO_C_RAW[curSite][i] = ad_jsubresults_INT2[0 + i] - ad_jsubresults_ASDX[0 + i];\n V_VDDG_LDO_C[curSite][i] = d_V_VDDG_LDO_C_RAW[curSite][i] - V_OFF1_ECOFF[curSite];\n FuncPrint(\"V_VDDG_LDO_C_RAW_\" + rdi.itos(curSite) + \"_\"+ rdi.itos(i) ,d_V_VDDG_LDO_C_RAW[curSite][i]);\n FuncPrint(s_Func_Test_Name_Add_2Num(\"V_VDDG_LDO_C_\", i), V_VDDG_LDO_C[curSite][i]);\n\t\t\t }\n FOR_EACH_SITE_END();\n\n\n /* Ori key coments in subpat1 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10003: {wri('ANA_TRM_RES_PROG0', 'REG_VALUE')}\n valid comment[ 1] @ avcline 11042: {Test End: T10_26_VDDG_LDO_Char}\n */\n static int i_vec_iposition1[32] = {\n 31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,\n 48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63\n };\n for (int i = 0; i < 32; i++)\n {\n i_vec_Num1[i] = i_vec_iposition1[i];\n }\n FOR_EACH_SITE_BEGIN();\n i_WRITE_BACK[curSite] = Switch_High_Low_Bits_16Bits(i_REG_VALUE[curSite]);\n Func_Vector_Dynamic_Write(s_splited_pat_name[1], \"SDX\", i_vec_Num1, 32, i_WRITE_BACK[curSite], 0, 2); //Notes. TEI check per project\n\n FOR_EACH_SITE_END();\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id1\");\n rdi.func().label(s_splited_pat_name[1]).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes1[curSite] = rdi.id(\"burst_id1\").getBurstPassFail();\n\n FOR_EACH_SITE_END();\n\n\n }\n\n ON_FIRST_INVOCATION_END();\n\n for(int i=0; i < 32; i++){ \n \t TestLog(s_Func_Test_Name_Add_2Num(\"V_VDDG_LDO_C_\", i), V_VDDG_LDO_C[curSite][i]);\n }\n i_funcRes[curSite] = i_funcRes0[curSite] && i_funcRes1[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T10_26_VDDG_LDO_Char_V2\", T10_26_VDDG_LDO_Char_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: GYRA bias current trimming\n# ib_gyr@ANAIO1\n# Notes: 1. gyr_trm_res_prog_i selected from trim loop\n# 2. gry_trm_res_prog_i2/a/fe/vco calculated based on gyr_trm_res_prog_i\n#############################################################################################################\ncmt('Version info: $Revision: 3 $ $Author: hmf1rt $ $Date: 2024/04/24 09:42:55 GMT $')\nwac('EXT_MODE', 0xc006) # Fcu page.\nwcb('temp_mode',0x1) # FCU_TEST_CONF, temp always on\nwcb('temp_test_odr',0x4) # FCU_TEST_CONF, set temp test ODR to 800\ndly(320e-6) \n# Config ANAIO pad, TM_PIN\nwac('EXT_MODE', 0xc00f) # Page Test, Reg TM_PIN\nwcb('tm_int2_en',0x1)\nwcb('tm_int2_sel',0x4) # TB1INP on anaio1\n# Config CTB_P/N, TM_ADDR\nwcb('tm_cfg', 0x1) # IB_GRY@CTP_P, IB_ACC@CTP_N\nwcb('tm_addr', 0xe) # COM_TIO_PWR, Signal :TM_PWRBLOCK_EN\n# Trim loop\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('OCP_MASK', 0x003f) # Set masking register\nfor n in range (0, 64, 1):\n cmt('Set trim index to value {} in range (0..63)'.format(n))\n wr('ANA_TRM_RES_PROG1', n) # <5:0> gyr_trm_res_prog_i\n rac('ANA_TRM_RES_PROG1', n, 0x003f)\n uclk('ASCX')\n bw('ASCX', 1)\n dly(271*74e-9)\t # Delay ~20us\n gac(f'I_BIAS_G[{n:02d}]', 'INT2', i_range=2e-6)\n log(f'I_BIAS_G[{n:02d}]')\n ubw('ASCX')\n clk('ASCX', 1/148e-9)\t\noti('N_OPT_IBIAS_G', 'I_BIAS_G', -2.5e-6) \nlog('N_OPT_IBIAS_G')\notv('I_OPT_IBIAS_G', 'I_BIAS_G', -2.5e-6) \nlog('I_OPT_IBIAS_G')\n# Write REG ANA_TRM_RES_PROG1\ncalc('RES_PROG_I','N_OPT_IBIAS_G') # <5:0> of ANA_TRM_RES_PROG1\ncalc('N_OPT_IBIAS_G_54','N_OPT_IBIAS_G','>>',4)\ncalc('RES_PROG_I2','N_OPT_IBIAS_G_54','<<',6) # <7:6> of ANA_TRM_RES_PROG1\ncalc('RES_PROG_A','N_OPT_IBIAS_G','<<',10) # <15:10> of ANA_TRM_RES_PROG1\nwri('ANA_TRM_RES_PROG1','RES_PROG_I') # current mask still 0x003f\nwr('OCP_MASK',0x0000)\nrac('OCP_MASK',0xffff)\nwac('OCP_MASK',0x00c0)\nwri('ANA_TRM_RES_PROG1','RES_PROG_I2')\nwr('OCP_MASK',0x0000)\nrac('OCP_MASK',0xffff)\nwac('OCP_MASK',0xfc00)\nwri('ANA_TRM_RES_PROG1','RES_PROG_A')\nwr('OCP_MASK',0x0000)\nrac('OCP_MASK',0xffff)\n# Read & Check ANA_TRM_RES_PROG1\nras('N_ANA_TRM_RES_PROG1_RD','ANA_TRM_RES_PROG1')\ncalc('RES_PROG_I_RD','N_ANA_TRM_RES_PROG1_RD', '&', 0x003f)\ncalc('N_ANA_TRM_RES_PROG1_RD_7_6','N_ANA_TRM_RES_PROG1_RD', '&', 0x00c0)\ncalc('RES_PROG_I2_RD','N_ANA_TRM_RES_PROG1_RD_7_6', '>>', 6)\ncalc('N_ANA_TRM_RES_PROG1_RD_15_10','N_ANA_TRM_RES_PROG1_RD', '&', 0xfc00)\ncalc('RES_PROG_A_RD','N_ANA_TRM_RES_PROG1_RD_15_10', '>>', 10)\nlog('RES_PROG_I_RD')\nlog('RES_PROG_I2_RD')\nlog('RES_PROG_A_RD')\ncmt('This item is fucntion fail if RES_PROG_I_RD != N_OPT_IBIAS_G')\ncmt('This item is fucntion fail if RES_PROG_I2_RD != N_OPT_IBIAS_G_54')\ncmt('This item is fucntion fail if RES_PROG_A_RD != N_OPT_IBIAS_G')\n# Write REG ANA_TRM_RES_PROG2\ncalc('RES_PROG_FE','N_OPT_IBIAS_G') # <5:0> of ANA_TRM_RES_PROG2\ncalc('RES_PROG_VCO','N_OPT_IBIAS_G','<<',8) # <13:8> of ANA_TRM_RES_PROG2\nwac('OCP_MASK',0x003f)\nwri('ANA_TRM_RES_PROG2','RES_PROG_FE')\nwr('OCP_MASK',0x0000)\nrac('OCP_MASK',0xffff)\nwac('OCP_MASK',0x3f00)\nwri('ANA_TRM_RES_PROG2','RES_PROG_VCO')\nwr('OCP_MASK',0x0000)\nrac('OCP_MASK',0xffff)\n# Read & Check ANA_TRM_RES_PROG2\nras('N_ANA_TRM_RES_PROG2_RD','ANA_TRM_RES_PROG2')\ncalc('RES_PROG_FE_RD','N_ANA_TRM_RES_PROG2_RD', '&', 0x003f)\ncalc('RES_PROG_VCO_RD','N_ANA_TRM_RES_PROG2_RD', '&', 0x3f00)\nlog('RES_PROG_FE_RD')\nlog('RES_PROG_VCO_RD')\ncmt('This item is fucntion fail if RES_PROG_FE_RD != RES_PROG_FE')\ncmt('This item is fucntion fail if RES_PROG_VCO_RD != RES_PROG_VCO')\n# Clean\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('EXT_MODE', 0xc006) # FCU page\nwcb('temp_mode',0x0) # FCU_TEST_CONF\nwcb('temp_test_odr',0x0) # FCU_TEST_CONF \n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T10_27_gyr_bias_current_trimming_V3: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n INT split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &split_pat_flag);\n vector s_splited_pat_name;\n const int split_count = 6; // Alarm:: split_count need manual confirm.\n s_splited_pat_name.resize(split_count);\n vector i_comment_line[split_count];\n\n\n static int N_OPT_IBIAS_G[xNSitES];\n static double I_BIAS_G[xNSitES][64], I_OPT_IBIAS_G[xNSitES];\n static int RES_PROG_I[xNSitES], N_OPT_IBIAS_G_54[xNSitES], RES_PROG_I2[xNSitES], RES_PROG_A[xNSitES];\n static int N_ANA_TRM_RES_PROG1_RD[xNSitES], RES_PROG_I_RD[xNSitES], N_ANA_TRM_RES_PROG1_RD_7_6[xNSitES], RES_PROG_I2_RD[xNSitES], N_ANA_TRM_RES_PROG1_RD_15_10[xNSitES];\n static int RES_PROG_A_RD[xNSitES], RES_PROG_FE[xNSitES], RES_PROG_VCO[xNSitES], RES_PROG_FE_RD[xNSitES], RES_PROG_VCO_RD[xNSitES], N_ANA_TRM_RES_PROG2_RD[xNSitES];\n\n ARRAY_LL RES_PROG_I_rtv(xNSitES), RES_PROG_I2_rtv(xNSitES), RES_PROG_A_rtv(xNSitES);\n ARRAY_LL RES_PROG_FE_rtv(xNSitES), RES_PROG_VCO_rtv(xNSitES);\n const int Wri_Bit_Length = 33;\n const int Wri_Bit_Position = 31;\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n\t rdi.enableOre(oreFlag);\n\t rdi.oreFile(\"./ORE_Files/rdi_ore_T10_27_GYR_BIAS_CURRENT_TRIMMING.xml\");\n\n GET_TESTSUITE_NAME(test_name);\n\n if (split_pat_flag)\n {\n split_pattern(s_label_name,\"wri\",split_pat_flag,s_splited_pat_name);\n }\n else\n {\n for (int i = 0; i of ANA_TRM_RES_PROG1\n// calc('N_OPT_IBIAS_G_54','N_OPT_IBIAS_G','>>',4)\n// calc('RES_PROG_I2','N_OPT_IBIAS_G_54','<<',6) # <7:6> of ANA_TRM_RES_PROG1\n// calc('RES_PROG_A','N_OPT_IBIAS_G','<<',10) # <15:10> of ANA_TRM_RES_PROG1\n// wri('ANA_TRM_RES_PROG1','RES_PROG_I') # current mask still 0x003f\n// wr('OCP_MASK',0x0000)\n// rac('OCP_MASK',0xffff)\n// wac('OCP_MASK',0x00c0)\n// wri('ANA_TRM_RES_PROG1','RES_PROG_I2')\n// wr('OCP_MASK',0x0000)\n// rac('OCP_MASK',0xffff)\n// wac('OCP_MASK',0xfc00)\n// wri('ANA_TRM_RES_PROG1','RES_PROG_A')\n// wr('OCP_MASK',0x0000)\n// rac('OCP_MASK',0xffff)\n// # Read & Check ANA_TRM_RES_PROG1\n// ras('N_ANA_TRM_RES_PROG1_RD','ANA_TRM_RES_PROG1')\n// calc('RES_PROG_I_RD','N_ANA_TRM_RES_PROG1_RD', '&', 0x003f)\n// calc('N_ANA_TRM_RES_PROG1_RD_7_6','N_ANA_TRM_RES_PROG1_RD', '&', 0x00c0)\n// calc('RES_PROG_I2_RD','N_ANA_TRM_RES_PROG1_RD_7_6', '>>', 6)\n// calc('N_ANA_TRM_RES_PROG1_RD_15_10','N_ANA_TRM_RES_PROG1_RD', '&', 0xfc00)\n// calc('RES_PROG_A_RD','N_ANA_TRM_RES_PROG1_RD_15_10', '>>', 10)\n// log('RES_PROG_I_RD')\n// log('RES_PROG_I2_RD')\n// log('RES_PROG_A_RD')\n// cmt('This item is fucntion fail if RES_PROG_I_RD != N_OPT_IBIAS_G')\n// cmt('This item is fucntion fail if RES_PROG_I2_RD != N_OPT_IBIAS_G_54')\n// cmt('This item is fucntion fail if RES_PROG_A_RD != N_OPT_IBIAS_G')\n// # Write REG ANA_TRM_RES_PROG2\n// calc('RES_PROG_FE','N_OPT_IBIAS_G') # <5:0> of ANA_TRM_RES_PROG2\n// calc('RES_PROG_VCO','N_OPT_IBIAS_G','<<',8) # <13:8> of ANA_TRM_RES_PROG2\n// wac('OCP_MASK',0x003f)\n// wri('ANA_TRM_RES_PROG2','RES_PROG_FE')\n// wr('OCP_MASK',0x0000)\n// rac('OCP_MASK',0xffff)\n// wac('OCP_MASK',0x3f00)\n// wri('ANA_TRM_RES_PROG2','RES_PROG_VCO')\n// wr('OCP_MASK',0x0000)\n// rac('OCP_MASK',0xffff)\n// # Read & Check ANA_TRM_RES_PROG2\n// ras('N_ANA_TRM_RES_PROG2_RD','ANA_TRM_RES_PROG2')\n// calc('RES_PROG_FE_RD','N_ANA_TRM_RES_PROG2_RD', '&', 0x003f)\n// calc('RES_PROG_VCO_RD','N_ANA_TRM_RES_PROG2_RD', '&', 0x3f00)\n// log('RES_PROG_FE_RD')\n// log('RES_PROG_VCO_RD')\n// cmt('This item is fucntion fail if RES_PROG_FE_RD != RES_PROG_FE')\n// cmt('This item is fucntion fail if RES_PROG_VCO_RD != RES_PROG_VCO')\n\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T10_27_gyr_bias_current_trimming_V3_PAT_id0\");\n for (int i = 0; i<64; i++)\n {\n \t rdi.dc(\"T10_27_gyr_bias_current_trimming_V3DC_id0\").label(s_splited_pat_name[0])// Alarm::vForce value had not been assigned in TOI, need manual check\n\t\t\t\t\t\t\t\t.insertSub(i_comment_line[0][i]).pin(\"INT2\").vForce(0 V).iMeas().valueMode(TA::BADC).iRange(1e-05 A).average(32).measWait(1 ms).cont();\n }\n rdi.dc(\"T10_27_gyr_bias_current_trimming_V3DC_id0\").execute();\n RDI_END();\n\n FOR_EACH_SITE_BEGIN();\n\t\t\t ARRAY_D JSUB_results_INT2;\n\t\t\t JSUB_results_INT2 = rdi.id(\"T10_27_gyr_bias_current_trimming_V3DC_id0\").getMultiValue(\"INT2\");\n\t\t\t for (int i = 0; i<64; i++)\n\t\t\t {\n\t\t\t\t I_BIAS_G[CURRENT_SITE_NUMBER()-1][i] = JSUB_results_INT2[i];\n\t\t\t\t FuncPrint(\"I_BIAS_G_\"+rdi.itos(i), I_BIAS_G[CURRENT_SITE_NUMBER()-1][i]);\n\t\t\t }\n\n\t\t\t N_OPT_IBIAS_G[CURRENT_SITE_NUMBER()-1] = i_Func_Optimal_Trim_Val(I_BIAS_G[CURRENT_SITE_NUMBER()-1], Target_T1027, 64);\n\t\t\t I_OPT_IBIAS_G[CURRENT_SITE_NUMBER()-1] = I_BIAS_G[CURRENT_SITE_NUMBER()-1][N_OPT_IBIAS_G[CURRENT_SITE_NUMBER()-1]];\n \t FuncPrint(\"N_OPT_IBIAS_G\", N_OPT_IBIAS_G[CURRENT_SITE_NUMBER()-1]);\n \t FuncPrint(\"I_OPT_IBIAS_G\", I_OPT_IBIAS_G[CURRENT_SITE_NUMBER()-1]);\n\n\t\t\t RES_PROG_I[CURRENT_SITE_NUMBER()-1] = N_OPT_IBIAS_G[CURRENT_SITE_NUMBER()-1] ;//<5:0> of ANA_TRM_RES_PROG1\n\t\t\t N_OPT_IBIAS_G_54[CURRENT_SITE_NUMBER()-1] = N_OPT_IBIAS_G[CURRENT_SITE_NUMBER()-1] >> 4;\n\t\t\t RES_PROG_I2[CURRENT_SITE_NUMBER()-1] = N_OPT_IBIAS_G_54[CURRENT_SITE_NUMBER()-1] << 6; //<7:6> of ANA_TRM_RES_PROG1\n\t\t\t RES_PROG_A[CURRENT_SITE_NUMBER()-1] = N_OPT_IBIAS_G[CURRENT_SITE_NUMBER()-1] << 10; //<15:10> of ANA_TRM_RES_PROG1\n\n\t\t\t FuncPrint(\"RES_PROG_I\", RES_PROG_I[CURRENT_SITE_NUMBER()-1]);\n\t\t\t FuncPrint(\"N_OPT_IBIAS_G_54\", N_OPT_IBIAS_G_54[CURRENT_SITE_NUMBER()-1]);\n\t\t\t FuncPrint(\"RES_PROG_I2\", RES_PROG_I2[CURRENT_SITE_NUMBER()-1]);\n\t\t\t FuncPrint(\"RES_PROG_A\", RES_PROG_A[CURRENT_SITE_NUMBER()-1]);\n\n\t\t\t RES_PROG_I_rtv[CURRENT_SITE_NUMBER()-1] = extend_Pmode_Herschel(RES_PROG_I[CURRENT_SITE_NUMBER()-1], 2);\n\t\t\t RES_PROG_I2_rtv[CURRENT_SITE_NUMBER()-1] = extend_Pmode_Herschel(RES_PROG_I2[CURRENT_SITE_NUMBER()-1], 2);\n\t\t\t RES_PROG_A_rtv[CURRENT_SITE_NUMBER()-1] = extend_Pmode_Herschel(RES_PROG_A[CURRENT_SITE_NUMBER()-1], 2);\n\n\t\t\t FuncPrint(\"RES_PROG_I_rtv\", RES_PROG_I_rtv[CURRENT_SITE_NUMBER()-1]);\n\t\t\t FuncPrint(\"RES_PROG_I2_rtv\", RES_PROG_I2_rtv[CURRENT_SITE_NUMBER()-1]);\n\t\t\t FuncPrint(\"RES_PROG_A_rtv\", RES_PROG_A_rtv[CURRENT_SITE_NUMBER()-1]);\n\n FOR_EACH_SITE_END();\n\n rdi.runTimeVal(\"RES_PROG_I_rtv\", RES_PROG_I_rtv);\n rdi.runTimeVal(\"RES_PROG_I2_rtv\", RES_PROG_I2_rtv);\n rdi.runTimeVal(\"RES_PROG_A_rtv\", RES_PROG_A_rtv);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T10_27_gyr_bias_current_trimming_V3_PAT_id1\");\n rdi.digCap(\"T10_27_gyr_bias_current_trimming_V3_Digcap_id\").vecVarOnly().pin(\"SDO\").capMode(TA::SER).samples(16*1).bitPerWord(16).execute();\n rdi.smartVec().label(s_splited_pat_name[1]).pin(\"SDX\").writeData(\"RES_PROG_I_rtv\", Wri_Bit_Length, Wri_Bit_Position).execute();\n rdi.smartVec().label(s_splited_pat_name[2]).pin(\"SDX\").writeData(\"RES_PROG_I2_rtv\", Wri_Bit_Length, Wri_Bit_Position).execute();\n rdi.smartVec().label(s_splited_pat_name[3]).pin(\"SDX\").writeData(\"RES_PROG_A_rtv\", Wri_Bit_Length, Wri_Bit_Position).execute();\n RDI_END();\n\n\n\n FOR_EACH_SITE_BEGIN();\n\t\t\t ARRAY_I Vec=rdi.id(\"T10_27_gyr_bias_current_trimming_V3_Digcap_id\").getVector();\n\t\t\t N_ANA_TRM_RES_PROG1_RD[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[0]);\n\n\t\t\t RES_PROG_I_RD[CURRENT_SITE_NUMBER()-1] = N_ANA_TRM_RES_PROG1_RD[CURRENT_SITE_NUMBER()-1] & 63;\n\t\t\t N_ANA_TRM_RES_PROG1_RD_7_6[CURRENT_SITE_NUMBER()-1] = N_ANA_TRM_RES_PROG1_RD[CURRENT_SITE_NUMBER()-1] & 192;\n\t\t\t RES_PROG_I2_RD[CURRENT_SITE_NUMBER()-1] = N_ANA_TRM_RES_PROG1_RD_7_6[CURRENT_SITE_NUMBER()-1] >> 6;\n\t\t\t N_ANA_TRM_RES_PROG1_RD_15_10[CURRENT_SITE_NUMBER()-1] = N_ANA_TRM_RES_PROG1_RD[CURRENT_SITE_NUMBER()-1] & 64512;\n\t\t\t RES_PROG_A_RD[CURRENT_SITE_NUMBER()-1] = N_ANA_TRM_RES_PROG1_RD_15_10[CURRENT_SITE_NUMBER()-1] >> 10;\n\n\t\t\t RES_PROG_FE[CURRENT_SITE_NUMBER()-1] = N_OPT_IBIAS_G[CURRENT_SITE_NUMBER()-1] ;\n\t\t\t RES_PROG_VCO[CURRENT_SITE_NUMBER()-1] = N_OPT_IBIAS_G[CURRENT_SITE_NUMBER()-1] << 8;\n\n\t\t\t FuncPrint(\"RES_PROG_I_RD\", RES_PROG_I_RD[CURRENT_SITE_NUMBER()-1]);\n\t\t\t FuncPrint(\"N_ANA_TRM_RES_PROG1_RD_7_6\", N_ANA_TRM_RES_PROG1_RD_7_6[CURRENT_SITE_NUMBER()-1]);\n\t\t\t FuncPrint(\"RES_PROG_I2_RD\", RES_PROG_I2_RD[CURRENT_SITE_NUMBER()-1]);\n\t\t\t FuncPrint(\"N_ANA_TRM_RES_PROG1_RD_15_10\", N_ANA_TRM_RES_PROG1_RD_15_10[CURRENT_SITE_NUMBER()-1]);\n\t\t\t FuncPrint(\"RES_PROG_A_RD\", RES_PROG_A_RD[CURRENT_SITE_NUMBER()-1]);\n\t\t\t FuncPrint(\"RES_PROG_FE\", RES_PROG_FE[CURRENT_SITE_NUMBER()-1]);\n\t\t\t FuncPrint(\"RES_PROG_VCO\", RES_PROG_VCO[CURRENT_SITE_NUMBER()-1]);\n\n\n\t\t\t RES_PROG_FE_rtv[CURRENT_SITE_NUMBER()-1] = extend_Pmode_Herschel(RES_PROG_FE[CURRENT_SITE_NUMBER()-1], 2);\n\t\t\t RES_PROG_VCO_rtv[CURRENT_SITE_NUMBER()-1] = extend_Pmode_Herschel(RES_PROG_VCO[CURRENT_SITE_NUMBER()-1], 2);\n\n\t\t\t FuncPrint(\"RES_PROG_FE_rtv\", RES_PROG_FE_rtv[CURRENT_SITE_NUMBER()-1]);\n\t\t\t FuncPrint(\"RES_PROG_VCO_rtv\", RES_PROG_VCO_rtv[CURRENT_SITE_NUMBER()-1]);\n FOR_EACH_SITE_END();\n\n rdi.runTimeVal(\"RES_PROG_FE_rtv\", RES_PROG_FE_rtv);\n rdi.runTimeVal(\"RES_PROG_VCO_rtv\", RES_PROG_VCO_rtv);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T10_27_gyr_bias_current_trimming_V3_PAT_id2\");\n rdi.digCap(\"T10_27_gyr_bias_current_trimming_V3_Digcap_id2\").vecVarOnly().pin(\"SDO\").capMode(TA::SER).samples(16*1).bitPerWord(16).execute();\n rdi.smartVec().label(s_splited_pat_name[4]).pin(\"SDX\").writeData(\"RES_PROG_FE_rtv\", Wri_Bit_Length, Wri_Bit_Position).execute();\n rdi.smartVec().label(s_splited_pat_name[5]).pin(\"SDX\").writeData(\"RES_PROG_VCO_rtv\", Wri_Bit_Length, Wri_Bit_Position).execute();\n RDI_END();\n\n FOR_EACH_SITE_BEGIN();\n\t\t\t ARRAY_I Vec=rdi.id(\"T10_27_gyr_bias_current_trimming_V3_Digcap_id2\").getVector();\n\t\t\t N_ANA_TRM_RES_PROG2_RD[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[0]);\n\t\t\t RES_PROG_FE_RD[CURRENT_SITE_NUMBER()-1] = N_ANA_TRM_RES_PROG2_RD[CURRENT_SITE_NUMBER()-1] & 63;\n\t\t\t RES_PROG_VCO_RD[CURRENT_SITE_NUMBER()-1] = N_ANA_TRM_RES_PROG2_RD[CURRENT_SITE_NUMBER()-1] & 16128;\n\t\t FOR_EACH_SITE_END();\n\n }\n ON_FIRST_INVOCATION_END();\n\n int Func_result0 = rdi.id(\"T10_27_gyr_bias_current_trimming_V3_PAT_id0\").getBurstPassFail();\n int Func_result1 = rdi.id(\"T10_27_gyr_bias_current_trimming_V3_PAT_id1\").getBurstPassFail();\n int Func_result2 = rdi.id(\"T10_27_gyr_bias_current_trimming_V3_PAT_id2\").getBurstPassFail();\n FuncPrint(\"Func_result0\", Func_result0);\n FuncPrint(\"Func_result1\", Func_result1);\n FuncPrint(\"Func_result2\", Func_result2);\n int Func_result = 1 * Func_result0 * Func_result1 * Func_result2;\n\n int RD_WR_compare = 1;\n if ((RES_PROG_I_RD[CURRENT_SITE_NUMBER()-1]) != N_OPT_IBIAS_G[CURRENT_SITE_NUMBER()-1])\t\tRD_WR_compare=0;\n if ((RES_PROG_I2_RD[CURRENT_SITE_NUMBER()-1]) != N_OPT_IBIAS_G_54[CURRENT_SITE_NUMBER()-1])\tRD_WR_compare=0;\n if ((RES_PROG_A_RD[CURRENT_SITE_NUMBER()-1]) != N_OPT_IBIAS_G[CURRENT_SITE_NUMBER()-1])\t\tRD_WR_compare=0;\n if ((RES_PROG_FE_RD[CURRENT_SITE_NUMBER()-1]) != RES_PROG_FE[CURRENT_SITE_NUMBER()-1])\t\tRD_WR_compare=0;\n if ((RES_PROG_VCO_RD[CURRENT_SITE_NUMBER()-1]) != RES_PROG_VCO[CURRENT_SITE_NUMBER()-1])\t\tRD_WR_compare=0;\n\n FuncPrint(\"RD_WR_compare\", RD_WR_compare);\n Func_result = Func_result * RD_WR_compare;\n FuncPrint(\"Func_result\", Func_result);\n\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n for (int i = 0; i<10; i++)\n {\n \t TestLog(\"I_BIAS_G_0\"+rdi.itos(i), I_BIAS_G[CURRENT_SITE_NUMBER()-1][i]);\n }\n for (int i = 10; i<64; i++)\n {\n \t TestLog(\"I_BIAS_G_\"+rdi.itos(i), I_BIAS_G[CURRENT_SITE_NUMBER()-1][i]);\n }\n TestLog(\"N_OPT_IBIAS_G\", N_OPT_IBIAS_G[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"I_OPT_IBIAS_G\", I_OPT_IBIAS_G[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"RES_PROG_I_RD\", RES_PROG_I_RD[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"RES_PROG_I2_RD\", RES_PROG_I2_RD[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"RES_PROG_A_RD\", RES_PROG_A_RD[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"RES_PROG_VCO_RD\", RES_PROG_VCO_RD[CURRENT_SITE_NUMBER()-1]>>8);\n TestLog(\"RES_PROG_FE_RD\", RES_PROG_FE_RD[CURRENT_SITE_NUMBER()-1]);\n // Auto_Code_Judge_and_log\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T10_27_gyr_bias_current_trimming_V3\", T10_27_gyr_bias_current_trimming_V3);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 2 $ $Author: laj1mu23 $ $Date: 2024/03/25 20:34:28 GMT $')\nwac('EXT_MODE', 0xc00f) # Switch to the TEST register page\nwac('TM_CONF', 0x0100) # tm_se_meas=1 tm_bus_inv=0 (COM_TIOP for BUF1_INP)\nwac('TM_PIN', 0x0009) # tm_int2_sel=4 (BUF1_INP) tm_int2_en=1\nwac('TM_ADDR', 0x010e) # tm_cfg=1 (COM_TB2= IB_ACC, COM_TB1= IB_GYR) tm_addr=e (tm_bus_sel=tm_addr(3:2)=3 (COM_TION/P) COM_TIO_REF;\n # enable the power_ana_test_multiplexor); any tm_addr value except off/0 enables the test module\ndly(100e-6)\ngac('I_BIAS_GYR_M', 'INT2', i_range=2e-6)\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T10_28_GYR_Bias_Current_Measurement_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n static double I_BIAS_GYR_M[xNSitES];\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T10_28_GYR_Bias_Current_Measurement_V2_PAT_id\");\n rdi.dc(\"T10_28_GYR_Bias_Current_Measurement_V2DC_id0\").label(s_label_name)\n// Alarm::vForce value had not been assigned in TOI, need manual check\n .insertSub(i_comment_line0[0]).pin(\"INT2\").vForce(0 V).iMeas().valueMode(TA::BADC).iRange(10e-06 A).average(16).measWait(0.1 ms) //I_BIAS_GYR_M\n .execute();\n RDI_END();\n\n ON_FIRST_INVOCATION_END();\n \n ARRAY_D JSUB_results_INT2;\n JSUB_results_INT2 = rdi.id(\"T10_28_GYR_Bias_Current_Measurement_V2DC_id0\").getMultiValue(\"INT2\");\n I_BIAS_GYR_M[CURRENT_SITE_NUMBER()-1] = JSUB_results_INT2[0];\n FuncPrint(\"I_BIAS_GYR_M\", I_BIAS_GYR_M[CURRENT_SITE_NUMBER()-1]);\n\n int Func_result = rdi.id(\"T10_28_GYR_Bias_Current_Measurement_V2_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"I_BIAS_GYR_M\", I_BIAS_GYR_M[CURRENT_SITE_NUMBER()-1]);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T10_28_GYR_Bias_Current_Measurement_V2\", T10_28_GYR_Bias_Current_Measurement_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: GYRA bias current characterization\n# Characterization loop derived from T10_27_gyr_bias_current_trimming\n# ib_gyr@ANAIO1\n#############################################################################################################\ncmt('Version info: $Revision: 4 $ $Author: luz3sgh $ $Date: 2024/07/02 01:48:53 GMT $')\nwac('EXT_MODE', 0xc00f) # Switch to the TEST register page\nwac('TM_CONF', 0x0100) # tm_se_meas=1 tm_bus_inv=0 (COM_TIOP for BUF1_INP)\nwac('TM_PIN', 0x0009) # tm_int2_sel=4 (BUF1_INP) tm_int2_en=1\nwac('TM_ADDR', 0x010e) # tm_cfg=1 (COM_TB2= IB_ACC, COM_TB1= IB_GYR) tm_addr=e (tm_bus_sel=tm_addr(3:2)=3 (COM_TION/P) COM_TIO_REF;\n # enable the power_ana_test_multiplexor); any tm_addr value except off/0 enables the test module\n# Characterization loop\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('OCP_MASK', 0x003f) # Set masking register\nras('REG_VALUE', 'ANA_TRM_RES_PROG1') # Store the current value\nfor n in range (0, 64, 1):\n cmt('Set trim index to value {} in range (0..63)'.format(n))\n wr('ANA_TRM_RES_PROG1', n) # <5:0> gyr_trm_res_prog_i\n rac('ANA_TRM_RES_PROG1', n, 0x003f)\n dly(271*74e-9)\n gac(f'I_BIAS_G_C[{n:02d}]', 'INT2', i_range=2e-6)\n log(f'I_BIAS_G_C[{n:02d}]')\ndly(148e-9)\nwri('ANA_TRM_RES_PROG1', 'REG_VALUE')\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n# Clean\nwac('EXT_MODE', 0xc00f) # Switch to the TEST register page\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\n", "output": "/*****************************************************\n * T10_29_GYR_Bias_Current_Char_V4, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n * JSH5SGH: fix some bugs.\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T10_29_GYR_Bias_Current_Char_V4: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 2;\n vector i_comment_line[i_split_count];\n\n static int i_REG_VALUE[xNSitES];\n ARRAY_I aI_Captured_0;\n static double d_I_BIAS_G_C[xNSitES][64];\n ARRAY_D ad_I_BIAS_G_C;\n\n static int i_WRITE_BACK[xNSitES];\n static int i_vec_Num1[32] = {0};\n static int i_funcRes0[xNSitES], i_funcRes1[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(i_REG_VALUE, 9, xNSitES);\n \n //!\"CTmsg: cut pattern to 2 parts @ oriAVCvecline [14205]\n //!\"CTmsg: cut pattern to 2 parts @ binarypatline [14195]\n if (i_split_pat_flag)\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n }\n else\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n for(int i=0; i }\n valid comment[ 1] @ avcline 1162: {ras('REG_VALUE', 'ANA_TRM_RES_PROG1')}\n valid comment[ 2] @ avcline 1275: {cmt: Set trim index to value 0 in range (0..63)}\n valid comment[ 3] @ avcline 1476: {gac('I_BIAS_G_C[00]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 3] @ avcline 1476: {log('I_BIAS_G_C[00]', '', '', 0, 0)}\n valid comment[ 4] @ avcline 1477: {cmt: Set trim index to value 1 in range (0..63)}\n valid comment[ 5] @ avcline 1678: {gac('I_BIAS_G_C[01]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 5] @ avcline 1678: {log('I_BIAS_G_C[01]', '', '', 0, 0)}\n valid comment[ 6] @ avcline 1679: {cmt: Set trim index to value 2 in range (0..63)}\n valid comment[ 7] @ avcline 1880: {gac('I_BIAS_G_C[02]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 7] @ avcline 1880: {log('I_BIAS_G_C[02]', '', '', 0, 0)}\n valid comment[ 8] @ avcline 1881: {cmt: Set trim index to value 3 in range (0..63)}\n valid comment[ 9] @ avcline 2082: {gac('I_BIAS_G_C[03]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 9] @ avcline 2082: {log('I_BIAS_G_C[03]', '', '', 0, 0)}\n valid comment[ 10] @ avcline 2083: {cmt: Set trim index to value 4 in range (0..63)}\n valid comment[ 11] @ avcline 2284: {gac('I_BIAS_G_C[04]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 11] @ avcline 2284: {log('I_BIAS_G_C[04]', '', '', 0, 0)}\n valid comment[ 12] @ avcline 2285: {cmt: Set trim index to value 5 in range (0..63)}\n valid comment[ 13] @ avcline 2486: {gac('I_BIAS_G_C[05]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 13] @ avcline 2486: {log('I_BIAS_G_C[05]', '', '', 0, 0)}\n valid comment[ 14] @ avcline 2487: {cmt: Set trim index to value 6 in range (0..63)}\n valid comment[ 15] @ avcline 2688: {gac('I_BIAS_G_C[06]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 15] @ avcline 2688: {log('I_BIAS_G_C[06]', '', '', 0, 0)}\n valid comment[ 16] @ avcline 2689: {cmt: Set trim index to value 7 in range (0..63)}\n valid comment[ 17] @ avcline 2890: {gac('I_BIAS_G_C[07]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 17] @ avcline 2890: {log('I_BIAS_G_C[07]', '', '', 0, 0)}\n valid comment[ 18] @ avcline 2891: {cmt: Set trim index to value 8 in range (0..63)}\n valid comment[ 19] @ avcline 3092: {gac('I_BIAS_G_C[08]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 19] @ avcline 3092: {log('I_BIAS_G_C[08]', '', '', 0, 0)}\n valid comment[ 20] @ avcline 3093: {cmt: Set trim index to value 9 in range (0..63)}\n valid comment[ 21] @ avcline 3294: {gac('I_BIAS_G_C[09]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 21] @ avcline 3294: {log('I_BIAS_G_C[09]', '', '', 0, 0)}\n valid comment[ 22] @ avcline 3295: {cmt: Set trim index to value 10 in range (0..63)}\n valid comment[ 23] @ avcline 3496: {gac('I_BIAS_G_C[10]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 23] @ avcline 3496: {log('I_BIAS_G_C[10]', '', '', 0, 0)}\n valid comment[ 24] @ avcline 3497: {cmt: Set trim index to value 11 in range (0..63)}\n valid comment[ 25] @ avcline 3698: {gac('I_BIAS_G_C[11]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 25] @ avcline 3698: {log('I_BIAS_G_C[11]', '', '', 0, 0)}\n valid comment[ 26] @ avcline 3699: {cmt: Set trim index to value 12 in range (0..63)}\n valid comment[ 27] @ avcline 3900: {gac('I_BIAS_G_C[12]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 27] @ avcline 3900: {log('I_BIAS_G_C[12]', '', '', 0, 0)}\n valid comment[ 28] @ avcline 3901: {cmt: Set trim index to value 13 in range (0..63)}\n valid comment[ 29] @ avcline 4102: {gac('I_BIAS_G_C[13]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 29] @ avcline 4102: {log('I_BIAS_G_C[13]', '', '', 0, 0)}\n valid comment[ 30] @ avcline 4103: {cmt: Set trim index to value 14 in range (0..63)}\n valid comment[ 31] @ avcline 4304: {gac('I_BIAS_G_C[14]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 31] @ avcline 4304: {log('I_BIAS_G_C[14]', '', '', 0, 0)}\n valid comment[ 32] @ avcline 4305: {cmt: Set trim index to value 15 in range (0..63)}\n valid comment[ 33] @ avcline 4506: {gac('I_BIAS_G_C[15]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 33] @ avcline 4506: {log('I_BIAS_G_C[15]', '', '', 0, 0)}\n valid comment[ 34] @ avcline 4507: {cmt: Set trim index to value 16 in range (0..63)}\n valid comment[ 35] @ avcline 4708: {gac('I_BIAS_G_C[16]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 35] @ avcline 4708: {log('I_BIAS_G_C[16]', '', '', 0, 0)}\n valid comment[ 36] @ avcline 4709: {cmt: Set trim index to value 17 in range (0..63)}\n valid comment[ 37] @ avcline 4910: {gac('I_BIAS_G_C[17]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 37] @ avcline 4910: {log('I_BIAS_G_C[17]', '', '', 0, 0)}\n valid comment[ 38] @ avcline 4911: {cmt: Set trim index to value 18 in range (0..63)}\n valid comment[ 39] @ avcline 5112: {gac('I_BIAS_G_C[18]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 39] @ avcline 5112: {log('I_BIAS_G_C[18]', '', '', 0, 0)}\n valid comment[ 40] @ avcline 5113: {cmt: Set trim index to value 19 in range (0..63)}\n valid comment[ 41] @ avcline 5314: {gac('I_BIAS_G_C[19]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 41] @ avcline 5314: {log('I_BIAS_G_C[19]', '', '', 0, 0)}\n valid comment[ 42] @ avcline 5315: {cmt: Set trim index to value 20 in range (0..63)}\n valid comment[ 43] @ avcline 5516: {gac('I_BIAS_G_C[20]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 43] @ avcline 5516: {log('I_BIAS_G_C[20]', '', '', 0, 0)}\n valid comment[ 44] @ avcline 5517: {cmt: Set trim index to value 21 in range (0..63)}\n valid comment[ 45] @ avcline 5718: {gac('I_BIAS_G_C[21]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 45] @ avcline 5718: {log('I_BIAS_G_C[21]', '', '', 0, 0)}\n valid comment[ 46] @ avcline 5719: {cmt: Set trim index to value 22 in range (0..63)}\n valid comment[ 47] @ avcline 5920: {gac('I_BIAS_G_C[22]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 47] @ avcline 5920: {log('I_BIAS_G_C[22]', '', '', 0, 0)}\n valid comment[ 48] @ avcline 5921: {cmt: Set trim index to value 23 in range (0..63)}\n valid comment[ 49] @ avcline 6122: {gac('I_BIAS_G_C[23]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 49] @ avcline 6122: {log('I_BIAS_G_C[23]', '', '', 0, 0)}\n valid comment[ 50] @ avcline 6123: {cmt: Set trim index to value 24 in range (0..63)}\n valid comment[ 51] @ avcline 6324: {gac('I_BIAS_G_C[24]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 51] @ avcline 6324: {log('I_BIAS_G_C[24]', '', '', 0, 0)}\n valid comment[ 52] @ avcline 6325: {cmt: Set trim index to value 25 in range (0..63)}\n valid comment[ 53] @ avcline 6526: {gac('I_BIAS_G_C[25]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 53] @ avcline 6526: {log('I_BIAS_G_C[25]', '', '', 0, 0)}\n valid comment[ 54] @ avcline 6527: {cmt: Set trim index to value 26 in range (0..63)}\n valid comment[ 55] @ avcline 6728: {gac('I_BIAS_G_C[26]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 55] @ avcline 6728: {log('I_BIAS_G_C[26]', '', '', 0, 0)}\n valid comment[ 56] @ avcline 6729: {cmt: Set trim index to value 27 in range (0..63)}\n valid comment[ 57] @ avcline 6930: {gac('I_BIAS_G_C[27]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 57] @ avcline 6930: {log('I_BIAS_G_C[27]', '', '', 0, 0)}\n valid comment[ 58] @ avcline 6931: {cmt: Set trim index to value 28 in range (0..63)}\n valid comment[ 59] @ avcline 7132: {gac('I_BIAS_G_C[28]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 59] @ avcline 7132: {log('I_BIAS_G_C[28]', '', '', 0, 0)}\n valid comment[ 60] @ avcline 7133: {cmt: Set trim index to value 29 in range (0..63)}\n valid comment[ 61] @ avcline 7334: {gac('I_BIAS_G_C[29]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 61] @ avcline 7334: {log('I_BIAS_G_C[29]', '', '', 0, 0)}\n valid comment[ 62] @ avcline 7335: {cmt: Set trim index to value 30 in range (0..63)}\n valid comment[ 63] @ avcline 7536: {gac('I_BIAS_G_C[30]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 63] @ avcline 7536: {log('I_BIAS_G_C[30]', '', '', 0, 0)}\n valid comment[ 64] @ avcline 7537: {cmt: Set trim index to value 31 in range (0..63)}\n valid comment[ 65] @ avcline 7738: {gac('I_BIAS_G_C[31]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 65] @ avcline 7738: {log('I_BIAS_G_C[31]', '', '', 0, 0)}\n valid comment[ 66] @ avcline 7739: {cmt: Set trim index to value 32 in range (0..63)}\n valid comment[ 67] @ avcline 7940: {gac('I_BIAS_G_C[32]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 67] @ avcline 7940: {log('I_BIAS_G_C[32]', '', '', 0, 0)}\n valid comment[ 68] @ avcline 7941: {cmt: Set trim index to value 33 in range (0..63)}\n valid comment[ 69] @ avcline 8142: {gac('I_BIAS_G_C[33]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 69] @ avcline 8142: {log('I_BIAS_G_C[33]', '', '', 0, 0)}\n valid comment[ 70] @ avcline 8143: {cmt: Set trim index to value 34 in range (0..63)}\n valid comment[ 71] @ avcline 8344: {gac('I_BIAS_G_C[34]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 71] @ avcline 8344: {log('I_BIAS_G_C[34]', '', '', 0, 0)}\n valid comment[ 72] @ avcline 8345: {cmt: Set trim index to value 35 in range (0..63)}\n valid comment[ 73] @ avcline 8546: {gac('I_BIAS_G_C[35]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 73] @ avcline 8546: {log('I_BIAS_G_C[35]', '', '', 0, 0)}\n valid comment[ 74] @ avcline 8547: {cmt: Set trim index to value 36 in range (0..63)}\n valid comment[ 75] @ avcline 8748: {gac('I_BIAS_G_C[36]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 75] @ avcline 8748: {log('I_BIAS_G_C[36]', '', '', 0, 0)}\n valid comment[ 76] @ avcline 8749: {cmt: Set trim index to value 37 in range (0..63)}\n valid comment[ 77] @ avcline 8950: {gac('I_BIAS_G_C[37]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 77] @ avcline 8950: {log('I_BIAS_G_C[37]', '', '', 0, 0)}\n valid comment[ 78] @ avcline 8951: {cmt: Set trim index to value 38 in range (0..63)}\n valid comment[ 79] @ avcline 9152: {gac('I_BIAS_G_C[38]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 79] @ avcline 9152: {log('I_BIAS_G_C[38]', '', '', 0, 0)}\n valid comment[ 80] @ avcline 9153: {cmt: Set trim index to value 39 in range (0..63)}\n valid comment[ 81] @ avcline 9354: {gac('I_BIAS_G_C[39]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 81] @ avcline 9354: {log('I_BIAS_G_C[39]', '', '', 0, 0)}\n valid comment[ 82] @ avcline 9355: {cmt: Set trim index to value 40 in range (0..63)}\n valid comment[ 83] @ avcline 9556: {gac('I_BIAS_G_C[40]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 83] @ avcline 9556: {log('I_BIAS_G_C[40]', '', '', 0, 0)}\n valid comment[ 84] @ avcline 9557: {cmt: Set trim index to value 41 in range (0..63)}\n valid comment[ 85] @ avcline 9758: {gac('I_BIAS_G_C[41]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 85] @ avcline 9758: {log('I_BIAS_G_C[41]', '', '', 0, 0)}\n valid comment[ 86] @ avcline 9759: {cmt: Set trim index to value 42 in range (0..63)}\n valid comment[ 87] @ avcline 9960: {gac('I_BIAS_G_C[42]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 87] @ avcline 9960: {log('I_BIAS_G_C[42]', '', '', 0, 0)}\n valid comment[ 88] @ avcline 9961: {cmt: Set trim index to value 43 in range (0..63)}\n valid comment[ 89] @ avcline 10162: {gac('I_BIAS_G_C[43]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 89] @ avcline 10162: {log('I_BIAS_G_C[43]', '', '', 0, 0)}\n valid comment[ 90] @ avcline 10163: {cmt: Set trim index to value 44 in range (0..63)}\n valid comment[ 91] @ avcline 10364: {gac('I_BIAS_G_C[44]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 91] @ avcline 10364: {log('I_BIAS_G_C[44]', '', '', 0, 0)}\n valid comment[ 92] @ avcline 10365: {cmt: Set trim index to value 45 in range (0..63)}\n valid comment[ 93] @ avcline 10566: {gac('I_BIAS_G_C[45]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 93] @ avcline 10566: {log('I_BIAS_G_C[45]', '', '', 0, 0)}\n valid comment[ 94] @ avcline 10567: {cmt: Set trim index to value 46 in range (0..63)}\n valid comment[ 95] @ avcline 10768: {gac('I_BIAS_G_C[46]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 95] @ avcline 10768: {log('I_BIAS_G_C[46]', '', '', 0, 0)}\n valid comment[ 96] @ avcline 10769: {cmt: Set trim index to value 47 in range (0..63)}\n valid comment[ 97] @ avcline 10970: {gac('I_BIAS_G_C[47]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 97] @ avcline 10970: {log('I_BIAS_G_C[47]', '', '', 0, 0)}\n valid comment[ 98] @ avcline 10971: {cmt: Set trim index to value 48 in range (0..63)}\n valid comment[ 99] @ avcline 11172: {gac('I_BIAS_G_C[48]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 99] @ avcline 11172: {log('I_BIAS_G_C[48]', '', '', 0, 0)}\n valid comment[100] @ avcline 11173: {cmt: Set trim index to value 49 in range (0..63)}\n valid comment[101] @ avcline 11374: {gac('I_BIAS_G_C[49]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[101] @ avcline 11374: {log('I_BIAS_G_C[49]', '', '', 0, 0)}\n valid comment[102] @ avcline 11375: {cmt: Set trim index to value 50 in range (0..63)}\n valid comment[103] @ avcline 11576: {gac('I_BIAS_G_C[50]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[103] @ avcline 11576: {log('I_BIAS_G_C[50]', '', '', 0, 0)}\n valid comment[104] @ avcline 11577: {cmt: Set trim index to value 51 in range (0..63)}\n valid comment[105] @ avcline 11778: {gac('I_BIAS_G_C[51]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[105] @ avcline 11778: {log('I_BIAS_G_C[51]', '', '', 0, 0)}\n valid comment[106] @ avcline 11779: {cmt: Set trim index to value 52 in range (0..63)}\n valid comment[107] @ avcline 11980: {gac('I_BIAS_G_C[52]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[107] @ avcline 11980: {log('I_BIAS_G_C[52]', '', '', 0, 0)}\n valid comment[108] @ avcline 11981: {cmt: Set trim index to value 53 in range (0..63)}\n valid comment[109] @ avcline 12182: {gac('I_BIAS_G_C[53]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[109] @ avcline 12182: {log('I_BIAS_G_C[53]', '', '', 0, 0)}\n valid comment[110] @ avcline 12183: {cmt: Set trim index to value 54 in range (0..63)}\n valid comment[111] @ avcline 12384: {gac('I_BIAS_G_C[54]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[111] @ avcline 12384: {log('I_BIAS_G_C[54]', '', '', 0, 0)}\n valid comment[112] @ avcline 12385: {cmt: Set trim index to value 55 in range (0..63)}\n valid comment[113] @ avcline 12586: {gac('I_BIAS_G_C[55]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[113] @ avcline 12586: {log('I_BIAS_G_C[55]', '', '', 0, 0)}\n valid comment[114] @ avcline 12587: {cmt: Set trim index to value 56 in range (0..63)}\n valid comment[115] @ avcline 12788: {gac('I_BIAS_G_C[56]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[115] @ avcline 12788: {log('I_BIAS_G_C[56]', '', '', 0, 0)}\n valid comment[116] @ avcline 12789: {cmt: Set trim index to value 57 in range (0..63)}\n valid comment[117] @ avcline 12990: {gac('I_BIAS_G_C[57]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[117] @ avcline 12990: {log('I_BIAS_G_C[57]', '', '', 0, 0)}\n valid comment[118] @ avcline 12991: {cmt: Set trim index to value 58 in range (0..63)}\n valid comment[119] @ avcline 13192: {gac('I_BIAS_G_C[58]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[119] @ avcline 13192: {log('I_BIAS_G_C[58]', '', '', 0, 0)}\n valid comment[120] @ avcline 13193: {cmt: Set trim index to value 59 in range (0..63)}\n valid comment[121] @ avcline 13394: {gac('I_BIAS_G_C[59]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[121] @ avcline 13394: {log('I_BIAS_G_C[59]', '', '', 0, 0)}\n valid comment[122] @ avcline 13395: {cmt: Set trim index to value 60 in range (0..63)}\n valid comment[123] @ avcline 13596: {gac('I_BIAS_G_C[60]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[123] @ avcline 13596: {log('I_BIAS_G_C[60]', '', '', 0, 0)}\n valid comment[124] @ avcline 13597: {cmt: Set trim index to value 61 in range (0..63)}\n valid comment[125] @ avcline 13798: {gac('I_BIAS_G_C[61]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[125] @ avcline 13798: {log('I_BIAS_G_C[61]', '', '', 0, 0)}\n valid comment[126] @ avcline 13799: {cmt: Set trim index to value 62 in range (0..63)}\n valid comment[127] @ avcline 14000: {gac('I_BIAS_G_C[62]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[127] @ avcline 14000: {log('I_BIAS_G_C[62]', '', '', 0, 0)}\n valid comment[128] @ avcline 14001: {cmt: Set trim index to value 63 in range (0..63)}\n valid comment[129] @ avcline 14202: {gac('I_BIAS_G_C[63]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[129] @ avcline 14202: {log('I_BIAS_G_C[63]', '', '', 0, 0)}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.digCap(\"digcapid_0\").vecVarOnly().pin(\"SDO\").capMode(TA::SER).bitPerWord(16).samples(1*16).execute();\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][3]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[00]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][5]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[01]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][7]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[02]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][9]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[03]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][11]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[04]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][13]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[05]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][15]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[06]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][17]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[07]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][19]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[08]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][21]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[09]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][23]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[10]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][25]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[11]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][27]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[12]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][29]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[13]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][31]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[14]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][33]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[15]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][35]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[16]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][37]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[17]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][39]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[18]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][41]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[19]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][43]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[20]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][45]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[21]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][47]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[22]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][49]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[23]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][51]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[24]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][53]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[25]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][55]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[26]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][57]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[27]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][59]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[28]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][61]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[29]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][63]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[30]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][65]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[31]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][67]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[32]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][69]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[33]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][71]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[34]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][73]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[35]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][75]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[36]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][77]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[37]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][79]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[38]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][81]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[39]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][83]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[40]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][85]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[41]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][87]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[42]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][89]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[43]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][91]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[44]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][93]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[45]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][95]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[46]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][97]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[47]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][99]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[48]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][101]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[49]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][103]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[50]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][105]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[51]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][107]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[52]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][109]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[53]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][111]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[54]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][113]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[55]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][115]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[56]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][117]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[57]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][119]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[58]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][121]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[59]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][123]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[60]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][125]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[61]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][127]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[62]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][129]).pin(\"INT2\").iMeas().iRange(10 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_G_C[63]', 'INT2', 2e-06, 0.0001, True)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n aI_Captured_0 = rdi.id(\"digcapid_0\").getVector(\"SDO\");\n ARRAY_D ad_jsubresults_INT2; ad_jsubresults_INT2.resize(64); ad_jsubresults_INT2.init(-9.9);\n ad_jsubresults_INT2 = rdi.id(\"dcid_0\").getMultiValue(\"INT2\");\n \n aI_Captured_0[0] = Switch_High_Low_Bits_16Bits(aI_Captured_0[0]);\n i_REG_VALUE[curSite] = aI_Captured_0[0];\n FuncPrint(\"REG_VALUE\",i_REG_VALUE[curSite]);\n for(int i=0; i<64; i++){\n d_I_BIAS_G_C[curSite][i] = ad_jsubresults_INT2[0 + i];\n FuncPrint(\"I_BIAS_G_C_\" + rdi.itos(curSite) + \"_\"+ rdi.itos(i) ,d_I_BIAS_G_C[curSite][i]);\n }\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n\n /* Ori key coments in subpat1 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 14205: {wri('ANA_TRM_RES_PROG1', 'REG_VALUE')}\n valid comment[ 1] @ avcline 15244: {Test End: T10_29_GYR_Bias_Current_Char}\n */\n static int i_vec_iposition1[32] = {\n 31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,\n 48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63\n };\n for (int i = 0; i < 32; i++)\n {\n i_vec_Num1[i] = i_vec_iposition1[i];\n }\n FOR_EACH_SITE_BEGIN();\n i_WRITE_BACK[curSite] = Switch_High_Low_Bits_16Bits(i_REG_VALUE[curSite]);\n Func_Vector_Dynamic_Write(s_splited_pat_name[1], \"SDX\", i_vec_Num1, 32, i_WRITE_BACK[curSite], 0, 2); //Notes. TEI check per project\n\n FOR_EACH_SITE_END();\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id1\");\n rdi.func().label(s_splited_pat_name[1]).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes1[curSite] = rdi.id(\"burst_id1\").getBurstPassFail();\n FOR_EACH_SITE_END();\n\n\n }\n\n ON_FIRST_INVOCATION_END();\n\n for(int i=0; i < 64; i++){ \n TestLog(s_Func_Test_Name_Add_2Num(\"I_BIAS_G_C_\", i), d_I_BIAS_G_C[curSite][i]);\n\t }\n i_funcRes[curSite] = i_funcRes0[curSite] && i_funcRes1[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T10_29_GYR_Bias_Current_Char_V4\", T10_29_GYR_Bias_Current_Char_V4);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 2 $ $Author: laj1mu23 $ $Date: 2024/03/25 20:34:28 GMT $')\nwac('EXT_MODE', 0xc00f) # Switch to the TEST register page\nwac('TM_CONF', 0x0101) # tm_se_meas=1 (BUFF2_INP= VSS) tm_bus_inv=0 tm_buf_pwrup=1 (tbuf_tb1_on)\n # single ended meas. because the power_ana_test_multiplexor_2 provides VDD_FOSC/VDD_BGP\nwac('TM_PIN', 0x0095) # tm_asdx_sel=4 (BUF2_INP) tm_asdx_en=1 tm_int2_sel=2 (BUF1_OUT) tm_int2_en=1\nwac('TM_ADDR', 0x0f0d) # tm_cfg=f (COM_TB2= VDD_BGP, COM_TB1= VDD_FOSC) tm_addr=d (COM_TIO_PWR;\n # enable the power_ana_test_multiplexor_2 for power supplies; tm_bus_sel=tm_addr(3:2)=3 (BUFF1/2_INP= COM_TIOP/N due to tm_bus_inv=0) );\n\t\t\t\t\t # any tm_addr value except off/0 enables the test module\ndly(100e-6)\ngav('V_VDD_FOSC_M_RAW', 'INT2', 'ASDX') # no check (V_OFF1_ECOFF)\ncalc('V_VDD_FOSC', 'V_VDD_FOSC_M_RAW', '-', 'V_OFF1_ECOFF')\nlog('V_VDD_FOSC')\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T10_30_VDD_FOSC_measurement_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n static double V_VDD_FOSC_M_RAW[xNSitES], V_VDD_FOSC[xNSitES];\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T10_30_VDD_FOSC_measurement_V2_PAT_id\");\n rdi.dc(\"T10_30_VDD_FOSC_measurement_V2DC_id0\").label(s_label_name)\n .insertSub(i_comment_line0[0]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms) //V_VDD_FOSC_M_RAW\n .execute();\n rdi.hwRelay().pin(\"INT2,ASDX\").setOff(\"ALL\").execute();\n RDI_END();\n ON_FIRST_INVOCATION_END();\n\n ARRAY_D JSUB_results_ASDX;\n JSUB_results_ASDX = rdi.id(\"T10_30_VDD_FOSC_measurement_V2DC_id0\").getMultiValue(\"ASDX\");\n ARRAY_D JSUB_results_INT2;\n JSUB_results_INT2 = rdi.id(\"T10_30_VDD_FOSC_measurement_V2DC_id0\").getMultiValue(\"INT2\");\n\n V_VDD_FOSC_M_RAW[CURRENT_SITE_NUMBER()-1] = JSUB_results_INT2[0] - JSUB_results_ASDX[0];\n V_VDD_FOSC[CURRENT_SITE_NUMBER()-1] = V_VDD_FOSC_M_RAW[CURRENT_SITE_NUMBER()-1] - V_OFF1_ECOFF[CURRENT_SITE_NUMBER()-1];\n\n FuncPrint(\"JSUB_results_ASDX\", JSUB_results_ASDX[0]);\n FuncPrint(\"JSUB_results_INT2\", JSUB_results_INT2[0]);\n FuncPrint(\"V_VDD_FOSC_M_RAW\", V_VDD_FOSC_M_RAW[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"V_VDD_FOSC\", V_VDD_FOSC[CURRENT_SITE_NUMBER()-1]);\n \n int Func_result = rdi.id(\"T10_30_VDD_FOSC_measurement_V2_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"V_VDD_FOSC\", V_VDD_FOSC[CURRENT_SITE_NUMBER()-1]);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T10_30_VDD_FOSC_measurement_V2\", T10_30_VDD_FOSC_measurement_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 2 $ $Author: laj1mu23 $ $Date: 2024/03/25 20:34:28 GMT $')\nwac('EXT_MODE', 0xc00f) # Switch to the TEST register page\nwac('TM_CONF', 0x0111) # tm_se_meas=1 (BUFF2_INP= VSS) tm_bus_inv=1 tm_buf_pwrup=1 (tbuf_tb1_on)\n # single ended meas. because the power_ana_test_multiplexor_2 provides VDD_FOSC/VDD_BGP\nwac('TM_PIN', 0x0095) # tm_asdx_sel=4 (BUF2_INP) tm_asdx_en=1 tm_int2_sel=2 (BUF1_OUT) tm_int2_en=1\nwac('TM_ADDR', 0x0f0d) # tm_cfg=f (COM_TB2= VDD_BGP, COM_TB1= VDD_FOSC) tm_addr=d (COM_TIO_PWR;\n # enable the power_ana_test_multiplexor_2 for power supplies; tm_bus_sel=tm_addr(3:2)=3 (BUFF1/2_INP= COM_TIOP/N due to tm_bus_inv=0) );\ndly(100e-6)\ngav('V_VDD_BGP_M_RAW', 'INT2', 'ASDX')\ncalc('V_VDD_BGP', 'V_VDD_BGP_M_RAW', '-', 'V_OFF1_ECOFF')\nlog('V_VDD_BGP')\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs and reset test configuration\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T10_31_VDD_BGP_measurement_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n static double V_VDD_BGP_M_RAW[xNSitES], V_VDD_BGP[xNSitES];\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T10_31_VDD_BGP_measurement_V2_PAT_id\");\n rdi.dc(\"T10_31_VDD_BGP_measurement_V2DC_id0\").label(s_label_name)\n .insertSub(i_comment_line0[0]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms) //V_VDD_BGP_M_RAW\n .execute();\n RDI_END();\n\n ON_FIRST_INVOCATION_END();\n\t\t ARRAY_D JSUB_results_ASDX;\n\t\t JSUB_results_ASDX = rdi.id(\"T10_31_VDD_BGP_measurement_V2DC_id0\").getMultiValue(\"ASDX\");\n\t\t ARRAY_D JSUB_results_INT2;\n\t\t JSUB_results_INT2 = rdi.id(\"T10_31_VDD_BGP_measurement_V2DC_id0\").getMultiValue(\"INT2\");\n\t\t V_VDD_BGP_M_RAW[CURRENT_SITE_NUMBER()-1] = JSUB_results_INT2[0] - JSUB_results_ASDX[0];\n V_VDD_BGP[CURRENT_SITE_NUMBER()-1] = V_VDD_BGP_M_RAW[CURRENT_SITE_NUMBER()-1] - V_OFF1_ECOFF[CURRENT_SITE_NUMBER()-1];\n\n \t\t FuncPrint(\"JSUB_results_ASDX\", JSUB_results_ASDX[0]);\n \t\t FuncPrint(\"JSUB_results_INT2\", JSUB_results_INT2[0]);\n \t\t FuncPrint(\"V_VDD_BGP_M_RAW\", V_VDD_BGP_M_RAW[CURRENT_SITE_NUMBER()-1]);\n \t\t FuncPrint(\"V_VDD_BGP\", V_VDD_BGP[CURRENT_SITE_NUMBER()-1]);\n \n int Func_result = rdi.id(\"T10_31_VDD_BGP_measurement_V2_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"V_VDD_BGP\", V_VDD_BGP[CURRENT_SITE_NUMBER()-1]);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T10_31_VDD_BGP_measurement_V2\", T10_31_VDD_BGP_measurement_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 2 $ $Author: laj1mu23 $ $Date: 2024/03/25 20:34:28 GMT $')\nwac('EXT_MODE', 0xc005) # Switch to the FIFO register page\nwac('OCP_MASK', 0x0102) # activate bit 8 (fifo_acc_en) and bit 1 (fifo_en)\nwac('FIFO_CONF', 0x0102) # fifo_acc_en=1 fifo_en=1 (new with CA version, see ASICAP-4450)\nwr('OCP_MASK', 0x0000) # reset OCP mask\nrac('OCP_MASK', 0xffff) # Check masking register reset\n\nwac('EXT_MODE', 0xc00f) # Switch to the TEST register page\nwac('TM_CONF', 0x0001) # tm_se_meas=0 tm_bus_inv=0 tm_buf_pwrup=1 (tbuf_tb1_on)\nwac('TM_PIN', 0x0095) # tm_asdx_sel=4 (BUF2_INP) tm_asdx_en=1 tm_int2_sel=2 (BUF1_OUT) tm_int2_en=1\nwac('TM_ADDR', 0x050d) # tm_cfg= 5 (COM_TB2= VSS, COM_TB1= VDDD_RAM; CFG[3]=0) tm_addr=d (COM_TIO_PWR;\n # enable the power_ana_test_multiplexor_2 for power supplies; tm_bus_sel=tm_addr(3:2)=3 (BUFF1/2_INP= COM_TIOP/N due to tm_bus_inv=0) );\n\t\t\t\t\t # any tm_addr value except off/0 enables the test module\ndly(100e-6)\ngav('V_VDDD_RAM_M_RAW', 'INT2', 'ASDX') # no check ()\ncalc('V_VDDD_RAM', 'V_VDDD_RAM_M_RAW', '-', 'V_OFF1_ECOFF')\nlog('V_VDDD_RAM')\n\nwac('EXT_MODE', 0xc00f) # Switch to the TEST register page\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\n\nwac('EXT_MODE', 0xc005) # Switch to the FIFO register page\nwac('OCP_MASK', 0x0102) # activate bit 8 (fifo_acc_en) and bit 1 (fifo_en)\nwac('FIFO_CONF', 0x0000) # reset value\nwr('OCP_MASK', 0x0000) # reset OCP mask\nrac('OCP_MASK', 0xffff) # Check masking register reset\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T10_33_VDDD_RAM_measurement_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n static double V_VDDD_RAM_M_RAW[xNSitES], V_VDDD_RAM[xNSitES];\n // Auto_Code_Variable_define\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T10_33_VDDD_RAM_measurement_V2_PAT_id\");\n rdi.dc(\"T10_33_VDDD_RAM_measurement_V2DC_id0\").label(s_label_name)\n .insertSub(i_comment_line0[0]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms) //V_VDDD_RAM_M_RAW\n .execute();\n RDI_END();\n\n // Auto_Code_Execution_Part\n\n\n\n ON_FIRST_INVOCATION_END();\n ARRAY_D JSUB_results_ASDX;\n JSUB_results_ASDX = rdi.id(\"T10_33_VDDD_RAM_measurement_V2DC_id0\").getMultiValue(\"ASDX\");\n ARRAY_D JSUB_results_INT2;\n JSUB_results_INT2 = rdi.id(\"T10_33_VDDD_RAM_measurement_V2DC_id0\").getMultiValue(\"INT2\");\n V_VDDD_RAM_M_RAW[CURRENT_SITE_NUMBER()-1] = JSUB_results_INT2[0] - JSUB_results_ASDX[0];\n\n V_VDDD_RAM[CURRENT_SITE_NUMBER()-1] = V_VDDD_RAM_M_RAW[CURRENT_SITE_NUMBER()-1] - V_OFF1_ECOFF[CURRENT_SITE_NUMBER()-1];\n\n \t\t FuncPrint(\"JSUB_results_ASDX\", JSUB_results_ASDX[0]);\n \t\t FuncPrint(\"JSUB_results_INT2\", JSUB_results_INT2[0]);\n \t\t FuncPrint(\"V_VDDD_RAM_M_RAW\", V_VDDD_RAM_M_RAW[CURRENT_SITE_NUMBER()-1]);\n \t\t FuncPrint(\"V_VDDD_RAM\", V_VDDD_RAM[CURRENT_SITE_NUMBER()-1]);\n // Auto_Code_Retrieve_Data\n \n int Func_result = rdi.id(\"T10_33_VDDD_RAM_measurement_V2_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"V_VDDD_RAM\", V_VDDD_RAM[CURRENT_SITE_NUMBER()-1]);\n // Auto_Code_Judge_and_log\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T10_33_VDDD_RAM_measurement_V2\", T10_33_VDDD_RAM_measurement_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 2 $ $Author: laj1mu23 $ $Date: 2024/03/25 20:34:28 GMT $')\nwac('EXT_MODE', 0xc006) # Switch to FCU register page\nwcb('temp_mode', 0x1) # Keep temp always on\nwcb('temp_test_odr', 0x4) # Set temp test ODR to 800\nwr('FCU_TEST_CMD', 0x8000) # Trigger temp datapath reset\n # values of T01_10_SET_DEVICE_CONFIG_STC_ACC\nwac('EXT_MODE', 0xc00f) # Switch to the TEST register page\nwac('TM_CONF', 0x0011) # tm_se_meas=0 tm_bus_inv=1 tm_buf_pwrup=1 (tbuf_tb1_on)\n # bus_inv required the power_ana_test_multiplexor_2 provides VSS_G/VDDT\nwac('TM_PIN', 0x0095) # tm_asdx_sel=4 (BUF2_INP) tm_asdx_en=1 tm_int2_sel=2 (BUF1_OUT) tm_int2_en=1\nwac('TM_ADDR', 0x0a0d) # tm_cfg=a (COM_TB2= VDDT, COM_TB1= VSS_G) tm_addr=d (COM_TIO_PWR;\n # enable the power_ana_test_multiplexor_2 for power supplies; tm_bus_sel=tm_addr(3:2)=3 (BUFF1/2_INP= COM_TION/P due to tm_bus_inv=1) );\ndly(100e-6)\ngav('V_VDDT_M_RAW', 'INT2', 'ASDX') # no check ()\ncalc('V_VDDT', 'V_VDDT_M_RAW', '-', 'V_OFF1_ECOFF')\nlog('V_VDDT')\n\nwac('EXT_MODE', 0xc00f) # Switch to the TEST register page\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T10_34_VDDT_LDO_measurement_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n static double V_VDDT_M_RAW[xNSitES], V_VDDT[xNSitES];\n // Auto_Code_Variable_define\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T10_34_VDDT_LDO_measurement_V2_PAT_id\");\n rdi.dc(\"T10_34_VDDT_LDO_measurement_V2DC_id0\").label(s_label_name)\n .insertSub(i_comment_line0[0]).pin(\"INT2,ASDX\",TA::BADC).vMeas().average(128).measWait(1 ms) //V_VDDT_M_RAW\n .execute();\n RDI_END();\n\n // Auto_Code_Execution_Part\n\n\n\n ON_FIRST_INVOCATION_END();\n ARRAY_D JSUB_results_ASDX;\n JSUB_results_ASDX = rdi.id(\"T10_34_VDDT_LDO_measurement_V2DC_id0\").getMultiValue(\"ASDX\");\n ARRAY_D JSUB_results_INT2;\n JSUB_results_INT2 = rdi.id(\"T10_34_VDDT_LDO_measurement_V2DC_id0\").getMultiValue(\"INT2\");\n V_VDDT_M_RAW[CURRENT_SITE_NUMBER()-1] = JSUB_results_INT2[0] - JSUB_results_ASDX[0];\n\n V_VDDT[CURRENT_SITE_NUMBER()-1] = V_VDDT_M_RAW[CURRENT_SITE_NUMBER()-1] - V_OFF1_ECOFF[CURRENT_SITE_NUMBER()-1];\n\n FuncPrint(\"JSUB_results_INT2\", JSUB_results_INT2[0]);\n FuncPrint(\"JSUB_results_ASDX\", JSUB_results_ASDX[0]);\n FuncPrint(\"V_VDDT_M_RAW\", V_VDDT_M_RAW[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"V_VDDT\", V_VDDT[CURRENT_SITE_NUMBER()-1]);\n // Auto_Code_Retrieve_Data\n \n int Func_result = rdi.id(\"T10_34_VDDT_LDO_measurement_V2_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"V_VDDT\", V_VDDT[CURRENT_SITE_NUMBER()-1]);\n // Auto_Code_Judge_and_log\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T10_34_VDDT_LDO_measurement_V2\", T10_34_VDDT_LDO_measurement_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: Bandgap temperature coefficient characterization\n# Characterization loop derived from T10_16_acc_bias_current_trimming\n# The ACC BIAS current is routed to the pin INT2.\n# For all the 16 values of pc_trm_bgp_tc the current values are logged to I_BIAS_ACC_TC[00] .. I_BIAS_ACC_TC[15].\n# The DMS model doesn't show any change for these different pc_trm_bgp_tc values.\n# In vbgp_acc_top (wreal) the input BGP_TRM_C (which is pc_trm_bgp_tc) affects only the voltage references\n# VREF_AA/_FA/_LA/_S, but not output currents IB_xx.\n#\n# The limit for all the values I_BIAS_ACC_TC[] is set to 0.8 .. 1.1e-6 (around the target 0.9e-6, see T10_16).\n#\n# After the characterization loop the register ANA_TRM_BG is set to the previous value,\n# and the test module / IO registers TM_CONF, TM_PIN, TM_ADDR, IO_TEST_IF are set to their reset values.\n#############################################################################################################\ncmt('Version info: $Revision: 3 $ $Author: luz3sgh $ $Date: 2024/07/02 01:51:04 GMT $')\nwac('EXT_MODE', 0xc00f) # Switch to the TEST register page\nwac('TM_CONF', 0x0110) # tm_se_meas=1 tm_bus_inv=1 (COM_TION instead of COM_TIOP for BUF1_INP)\nwac('TM_PIN', 0x0009) # tm_int2_sel=4 (BUF1_INP) tm_int2_en=1\nwac('TM_ADDR', 0x010e) # tm_cfg=1 (COM_TB2= IB_ACC, COM_TB1= IB_GYR) tm_addr=e (tm_bus_sel=tm_addr(3:2)=3 (COM_TION/P) COM_TIO_REF;\n # enable the power_ana_test_multiplexor); any tm_addr value except off/0 enables the test module\n# Characterization loop\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('OCP_MASK', 0x000f) # ANA_TRM_BG<3:0> pc_trm_bgp_tc\nras('REG_VALUE', 'ANA_TRM_BG') # Store the current value\nfor n in range (0, 16, 1):\n cmt('Set trim index to value {} in range (0..15)'.format(n))\n wr('ANA_TRM_BG', n) # ANA_TRM_BG<3:0> pc_trm_bgp_tc\n rac('ANA_TRM_BG',n, 0x000f)\n dly(20e-6)\n gac(f'I_BIAS_ACC_TC[{n:02d}]', 'INT2', i_range=2e-6)\n log(f'I_BIAS_ACC_TC[{n:02d}]')\ndly(592e-9)\nwri('ANA_TRM_BG','REG_VALUE')\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n# Clean\nwac('EXT_MODE', 0xc00f) # Switch to the TEST register page\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\n", "output": "/*****************************************************\n * T10_36_ACC_Bias_TC_Char_V3, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n * JSH5SGH: fix some bugs.\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T10_36_ACC_Bias_TC_Char_V3: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n\nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 2;\n vector i_comment_line[i_split_count];\n\n static int i_REG_VALUE[xNSitES];\n ARRAY_I aI_Captured_0;\n static double d_I_BIAS_ACC_TC[xNSitES][16];\n ARRAY_D ad_I_BIAS_ACC_TC;\n\n static int i_WRITE_BACK[xNSitES];\n static int i_vec_Num1[32] = {0};\n static int i_funcRes0[xNSitES], i_funcRes1[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(i_REG_VALUE, 9, xNSitES);\n \n //!\"CTmsg: cut pattern to 2 parts @ oriAVCvecline [4515]\n //!\"CTmsg: cut pattern to 2 parts @ binarypatline [4505]\n if (i_split_pat_flag)\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n }\n else\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n for(int i=0; i }\n valid comment[ 1] @ avcline 1162: {ras('REG_VALUE', 'ANA_TRM_BG')}\n valid comment[ 2] @ avcline 1275: {cmt: Set trim index to value 0 in range (0..15)}\n valid comment[ 3] @ avcline 1476: {gac('I_BIAS_ACC_TC[00]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 3] @ avcline 1476: {log('I_BIAS_ACC_TC[00]', '', '', 0, 0)}\n valid comment[ 4] @ avcline 1477: {cmt: Set trim index to value 1 in range (0..15)}\n valid comment[ 5] @ avcline 1678: {gac('I_BIAS_ACC_TC[01]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 5] @ avcline 1678: {log('I_BIAS_ACC_TC[01]', '', '', 0, 0)}\n valid comment[ 6] @ avcline 1679: {cmt: Set trim index to value 2 in range (0..15)}\n valid comment[ 7] @ avcline 1880: {gac('I_BIAS_ACC_TC[02]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 7] @ avcline 1880: {log('I_BIAS_ACC_TC[02]', '', '', 0, 0)}\n valid comment[ 8] @ avcline 1881: {cmt: Set trim index to value 3 in range (0..15)}\n valid comment[ 9] @ avcline 2082: {gac('I_BIAS_ACC_TC[03]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 9] @ avcline 2082: {log('I_BIAS_ACC_TC[03]', '', '', 0, 0)}\n valid comment[ 10] @ avcline 2083: {cmt: Set trim index to value 4 in range (0..15)}\n valid comment[ 11] @ avcline 2284: {gac('I_BIAS_ACC_TC[04]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 11] @ avcline 2284: {log('I_BIAS_ACC_TC[04]', '', '', 0, 0)}\n valid comment[ 12] @ avcline 2285: {cmt: Set trim index to value 5 in range (0..15)}\n valid comment[ 13] @ avcline 2486: {gac('I_BIAS_ACC_TC[05]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 13] @ avcline 2486: {log('I_BIAS_ACC_TC[05]', '', '', 0, 0)}\n valid comment[ 14] @ avcline 2487: {cmt: Set trim index to value 6 in range (0..15)}\n valid comment[ 15] @ avcline 2688: {gac('I_BIAS_ACC_TC[06]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 15] @ avcline 2688: {log('I_BIAS_ACC_TC[06]', '', '', 0, 0)}\n valid comment[ 16] @ avcline 2689: {cmt: Set trim index to value 7 in range (0..15)}\n valid comment[ 17] @ avcline 2890: {gac('I_BIAS_ACC_TC[07]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 17] @ avcline 2890: {log('I_BIAS_ACC_TC[07]', '', '', 0, 0)}\n valid comment[ 18] @ avcline 2891: {cmt: Set trim index to value 8 in range (0..15)}\n valid comment[ 19] @ avcline 3092: {gac('I_BIAS_ACC_TC[08]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 19] @ avcline 3092: {log('I_BIAS_ACC_TC[08]', '', '', 0, 0)}\n valid comment[ 20] @ avcline 3093: {cmt: Set trim index to value 9 in range (0..15)}\n valid comment[ 21] @ avcline 3294: {gac('I_BIAS_ACC_TC[09]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 21] @ avcline 3294: {log('I_BIAS_ACC_TC[09]', '', '', 0, 0)}\n valid comment[ 22] @ avcline 3295: {cmt: Set trim index to value 10 in range (0..15)}\n valid comment[ 23] @ avcline 3496: {gac('I_BIAS_ACC_TC[10]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 23] @ avcline 3496: {log('I_BIAS_ACC_TC[10]', '', '', 0, 0)}\n valid comment[ 24] @ avcline 3497: {cmt: Set trim index to value 11 in range (0..15)}\n valid comment[ 25] @ avcline 3698: {gac('I_BIAS_ACC_TC[11]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 25] @ avcline 3698: {log('I_BIAS_ACC_TC[11]', '', '', 0, 0)}\n valid comment[ 26] @ avcline 3699: {cmt: Set trim index to value 12 in range (0..15)}\n valid comment[ 27] @ avcline 3900: {gac('I_BIAS_ACC_TC[12]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 27] @ avcline 3900: {log('I_BIAS_ACC_TC[12]', '', '', 0, 0)}\n valid comment[ 28] @ avcline 3901: {cmt: Set trim index to value 13 in range (0..15)}\n valid comment[ 29] @ avcline 4102: {gac('I_BIAS_ACC_TC[13]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 29] @ avcline 4102: {log('I_BIAS_ACC_TC[13]', '', '', 0, 0)}\n valid comment[ 30] @ avcline 4103: {cmt: Set trim index to value 14 in range (0..15)}\n valid comment[ 31] @ avcline 4304: {gac('I_BIAS_ACC_TC[14]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 31] @ avcline 4304: {log('I_BIAS_ACC_TC[14]', '', '', 0, 0)}\n valid comment[ 32] @ avcline 4305: {cmt: Set trim index to value 15 in range (0..15)}\n valid comment[ 33] @ avcline 4506: {gac('I_BIAS_ACC_TC[15]', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 33] @ avcline 4506: {log('I_BIAS_ACC_TC[15]', '', '', 0, 0)}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.digCap(\"digcapid_0\").vecVarOnly().pin(\"SDO\").capMode(TA::SER).bitPerWord(16).samples(1*16).execute();\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][3]).pin(\"INT2\").iMeas().iRange(2 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_ACC_TC[00]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][5]).pin(\"INT2\").iMeas().iRange(2 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_ACC_TC[01]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][7]).pin(\"INT2\").iMeas().iRange(2 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_ACC_TC[02]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][9]).pin(\"INT2\").iMeas().iRange(2 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_ACC_TC[03]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][11]).pin(\"INT2\").iMeas().iRange(2 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_ACC_TC[04]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][13]).pin(\"INT2\").iMeas().iRange(2 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_ACC_TC[05]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][15]).pin(\"INT2\").iMeas().iRange(2 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_ACC_TC[06]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][17]).pin(\"INT2\").iMeas().iRange(2 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_ACC_TC[07]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][19]).pin(\"INT2\").iMeas().iRange(2 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_ACC_TC[08]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][21]).pin(\"INT2\").iMeas().iRange(2 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_ACC_TC[09]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][23]).pin(\"INT2\").iMeas().iRange(2 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_ACC_TC[10]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][25]).pin(\"INT2\").iMeas().iRange(2 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_ACC_TC[11]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][27]).pin(\"INT2\").iMeas().iRange(2 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_ACC_TC[12]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][29]).pin(\"INT2\").iMeas().iRange(2 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_ACC_TC[13]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][31]).pin(\"INT2\").iMeas().iRange(2 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_ACC_TC[14]', 'INT2', 2e-06, 0.0001, True)}\n .insertSub(i_comment_line[0][33]).pin(\"INT2\").iMeas().iRange(2 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_BIAS_ACC_TC[15]', 'INT2', 2e-06, 0.0001, True)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n aI_Captured_0 = rdi.id(\"digcapid_0\").getVector(\"SDO\");\n ARRAY_D ad_jsubresults_INT2; ad_jsubresults_INT2.resize(16); ad_jsubresults_INT2.init(-9.9);\n ad_jsubresults_INT2 = rdi.id(\"dcid_0\").getMultiValue(\"INT2\");\n \n aI_Captured_0[0] = Switch_High_Low_Bits_16Bits(aI_Captured_0[0]);\n i_REG_VALUE[curSite] = aI_Captured_0[0];\n FuncPrint(\"REG_VALUE\",i_REG_VALUE[curSite]);\n for(int i=0; i<16; i++){\n d_I_BIAS_ACC_TC[curSite][i] = ad_jsubresults_INT2[0 + i];\n FuncPrint(\"I_BIAS_ACC_TC_\" + rdi.itos(curSite) + \"_\"+ rdi.itos(i) ,d_I_BIAS_ACC_TC[curSite][i]);\n }\n FOR_EACH_SITE_END();\n\n\n /* Ori key coments in subpat1 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 4515: {wri('ANA_TRM_BG', 'REG_VALUE')}\n valid comment[ 1] @ avcline 5554: {Test End: T10_36_ACC_Bias_TC_Char}\n */\n static int i_vec_iposition1[32] = {\n 31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,\n 48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63\n };\n for (int i = 0; i < 32; i++)\n {\n i_vec_Num1[i] = i_vec_iposition1[i];\n }\n FOR_EACH_SITE_BEGIN();\n i_WRITE_BACK[curSite] = Switch_High_Low_Bits_16Bits(i_REG_VALUE[curSite]);\n Func_Vector_Dynamic_Write(s_splited_pat_name[1], \"SDX\", i_vec_Num1, 32, i_WRITE_BACK[curSite], 0, 2); //Notes. TEI check per project\n\n FOR_EACH_SITE_END();\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id1\");\n rdi.func().label(s_splited_pat_name[1]).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes1[curSite] = rdi.id(\"burst_id1\").getBurstPassFail();\n FOR_EACH_SITE_END();\n\n\n }\n\n ON_FIRST_INVOCATION_END();\n\n for(int i=0; i < 16; i++){ \n TestLog(s_Func_Test_Name_Add_2Num(\"I_BIAS_ACC_TC_\", i), d_I_BIAS_ACC_TC[curSite][i]);\n }\n i_funcRes[curSite] = i_funcRes0[curSite] && i_funcRes1[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T10_36_ACC_Bias_TC_Char_V3\", T10_36_ACC_Bias_TC_Char_V3);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: FOSC trimming\n# Info : osc frequency changes monotonically with pc_trm_ftc= 0 ... 5\n# Steps: 1. Route fosc to INT1 pad\n# 2. Loop over trim steps and store the frequency values\n#############################################################################################################\ncmt('Version info: $Revision: bai430aa_rel/1 $ $Author: hmf1rt $ $Date: 2024/07/18 13:26:36 GMT $')\nscmd('set_tb_global VDDmin_scale(0.8);') # extend model check min/max range for Trim-sweep\nscmd('set_tb_global VDDmax_scale(1.6);') # extend model check min/max range for Trim-sweep\nwr('EXT_MODE', 0xc00f) # Switch to TEST page\nwac('DTB1',0x004c) # Route fosc_clk to INT1\nwr('EXT_MODE', 0xc00d) # Switch to ANA page\nwac('OCP_MASK', 0x0e00) # ANA_TRM_PMU<14:12> pc_trm_ftc\nras('REG_VALUE', 'ANA_TRM_PMU') # Store the current value\nfor n in range (0, 6, 1): # in design FTC trim is clipped at 5\n cmt('Set trim index to value {} in range (0..5)'.format(n))\n wr('ANA_TRM_PMU', n*2**9) # ANA_TRM_PMU<3:0> pc_trm_ftc\n rac('ANA_TRM_PMU',n*2**9, 0x0e00)\n dly(10e-6)\n gaf('F_FOSC_FTC[{:03d}]'.format(n), 'INT1')\n log('F_FOSC_FTC[{:03d}]'.format(n))\ndly(592e-9)\nwri('ANA_TRM_PMU','REG_VALUE')\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n# Clean\nwr('EXT_MODE', 0xc00f) # Switch to TEST page\nwac('DTB1',0x0000) # reset value\nscmd('set_tb_global VDDmin_scale(1.0);') # reset model check min/max range \nscmd('set_tb_global VDDmax_scale(1.0);') # reset model check min/max range \n", "output": "/*****************************************************\n * T10_38_FOSC_FTC_Char_R1, description file version Notfound, avc file version Notfound\n * First Editor : jsh5sgh\n * Code generated with autocoding tool V2.9.1, in TOI2 standard way by module write_standard\n * Change History:\n * JSH5SGH V4: correct wrong comment.\n * JSH5SGH R1: version update.\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\n\n\n\nclass T10_38_FOSC_FTC_Char_R1: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n double SAMPLE_PERIOD_US;\nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 3;\n vector i_comment_line[i_split_count];\n\n ARRAY_I aI_Captured_0;\n static double d_F_FOSC_FTC[xNSitES][6];\n static int i_REG_VALUE[xNSitES];\n static int i_WRITE_BACK[xNSitES];\n static int i_vec_Num2[32] = {0};\n static int i_funcRes0[xNSitES], i_funcRes1[xNSitES], i_funcRes2[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n \n //!\"CTmsg: cut pattern to 3 parts @ oriAVCvecline [867, 1891]\n //!\"CTmsg: cut pattern to 3 parts @ binarypatline [857, 1881]\n if (i_split_pat_flag)\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n }\n else\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n for(int i=0; i }\n valid comment[ 1] @ avcline 552: {ras('REG_VALUE', 'ANA_TRM_PMU')}\n valid comment[ 2] @ avcline 665: {cmt: Set trim index to value 0 in range (0..7)}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.digCap(\"digcapid_0\").label(s_splited_pat_name[0]).pin(\"SDO\").capMode(TA::SER).bitPerWord(16).samples(1*16).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n aI_Captured_0 = rdi.id(\"digcapid_0\").getVector(\"SDO\");\n aI_Captured_0[0] = Switch_High_Low_Bits_16Bits(aI_Captured_0[0]);\n i_REG_VALUE[curSite] = aI_Captured_0[0];\n FuncPrint(\"REG_VALUE\",i_REG_VALUE[curSite]);\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n\n /* Ori key coments in subpat1 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 867: {gaf('F_FOSC_FTC[000]', 'INT1', 2e+07, True)}\n valid comment[ 0] @ avcline 867: {log('F_FOSC_FTC[000]', '', '', 0, 0)}\n valid comment[ 1] @ avcline 868: {cmt: Set trim index to value 1 in range (0..7)}\n valid comment[ 2] @ avcline 1070: {gaf('F_FOSC_FTC[001]', 'INT1', 2e+07, True)}\n valid comment[ 2] @ avcline 1070: {log('F_FOSC_FTC[001]', '', '', 0, 0)}\n valid comment[ 3] @ avcline 1071: {cmt: Set trim index to value 2 in range (0..7)}\n valid comment[ 4] @ avcline 1273: {gaf('F_FOSC_FTC[002]', 'INT1', 2e+07, True)}\n valid comment[ 4] @ avcline 1273: {log('F_FOSC_FTC[002]', '', '', 0, 0)}\n valid comment[ 5] @ avcline 1274: {cmt: Set trim index to value 3 in range (0..7)}\n valid comment[ 6] @ avcline 1476: {gaf('F_FOSC_FTC[003]', 'INT1', 2e+07, True)}\n valid comment[ 6] @ avcline 1476: {log('F_FOSC_FTC[003]', '', '', 0, 0)}\n valid comment[ 7] @ avcline 1477: {cmt: Set trim index to value 4 in range (0..7)}\n valid comment[ 8] @ avcline 1679: {gaf('F_FOSC_FTC[004]', 'INT1', 2e+07, True)}\n valid comment[ 8] @ avcline 1679: {log('F_FOSC_FTC[004]', '', '', 0, 0)}\n valid comment[ 9] @ avcline 1680: {cmt: Set trim index to value 5 in range (0..7)}\n valid comment[ 10] @ avcline 1882: {gaf('F_FOSC_FTC[005]', 'INT1', 2e+07, True)}\n valid comment[ 10] @ avcline 1882: {log('F_FOSC_FTC[005]', '', '', 0, 0)}\n */\n Primary.timing(SPECIFICATION(\"SPI_STD_INT1_FREQ_MEAS\"));\n FLUSH(TM::APRM);\n SAMPLE_PERIOD_US = Primary.getSpecification().getSpecValue(\"per_ns@INT1_Port\") * 1e-03;\n FuncPrint(\"SAMPLE_PERIOD_US\", SAMPLE_PERIOD_US);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id1\");\n\t\t\t for(int i=0; i<5; i++)\n\t\t\t {\n\t\t\t\t rdi.port(\"INT1_Port\").digCap(\"vv_meas_code_\"+rdi.itos(i)).pin(\"INT1\").capMode(TA::SER).samples(4096).bitPerWord(1).execute();\n\t\t\t\t rdi.portSync();\n\t\t\t\t rdi.port(\"Non_INT1_Port\").func().label(s_splited_pat_name[1]).startVec(i_comment_line[1][2*i]).stopVec(i_comment_line[1][2*i+2]-1).execute();\n\t\t\t\t rdi.portSync();\n\t\t\t }\n\t\t\t rdi.port(\"INT1_Port\").digCap(\"vv_meas_code_\"+rdi.itos(5)).pin(\"INT1\").capMode(TA::SER).samples(4096).bitPerWord(1).execute();\n\t\t\t rdi.portSync();\n\t\t\t rdi.port(\"Non_INT1_Port\").func().label(s_splited_pat_name[1]).startVec(i_comment_line[1][10]).execute();\n\t\t\t rdi.portSync();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes1[curSite] = rdi.id(\"burst_id1\").getBurstPassFail();\n\t\t\t ARRAY_I ai_meas_code;\n\t\t\t for(int i=0; i<6; i++){\n\t\t\t\t ai_meas_code = rdi.id(\"vv_meas_code_\" + rdi.itos(i)).getVector();\n\t\t\t\t d_F_FOSC_FTC[curSite][i] = d_Func_Calculate_Freq_ByFFT(ai_meas_code, SAMPLE_PERIOD_US) *1e6;\n\t\t\t\t FuncPrint(s_Func_Test_Name_Add_3Num(\"d_F_FOSC_FTC_\", i), d_F_FOSC_FTC[curSite][i]);\n\t\t\t }\n\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n Primary.timing(TIMING_SPEC(1,1));\n Primary.timing(1);\n FLUSH(TM::APRM);\n\n /* Ori key coments in subpat2 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 1891: {wri('ANA_TRM_PMU', 'REG_VALUE')}\n valid comment[ 1] @ avcline 2433: {Test End: T10_38_FOSC_FTC_Char}\n */\n\n static int i_vec_iposition2[32] = {\n 31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,\n 48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63\n };\n for (int i = 0; i < 32; i++)\n {\n i_vec_Num2[i] = i_vec_iposition2[i];\n }\n FOR_EACH_SITE_BEGIN();\n i_WRITE_BACK[curSite] = Switch_High_Low_Bits_16Bits(i_REG_VALUE[curSite]);\n Func_Vector_Dynamic_Write(s_splited_pat_name[2], \"SDX\", i_vec_Num2, 32, i_WRITE_BACK[curSite], 0, 2); //Notes. TEI check per project\n\n FOR_EACH_SITE_END();\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id2\");\n rdi.func().label(s_splited_pat_name[2]).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes2[curSite] = rdi.id(\"burst_id2\").getBurstPassFail();\n\n FOR_EACH_SITE_END();\n\n\n }\n\n ON_FIRST_INVOCATION_END();\n\t for(int i=0; i<6; i++){\n\t\t TestLog(s_Func_Test_Name_Add_3Num(\"F_FOSC_FTC_\", i), d_F_FOSC_FTC[curSite][i]);\n\t }\n i_funcRes[curSite] = i_funcRes0[curSite] && i_funcRes1[curSite] && i_funcRes2[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T10_38_FOSC_FTC_Char_R1\", T10_38_FOSC_FTC_Char_R1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: Bandgap temperature coefficient characterization\n# Characterization loop derived from T10_11_acc_bandgap_trimming\n# - VSS_A to ANAIO2, VREF_AA to ANAIO1 with buffer 1 enabled only\n# For all the 16 values of pc_trm_bgp_tc the current values are logged to V_VBG_ACC_TC[00] .. V_VBG_ACC_TC[15].\n# In vbgp_acc_top (wreal) the input BGP_TRM_C (which is pc_trm_bgp_tc) affects the voltage references\n# VREF_AA/_FA/_LA/_S.\n#\n# The limit for all the values V_VBG_ACC_TC[] is set to 0.73 .. 0.77 (around the target 0.75, see T10_11).\n#\n# After the characterization loop the register ANA_TRM_BG is set to the previous value,\n# and the test module / IO registers TM_CONF, TM_PIN, TM_ADDR, IO_TEST_IF are set to their reset values.\n#############################################################################################################\nfrom test_sub_functions import *\ncmt('Version info: $Revision: 2 $ $Author: laj1mu23 $ $Date: 2024/03/25 20:34:28 GMT $')\nwac('EXT_MODE', 0xc00f) # Switch to the TEST register page\nwac('TM_CONF', 0x0011) # tm_se_meas=0 tm_bus_inv=1 tm_buf_pwrup=1 (tbuf_tb1_on)\n # bus_inv. because the power_ana_test_multiplexor_refs provides VSS_A/VREF_AA\nwac('TM_PIN', 0x0095) # tm_asdx_sel=4 (BUF2_INP) tm_asdx_en=1 tm_int2_sel=2 (BUF1_OUT) tm_int2_en=1\nwac('TM_ADDR', 0x060e) # tm_cfg=6 (COM_TB2= VREF_AA, COM_TB1= VSS_A) tm_addr=e (tm_bus_sel=tm_addr(3:2)=3 (COM_TION/P) COM_TIO_REF;\n # enable the power_ana_test_multiplexor); any tm_addr value except off/0 enables the test module\n# Characterization loop\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('OCP_MASK', 0x000f) # ANA_TRM_BG<3:0> pc_trm_bgp_tc\nras('REG_VALUE', 'ANA_TRM_BG') # Store the current value\nfor n in range (0, 16, 1):\n cmt('Set trim index to value {} in range (0..15)'.format(n))\n wr('ANA_TRM_BG', n) # ANA_TRM_BG<3:0> pc_trm_bgp_tc\n rac('ANA_TRM_BG', n, 0x000f)\n dly(100e-6)\n gav('V_VBG_ACC_TC_RAW[{:02d}]'.format(n), 'INT2', 'ASDX') \n calc('V_VBG_ACC_TC[{:02d}]'.format(n), 'V_VBG_ACC_TC_RAW[{:02d}]'.format(n), '-', 'V_OFF1_ECOFF')\n log(f'V_VBG_ACC_TC[{n:02}]')\ndly(592e-9)\nwri('ANA_TRM_BG','REG_VALUE')\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n# Clean\nwac('EXT_MODE', 0xc00f) # Switch to the TEST register page\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\n", "output": "/*****************************************************\n * T10_39_ACC_Bandgap_TC_Char_V2, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n * JSH5SGH: fix some bugs.\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T10_39_ACC_Bandgap_TC_Char_V2: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 2;\n vector i_comment_line[i_split_count];\n\n static int i_REG_VALUE[xNSitES];\n ARRAY_I aI_Captured_0;\n static double d_V_VBG_ACC_TC_RAW[xNSitES][16];\n static double V_VBG_ACC_TC[xNSitES][16];\n ARRAY_D ad_V_VBG_ACC_TC_RAW;\n\n static int i_WRITE_BACK[xNSitES];\n static int i_vec_Num1[32] = {0};\n static int i_funcRes0[xNSitES], i_funcRes1[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(i_REG_VALUE, 9, xNSitES);\n \n //!\"CTmsg: cut pattern to 2 parts @ oriAVCvecline [4531]\n //!\"CTmsg: cut pattern to 2 parts @ binarypatline [4521]\n if (i_split_pat_flag)\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n }\n else\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n for(int i=0; i }\n valid comment[ 1] @ avcline 1162: {ras('REG_VALUE', 'ANA_TRM_BG')}\n valid comment[ 2] @ avcline 1275: {cmt: Set trim index to value 0 in range (0..15)}\n valid comment[ 3] @ avcline 1477: {gav('V_VBG_ACC_TC_RAW[00]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 3] @ avcline 1477: {calc('V_VBG_ACC_TC[00]', 'V_VBG_ACC_TC_RAW[00]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 3] @ avcline 1477: {log('V_VBG_ACC_TC[00]', '', '', 0, 0)}\n valid comment[ 4] @ avcline 1478: {cmt: Set trim index to value 1 in range (0..15)}\n valid comment[ 5] @ avcline 1680: {gav('V_VBG_ACC_TC_RAW[01]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 5] @ avcline 1680: {calc('V_VBG_ACC_TC[01]', 'V_VBG_ACC_TC_RAW[01]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 5] @ avcline 1680: {log('V_VBG_ACC_TC[01]', '', '', 0, 0)}\n valid comment[ 6] @ avcline 1681: {cmt: Set trim index to value 2 in range (0..15)}\n valid comment[ 7] @ avcline 1883: {gav('V_VBG_ACC_TC_RAW[02]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 7] @ avcline 1883: {calc('V_VBG_ACC_TC[02]', 'V_VBG_ACC_TC_RAW[02]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 7] @ avcline 1883: {log('V_VBG_ACC_TC[02]', '', '', 0, 0)}\n valid comment[ 8] @ avcline 1884: {cmt: Set trim index to value 3 in range (0..15)}\n valid comment[ 9] @ avcline 2086: {gav('V_VBG_ACC_TC_RAW[03]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 9] @ avcline 2086: {calc('V_VBG_ACC_TC[03]', 'V_VBG_ACC_TC_RAW[03]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 9] @ avcline 2086: {log('V_VBG_ACC_TC[03]', '', '', 0, 0)}\n valid comment[ 10] @ avcline 2087: {cmt: Set trim index to value 4 in range (0..15)}\n valid comment[ 11] @ avcline 2289: {gav('V_VBG_ACC_TC_RAW[04]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 11] @ avcline 2289: {calc('V_VBG_ACC_TC[04]', 'V_VBG_ACC_TC_RAW[04]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 11] @ avcline 2289: {log('V_VBG_ACC_TC[04]', '', '', 0, 0)}\n valid comment[ 12] @ avcline 2290: {cmt: Set trim index to value 5 in range (0..15)}\n valid comment[ 13] @ avcline 2492: {gav('V_VBG_ACC_TC_RAW[05]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 13] @ avcline 2492: {calc('V_VBG_ACC_TC[05]', 'V_VBG_ACC_TC_RAW[05]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 13] @ avcline 2492: {log('V_VBG_ACC_TC[05]', '', '', 0, 0)}\n valid comment[ 14] @ avcline 2493: {cmt: Set trim index to value 6 in range (0..15)}\n valid comment[ 15] @ avcline 2695: {gav('V_VBG_ACC_TC_RAW[06]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 15] @ avcline 2695: {calc('V_VBG_ACC_TC[06]', 'V_VBG_ACC_TC_RAW[06]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 15] @ avcline 2695: {log('V_VBG_ACC_TC[06]', '', '', 0, 0)}\n valid comment[ 16] @ avcline 2696: {cmt: Set trim index to value 7 in range (0..15)}\n valid comment[ 17] @ avcline 2898: {gav('V_VBG_ACC_TC_RAW[07]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 17] @ avcline 2898: {calc('V_VBG_ACC_TC[07]', 'V_VBG_ACC_TC_RAW[07]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 17] @ avcline 2898: {log('V_VBG_ACC_TC[07]', '', '', 0, 0)}\n valid comment[ 18] @ avcline 2899: {cmt: Set trim index to value 8 in range (0..15)}\n valid comment[ 19] @ avcline 3101: {gav('V_VBG_ACC_TC_RAW[08]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 19] @ avcline 3101: {calc('V_VBG_ACC_TC[08]', 'V_VBG_ACC_TC_RAW[08]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 19] @ avcline 3101: {log('V_VBG_ACC_TC[08]', '', '', 0, 0)}\n valid comment[ 20] @ avcline 3102: {cmt: Set trim index to value 9 in range (0..15)}\n valid comment[ 21] @ avcline 3304: {gav('V_VBG_ACC_TC_RAW[09]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 21] @ avcline 3304: {calc('V_VBG_ACC_TC[09]', 'V_VBG_ACC_TC_RAW[09]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 21] @ avcline 3304: {log('V_VBG_ACC_TC[09]', '', '', 0, 0)}\n valid comment[ 22] @ avcline 3305: {cmt: Set trim index to value 10 in range (0..15)}\n valid comment[ 23] @ avcline 3507: {gav('V_VBG_ACC_TC_RAW[10]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 23] @ avcline 3507: {calc('V_VBG_ACC_TC[10]', 'V_VBG_ACC_TC_RAW[10]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 23] @ avcline 3507: {log('V_VBG_ACC_TC[10]', '', '', 0, 0)}\n valid comment[ 24] @ avcline 3508: {cmt: Set trim index to value 11 in range (0..15)}\n valid comment[ 25] @ avcline 3710: {gav('V_VBG_ACC_TC_RAW[11]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 25] @ avcline 3710: {calc('V_VBG_ACC_TC[11]', 'V_VBG_ACC_TC_RAW[11]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 25] @ avcline 3710: {log('V_VBG_ACC_TC[11]', '', '', 0, 0)}\n valid comment[ 26] @ avcline 3711: {cmt: Set trim index to value 12 in range (0..15)}\n valid comment[ 27] @ avcline 3913: {gav('V_VBG_ACC_TC_RAW[12]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 27] @ avcline 3913: {calc('V_VBG_ACC_TC[12]', 'V_VBG_ACC_TC_RAW[12]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 27] @ avcline 3913: {log('V_VBG_ACC_TC[12]', '', '', 0, 0)}\n valid comment[ 28] @ avcline 3914: {cmt: Set trim index to value 13 in range (0..15)}\n valid comment[ 29] @ avcline 4116: {gav('V_VBG_ACC_TC_RAW[13]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 29] @ avcline 4116: {calc('V_VBG_ACC_TC[13]', 'V_VBG_ACC_TC_RAW[13]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 29] @ avcline 4116: {log('V_VBG_ACC_TC[13]', '', '', 0, 0)}\n valid comment[ 30] @ avcline 4117: {cmt: Set trim index to value 14 in range (0..15)}\n valid comment[ 31] @ avcline 4319: {gav('V_VBG_ACC_TC_RAW[14]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 31] @ avcline 4319: {calc('V_VBG_ACC_TC[14]', 'V_VBG_ACC_TC_RAW[14]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 31] @ avcline 4319: {log('V_VBG_ACC_TC[14]', '', '', 0, 0)}\n valid comment[ 32] @ avcline 4320: {cmt: Set trim index to value 15 in range (0..15)}\n valid comment[ 33] @ avcline 4522: {gav('V_VBG_ACC_TC_RAW[15]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 33] @ avcline 4522: {calc('V_VBG_ACC_TC[15]', 'V_VBG_ACC_TC_RAW[15]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 33] @ avcline 4522: {log('V_VBG_ACC_TC[15]', '', '', 0, 0)}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.digCap(\"digcapid_0\").vecVarOnly().pin(\"SDO\").capMode(TA::SER).bitPerWord(16).samples(1*16).execute();\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][3]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_TC_RAW_00//{gav('V_VBG_ACC_TC_RAW[00]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][5]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_TC_RAW_01//{gav('V_VBG_ACC_TC_RAW[01]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][7]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_TC_RAW_02//{gav('V_VBG_ACC_TC_RAW[02]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][9]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_TC_RAW_03//{gav('V_VBG_ACC_TC_RAW[03]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][11]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_TC_RAW_04//{gav('V_VBG_ACC_TC_RAW[04]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][13]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_TC_RAW_05//{gav('V_VBG_ACC_TC_RAW[05]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][15]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_TC_RAW_06//{gav('V_VBG_ACC_TC_RAW[06]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][17]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_TC_RAW_07//{gav('V_VBG_ACC_TC_RAW[07]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][19]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_TC_RAW_08//{gav('V_VBG_ACC_TC_RAW[08]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][21]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_TC_RAW_09//{gav('V_VBG_ACC_TC_RAW[09]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][23]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_TC_RAW_10//{gav('V_VBG_ACC_TC_RAW[10]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][25]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_TC_RAW_11//{gav('V_VBG_ACC_TC_RAW[11]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][27]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_TC_RAW_12//{gav('V_VBG_ACC_TC_RAW[12]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][29]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_TC_RAW_13//{gav('V_VBG_ACC_TC_RAW[13]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][31]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_TC_RAW_14//{gav('V_VBG_ACC_TC_RAW[14]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][33]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_ACC_TC_RAW_15//{gav('V_VBG_ACC_TC_RAW[15]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n aI_Captured_0 = rdi.id(\"digcapid_0\").getVector(\"SDO\");\n ARRAY_D ad_jsubresults_INT2; ad_jsubresults_INT2.resize(16); ad_jsubresults_INT2.init(-9.9);\n ARRAY_D ad_jsubresults_ASDX; ad_jsubresults_ASDX.resize(16); ad_jsubresults_ASDX.init(-9.9);\n ad_jsubresults_INT2 = rdi.id(\"dcid_0\").getMultiValue(\"INT2\");\n ad_jsubresults_ASDX = rdi.id(\"dcid_0\").getMultiValue(\"ASDX\");\n \n aI_Captured_0[0] = Switch_High_Low_Bits_16Bits(aI_Captured_0[0]);\n i_REG_VALUE[curSite] = aI_Captured_0[0];\n FuncPrint(\"REG_VALUE\",i_REG_VALUE[curSite]);\n\n for(int i=0; i<16; i++){\n d_V_VBG_ACC_TC_RAW[curSite][i] = ad_jsubresults_INT2[0 + i] - ad_jsubresults_ASDX[0 + i];\n FuncPrint(\"V_VBG_ACC_TC_RAW_\" + rdi.itos(curSite) + \"_\"+ rdi.itos(i) ,d_V_VBG_ACC_TC_RAW[curSite][i]);\n V_VBG_ACC_TC[curSite][i] = d_V_VBG_ACC_TC_RAW[curSite][i] - V_OFF1_ECOFF[curSite];\n FuncPrint(s_Func_Test_Name_Add_2Num(\"V_VBG_ACC_TC_\", i), V_VBG_ACC_TC[curSite][i]);\n\t\t\t }\n FOR_EACH_SITE_END();\n\n\n /* Ori key coments in subpat1 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 4531: {wri('ANA_TRM_BG', 'REG_VALUE')}\n valid comment[ 1] @ avcline 5570: {Test End: T10_39_ACC_Bandgap_TC_Char}\n */\n static int i_vec_iposition1[32] = {\n 31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,\n 48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63\n };\n for (int i = 0; i < 32; i++)\n {\n i_vec_Num1[i] = i_vec_iposition1[i];\n }\n FOR_EACH_SITE_BEGIN();\n i_WRITE_BACK[curSite] = Switch_High_Low_Bits_16Bits(i_REG_VALUE[curSite]);\n Func_Vector_Dynamic_Write(s_splited_pat_name[1], \"SDX\", i_vec_Num1, 32, i_WRITE_BACK[curSite], 0, 2); //Notes. TEI check per project\n //TODO pl.TEI check position & mask\n FOR_EACH_SITE_END();\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id1\");\n rdi.func().label(s_splited_pat_name[1]).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes1[curSite] = rdi.id(\"burst_id1\").getBurstPassFail();\n FuncPrint(\"REG_VALUE\", i_REG_VALUE[curSite]);\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n\n }\n\n ON_FIRST_INVOCATION_END();\n\n for(int i=0; i < 16; i++){ \n \t TestLog(s_Func_Test_Name_Add_2Num(\"V_VBG_ACC_TC_\", i), V_VBG_ACC_TC[curSite][i]);\n }\n i_funcRes[curSite] = i_funcRes0[curSite] && i_funcRes1[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T10_39_ACC_Bandgap_TC_Char_V2\", T10_39_ACC_Bandgap_TC_Char_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: Bandgap temperature coefficient characterization\n# Characterization loop derived from T10_16_acc_bias_current_trimming\n# - VSS to ASDX(ANAIO2), VREFD to INT2(ANAIO1) with buffer 1 enabled only\n#\n# For all the 16 values of pc_trm_bgp_tc the current values are logged to V_REF_D_TC[00] .. V_REF_D_TC[15].\n# The signal pc_trm_bgp_tc isn't routed to the instance power_topi.PWR_ANA.STBY_REG.\n# Different VREFD values can't be expected.\n#\n# The limit for all the values V_REF_D_TC[] is set to 1.0 .. 1.2 (around the target 1.1, see T10_01).\n#\n# After the characterization loop the register ANA_TRM_BG is set to the previous value,\n# and the test module / IO registers TM_CONF, TM_PIN, TM_ADDR, IO_TEST_IF are set to their reset values.\n#############################################################################################################\ncmt('Version info: $Revision: 2 $ $Author: laj1mu23 $ $Date: 2024/03/25 20:34:28 GMT $')\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_CONF', 0x0011) # Enable TB1; invert test bus\nwac('TM_PIN', 0x0095) # Enable ANAIO1/2; TB1_OUT on ANAIO1; TB2_INP on ANAIO2\nwac('TM_ADDR', 0x070e) # Enable reference block on ATM; Connect VREFD/VSS\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('OCP_MASK', 0x000f) # ANA_TRM_BG<3:0> pc_trm_bgp_tc\nras('REG_VALUE', 'ANA_TRM_BG') # Store the current value\nfor n in range (0, 16, 1):\n cmt('Set trim index to value {} in range (0..15)'.format(n))\n wr('ANA_TRM_BG', n) # ANA_TRM_BG<3:0> pc_trm_bgp_tc\n rac('ANA_TRM_BG',n, 0x000f)\n dly(100e-6)\n gav('V_REF_D_TC_RAW[{:02d}]'.format(n), 'INT2', 'ASDX')\n calc('V_REF_D_TC[{:02d}]'.format(n), 'V_REF_D_TC_RAW[{:02d}]'.format(n), '-', 'V_OFF1_ECOFF')\n log('V_REF_D_TC[{:02d}]'.format(n))\ndly(592e-9)\nwri('ANA_TRM_BG','REG_VALUE') # Write back the stored value\n\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\n", "output": "/*****************************************************\n * T10_40_Standby_Regulator_TC_Char_V2, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n * JSH5SGH: fix some bugs.\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T10_40_Standby_Regulator_TC_Char_V2: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 2;\n vector i_comment_line[i_split_count];\n\n static int i_REG_VALUE[xNSitES];\n ARRAY_I aI_Captured_0;\n static double d_V_REF_D_TC_RAW[xNSitES][16];\n static double V_REF_D_TC[xNSitES][16];\n ARRAY_D ad_V_REF_D_TC_RAW;\n\n static int i_WRITE_BACK[xNSitES];\n static int i_vec_Num1[32] = {0};\n static int i_funcRes0[xNSitES], i_funcRes1[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(i_REG_VALUE, 9, xNSitES);\n \n //!\"CTmsg: cut pattern to 2 parts @ oriAVCvecline [4531]\n //!\"CTmsg: cut pattern to 2 parts @ binarypatline [4521]\n if (i_split_pat_flag)\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n }\n else\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n for(int i=0; i }\n valid comment[ 1] @ avcline 1162: {ras('REG_VALUE', 'ANA_TRM_BG')}\n valid comment[ 2] @ avcline 1275: {cmt: Set trim index to value 0 in range (0..15)}\n valid comment[ 3] @ avcline 1477: {gav('V_REF_D_TC_RAW[00]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 3] @ avcline 1477: {calc('V_REF_D_TC[00]', 'V_REF_D_TC_RAW[00]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 3] @ avcline 1477: {log('V_REF_D_TC[00]', '', '', 0, 0)}\n valid comment[ 4] @ avcline 1478: {cmt: Set trim index to value 1 in range (0..15)}\n valid comment[ 5] @ avcline 1680: {gav('V_REF_D_TC_RAW[01]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 5] @ avcline 1680: {calc('V_REF_D_TC[01]', 'V_REF_D_TC_RAW[01]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 5] @ avcline 1680: {log('V_REF_D_TC[01]', '', '', 0, 0)}\n valid comment[ 6] @ avcline 1681: {cmt: Set trim index to value 2 in range (0..15)}\n valid comment[ 7] @ avcline 1883: {gav('V_REF_D_TC_RAW[02]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 7] @ avcline 1883: {calc('V_REF_D_TC[02]', 'V_REF_D_TC_RAW[02]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 7] @ avcline 1883: {log('V_REF_D_TC[02]', '', '', 0, 0)}\n valid comment[ 8] @ avcline 1884: {cmt: Set trim index to value 3 in range (0..15)}\n valid comment[ 9] @ avcline 2086: {gav('V_REF_D_TC_RAW[03]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 9] @ avcline 2086: {calc('V_REF_D_TC[03]', 'V_REF_D_TC_RAW[03]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 9] @ avcline 2086: {log('V_REF_D_TC[03]', '', '', 0, 0)}\n valid comment[ 10] @ avcline 2087: {cmt: Set trim index to value 4 in range (0..15)}\n valid comment[ 11] @ avcline 2289: {gav('V_REF_D_TC_RAW[04]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 11] @ avcline 2289: {calc('V_REF_D_TC[04]', 'V_REF_D_TC_RAW[04]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 11] @ avcline 2289: {log('V_REF_D_TC[04]', '', '', 0, 0)}\n valid comment[ 12] @ avcline 2290: {cmt: Set trim index to value 5 in range (0..15)}\n valid comment[ 13] @ avcline 2492: {gav('V_REF_D_TC_RAW[05]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 13] @ avcline 2492: {calc('V_REF_D_TC[05]', 'V_REF_D_TC_RAW[05]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 13] @ avcline 2492: {log('V_REF_D_TC[05]', '', '', 0, 0)}\n valid comment[ 14] @ avcline 2493: {cmt: Set trim index to value 6 in range (0..15)}\n valid comment[ 15] @ avcline 2695: {gav('V_REF_D_TC_RAW[06]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 15] @ avcline 2695: {calc('V_REF_D_TC[06]', 'V_REF_D_TC_RAW[06]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 15] @ avcline 2695: {log('V_REF_D_TC[06]', '', '', 0, 0)}\n valid comment[ 16] @ avcline 2696: {cmt: Set trim index to value 7 in range (0..15)}\n valid comment[ 17] @ avcline 2898: {gav('V_REF_D_TC_RAW[07]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 17] @ avcline 2898: {calc('V_REF_D_TC[07]', 'V_REF_D_TC_RAW[07]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 17] @ avcline 2898: {log('V_REF_D_TC[07]', '', '', 0, 0)}\n valid comment[ 18] @ avcline 2899: {cmt: Set trim index to value 8 in range (0..15)}\n valid comment[ 19] @ avcline 3101: {gav('V_REF_D_TC_RAW[08]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 19] @ avcline 3101: {calc('V_REF_D_TC[08]', 'V_REF_D_TC_RAW[08]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 19] @ avcline 3101: {log('V_REF_D_TC[08]', '', '', 0, 0)}\n valid comment[ 20] @ avcline 3102: {cmt: Set trim index to value 9 in range (0..15)}\n valid comment[ 21] @ avcline 3304: {gav('V_REF_D_TC_RAW[09]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 21] @ avcline 3304: {calc('V_REF_D_TC[09]', 'V_REF_D_TC_RAW[09]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 21] @ avcline 3304: {log('V_REF_D_TC[09]', '', '', 0, 0)}\n valid comment[ 22] @ avcline 3305: {cmt: Set trim index to value 10 in range (0..15)}\n valid comment[ 23] @ avcline 3507: {gav('V_REF_D_TC_RAW[10]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 23] @ avcline 3507: {calc('V_REF_D_TC[10]', 'V_REF_D_TC_RAW[10]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 23] @ avcline 3507: {log('V_REF_D_TC[10]', '', '', 0, 0)}\n valid comment[ 24] @ avcline 3508: {cmt: Set trim index to value 11 in range (0..15)}\n valid comment[ 25] @ avcline 3710: {gav('V_REF_D_TC_RAW[11]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 25] @ avcline 3710: {calc('V_REF_D_TC[11]', 'V_REF_D_TC_RAW[11]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 25] @ avcline 3710: {log('V_REF_D_TC[11]', '', '', 0, 0)}\n valid comment[ 26] @ avcline 3711: {cmt: Set trim index to value 12 in range (0..15)}\n valid comment[ 27] @ avcline 3913: {gav('V_REF_D_TC_RAW[12]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 27] @ avcline 3913: {calc('V_REF_D_TC[12]', 'V_REF_D_TC_RAW[12]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 27] @ avcline 3913: {log('V_REF_D_TC[12]', '', '', 0, 0)}\n valid comment[ 28] @ avcline 3914: {cmt: Set trim index to value 13 in range (0..15)}\n valid comment[ 29] @ avcline 4116: {gav('V_REF_D_TC_RAW[13]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 29] @ avcline 4116: {calc('V_REF_D_TC[13]', 'V_REF_D_TC_RAW[13]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 29] @ avcline 4116: {log('V_REF_D_TC[13]', '', '', 0, 0)}\n valid comment[ 30] @ avcline 4117: {cmt: Set trim index to value 14 in range (0..15)}\n valid comment[ 31] @ avcline 4319: {gav('V_REF_D_TC_RAW[14]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 31] @ avcline 4319: {calc('V_REF_D_TC[14]', 'V_REF_D_TC_RAW[14]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 31] @ avcline 4319: {log('V_REF_D_TC[14]', '', '', 0, 0)}\n valid comment[ 32] @ avcline 4320: {cmt: Set trim index to value 15 in range (0..15)}\n valid comment[ 33] @ avcline 4522: {gav('V_REF_D_TC_RAW[15]', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 33] @ avcline 4522: {calc('V_REF_D_TC[15]', 'V_REF_D_TC_RAW[15]', '-', 'V_OFF1_ECOFF')}\n valid comment[ 33] @ avcline 4522: {log('V_REF_D_TC[15]', '', '', 0, 0)}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.digCap(\"digcapid_0\").vecVarOnly().pin(\"SDO\").capMode(TA::SER).bitPerWord(16).samples(1*16).execute();\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][3]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_REF_D_TC_RAW_00//{gav('V_REF_D_TC_RAW[00]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][5]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_REF_D_TC_RAW_01//{gav('V_REF_D_TC_RAW[01]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][7]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_REF_D_TC_RAW_02//{gav('V_REF_D_TC_RAW[02]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][9]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_REF_D_TC_RAW_03//{gav('V_REF_D_TC_RAW[03]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][11]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_REF_D_TC_RAW_04//{gav('V_REF_D_TC_RAW[04]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][13]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_REF_D_TC_RAW_05//{gav('V_REF_D_TC_RAW[05]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][15]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_REF_D_TC_RAW_06//{gav('V_REF_D_TC_RAW[06]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][17]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_REF_D_TC_RAW_07//{gav('V_REF_D_TC_RAW[07]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][19]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_REF_D_TC_RAW_08//{gav('V_REF_D_TC_RAW[08]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][21]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_REF_D_TC_RAW_09//{gav('V_REF_D_TC_RAW[09]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][23]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_REF_D_TC_RAW_10//{gav('V_REF_D_TC_RAW[10]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][25]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_REF_D_TC_RAW_11//{gav('V_REF_D_TC_RAW[11]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][27]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_REF_D_TC_RAW_12//{gav('V_REF_D_TC_RAW[12]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][29]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_REF_D_TC_RAW_13//{gav('V_REF_D_TC_RAW[13]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][31]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_REF_D_TC_RAW_14//{gav('V_REF_D_TC_RAW[14]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][33]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_REF_D_TC_RAW_15//{gav('V_REF_D_TC_RAW[15]', 'INT2', 'ASDX', 2, 0.0001, True)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n aI_Captured_0 = rdi.id(\"digcapid_0\").getVector(\"SDO\");\n ARRAY_D ad_jsubresults_INT2; ad_jsubresults_INT2.resize(16); ad_jsubresults_INT2.init(-9.9);\n ARRAY_D ad_jsubresults_ASDX; ad_jsubresults_ASDX.resize(16); ad_jsubresults_ASDX.init(-9.9);\n ad_jsubresults_INT2 = rdi.id(\"dcid_0\").getMultiValue(\"INT2\");\n ad_jsubresults_ASDX = rdi.id(\"dcid_0\").getMultiValue(\"ASDX\");\n \n aI_Captured_0[0] = Switch_High_Low_Bits_16Bits(aI_Captured_0[0]);\n i_REG_VALUE[curSite] = aI_Captured_0[0];\n FuncPrint(\"REG_VALUE\",i_REG_VALUE[curSite]);\n\n for(int i=0; i<16; i++){\n d_V_REF_D_TC_RAW[curSite][i] = ad_jsubresults_INT2[0 + i] - ad_jsubresults_ASDX[0 + i];\n FuncPrint(\"V_REF_D_TC_RAW_\" + rdi.itos(curSite) + \"_\"+ rdi.itos(i) ,d_V_REF_D_TC_RAW[curSite][i]);\n V_REF_D_TC[curSite][i] = d_V_REF_D_TC_RAW[curSite][i] - V_OFF1_ECOFF[curSite];\n FuncPrint(s_Func_Test_Name_Add_2Num(\"V_REF_D_TC_\", i), V_REF_D_TC[curSite][i]);\n\t\t\t }\n FOR_EACH_SITE_END();\n\n\n /* Ori key coments in subpat1 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 4531: {wri('ANA_TRM_BG', 'REG_VALUE')}\n valid comment[ 1] @ avcline 5570: {Test End: T10_40_Standby_Regulator_TC_Char}\n */\n static int i_vec_iposition1[32] = {\n 31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,\n 48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63\n };\n for (int i = 0; i < 32; i++)\n {\n i_vec_Num1[i] = i_vec_iposition1[i];\n }\n FOR_EACH_SITE_BEGIN();\n i_WRITE_BACK[curSite] = Switch_High_Low_Bits_16Bits(i_REG_VALUE[curSite]);\n Func_Vector_Dynamic_Write(s_splited_pat_name[1], \"SDX\", i_vec_Num1, 32, i_WRITE_BACK[curSite], 0, 2); //Notes. TEI check per project\n\n FOR_EACH_SITE_END();\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id1\");\n rdi.func().label(s_splited_pat_name[1]).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes1[curSite] = rdi.id(\"burst_id1\").getBurstPassFail();\n FOR_EACH_SITE_END();\n\n\n }\n\n ON_FIRST_INVOCATION_END();\n\n for(int i=0; i < 16; i++){ \n \t TestLog(s_Func_Test_Name_Add_2Num(\"V_REF_D_TC_\", i), V_REF_D_TC[curSite][i]);\n\t }\n i_funcRes[curSite] = i_funcRes0[curSite] && i_funcRes1[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T10_40_Standby_Regulator_TC_Char_V2\", T10_40_Standby_Regulator_TC_Char_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description:\n# - measure currents for different external voltages, routed VDDD\n# (T02_18_enable_vddd_dc_and_vdda_external_bypass executed before)\n#############################################################################################################\ncmt('Version info: $Revision: 1 $ $Author: hmf1rt $ $Date: 2024/03/13 13:36:52 GMT $')\nfor n in range (13, 8, -1):\n cmt(\"Set voltage to {} V on pad INT1 and measure current\".format(n/10))\n sav(\"INT1\", n/10)\n dly(100e-6)\n gac(f\"I_VDDD_DC_VEXT_{n:02d}\", \"INT1\", i_range=1e-3)\n log(f\"I_VDDD_DC_VEXT_{n:02d}\")\nsav(\"INT1\", 1.1) # as in T02_18_enable_vddd_dc_and_vdda_external_bypass\ndly(100e-6)\n", "output": "/*****************************************************\n * T10_41_VDDD_DC_Vext_Char_V1, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T10_41_VDDD_DC_Vext_Char_V1: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static double d_I_VDDD_DC_VEXT_09[xNSitES];\n static double d_I_VDDD_DC_VEXT_10[xNSitES];\n static double d_I_VDDD_DC_VEXT_11[xNSitES];\n static double d_I_VDDD_DC_VEXT_12[xNSitES];\n static double d_I_VDDD_DC_VEXT_13[xNSitES];\n static int i_funcRes0[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(d_I_VDDD_DC_VEXT_09, 9.9, xNSitES);\n Func_Init_Var(d_I_VDDD_DC_VEXT_10, 9.9, xNSitES);\n Func_Init_Var(d_I_VDDD_DC_VEXT_11, 9.9, xNSitES);\n Func_Init_Var(d_I_VDDD_DC_VEXT_12, 9.9, xNSitES);\n Func_Init_Var(d_I_VDDD_DC_VEXT_13, 9.9, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T10_41_VDDD_DC_Vext_Char}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 0] @ avcline 10: {cmt: Set voltage to 1.3 V on pad INT1 and measure current}\n valid comment[ 0] @ avcline 10: {sav('INT1', 1.3, 2, 0.01, False, False)}\n valid comment[ 1] @ avcline 19: {gac('I_VDDD_DC_VEXT_13', 'INT1', 0.001, 0.0001, True)}\n valid comment[ 1] @ avcline 19: {log('I_VDDD_DC_VEXT_13', '', '', 0, 0)}\n valid comment[ 2] @ avcline 20: {cmt: Set voltage to 1.2 V on pad INT1 and measure current}\n valid comment[ 2] @ avcline 20: {sav('INT1', 1.2, 2, 0.01, False, False)}\n valid comment[ 3] @ avcline 30: {gac('I_VDDD_DC_VEXT_12', 'INT1', 0.001, 0.0001, True)}\n valid comment[ 3] @ avcline 30: {log('I_VDDD_DC_VEXT_12', '', '', 0, 0)}\n valid comment[ 4] @ avcline 31: {cmt: Set voltage to 1.1 V on pad INT1 and measure current}\n valid comment[ 4] @ avcline 31: {sav('INT1', 1.1, 2, 0.01, False, False)}\n valid comment[ 5] @ avcline 40: {gac('I_VDDD_DC_VEXT_11', 'INT1', 0.001, 0.0001, True)}\n valid comment[ 5] @ avcline 40: {log('I_VDDD_DC_VEXT_11', '', '', 0, 0)}\n valid comment[ 6] @ avcline 41: {cmt: Set voltage to 1.0 V on pad INT1 and measure current}\n valid comment[ 6] @ avcline 41: {sav('INT1', 1, 2, 0.01, False, False)}\n valid comment[ 7] @ avcline 50: {gac('I_VDDD_DC_VEXT_10', 'INT1', 0.001, 0.0001, True)}\n valid comment[ 7] @ avcline 50: {log('I_VDDD_DC_VEXT_10', '', '', 0, 0)}\n valid comment[ 8] @ avcline 51: {cmt: Set voltage to 0.9 V on pad INT1 and measure current}\n valid comment[ 8] @ avcline 51: {sav('INT1', 0.9, 2, 0.01, False, False)}\n valid comment[ 9] @ avcline 61: {gac('I_VDDD_DC_VEXT_09', 'INT1', 0.001, 0.0001, True)}\n valid comment[ 9] @ avcline 61: {log('I_VDDD_DC_VEXT_09', '', '', 0, 0)}\n valid comment[ 10] @ avcline 62: {sav('INT1', 1.1, 2, 0.01, False, False)}\n valid comment[ 11] @ avcline 71: {Test End: T10_41_VDDD_DC_Vext_Char}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][0]).pin(\"INT1\").vForce(1.3 V)//{sav('INT1', 1.3, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][1]).pin(\"INT1\").vForce(1.3 V).iMeas().iRange(100 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_VDDD_DC_VEXT_13', 'INT1', 0.001, 0.0001, True)}\n .insertSub(i_comment_line[0][2]).pin(\"INT1\").vForce(1.2 V)//{sav('INT1', 1.2, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][3]).pin(\"INT1\").vForce(1.2 V).iMeas().iRange(100 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_VDDD_DC_VEXT_12', 'INT1', 0.001, 0.0001, True)}\n .insertSub(i_comment_line[0][4]).pin(\"INT1\").vForce(1.1 V)//{sav('INT1', 1.1, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][5]).pin(\"INT1\").vForce(1.1 V).iMeas().iRange(100 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_VDDD_DC_VEXT_11', 'INT1', 0.001, 0.0001, True)}\n .insertSub(i_comment_line[0][6]).pin(\"INT1\").vForce(1 V)//{sav('INT1', 1, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][7]).pin(\"INT1\").vForce(1 V).iMeas().iRange(100 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_VDDD_DC_VEXT_10', 'INT1', 0.001, 0.0001, True)}\n .insertSub(i_comment_line[0][8]).pin(\"INT1\").vForce(0.9 V)//{sav('INT1', 0.9, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][9]).pin(\"INT1\").vForce(0.9 V).iMeas().iRange(100 uA).valueMode(TA::BADC).average(128).measWait(1 ms)//{gac('I_VDDD_DC_VEXT_09', 'INT1', 0.001, 0.0001, True)}\n .insertSub(i_comment_line[0][10]).pin(\"INT1\").vForce(1.1 V).iRange(40 mA)//{sav('INT1', 1.1, 2, 0.01, False, False)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n ARRAY_D ad_jsubresults_INT1; ad_jsubresults_INT1.resize(5); ad_jsubresults_INT1.init(-9.9);\n ad_jsubresults_INT1 = rdi.id(\"dcid_0\").getMultiValue(\"INT1\");\n \n d_I_VDDD_DC_VEXT_09[curSite] = ad_jsubresults_INT1[4];\n d_I_VDDD_DC_VEXT_10[curSite] = ad_jsubresults_INT1[3];\n d_I_VDDD_DC_VEXT_11[curSite] = ad_jsubresults_INT1[2];\n d_I_VDDD_DC_VEXT_12[curSite] = ad_jsubresults_INT1[1];\n d_I_VDDD_DC_VEXT_13[curSite] = ad_jsubresults_INT1[0];\n FuncPrint(\"I_VDDD_DC_VEXT_09\",d_I_VDDD_DC_VEXT_09[curSite]);\n FuncPrint(\"I_VDDD_DC_VEXT_10\",d_I_VDDD_DC_VEXT_10[curSite]);\n FuncPrint(\"I_VDDD_DC_VEXT_11\",d_I_VDDD_DC_VEXT_11[curSite]);\n FuncPrint(\"I_VDDD_DC_VEXT_12\",d_I_VDDD_DC_VEXT_12[curSite]);\n FuncPrint(\"I_VDDD_DC_VEXT_13\",d_I_VDDD_DC_VEXT_13[curSite]);\n\n FOR_EACH_SITE_END();\n\n\n ON_FIRST_INVOCATION_END();\n\n TestLog(\"I_VDDD_DC_VEXT_09\", d_I_VDDD_DC_VEXT_09[curSite]);\n TestLog(\"I_VDDD_DC_VEXT_10\", d_I_VDDD_DC_VEXT_10[curSite]);\n TestLog(\"I_VDDD_DC_VEXT_11\", d_I_VDDD_DC_VEXT_11[curSite]);\n TestLog(\"I_VDDD_DC_VEXT_12\", d_I_VDDD_DC_VEXT_12[curSite]);\n TestLog(\"I_VDDD_DC_VEXT_13\", d_I_VDDD_DC_VEXT_13[curSite]);\n i_funcRes[curSite] = i_funcRes0[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T10_41_VDDD_DC_Vext_Char_V1\", T10_41_VDDD_DC_Vext_Char_V1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: FOSC measurement (FOSC_div8)\n# Steps: 1. Route fsoc_div8 to OSDO pad\n#############################################################################################################\ncmt('Version info: $Revision: bai430aa_rel/2 $ $Author: hmf1rt $ $Date: 2024/08/15 06:39:49 GMT $')\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('DTB3',0x004c) # Route fosc_clk to OSDO\ndly(100e-6)\ngaf('F_FOSC_M', 'OSDO', f_range=10e6)\nlog('F_FOSC_M')\nwac('DTB3',0x0000) # Disable DTB3X\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T11_02_fosc_reference_measurement_V1: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n static double F_FOSC_M[xNSitES];\n // Auto_Code_Variable_define\n string Mean_Port = \"Non_OSDO_ASDX_Port\";\n string Measure_Port = \"OSDO_Port\";\n static double sample_period_INT1;\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n sample_period_INT1 = Primary.getSpecification().getSpecValue(\"per_ns@OSDO_Port\");\n rdi.enableOre(oreFlag);\n rdi.oreFile(\"./ORE_Files/rdi_ore_T11_02_fosc_reference_measurement.xml\");\n\n rdi.dc().pin(\"VDDIO\").vForce(1.8 V).execute();\n Primary.getLevelSpec().change(\"VDDIO\",1.8);\n FLUSH(TM::APRM);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T11_02_fosc_reference_measurement_V1_PAT_id\");\n rdi.port(Mean_Port).func().label(s_label_name).stopVec(i_comment_line0[0]-1).execute();\n rdi.portSync();\n rdi.port(Measure_Port).digCap(\"T11_02_fosc_reference_measurement_V1_DigcapInsert_id\").pin(\"OSDO\").capMode(TA::PAR).samples(16384).bitPerWord(1).execute();\n rdi.portSync();\n rdi.port(Mean_Port).func().label(s_label_name).startVec(i_comment_line0[0]).execute();\n for (int i=0; i<100; i++)\n {\n \t rdi.port(Mean_Port).func().label(s_label_name).execute();\n }\n\n RDI_END();\n\n // Auto_Code_Execution_Part\n\n rdi.dc().pin(\"VDDIO\").vForce(3 V).execute();\n Primary.getLevelSpec().change(\"VDDIO\",3);\n FLUSH(TM::APRM);\n\n ON_FIRST_INVOCATION_END();\n // Auto_Code_Retrieve_Data\n \n int Func_result = rdi.id(\"T11_02_fosc_reference_measurement_V1_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n\n ARRAY_I vec = rdi.id(\"T11_02_fosc_reference_measurement_V1_DigcapInsert_id\").getVector(\"OSDO\");\n F_FOSC_M[CURRENT_SITE_NUMBER()-1] = d_Func_Calculate_Freq_ByFFT(vec,sample_period_INT1*1e-3) * 1e6;\n FuncPrint(\"F_FOSC_M\", F_FOSC_M[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"F_FOSC_M\", F_FOSC_M[CURRENT_SITE_NUMBER()-1]);\n // Auto_Code_Judge_and_log\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T11_02_fosc_reference_measurement_V1\", T11_02_fosc_reference_measurement_V1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: FOSC characterization\n# Info : fosc frequency control variable monotonically increasing from -128 to 127\n# Steps: 1. Route fosc to INT1 pad\n# 2. Loop over trim steps, measure and log the frequency\n#############################################################################################################\ncmt('Version info: $Revision: bai430aa_rel/1 $ $Author: hmf1rt $ $Date: 2024/07/18 13:26:36 GMT $')\nwr('EXT_MODE', 0xc00f) # Switch to TEST page\nwac('DTB1',0x004c) # Route fosc_clk to INT1\nwr('EXT_MODE', 0xc00d) # Switch to ANA page\nwac('OCP_MASK', 0xff00) # Set masking register\nras('REG_VALUE', 'ANA_TRM_OSC') # Store the current value\nfor n in range (0, 256, 1): \n cmt('Set trim index to value {} in range (0..255)'.format(n))\n wr('ANA_TRM_OSC',n*256) # <15:8>, pc_trm_fosc \n rac('ANA_TRM_OSC',n*256, 0xff00)\n dly(10e-6)\n gaf('F_FOSC_REF_C[{:03d}]'.format(n), 'INT1')\n log('F_FOSC_REF_C[{:03d}]'.format(n))\ndly(296e-9)\nwri('ANA_TRM_OSC','REG_VALUE' ) # Write back the original value\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n# Clean\nwr('EXT_MODE', 0xc00f) # Switch to TEST page\nwac('DTB1',0x0000) # Disable DTB1\n", "output": "/*****************************************************\n * T11_03_FOSC_Reference_Char_R1, description file version Notfound, avc file version Notfound\n * First Editor : jsh5sgh\n * Code generated with autocoding tool V2.9.1, in TOI2 standard way by module write_standard\n * Change History:\n * JSH5SGH R1: version update.\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T11_03_FOSC_Reference_Char_R1: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 3;\n vector i_comment_line[i_split_count];\n\n ARRAY_I aI_Captured_0;\n static double F_FOSC_REF_C[xNSitES][256];\n static double SAMPLE_PERIOD_US;\n\n static int i_REG_VALUE[xNSitES];\n static int i_WRITE_BACK[xNSitES];\n static int i_vec_Num2[32] = {0};\n static int i_funcRes0[xNSitES], i_funcRes1[xNSitES], i_funcRes2[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n \n //!\"CTmsg: cut pattern to 3 parts @ oriAVCvecline [867, 52637]\n //!\"CTmsg: cut pattern to 3 parts @ binarypatline [857, 52627]\n if (i_split_pat_flag)\n {\n \t split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n }\n else\n {\n\t\t\t split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n\t\t\t for(int i=0; i }\n valid comment[ 1] @ avcline 552: {ras('REG_VALUE', 'ANA_TRM_OSC')}\n valid comment[ 2] @ avcline 665: {cmt: Set trim index to value 0 in range (0..255)}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.digCap(\"digcapid_0\").label(s_splited_pat_name[0]).pin(\"SDO\").capMode(TA::SER).bitPerWord(16).samples(1*16).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n aI_Captured_0 = rdi.id(\"digcapid_0\").getVector(\"SDO\");\n aI_Captured_0[0] = Switch_High_Low_Bits_16Bits(aI_Captured_0[0]);\n i_REG_VALUE[curSite] = aI_Captured_0[0];\n FuncPrint(\"REG_VALUE\",i_REG_VALUE[curSite]);\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n\n /* Ori key coments in subpat1 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 867: {gaf('F_FOSC_REF_C[000]', 'INT1', 2e+07, True)}\n valid comment[ 0] @ avcline 867: {log('F_FOSC_REF_C[000]', '', '', 0, 0)}\n valid comment[ 1] @ avcline 868: {cmt: Set trim index to value 1 in range (0..255)}\n\n valid comment[ 2] @ avcline 1070: {gaf('F_FOSC_REF_C[001]', 'INT1', 2e+07, True)}\n valid comment[ 2] @ avcline 1070: {log('F_FOSC_REF_C[001]', '', '', 0, 0)}\n valid comment[ 3] @ avcline 1071: {cmt: Set trim index to value 2 in range (0..255)}\n valid comment[ 4] @ avcline 1273: {gaf('F_FOSC_REF_C[002]', 'INT1', 2e+07, True)}\n valid comment[ 4] @ avcline 1273: {log('F_FOSC_REF_C[002]', '', '', 0, 0)}\n ...\n valid comment[509] @ avcline 52430: {cmt: Set trim index to value 255 in range (0..255)}\n valid comment[510] @ avcline 52632: {gaf('F_FOSC_REF_C[255]', 'INT1', 2e+07, True)}\n valid comment[510] @ avcline 52632: {log('F_FOSC_REF_C[255]', '', '', 0, 0)}\n */\n\n Primary.timing(SPECIFICATION(\"SPI_STD_INT1_FREQ_MEAS\"));\n FLUSH(TM::APRM);\n SAMPLE_PERIOD_US = Primary.getSpecification().getSpecValue(\"per_ns@INT1_Port\") * 1e-03;\n FuncPrint(\"SAMPLE_PERIOD_US\", SAMPLE_PERIOD_US);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id1\");\n\t\t\t for(int i=0; i<255; i++)\n\t\t\t {\n\t\t\t\t rdi.port(\"INT1_Port\").digCap(\"vv_meas_code_\"+rdi.itos(i)).pin(\"INT1\").capMode(TA::SER).samples(4096).bitPerWord(1).execute();\n\t\t\t\t rdi.portSync();\n\t\t\t\t rdi.port(\"Non_INT1_Port\").func().label(s_splited_pat_name[1]).startVec(i_comment_line[1][2*i]).stopVec(i_comment_line[1][2*i+2]-1).execute();\n\t\t\t\t rdi.portSync();\n\t\t\t }\n\t\t\t rdi.port(\"INT1_Port\").digCap(\"vv_meas_code_\"+rdi.itos(255)).pin(\"INT1\").capMode(TA::SER).samples(4096).bitPerWord(1).execute();\n\t\t\t rdi.portSync();\n\t\t\t rdi.port(\"Non_INT1_Port\").func().label(s_splited_pat_name[1]).startVec(i_comment_line[1][510]).execute();\n\t\t\t rdi.portSync();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n\t\t\t i_funcRes1[curSite] = rdi.id(\"burst_id1\").getBurstPassFail();\n\t\t\t ARRAY_I ai_meas_code;\n\t\t\t for(int i=0; i<256; i++){\n\t\t\t\t ai_meas_code = rdi.id(\"vv_meas_code_\" + rdi.itos(i)).getVector();\n\t\t\t\t F_FOSC_REF_C[curSite][i] = d_Func_Calculate_Freq_ByFFT(ai_meas_code, SAMPLE_PERIOD_US) *1e6;\n\t\t\t\t FuncPrint(\"F_FOSC_REF_C_\"+rdi.itos(i), F_FOSC_REF_C[curSite][i]);\n\t\t\t }\n\n FOR_EACH_SITE_END();\n\n Primary.timing(TIMING_SPEC(1,1));\n Primary.timing(1);\n FLUSH(TM::APRM);\n /* Ori key coments in subpat2 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 52637: {wri('ANA_TRM_OSC', 'REG_VALUE')}\n valid comment[ 1] @ avcline 53179: {Test End: T11_03_FOSC_Reference_Char}\n */\n static int i_vec_iposition2[32] = {\n 31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,\n 48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63\n };\n for (int i = 0; i < 32; i++)\n {\n i_vec_Num2[i] = i_vec_iposition2[i];\n }\n FOR_EACH_SITE_BEGIN();\n i_WRITE_BACK[curSite] = Switch_High_Low_Bits_16Bits(i_REG_VALUE[curSite]);\n Func_Vector_Dynamic_Write(s_splited_pat_name[2], \"SDX\", i_vec_Num2, 32, i_WRITE_BACK[curSite], 0, 2); //Notes. TEI check per project\n FOR_EACH_SITE_END();\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id2\");\n rdi.func().label(s_splited_pat_name[2]).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes2[curSite] = rdi.id(\"burst_id2\").getBurstPassFail();\n\n FOR_EACH_SITE_END();\n\n\n }\n\n ON_FIRST_INVOCATION_END();\n\n\t for(int i=0; i<256; i++){\n\t\t TestLog(s_Func_Test_Name_Add_3Num(\"F_FOSC_REF_C_\",i), F_FOSC_REF_C[curSite][i]);\n\t }\n i_funcRes[curSite] = i_funcRes0[curSite] && i_funcRes1[curSite] && i_funcRes2[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T11_03_FOSC_Reference_Char_R1\", T11_03_FOSC_Reference_Char_R1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 3 $ $Author: hmf1rt $ $Date: 2024/04/24 11:23:42 GMT $')\ncmt('Execute this pattern with spi_slow DVC timing file')\nfor n in range (0, 256, 1):\n cmt('Set trim index to value {} in range (0..255)'.format(n))\n wac('EXT_MODE', 0xc00d) # Switch to ANA, PMU register page\n wac('OCP_MASK', 0xff00) # select pc_trm_fosc\n wr('ANA_TRM_OSC', n*256) # Set trim value\n rac('ANA_TRM_OSC',n*256, 0xff00) # Check register setting for pc_trm_fosc\n wr('OCP_MASK', 0x0000) # reset OCP mask\n rac('OCP_MASK', 0xffff) # Check masking register reset\n wr('EXT_MODE', 0xc006) # Switch to FCU register page\n ras('N_ST1_{:03d}'.format(n), 'WLT_TEST_CNT') # 1st read of the counter\n dly((1216-113)*148e-9) # SPI read access: 113 tester cycles\n ras('N_ST2_{:03d}'.format(n), 'WLT_TEST_CNT') # 2nd read of the counter\ncmt('all calc() operations outside of the main loop')\nfor n in range (0, 256, 1):\n calc('DIFF_CNT','N_ST2_{:03d}'.format(n),'-','N_ST1_{:03d}'.format(n))\n dly(148e-9) \n calc('DIFF[{}]'.format(n), 'DIFF_CNT','csu', 12) # for 12bit counter\t\ncmt('Select N_OPT_PC_TRM_FOSC = n with minimal absolute difference to the target value 1216*148ns*6.72MHz=1209); 179.968us')\noti('N_OPT_CNT_TRM_FOSC','DIFF', 1209)\nlog('N_OPT_CNT_TRM_FOSC')\notv('CNT_TRM_FOSC','DIFF', 1209)\ncalc('F_OTP_CNT_TRM_FOSC', 'CNT_TRM_FOSC', '/', 179.968e-6)\nlog('F_OPT_CNT_TRM_FOSC')\nwac('EXT_MODE', 0xc00d) # Switch to ANA, PMU register page\ncalc('ANA_TRM_OSC_VAL','N_OPT_CNT_TRM_FOSC','*','{}'.format(256))\nlog('ANA_TRM_OSC_VAL')\nwac('OCP_MASK', 0xff00) # select pc_trm_fosc\nwri('ANA_TRM_OSC','ANA_TRM_OSC_VAL' ) # Write the trim value\nras('ANA_TRM_OSC_15_8', 'ANA_TRM_OSC' ) # read it back\ncalc('ANA_TRM_OSC_RD', 'ANA_TRM_OSC_15_8', '>>', 8)\ncmt('The test item is a functional fail if ANA_TRM_OSC_RD != N_OPT_CNT_TRM_FOSC')\nwr('OCP_MASK', 0x0000) # reset OCP mask\nrac('OCP_MASK', 0xffff) # Check masking register reset\n\n###############################\n## assumption A: period is linear with 256 steps from 4.4MHz to 12MHz\n##\n## frequency error for LSB(ANA_TRM_OSC): f(target+1)-f(target)= (12.0-4.4)/256 MHz= 29kHz\n##\n## measurement error: both N_ST1 and N_ST2 have a quantization error of 1 (different clock domains FCLK / TESTER(SPI))\n## worst case at 4.4 MHz: 792 edge counts in the measurement window 179.968us\n## ((1+1)/ 792) * 4.4MHz = 11.1kHz ==> enough for the trimming at a frequency of 4.4MHz\n##\n## 1216*148ns * 12MHz = 2160 < 4096 ==> no overrun; no additional read required\n##\n## TODO: rewrite the dly() method to tester cycle count; correct the target value for the counter difference\n## verify the N_OPT_PC_TRM_FOSC against analog values (e.g. TRIM resistors)\n##\n## TODO: check tb_bai450_top.i_bai_top.bai_core.power_topi.PWR_FOSC.FOSC.TRM for the assumption A\n## frequency error is 16/14*29kHz= 33kHz (see the DMS model)\n## frequency is linear for signed (!) values of ANA_TRM_OSC => start with 0 for binary search\n## double check the formulas in the PWR_FOSC.FOSC.TRM wreal model with the analog circuit\n## Which trimmed voltages/currents are required for the FOSC trimming ?\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T11_05_FOSC_CNT_reference_trimming_V3: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n INT split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &split_pat_flag);\n vector s_splited_pat_name;\n const int split_count = 2; // Alarm:: split_count need manual confirm.\n s_splited_pat_name.resize(split_count);\n vector i_comment_line[split_count];\n\n static int N_ST1[xNSitES][256], N_ST2[xNSitES][256];\n int DIFF_CNT;\n static int diff[xNSitES][256];\n static int ANA_TRM_OSC_15_8[xNSitES];\n static int N_OPT_CNT_TRM_FOSC[xNSitES], CNT_TRM_FOSC[xNSitES], ANA_TRM_OSC_VAL[xNSitES], ANA_TRM_OSC_RD[xNSitES];\n static double F_OPT_CNT_TRM_FOSC[xNSitES];\n ARRAY_LL ANA_TRM_OSC_VAL_rtv;\n const int Wri_Bit_Length = 33;\n const int Wri_Bit_Position = 31;\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n//\t rdi.enableOre(oreFlag);\n//\t rdi.oreFile(\"./ORE_Files/rdi_ore_T11_05_FOSC_CNT_REFERENCE_TRIMMING.xml\");\n\n GET_TESTSUITE_NAME(test_name);\n ANA_TRM_OSC_VAL_rtv.resize(xNSitES);\n\n if (split_pat_flag)\n {\n split_pattern(s_label_name,\"wri\",split_pat_flag,s_splited_pat_name);\n }\n else\n {\n for (int i = 0; i> 8;\n// // Auto_Code_Retrieve_Data\n//\n int Func_result0 = rdi.id(\"T11_05_FOSC_CNT_reference_trimming_V3_PAT_id0\").getBurstPassFail();\n int Func_result1 = rdi.id(\"T11_05_FOSC_CNT_reference_trimming_V3_PAT_id1\").getBurstPassFail();\n FuncPrint(\"Func_result0\", Func_result0);\n FuncPrint(\"Func_result1\", Func_result1);\n int Func_result = 1 * Func_result0 * Func_result1;\n if ((ANA_TRM_OSC_RD[CURRENT_SITE_NUMBER()-1]) != N_OPT_CNT_TRM_FOSC[CURRENT_SITE_NUMBER()-1]) Func_result=99;\n FuncPrint(\"Func_result\", Func_result);\n FuncPrint(\"ANA_TRM_OSC_RD\", ANA_TRM_OSC_RD[CURRENT_SITE_NUMBER()-1]);\n// FuncPrint(\"N_OPT_CNT_TRM_FOSC\", N_OPT_CNT_TRM_FOSC[CURRENT_SITE_NUMBER()-1]);\n\n\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n TestLog(\"N_OPT_CNT_TRM_FOSC\", N_OPT_CNT_TRM_FOSC[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"F_OPT_CNT_TRM_FOSC\", F_OPT_CNT_TRM_FOSC[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"ANA_TRM_OSC_VAL\", ANA_TRM_OSC_VAL[CURRENT_SITE_NUMBER()-1]);\n // Auto_Code_Judge_and_log\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T11_05_FOSC_CNT_reference_trimming_V3\", T11_05_FOSC_CNT_reference_trimming_V3);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: bai430aa_rel/1 $ $Author: hmf1rt $ $Date: 2024/07/18 13:26:36 GMT $')\nwr('EXT_MODE', 0xc006) # Switch to FCU register page\nras('N_ST1', 'WLT_TEST_CNT') # 1st read of the counter\ndly((1216-113)*74.0e-9) # SPI read access: 113 tester cycles\nras('N_ST2', 'WLT_TEST_CNT') # 2nd read of the counter\ncalc('DIFF_CNT','N_ST2','-','N_ST1')\ncalc('DIFF_FOSC_CNT_M', 'DIFF_CNT','csu', 12) # for 12bit counter\nlog('DIFF_FOSC_CNT_M')\n", "output": "/*****************************************************\n * T11_06_FOSC_CNT_Measurement_R1, description file version Notfound, avc file version Notfound\n * First Editor : jsh5sgh\n * Code generated with autocoding tool V2.9.1, in TOI2 standard way by module write_standard\n * Change History:\n * JSH5SGH R1: version update.\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T11_06_FOSC_CNT_Measurement_R1: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static int N_ST1[xNSitES], N_ST2[xNSitES];\n static int DIFF_CNT[xNSitES], DIFF_FOSC_CNT_M[xNSitES];\n ARRAY_I aI_Captured_0;\n static int i_funcRes0[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(N_ST1, 9, xNSitES);\n Func_Init_Var(N_ST2, 9, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T11_06_FOSC_CNT_Measurement}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 1] @ avcline 89: {ras('N_ST1', 'WLT_TEST_CNT')}\n valid comment[ 2] @ avcline 211: {ras('N_ST2', 'WLT_TEST_CNT')}\n valid comment[ 3] @ avcline 324: {calc('DIFF_CNT', 'N_ST2', '-', 'N_ST1')}\n valid comment[ 3] @ avcline 324: {calc('DIFF_FOSC_CNT_M', 'DIFF_CNT', 'csu', '12')}\n valid comment[ 3] @ avcline 324: {log('DIFF_FOSC_CNT_M', '', '', 0, 0)}\n valid comment[ 4] @ avcline 325: {Test End: T11_06_FOSC_CNT_Measurement}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.digCap(\"digcapid_0\").label(s_splited_pat_name[0]).pin(\"SDO\").capMode(TA::SER).bitPerWord(16).samples(2*16).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n aI_Captured_0 = rdi.id(\"digcapid_0\").getVector(\"SDO\");\n\n aI_Captured_0[0] = Switch_High_Low_Bits_16Bits(aI_Captured_0[0]);\n N_ST1[curSite] = aI_Captured_0[0];\n FuncPrint(\"N_ST1\",N_ST1[curSite]);\n\n aI_Captured_0[1] = Switch_High_Low_Bits_16Bits(aI_Captured_0[1]);\n N_ST2[curSite] = aI_Captured_0[1];\n FuncPrint(\"N_ST2\",N_ST2[curSite]);\n\n DIFF_CNT[curSite] = N_ST2[curSite] - N_ST1[curSite];\n DIFF_FOSC_CNT_M[curSite] = i_Func_Signed_To_Unsigned(DIFF_CNT[curSite], 12);\n FuncPrint(\"DIFF_FOSC_CNT_M\",DIFF_FOSC_CNT_M[curSite]);\n\n FOR_EACH_SITE_END();\n\n\n ON_FIRST_INVOCATION_END();\n\n TestLog(\"DIFF_FOSC_CNT_M\",DIFF_FOSC_CNT_M[curSite]);\n i_funcRes[curSite] = i_funcRes0[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T11_06_FOSC_CNT_Measurement_R1\", T11_06_FOSC_CNT_Measurement_R1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: bai430aa_rel/1 $ $Author: hmf1rt $ $Date: 2024/07/18 13:26:36 GMT $')\nwac('EXT_MODE', 0xc00d) # Switch to ANA, PMU register page\nras('REG_VALUE', 'ANA_TRM_OSC') # Store the current value\nfor n in range (0, 256, 1):\n cmt('Set char index to value {} in range (0..255)'.format(n))\n wac('EXT_MODE', 0xc00d) # Switch to ANA, PMU register page\n wac('OCP_MASK', 0xff00) # select pc_trm_fosc\n wr('ANA_TRM_OSC', n*256) # Set char value\n rac('ANA_TRM_OSC',n*256, 0xff00) # Check register setting for pc_trm_fosc\n wr('OCP_MASK', 0x0000) # reset OCP mask\n rac('OCP_MASK', 0xffff) # Check masking register reset\n## checks wac()/rac() take longer than the dly() for measurement (inside the loop)\n wr('EXT_MODE', 0xc006) # Switch to FCU register page\n ras('N_ST1_{:03d}'.format(n), 'WLT_TEST_CNT') # 1st read of the counter\n dly((1216-113)*74.0e-9) # SPI read access: 113 tester cycles\n ras('N_ST2_{:03d}'.format(n), 'WLT_TEST_CNT') # 2nd read of the counter\ncmt('all calc() operations outside of the main loop')\nfor n in range (0, 256, 1):\n calc('DIFF_CNT','N_ST2_{:03d}'.format(n),'-','N_ST1_{:03d}'.format(n))\n dly(296e-9) # avoid long lines\n calc('DIFF_FOSC_CNT_C[{}]'.format(n), 'DIFF_CNT','csu', 12) # for 12bit counter\n log('DIFF_FOSC_CNT_C[{}]'.format(n))\nwac('EXT_MODE', 0xc00d) # Switch to ANA, PMU register page\nwac('OCP_MASK', 0xff00) # select pc_trm_fosc\nwri('ANA_TRM_OSC','REG_VALUE' ) # Write back the original value\nwr('OCP_MASK', 0x0000) # reset OCP mask\nrac('OCP_MASK', 0xffff) # Check masking register reset\n", "output": "/*****************************************************\n * T11_07_FOSC_CNT_Char_R1, description file version Notfound, avc file version Notfound\n * First Editor : jsh5sgh\n * Code generated with autocoding tool V2.9.1, in TOI2 standard way by module write_standard\n * Change History:\n * JSH5SGH R1: version update.\n * JSH5SGH: fix testlog bug.\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T11_07_FOSC_CNT_Char_R1: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 2;\n vector i_comment_line[i_split_count];\n\n static int N_ST1[xNSitES][256], N_ST2[xNSitES][256];\n static int DIFF_CNT[xNSitES][256], DIFF_FOSC_CNT_C[xNSitES][256];\n ARRAY_I aI_Captured_0;\n static int i_REG_VALUE[xNSitES];\n static int i_WRITE_BACK[xNSitES];\n static int i_vec_Num1[32] = {0};\n static int i_funcRes0[xNSitES], i_funcRes1[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(i_REG_VALUE, 9, xNSitES);\n //!\"CTmsg: cut pattern to 2 parts @ oriAVCvecline [278971]\n //!\"CTmsg: cut pattern to 2 parts @ binarypatline [278961]\n if (i_split_pat_flag)\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n }\n else\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n for(int i=0; i }\n valid comment[ 1] @ avcline 202: {ras('REG_VALUE', 'ANA_TRM_OSC')}\n valid comment[ 2] @ avcline 315: {cmt: Set char index to value 0 in range (0..255)}\n valid comment[ 3] @ avcline 1162: {ras('N_ST1_000', 'WLT_TEST_CNT')}\n valid comment[ 4] @ avcline 1284: {ras('N_ST2_000', 'WLT_TEST_CNT')}\n\n valid comment[ 5] @ avcline 1397: {cmt: Set char index to value 1 in range (0..255)}\n valid comment[ 6] @ avcline 2244: {ras('N_ST1_001', 'WLT_TEST_CNT')}\n valid comment[ 7] @ avcline 2366: {ras('N_ST2_001', 'WLT_TEST_CNT')}\n ...\n valid comment[767] @ avcline 276225: {cmt: Set char index to value 255 in range (0..255)}\n valid comment[768] @ avcline 277072: {ras('N_ST1_255', 'WLT_TEST_CNT')}\n valid comment[769] @ avcline 277194: {ras('N_ST2_255', 'WLT_TEST_CNT')}\n\n valid comment[770] @ avcline 277307: {cmt: all calc() operations outside of the main loop}\n valid comment[770] @ avcline 277307: {calc('DIFF_CNT', 'N_ST2_000', '-', 'N_ST1_000')}\n valid comment[771] @ avcline 277311: {calc('DIFF_FOSC_CNT_C[0]', 'DIFF_CNT', 'csu', '12')}\n valid comment[771] @ avcline 277311: {log('DIFF_FOSC_CNT_C[0]', '', '', 0, 0)}\n\n valid comment[772] @ avcline 277312: {calc('DIFF_CNT', 'N_ST2_001', '-', 'N_ST1_001')}\n valid comment[773] @ avcline 277316: {calc('DIFF_FOSC_CNT_C[1]', 'DIFF_CNT', 'csu', '12')}\n valid comment[773] @ avcline 277316: {log('DIFF_FOSC_CNT_C[1]', '', '', 0, 0)}\n ...\n valid comment[1280] @ avcline 278582: {calc('DIFF_CNT', 'N_ST2_255', '-', 'N_ST1_255')}\n valid comment[1281] @ avcline 278586: {calc('DIFF_FOSC_CNT_C[255]', 'DIFF_CNT', 'csu', '12')}\n valid comment[1281] @ avcline 278586: {log('DIFF_FOSC_CNT_C[255]', '', '', 0, 0)}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.digCap(\"digcapid_0\").label(s_splited_pat_name[0]).pin(\"SDO\").capMode(TA::SER).bitPerWord(16).samples(513*16).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n aI_Captured_0 = rdi.id(\"digcapid_0\").getVector(\"SDO\");\n\n aI_Captured_0[0] = Switch_High_Low_Bits_16Bits(aI_Captured_0[0]);\n i_REG_VALUE[curSite] = aI_Captured_0[0];\n for(int i=0; i<256; i++) {\n aI_Captured_0[2*i+1] = Switch_High_Low_Bits_16Bits(aI_Captured_0[2*i+1]);\n\t\t\t\t N_ST1[curSite][i] = aI_Captured_0[2*i+1];\n\t\t\t\t FuncPrint(\"N_ST1_\"+rdi.itos(i),N_ST1[curSite][i]);\n\n\t\t\t\t aI_Captured_0[2*i+2] = Switch_High_Low_Bits_16Bits(aI_Captured_0[2*i+2]);\n\t\t\t\t N_ST2[curSite][i] = aI_Captured_0[2*i+2];\n\t\t\t\t FuncPrint(\"N_ST2_\"+rdi.itos(i),N_ST2[curSite][i]);\n\n\t\t\t\t DIFF_CNT[curSite][i] = N_ST2[curSite][i] - N_ST1[curSite][i];\n\t\t\t\t DIFF_FOSC_CNT_C[curSite][i] = i_Func_Signed_To_Unsigned(DIFF_CNT[curSite][i], 12);\n\t\t\t\t FuncPrint(\"DIFF_FOSC_CNT_C_\"+rdi.itos(i),DIFF_FOSC_CNT_C[curSite][i]);\n }\n FOR_EACH_SITE_END();\n\n\n /* Ori key coments in subpat1 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 278971: {wri('ANA_TRM_OSC', 'REG_VALUE')}\n valid comment[ 1] @ avcline 279242: {Test End: T11_07_FOSC_CNT_Char}\n */\n static int i_vec_iposition1[32] = {\n 31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,\n 48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63\n };\n for (int i = 0; i < 32; i++)\n {\n i_vec_Num1[i] = i_vec_iposition1[i];\n }\n FOR_EACH_SITE_BEGIN();\n i_WRITE_BACK[curSite] = Switch_High_Low_Bits_16Bits(i_REG_VALUE[curSite]);\n Func_Vector_Dynamic_Write(s_splited_pat_name[1], \"SDX\", i_vec_Num1, 32, i_WRITE_BACK[curSite], 0, 2); //Notes. TEI check per project\n //TODO pl.TEI check position & mask\n FOR_EACH_SITE_END();\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id1\");\n rdi.func().label(s_splited_pat_name[1]).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes1[curSite] = rdi.id(\"burst_id1\").getBurstPassFail();\n\n FOR_EACH_SITE_END();\n\n\n }\n\n ON_FIRST_INVOCATION_END();\n for(int i=0; i<256; i++) {\n \t TestLog(s_Func_Test_Name_Add_3Num(\"DIFF_FOSC_CNT_C_\", i), DIFF_FOSC_CNT_C[curSite][i]);\n }\n i_funcRes[curSite] = i_funcRes0[curSite] && i_funcRes1[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T11_07_FOSC_CNT_Char_R1\", T11_07_FOSC_CNT_Char_R1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: bai430aa_rel/1 $ $Author: hmf1rt $ $Date: 2024/08/15 06:39:49 GMT $')\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('DTB3',0x004b) # Route vco_clk to OSDO\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('OCP_MASK', 0x03e0) # Set masking register\n# Measure with trim setting 12\nwr('ANA_TRM_CAP_PROG_DRV', 0x0c*32) # Set trim value\nrac('ANA_TRM_CAP_PROG_DRV', 0x0c*32, 0x03e0) # Check register setting\nuclk('ASCX')\nbw('ASCX', 1)\ndly(1352*74e-9)\ngaf('F_VCO_12', 'OSDO')\nlog('F_VCO_12')\nubw('ASCX')\nclk('ASCX', 1/148e-9)\n# Measure with trim setting 18\nwr('ANA_TRM_CAP_PROG_DRV', 0x12*32) # Set trim value\nrac('ANA_TRM_CAP_PROG_DRV', 0x12*32, 0x03e0) # Check register setting\nuclk('ASCX')\nbw('ASCX', 1)\ndly(1352*74e-9)\ngaf('F_VCO_18', 'OSDO')\nlog('F_VCO_18')\nubw('ASCX')\nclk('ASCX', 1/148e-9)\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n# Calculate the optimum trim index N_OPT_VCO\ncalc('T_M1', 1, '/', 'F_VCO_12')\ncalc('T_M2', 1, '/', 'F_VCO_18')\ncalc('DELTA_TARGET', 148.8e-9, '-', 'T_M1')\ncalc('DELTA_T', 'T_M2', '-', 'T_M1')\ncalc('TEMP1', 'DELTA_TARGET', '/', 'DELTA_T')\ncalc('TEMP2', 'TEMP1', '*', 6)\ncalc('TEMP3', 'TEMP2', '+', 12)\ncalc('N_OPT_VCO', 'TEMP3', 'round')\nlog('N_OPT_VCO')\n# Calculate the trimmed frequency\ncalc('DELTA_T_LSB', 'DELTA_T', '/', 6)\ncalc('DELTA_N_OPT', 'N_OPT_VCO', '-', 12)\ncalc('DELTA_T_TRIM', 'DELTA_N_OPT', '*', 'DELTA_T_LSB')\ncalc('T_TRIM', 'DELTA_T_TRIM', '+', 'T_M1') \ncalc('F_OPT_VCO', 1, '/', 'T_TRIM')\nlog('F_OPT_VCO')\n# Write N_OTP_VCO to DUT\nwac('OCP_MASK', 0x03e0) # Set masking register\ncalc('ANA_TRM_CAP_PROG_DRV_WR', 'N_OPT_VCO', '<<', 5)\nwri('ANA_TRM_CAP_PROG_DRV', 'ANA_TRM_CAP_PROG_DRV_WR' ) # Write the trim value\nwr('OCP_MASK', 0x0000) # Reset masking register\nras('ANA_TRM_CAP_PROG_DRV_RD', 'ANA_TRM_CAP_PROG_DRV') # Read and save register\ncalc('N_ANA_TRM_CAP_PROG_DRV_RD_9_5', 'ANA_TRM_CAP_PROG_DRV_RD', '&', 0x03e0)\ncalc('N_OPT_VCO_RD', 'N_ANA_TRM_CAP_PROG_DRV_RD_9_5', '>>', 5)\ncmt('The test item is a functional fail if N_OPT_VCO_RD != N_OPT_VCO')\nrac('OCP_MASK', 0xffff) # Check masking register reset\n\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('DTB3',0x0000) # Disable DTB3X\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T11_20_VCO_reference_trimming_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n INT split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &split_pat_flag);\n vector s_splited_pat_name;\n const int split_count = 2;\n s_splited_pat_name.resize(split_count);\n vector i_comment_line[split_count];\n\n ARRAY_LL ANA_TRM_CAP_PROG_DRV_WR_rtv(xNSitES);\n const int Wri_Bit_Length = 33;\n const int Wri_Bit_Position = 31;\n\n// static int N_OPT_VCO[xNSitES],\n static int ANA_TRM_CAP_PROG_DRV_WR[xNSitES];\n static double F_VCO_12[xNSitES];\n static double F_VCO_18[xNSitES];\n static double F_OPT_VCO[xNSitES];\n static int ANA_TRM_CAP_PROG_DRV_RD[xNSitES], N_ANA_TRM_CAP_PROG_DRV_RD_9_5[xNSitES], N_OPT_VCO_RD[xNSitES];\n\n string Mean_Port = \"Non_OSDO_ASDX_Port\";\n string Measure_Port = \"OSDO_Port\";\n static double sample_period_INT1;\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n GET_TESTSUITE_NAME(test_name);\n// ANA_TRM_CAP_PROG_DRV_WR_rtv.resize(xNSitES);\n\n// rdi.enableOre(oreFlag);\n// rdi.oreFile(\"./ORE_Files/rdi_ore_T11_20_VCO_CNT_REFERENCE_TRIMMING.xml\");\n\n if (split_pat_flag)\n {\n split_pattern(s_label_name,\"wri\",split_pat_flag,s_splited_pat_name);\n }\n else\n {\n for (int i = 0; i> 5;\n\n FuncPrint(\"ANA_TRM_CAP_PROG_DRV_RD\", ANA_TRM_CAP_PROG_DRV_RD[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"N_ANA_TRM_CAP_PROG_DRV_RD_9_5\", N_ANA_TRM_CAP_PROG_DRV_RD_9_5[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"N_OPT_VCO_RD\", N_OPT_VCO_RD[CURRENT_SITE_NUMBER()-1]);\n\n\n int Func_result0 = rdi.id(\"T11_20_VCO_reference_trimming_V2_PAT_id0\").getBurstPassFail();\n int Func_result1 = rdi.id(\"T11_20_VCO_reference_trimming_V2_PAT_id1\").getBurstPassFail();\n FuncPrint(\"Func_result0\", Func_result0);\n FuncPrint(\"Func_result1\", Func_result1);\n int Func_result = 1 * Func_result0 * Func_result1;\n if (N_OPT_VCO_RD[CURRENT_SITE_NUMBER()-1] != N_OPT_VCO[CURRENT_SITE_NUMBER()-1]) Func_result=99;\n FuncPrint(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n TestLog(\"F_VCO_12\", F_VCO_12[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"F_VCO_18\", F_VCO_18[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"N_OPT_VCO\", N_OPT_VCO[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"F_OPT_VCO\", F_OPT_VCO[CURRENT_SITE_NUMBER()-1]);\n // Auto_Code_Judge_and_log\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T11_20_VCO_reference_trimming_V2\", T11_20_VCO_reference_trimming_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: bai430aa_rel/1 $ $Author: hmf1rt $ $Date: 2024/08/15 06:39:49 GMT $')\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('DTB3',0x004b) # Route vco_clk to OSDO\ndly(100e-6)\ngaf('F_VCO', 'OSDO', f_range=10e6)\nlog('F_VCO')\nwac('DTB3',0x0000) # Disable DTB3X\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T11_21_VCO_reference_measurement_V1: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n static double F_VCO[xNSitES];\n // Auto_Code_Variable_define\n string Mean_Port = \"Non_OSDO_ASDX_Port\";\n string Measure_Port = \"OSDO_Port\";\n static double sample_period_INT1;\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n rdi.enableOre(oreFlag);\n rdi.oreFile(\"./ORE_Files/rdi_ore_T11_21_VCO_reference_measurement_V1.xml\");\n\n sample_period_INT1 = Primary.getSpecification().getSpecValue(\"per_ns@OSDO_Port\");\n\n rdi.dc().pin(\"VDDIO\").vForce(1.8 V).execute();\n Primary.getLevelSpec().change(\"VDDIO\",1.8);\n FLUSH(TM::APRM);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T11_21_VCO_reference_measurement_V1_PAT_id\");\n rdi.port(Mean_Port).func().label(s_label_name).stopVec(i_comment_line0[0]-1).execute();\n rdi.portSync();\n rdi.port(Measure_Port).digCap(\"T11_21_VCO_reference_measurement_V1_DigcapInsert_id\").pin(\"OSDO\").capMode(TA::PAR).samples(16384).bitPerWord(1).execute();\n rdi.portSync();\n rdi.port(Mean_Port).func().label(s_label_name).startVec(i_comment_line0[0]).execute();\n RDI_END();\n\n // Auto_Code_Execution_Part\n rdi.dc().pin(\"VDDIO\").vForce(3 V).execute();\n Primary.getLevelSpec().change(\"VDDIO\",3);\n FLUSH(TM::APRM);\n\n\n ON_FIRST_INVOCATION_END();\n // Auto_Code_Retrieve_Data\n \n int Func_result = rdi.id(\"T11_21_VCO_reference_measurement_V1_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n\n ARRAY_I vec = rdi.id(\"T11_21_VCO_reference_measurement_V1_DigcapInsert_id\").getVector(\"OSDO\");\n// cout << vec<< endl;\n F_VCO[CURRENT_SITE_NUMBER()-1] = d_Func_Calculate_Freq_ByFFT(vec,sample_period_INT1*1e-3) * 1e6;\n FuncPrint(\"F_VCO\", F_VCO[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"F_VCO\", F_VCO[CURRENT_SITE_NUMBER()-1]);\n // Auto_Code_Judge_and_log\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T11_21_VCO_reference_measurement_V1\", T11_21_VCO_reference_measurement_V1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description:\n# - set vco in all possible trim steps (gyr_trm_cap_prog_vco, not gyr_trm_res_prog_vco)\n# and measure the VCO center frequency (with GYR_TEST_EN.gyr_test_vco_en=1 (T01_20)\n# the input current is switched off).\n#############################################################################################################\ncmt('Version info: $Revision: 2 $ $Author: luz3sgh $ $Date: 2024/07/03 01:45:36 GMT $')\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('DTB1',0x004b) # Route vco_clk to INT1\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac(\"OCP_MASK\", 0x03e0) # activate bits 9..5\nras('REG_VALUE', 'ANA_TRM_CAP_PROG_DRV') # Store the current value\nfor n in range(32):\n cmt(f\"Set trim index to value {n} in range (0..31)\")\n wr(\"ANA_TRM_CAP_PROG_DRV\", n*32) # gyr_trm_cap_prog_vco\n rac(\"ANA_TRM_CAP_PROG_DRV\", n*32, 0x03e0) # Check register setting\n dly(100e-6)\n gaf(f\"F_VCO_DIV8_C_{n:02d}\", \"INT1\")\n log(f\"F_VCO_DIV8_C_{n:02d}\")\ndly(592e-9)\nwri('ANA_TRM_CAP_PROG_DRV','REG_VALUE') # write back the stored value\nwr(\"OCP_MASK\", 0x0000) # Reset masking register\nrac(\"OCP_MASK\", 0xffff) # Check masking register reset\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac(\"DTB1\", 0x0000) # Disable DTM\n", "output": "/*****************************************************\n * T11_22_VCO_Reference_Char_V2, description file version Notfound, avc file version Notfound\n * First Editor : jsh5sgh\n * Code generated with autocoding tool V2.9.1, in TOI2 standard way by module write_standard\n * Change History:\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T11_22_VCO_Reference_Char_V2: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 3;\n vector i_comment_line[i_split_count];\n\n ARRAY_I aI_Captured_0;\n static double F_VCO_DIV8_C[xNSitES][32];\n static int i_REG_VALUE[xNSitES];\n static int i_WRITE_BACK[xNSitES];\n static int i_vec_Num2[32] = {0};\n static int i_funcRes0[xNSitES], i_funcRes1[xNSitES], i_funcRes2[xNSitES];\n static double SAMPLE_PERIOD_US;\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(i_REG_VALUE, 9, xNSitES);\n //!\"CTmsg: cut pattern to 3 parts @ oriAVCvecline [1093, 7395]\n //!\"CTmsg: cut pattern to 3 parts @ binarypatline [1083, 7385]\n if (i_split_pat_flag)\n {\n \t split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n }\n else\n {\n \t split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n\t\t\t for(int i=0; i }\n valid comment[ 1] @ avcline 778: {ras('REG_VALUE', 'ANA_TRM_CAP_PROG_DRV')}\n valid comment[ 2] @ avcline 891: {cmt: Set trim index to value 0 in range (0..31)}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.digCap(\"digcapid_0\").label(s_splited_pat_name[0]).pin(\"SDO\").capMode(TA::SER).bitPerWord(16).samples(1*16).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n aI_Captured_0 = rdi.id(\"digcapid_0\").getVector(\"SDO\");\n aI_Captured_0[0] = Switch_High_Low_Bits_16Bits(aI_Captured_0[0]);\n i_REG_VALUE[curSite] = aI_Captured_0[0];\n FuncPrint(\"REG_VALUE\",i_REG_VALUE[curSite]);\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n\n /* Ori key coments in subpat1 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 1093: {gaf('F_VCO_DIV8_C_00', 'INT1', 2e+07, True)}\n valid comment[ 0] @ avcline 1093: {log('F_VCO_DIV8_C_00', '', '', 0, 0)}\n\n valid comment[ 1] @ avcline 1094: {cmt: Set trim index to value 1 in range (0..31)}\n valid comment[ 2] @ avcline 1296: {gaf('F_VCO_DIV8_C_01', 'INT1', 2e+07, True)}\n valid comment[ 2] @ avcline 1296: {log('F_VCO_DIV8_C_01', '', '', 0, 0)}\n\t\t ...\n valid comment[ 61] @ avcline 7184: {cmt: Set trim index to value 31 in range (0..31)}\n valid comment[ 62] @ avcline 7386: {gaf('F_VCO_DIV8_C_31', 'INT1', 2e+07, True)}\n valid comment[ 62] @ avcline 7386: {log('F_VCO_DIV8_C_31', '', '', 0, 0)}\n */\n\n Primary.timing(SPECIFICATION(\"SPI_STD_INT1_FREQ_MEAS\"));\n FLUSH(TM::APRM);\n SAMPLE_PERIOD_US = Primary.getSpecification().getSpecValue(\"per_ns@INT1_Port\") * 1e-03;\n FuncPrint(\"SAMPLE_PERIOD_US\", SAMPLE_PERIOD_US);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id1\");\n\t\t\t for(int i=0; i<31; i++)\n\t\t\t {\n\t\t\t\t rdi.port(\"INT1_Port\").digCap(\"vv_meas_code_\"+rdi.itos(i)).pin(\"INT1\").capMode(TA::SER).samples(4096).bitPerWord(1).execute();\n\t\t\t\t rdi.portSync();\n\t\t\t\t rdi.port(\"Non_INT1_Port\").func().label(s_splited_pat_name[1]).startVec(i_comment_line[1][2*i]).stopVec(i_comment_line[1][2*i+2]-1).execute();\n\t\t\t\t rdi.portSync();\n\t\t\t }\n\t\t\t rdi.port(\"INT1_Port\").digCap(\"vv_meas_code_\"+rdi.itos(31)).pin(\"INT1\").capMode(TA::SER).samples(4096).bitPerWord(1).execute();\n\t\t\t rdi.portSync();\n\t\t\t rdi.port(\"Non_INT1_Port\").func().label(s_splited_pat_name[1]).startVec(i_comment_line[1][62]).execute();\n\t\t\t rdi.portSync();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes1[curSite] = rdi.id(\"burst_id1\").getBurstPassFail();\n\t\t\t ARRAY_I ai_meas_code;\n\t\t\t for(int i=0; i<32; i++){\n\t\t\t\t ai_meas_code = rdi.id(\"vv_meas_code_\" + rdi.itos(i)).getVector();\n\t\t\t\t F_VCO_DIV8_C[curSite][i] = d_Func_Calculate_Freq_ByFFT(ai_meas_code, SAMPLE_PERIOD_US) *1e6;\n\t\t\t\t FuncPrint(\"F_VCO_DIV8_C_\"+rdi.itos(i), F_VCO_DIV8_C[curSite][i]);\n\t\t\t }\n FOR_EACH_SITE_END();\n\n\n /* Ori key coments in subpat2 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 7395: {wri('ANA_TRM_CAP_PROG_DRV', 'REG_VALUE')}\n valid comment[ 1] @ avcline 8050: {Test End: T11_22_VCO_Reference_Char}\n */\n Primary.timing(TIMING_SPEC(1,1));\n Primary.timing(1);\n FLUSH(TM::APRM);\n\n static int i_vec_iposition2[32] = {\n 31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,\n 48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63\n };\n for (int i = 0; i < 32; i++)\n {\n i_vec_Num2[i] = i_vec_iposition2[i];\n }\n FOR_EACH_SITE_BEGIN();\n i_WRITE_BACK[curSite] = Switch_High_Low_Bits_16Bits(i_REG_VALUE[curSite]);\n Func_Vector_Dynamic_Write(s_splited_pat_name[2], \"SDX\", i_vec_Num2, 32, i_WRITE_BACK[curSite], 0, 2); //Notes. TEI check per project\n\n FOR_EACH_SITE_END();\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id2\");\n rdi.func().label(s_splited_pat_name[2]).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes2[curSite] = rdi.id(\"burst_id2\").getBurstPassFail();\n FOR_EACH_SITE_END();\n }\n\n ON_FIRST_INVOCATION_END();\n\n\t for(int i=0; i<32; i++){\n\t\t TestLog(s_Func_Test_Name_Add_2Num(\"F_VCO_DIV8_C_\",i), F_VCO_DIV8_C[curSite][i]);\n\t }\n i_funcRes[curSite] = i_funcRes0[curSite] && i_funcRes1[curSite] && i_funcRes2[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T11_22_VCO_Reference_Char_V2\", T11_22_VCO_Reference_Char_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description:\n# - Enable GYR_CLK_POS_P on pad INT1 (to check frequency)\n# - frequency of 35kHz applied to ASCX/OCSB\n# - This frequency is routed through the test module to the signals GYR_D_TINP/N, which are applied\n# to the test inputs IN_TEST_P/_N on the GYRO DRIVE CV. It acts as the control frequency to the PLL, and latest\n# after 4ms the PLL is locked. Its frequency is routed to the INT1 output, and the (nearly constant)\n# phase voltage POUT_P/_N is switched to the signals POUT_P/_N_TM and routed through\n# the GYRO_CORE.GYRO_ANALOG_TESTMUX and (as GYR_TIO_P/_N) through the test_module to the pads ASCX/INT2.\n# On INT1 the same frequency as on ASCX is expected.\n# The frequency on ASCX/OCSB is varied around 35kHz (with respect to the tester paeriod of 296ns),\n# and the VCO voltage is logged.\n# The coefficient voltage/frequency can be measured, but what about the delta_phase/voltage ratio ??\n#############################################################################################################\ncmt('Version info: $Revision: bai430aa_rel/1 $ $Author: hmf1rt $ $Date: 2024/07/18 13:26:36 GMT $')\nwac('EXT_MODE', 0xc00f) # Switch to the TEST register page\nwac(\"DTB1\", 0x0030) # Enable GYR_CLK_POS_P on pad INT1\nwac('TM_CONF', 0x0003) # tm_se_meas=0 tm_bus_inv=0 tm_buf_pwrup=3 (tbuf_tb1_tb2_on)\n # bus_inv. because the power_ana_test_multiplexor_2 provides VSS_A/VDDA\nwac('TM_GYR', 0x0001) # tm_gyr_s_sel=0 tm_gyr_d_sel=1\n\nwac('TM_PIN', 0x1155) # tm_asdx_sel=2 (BUF2_OUT) tm_asdx_en=1 tm_int2_sel=2 (BUF1_OUT) tm_int2_en=1\n # tm_ascx_sel=0 (NC) tm_ascx_en=1 tm_ocsb_sel=0 (NC) tm_ocsb_en=1\n\t\t\t\t\t# enable ASCX/OCSB; otherwise VSS to the PAD\nwac('TM_ADDR', 0x0606) # tm_cfg=6 (GYR_TIOP/N= POUT_P/_N) tm_addr=6 (GYR_D_TIN; BUF1/2_INP= GYR_TIOP/N)\n # \nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac(\"GYR_TEST_EN\", 0x0000) # Disable VCO TM\nwac(\"GYR_TEST_EN\", 0x8000) # gyr_test_vco_en=0; gyr_test_cvs2atb_en=1, gyr_test_cvs2cvd_en=0\n # switches the external clock (ASCX/OCSB) to the GYRO DRIVE CV\nsav(\"OCSB\", 0.0)\ncmt(\"TOI: change the voltage on ASCX to 1.2V\")\nfor n in [95, 96, 97, 98, 99]:\n cmt('Apply a dig clock with a frequency of {:.3f} kHz and a high level'.format(1/(n*296e-6)))\n cmt(f'of V_IH = 1.20 V on pad ASCX; Vector period => {n}*296 ns = {n*296} ns')\n clk(\"ASCX\", 1/(n*4*74e-9)) # Apply clock on ASCX, from 35.56KHz to 34.124KHz\n dly(4.0e-3)\n gaf(f'F_VCO_K_{n}', \"INT1\")\n log(f'F_VCO_K_{n}')\n gav(f'V_VCO_K_P_RAW_{n}', \"INT2\")\n gav(f'V_VCO_K_N_RAW_{n}', \"ASDX\")\n calc(f'V_VCO_K_P_{n}', f'V_VCO_K_P_RAW_{n}', \"-\", \"V_OFF1_ECOFF\")\n calc(f'V_VCO_K_N_{n}', f'V_VCO_K_N_RAW_{n}', \"-\", \"V_OFF2_ECOFF\")\n calc(f'V_VCO_K_{n}', f'V_VCO_K_P_{n}', \"-\", f'V_VCO_K_N_{n}')\n log(f'V_VCO_K_{n}')\nwac('GYR_TEST_EN', 0x0004) # Enable VCO free-running frequency as in T01_20_switch_on_GYR_wo_drive\nuclk(\"ASCX\")\nuav(\"OCSB\")\nwac('EXT_MODE', 0xc00f) # Switch to the TEST register page\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\nwac('TM_GYR', 0x0000) # reset value\nwac(\"DTB1\", 0x0000) # Disable DTM\n\n# Data evaluation:\ncmt('Do data evaluation as below')\ncmt('F_VCO_MEAN = sum(F_VCO_K_{n})/5')\ncmt('V_VCO_MEAN = sum(V_VCO_K_{n})/5')\ncmt('R_VCO_K = sum((F_VCO_K_{n}-F_VCO_MEAN)*(V_VCO_K_{n}-V_VCO_MEAN))/sum((F_VCO_K_{n}-F_VCO_MEAN)^2)')\ncmt('RN_VCO_K = 1/R_VCO_K*192')\n\nlog('RN_VCO_K')\n", "output": "/*****************************************************\n * T11_23_VCO_K_Coefficient_Char_R1, description file version Notfound, avc file version Notfound\n * First Editor : jsh5sgh\n * Code generated with autocoding tool V2.9.1, in TOI2 standard way by module write_standard\n * Change History:\n * JSH5SGH R1: version update.\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T11_23_VCO_K_Coefficient_Char_R1: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n double SAMPLE_PERIOD_US;\n\nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 3;\n vector i_comment_line[i_split_count];\n static double sample_period_INT1;\n\n static double \tV_VCO_K_N_RAW[xNSitES][5], V_VCO_K_P_RAW[xNSitES][5];\n static double \tV_VCO_K_N[xNSitES][5], V_VCO_K_P[xNSitES][5];\n static double \tF_VCO_K[xNSitES][5], V_VCO_K[xNSitES][5];\n static double\t\tF_VCO_MEAN[xNSitES], V_VCO_MEAN[xNSitES], R_VCO_K[xNSitES], RN_VCO_K[xNSitES];\n static int \t\ti_funcRes0[xNSitES], i_funcRes10[xNSitES];\n static int \t\ti_funcRes1[xNSitES][5];\n const int \t\tindex[] = {95, 96, 97, 98, 99};\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n\n //!\"CTmsg: cut pattern to 11 parts @ oriAVCvecline [4019, 4020, 5723, 5724, 7957, 7958, 9673, 9674, 11865, 11866]\n //!\"CTmsg: cut pattern to 11 parts @ binarypatline [4009, 4010, 5713, 5714, 7947, 7948, 9663, 9664, 11855, 11856]\n if (i_split_pat_flag)\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n }\n else\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n for(int i=0; i }\n valid comment[ 1] @ avcline 1738: {sav('OCSB', 0, 2, 0.01, False, False)}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][1]).pin(\"OCSB\").vForce(0 V)//{sav('OCSB', 0, 2, 0.01, False, False)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n Primary.timing(SPECIFICATION(\"PLL_Lock\"));\n// Primary.getLevelSpec().change(\"ASCX\", 1.2);\n Primary.getLevelSpec().change(\"VDDIO\", 1.2, \"ASCX\");\n FLUSH(TM::APRM);\n sample_period_INT1 = Primary.getSpecification().getSpecValue(\"per_ns@INT1_Port\")/1000;\n\n for(int i=0; i<5; i++) {\n \t double period_ns = index[i] * 296.0 / 1000;\n Primary.getSpecification().change(\"per_ns@ASCX_Port\", period_ns);// 1000 cycles per clk 1/(28.172e-9*1e3)=34828.6\n \t\t RDI_BEGIN(mode);\n \t\t \t rdi.burstId(\"burst_id\"+rdi.itos(i+1));\n \t\t \t for (int j=0; j<3000; j++) // 34.829kHz, each cycle 28.712e-5 s = 288us, need 5ms more\n \t\t \t {\n \t\t \t\t rdi.port(\"ASCX_Port\").func().label(\"T11_23_VCO_K_Coefficient_Char_ASCX_CLK\").execute();\n \t\t \t }\n \t\t \t rdi.port(\"Non_INT1_ASCX_Port\").wait(4 ms);\n \t\t \t rdi.port(\"INT1_Port\").wait(4 ms);\n \t\t \t rdi.port(\"INT1_Port\").digCap(\"vv_F_VCO_K_\"+rdi.itos(index[i])).pin(\"INT1\").capMode(TA::PAR).samples(16384).bitPerWord(1).execute();// this freq should 33~36kHz, need increase the sampling period\n \t\t \t rdi.port(\"Non_INT1_ASCX_Port\").dc(\"dcid_\"+rdi.itos(i+1)).pin(\"INT2,ASDX\",TA::BADC).vMeas().average(128).measWait(1 ms).execute();\n \t\t RDI_END();\n\n\t\t\t FOR_EACH_SITE_BEGIN();\n\t\t\t \t i_funcRes1[curSite][i]= rdi.id(\"burst_id\"+rdi.itos(i+1)).getBurstPassFail();\n\t\t\t\t ARRAY_I ai_F_VCO_K;\n\t\t\t\t ai_F_VCO_K = rdi.id(\"vv_F_VCO_K_\"+rdi.itos(index[i])).getVector();\n\n\t\t\t\t F_VCO_K[curSite][i] = d_Func_Calculate_Freq_ByFFT(ai_F_VCO_K, sample_period_INT1)*1e6;\n\t\t\t\t FuncPrint(\"F_VCO_K_\"+rdi.itos(index[i]),F_VCO_K[curSite][i]);\n\n\t V_VCO_K_P_RAW[curSite][i] = rdi.id(\"dcid_\"+rdi.itos(i+1)).getValue(\"INT2\");\n\t FuncPrint(\"V_VCO_K_P_RAW_\"+rdi.itos(index[i]),\tV_VCO_K_P_RAW[curSite][i]);\n\t V_VCO_K_P[curSite][i] = V_VCO_K_P_RAW[curSite][i] - V_OFF1_ECOFF[curSite];\n\t FuncPrint(\"V_VCO_K_P_\"+rdi.itos(index[i]),\tV_VCO_K_P[curSite][i]);\n\n\t V_VCO_K_N_RAW[curSite][i] = rdi.id(\"dcid_\"+rdi.itos(i+1)).getValue(\"ASDX\");;\n\t FuncPrint(\"V_VCO_K_N_RAW_\"+rdi.itos(index[i]),\tV_VCO_K_N_RAW[curSite][i]);\n\t V_VCO_K_N[curSite][i] = V_VCO_K_N_RAW[curSite][i] - V_OFF2_ECOFF[curSite];\n\t FuncPrint(\"V_VCO_K_N_\"+rdi.itos(index[i]),\tV_VCO_K_N[curSite][i]);\n\n\t V_VCO_K[curSite][i] = V_VCO_K_P[curSite][i] - V_VCO_K_N[curSite][i];\n\t\t\t\t FuncPrint(\"V_VCO_K_\"+rdi.itos(index[i]),\tV_VCO_K[curSite][i]);\n\n\t\t\t FOR_EACH_SITE_END();\n }\n\n /* Ori key coments in subpat10 ~~~~~~~~~~~~~~\n valid comment[ 1] @ avcline 12059: {uav('OCSB', False)}\n valid comment[ 2] @ avcline 13211: {cmt: Do data evaluation as below}\n valid comment[ 2] @ avcline 13211: {cmt: F_VCO_MEAN = sum(F_VCO_K_{n}\n valid comment[ 2] @ avcline 13211: {cmt: V_VCO_MEAN = sum(V_VCO_K_{n}\n valid comment[ 2] @ avcline 13211: {cmt: R_VCO_K = sum((F_VCO_K_{n}\n valid comment[ 2] @ avcline 13211: {cmt: RN_VCO_K = 1/R_VCO_K*192}\n valid comment[ 2] @ avcline 13211: {log('RN_VCO_K', '', '', 0, 0)}\n valid comment[ 3] @ avcline 13212: {Test End: T11_23_VCO_K_Coefficient_Char}\n */\n Primary.timing(TIMING_SPEC(1,1));\n Primary.timing(1);\n Primary.getLevelSpec().restore();\n FLUSH(TM::APRM);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id10\");\n rdi.dc(\"dcid_10\").label(s_splited_pat_name[2])\n .insertSub(i_comment_line[2][1]).pin(\"OCSB\").relay(TA::ppmuRly_offALL)////{uav('OCSB', False)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes10[curSite] = rdi.id(\"burst_id10\").getBurstPassFail();\n double mean, sigma;\n DSP_MEAN(F_VCO_K[curSite], &mean, &sigma, 5);\n F_VCO_MEAN[curSite] = mean;\n\n DSP_MEAN(V_VCO_K[curSite], &mean, &sigma, 5);\n V_VCO_MEAN[curSite] = mean;\n\n double sum1=0, sum2=0;\n for(int i=0; i<5; i++) {\n \t sum1 += (F_VCO_K[curSite][i] - F_VCO_MEAN[curSite])*(V_VCO_K[curSite][i] - V_VCO_MEAN[curSite]);\n \t sum2 += pow((F_VCO_K[curSite][i] - F_VCO_MEAN[curSite]), 2);\n }\n R_VCO_K[curSite] =sum1/sum2;\n\t\t\t FuncPrint(\"R_VCO_K\",\tR_VCO_K[curSite]);\n\n RN_VCO_K[curSite] =1/R_VCO_K[curSite]*192; //todo double confirm the equation.\n\t\t\t FuncPrint(\"RN_VCO_K\",\tRN_VCO_K[curSite]);\n\n FOR_EACH_SITE_END();\n\n\n }\n\n ON_FIRST_INVOCATION_END();\n for(int i=0; i<5; i++) {\n\t\t TestLog(\"F_VCO_K_\"+rdi.itos(index[i]),F_VCO_K[curSite][i]);\n\t\t TestLog(\"V_VCO_K_\"+rdi.itos(index[i]),V_VCO_K[curSite][i]);\n }\n TestLog(\"RN_VCO_K\",\tRN_VCO_K[curSite]);\n\n i_funcRes[curSite] = i_funcRes0[curSite] && i_funcRes1[curSite][0] && i_funcRes1[curSite][1]\n && i_funcRes1[curSite][2] && i_funcRes1[curSite][3] && i_funcRes1[curSite][4]\n && i_funcRes10[curSite];\n\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T11_23_VCO_K_Coefficient_Char_R1\", T11_23_VCO_K_Coefficient_Char_R1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# - Get VCO trim value from VCO reference trimming\n# - Calculate cap_prog_q/p/r based on VCO trim value\n# - Write cap_prog_q/p/r to device\n#############################################################################################################\ncmt('Version info: $Revision: 1 $ $Author: hmf1rt $ $Date: 2024/03/13 13:36:52 GMT $')\n\ncalc('N_OPT_VCO', 0x11) # Assign placeholder value for simulation, REPLACE with trim value\n\ncmt('Get result parameter N_OPT_VCO from test item T11.20 and increase 3 LSB')\ncalc('N_OPT_P3', 'N_OPT_VCO', '+', 3) # Get N_OPT_VCO from test item T11.20 and add 3 LSB\ncmt('This test item is a functional fail if N_OPT_P3 > 31')\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('OCP_MASK', 0x7fff) # Set masking register\n# Calculate CAP_PROG_QPR trim value\ncalc('N_OPT_Q', 'N_OPT_P3', '<<', 10)\ncalc('N_OPT_P', 'N_OPT_P3', '<<', 5)\ncalc('N_OPT_R', 'N_OPT_P3')\ncalc('N_OPT_QP', 'N_OPT_Q', '+', 'N_OPT_P')\ncalc('N_OPT_QPR', 'N_OPT_QP', '+', 'N_OPT_R')\n# Write CAP_PROG_QPR to DUT\nwri('ANA_TRM_CAP_PROG0', 'N_OPT_QPR')\nras('N_OPT_QPR_RD','ANA_TRM_CAP_PROG0')\ncalc('N_OPT_QPR_RD_14_0', 'N_OPT_QPR_RD', '&', 0x7fff)\ncmt('The test item is a functional fail if N_OPT_QPR_RD_14_0 != N_OPT_QPR')\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T11_26_pre_trimming_of_QPR_integrators_V1: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n static int N_OPT_QPR_RD[xNSitES], N_OPT_P3[xNSitES], N_OPT_Q[xNSitES], N_OPT_P[xNSitES], N_OPT_R[xNSitES], N_OPT_QP[xNSitES], N_OPT_QPR[xNSitES], N_OPT_QPR_RD_14_0[xNSitES];\n // Auto_Code_Variable_define\n ARRAY_LL N_OPT_QPR_RD_rtv(xNSitES);\n const int Wri_Bit_Length = 33;\n const int Wri_Bit_Position = 415;\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n FOR_EACH_SITE_BEGIN();\n N_OPT_P3[CURRENT_SITE_NUMBER()-1] = N_OPT_VCO[CURRENT_SITE_NUMBER()-1] + 3;\n N_OPT_Q[CURRENT_SITE_NUMBER()-1] = N_OPT_P3[CURRENT_SITE_NUMBER()-1] << 10;\n N_OPT_P[CURRENT_SITE_NUMBER()-1] = N_OPT_P3[CURRENT_SITE_NUMBER()-1] << 5;\n N_OPT_R[CURRENT_SITE_NUMBER()-1] = N_OPT_P3[CURRENT_SITE_NUMBER()-1] ;\n N_OPT_QP[CURRENT_SITE_NUMBER()-1] = N_OPT_Q[CURRENT_SITE_NUMBER()-1] + N_OPT_P[CURRENT_SITE_NUMBER()-1];\n N_OPT_QPR[CURRENT_SITE_NUMBER()-1] = N_OPT_QP[CURRENT_SITE_NUMBER()-1] + N_OPT_R[CURRENT_SITE_NUMBER()-1];\n N_OPT_QPR_RD_rtv[CURRENT_SITE_NUMBER()-1] = extend_Pmode_Herschel(N_OPT_QPR[CURRENT_SITE_NUMBER()-1], 2);\n\n FuncPrint(\"N_OPT_VCO\", N_OPT_VCO[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"N_OPT_P3\", N_OPT_P3[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"N_OPT_Q\", N_OPT_Q[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"N_OPT_P\", N_OPT_P[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"N_OPT_R\", N_OPT_R[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"N_OPT_QP\", N_OPT_QP[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"N_OPT_QPR\", N_OPT_QPR[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"N_OPT_QPR_RD_rtv\", N_OPT_QPR_RD_rtv[CURRENT_SITE_NUMBER()-1]);\n\n\t FOR_EACH_SITE_END();\n\n\n rdi.runTimeVal(\"N_OPT_QPR_RD_rtv\", N_OPT_QPR_RD_rtv);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T11_26_pre_trimming_of_QPR_integrators_V1_PAT_id\");\n rdi.digCap(\"T11_26_pre_trimming_of_QPR_integrators_V1_Digcap_id\").vecVarOnly().pin(\"SDO\").capMode(TA::SER).samples(16*1).bitPerWord(16).execute();\n rdi.smartVec().label(s_label_name).pin(\"SDX\").writeData(\"N_OPT_QPR_RD_rtv\", Wri_Bit_Length, Wri_Bit_Position).execute();\n RDI_END();\n\n ON_FIRST_INVOCATION_END();\n\t\t ARRAY_I Vec=rdi.id(\"T11_26_pre_trimming_of_QPR_integrators_V1_Digcap_id\").getVector();\n\t\t N_OPT_QPR_RD[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[0]);\n\t\t N_OPT_QPR_RD_14_0[CURRENT_SITE_NUMBER()-1] = N_OPT_QPR_RD[CURRENT_SITE_NUMBER()-1] & 32767;\n\n\t\t FuncPrint(\"N_OPT_QPR_RD\", N_OPT_QPR_RD[CURRENT_SITE_NUMBER()-1]);\n\t\t FuncPrint(\"N_OPT_QPR_RD_14_0\", N_OPT_QPR_RD_14_0[CURRENT_SITE_NUMBER()-1]);\n\n//\n// N_OPT_VCO[CURRENT_SITE_NUMBER()-1] = 17 ;\n\n// // Auto_Code_Retrieve_Data\n//\n int Func_result = rdi.id(\"T11_26_pre_trimming_of_QPR_integrators_V1_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n if (N_OPT_QPR_RD_14_0[CURRENT_SITE_NUMBER()-1] != N_OPT_QPR[CURRENT_SITE_NUMBER()-1]) Func_result=99;\n if (N_OPT_P3[CURRENT_SITE_NUMBER()-1] >31) Func_result=10;\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n // Auto_Code_Judge_and_log\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T11_26_pre_trimming_of_QPR_integrators_V1\", T11_26_pre_trimming_of_QPR_integrators_V1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description:\n# - NVM bulk erase\n# - bulk program all ones\n# - margin read for all ones\n# - NVM bulk erase\n# - bulk program all zeroes\n# - margin read for all zeroes\n# - Notes: assume T02_14 executed \n#############################################################################################################\ncmt('Version info: $Revision: 3 $ $Author: luz3sgh $ $Date: 2024/04/22 08:17:02 GMT $')\nwac(\"EXT_MODE\", 0xc00d) # Enter pmu page\nwac(\"PMU_TEST_MISC\", 0x0004) # nvmotp_power_en to 1\ndly(200e-6)\nwac(\"EXT_MODE\", 0xc00f) # change to page f\nwac(\"NVM_TEST_CTRL\", 0x0002) # Enable IP \n# NVM bulk erase\nwac(\"NVM_WRITE_PROT_CTRL\", 0x0002) # Enable NVM program/erease\nwac(\"NVM_TEST\", 0x0018) # Enable NVM bulk erase/prog mode, tms=3\nwac(\"NVM_DIR_ADDR\", 0x0000) # Place all zeroes on direct address\nrac(\"NVM_DIR_STATUS\", 0x0001, 0x0003) # Check NVM ready/fail flag\nwr(\"NVM_DIR_CMD\", 0x0003) # Trigger NVM erase\nrac(\"NVM_DIR_STATUS\", 0x0000, 0x0003) # Check NVM busy/fail flag \ndly(5.8e-3)\nrac(\"NVM_DIR_STATUS\", 0x0001, 0x0003) # Check NVM ready/fail flag\n# bulk program all ones\nwac(\"NVM_DIR_DATA\", 0xffff) # Write all ones to nvm_data\nrac(\"NVM_DIR_STATUS\", 0x0001, 0x0003) # Check NVM ready/fail flag\nwr(\"NVM_DIR_CMD\", 0x0002) # Trigger NVM prog\nrac(\"NVM_DIR_STATUS\", 0x0000, 0x0003) # Check NVM busy/fail flag \ndly(5.8e-3)\nrac(\"NVM_DIR_STATUS\", 0x0001, 0x0003) # Check NVM ready/fail flag\n# margin read for all ones\nwac(\"NVM_WRITE_PROT_CTRL\", 0x0001) # Disable NVM program/erease\nwac(\"NVM_TEST\", 0x002d) # Enable NVM margin read test mode, tms=5,margin=5\nfor row in range(8):\n cmt(f\"Set NVM row address to {row} and run margin read for all ones\")\n wac(\"NVM_DIR_ADDR\", row) # Set NVM row address\n wac(\"NVM_DIR_DATA\", 0xffff) # Put expected pattern to DIN \n rac(\"NVM_DIR_STATUS\", 0x0001, 0x0003) # Check NVM ready/fail flag\n wr(\"NVM_DIR_CMD\", 0x0001) # Trigger NVM load\n rac(\"NVM_DIR_STATUS\", 0x0001, 0x0003) # Check NVM ready/fail flag\n rac(\"NVM_DIR_DATA\", 0xffff) # Read-back the loaded pattern on DOUT\nwac(\"NVM_WRITE_PROT_CTRL\", 0x0002) # Enable NVM program/erease\n# NVM bulk erase\nwac(\"NVM_TEST\", 0x0018) # Enable NVM bulk erase/prog mode, tms=3\nwac(\"NVM_DIR_ADDR\", 0x0000) # Place all zeroes on direct address\nrac(\"NVM_DIR_STATUS\", 0x0001, 0x0003) # Check NVM ready/fail flag\nwr(\"NVM_DIR_CMD\", 0x0003) # Trigger NVM erase\nrac(\"NVM_DIR_STATUS\", 0x0000, 0x0003) # Check NVM busy/fail flag \ndly(5.8e-3)\nrac(\"NVM_DIR_STATUS\", 0x0001, 0x0003) # Check NVM ready/fail flag\n# bulk program all zeroes\nwac(\"NVM_DIR_DATA\", 0x0000) # Write all zeroes to nvm_data\nrac(\"NVM_DIR_STATUS\", 0x0001, 0x0003) # Check NVM ready/fail flag\nwr(\"NVM_DIR_CMD\", 0x0002) # Trigger NVM prog\nrac(\"NVM_DIR_STATUS\", 0x0000, 0x0003) # Check NVM busy/fail flag \ndly(5.8e-3)\nrac(\"NVM_DIR_STATUS\", 0x0001, 0x0003) # Check NVM ready/fail flag\n# margin read for all zeroes\nwac(\"NVM_WRITE_PROT_CTRL\", 0x0001) # Disable NVM program/erease\nwac(\"NVM_TEST\", 0x002d) # Enable NVM margin read test mode, tms=5,margin=5\nfor row in range(8):\n cmt(f\"Set NVM row address to {row} and run margin read for all ones\")\n wac(\"NVM_DIR_ADDR\", row) # Set NVM row address\n wac(\"NVM_DIR_DATA\", 0x0000) # Put expected pattern to DIN\n rac(\"NVM_DIR_STATUS\", 0x0001, 0x0003) # Check NVM ready/fail flag\n wr(\"NVM_DIR_CMD\", 0x0001) # Trigger NVM load\n rac(\"NVM_DIR_STATUS\", 0x0001, 0x0003) # Check NVM ready/fail flag\n rac(\"NVM_DIR_DATA\", 0x0000) # Read-back the loaded pattern on DOUT\n# clean-up\nwac(\"NVM_DIR_ADDR\", 0x0000) # Reset NVM row address register\nwac(\"NVM_DIR_DATA\", 0x0000) # Reset NVM data register\nwac(\"NVM_TEST\", 0x0000) # Set NVM user mode\nwac(\"NVM_TEST_CTRL\", 0x0000) # Reset nvm_ip_always_en to 0\nwac(\"EXT_MODE\", 0xc00d) # Enter pmu page\nwac(\"PMU_TEST_MISC\", 0x0000) # nvmotp_power_en to 0\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T12_01_nvm_function_test_V3: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n // Auto_Code_Variable_define\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T12_01_nvm_function_test_V3_PAT_id\");\n rdi.func().label(s_label_name).execute();\n RDI_END();\n // Auto_Code_Execution_Part\n\n\n\n ON_FIRST_INVOCATION_END();\n // Auto_Code_Retrieve_Data\n \n int Func_result = rdi.id(\"T12_01_nvm_function_test_V3_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n // Auto_Code_Judge_and_log\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T12_01_nvm_function_test_V3\", T12_01_nvm_function_test_V3);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description:\n# Erase+ Program + Read with given address and data\n# - Notes: assume T02_14 executed \n#############################################################################################################\ncmt('Version info: $Revision: 4 $ $Author: luz3sgh $ $Date: 2024/04/22 08:35:27 GMT $')\ntable = [\n#| adr | data |\n#+-------+--------+\n (0x0003, 0x3333),\n (0x0004, 0xcccc),\n (0x0001, 0x0f0f), \n (0x0006, 0xf0f0), \n (0x0002, 0x8181),\n]\n\nwac(\"EXT_MODE\", 0xc00d) # Enter pmu page\nwac(\"PMU_TEST_MISC\", 0x0004) # nvmotp_power_en to 1\ndly(200e-6)\nsav(\"OCSB\", 0.96, v_range=2.0, i_comp=10e-3) # Set low voltage supply\ndly(100e-6)\nwac(\"EXT_MODE\", 0xc00f) # change to page f\nwac(\"NVM_TEST_CTRL\", 0x0002) # Enable IP \n# Erase + Program Decoder Validation\nwac(\"NVM_WRITE_PROT_CTRL\", 0x0002) # Enable NVM program/erease\nfor addr, data in table:\n cmt(f\"Set 0x{addr:02x}/0x{data:04x} for erase/prog data\")\n wac(\"NVM_DIR_ADDR\", addr) # Set ADDR\n rac(\"NVM_DIR_STATUS\", 0x0001, 0x0003) # Check NVM ready/fail flag\n wr(\"NVM_DIR_CMD\", 0x0003) # Trigger erase\n rac(\"NVM_DIR_STATUS\", 0x0000, 0x0003) # Check NVM busy/fail flag \n dly(5.8e-3)\n rac(\"NVM_DIR_STATUS\", 0x0001, 0x0003) # Check NVM ready/fail flag \n wac(\"NVM_DIR_DATA\", data) # Set DIN\n wr(\"NVM_DIR_CMD\", 0x0002) # Trigger prog\n rac(\"NVM_DIR_STATUS\", 0x0000, 0x0003) # Check NVM busy/fail flag \n dly(5.8e-3)\n rac(\"NVM_DIR_STATUS\", 0x0001, 0x0003) # Check NVM ready/fail flag\nwac(\"NVM_WRITE_PROT_CTRL\", 0x0001) # Restore pgm/erease protect\n# Read Decoder Validation\nfor addr, data in table:\n cmt(f\"read nvm add {addr} = 0x{data:04x}\")\n wac(\"NVM_DIR_ADDR\", addr) # Set row address\n rac(\"NVM_DIR_STATUS\", 0x0001, 0x0003) # Check NVM ready/fail flag\n wr(\"NVM_DIR_CMD\", 0x0001) # Trigger NVM load\n rac(\"NVM_DIR_STATUS\", 0x0001, 0x0003) # Check NVM ready/fail flag\n rac(\"NVM_DIR_DATA\", data) # Read-back the signature on DOUT\ndly(100e-6)\n# clean-up\nsav(\"OCSB\", 1.50, v_range=2.0, i_comp=10e-3) # Set typical voltage supply\ndly(100e-6)\nwac(\"NVM_DIR_ADDR\", 0x0000) # Reset NVM row address register\nwac(\"NVM_DIR_DATA\", 0x0000) # Reset NVM data register\nwac(\"NVM_TEST_CTRL\", 0x0000) # Reset nvm_ip_always_en to 0\nwac(\"EXT_MODE\", 0xc00d) # Enter pmu page\nwac(\"PMU_TEST_MISC\", 0x0000) # nvmotp_power_en to 0\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T12_03_nvm_lv_decoder_validation_V4: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n // Auto_Code_Variable_define\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T12_03_nvm_lv_decoder_validation_V4_PAT_id\");\n rdi.dc(\"T12_03_nvm_lv_decoder_validation_V4DC_id0\").label(s_label_name)\n .insertSub(i_comment_line0[0]).pin(\"OCSB\").vForce(0.96)\n .insertSub(i_comment_line0[1]).pin(\"OCSB\").vForce(1.5)\n .execute();\n RDI_END();\n\n // Auto_Code_Execution_Part\n\n\n\n ON_FIRST_INVOCATION_END();\n\n\n // Auto_Code_Retrieve_Data\n \n int Func_result = rdi.id(\"T12_03_nvm_lv_decoder_validation_V4_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n // Auto_Code_Judge_and_log\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T12_03_nvm_lv_decoder_validation_V4\", T12_03_nvm_lv_decoder_validation_V4);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description:\n# - NVM bulk erase -> all zeros\n# - bulk program even with 0x5555\n# - bulk program odd with 0xaaaa\n# - Notes: assume T02_16 executed \n#############################################################################################################\ncmt('Version info: $Revision: 2 $ $Author: hmf1rt $ $Date: 2024/04/19 13:34:47 GMT $')\nwac(\"EXT_MODE\", 0xc00d) # Enter pmu page\nwac(\"PMU_TEST_MISC\", 0x0004) # nvmotp_power_en to 1\ndly(200e-6)\nwac(\"EXT_MODE\", 0xc00f) # change to page f\nwac(\"NVM_TEST_CTRL\", 0x0002) # Enable IP \n# NVM bulk erase\nwac(\"NVM_WRITE_PROT_CTRL\", 0x0002) # Disable pgm/erase protect \nwac(\"NVM_TEST\", 0x0018) # Enable NVM bulk erase/prog, nvm_tms to 3\nwac(\"NVM_DIR_ADDR\", 0x0000) # Place all zeroes on address\nrac(\"NVM_DIR_STATUS\", 0x0001, 0x0003) # Check NVM is ready/fail flag\nwr(\"NVM_DIR_CMD\", 0x0003) # Trigger NVM erase\nrac(\"NVM_DIR_STATUS\", 0x0000, 0x0003) # Check NVM busy/fail flag \ndly(5.8e-3)\nrac(\"NVM_DIR_STATUS\", 0x0001, 0x0003) # Check NVM ready/fail flag\n# bulk program even\nwac(\"NVM_TEST\", 0x0008) # Enable NVM even bulk prog mode,nvm_tms to 1\nwac(\"NVM_DIR_ADDR\", 0x0000) # Select an even address\nwac(\"NVM_DIR_DATA\", 0x5555) # Place CKB pattern on DIN\nrac(\"NVM_DIR_STATUS\", 0x0001, 0x0003) # Check NVM is ready/fail flag\nwr(\"NVM_DIR_CMD\", 0x0002) # Trigger NVM prog, dir_cmd 2\nrac(\"NVM_DIR_STATUS\", 0x0000, 0x0003) # Check NVM busy/fail flag \ndly(5.8e-3)\nrac(\"NVM_DIR_STATUS\", 0x0001, 0x0003) # Check NVM ready/fail flag\n# bulk program odd\nwac(\"NVM_TEST\", 0x0010) # Enable NVM odd bulk prog mode, nvm_tms to 2\nwac(\"NVM_DIR_ADDR\", 0x0001) # Select an odd address\nwac(\"NVM_DIR_DATA\", 0xaaaa) # Place inverse CKB pattern on DIN\nrac(\"NVM_DIR_STATUS\", 0x0001, 0x0003) # Check NVM ready/fail flag\nwr(\"NVM_DIR_CMD\", 0x0002) # Trigger NVM prog, dir_cmd 2\nrac(\"NVM_DIR_STATUS\", 0x0000, 0x0003) # Check NVM busy/fail flag \ndly(5.8e-3)\nrac(\"NVM_DIR_STATUS\", 0x0001, 0x0003) # Check NVM ready/fail flag\nwac(\"NVM_WRITE_PROT_CTRL\",0x0001) # Enable program/write protect\n# clean-up\nwac(\"NVM_DIR_ADDR\", 0x0000) # Reset NVM row address register\nwac(\"NVM_DIR_DATA\", 0x0000) # Reset NVM data register\nwac(\"NVM_TEST\", 0x0000) # Set NVM user mode, nvm_tms to 0\nwac(\"NVM_TEST_CTRL\", 0x0000) # Disable ip_always_on; \nwac(\"EXT_MODE\", 0xc00d) # Switch to PMU register page\nwac(\"PMU_TEST_MISC\", 0x0000) # nvmotp_power_en to 0\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T12_05_nvm_write_ckb_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n // Auto_Code_Variable_define\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T12_05_nvm_write_ckb_V2_PAT_id\");\n rdi.func().label(s_label_name).execute();\n RDI_END();\n // Auto_Code_Execution_Part\n\n\n\n ON_FIRST_INVOCATION_END();\n // Auto_Code_Retrieve_Data\n \n int Func_result = rdi.id(\"T12_05_nvm_write_ckb_V2_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n // Auto_Code_Judge_and_log\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T12_05_nvm_write_ckb_V2\", T12_05_nvm_write_ckb_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description:\n# - read even nvm adress and compares\n# - read odd nvm adress and compares\n#############################################################################################################\ncmt('Version info: $Revision: 2 $ $Author: laj1mu23 $ $Date: 2024/03/25 21:11:14 GMT $')\nwac(\"EXT_MODE\", 0xc00d) # Enter pmu page\nwac(\"PMU_TEST_MISC\", 0x0004) # nvmotp_power_en to 1\ndly(200e-6)\nwac(\"EXT_MODE\", 0xc00f) # change to page f\nwac(\"NVM_TEST_CTRL\", 0x0002) # Enable IP \n# margin read\nwac(\"NVM_TEST\", 0x02d) # Enable NVM margin read test mode TMS=0x05, margin=5\nfor row in range(0, 8, 2): # Check the loop things\n cmt(f\"Set NVM row addr to {row} run margin read\")\n wac(\"NVM_DIR_ADDR\", row) # 3.Set NVM row address\n wac(\"NVM_DIR_DATA\", 0x5555) # 4.Set DIN\n rac(\"NVM_DIR_STATUS\", 0x0001, 0x0003) # Check NVM ready/fail flag\n wr(\"NVM_DIR_CMD\", 0x0001) # 5.Trigger NVM load\n rac(\"NVM_DIR_STATUS\", 0x0001, 0x0003) # 6.Check NVM ready/fail flag \n rac(\"NVM_DIR_DATA\", 0x5555) # 7.Read-back ckb\n row += 1\n cmt(f\"Set NVM row addr to {row} and run margin read\")\n wac(\"NVM_DIR_ADDR\", row) # Set NVM row address\n wac(\"NVM_DIR_DATA\", 0xaaaa) \n rac(\"NVM_DIR_STATUS\", 0x0001, 0x0003) # Check NVM ready/fail flag\n wr(\"NVM_DIR_CMD\", 0x0001) # Trigger NVM load\n rac(\"NVM_DIR_STATUS\", 0x0001, 0x0003) # Check NVM ready/fail flag \n rac(\"NVM_DIR_DATA\", 0xaaaa) # Read-back ckb\n# clean-up\nwac(\"NVM_DIR_ADDR\", 0x0000) # Reset NVM row address register\nwac(\"NVM_DIR_DATA\", 0x0000) # Reset NVM data register\nwac(\"NVM_TEST\", 0x0000) # Set NVM user mode, nvm_tms to 0\nwac(\"NVM_TEST_CTRL\", 0x0000) # Disable ip_always_on; \nwac(\"EXT_MODE\", 0xc00d) # Switch to PMU register page\nwac(\"PMU_TEST_MISC\", 0x0000) # nvmotp_power_en to 0\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T12_06_nvm_margin_read_ckb_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n // Auto_Code_Variable_define\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T12_06_nvm_margin_read_ckb_V2_PAT_id\");\n rdi.func().label(s_label_name).execute();\n RDI_END();\n // Auto_Code_Execution_Part\n\n\n\n ON_FIRST_INVOCATION_END();\n // Auto_Code_Retrieve_Data\n \n int Func_result = rdi.id(\"T12_06_nvm_margin_read_ckb_V2_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n // Auto_Code_Judge_and_log\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T12_06_nvm_margin_read_ckb_V2\", T12_06_nvm_margin_read_ckb_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description:\n# - read even nvm adress and compares\n# - read odd nvm adress and compares\n#############################################################################################################\ncmt('Version info: $Revision: 1 $ $Author: hmf1rt $ $Date: 2024/04/19 13:34:57 GMT $')\nwac(\"EXT_MODE\", 0xc00d) # Enter pmu page\nwac(\"PMU_TEST_MISC\", 0x0004) # nvmotp_power_en to 1\ndly(200e-6)\nwac(\"EXT_MODE\", 0xc00f) # change to page f\nwac(\"NVM_TEST_CTRL\", 0x0002) # Enable IP \n# margin read\nwac(\"NVM_TEST\", 0x02e) # Enable NVM margin read test mode TMS=0x05, margin=6\nfor row in range(0, 8, 2): # Check the loop things\n cmt(f\"Set NVM row addr to {row} run margin read\")\n wac(\"NVM_DIR_ADDR\", row) # 3.Set NVM row address\n wac(\"NVM_DIR_DATA\", 0x5555) # 4.Set DIN\n rac(\"NVM_DIR_STATUS\", 0x0001, 0x0003) # Check NVM ready/fail flag\n wr(\"NVM_DIR_CMD\", 0x0001) # 5.Trigger NVM load\n rac(\"NVM_DIR_STATUS\", 0x0001, 0x0003) # 6.Check NVM ready/fail flag \n rac(\"NVM_DIR_DATA\", 0x5555) # 7.Read-back ckb\n row += 1\n cmt(f\"Set NVM row addr to {row} and run margin read\")\n wac(\"NVM_DIR_ADDR\", row) # Set NVM row address\n wac(\"NVM_DIR_DATA\", 0xaaaa) \n rac(\"NVM_DIR_STATUS\", 0x0001, 0x0003) # Check NVM ready/fail flag\n wr(\"NVM_DIR_CMD\", 0x0001) # Trigger NVM load\n rac(\"NVM_DIR_STATUS\", 0x0001, 0x0003) # Check NVM ready/fail flag \n rac(\"NVM_DIR_DATA\", 0xaaaa) # Read-back ckb\n# clean-up\nwac(\"NVM_DIR_ADDR\", 0x0000) # Reset NVM row address register\nwac(\"NVM_DIR_DATA\", 0x0000) # Reset NVM data register\nwac(\"NVM_TEST\", 0x0000) # Set NVM user mode, nvm_tms to 0\nwac(\"NVM_TEST_CTRL\", 0x0000) # Disable ip_always_on; \nwac(\"EXT_MODE\", 0xc00d) # Switch to PMU register page\nwac(\"PMU_TEST_MISC\", 0x0000) # nvmotp_power_en to 0\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T12_07_nvm_margin_read_ckb_post_bake_V1: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n // Auto_Code_Variable_define\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T12_07_nvm_margin_read_ckb_post_bake_V1_PAT_id\");\n rdi.func().label(s_label_name).execute();\n RDI_END();\n // Auto_Code_Execution_Part\n\n\n\n ON_FIRST_INVOCATION_END();\n // Auto_Code_Retrieve_Data\n \n int Func_result = rdi.id(\"T12_07_nvm_margin_read_ckb_post_bake_V1_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n // Auto_Code_Judge_and_log\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T12_07_nvm_margin_read_ckb_post_bake_V1\", T12_07_nvm_margin_read_ckb_post_bake_V1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: \n# - NVM bulk erase\n# - Bulk program all zeroes\n# - Read for all zeroes\n# - Set row 0 to 0024h and 0001h, with boot erase+pgm+read\n# - Read and save parity error bit\n#############################################################################################################\ncmt('$Revision: bai430aa_rel/1 $ $Author: hmf1rt $ $Date: 2024/08/17 02:25:11 GMT $')\nwac('EXT_MODE', 0xc00d) # Switch to PMU register page\nwac('PMU_TEST_MISC', 0x0004) # nvmotp_power_en to 1\ndly(200e-6)\nwac('EXT_MODE', 0xc00f) # Switch to NVM/BOOT register page\nwac('NVM_TEST_CTRL', 0x0002) # Enable IP \n# NVM bulk erase\nwac('NVM_WRITE_PROT_CTRL', 0x0002) # Disable pgm/erase protect \nwac('NVM_TEST', 0x0018) # Enable NVM bulk erase/prog mode\nwac('NVM_DIR_ADDR', 0x0000) # Place all zeroes on direct address\nrac('NVM_DIR_STATUS', 0x0001, 0x0003) # Check NVM ready/fail flag\nwr('NVM_DIR_CMD', 0x0003) # Trigger NVM erase\nrac('NVM_DIR_STATUS', 0x0000, 0x0003) # Check NVM busy/fail flag \ndly(5.8e-3)\nrac('NVM_DIR_STATUS', 0x0001, 0x0003) # Check NVM ready/fail flag\n# bulk program all zeroes\nwac('NVM_DIR_DATA', 0x0000) # Write all zeroes to nvm_data\nrac('NVM_DIR_STATUS', 0x0001, 0x0003) # Check NVM ready/fail flag\nwr('NVM_DIR_CMD', 0x0002) # Trigger NVM prog\nrac('NVM_DIR_STATUS', 0x0000, 0x0003) # Check NVM busy/fail flag \ndly(5.8e-3)\nrac('NVM_DIR_STATUS', 0x0001, 0x0003) # Check NVM ready/fail flag\nwac('NVM_TEST',0x0000) # Exit bulk test mode\nwac('NVM_WRITE_PROT_CTRL', 0x0001) # Restore pgm/erase protect \n# read for all zeroes\nfor row in range(8):\n cmt(f'Set NVM row address to {row} and read for all zeroes')\n wac('NVM_DIR_ADDR', row) # Set NVM row address\n rac('NVM_DIR_STATUS', 0x0001, 0x0003) # Check NVM ready/fail flag\n wr('NVM_DIR_CMD', 0x0001) # Trigger NVM load, read should finish witin 520ns by datasheet\n rac('NVM_DIR_STATUS', 0x0001, 0x0003) # Check NVM ready/fail flag\n rac('NVM_DIR_DATA', 0x0000) # Read-back the loaded pattern on DOUT\n# Erase address pair 0x0 (=address 0x00 and 0x01)\nwac('NVM_WRITE_PROT_CTRL', 0x0002) # Enable NVM program/erease\nwac('NVM_DIR_ADDR', 0x0000) # Set NVM address to 0\nrac('NVM_DIR_STATUS', 0x0001, 0x0003) # Check NVM ready/fail flag\nwr('NVM_DIR_CMD', 0x0003) # Trigger NVM erase\nrac('NVM_DIR_STATUS', 0x0000, 0x0003) # Check NVM busy/fail flag \ndly(7.1e-3)\nrac('NVM_DIR_STATUS', 0x0001, 0x0003) # Check NVM ready/fail flag\n# Program\nwac('NVM_DIR_DATA', 0x0124) # Set NVM data to reset value for addr 0\nwr('NVM_DIR_CMD', 0x0002) # Trigger NVM Program\nrac('NVM_DIR_STATUS', 0x0000, 0x0003) # Check NVM busy/fail flag \ndly(7.1e-3)\nrac('NVM_DIR_STATUS', 0x0001, 0x0003) # Check NVM ready/fail flag\nwac('NVM_WRITE_PROT_CTRL', 0x0001) # Restore pgm/erease protect\nwac('NVM_DIR_DATA', 0x0000) # Clean NVM data register\n# Read\nwr('NVM_DIR_CMD', 0x0001) # Trigger NVM load\nrac('NVM_DIR_STATUS', 0x0001, 0x0003) # Check NVM ready/fail flag\nrac('NVM_DIR_DATA', 0x0124) # Check data loaded from NVM\n# clean-up\nwac('EXT_MODE', 0xc00f) # Switch to NVM/BOOT register page\nwac('NVM_DIR_DATA', 0x0000) # Reset NVM data register\nwac('NVM_DIR_ADDR', 0x0000) # Reset NVM row address register\nwac('NVM_TEST_CTRL', 0x0000) # Reset nvm_ip_always_en to 0\nwac('EXT_MODE', 0xc00d) # Enter pmu page\nwac('PMU_TEST_MISC', 0x0000) # nvmotp_power_en to 0\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T12_08_nvm_program_reset_values_V6: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n// static int BOOT_STATUS[xNSitES], BOOT_PARITY_ERROR_WLT[xNSitES];\n // Auto_Code_Variable_define\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T12_08_nvm_program_reset_values_PAT_id\");\n rdi.func().label(s_label_name).execute();\n RDI_END();\n\n ON_FIRST_INVOCATION_END();\n \n int Func_result = rdi.id(\"T12_08_nvm_program_reset_values_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n// TestLog(\"BOOT_PARITY_ERROR_WLT\", BOOT_PARITY_ERROR_WLT[CURRENT_SITE_NUMBER()-1]);\n // Auto_Code_Judge_and_log\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T12_08_nvm_program_reset_values_V6\", T12_08_nvm_program_reset_values_V6);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description:\n# - Measure leak current on VDDA\n# - Enable NVM\n# - Supply current measure\n#############################################################################################################\ncmt('Version info: $Revision: 2 $ $Author: hmf1rt $ $Date: 2024/04/19 13:01:00 GMT $')\nuclk('ASCX')\nbw('ASCX', 1)\ndly(1352*74e-9) # Delay ~100us\ngac(\"I_VDDA_LEAK\", \"OCSB\", i_range=2e-6)\nubw('ASCX')\nclk('ASCX', 1/148e-9)\n# Enable IP\nwac(\"EXT_MODE\", 0xc00d) # Enter pmu page\nwac('OCP_MASK', 0x0018) # bit3, nvmopt_owr_en\nwr (\"PMU_TEST_MISC\", 0x0018) # bit4, owr_nvm_pwrup\nrac(\"PMU_TEST_MISC\", 0x0018, 0x0018) \nwr ('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac(\"EXT_MODE\", 0xc00f) # change to page f\nwac(\"NVM_TEST_CTRL\", 0x0002) # nvm_ip_always_en \n# Enter User mode\nwac(\"NVM_TEST\",0x0000)\nuclk('ASCX')\nbw('ASCX', 1)\ndly(2704*74e-9) # Delay ~200us\ngac(\"I_NVM_LEAK\", \"OCSB\", i_range=2e-6)\ncalc(\"I_NVM_SUPPLY\", \"I_NVM_LEAK\", \"-\", \"I_VDDA_LEAK\")\nlog(\"I_VDDA_LEAK\")\nlog(\"I_NVM_SUPPLY\")\nubw('ASCX')\nclk('ASCX', 1/148e-9)\n# cleanup\nwac(\"NVM_TEST_CTRL\", 0x0000) # Disable IP control overwrite\nwac(\"EXT_MODE\", 0xc00d) # Enter pmu page\nwac(\"EXT_MODE\", 0xc00d) # Enter pmu page\nwac('OCP_MASK', 0x0018) # bit3, nvmopt_owr_en\nwr (\"PMU_TEST_MISC\", 0x0000) # bit4, owr_nvm_pwrup\nrac(\"PMU_TEST_MISC\", 0x0000, 0x0018) \nwr ('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T12_10_nvm_supply_current_test_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n static double I_VDDA_LEAK[xNSitES];\n static double I_NVM_LEAK[xNSitES], I_NVM_SUPPLY[xNSitES];\n // Auto_Code_Variable_define\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n\t rdi.enableOre(oreFlag);\n\t rdi.oreFile(\"./ORE_Files/rdi_ore_T12_10_NVM_SUPPLY_CURRENT_TEST.xml\");\n\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T12_10_nvm_supply_current_test_V2_PAT_id\");\n rdi.dc(\"T12_10_nvm_supply_current_test_V2DC_id0\").label(s_label_name)\n .insertSub(i_comment_line0[0]).pin(\"OCSB\").vForce(1.5 V).iMeas().valueMode(TA::BADC).iRange(10e-06 A).average(16).measWait(10 ms) //I_VDDA_LEAK\n .insertSub(i_comment_line0[0]).pin(\"OCSB\").vForce(1.5 V).iRange(40 mA)\n .insertSub(i_comment_line0[1]).pin(\"OCSB\").vForce(1.5 V).iMeas().valueMode(TA::BADC).iRange(2e-06 A).average(16).measWait(10 ms) //I_NVM_LEAK\n .insertSub(i_comment_line0[1]).pin(\"OCSB\").vForce(1.5 V).iRange(40 mA)\n .execute();\n RDI_END();\n\n // Auto_Code_Execution_Part\n\n// rdi.func().label(\"T12_11_nvm_oscillator_measurement_V2_AVC2_PY2\").execute();\n\n ON_FIRST_INVOCATION_END();\n ARRAY_D JSUB_results_OCSB;\n JSUB_results_OCSB = rdi.id(\"T12_10_nvm_supply_current_test_V2DC_id0\").getMultiValue(\"OCSB\");\n I_VDDA_LEAK[CURRENT_SITE_NUMBER()-1] = JSUB_results_OCSB[0];\n I_NVM_LEAK[CURRENT_SITE_NUMBER()-1] = JSUB_results_OCSB[1];\n\n I_NVM_SUPPLY[CURRENT_SITE_NUMBER()-1] = I_NVM_LEAK[CURRENT_SITE_NUMBER()-1] - I_VDDA_LEAK[CURRENT_SITE_NUMBER()-1];\n FuncPrint(\"I_NVM_LEAK\", I_NVM_LEAK[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"I_VDDA_LEAK\", I_VDDA_LEAK[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"I_NVM_SUPPLY\", I_NVM_SUPPLY[CURRENT_SITE_NUMBER()-1]);\n // Auto_Code_Retrieve_Data\n \n int Func_result = rdi.id(\"T12_10_nvm_supply_current_test_V2_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"I_VDDA_LEAK\", I_VDDA_LEAK[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"I_NVM_SUPPLY\", I_NVM_SUPPLY[CURRENT_SITE_NUMBER()-1]);\n // Auto_Code_Judge_and_log\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T12_10_nvm_supply_current_test_V2\", T12_10_nvm_supply_current_test_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description:\n# - Powerup and enable NVM IP\n# - Select NVM_TMS 6\n# - Route NVM_TM1 to ASDX\n# - Measure NVM_OSC\n# - Notes: assume T02_14 executed \n#############################################################################################################\ncmt('Version info: $Revision: 2 $ $Author: hmf1rt $ $Date: 2024/04/19 13:01:00 GMT $')\n# Power up NVM & enable always on\nwac(\"EXT_MODE\", 0xc00d) # Enter pmu page\nwac(\"PMU_TEST_MISC\", 0x0004) # nvmotp_power_en to 1\ndly(200e-6)\nwac(\"EXT_MODE\", 0xc00f) # Enter TEST page..NVMCTRL..in extended mode\nwac(\"NVM_TEST_CTRL\", 0x0002) # nvm_ip_always_en\n# TMS set to 6, and rout osc to DTB3\nwac(\"NVM_TEST\", 0x0030) # nvm_tms to 6\nwac(\"DTB3\", 0x0021) # NVM_TM1 to DTB3-test_out2,ASDX\nuclk('ASCX')\nbw('ASCX', 1)\ndly(1352*74e-9) # Delay ~100us\ngaf(\"F_NVM_OSC\",\"ASDX\", f_range=5e6)\nlog(\"F_NVM_OSC\")\nubw('ASCX')\nclk('ASCX', 1/148e-9)\n# clean-up\nwac(\"DTB3\", 0x0000) \nwac(\"NVM_TEST\", 0x0000) \nwac(\"NVM_TEST_CTRL\", 0x0000) # Disable IP\nwac(\"EXT_MODE\", 0xc00d)\nwac(\"PMU_TEST_MISC\", 0x0000) # nvmotp_power_en to 0\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T12_11_nvm_oscillator_measurement_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n static double F_NVM_OSC[xNSitES];\n static double sample_period_ASDX;\n // Auto_Code_Variable_define\n\n string Mean_Port = \"Non_ASDX_Port\";\n string Measure_Port = \"ASDX_Port\";\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n\t rdi.enableOre(oreFlag);\n\t rdi.oreFile(\"./ORE_Files/rdi_ore_T12_11_NVM_OSCILLATOR_MEASUREMENT.xml\");\n\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n sample_period_ASDX = Primary.getSpecification().getSpecValue(\"per_ns@ASDX_Port\");\n\n FuncPrint(\"sample_period_ASDX\", sample_period_ASDX);\n\n// rdi.util().pin(\"K1_K2\").setOff().execute();\n rdi.dc().pin(\"VDDIO\").vForce(1.8 V).execute();\n Primary.getLevelSpec().change(\"VDDIO\",1.8);\n FLUSH(TM::APRM);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T12_11_nvm_oscillator_measurement_V2_PAT_id\");\n// rdi.port(Mean_Port).func().label(s_label_name).stopVec(582).execute();\n rdi.port(Mean_Port).func().label(s_label_name).stopVec(i_comment_line0[0]-1).execute();\n rdi.portSync();\n rdi.port(Measure_Port).digCap(\"T12_11_nvm_oscillator_measurement_V2_DigcapInsert_id\").pin(\"ASDX\").capMode(TA::PAR).samples(1024).bitPerWord(1).execute();\n rdi.portSync();\n rdi.port(Mean_Port).func().label(s_label_name).startVec(i_comment_line0[0]).execute();\n RDI_END();\n\n // Auto_Code_Execution_Part\n\n// rdi.util().pin(\"K1_K2\").setOn().execute();\n rdi.dc().pin(\"VDDIO\").vForce(3 V).execute();\n Primary.getLevelSpec().change(\"VDDIO\",3);\n FLUSH(TM::APRM);\n\n ON_FIRST_INVOCATION_END();\n // Auto_Code_Retrieve_Data\n \n int Func_result = rdi.id(\"T12_11_nvm_oscillator_measurement_V2_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n\n ARRAY_I vec = rdi.id(\"T12_11_nvm_oscillator_measurement_V2_DigcapInsert_id\").getVector(\"ASDX\");\n F_NVM_OSC[CURRENT_SITE_NUMBER()-1] = d_Func_Calculate_Freq_ByFFT(vec,sample_period_ASDX*1e-3)*1e6;\n FuncPrint(\"F_NVM_OSC\", F_NVM_OSC[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"F_NVM_OSC\", F_NVM_OSC[CURRENT_SITE_NUMBER()-1]);\n // Auto_Code_Judge_and_log\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T12_11_nvm_oscillator_measurement_V2\", T12_11_nvm_oscillator_measurement_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description:\n# Run with exteranl power supply\n#############################################################################################################\ncmt('Version info: $Revision: 1 $ $Author: hmf1rt $ $Date: 2024/03/13 13:36:52 GMT $')\nsupply = [\n#| VDDA | VDDD_DC |\n#+---------+---------+\n ( 1.35, 1.05 ), # n = 0; min supply\n ( 1.55, 1.20 ), # n = 1; max supply\n ( 1.55, 1.05 ) # n = 2; supply skew\n]\n\nwac('EXT_MODE', 0xc00d) # Switch to PMU register page\nwcb('nvmotp_power_en',0x1) \ndly(300e-6)\nwac('EXT_MODE', 0xc00f) # Switch to OTPCTRL register page\nfor n in range(0, 3, 1):\n sav('OCSB', supply[n][0])\n sav('INT1', supply[n][1])\n dly(100e-6)\n for i in range(0, 256, 1):\n wac('OTP_ADDR', i) # Set OTP address\n rac('OTP_STATUS', 0x0001) # Check OTP ready flag\n wr('OTP_CMD', 0x0001) # Trigger OTP read\n rac('OTP_DATA', 0x0000) # Check OTP read result\nwac('OTP_ADDR', 0x0000) # Reset OTP address\nsav('OCSB', 1.5)\nsav('INT1', 1.1) \ndly(100e-6)\nwac('EXT_MODE', 0xc00d) # Switch to PMU register page\nwcb('nvmotp_owr_en', 0x0) # Disable OTP power\ndly(100e-6)\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T13_04_otp_blank_read_V1: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n double d_V_INT1, d_V_OCSB;\n // Auto_Code_Variable_define\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n d_V_INT1 = Primary.getLevelSpec().getSpecValue(\"INT1\");\n d_V_OCSB = Primary.getLevelSpec().getSpecValue(\"OCSB\");\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T13_04_otp_blank_read_V1_PAT_id\");\n rdi.dc(\"T13_04_otp_blank_read_V1DC_id0\").label(s_label_name)\n .insertSub(i_comment_line0[0]).pin(\"OCSB\").vForce(1.35).iRange(40 mA)\n .insertSub(i_comment_line0[0]).pin(\"INT1\").vForce(1.05).iRange(40 mA)\n .insertSub(i_comment_line0[1]).pin(\"OCSB\").vForce(1.55)\n .insertSub(i_comment_line0[1]).pin(\"INT1\").vForce(1.2)\n .insertSub(i_comment_line0[2]).pin(\"OCSB\").vForce(1.55)\n .insertSub(i_comment_line0[2]).pin(\"INT1\").vForce(1.05)\n .insertSub(i_comment_line0[3]).pin(\"OCSB\").vForce(d_V_OCSB)\n .insertSub(i_comment_line0[3]).pin(\"INT1\").vForce(d_V_INT1)\n .execute();\n RDI_END();\n\n // Auto_Code_Execution_Part\n\n\n\n ON_FIRST_INVOCATION_END();\n\n\n // Auto_Code_Retrieve_Data\n \n int Func_result = rdi.id(\"T13_04_otp_blank_read_V1_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n // Auto_Code_Judge_and_log\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T13_04_otp_blank_read_V1\", T13_04_otp_blank_read_V1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description:\n# Run with interanl power supply\n# Notes: set otp_cmd to 1 will trig pwr_status_otp change\n#############################################################################################################\ncmt('Version info: $Revision: 1 $ $Author: hmf1rt $ $Date: 2024/03/13 13:36:52 GMT $')\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwcb('nvmotp_power_en',0x1) # either use interanl ldo\ndly(300e-6) # 160+us pwr_status_otp to 3\nwac('EXT_MODE', 0xc00f) # Switch to OTPCTRL register page\nfor margin in [0x1, 0x2]: # 1 REFP,bigger refer, 2 REFM samller ref\n wcb('mr',margin) #OTP_TEST_CFG\n for n in range(0, 256, 1): \n wac('OTP_ADDR', n) # Set OTP address\n rac('OTP_STATUS', 0x0001) # Check OTP ready flag\n wr('OTP_CMD', 0x0001) # Trigger OTP read\n rac('OTP_DATA', 0x0000) # Check OTP read result\nwcb('otp_word_addr', 0x0000) # Reset OTP address\nwcb('mr', 0x0) # Reset margin mode\n# Clean\nwac('EXT_MODE', 0xc00d) # Switch to PMU register page\nwcb('nvmotp_power_en', 0x0) # Disable OTP power\ndly(100e-6)\n", "output": "/*****************************************************\n * T13_05_otp_blank_margin_read_V1, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T13_05_otp_blank_margin_read_V1: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static int i_funcRes0[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T13_05_otp_blank_margin_read}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 1] @ avcline 257169: {Test End: T13_05_otp_blank_margin_read}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.func().label(s_splited_pat_name[0]).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n FuncPrint(\"i_funcRes0\", i_funcRes0[curSite]);\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n\n ON_FIRST_INVOCATION_END();\n\n i_funcRes[curSite] = i_funcRes0[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T13_05_otp_blank_margin_read_V1\", T13_05_otp_blank_margin_read_V1);" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description:\n# Run with interanl power supply, vddp to external VDD pad\n#############################################################################################################\ncmt('Version info: $Revision: 1 $ $Author: hmf1rt $ $Date: 2024/03/13 13:36:52 GMT $')\nwac('EXT_MODE', 0xc00d) # Switch to PMU register page\nwcb('nvmotp_power_en', 0x1) # Enable OTP power\ndly(300e-6)\nwac('EXT_MODE', 0xc00f) # Switch to OTPCTRL register page\nwcb('twlb', 0x3) # Turn on the redundant row\n# Read unprogrammed information row\nwac('OTP_ADDR', 0x0000) # Set OTP inf row address to 0\nrac('OTP_STATUS', 0x0001) # Check OTP ready flag\nwr('OTP_CMD', 0x0001) \t # Trigger OTP direct read\nrac('OTP_DATA', 0x0000) # Check OTP read result\n# Program reseved bytes in information row\nwcb('otp_prog_en', 0x1) # Enable OTP program\nwcb('vddp_sw',0x1) # connect VDDP to external supply VDD\ndly(100e-6) \nsav('VDD', 3.6, v_range=4.0, i_comp=40e-3)\ndly(1e-3) \nwcb('otp_data', 0xffff) # Set prog data to all ones\nrcb('otp_cmd_rdy', 0x1) # Check OTP is ready\nwrb('otp_cmd', 0x4) # Trigger OTP direct program\ndly(300e-6)\nrcb('otp_cmd_rdy', 0x1) # Check OTP back to ready status\nsav('VDD', 1.8, v_range=4.0, i_comp=10e-3)\ndly(1e-3)\nwcb('vddp_sw',0x0) # VDDP connect to interanl supply VDDDC \nwcb('otp_prog_en', 0x0) # Disable OTP program\n# Read and check data in information row\nfor margin in [0x0, 0x1, 0x2]: \n wcb('mr', margin) # Set margin mode\n rac('OTP_STATUS', 0x0001) # Check OTP ready flag\n wr('OTP_CMD', 0x0001) \t # Trigger OTP direct read\n rac('OTP_DATA', 0xffff) # Check OTP read result\n# Clean-up\nwcb('twlb', 0x0) # Turn on main array; \nwcb('mr', 0x0) # disable margin TM \nwcb('otp_word_addr', 0x0000) # Reset OTP address\nwac('EXT_MODE', 0xc00d) # Switch to PMU register page\nwcb('nvmotp_power_en', 0x0000) # Disable OTP power\n", "output": "/*****************************************************\n * T13_06_otp_prog_cells_margin_read_V1, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T13_06_otp_prog_cells_margin_read_V1: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static int i_funcRes0[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][1]).pin(\"VDD\").vForce(3.6 V).iRange(40 mA)//{sav('VDD', 3.6, 4, 0.04, False, False)}\n .insertSub(i_comment_line[0][2]).pin(\"VDD\").vForce(1.8 V).iRange(40 mA)//{sav('VDD', 1.8, 4, 0.01, False, False)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n//rdi.func().label(\"T04_06_i2c_delay_trimming_V3_AVC3_PY3\").execute();\n ON_FIRST_INVOCATION_END();\n\n i_funcRes[curSite] = i_funcRes0[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T13_06_otp_prog_cells_margin_read_V1\", T13_06_otp_prog_cells_margin_read_V1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: Measure suspend current\n# - Entry condition STC_ACC\n# - Power up OTP Only\n# - Boot OPT contents to Shadow\n#############################################################################################################\ncmt('Version info: $Revision: 2 $ $Author: luz3sgh $ $Date: 2024/06/03 06:30:18 GMT $')\nwac('EXT_MODE', 0xc00f) # Switch to OTPCTRL page\nwac('OCP_MASK', 0x000c)\t\t\t\t# Set masking register\nwr ('OTP_TEST_CFG', 0x0004)\t\t\t# Set margin mode, REFP, bigger reference value(ref+)\nrac('OTP_TEST_CFG', 0x0004, 0x000c)\t # Check register setting\nwr ('OCP_MASK', 0x0000)\t\t\t\t# Reset masking register\nrac('OCP_MASK', 0xffff)\t\t\t\t# Check masking register reset\n# Power on OTP\nwac('EXT_MODE', 0xc00d)\t\t\t\t# Switch to PMU page\nwac('OCP_MASK', 0x0004)\t\t\t\t# Set masking register\nwr ('PMU_TEST_MISC', 0x0004) # bit2, nvmotp_power_en\nrac('PMU_TEST_MISC', 0x0004, 0x0004)\t # Enable OTP power\nwr ('OCP_MASK', 0x0000)\t\t\t\t# Reset masking register\nrac('OCP_MASK', 0xffff)\t\t\t\t# Check masking register reset\ndly(300e-6)\n# Boot OTP to shadow \nwac('EXT_MODE', 0xc00f) # Switch to BOOT register page\nwac('BOOT_RANGE', 0xff00) # Default value, start & stop range to max,\nrac('BOOT_STATUS', 0x0001) # Check boot commmand status\nwr('BOOT_CMD', 0x0001) # Trigger boot full otp\ndly(1.2e-3) \nrac('BOOT_STATUS', 0x0001) # Check boot commmand status\n# Clean-up \nwac('EXT_MODE', 0xc00f) # Switch to OTPCTRL page\nwac('OCP_MASK', 0x000c)\t\t\t\t# Set masking register\nwr ('OTP_TEST_CFG', 0x0000)\t\t\t# Deafult mr is 0, REF\nrac('OTP_TEST_CFG', 0x0000, 0x000c)\t # Check register setting\nwr ('OCP_MASK', 0x0000)\t\t\t\t# Reset masking register\nrac('OCP_MASK', 0xffff)\t\t\t\t# Check masking register reset\n\nwac('EXT_MODE', 0xc00d)\t\t\t\t# Switch to PMU page\nwac('OCP_MASK', 0x0004)\t\t\t\t# Set masking register\nwr ('PMU_TEST_MISC', 0x0000) # bit2, nvmotp_power_en\nrac('PMU_TEST_MISC', 0x0000, 0x0004)\t # Enable OTP power\nwr ('OCP_MASK', 0x0000)\t\t\t\t# Reset masking register\nrac('OCP_MASK', 0xffff)\t\t\t\t# Check masking register reset\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T13_08_OTP_Margin_Boot_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n // Auto_Code_Variable_define\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n// i_comment_line0 = search_comment_line(s_label_name);\n// print_key_comment(s_label_name, i_comment_line0, printFlag);\n//\n RDI_BEGIN(mode);\n rdi.burstId(\"T13_08_OTP_Margin_Boot_V2_PAT_id\");\n rdi.func().label(s_label_name).execute();\n RDI_END();\n// // Auto_Code_Execution_Part\n//\n//\n//\n// }\n ON_FIRST_INVOCATION_END();\n // Auto_Code_Retrieve_Data\n \n int Func_result = rdi.id(\"T13_08_OTP_Margin_Boot_V2_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n // Auto_Code_Judge_and_log\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T13_08_OTP_Margin_Boot_V2\", T13_08_OTP_Margin_Boot_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: Low volt con-current test\n# Run with exteranl power supply\n# Run with external clock <5MHz\n#############################################################################################################\ncmt('Version info: $Revision: 2 $ $Author: hmf1rt $ $Date: 2024/04/24 11:23:05 GMT $')\ncmt('Execute this pattern with spi_slow DVC timing file')\nsav('INT1', 1.00) # Set VDDD_DC = OTP_VDD to 1V\nsav('OCSB', 1.05) # Set VDDA = VDDP to 1.05V\ndly(100e-6) \nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwcb('nvmotp_power_en',0x1) # Enable OTP power\ndly(300e-6) \nwac('EXT_MODE', 0xc00f) # Switch to OTPCTRL register page\nwcb('sap',0x0) # Set OTP_TEST_CFG.sap to 0\nwcb('clvwr_en',0x1) # Enable CLVWR test mode \nfor n in range(0, 255, 1):\n wr('OTP_ADDR', n) # Set OTP address\n for i in range(0, 16, 1):\n wr('OTP_TEST_CLVWR', i) # Set bit address for CLVWR mode \n rac('OTP_DATA', 2**i) # Check OTP read result\n# Clean\nwcb('sap', 0x2) # Set SAP back to default value 2; \nwcb('clvwr_en',0x0) # Disable CLVWR test mode\nwcb('otp_word_addr', 0x0000) # Reset OTP address\nwcb('clvwr_bit_addr', 0x0000) # Reset CLVWR bit address\nwrb('otp_data', 0x0000) # Reset OTP data\nwac('EXT_MODE', 0xc00d) # Switch to PMU register page\nwcb('nvmotp_power_en',0x0) # Disable OTP power \ndly(100e-6)\nsav('INT1', 1.10) # Set VDDD_DC to default suppy\nsav('OCSB', 1.50) # Set VDDA to default supply\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T13_14_otp_clvwr_test_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n // Auto_Code_Variable_define\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T13_14_otp_clvwr_test_V2_PAT_id\");\n rdi.dc(\"T13_14_otp_clvwr_test_V2DC_id0\").label(s_label_name)\n// .insertSub(i_comment_line0[0]).pin(\"INT1\").vForce(1.05)\n// .insertSub(i_comment_line0[0]).wait(0.1 ms)\n .insertSub(i_comment_line0[0]).pin(\"INT1\").vForce(1.0)\n .insertSub(i_comment_line0[0]).pin(\"OCSB\").vForce(1.05)\n .insertSub(i_comment_line0[0]).wait(1 ms)\n .insertSub(i_comment_line0[1]).pin(\"INT1\").vForce(1.1)\n .insertSub(i_comment_line0[1]).pin(\"OCSB\").vForce(1.5)\n .execute();\n RDI_END();\n\n // Auto_Code_Execution_Part\n\n\n\n ON_FIRST_INVOCATION_END();\n\n\n // Auto_Code_Retrieve_Data\n \n int Func_result = rdi.id(\"T13_14_otp_clvwr_test_V2_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n // Auto_Code_Judge_and_log\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T13_14_otp_clvwr_test_V2\", T13_14_otp_clvwr_test_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: bai430aa_rel/1 $ $Author: hmf1rt $ $Date: 2024/08/07 15:21:03 GMT $')\n# Initialize variable (for simulation only!)\ncalc('TEMP_AMB', 30) # Assign TEMP_AMB variable, chuck temp set to 30deg\n# Reset temperature offset compensation\nwac('EXT_MODE', 0xc00a) # Switch to TEMP register page\nwac('OCP_MASK', 0x00ff) # Set masking register\nwr('TEMP_TRM_OFF_DGAIN', 0x0000) # Reset temperature offset compensation\nrac('TEMP_TRM_OFF_DGAIN', 0x0000, 0x00ff) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n# Disable ACC and measaure temperature\nwac('EXT_MODE', 0xc000) # Switch to USR register page\nwac('ACC_CONF', 0x024c) # Disable ACC\ndly(100e-6)\nwac('EXT_MODE', 0xc006) # Switch to FCU register page\nwr('FCU_TEST_CMD', 0x8000) # Trigger temp datapath reset\nwcb('temp_test_odr', 0x2) # Set temp ODR to 200\nwcb('temp_mode', 0x1) # Switch on temp sensor only \nwac('EXT_MODE', 0xc000) # Switch to USR register page\ndly(12e-3) # Wait for min 2 samples\nras('NU_TEMP', 'TEMP_DATA') # Read and save temp data\ncmt('This test item is a functinal fail if NU_TEMP = 0x8000')\n# Calculate offset calibration word TOFFSET\ncalc('NS_TEMP', 'NU_TEMP', 'cus', '16')\nlog('NS_TEMP')\ncmt('Get set chuck temperature in degree celsius and store in TEMP_AMB')\nlog ('TEMP_AMB')\n# Calculate NS_TOFFSET = round((-1)*NS_TEMP/64 + 4*TEMP_AMB - 92)\ncalc('DIV1', 'NS_TEMP', '/', 64)\ncalc('FAC1', 'DIV1', '*', -1)\ncalc('FAC2', 'TEMP_AMB', '*', 4)\ncalc('SUM1', 'FAC1', '+', 'FAC2')\ncalc('SUM2', 'SUM1', '-', 92)\ncalc('NS_TOFFSET', 'SUM2', 'round')\nlog('NS_TOFFSET')\ncmt('The test item is a funational fail if NS_TOFFSET > 127')\ncmt('The test item is a funational fail if NS_TOFFSET < -128')\ndly(74e-9)\nwac('EXT_MODE', 0xc006) # Switch to FCU register page\nwcb('temp_mode', 0x0) # Switch of temp sensor only\nwcb('temp_test_odr', 0x0) # Set temp ODR to default\ncalc('NU_TOFFSET', 'NS_TOFFSET', 'csu', '8')\n# Write offset calibration word back to DUT\nwac('EXT_MODE', 0xc00a) # Switch to TEMP register page\nwac('OCP_MASK', 0x00ff) # Set masking register\nwri('TEMP_TRM_OFF_DGAIN', 'NU_TOFFSET') # Write temp offset calibration\nras('NU_TOFFSET_RD', 'TEMP_TRM_OFF_DGAIN') # Read and save register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\ncmt('The test item is a functional fail if (NU_TOFFSET_RD & 0x00ff) != NU_TOFFSET')\nwac('EXT_MODE', 0xc006) # Switch to FCU register page\nwr('FCU_TEST_CMD', 0x8000) # Trigger temp datapath reset\nwac('EXT_MODE', 0xc000) # Switch to USR register page\nwac('ACC_CONF', 0xe24c) # Enable ACC in HPM\ndly(3e-3)\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T14_01_temperature_sensor_calibration_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n INT split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &split_pat_flag);\n vector s_splited_pat_name;\n const int split_count = 2; // Alarm:: split_count need manual confirm.\n s_splited_pat_name.resize(split_count);\n vector i_comment_line[split_count];\n\n static int NU_TEMP[xNSitES],NS_TEMP[xNSitES], NS_TOFFSET[xNSitES], NU_TOFFSET[xNSitES];\n static int NU_TOFFSET_RD[xNSitES];\n\n static double DIV1[xNSitES], FAC1[xNSitES], FAC2[xNSitES], SUM1[xNSitES], SUM2[xNSitES];\n\n\n ARRAY_LL NU_TOFFSET_rtv;\n const int Wri_Bit_Length = 33;\n const int Wri_Bit_Position = 31;\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n GET_TESTSUITE_NAME(test_name);\n NU_TOFFSET_rtv.resize(xNSitES);\n\n if (split_pat_flag)\n {\n split_pattern(s_label_name,\"wri\",split_pat_flag,s_splited_pat_name);\n }\n else\n {\n for (int i = 0; i 127}\n// \t {cmt: The test item is a funational fail if NS_TOFFSET < -128} {dly(7.4e-08, 0)};\n\n FOR_EACH_SITE_END();\n\n rdi.runTimeVal(\"NU_TOFFSET_rtv\", NU_TOFFSET_rtv);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T14_01_temperature_sensor_calibration_V2_PAT_id1\");\n rdi.digCap(\"T14_01_temperature_sensor_calibration_V2_Digcap_id1\").vecVarOnly().pin(\"SDO\").capMode(TA::SER).samples(16*1).bitPerWord(16).execute();\n rdi.smartVec().label(s_splited_pat_name[1]).pin(\"SDX\").writeData(\"NU_TOFFSET_rtv\", Wri_Bit_Length, Wri_Bit_Position).execute();\n RDI_END();\n }\n\n ON_FIRST_INVOCATION_END();\n \t ARRAY_I Vec=rdi.id(\"T14_01_temperature_sensor_calibration_V2_Digcap_id1\").getVector();\n \t NU_TOFFSET_RD[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[0]);\n \t FuncPrint(\"NU_TOFFSET_RD\", NU_TOFFSET_RD[CURRENT_SITE_NUMBER()-1]);\n\n int Func_result0 = rdi.id(\"T14_01_temperature_sensor_calibration_V2_PAT_id0\").getBurstPassFail();\n int Func_result1 = rdi.id(\"T14_01_temperature_sensor_calibration_V2_PAT_id1\").getBurstPassFail();\n FuncPrint(\"Func_result0\", Func_result0);\n FuncPrint(\"Func_result1\", Func_result1);\n int Func_result = 1 * Func_result0 * Func_result1;\n if (NU_TEMP[CURRENT_SITE_NUMBER()-1] == 0x8000) Func_result=10;\n if (NU_TOFFSET_RD[CURRENT_SITE_NUMBER()-1] != NU_TOFFSET[CURRENT_SITE_NUMBER()-1] ) Func_result=99;\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n//\n TestLog(\"NS_TEMP\", NS_TEMP[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"TEMP_AMB\", TEMP_AMB);\n TestLog(\"NS_TOFFSET\", NS_TOFFSET[CURRENT_SITE_NUMBER()-1]);\n // Auto_Code_Judge_and_log\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T14_01_temperature_sensor_calibration_V2\", T14_01_temperature_sensor_calibration_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 1 $ $Author: hmf1rt $ $Date: 2024/03/13 13:36:52 GMT $')\nwac('EXT_MODE', 0xc000) # Switch to USR register page\nwac('ACC_CONF', 0x024c) # Disable ACC\ndly(100e-6)\nwac('EXT_MODE', 0xc006) # Switch to FCU register page\nwr('FCU_TEST_CMD', 0x8000) # Trigger temp datapath reset\nwcb('temp_test_odr', 0x2) # Set temp ODR to 200\nwcb('temp_mode', 0x1) # Switch on temp sensor only \nwac('EXT_MODE', 0xc000) # Switch to USR register page\ndly(12e-3) # Wait for min 2 samples\nras('NU_TEMP_M', 'TEMP_DATA') # Read and save temp data\ncalc('NS_TEMP_M', 'NU_TEMP_M', 'cus', '16')\ncalc('NS_TEMP_M_FLOAT', 'NS_TEMP_M', '/', '256')\ncalc('TEMP_M', 'NS_TEMP_M_FLOAT', '+', '23')\nlog('TEMP_M')\nwac('EXT_MODE', 0xc006) # Switch to FCU register page\nwcb('temp_mode', 0x0) # Switch of temp sensor only\nwcb('temp_test_odr', 0x0) # Set temp ODR to default\nwr('FCU_TEST_CMD', 0x8000) # Trigger temp datapath reset\nwac('EXT_MODE', 0xc000) # Switch to USR register page\nwac('ACC_CONF', 0xe24c) # Enable ACC in HPM\ndly(3e-3)\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T14_02_temperature_sensor_measurement_V1: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n static int NU_TEMP_M[xNSitES], NS_TEMP_M[xNSitES];\n static double NS_TEMP_M_FLOAT[xNSitES], TEMP_M[xNSitES];\n // Auto_Code_Variable_define\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T14_02_temperature_sensor_measurement_V1_PAT_id\");\n rdi.digCap(\"T14_02_temperature_sensor_measurement_V1_Digcap_id\").label(s_label_name)\n .pin(\"SDO\").capMode(TA::SER).samples(16*1).bitPerWord(16)\n .execute();\n RDI_END();\n\n // Auto_Code_Execution_Part\n\n\n\n ON_FIRST_INVOCATION_END();\n ARRAY_I Vec=rdi.id(\"T14_02_temperature_sensor_measurement_V1_Digcap_id\").getVector();\n NU_TEMP_M[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[0]);\n\n NS_TEMP_M[CURRENT_SITE_NUMBER()-1] = i_Func_Unsigned_To_Signed(NU_TEMP_M[CURRENT_SITE_NUMBER()-1], 16);\n NS_TEMP_M_FLOAT[CURRENT_SITE_NUMBER()-1] = 1.000 * NS_TEMP_M[CURRENT_SITE_NUMBER()-1] / 256;\n TEMP_M[CURRENT_SITE_NUMBER()-1] = NS_TEMP_M_FLOAT[CURRENT_SITE_NUMBER()-1] + 23;\n\n int Func_result = rdi.id(\"T14_02_temperature_sensor_measurement_V1_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n FuncPrint(\"NU_TEMP_M\", NU_TEMP_M[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"NS_TEMP_M\", NS_TEMP_M[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"NS_TEMP_M_FLOAT\", NS_TEMP_M_FLOAT[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"TEMP_M\", TEMP_M[CURRENT_SITE_NUMBER()-1]);\n \n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"TEMP_M\", TEMP_M[CURRENT_SITE_NUMBER()-1]);\n // Auto_Code_Judge_and_log\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T14_02_temperature_sensor_measurement_V1\", T14_02_temperature_sensor_measurement_V1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 3 $ $Author: luz3sgh $ $Date: 2024/05/17 08:35:23 GMT $')\n \ntadc = [\n#| TADC range | INT2 | ASDX / name ANAIO1 |ANAIO2 before\n#+------------+---------+--------+--------+\n (0x0007, 1.0, 0.0, '2P4_1' ), # n = 0 test_adc_src=3 (EXTERNAL)\n (0x0007, 0.0, 0.0, '2P4_2' ), # n = 1\n (0x0007, 0.0, 1.0, '2P4_3' ), # n = 2\n (0x0003, 1.0, 0.0, '1P2_1' ), # n = 3 \n (0x0003, 0.0, 0.0, '1P2_2' ), # n = 4\n (0x0003, 0.0, 1.0, '1P2_3' ) # n = 5\n]\nwac('EXT_MODE', 0xc00f) # Switch to the TEST register page\nwac('TM_TEMP', 0x000b) # Enable TADC: tm_temp_adc_en=0x1; select external voltage measurement: tm_test_adc_tb1_bypass=0x1 and tm_test_adc_tb2_bypass=0x1\nwac('TM_PIN', 0x00dd) # tm_asdx_sel=6 (DEV_TION) tm_asdx_en=1 tm_int2_sel=6 (DEV_TIOP) tm_int2_en=1\nwac('TM_ADDR', 0x0003) # tm_cfg=0 (reset value) tm_addr=3 (NA; tm_bus_sel=tm_addr(3:2)=0 (DEV_TIOP/N)\n # enables test module\nwac('EXT_MODE', 0xc00a) # Switch to TEMP register page\nwcb('test_adc_src', 0x0003) # Set TADC source to external TEMP_DP.TEMP_TEST_TADC<1:0>\nwcb('test_bypass_comp', 0x1) # Bypass compensation of temp datapath TEMP_DP.TEMP_TES<0>\nwac('EXT_MODE', 0xc006) # Switch to FCU register page\nwcb('temp_mode', 0x1) # Keep temp always on\nwcb('temp_test_odr', 0x4) # Set temp test ODR to 800 (results in temp filter resolution of 512)\ndly(2.3e-3) # additional time for fcu.temp_ctrl.state=e_init_acc\n # time according filter resolution of 1024 (choosen for temp_init_meas)\n # additional time (temp_afe, synchronization to 25.6kHz) is covered\n\t\t\t\t\t# by the previous SPI commands\nwac('EXT_MODE', 0xc00a) # Switch to TEMP register page, temp_trm_fs2v4 reset va also 0\nwcb('temp_trm_fs2v4',0x0) # temp_trm_fs2v4=0 + test_adc_rng=1 --> TADC_RANGE=2.4V \nfor n in range(0, 6, 1): # temp_trm_fs2v4=0 + test_adc_rng=0 --> TADC_RANGE=1.2V\n wac('TEMP_TEST_TADC', tadc[n][0]) # test_adc_rng, test_adc_src\n sav('INT2', tadc[n][1])\n sav('ASDX', tadc[n][2])\n dly(100e-6) # 100 micro-seconds\n wac('EXT_MODE', 0xc006) # Switch to FCU register page\n wr('FCU_TEST_CMD', 0x8000) # Trigger temp datapath reset\n wac('EXT_MODE', 0xc000) # Switch to USR register page\n dly(2.9e-3) # temp power enable (320us) + 2.6ms (for temp filter resolution of 512)\n ras('NU_TADC_{}'.format(tadc[n][3]), 'TEMP_DATA')\n calc('NS_TADC_{}'.format(tadc[n][3]), 'NU_TADC_{}'.format(tadc[n][3]), 'cus', '16')\n log('NS_TADC_{}'.format(tadc[n][3]))\n wac('EXT_MODE', 0xc00a) # Switch to TEMP register page\nuav('INT2')\nuav('ASDX')\nwcb('test_adc_src', 0x0000) # Set TADC source CTAT\nwcb('test_bypass_comp', 0x0) # Reset bypass compensation\nwac('EXT_MODE', 0xc006) # Switch to FCU register page\nwcb('temp_mode', 0x0) # Switch temp mode to follow the sensors\nwcb('temp_test_odr', 0x0) # Set temp ODR to auto\nwr('FCU_TEST_CMD', 0x8000) # Trigger temp datapath reset\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('EXT_MODE', 0xc00f) # Switch to the TEST register page\nwac('TM_TEMP', 0x0000) # Disable TADC\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T14_03_temperature_ADC_test_V3: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n static int NU_TADC_2P4_1[xNSitES];\n static int NU_TADC_2P4_2[xNSitES];\n static int NU_TADC_2P4_3[xNSitES];\n static int NU_TADC_1P2_1[xNSitES];\n static int NU_TADC_1P2_2[xNSitES];\n static int NU_TADC_1P2_3[xNSitES];\n\n static int NS_TADC_2P4_1[xNSitES];\n static int NS_TADC_2P4_2[xNSitES];\n static int NS_TADC_2P4_3[xNSitES];\n static int NS_TADC_1P2_1[xNSitES];\n static int NS_TADC_1P2_2[xNSitES];\n static int NS_TADC_1P2_3[xNSitES];\n // Auto_Code_Variable_define\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n// ===========Pattern T14_03_temperature_ADC_test_V3_AVC3_PY3=============\n// key comment[0]is || TCMT 3292,\" {sav('INT2', 1, 2, 0.01, False, False)} {sav('ASDX', 0, 2, 0.01, False, False)} {dly(0.0001, 0)}\"\n//\n// key comment[1]is || TCMT 3769,\" {ras('NU_TADC_2P4_1', 'TEMP_DATA')}\"\n//\n// key comment[2]is || TCMT 4267,\" {sav('INT2', 0, 2, 0.01, False, False)} {sav('ASDX', 0, 2, 0.01, False, False)} {dly(0.0001, 0)}\"\n//\n// key comment[3]is || TCMT 4744,\" {ras('NU_TADC_2P4_2', 'TEMP_DATA')}\"\n//\n// key comment[4]is || TCMT 5242,\" {sav('INT2', 0, 2, 0.01, False, False)} {sav('ASDX', 1, 2, 0.01, False, False)} {dly(0.0001, 0)}\"\n//\n// key comment[5]is || TCMT 5719,\" {ras('NU_TADC_2P4_3', 'TEMP_DATA')}\"\n//\n// key comment[6]is || TCMT 6217,\" {sav('INT2', 1, 2, 0.01, False, False)} {sav('ASDX', 0, 2, 0.01, False, False)} {dly(0.0001, 0)}\"\n//\n// key comment[7]is || TCMT 6694,\" {ras('NU_TADC_1P2_1', 'TEMP_DATA')}\"\n//\n// key comment[8]is || TCMT 7192,\" {sav('INT2', 0, 2, 0.01, False, False)} {sav('ASDX', 0, 2, 0.01, False, False)} {dly(0.0001, 0)}\"\n//\n// key comment[9]is || TCMT 7669,\" {ras('NU_TADC_1P2_2', 'TEMP_DATA')}\"\n//\n// key comment[10]is || TCMT 8167,\" {sav('INT2', 0, 2, 0.01, False, False)} {sav('ASDX', 1, 2, 0.01, False, False)} {dly(0.0001, 0)}\"\n//\n// key comment[11]is || TCMT 8644,\" {ras('NU_TADC_1P2_3', 'TEMP_DATA')}\"\n//\n// key comment[12]is || TCMT 8950,\" {uav('INT2', False)} {uav('ASDX', False)} {wcb('test_adc_src', 0x0000)}\"\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T14_03_temperature_ADC_test_V3_PAT_id\");\n rdi.digCap(\"T14_03_temperature_ADC_test_V3_Digcap_id0\").vecVarOnly().pin(\"SDO\").capMode(TA::SER).samples(16*6).bitPerWord(16).execute();\n rdi.dc(\"T14_03_temperature_ADC_test_V3_DC_id0\").label(s_label_name)\n .insertSub(i_comment_line0[0]).pin(\"INT2\").vForce(1).insertSub(i_comment_line0[0]).pin(\"ASDX\").vForce(0)\n .insertSub(i_comment_line0[2]).pin(\"INT2\").vForce(0).insertSub(i_comment_line0[2]).pin(\"ASDX\").vForce(0)\n .insertSub(i_comment_line0[4]).pin(\"INT2\").vForce(0).insertSub(i_comment_line0[4]).pin(\"ASDX\").vForce(1)\n .insertSub(i_comment_line0[6]).pin(\"INT2\").vForce(1).insertSub(i_comment_line0[6]).pin(\"ASDX\").vForce(0)\n .insertSub(i_comment_line0[8]).pin(\"INT2\").vForce(0).insertSub(i_comment_line0[8]).pin(\"ASDX\").vForce(0)\n .insertSub(i_comment_line0[10]).pin(\"INT2\").vForce(0).insertSub(i_comment_line0[10]).pin(\"ASDX\").vForce(1)\n .insertSub(i_comment_line0[12]).pin(\"INT2,ASDX\").relay(TA::ppmuRly_offALL)\n .execute();\n RDI_END();\n ON_FIRST_INVOCATION_END();\n // Auto_Code_Retrieve_Data\n \n int Func_result = rdi.id(\"T14_03_temperature_ADC_test_V3_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n \t ARRAY_I Vec=rdi.id(\"T14_03_temperature_ADC_test_V3_Digcap_id0\").getVector();\n \t NU_TADC_2P4_1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[0]);\n \t NU_TADC_2P4_2[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[1]);\n \t NU_TADC_2P4_3[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[2]);\n \t NU_TADC_1P2_1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[3]);\n \t NU_TADC_1P2_2[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[4]);\n \t NU_TADC_1P2_3[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[5]);\n\n \t NS_TADC_2P4_1[CURRENT_SITE_NUMBER()-1] = i_Func_Unsigned_To_Signed(NU_TADC_2P4_1[CURRENT_SITE_NUMBER()-1], 16);\n \t NS_TADC_2P4_2[CURRENT_SITE_NUMBER()-1] = i_Func_Unsigned_To_Signed(NU_TADC_2P4_2[CURRENT_SITE_NUMBER()-1], 16);\n \t NS_TADC_2P4_3[CURRENT_SITE_NUMBER()-1] = i_Func_Unsigned_To_Signed(NU_TADC_2P4_3[CURRENT_SITE_NUMBER()-1], 16);\n \t NS_TADC_1P2_1[CURRENT_SITE_NUMBER()-1] = i_Func_Unsigned_To_Signed(NU_TADC_1P2_1[CURRENT_SITE_NUMBER()-1], 16);\n \t NS_TADC_1P2_2[CURRENT_SITE_NUMBER()-1] = i_Func_Unsigned_To_Signed(NU_TADC_1P2_2[CURRENT_SITE_NUMBER()-1], 16);\n \t NS_TADC_1P2_3[CURRENT_SITE_NUMBER()-1] = i_Func_Unsigned_To_Signed(NU_TADC_1P2_3[CURRENT_SITE_NUMBER()-1], 16);\n\n\n \tFuncPrint(\"NS_TADC_2P4_1\", NS_TADC_2P4_1[CURRENT_SITE_NUMBER()-1]);\n \tFuncPrint(\"NS_TADC_2P4_2\", NS_TADC_2P4_2[CURRENT_SITE_NUMBER()-1]);\n \tFuncPrint(\"NS_TADC_2P4_3\", NS_TADC_2P4_3[CURRENT_SITE_NUMBER()-1]);\n \tFuncPrint(\"NS_TADC_1P2_1\", NS_TADC_1P2_1[CURRENT_SITE_NUMBER()-1]);\n \tFuncPrint(\"NS_TADC_1P2_2\", NS_TADC_1P2_2[CURRENT_SITE_NUMBER()-1]);\n \tFuncPrint(\"NS_TADC_1P2_3\", NS_TADC_1P2_3[CURRENT_SITE_NUMBER()-1]);\n\n TestLog(\"NS_TADC_2P4_1\", NS_TADC_2P4_1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"NS_TADC_2P4_2\", NS_TADC_2P4_2[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"NS_TADC_2P4_3\", NS_TADC_2P4_3[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"NS_TADC_1P2_1\", NS_TADC_1P2_1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"NS_TADC_1P2_2\", NS_TADC_1P2_2[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"NS_TADC_1P2_3\", NS_TADC_1P2_3[CURRENT_SITE_NUMBER()-1]);\n // Auto_Code_Judge_and_log\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T14_03_temperature_ADC_test_V3\", T14_03_temperature_ADC_test_V3);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: bai430aa_rel/1 $ $Author: hmf1rt $ $Date: 2024/07/18 13:27:10 GMT $') \nwac('EXT_MODE', 0xc00f) # Switch to the TEST register page\nwac('TM_TEMP', 0x000b) # Enable TADC: tm_temp_adc_en=0x1; select external voltage measurement: tm_test_adc_tb1_bypass=0x1 and tm_test_adc_tb2_bypass=0x1\nwac('EXT_MODE', 0xc00a) # Switch to TEMP_DP register page\nwcb('test_bypass_comp', 0x1) # Bypass compensation of temp datapath\nwac('EXT_MODE', 0xc006) # Switch to FCU register page\nwcb('temp_mode', 0x1) # Keep temp always on\nwcb('temp_test_odr', 0x4) # Set temp test ODR to 800 (results in temp filter resolution of 512)\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('TEMP_TEST_ADC', 0x0001) # TEMP_TEST_ADC<0> temp_test_adc_inp_short=1\nwac('EXT_MODE', 0xc006) # Switch to FCU register page\nwr('FCU_TEST_CMD', 0x8000) # Trigger temp datapath reset\ndly(2.3e-3)\nwac('EXT_MODE', 0xc000) # Switch to USR register page \ndly(2.9e-3) # temp power enable (320us) + 2.6ms (for temp filter resolution of 512)\nras('NU_TADC_ZERO', 'TEMP_DATA')\ncalc('NS_TADC_ZERO', 'NU_TADC_ZERO', 'cus', '16')\nlog('NS_TADC_ZERO')\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('TEMP_TEST_ADC', 0x0000) # reset value\nwac('EXT_MODE', 0xc00a) # Switch to TEMP register page\nwcb('test_bypass_comp', 0x0) # Reset bypass compensation\nwac('EXT_MODE', 0xc006) # Switch to FCU register page\nwcb('temp_mode', 0x0) # Switch temp mode to follow the sensors\nwcb('temp_test_odr', 0x0) # Set temp ODR to auto\nwr('FCU_TEST_CMD', 0x8000) # Trigger temp datapath reset\nwac('EXT_MODE', 0xc00f) # Switch to the TEST register page\nwac('TM_TEMP', 0x0000) # Disable TADC\n", "output": "/*****************************************************\n * T14_04_Temperature_ADC_Short_Test_R1, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n * JSH5SGH: fix some bugs.\n * JSH5SGH R1: version update.\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T14_04_Temperature_ADC_Short_Test_R1: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static int i_NU_TADC_ZERO[xNSitES];\n static int NS_TADC_ZERO[xNSitES];\n ARRAY_I aI_Captured_0;\n static int i_funcRes0[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(i_NU_TADC_ZERO, 9, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T14_04_Temperature_ADC_Short_Test}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 1] @ avcline 2691: {ras('NU_TADC_ZERO', 'TEMP_DATA')}\n valid comment[ 2] @ avcline 2804: {calc('NS_TADC_ZERO', 'NU_TADC_ZERO', 'cus', '16')}\n valid comment[ 2] @ avcline 2804: {log('NS_TADC_ZERO', '', '', 0, 0)}\n valid comment[ 3] @ avcline 5086: {Test End: T14_04_Temperature_ADC_Short_Test}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.digCap(\"digcapid_0\").label(s_splited_pat_name[0]).pin(\"SDO\").capMode(TA::SER).bitPerWord(16).samples(1*16).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n aI_Captured_0 = rdi.id(\"digcapid_0\").getVector(\"SDO\");\n aI_Captured_0[0] = Switch_High_Low_Bits_16Bits(aI_Captured_0[0]);\n i_NU_TADC_ZERO[curSite] = aI_Captured_0[0];\n FuncPrint(\"NU_TADC_ZERO\", i_NU_TADC_ZERO[curSite]);\n NS_TADC_ZERO[curSite] = i_Func_Unsigned_To_Signed(i_NU_TADC_ZERO[curSite], 16);\n FuncPrint(\"NS_TADC_ZERO\", NS_TADC_ZERO[curSite]);\n\n FOR_EACH_SITE_END();\n\n\n ON_FIRST_INVOCATION_END();\n\n TestLog(\"NS_TADC_ZERO\", NS_TADC_ZERO[curSite]);\n i_funcRes[curSite] = i_funcRes0[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T14_04_Temperature_ADC_Short_Test_R1\", T14_04_Temperature_ADC_Short_Test_R1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "# VBGP_CTAT/VBGP_REFN routed to INT2/ASDX; measured and logged\ncmt('Version info: $Revision: 2 $ $Author: laj1mu23 $ $Date: 2024/03/25 21:07:43 GMT $')\nwac('EXT_MODE', 0xc00f) # Switch to the TEST register page\nwac('TM_CONF', 0x0011) # tm_se_meas=0 tm_bus_inv=1 tm_buf_pwrup=1 (tbuf_tb1_on)\n # bus_inv. because the power_ana_test_multiplexor_refs provides VSS_A/VREF_AA\nwac('TM_PIN', 0x0095) # tm_asdx_sel=4 (BUF2_INP) tm_asdx_en=1 tm_int2_sel=2 (BUF1_OUT) tm_int2_en=1\nwac('TM_ADDR', 0x0c0e) # tm_cfg=c (COM_TB2= VBGP_CTAT, COM_TB1= VBGP_REFN) tm_addr=e (tm_bus_sel=tm_addr(3:2)=3 (COM_TION/P) COM_TIO_REF;\n # enable the power_ana_test_multiplexor); any tm_addr value except off/0 enables the test module\ndly(100e-6)\ngav('V_VBG_CTAT_M_RAW', 'INT2', 'ASDX')\ncalc('V_VBG_CTAT_M', 'V_VBG_CTAT_M_RAW', '-', 'V_OFF1_ECOFF')\nlog('V_VBG_CTAT_M')\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\n", "output": "/*****************************************************\n * T14_05_CTAT_Measurement_V2, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n * JSH5SGH: fix some bugs.\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T14_05_CTAT_Measurement_V2: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static double d_V_VBG_CTAT_M_RAW[xNSitES];\n static double V_VBG_CTAT_M[xNSitES];\n static int i_funcRes0[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(d_V_VBG_CTAT_M_RAW, 9.9, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T14_05_CTAT_Measurement}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 1] @ avcline 788: {gav('V_VBG_CTAT_M_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 1] @ avcline 788: {calc('V_VBG_CTAT_M', 'V_VBG_CTAT_M_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 1] @ avcline 788: {log('V_VBG_CTAT_M', '', '', 0, 0)}\n valid comment[ 2] @ avcline 1365: {Test End: T14_05_CTAT_Measurement}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][1]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_VBG_CTAT_M_RAW//{gav('V_VBG_CTAT_M_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n ARRAY_D ad_jsubresults_INT2; ad_jsubresults_INT2.resize(1); ad_jsubresults_INT2.init(-9.9);\n ARRAY_D ad_jsubresults_ASDX; ad_jsubresults_ASDX.resize(1); ad_jsubresults_ASDX.init(-9.9);\n ad_jsubresults_INT2 = rdi.id(\"dcid_0\").getMultiValue(\"INT2\");\n ad_jsubresults_ASDX = rdi.id(\"dcid_0\").getMultiValue(\"ASDX\");\n \n d_V_VBG_CTAT_M_RAW[curSite] = ad_jsubresults_INT2[0] - ad_jsubresults_ASDX[0];\n FuncPrint(\"V_VBG_CTAT_M_RAW\",d_V_VBG_CTAT_M_RAW[curSite]);\n\n V_VBG_CTAT_M[curSite] = d_V_VBG_CTAT_M_RAW[curSite] - V_OFF1_ECOFF[curSite];\n FuncPrint(\"V_VBG_CTAT_M\",V_VBG_CTAT_M[curSite]);\n FOR_EACH_SITE_END();\n\n\n ON_FIRST_INVOCATION_END();\n\n TestLog(\"V_VBG_CTAT_M\",\tV_VBG_CTAT_M[curSite]);\n i_funcRes[curSite] = i_funcRes0[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T14_05_CTAT_Measurement_V2\", T14_05_CTAT_Measurement_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 2 $ $Author: laj1mu23 $ $Date: 2024/03/25 21:07:43 GMT $')\nwac('EXT_MODE', 0xc006) # Switch to FCU register page\nwcb('temp_test_odr', 0x6) # Set temp test ODR to 3k2 (cont. temp operation)\nwcb('temp_mode', 0x1) # Keep temp always on\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_CONF', 0x0001) # Switch on TB1\nwac('TM_PIN', 0x0095) # Enable ANAIO1/2; TB1_OUT on ANAIO1; TB2_INP on ANAIO2\nwac('EXT_MODE', 0xc00d) # Switch to the ANA register page\nwac('TEMP_TEST_ADC', 0x0004) # Set temp_adc_test_vref_p=1\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_ADDR', 0x000c) # Set tm_addr to ATM configuration for temp/stress sensor test\ndly(100e-6)\ngav('V_TEMP_ADC_VREF_P_RAW', 'INT2', 'ASDX')\ncalc('V_TEMP_ADC_VREF_P', 'V_TEMP_ADC_VREF_P_RAW', '-', 'V_OFF1_ECOFF')\nlog('V_TEMP_ADC_VREF_P')\nwac('TM_ADDR', 0x0000) # Disable ATM\n\nwac('EXT_MODE', 0xc00e) # Switch to the AFE register page\nwcb('TEMP_TRM_CTRL.temp_trm_pwr_mode', 1) #enable continue mode\n\nwac('EXT_MODE', 0xc00d) # Switch to the ANA register page\nwac('TEMP_TEST_ADC', 0x0008) # Set temp_adc_test_vcm=1\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_ADDR', 0x000c) # Set tm_addr to ATM configuration for temp/stress sensor test\ndly(100e-6)\ngav('V_TEMP_ADC_VCM_RAW', 'INT2', 'ASDX')\ncalc('V_TEMP_ADC_VCM', 'V_TEMP_ADC_VCM_RAW', '-', 'V_OFF1_ECOFF')\nlog('V_TEMP_ADC_VCM')\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\n\nwac('EXT_MODE', 0xc00e) # Switch to the AFE register page\nwcb('TEMP_TRM_CTRL.temp_trm_pwr_mode', 0) # disable continue mode\n\nwac('EXT_MODE', 0xc00d) # Switch to the ANA register page\nwac('TEMP_TEST_ADC', 0x0000) # Reset temperature test register\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_CONF', 0x0000) # Disable TBs\nwac('EXT_MODE', 0xc006) # Switch to FCU register page\nwcb('temp_mode', 0x0) # Disable temp force\nwcb('temp_test_odr', 0x0) # Set temp test ODR to default\ndly(100e-6)\n", "output": "/*****************************************************\n * T14_07_TADC_internal_buffer_output_V2, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n * JSH5SGH: fix some bugs.\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T14_07_TADC_internal_buffer_output_V2: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static double d_V_TEMP_ADC_VCM_RAW[xNSitES];\n static double d_V_TEMP_ADC_VREF_P_RAW[xNSitES];\n static double V_TEMP_ADC_VCM[xNSitES];\n static double V_TEMP_ADC_VREF_P[xNSitES];\n static int i_funcRes0[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(d_V_TEMP_ADC_VCM_RAW, 9.9, xNSitES);\n Func_Init_Var(d_V_TEMP_ADC_VREF_P_RAW, 9.9, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T14_07_TADC_internal_buffer_output}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 1] @ avcline 2256: {gav('V_TEMP_ADC_VREF_P_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 1] @ avcline 2256: {calc('V_TEMP_ADC_VREF_P', 'V_TEMP_ADC_VREF_P_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 1] @ avcline 2256: {log('V_TEMP_ADC_VREF_P', '', '', 0, 0)}\n valid comment[ 2] @ avcline 3769: {gav('V_TEMP_ADC_VCM_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 2] @ avcline 3769: {calc('V_TEMP_ADC_VCM', 'V_TEMP_ADC_VCM_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 2] @ avcline 3769: {log('V_TEMP_ADC_VCM', '', '', 0, 0)}\n valid comment[ 3] @ avcline 6366: {Test End: T14_07_TADC_internal_buffer_output}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][1]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(32).measWait(1 ms)//V_TEMP_ADC_VREF_P_RAW//{gav('V_TEMP_ADC_VREF_P_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][2]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(32).measWait(1 ms)//V_TEMP_ADC_VCM_RAW//{gav('V_TEMP_ADC_VCM_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n ARRAY_D ad_jsubresults_INT2; ad_jsubresults_INT2.resize(2); ad_jsubresults_INT2.init(-9.9);\n ARRAY_D ad_jsubresults_ASDX; ad_jsubresults_ASDX.resize(2); ad_jsubresults_ASDX.init(-9.9);\n ad_jsubresults_INT2 = rdi.id(\"dcid_0\").getMultiValue(\"INT2\");\n ad_jsubresults_ASDX = rdi.id(\"dcid_0\").getMultiValue(\"ASDX\");\n \n d_V_TEMP_ADC_VCM_RAW[curSite] = ad_jsubresults_INT2[1] - ad_jsubresults_ASDX[1];\n FuncPrint(\"V_TEMP_ADC_VCM_RAW\",\td_V_TEMP_ADC_VCM_RAW[curSite]);\n V_TEMP_ADC_VCM[curSite] = d_V_TEMP_ADC_VCM_RAW[curSite] - V_OFF1_ECOFF[curSite];\n FuncPrint(\"V_TEMP_ADC_VCM\",\t\tV_TEMP_ADC_VCM[curSite]);\n\n d_V_TEMP_ADC_VREF_P_RAW[curSite] = ad_jsubresults_INT2[0] - ad_jsubresults_ASDX[0];\n FuncPrint(\"V_TEMP_ADC_VREF_P_RAW\",\td_V_TEMP_ADC_VREF_P_RAW[curSite]);\n V_TEMP_ADC_VREF_P[curSite] = d_V_TEMP_ADC_VREF_P_RAW[curSite] - V_OFF1_ECOFF[curSite];\n FuncPrint(\"V_TEMP_ADC_VREF_P\",\t\tV_TEMP_ADC_VREF_P[curSite]);\n\n FOR_EACH_SITE_END();\n\n\n ON_FIRST_INVOCATION_END();\n\n TestLog(\"V_TEMP_ADC_VCM\",\t\tV_TEMP_ADC_VCM[curSite]);\n TestLog(\"V_TEMP_ADC_VREF_P\",\tV_TEMP_ADC_VREF_P[curSite]);\n i_funcRes[curSite] = i_funcRes0[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T14_07_TADC_internal_buffer_output_V2\", T14_07_TADC_internal_buffer_output_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 2 $ $Author: laj1mu23 $ $Date: 2024/03/25 20:39:17 GMT $')\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_CONF', 0x0101) # Enable TB1; enable se_meas\nwac('TM_PIN', 0x0095) # Enable ANAIO1/2; TB1_OUT on ANAIO1; TB2_INP on ANAIO2\nwac('TM_ADDR', 0x000b) # Enable ACC AFE aux block on ATM; Connect VEXH/VCM\ndly(100e-6)\ngav('V_EXH_RAW', 'INT2', 'ASDX')\ncalc('V_EXH', 'V_EXH_RAW', '-', 'V_OFF1_ECOFF')\nlog('V_EXH')\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_CONF', 0x0111) # Invert test bus; keep TB1 and se_meas\nwac('TM_ADDR', 0x000b) # Enable ACC AFE aux block on ATM; Connect VEXH/VCM\ndly(100e-6)\ngav('V_CM_ACC_RAW', 'INT2', 'ASDX')\ncalc('V_CM_ACC', 'V_CM_ACC_RAW', '-', 'V_OFF1_ECOFF')\nlog('V_CM_ACC')\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Reset test config\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T15_01_ACC_AFE_internal_reference_measurement_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n static double V_EXH_RAW[xNSitES];\n static double V_CM_ACC_RAW[xNSitES];\n // Auto_Code_Variable_define\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T15_01_ACC_AFE_internal_reference_measurement_V2_PAT_id\");\n rdi.dc(\"T15_01_ACC_AFE_internal_reference_measurement_V2DC_id0\").label(s_label_name)\n .insertSub(i_comment_line0[0]).pin(\"INT2,ASDX\",TA::BADC).vMeas().average(128).measWait(1 ms) //V_EXH_RAW\n .insertSub(i_comment_line0[1]).pin(\"INT2,ASDX\",TA::BADC).vMeas().average(128).measWait(1 ms) //V_CM_ACC_RAW\n .execute();\n RDI_END();\n\n // Auto_Code_Execution_Part\n\n\n\n ON_FIRST_INVOCATION_END();\n ARRAY_D JSUB_results_ASDX;\n JSUB_results_ASDX = rdi.id(\"T15_01_ACC_AFE_internal_reference_measurement_V2DC_id0\").getMultiValue(\"ASDX\");\n ARRAY_D JSUB_results_INT2;\n JSUB_results_INT2 = rdi.id(\"T15_01_ACC_AFE_internal_reference_measurement_V2DC_id0\").getMultiValue(\"INT2\");\n V_EXH_RAW[CURRENT_SITE_NUMBER()-1] = JSUB_results_INT2[0] - JSUB_results_ASDX[0];\n V_CM_ACC_RAW[CURRENT_SITE_NUMBER()-1] = JSUB_results_INT2[1] - JSUB_results_ASDX[1];\n\n double V_EXH, V_CM_ACC;\n V_EXH = V_EXH_RAW[CURRENT_SITE_NUMBER()-1] - V_OFF1_ECOFF[CURRENT_SITE_NUMBER()-1];\n V_CM_ACC = V_CM_ACC_RAW[CURRENT_SITE_NUMBER()-1] - V_OFF1_ECOFF[CURRENT_SITE_NUMBER()-1];\n\n FuncPrint(\"JSUB_results_ASDX[0]\", JSUB_results_ASDX[0]);\n FuncPrint(\"JSUB_results_ASDX[1]\", JSUB_results_ASDX[1]);\n FuncPrint(\"JSUB_results_INT2[0]\", JSUB_results_INT2[0]);\n FuncPrint(\"JSUB_results_INT2[1]\", JSUB_results_INT2[1]);\n\n FuncPrint(\"V_EXH_RAW\", V_EXH_RAW[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"V_CM_ACC_RAW\", V_CM_ACC_RAW[CURRENT_SITE_NUMBER()-1]);\n\n FuncPrint(\"V_EXH\", V_EXH);\n FuncPrint(\"V_CM_ACC\", V_CM_ACC);\n\n // Auto_Code_Retrieve_Data\n \n int Func_result = rdi.id(\"T15_01_ACC_AFE_internal_reference_measurement_V2_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"V_EXH\", V_EXH);\n TestLog(\"V_CM_ACC\", V_CM_ACC);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T15_01_ACC_AFE_internal_reference_measurement_V2\", T15_01_ACC_AFE_internal_reference_measurement_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: test diffirent gain settings of DCV (each bit of DCFB trim)\n# - Reset DP\n# - Disable Sensor drive, disconnect Mems, 3 channle keep enable\n# - Set acc_trm_gmboost_ch1/2/3 to 0\n# - Set DLG to 7?\n# - Set Offset to 8, sign to 0 ?\n# - Set DGAIN to 0?\n# - Set Filter to bypass ?\n# - Loop measure with DCFB set to 0,1,3,7,15,31\n#############################################################################################################\ncmt('Version info: $Revision: bai430aa_rel/1 $ $Author: bes1rt $ $Date: 2024/07/17 16:27:03 GMT $')\n\n# Set capacitive Offset to 8,sign to 0\nwac('EXT_MODE',0xc00d) # ANA page\nwac(\"OCP_MASK\", 0x1fff)\nwr('ANA_TRM_ACC_CH1',0x0008) # Set Offset=8, off_Sign, C0 to 0 \nrac('ANA_TRM_ACC_CH1',0x0008,0x1fff) \nwr('ANA_TRM_ACC_CH2',0x0008) # Set Offset=8, off_Sign, C0 to 0 \nrac('ANA_TRM_ACC_CH2',0x0008,0x1fff) \nwr('ANA_TRM_ACC_CH3',0x0008) # Set Offset=8, off_Sign, C0 to 0\nrac('ANA_TRM_ACC_CH3',0x0008,0x1fff) \nwr(\"OCP_MASK\", 0x0000) # Reset masking register\nrac(\"OCP_MASK\", 0xffff) # Check masking register reset\n\nfor n in [0, 1, 3, 7, 15, 31]:\n # Set DCFB\n wac(\"EXT_MODE\", 0xc00e) # change to page 14, ACC_AFE\n wac(\"OCP_MASK\", 0x7fff)\t\t\t\t# Set masking register\n wr(\"ACC_TRM_CFB\", 1024*n+32*n+n) # Set DCFB ch1/2/3\n rac(\"ACC_TRM_CFB\", 1024*n+32*n+n, 0x7fff) # Check register setting\n l = min(n+1, 31)\n wr(\"ACC_TRM_LOOPG\", 1024*l+32*l+l) # Set DLG ch1/2/3\n rac(\"ACC_TRM_LOOPG\", 1024*l+32*l+l, 0x7fff) # Check register setting\n wr(\"OCP_MASK\", 0x0000) # Reset masking register\n rac(\"OCP_MASK\", 0xffff) # Check masking register reset \n\n # Read ACC data\n wac(\"EXT_MODE\", 0xc002) # Access user register page/SHDW page\n dly(2e-3)\n cmt(f\"Burst read over 6 data registers and save in array NU_DCFB_{n:02d}\")\n bras(f\"NU_DCFB_{n:02d}\", \"ACC_DATA_X_LSB\", 6)\n # Convert 32-bit unsigned parameters NU_DCFB_a_n to signed parameters NS_DCFB_a_n\n calc(\"MSB\", f\"NU_DCFB_{n:02d}[1]\", '<<',16)\n calc(\"NU_DCFB\", f\"NU_DCFB_{n:02d}[0]\", '+',\"MSB\")\n calc(f\"NS_DCFB_X_{n:02d}\", \"NU_DCFB\", 'cus', 32)\n dly(296e-9)\n calc(\"MSB\", f\"NU_DCFB_{n:02d}[3]\", '<<',16)\n calc(\"NU_DCFB\", f\"NU_DCFB_{n:02d}[2]\", '+',\"MSB\")\n calc(f\"NS_DCFB_Y_{n:02d}\", \"NU_DCFB\", 'cus', 32)\n dly(296e-9)\n calc(\"MSB\", f\"NU_DCFB_{n:02d}[5]\", '<<',16)\n calc(\"NU_DCFB\", f\"NU_DCFB_{n:02d}[4]\", '+',\"MSB\")\n calc(f\"NS_DCFB_Z_{n:02d}\", \"NU_DCFB\", 'cus', 32)\n dly(296e-9)\nwac(\"EXT_MODE\", 0xc00e) # change to acc_afe page\nwac(\"ACC_TRM_LOOPG\", 0x7fff) # Reset to default value\nwac(\"ACC_TRM_CFB\", 0x7fff ) # Reset to default value\nwac(\"EXT_MODE\", 0xc00d) # change to page ANA\nwac(\"ANA_TRM_ACC_CH1\", 0x0000) # Reset to default value\nwac(\"ANA_TRM_ACC_CH2\", 0x0000) \nwac(\"ANA_TRM_ACC_CH3\", 0x0000) \n\n# Data evaluation and logging\n# Calculate N_RATIO_DCFB_a_00_01 = NS_DCFB_a_00 / NS_DCFB_a_01, for every axis a = {X,Y,Z}\n# Calculate N_RATIO_DCFB_a_01_03 = NS_DCFB_a_01 / NS_DCFB_a_03, for every axis a = {X,Y,Z}\n# Calculate N_RATIO_DCFB_a_03_07 = NS_DCFB_a_03 / NS_DCFB_a_07, for every axis a = {X,Y,Z}\n# Calculate N_RATIO_DCFB_a_07_15 = NS_DCFB_a_07 / NS_DCFB_a_15, for every axis a = {X,Y,Z}\n# Calculate N_RATIO_DCFB_a_15_31 = NS_DCFB_a_15 / NS_DCFB_a_31, for every axis a = {X,Y,Z}\n# Calculate N_RATIO_XY_DCFB = NS_DCFB_X_00 / NS_DCFB_Y_00\n# Calculate N_RATIO_YZ_DCFB = NS_DCFB_Y_00 / NS_DCFB_Z_00\n# Calculate N_RATIO_ZX_DCFB = NS_DCFB_Z_00 / NS_DCFB_X_00\n\nlog(\"N_RATIO_XY_DCFB\")\nlog(\"N_RATIO_YZ_DCFB\")\nlog(\"N_RATIO_ZX_DCFB\")\n\nfor a in [\"X\", \"Y\", \"Z\"]:\n log(f\"N_RATIO_DCFB_{a}_00_01\")\n log(f\"N_RATIO_DCFB_{a}_01_03\")\n log(f\"N_RATIO_DCFB_{a}_03_07\")\n log(f\"N_RATIO_DCFB_{a}_07_15\")\n log(f\"N_RATIO_DCFB_{a}_15_31\")\n dly(296e-9)\n for n in [0, 1, 3, 7, 15, 31]:\n log(f\"NS_DCFB_{a}_{n:02d}\")\n dly(296e-9)\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T15_02_ACC_AFE_DCFB_Test_R1: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n const string n_string[6] = {\"00\", \"01\", \"03\", \"07\", \"15\", \"31\"};\n const string axis_string[3] = {\"X\", \"Y\", \"Z\"};\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n rdi.enableOre(oreFlag);\n rdi.oreFile(\"./ORE_Files/rdi_ore_T15_02_ACC_AFE_DCFB_TEST.xml\");\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T15_02_ACC_AFE_DCFB_Test_R1_PAT_id\");\n rdi.digCap(\"T15_02_ACC_AFE_DCFB_Test_R1_Digcap_id\").label(s_label_name)\n .pin(\"SDO\").capMode(TA::SER).samples(16*36).bitPerWord(16)\n .execute();\n RDI_END();\n ON_FIRST_INVOCATION_END();\n\n ARRAY_I Vec=rdi.id(\"T15_02_ACC_AFE_DCFB_Test_R1_Digcap_id\").getVector();\n\n int NU_DCFB[6][6];// NU_DCFB[00/01/03/07/15/31][x/x/y/y/z/z]\n int NS_DCFB[6][3];// NS_DCFB[00/01/03/07/15/31][x/y/z]\n\n for (int i=0; i<6; i++)\n {\n \t for (int j=0; j<6; j++)\n \t {\n \t\t NU_DCFB[i][j] = reverse_ras_result(Vec[i*6+j]);\n// \t\t cout << \"NU_DCFB_\" + n_string[i] + \"[\" + rdi.itos(j) + \"] = Vec[\" << i*6+j << \"]\"<< endl;\n \t\t FuncPrint(\"NU_DCFB_\" + n_string[i] + \"_\"+ rdi.itos(j), NU_DCFB[i][j]);\n \t }\n }\n\n for (int i=0; i<6; i++)\n {\n \t for (int j=0; j<3; j++)\n \t {\n \t\t NS_DCFB[i][j] = i_Func_Unsigned_To_Signed((NU_DCFB[i][j*2+1] << 16) + NU_DCFB[i][j*2+0], 32);\n \t\t FuncPrint(\"NS_DCFB_\" + n_string[i] + \"_\"+ axis_string[j], NS_DCFB[i][j]);\n \t }\n }\n double N_RATIO_DCFB_00_01[3], N_RATIO_DCFB_01_03[3], N_RATIO_DCFB_03_07[3], N_RATIO_DCFB_07_15[3], N_RATIO_DCFB_15_31[3];\n\n for (int i=0; i<3; i++)\n {\n \t N_RATIO_DCFB_00_01[i] = 1.000 * NS_DCFB[0][i] / NS_DCFB[1][i];\n \t N_RATIO_DCFB_01_03[i] = 1.000 * NS_DCFB[1][i] / NS_DCFB[2][i];\n \t N_RATIO_DCFB_03_07[i] = 1.000 * NS_DCFB[2][i] / NS_DCFB[3][i];\n \t N_RATIO_DCFB_07_15[i] = 1.000 * NS_DCFB[3][i] / NS_DCFB[4][i];\n \t N_RATIO_DCFB_15_31[i] = 1.000 * NS_DCFB[4][i] / NS_DCFB[5][i];\n }\n double N_RATIO_XY_DCFB = 1.000 * NS_DCFB[0][0] / NS_DCFB[0][1];\n double N_RATIO_YZ_DCFB = 1.000 * NS_DCFB[0][1] / NS_DCFB[0][2];\n double N_RATIO_ZX_DCFB = 1.000 * NS_DCFB[0][2] / NS_DCFB[0][0];\n\n \n int Func_result = rdi.id(\"T15_02_ACC_AFE_DCFB_Test_R1_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n TestLog(\"N_RATIO_XY_DCFB\", N_RATIO_XY_DCFB);\n TestLog(\"N_RATIO_YZ_DCFB\", N_RATIO_YZ_DCFB);\n TestLog(\"N_RATIO_ZX_DCFB\", N_RATIO_ZX_DCFB);\n\n for (int i=0; i<3; i++)\n {\n \t TestLog(\"N_RATIO_DCFB_\" + axis_string[i] + \"_00_01\", N_RATIO_DCFB_00_01[i]);\n \t TestLog(\"N_RATIO_DCFB_\" + axis_string[i] + \"_01_03\", N_RATIO_DCFB_01_03[i]);\n \t TestLog(\"N_RATIO_DCFB_\" + axis_string[i] + \"_03_07\", N_RATIO_DCFB_03_07[i]);\n \t TestLog(\"N_RATIO_DCFB_\" + axis_string[i] + \"_07_15\", N_RATIO_DCFB_07_15[i]);\n \t TestLog(\"N_RATIO_DCFB_\" + axis_string[i] + \"_15_31\", N_RATIO_DCFB_15_31[i]);\n }\n\n for (int i=0; i<6; i++)\n {\n \t for (int j=0; j<3; j++)\n \t {\n \t\t TestLog(\"NS_DCFB_\" + axis_string[j] + \"_\" + n_string[i], NS_DCFB[i][j]);\n \t }\n }\n\n FuncPrint(\"N_RATIO_XY_DCFB\", N_RATIO_XY_DCFB);\n FuncPrint(\"N_RATIO_YZ_DCFB\", N_RATIO_YZ_DCFB);\n FuncPrint(\"N_RATIO_ZX_DCFB\", N_RATIO_ZX_DCFB);\n\n for (int i=0; i<3; i++)\n {\n \t FuncPrint(\"N_RATIO_DCFB_\" + axis_string[i] + \"_00_01\", N_RATIO_DCFB_00_01[i]);\n \t FuncPrint(\"N_RATIO_DCFB_\" + axis_string[i] + \"_01_03\", N_RATIO_DCFB_01_03[i]);\n \t FuncPrint(\"N_RATIO_DCFB_\" + axis_string[i] + \"_03_07\", N_RATIO_DCFB_03_07[i]);\n \t FuncPrint(\"N_RATIO_DCFB_\" + axis_string[i] + \"_07_15\", N_RATIO_DCFB_07_15[i]);\n \t FuncPrint(\"N_RATIO_DCFB_\" + axis_string[i] + \"_15_31\", N_RATIO_DCFB_15_31[i]);\n }\n\n for (int i=0; i<6; i++)\n {\n \t for (int j=0; j<3; j++)\n \t {\n \t\t FuncPrint(\"NS_DCFB_\" + axis_string[j] + \"_\" + n_string[i], NS_DCFB[i][j]);\n \t }\n }\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T15_02_ACC_AFE_DCFB_Test_R1\", T15_02_ACC_AFE_DCFB_Test_R1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description:\n# - test each bit of dcoff dac\n#############################################################################################################\ncmt('Version info: $Revision: bai430aa_rel/1 $ $Author: bes1rt $ $Date: 2024/07/17 16:27:03 GMT $')\n\nwac('EXT_MODE',0xc00d) # ANA page\nwac(\"OCP_MASK\", 0x1fff)\nwr('ANA_TRM_ACC_CH1',0x0000) # Set Offset, off_Sign, C0 to 0 \nrac('ANA_TRM_ACC_CH1',0x0000,0x1fff) \nwr('ANA_TRM_ACC_CH2',0x0000) # Set Offset, off_Sign, C0 to 0 \nrac('ANA_TRM_ACC_CH2',0x0000,0x1fff) \nwr('ANA_TRM_ACC_CH3',0x0000) # Set Offset, off_Sign, C0 to 0\nrac('ANA_TRM_ACC_CH3',0x0000,0x1fff) \nwr(\"OCP_MASK\", 0x0000) # Reset masking register\nrac(\"OCP_MASK\", 0xffff) # Check masking register reset\n\n# Set DCFB\nwac(\"EXT_MODE\", 0xc00e) # change to page 14, ACC_AFE\nwac(\"OCP_MASK\", 0x7fff) # Set masking register\nwr(\"ACC_TRM_CFB\", 1024*7+32*7+7) # Set DCFB ch1/2/3 to 7\nrac(\"ACC_TRM_CFB\", 1024*7+32*7+7, 0x7fff) # Check register setting\nwr(\"ACC_TRM_LOOPG\", 1024*8+32*8+8) # Set DLG ch1/2/3 to 8\nrac(\"ACC_TRM_LOOPG\", 1024*8+32*8+8, 0x7fff) # Check register setting\nwr(\"OCP_MASK\", 0x0000) # Reset masking register\nrac(\"OCP_MASK\", 0xffff) # Check masking register reset \n\nfor n in [0, 1, 2, 4, 8, 16, 32, 64, 128]: # cosier of 7bits width\n wac(\"EXT_MODE\", 0xc00d) # change to page ANA\n wac(\"OCP_MASK\", 0x01ff)\n wr(\"ANA_TRM_ACC_CH1\", n) # Set os_ch1; set sign_ch1 to 0\n rac(\"ANA_TRM_ACC_CH1\", n, 0x01ff) # Set os_ch1; set sign_ch1 to 0 \n wr(\"ANA_TRM_ACC_CH2\", n) # Set os_ch2; set sign_ch2 to 0\n rac(\"ANA_TRM_ACC_CH2\", n, 0x01ff) # Set os_ch2; set sign_ch2 to 0\n wr(\"ANA_TRM_ACC_CH3\", n) # Set os_ch3; set sign_ch3 to 0\n rac(\"ANA_TRM_ACC_CH3\", n, 0x01ff) # Set os_ch3; set sign_ch3 to 0\n wr(\"OCP_MASK\", 0x0000) # Reset masking register\n rac(\"OCP_MASK\", 0xffff) \n # Read ACC data\n wac(\"EXT_MODE\", 0xc002) # Access user register page/SHDW page\n dly(2e-3)\n cmt(f\"Burst read over 6 data registers and save in array NU_DCFB_{n:02d}\")\n bras(f\"NU_DCOFF0_{n:02d}\", \"ACC_DATA_X_LSB\", 6)\n # Convert 32-bit unsigned parameters NU_DCFB_a_n to signed parameters NS_DCFB_a_n\n calc(\"MSB\", f\"NU_DCOFF0_{n:02d}[1]\", '<<',16)\n calc(\"NU_MSB_LSB\", f\"NU_DCOFF0_{n:02d}[0]\", '+',\"MSB\")\n calc(f\"NS_DCOFF0_X_{n:02d}\", \"NU_MSB_LSB\", 'cus', 32)\n dly(296e-9)\n calc(\"MSB\", f\"NU_DCOFF0_{n:02d}[3]\", '<<',16)\n calc(\"NU_MSB_LSB\", f\"NU_DCOFF0_{n:02d}[2]\", '+',\"MSB\")\n calc(f\"NS_DCOFF0_Y_{n:02d}\", \"NU_MSB_LSB\", 'cus', 32)\n dly(296e-9)\n calc(\"MSB\", f\"NU_DCOFF0_{n:02d}[5]\", '<<',16)\n calc(\"NU_MSB_LSB\", f\"NU_DCOFF0_{n:02d}[4]\", '+',\"MSB\")\n calc(f\"NS_DCOFF0_Z_{n:02d}\", \"NU_MSB_LSB\", 'cus', 32)\n dly(296e-9)\n wac(\"EXT_MODE\", 0xc00d) # change to page ANA\n wac(\"OCP_MASK\", 0x01ff)\n wr(\"ANA_TRM_ACC_CH1\", n+256) # Set os_ch1; set sign_ch1 to 1\n rac(\"ANA_TRM_ACC_CH1\", n+256, 0x01ff) # Set os_ch1; set sign_ch1 to 1 \n wr(\"ANA_TRM_ACC_CH2\", n+256) # Set os_ch2; set sign_ch2 to 1\n rac(\"ANA_TRM_ACC_CH2\", n+256, 0x01ff) # Set os_ch2; set sign_ch2 to 1\n wr(\"ANA_TRM_ACC_CH3\", n+256) # Set os_ch3; set sign_ch3 to 1\n rac(\"ANA_TRM_ACC_CH3\", n+256, 0x01ff) # Set os_ch3; set sign_ch3 to 1\n wr(\"OCP_MASK\", 0x0000) # Reset masking register\n rac(\"OCP_MASK\", 0xffff) \n # Read ACC data\n wac(\"EXT_MODE\", 0xc002) # Access user register page/SHDW page\n dly(2e-3)\n cmt(f\"Burst read over 6 data registers and save in array NU_DCFB_{n:02d}\")\n bras(f\"NU_DCOFF1_{n:02d}\", \"ACC_DATA_X_LSB\", 6)\n # Convert 32-bit unsigned parameters NU_DCFB_a_n to signed parameters NS_DCFB_a_n\n calc(\"MSB\", f\"NU_DCOFF1_{n:02d}[1]\", '<<',16)\n calc(\"NU_MSB_LSB\", f\"NU_DCOFF1_{n:02d}[0]\", '+',\"MSB\")\n calc(f\"NS_DCOFF1_X_{n:02d}\", \"NU_MSB_LSB\", 'cus', 32)\n calc(\"MSB\", f\"NU_DCOFF1_{n:02d}[3]\", '<<',16)\n calc(\"NU_MSB_LSB\", f\"NU_DCOFF1_{n:02d}[2]\", '+',\"MSB\")\n calc(f\"NS_DCOFF1_Y_{n:02d}\", \"NU_MSB_LSB\", 'cus', 32)\n calc(\"MSB\", f\"NU_DCOFF1_{n:02d}[5]\", '<<',16)\n calc(\"NU_MSB_LSB\", f\"NU_DCOFF1_{n:02d}[4]\", '+',\"MSB\")\n calc(f\"NS_DCOFF1_Z_{n:02d}\", \"NU_MSB_LSB\", 'cus', 32)\n\nwac(\"EXT_MODE\", 0xc00e) # change to acc_afe page\nwac(\"ACC_TRM_CFB\", 0x7fff ) # Reset to default value\nwac(\"ACC_TRM_LOOPG\", 0x7fff) # Reset to default value\n\nwac(\"EXT_MODE\", 0xc00d) # change to page ANA\nwac(\"OCP_MASK\", 0x01ff)\nwr(\"ANA_TRM_ACC_CH1\", 0x0000) # Reset to default value\nrac(\"ANA_TRM_ACC_CH1\", 0x0000, 0x01ff)\nwr(\"ANA_TRM_ACC_CH2\", 0x0000) \nrac(\"ANA_TRM_ACC_CH2\", 0x0000, 0x01ff)\nwr(\"ANA_TRM_ACC_CH3\", 0x0000) \nrac(\"ANA_TRM_ACC_CH3\", 0x0000, 0x01ff)\nwr(\"OCP_MASK\", 0x0000) \nrac(\"OCP_MASK\", 0xffff) \n\n# Data evaluation and logging\n# Calculate XD_DCOFF_a_n = NS_DCOFF1_a_n - NS_DCOFF0_a_n, for every axis a = {X,Y,Z} and every setting n = {0,1,2,4,8,16,32,64,128}\n# Calculate XOFF_DCOFF_a_00 = (NS_DCOFF1_a_00 + NS_DCOFF0_a_00)/2 for every axis a = {X,Y,Z}\n# Calculate D_XOFF_DCOFF_a_n = (NS_DCOFF1_a_n + NS_DCOFF0_a_n)/2 - XOFF_DCOFF_a_00, for every axis a = {X,Y,Z} and every setting n = {1,2,4,8,16,32,64,128}\n# Calculate N_RATIO_DCOFF_a_02_01 = (NS_DCOFF1_a_02 - NS_DCOFF1_a_00) / (NS_DCOFF1_a_01 - NS_DCOFF1_a_00), for every axis a = {X,Y,Z}\n# Calculate N_RATIO_DCOFF_a_04_02 = (NS_DCOFF1_a_04 - NS_DCOFF1_a_00) / (NS_DCOFF1_a_02 - NS_DCOFF1_a_00), for every axis a = {X,Y,Z}\n# Calculate N_RATIO_DCOFF_a_08_04 = (NS_DCOFF1_a_08 - NS_DCOFF1_a_00) / (NS_DCOFF1_a_04 - NS_DCOFF1_a_00), for every axis a = {X,Y,Z}\n# Calculate N_RATIO_DCOFF_a_16_08 = (NS_DCOFF1_a_16 - NS_DCOFF1_a_00) / (NS_DCOFF1_a_08 - NS_DCOFF1_a_00), for every axis a = {X,Y,Z}\n# Calculate N_RATIO_DCOFF_a_32_16 = (NS_DCOFF1_a_32 - NS_DCOFF1_a_00) / (NS_DCOFF1_a_16 - NS_DCOFF1_a_00), for every axis a = {X,Y,Z}\n# Calculate N_RATIO_DCOFF_a_64_32 = (NS_DCOFF1_a_64 - NS_DCOFF1_a_00) / (NS_DCOFF1_a_32 - NS_DCOFF1_a_00), for every axis a = {X,Y,Z}\n# Calculate N_RATIO_DCOFF_a_128_64 = (NS_DCOFF1_a_128 - NS_DCOFF1_a_00) / (NS_DCOFF1_a_64 - NS_DCOFF1_a_00), for every axis a = {X,Y,Z}\n\nfor a in [\"X\", \"Y\", \"Z\"]:\n log(f\"XOFF_DCOFF_{a}_00\")\n log(f\"N_RATIO_DCOFF_{a}_02_01\")\n log(f\"N_RATIO_DCOFF_{a}_04_02\")\n log(f\"N_RATIO_DCOFF_{a}_08_04\")\n log(f\"N_RATIO_DCOFF_{a}_16_08\")\n log(f\"N_RATIO_DCOFF_{a}_32_16\")\n log(f\"N_RATIO_DCOFF_{a}_64_32\")\n log(f\"N_RATIO_DCOFF_{a}_128_64\")\n dly(296e-9)\n for n in [0, 1, 2, 4, 8, 16, 32, 64, 128]:\n log(f\"NS_DCOFF0_{a}_{n:03d}\")\n log(f\"NS_DCOFF1_{a}_{n:03d}\")\n log(f\"XD_DCOFF_{a}_{n:03d}\")\n log(f\"D_XOFF_DCOFF_{a}_{n:03d}\")\n dly(296e-9)\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T15_04_ACC_AFE_DCOFF_Test_R1: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n const string n_string[9] = {\"000\", \"001\", \"002\", \"004\", \"008\", \"016\", \"032\", \"064\", \"128\"};\n const string axis_string[3] = {\"X\", \"Y\", \"Z\"};\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n rdi.enableOre(oreFlag);\n rdi.oreFile(\"./ORE_Files/rdi_ore_T15_04_ACC_AFE_DCOFF_TEST.xml\");\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T15_04_ACC_AFE_DCOFF_Test_R1_PAT_id\");\n rdi.digCap(\"T15_04_ACC_AFE_DCOFF_Test_R1_Digcap_id\").label(s_label_name)\n .pin(\"SDO\").capMode(TA::SER).samples(16*108).bitPerWord(16)\n .execute();\n RDI_END();\n\n ON_FIRST_INVOCATION_END();\n ARRAY_I Vec=rdi.id(\"T15_04_ACC_AFE_DCOFF_Test_R1_Digcap_id\").getVector();\n\n int NU_DCOFF[2][9][6]; //[DCOFF0/DCOFF1][0/1/2/4/8/16/32/64/128][xx/yy/zz]\n int NS_DCOFF[2][9][3]; //[DCOFF0/DCOFF1][0/1/2/4/8/16/32/64/128][x/y/z]\n\n for (int j=0; j<9; j++)\n {\n \t for (int i=0; i<2; i++)\n \t {\n \t\t for (int k=0; k<6; k++)\n \t\t {\n \t\t\t NU_DCOFF[i][j][k] = reverse_ras_result(Vec[k+j*12+i*6]);\n// \t\t\t cout << \"NU_DCOFF\" + rdi.itos(i) + \"_\" + n_string[j] + \"[\" + rdi.itos(k) + \"] = Vec[\" << k+j*12+i*6 << \"]\"<< endl;\n \t\t\t FuncPrint(\"NU_DCOFF_\" + rdi.itos(i) + \"_\" + n_string[j] + \"_\"+ rdi.itos(k), NU_DCOFF[i][j][k]);\n \t\t }\n \t }\n }\n\n for (int j=0; j<9; j++)\n {\n \t for (int i=0; i<2; i++)\n \t {\n \t\t for (int k=0; k<3; k++)\n \t\t {\n \t\t\t NS_DCOFF[i][j][k] = i_Func_Unsigned_To_Signed((NU_DCOFF[i][j][k*2+1] << 16) + NU_DCOFF[i][j][k*2+0], 32);\n \t\t\t FuncPrint(\"NS_DCOFF\" + rdi.itos(i) + \"_\" + axis_string[k] + \"_\" + n_string[j] , NS_DCOFF[i][j][k]);\n \t\t }\n \t }\n }\n \n double XOFF_DCOFF_00[3];//[x/y/z]\n for (int i=0; i<3; i++)\n {\n \t XOFF_DCOFF_00[i] = NS_DCOFF[1][0][i] - NS_DCOFF[0][0][i];\n \t TestLog(\"XOFF_DCOFF_\" + axis_string[i] + \"_00\", XOFF_DCOFF_00[i]);\n \t FuncPrint(\"XOFF_DCOFF_\" + axis_string[i] + \"_00\", XOFF_DCOFF_00[i]);\n }\n\n double N_RATIO_DCOFF_002_001[3], N_RATIO_DCOFF_004_002[3], N_RATIO_DCOFF_008_004[3], N_RATIO_DCOFF_016_008[3], N_RATIO_DCOFF_032_016[3], N_RATIO_DCOFF_064_032[3], N_RATIO_DCOFF_128_064[3];\n for (int i=0; i<3; i++)\n {\n \t N_RATIO_DCOFF_002_001[i] = 1.000 * (NS_DCOFF[1][2][i] - NS_DCOFF[1][0][i]) / (NS_DCOFF[1][1][i] - NS_DCOFF[1][0][i]);\n \t N_RATIO_DCOFF_004_002[i] = 1.000 * (NS_DCOFF[1][3][i] - NS_DCOFF[1][0][i]) / (NS_DCOFF[1][2][i] - NS_DCOFF[1][0][i]);\n \t N_RATIO_DCOFF_008_004[i] = 1.000 * (NS_DCOFF[1][4][i] - NS_DCOFF[1][0][i]) / (NS_DCOFF[1][3][i] - NS_DCOFF[1][0][i]);\n \t N_RATIO_DCOFF_016_008[i] = 1.000 * (NS_DCOFF[1][5][i] - NS_DCOFF[1][0][i]) / (NS_DCOFF[1][4][i] - NS_DCOFF[1][0][i]);\n \t N_RATIO_DCOFF_032_016[i] = 1.000 * (NS_DCOFF[1][6][i] - NS_DCOFF[1][0][i]) / (NS_DCOFF[1][5][i] - NS_DCOFF[1][0][i]);\n \t N_RATIO_DCOFF_064_032[i] = 1.000 * (NS_DCOFF[1][7][i] - NS_DCOFF[1][0][i]) / (NS_DCOFF[1][6][i] - NS_DCOFF[1][0][i]);\n \t N_RATIO_DCOFF_128_064[i] = 1.000 * (NS_DCOFF[1][8][i] - NS_DCOFF[1][0][i]) / (NS_DCOFF[1][7][i] - NS_DCOFF[1][0][i]);\n\n \t TestLog(\"N_RATIO_DCOFF_\" + axis_string[i] + \"_002_001\", N_RATIO_DCOFF_002_001[i]);\n \t TestLog(\"N_RATIO_DCOFF_\" + axis_string[i] + \"_004_002\", N_RATIO_DCOFF_004_002[i]);\n \t TestLog(\"N_RATIO_DCOFF_\" + axis_string[i] + \"_008_004\", N_RATIO_DCOFF_008_004[i]);\n \t TestLog(\"N_RATIO_DCOFF_\" + axis_string[i] + \"_016_008\", N_RATIO_DCOFF_016_008[i]);\n \t TestLog(\"N_RATIO_DCOFF_\" + axis_string[i] + \"_032_016\", N_RATIO_DCOFF_032_016[i]);\n \t TestLog(\"N_RATIO_DCOFF_\" + axis_string[i] + \"_064_032\", N_RATIO_DCOFF_064_032[i]);\n \t TestLog(\"N_RATIO_DCOFF_\" + axis_string[i] + \"_128_064\", N_RATIO_DCOFF_128_064[i]);\n\n \t FuncPrint(\"N_RATIO_DCOFF_\" + axis_string[i] + \"_002_001\", N_RATIO_DCOFF_002_001[i]);\n \t FuncPrint(\"N_RATIO_DCOFF_\" + axis_string[i] + \"_004_002\", N_RATIO_DCOFF_004_002[i]);\n \t FuncPrint(\"N_RATIO_DCOFF_\" + axis_string[i] + \"_008_004\", N_RATIO_DCOFF_008_004[i]);\n \t FuncPrint(\"N_RATIO_DCOFF_\" + axis_string[i] + \"_016_008\", N_RATIO_DCOFF_016_008[i]);\n \t FuncPrint(\"N_RATIO_DCOFF_\" + axis_string[i] + \"_032_016\", N_RATIO_DCOFF_032_016[i]);\n \t FuncPrint(\"N_RATIO_DCOFF_\" + axis_string[i] + \"_064_032\", N_RATIO_DCOFF_064_032[i]);\n \t FuncPrint(\"N_RATIO_DCOFF_\" + axis_string[i] + \"_128_064\", N_RATIO_DCOFF_128_064[i]);\n }\n\n for (int j=0; j<9; j++)\n {\n \t for (int i=0; i<2; i++)\n \t {\n \t\t for (int k=0; k<3; k++)\n \t\t {\n \t\t\t TestLog(\"NS_DCOFF\" + rdi.itos(i) + \"_\" + axis_string[k] + \"_\" + n_string[j] , NS_DCOFF[i][j][k]);\n \t\t }\n \t }\n }\n\n double D_XOFF_DCOFF[9][3];//[0/1/2/4/8/16/32/64/128][x/y/z]\n double XOFF_DCOFF[9][3];//[0/1/2/4/8/16/32/64/128][x/y/z]\n double XD_DCOFF[9][3];//[0/1/2/4/8/16/32/64/128][x/y/z]\n\n for (int j=0; j<9; j++)\n {\n\t\t for (int k=0; k<3; k++)\n\t\t {\n\t\t\t XD_DCOFF[j][k] = 1.000 * (NS_DCOFF[1][j][k] - NS_DCOFF[0][j][k]);\n//\t\t\t D_XOFF_DCOFF[j][k] = 1.000 * (NS_DCOFF[1][j][k] + NS_DCOFF[0][j][k]) / 2 -\n\t\t\t TestLog(\"XD_DCOFF_\" + axis_string[k] + \"_\" + n_string[j], XD_DCOFF[j][k]);\n\t\t\t FuncPrint(\"XD_DCOFF_\" + axis_string[k] + \"_\" + n_string[j], XD_DCOFF[j][k]);\n\t\t }\n }\n\n\t for (int k=0; k<3; k++)\n\t {\n\t\t XOFF_DCOFF[0][k] = 1.000 * (NS_DCOFF[1][0][k] + NS_DCOFF[0][0][k]) / 2;\n\t }\n\n for (int j=0; j<9; j++)\n {\n\t\t for (int k=0; k<3; k++)\n\t\t {\n\t\t\t D_XOFF_DCOFF[j][k] = 1.000 * (NS_DCOFF[1][j][k] + NS_DCOFF[0][j][k]) / 2 - XOFF_DCOFF[0][k];\n\t\t\t TestLog(\"D_XOFF_DCOFF_\" + axis_string[k] + \"_\" + n_string[j], D_XOFF_DCOFF[j][k]);\n\t\t\t FuncPrint(\"D_XOFF_DCOFF_\" + axis_string[k] + \"_\" + n_string[j], D_XOFF_DCOFF[j][k]);\n\t\t }\n }\n\n int Func_result = rdi.id(\"T15_04_ACC_AFE_DCOFF_Test_R1_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T15_04_ACC_AFE_DCOFF_Test_R1\", T15_04_ACC_AFE_DCOFF_Test_R1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description:\n# - Reset DP\n# - Disable Sensor drive, disconnect mems, enable loopgain test mode\n# - Set DCFB to 0\n# - Set capacitive offset to 1, set sign to 0\n# - Set DGAIN to 0x3555\n# - loop through through all bits of ACC_TRM_LG and measure the acc output value \n#############################################################################################################\ncmt('Version info: $Revision: 1 $ $Author: hmf1rt $ $Date: 2024/03/13 13:36:52 GMT $')\n\n# Enable loopgain test mode\nwac('EXT_MODE',0xc00e) # AFE(acc afe) page\nwac(\"OCP_MASK\", 0x0200)\nwr('ACC_TEST_CTRL',0x0200) # acc_test_loopgain 1\nrac('ACC_TEST_CTRL',0x0200,0x0200) # Check register setting\nwr(\"OCP_MASK\", 0x0000) # Reset masking register\nrac(\"OCP_MASK\", 0xffff) # Check masking register reset\n\n# Set DCFB to 0\nwac(\"EXT_MODE\", 0xc00e) # change to page 14, ACC_AFE\nwac(\"OCP_MASK\", 0x7fff) # Set masking register\nwr(\"ACC_TRM_CFB\", 1024*0+32*0+0) # Set DCFB ch1/2/3 to 0\nrac(\"ACC_TRM_CFB\", 1024*0+32*0+0, 0x7fff) # Check register setting\nwr(\"OCP_MASK\", 0x0000) # Reset masking register\nrac(\"OCP_MASK\", 0xffff) # Check masking register reset \n\n# Set capacitive Offset to 1,sign to 0\nwac(\"EXT_MODE\", 0xc00d) # change to page ANA\nwac(\"OCP_MASK\", 0x01ff)\nwr(\"ANA_TRM_ACC_CH1\", 1) # Set acc_trm_os_ch1 to 1, set *sign_ch1 to 0\nwr(\"ANA_TRM_ACC_CH2\", 1) \nwr(\"ANA_TRM_ACC_CH3\", 1) \nrac(\"ANA_TRM_ACC_CH1\", 1, 0x01ff) \nrac(\"ANA_TRM_ACC_CH2\", 1, 0x01ff) \nrac(\"ANA_TRM_ACC_CH3\", 1, 0x01ff) \nwr(\"OCP_MASK\", 0x0000) # Reset masking register\nrac(\"OCP_MASK\", 0xffff) \n # TODO Check with Mr. Steffen\nfor n in [0, 1, 2, 4, 8, 16]:\n # Set DLG\n wac(\"EXT_MODE\", 0xc00e) # change to page 14, ACC_AFE\n wac(\"OCP_MASK\", 0x7fff) # Set masking register\n wr(\"ACC_TRM_LOOPG\", 1024*n+32*n+n) # Set DLG ch1/2/3\n rac(\"ACC_TRM_LOOPG\", 1024*n+32*n+n, 0x7fff) # Check register setting\n wr(\"OCP_MASK\", 0x0000) # Reset masking register\n rac(\"OCP_MASK\", 0xffff) # Check masking register reset \n # Read ACC data\n wac(\"EXT_MODE\", 0xc002) # Access user register page/SHDW page\n dly(2e-3)\n cmt(f\"Burst read over 6 data registers and save in array NU_DLG_{n:02d}\")\n bras(f\"NU_DLG_{n:02d}\", \"ACC_DATA_X_LSB\", 6)\n # Convert 32-bit unsigned parameters NU_DLG_a_n to signed parameters NS_DLG_a_n\n calc(\"MSB\", f\"NU_DLG_{n:02d}[1]\", '<<',16)\n calc(\"NU_DLG\", f\"NU_DLG_{n:02d}[0]\", '+',\"MSB\")\n calc(f\"NS_DLG_X_{n:02d}\", \"NU_DLG\", 'cus', 32)\n dly(296e-9)\n calc(\"MSB\", f\"NU_DLG_{n:02d}[3]\", '<<',16)\n calc(\"NU_DLG\", f\"NU_DLG_{n:02d}[2]\", '+',\"MSB\")\n calc(f\"NS_DLG_Y_{n:02d}\", \"NU_DLG\", 'cus', 32)\n dly(296e-9)\n calc(\"MSB\", f\"NU_DLG_{n:02d}[5]\", '<<',16)\n calc(\"NU_DLG\", f\"NU_DLG_{n:02d}[4]\", '+',\"MSB\")\n calc(f\"NS_DLG_Z_{n:02d}\", \"NU_DLG\", 'cus', 32)\n dly(296e-9)\nwac('EXT_MODE',0xc00e) \t\t\t# AFE(acc afe) page\nwac(\"OCP_MASK\", 0x0e00)\nwr('ACC_TRM_CTRL', 0x0e00) # gmboost=1\nrac('ACC_TRM_CTRL', 0x0e00, 0x0e00)\nwr(\"OCP_MASK\", 0x0000) \nrac(\"OCP_MASK\", 0xffff) \n\n# Read ACC data\nwac(\"EXT_MODE\", 0xc002) # Access user register page/SHDW page\ndly(2e-3)\ncmt(f\"Burst read over 6 data registers and save in array NU_DLG_32\")\nbras(f\"NU_DLG_32\", \"ACC_DATA_X_LSB\", 6)\n# Convert 32-bit unsigned parameters NU_DLG_a_n to signed parameters NS_DLG_a_n\ncalc(\"MSB\", f\"NU_DLG_32[1]\", '<<',16)\ncalc(\"NU_DLG\", f\"NU_DLG_32[0]\", '+',\"MSB\")\ncalc(f\"NS_DLG_X_32\", \"NU_DLG\", 'cus', 32)\ndly(296e-9) \ncalc(\"MSB\", f\"NU_DLG_32[3]\", '<<',16)\ncalc(\"NU_DLG\", f\"NU_DLG_32[2]\", '+',\"MSB\")\ncalc(f\"NS_DLG_Y_32\", \"NU_DLG\", 'cus', 32)\ndly(296e-9)\ncalc(\"MSB\", f\"NU_DLG_32[5]\", '<<',16)\ncalc(\"NU_DLG\", f\"NU_DLG_32[4]\", '+',\"MSB\")\ncalc(f\"NS_DLG_Z_32\", \"NU_DLG\", 'cus', 32)\ndly(296e-9)\n\nwac('EXT_MODE',0xc00e) \t\t\t# AFE(acc afe) page\nwac(\"OCP_MASK\", 0x0e00)\nwr('ACC_TRM_CTRL', 0x0000) # gmboost=0\nrac('ACC_TRM_CTRL', 0x0000, 0x0e00)\nwr(\"OCP_MASK\", 0x0000) \nrac(\"OCP_MASK\", 0xffff) \n\nwac(\"EXT_MODE\", 0xc00e) # change to page 14, ACC_AFE\nwac(\"ACC_TRM_LOOPG\", 0x7fff) # back to reset value\nwac(\"ACC_TRM_CFB\", 0x7fff) # back to reset value\nwac(\"OCP_MASK\", 0x0200)\nwr('ACC_TEST_CTRL',0x0000) # acc_test_loopgain 1\nrac('ACC_TEST_CTRL',0x0000,0x0200) # Check register setting\nwr(\"OCP_MASK\", 0x0000) # Reset masking register\nrac(\"OCP_MASK\", 0xffff) # Check masking register reset\n\nwac(\"EXT_MODE\", 0xc00d) # change to page ANA\nwac(\"OCP_MASK\", 0x01ff)\nwr(\"ANA_TRM_ACC_CH1\", 0x0000) # Reset to default value\nrac(\"ANA_TRM_ACC_CH1\", 0x0000, 0x01ff)\nwr(\"ANA_TRM_ACC_CH2\", 0x0000) \nrac(\"ANA_TRM_ACC_CH2\", 0x0000, 0x01ff)\nwr(\"ANA_TRM_ACC_CH3\", 0x0000) \nrac(\"ANA_TRM_ACC_CH3\", 0x0000, 0x01ff)\nwr(\"OCP_MASK\", 0x0000) \nrac(\"OCP_MASK\", 0xffff) \n\n# Data evaluation and logging\n# Calculate N_RATIO_DLG_a_02_01 = (1.0/NS_DLG_a_02 - 1.0/NS_DLG_a_00) / (1.0/NS_DLG_a_01 - 1.0/NS_DLG_a_00), for every axis a = {X,Y,Z}\n# Calculate N_RATIO_DLG_a_04_02 = (1.0/NS_DLG_a_04 - 1.0/NS_DLG_a_00) / (1.0/NS_DLG_a_02 - 1.0/NS_DLG_a_00), for every axis a = {X,Y,Z}\n# Calculate N_RATIO_DLG_a_08_04 = (1.0/NS_DLG_a_08 - 1.0/NS_DLG_a_00) / (1.0/NS_DLG_a_04 - 1.0/NS_DLG_a_00), for every axis a = {X,Y,Z}\n# Calculate N_RATIO_DLG_a_16_08 = (1.0/NS_DLG_a_16 - 1.0/NS_DLG_a_00) / (1.0/NS_DLG_a_08 - 1.0/NS_DLG_a_00), for every axis a = {X,Y,Z}\n# Calculate N_RATIO_DLG_a_32_16 = (1.0/NS_DLG_a_32 - 1.0/NS_DLG_a_00) / (1.0/NS_DLG_a_16 - 1.0/NS_DLG_a_00), for every axis a = {X,Y,Z}\n\nfor a in [\"X\", \"Y\", \"Z\"]:\n log(f\"N_RATIO_DLG_{a}_02_01\")\n log(f\"N_RATIO_DLG_{a}_04_02\")\n log(f\"N_RATIO_DLG_{a}_08_04\")\n log(f\"N_RATIO_DLG_{a}_16_08\")\n log(f\"N_RATIO_DLG_{a}_32_16\")\n dly(296e-9)\n for n in [0, 1, 2, 4, 8, 16, 32]:\n log(f\"NS_DLG_{a}_{n:02d}\")\n dly(296e-9)\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T15_08_ACC_AFE_DLG_Test_R1: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n const string n_string[7] = {\"00\", \"01\", \"02\", \"04\", \"08\", \"16\", \"32\"};\n const string axis_string[3] = {\"X\", \"Y\", \"Z\"};\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n rdi.enableOre(oreFlag);\n rdi.oreFile(\"./ORE_Files/rdi_ore_T15_08_ACC_AFE_DLG_TEST.xml\");\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T15_08_ACC_AFE_DLG_Test_R1_PAT_id\");\n rdi.digCap(\"T15_08_ACC_AFE_DLG_Test_R1_Digcap_id\").label(s_label_name)\n .pin(\"SDO\").capMode(TA::SER).samples(16*42).bitPerWord(16)\n .execute();\n RDI_END();\n\n // Auto_Code_Execution_Part\n\n\n\n ON_FIRST_INVOCATION_END();\n ARRAY_I Vec=rdi.id(\"T15_08_ACC_AFE_DLG_Test_R1_Digcap_id\").getVector();\n\n int NU_DLG[7][6];//[0/1/2/4/8/16/32][xx/yy/zz]\n int NS_DLG[7][3];//[0/1/2/4/8/16/32][x/y/z]\n\n for (int i=0; i<7; i++)\n {\n \t for (int j=0; j<6; j++)\n \t {\n \t\t NU_DLG[i][j] = reverse_ras_result(Vec[i*6+j]);\n//\t\t\t cout << \"NU_DLG_\" + n_string[i] + \"[\" + rdi.itos(j) + \"] = Vec[\" << i*6+j << \"]\"<< endl;\n \t\t FuncPrint(\"NU_DLG_\" + n_string[i] + \"_\"+ rdi.itos(j), NU_DLG[i][j]);\n \t }\n }\n\n for (int i=0; i<7; i++)\n {\n \t for (int j=0; j<3; j++)\n \t {\n \t\t NS_DLG[i][j] = i_Func_Unsigned_To_Signed((NU_DLG[i][j*2+1] << 16) + NU_DLG[i][j*2+0], 32);\n \t\t TestLog(\"NS_DLG_\" + axis_string[j] + \"_\"+ n_string[i], NS_DLG[i][j]);\n \t\t FuncPrint(\"NS_DLG_\" + axis_string[j] + \"_\"+ n_string[i], NS_DLG[i][j]);\n \t }\n }\n \n double N_RATIO_DLG_02_01[3], N_RATIO_DLG_04_02[3], N_RATIO_DLG_08_04[3], N_RATIO_DLG_16_08[3], N_RATIO_DLG_32_16[3];//[x/y/z]\n for (int i=0; i<3; i++)\n {\n \t N_RATIO_DLG_02_01[i] = (1.000/NS_DLG[2][i] - 1.000/NS_DLG[0][i]) / (1.000/NS_DLG[1][i] - 1.000/NS_DLG[0][i]);\n \t N_RATIO_DLG_04_02[i] = (1.000/NS_DLG[3][i] - 1.000/NS_DLG[0][i]) / (1.000/NS_DLG[2][i] - 1.000/NS_DLG[0][i]);\n \t N_RATIO_DLG_08_04[i] = (1.000/NS_DLG[4][i] - 1.000/NS_DLG[0][i]) / (1.000/NS_DLG[3][i] - 1.000/NS_DLG[0][i]);\n \t N_RATIO_DLG_16_08[i] = (1.000/NS_DLG[5][i] - 1.000/NS_DLG[0][i]) / (1.000/NS_DLG[4][i] - 1.000/NS_DLG[0][i]);\n \t N_RATIO_DLG_32_16[i] = (1.000/NS_DLG[6][i] - 1.000/NS_DLG[0][i]) / (1.000/NS_DLG[5][i] - 1.000/NS_DLG[0][i]);\n\n \t TestLog(\"N_RATIO_DLG_\" + axis_string[i] + \"_02_01\", N_RATIO_DLG_02_01[i]);\n \t TestLog(\"N_RATIO_DLG_\" + axis_string[i] + \"_04_02\", N_RATIO_DLG_04_02[i]);\n \t TestLog(\"N_RATIO_DLG_\" + axis_string[i] + \"_08_04\", N_RATIO_DLG_08_04[i]);\n \t TestLog(\"N_RATIO_DLG_\" + axis_string[i] + \"_16_08\", N_RATIO_DLG_16_08[i]);\n \t TestLog(\"N_RATIO_DLG_\" + axis_string[i] + \"_32_16\", N_RATIO_DLG_32_16[i]);\n\n \t FuncPrint(\"N_RATIO_DLG_\" + axis_string[i] + \"_02_01\", N_RATIO_DLG_02_01[i]);\n \t FuncPrint(\"N_RATIO_DLG_\" + axis_string[i] + \"_04_02\", N_RATIO_DLG_04_02[i]);\n \t FuncPrint(\"N_RATIO_DLG_\" + axis_string[i] + \"_08_04\", N_RATIO_DLG_08_04[i]);\n \t FuncPrint(\"N_RATIO_DLG_\" + axis_string[i] + \"_16_08\", N_RATIO_DLG_16_08[i]);\n \t FuncPrint(\"N_RATIO_DLG_\" + axis_string[i] + \"_32_16\", N_RATIO_DLG_32_16[i]);\n }\n\n\n int Func_result = rdi.id(\"T15_08_ACC_AFE_DLG_Test_R1_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n // Auto_Code_Judge_and_log\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T15_08_ACC_AFE_DLG_Test_R1\", T15_08_ACC_AFE_DLG_Test_R1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description:\n# - test each bit of dcoff dac\n#############################################################################################################\ncmt('Version info: $Revision: bai430aa_rel/2 $ $Author: luz3sgh $ $Date: 2024/07/23 05:38:30 GMT $')\n\nwac('EXT_MODE',0xc00d) # ANA page\nwac(\"OCP_MASK\", 0x1fff)\nwr('ANA_TRM_ACC_CH1',0x0000) # Set Offset, off_Sign, C0 to 0 \nrac('ANA_TRM_ACC_CH1',0x0000,0x1fff) \nwr('ANA_TRM_ACC_CH2',0x0000) # Set Offset, off_Sign, C0 to 0 \nrac('ANA_TRM_ACC_CH2',0x0000,0x1fff) \nwr('ANA_TRM_ACC_CH3',0x0000) # Set Offset, off_Sign, C0 to 0\nrac('ANA_TRM_ACC_CH3',0x0000,0x1fff) \nwr(\"OCP_MASK\", 0x0000) # Reset masking register\nrac(\"OCP_MASK\", 0xffff) # Check masking register reset\n\n# Set DCFB\nwac(\"EXT_MODE\", 0xc00e) # change to page 14, ACC_AFE\nwac(\"OCP_MASK\", 0x7fff) # Set masking register\nwr(\"ACC_TRM_CFB\", 1024*7+32*7+7) # Set DCFB ch1/2/3 to 7\nrac(\"ACC_TRM_CFB\", 1024*7+32*7+7, 0x7fff) # Check register setting\nwr(\"ACC_TRM_LOOPG\", 1024*8+32*8+8) # Set DLG ch1/2/3 to 23\nrac(\"ACC_TRM_LOOPG\", 1024*8+32*8+8, 0x7fff) # Check register setting\nwr(\"OCP_MASK\", 0x0000) # Reset masking register\nrac(\"OCP_MASK\", 0xffff) # Check masking register reset \n\nwac('EXT_MODE',0xc000) # User page\nwac('ACC_CONF', 0x804e) # Enable ACC in NORM; set AFS=32g; set ODR=3200; set BW=AUTO\n\nwac(\"EXT_MODE\", 0xc002) # Access user register page/SHDW page\ndly(2e-3)\nfor n in range(30): # cosier of 7bits width\n # Read ACC data\n dly(800e-6)\n cmt(f\"Burst read over 6 data registers and save in array NU_ACCALPN_{n:02d}\")\n bras(f\"NU_ACCALPN_{n:02d}\", \"ACC_DATA_X_LSB\", 6)\n # Convert 32-bit unsigned parameters NU_ACCALPN_a_n to signed parameters NS_ACCALPN_a_n\n calc(\"MSB\", f\"NU_ACCALPN_{n:02d}[1]\", '<<',16)\n calc(\"NU_MSB_LSB\", f\"NU_ACCALPN_{n:02d}[0]\", '+',\"MSB\")\n calc(f\"NS_ACCALPN_X_{n:02d}\", \"NU_MSB_LSB\", 'cus', 32)\n dly(296e-9)\n calc(\"MSB\", f\"NU_ACCALPN_{n:02d}[3]\", '<<',16)\n calc(\"NU_MSB_LSB\", f\"NU_ACCALPN_{n:02d}[2]\", '+',\"MSB\")\n calc(f\"NS_ACCALPN_Y_{n:02d}\", \"NU_MSB_LSB\", 'cus', 32)\n dly(296e-9)\n calc(\"MSB\", f\"NU_ACCALPN_{n:02d}[5]\", '<<',16)\n calc(\"NU_MSB_LSB\", f\"NU_ACCALPN_{n:02d}[4]\", '+',\"MSB\")\n calc(f\"NS_ACCALPN_Z_{n:02d}\", \"NU_MSB_LSB\", 'cus', 32)\n dly(296e-9)\nwac('EXT_MODE',0xc000) # User page\nwac('ACC_CONF', 0xe04e) # Enable ACC in HPM; set AFS=32g; set ODR=3200; set BW=AUTO\n\nwac(\"EXT_MODE\", 0xc002) # Access user register page/SHDW page\ndly(2e-3)\nfor n in range(30): # cosier of 7bits width\n # Read ACC data\n dly(800e-6)\n cmt(f\"Burst read over 6 data registers and save in array NU_ACCN_{n:02d}\")\n bras(f\"NU_ACCN_{n:02d}\", \"ACC_DATA_X_LSB\", 6)\n # Convert 32-bit unsigned parameters NU_ACCN_a_n to signed parameters NS_ACCN_a_n\n calc(\"MSB\", f\"NU_ACCN_{n:02d}[1]\", '<<',16)\n calc(\"NU_MSB_LSB\", f\"NU_ACCN_{n:02d}[0]\", '+',\"MSB\")\n calc(f\"NS_ACCN_X_{n:02d}\", \"NU_MSB_LSB\", 'cus', 32)\n dly(296e-9)\n calc(\"MSB\", f\"NU_ACCN_{n:02d}[3]\", '<<',16)\n calc(\"NU_MSB_LSB\", f\"NU_ACCN_{n:02d}[2]\", '+',\"MSB\")\n calc(f\"NS_ACCN_Y_{n:02d}\", \"NU_MSB_LSB\", 'cus', 32)\n dly(296e-9)\n calc(\"MSB\", f\"NU_ACCN_{n:02d}[5]\", '<<',16)\n calc(\"NU_MSB_LSB\", f\"NU_ACCN_{n:02d}[4]\", '+',\"MSB\")\n calc(f\"NS_ACCN_Z_{n:02d}\", \"NU_MSB_LSB\", 'cus', 32)\n dly(296e-9)\nwac('EXT_MODE',0xc00e) \t\t\t# AFE(acc afe) page\nwac(\"OCP_MASK\", 0x0e00)\nwr('ACC_TRM_CTRL', 0x0e00) # gmboost=1\nrac('ACC_TRM_CTRL', 0x0e00, 0x0e00)\nwr(\"OCP_MASK\", 0x0000) \nrac(\"OCP_MASK\", 0xffff) \n\nwac(\"EXT_MODE\", 0xc002) # Access user register page/SHDW page\ndly(2e-3)\nfor n in range(30): # cosier of 7bits width\n # Read ACC data\n dly(800e-6)\n cmt(f\"Burst read over 6 data registers and save in array NU_ACCGMN_{n:02d}\")\n bras(f\"NU_ACCGMN_{n:02d}\", \"ACC_DATA_X_LSB\", 6)\n # Convert 32-bit unsigned parameters NU_ACCGMN_a_n to signed parameters NS_ACCGMN_a_n\n calc(\"MSB\", f\"NU_ACCGMN_{n:02d}[1]\", '<<',16)\n calc(\"NU_MSB_LSB\", f\"NU_ACCGMN_{n:02d}[0]\", '+',\"MSB\")\n calc(f\"NS_ACCGMN_X_{n:02d}\", \"NU_MSB_LSB\", 'cus', 32)\n dly(296e-9)\n calc(\"MSB\", f\"NU_ACCGMN_{n:02d}[3]\", '<<',16)\n calc(\"NU_MSB_LSB\", f\"NU_ACCGMN_{n:02d}[2]\", '+',\"MSB\")\n calc(f\"NS_ACCGMN_Y_{n:02d}\", \"NU_MSB_LSB\", 'cus', 32)\n dly(296e-9)\n calc(\"MSB\", f\"NU_ACCGMN_{n:02d}[5]\", '<<',16)\n calc(\"NU_MSB_LSB\", f\"NU_ACCGMN_{n:02d}[4]\", '+',\"MSB\")\n calc(f\"NS_ACCGMN_Z_{n:02d}\", \"NU_MSB_LSB\", 'cus', 32)\n dly(296e-9)\nwac('EXT_MODE',0xc00e) \t\t\t# AFE(acc afe) page\nwac(\"OCP_MASK\", 0x0e00)\nwr('ACC_TRM_CTRL', 0x0000) # gmboost=0\nrac('ACC_TRM_CTRL', 0x0000, 0x0e00)\nwr(\"OCP_MASK\", 0x0000) \nrac(\"OCP_MASK\", 0xffff) \n\n\n\nwac(\"OCP_MASK\", 0x0020)\nwr('ACC_TEST_CTRL', 0x0020) # test_az=1\nrac('ACC_TEST_CTRL', 0x0020, 0x0020)\nwr(\"OCP_MASK\", 0x0000) \nrac(\"OCP_MASK\", 0xffff) \n\nwac(\"EXT_MODE\", 0xc002) # Access user register page/SHDW page\ndly(2e-3)\nfor n in range(30): # cosier of 7bits width\n # Read ACC data\n dly(800e-6)\n cmt(f\"Burst read over 6 data registers and save in array NU_ACCAZN_{n:02d}\")\n bras(f\"NU_ACCAZN_{n:02d}\", \"ACC_DATA_X_LSB\", 6)\n # Convert 32-bit unsigned parameters NU_ACCAZN_a_n to signed parameters NS_ACCAZN_a_n\n calc(\"MSB\", f\"NU_ACCAZN_{n:02d}[1]\", '<<',16)\n calc(\"NU_MSB_LSB\", f\"NU_ACCAZN_{n:02d}[0]\", '+',\"MSB\")\n calc(f\"NS_ACCAZN_X_{n:02d}\", \"NU_MSB_LSB\", 'cus', 32)\n dly(296e-9)\n calc(\"MSB\", f\"NU_ACCAZN_{n:02d}[3]\", '<<',16)\n calc(\"NU_MSB_LSB\", f\"NU_ACCAZN_{n:02d}[2]\", '+',\"MSB\")\n calc(f\"NS_ACCAZN_Y_{n:02d}\", \"NU_MSB_LSB\", 'cus', 32)\n dly(296e-9)\n calc(\"MSB\", f\"NU_ACCAZN_{n:02d}[5]\", '<<',16)\n calc(\"NU_MSB_LSB\", f\"NU_ACCAZN_{n:02d}[4]\", '+',\"MSB\")\n calc(f\"NS_ACCAZN_Z_{n:02d}\", \"NU_MSB_LSB\", 'cus', 32)\n dly(296e-9)\nwac('EXT_MODE',0xc00e) \t\t\t# AFE(acc afe) page\nwac(\"OCP_MASK\", 0x0020)\nwr('ACC_TEST_CTRL', 0x0000) # test_az=0\nrac('ACC_TEST_CTRL', 0x0000, 0x0020)\nwr(\"OCP_MASK\", 0x0000) \nrac(\"OCP_MASK\", 0xffff) \n\n# Set DCFB\nwac(\"OCP_MASK\", 0x7fff) # Set masking register\nwr(\"ACC_TRM_CFB\", 1024*0+32*0+0) # Set DCFB ch1/2/3 to 0\nrac(\"ACC_TRM_CFB\", 1024*0+32*0+0, 0x7fff) # Check register setting\nwr(\"ACC_TRM_LOOPG\", 1024*31+32*31+31) # Set DLG ch1/2/3 to 31\nrac(\"ACC_TRM_LOOPG\", 1024*31+32*31+31, 0x7fff) # Check register setting\nwr(\"OCP_MASK\", 0x0000) # Reset masking register\nrac(\"OCP_MASK\", 0xffff) # Check masking register reset \n\nwac('EXT_MODE',0xc000) # User page\nwac('ACC_CONF', 0x804e) # Enable ACC in NORM; set AFS=32g; set ODR=3200; set BW=AUTO\n\nwac(\"EXT_MODE\", 0xc002) # Access user register page/SHDW page\ndly(2e-3)\nfor n in range(30): # cosier of 7bits width\n # Read ACC data\n dly(800e-6)\n cmt(f\"Burst read over 6 data registers and save in array NU_ACCALPN_{n:02d}\")\n bras(f\"NU_ACCS_{n:02d}\", \"ACC_DATA_X_LSB\", 6)\n # Convert 32-bit unsigned parameters NU_ACCS_a_n to signed parameters NS_ACCS_a_n\n calc(\"MSB\", f\"NU_ACCS_{n:02d}[1]\", '<<',16)\n calc(\"NU_MSB_LSB\", f\"NU_ACCS_{n:02d}[0]\", '+',\"MSB\")\n calc(f\"NS_ACCS_X_{n:02d}\", \"NU_MSB_LSB\", 'cus', 32)\n dly(296e-9)\n calc(\"MSB\", f\"NU_ACCS_{n:02d}[3]\", '<<',16)\n calc(\"NU_MSB_LSB\", f\"NU_ACCS_{n:02d}[2]\", '+',\"MSB\")\n calc(f\"NS_ACCS_Y_{n:02d}\", \"NU_MSB_LSB\", 'cus', 32)\n dly(296e-9)\n calc(\"MSB\", f\"NU_ACCS_{n:02d}[5]\", '<<',16)\n calc(\"NU_MSB_LSB\", f\"NU_ACCS_{n:02d}[4]\", '+',\"MSB\")\n calc(f\"NS_ACCS_Z_{n:02d}\", \"NU_MSB_LSB\", 'cus', 32)\n dly(296e-9)\nwac('EXT_MODE',0xc000) # User page\nwac('ACC_CONF', 0xe04e) # Enable ACC in HPM; set AFS=32g; set ODR=3200; set BW=AUTO\n\n\nwac(\"EXT_MODE\", 0xc00e) # change to acc_afe page\nwac(\"ACC_TRM_CFB\", 0x7fff ) # Reset to default value\nwac(\"ACC_TRM_LOOPG\", 0x7fff) # Reset to default value\n\nwac(\"EXT_MODE\", 0xc00d) # change to page ANA\nwac(\"OCP_MASK\", 0x01ff)\nwr(\"ANA_TRM_ACC_CH1\", 0x0000) # Reset to default value\nrac(\"ANA_TRM_ACC_CH1\", 0x0000, 0x01ff)\nwr(\"ANA_TRM_ACC_CH2\", 0x0000) \nrac(\"ANA_TRM_ACC_CH2\", 0x0000, 0x01ff)\nwr(\"ANA_TRM_ACC_CH3\", 0x0000) \nrac(\"ANA_TRM_ACC_CH3\", 0x0000, 0x01ff)\nwr(\"OCP_MASK\", 0x0000) \nrac(\"OCP_MASK\", 0xffff) \n\n# Data evaluation and logging\n# Calculate mean value MEAN_ACCALPN_a, MEAN_ACCN_a, MEAN_ACCGMN_a and MEAN_ACCAZN_a\n# Calculate MEAN_ACCALPN_a = SUMn(NS_ACCALPN_a_n)/30, for every axis a = {X,Y,Z}\n# Calculate MEAN_ACCN_a = SUMn(NS_ACCN_a_n)/30, for every axis a = {X,Y,Z} \n# Calculate MEAN_ACCGMN_a = SUMn(NS_ACCGMN_a_n)/30, for every axis a = {X,Y,Z} \n# Calculate MEAN_ACCAZN_a = SUMn(NS_ACCAZN_a_n)/30, for every axis a = {X,Y,Z}\n# Calculate MEAN_ACCS_a = SUMn(NS_ACCS_a_n)/30, for every axis a = {X,Y,Z}\n\n# Calculate the standard deviation SD_ACCAZN_a, SD_ACCN_a, SD_ACCGMN_a and SD_ACCAZN_a\n# Calculate SD_ACCALPN_a = SQRT(SUMn((NS_ACCALPN_a_n-MEAN_ACCALPN_a)^2)/29), for every axis a = {X,Y,Z} \n# Calculate SD_ACCN_a = SQRT(SUMn((NS_ACCN_a_n-MEAN_ACCN_a)^2)/29), for every axis a = {X,Y,Z} \n# Calculate SD_ACCGMN_a = SQRT(SUMn((NS_ACCGMN_a_n-MEAN_ACCGMN_a)^2)/29), for every axis a = {X,Y,Z} \n# Calculate SD_ACCAZN_a = SQRT(SUMn((NS_ACCAZN_a_n-MEAN_ACCAZN_a)^2)/29), for every axis a = {X,Y,Z} \n# Calculate SD_ACCS_a = SQRT(SUMn((NS_ACCS_a_n-MEAN_ACCS_a)^2)/29), for every axis a = {X,Y,Z} \n\nfor a in [\"X\", \"Y\", \"Z\"]:\n log(f\"MEAN_ACCALPN_{a}\")\n log(f\"MEAN_ACCN_{a}\")\n log(f\"MEAN_ACCGMN_{a}\")\n log(f\"MEAN_ACCAZN_{a}\")\n log(f\"MEAN_ACCS_{a}\")\n log(f\"SD_ACCALPN_{a}\")\n log(f\"SD_ACCN_{a}\")\n log(f\"SD_ACCGMN_{a}\")\n log(f\"SD_ACCAZN_{a}\")\n log(f\"SD_ACCS_{a}\")\n dly(296e-9)\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T15_12_ACC_AFE_CBIST_Noise_Test_R2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n const string axis_string[3] = {\"X\", \"Y\", \"Z\"};\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n rdi.enableOre(oreFlag);\n rdi.oreFile(\"./ORE_Files/rdi_ore_T15_12_ACC_AFE_CBIST_NOISE_TEST.xml\");\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T15_12_ACC_AFE_CBIST_Noise_Test_R2_PAT_id\");\n rdi.digCap(\"T15_12_ACC_AFE_CBIST_Noise_Test_R2_Digcap_id\").label(s_label_name)\n .pin(\"SDO\").capMode(TA::SER).samples(16*900).bitPerWord(16)\n .execute();\n RDI_END();\n\n // Auto_Code_Execution_Part\n\n\n\n ON_FIRST_INVOCATION_END();\n ARRAY_I Vec=rdi.id(\"T15_12_ACC_AFE_CBIST_Noise_Test_R2_Digcap_id\").getVector();\n\n long long NU_ACCALPN[30][6], NU_ACCN[30][6], NU_ACCGMN[30][6], NU_ACCAZN[30][6], NU_ACCS[30][6];\n double NS_ACCALPN[3][30], NS_ACCN[3][30], NS_ACCGMN[3][30], NS_ACCAZN[3][30], NS_ACCS[3][30];\n\n for (int i=0; i<30; i++)\n {\n \t for (int j=0; j<6; j++)\n \t {\n \t\t NU_ACCALPN[i][j] = reverse_ras_result(Vec[i*6+j]);\n \t\t NU_ACCN[i][j] = reverse_ras_result(Vec[i*6+j+180]);\n \t\t NU_ACCGMN[i][j] = reverse_ras_result(Vec[i*6+j+180*2]);\n \t\t NU_ACCAZN[i][j] = reverse_ras_result(Vec[i*6+j+180*3]);\n \t\t NU_ACCS[i][j] = reverse_ras_result(Vec[i*6+j+180*4]);\n\n//\t\t\t cout << \"NU_ACCALPN_\" + rdi.itos(i) + \"[\" + rdi.itos(j) + \"] = Vec[\" << i*6+j << \"]\"<< endl;\n// \t\t cout << \"NU_ACCN_\" + rdi.itos(i) + \"[\" + rdi.itos(j) + \"] = Vec[\" << i*6+j+180 << \"]\"<< endl;\n// \t\t cout << \"NU_ACCGMN_\" + rdi.itos(i) + \"[\" + rdi.itos(j) + \"] = Vec[\" << i*6+j+180*2 << \"]\"<< endl;\n// \t\t cout << \"NU_ACCAZN_\" + rdi.itos(i) + \"[\" + rdi.itos(j) + \"] = Vec[\" << i*6+j+180*3 << \"]\"<< endl;\n// \t\t cout << \"NU_ACCS_\" + rdi.itos(i) + \"[\" + rdi.itos(j) + \"] = Vec[\" << i*6+j+180*4 << \"]\"<< endl;\n// \t\t FuncPrint(\"NU_ACCALPN_\" + rdi.itos(i) + \"_\"+ rdi.itos(j), NU_ACCALPN[i][j]);\n \t }\n }\n\n for (int i=0; i<30; i++)\n {\n \t for (int j=0; j<6; j++)\n \t {\n// \t\t FuncPrint(\"NU_ACCALPN_\" + rdi.itos(i) + \"_\"+ rdi.itos(j), NU_ACCALPN[i][j]);\n// \t\t FuncPrint(\"NU_ACCN_\" + rdi.itos(i) + \"_\"+ rdi.itos(j), NU_ACCN[i][j]);\n// \t\t FuncPrint(\"NU_ACCGMN_\" + rdi.itos(i) + \"_\"+ rdi.itos(j), NU_ACCGMN[i][j]);\n// \t\t FuncPrint(\"NU_ACCAZN_\" + rdi.itos(i) + \"_\"+ rdi.itos(j), NU_ACCAZN[i][j]);\n// \t\t FuncPrint(\"NU_ACCS_\" + rdi.itos(i) + \"_\"+ rdi.itos(j), NU_ACCS[i][j]);\n \t }\n\n }\n\n for (int i=0; i<30; i++)\n {\n \t for (int j=0; j<3; j++)\n \t {\n \t\t NS_ACCALPN[j][i] = i_Func_Unsigned_To_Signed((NU_ACCALPN[i][j*2+1] << 16) + NU_ACCALPN[i][j*2+0], 32);\n \t\t NS_ACCN[j][i] = i_Func_Unsigned_To_Signed((NU_ACCN[i][j*2+1] << 16) + NU_ACCN[i][j*2+0], 32);\n \t\t NS_ACCGMN[j][i] = i_Func_Unsigned_To_Signed((NU_ACCGMN[i][j*2+1] << 16) + NU_ACCGMN[i][j*2+0], 32);\n \t\t NS_ACCAZN[j][i] = i_Func_Unsigned_To_Signed((NU_ACCAZN[i][j*2+1] << 16) + NU_ACCAZN[i][j*2+0], 32);\n \t\t NS_ACCS[j][i] = i_Func_Unsigned_To_Signed((NU_ACCS[i][j*2+1] << 16) + NU_ACCS[i][j*2+0], 32);\n\n// \t\t FuncPrint(\"NS_ACCALPN_\" + rdi.itos(i) + \"[\" + rdi.itos(j) + \"]\", NS_ACCALPN[i][j]);\n \t }\n \t FuncPrint(\"NS_ACCALPN_X_\"+rdi.itos(i), NS_ACCALPN[0][i]);\n }\n\n for (int i=0; i<30; i++)\n {\n \t for (int j=0; j<3; j++)\n \t {\n \t\t FuncPrint(\"NS_ACCALPN_\" + rdi.itos(i) + \"[\" + rdi.itos(j) + \"]\", NS_ACCALPN[j][i]);\n \t\t FuncPrint(\"NS_ACCN_\" + rdi.itos(i) + \"[\" + rdi.itos(j) + \"]\", NS_ACCN[j][i]);\n \t\t FuncPrint(\"NS_ACCGMN_\" + rdi.itos(i) + \"[\" + rdi.itos(j) + \"]\", NS_ACCGMN[j][i]);\n \t\t FuncPrint(\"NS_ACCAZN_\" + rdi.itos(i) + \"[\" + rdi.itos(j) + \"]\", NS_ACCAZN[j][i]);\n \t\t FuncPrint(\"NS_ACCS_\" + rdi.itos(i) + \"[\" + rdi.itos(j) + \"]\", NS_ACCS[j][i]);\n \t }\n }\n\n double MEAN_ACCALPN[3], MEAN_ACCN[3], MEAN_ACCGMN[3], MEAN_ACCAZN[3], MEAN_ACCS[3], SD_ACCALPN[3], SD_ACCN[3], SD_ACCGMN[3], SD_ACCAZN[3], SD_ACCS[3];\n\n for (int i=0; i<3; i++)\n {\n \t DSP_MEAN(NS_ACCALPN[i], &MEAN_ACCALPN[i], &SD_ACCALPN[i], 30);\n \t DSP_MEAN(NS_ACCN[i], &MEAN_ACCN[i], &SD_ACCN[i], 30);\n \t DSP_MEAN(NS_ACCGMN[i], &MEAN_ACCGMN[i], &SD_ACCGMN[i], 30);\n \t DSP_MEAN(NS_ACCAZN[i], &MEAN_ACCAZN[i], &SD_ACCAZN[i], 30);\n \t DSP_MEAN(NS_ACCS[i], &MEAN_ACCS[i], &SD_ACCS[i], 30);\n }\n\n\n\n for (int i=0; i<3; i++)\n {\n \t FuncPrint(\"MEAN_ACCALPN_\"+axis_string[i], MEAN_ACCALPN[i]);\n \t FuncPrint(\"MEAN_ACCN_\"+axis_string[i], MEAN_ACCN[i]);\n \t FuncPrint(\"MEAN_ACCGMN_\"+axis_string[i], MEAN_ACCGMN[i]);\n \t FuncPrint(\"MEAN_ACCAZN_\"+axis_string[i], MEAN_ACCAZN[i]);\n \t FuncPrint(\"MEAN_ACCS_\"+axis_string[i], MEAN_ACCS[i]);\n\n \t FuncPrint(\"SD_ACCALPN_\"+axis_string[i], SD_ACCALPN[i]);\n \t FuncPrint(\"SD_ACCN_\"+axis_string[i], SD_ACCN[i]);\n \t FuncPrint(\"SD_ACCGMN_\"+axis_string[i], SD_ACCGMN[i]);\n \t FuncPrint(\"SD_ACCAZN_\"+axis_string[i], SD_ACCAZN[i]);\n \t FuncPrint(\"SD_ACCS_\"+axis_string[i], SD_ACCS[i]);\n }\n\n for (int i=0; i<3; i++)\n {\n \t TestLog(\"MEAN_ACCALPN_\"+axis_string[i], MEAN_ACCALPN[i]);\n \t TestLog(\"MEAN_ACCN_\"+axis_string[i], MEAN_ACCN[i]);\n \t TestLog(\"MEAN_ACCGMN_\"+axis_string[i], MEAN_ACCGMN[i]);\n \t TestLog(\"MEAN_ACCAZN_\"+axis_string[i], MEAN_ACCAZN[i]);\n \t TestLog(\"MEAN_ACCS_\"+axis_string[i], MEAN_ACCS[i]);\n\n \t TestLog(\"SD_ACCALPN_\"+axis_string[i], SD_ACCALPN[i]);\n \t TestLog(\"SD_ACCN_\"+axis_string[i], SD_ACCN[i]);\n \t TestLog(\"SD_ACCGMN_\"+axis_string[i], SD_ACCGMN[i]);\n \t TestLog(\"SD_ACCAZN_\"+axis_string[i], SD_ACCAZN[i]);\n \t TestLog(\"SD_ACCS_\"+axis_string[i], SD_ACCS[i]);\n }\n\n int Func_result = rdi.id(\"T15_12_ACC_AFE_CBIST_Noise_Test_R2_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n // Auto_Code_Judge_and_log\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T15_12_ACC_AFE_CBIST_Noise_Test_R2\", T15_12_ACC_AFE_CBIST_Noise_Test_R2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description:\n# - Reset DP\n# - Disable Sensoer drive, disconnet Mems\n# - Set CO to 10\n# - Set capacitive offset to 255, sign to 1\n# - Set DCFB to 7\n# - Set acc_trm_gmboost_ch1/2/3 to 0\n# - Set DLG to 7\n# - For ACC AFE X/Y/Z Channel measure \n# VBP, VCP; VCN, VCMI; VBN, VBC\n# - Clean\n#############################################################################################################\ncmt('Version info: $Revision: 3 $ $Author: luz3sgh $ $Date: 2024/04/15 01:49:10 GMT $')\n\nwac('EXT_MODE',0xc00d) # ANA page\nwac(\"OCP_MASK\", 0x1fff)\nwr('ANA_TRM_ACC_CH1',0x0000) # Set Offset, off_Sign, C0 to 0 \nrac('ANA_TRM_ACC_CH1',0x0000,0x1fff) \nwr('ANA_TRM_ACC_CH2',0x0000) # Set Offset, off_Sign, C0 to 0 \nrac('ANA_TRM_ACC_CH2',0x0000,0x1fff) \nwr('ANA_TRM_ACC_CH3',0x0000) # Set Offset, off_Sign, C0 to 0\nrac('ANA_TRM_ACC_CH3',0x0000,0x1fff) \nwr(\"OCP_MASK\", 0x0000) # Reset masking register\nrac(\"OCP_MASK\", 0xffff) # Check masking register reset\n\n# Set DCFB\nwac(\"EXT_MODE\", 0xc00e) # change to page 14, ACC_AFE\nwac(\"OCP_MASK\", 0x7fff) # Set masking register\nwr(\"ACC_TRM_CFB\", 1024*7+32*7+7) # Set DCFB ch1/2/3 to 7\nrac(\"ACC_TRM_CFB\", 1024*7+32*7+7, 0x7fff) # Check register setting\nwr(\"ACC_TRM_LOOPG\", 1024*23+32*23+23) # Set DLG ch1/2/3 to 23\nrac(\"ACC_TRM_LOOPG\", 1024*23+32*23+23, 0x7fff) # Check register setting\nwr(\"OCP_MASK\", 0x0000) # Reset masking register\nrac(\"OCP_MASK\", 0xffff) # Check masking register reset \n\n# ******** Voltage measurement\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_CONF', 0x0101) # Enable TB1; enable se_meas\nwac('TM_PIN', 0x0095) # Enable ANAIO1/2; TB1_OUT on ANAIO1; TB2_INP on ANAIO2\n\nfor ch, ch_str in [(0x8,\"X\"),(0x9, \"Y\"),(0xa, \"Z\")]:\n # Measure CVOP & CVOM\n wac('TM_CONF', 0x0101) # Enable TB1; NOT_INV; se_meas\n wac('TM_ADDR', 0x0200 + ch) # cfg 2 for CVOP, CVOM connection\n dly(100e-6)\n gav(f'V_CVOP_{ch_str}_RAW', 'INT2', 'ASDX')\n calc(f'V_CVOP_{ch_str}', f'V_CVOP_{ch_str}_RAW', '-', 'V_OFF1_ECOFF')\n log(f'V_CVOP_{ch_str}')\n wac('TM_ADDR', 0x0000) # Disable ATM\n wac('TM_CONF', 0x0111) # Invert test bus; keep TB1 and se_meas\n wac('TM_ADDR', 0x0200 + ch) # cfg 2 for CVOP, CVOM connection\n dly(100e-6)\n gav(f'V_CVOM_{ch_str}_RAW', 'INT2', 'ASDX')\n calc(f'V_CVOM_{ch_str}', f'V_CVOM_{ch_str}_RAW', '-', 'V_OFF1_ECOFF')\n log(f'V_CVOM_{ch_str}')\n wac('TM_ADDR', 0x0000) \n\n # Measure BOXP & BOXM\n wac('TM_CONF', 0x0101) # Enable TB1; NOT_INV; se_meas\n wac('TM_ADDR', 0x0400 + ch) # cfg 4 for BOXP, BOXM connection\n dly(100e-6)\n gav(f'V_BOXP_{ch_str}_RAW', 'INT2', 'ASDX')\n calc(f'V_BOXP_{ch_str}', f'V_BOXP_{ch_str}_RAW', '-', 'V_OFF1_ECOFF')\n log(f'V_BOXP_{ch_str}')\n wac('TM_ADDR', 0x0000) # Disable ATM\n wac('TM_CONF', 0x0111) # Invert test bus; keep TB1 and se_meas\n wac('TM_ADDR', 0x0400 + ch) # cfg 4 for BOXP, BOXM connection\n dly(100e-6)\n gav(f'V_BOXM_{ch_str}_RAW', 'INT2', 'ASDX')\n calc(f'V_BOXM_{ch_str}', f'V_BOXM_{ch_str}_RAW', '-', 'V_OFF1_ECOFF')\n log(f'V_BOXM_{ch_str}')\n wac('TM_ADDR', 0x0000) \n\n # Measure VBP & VCP\n wac('TM_CONF', 0x0101) # Enable TB1; NOT_INV; se_meas\n wac('TM_ADDR', 0x0500 + ch) # cfg 5 for VBP, VCP connection\n dly(100e-6)\n gav(f'V_VBP_{ch_str}_RAW', 'INT2', 'ASDX')\n calc(f'V_VBP_{ch_str}', f'V_VBP_{ch_str}_RAW', '-', 'V_OFF1_ECOFF')\n log(f'V_VBP_{ch_str}')\n wac('TM_ADDR', 0x0000) # Disable ATM\n wac('TM_CONF', 0x0111) # Invert test bus; keep TB1 and se_meas\n wac('TM_ADDR', 0x0500 + ch) # cfg 5 for VBP, VCP connection\n dly(100e-6)\n gav(f'V_VCP_{ch_str}_RAW', 'INT2', 'ASDX')\n calc(f'V_VCP_{ch_str}', f'V_VCP_{ch_str}_RAW', '-', 'V_OFF1_ECOFF')\n log(f'V_VCP_{ch_str}')\n wac('TM_ADDR', 0x0000) \n \n # Measure VCN & VCMI\n wac('TM_CONF', 0x0101) \n wac('TM_ADDR', 0x0600 + ch) \n dly(100e-6)\n gav(f'V_VCN_{ch_str}_RAW', 'INT2', 'ASDX')\n calc(f'V_VCN_{ch_str}', f'V_VCN_{ch_str}_RAW', '-', 'V_OFF1_ECOFF')\n log(f'V_VCN_{ch_str}')\n wac('TM_ADDR', 0x0000) \n wac('TM_CONF', 0x0111) \n wac('TM_ADDR', 0x0600 + ch) \n dly(100e-6)\n gav(f'V_VCMI_{ch_str}_RAW', 'INT2', 'ASDX')\n calc(f'V_VCMI_{ch_str}', f'V_VCMI_{ch_str}_RAW', '-', 'V_OFF1_ECOFF')\n log(f'V_VCMI_{ch_str}')\n wac('TM_ADDR', 0x0000) \n\n # Measure VBN & VBC\n wac('TM_CONF', 0x0101) \n wac('TM_ADDR', 0x0700 + ch) \n dly(100e-6)\n gav(f'V_VBN_{ch_str}_RAW', 'INT2', 'ASDX')\n calc(f'V_VBN_{ch_str}', f'V_VBN_{ch_str}_RAW', '-', 'V_OFF1_ECOFF')\n log(f'V_VBN_{ch_str}')\n wac('TM_ADDR', 0x0000) \n wac('TM_CONF', 0x0111) \n wac('TM_ADDR', 0x0700 + ch) \n dly(100e-6)\n gav(f'V_VBC_{ch_str}_RAW', 'INT2', 'ASDX')\n calc(f'V_VBC_{ch_str}', f'V_VBC_{ch_str}_RAW', '-', 'V_OFF1_ECOFF')\n log(f'V_VBC_{ch_str}')\n wac('TM_ADDR', 0x0000) \n\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('EXT_MODE', 0xc009) # Switch to IO register page\nwac('OCP_MASK', 0x0600) # Set masking register\nwr('IO_TEST_IF', 0x0000) # Disable ANAIO1+2\nrac('IO_TEST_IF', 0x0000, 0x0600) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_CONF', 0x0000) # Reset test config\n\n# ********** ACC AFE setting clean\nwac(\"EXT_MODE\", 0xc00e) # change to acc_afe page\nwac(\"ACC_TRM_CFB\", 0x7fff ) # Reset to default value\nwac(\"ACC_TRM_LOOPG\", 0x7fff) # Reset to default value\n\nwac(\"EXT_MODE\", 0xc00d) # change to page ANA\nwac(\"OCP_MASK\", 0x01ff)\nwr(\"ANA_TRM_ACC_CH1\", 0x0000) # Reset to default value\nrac(\"ANA_TRM_ACC_CH1\", 0x0000, 0x01ff)\nwr(\"ANA_TRM_ACC_CH2\", 0x0000) \nrac(\"ANA_TRM_ACC_CH2\", 0x0000, 0x01ff)\nwr(\"ANA_TRM_ACC_CH3\", 0x0000) \nrac(\"ANA_TRM_ACC_CH3\", 0x0000, 0x01ff)\nwr(\"OCP_MASK\", 0x0000) \nrac(\"OCP_MASK\", 0xffff) \n", "output": "/*****************************************************\n * T15_20_ACC_BIAS_Measurement_R1, description file version Notfound, avc file version Notfound\n * First Editor : jsh5sgh\n * Code generated with autocoding tool V2.9.1, in TOI2 standard way by module write_standard\n * Change History:\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T15_20_ACC_BIAS_Measurement_R1: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static string ch_str[] = {\"X\", \"Y\", \"Z\"};\n static string acc_str[] = {\"CVOP\", \"CVOM\", \"BOXP\", \"BOXM\", \"VBP\", \"VCP\", \"VCN\", \"VCMI\", \"VBN\", \"VBC\"};\n static double d_VOLT_RAW[xNSitES][3][10], d_VOLT[xNSitES][3][10];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T15_20_ACC_BIAS_Measurement}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 1] @ avcline 3092: {gav('V_CVOP_X_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 1] @ avcline 3092: {calc('V_CVOP_X', 'V_CVOP_X_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 1] @ avcline 3092: {log('V_CVOP_X', '', '', 0, 0)}\n valid comment[ 2] @ avcline 3679: {gav('V_CVOM_X_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 2] @ avcline 3679: {calc('V_CVOM_X', 'V_CVOM_X_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 2] @ avcline 3679: {log('V_CVOM_X', '', '', 0, 0)}\n valid comment[ 3] @ avcline 4266: {gav('V_BOXP_X_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 3] @ avcline 4266: {calc('V_BOXP_X', 'V_BOXP_X_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 3] @ avcline 4266: {log('V_BOXP_X', '', '', 0, 0)}\n valid comment[ 4] @ avcline 4853: {gav('V_BOXM_X_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 4] @ avcline 4853: {calc('V_BOXM_X', 'V_BOXM_X_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 4] @ avcline 4853: {log('V_BOXM_X', '', '', 0, 0)}\n valid comment[ 5] @ avcline 5440: {gav('V_VBP_X_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 5] @ avcline 5440: {calc('V_VBP_X', 'V_VBP_X_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 5] @ avcline 5440: {log('V_VBP_X', '', '', 0, 0)}\n valid comment[ 6] @ avcline 6027: {gav('V_VCP_X_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 6] @ avcline 6027: {calc('V_VCP_X', 'V_VCP_X_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 6] @ avcline 6027: {log('V_VCP_X', '', '', 0, 0)}\n valid comment[ 7] @ avcline 6614: {gav('V_VCN_X_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 7] @ avcline 6614: {calc('V_VCN_X', 'V_VCN_X_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 7] @ avcline 6614: {log('V_VCN_X', '', '', 0, 0)}\n valid comment[ 8] @ avcline 7201: {gav('V_VCMI_X_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 8] @ avcline 7201: {calc('V_VCMI_X', 'V_VCMI_X_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 8] @ avcline 7201: {log('V_VCMI_X', '', '', 0, 0)}\n valid comment[ 9] @ avcline 7788: {gav('V_VBN_X_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 9] @ avcline 7788: {calc('V_VBN_X', 'V_VBN_X_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 9] @ avcline 7788: {log('V_VBN_X', '', '', 0, 0)}\n valid comment[ 10] @ avcline 8375: {gav('V_VBC_X_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 10] @ avcline 8375: {calc('V_VBC_X', 'V_VBC_X_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 10] @ avcline 8375: {log('V_VBC_X', '', '', 0, 0)}\n valid comment[ 11] @ avcline 8962: {gav('V_CVOP_Y_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 11] @ avcline 8962: {calc('V_CVOP_Y', 'V_CVOP_Y_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 11] @ avcline 8962: {log('V_CVOP_Y', '', '', 0, 0)}\n valid comment[ 12] @ avcline 9549: {gav('V_CVOM_Y_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 12] @ avcline 9549: {calc('V_CVOM_Y', 'V_CVOM_Y_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 12] @ avcline 9549: {log('V_CVOM_Y', '', '', 0, 0)}\n valid comment[ 13] @ avcline 10136: {gav('V_BOXP_Y_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 13] @ avcline 10136: {calc('V_BOXP_Y', 'V_BOXP_Y_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 13] @ avcline 10136: {log('V_BOXP_Y', '', '', 0, 0)}\n valid comment[ 14] @ avcline 10723: {gav('V_BOXM_Y_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 14] @ avcline 10723: {calc('V_BOXM_Y', 'V_BOXM_Y_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 14] @ avcline 10723: {log('V_BOXM_Y', '', '', 0, 0)}\n valid comment[ 15] @ avcline 11310: {gav('V_VBP_Y_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 15] @ avcline 11310: {calc('V_VBP_Y', 'V_VBP_Y_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 15] @ avcline 11310: {log('V_VBP_Y', '', '', 0, 0)}\n valid comment[ 16] @ avcline 11897: {gav('V_VCP_Y_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 16] @ avcline 11897: {calc('V_VCP_Y', 'V_VCP_Y_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 16] @ avcline 11897: {log('V_VCP_Y', '', '', 0, 0)}\n valid comment[ 17] @ avcline 12484: {gav('V_VCN_Y_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 17] @ avcline 12484: {calc('V_VCN_Y', 'V_VCN_Y_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 17] @ avcline 12484: {log('V_VCN_Y', '', '', 0, 0)}\n valid comment[ 18] @ avcline 13071: {gav('V_VCMI_Y_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 18] @ avcline 13071: {calc('V_VCMI_Y', 'V_VCMI_Y_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 18] @ avcline 13071: {log('V_VCMI_Y', '', '', 0, 0)}\n valid comment[ 19] @ avcline 13658: {gav('V_VBN_Y_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 19] @ avcline 13658: {calc('V_VBN_Y', 'V_VBN_Y_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 19] @ avcline 13658: {log('V_VBN_Y', '', '', 0, 0)}\n valid comment[ 20] @ avcline 14245: {gav('V_VBC_Y_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 20] @ avcline 14245: {calc('V_VBC_Y', 'V_VBC_Y_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 20] @ avcline 14245: {log('V_VBC_Y', '', '', 0, 0)}\n valid comment[ 21] @ avcline 14832: {gav('V_CVOP_Z_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 21] @ avcline 14832: {calc('V_CVOP_Z', 'V_CVOP_Z_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 21] @ avcline 14832: {log('V_CVOP_Z', '', '', 0, 0)}\n valid comment[ 22] @ avcline 15419: {gav('V_CVOM_Z_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 22] @ avcline 15419: {calc('V_CVOM_Z', 'V_CVOM_Z_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 22] @ avcline 15419: {log('V_CVOM_Z', '', '', 0, 0)}\n valid comment[ 23] @ avcline 16006: {gav('V_BOXP_Z_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 23] @ avcline 16006: {calc('V_BOXP_Z', 'V_BOXP_Z_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 23] @ avcline 16006: {log('V_BOXP_Z', '', '', 0, 0)}\n valid comment[ 24] @ avcline 16593: {gav('V_BOXM_Z_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 24] @ avcline 16593: {calc('V_BOXM_Z', 'V_BOXM_Z_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 24] @ avcline 16593: {log('V_BOXM_Z', '', '', 0, 0)}\n valid comment[ 25] @ avcline 17180: {gav('V_VBP_Z_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 25] @ avcline 17180: {calc('V_VBP_Z', 'V_VBP_Z_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 25] @ avcline 17180: {log('V_VBP_Z', '', '', 0, 0)}\n valid comment[ 26] @ avcline 17767: {gav('V_VCP_Z_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 26] @ avcline 17767: {calc('V_VCP_Z', 'V_VCP_Z_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 26] @ avcline 17767: {log('V_VCP_Z', '', '', 0, 0)}\n valid comment[ 27] @ avcline 18354: {gav('V_VCN_Z_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 27] @ avcline 18354: {calc('V_VCN_Z', 'V_VCN_Z_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 27] @ avcline 18354: {log('V_VCN_Z', '', '', 0, 0)}\n valid comment[ 28] @ avcline 18941: {gav('V_VCMI_Z_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 28] @ avcline 18941: {calc('V_VCMI_Z', 'V_VCMI_Z_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 28] @ avcline 18941: {log('V_VCMI_Z', '', '', 0, 0)}\n valid comment[ 29] @ avcline 19528: {gav('V_VBN_Z_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 29] @ avcline 19528: {calc('V_VBN_Z', 'V_VBN_Z_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 29] @ avcline 19528: {log('V_VBN_Z', '', '', 0, 0)}\n valid comment[ 30] @ avcline 20115: {gav('V_VBC_Z_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 30] @ avcline 20115: {calc('V_VBC_Z', 'V_VBC_Z_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 30] @ avcline 20115: {log('V_VBC_Z', '', '', 0, 0)}\n valid comment[ 31] @ avcline 23380: {Test End: T15_20_ACC_BIAS_Measurement}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n for(int i=0; i<30; i++)\n {\n\t\t\t\t rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n\t\t\t\t\t\t\t.insertSub(i_comment_line[0][1+i]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(64).measWait(1 ms)//V_CVOP_X_RAW//{gav('V_CVOP_X_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n\t\t\t\t\t\t\t.cont();\n }\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0]).execute();\n RDI_END();\n\n ON_FIRST_INVOCATION_END();\n\n ARRAY_D ad_jsubresults_INT2 = rdi.id(\"dcid_0\").getMultiValue(\"INT2\");\n ARRAY_D ad_jsubresults_ASDX = rdi.id(\"dcid_0\").getMultiValue(\"ASDX\");\n\n for(int i=0; i<3; i++) {\n \t for(int j=0; j<10; j++) {\n \t\t d_VOLT_RAW[curSite][i][j] = ad_jsubresults_INT2[i*10+j] - ad_jsubresults_ASDX[i*10+j];\n \t FuncPrint(\"V_\"+acc_str[j]+\"_\"+ch_str[i]+\"_RAW\", d_VOLT_RAW[curSite][i][j]);\n \t\t d_VOLT[curSite][i][j] = d_VOLT_RAW[curSite][i][j] - V_OFF1_ECOFF[curSite];\n \t FuncPrint(\"V_\"+acc_str[j]+\"_\"+ch_str[i],\td_VOLT_RAW[curSite][i][j]);\n \t TestLog(\"V_\"+acc_str[j]+\"_\"+ch_str[i], \td_VOLT_RAW[curSite][i][j]);\n \t }\n }\n\n int Func_result = rdi.id(\"burst_id0\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T15_20_ACC_BIAS_Measurement_R1\", T15_20_ACC_BIAS_Measurement_R1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: Measure scaled down cgm voltage\n#############################################################################################################\ncmt('Version info: $Revision: 2 $ $Author: laj1mu23 $ $Date: 2024/03/25 20:39:17 GMT $')\n# Config Buffer, TM_CONF \nwac('EXT_MODE', 0xc00f) # Page Test, Reg TM_CONF \nwcb('tm_buf_pwrup',0x1) # Enable TB1 only\nwcb('tm_bus_inv',0x0) # 0 is default value,'Do not invert analog test bus'\n# Config ANAIO pad, TM_PIN \nwcb('tm_int2_en',0x1)\nwcb('tm_int2_sel',0x2) # TB1OUT on anaio1\nwcb('tm_asdx_en',0x1)\nwcb('tm_asdx_sel',0x4) # TB2IN on anaio2\n# Config CTB_P/N, TM_ADDR\nwac('EXT_MODE', 0xc00f) # Page Test, Reg TM_ADDR\nwcb('tm_cfg', 0x1) # VGM_VCTRL@GYR_TB_P, VSS@GYR_RB_N\nwcb('tm_addr', 0x4) # GYRO I/O tests \n# Measure\ndly(100e-6)\ngav(f'V_VGM_VCTRL_RAW', 'INT2','ASDX')\ncalc('V_VGM_VCTRL','V_VGM_VCTRL_RAW','-','V_OFF1_ECOFF')\nlog('V_VGM_VCTRL')\n# Reset all ana test mode settings\nwac('TM_ADDR', 0x0000)\nwac('TM_PIN',0x0000)\nwac('TM_CONF',0x0000)\n# Config Buffer, TM_CONF\nwcb('tm_buf_pwrup',0x1) # Enable TB1 only\nwcb('tm_bus_inv',0x0) # 0 is default value,'Do not invert analog test bus'\nwcb('tm_se_meas',0x1)\n# Config ANAIO pad, TM_PIN \nwcb('tm_int2_en',0x1)\nwcb('tm_int2_sel',0x2) # TB1OUT on anaio1\nwcb('tm_asdx_en',0x1)\nwcb('tm_asdx_sel',0x4) # TB2IN on anaio2\n# Config CTB_P/N, TM_ADDR\nwac('EXT_MODE', 0xc00f) # Page Test, Reg TM_ADDR\nwcb('tm_cfg', 0x7) # HV_VCM@GYR_TB_P, VREF_VCM@GYR_RB_N\nwcb('tm_addr', 0x4) # GYRO I/O tests \n# Measure\ndly(100e-6)\ngav(f'V_HV_VCM_RAW', 'INT2','ASDX')\ncalc('V_HV_VCM','V_HV_VCM_RAW','-','V_OFF1_ECOFF')\nlog('V_HV_VCM')\n# Set up and measure VREF_VCM\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_CONF', 0x0111) # Invert test bus; keep TB1 and se_meas\nwac('TM_ADDR', 0x0704) # VREF_VCM now on INT2\ndly(100e-6)\ngav(f'V_VREF_VCM_RAW', 'INT2','ASDX')\ncalc('V_VREF_VCM','V_VREF_VCM_RAW','-','V_OFF1_ECOFF')\nlog('V_VREF_VCM')\ndly(296e-9)\ncalc('V_CGM_OFFSET', 'V_HV_VCM', '-', 'V_VREF_VCM')\nlog('V_CGM_OFFSET')\n# Clean-up\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\nwac('EXT_MODE', 0xc000) # Switch back to USR page\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T16_03_S15_cgm_offset_test_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n static double V_VGM_VCTRL_RAW[xNSitES];\n static double V_HV_VCM_RAW[xNSitES];\n static double V_VREF_VCM_RAW[xNSitES];\n\n static double V_VGM_VCTRL[xNSitES], V_HV_VCM[xNSitES], V_VREF_VCM[xNSitES], V_CGM_OFFSET[xNSitES];\n // Auto_Code_Variable_define\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T16_03_S15_cgm_offset_test_V2_PAT_id\");\n rdi.dc(\"T16_03_S15_cgm_offset_test_V2DC_id0\").label(s_label_name)\n .insertSub(i_comment_line0[0]).pin(\"INT2,ASDX\",TA::BADC).vMeas().average(128).measWait(1 ms) //V_VGM_VCTRL_RAW\n .insertSub(i_comment_line0[1]).pin(\"INT2,ASDX\",TA::BADC).vMeas().average(128).measWait(1 ms) //V_HV_VCM_RAW\n .insertSub(i_comment_line0[2]).pin(\"INT2,ASDX\",TA::BADC).vMeas().average(128).measWait(1 ms) //V_VREF_VCM_RAW\n .execute();\n RDI_END();\n\n // Auto_Code_Execution_Part\n\n ON_FIRST_INVOCATION_END();\n\t\t\tARRAY_D JSUB_results_ASDX;\n\t\t\tJSUB_results_ASDX = rdi.id(\"T16_03_S15_cgm_offset_test_V2DC_id0\").getMultiValue(\"ASDX\");\n\t\t\tARRAY_D JSUB_results_INT2;\n\t\t\tJSUB_results_INT2 = rdi.id(\"T16_03_S15_cgm_offset_test_V2DC_id0\").getMultiValue(\"INT2\");\n\t\t\tV_VGM_VCTRL_RAW[CURRENT_SITE_NUMBER()-1] = JSUB_results_INT2[0] - JSUB_results_ASDX[0];\n\t\t\tV_HV_VCM_RAW[CURRENT_SITE_NUMBER()-1] = JSUB_results_INT2[1] - JSUB_results_ASDX[1];\n\t\t\tV_VREF_VCM_RAW[CURRENT_SITE_NUMBER()-1] = JSUB_results_INT2[2] - JSUB_results_ASDX[2];\n\n V_VGM_VCTRL[CURRENT_SITE_NUMBER()-1] = V_VGM_VCTRL_RAW[CURRENT_SITE_NUMBER()-1] - V_OFF1_ECOFF[CURRENT_SITE_NUMBER()-1];\n V_HV_VCM[CURRENT_SITE_NUMBER()-1] = V_HV_VCM_RAW[CURRENT_SITE_NUMBER()-1] - V_OFF1_ECOFF[CURRENT_SITE_NUMBER()-1];\n V_VREF_VCM[CURRENT_SITE_NUMBER()-1] = V_VREF_VCM_RAW[CURRENT_SITE_NUMBER()-1] - V_OFF1_ECOFF[CURRENT_SITE_NUMBER()-1];\n V_CGM_OFFSET[CURRENT_SITE_NUMBER()-1] = V_HV_VCM[CURRENT_SITE_NUMBER()-1] - V_VREF_VCM[CURRENT_SITE_NUMBER()-1];\n\n FuncPrint(\"JSUB_results_INT2_0\", JSUB_results_INT2[0]);\n FuncPrint(\"JSUB_results_ASDX_0\", JSUB_results_ASDX[0]);\n FuncPrint(\"V_VGM_VCTRL_RAW\", V_VGM_VCTRL_RAW[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"V_VGM_VCTRL\", V_VGM_VCTRL[CURRENT_SITE_NUMBER()-1]);\n\n FuncPrint(\"JSUB_results_INT2_1\", JSUB_results_INT2[1]);\n FuncPrint(\"JSUB_results_ASDX_1\", JSUB_results_ASDX[1]);\n FuncPrint(\"V_HV_VCM_RAW\", V_HV_VCM_RAW[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"V_HV_VCM\", V_HV_VCM[CURRENT_SITE_NUMBER()-1]);\n\n FuncPrint(\"JSUB_results_INT2_2\", JSUB_results_INT2[2]);\n FuncPrint(\"JSUB_results_ASDX_2\", JSUB_results_ASDX[2]);\n FuncPrint(\"V_VREF_VCM_RAW\", V_VREF_VCM_RAW[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"V_VREF_VCM\", V_VREF_VCM[CURRENT_SITE_NUMBER()-1]);\n\n FuncPrint(\"V_CGM_OFFSET\", V_CGM_OFFSET[CURRENT_SITE_NUMBER()-1]);\n // Auto_Code_Retrieve_Data\n \n int Func_result = rdi.id(\"T16_03_S15_cgm_offset_test_V2_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n FuncPrint(\"V_VGM_VCTRL\", V_VGM_VCTRL[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"V_HV_VCM\", V_HV_VCM[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"V_VREF_VCM\", V_VREF_VCM[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"V_CGM_OFFSET\", V_CGM_OFFSET[CURRENT_SITE_NUMBER()-1]);\n\n\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"V_VGM_VCTRL\", V_VGM_VCTRL[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"V_HV_VCM\", V_HV_VCM[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"V_VREF_VCM\", V_VREF_VCM[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"V_CGM_OFFSET\", V_CGM_OFFSET[CURRENT_SITE_NUMBER()-1]);\n // Auto_Code_Judge_and_log\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T16_03_S15_cgm_offset_test_V2\", T16_03_S15_cgm_offset_test_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: TOSK voltage measure\n# Steps: Meausre TOSK with QP & QN eclectorde set to 0\n# Meausre TOSK with QP & QN eclectorde set to 3\n#############################################################################################################\ncmt('Version info: $Revision: 3 $ $Author: luz3sgh $ $Date: 2024/05/20 05:10:20 GMT $')\nsav('VDD', 3.6, v_range=4.0)\nsav('VDDIO', 3.6, v_range=4.0)\ndly(100e-6)\nwac('EXT_MODE',0xc00e) # Page GYR_AFE\nwcb('gyr_test_tosk_en',0x1) # Reg GYR_TEST_TOSK, Enable tosk, qp, qn default value 0x0\ndly(100e-6)\n# Config Buffer, TM_CONF \nwac('EXT_MODE', 0xc00f) # Page Test, Reg TM_CONF \nwcb('tm_buf_pwrup',0x1) # Enable TB1 only\nwcb('tm_se_meas',0x1) # Force single end measurement\n# Config ANAIO pad, TM_PIN \nwcb('tm_int2_en',0x1)\nwcb('tm_int2_sel',0x2) # TB1OUT on anaio1\nwcb('tm_asdx_en',0x1)\nwcb('tm_asdx_sel',0x4) # TB2IN on anaio2\n# Config CTB_P/N, TM_ADDR\nwcb('tm_cfg', 0xb) # GYR_QP_CORE@GYR_TB_P, GYR_QP_CORE@GYR_TB_N\nwcb('tm_addr', 0x4) # GYRO I/O tests \n# Measure @tosk_q

equal to 0\ngav(f'V_TOSK_QP0_RAW', 'INT2','ASDX')\ncalc('V_TOSK_QP0','V_TOSK_QP0_RAW','-','V_OFF1_ECOFF')\nlog('V_TOSK_QP0')\nwcb('tm_bus_inv',0x1) # Invert analog test bus, GYR_QN_CORE@GYR_TB_P\ngav(f'V_TOSK_QN0_RAW', 'INT2','ASDX')\ncalc('V_TOSK_QN0','V_TOSK_QN0_RAW','-','V_OFF1_ECOFF')\nlog('V_TOSK_QN0')\nwcb('tm_bus_inv',0x0) # Reset bus_inv\n# Measure @tosk_q

equal to 3\nwac('EXT_MODE',0xc00e) # Page GYR_AFE\nwcb('gyr_test_tosk_qp',0x3) # Reg GYR_TEST_TOSK, tosk keep enabled\nwcb('gyr_test_tosk_qn',0x3)\ndly(100e-6)\ngav(f'V_TOSK_QP3_RAW', 'INT2','ASDX')\ncalc('V_TOSK_QP3','V_TOSK_QP3_RAW','-','V_OFF1_ECOFF')\nlog('V_TOSK_QP3')\nwac('EXT_MODE', 0xc00f) # Page Test, Reg TM_CONF \nwcb('tm_bus_inv',0x1) # Invert analog test bus, GYR_QN_CORE@GYR_TB_P\ngav(f'V_TOSK_QN3_RAW', 'INT2','ASDX')\ncalc('V_TOSK_QN3','V_TOSK_QN3_RAW','-','V_OFF1_ECOFF')\nlog('V_TOSK_QN3')\n# Clean\nwac('EXT_MODE',0xc00e) # Page GYR_AFE\nwac('GYR_TEST_TOSK',0x0000) # Disable tosk, qp & qn back to 0 \nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\n", "output": "/*****************************************************\n * T16_08_tosk_voltage_measurement_V3, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T16_08_tosk_voltage_measurement_V3: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static double d_V_TOSK_QN0_RAW[xNSitES], d_V_TOSK_QN0[xNSitES];\n static double d_V_TOSK_QN3_RAW[xNSitES], d_V_TOSK_QN3[xNSitES];\n static double d_V_TOSK_QP0_RAW[xNSitES], d_V_TOSK_QP0[xNSitES];\n static double d_V_TOSK_QP3_RAW[xNSitES], d_V_TOSK_QP3[xNSitES];\n static int i_funcRes0[xNSitES];\n\n static double v_VDDIO, v_VDD;\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(d_V_TOSK_QN0_RAW, 9.9, xNSitES);\n Func_Init_Var(d_V_TOSK_QN3_RAW, 9.9, xNSitES);\n Func_Init_Var(d_V_TOSK_QP0_RAW, 9.9, xNSitES);\n Func_Init_Var(d_V_TOSK_QP3_RAW, 9.9, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n v_VDDIO = Primary.getLevelSpec().getSpecValue(\"VDDIO\");\n v_VDD = Primary.getLevelSpec().getSpecValue(\"VDD\");\n\n// rdi.dc().pin(\"VDDIO\").vForce(1.8 V).execute();\n// Primary.getLevelSpec().change(\"VDDIO\",1.8);\n// FLUSH(TM::APRM);\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T16_08_tosk_voltage_measurement}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 0] @ avcline 10: {sav('VDD', 3.6, 4, 0.01, False, False)}\n valid comment[ 0] @ avcline 10: {sav('VDDIO', 3.6, 4, 0.01, False, False)}\n valid comment[ 1] @ avcline 3564: {gav('V_TOSK_QP0_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 1] @ avcline 3564: {calc('V_TOSK_QP0', 'V_TOSK_QP0_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 1] @ avcline 3564: {log('V_TOSK_QP0', '', '', 0, 0)}\n valid comment[ 2] @ avcline 3915: {gav('V_TOSK_QN0_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 2] @ avcline 3915: {calc('V_TOSK_QN0', 'V_TOSK_QN0_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 2] @ avcline 3915: {log('V_TOSK_QN0', '', '', 0, 0)}\n valid comment[ 3] @ avcline 5168: {gav('V_TOSK_QP3_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 3] @ avcline 5168: {calc('V_TOSK_QP3', 'V_TOSK_QP3_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 3] @ avcline 5168: {log('V_TOSK_QP3', '', '', 0, 0)}\n valid comment[ 4] @ avcline 5711: {gav('V_TOSK_QN3_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 4] @ avcline 5711: {calc('V_TOSK_QN3', 'V_TOSK_QN3_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 4] @ avcline 5711: {log('V_TOSK_QN3', '', '', 0, 0)}\n valid comment[ 5] @ avcline 6864: {Test End: T16_08_tosk_voltage_measurement}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][0]).pin(\"VDD\").vForce(v_VDD V).iRange(40 mA)//{sav('VDD', 3.6, 4, 0.01, False, False)}\n .insertSub(i_comment_line[0][0]).pin(\"VDDIO\").vForce(v_VDDIO V).iRange(40 mA)//{sav('VDDIO', 3.6, 4, 0.01, False, False)}\n .insertSub(i_comment_line[0][1]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_TOSK_QP0_RAW//{gav('V_TOSK_QP0_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][2]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_TOSK_QN0_RAW//{gav('V_TOSK_QN0_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][3]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_TOSK_QP3_RAW//{gav('V_TOSK_QP3_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][4]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_TOSK_QN3_RAW//{gav('V_TOSK_QN3_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n ARRAY_D ad_jsubresults_INT2; ad_jsubresults_INT2.resize(4); ad_jsubresults_INT2.init(-9.9);\n ARRAY_D ad_jsubresults_ASDX; ad_jsubresults_ASDX.resize(4); ad_jsubresults_ASDX.init(-9.9);\n ad_jsubresults_INT2 = rdi.id(\"dcid_0\").getMultiValue(\"INT2\");\n ad_jsubresults_ASDX = rdi.id(\"dcid_0\").getMultiValue(\"ASDX\");\n\n FuncPrint(\"ad_jsubresults_INT2_0\", ad_jsubresults_INT2[0]);\n FuncPrint(\"ad_jsubresults_ASDX_0\", ad_jsubresults_ASDX[0]);\n FuncPrint(\"ad_jsubresults_INT2_1\", ad_jsubresults_INT2[1]);\n FuncPrint(\"ad_jsubresults_ASDX_1\", ad_jsubresults_ASDX[1]);\n FuncPrint(\"ad_jsubresults_INT2_2\", ad_jsubresults_INT2[2]);\n FuncPrint(\"ad_jsubresults_ASDX_2\", ad_jsubresults_ASDX[2]);\n FuncPrint(\"ad_jsubresults_INT2_3\", ad_jsubresults_INT2[3]);\n FuncPrint(\"ad_jsubresults_ASDX_3\", ad_jsubresults_ASDX[3]);\n\n d_V_TOSK_QP0_RAW[curSite] = ad_jsubresults_INT2[0] - ad_jsubresults_ASDX[0];\n d_V_TOSK_QN0_RAW[curSite] = ad_jsubresults_INT2[1] - ad_jsubresults_ASDX[1];\n d_V_TOSK_QP3_RAW[curSite] = ad_jsubresults_INT2[2] - ad_jsubresults_ASDX[2];\n d_V_TOSK_QN3_RAW[curSite] = ad_jsubresults_INT2[3] - ad_jsubresults_ASDX[3];\n\n d_V_TOSK_QP0[curSite] = d_V_TOSK_QP0_RAW[curSite] - V_OFF1_ECOFF[curSite];\n d_V_TOSK_QN0[curSite] = d_V_TOSK_QN0_RAW[curSite] - V_OFF1_ECOFF[curSite];\n d_V_TOSK_QP3[curSite] = d_V_TOSK_QP3_RAW[curSite] - V_OFF1_ECOFF[curSite];\n d_V_TOSK_QN3[curSite] = d_V_TOSK_QN3_RAW[curSite] - V_OFF1_ECOFF[curSite];\n\n FuncPrint(\"V_TOSK_QN0_RAW\",d_V_TOSK_QN0_RAW[curSite]);\n FuncPrint(\"V_TOSK_QN3_RAW\",d_V_TOSK_QN3_RAW[curSite]);\n FuncPrint(\"V_TOSK_QP0_RAW\",d_V_TOSK_QP0_RAW[curSite]);\n FuncPrint(\"V_TOSK_QP3_RAW\",d_V_TOSK_QP3_RAW[curSite]);\n\n FuncPrint(\"d_V_TOSK_QP0\",d_V_TOSK_QP0[curSite]);\n FuncPrint(\"d_V_TOSK_QN0\",d_V_TOSK_QN0[curSite]);\n FuncPrint(\"d_V_TOSK_QP3\",d_V_TOSK_QP3[curSite]);\n FuncPrint(\"d_V_TOSK_QN3\",d_V_TOSK_QN3[curSite]);\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n// rdi.dc().pin(\"VDDIO\").vForce(v_VDDIO V).execute();\n// Primary.getLevelSpec().change(\"VDDIO\",v_VDDIO);\n// FLUSH(TM::APRM);\n\n ON_FIRST_INVOCATION_END();\n\n TestLog(\"V_TOSK_QP0\",d_V_TOSK_QP0[curSite]);\n TestLog(\"V_TOSK_QN0\",d_V_TOSK_QN0[curSite]);\n TestLog(\"V_TOSK_QP3\",d_V_TOSK_QP3[curSite]);\n TestLog(\"V_TOSK_QN3\",d_V_TOSK_QN3[curSite]);\n i_funcRes[curSite] = i_funcRes0[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T16_08_tosk_voltage_measurement_V3\", T16_08_tosk_voltage_measurement_V3);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: TOSK voltage measure\n# Steps: 1. enalbe test mdoe\n# 2. measure gyro tosk for QN+QP with all settings\n#############################################################################################################\ncmt('Version info: $Revision: 2 $ $Author: laj1mu23 $ $Date: 2024/03/25 20:39:17 GMT $')\nwac('EXT_MODE',0xc00e) # Page GYR_AFE\nwcb('gyr_test_tosk_en',0x1) # Reg GYR_TEST_TOSK, Enable tosk, qp, qn default value 0x0\ndly(100e-6)\n# Config Buffer, TM_CONF \nwac('EXT_MODE', 0xc00f) # Page Test, Reg TM_CONF \nwcb('tm_buf_pwrup',0x1) # Enable TB1 only\nwcb('tm_se_meas',0x1) # Force single end measurement\n# Config ANAIO pad, TM_PIN \nwcb('tm_int2_en',0x1)\nwcb('tm_int2_sel',0x2) # TB1OUT on anaio1\nwcb('tm_asdx_en',0x1)\nwcb('tm_asdx_sel',0x4) # TB2IN on anaio2\n# Config CTB_P/N, TM_ADDR\nwcb('tm_cfg', 0xb) # GYR_QP_CORE@GYR_TB_P, GYR_QP_CORE@GYR_TB_N\nwcb('tm_addr', 0x4) # GYRO I/O tests \n\nfor n in [0, 2, 3, 4, 5]:\n wac('EXT_MODE', 0xc00f) # Page Test, Reg TM_CONF \n wcb('tm_bus_inv',0x0) \n wac('EXT_MODE',0xc00e) # Page GYR_AFE\n wcb('gyr_test_tosk_qp',n) # Reg GYR_TEST_TOSK, tosk keep enabled\n wcb('gyr_test_tosk_qn',n)\n dly(100e-6)\n gav(f'V_TOSK_QP{n}_RAW', 'INT2','ASDX')\n calc(f'V_TOSK_QP{n}',f'V_TOSK_QP{n}_RAW','-','V_OFF1_ECOFF')\n log(f'V_TOSK_QP{n}')\n wac('EXT_MODE', 0xc00f) # Page Test, Reg TM_CONF \n wcb('tm_bus_inv',0x1) # Invert test bus, GYR_QN_CORE@GYR_TB_P\n gav(f'V_TOSK_QN{n}_RAW', 'INT2','ASDX')\n calc(f'V_TOSK_QN{n}',f'V_TOSK_QN{n}_RAW','-','V_OFF1_ECOFF')\n log(f'V_TOSK_QN{n}')\n\n# Measure for step 1, QP close to 0, measure without buffer\nwac('EXT_MODE', 0xc00f) # Page Test, Reg TM_CONF \nwcb('tm_bus_inv',0x0) \nwcb('tm_int2_sel',0x4) # TB1IN on anaio1 \nwcb('tm_buf_pwrup',0x0) # Disable TB1\nwac('EXT_MODE',0xc00e) # Page GYR_AFE\nwcb('gyr_test_tosk_qp',1) # Reg GYR_TEST_TOSK, tosk keep enabled\nwcb('gyr_test_tosk_qn',1)\ndly(100e-6)\ngav(f'V_TOSK_QP1', 'INT2','ASDX')\nlog(f'V_TOSK_QP1')\nwac('EXT_MODE', 0xc00f) # Page Test, Reg TM_CONF \nwcb('tm_bus_inv',0x1) # Invert test bus, GYR_QN_CORE@GYR_TB_P\nwcb('tm_buf_pwrup',0x1) # Enable TB1\nwcb('tm_int2_sel',0x2) # TB1OUT on anaio1\ngav(f'V_TOSK_QN1_RAW', 'INT2','ASDX')\ncalc(f'V_TOSK_QN1',f'V_TOSK_QN1_RAW','-','V_OFF1_ECOFF')\nlog(f'V_TOSK_QN1')\nwcb('tm_bus_inv',0x0) # Reset bus_inv\n\n# Measure for step 6, QN close to 0, measure without buffer\nwac('EXT_MODE', 0xc00f) # Page Test, Reg TM_CONF \nwcb('tm_bus_inv',0x0) \nwcb('tm_buf_pwrup',0x1) # Enable TB1\nwcb('tm_int2_sel',0x2) # TB1OUT on anaio1\nwac('EXT_MODE',0xc00e) # Page GYR_AFE\nwcb('gyr_test_tosk_qp',6) # Reg GYR_TEST_TOSK, tosk keep enabled\nwcb('gyr_test_tosk_qn',6)\ndly(100e-6)\ngav(f'V_TOSK_QP6_RAW', 'INT2','ASDX')\ncalc(f'V_TOSK_QP6',f'V_TOSK_QP6_RAW','-','V_OFF1_ECOFF')\nlog(f'V_TOSK_QP6')\nwac('EXT_MODE', 0xc00f) # Page Test, Reg TM_CONF \nwcb('tm_bus_inv',0x1) # Invert test bus, GYR_QN_CORE@GYR_TB_P\nwcb('tm_buf_pwrup',0x0) # Disable TB1\nwcb('tm_int2_sel',0x4) # TB1IN on anaio1 \ngav(f'V_TOSK_QN6', 'INT2','ASDX')\nlog(f'V_TOSK_QN6')\n\n# Clean\nwac('EXT_MODE',0xc00e) # Page GYR_AFE\nwac('GYR_TEST_TOSK',0x0000) # Disable tosk, qp & qn back to 0 \nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\n", "output": "/*****************************************************\n * T16_09_tosk_voltage_char_V2, description file version Notfound, avc file version Notfound\n * First Editor : jsh5sgh\n * Code generated with autocoding tool V2.9.1, in TOI2 standard way by module write_standard\n * Change History:\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T16_09_tosk_voltage_char_V2: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static double d_V_TOSK_QN0_RAW[xNSitES];\n static double d_V_TOSK_QN2_RAW[xNSitES];\n static double d_V_TOSK_QN3_RAW[xNSitES];\n static double d_V_TOSK_QN4_RAW[xNSitES];\n static double d_V_TOSK_QN5_RAW[xNSitES];\n static double d_V_TOSK_QN0[xNSitES];\n static double d_V_TOSK_QN2[xNSitES];\n static double d_V_TOSK_QN3[xNSitES];\n static double d_V_TOSK_QN4[xNSitES];\n static double d_V_TOSK_QN5[xNSitES];\n\n static double d_V_TOSK_QP0_RAW[xNSitES];\n static double d_V_TOSK_QP2_RAW[xNSitES];\n static double d_V_TOSK_QP3_RAW[xNSitES];\n static double d_V_TOSK_QP4_RAW[xNSitES];\n static double d_V_TOSK_QP5_RAW[xNSitES];\n static double d_V_TOSK_QP0[xNSitES];\n static double d_V_TOSK_QP2[xNSitES];\n static double d_V_TOSK_QP3[xNSitES];\n static double d_V_TOSK_QP4[xNSitES];\n static double d_V_TOSK_QP5[xNSitES];\n\n static double d_V_TOSK_QP1[xNSitES];\n static double d_V_TOSK_QN1_RAW[xNSitES];\n static double d_V_TOSK_QN1[xNSitES];\n\n static double d_V_TOSK_QP6_RAW[xNSitES];\n static double d_V_TOSK_QP6[xNSitES];\n static double d_V_TOSK_QN6[xNSitES];\n\n static int i_funcRes0[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(d_V_TOSK_QN0_RAW, 9.9, xNSitES);\n Func_Init_Var(d_V_TOSK_QN1_RAW, 9.9, xNSitES);\n Func_Init_Var(d_V_TOSK_QN2_RAW, 9.9, xNSitES);\n Func_Init_Var(d_V_TOSK_QN3_RAW, 9.9, xNSitES);\n Func_Init_Var(d_V_TOSK_QN4_RAW, 9.9, xNSitES);\n Func_Init_Var(d_V_TOSK_QN5_RAW, 9.9, xNSitES);\n Func_Init_Var(d_V_TOSK_QN6, 9.9, xNSitES);\n Func_Init_Var(d_V_TOSK_QP0_RAW, 9.9, xNSitES);\n Func_Init_Var(d_V_TOSK_QP1, 9.9, xNSitES);\n Func_Init_Var(d_V_TOSK_QP2_RAW, 9.9, xNSitES);\n Func_Init_Var(d_V_TOSK_QP3_RAW, 9.9, xNSitES);\n Func_Init_Var(d_V_TOSK_QP4_RAW, 9.9, xNSitES);\n Func_Init_Var(d_V_TOSK_QP5_RAW, 9.9, xNSitES);\n Func_Init_Var(d_V_TOSK_QP6_RAW, 9.9, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T16_09_tosk_voltage_char}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 1] @ avcline 4998: {gav('V_TOSK_QP0_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 1] @ avcline 4998: {calc('V_TOSK_QP0', 'V_TOSK_QP0_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 1] @ avcline 4998: {log('V_TOSK_QP0', '', '', 0, 0)}\n valid comment[ 2] @ avcline 5541: {gav('V_TOSK_QN0_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 2] @ avcline 5541: {calc('V_TOSK_QN0', 'V_TOSK_QN0_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 2] @ avcline 5541: {log('V_TOSK_QN0', '', '', 0, 0)}\n valid comment[ 3] @ avcline 6986: {gav('V_TOSK_QP2_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 3] @ avcline 6986: {calc('V_TOSK_QP2', 'V_TOSK_QP2_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 3] @ avcline 6986: {log('V_TOSK_QP2', '', '', 0, 0)}\n valid comment[ 4] @ avcline 7529: {gav('V_TOSK_QN2_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 4] @ avcline 7529: {calc('V_TOSK_QN2', 'V_TOSK_QN2_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 4] @ avcline 7529: {log('V_TOSK_QN2', '', '', 0, 0)}\n valid comment[ 5] @ avcline 8974: {gav('V_TOSK_QP3_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 5] @ avcline 8974: {calc('V_TOSK_QP3', 'V_TOSK_QP3_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 5] @ avcline 8974: {log('V_TOSK_QP3', '', '', 0, 0)}\n valid comment[ 6] @ avcline 9517: {gav('V_TOSK_QN3_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 6] @ avcline 9517: {calc('V_TOSK_QN3', 'V_TOSK_QN3_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 6] @ avcline 9517: {log('V_TOSK_QN3', '', '', 0, 0)}\n valid comment[ 7] @ avcline 10962: {gav('V_TOSK_QP4_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 7] @ avcline 10962: {calc('V_TOSK_QP4', 'V_TOSK_QP4_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 7] @ avcline 10962: {log('V_TOSK_QP4', '', '', 0, 0)}\n valid comment[ 8] @ avcline 11505: {gav('V_TOSK_QN4_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 8] @ avcline 11505: {calc('V_TOSK_QN4', 'V_TOSK_QN4_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 8] @ avcline 11505: {log('V_TOSK_QN4', '', '', 0, 0)}\n valid comment[ 9] @ avcline 12950: {gav('V_TOSK_QP5_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 9] @ avcline 12950: {calc('V_TOSK_QP5', 'V_TOSK_QP5_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 9] @ avcline 12950: {log('V_TOSK_QP5', '', '', 0, 0)}\n valid comment[ 10] @ avcline 13493: {gav('V_TOSK_QN5_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 10] @ avcline 13493: {calc('V_TOSK_QN5', 'V_TOSK_QN5_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 10] @ avcline 13493: {log('V_TOSK_QN5', '', '', 0, 0)}\n valid comment[ 11] @ avcline 15638: {gav('V_TOSK_QP1', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 11] @ avcline 15638: {log('V_TOSK_QP1', '', '', 0, 0)}\n valid comment[ 12] @ avcline 16881: {gav('V_TOSK_QN1_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 12] @ avcline 16881: {calc('V_TOSK_QN1', 'V_TOSK_QN1_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 12] @ avcline 16881: {log('V_TOSK_QN1', '', '', 0, 0)}\n valid comment[ 13] @ avcline 19376: {gav('V_TOSK_QP6_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 13] @ avcline 19376: {calc('V_TOSK_QP6', 'V_TOSK_QP6_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 13] @ avcline 19376: {log('V_TOSK_QP6', '', '', 0, 0)}\n valid comment[ 14] @ avcline 20619: {gav('V_TOSK_QN6', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 14] @ avcline 20619: {log('V_TOSK_QN6', '', '', 0, 0)}\n valid comment[ 15] @ avcline 21772: {Test End: T16_09_tosk_voltage_char}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][1]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_TOSK_QP0_RAW//{gav('V_TOSK_QP0_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][2]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_TOSK_QN0_RAW//{gav('V_TOSK_QN0_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][3]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_TOSK_QP2_RAW//{gav('V_TOSK_QP2_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][4]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_TOSK_QN2_RAW//{gav('V_TOSK_QN2_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][5]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_TOSK_QP3_RAW//{gav('V_TOSK_QP3_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][6]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_TOSK_QN3_RAW//{gav('V_TOSK_QN3_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][7]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_TOSK_QP4_RAW//{gav('V_TOSK_QP4_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][8]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_TOSK_QN4_RAW//{gav('V_TOSK_QN4_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][9]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_TOSK_QP5_RAW//{gav('V_TOSK_QP5_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][10]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_TOSK_QN5_RAW//{gav('V_TOSK_QN5_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][11]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_TOSK_QP1//{gav('V_TOSK_QP1', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][12]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_TOSK_QN1_RAW//{gav('V_TOSK_QN1_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][13]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_TOSK_QP6_RAW//{gav('V_TOSK_QP6_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][14]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_TOSK_QN6//{gav('V_TOSK_QN6', 'INT2', 'ASDX', 2, 0.0001, True)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n ARRAY_D ad_jsubresults_INT2; ad_jsubresults_INT2.resize(14); ad_jsubresults_INT2.init(-9.9);\n ARRAY_D ad_jsubresults_ASDX; ad_jsubresults_ASDX.resize(14); ad_jsubresults_ASDX.init(-9.9);\n ad_jsubresults_INT2 = rdi.id(\"dcid_0\").getMultiValue(\"INT2\");\n ad_jsubresults_ASDX = rdi.id(\"dcid_0\").getMultiValue(\"ASDX\");\n \n d_V_TOSK_QP0_RAW[curSite] = ad_jsubresults_INT2[0] - ad_jsubresults_ASDX[0];\n d_V_TOSK_QN0_RAW[curSite] = ad_jsubresults_INT2[1] - ad_jsubresults_ASDX[1];\n d_V_TOSK_QP2_RAW[curSite] = ad_jsubresults_INT2[2] - ad_jsubresults_ASDX[2];\n d_V_TOSK_QN2_RAW[curSite] = ad_jsubresults_INT2[3] - ad_jsubresults_ASDX[3];\n d_V_TOSK_QP3_RAW[curSite] = ad_jsubresults_INT2[4] - ad_jsubresults_ASDX[4];\n d_V_TOSK_QN3_RAW[curSite] = ad_jsubresults_INT2[5] - ad_jsubresults_ASDX[5];\n d_V_TOSK_QP4_RAW[curSite] = ad_jsubresults_INT2[6] - ad_jsubresults_ASDX[6];\n d_V_TOSK_QN4_RAW[curSite] = ad_jsubresults_INT2[7] - ad_jsubresults_ASDX[7];\n d_V_TOSK_QP5_RAW[curSite] = ad_jsubresults_INT2[8] - ad_jsubresults_ASDX[8];\n d_V_TOSK_QN5_RAW[curSite] = ad_jsubresults_INT2[9] - ad_jsubresults_ASDX[9];\n d_V_TOSK_QP0[curSite] = d_V_TOSK_QP0_RAW[curSite] - V_OFF1_ECOFF[curSite];\n d_V_TOSK_QN0[curSite] = d_V_TOSK_QN0_RAW[curSite] - V_OFF1_ECOFF[curSite];\n d_V_TOSK_QP2[curSite] = d_V_TOSK_QP2_RAW[curSite] - V_OFF1_ECOFF[curSite];\n d_V_TOSK_QN2[curSite] = d_V_TOSK_QN2_RAW[curSite] - V_OFF1_ECOFF[curSite];\n d_V_TOSK_QP3[curSite] = d_V_TOSK_QP3_RAW[curSite] - V_OFF1_ECOFF[curSite];\n d_V_TOSK_QN3[curSite] = d_V_TOSK_QN3_RAW[curSite] - V_OFF1_ECOFF[curSite];\n d_V_TOSK_QP4[curSite] = d_V_TOSK_QP4_RAW[curSite] - V_OFF1_ECOFF[curSite];\n d_V_TOSK_QN4[curSite] = d_V_TOSK_QN4_RAW[curSite] - V_OFF1_ECOFF[curSite];\n d_V_TOSK_QP5[curSite] = d_V_TOSK_QP5_RAW[curSite] - V_OFF1_ECOFF[curSite];\n d_V_TOSK_QN5[curSite] = d_V_TOSK_QN5_RAW[curSite] - V_OFF1_ECOFF[curSite];\n\n d_V_TOSK_QP1[curSite] = ad_jsubresults_INT2[10] - ad_jsubresults_ASDX[10];\n d_V_TOSK_QN1_RAW[curSite] = ad_jsubresults_INT2[11] - ad_jsubresults_ASDX[11];\n d_V_TOSK_QN1[curSite] = d_V_TOSK_QN1_RAW[curSite] - V_OFF1_ECOFF[curSite];\n\n d_V_TOSK_QP6_RAW[curSite] = ad_jsubresults_INT2[12] - ad_jsubresults_ASDX[12];\n d_V_TOSK_QP6_RAW[curSite] = d_V_TOSK_QP6_RAW[curSite] - V_OFF1_ECOFF[curSite];\n d_V_TOSK_QN6[curSite] = ad_jsubresults_INT2[13] - ad_jsubresults_ASDX[13];\n\n FuncPrint(\"V_TOSK_QP0_RAW\",d_V_TOSK_QP0_RAW[curSite]);\n FuncPrint(\"V_TOSK_QN0_RAW\",d_V_TOSK_QN0_RAW[curSite]);\n FuncPrint(\"V_TOSK_QP2_RAW\",d_V_TOSK_QP2_RAW[curSite]);\n FuncPrint(\"V_TOSK_QN2_RAW\",d_V_TOSK_QN2_RAW[curSite]);\n FuncPrint(\"V_TOSK_QP3_RAW\",d_V_TOSK_QP3_RAW[curSite]);\n FuncPrint(\"V_TOSK_QN3_RAW\",d_V_TOSK_QN3_RAW[curSite]);\n FuncPrint(\"V_TOSK_QP4_RAW\",d_V_TOSK_QP4_RAW[curSite]);\n FuncPrint(\"V_TOSK_QN4_RAW\",d_V_TOSK_QN4_RAW[curSite]);\n FuncPrint(\"V_TOSK_QP5_RAW\",d_V_TOSK_QP5_RAW[curSite]);\n FuncPrint(\"V_TOSK_QN5_RAW\",d_V_TOSK_QN5_RAW[curSite]);\n FuncPrint(\"V_TOSK_QP0\",d_V_TOSK_QP0[curSite]);\n FuncPrint(\"V_TOSK_QN0\",d_V_TOSK_QN0[curSite]);\n FuncPrint(\"V_TOSK_QP2\",d_V_TOSK_QP2[curSite]);\n FuncPrint(\"V_TOSK_QN2\",d_V_TOSK_QN2[curSite]);\n FuncPrint(\"V_TOSK_QP3\",d_V_TOSK_QP3[curSite]);\n FuncPrint(\"V_TOSK_QN3\",d_V_TOSK_QN3[curSite]);\n FuncPrint(\"V_TOSK_QP4\",d_V_TOSK_QP4[curSite]);\n FuncPrint(\"V_TOSK_QN4\",d_V_TOSK_QN4[curSite]);\n FuncPrint(\"V_TOSK_QP5\",d_V_TOSK_QP5[curSite]);\n FuncPrint(\"V_TOSK_QN5\",d_V_TOSK_QN5[curSite]);\n\n FuncPrint(\"V_TOSK_QP1\",d_V_TOSK_QP1[curSite]);\n FuncPrint(\"V_TOSK_QN1_RAW\",d_V_TOSK_QN1_RAW[curSite]);\n FuncPrint(\"V_TOSK_QN1\",d_V_TOSK_QN1[curSite]);\n\n FuncPrint(\"V_TOSK_QP6_RAW\",d_V_TOSK_QP6_RAW[curSite]);\n FuncPrint(\"V_TOSK_QP6\",d_V_TOSK_QP6[curSite]);\n FuncPrint(\"V_TOSK_QN6\",d_V_TOSK_QN6[curSite]);\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n\n ON_FIRST_INVOCATION_END();\n\n TestLog(\"V_TOSK_QN0\",d_V_TOSK_QN0[curSite]);\n TestLog(\"V_TOSK_QN1\",d_V_TOSK_QN1[curSite]);\n TestLog(\"V_TOSK_QN2\",d_V_TOSK_QN2[curSite]);\n TestLog(\"V_TOSK_QN3\",d_V_TOSK_QN3[curSite]);\n TestLog(\"V_TOSK_QN4\",d_V_TOSK_QN4[curSite]);\n TestLog(\"V_TOSK_QN5\",d_V_TOSK_QN5[curSite]);\n TestLog(\"V_TOSK_QN6\",d_V_TOSK_QN6[curSite]);\n TestLog(\"V_TOSK_QP0\",d_V_TOSK_QP0[curSite]);\n TestLog(\"V_TOSK_QP1\",d_V_TOSK_QP1[curSite]);\n TestLog(\"V_TOSK_QP2\",d_V_TOSK_QP2[curSite]);\n TestLog(\"V_TOSK_QP3\",d_V_TOSK_QP3[curSite]);\n TestLog(\"V_TOSK_QP4\",d_V_TOSK_QP4[curSite]);\n TestLog(\"V_TOSK_QP5\",d_V_TOSK_QP5[curSite]);\n TestLog(\"V_TOSK_QP6\",d_V_TOSK_QP6[curSite]);\n i_funcRes[curSite] = i_funcRes0[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T16_09_tosk_voltage_char_V2\", T16_09_tosk_voltage_char_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: measure VDDG3V, 3.4V charge pump output\n# Steps: 1. Set pad drive strength to 0\n# 2. Set VDD, VDDIO to 3.6V\n# 3. Config ATM, measure VDDG3V\n# 4. Set pad drive strength to 1\n# Notes: VDD, VDDIO set to 3.6V in both cp and char flow--no vmin, vmax condition\n#############################################################################################################\ncmt('Version info: $Revision: bai430aa_rel/2 $ $Author: hmf1rt $ $Date: 2024/09/25 12:29:15 GMT $')\nwac('EXT_MODE', 0xc000) # Switch to USR register page\nwac('IO_PAD_STRENGTH', 0x0040) # Set pad drive strength to 0 for prim/sec IF\nsav('VDD', 3.6, v_range=4.0)\nsav('VDDIO', 3.6, v_range=4.0)\ndly(100e-6)\n# Config ANAIO pad, TM_PIN \nwac('EXT_MODE', 0xc00f) # Page Test, Reg TM_PIN\nwac('TM_PIN', 0x0099) # TB1IN on anaio1,TB2IN on anaio2 \n# Config CTB_P/N, TM_ADDR \nwac('TM_ADDR', 0x0c04) # VDDG3V@GYR_TB_P, VSS@GYR_RB_N\n# Measure\ndly(100e-6)\ngav(f'V_VDDG3V', 'INT2','ASDX',v_range=4.0)\nlog('V_VDDG3V')\n# Clean\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('EXT_MODE', 0xc000) # Switch to USR register page\nwac('IO_PAD_STRENGTH', 0x0049) # Set pad drive strength to 1 for prim/sec IF\n", "output": "/*****************************************************\n * T16_10_drive_charge_pump_test_V3, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T16_10_drive_charge_pump_test_V3: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n\n vector i_comment_line;\n ARRAY_LL IO_PAD_STRENGTH_rtv(xNSitES),IO_PAD_STRENGTH_restore_rtv(xNSitES);\n const int Wri_Bit_Length = 33;\n const int Wri_Bit_Position = 415;\n int IO_PAD_STRENGTH = 0;\n int IO_PAD_STRENGTH_restore = 2;\n\n static double d_V_VDDG3V[xNSitES];\n static int i_funcRes0[xNSitES];\n static double v_VDDIO, v_VDD;\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(d_V_VDDG3V, 9.9, xNSitES);\n i_comment_line = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line, printFlag);\n\n v_VDDIO = Primary.getLevelSpec().getSpecValue(\"VDDIO\");\n v_VDD = Primary.getLevelSpec().getSpecValue(\"VDD\");\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T16_10_drive_charge_pump_test}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 0] @ avcline 10: {sav('VDD', 3.6, 4, 0.01, False, False)}\n valid comment[ 0] @ avcline 10: {sav('VDDIO', 3.6, 4, 0.01, False, False)}\n valid comment[ 1] @ avcline 2322: {gav('V_VDDG3V', 'INT2', 'ASDX', 4, 0.0001, True)}\n valid comment[ 1] @ avcline 2322: {log('V_VDDG3V', '', '', 0, 0)}\n valid comment[ 2] @ avcline 2707: {Test End: T16_10_drive_charge_pump_test}\n */\n\n\n FOR_EACH_SITE_BEGIN();\n \t IO_PAD_STRENGTH_rtv[CURRENT_SITE_NUMBER()-1] = extend_Pmode_Herschel(IO_PAD_STRENGTH, 2);\n \t IO_PAD_STRENGTH_restore_rtv[CURRENT_SITE_NUMBER()-1] = extend_Pmode_Herschel(IO_PAD_STRENGTH_restore, 2);\n FOR_EACH_SITE_END();\n\n rdi.runTimeVal(\"IO_PAD_STRENGTH_rtv\", IO_PAD_STRENGTH_rtv);\n rdi.runTimeVal(\"IO_PAD_STRENGTH_restore_rtv\", IO_PAD_STRENGTH_restore_rtv);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"id2\");\n rdi.digCap(\"pad_drv_digcap\").vecVarOnly().pin(\"SDO\").capMode(TA::SER).samples(16*1).bitPerWord(16).execute();\n rdi.smartVec().label(\"T08_99_Pad_Drive_setting_R1\").pin(\"SDX\").writeData(\"IO_PAD_STRENGTH_rtv\", Wri_Bit_Length, Wri_Bit_Position).execute();\n RDI_END();\n\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(6).pin(\"VDD\").vForce(v_VDD).iRange(40 mA)//{sav('VDD', 3.6, 4, 0.01, False, False)}\n .insertSub(6).pin(\"VDDIO\").vForce(v_VDDIO).iRange(40 mA)//{sav('VDDIO', 3.6, 4, 0.01, False, False)}\n .insertSub(6).wait(10 ms)\n .insertSub(i_comment_line[1]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(10 ms)//V_VDDG3V//{gav('V_VDDG3V', 'INT2', 'ASDX', 4, 0.0001, True)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n ARRAY_D ad_jsubresults_INT2; ad_jsubresults_INT2.resize(1); ad_jsubresults_INT2.init(-9.9);\n ARRAY_D ad_jsubresults_ASDX; ad_jsubresults_ASDX.resize(1); ad_jsubresults_ASDX.init(-9.9);\n ad_jsubresults_INT2 = rdi.id(\"dcid_0\").getMultiValue(\"INT2\");\n ad_jsubresults_ASDX = rdi.id(\"dcid_0\").getMultiValue(\"ASDX\");\n \n d_V_VDDG3V[curSite] = ad_jsubresults_INT2[0] - ad_jsubresults_ASDX[0];\n FuncPrint(\"ad_jsubresults_INT2\",ad_jsubresults_INT2[0]);\n FuncPrint(\"ad_jsubresults_ASDX\",ad_jsubresults_ASDX[0]);\n FuncPrint(\"V_VDDG3V\",d_V_VDDG3V[curSite]);\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n RDI_BEGIN(mode);\n rdi.burstId(\"id3\");\n rdi.digCap(\"pad_drv_digcap_restore\").vecVarOnly().pin(\"SDO\").capMode(TA::SER).samples(16*1).bitPerWord(16).execute();\n rdi.smartVec().label(\"T08_99_Pad_Drive_setting_R1\").pin(\"SDX\").writeData(\"IO_PAD_STRENGTH_restore_rtv\", Wri_Bit_Length, Wri_Bit_Position).execute();\n RDI_END();\n\n\n\n ON_FIRST_INVOCATION_END();\n\n TestLog(\"V_VDDG3V\",d_V_VDDG3V[curSite]);\n i_funcRes[curSite] = i_funcRes0[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n\n int Func_result2 = rdi.id(\"id2\").getBurstPassFail();\n FuncPrint(\"Func_result2\", Func_result2);\n int Func_result3 = rdi.id(\"id3\").getBurstPassFail();\n FuncPrint(\"Func_result3\", Func_result3);\n\n ARRAY_I Vec1=rdi.id(\"pad_drv_digcap\").getVector();\n FuncPrint(\"IO_PAD_STRENGTH_RD\", reverse_ras_result(Vec1[0])&0x7);\n FuncPrint(\"IO_PAD_STRENGTH\", IO_PAD_STRENGTH);\n\n ARRAY_I Vec2=rdi.id(\"pad_drv_digcap_restore\").getVector();\n FuncPrint(\"IO_PAD_STRENGTH_restore_RD\", reverse_ras_result(Vec2[0])&0x7);\n FuncPrint(\"IO_PAD_STRENGTH_restore\", IO_PAD_STRENGTH_restore);\n\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T16_10_drive_charge_pump_test_V3\", T16_10_drive_charge_pump_test_V3);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: Measure of GYR_CGM pad voltage\n#############################################################################################################\ncmt('Version info: $Revision: 1 $ $Author: hmf1rt $ $Date: 2024/03/13 13:36:52 GMT $')\ndly(1e-3)\ncmt('Measure voltage V_CGM_M at pad GYR_CGM. Voltage may up to 14V, use a high impedance measurement channel')\nlog('V_CGM_M')\n", "output": "/*****************************************************\n * T16_11_cgm_pad_measurement_V1, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T16_11_cgm_pad_measurement_V1: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static int i_funcRes0[xNSitES];\n static double d_V_GYR_CGM_AVI64[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T16_11_cgm_pad_measurement}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 1] @ avcline 18: {cmt: Measure voltage V_CGM_M at pad GYR_CGM. Voltage may up to 14V, use a high impedance measurement channel}\n valid comment[ 1] @ avcline 18: {log('V_CGM_M', '', '', 0, 0)}\n valid comment[ 2] @ avcline 19: {Test End: T16_11_cgm_pad_measurement}\n */\n\n rdi.util().pin(\"K5,K9\").setOn().execute();\n rdi.dc().pin(\"GYR_CGM\").vMeasRange(30 V).connectState(TA::HIZ).execute();\n\n\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(6).pin(\"GYR_CGM\").vMeas().average(128).measWait(1 ms)\n .execute();\n RDI_END();\n\n FOR_EACH_SITE_BEGIN();\n \t ARRAY_D ad_jsubresults_GYR_CGM;\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n ad_jsubresults_GYR_CGM = rdi.id(\"dcid_0\").getMultiValue(\"GYR_CGM\");\n FuncPrint(\"i_funcRes0\", i_funcRes0[curSite]);\n //Add calc code if necessary\n d_V_GYR_CGM_AVI64[curSite] = ad_jsubresults_GYR_CGM[0];\n FuncPrint(\"V_GYR_CGM_AVI64\",d_V_GYR_CGM_AVI64[curSite]);\n\n FOR_EACH_SITE_END();\n rdi.dc().pin(\"GYR_CGM\").disconnect().execute();\n rdi.util().pin(\"K5,K9\").setOff().execute();\n\n\n ON_FIRST_INVOCATION_END();\n\n i_funcRes[curSite] = i_funcRes0[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n TestLog(\"V_CGM_M\",d_V_GYR_CGM_AVI64[curSite]);\n\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T16_11_cgm_pad_measurement_V1\", T16_11_cgm_pad_measurement_V1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: Measure of GYR_CGM pad voltage over all trim steps\n# - Loop over all trim steps and measure voltage\n# - Set back to fix step 8 which corresponds to 12V\n#############################################################################################################\nfrom test_sub_functions import *\ncmt('Version info: $Revision: bai430aa_rel/1 $ $Author: hmf1rt $ $Date: 2024/07/18 13:27:42 GMT $')\nsav('OCSB', 1.5) # Set voltage on OCSB\ndly(100e-6)\nwac('EXT_MODE', 0xc00d) # Switch to PMU page\nwac(\"GYR_TEST_OWR1\",0x23ff) # enable all GYR blocks except LDO\n# run VGM trim loops\nwac('EXT_MODE', 0xc00d) # Switch to ANA page\ncmt('Voltage may go up to 16V, and should be measured with high impedance channel')\nfor n in range(0, 32, 2):\n wcb('gyr_trm_res_prog_ldovcm',n) # Reg ANA_TRM_RES_PROG0<5:0> \n dly(5e-3)\n cmt(f'Measure voltage V_CBGM_C_OCSB1P5V_{n:02d} at pad GYR_CGM')\n log(f'V_CBGM_C_OCSB1P5V_{n:02d}')\n\nsav('OCSB', 1.85) # Set voltage on OCSB\ncmt('Set VDDG voltage to 1.85V to achieve VGM levels up to 18.8V')\nfor n in range(20, 36, 2): \n wcb('gyr_trm_res_prog_ldovcm',n) # Reg ANA_TRM_RES_PROG0<5:0> \n dly(2e-3)\n cmt(f'Measure voltage V_CBGM_C_highocsb_OCSB1P85V_{n:02d} at pad GYR_CGM')\n log(f'V_CBGM_C_OCSB1P85V_{n:02d}')\nwcb('gyr_trm_res_prog_ldovcm',0x8) # Reg ANA_TRM_RES_PROG0<5:0> \ndly(2e-3)\nuav('OCSB') # unset voltage on OCSB\n# Clean\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\nwac('EXT_MODE',0xc00d) # Page Test, Reg PMU\nwcb('owr_vddg_en',0x0) # GYR_TEST_OWR1 bit10\nwcb('gyr_owr_en',0x0) # GYR_TEST_OWR1 bit0\n", "output": "/*****************************************************\n * T16_12_cgm_pad_char_R1, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n * JSH5SGH: update to V3.\n * JSH5SGH R1: version update.\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T16_12_cgm_pad_char_R1: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n static double d_V_CBGM_C[xNSitES][24];\n static int i_funcRes0[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n i_comment_line[0] = search_comment_line(s_label_name, \"cmt\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T16_12_cgm_pad_char}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 0] @ avcline 10: {sav('OCSB', 1.5, 2, 0.01, False, False)}\n valid comment[ 1] @ avcline 595: {cmt: Voltage may go up to 16V, and should be measured with high impedance channel}\n valid comment[ 2] @ avcline 955: {cmt: Measure voltage V_CBGM_C_OCSB1P5V_00 at pad GYR_CGM}\n valid comment[ 2] @ avcline 955: {log('V_CBGM_C_OCSB1P5V_00', '', '', 0, 0)}\n valid comment[ 3] @ avcline 1316: {cmt: Measure voltage V_CBGM_C_OCSB1P5V_02 at pad GYR_CGM}\n valid comment[ 3] @ avcline 1316: {log('V_CBGM_C_OCSB1P5V_02', '', '', 0, 0)}\n valid comment[ 4] @ avcline 1677: {cmt: Measure voltage V_CBGM_C_OCSB1P5V_04 at pad GYR_CGM}\n valid comment[ 4] @ avcline 1677: {log('V_CBGM_C_OCSB1P5V_04', '', '', 0, 0)}\n valid comment[ 5] @ avcline 2038: {cmt: Measure voltage V_CBGM_C_OCSB1P5V_06 at pad GYR_CGM}\n valid comment[ 5] @ avcline 2038: {log('V_CBGM_C_OCSB1P5V_06', '', '', 0, 0)}\n valid comment[ 6] @ avcline 2399: {cmt: Measure voltage V_CBGM_C_OCSB1P5V_08 at pad GYR_CGM}\n valid comment[ 6] @ avcline 2399: {log('V_CBGM_C_OCSB1P5V_08', '', '', 0, 0)}\n valid comment[ 7] @ avcline 2760: {cmt: Measure voltage V_CBGM_C_OCSB1P5V_10 at pad GYR_CGM}\n valid comment[ 7] @ avcline 2760: {log('V_CBGM_C_OCSB1P5V_10', '', '', 0, 0)}\n valid comment[ 8] @ avcline 3121: {cmt: Measure voltage V_CBGM_C_OCSB1P5V_12 at pad GYR_CGM}\n valid comment[ 8] @ avcline 3121: {log('V_CBGM_C_OCSB1P5V_12', '', '', 0, 0)}\n valid comment[ 9] @ avcline 3482: {cmt: Measure voltage V_CBGM_C_OCSB1P5V_14 at pad GYR_CGM}\n valid comment[ 9] @ avcline 3482: {log('V_CBGM_C_OCSB1P5V_14', '', '', 0, 0)}\n valid comment[ 10] @ avcline 3843: {cmt: Measure voltage V_CBGM_C_OCSB1P5V_16 at pad GYR_CGM}\n valid comment[ 10] @ avcline 3843: {log('V_CBGM_C_OCSB1P5V_16', '', '', 0, 0)}\n valid comment[ 11] @ avcline 4204: {cmt: Measure voltage V_CBGM_C_OCSB1P5V_18 at pad GYR_CGM}\n valid comment[ 11] @ avcline 4204: {log('V_CBGM_C_OCSB1P5V_18', '', '', 0, 0)}\n valid comment[ 12] @ avcline 4565: {cmt: Measure voltage V_CBGM_C_OCSB1P5V_20 at pad GYR_CGM}\n valid comment[ 12] @ avcline 4565: {log('V_CBGM_C_OCSB1P5V_20', '', '', 0, 0)}\n valid comment[ 13] @ avcline 4926: {cmt: Measure voltage V_CBGM_C_OCSB1P5V_22 at pad GYR_CGM}\n valid comment[ 13] @ avcline 4926: {log('V_CBGM_C_OCSB1P5V_22', '', '', 0, 0)}\n valid comment[ 14] @ avcline 5287: {cmt: Measure voltage V_CBGM_C_OCSB1P5V_24 at pad GYR_CGM}\n valid comment[ 14] @ avcline 5287: {log('V_CBGM_C_OCSB1P5V_24', '', '', 0, 0)}\n valid comment[ 15] @ avcline 5648: {cmt: Measure voltage V_CBGM_C_OCSB1P5V_26 at pad GYR_CGM}\n valid comment[ 15] @ avcline 5648: {log('V_CBGM_C_OCSB1P5V_26', '', '', 0, 0)}\n valid comment[ 16] @ avcline 6009: {cmt: Measure voltage V_CBGM_C_OCSB1P5V_28 at pad GYR_CGM}\n valid comment[ 16] @ avcline 6009: {log('V_CBGM_C_OCSB1P5V_28', '', '', 0, 0)}\n valid comment[ 17] @ avcline 6370: {cmt: Measure voltage V_CBGM_C_OCSB1P5V_30 at pad GYR_CGM}\n valid comment[ 17] @ avcline 6370: {log('V_CBGM_C_OCSB1P5V_30', '', '', 0, 0)}\n valid comment[ 18] @ avcline 6371: {sav('OCSB', 1.85, 2, 0.01, False, False)}\n valid comment[ 18] @ avcline 6371: {cmt: Set VDDG voltage to 1.85V to achieve VGM levels up to 18.8V}\n valid comment[ 19] @ avcline 6731: {cmt: Measure voltage V_CBGM_C_highocsb_OCSB1P85V_20 at pad GYR_CGM}\n valid comment[ 19] @ avcline 6731: {log('V_CBGM_C_OCSB1P85V_20', '', '', 0, 0)}\n valid comment[ 20] @ avcline 7092: {cmt: Measure voltage V_CBGM_C_highocsb_OCSB1P85V_22 at pad GYR_CGM}\n valid comment[ 20] @ avcline 7092: {log('V_CBGM_C_OCSB1P85V_22', '', '', 0, 0)}\n valid comment[ 21] @ avcline 7453: {cmt: Measure voltage V_CBGM_C_highocsb_OCSB1P85V_24 at pad GYR_CGM}\n valid comment[ 21] @ avcline 7453: {log('V_CBGM_C_OCSB1P85V_24', '', '', 0, 0)}\n valid comment[ 22] @ avcline 7814: {cmt: Measure voltage V_CBGM_C_highocsb_OCSB1P85V_26 at pad GYR_CGM}\n valid comment[ 22] @ avcline 7814: {log('V_CBGM_C_OCSB1P85V_26', '', '', 0, 0)}\n valid comment[ 23] @ avcline 8175: {cmt: Measure voltage V_CBGM_C_highocsb_OCSB1P85V_28 at pad GYR_CGM}\n valid comment[ 23] @ avcline 8175: {log('V_CBGM_C_OCSB1P85V_28', '', '', 0, 0)}\n valid comment[ 24] @ avcline 8536: {cmt: Measure voltage V_CBGM_C_highocsb_OCSB1P85V_30 at pad GYR_CGM}\n valid comment[ 24] @ avcline 8536: {log('V_CBGM_C_OCSB1P85V_30', '', '', 0, 0)}\n valid comment[ 25] @ avcline 8897: {cmt: Measure voltage V_CBGM_C_highocsb_OCSB1P85V_32 at pad GYR_CGM}\n valid comment[ 25] @ avcline 8897: {log('V_CBGM_C_OCSB1P85V_32', '', '', 0, 0)}\n valid comment[ 26] @ avcline 9258: {cmt: Measure voltage V_CBGM_C_highocsb_OCSB1P85V_34 at pad GYR_CGM}\n valid comment[ 26] @ avcline 9258: {log('V_CBGM_C_OCSB1P85V_34', '', '', 0, 0)}\n valid comment[ 27] @ avcline 9619: {uav('OCSB', False)}\n valid comment[ 28] @ avcline 11279: {Test End: T16_12_cgm_pad_char}\n */\n\n rdi.util().pin(\"K5,K9\").setOn().execute();\n rdi.dc().pin(\"GYR_CGM\").vMeasRange(30 V).connectState(TA::HIZ).execute();\n\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][0]).pin(\"OCSB\").vForce(1.3 V).iRange(40 mA)\n .insertSub(i_comment_line[0][2]).pin(\"GYR_CGM\").vMeas().average(128).measWait(10 ms)\n .insertSub(i_comment_line[0][3]).pin(\"GYR_CGM\").vMeas().average(128).measWait(10 ms)\n .insertSub(i_comment_line[0][4]).pin(\"GYR_CGM\").vMeas().average(128).measWait(10 ms)\n .insertSub(i_comment_line[0][5]).pin(\"GYR_CGM\").vMeas().average(128).measWait(10 ms)\n .insertSub(i_comment_line[0][6]).pin(\"GYR_CGM\").vMeas().average(128).measWait(10 ms)\n .insertSub(i_comment_line[0][7]).pin(\"GYR_CGM\").vMeas().average(128).measWait(10 ms)\n .insertSub(i_comment_line[0][8]).pin(\"GYR_CGM\").vMeas().average(128).measWait(10 ms)\n .insertSub(i_comment_line[0][9]).pin(\"GYR_CGM\").vMeas().average(128).measWait(10 ms)\n .insertSub(i_comment_line[0][10]).pin(\"GYR_CGM\").vMeas().average(128).measWait(10 ms)\n .insertSub(i_comment_line[0][11]).pin(\"GYR_CGM\").vMeas().average(128).measWait(10 ms)\n .insertSub(i_comment_line[0][12]).pin(\"GYR_CGM\").vMeas().average(128).measWait(10 ms)\n .insertSub(i_comment_line[0][13]).pin(\"GYR_CGM\").vMeas().average(128).measWait(10 ms)\n .insertSub(i_comment_line[0][14]).pin(\"GYR_CGM\").vMeas().average(128).measWait(10 ms)\n .insertSub(i_comment_line[0][15]).pin(\"GYR_CGM\").vMeas().average(128).measWait(10 ms)\n .insertSub(i_comment_line[0][16]).pin(\"GYR_CGM\").vMeas().average(128).measWait(10 ms)\n .insertSub(i_comment_line[0][17]).pin(\"GYR_CGM\").vMeas().average(128).measWait(10 ms)\n .insertSub(i_comment_line[0][18]).pin(\"OCSB\").vForce(1.85 V).iRange(40 mA)\n .insertSub(i_comment_line[0][19]).pin(\"GYR_CGM\").vMeas().average(128).measWait(10 ms)\n .insertSub(i_comment_line[0][20]).pin(\"GYR_CGM\").vMeas().average(128).measWait(10 ms)\n .insertSub(i_comment_line[0][21]).pin(\"GYR_CGM\").vMeas().average(128).measWait(10 ms)\n .insertSub(i_comment_line[0][22]).pin(\"GYR_CGM\").vMeas().average(128).measWait(10 ms)\n .insertSub(i_comment_line[0][23]).pin(\"GYR_CGM\").vMeas().average(128).measWait(10 ms)\n .insertSub(i_comment_line[0][24]).pin(\"GYR_CGM\").vMeas().average(128).measWait(10 ms)\n .insertSub(i_comment_line[0][25]).pin(\"GYR_CGM\").vMeas().average(128).measWait(10 ms)\n .insertSub(i_comment_line[0][26]).pin(\"GYR_CGM\").vMeas().average(128).measWait(10 ms)\n// .insertSub(i_comment_line[0][27]).pin(\"OCSB\").relay(TA::ppmuRly_offALL)////{uav('OCSB', False)}\n .execute();\n RDI_END();\n\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n FuncPrint(\"i_funcRes0\", i_funcRes0[curSite]);\n \t ARRAY_D ad_jsubresults_GYR_CGM;\n ad_jsubresults_GYR_CGM = rdi.id(\"dcid_0\").getMultiValue(\"GYR_CGM\");\n \t \t for ( int i = 0; i < 24; i++)\n \t \t {\n \t \t\t d_V_CBGM_C[curSite][i] = ad_jsubresults_GYR_CGM[i];\n \t \t\t FuncPrint(s_Func_Test_Name_Add_2Num(\"V_CBGM_C_\",i*2),d_V_CBGM_C[curSite][i]);\n \t \t }\n FOR_EACH_SITE_END();\n\n rdi.dc().pin(\"GYR_CGM\").disconnect().execute();\n rdi.util().pin(\"K5,K9\").setOff().execute();\n\n\n ON_FIRST_INVOCATION_END();\n\n \t for ( int i = 0; i < 16; i++)\n \t {\n \t\t TestLog(s_Func_Test_Name_Add_2Num(\"V_CBGM_C_OCSB1P5V_\",(i*2)),d_V_CBGM_C[curSite][i]);\n \t }\n\n \t for ( int i = 0; i < 8; i++)\n \t {\n \t\t TestLog(s_Func_Test_Name_Add_2Num(\"V_CBGM_C_OCSB1P85V_\",(i*2+20)),d_V_CBGM_C[curSite][i+16]);\n \t }\n\n i_funcRes[curSite] = i_funcRes0[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T16_12_cgm_pad_char_R1\", T16_12_cgm_pad_char_R1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description:\n# - Enable GYR_CLK_POS_P on pad INT1 (to check frequency)\n# - frequency of 35kHz applied to ASCX/OCSB\n# - This frequency is routed through the test module to the signals GYR_D_TINP/N, which are applied\n# to the test inputs IN_TEST_P/_N on the GYRO DRIVE CV. It acts as the control frequency to the PLL, and latest\n# after 5ms the PLL is locked. Its frequency is routed to the INT1 output, and the (nearly constant)\n# phase voltage POUT_P/_N is switched to the signals POUT_P/_N_TM and routed through\n# the GYRO_CORE.GYRO_ANALOG_TESTMUX and (as GYR_TIO_P/_N) through the test_module to the pads ASCX/INT2.\n# On INT1 the same frequency as on ASCX is expected.\n#############################################################################################################\ncmt('Version info: $Revision: 3 $ $Author: luz3sgh $ $Date: 2024/05/20 07:21:56 GMT $')\n\nwac('EXT_MODE', 0xc00f) # Switch to the TEST register page\nwac(\"DTB1\", 0x0030) # Enable GYR_CLK_POS_P on pad INT1\nwac('TM_CONF', 0x0003) # tm_se_meas=0 tm_bus_inv=0 tm_buf_pwrup=3 (tbuf_tb1_tb2_on)\n # bus_inv. because the power_ana_test_multiplexor_2 provides VSS_A/VDDA\nwac('TM_GYR', 0x0001) # tm_gyr_s_sel=0 tm_gyr_d_sel=1\nwac('TM_PIN', 0x1155) # tm_asdx_sel=2 (BUF2_OUT) tm_asdx_en=1 tm_int2_sel=2 (BUF1_OUT) tm_int2_en=1\n # tm_ascx_sel=0 (NC) tm_ascx_en=1 tm_ocsb_sel=0 (NC) tm_ocsb_en=1\n # enable ASCX/OCSB; otherwise VSS to the PAD\nwac('TM_ADDR', 0x0606) # tm_cfg=6 (GYR_TIOP/N= POUT_P/_N) tm_addr=6 (GYR_D_TIN; BUF1/2_INP= GYR_TIOP/N)\n# save register value\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nras('ANA_TRM_CAP_PROG_DRV_REG', 'ANA_TRM_CAP_PROG_DRV')\nwac('OCP_MASK', 0x001f) # activate bits 4:0\nwr('ANA_TRM_CAP_PROG_DRV', 0x001f) # Set gyr_trm_cap_prog_cv_d to min gain\nrac('ANA_TRM_CAP_PROG_DRV', 0x001f, 0x001f) # Check register setting \nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('GYR_TEST_EN', 0x8000) # gyr_test_vco_en=0; gyr_test_cvs2atb_en=1, gyr_test_cvs2cvd_en=0\nbw('OCSB', 0)\n# Measure PLL lock at 34.829 kHz\ncmt('TOI: change the voltage on ASCX to 1.2V')\nclk('ASCX', 1/(97*4*74e-9)) # Apply 34.829 kHz clock on ASCX\ndly(5e-3) # settling time of the PLL\ngaf('F_PLL_LOCK_34829', 'INT1')\nlog('F_PLL_LOCK_34829')\ncmt('Execute following 2 voltage measurements at the same time')\ndly(74e-9) # dummy dly to seprate gaf/gav,only for ATE coding convinience \ngav('V_PLL_LOCK_P_RAW', 'INT2')\ncalc('V_PLL_LOCK_34829_P', 'V_PLL_LOCK_P_RAW', '-', 'V_OFF1_ECOFF')\nlog('V_PLL_LOCK_34829_P')\ngav('V_PLL_LOCK_N_RAW', 'ASDX')\ncalc('V_PLL_LOCK_34829_N', 'V_PLL_LOCK_N_RAW', '-', 'V_OFF2_ECOFF')\nlog('V_PLL_LOCK_34829_N')\ncalc('V_PLL_LOCK_34829', 'V_PLL_LOCK_34829_P', '-', 'V_PLL_LOCK_34829_N')\nlog('V_PLL_LOCK_34829')\n# Measure PLL lock at 35.562 kHz\ncmt('TOI: change the voltage on ASCX to 1.2V')\nclk('ASCX', 1/(95*4*74e-9)) # Apply 35.562 kHz clock on ASCX\ndly(5e-3) # settling time of the PLL\ngaf('F_PLL_LOCK_35562', 'INT1')\nlog('F_PLL_LOCK_35562')\ncmt('Execute following 2 voltage measurements at the same time')\ndly(74e-9) # dummy dly to seprate gaf/gav,only for ATE coding convinience \ngav('V_PLL_LOCK_P_RAW', 'INT2')\ncalc('V_PLL_LOCK_35562_P', 'V_PLL_LOCK_P_RAW', '-', 'V_OFF1_ECOFF')\nlog('V_PLL_LOCK_35562_P')\ngav('V_PLL_LOCK_N_RAW', 'ASDX')\ncalc('V_PLL_LOCK_35562_N', 'V_PLL_LOCK_N_RAW', '-', 'V_OFF2_ECOFF')\nlog('V_PLL_LOCK_35562_N')\ncalc('V_PLL_LOCK_35562', 'V_PLL_LOCK_35562_P', '-', 'V_PLL_LOCK_35562_N')\nlog('V_PLL_LOCK_35562')\n# Measure PLL lock at 34.125 kHz\ncmt('TOI: change the voltage on ASCX to 1.2V')\nclk('ASCX', 1/(99*4*74e-9)) # Apply 34.125 kHz clock on ASCX\ndly(5e-3) # settling time of the PLL\ngaf('F_PLL_LOCK_34125', 'INT1')\nlog('F_PLL_LOCK_34125')\ncmt('Execute following 2 voltage measurements at the same time')\ndly(74e-9) # dummy dly to seprate gaf/gav,only for ATE coding convinience \ngav('V_PLL_LOCK_P_RAW', 'INT2')\ncalc('V_PLL_LOCK_34125_P', 'V_PLL_LOCK_P_RAW', '-', 'V_OFF1_ECOFF')\nlog('V_PLL_LOCK_34125_P')\ngav('V_PLL_LOCK_N_RAW', 'ASDX')\ncalc('V_PLL_LOCK_34125_N', 'V_PLL_LOCK_N_RAW', '-', 'V_OFF2_ECOFF')\nlog('V_PLL_LOCK_34125_N')\ncalc('V_PLL_LOCK_34125', 'V_PLL_LOCK_34125_P', '-', 'V_PLL_LOCK_34125_N')\nlog('V_PLL_LOCK_34125')\n# Enable VCO free-running frequency\nwac('GYR_TEST_EN', 0x0004) # Enable VCO free-running frequency as in T01_20_switch_on_GYR_wo_drive\n# write back register value\nwri('ANA_TRM_CAP_PROG_DRV', 'ANA_TRM_CAP_PROG_DRV_REG')\nras('ANA_TRM_CAP_PROG_DRV_REG_RD', 'ANA_TRM_CAP_PROG_DRV')\ncmt('This test item is a functionl fail if ANA_TRM_CAP_PROG_DRV_REG_RD != ANA_TRM_CAP_PROG_DRV_REG')\n#clean-up\nuclk('ASCX')\nubw('OCSB')\nwac('EXT_MODE', 0xc00f) # Switch to the TEST register page\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\nwac('TM_GYR', 0x0000) # reset value\nwac('DTB1', 0x0000) # Disable DTM\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T16_13_PLL_Lock_Test_V3: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n INT split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &split_pat_flag);\n vector s_splited_pat_name;\n const int split_count = 5; // Alarm:: split_count need manual confirm.\n s_splited_pat_name.resize(split_count);\n\n static int ANA_TRM_CAP_PROG_DRV_REG[xNSitES];\n static int ANA_TRM_CAP_PROG_DRV_REG_RD[xNSitES];\n static double F_PLL_LOCK_34829[xNSitES];\n// static double V_PLL_LOCK_P_RAW[xNSitES];\n// static double V_PLL_LOCK_N_RAW[xNSitES];\n static double F_PLL_LOCK_35562[xNSitES];\n static double F_PLL_LOCK_34125[xNSitES];\n \n string Mean_Port = \"Non_INT1_ASCX_Port\";\n string Measure_Port = \"INT1_Port\";\n string CLK_Port = \"ASCX_Port\";\n static double sample_period_INT1;\n ARRAY_LL ANA_TRM_CAP_PROG_DRV_REG_rtv(xNSitES);\n const int Wri_Bit_Length = 33;\n const int Wri_Bit_Position = 31;\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n\t rdi.enableOre(oreFlag);\n\t rdi.oreFile(\"./ORE_Files/rdi_ore_T16_13_PLL_LOCK_TEST.xml\");\n\n GET_TESTSUITE_NAME(test_name);\n if (split_pat_flag)\n {\n split_pattern(s_label_name,\"gaf\",\"wri\",split_pat_flag,s_splited_pat_name);\n }\n else\n {\n for (int i = 0; i highZ\nwac('TM_CONF' , 0x0000) # Disable TBs\nwac('EXT_MODE', 0xc00d) # Switch to PMU page\nwac(\"PMU_TEST_OWR\",0x0030) # enable VDDT (required for Gyro BG and Bias)\nwac(\"OCP_MASK\", 0x0010) # Set masking register\nwr(\"ANA_TEST_PWR\",0x0010) # vddg_ext_en to 1: connecting VDDG to IO_OCSB_LOWRES\nrac(\"ANA_TEST_PWR\", 0x0010, 0x0010) # Check register setting\nwr(\"OCP_MASK\", 0x0000) # Reset masking register\nrac(\"OCP_MASK\", 0xffff) # Check masking register reset\ndly(100e-6)\nsav('OCSB', 1.8) # Set voltage on OCSB\ndly(100e-6)\n\n#bakup register setting\nras('ANA_TRM_RES_PROG0_RB', 'ANA_TRM_RES_PROG0')\n#set trim bit & enable cgm high V\ncmt('Voltage may go up to 18V, and should be measured with high impedance channel')\nwcb('gyr_trm_res_prog_ldovcm',30) # Reg ANA_TRM_RES_PROG0<5:0> \nwac(\"GYR_TEST_OWR1\",0x0000) # clean unnessary gyro modules\n#skip setting of cvd,ampli,phase,ctat,vddg,dmyload,comp\nwcb('owr_gyr_pwrup_cp_vgm',0x1) # must have \nwcb('owr_gyr_pwrup_vco',0x1) # must have \nwcb('owr_gyr_pwrup_vddg3v',0x1) # must have \nwcb('owr_pc_ib_gyr_en',0x1) # must have \nwcb('owr_pc_bg_gyr_en',0x1) # must have \nwcb('gyr_owr_en',0x1)\ncmt('Voltage may go up to 18V, and should be measured with high impedance channel')\ndly(3e-3)\ncmt(f'Measure voltage V_CGM_30_HVS at pad GYR_CGM')\nlog(f'V_CGM_30_HVS')\n\n#restore register setting & clean\nwri('ANA_TRM_RES_PROG0','ANA_TRM_RES_PROG0_RB') # Reg ANA_TRM_RES_PROG0<5:0> \nuav('OCSB') # unset voltage on OCSB\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\nwac('EXT_MODE',0xc00d) # Page Test, Reg PMU\nwcb('owr_vddg_en',0x0) # GYR_TEST_OWR1 bit10\nwcb('gyr_owr_en',0x0) # GYR_TEST_OWR1 bit0\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T16_19_cgm_hvs_test_V3: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n INT split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &split_pat_flag);\n vector s_splited_pat_name;\n const int split_count = 3; // Alarm:: split_count need manual confirm.\n s_splited_pat_name.resize(split_count);\n vector i_comment_line[split_count];\n\n static int ANA_TRM_RES_PROG0_RB[xNSitES];\n ARRAY_LL ANA_TRM_RES_PROG0_RB_rtv(xNSitES);\n const int Wri_Bit_Length = 33;\n const int Wri_Bit_Position = 31;\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n GET_TESTSUITE_NAME(test_name);\n if (split_pat_flag)\n {\n split_pattern(s_label_name,\"wri\",split_pat_flag,s_splited_pat_name);\n }\n else\n {\n for (int i = 0; i i_comment_line0;\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n\n// RDI_BEGIN(mode);\n// rdi.burstId(\"T16_20_cgm_monitor_test_V5_PAT_id\");\n// rdi.digCap(\"T16_20_cgm_monitor_test_V5_Digcap_id\").vecVarOnly().pin(\"SDO\").bitPerWord(1).samples(4).execute();\n// rdi.dc(\"T16_20_cgm_monitor_test_V5DC_id\").label(s_label_name)\n//// .insertSub(0).pin(\"INT2\").vForce(0.1).iRange(40 mA)\n//// .insertSub(0).wait(1 ms)\n//// .insertSub(0).pin(\"INT2\").vForce(0.15).iRange(40 mA)\n//// .insertSub(0).wait(1 ms)\n//// .insertSub(0).pin(\"INT2\").vForce(0.2).iRange(40 mA)\n//// .insertSub(0).wait(1 ms)\n//// .insertSub(0).pin(\"INT2\").vForce(0.25).iRange(40 mA)\n//// .insertSub(0).wait(1 ms)\n//// .insertSub(0).pin(\"INT2\").vForce(0.3).iRange(40 mA)\n//// .insertSub(0).wait(1 ms)\n//// .insertSub(0).pin(\"INT2\").vForce(0.35).iRange(40 mA)\n//// .insertSub(0).wait(1 ms)\n//// .insertSub(0).pin(\"INT2\").vForce(0.4).iRange(40 mA)\n//// .insertSub(0).wait(1 ms)\n//// .insertSub(0).pin(\"INT2\").vForce(0.45).iRange(40 mA)\n//// .insertSub(0).wait(1 ms)\n// .insertSub(0).pin(\"INT2\").vForce(0.5).iRange(40 mA)\n// .insertSub(0).wait(1 ms)\n// .insertSub(0).pin(\"INT2\").vForce(0.55).iRange(40 mA)\n// .insertSub(0).wait(1 ms)\n// .insertSub(0).pin(\"INT2\").vForce(0.6).iRange(40 mA)\n// .insertSub(0).wait(1 ms)\n// .insertSub(0).pin(\"INT2\").vForce(0.65).iRange(40 mA)\n// .insertSub(0).wait(1 ms)\n// .insertSub(0).pin(\"INT2\").vForce(0.7).iRange(40 mA)\n// .insertSub(0).wait(1 ms)\n// .insertSub(0).pin(\"INT2\").vForce(0.75).iRange(40 mA)\n// .insertSub(0).wait(1 ms)\n// .insertSub(0).pin(\"INT2\").vForce(0.8).iRange(40 mA)\n// .insertSub(0).wait(1 ms)\n// .insertSub(0).pin(\"INT2\").vForce(0.85).iRange(40 mA)\n// .insertSub(0).wait(1 ms)\n// .insertSub(0).pin(\"INT2\").vForce(0.9).iRange(40 mA)\n// .insertSub(0).wait(1 ms)\n// .insertSub(0).pin(\"INT2\").vForce(0.93).iRange(40 mA)\n//// .insertSub(i_comment_line0[0]).pin(\"INT2\").vForce(0.93).iRange(40 mA)\n// .insertSub(i_comment_line0[1]).pin(\"INT2\").vForce(0.83).iRange(40 mA)\n// .insertSub(i_comment_line0[1]).wait(1 ms)\n// .insertSub(i_comment_line0[1]).pin(\"INT2\").vForce(0.805).iRange(40 mA)\n// .insertSub(i_comment_line0[1]).wait(1 ms)\n// .insertSub(i_comment_line0[1]).pin(\"INT2\").vForce(0.78).iRange(40 mA)\n// .insertSub(i_comment_line0[1]).wait(1 ms)\n// .insertSub(i_comment_line0[1]).pin(\"INT2\").vForce(0.755).iRange(40 mA)\n// .insertSub(i_comment_line0[1]).wait(1 ms)\n// .insertSub(i_comment_line0[1]).pin(\"INT2\").vForce(0.73).iRange(40 mA)\n// .insertSub(i_comment_line0[1]).wait(1 ms)\n// .insertSub(11136).pin(\"INT2\").vForce(0.73).iRange(40 mA)\n// .insertSub(11136).wait(1 ms)\n// .insertSub(11136).pin(\"INT2\").vForce(0.77).iRange(40 mA)\n// .insertSub(11136).wait(1 ms)\n// .insertSub(11136).pin(\"INT2\").vForce(0.82).iRange(40 mA)\n// .insertSub(11136).wait(1 ms)\n// .insertSub(11136).pin(\"INT2\").vForce(0.87).iRange(40 mA)\n// .insertSub(11136).wait(1 ms)\n// .insertSub(11136).pin(\"INT2\").vForce(0.92).iRange(40 mA)\n// .insertSub(11136).wait(1 ms)\n// .insertSub(11136).pin(\"INT2\").vForce(0.97).iRange(40 mA)\n// .insertSub(11136).wait(1 ms)\n// .insertSub(11136).pin(\"INT2\").vForce(1.02).iRange(40 mA)\n// .insertSub(11136).wait(1 ms)\n// .insertSub(11136).pin(\"INT2\").vForce(1.07).iRange(40 mA)\n// .insertSub(11136).wait(1 ms)\n// .insertSub(11136).pin(\"INT2\").vForce(1.12).iRange(40 mA)\n// .insertSub(11136).wait(1 ms)\n// .insertSub(11136).pin(\"INT2\").vForce(1.17).iRange(40 mA)\n// .insertSub(11136).wait(1 ms)\n// .insertSub(11136).pin(\"INT2\").vForce(1.22).iRange(40 mA)\n// .insertSub(11136).wait(1 ms)\n//// .insertSub(i_comment_line0[3]).pin(\"INT2\").vForce(1.22).iRange(40 mA)\n// .insertSub(i_comment_line0[4]).pin(\"INT2\").vForce(1.22).iRange(40 mA)\n// .insertSub(11136).wait(1 ms)\n// .insertSub(i_comment_line0[4]).pin(\"INT2\").vForce(1.17).iRange(40 mA)\n// .insertSub(11136).wait(1 ms)\n// .insertSub(i_comment_line0[4]).pin(\"INT2\").vForce(1.12).iRange(40 mA)\n// .insertSub(11136).wait(1 ms)\n// .insertSub(i_comment_line0[4]).pin(\"INT2\").vForce(1.07).iRange(40 mA)\n// .insertSub(11136).wait(1 ms)\n// .insertSub(i_comment_line0[4]).pin(\"INT2\").vForce(1.02).iRange(40 mA)\n// .insertSub(11136).wait(1 ms)\n//// .insertSub(i_comment_line0[5]).pin(\"INT2\").relay(TA::ppmuRly_offALL,TA::ppmuRly_offALL)\n// .execute();\n// RDI_END();\n\n\n i_comment_line0 = search_comment_line(\"T16_20_cgm_monitor_test_R2_AVCba_PYba_test1half\");\n print_key_comment(\"T16_20_cgm_monitor_test_R2_AVCba_PYba_test1half\", i_comment_line0, printFlag);\n\n\n// cout << \"Starting first_part_test@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\" << endl;\n double start_v =0.0;\n double stop_v = 0.93;\n double step_v = (stop_v-start_v)/20;\n\n for(int i=0;i<20;i++)\n { double force_v = start_v + step_v*i;\n \t rdi.dc().pin(\"INT2\").vForce(force_v).execute();\n \t rdi.wait(1 ms);\n }\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T16_20_cgm_monitor_test_V5_PAT_id1\");\n rdi.digCap(\"T16_20_cgm_monitor_test_V5_Digcap_id1\").vecVarOnly().pin(\"SDO\").bitPerWord(1).samples(2).execute();\n rdi.dc(\"T16_20_cgm_monitor_test_V5DC_id1\").label(\"T16_20_cgm_monitor_test_R2_AVCba_PYba_test1half\")\n // .insertSub(0).pin(\"INT2\").vForce(0.1).iRange(40 mA)\n // .insertSub(0).wait(1 ms)\n // .insertSub(0).pin(\"INT2\").vForce(0.2).iRange(40 mA)\n // .insertSub(0).wait(1 ms)\n // .insertSub(0).pin(\"INT2\").vForce(0.3).iRange(40 mA)\n // .insertSub(0).wait(1 ms)\n // .insertSub(0).pin(\"INT2\").vForce(0.4).iRange(40 mA)\n // .insertSub(0).wait(1 ms)\n // .insertSub(0).pin(\"INT2\").vForce(0.5).iRange(40 mA)\n // .insertSub(0).wait(1 ms)\n // .insertSub(0).pin(\"INT2\").vForce(0.6).iRange(40 mA)\n // .insertSub(0).wait(1 ms)\n // .insertSub(0).pin(\"INT2\").vForce(0.7).iRange(40 mA)\n // .insertSub(0).wait(1 ms)\n // .insertSub(0).pin(\"INT2\").vForce(0.8).iRange(40 mA)\n // .insertSub(0).wait(1 ms)\n // .insertSub(0).pin(\"INT2\").vForce(0.9).iRange(40 mA)\n // .insertSub(0).wait(1 ms)\n .insertSub(0).pin(\"INT2\").vForce(0.93).iRange(40 mA)\n // .insertSub(i_comment_line0[0]).pin(\"INT2\").vForce(0.93).iRange(40 mA)\n .insertSub(i_comment_line0[1]).pin(\"INT2\").vForce(0.83).iRange(40 mA)\n .insertSub(i_comment_line0[1]).wait(1 ms)\n .insertSub(i_comment_line0[1]).pin(\"INT2\").vForce(0.805).iRange(40 mA)\n .insertSub(i_comment_line0[1]).wait(1 ms)\n .insertSub(i_comment_line0[1]).pin(\"INT2\").vForce(0.78).iRange(40 mA)\n .insertSub(i_comment_line0[1]).wait(1 ms)\n .insertSub(i_comment_line0[1]).pin(\"INT2\").vForce(0.755).iRange(40 mA)\n .insertSub(i_comment_line0[1]).wait(1 ms)\n .insertSub(i_comment_line0[1]).pin(\"INT2\").vForce(0.73).iRange(40 mA)\n .insertSub(i_comment_line0[1]).wait(1 ms)\n // .insertSub(10176).pin(\"INT2\").vForce(1.22).iRange(40 mA)\n // .insertSub(i_comment_line0[3]).pin(\"INT2\").vForce(1.22).iRange(40 mA)\n // .insertSub(i_comment_line0[4]).pin(\"INT2\").vForce(1.02).iRange(40 mA)\n // .insertSub(i_comment_line0[5]).pin(\"INT2\").relay(TA::ppmuRly_offALL,TA::ppmuRly_offALL)\n .execute();\n RDI_END();\n\n\n\n i_comment_line0 = search_comment_line(\"T16_20_cgm_monitor_test_R2_AVCba_PYba_test2half\");\n print_key_comment(\"T16_20_cgm_monitor_test_R2_AVCba_PYba_test2half\", i_comment_line0, printFlag);\n\n\n\n start_v =0.73;\n stop_v = 1.22;\n step_v = (stop_v-start_v)/20;\n\n for(int i=0;i<20;i++)\n { double force_v = start_v + step_v*i;\n \t rdi.dc().pin(\"INT2\").vForce(force_v).execute();\n \t rdi.wait(1 ms);\n }\n\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T16_20_cgm_monitor_test_V5_PAT_id2\");\n rdi.digCap(\"T16_20_cgm_monitor_test_V5_Digcap_id2\").vecVarOnly().pin(\"SDO\").bitPerWord(1).samples(2).execute();\n rdi.dc(\"T16_20_cgm_monitor_test_V5DC_id2\").label(\"T16_20_cgm_monitor_test_R2_AVCba_PYba_test2half\")\n // .insertSub(0).pin(\"INT2\").vForce(0.73).iRange(40 mA)\n // .insertSub(0).wait(1 ms)\n // .insertSub(0).pin(\"INT2\").vForce(0.83).iRange(40 mA)\n // .insertSub(0).wait(1 ms)\n // .insertSub(0).pin(\"INT2\").vForce(0.93).iRange(40 mA)\n // .insertSub(0).wait(1 ms)\n // .insertSub(0).pin(\"INT2\").vForce(1.03).iRange(40 mA)\n // .insertSub(0).wait(1 ms)\n // .insertSub(0).pin(\"INT2\").vForce(1.13).iRange(40 mA)\n // .insertSub(0).wait(1 ms)\n .insertSub(0).pin(\"INT2\").vForce(1.22).iRange(40 mA)\n // .insertSub(i_comment_line0[0]).pin(\"INT2\").vForce(0.93).iRange(40 mA)\n .insertSub(i_comment_line0[1]).pin(\"INT2\").vForce(1.17).iRange(40 mA)\n .insertSub(i_comment_line0[1]).wait(1 ms)\n .insertSub(i_comment_line0[1]).pin(\"INT2\").vForce(1.12).iRange(40 mA)\n .insertSub(i_comment_line0[1]).wait(1 ms)\n .insertSub(i_comment_line0[1]).pin(\"INT2\").vForce(1.07).iRange(40 mA)\n .insertSub(i_comment_line0[1]).wait(1 ms)\n .insertSub(i_comment_line0[1]).pin(\"INT2\").vForce(1.02).iRange(40 mA)\n .insertSub(i_comment_line0[1]).wait(1 ms)\n // .insertSub(10176).pin(\"INT2\").vForce(1.22).iRange(40 mA)\n // .insertSub(i_comment_line0[3]).pin(\"INT2\").vForce(1.22).iRange(40 mA)\n // .insertSub(i_comment_line0[4]).pin(\"INT2\").vForce(1.02).iRange(40 mA)\n // .insertSub(i_comment_line0[5]).pin(\"INT2\").relay(TA::ppmuRly_offALL,TA::ppmuRly_offALL)\n .execute();\n RDI_END();\n\n ON_FIRST_INVOCATION_END();\n\n\n ARRAY_I Vec1=rdi.id(\"T16_20_cgm_monitor_test_V5_Digcap_id1\").getVector();\n ARRAY_I Vec2=rdi.id(\"T16_20_cgm_monitor_test_V5_Digcap_id2\").getVector();\n int cp_vgm_error_min_high = Vec1[0];\n int cp_vgm_error_min_low = Vec1[1];\n int cp_vgm_error_typ_high = Vec2[0];\n int cp_vgm_error_typ_low = Vec2[1];\n int Func_result1 = rdi.id(\"T16_20_cgm_monitor_test_V5_PAT_id1\").getBurstPassFail();\n int Func_result2 = rdi.id(\"T16_20_cgm_monitor_test_V5_PAT_id2\").getBurstPassFail();\n FuncPrint(\"Func_result1\", Func_result1);\n FuncPrint(\"Func_result2\", Func_result2);\n FuncPrint(\"CP_VGM_ERROR_MIN_HIGH\", cp_vgm_error_min_high);\n FuncPrint(\"CP_VGM_ERROR_MIN_LOW\", cp_vgm_error_min_low);\n FuncPrint(\"CP_VGM_ERROR_TYP_HIGH\", cp_vgm_error_typ_high);\n FuncPrint(\"CP_VGM_ERROR_TYP_LOW\", cp_vgm_error_typ_low);\n\n\n\n int Func_result = Func_result1 && Func_result2;\n FuncPrint(\"Func_result\", Func_result);\n\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"CP_VGM_ERROR_MIN_HIGH\", cp_vgm_error_min_high);\n TestLog(\"CP_VGM_ERROR_MIN_LOW\", cp_vgm_error_min_low);\n TestLog(\"CP_VGM_ERROR_TYP_HIGH\", cp_vgm_error_typ_high);\n TestLog(\"CP_VGM_ERROR_TYP_LOW\", cp_vgm_error_typ_low);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T16_20_cgm_monitor_test_V5\", T16_20_cgm_monitor_test_V5);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: Sweep external DC voltage on the external pad check comparator's hysteresis\n# refer to https://inside-docupedia.bosch.com/confluence2/display/ach/VGM+Monitor+Test+Procedure\n# precondition: stc_ac, post condition: stc_acc\n# - route vgm montor test input to ANAIO1 (INT2)\n# - route compartor out to DTB(INT1)\n# - enable vgm-comparator and then trun on GYR\n# - set INT2 voltage from 100mV higher until 100mV lower than vref_threshold, check cp_vgm_error bit status\n#############################################################################################################\nfrom test_sub_functions import *\ncmt('Version info: $Revision: bai430aa_rel/2 $ $Author: luz3sgh $ $Date: 2024/09/25 06:04:01 GMT $')\n\ni_threshold_setting = [(\"min\",3, 0.93 ), # threshold 0.93V \n (\"typ\",12,1.22) ] # threshold 1.22V \nfor i in range(2):\n cmt(f\"Start loop\")\n wac('EXT_MODE', 0xc00f) # Switch to TST register page\n wac('TM_PIN' , 0x0009) # Set ATM ANAIO1(int2) as input\n wac('TM_ADDR' , 0x0004) # ADDR 0X04, CFG 0x00, VGM_COMP_TEST_IN to TB_P\n wac('DTB3', 0x0037) # Route VGM comparator output to INT1\n \n wac('EXT_MODE', 0xc00a) # Switch to TEMP_DP page\n wcb('gyr_trm_drv_abort_dis',0x1)\n wcb('gyr_trm_vgm_comp_cp_en',0x1)\n\n wac('EXT_MODE', 0xc00d) # Switch to PMU page\n wac('GYR_VGM_MON_CTRL', i_threshold_setting[i][1]<<2) #bit[5:2]\n\n seq_switch_on_GYR_wo_drive()\n \n for j in range(41): \n d_INT2_voltage = i_threshold_setting[i][2]-0.005*j\n sav(\"INT2\", d_INT2_voltage)\n dly(14.8e-6) # sim show roughly 11us required for toggle \n rsb(f'cp_vgm_error_{i_threshold_setting[i][0]}_{j:02d}','PMU_ERROR.gyr_cp_vgm_error')\n log(f'cp_vgm_error_{i_threshold_setting[i][0]}_{j:02d}')\n cmt(f'TOI, Find out the step in which cp_vgm_error_{i_threshold_setting[i][0]} stay at zero for the last time') \n cmt(f'log corrspond INT2 voltage as cp_vgm_threshold_{i_threshold_setting[i][0]}')\n log(f'cp_vgm_threshold_{i_threshold_setting[i][0]}')\n uav('INT2') # unset voltage\n \n seq_switch_off_GYR_wo_drive()\n #clean\n wac('EXT_MODE', 0xc00a) # Switch to TEMP_DP page\n wcb('gyr_trm_vgm_comp_cp_en',0x0)\n wcb('gyr_trm_drv_abort_dis',0x0)\n wac('EXT_MODE',0xc00f) # Switch to TST register page\n wac('DTB3', 0x0000) # default value\n wac('TM_ADDR', 0x0000) # Disable ATM\n wac('TM_PIN', 0x0000) # Reset pin config\n", "output": "/*****************************************************\n * T16_21_cgm_monitor_char_R1, description file version Notfound, avc file version Notfound\n * First Editor : jsh5sgh\n * Code generated with autocoding tool V2.9.1, in TOI2 standard way by module write_standard\n * Change History:\n * JSH5SGH R1: version update.\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T16_21_cgm_monitor_char_R1: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static int i_funcRes0[xNSitES];\n\n const string volt[] = {\"MIN\", \"TYP\"};\n const double thres[] = {0.93, 1.22};\n const int line_num[] = {1, 85};\n static int cp_vgm_error[xNSitES][2][41];\n static double cp_vgm_threshold[xNSitES][2];\n static int switch_point[xNSitES][2];\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T16_21_cgm_monitor_char}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 1] @ avcline 5441: {sav('INT2', 0.93, 2, 0.01, False, False)}\n valid comment[ 2] @ avcline 5564: {log('cp_vgm_error_min_00', '', '', 0, 0)}\n\n valid comment[ 3] @ avcline 5949: {sav('INT2', 0.925, 2, 0.01, False, False)}\n valid comment[ 4] @ avcline 6072: {log('cp_vgm_error_min_01', '', '', 0, 0)}\n ...\n valid comment[ 81] @ avcline 25761: {sav('INT2', 0.73, 2, 0.01, False, False)}\n valid comment[ 82] @ avcline 25884: {log('cp_vgm_error_min_40', '', '', 0, 0)}\n\n valid comment[ 83] @ avcline 25885: {cmt: TOI, Find out the step in which cp_vgm_error_min stay at zero for the last time}\n valid comment[ 83] @ avcline 25885: {cmt: log corrspond INT2 voltage as cp_vgm_threshold_min}\n valid comment[ 83] @ avcline 25885: {log('cp_vgm_threshold_min', '', '', 0, 0)}\n valid comment[ 84] @ avcline 25886: {uav('INT2', False)}\n valid comment[ 85] @ avcline 33936: {sav('INT2', 1.22, 2, 0.01, False, False)}\n valid comment[ 86] @ avcline 34059: {log('cp_vgm_error_typ_00', '', '', 0, 0)}\n\n valid comment[ 87] @ avcline 34444: {sav('INT2', 1.215, 2, 0.01, False, False)}\n valid comment[ 88] @ avcline 34567: {log('cp_vgm_error_typ_01', '', '', 0, 0)}\n ...\n valid comment[165] @ avcline 54256: {sav('INT2', 1.02, 2, 0.01, False, False)}\n valid comment[166] @ avcline 54379: {log('cp_vgm_error_typ_40', '', '', 0, 0)}\n\n valid comment[167] @ avcline 54380: {cmt: TOI, Find out the step in which cp_vgm_error_typ stay at zero for the last time}\n valid comment[167] @ avcline 54380: {cmt: log corrspond INT2 voltage as cp_vgm_threshold_typ}\n valid comment[167] @ avcline 54380: {log('cp_vgm_threshold_typ', '', '', 0, 0)}\n valid comment[168] @ avcline 54381: {uav('INT2', False)}\n valid comment[169] @ avcline 59428: {Test End: T16_21_cgm_monitor_char}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n \t\t rdi.digCap(\"digcapid_0\").vecVarOnly().pin(\"SDO\").capMode(TA::SER).bitPerWord(1).samples(41*2).execute();\n for(int i=0; i<2; i++) {\n \t for(int j=0; j<41; j++) {\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n\t\t\t\t\t\t\t\t.insertSub(i_comment_line[0][line_num[i]+2*i+1]).pin(\"INT2\").vForce(thres[i] - j*0.005 V)//{sav('INT2', 0.93, 2, 0.01, False, False)}\n\t\t .cont();\n \t }\n }\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][168]).pin(\"INT2\").relay(TA::ppmuRly_offALL)////{uav('INT2', False)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n ARRAY_I aI_Captured_0 = rdi.id(\"digcapid_0\").getVector(\"SDO\");\n for(int i=0; i<41; i++) {\n \t cp_vgm_error[curSite][0][i] = aI_Captured_0[i];\n \t cp_vgm_error[curSite][1][i] = aI_Captured_0[i+41];\n \t FuncPrint(s_Func_Test_Name_Add_2Num(\"cp_vgm_error_\"+volt[0]+\"_\", i), cp_vgm_error[curSite][0][i]);\n \t FuncPrint(s_Func_Test_Name_Add_2Num(\"cp_vgm_error_\"+volt[1]+\"_\", i), cp_vgm_error[curSite][1][i]);\n }\n switch_point[curSite][0] = Find_first_Switch_point_index(cp_vgm_error[curSite][0],0.5, 41);\n switch_point[curSite][1] = Find_first_Switch_point_index(cp_vgm_error[curSite][1],0.5, 41);\n\n cp_vgm_threshold[curSite][0] = cp_vgm_error[curSite][0][switch_point[curSite][0]];\n cp_vgm_threshold[curSite][1] = cp_vgm_error[curSite][1][switch_point[curSite][1]];\n FuncPrint(\"cp_vgm_threshold_\"+volt[0], cp_vgm_threshold[curSite][0]);\n FuncPrint(\"cp_vgm_threshold_\"+volt[1], cp_vgm_threshold[curSite][1]);\n\n FOR_EACH_SITE_END();\n\n\n ON_FIRST_INVOCATION_END();\n for(int i=0; i<41; i++) {\n \t TestLog(s_Func_Test_Name_Add_2Num(\"CP_VGM_ERROR_\"+volt[0]+\"_\", i), cp_vgm_error[curSite][0][i]);\n \t TestLog(s_Func_Test_Name_Add_2Num(\"CP_VGM_ERROR_\"+volt[1]+\"_\", i), cp_vgm_error[curSite][1][i]);\n }\n TestLog(\"CP_VGM_THRESHOLD_\"+volt[0], cp_vgm_threshold[curSite][0]);\n TestLog(\"CP_VGM_THRESHOLD_\"+volt[1], cp_vgm_threshold[curSite][1]);\n\n i_funcRes[curSite] = i_funcRes0[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T16_21_cgm_monitor_char_R1\", T16_21_cgm_monitor_char_R1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: VERF VGM COMP voltage measure\n#############################################################################################################\ncmt('Version info: $Revision: 1 $ $Author: luz3sgh $ $Date: 2024/06/13 08:09:53 GMT $')\n# Measure VREF_VGM_COMP_GYR\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_CONF', 0x0111) # tm_se_meas=1 tm_bus_inv=1 tm_buf_pwrup=1 (tbuf_tb1_on)\nwac('TM_PIN', 0x0005) # tm_int2_sel=2 (BUFF1_OUT) tm_int2_en=1\nwac('TM_ADDR', 0x0f0e) # tm_cfg=0xf; tm_addr=0xe (reference voltage/current test)\nwac('EXT_MODE', 0xc00d) # Switch to PMU(ANA) register page\nwcb('owr_gyr_pwrup_comp_cp_vgm',0x1) # enable vgm comparator\nwcb('gyr_comp_cp_owr_en',0x1)\ndly(100e-6)\ngav('V_VREF_VGM_COMP_RAW', 'INT2')\ncalc('V_VREF_VGM_COMP', 'V_VREF_VGM_COMP_RAW', '-', 'V_OFF1_ECOFF')\nlog('V_VREF_VGM_COMP')\nwcb('owr_gyr_pwrup_comp_cp_vgm',0x0) # turn off comparator\nwcb('gyr_comp_cp_owr_en',0x0) # disable overwirte enable bit \n#clean \nwac('EXT_MODE',0xc00f) # Switch to TST register page\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs and reset test config\n", "output": "/*****************************************************\n * T16_22_VREF_VGM_COMP_measure_V1, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T16_22_VREF_VGM_COMP_measure_V1: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static double d_V_VREF_VGM_COMP_RAW[xNSitES];\n static double d_V_VREF_VGM_COMP[xNSitES];\n static int i_funcRes0[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(d_V_VREF_VGM_COMP_RAW, 9.9, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T16_22_VREF_VGM_COMP_measure}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 1] @ avcline 1680: {gav('V_VREF_VGM_COMP_RAW', 'INT2', '', 2, 0.0001, True)}\n valid comment[ 1] @ avcline 1680: {calc('V_VREF_VGM_COMP', 'V_VREF_VGM_COMP_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 1] @ avcline 1680: {log('V_VREF_VGM_COMP', '', '', 0, 0)}\n valid comment[ 2] @ avcline 3149: {Test End: T16_22_VREF_VGM_COMP_measure}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][1]).pin(\"INT2\")/*, TA::BADC)*/.iForce(0).vMeas().average(128).measWait(2 ms).valueMode(TA::BADC)//.relay(TA::ppmuRly_onDC_offACPPMU)//, TA::ppmuRly_offALL)//V_VREF_VGM_COMP_RAW//{gav('V_VREF_VGM_COMP_RAW', 'INT2', '', 2, 0.0001, True)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n ARRAY_D ad_jsubresults_INT2; ad_jsubresults_INT2.resize(1); ad_jsubresults_INT2.init(-9.9);\n ad_jsubresults_INT2 = rdi.id(\"dcid_0\").getMultiValue(\"INT2\");\n \n d_V_VREF_VGM_COMP_RAW[curSite] = ad_jsubresults_INT2[0];\n FuncPrint(\"V_VREF_VGM_COMP_RAW\",d_V_VREF_VGM_COMP_RAW[curSite]);\n\n d_V_VREF_VGM_COMP[curSite] = ad_jsubresults_INT2[0] - V_OFF1_ECOFF[curSite];\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n\n ON_FIRST_INVOCATION_END();\n\n TestLog(\"V_VREF_VGM_COMP\",d_V_VREF_VGM_COMP[curSite]);\n i_funcRes[curSite] = i_funcRes0[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T16_22_VREF_VGM_COMP_measure_V1\", T16_22_VREF_VGM_COMP_measure_V1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: VERF VGM COMP voltage measure\n#############################################################################################################\ncmt('Version info: $Revision: 1 $ $Author: luz3sgh $ $Date: 2024/06/13 08:09:53 GMT $')\n# Measure VREF_VGM_COMP_GYR\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_CONF', 0x0111) # tm_se_meas=1 tm_bus_inv=1 tm_buf_pwrup=1 (tbuf_tb1_on)\nwac('TM_PIN', 0x0005) # tm_int2_sel=2 (BUFF1_OUT) tm_int2_en=1\nwac('TM_ADDR', 0x0f0e) # tm_cfg=0xf; tm_addr=0xe (reference voltage/current test)\ndly(100e-6)\nwac('EXT_MODE', 0xc00d) # Switch to PMU(ANA) register page\nwcb('owr_gyr_pwrup_comp_cp_vgm',0x1) # enable vgm comparator\nwcb('gyr_comp_cp_owr_en',0x1)\nfor n in range(3,16,1):\n wac('GYR_VGM_MON_CTRL',n<<2) # bit<5:2>, other bits not used, skip mask setting \n gav(f'V_VREF_VGM_COMP_RAW_{n:02d}', 'INT2')\n calc(f'V_VREF_VGM_COMP_{n:02d}', f'V_VREF_VGM_COMP_RAW_{n:02d}', '-', 'V_OFF1_ECOFF')\n log(f'V_VREF_VGM_COMP_{n:02d}')\nwac('GYR_VGM_MON_CTRL', 0x0030)\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs and reset test config\n", "output": "/*****************************************************\n * T16_23_VREF_VGM_COMP_char_V1, description file version Notfound, avc file version Notfound\n * First Editor : jsh5sgh\n * Code generated with autocoding tool V2.9.1, in TOI2 standard way by module write_standard\n * Change History:\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T16_23_VREF_VGM_COMP_char_V1: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static double V_VREF_VGM_COMP_RAW[xNSitES][13];\n static double V_VREF_VGM_COMP[xNSitES][13];\n\n static int i_funcRes0[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T16_23_VREF_VGM_COMP_char}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n\n valid comment[ 1] @ avcline 1872: {gav('V_VREF_VGM_COMP_RAW_03', 'INT2', '', 2, 0.0001, True)}\n valid comment[ 1] @ avcline 1872: {calc('V_VREF_VGM_COMP_03', 'V_VREF_VGM_COMP_RAW_03', '-', 'V_OFF1_ECOFF')}\n valid comment[ 1] @ avcline 1872: {log('V_VREF_VGM_COMP_03', '', '', 0, 0)}\n\n valid comment[ 2] @ avcline 2065: {gav('V_VREF_VGM_COMP_RAW_04', 'INT2', '', 2, 0.0001, True)}\n valid comment[ 2] @ avcline 2065: {calc('V_VREF_VGM_COMP_04', 'V_VREF_VGM_COMP_RAW_04', '-', 'V_OFF1_ECOFF')}\n valid comment[ 2] @ avcline 2065: {log('V_VREF_VGM_COMP_04', '', '', 0, 0)}\n ...\n valid comment[ 13] @ avcline 4188: {gav('V_VREF_VGM_COMP_RAW_15', 'INT2', '', 2, 0.0001, True)}\n valid comment[ 13] @ avcline 4188: {calc('V_VREF_VGM_COMP_15', 'V_VREF_VGM_COMP_RAW_15', '-', 'V_OFF1_ECOFF')}\n valid comment[ 13] @ avcline 4188: {log('V_VREF_VGM_COMP_15', '', '', 0, 0)}\n valid comment[ 14] @ avcline 5149: {Test End: T16_23_VREF_VGM_COMP_char}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n for (int i=0; i<13; i++) {\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][i+1]).pin(\"INT2\", TA::BADC).vMeas().average(64).measWait(1 ms)//V_VREF_VGM_COMP_RAW_03//{gav('V_VREF_VGM_COMP_RAW_03', 'INT2', '', 2, 0.0001, True)}\n .cont();\n }\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0]).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n ARRAY_D ad_jsubresults_INT2; ad_jsubresults_INT2.resize(13); ad_jsubresults_INT2.init(-9.9);\n ad_jsubresults_INT2 = rdi.id(\"dcid_0\").getMultiValue(\"INT2\");\n for(int i=0; i<13; i++) {\n \t V_VREF_VGM_COMP_RAW[curSite][i] = ad_jsubresults_INT2[i];\n FuncPrint(s_Func_Test_Name_Add_2Num(\"V_VREF_VGM_COMP_RAW_\", i+3), V_VREF_VGM_COMP_RAW[curSite][i]);\n\n V_VREF_VGM_COMP[curSite][i] = V_VREF_VGM_COMP_RAW[curSite][i] - V_OFF1_ECOFF[curSite];\n FuncPrint(s_Func_Test_Name_Add_2Num(\"V_VREF_VGM_COMP_\", i+3), V_VREF_VGM_COMP[curSite][i]);\n }\n FOR_EACH_SITE_END();\n ON_FIRST_INVOCATION_END();\n for(int i=0; i<13; i++) {\n \t TestLog(s_Func_Test_Name_Add_2Num(\"V_VREF_VGM_COMP_\", i+3), V_VREF_VGM_COMP[curSite][i]);\n }\n i_funcRes[curSite] = i_funcRes0[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T16_23_VREF_VGM_COMP_char_V1\", T16_23_VREF_VGM_COMP_char_V1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# Description:\n# An external frequency (35 kHz on ASCX/OCSB) is applied to the GYRO DRIVE CV input to control the DRIVE PLL,\n# as the gyro drive is switched off (see T01_20_switch_on_GYR_wo_drive).\n# The Sense CVs operate in the WLT (wafer level test mode). It means a constant current is added to the IDAC current\n# from the feed back ADC code. The modulation is done with the signal CLK_VEL_P (synchronized to the input clock\n# on ASCX/OCSB). The gain cap prog cv values are set to its maximal values; the cap_prog_qc values are set to\n# different values for the three channels (low enough to avoid saturation).\n# After enabling/changing the WLT signal generation the GYR (CV until DP) is reset via reconfiguration.\n# The results are logged in NS_RATE_WLT1/2_CH1/2/3 (WLT2 after a sign change).\n#############################################################################################################\ncmt('Version info: $Revision: 3 $ $Author: hmf1rt $ $Date: 2024/06/14 14:31:40 GMT $')\n# Configure ATM\nwac('EXT_MODE', 0xc00f) # Switch to TEST register page\nwac('TM_GYR', 0x0001) # Set tm_gyr_d_sel to connect ANAIO3+4 to gyro analog drive-in test mode\nwac('TM_PIN', 0x1100) # Enable ASCX and OCSB; keep pin_sel at high-Z configuration for ATM outputs\nwac('TM_ADDR', 0x0006) # Set GYR_D_TIN test mode\n# Trim cap_prog_cv and cap_prog_qc \nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('OCP_MASK', 0x3fff) # Set masking register\nwr('ANA_TRM_CAP_PROG_CH1', 0x0b9f) # Set gyr_trm_cap_prog_cv_ch1 to max; set gyr_trm_cap_prog_qc_ch1 to 0x4d\nwr('ANA_TRM_CAP_PROG_CH2', 0x0b9f) # Set gyr_trm_cap_prog_cv_ch2 to max; set gyr_trm_cap_prog_qc_ch2 to 0x4d\nwr('ANA_TRM_CAP_PROG_CH3', 0x0b9f) # Set gyr_trm_cap_prog_cv_ch3 to max; set gyr_trm_cap_prog_qc_ch3 to 0x4d\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n# Reduce the gain of all sense CVs\nwac('OCP_MASK',0x8000) # Set masking register\nwr('ANA_TRM_CAP_PROG_CH1', 0x8000) # Reduce the gain of all sense C/V\nrac('ANA_TRM_CAP_PROG_CH1', 0x8000, 0x8000) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n# Change modulation to square wave\nwac('EXT_MODE', 0xc00e) # Switch to GYR AFE register page\nwac('OCP_MASK', 0x0fc0) # Set masking register\nwr('GYR_TEST_FILT', 0x06c0) # Set sqwave demodulation testmode GRD1 + GRD2; set rdem to QUAD; set qdem to QUAD\nrac('GYR_TEST_FILT', 0x06c0, 0x0fc0) # Check register setting \nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n# Disable VCO TM and enable ATM to CVs \nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('GYR_TEST_EN',0x8200) # Disable VCO TM; enable IN_TEST; enable path from CVs to IN_TEST\n# Apply 35kHz clock from external and set WLT TM\nbw('OCSB', 0)\ncmt('TOI: change the voltage on ASCX to 1.2V')\nclk('ASCX', 1/(97*296e-9)) # Apply 35 kHz clock on ASCX\nwac('EXT_MODE', 0xc006) # Switch to FCU register page\nwr('FCU_TEST_CMD', 0x8500) # Trigger GYR DP reset; trigger GYR AFE reset; trigger temp DP reset \nwac('EXT_MODE', 0xc00d) # Switch to the ANA register page\nwac('GYR_TEST_WFR', 0x0001) # Enable WLT mode of sense FE\n\n# Read RATE\ndly(10e-3)\nwac('EXT_MODE', 0xc000) # Switch to the USR register page \nbras(f'NU_RAW', 'GYR_DATA_X_LSB', 6) # Burst read over 6 data registers\nfor n in range(1, 4, 1):\n calc('NU_DATA_CH{}_HIGH'.format(n), 'NU_RAW[{}]'.format(2*(n-1)+1), '*', '65536')\n calc('NU_DATA_CH{}'.format(n), 'NU_DATA_CH{}_HIGH'.format(n), '+', 'NU_RAW[{}]'.format(2*(n-1)))\n calc('NS_RATE_WLT1_CH{}'.format(n), 'NU_DATA_CH{}'.format(n), 'cus', 32)\n log('NS_RATE_WLT1_CH{}'.format(n))\n\n# Change sign of WLT signal\nwac('EXT_MODE', 0xc00d) # Switch to the ANA register page\nwac('GYR_TEST_WFR', 0x0003) # Change sign of WT signal; keep WLT mode\nwac('EXT_MODE', 0xc006) # Switch to FCU register page\nwr('FCU_TEST_CMD', 0x8500) # Trigger GYR DP reset; trigger GYR AFE reset; trigger temp DP reset \n\n# Read RATE\ndly(10e-3)\nwac('EXT_MODE', 0xc000) # Switch to the USR register page \nbras(f'NU_RAW', 'GYR_DATA_X_LSB', 6) # Burst read over 6 data registers\nfor n in range(1, 4, 1):\n calc('NU_DATA_CH{}_HIGH'.format(n), 'NU_RAW[{}]'.format(2*(n-1)+1), '*', '65536')\n calc('NU_DATA_CH{}'.format(n), 'NU_DATA_CH{}_HIGH'.format(n), '+', 'NU_RAW[{}]'.format(2*(n-1)))\n calc('NS_RATE_WLT2_CH{}'.format(n), 'NU_DATA_CH{}'.format(n), 'cus', 32)\n log('NS_RATE_WLT2_CH{}'.format(n))\n\n# Clean-up\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('GYR_TEST_EN', 0x0004) # Enable VCO free-running frequency; disable IN_TEST; disable path from CVs to IN_TEST\nubw('OCSB')\nuclk('ASCX')\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('GYR_TEST_WFR', 0x0000) # Disable WLT test-mode\nwac('EXT_MODE', 0xc00e) # Switch to GYR AFE register page\nwac('OCP_MASK', 0x0fc0) # Set masking register\nwr('GYR_TEST_FILT', 0x0000) # Unset sqwave demodulation testmode GRD1 + GRD2; set rdem to DC; set qdem to DC\nrac('GYR_TEST_FILT',0x0000, 0x0fc0) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('OCP_MASK',0x8000) # Set masking register\nwr('ANA_TRM_CAP_PROG_CH1', 0x0000) # Reset the gain of all sense C/V\nrac('ANA_TRM_CAP_PROG_CH1', 0x0000, 0x8000) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('OCP_MASK', 0x3fff) # Set masking register\nwr('ANA_TRM_CAP_PROG_CH1', 0x0010) # Set cap_prog_cv_ch1/2/3 to reset value; set cap_prog_qc_ch1/2/3 to default value\nwr('ANA_TRM_CAP_PROG_CH2', 0x0010) # Set cap_prog_cv_ch1/2/3 to reset value; set cap_prog_qc_ch1/2/3 to default value\nwr('ANA_TRM_CAP_PROG_CH3', 0x0010) # Set cap_prog_cv_ch1/2/3 to reset value; set cap_prog_qc_ch1/2/3 to default value\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('EXT_MODE', 0xc006) # Switch to FCU register page\nwr('FCU_TEST_CMD', 0x8500) # Trigger GYR DP reset; trigger GYR AFE reset; trigger temp DP reset \nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\nwac('TM_GYR', 0x0000) # Unset tm_gyr_d_sel\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T17_01_GYR_AFE_Functional_Test_V3: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n// static int NU_RAW[xNSitES];\n // Auto_Code_Variable_define\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T17_01_GYR_AFE_Functional_Test_V3_PAT_id\");\n rdi.digCap(\"T17_01_GYR_AFE_Functional_Test_V3_Digcap_id\").label(s_label_name)\n .pin(\"SDO\").capMode(TA::SER).samples(16*12).bitPerWord(16)\n .execute();\n RDI_END();\n\n ON_FIRST_INVOCATION_END();\n\n int NU_RAW_WLT1[6], NU_RAW_WLT2[6];\n int NU_DATA_CH1_HIGH,NU_DATA_CH1,NS_RATE_WLT1_CH1, NS_RATE_WLT2_CH1;\n int NU_DATA_CH2_HIGH,NU_DATA_CH2,NS_RATE_WLT1_CH2, NS_RATE_WLT2_CH2;\n int NU_DATA_CH3_HIGH,NU_DATA_CH3,NS_RATE_WLT1_CH3, NS_RATE_WLT2_CH3;\n\n ARRAY_I Vec=rdi.id(\"T17_01_GYR_AFE_Functional_Test_V3_Digcap_id\").getVector();\n for (int i=0; i<6; i++)\n {\n \t NU_RAW_WLT1[i] = reverse_ras_result(Vec[i]);\n \t NU_RAW_WLT2[i] = reverse_ras_result(Vec[6+i]);\n }\n\n\t\tNU_DATA_CH1_HIGH = NU_RAW_WLT1[1] * 65536;\n\t\tNU_DATA_CH1 = NU_DATA_CH1_HIGH + NU_RAW_WLT1[0];\n\t\tNS_RATE_WLT1_CH1 = i_Func_Unsigned_To_Signed(NU_DATA_CH1, 32);\n\t\tNU_DATA_CH2_HIGH = NU_RAW_WLT1[3] * 65536;\n\t\tNU_DATA_CH2 = NU_DATA_CH2_HIGH + NU_RAW_WLT1[2];\n\t\tNS_RATE_WLT1_CH2 = i_Func_Unsigned_To_Signed(NU_DATA_CH2 , 32);\n\t\tNU_DATA_CH3_HIGH = NU_RAW_WLT1[5] * 65536;\n\t\tNU_DATA_CH3 = NU_DATA_CH3_HIGH + NU_RAW_WLT1[4];\n\t\tNS_RATE_WLT1_CH3 = i_Func_Unsigned_To_Signed(NU_DATA_CH3 , 32);\n\n\t\tNU_DATA_CH1_HIGH = NU_RAW_WLT2[1] * 65536;\n\t\tNU_DATA_CH1 = NU_DATA_CH1_HIGH + NU_RAW_WLT2[0];\n\t\tNS_RATE_WLT2_CH1 = i_Func_Unsigned_To_Signed(NU_DATA_CH1 , 32);\n\t\tNU_DATA_CH2_HIGH = NU_RAW_WLT2[3] * 65536;\n\t\tNU_DATA_CH2 = NU_DATA_CH2_HIGH + NU_RAW_WLT2[2];\n\t\tNS_RATE_WLT2_CH2 = i_Func_Unsigned_To_Signed(NU_DATA_CH2 , 32);\n\t\tNU_DATA_CH3_HIGH = NU_RAW_WLT2[5] * 65536;\n\t\tNU_DATA_CH3 = NU_DATA_CH3_HIGH + NU_RAW_WLT2[4];\n\t\tNS_RATE_WLT2_CH3 = i_Func_Unsigned_To_Signed(NU_DATA_CH3 , 32);\n//\n int Func_result = rdi.id(\"T17_01_GYR_AFE_Functional_Test_V3_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n FuncPrint(\"NU_RAW_WLT1[0]\", NU_RAW_WLT1[0]);\n FuncPrint(\"NU_RAW_WLT1[1]\", NU_RAW_WLT1[1]);\n FuncPrint(\"NU_RAW_WLT1[2]\", NU_RAW_WLT1[2]);\n FuncPrint(\"NU_RAW_WLT1[3]\", NU_RAW_WLT1[3]);\n FuncPrint(\"NU_RAW_WLT1[4]\", NU_RAW_WLT1[4]);\n FuncPrint(\"NU_RAW_WLT1[5]\", NU_RAW_WLT1[5]);\n FuncPrint(\"NU_DATA_CH1\", NU_DATA_CH1);\n FuncPrint(\"NU_DATA_CH2\", NU_DATA_CH2);\n FuncPrint(\"NU_DATA_CH3\", NU_DATA_CH3);\n FuncPrint(\"NS_RATE_WLT1_CH1\", NS_RATE_WLT1_CH1);\n FuncPrint(\"NS_RATE_WLT1_CH2\", NS_RATE_WLT1_CH2);\n FuncPrint(\"NS_RATE_WLT1_CH3\", NS_RATE_WLT1_CH3);\n// cout << \"===============================\" << endl;\n FuncPrint(\"NU_RAW_WLT2[0]\", NU_RAW_WLT2[0]);\n FuncPrint(\"NU_RAW_WLT2[1]\", NU_RAW_WLT2[1]);\n FuncPrint(\"NU_RAW_WLT2[2]\", NU_RAW_WLT2[2]);\n FuncPrint(\"NU_RAW_WLT2[3]\", NU_RAW_WLT2[3]);\n FuncPrint(\"NU_RAW_WLT2[4]\", NU_RAW_WLT2[4]);\n FuncPrint(\"NU_RAW_WLT2[5]\", NU_RAW_WLT2[5]);\n FuncPrint(\"NU_DATA_CH1\", NU_DATA_CH1);\n FuncPrint(\"NU_DATA_CH2\", NU_DATA_CH2);\n FuncPrint(\"NU_DATA_CH3\", NU_DATA_CH3);\n FuncPrint(\"NS_RATE_WLT2_CH1\", NS_RATE_WLT2_CH1);\n FuncPrint(\"NS_RATE_WLT2_CH2\", NS_RATE_WLT2_CH2);\n FuncPrint(\"NS_RATE_WLT2_CH3\", NS_RATE_WLT2_CH3);\n\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"NS_RATE_WLT1_CH1\", NS_RATE_WLT1_CH1);\n TestLog(\"NS_RATE_WLT1_CH2\", NS_RATE_WLT1_CH2);\n TestLog(\"NS_RATE_WLT1_CH3\", NS_RATE_WLT1_CH3);\n TestLog(\"NS_RATE_WLT2_CH1\", NS_RATE_WLT2_CH1);\n TestLog(\"NS_RATE_WLT2_CH2\", NS_RATE_WLT2_CH2);\n TestLog(\"NS_RATE_WLT2_CH3\", NS_RATE_WLT2_CH3);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T17_01_GYR_AFE_Functional_Test_V3\", T17_01_GYR_AFE_Functional_Test_V3);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description:\n# - measures the output of the DRIVE C/V converter on the INT2/ASDX pads\n# The DRIVE CV outputs CVD_OUT_P/_N are buffered to the signals CV_DR_P/_N, switched to the signals CV_DR_P/_N_TM\n# and routed through the GYRO_CORE.GYRO_ANALOG_TESTMUX and (as GYR_TIO_P/_N) through the test_module to the pads ASCX/INT2.\n# As the Drive is switched off, the Drive CV provides the reference voltage VREF_CM_GYR on both outputs\n# CVD_OUT_P/_N. This voltage is half of the voltage VDDG (see PWR_ANA.VDDG_LDO).\n# The expected voltages are 0.75V (see T10_24_vddg_ldo_trimming).\n#############################################################################################################\ncmt('Version info: $Revision: bai430aa_rel/1 $ $Author: hmf1rt $ $Date: 2024/07/18 13:31:35 GMT $')\nwac('EXT_MODE', 0xc00f) # Switch to the TEST register page\nwac('TM_CONF', 0x0101) # tm_se_meas=1 tm_bus_inv=0 tm_buf_pwrup=1 (tbuf_tb1_on)\nwac('TM_PIN', 0x0095) # tm_asdx_sel=4 (BUF2_INP) tm_asdx_en=1 tm_int2_sel=2 (BUF1_OUT) tm_int2_en=1\nwac('TM_ADDR', 0x0404) # tm_cfg=4 (CV_DRV_P/N) tm_addr=4 (GYR_TIO)\ndly(100e-6) \ngav('V_CV_DR_P_RAW', 'INT2', 'ASDX')\ncalc('V_CV_DR_P', 'V_CV_DR_P_RAW', '-', 'V_OFF1_ECOFF')\nlog('V_CV_DR_P')\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_CONF', 0x0111) # tm_se_meas=1 tm_bus_inv=1 tm_buf_pwrup=1 (tbuf_tb1_on)\nwac('TM_ADDR', 0x0404) # tm_cfg=4 (GYR_TIOP/N= POUT_P/_N) tm_addr=4 (GYR_TIO; BUF1/2_INP= GYR_TIOP/N)\ndly(100e-6)\ngav('V_CV_DR_N_RAW', 'INT2', 'ASDX')\ncalc('V_CV_DR_N', 'V_CV_DR_N_RAW', '-', 'V_OFF1_ECOFF')\nlog('V_CV_DR_N')\ncalc('V_CV_DR', 'V_CV_DR_P', '-', 'V_CV_DR_N')\nlog ('V_CV_DR')\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs\n", "output": "/*****************************************************\n * T17_02_CV_Drive_Voltage_Test_R1, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n * JSH5SGH: fix some bugs.\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T17_02_CV_Drive_Voltage_Test_R1: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static double d_V_CV_DR_N_RAW[xNSitES];\n static double d_V_CV_DR_P_RAW[xNSitES];\n static double V_CV_DR_N[xNSitES];\n static double V_CV_DR_P[xNSitES];\n static int i_funcRes0[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(d_V_CV_DR_N_RAW, 9.9, xNSitES);\n Func_Init_Var(d_V_CV_DR_P_RAW, 9.9, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T17_02_CV_Drive_Voltage_Test}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 1] @ avcline 788: {gav('V_CV_DR_P_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 1] @ avcline 788: {calc('V_CV_DR_P', 'V_CV_DR_P_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 1] @ avcline 788: {log('V_CV_DR_P', '', '', 0, 0)}\n valid comment[ 2] @ avcline 1375: {gav('V_CV_DR_N_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 2] @ avcline 1375: {calc('V_CV_DR_N', 'V_CV_DR_N_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 2] @ avcline 1375: {log('V_CV_DR_N', '', '', 0, 0)}\n valid comment[ 3] @ avcline 1376: {calc('V_CV_DR', 'V_CV_DR_P', '-', 'V_CV_DR_N')}\n valid comment[ 3] @ avcline 1376: {log('V_CV_DR', '', '', 0, 0)}\n valid comment[ 4] @ avcline 1953: {Test End: T17_02_CV_Drive_Voltage_Test}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][1]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_CV_DR_P_RAW//{gav('V_CV_DR_P_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][2]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_CV_DR_N_RAW//{gav('V_CV_DR_N_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n ARRAY_D ad_jsubresults_INT2; ad_jsubresults_INT2.resize(2); ad_jsubresults_INT2.init(-9.9);\n ARRAY_D ad_jsubresults_ASDX; ad_jsubresults_ASDX.resize(2); ad_jsubresults_ASDX.init(-9.9);\n ad_jsubresults_INT2 = rdi.id(\"dcid_0\").getMultiValue(\"INT2\");\n ad_jsubresults_ASDX = rdi.id(\"dcid_0\").getMultiValue(\"ASDX\");\n \n d_V_CV_DR_N_RAW[curSite] = ad_jsubresults_INT2[1] - ad_jsubresults_ASDX[1];\n d_V_CV_DR_P_RAW[curSite] = ad_jsubresults_INT2[0] - ad_jsubresults_ASDX[0];\n FuncPrint(\"V_CV_DR_N_RAW\",d_V_CV_DR_N_RAW[curSite]);\n FuncPrint(\"V_CV_DR_P_RAW\",d_V_CV_DR_P_RAW[curSite]);\n\n V_CV_DR_P[curSite] = d_V_CV_DR_P_RAW[curSite] - V_OFF1_ECOFF[curSite];\n V_CV_DR_N[curSite] = d_V_CV_DR_N_RAW[curSite] - V_OFF1_ECOFF[curSite];\n FuncPrint(\"V_CV_DR_P\",V_CV_DR_P[curSite]);\n FuncPrint(\"V_CV_DR_P\",V_CV_DR_P[curSite]);\n\n FOR_EACH_SITE_END();\n\n\n ON_FIRST_INVOCATION_END();\n\n TestLog(\"V_CV_DR_P\",V_CV_DR_P[curSite]);\n TestLog(\"V_CV_DR_P\",V_CV_DR_P[curSite]);\n i_funcRes[curSite] = i_funcRes0[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T17_02_CV_Drive_Voltage_Test_R1\", T17_02_CV_Drive_Voltage_Test_R1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description:\n# - measure IDLE rate data and calculate the standard deviation and mean value\n# - the setup of the GYR_AFE+GYR_DP is done in T01_20_switch_on_GYR_wo_drive\n#############################################################################################################\ncmt('Version info: $Revision: bai430aa_rel/1 $ $Author: hmf1rt $ $Date: 2024/07/18 13:31:35 GMT $')\nwac('EXT_MODE', 0xc000) # Switch to the USR register page\ndly(7e-3) # additional time to activate datapath and filters\nfor i in range(0, 30, 1):\n dly(160e-6) # ODR trim +2% variation\n bras(f'NU_IDLE_{i}', 'GYR_DATA_X_LSB', 6) # Burst read over 6 data registers, takes 74micro-seconds\n dly(74e-9) \n calc(f'NU_IDLE_CH1_HIGH_{i:02}', f'NU_IDLE_{i}[1]', '*', '65536')\n calc(f'NU_IDLE_CH1_{i:02}', f'NU_IDLE_CH1_HIGH_{i:02}', '+', f'NU_IDLE_{i}[0]')\n calc(f'NS_IDLE_CH1_{i:02}', f'NU_IDLE_CH1_{i:02}', 'cus', 32)\n dly(74e-9) \n calc(f'NU_IDLE_CH2_HIGH_{i:02}', f'NU_IDLE_{i}[3]', '*', '65536')\n calc(f'NU_IDLE_CH2_{i:02}', f'NU_IDLE_CH2_HIGH_{i:02}', '+' , f'NU_IDLE_{i}[2]')\n calc(f'NS_IDLE_CH2_{i:02}', f'NU_IDLE_CH2_{i:02}', 'cus', 32)\n dly(74e-9) \n calc(f'NU_IDLE_CH3_HIGH_{i:02}', f'NU_IDLE_{i}[5]', '*', '65536')\n calc(f'NU_IDLE_CH3_{i:02}', f'NU_IDLE_CH3_HIGH_{i:02}', '+', f'NU_IDLE_{i}[4]')\n calc(f'NS_IDLE_CH3_{i:02}', f'NU_IDLE_CH3_{i:02}', 'cus', 32)\ndly(74e-9)\ncmt('This test item is a functional fail if NU_IDLE_CH1_00 == 0xff80000')\ncmt('This test item is a functional fail if NU_IDLE_CH2_00 == 0xff80000')\ncmt('This test item is a functional fail if NU_IDLE_CH3_00 == 0xff80000')\ndly(74e-9)\ncmt('Calculate the mean value DPS_MEAN_IDLE_a = SUM(NS_IDLE_a[i])/30 * 4000/2^23 for a=(CH1,CH2,CH3)')\ncmt('Calculate the standard deviation DPS_SD_IDLE_a = SQRT(SUM((NS_IDLE_a[i] - SUM(NS_IDLE_a[i])/30)^2)/29) * 4000/2^23 for a=(CH1,CH2,CH3)')\nlog('DPS_MEAN_IDLE_CH1')\nlog('DPS_MEAN_IDLE_CH2')\nlog('DPS_MEAN_IDLE_CH3')\nlog('DPS_SD_IDLE_CH1')\nlog('DPS_SD_IDLE_CH2')\nlog('DPS_SD_IDLE_CH3')\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T17_03_GYR_Idle_Sense_Data_V3: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n static long long NU_IDLE[30][6][xNSitES], NU_IDLE_CH1_HIGH[30][xNSitES], NU_IDLE_CH2_HIGH[30][xNSitES], NU_IDLE_CH3_HIGH[30][xNSitES];\n static long long NU_IDLE_CH1_LOW[30][xNSitES], NU_IDLE_CH2_LOW[30][xNSitES], NU_IDLE_CH3_LOW[30][xNSitES];\n static long long NU_IDLE_CH1[30][xNSitES], NU_IDLE_CH2[30][xNSitES], NU_IDLE_CH3[30][xNSitES];\n static INT NS_IDLE_CH1[xNSitES][30], NS_IDLE_CH2[xNSitES][30], NS_IDLE_CH3[xNSitES][30];\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n rdi.enableOre(oreFlag);\n rdi.oreFile(\"./ORE_Files/rdi_ore_T17_03_GYR_Idle_Sense_Data.xml\");\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T17_03_GYR_Idle_Sense_Data_V3_PAT_id\");\n rdi.digCap(\"T17_03_GYR_Idle_Sense_Data_V3_Digcap_id\").label(s_label_name)\n .pin(\"SDO\").capMode(TA::SER).samples(16*180).bitPerWord(16)\n .execute();\n RDI_END();\n\n// std::cout<< \"size of int:\" << sizeof(int) << endl;\n\n ON_FIRST_INVOCATION_END();\n \t ARRAY_I Vec=rdi.id(\"T17_03_GYR_Idle_Sense_Data_V3_Digcap_id\").getVector();\n\n \t for(int i=0; i<30; i++)\n \t {\n \t\t for (int j=0; j<6; j++)\n \t\t {\n \t\t\t NU_IDLE[i][j][CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[i*6+j]);\n \t\t }\n\n \t\t NU_IDLE_CH1_HIGH[i][CURRENT_SITE_NUMBER()-1] = NU_IDLE[i][1][CURRENT_SITE_NUMBER()-1] * 65536;\n \t\t NU_IDLE_CH1_LOW[i][CURRENT_SITE_NUMBER()-1] = NU_IDLE[i][0][CURRENT_SITE_NUMBER()-1];\n \t\t NU_IDLE_CH1[i][CURRENT_SITE_NUMBER()-1] = NU_IDLE_CH1_HIGH[i][CURRENT_SITE_NUMBER()-1] + NU_IDLE[i][0][CURRENT_SITE_NUMBER()-1];\n\n \t\t NU_IDLE_CH2_HIGH[i][CURRENT_SITE_NUMBER()-1] = NU_IDLE[i][3][CURRENT_SITE_NUMBER()-1] * 65536;\n \t\t NU_IDLE_CH2_LOW[i][CURRENT_SITE_NUMBER()-1] = NU_IDLE[i][2][CURRENT_SITE_NUMBER()-1];\n \t\t NU_IDLE_CH2[i][CURRENT_SITE_NUMBER()-1] = NU_IDLE_CH2_HIGH[i][CURRENT_SITE_NUMBER()-1] + NU_IDLE[i][2][CURRENT_SITE_NUMBER()-1];\n\n \t\t NU_IDLE_CH3_HIGH[i][CURRENT_SITE_NUMBER()-1] = NU_IDLE[i][5][CURRENT_SITE_NUMBER()-1] * 65536;\n \t\t NU_IDLE_CH3_LOW[i][CURRENT_SITE_NUMBER()-1] = NU_IDLE[i][4][CURRENT_SITE_NUMBER()-1];\n \t\t NU_IDLE_CH3[i][CURRENT_SITE_NUMBER()-1] = NU_IDLE_CH3_HIGH[i][CURRENT_SITE_NUMBER()-1] + NU_IDLE[i][4][CURRENT_SITE_NUMBER()-1];\n\n \t\t NS_IDLE_CH1[CURRENT_SITE_NUMBER()-1][i] = i_Func_Unsigned_To_Signed(NU_IDLE_CH1[i][CURRENT_SITE_NUMBER()-1], 32);\n \t\t NS_IDLE_CH2[CURRENT_SITE_NUMBER()-1][i] = i_Func_Unsigned_To_Signed(NU_IDLE_CH2[i][CURRENT_SITE_NUMBER()-1], 32);\n \t\t NS_IDLE_CH3[CURRENT_SITE_NUMBER()-1][i] = i_Func_Unsigned_To_Signed(NU_IDLE_CH3[i][CURRENT_SITE_NUMBER()-1], 32);\n \t }\n\n \t for(int i=0; i<30; i++)\n \t {\n \t\t FuncPrint(\"NU_IDLE_CH1_HIGH_\"+rdi.itos(i), NU_IDLE_CH1_HIGH[i][CURRENT_SITE_NUMBER()-1]);\n \t\t FuncPrint(\"NU_IDLE_CH1_LOW_\"+rdi.itos(i), NU_IDLE_CH1_LOW[i][CURRENT_SITE_NUMBER()-1]);\n \t\t FuncPrint(\"NU_IDLE_CH1_\"+rdi.itos(i), NU_IDLE_CH1[i][CURRENT_SITE_NUMBER()-1]);\n \t\t FuncPrint(\"NS_IDLE_CH1_\"+rdi.itos(i), NS_IDLE_CH1[CURRENT_SITE_NUMBER()-1][i]);\n\n \t\t FuncPrint(\"NU_IDLE_CH2_HIGH_\"+rdi.itos(i), NU_IDLE_CH2_HIGH[i][CURRENT_SITE_NUMBER()-1]);\n \t\t FuncPrint(\"NU_IDLE_CH2_LOW_\"+rdi.itos(i), NU_IDLE_CH2_LOW[i][CURRENT_SITE_NUMBER()-1]);\n \t\t FuncPrint(\"NU_IDLE_CH2_\"+rdi.itos(i), NU_IDLE_CH2[i][CURRENT_SITE_NUMBER()-1]);\n \t\t FuncPrint(\"NS_IDLE_CH2_\"+rdi.itos(i), NS_IDLE_CH2[CURRENT_SITE_NUMBER()-1][i]);\n\n \t\t FuncPrint(\"NU_IDLE_CH3_HIGH_\"+rdi.itos(i), NU_IDLE_CH3_HIGH[i][CURRENT_SITE_NUMBER()-1]);\n \t\t FuncPrint(\"NU_IDLE_CH3_LOW_\"+rdi.itos(i), NU_IDLE_CH3_LOW[i][CURRENT_SITE_NUMBER()-1]);\n \t\t FuncPrint(\"NU_IDLE_CH3_\"+rdi.itos(i), NU_IDLE_CH3[i][CURRENT_SITE_NUMBER()-1]);\n \t\t FuncPrint(\"NS_IDLE_CH3_\"+rdi.itos(i), NS_IDLE_CH3[CURRENT_SITE_NUMBER()-1][i]);\n \t }\n\n\n//\n \t int Func_result = rdi.id(\"T17_03_GYR_Idle_Sense_Data_V3_PAT_id\").getBurstPassFail();\n \t FuncPrint(\"Func_result\", Func_result);\n\n \t if (NU_IDLE_CH1[0][CURRENT_SITE_NUMBER()-1] == 0xff80000) Func_result = 11;\n \t if (NU_IDLE_CH2[0][CURRENT_SITE_NUMBER()-1] == 0xff80000) Func_result = 12;\n \t if (NU_IDLE_CH3[0][CURRENT_SITE_NUMBER()-1] == 0xff80000) Func_result = 13;\n \t FuncPrint(\"Func_result\", Func_result);\n\n \t double DPS_MEAN_IDLE_CH1, DPS_MEAN_IDLE_CH2, DPS_MEAN_IDLE_CH3, DPS_SD_IDLE_CH1, DPS_SD_IDLE_CH2, DPS_SD_IDLE_CH3;\n \t DSP_MEAN(NS_IDLE_CH1[CURRENT_SITE_NUMBER()-1], &DPS_MEAN_IDLE_CH1, &DPS_SD_IDLE_CH1, 30);\n \t DSP_MEAN(NS_IDLE_CH2[CURRENT_SITE_NUMBER()-1], &DPS_MEAN_IDLE_CH2, &DPS_SD_IDLE_CH2, 30);\n \t DSP_MEAN(NS_IDLE_CH3[CURRENT_SITE_NUMBER()-1], &DPS_MEAN_IDLE_CH3, &DPS_SD_IDLE_CH3, 30);\n\n \t FuncPrint(\"DPS_MEAN_IDLE_CH1\", DPS_MEAN_IDLE_CH1*4000/pow(2,23.0));\n \t FuncPrint(\"DPS_MEAN_IDLE_CH2\", DPS_MEAN_IDLE_CH2*4000/pow(2,23.0));\n \t FuncPrint(\"DPS_MEAN_IDLE_CH3\", DPS_MEAN_IDLE_CH3*4000/pow(2,23.0));\n \t FuncPrint(\"DPS_SD_IDLE_CH1\", DPS_SD_IDLE_CH1*4000/pow(2,23.0));\n \t FuncPrint(\"DPS_SD_IDLE_CH2\", DPS_SD_IDLE_CH2*4000/pow(2,23.0));\n \t FuncPrint(\"DPS_SD_IDLE_CH3\", DPS_SD_IDLE_CH3*4000/pow(2,23.0));\n\n \t TestLog(\"FUNCTIONAL_TEST\", Func_result);\n \tTestLog(\"DPS_MEAN_IDLE_CH1\", DPS_MEAN_IDLE_CH1*4000/pow(2,23.0));\n \tTestLog(\"DPS_MEAN_IDLE_CH2\", DPS_MEAN_IDLE_CH2*4000/pow(2,23.0));\n \tTestLog(\"DPS_MEAN_IDLE_CH3\", DPS_MEAN_IDLE_CH3*4000/pow(2,23.0));\n \tTestLog(\"DPS_SD_IDLE_CH1\", DPS_SD_IDLE_CH1*4000/pow(2,23.0));\n \tTestLog(\"DPS_SD_IDLE_CH2\", DPS_SD_IDLE_CH2*4000/pow(2,23.0));\n \tTestLog(\"DPS_SD_IDLE_CH3\", DPS_SD_IDLE_CH3*4000/pow(2,23.0));\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T17_03_GYR_Idle_Sense_Data_V3\", T17_03_GYR_Idle_Sense_Data_V3);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description:\n# - measure IDLE quad data and calculate the standard deviation and mean value\n# - the setup of the GYR_AFE+GYR_DP is done in T01_20_switch_on_GYR_wo_drive\n# - additionally the quad SD bitstream is routed to the rate CICs\n# - With gyr_test_quad_sel the channel is selected, and the gyr_afe_ reset is applied to make it effective.\n# - With gyr_test_quad2rate_sel=3 the QUAD bitstream is sent to all rate CICs\n# - The ac2qpqn instance select this multiplexor output only with gyr_test_ac2qpqn_en=1\n# (even if it's not an acqpqn test; with iq_mod_en=0 the data are sent through).\n# - Set quadrature avrg bypass\n# - Only the CH1 data are read; CH2, CH3 results are the same (quad2rate_sel=QSQSQS).\n#############################################################################################################\ncmt('Version info: $Revision: bai430aa_rel/2 $ $Author: hmf1rt $ $Date: 2024/07/30 14:45:39 GMT $')\n# Bypass averaging of quad output data\nwac('EXT_MODE', 0xc00e) # Switch to GYR_AFE register page\nwac('OCP_MASK', 0x0010) # Set masking register\nwr('GYR_TEST_FILT', 0x0010) # Bypass averaging of quadrature output data\nrac('GYR_TEST_FILT', 0x0010, 0x0010) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n# Enable AC2QPQN modulation\nwac('OCP_MASK', 0x0400) # Set masking register\nwr('GYR_TEST_TOSK', 0x0400) # gyr_test_ac2qpqn_en=1 (ac2qpqn_i: use notch_rate (output of q2r_mux) instead of mash_rate\nrac('GYR_TEST_TOSK',0x0400, 0x0400) # Check register setting \nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nfor n in range(1, 4, 1):\n # Select quadrature channel\n wac('EXT_MODE', 0xc00e) # Switch to GYR_AFE register page\n wac('OCP_MASK', 0x000f) # Set masking register\n wr('GYR_TEST_FILT', 3*4+n) # gyr_test_quad_sel=n, gyr_test_quad2rate_sel=3 (QSQSQS)\n rac('GYR_TEST_FILT', 3*4+n, 0x000f)# Check register setting \n wr('OCP_MASK', 0x0000) # Reset masking register\n rac('OCP_MASK', 0xffff) # Check masking register reset\n wac('EXT_MODE', 0xc006) # Switch to FCU register page\n wr('FCU_TEST_CMD', 0x0400) # Trigger UI GYR AFE reset\n wac('EXT_MODE', 0xc000) # Switch to the USR register page\n # Sample data\n dly(7e-3) \n for i in range(0, 30, 1):\n dly(160e-6) # ODR trim +2% variation\n bras(f'NU_QUAD_{i}', 'GYR_DATA_X_LSB', 2) # Burst read over 2 data registers\n dly(74e-9) \n calc(f'NU_QUAD_CH{n}_HIGH_{i:02}', f'NU_QUAD_{i}[1]', '*', '65536')\n calc(f'NU_QUAD_CH{n}_{i:02}', f'NU_QUAD_CH{n}_HIGH_{i:02}', '+', f'NU_QUAD_{i}[0]')\n calc(f'NS_QUAD_CH{n}_{i:02}', f'NU_QUAD_CH{n}_{i:02}', 'cus', 32)\n dly(74e-9) \ncmt('This test item is a functional fail if NU_QUAD_CH1_00 == 0xff80000')\ncmt('This test item is a functional fail if NU_QUAD_CH2_00 == 0xff80000')\ncmt('This test item is a functional fail if NU_QUAD_CH3_00 == 0xff80000')\ndly(74e-9)\ncmt('Calculate the mean value DPS_MEAN_QUAD_a = SUM(NS_QUAD_a[i])/30 * 8000/2^23 for a=(CH1,CH2,CH3)')\ncmt('Calculate the standard deviation DPS_SD_QUAD_a = SQRT(SUM((NS_QUAD_a[i] - SUM(NS_QUAD_a[i])/30)^2)/29) * 8000/2^23 for a=(CH1,CH2,CH3)')\nlog('DPS_MEAN_QUAD_CH1')\nlog('DPS_MEAN_QUAD_CH2')\nlog('DPS_MEAN_QUAD_CH3')\nlog('DPS_SD_QUAD_CH1')\nlog('DPS_SD_QUAD_CH2')\nlog('DPS_SD_QUAD_CH3')\n# Clean-up\nwac('EXT_MODE', 0xc00e) # Switch to GYR_AFE register page\nwac('OCP_MASK', 0x001f) # Set masking register\nwr('GYR_TEST_FILT', 0x0000) # Reset value\nrac('GYR_TEST_FILT',0x0000, 0x001f) # Check register setting \nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('OCP_MASK', 0x0400) # Set masking register\nwr('GYR_TEST_TOSK', 0x0000) # gyr_test_ac2qpqn_en=0 (reset value)\nrac('GYR_TEST_TOSK',0x0000, 0x0400) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T17_04_GYR_Idle_Quad_Data_R1: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n static long long NU_QUAD[30][2][xNSitES];\n static long long NU_QUAD_CH1_HIGH[30][xNSitES], NU_QUAD_CH2_HIGH[30][xNSitES], NU_QUAD_CH3_HIGH[30][xNSitES];\n static long long NU_QUAD_CH1[30][xNSitES], NU_QUAD_CH2[30][xNSitES], NU_QUAD_CH3[30][xNSitES];\n static INT NS_QUAD_CH1[xNSitES][30], NS_QUAD_CH2[xNSitES][30], NS_QUAD_CH3[xNSitES][30];\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n// rdi.enableOre(oreFlag);\n// rdi.oreFile(\"./ORE_Files/rdi_ore_T17_04_GYR_IDLE_QUAD_DATA.xml\");\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T17_04_GYR_Idle_Quad_Data_R1_PAT_id\");\n rdi.digCap(\"T17_04_GYR_Idle_Quad_Data_R1_Digcap_id\").label(s_label_name)\n .pin(\"SDO\").capMode(TA::SER).samples(16*180).bitPerWord(16)\n .execute();\n RDI_END();\n ON_FIRST_INVOCATION_END();\n\n ARRAY_I Vec=rdi.id(\"T17_04_GYR_Idle_Quad_Data_R1_Digcap_id\").getVector();\n \t for(int i=0; i<30; i++)\n \t {\n \t\t for (int j=0; j<2; j++)\n \t\t {\n \t\t\t NU_QUAD[i][j][CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[i*2+j]);\n \t\t }\n \t\t NU_QUAD_CH1_HIGH[i][CURRENT_SITE_NUMBER()-1] = NU_QUAD[i][1][CURRENT_SITE_NUMBER()-1] * 65536;\n \t\t NU_QUAD_CH1[i][CURRENT_SITE_NUMBER()-1] = NU_QUAD_CH1_HIGH[i][CURRENT_SITE_NUMBER()-1] + NU_QUAD[i][0][CURRENT_SITE_NUMBER()-1];\n \t }\n \t for(int i=0; i<30; i++)\n \t {\n \t\t FuncPrint(\"NU_QUAD_CH1_HIGH_\"+rdi.itos(i), NU_QUAD_CH1_HIGH[i][CURRENT_SITE_NUMBER()-1]);\n \t\t FuncPrint(\"NU_QUAD_CH1_LOW_\"+rdi.itos(i), NU_QUAD[i][0][CURRENT_SITE_NUMBER()-1]);\n \t\t FuncPrint(\"NU_QUAD_CH1_\"+rdi.itos(i), NU_QUAD_CH1[i][CURRENT_SITE_NUMBER()-1]);\n\n \t }\n\n \t for(int i=0; i<30; i++)\n \t {\n \t\t for (int j=0; j<2; j++)\n \t\t {\n \t\t\t NU_QUAD[i][j][CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[i*2+j+60]);\n \t\t }\n \t\t NU_QUAD_CH2_HIGH[i][CURRENT_SITE_NUMBER()-1] = NU_QUAD[i][1][CURRENT_SITE_NUMBER()-1] * 65536;\n \t\t NU_QUAD_CH2[i][CURRENT_SITE_NUMBER()-1] = NU_QUAD_CH2_HIGH[i][CURRENT_SITE_NUMBER()-1] + NU_QUAD[i][0][CURRENT_SITE_NUMBER()-1];\n \t }\n \t for(int i=0; i<30; i++)\n \t {\n \t\t FuncPrint(\"NU_QUAD_CH2_HIGH_\"+rdi.itos(i), NU_QUAD_CH2_HIGH[i][CURRENT_SITE_NUMBER()-1]);\n \t\t FuncPrint(\"NU_QUAD_CH2_LOW_\"+rdi.itos(i), NU_QUAD[i][0][CURRENT_SITE_NUMBER()-1]);\n \t\t FuncPrint(\"NU_QUAD_CH2_\"+rdi.itos(i), NU_QUAD_CH2[i][CURRENT_SITE_NUMBER()-1]);\n\n \t }\n\n \t for(int i=0; i<30; i++)\n \t {\n \t\t for (int j=0; j<2; j++)\n \t\t {\n \t\t\t NU_QUAD[i][j][CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[i*2+j+120]);\n \t\t }\n \t\t NU_QUAD_CH3_HIGH[i][CURRENT_SITE_NUMBER()-1] = NU_QUAD[i][1][CURRENT_SITE_NUMBER()-1] * 65536;\n \t\t NU_QUAD_CH3[i][CURRENT_SITE_NUMBER()-1] = NU_QUAD_CH3_HIGH[i][CURRENT_SITE_NUMBER()-1] + NU_QUAD[i][0][CURRENT_SITE_NUMBER()-1];\n \t }\n \t for(int i=0; i<30; i++)\n \t {\n \t\t FuncPrint(\"NU_QUAD_CH3_HIGH_\"+rdi.itos(i), NU_QUAD_CH3_HIGH[i][CURRENT_SITE_NUMBER()-1]);\n \t\t FuncPrint(\"NU_QUAD_CH3_LOW_\"+rdi.itos(i), NU_QUAD[i][0][CURRENT_SITE_NUMBER()-1]);\n \t\t FuncPrint(\"NU_QUAD_CH3_\"+rdi.itos(i), NU_QUAD_CH3[i][CURRENT_SITE_NUMBER()-1]);\n\n \t }\n\n \t for(int i=0; i<30; i++)\n \t {\n \t\t NS_QUAD_CH1[CURRENT_SITE_NUMBER()-1][i] = i_Func_Unsigned_To_Signed(NU_QUAD_CH1[i][CURRENT_SITE_NUMBER()-1], 32);\n \t\t NS_QUAD_CH2[CURRENT_SITE_NUMBER()-1][i] = i_Func_Unsigned_To_Signed(NU_QUAD_CH2[i][CURRENT_SITE_NUMBER()-1], 32);\n \t\t NS_QUAD_CH3[CURRENT_SITE_NUMBER()-1][i] = i_Func_Unsigned_To_Signed(NU_QUAD_CH3[i][CURRENT_SITE_NUMBER()-1], 32);\n \t }\n\n \t for(int i=0; i<30; i++)\n \t {\n \t\tFuncPrint(\"NS_QUAD_CH1_\"+rdi.itos(i), NS_QUAD_CH1[CURRENT_SITE_NUMBER()-1][i]);\n \t\tFuncPrint(\"NS_QUAD_CH2_\"+rdi.itos(i), NS_QUAD_CH2[CURRENT_SITE_NUMBER()-1][i]);\n \t\tFuncPrint(\"NS_QUAD_CH3_\"+rdi.itos(i), NS_QUAD_CH3[CURRENT_SITE_NUMBER()-1][i]);\n \t }\n int Func_result = rdi.id(\"T17_04_GYR_Idle_Quad_Data_R1_PAT_id\").getBurstPassFail();\n// FuncPrint(\"Func_result\", Func_result);\n// TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n// TestLog(\"DPS_MEAN_IDLE_CH1\", DPS_MEAN_IDLE_CH1[CURRENT_SITE_NUMBER()-1]);\n \t if (NU_QUAD_CH1[0][CURRENT_SITE_NUMBER()-1] == 0xff80000) Func_result = 11;\n \t if (NU_QUAD_CH2[0][CURRENT_SITE_NUMBER()-1] == 0xff80000) Func_result = 12;\n \t if (NU_QUAD_CH3[0][CURRENT_SITE_NUMBER()-1] == 0xff80000) Func_result = 13;\n \t FuncPrint(\"Func_result\", Func_result);\n\n \t double DPS_MEAN_QUAD_CH1, DPS_MEAN_QUAD_CH2, DPS_MEAN_QUAD_CH3, DPS_SD_QUAD_CH1, DPS_SD_QUAD_CH2, DPS_SD_QUAD_CH3;\n \t DSP_MEAN(NS_QUAD_CH1[CURRENT_SITE_NUMBER()-1], &DPS_MEAN_QUAD_CH1, &DPS_SD_QUAD_CH1, 30);\n \t DSP_MEAN(NS_QUAD_CH2[CURRENT_SITE_NUMBER()-1], &DPS_MEAN_QUAD_CH2, &DPS_SD_QUAD_CH2, 30);\n \t DSP_MEAN(NS_QUAD_CH3[CURRENT_SITE_NUMBER()-1], &DPS_MEAN_QUAD_CH3, &DPS_SD_QUAD_CH3, 30);\n\n \t FuncPrint(\"DPS_MEAN_QUAD_CH1\", DPS_MEAN_QUAD_CH1*8000/pow(2,23.0));\n \t FuncPrint(\"DPS_MEAN_QUAD_CH2\", DPS_MEAN_QUAD_CH2*8000/pow(2,23.0));\n \t FuncPrint(\"DPS_MEAN_QUAD_CH3\", DPS_MEAN_QUAD_CH3*8000/pow(2,23.0));\n \t FuncPrint(\"DPS_SD_QUAD_CH1\", DPS_SD_QUAD_CH1*8000/pow(2,23.0));\n \t FuncPrint(\"DPS_SD_QUAD_CH2\", DPS_SD_QUAD_CH2*8000/pow(2,23.0));\n \t FuncPrint(\"DPS_SD_QUAD_CH3\", DPS_SD_QUAD_CH3*8000/pow(2,23.0));\n\n \t TestLog(\"FUNCTIONAL_TEST\", Func_result);\n// \t TestLog(\"DPS_MEAN_QUAD_CH1\", DPS_MEAN_QUAD_CH1);\n// \t TestLog(\"DPS_MEAN_QUAD_CH2\", DPS_MEAN_QUAD_CH2);\n// \t TestLog(\"DPS_MEAN_QUAD_CH3\", DPS_MEAN_QUAD_CH3);\n// \t TestLog(\"DPS_SD_QUAD_CH1\", DPS_SD_QUAD_CH1);\n// \t TestLog(\"DPS_SD_QUAD_CH2\", DPS_SD_QUAD_CH2);\n// \t TestLog(\"DPS_SD_QUAD_CH3\", DPS_SD_QUAD_CH3);\n \tTestLog(\"DPS_MEAN_QUAD_CH1\", DPS_MEAN_QUAD_CH1*8000/pow(2,23.0));\n \tTestLog(\"DPS_MEAN_QUAD_CH2\", DPS_MEAN_QUAD_CH2*8000/pow(2,23.0));\n \tTestLog(\"DPS_MEAN_QUAD_CH3\", DPS_MEAN_QUAD_CH3*8000/pow(2,23.0));\n \tTestLog(\"DPS_SD_QUAD_CH1\", DPS_SD_QUAD_CH1*8000/pow(2,23.0));\n \tTestLog(\"DPS_SD_QUAD_CH2\", DPS_SD_QUAD_CH2*8000/pow(2,23.0));\n \tTestLog(\"DPS_SD_QUAD_CH3\", DPS_SD_QUAD_CH3*8000/pow(2,23.0));\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T17_04_GYR_Idle_Quad_Data_R1\", T17_04_GYR_Idle_Quad_Data_R1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description:\n# Enable quadrature averaging bypass\n# The same VCM voltage is applied to the P/N inputs of the Rate and Quad ADCs.\n# The following measurement/result reading is the same as in T17_06_GYR_ADC_External_Input.\n# The results are logged in NS_RATE/QUAD_ZERO_CH1/2/3.\n#############################################################################################################\ncmt('Version info: $Revision: bai430aa_rel/1 $ $Author: hmf1rt $ $Date: 2024/07/18 13:31:35 GMT $')\n# Bypass averaging of quad output data\nwac('EXT_MODE', 0xc00e) # Switch to GYR_AFE register page\nwac('OCP_MASK', 0x0010) # Set masking register\nwr('GYR_TEST_FILT', 0x0010) # Bypass averaging of quadrature output data\nrac('GYR_TEST_FILT', 0x0010, 0x0010) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n# Connect the GYR ADC to VCM\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('OCP_MASK', 0x0c00) # Set masking register\nwr('GYR_TEST_EN', 0x0400) \t # gyr_test_adc_input_sel=1 (VCM)\nrac('GYR_TEST_EN',0x0400, 0x0c00) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n# Set rate and quad integrator demodulation to DC\nwac('EXT_MODE', 0xc00e) # Switch to GYR_AFE register page\nwac('OCP_MASK', 0x0f00) # Set masking register\nwr('GYR_TEST_FILT', 0x0f00) # gyr_test_rdem_sel=3 (DC) CLK_DEM=1 on gyro_sense_adc_input_demux\nrac('GYR_TEST_FILT',0x0f00, 0x0f00) # gyr_test_qdem_sel=3 (DC) CLK_DEM=1 on gyro_sense_quad_int_top2_casc\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n# Read data\nwac('EXT_MODE', 0xc000) # Switch to the USR register page\ndly(2*3*1.7e-3) # for 3xQUAD (continuous mode, +synchronization), register update once for all three channels\n # RATE runs parallel\nfor i in range(0, 30, 1):\n dly(160e-6) # ODR trim +2% variation\n bras(f'NU_RATE_ZERO_{i}', 'GYR_DATA_X_LSB', 6) # Burst read over 6 data registers, takes 74micro-seconds\n dly(74e-9) \n calc(f'NU_RATE_ZERO_CH1_HIGH_{i:02}', f'NU_RATE_ZERO_{i}[1]', '*', '65536')\n calc(f'NU_RATE_ZERO_CH1_{i:02}', f'NU_RATE_ZERO_CH1_HIGH_{i:02}', '+', f'NU_RATE_ZERO_{i}[0]')\n calc(f'NS_RATE_ZERO_CH1_{i:02}', f'NU_RATE_ZERO_CH1_{i:02}', 'cus', 32)\n dly(74e-9) \n calc(f'NU_RATE_ZERO_CH2_HIGH_{i:02}', f'NU_RATE_ZERO_{i}[3]', '*', '65536')\n calc(f'NU_RATE_ZERO_CH2_{i:02}', f'NU_RATE_ZERO_CH2_HIGH_{i:02}', '+' , f'NU_RATE_ZERO_{i}[2]')\n calc(f'NS_RATE_ZERO_CH2_{i:02}', f'NU_RATE_ZERO_CH2_{i:02}', 'cus', 32)\n dly(74e-9) \n calc(f'NU_RATE_ZERO_CH3_HIGH_{i:02}', f'NU_RATE_ZERO_{i}[5]', '*', '65536')\n calc(f'NU_RATE_ZERO_CH3_{i:02}', f'NU_RATE_ZERO_CH3_HIGH_{i:02}', '+', f'NU_RATE_ZERO_{i}[4]')\n calc(f'NS_RATE_ZERO_CH3_{i:02}', f'NU_RATE_ZERO_CH3_{i:02}', 'cus', 32)\ndly(74e-9)\ncmt('This test item is a functional fail if NU_RATE_ZERO_CH1_00 == 0xff80000')\ncmt('This test item is a functional fail if NU_RATE_ZERO_CH2_00 == 0xff80000')\ncmt('This test item is a functional fail if NU_RATE_ZERO_CH3_00 == 0xff80000')\ndly(74e-9)\ncmt('Calculate the mean value DPS_MEAN_RATE_ZERO_a = SUM(NS_RATE_ZERO_a[i])/30 * 4000/2^23 for a=(CH1,CH2,CH3)')\ncmt('Calculate the standard deviation DPS_SD_RATE_ZERO_a = SQRT(SUM((NS_RATE_ZERO_a[i] - SUM(NS_RATE_ZERO_a[i])/30)^2)/29) * 4000/2^23')\nlog('DPS_MEAN_RATE_ZERO_CH1')\nlog('DPS_MEAN_RATE_ZERO_CH2')\nlog('DPS_MEAN_RATE_ZERO_CH3')\nlog('DPS_SD_RATE_ZERO_CH1')\nlog('DPS_SD_RATE_ZERO_CH2')\nlog('DPS_SD_RATE_ZERO_CH3')\nwac('EXT_MODE', 0xc00e) # Switch to GYR_AFE register page\nbras(f'NU_QUAD_ZERO', 'GYR_TEST_QUAD1_LSB', 6) # Burst read over 6 data registers\ndly(74e-9) \ncalc(f'NU_QUAD_ZERO_CH1_HIGH', f'NU_QUAD_ZERO[1]', '*', '65536')\ncalc(f'NU_QUAD_ZERO_CH1', f'NU_QUAD_ZERO_CH1_HIGH', '+', f'NU_QUAD_ZERO[0]')\ncalc(f'NS_QUAD_ZERO_CH1', f'NU_QUAD_ZERO_CH1', 'cus', 32)\ndly(74e-9) \ncalc(f'NU_QUAD_ZERO_CH2_HIGH', f'NU_QUAD_ZERO[3]', '*', '65536')\ncalc(f'NU_QUAD_ZERO_CH2', f'NU_QUAD_ZERO_CH2_HIGH', '+' , f'NU_QUAD_ZERO[2]')\ncalc(f'NS_QUAD_ZERO_CH2', f'NU_QUAD_ZERO_CH2', 'cus', 32)\ndly(74e-9) \ncalc(f'NU_QUAD_ZERO_CH3_HIGH', f'NU_QUAD_ZERO[5]', '*', '65536')\ncalc(f'NU_QUAD_ZERO_CH3', f'NU_QUAD_ZERO_CH3_HIGH', '+', f'NU_QUAD_ZERO[4]')\ncalc(f'NS_QUAD_ZERO_CH3', f'NU_QUAD_ZERO_CH3', 'cus', 32)\nlog('NS_QUAD_ZERO_CH1')\nlog('NS_QUAD_ZERO_CH2')\nlog('NS_QUAD_ZERO_CH3')\n# Clean-up\nwac('OCP_MASK', 0x0f00) # Set masking register\nwr('GYR_TEST_FILT', 0x0000) # gyr_test_rdem_sel=0 (NONE) reset value\nrac('GYR_TEST_FILT',0x0000, 0x0f00) # gyr_test_qdem_sel=0 (NONE) reset value\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('OCP_MASK', 0x0c00) # Set masking register\nwr('GYR_TEST_EN', 0x0000) \t # Reset value\nrac('GYR_TEST_EN',0x0000, 0x0c00) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('EXT_MODE', 0xc00e) # Switch to GYR_AFE register page\nwac('OCP_MASK', 0x0010) # Set masking register\nwr('GYR_TEST_FILT', 0x0000) # Reset value\nrac('GYR_TEST_FILT',0x0000, 0x0010) # Check register setting \nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n", "output": "/*****************************************************\n * T17_05_GYR_ADC_Shorted_Input_R1, description file version Notfound, avc file version Notfound\n * First Editor : jsh5sgh\n * Code generated with autocoding tool V2.9.1, in TOI2 standard way by module write_standard\n * Change History:\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T17_05_GYR_ADC_Shorted_Input_R1: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static long long \ti_NU_RATE_ZERO[xNSitES][30][6];\n static long long \ti_NU_RATE_ZERO_CH1_HIGH[xNSitES][30], \ti_NU_RATE_ZERO_CH2_HIGH[xNSitES][30], \ti_NU_RATE_ZERO_CH3_HIGH[xNSitES][30];\n static long long \ti_NU_RATE_ZERO_CH1[xNSitES][30], \t\ti_NU_RATE_ZERO_CH2[xNSitES][30], \t\ti_NU_RATE_ZERO_CH3[xNSitES][30];\n static int \t\ti_NS_RATE_ZERO_CH1[xNSitES][30], \t\ti_NS_RATE_ZERO_CH2[xNSitES][30], \t\ti_NS_RATE_ZERO_CH3[xNSitES][30];\n\n static long long \ti_NU_QUAD_ZERO[xNSitES][6];\n static long long \ti_NU_QUAD_ZERO_CH1_HIGH[xNSitES], \ti_NU_QUAD_ZERO_CH2_HIGH[xNSitES], \ti_NU_QUAD_ZERO_CH3_HIGH[xNSitES];\n static long long \ti_NU_QUAD_ZERO_CH1[xNSitES], \t\ti_NU_QUAD_ZERO_CH2[xNSitES], \t\ti_NU_QUAD_ZERO_CH3[xNSitES];\n static int \t\ti_NS_QUAD_ZERO_CH1[xNSitES], \t\ti_NS_QUAD_ZERO_CH2[xNSitES], \t\ti_NS_QUAD_ZERO_CH3[xNSitES];\n\n static double \td_DPS_MEAN_RATE_ZERO_CH1[xNSitES], \td_DPS_MEAN_RATE_ZERO_CH2[xNSitES], \td_DPS_MEAN_RATE_ZERO_CH3[xNSitES];\n static double \td_DPS_SD_RATE_ZERO_CH1[xNSitES], \td_DPS_SD_RATE_ZERO_CH2[xNSitES], \td_DPS_SD_RATE_ZERO_CH3[xNSitES];\n static int \t\ti_funcRes0[xNSitES];\n\n static double \td_factor = 4000.0/pow(2, 23.0);\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T17_05_GYR_ADC_Shorted_Input}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 1] @ avcline 2522: {bras('NU_RATE_ZERO_0', 'GYR_DATA_X_LSB', 0x0006)}\n valid comment[ 2] @ avcline 2806: {calc('NU_RATE_ZERO_CH1_HIGH_00', 'NU_RATE_ZERO_0[1]', '*', '65536')}\n valid comment[ 2] @ avcline 2806: {calc('NU_RATE_ZERO_CH1_00', 'NU_RATE_ZERO_CH1_HIGH_00', '+', 'NU_RATE_ZERO_0[0]')}\n valid comment[ 2] @ avcline 2806: {calc('NS_RATE_ZERO_CH1_00', 'NU_RATE_ZERO_CH1_00', 'cus', '32')}\n valid comment[ 3] @ avcline 2807: {calc('NU_RATE_ZERO_CH2_HIGH_00', 'NU_RATE_ZERO_0[3]', '*', '65536')}\n valid comment[ 3] @ avcline 2807: {calc('NU_RATE_ZERO_CH2_00', 'NU_RATE_ZERO_CH2_HIGH_00', '+', 'NU_RATE_ZERO_0[2]')}\n valid comment[ 3] @ avcline 2807: {calc('NS_RATE_ZERO_CH2_00', 'NU_RATE_ZERO_CH2_00', 'cus', '32')}\n valid comment[ 4] @ avcline 2808: {calc('NU_RATE_ZERO_CH3_HIGH_00', 'NU_RATE_ZERO_0[5]', '*', '65536')}\n valid comment[ 4] @ avcline 2808: {calc('NU_RATE_ZERO_CH3_00', 'NU_RATE_ZERO_CH3_HIGH_00', '+', 'NU_RATE_ZERO_0[4]')}\n valid comment[ 4] @ avcline 2808: {calc('NS_RATE_ZERO_CH3_00', 'NU_RATE_ZERO_CH3_00', 'cus', '32')}\n valid comment[ 5] @ avcline 2817: {bras('NU_RATE_ZERO_1', 'GYR_DATA_X_LSB', 0x0006)}\n valid comment[ 6] @ avcline 3101: {calc('NU_RATE_ZERO_CH1_HIGH_01', 'NU_RATE_ZERO_1[1]', '*', '65536')}\n valid comment[ 6] @ avcline 3101: {calc('NU_RATE_ZERO_CH1_01', 'NU_RATE_ZERO_CH1_HIGH_01', '+', 'NU_RATE_ZERO_1[0]')}\n valid comment[ 6] @ avcline 3101: {calc('NS_RATE_ZERO_CH1_01', 'NU_RATE_ZERO_CH1_01', 'cus', '32')}\n valid comment[ 7] @ avcline 3102: {calc('NU_RATE_ZERO_CH2_HIGH_01', 'NU_RATE_ZERO_1[3]', '*', '65536')}\n valid comment[ 7] @ avcline 3102: {calc('NU_RATE_ZERO_CH2_01', 'NU_RATE_ZERO_CH2_HIGH_01', '+', 'NU_RATE_ZERO_1[2]')}\n valid comment[ 7] @ avcline 3102: {calc('NS_RATE_ZERO_CH2_01', 'NU_RATE_ZERO_CH2_01', 'cus', '32')}\n valid comment[ 8] @ avcline 3103: {calc('NU_RATE_ZERO_CH3_HIGH_01', 'NU_RATE_ZERO_1[5]', '*', '65536')}\n valid comment[ 8] @ avcline 3103: {calc('NU_RATE_ZERO_CH3_01', 'NU_RATE_ZERO_CH3_HIGH_01', '+', 'NU_RATE_ZERO_1[4]')}\n valid comment[ 8] @ avcline 3103: {calc('NS_RATE_ZERO_CH3_01', 'NU_RATE_ZERO_CH3_01', 'cus', '32')}\n valid comment[ 9] @ avcline 3112: {bras('NU_RATE_ZERO_2', 'GYR_DATA_X_LSB', 0x0006)}\n valid comment[ 10] @ avcline 3396: {calc('NU_RATE_ZERO_CH1_HIGH_02', 'NU_RATE_ZERO_2[1]', '*', '65536')}\n valid comment[ 10] @ avcline 3396: {calc('NU_RATE_ZERO_CH1_02', 'NU_RATE_ZERO_CH1_HIGH_02', '+', 'NU_RATE_ZERO_2[0]')}\n valid comment[ 10] @ avcline 3396: {calc('NS_RATE_ZERO_CH1_02', 'NU_RATE_ZERO_CH1_02', 'cus', '32')}\n valid comment[ 11] @ avcline 3397: {calc('NU_RATE_ZERO_CH2_HIGH_02', 'NU_RATE_ZERO_2[3]', '*', '65536')}\n valid comment[ 11] @ avcline 3397: {calc('NU_RATE_ZERO_CH2_02', 'NU_RATE_ZERO_CH2_HIGH_02', '+', 'NU_RATE_ZERO_2[2]')}\n valid comment[ 11] @ avcline 3397: {calc('NS_RATE_ZERO_CH2_02', 'NU_RATE_ZERO_CH2_02', 'cus', '32')}\n valid comment[ 12] @ avcline 3398: {calc('NU_RATE_ZERO_CH3_HIGH_02', 'NU_RATE_ZERO_2[5]', '*', '65536')}\n valid comment[ 12] @ avcline 3398: {calc('NU_RATE_ZERO_CH3_02', 'NU_RATE_ZERO_CH3_HIGH_02', '+', 'NU_RATE_ZERO_2[4]')}\n valid comment[ 12] @ avcline 3398: {calc('NS_RATE_ZERO_CH3_02', 'NU_RATE_ZERO_CH3_02', 'cus', '32')}\n valid comment[ 13] @ avcline 3407: {bras('NU_RATE_ZERO_3', 'GYR_DATA_X_LSB', 0x0006)}\n valid comment[ 14] @ avcline 3691: {calc('NU_RATE_ZERO_CH1_HIGH_03', 'NU_RATE_ZERO_3[1]', '*', '65536')}\n valid comment[ 14] @ avcline 3691: {calc('NU_RATE_ZERO_CH1_03', 'NU_RATE_ZERO_CH1_HIGH_03', '+', 'NU_RATE_ZERO_3[0]')}\n valid comment[ 14] @ avcline 3691: {calc('NS_RATE_ZERO_CH1_03', 'NU_RATE_ZERO_CH1_03', 'cus', '32')}\n valid comment[ 15] @ avcline 3692: {calc('NU_RATE_ZERO_CH2_HIGH_03', 'NU_RATE_ZERO_3[3]', '*', '65536')}\n valid comment[ 15] @ avcline 3692: {calc('NU_RATE_ZERO_CH2_03', 'NU_RATE_ZERO_CH2_HIGH_03', '+', 'NU_RATE_ZERO_3[2]')}\n valid comment[ 15] @ avcline 3692: {calc('NS_RATE_ZERO_CH2_03', 'NU_RATE_ZERO_CH2_03', 'cus', '32')}\n valid comment[ 16] @ avcline 3693: {calc('NU_RATE_ZERO_CH3_HIGH_03', 'NU_RATE_ZERO_3[5]', '*', '65536')}\n valid comment[ 16] @ avcline 3693: {calc('NU_RATE_ZERO_CH3_03', 'NU_RATE_ZERO_CH3_HIGH_03', '+', 'NU_RATE_ZERO_3[4]')}\n valid comment[ 16] @ avcline 3693: {calc('NS_RATE_ZERO_CH3_03', 'NU_RATE_ZERO_CH3_03', 'cus', '32')}\n valid comment[ 17] @ avcline 3702: {bras('NU_RATE_ZERO_4', 'GYR_DATA_X_LSB', 0x0006)}\n valid comment[ 18] @ avcline 3986: {calc('NU_RATE_ZERO_CH1_HIGH_04', 'NU_RATE_ZERO_4[1]', '*', '65536')}\n valid comment[ 18] @ avcline 3986: {calc('NU_RATE_ZERO_CH1_04', 'NU_RATE_ZERO_CH1_HIGH_04', '+', 'NU_RATE_ZERO_4[0]')}\n valid comment[ 18] @ avcline 3986: {calc('NS_RATE_ZERO_CH1_04', 'NU_RATE_ZERO_CH1_04', 'cus', '32')}\n valid comment[ 19] @ avcline 3987: {calc('NU_RATE_ZERO_CH2_HIGH_04', 'NU_RATE_ZERO_4[3]', '*', '65536')}\n valid comment[ 19] @ avcline 3987: {calc('NU_RATE_ZERO_CH2_04', 'NU_RATE_ZERO_CH2_HIGH_04', '+', 'NU_RATE_ZERO_4[2]')}\n valid comment[ 19] @ avcline 3987: {calc('NS_RATE_ZERO_CH2_04', 'NU_RATE_ZERO_CH2_04', 'cus', '32')}\n valid comment[ 20] @ avcline 3988: {calc('NU_RATE_ZERO_CH3_HIGH_04', 'NU_RATE_ZERO_4[5]', '*', '65536')}\n valid comment[ 20] @ avcline 3988: {calc('NU_RATE_ZERO_CH3_04', 'NU_RATE_ZERO_CH3_HIGH_04', '+', 'NU_RATE_ZERO_4[4]')}\n valid comment[ 20] @ avcline 3988: {calc('NS_RATE_ZERO_CH3_04', 'NU_RATE_ZERO_CH3_04', 'cus', '32')}\n valid comment[ 21] @ avcline 3997: {bras('NU_RATE_ZERO_5', 'GYR_DATA_X_LSB', 0x0006)}\n valid comment[ 22] @ avcline 4281: {calc('NU_RATE_ZERO_CH1_HIGH_05', 'NU_RATE_ZERO_5[1]', '*', '65536')}\n valid comment[ 22] @ avcline 4281: {calc('NU_RATE_ZERO_CH1_05', 'NU_RATE_ZERO_CH1_HIGH_05', '+', 'NU_RATE_ZERO_5[0]')}\n valid comment[ 22] @ avcline 4281: {calc('NS_RATE_ZERO_CH1_05', 'NU_RATE_ZERO_CH1_05', 'cus', '32')}\n valid comment[ 23] @ avcline 4282: {calc('NU_RATE_ZERO_CH2_HIGH_05', 'NU_RATE_ZERO_5[3]', '*', '65536')}\n valid comment[ 23] @ avcline 4282: {calc('NU_RATE_ZERO_CH2_05', 'NU_RATE_ZERO_CH2_HIGH_05', '+', 'NU_RATE_ZERO_5[2]')}\n valid comment[ 23] @ avcline 4282: {calc('NS_RATE_ZERO_CH2_05', 'NU_RATE_ZERO_CH2_05', 'cus', '32')}\n valid comment[ 24] @ avcline 4283: {calc('NU_RATE_ZERO_CH3_HIGH_05', 'NU_RATE_ZERO_5[5]', '*', '65536')}\n valid comment[ 24] @ avcline 4283: {calc('NU_RATE_ZERO_CH3_05', 'NU_RATE_ZERO_CH3_HIGH_05', '+', 'NU_RATE_ZERO_5[4]')}\n valid comment[ 24] @ avcline 4283: {calc('NS_RATE_ZERO_CH3_05', 'NU_RATE_ZERO_CH3_05', 'cus', '32')}\n valid comment[ 25] @ avcline 4292: {bras('NU_RATE_ZERO_6', 'GYR_DATA_X_LSB', 0x0006)}\n valid comment[ 26] @ avcline 4576: {calc('NU_RATE_ZERO_CH1_HIGH_06', 'NU_RATE_ZERO_6[1]', '*', '65536')}\n valid comment[ 26] @ avcline 4576: {calc('NU_RATE_ZERO_CH1_06', 'NU_RATE_ZERO_CH1_HIGH_06', '+', 'NU_RATE_ZERO_6[0]')}\n valid comment[ 26] @ avcline 4576: {calc('NS_RATE_ZERO_CH1_06', 'NU_RATE_ZERO_CH1_06', 'cus', '32')}\n valid comment[ 27] @ avcline 4577: {calc('NU_RATE_ZERO_CH2_HIGH_06', 'NU_RATE_ZERO_6[3]', '*', '65536')}\n valid comment[ 27] @ avcline 4577: {calc('NU_RATE_ZERO_CH2_06', 'NU_RATE_ZERO_CH2_HIGH_06', '+', 'NU_RATE_ZERO_6[2]')}\n valid comment[ 27] @ avcline 4577: {calc('NS_RATE_ZERO_CH2_06', 'NU_RATE_ZERO_CH2_06', 'cus', '32')}\n valid comment[ 28] @ avcline 4578: {calc('NU_RATE_ZERO_CH3_HIGH_06', 'NU_RATE_ZERO_6[5]', '*', '65536')}\n valid comment[ 28] @ avcline 4578: {calc('NU_RATE_ZERO_CH3_06', 'NU_RATE_ZERO_CH3_HIGH_06', '+', 'NU_RATE_ZERO_6[4]')}\n valid comment[ 28] @ avcline 4578: {calc('NS_RATE_ZERO_CH3_06', 'NU_RATE_ZERO_CH3_06', 'cus', '32')}\n valid comment[ 29] @ avcline 4587: {bras('NU_RATE_ZERO_7', 'GYR_DATA_X_LSB', 0x0006)}\n valid comment[ 30] @ avcline 4871: {calc('NU_RATE_ZERO_CH1_HIGH_07', 'NU_RATE_ZERO_7[1]', '*', '65536')}\n valid comment[ 30] @ avcline 4871: {calc('NU_RATE_ZERO_CH1_07', 'NU_RATE_ZERO_CH1_HIGH_07', '+', 'NU_RATE_ZERO_7[0]')}\n valid comment[ 30] @ avcline 4871: {calc('NS_RATE_ZERO_CH1_07', 'NU_RATE_ZERO_CH1_07', 'cus', '32')}\n valid comment[ 31] @ avcline 4872: {calc('NU_RATE_ZERO_CH2_HIGH_07', 'NU_RATE_ZERO_7[3]', '*', '65536')}\n valid comment[ 31] @ avcline 4872: {calc('NU_RATE_ZERO_CH2_07', 'NU_RATE_ZERO_CH2_HIGH_07', '+', 'NU_RATE_ZERO_7[2]')}\n valid comment[ 31] @ avcline 4872: {calc('NS_RATE_ZERO_CH2_07', 'NU_RATE_ZERO_CH2_07', 'cus', '32')}\n valid comment[ 32] @ avcline 4873: {calc('NU_RATE_ZERO_CH3_HIGH_07', 'NU_RATE_ZERO_7[5]', '*', '65536')}\n valid comment[ 32] @ avcline 4873: {calc('NU_RATE_ZERO_CH3_07', 'NU_RATE_ZERO_CH3_HIGH_07', '+', 'NU_RATE_ZERO_7[4]')}\n valid comment[ 32] @ avcline 4873: {calc('NS_RATE_ZERO_CH3_07', 'NU_RATE_ZERO_CH3_07', 'cus', '32')}\n valid comment[ 33] @ avcline 4882: {bras('NU_RATE_ZERO_8', 'GYR_DATA_X_LSB', 0x0006)}\n valid comment[ 34] @ avcline 5166: {calc('NU_RATE_ZERO_CH1_HIGH_08', 'NU_RATE_ZERO_8[1]', '*', '65536')}\n valid comment[ 34] @ avcline 5166: {calc('NU_RATE_ZERO_CH1_08', 'NU_RATE_ZERO_CH1_HIGH_08', '+', 'NU_RATE_ZERO_8[0]')}\n valid comment[ 34] @ avcline 5166: {calc('NS_RATE_ZERO_CH1_08', 'NU_RATE_ZERO_CH1_08', 'cus', '32')}\n valid comment[ 35] @ avcline 5167: {calc('NU_RATE_ZERO_CH2_HIGH_08', 'NU_RATE_ZERO_8[3]', '*', '65536')}\n valid comment[ 35] @ avcline 5167: {calc('NU_RATE_ZERO_CH2_08', 'NU_RATE_ZERO_CH2_HIGH_08', '+', 'NU_RATE_ZERO_8[2]')}\n valid comment[ 35] @ avcline 5167: {calc('NS_RATE_ZERO_CH2_08', 'NU_RATE_ZERO_CH2_08', 'cus', '32')}\n valid comment[ 36] @ avcline 5168: {calc('NU_RATE_ZERO_CH3_HIGH_08', 'NU_RATE_ZERO_8[5]', '*', '65536')}\n valid comment[ 36] @ avcline 5168: {calc('NU_RATE_ZERO_CH3_08', 'NU_RATE_ZERO_CH3_HIGH_08', '+', 'NU_RATE_ZERO_8[4]')}\n valid comment[ 36] @ avcline 5168: {calc('NS_RATE_ZERO_CH3_08', 'NU_RATE_ZERO_CH3_08', 'cus', '32')}\n valid comment[ 37] @ avcline 5177: {bras('NU_RATE_ZERO_9', 'GYR_DATA_X_LSB', 0x0006)}\n valid comment[ 38] @ avcline 5461: {calc('NU_RATE_ZERO_CH1_HIGH_09', 'NU_RATE_ZERO_9[1]', '*', '65536')}\n valid comment[ 38] @ avcline 5461: {calc('NU_RATE_ZERO_CH1_09', 'NU_RATE_ZERO_CH1_HIGH_09', '+', 'NU_RATE_ZERO_9[0]')}\n valid comment[ 38] @ avcline 5461: {calc('NS_RATE_ZERO_CH1_09', 'NU_RATE_ZERO_CH1_09', 'cus', '32')}\n valid comment[ 39] @ avcline 5462: {calc('NU_RATE_ZERO_CH2_HIGH_09', 'NU_RATE_ZERO_9[3]', '*', '65536')}\n valid comment[ 39] @ avcline 5462: {calc('NU_RATE_ZERO_CH2_09', 'NU_RATE_ZERO_CH2_HIGH_09', '+', 'NU_RATE_ZERO_9[2]')}\n valid comment[ 39] @ avcline 5462: {calc('NS_RATE_ZERO_CH2_09', 'NU_RATE_ZERO_CH2_09', 'cus', '32')}\n valid comment[ 40] @ avcline 5463: {calc('NU_RATE_ZERO_CH3_HIGH_09', 'NU_RATE_ZERO_9[5]', '*', '65536')}\n valid comment[ 40] @ avcline 5463: {calc('NU_RATE_ZERO_CH3_09', 'NU_RATE_ZERO_CH3_HIGH_09', '+', 'NU_RATE_ZERO_9[4]')}\n valid comment[ 40] @ avcline 5463: {calc('NS_RATE_ZERO_CH3_09', 'NU_RATE_ZERO_CH3_09', 'cus', '32')}\n valid comment[ 41] @ avcline 5472: {bras('NU_RATE_ZERO_10', 'GYR_DATA_X_LSB', 0x0006)}\n valid comment[ 42] @ avcline 5756: {calc('NU_RATE_ZERO_CH1_HIGH_10', 'NU_RATE_ZERO_10[1]', '*', '65536')}\n valid comment[ 42] @ avcline 5756: {calc('NU_RATE_ZERO_CH1_10', 'NU_RATE_ZERO_CH1_HIGH_10', '+', 'NU_RATE_ZERO_10[0]')}\n valid comment[ 42] @ avcline 5756: {calc('NS_RATE_ZERO_CH1_10', 'NU_RATE_ZERO_CH1_10', 'cus', '32')}\n valid comment[ 43] @ avcline 5757: {calc('NU_RATE_ZERO_CH2_HIGH_10', 'NU_RATE_ZERO_10[3]', '*', '65536')}\n valid comment[ 43] @ avcline 5757: {calc('NU_RATE_ZERO_CH2_10', 'NU_RATE_ZERO_CH2_HIGH_10', '+', 'NU_RATE_ZERO_10[2]')}\n valid comment[ 43] @ avcline 5757: {calc('NS_RATE_ZERO_CH2_10', 'NU_RATE_ZERO_CH2_10', 'cus', '32')}\n valid comment[ 44] @ avcline 5758: {calc('NU_RATE_ZERO_CH3_HIGH_10', 'NU_RATE_ZERO_10[5]', '*', '65536')}\n valid comment[ 44] @ avcline 5758: {calc('NU_RATE_ZERO_CH3_10', 'NU_RATE_ZERO_CH3_HIGH_10', '+', 'NU_RATE_ZERO_10[4]')}\n valid comment[ 44] @ avcline 5758: {calc('NS_RATE_ZERO_CH3_10', 'NU_RATE_ZERO_CH3_10', 'cus', '32')}\n valid comment[ 45] @ avcline 5767: {bras('NU_RATE_ZERO_11', 'GYR_DATA_X_LSB', 0x0006)}\n valid comment[ 46] @ avcline 6051: {calc('NU_RATE_ZERO_CH1_HIGH_11', 'NU_RATE_ZERO_11[1]', '*', '65536')}\n valid comment[ 46] @ avcline 6051: {calc('NU_RATE_ZERO_CH1_11', 'NU_RATE_ZERO_CH1_HIGH_11', '+', 'NU_RATE_ZERO_11[0]')}\n valid comment[ 46] @ avcline 6051: {calc('NS_RATE_ZERO_CH1_11', 'NU_RATE_ZERO_CH1_11', 'cus', '32')}\n valid comment[ 47] @ avcline 6052: {calc('NU_RATE_ZERO_CH2_HIGH_11', 'NU_RATE_ZERO_11[3]', '*', '65536')}\n valid comment[ 47] @ avcline 6052: {calc('NU_RATE_ZERO_CH2_11', 'NU_RATE_ZERO_CH2_HIGH_11', '+', 'NU_RATE_ZERO_11[2]')}\n valid comment[ 47] @ avcline 6052: {calc('NS_RATE_ZERO_CH2_11', 'NU_RATE_ZERO_CH2_11', 'cus', '32')}\n valid comment[ 48] @ avcline 6053: {calc('NU_RATE_ZERO_CH3_HIGH_11', 'NU_RATE_ZERO_11[5]', '*', '65536')}\n valid comment[ 48] @ avcline 6053: {calc('NU_RATE_ZERO_CH3_11', 'NU_RATE_ZERO_CH3_HIGH_11', '+', 'NU_RATE_ZERO_11[4]')}\n valid comment[ 48] @ avcline 6053: {calc('NS_RATE_ZERO_CH3_11', 'NU_RATE_ZERO_CH3_11', 'cus', '32')}\n valid comment[ 49] @ avcline 6062: {bras('NU_RATE_ZERO_12', 'GYR_DATA_X_LSB', 0x0006)}\n valid comment[ 50] @ avcline 6346: {calc('NU_RATE_ZERO_CH1_HIGH_12', 'NU_RATE_ZERO_12[1]', '*', '65536')}\n valid comment[ 50] @ avcline 6346: {calc('NU_RATE_ZERO_CH1_12', 'NU_RATE_ZERO_CH1_HIGH_12', '+', 'NU_RATE_ZERO_12[0]')}\n valid comment[ 50] @ avcline 6346: {calc('NS_RATE_ZERO_CH1_12', 'NU_RATE_ZERO_CH1_12', 'cus', '32')}\n valid comment[ 51] @ avcline 6347: {calc('NU_RATE_ZERO_CH2_HIGH_12', 'NU_RATE_ZERO_12[3]', '*', '65536')}\n valid comment[ 51] @ avcline 6347: {calc('NU_RATE_ZERO_CH2_12', 'NU_RATE_ZERO_CH2_HIGH_12', '+', 'NU_RATE_ZERO_12[2]')}\n valid comment[ 51] @ avcline 6347: {calc('NS_RATE_ZERO_CH2_12', 'NU_RATE_ZERO_CH2_12', 'cus', '32')}\n valid comment[ 52] @ avcline 6348: {calc('NU_RATE_ZERO_CH3_HIGH_12', 'NU_RATE_ZERO_12[5]', '*', '65536')}\n valid comment[ 52] @ avcline 6348: {calc('NU_RATE_ZERO_CH3_12', 'NU_RATE_ZERO_CH3_HIGH_12', '+', 'NU_RATE_ZERO_12[4]')}\n valid comment[ 52] @ avcline 6348: {calc('NS_RATE_ZERO_CH3_12', 'NU_RATE_ZERO_CH3_12', 'cus', '32')}\n valid comment[ 53] @ avcline 6357: {bras('NU_RATE_ZERO_13', 'GYR_DATA_X_LSB', 0x0006)}\n valid comment[ 54] @ avcline 6641: {calc('NU_RATE_ZERO_CH1_HIGH_13', 'NU_RATE_ZERO_13[1]', '*', '65536')}\n valid comment[ 54] @ avcline 6641: {calc('NU_RATE_ZERO_CH1_13', 'NU_RATE_ZERO_CH1_HIGH_13', '+', 'NU_RATE_ZERO_13[0]')}\n valid comment[ 54] @ avcline 6641: {calc('NS_RATE_ZERO_CH1_13', 'NU_RATE_ZERO_CH1_13', 'cus', '32')}\n valid comment[ 55] @ avcline 6642: {calc('NU_RATE_ZERO_CH2_HIGH_13', 'NU_RATE_ZERO_13[3]', '*', '65536')}\n valid comment[ 55] @ avcline 6642: {calc('NU_RATE_ZERO_CH2_13', 'NU_RATE_ZERO_CH2_HIGH_13', '+', 'NU_RATE_ZERO_13[2]')}\n valid comment[ 55] @ avcline 6642: {calc('NS_RATE_ZERO_CH2_13', 'NU_RATE_ZERO_CH2_13', 'cus', '32')}\n valid comment[ 56] @ avcline 6643: {calc('NU_RATE_ZERO_CH3_HIGH_13', 'NU_RATE_ZERO_13[5]', '*', '65536')}\n valid comment[ 56] @ avcline 6643: {calc('NU_RATE_ZERO_CH3_13', 'NU_RATE_ZERO_CH3_HIGH_13', '+', 'NU_RATE_ZERO_13[4]')}\n valid comment[ 56] @ avcline 6643: {calc('NS_RATE_ZERO_CH3_13', 'NU_RATE_ZERO_CH3_13', 'cus', '32')}\n valid comment[ 57] @ avcline 6652: {bras('NU_RATE_ZERO_14', 'GYR_DATA_X_LSB', 0x0006)}\n valid comment[ 58] @ avcline 6936: {calc('NU_RATE_ZERO_CH1_HIGH_14', 'NU_RATE_ZERO_14[1]', '*', '65536')}\n valid comment[ 58] @ avcline 6936: {calc('NU_RATE_ZERO_CH1_14', 'NU_RATE_ZERO_CH1_HIGH_14', '+', 'NU_RATE_ZERO_14[0]')}\n valid comment[ 58] @ avcline 6936: {calc('NS_RATE_ZERO_CH1_14', 'NU_RATE_ZERO_CH1_14', 'cus', '32')}\n valid comment[ 59] @ avcline 6937: {calc('NU_RATE_ZERO_CH2_HIGH_14', 'NU_RATE_ZERO_14[3]', '*', '65536')}\n valid comment[ 59] @ avcline 6937: {calc('NU_RATE_ZERO_CH2_14', 'NU_RATE_ZERO_CH2_HIGH_14', '+', 'NU_RATE_ZERO_14[2]')}\n valid comment[ 59] @ avcline 6937: {calc('NS_RATE_ZERO_CH2_14', 'NU_RATE_ZERO_CH2_14', 'cus', '32')}\n valid comment[ 60] @ avcline 6938: {calc('NU_RATE_ZERO_CH3_HIGH_14', 'NU_RATE_ZERO_14[5]', '*', '65536')}\n valid comment[ 60] @ avcline 6938: {calc('NU_RATE_ZERO_CH3_14', 'NU_RATE_ZERO_CH3_HIGH_14', '+', 'NU_RATE_ZERO_14[4]')}\n valid comment[ 60] @ avcline 6938: {calc('NS_RATE_ZERO_CH3_14', 'NU_RATE_ZERO_CH3_14', 'cus', '32')}\n valid comment[ 61] @ avcline 6947: {bras('NU_RATE_ZERO_15', 'GYR_DATA_X_LSB', 0x0006)}\n valid comment[ 62] @ avcline 7231: {calc('NU_RATE_ZERO_CH1_HIGH_15', 'NU_RATE_ZERO_15[1]', '*', '65536')}\n valid comment[ 62] @ avcline 7231: {calc('NU_RATE_ZERO_CH1_15', 'NU_RATE_ZERO_CH1_HIGH_15', '+', 'NU_RATE_ZERO_15[0]')}\n valid comment[ 62] @ avcline 7231: {calc('NS_RATE_ZERO_CH1_15', 'NU_RATE_ZERO_CH1_15', 'cus', '32')}\n valid comment[ 63] @ avcline 7232: {calc('NU_RATE_ZERO_CH2_HIGH_15', 'NU_RATE_ZERO_15[3]', '*', '65536')}\n valid comment[ 63] @ avcline 7232: {calc('NU_RATE_ZERO_CH2_15', 'NU_RATE_ZERO_CH2_HIGH_15', '+', 'NU_RATE_ZERO_15[2]')}\n valid comment[ 63] @ avcline 7232: {calc('NS_RATE_ZERO_CH2_15', 'NU_RATE_ZERO_CH2_15', 'cus', '32')}\n valid comment[ 64] @ avcline 7233: {calc('NU_RATE_ZERO_CH3_HIGH_15', 'NU_RATE_ZERO_15[5]', '*', '65536')}\n valid comment[ 64] @ avcline 7233: {calc('NU_RATE_ZERO_CH3_15', 'NU_RATE_ZERO_CH3_HIGH_15', '+', 'NU_RATE_ZERO_15[4]')}\n valid comment[ 64] @ avcline 7233: {calc('NS_RATE_ZERO_CH3_15', 'NU_RATE_ZERO_CH3_15', 'cus', '32')}\n valid comment[ 65] @ avcline 7242: {bras('NU_RATE_ZERO_16', 'GYR_DATA_X_LSB', 0x0006)}\n valid comment[ 66] @ avcline 7526: {calc('NU_RATE_ZERO_CH1_HIGH_16', 'NU_RATE_ZERO_16[1]', '*', '65536')}\n valid comment[ 66] @ avcline 7526: {calc('NU_RATE_ZERO_CH1_16', 'NU_RATE_ZERO_CH1_HIGH_16', '+', 'NU_RATE_ZERO_16[0]')}\n valid comment[ 66] @ avcline 7526: {calc('NS_RATE_ZERO_CH1_16', 'NU_RATE_ZERO_CH1_16', 'cus', '32')}\n valid comment[ 67] @ avcline 7527: {calc('NU_RATE_ZERO_CH2_HIGH_16', 'NU_RATE_ZERO_16[3]', '*', '65536')}\n valid comment[ 67] @ avcline 7527: {calc('NU_RATE_ZERO_CH2_16', 'NU_RATE_ZERO_CH2_HIGH_16', '+', 'NU_RATE_ZERO_16[2]')}\n valid comment[ 67] @ avcline 7527: {calc('NS_RATE_ZERO_CH2_16', 'NU_RATE_ZERO_CH2_16', 'cus', '32')}\n valid comment[ 68] @ avcline 7528: {calc('NU_RATE_ZERO_CH3_HIGH_16', 'NU_RATE_ZERO_16[5]', '*', '65536')}\n valid comment[ 68] @ avcline 7528: {calc('NU_RATE_ZERO_CH3_16', 'NU_RATE_ZERO_CH3_HIGH_16', '+', 'NU_RATE_ZERO_16[4]')}\n valid comment[ 68] @ avcline 7528: {calc('NS_RATE_ZERO_CH3_16', 'NU_RATE_ZERO_CH3_16', 'cus', '32')}\n valid comment[ 69] @ avcline 7537: {bras('NU_RATE_ZERO_17', 'GYR_DATA_X_LSB', 0x0006)}\n valid comment[ 70] @ avcline 7821: {calc('NU_RATE_ZERO_CH1_HIGH_17', 'NU_RATE_ZERO_17[1]', '*', '65536')}\n valid comment[ 70] @ avcline 7821: {calc('NU_RATE_ZERO_CH1_17', 'NU_RATE_ZERO_CH1_HIGH_17', '+', 'NU_RATE_ZERO_17[0]')}\n valid comment[ 70] @ avcline 7821: {calc('NS_RATE_ZERO_CH1_17', 'NU_RATE_ZERO_CH1_17', 'cus', '32')}\n valid comment[ 71] @ avcline 7822: {calc('NU_RATE_ZERO_CH2_HIGH_17', 'NU_RATE_ZERO_17[3]', '*', '65536')}\n valid comment[ 71] @ avcline 7822: {calc('NU_RATE_ZERO_CH2_17', 'NU_RATE_ZERO_CH2_HIGH_17', '+', 'NU_RATE_ZERO_17[2]')}\n valid comment[ 71] @ avcline 7822: {calc('NS_RATE_ZERO_CH2_17', 'NU_RATE_ZERO_CH2_17', 'cus', '32')}\n valid comment[ 72] @ avcline 7823: {calc('NU_RATE_ZERO_CH3_HIGH_17', 'NU_RATE_ZERO_17[5]', '*', '65536')}\n valid comment[ 72] @ avcline 7823: {calc('NU_RATE_ZERO_CH3_17', 'NU_RATE_ZERO_CH3_HIGH_17', '+', 'NU_RATE_ZERO_17[4]')}\n valid comment[ 72] @ avcline 7823: {calc('NS_RATE_ZERO_CH3_17', 'NU_RATE_ZERO_CH3_17', 'cus', '32')}\n valid comment[ 73] @ avcline 7832: {bras('NU_RATE_ZERO_18', 'GYR_DATA_X_LSB', 0x0006)}\n valid comment[ 74] @ avcline 8116: {calc('NU_RATE_ZERO_CH1_HIGH_18', 'NU_RATE_ZERO_18[1]', '*', '65536')}\n valid comment[ 74] @ avcline 8116: {calc('NU_RATE_ZERO_CH1_18', 'NU_RATE_ZERO_CH1_HIGH_18', '+', 'NU_RATE_ZERO_18[0]')}\n valid comment[ 74] @ avcline 8116: {calc('NS_RATE_ZERO_CH1_18', 'NU_RATE_ZERO_CH1_18', 'cus', '32')}\n valid comment[ 75] @ avcline 8117: {calc('NU_RATE_ZERO_CH2_HIGH_18', 'NU_RATE_ZERO_18[3]', '*', '65536')}\n valid comment[ 75] @ avcline 8117: {calc('NU_RATE_ZERO_CH2_18', 'NU_RATE_ZERO_CH2_HIGH_18', '+', 'NU_RATE_ZERO_18[2]')}\n valid comment[ 75] @ avcline 8117: {calc('NS_RATE_ZERO_CH2_18', 'NU_RATE_ZERO_CH2_18', 'cus', '32')}\n valid comment[ 76] @ avcline 8118: {calc('NU_RATE_ZERO_CH3_HIGH_18', 'NU_RATE_ZERO_18[5]', '*', '65536')}\n valid comment[ 76] @ avcline 8118: {calc('NU_RATE_ZERO_CH3_18', 'NU_RATE_ZERO_CH3_HIGH_18', '+', 'NU_RATE_ZERO_18[4]')}\n valid comment[ 76] @ avcline 8118: {calc('NS_RATE_ZERO_CH3_18', 'NU_RATE_ZERO_CH3_18', 'cus', '32')}\n valid comment[ 77] @ avcline 8127: {bras('NU_RATE_ZERO_19', 'GYR_DATA_X_LSB', 0x0006)}\n valid comment[ 78] @ avcline 8411: {calc('NU_RATE_ZERO_CH1_HIGH_19', 'NU_RATE_ZERO_19[1]', '*', '65536')}\n valid comment[ 78] @ avcline 8411: {calc('NU_RATE_ZERO_CH1_19', 'NU_RATE_ZERO_CH1_HIGH_19', '+', 'NU_RATE_ZERO_19[0]')}\n valid comment[ 78] @ avcline 8411: {calc('NS_RATE_ZERO_CH1_19', 'NU_RATE_ZERO_CH1_19', 'cus', '32')}\n valid comment[ 79] @ avcline 8412: {calc('NU_RATE_ZERO_CH2_HIGH_19', 'NU_RATE_ZERO_19[3]', '*', '65536')}\n valid comment[ 79] @ avcline 8412: {calc('NU_RATE_ZERO_CH2_19', 'NU_RATE_ZERO_CH2_HIGH_19', '+', 'NU_RATE_ZERO_19[2]')}\n valid comment[ 79] @ avcline 8412: {calc('NS_RATE_ZERO_CH2_19', 'NU_RATE_ZERO_CH2_19', 'cus', '32')}\n valid comment[ 80] @ avcline 8413: {calc('NU_RATE_ZERO_CH3_HIGH_19', 'NU_RATE_ZERO_19[5]', '*', '65536')}\n valid comment[ 80] @ avcline 8413: {calc('NU_RATE_ZERO_CH3_19', 'NU_RATE_ZERO_CH3_HIGH_19', '+', 'NU_RATE_ZERO_19[4]')}\n valid comment[ 80] @ avcline 8413: {calc('NS_RATE_ZERO_CH3_19', 'NU_RATE_ZERO_CH3_19', 'cus', '32')}\n valid comment[ 81] @ avcline 8422: {bras('NU_RATE_ZERO_20', 'GYR_DATA_X_LSB', 0x0006)}\n valid comment[ 82] @ avcline 8706: {calc('NU_RATE_ZERO_CH1_HIGH_20', 'NU_RATE_ZERO_20[1]', '*', '65536')}\n valid comment[ 82] @ avcline 8706: {calc('NU_RATE_ZERO_CH1_20', 'NU_RATE_ZERO_CH1_HIGH_20', '+', 'NU_RATE_ZERO_20[0]')}\n valid comment[ 82] @ avcline 8706: {calc('NS_RATE_ZERO_CH1_20', 'NU_RATE_ZERO_CH1_20', 'cus', '32')}\n valid comment[ 83] @ avcline 8707: {calc('NU_RATE_ZERO_CH2_HIGH_20', 'NU_RATE_ZERO_20[3]', '*', '65536')}\n valid comment[ 83] @ avcline 8707: {calc('NU_RATE_ZERO_CH2_20', 'NU_RATE_ZERO_CH2_HIGH_20', '+', 'NU_RATE_ZERO_20[2]')}\n valid comment[ 83] @ avcline 8707: {calc('NS_RATE_ZERO_CH2_20', 'NU_RATE_ZERO_CH2_20', 'cus', '32')}\n valid comment[ 84] @ avcline 8708: {calc('NU_RATE_ZERO_CH3_HIGH_20', 'NU_RATE_ZERO_20[5]', '*', '65536')}\n valid comment[ 84] @ avcline 8708: {calc('NU_RATE_ZERO_CH3_20', 'NU_RATE_ZERO_CH3_HIGH_20', '+', 'NU_RATE_ZERO_20[4]')}\n valid comment[ 84] @ avcline 8708: {calc('NS_RATE_ZERO_CH3_20', 'NU_RATE_ZERO_CH3_20', 'cus', '32')}\n valid comment[ 85] @ avcline 8717: {bras('NU_RATE_ZERO_21', 'GYR_DATA_X_LSB', 0x0006)}\n valid comment[ 86] @ avcline 9001: {calc('NU_RATE_ZERO_CH1_HIGH_21', 'NU_RATE_ZERO_21[1]', '*', '65536')}\n valid comment[ 86] @ avcline 9001: {calc('NU_RATE_ZERO_CH1_21', 'NU_RATE_ZERO_CH1_HIGH_21', '+', 'NU_RATE_ZERO_21[0]')}\n valid comment[ 86] @ avcline 9001: {calc('NS_RATE_ZERO_CH1_21', 'NU_RATE_ZERO_CH1_21', 'cus', '32')}\n valid comment[ 87] @ avcline 9002: {calc('NU_RATE_ZERO_CH2_HIGH_21', 'NU_RATE_ZERO_21[3]', '*', '65536')}\n valid comment[ 87] @ avcline 9002: {calc('NU_RATE_ZERO_CH2_21', 'NU_RATE_ZERO_CH2_HIGH_21', '+', 'NU_RATE_ZERO_21[2]')}\n valid comment[ 87] @ avcline 9002: {calc('NS_RATE_ZERO_CH2_21', 'NU_RATE_ZERO_CH2_21', 'cus', '32')}\n valid comment[ 88] @ avcline 9003: {calc('NU_RATE_ZERO_CH3_HIGH_21', 'NU_RATE_ZERO_21[5]', '*', '65536')}\n valid comment[ 88] @ avcline 9003: {calc('NU_RATE_ZERO_CH3_21', 'NU_RATE_ZERO_CH3_HIGH_21', '+', 'NU_RATE_ZERO_21[4]')}\n valid comment[ 88] @ avcline 9003: {calc('NS_RATE_ZERO_CH3_21', 'NU_RATE_ZERO_CH3_21', 'cus', '32')}\n valid comment[ 89] @ avcline 9012: {bras('NU_RATE_ZERO_22', 'GYR_DATA_X_LSB', 0x0006)}\n valid comment[ 90] @ avcline 9296: {calc('NU_RATE_ZERO_CH1_HIGH_22', 'NU_RATE_ZERO_22[1]', '*', '65536')}\n valid comment[ 90] @ avcline 9296: {calc('NU_RATE_ZERO_CH1_22', 'NU_RATE_ZERO_CH1_HIGH_22', '+', 'NU_RATE_ZERO_22[0]')}\n valid comment[ 90] @ avcline 9296: {calc('NS_RATE_ZERO_CH1_22', 'NU_RATE_ZERO_CH1_22', 'cus', '32')}\n valid comment[ 91] @ avcline 9297: {calc('NU_RATE_ZERO_CH2_HIGH_22', 'NU_RATE_ZERO_22[3]', '*', '65536')}\n valid comment[ 91] @ avcline 9297: {calc('NU_RATE_ZERO_CH2_22', 'NU_RATE_ZERO_CH2_HIGH_22', '+', 'NU_RATE_ZERO_22[2]')}\n valid comment[ 91] @ avcline 9297: {calc('NS_RATE_ZERO_CH2_22', 'NU_RATE_ZERO_CH2_22', 'cus', '32')}\n valid comment[ 92] @ avcline 9298: {calc('NU_RATE_ZERO_CH3_HIGH_22', 'NU_RATE_ZERO_22[5]', '*', '65536')}\n valid comment[ 92] @ avcline 9298: {calc('NU_RATE_ZERO_CH3_22', 'NU_RATE_ZERO_CH3_HIGH_22', '+', 'NU_RATE_ZERO_22[4]')}\n valid comment[ 92] @ avcline 9298: {calc('NS_RATE_ZERO_CH3_22', 'NU_RATE_ZERO_CH3_22', 'cus', '32')}\n valid comment[ 93] @ avcline 9307: {bras('NU_RATE_ZERO_23', 'GYR_DATA_X_LSB', 0x0006)}\n valid comment[ 94] @ avcline 9591: {calc('NU_RATE_ZERO_CH1_HIGH_23', 'NU_RATE_ZERO_23[1]', '*', '65536')}\n valid comment[ 94] @ avcline 9591: {calc('NU_RATE_ZERO_CH1_23', 'NU_RATE_ZERO_CH1_HIGH_23', '+', 'NU_RATE_ZERO_23[0]')}\n valid comment[ 94] @ avcline 9591: {calc('NS_RATE_ZERO_CH1_23', 'NU_RATE_ZERO_CH1_23', 'cus', '32')}\n valid comment[ 95] @ avcline 9592: {calc('NU_RATE_ZERO_CH2_HIGH_23', 'NU_RATE_ZERO_23[3]', '*', '65536')}\n valid comment[ 95] @ avcline 9592: {calc('NU_RATE_ZERO_CH2_23', 'NU_RATE_ZERO_CH2_HIGH_23', '+', 'NU_RATE_ZERO_23[2]')}\n valid comment[ 95] @ avcline 9592: {calc('NS_RATE_ZERO_CH2_23', 'NU_RATE_ZERO_CH2_23', 'cus', '32')}\n valid comment[ 96] @ avcline 9593: {calc('NU_RATE_ZERO_CH3_HIGH_23', 'NU_RATE_ZERO_23[5]', '*', '65536')}\n valid comment[ 96] @ avcline 9593: {calc('NU_RATE_ZERO_CH3_23', 'NU_RATE_ZERO_CH3_HIGH_23', '+', 'NU_RATE_ZERO_23[4]')}\n valid comment[ 96] @ avcline 9593: {calc('NS_RATE_ZERO_CH3_23', 'NU_RATE_ZERO_CH3_23', 'cus', '32')}\n valid comment[ 97] @ avcline 9602: {bras('NU_RATE_ZERO_24', 'GYR_DATA_X_LSB', 0x0006)}\n valid comment[ 98] @ avcline 9886: {calc('NU_RATE_ZERO_CH1_HIGH_24', 'NU_RATE_ZERO_24[1]', '*', '65536')}\n valid comment[ 98] @ avcline 9886: {calc('NU_RATE_ZERO_CH1_24', 'NU_RATE_ZERO_CH1_HIGH_24', '+', 'NU_RATE_ZERO_24[0]')}\n valid comment[ 98] @ avcline 9886: {calc('NS_RATE_ZERO_CH1_24', 'NU_RATE_ZERO_CH1_24', 'cus', '32')}\n valid comment[ 99] @ avcline 9887: {calc('NU_RATE_ZERO_CH2_HIGH_24', 'NU_RATE_ZERO_24[3]', '*', '65536')}\n valid comment[ 99] @ avcline 9887: {calc('NU_RATE_ZERO_CH2_24', 'NU_RATE_ZERO_CH2_HIGH_24', '+', 'NU_RATE_ZERO_24[2]')}\n valid comment[ 99] @ avcline 9887: {calc('NS_RATE_ZERO_CH2_24', 'NU_RATE_ZERO_CH2_24', 'cus', '32')}\n valid comment[100] @ avcline 9888: {calc('NU_RATE_ZERO_CH3_HIGH_24', 'NU_RATE_ZERO_24[5]', '*', '65536')}\n valid comment[100] @ avcline 9888: {calc('NU_RATE_ZERO_CH3_24', 'NU_RATE_ZERO_CH3_HIGH_24', '+', 'NU_RATE_ZERO_24[4]')}\n valid comment[100] @ avcline 9888: {calc('NS_RATE_ZERO_CH3_24', 'NU_RATE_ZERO_CH3_24', 'cus', '32')}\n valid comment[101] @ avcline 9897: {bras('NU_RATE_ZERO_25', 'GYR_DATA_X_LSB', 0x0006)}\n valid comment[102] @ avcline 10181: {calc('NU_RATE_ZERO_CH1_HIGH_25', 'NU_RATE_ZERO_25[1]', '*', '65536')}\n valid comment[102] @ avcline 10181: {calc('NU_RATE_ZERO_CH1_25', 'NU_RATE_ZERO_CH1_HIGH_25', '+', 'NU_RATE_ZERO_25[0]')}\n valid comment[102] @ avcline 10181: {calc('NS_RATE_ZERO_CH1_25', 'NU_RATE_ZERO_CH1_25', 'cus', '32')}\n valid comment[103] @ avcline 10182: {calc('NU_RATE_ZERO_CH2_HIGH_25', 'NU_RATE_ZERO_25[3]', '*', '65536')}\n valid comment[103] @ avcline 10182: {calc('NU_RATE_ZERO_CH2_25', 'NU_RATE_ZERO_CH2_HIGH_25', '+', 'NU_RATE_ZERO_25[2]')}\n valid comment[103] @ avcline 10182: {calc('NS_RATE_ZERO_CH2_25', 'NU_RATE_ZERO_CH2_25', 'cus', '32')}\n valid comment[104] @ avcline 10183: {calc('NU_RATE_ZERO_CH3_HIGH_25', 'NU_RATE_ZERO_25[5]', '*', '65536')}\n valid comment[104] @ avcline 10183: {calc('NU_RATE_ZERO_CH3_25', 'NU_RATE_ZERO_CH3_HIGH_25', '+', 'NU_RATE_ZERO_25[4]')}\n valid comment[104] @ avcline 10183: {calc('NS_RATE_ZERO_CH3_25', 'NU_RATE_ZERO_CH3_25', 'cus', '32')}\n valid comment[105] @ avcline 10192: {bras('NU_RATE_ZERO_26', 'GYR_DATA_X_LSB', 0x0006)}\n valid comment[106] @ avcline 10476: {calc('NU_RATE_ZERO_CH1_HIGH_26', 'NU_RATE_ZERO_26[1]', '*', '65536')}\n valid comment[106] @ avcline 10476: {calc('NU_RATE_ZERO_CH1_26', 'NU_RATE_ZERO_CH1_HIGH_26', '+', 'NU_RATE_ZERO_26[0]')}\n valid comment[106] @ avcline 10476: {calc('NS_RATE_ZERO_CH1_26', 'NU_RATE_ZERO_CH1_26', 'cus', '32')}\n valid comment[107] @ avcline 10477: {calc('NU_RATE_ZERO_CH2_HIGH_26', 'NU_RATE_ZERO_26[3]', '*', '65536')}\n valid comment[107] @ avcline 10477: {calc('NU_RATE_ZERO_CH2_26', 'NU_RATE_ZERO_CH2_HIGH_26', '+', 'NU_RATE_ZERO_26[2]')}\n valid comment[107] @ avcline 10477: {calc('NS_RATE_ZERO_CH2_26', 'NU_RATE_ZERO_CH2_26', 'cus', '32')}\n valid comment[108] @ avcline 10478: {calc('NU_RATE_ZERO_CH3_HIGH_26', 'NU_RATE_ZERO_26[5]', '*', '65536')}\n valid comment[108] @ avcline 10478: {calc('NU_RATE_ZERO_CH3_26', 'NU_RATE_ZERO_CH3_HIGH_26', '+', 'NU_RATE_ZERO_26[4]')}\n valid comment[108] @ avcline 10478: {calc('NS_RATE_ZERO_CH3_26', 'NU_RATE_ZERO_CH3_26', 'cus', '32')}\n valid comment[109] @ avcline 10487: {bras('NU_RATE_ZERO_27', 'GYR_DATA_X_LSB', 0x0006)}\n valid comment[110] @ avcline 10771: {calc('NU_RATE_ZERO_CH1_HIGH_27', 'NU_RATE_ZERO_27[1]', '*', '65536')}\n valid comment[110] @ avcline 10771: {calc('NU_RATE_ZERO_CH1_27', 'NU_RATE_ZERO_CH1_HIGH_27', '+', 'NU_RATE_ZERO_27[0]')}\n valid comment[110] @ avcline 10771: {calc('NS_RATE_ZERO_CH1_27', 'NU_RATE_ZERO_CH1_27', 'cus', '32')}\n valid comment[111] @ avcline 10772: {calc('NU_RATE_ZERO_CH2_HIGH_27', 'NU_RATE_ZERO_27[3]', '*', '65536')}\n valid comment[111] @ avcline 10772: {calc('NU_RATE_ZERO_CH2_27', 'NU_RATE_ZERO_CH2_HIGH_27', '+', 'NU_RATE_ZERO_27[2]')}\n valid comment[111] @ avcline 10772: {calc('NS_RATE_ZERO_CH2_27', 'NU_RATE_ZERO_CH2_27', 'cus', '32')}\n valid comment[112] @ avcline 10773: {calc('NU_RATE_ZERO_CH3_HIGH_27', 'NU_RATE_ZERO_27[5]', '*', '65536')}\n valid comment[112] @ avcline 10773: {calc('NU_RATE_ZERO_CH3_27', 'NU_RATE_ZERO_CH3_HIGH_27', '+', 'NU_RATE_ZERO_27[4]')}\n valid comment[112] @ avcline 10773: {calc('NS_RATE_ZERO_CH3_27', 'NU_RATE_ZERO_CH3_27', 'cus', '32')}\n valid comment[113] @ avcline 10782: {bras('NU_RATE_ZERO_28', 'GYR_DATA_X_LSB', 0x0006)}\n valid comment[114] @ avcline 11066: {calc('NU_RATE_ZERO_CH1_HIGH_28', 'NU_RATE_ZERO_28[1]', '*', '65536')}\n valid comment[114] @ avcline 11066: {calc('NU_RATE_ZERO_CH1_28', 'NU_RATE_ZERO_CH1_HIGH_28', '+', 'NU_RATE_ZERO_28[0]')}\n valid comment[114] @ avcline 11066: {calc('NS_RATE_ZERO_CH1_28', 'NU_RATE_ZERO_CH1_28', 'cus', '32')}\n valid comment[115] @ avcline 11067: {calc('NU_RATE_ZERO_CH2_HIGH_28', 'NU_RATE_ZERO_28[3]', '*', '65536')}\n valid comment[115] @ avcline 11067: {calc('NU_RATE_ZERO_CH2_28', 'NU_RATE_ZERO_CH2_HIGH_28', '+', 'NU_RATE_ZERO_28[2]')}\n valid comment[115] @ avcline 11067: {calc('NS_RATE_ZERO_CH2_28', 'NU_RATE_ZERO_CH2_28', 'cus', '32')}\n valid comment[116] @ avcline 11068: {calc('NU_RATE_ZERO_CH3_HIGH_28', 'NU_RATE_ZERO_28[5]', '*', '65536')}\n valid comment[116] @ avcline 11068: {calc('NU_RATE_ZERO_CH3_28', 'NU_RATE_ZERO_CH3_HIGH_28', '+', 'NU_RATE_ZERO_28[4]')}\n valid comment[116] @ avcline 11068: {calc('NS_RATE_ZERO_CH3_28', 'NU_RATE_ZERO_CH3_28', 'cus', '32')}\n valid comment[117] @ avcline 11077: {bras('NU_RATE_ZERO_29', 'GYR_DATA_X_LSB', 0x0006)}\n valid comment[118] @ avcline 11361: {calc('NU_RATE_ZERO_CH1_HIGH_29', 'NU_RATE_ZERO_29[1]', '*', '65536')}\n valid comment[118] @ avcline 11361: {calc('NU_RATE_ZERO_CH1_29', 'NU_RATE_ZERO_CH1_HIGH_29', '+', 'NU_RATE_ZERO_29[0]')}\n valid comment[118] @ avcline 11361: {calc('NS_RATE_ZERO_CH1_29', 'NU_RATE_ZERO_CH1_29', 'cus', '32')}\n valid comment[119] @ avcline 11362: {calc('NU_RATE_ZERO_CH2_HIGH_29', 'NU_RATE_ZERO_29[3]', '*', '65536')}\n valid comment[119] @ avcline 11362: {calc('NU_RATE_ZERO_CH2_29', 'NU_RATE_ZERO_CH2_HIGH_29', '+', 'NU_RATE_ZERO_29[2]')}\n valid comment[119] @ avcline 11362: {calc('NS_RATE_ZERO_CH2_29', 'NU_RATE_ZERO_CH2_29', 'cus', '32')}\n valid comment[120] @ avcline 11363: {calc('NU_RATE_ZERO_CH3_HIGH_29', 'NU_RATE_ZERO_29[5]', '*', '65536')}\n valid comment[120] @ avcline 11363: {calc('NU_RATE_ZERO_CH3_29', 'NU_RATE_ZERO_CH3_HIGH_29', '+', 'NU_RATE_ZERO_29[4]')}\n valid comment[120] @ avcline 11363: {calc('NS_RATE_ZERO_CH3_29', 'NU_RATE_ZERO_CH3_29', 'cus', '32')}\n valid comment[121] @ avcline 11364: {cmt: This test item is a functional fail if NU_RATE_ZERO_CH1_00 == 0xff80000}\n valid comment[121] @ avcline 11364: {cmt: This test item is a functional fail if NU_RATE_ZERO_CH2_00 == 0xff80000}\n valid comment[121] @ avcline 11364: {cmt: This test item is a functional fail if NU_RATE_ZERO_CH3_00 == 0xff80000}\n valid comment[122] @ avcline 11365: {cmt: Calculate the mean value DPS_MEAN_RATE_ZERO_a = SUM(NS_RATE_ZERO_a[i])/30 * 4000/2^23 for a=(CH1,CH2,CH3)}\n valid comment[122] @ avcline 11365: {cmt: Calculate the standard deviation DPS_SD_RATE_ZERO_a = SQRT(SUM((NS_RATE_ZERO_a[i] - SUM(NS_RATE_ZERO_a[i])/30)^2)/29) * 4000/2^23}\n valid comment[122] @ avcline 11365: {log('DPS_MEAN_RATE_ZERO_CH1', '', '', 0, 0)}\n valid comment[123] @ avcline 11366: {log('DPS_MEAN_RATE_ZERO_CH2', '', '', 0, 0)}\n valid comment[124] @ avcline 11367: {log('DPS_MEAN_RATE_ZERO_CH3', '', '', 0, 0)}\n valid comment[125] @ avcline 11368: {log('DPS_SD_RATE_ZERO_CH1', '', '', 0, 0)}\n valid comment[126] @ avcline 11369: {log('DPS_SD_RATE_ZERO_CH2', '', '', 0, 0)}\n valid comment[127] @ avcline 11370: {log('DPS_SD_RATE_ZERO_CH3', '', '', 0, 0)}\n valid comment[128] @ avcline 11563: {bras('NU_QUAD_ZERO', 'GYR_TEST_QUAD1_LSB', 0x0006)}\n valid comment[129] @ avcline 11847: {calc('NU_QUAD_ZERO_CH1_HIGH', 'NU_QUAD_ZERO[1]', '*', '65536')}\n valid comment[129] @ avcline 11847: {calc('NU_QUAD_ZERO_CH1', 'NU_QUAD_ZERO_CH1_HIGH', '+', 'NU_QUAD_ZERO[0]')}\n valid comment[129] @ avcline 11847: {calc('NS_QUAD_ZERO_CH1', 'NU_QUAD_ZERO_CH1', 'cus', '32')}\n valid comment[130] @ avcline 11848: {calc('NU_QUAD_ZERO_CH2_HIGH', 'NU_QUAD_ZERO[3]', '*', '65536')}\n valid comment[130] @ avcline 11848: {calc('NU_QUAD_ZERO_CH2', 'NU_QUAD_ZERO_CH2_HIGH', '+', 'NU_QUAD_ZERO[2]')}\n valid comment[130] @ avcline 11848: {calc('NS_QUAD_ZERO_CH2', 'NU_QUAD_ZERO_CH2', 'cus', '32')}\n valid comment[131] @ avcline 11849: {calc('NU_QUAD_ZERO_CH3_HIGH', 'NU_QUAD_ZERO[5]', '*', '65536')}\n valid comment[131] @ avcline 11849: {calc('NU_QUAD_ZERO_CH3', 'NU_QUAD_ZERO_CH3_HIGH', '+', 'NU_QUAD_ZERO[4]')}\n valid comment[131] @ avcline 11849: {calc('NS_QUAD_ZERO_CH3', 'NU_QUAD_ZERO_CH3', 'cus', '32')}\n valid comment[131] @ avcline 11849: {log('NS_QUAD_ZERO_CH1', '', '', 0, 0)}\n valid comment[132] @ avcline 11850: {log('NS_QUAD_ZERO_CH2', '', '', 0, 0)}\n valid comment[133] @ avcline 11851: {log('NS_QUAD_ZERO_CH3', '', '', 0, 0)}\n valid comment[134] @ avcline 13964: {Test End: T17_05_GYR_ADC_Shorted_Input}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.digCap(\"digcapid_0\").label(s_splited_pat_name[0]).pin(\"SDO\").capMode(TA::SER).bitPerWord(16).samples(186*16).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n ARRAY_I aI_Captured_0 = rdi.id(\"digcapid_0\").getVector(\"SDO\");\n for(int i=0; i<30; i++){\n \t for(int j=0; j<6; j++){\n \t\t i_NU_RATE_ZERO[curSite][i][j] = Switch_High_Low_Bits_16Bits(aI_Captured_0[i*6+j]);\n \t \t\t FuncPrint(\"i_NU_RATE_ZERO_\"+rdi.itos(i)+\"_\"+rdi.itos(j),\ti_NU_RATE_ZERO[curSite][i][j]);\n \t }\n\n \t i_NU_RATE_ZERO_CH1_HIGH[curSite][i]\t= i_NU_RATE_ZERO[curSite][i][1] * 65536;\n \t i_NU_RATE_ZERO_CH1[curSite][i] \t\t= i_NU_RATE_ZERO_CH1_HIGH[curSite][i] + i_NU_RATE_ZERO[curSite][i][0];\n\t\t\t\t i_NS_RATE_ZERO_CH1[curSite][i]\t\t= i_Func_Unsigned_To_Signed_longlong(i_NU_RATE_ZERO_CH1[curSite][i], 32);\n\n\t\t\t\t FuncPrint(\"i_NU_RATE_ZERO_CH1_HIGH_\"+rdi.itos(i),\ti_NU_RATE_ZERO_CH1_HIGH[curSite][i]);\n\t\t\t\t FuncPrint(\"i_NU_RATE_ZERO_CH1_\"+rdi.itos(i),\t\ti_NU_RATE_ZERO_CH1[curSite][i]);\n FuncPrint(\"NS_RATE_ZERO_CH1_\"+rdi.itos(i),\t\ti_NS_RATE_ZERO_CH1[curSite][i]);\n\n \t i_NU_RATE_ZERO_CH2_HIGH[curSite][i]\t= i_NU_RATE_ZERO[curSite][i][3] * 65536;\n \t i_NU_RATE_ZERO_CH2[curSite][i]\t\t= i_NU_RATE_ZERO_CH2_HIGH[curSite][i] + i_NU_RATE_ZERO[curSite][i][2];\n\t\t\t\t i_NS_RATE_ZERO_CH2[curSite][i]\t\t= i_Func_Unsigned_To_Signed_longlong(i_NU_RATE_ZERO_CH2[curSite][i], 32);\n\n\t\t\t\t FuncPrint(\"i_NU_RATE_ZERO_CH2_HIGH_\"+rdi.itos(i),\ti_NU_RATE_ZERO_CH2_HIGH[curSite][i]);\n\t\t\t\t FuncPrint(\"i_NU_RATE_ZERO_CH2_\"+rdi.itos(i),\t\ti_NU_RATE_ZERO_CH2[curSite][i]);\n FuncPrint(\"NS_RATE_ZERO_CH2_\"+rdi.itos(i),\t\ti_NS_RATE_ZERO_CH2[curSite][i]);\n\n \t i_NU_RATE_ZERO_CH3_HIGH[curSite][i]\t= i_NU_RATE_ZERO[curSite][i][5] * 65536;\n \t i_NU_RATE_ZERO_CH3[curSite][i]\t\t= i_NU_RATE_ZERO_CH3_HIGH[curSite][i] + i_NU_RATE_ZERO[curSite][i][4];\n\t\t\t\t i_NS_RATE_ZERO_CH3[curSite][i]\t\t= i_Func_Unsigned_To_Signed_longlong(i_NU_RATE_ZERO_CH3[curSite][i], 32);\n\n\t\t\t\t FuncPrint(\"i_NU_RATE_ZERO_CH3_HIGH_\"+rdi.itos(i),\ti_NU_RATE_ZERO_CH3_HIGH[curSite][i]);\n\t\t\t\t FuncPrint(\"i_NU_RATE_ZERO_CH3_\"+rdi.itos(i),\t\ti_NU_RATE_ZERO_CH3[curSite][i]);\n FuncPrint(\"NS_RATE_ZERO_CH3_\"+rdi.itos(i),\t\ti_NS_RATE_ZERO_CH3[curSite][i]);\n }\n \t DSP_MEAN(i_NS_RATE_ZERO_CH1[curSite], &d_DPS_MEAN_RATE_ZERO_CH1[curSite], &d_DPS_SD_RATE_ZERO_CH1[curSite], 30);\n \t DSP_MEAN(i_NS_RATE_ZERO_CH2[curSite], &d_DPS_MEAN_RATE_ZERO_CH2[curSite], &d_DPS_SD_RATE_ZERO_CH2[curSite], 30);\n \t DSP_MEAN(i_NS_RATE_ZERO_CH3[curSite], &d_DPS_MEAN_RATE_ZERO_CH3[curSite], &d_DPS_SD_RATE_ZERO_CH3[curSite], 30);\n\n FuncPrint(\"DPS_MEAN_RATE_ZERO_CH1\",\td_DPS_MEAN_RATE_ZERO_CH1[curSite] * d_factor);\n FuncPrint(\"DPS_MEAN_RATE_ZERO_CH2\",\td_DPS_MEAN_RATE_ZERO_CH2[curSite] * d_factor);\n FuncPrint(\"DPS_MEAN_RATE_ZERO_CH3\",\td_DPS_MEAN_RATE_ZERO_CH3[curSite] * d_factor);\n\n FuncPrint(\"DPS_SD_RATE_ZERO_CH1\",\t\td_DPS_SD_RATE_ZERO_CH1[curSite] * d_factor);\n FuncPrint(\"DPS_SD_RATE_ZERO_CH2\",\t\td_DPS_SD_RATE_ZERO_CH2[curSite] * d_factor);\n FuncPrint(\"DPS_SD_RATE_ZERO_CH3\",\t\td_DPS_SD_RATE_ZERO_CH3[curSite] * d_factor);\n\n \t for(int i=0; i<6; i++){\n \t\t i_NU_QUAD_ZERO[curSite][i] = Switch_High_Low_Bits_16Bits(aI_Captured_0[180+i]);\n\t \t\t FuncPrint(\"i_NU_QUAD_ZERO_\"+rdi.itos(i),\ti_NU_QUAD_ZERO[curSite][i]);\n \t }\n\n \t i_NU_QUAD_ZERO_CH1_HIGH[curSite]\t= i_NU_QUAD_ZERO[curSite][1] * 65536;\n \t i_NU_QUAD_ZERO_CH1[curSite] \t\t= i_NU_QUAD_ZERO_CH1_HIGH[curSite] + i_NU_QUAD_ZERO[curSite][0];\n\t\t\t i_NS_QUAD_ZERO_CH1[curSite]\t\t= i_Func_Unsigned_To_Signed_longlong(i_NU_QUAD_ZERO_CH1[curSite], 32);\n\n\t\t\t FuncPrint(\"i_NU_QUAD_ZERO_CH1_HIGH\",\ti_NU_QUAD_ZERO_CH1_HIGH[curSite]);\n\t\t\t FuncPrint(\"i_NU_QUAD_ZERO_CH1\",\t\ti_NU_QUAD_ZERO_CH1[curSite]);\n FuncPrint(\"NS_QUAD_ZERO_CH1\",\t\t\ti_NS_QUAD_ZERO_CH1[curSite]);\n\n \t i_NU_QUAD_ZERO_CH2_HIGH[curSite]\t= i_NU_QUAD_ZERO[curSite][3] * 65536;\n \t i_NU_QUAD_ZERO_CH2[curSite]\t\t= i_NU_QUAD_ZERO_CH2_HIGH[curSite] + i_NU_QUAD_ZERO[curSite][2];\n\t\t\t i_NS_QUAD_ZERO_CH2[curSite]\t\t= i_Func_Unsigned_To_Signed_longlong(i_NU_QUAD_ZERO_CH2[curSite], 32);\n\n\t\t\t FuncPrint(\"i_NU_QUAD_ZERO_CH2_HIGH\",\ti_NU_QUAD_ZERO_CH2_HIGH[curSite]);\n\t\t\t FuncPrint(\"i_NU_QUAD_ZERO_CH2\",\t\ti_NU_QUAD_ZERO_CH2[curSite]);\n FuncPrint(\"NS_QUAD_ZERO_CH2\",\t\t\ti_NS_QUAD_ZERO_CH2[curSite]);\n\n \t i_NU_QUAD_ZERO_CH3_HIGH[curSite]\t= i_NU_QUAD_ZERO[curSite][5] * 65536;\n \t i_NU_QUAD_ZERO_CH3[curSite]\t\t= i_NU_QUAD_ZERO_CH3_HIGH[curSite] + i_NU_QUAD_ZERO[curSite][4];\n\t\t\t i_NS_QUAD_ZERO_CH3[curSite]\t\t= i_Func_Unsigned_To_Signed_longlong(i_NU_QUAD_ZERO_CH3[curSite], 32);\n\n\t\t\t FuncPrint(\"i_NU_QUAD_ZERO_CH3_HIGH\",\ti_NU_QUAD_ZERO_CH3_HIGH[curSite]);\n\t\t\t FuncPrint(\"i_NU_QUAD_ZERO_CH3\",\t\ti_NU_QUAD_ZERO_CH3[curSite]);\n FuncPrint(\"NS_QUAD_ZERO_CH3\",\t\t\ti_NS_QUAD_ZERO_CH3[curSite]);\n\n FOR_EACH_SITE_END();\n\n\n ON_FIRST_INVOCATION_END();\n\n TestLog(\"DPS_MEAN_RATE_ZERO_CH1\",\t\td_DPS_MEAN_RATE_ZERO_CH1[curSite] * d_factor);\n TestLog(\"DPS_MEAN_RATE_ZERO_CH2\",\t\td_DPS_MEAN_RATE_ZERO_CH2[curSite] * d_factor);\n TestLog(\"DPS_MEAN_RATE_ZERO_CH3\",\t\td_DPS_MEAN_RATE_ZERO_CH3[curSite] * d_factor);\n TestLog(\"DPS_SD_RATE_ZERO_CH1\",\t\td_DPS_SD_RATE_ZERO_CH1[curSite] * d_factor);\n TestLog(\"DPS_SD_RATE_ZERO_CH2\",\t\td_DPS_SD_RATE_ZERO_CH2[curSite] * d_factor);\n TestLog(\"DPS_SD_RATE_ZERO_CH3\",\t\td_DPS_SD_RATE_ZERO_CH3[curSite] * d_factor);\n TestLog(\"NS_QUAD_ZERO_CH1\",\t\t\ti_NS_QUAD_ZERO_CH1[curSite]);\n TestLog(\"NS_QUAD_ZERO_CH2\",\t\t\ti_NS_QUAD_ZERO_CH2[curSite]);\n TestLog(\"NS_QUAD_ZERO_CH3\",\t\t\ti_NS_QUAD_ZERO_CH3[curSite]);\n\n i_funcRes[curSite] = i_funcRes0[curSite];\n \t if (i_NU_RATE_ZERO_CH1[curSite][0] == 0xff80000) i_funcRes[curSite] = 11;\n \t if (i_NU_RATE_ZERO_CH2[curSite][0] == 0xff80000) i_funcRes[curSite] = 12;\n \t if (i_NU_RATE_ZERO_CH3[curSite][0] == 0xff80000) i_funcRes[curSite] = 13;\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T17_05_GYR_ADC_Shorted_Input_R1\", T17_05_GYR_ADC_Shorted_Input_R1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description:\n# A voltage from INT2/ASDX is switched through the test module to the input multiplexor of the Rate and Quad ADCs.\n# (TESTMODULE.GYR_S_TINP/N => GYRO.GYR_TINP/N => GYRO_CORE.GYRO_SENSE.IN_TEST_P/_N).\n# With gyr_test_adc_input_sel=2 the signal is modulated with CLK_DEM (in the SENSE RATE ADC input multiplexor,\n# test signal instead of the C/V output signal) and distributed to all three Rate ADCs\n# and to the input multiplexor of the combined Quad ADC (selects one of the three channels).\n# CLK_DEM is set to a constant in rate/quad ADCs (demodulation off).\n# The (constant) input voltage generates a current, which is added to the current from the feed back signal signal.\n# After the settle time (latency) of the GYR_AFE/GYR_DP the rate data are read (quad data muted)\n# The results are logged in NS_RATE_EXT2/1_CH1/2/3 and NS_QUAD_EXT2/2_CH1/2/3.\n# NS_RATE_EXT2 for 925mV-675mV; NS_RATE_EXT2 for 675mV-925mV\n#############################################################################################################\ncmt('Version info: $Revision: bai430aa_rel/1 $ $Author: hmf1rt $ $Date: 2024/07/18 13:31:35 GMT $')\n# Bypass averaging of quad output data\nwac('EXT_MODE', 0xc00e) # Switch to GYR_AFE register page\nwac('OCP_MASK', 0x0010) # Set masking register\nwr('GYR_TEST_FILT', 0x0010) # Bypass averaging of quadrature output data\nrac('GYR_TEST_FILT', 0x0010, 0x0010) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n# Configure ATM\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_PIN', 0x0011) # tm_asdx_sel=6 (DEV_TION) tm_asdx_en=1 tm_int2_sel=6 (DEV_TIOP) tm_int2_en=1\nwac('TM_ADDR', 0x0005) # tm_cfg=0 (see specification 'Analog Test Module') tm_addr=5 (GYR_S_TIN) enables TEST_MODULE.GYR_S_MUX\nsav('INT2', 0.925) # keep GYR_AFE in Reset, when new input data are applied (GYR_TEST_EN)\nsav('ASDX', 0.675)\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('OCP_MASK', 0x0c00) # Set masking register\nwr('GYR_TEST_EN', 0x0800) \t # gyr_test_adc_input_sel=2 (modulated)\nrac('GYR_TEST_EN',0x0800, 0x0c00) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n# Set rate and quad integrator demodulation to DC\nwac('EXT_MODE', 0xc00e) # Switch to GYR_AFE register page\nwac('OCP_MASK', 0x0f00) # activate bits 11 .. 8\nwr('GYR_TEST_FILT', 0x0f00) # gyr_test_rdem_sel=3 (DC) CLK_DEM=1 on gyro_sense_adc_input_demux\nrac('GYR_TEST_FILT',0x0f00, 0x0f00) # gyr_test_qdem_sel=3 (DC) CLK_DEM=1 on gyro_sense_quad_int_top2_casc\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n# Read data\nwac('EXT_MODE', 0xc000) # Switch to USR register page\ndly(2*3*1.7e-3) # for 3xQUAD (continuous mode, +synchronization), register update once for all three channels\n # RATE runs parallel\nbras(f'NU_RAW', 'GYR_DATA_X_LSB', 6) # Burst read over 6 data registers\nfor n in range(1, 4, 1):\n calc('NU_RATE_EXT1_CH{}_HIGH'.format(n), 'NU_RAW[{}]'.format(2*(n-1)+1), '*', '65536')\n calc('NU_RATE_EXT1_CH{}'.format(n), 'NU_RATE_EXT1_CH{}_HIGH'.format(n), '+', 'NU_RAW[{}]'.format(2*(n-1)))\n calc('NS_RATE_EXT1_CH{}'.format(n), 'NU_RATE_EXT1_CH{}'.format(n), 'cus', 32)\n log('NS_RATE_EXT1_CH{}'.format(n))\n\nwac('EXT_MODE', 0xc00e) # Switch to GYR_AFE register page\nbras(f'NU_QUAD_EXT1', 'GYR_TEST_QUAD1_LSB', 6) # Burst read over 6 data registers\ndly(74e-9) \ncalc(f'NU_QUAD_EXT1_CH1_HIGH', f'NU_QUAD_EXT1[1]', '*', '65536')\ncalc(f'NU_QUAD_EXT1_CH1', f'NU_QUAD_EXT1_CH1_HIGH', '+', f'NU_QUAD_EXT1[0]')\ncalc(f'NS_QUAD_EXT1_CH1', f'NU_QUAD_EXT1_CH1', 'cus', 32)\ndly(74e-9) \ncalc(f'NU_QUAD_EXT1_CH2_HIGH', f'NU_QUAD_EXT1[3]', '*', '65536')\ncalc(f'NU_QUAD_EXT1_CH2', f'NU_QUAD_EXT1_CH2_HIGH', '+' , f'NU_QUAD_EXT1[2]')\ncalc(f'NS_QUAD_EXT1_CH2', f'NU_QUAD_EXT1_CH2', 'cus', 32)\ndly(74e-9) \ncalc(f'NU_QUAD_EXT1_CH3_HIGH', f'NU_QUAD_EXT1[5]', '*', '65536')\ncalc(f'NU_QUAD_EXT1_CH3', f'NU_QUAD_EXT1_CH3_HIGH', '+', f'NU_QUAD_EXT1[4]')\ncalc(f'NS_QUAD_EXT1_CH3', f'NU_QUAD_EXT1_CH3', 'cus', 32)\nlog('NS_QUAD_EXT1_CH1')\nlog('NS_QUAD_EXT1_CH2')\nlog('NS_QUAD_EXT1_CH3')\n\nsav('INT2', 0.675)\nsav('ASDX', 0.925)\nwac('EXT_MODE', 0xc000) # Switch to USR register page\ndly(2*3*1.7e-3) # for 3xQUAD (continuous mode, +synchronization), register update once for all three channels\n # RATE runs parallel\nbras(f'NU_RAW', 'GYR_DATA_X_LSB', 6) # Burst read over 6 data registers\nfor n in range(1, 4, 1):\n calc('NU_RATE_EXT2_CH{}_HIGH'.format(n), 'NU_RAW[{}]'.format(2*(n-1)+1), '*', '65536')\n calc('NU_RATE_EXT2_CH{}'.format(n), 'NU_RATE_EXT2_CH{}_HIGH'.format(n), '+', 'NU_RAW[{}]'.format(2*(n-1)))\n calc('NS_RATE_EXT2_CH{}'.format(n), 'NU_RATE_EXT2_CH{}'.format(n), 'cus', 32)\n log('NS_RATE_EXT2_CH{}'.format(n))\n\nwac('EXT_MODE', 0xc00e) # Switch to GYR_AFE register page\nbras(f'NU_QUAD_EXT2', 'GYR_TEST_QUAD1_LSB', 6) # Burst read over 6 data registers\ndly(74e-9) \ncalc(f'NU_QUAD_EXT2_CH1_HIGH', f'NU_QUAD_EXT2[1]', '*', '65536')\ncalc(f'NU_QUAD_EXT2_CH1', f'NU_QUAD_EXT2_CH1_HIGH', '+', f'NU_QUAD_EXT2[0]')\ncalc(f'NS_QUAD_EXT2_CH1', f'NU_QUAD_EXT2_CH1', 'cus', 32)\ndly(74e-9) \ncalc(f'NU_QUAD_EXT2_CH2_HIGH', f'NU_QUAD_EXT2[3]', '*', '65536')\ncalc(f'NU_QUAD_EXT2_CH2', f'NU_QUAD_EXT2_CH2_HIGH', '+' , f'NU_QUAD_EXT2[2]')\ncalc(f'NS_QUAD_EXT2_CH2', f'NU_QUAD_EXT2_CH2', 'cus', 32)\ndly(74e-9) \ncalc(f'NU_QUAD_EXT2_CH3_HIGH', f'NU_QUAD_EXT2[5]', '*', '65536')\ncalc(f'NU_QUAD_EXT2_CH3', f'NU_QUAD_EXT2_CH3_HIGH', '+', f'NU_QUAD_EXT2[4]')\ncalc(f'NS_QUAD_EXT2_CH3', f'NU_QUAD_EXT2_CH3', 'cus', 32)\nlog('NS_QUAD_EXT2_CH1')\nlog('NS_QUAD_EXT2_CH2')\nlog('NS_QUAD_EXT2_CH3')\n# Clean-up\nwac('OCP_MASK', 0x0f00) # Set masking register\nwr('GYR_TEST_FILT', 0x0000) # gyr_test_rdem_sel=0 (NONE) reset value\nrac('GYR_TEST_FILT',0x0000, 0x0f00) # gyr_test_qdem_sel=0 (NONE) reset value\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('OCP_MASK', 0x0c00) # Set masking register\nwr('GYR_TEST_EN', 0x0000) # Reset gyr_test_adc_input_sel\nrac('GYR_TEST_EN', 0x0000, 0x0c00) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nuav('INT2')\nuav('ASDX')\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('EXT_MODE', 0xc00e) # Switch to GYR_AFE register page\nwac('OCP_MASK', 0x0010) # Set masking register\nwr('GYR_TEST_FILT', 0x0000) # Disable averaging of quad\nrac('GYR_TEST_FILT',0x0000, 0x0010) # Check register setting \nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n", "output": "/*****************************************************\n * T17_06_GYR_ADC_External_Input_R1, description file version Notfound, avc file version Notfound\n * First Editor : jsh5sgh\n * Code generated with autocoding tool V2.9.1, in TOI2 standard way by module write_standard\n * Change History:\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T17_06_GYR_ADC_External_Input_R1: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static long long NU_RAW[xNSitES][4][6];\n static long long NU_EXT_CH[xNSitES][4][3], NU_EXT_CH_HIGH[xNSitES][4][3], NS_EXT_CH[xNSitES][4][3];\n static string str[] = {\"RATE_EXT1\", \"QUAD_EXT1\", \"RATE_EXT2\", \"QUAD_EXT2\"};\n static string ch[] = {\"CH1\", \"CH2\", \"CH3\"};\n static int i_funcRes0[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T17_06_GYR_ADC_External_Input}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 1] @ avcline 1354: {sav('INT2', 0.925, 2, 0.01, False, False)}\n valid comment[ 1] @ avcline 1354: {sav('ASDX', 0.675, 2, 0.01, False, False)}\n valid comment[ 2] @ avcline 3090: {bras('NU_RAW', 'GYR_DATA_X_LSB', 0x0006)}\n valid comment[ 3] @ avcline 3373: {calc('NU_RATE_EXT1_CH1_HIGH', 'NU_RAW[1]', '*', '65536')}\n valid comment[ 3] @ avcline 3373: {calc('NU_RATE_EXT1_CH1', 'NU_RATE_EXT1_CH1_HIGH', '+', 'NU_RAW[0]')}\n valid comment[ 3] @ avcline 3373: {calc('NS_RATE_EXT1_CH1', 'NU_RATE_EXT1_CH1', 'cus', '32')}\n valid comment[ 3] @ avcline 3373: {log('NS_RATE_EXT1_CH1', '', '', 0, 0)}\n valid comment[ 4] @ avcline 3374: {calc('NU_RATE_EXT1_CH2_HIGH', 'NU_RAW[3]', '*', '65536')}\n valid comment[ 4] @ avcline 3374: {calc('NU_RATE_EXT1_CH2', 'NU_RATE_EXT1_CH2_HIGH', '+', 'NU_RAW[2]')}\n valid comment[ 4] @ avcline 3374: {calc('NS_RATE_EXT1_CH2', 'NU_RATE_EXT1_CH2', 'cus', '32')}\n valid comment[ 4] @ avcline 3374: {log('NS_RATE_EXT1_CH2', '', '', 0, 0)}\n valid comment[ 5] @ avcline 3375: {calc('NU_RATE_EXT1_CH3_HIGH', 'NU_RAW[5]', '*', '65536')}\n valid comment[ 5] @ avcline 3375: {calc('NU_RATE_EXT1_CH3', 'NU_RATE_EXT1_CH3_HIGH', '+', 'NU_RAW[4]')}\n valid comment[ 5] @ avcline 3375: {calc('NS_RATE_EXT1_CH3', 'NU_RATE_EXT1_CH3', 'cus', '32')}\n valid comment[ 5] @ avcline 3375: {log('NS_RATE_EXT1_CH3', '', '', 0, 0)}\n valid comment[ 6] @ avcline 3568: {bras('NU_QUAD_EXT1', 'GYR_TEST_QUAD1_LSB', 0x0006)}\n valid comment[ 7] @ avcline 3852: {calc('NU_QUAD_EXT1_CH1_HIGH', 'NU_QUAD_EXT1[1]', '*', '65536')}\n valid comment[ 7] @ avcline 3852: {calc('NU_QUAD_EXT1_CH1', 'NU_QUAD_EXT1_CH1_HIGH', '+', 'NU_QUAD_EXT1[0]')}\n valid comment[ 7] @ avcline 3852: {calc('NS_QUAD_EXT1_CH1', 'NU_QUAD_EXT1_CH1', 'cus', '32')}\n valid comment[ 8] @ avcline 3853: {calc('NU_QUAD_EXT1_CH2_HIGH', 'NU_QUAD_EXT1[3]', '*', '65536')}\n valid comment[ 8] @ avcline 3853: {calc('NU_QUAD_EXT1_CH2', 'NU_QUAD_EXT1_CH2_HIGH', '+', 'NU_QUAD_EXT1[2]')}\n valid comment[ 8] @ avcline 3853: {calc('NS_QUAD_EXT1_CH2', 'NU_QUAD_EXT1_CH2', 'cus', '32')}\n valid comment[ 9] @ avcline 3854: {calc('NU_QUAD_EXT1_CH3_HIGH', 'NU_QUAD_EXT1[5]', '*', '65536')}\n valid comment[ 9] @ avcline 3854: {calc('NU_QUAD_EXT1_CH3', 'NU_QUAD_EXT1_CH3_HIGH', '+', 'NU_QUAD_EXT1[4]')}\n valid comment[ 9] @ avcline 3854: {calc('NS_QUAD_EXT1_CH3', 'NU_QUAD_EXT1_CH3', 'cus', '32')}\n valid comment[ 9] @ avcline 3854: {log('NS_QUAD_EXT1_CH1', '', '', 0, 0)}\n valid comment[ 10] @ avcline 3855: {log('NS_QUAD_EXT1_CH2', '', '', 0, 0)}\n valid comment[ 11] @ avcline 3856: {log('NS_QUAD_EXT1_CH3', '', '', 0, 0)}\n valid comment[ 12] @ avcline 3857: {sav('INT2', 0.675, 2, 0.01, False, False)}\n valid comment[ 12] @ avcline 3857: {sav('ASDX', 0.925, 2, 0.01, False, False)}\n valid comment[ 13] @ avcline 4057: {bras('NU_RAW', 'GYR_DATA_X_LSB', 0x0006)}\n valid comment[ 14] @ avcline 4340: {calc('NU_RATE_EXT2_CH1_HIGH', 'NU_RAW[1]', '*', '65536')}\n valid comment[ 14] @ avcline 4340: {calc('NU_RATE_EXT2_CH1', 'NU_RATE_EXT2_CH1_HIGH', '+', 'NU_RAW[0]')}\n valid comment[ 14] @ avcline 4340: {calc('NS_RATE_EXT2_CH1', 'NU_RATE_EXT2_CH1', 'cus', '32')}\n valid comment[ 14] @ avcline 4340: {log('NS_RATE_EXT2_CH1', '', '', 0, 0)}\n valid comment[ 15] @ avcline 4341: {calc('NU_RATE_EXT2_CH2_HIGH', 'NU_RAW[3]', '*', '65536')}\n valid comment[ 15] @ avcline 4341: {calc('NU_RATE_EXT2_CH2', 'NU_RATE_EXT2_CH2_HIGH', '+', 'NU_RAW[2]')}\n valid comment[ 15] @ avcline 4341: {calc('NS_RATE_EXT2_CH2', 'NU_RATE_EXT2_CH2', 'cus', '32')}\n valid comment[ 15] @ avcline 4341: {log('NS_RATE_EXT2_CH2', '', '', 0, 0)}\n valid comment[ 16] @ avcline 4342: {calc('NU_RATE_EXT2_CH3_HIGH', 'NU_RAW[5]', '*', '65536')}\n valid comment[ 16] @ avcline 4342: {calc('NU_RATE_EXT2_CH3', 'NU_RATE_EXT2_CH3_HIGH', '+', 'NU_RAW[4]')}\n valid comment[ 16] @ avcline 4342: {calc('NS_RATE_EXT2_CH3', 'NU_RATE_EXT2_CH3', 'cus', '32')}\n valid comment[ 16] @ avcline 4342: {log('NS_RATE_EXT2_CH3', '', '', 0, 0)}\n valid comment[ 17] @ avcline 4535: {bras('NU_QUAD_EXT2', 'GYR_TEST_QUAD1_LSB', 0x0006)}\n valid comment[ 18] @ avcline 4819: {calc('NU_QUAD_EXT2_CH1_HIGH', 'NU_QUAD_EXT2[1]', '*', '65536')}\n valid comment[ 18] @ avcline 4819: {calc('NU_QUAD_EXT2_CH1', 'NU_QUAD_EXT2_CH1_HIGH', '+', 'NU_QUAD_EXT2[0]')}\n valid comment[ 18] @ avcline 4819: {calc('NS_QUAD_EXT2_CH1', 'NU_QUAD_EXT2_CH1', 'cus', '32')}\n valid comment[ 19] @ avcline 4820: {calc('NU_QUAD_EXT2_CH2_HIGH', 'NU_QUAD_EXT2[3]', '*', '65536')}\n valid comment[ 19] @ avcline 4820: {calc('NU_QUAD_EXT2_CH2', 'NU_QUAD_EXT2_CH2_HIGH', '+', 'NU_QUAD_EXT2[2]')}\n valid comment[ 19] @ avcline 4820: {calc('NS_QUAD_EXT2_CH2', 'NU_QUAD_EXT2_CH2', 'cus', '32')}\n valid comment[ 20] @ avcline 4821: {calc('NU_QUAD_EXT2_CH3_HIGH', 'NU_QUAD_EXT2[5]', '*', '65536')}\n valid comment[ 20] @ avcline 4821: {calc('NU_QUAD_EXT2_CH3', 'NU_QUAD_EXT2_CH3_HIGH', '+', 'NU_QUAD_EXT2[4]')}\n valid comment[ 20] @ avcline 4821: {calc('NS_QUAD_EXT2_CH3', 'NU_QUAD_EXT2_CH3', 'cus', '32')}\n valid comment[ 20] @ avcline 4821: {log('NS_QUAD_EXT2_CH1', '', '', 0, 0)}\n valid comment[ 21] @ avcline 4822: {log('NS_QUAD_EXT2_CH2', '', '', 0, 0)}\n valid comment[ 22] @ avcline 4823: {log('NS_QUAD_EXT2_CH3', '', '', 0, 0)}\n valid comment[ 23] @ avcline 6168: {uav('INT2', False)}\n valid comment[ 23] @ avcline 6168: {uav('ASDX', False)}\n valid comment[ 24] @ avcline 7512: {Test End: T17_06_GYR_ADC_External_Input}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.digCap(\"digcapid_0\").vecVarOnly().pin(\"SDO\").capMode(TA::SER).bitPerWord(16).samples(24*16).execute();\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][1]).pin(\"INT2\").vForce(0.925 V)//{sav('INT2', 0.925, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][1]).pin(\"ASDX\").vForce(0.675 V)//{sav('ASDX', 0.675, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][12]).pin(\"INT2\").vForce(0.675 V)//{sav('INT2', 0.675, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][12]).pin(\"ASDX\").vForce(0.925 V)//{sav('ASDX', 0.925, 2, 0.01, False, False)}\n .insertSub(i_comment_line[0][23]).pin(\"INT2\").relay(TA::ppmuRly_offALL)////{uav('INT2', False)}\n .insertSub(i_comment_line[0][23]).pin(\"ASDX\").relay(TA::ppmuRly_offALL)////{uav('ASDX', False)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n ARRAY_I aI_Captured_0 = rdi.id(\"digcapid_0\").getVector(\"SDO\");\n for(int i=0; i<4; i++){\n \t for(int j=0; j<3; j++){\n \t\t NU_RAW[curSite][i][2*j] \t\t= Switch_High_Low_Bits_16Bits(aI_Captured_0[i*6+2*j]);\n \t\t NU_RAW[curSite][i][2*j+1] \t= Switch_High_Low_Bits_16Bits(aI_Captured_0[i*6+2*j+1]);\n \t\t\t FuncPrint(\"NU_\"+str[i]+\"_\"+rdi.itos(2*j),\t\t\tNU_RAW[curSite][i][2*j]);\n \t\t\t FuncPrint(\"NU_\"+str[i]+\"_\"+rdi.itos(2*j+1),\t\t\tNU_RAW[curSite][i][2*j]+1);\n\n \t\t NU_EXT_CH_HIGH[curSite][i][j]\t= NU_RAW[curSite][i][2*j+1] * 65536;\n \t\t NU_EXT_CH[curSite][i][j]\t\t= NU_EXT_CH_HIGH[curSite][i][j] + NU_RAW[curSite][i][2*j];\n \t\t NS_EXT_CH[curSite][i][j]\t\t= i_Func_Unsigned_To_Signed_longlong(NU_EXT_CH[curSite][i][j], 32);\n \t\t\t FuncPrint(\"NU_\"+str[i]+\"_\"+ch[j]+\"_HIGH\",\tNU_EXT_CH_HIGH[curSite][i][j]);\n \t\t\t FuncPrint(\"NU_\"+str[i]+\"_\"+ch[j],\t\t\tNU_EXT_CH[curSite][i][j]);\n FuncPrint(\"NS_\"+str[i]+\"_\"+ch[j],\t\t\tNS_EXT_CH[curSite][i][j]);\n \t }\n }\n\n FOR_EACH_SITE_END();\n\n\n ON_FIRST_INVOCATION_END();\n for(int i=0; i<4; i++){\n \t for(int j=0; j<3; j++){\n \t\t TestLog(\"NS_\"+str[i]+\"_\"+ch[j],\tNS_EXT_CH[curSite][i][j]);\n \t }\n }\n i_funcRes[curSite] = i_funcRes0[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T17_06_GYR_ADC_External_Input_R1\", T17_06_GYR_ADC_External_Input_R1);\n\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: 3 $ $Author: luz3sgh $ $Date: 2024/06/11 07:44:31 GMT $')\n# Measure VCM_GYR and VCM_GYR_BUF\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_CONF', 0x0101) # tm_se_meas=1 tm_bus_inv=0 tm_buf_pwrup=1 (tbuf_tb1_on)\nwac('TM_PIN', 0x0095) # tm_asdx_sel=4 (BUFF2_INP) tm_asdx_en=1 tm_int2_sel=2 (BUFF1_OUT) tm_int2_en=1\nwac('TM_ADDR', 0x0b0e) # tm_cfg=0xb; tm_addr=0xe (reference voltage/current test)\ndly(100e-6)\ngav('V_CM_GYR_RAW', 'INT2', 'ASDX')\ncalc('V_CM_GYR', 'V_CM_GYR_RAW', '-', 'V_OFF1_ECOFF')\nlog('V_CM_GYR')\nwac('TM_CONF', 0x0111) # tm_se_meas=1 tm_bus_inv=1 tm_buf_pwrup=1 (tbuf_tb1_on)\ndly(100e-6)\ngav('V_CM_GYR_BUF_RAW', 'INT2', 'ASDX')\ncalc('V_CM_GYR_BUF', 'V_CM_GYR_BUF_RAW', '-', 'V_OFF1_ECOFF')\nlog('V_CM_GYR_BUF')\nwac('TM_ADDR', 0x0000) # Disable ATM\nwac('TM_PIN', 0x0000) # Reset pin config\nwac('TM_CONF', 0x0000) # Disable TBs and reset test config\n", "output": "/*****************************************************\n * T17_10_GYR_CM_reference_measurement_V3, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n * JSH5SGH: fix some bugs.\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T17_10_GYR_CM_reference_measurement_V3: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static double d_V_CM_GYR_BUF_RAW[xNSitES];\n static double d_V_CM_GYR_RAW[xNSitES];\n static double V_CM_GYR_BUF[xNSitES];\n static double V_CM_GYR[xNSitES];\n static int i_funcRes0[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(d_V_CM_GYR_BUF_RAW, 9.9, xNSitES);\n Func_Init_Var(d_V_CM_GYR_RAW, 9.9, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T17_10_GYR_CM_reference_measurement}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 1] @ avcline 788: {gav('V_CM_GYR_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 1] @ avcline 788: {calc('V_CM_GYR', 'V_CM_GYR_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 1] @ avcline 788: {log('V_CM_GYR', '', '', 0, 0)}\n valid comment[ 2] @ avcline 991: {gav('V_CM_GYR_BUF_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n valid comment[ 2] @ avcline 991: {calc('V_CM_GYR_BUF', 'V_CM_GYR_BUF_RAW', '-', 'V_OFF1_ECOFF')}\n valid comment[ 2] @ avcline 991: {log('V_CM_GYR_BUF', '', '', 0, 0)}\n valid comment[ 3] @ avcline 1568: {Test End: T17_10_GYR_CM_reference_measurement}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][1]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_CM_GYR_RAW//{gav('V_CM_GYR_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n .insertSub(i_comment_line[0][2]).pin(\"INT2,ASDX\", TA::BADC).vMeas().average(128).measWait(1 ms)//V_CM_GYR_BUF_RAW//{gav('V_CM_GYR_BUF_RAW', 'INT2', 'ASDX', 2, 0.0001, True)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n ARRAY_D ad_jsubresults_INT2; ad_jsubresults_INT2.resize(2); ad_jsubresults_INT2.init(-9.9);\n ARRAY_D ad_jsubresults_ASDX; ad_jsubresults_ASDX.resize(2); ad_jsubresults_ASDX.init(-9.9);\n ad_jsubresults_INT2 = rdi.id(\"dcid_0\").getMultiValue(\"INT2\");\n ad_jsubresults_ASDX = rdi.id(\"dcid_0\").getMultiValue(\"ASDX\");\n \n d_V_CM_GYR_BUF_RAW[curSite] = ad_jsubresults_INT2[1] - ad_jsubresults_ASDX[1] - V_OFF1_ECOFF[curSite];\n d_V_CM_GYR_RAW[curSite] = ad_jsubresults_INT2[0] - ad_jsubresults_ASDX[0] - V_OFF1_ECOFF[curSite];\n FuncPrint(\"V_CM_GYR_BUF_RAW\",d_V_CM_GYR_BUF_RAW[curSite]);\n FuncPrint(\"V_CM_GYR_RAW\",d_V_CM_GYR_RAW[curSite]);\n\n V_CM_GYR_BUF[curSite] = d_V_CM_GYR_BUF_RAW[curSite] - V_OFF1_ECOFF[curSite];\n V_CM_GYR[curSite] = d_V_CM_GYR_RAW[curSite] - V_OFF1_ECOFF[curSite];\n FuncPrint(\"V_CM_GYR_BUF\",V_CM_GYR_BUF[curSite]);\n FuncPrint(\"V_CM_GYR\",V_CM_GYR[curSite]);\n\n FOR_EACH_SITE_END();\n\n\n ON_FIRST_INVOCATION_END();\n\n TestLog(\"V_CM_GYR_BUF\",V_CM_GYR_BUF[curSite]);\n TestLog(\"V_CM_GYR\",V_CM_GYR[curSite]);\n\n i_funcRes[curSite] = i_funcRes0[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T17_10_GYR_CM_reference_measurement_V3\", T17_10_GYR_CM_reference_measurement_V3);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: Measure suspend current\n# - Entry condition STC_ACC\n# - External bypass MEM supply\n# - Power up memory\n# - Measure and calc power cosumption of memory\n#############################################################################################################\ncmt('Version info: $Revision: 3 $ $Author: luz3sgh $ $Date: 2024/04/23 07:53:06 GMT $')\nwac('EXT_MODE', 0xc00d) # Switch to ANA/PMU register page\nwac('PMU_TEST_DPWR_CTRL', 0x0016) # mem_precharge_n=1; mem_enable_n=1; mem_discharge=0; mem_iso_en=1\nwac('PMU_TEST_DPWR_CTRL', 0x0017) # Enable mem power overwrite signals\ndly(100e-6)\nsav('OCSB', 1.1, v_range=2.0, i_comp=10e-3) \ndly(100e-6)\nwac('EXT_MODE', 0xc00d) # Switch to ANA/PMU register page\nwac('OCP_MASK', 0x4000) # Set masking register\nwr('ANA_TEST_PWR', 0x4000) # Bypass VDDD_MEM to external pad\nrac('ANA_TEST_PWR', 0x4000,0x4000) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('EXT_MODE', 0xc007) # Switch to MCU register page\nwac('MCU_GLOB_CTRL', 0x0001) # Power on memory/DMA; assign 8kB (max) RAM to MCU\ndly(300e-6)\ngac('I_VDD_MEM', 'OCSB', i_range=100e-6)\nwac('MCU_GLOB_CTRL', 0x4000) # Power off memory/DMA; reset memory assignment-2K fifo, 6k mcu\nwac('EXT_MODE', 0xc00d) # Switch to ANA/PMU register page\nwac('OCP_MASK', 0x4000) # Set masking register\nwr('ANA_TEST_PWR', 0x0000) # Disable VDDD_MEM to external pad bypass\nrac('ANA_TEST_PWR', 0x0000,0x4000) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nuav('OCSB')\ndly(100e-6)\nwac('EXT_MODE', 0xc00d) # Switch to ANA/PMU register page\nwac('PMU_TEST_DPWR_CTRL', 0x0016) # Disable mem power overwrite signals\nwac('PMU_TEST_DPWR_CTRL', 0x001e) # Reset register settings\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T18_01_Current_Consumption_Memory_V3: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n static double I_VDD_MEM[xNSitES];\n // Auto_Code_Variable_define\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n rdi.enableOre(oreFlag);\n rdi.oreFile(\"./ORE_Files/rdi_ore_T18_01_CURRENT_CONSUMPTION_MEMORY.xml\");\n\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T18_01_Current_Consumption_Memory_V3_PAT_id\");\n rdi.dc(\"T18_01_Current_Consumption_Memory_V3DC_id0\").label(s_label_name)\n .insertSub(i_comment_line0[0]).pin(\"OCSB\").vForce(1.1)\n// Alarm::vForce value had not been assigned in TOI, need manual check\n .insertSub(i_comment_line0[1]).pin(\"OCSB\").vForce(1.1 V).iMeas().valueMode(TA::BADC).iRange(100 uA).average(16).measWait(10 ms) //I_VDD_MEM\n .insertSub(i_comment_line0[2]).pin(\"OCSB\").relay(TA::ppmuRly_offALL)\n .execute();\n RDI_END();\n\n // Auto_Code_Execution_Part\n\n\n\n ON_FIRST_INVOCATION_END();\n ARRAY_D JSUB_results_OCSB;\n JSUB_results_OCSB = rdi.id(\"T18_01_Current_Consumption_Memory_V3DC_id0\").getMultiValue(\"OCSB\");\n I_VDD_MEM[CURRENT_SITE_NUMBER()-1] = JSUB_results_OCSB[0];\n FuncPrint(\"I_VDD_MEM\", I_VDD_MEM[CURRENT_SITE_NUMBER()-1]);\n\n // Auto_Code_Retrieve_Data\n \n int Func_result = rdi.id(\"T18_01_Current_Consumption_Memory_V3_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"I_VDD_MEM\", I_VDD_MEM[CURRENT_SITE_NUMBER()-1]);\n // Auto_Code_Judge_and_log\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T18_01_Current_Consumption_Memory_V3\", T18_01_Current_Consumption_Memory_V3);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: Measure suspend current\n# Setup phase--external bypass MEM supply to OCSB\n# Set supply on OSCB from 1.1V to 0.4V in 0.05V steps\n# Run MBIST and store pass fail\n# Log last MBIST pass voltage\n#############################################################################################################\n\nfrom test_sub_functions import *\nCRC = get_rom_crc() # Parameter to calculate the current ROM CRC\n\ncmt('Version info: $Revision: bai430aa_rel/1 $ $Author: luz3sgh $ $Date: 2024/09/03 02:00:35 GMT $')\n#Set up phase--disable internal memory supply\nwac('EXT_MODE', 0xc00d) # Switch to ANA/PMU register page\nwcb('dpwr_mem_owr_en',1) # PMU_TEST_DPWR_CTRL.bit0 , Activate above overwrite controls\nwcb('owr_dpwr_mem_discharge',0) # PMU_TEST_DPWR_CTRL.bit3 , open S5\nwcb('owr_dpwr_mem_enable_n',1) # PMU_TEST_DPWR_CTRL.bit2 , low active , set to 1 to open S3\n#Set up phase--enable external memory supply\ndly(100e-6)\nsav('OCSB', 1.1, v_range=2.0, i_comp=10e-3)\ndly(100e-6)\nwac('EXT_MODE', 0xc00d) # Switch to ANA/PMU register page\nwac('OCP_MASK', 0x4000) # Set masking register\nwr('ANA_TEST_PWR', 0x4000) # Bypass VDDD_MEM to external pad, bit14, vddd_mem_ext_en set to 1, Close S8\nrac('ANA_TEST_PWR', 0x4000,0x4000) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n#Config MBIST\nwac('EXT_MODE',0xc00d) # Switch to PMU register page\nwcb('owr_dpwr_mem_iso_en', 0) # PMU_TEST_DPWR_CTRL.bit4 , Release memory isolation\nwcb('force_ds_pwr_on', 0x1) # PMU.PMU_TEST_DPWR_CTRL, force digital switch power domain always powered on\nwac('EXT_MODE',0xc000) # Switch to USR register page\nwcb('mem_conf_ram', 0x0) # USR/MCU.MCU_GLOB_CTRL bit 15:14, Assign 4kB RAM to MCU\nwac('IO_INT_CTRL', 0x0005) # Enable INT1 as output and active high\nwac('INT_MAP_MCU', 0x4000) # Map command execution interrupt to INT1\nwac('INT_CONF', 0x0001) # Use latched interrupt mode for INT1\n#Run MBIST\ncmt(\"MBIST sequence start--\")\nsav('OCSB', 1.1, v_range=2.0, i_comp=10e-3)\nwr('MCU_GP_1', 0x007b) # MCU boot ASIC test; Select MBIST\nwr('MCU_GP_STATUS', 0x0001) # Sync GP register\nwcb('mcu_mode', 0x3) # *** USR/MCU.MCU_GLOB_CTRL bit 1:0,Power on MCU\ndly(125e-3)\nbc('INT1', 1) # Check FW ready interrupt\nrac('MCU_GP_0', 0x017B) # Check MBIST test result\nrac('MCU_SW_STATUS3', CRC) # Check ROM CRC\nwcb('mcu_mode', 0x0) # Power off MCU (reset of MCU_GLOB_CTRL splited to two steps)\ncmt(\"--MBIST sequence end\")\ncmt(\"TOI: If MBIST sequence pass, reduce OCSB voltage by 50mV and repeat untill MBIST fail or OCSB voltage equal to 400mV\")\ncmt(\"TOI: Log OCSB voltage at which MBIST passes for the last time as V_MEM_SUPPLY_MIN\")\nlog(\"V_MEM_SUPPLY_MIN\")\n#Clean\nwac('IO_INT_CTRL', 0x0000) # User page reg, Reset IO configuration\nwac('INT_MAP_MCU', 0x0000) # Reset interrupt mapping\nwac('INT_CONF', 0x0000) # Reset interrupt configuration\nwcb('mem_conf_ram', 0x2) # Set RAM config to default(2nd step of MCU_GLOB_CTRL reset)\nwac('EXT_MODE', 0xc00d) # Switch to ANA/PMU register page\nwac('OCP_MASK', 0x4000) # Set masking register\nwr('ANA_TEST_PWR', 0x0000) # Disable VDDD_MEM to external pad bypass\nrac('ANA_TEST_PWR', 0x0000,0x4000) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nuav('OCSB')\ndly(100e-6)\nwac('EXT_MODE', 0xc00d) # Switch to ANA/PMU register page\nwac('PMU_TEST_DPWR_CTRL', 0x0016) # Disable mem power overwrite signals\nwac('PMU_TEST_DPWR_CTRL', 0x001e) # Reset register settings\n", "output": "/*****************************************************\n * T18_02_Memory_Supply_Char_R1, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n * JSH5SGH: update algorithm.\n * JSH5SGH: update pattern to R1.\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T18_02_Memory_Supply_Char_R1: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 3;\n vector i_comment_line[i_split_count];\n\n static int i_funcRes0[xNSitES], i_funcRes2[xNSitES];\n static double V_MEM_SUPPLY_MIN[xNSitES];\n\n const int reduce_step = 20;\n const double v_OCSB_start = 1.3;\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n if (i_split_pat_flag)\n {\n \t split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n }\n else\n {\n\t\t\t split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n\t\t\t for(int i=0; i }\n valid comment[ 1] @ avcline 1262: {sav('OCSB', 1.1, 2, 0.01, False, False)}\n\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][1]).pin(\"OCSB\").vForce(v_OCSB_start)//{sav('OCSB', 1.1, 2, 0.01, False, False)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n FuncPrint(\"i_funcRes0\", i_funcRes0[curSite]);\n FOR_EACH_SITE_END();\n /* Ori key coments in subpat1 ~~~~~~~~~~~~~~\n Manually add cut_here\n valid comment[ 0] @ avcline 4049: {cmt: MBIST sequence start--}\n valid comment[ 0] @ avcline 4049: {sav('OCSB', 1.1, 2, 0.01, False, False)}\n valid comment[ 1] @ avcline 4791: {cmt: --MBIST sequence end}\n valid comment[ 2] @ avcline 4791: {cmt: TOI: If MBIST sequence pass, reduce OCSB voltage by 50mV and repeat untill MBIST fail or OCSB voltage equal to 400mV}\n valid comment[ 2] @ avcline 4791: {cmt: TOI: Log OCSB voltage at which MBIST passes for the last time as V_MEM_SUPPLY_MIN}\n valid comment[ 2] @ avcline 4791: {log('V_MEM_SUPPLY_MIN', '', '', 0, 0)}l\n */\n for(int i=0; i i_comment_line0;\n\n static double I_VDDP_OTP_OFF[xNSitES];\n static double I_VDDD_OTP_OFF[xNSitES];\n static double I_VDDP_OTP_ON[xNSitES];\n static double I_VDDD_OTP_ON[xNSitES];\n static double I_VDDP_OTP[xNSitES];\n static double I_VDDD_OTP[xNSitES];\n // Auto_Code_Variable_define\n double d_V_INT1, d_V_OCSB;\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n d_V_INT1 = Primary.getLevelSpec().getSpecValue(\"INT1\");\n d_V_OCSB = Primary.getLevelSpec().getSpecValue(\"OCSB\");\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T18_03_Current_Consumption_OTP_V2_PAT_id\");\n rdi.dc(\"T18_03_Current_Consumption_OTP_V2DC_id0\").label(s_label_name)\n .insertSub(i_comment_line0[0]).pin(\"OCSB\").vForce(d_V_OCSB).iMeas().valueMode(TA::BADC).iRange(1e-05 A).average(16).measWait(10 ms) //I_VDDP_OTP_OFF\n .insertSub(i_comment_line0[0]).pin(\"INT1\").vForce(d_V_INT1).iMeas().valueMode(TA::BADC).iRange(10e-05 A).average(16).measWait(10 ms) //I_VDDD_OTP_OFF\n .insertSub(i_comment_line0[0]).pin(\"OCSB\").vForce(d_V_OCSB).iRange(40 mA)\n .insertSub(i_comment_line0[0]).pin(\"INT1\").vForce(d_V_INT1).iRange(40 mA)\n .insertSub(i_comment_line0[1]).pin(\"OCSB\").vForce(d_V_OCSB).iMeas().valueMode(TA::BADC).iRange(1e-05 A).average(16).measWait(10 ms) //I_VDDP_OTP_ON\n .insertSub(i_comment_line0[1]).pin(\"INT1\").vForce(d_V_INT1).iMeas().valueMode(TA::BADC).iRange(10e-05 A).average(16).measWait(10 ms) //I_VDDD_OTP_ON\n .insertSub(i_comment_line0[1]).pin(\"OCSB\").vForce(d_V_OCSB).iRange(40 mA)\n .insertSub(i_comment_line0[1]).pin(\"INT1\").vForce(d_V_INT1).iRange(40 mA)\n .execute();\n RDI_END();\n\n ON_FIRST_INVOCATION_END();\n ARRAY_D JSUB_results_OCSB;\n JSUB_results_OCSB = rdi.id(\"T18_03_Current_Consumption_OTP_V2DC_id0\").getMultiValue(\"OCSB\");\n ARRAY_D JSUB_results_INT1;\n JSUB_results_INT1 = rdi.id(\"T18_03_Current_Consumption_OTP_V2DC_id0\").getMultiValue(\"INT1\");\n I_VDDP_OTP_OFF[CURRENT_SITE_NUMBER()-1] = JSUB_results_OCSB[0];\n I_VDDD_OTP_OFF[CURRENT_SITE_NUMBER()-1] = JSUB_results_INT1[0];\n I_VDDP_OTP_ON[CURRENT_SITE_NUMBER()-1] = JSUB_results_OCSB[1];\n I_VDDD_OTP_ON[CURRENT_SITE_NUMBER()-1] = JSUB_results_INT1[1];\n\n I_VDDP_OTP[CURRENT_SITE_NUMBER()-1] = I_VDDP_OTP_ON[CURRENT_SITE_NUMBER()-1] - I_VDDP_OTP_OFF[CURRENT_SITE_NUMBER()-1];\n I_VDDD_OTP[CURRENT_SITE_NUMBER()-1] = I_VDDD_OTP_ON[CURRENT_SITE_NUMBER()-1] - I_VDDD_OTP_OFF[CURRENT_SITE_NUMBER()-1];\n FuncPrint(\"I_VDDP_OTP_OFF\", I_VDDP_OTP_OFF[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"I_VDDD_OTP_OFF\", I_VDDD_OTP_OFF[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"I_VDDP_OTP_ON\", I_VDDP_OTP_ON[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"I_VDDD_OTP_ON\", I_VDDD_OTP_ON[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"I_VDDP_OTP\", I_VDDP_OTP[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"I_VDDD_OTP\", I_VDDD_OTP[CURRENT_SITE_NUMBER()-1]);\n // Auto_Code_Retrieve_Data\n \n int Func_result = rdi.id(\"T18_03_Current_Consumption_OTP_V2_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"I_VDDP_OTP\", I_VDDP_OTP[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"I_VDDD_OTP\", I_VDDD_OTP[CURRENT_SITE_NUMBER()-1]);\n // Auto_Code_Judge_and_log\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T18_03_Current_Consumption_OTP_V2\", T18_03_Current_Consumption_OTP_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: Measure the Standby mode current on VDD, VDDIO\n# - Measure directly after chip power on\n#############################################################################################################\ncmt('Version info: $Revision: 2 $ $Author: hmf1rt $ $Date: 2024/07/08 08:09:24 GMT $')\ndly(74e-9)\ngac('I_VDD_STANDBY', 'VDD', i_range = 20e-6)\ngac('I_VDDIO_STANDBY', 'VDDIO', i_range = 10e-6 )\nlog('I_VDD_STANDBY')\nlog('I_VDDIO_STANDBY')\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T18_18_Current_Consumption_Test_Standby_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n static double I_VDD_STANDBY[xNSitES];\n static double I_VDDIO_STANDBY[xNSitES];\n static double v_VDDIO, v_VDD;\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n v_VDDIO = Primary.getLevelSpec().getSpecValue(\"VDDIO\");\n v_VDD = Primary.getLevelSpec().getSpecValue(\"VDD\");\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T18_18_Current_Consumption_Test_Standby_V2_PAT_id\");\n rdi.dc(\"T18_18_Current_Consumption_Test_Standby_V2DC_id0\").label(s_label_name)\n .insertSub(i_comment_line0[0]).pin(\"VDD\").vForce(v_VDD).iMeas().valueMode(TA::BADC).iRange(2e-05 A).average(16).measWait(1 ms) //I_VDD_STANDBY\n .insertSub(i_comment_line0[0]).pin(\"VDDIO\").vForce(v_VDDIO).iMeas().valueMode(TA::BADC).iRange(1e-05 A).average(16).measWait(1 ms) //I_VDDIO_STANDBY\n .insertSub(i_comment_line0[0]).pin(\"VDD\").vForce(v_VDD).iRange(40 mA)\n .insertSub(i_comment_line0[0]).pin(\"VDDIO\").vForce(v_VDDIO).iRange(40 mA)\n .execute();\n RDI_END();\n\n // Auto_Code_Execution_Part\n\n\n\n ON_FIRST_INVOCATION_END();\n ARRAY_D JSUB_results_VDD;\n JSUB_results_VDD = rdi.id(\"T18_18_Current_Consumption_Test_Standby_V2DC_id0\").getMultiValue(\"VDD\");\n ARRAY_D JSUB_results_VDDIO;\n JSUB_results_VDDIO = rdi.id(\"T18_18_Current_Consumption_Test_Standby_V2DC_id0\").getMultiValue(\"VDDIO\");\n I_VDD_STANDBY[CURRENT_SITE_NUMBER()-1] = JSUB_results_VDD[0];\n I_VDDIO_STANDBY[CURRENT_SITE_NUMBER()-1] = JSUB_results_VDDIO[0];\n\n FuncPrint(\"I_VDD_STANDBY\", I_VDD_STANDBY[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"I_VDDIO_STANDBY\", I_VDDIO_STANDBY[CURRENT_SITE_NUMBER()-1]);\n // Auto_Code_Retrieve_Data\n \n int Func_result = rdi.id(\"T18_18_Current_Consumption_Test_Standby_V2_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"I_VDD_STANDBY\", I_VDD_STANDBY[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"I_VDDIO_STANDBY\", I_VDDIO_STANDBY[CURRENT_SITE_NUMBER()-1]);\n // Auto_Code_Judge_and_log\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T18_18_Current_Consumption_Test_Standby_V2\", T18_18_Current_Consumption_Test_Standby_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: Measure suspend current\n# - Item run after power cycle & SPI4 enabled\n#############################################################################################################\ncmt('Version info: $Revision: 2 $ $Author: luz3sgh $ $Date: 2024/05/22 08:03:42 GMT $')\nrac('CHIP_ID', 0x00af, 0x00ff) # Check chip access \nwr('PWR_CONF', 0x0001) # Advance power save enabled\ndly(200e-6)\nrac('PWR_CONF',0x0001,0x0001)\ndly(100e-6)\ngac('I_VDD_SUSPEND', 'VDD', i_range = 20e-6 )\ngac('I_VDDIO_SUSPEND', 'VDDIO', i_range = 10e-6 )\nlog('I_VDD_SUSPEND')\nlog('I_VDDIO_SUSPEND')\ndly(100e-6)\nwr('PWR_CONF', 0x0000) # Disable advanced power save\ndly(200e-6)\nrac('PWR_CONF', 0x0000) # Check register setting\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T18_20_Current_Consumption_Test_Suspend_V1: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n static double I_VDD_SUSPEND[xNSitES];\n static double I_VDDIO_SUSPEND[xNSitES];\n\n static double v_VDDIO, v_VDD;\n // Auto_Code_Variable_define\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n v_VDDIO = Primary.getLevelSpec().getSpecValue(\"VDDIO\");\n v_VDD = Primary.getLevelSpec().getSpecValue(\"VDD\");\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T18_20_Current_Consumption_Test_Suspend_V1_PAT_id\");\n rdi.dc(\"T18_20_Current_Consumption_Test_Suspend_V1DC_id0\").label(s_label_name)\n .insertSub(i_comment_line0[0]).pin(\"VDD\").vForce(v_VDD V).iMeas().valueMode(TA::BADC).iRange(100 uA).average(16).measWait(1 ms) //I_VDD_SUSPEND\n .insertSub(i_comment_line0[0]).pin(\"VDDIO\").vForce(v_VDDIO V).iMeas().valueMode(TA::BADC).iRange(1e-05 A).average(16).measWait(1 ms) //I_VDDIO_SUSPEND\n .insertSub(i_comment_line0[0]).pin(\"VDD\").vForce(v_VDD).iRange(40 mA)\n .insertSub(i_comment_line0[0]).pin(\"VDDIO\").vForce(v_VDDIO).iRange(40 mA)\n .execute();\n RDI_END();\n\n ON_FIRST_INVOCATION_END();\n ARRAY_D JSUB_results_VDDIO;\n JSUB_results_VDDIO = rdi.id(\"T18_20_Current_Consumption_Test_Suspend_V1DC_id0\").getMultiValue(\"VDDIO\");\n ARRAY_D JSUB_results_VDD;\n JSUB_results_VDD = rdi.id(\"T18_20_Current_Consumption_Test_Suspend_V1DC_id0\").getMultiValue(\"VDD\");\n I_VDD_SUSPEND[CURRENT_SITE_NUMBER()-1] = JSUB_results_VDD[0];\n I_VDDIO_SUSPEND[CURRENT_SITE_NUMBER()-1] = JSUB_results_VDDIO[0];\n\n int Func_result = rdi.id(\"T18_20_Current_Consumption_Test_Suspend_V1_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n FuncPrint(\"I_VDD_SUSPEND\", I_VDD_SUSPEND[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"I_VDDIO_SUSPEND\", I_VDDIO_SUSPEND[CURRENT_SITE_NUMBER()-1]);\n\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"I_VDD_SUSPEND\", I_VDD_SUSPEND[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"I_VDDIO_SUSPEND\", I_VDDIO_SUSPEND[CURRENT_SITE_NUMBER()-1]);\n // Auto_Code_Judge_and_log\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T18_20_Current_Consumption_Test_Suspend_V1\", T18_20_Current_Consumption_Test_Suspend_V1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: Measure the Combo mode current on VDD, VDDIO\n# - The settings of T01_11_set_device_config_STC_COMBO are used unchanged.\n# ACC in HPM; AFS=32g; ODR=1600; BW=200\n# GYR in HPM; GFS=4K; ODR=1600; BW=200\n#############################################################################################################\ncmt('Version info: $Revision: bai430aa_rel/1 $ $Author: hmk2rt $ $Date: 2024/10/04 10:51:05 GMT $')\nwac('EXT_MODE', 0x0000) # Normal mode and user page.\ndly(200e-6)\n\ngac('I_VDD_COMBO', 'VDD', i_range = 1e-3 )\nlog('I_VDD_COMBO')\ngac('I_VDDIO_COMBO', 'VDDIO', i_range = 10e-6 )\nlog('I_VDDIO_COMBO')\n\nwr('CMD', 0xBB3A) # 1st command for enabling the extended mode\nwr('CMD', 0x2C62) # 2nd command for enabling the extended mode\nwr('CMD', 0xA576) # 1st command for enabling the super privilege mode\nwr('CMD', 0x34D6) # 2nd command for enabling the super privilege mode\ndly(200e-6)\n", "output": "/*****************************************************\n * T18_21_Current_Consumption_Test_Combo_V1, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T18_21_Current_Consumption_Test_Combo_V1: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static double d_I_VDDIO_COMBO[xNSitES];\n static double d_I_VDD_COMBO[xNSitES];\n static int i_funcRes0[xNSitES];\n static double d_v_VDDIO, d_v_VDD;\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(d_I_VDDIO_COMBO, 9.9, xNSitES);\n Func_Init_Var(d_I_VDD_COMBO, 9.9, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T18_21_Current_Consumption_Test_Combo}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 1] @ avcline 20: {gac('I_VDD_COMBO', 'VDD', 0.001, 0.0001, True)}\n valid comment[ 1] @ avcline 20: {log('I_VDD_COMBO', '', '', 0, 0)}\n valid comment[ 2] @ avcline 21: {gac('I_VDDIO_COMBO', 'VDDIO', 1e-05, 0.0001, True)}\n valid comment[ 2] @ avcline 21: {log('I_VDDIO_COMBO', '', '', 0, 0)}\n valid comment[ 3] @ avcline 22: {Test End: T18_21_Current_Consumption_Test_Combo}\n */\n\n d_v_VDDIO = Primary.getLevelSpec().getSpecValue(\"VDDIO\");\n d_v_VDD = Primary.getLevelSpec().getSpecValue(\"VDD\");\n\n\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][1]).pin(\"VDD\").iClamp(500 mA)//todo 500mA not avaliable\n .insertSub(i_comment_line[0][1]).pin(\"VDD\").iForceRange(500 mA)\n .insertSub(i_comment_line[0][1]).pin(\"VDD\").vForce(d_v_VDD V).iMeas().valueMode(TA::BADC)//{gac('I_VDD_COMBO', 'VDD', 0.001, 0.0001, True)}\n .insertSub(i_comment_line[0][2]).pin(\"VDDIO\").iClamp(500 mA)\n .insertSub(i_comment_line[0][2]).pin(\"VDDIO\").iForceRange(500 mA)\n .insertSub(i_comment_line[0][2]).pin(\"VDDIO\").vForce(d_v_VDDIO V).iMeas().valueMode(TA::BADC)//{gac('I_VDDIO_COMBO', 'VDDIO', 1e-05, 0.0001, True)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n ARRAY_D ad_jsubresults_VDD; ad_jsubresults_VDD.resize(1); ad_jsubresults_VDD.init(-9.9);\n ARRAY_D ad_jsubresults_VDDIO; ad_jsubresults_VDDIO.resize(1); ad_jsubresults_VDDIO.init(-9.9);\n ad_jsubresults_VDD = rdi.id(\"dcid_0\").getMultiValue(\"VDD\");\n \n ad_jsubresults_VDDIO = rdi.id(\"dcid_0\").getMultiValue(\"VDDIO\");\n \n d_I_VDD_COMBO[curSite] = ad_jsubresults_VDD[0];\n d_I_VDDIO_COMBO[curSite] = ad_jsubresults_VDDIO[0];\n FuncPrint(\"I_VDDIO_COMBO\",d_I_VDDIO_COMBO[curSite]);\n FuncPrint(\"I_VDD_COMBO\",d_I_VDD_COMBO[curSite]);\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n\n ON_FIRST_INVOCATION_END();\n\n TestLog(\"I_VDDIO_COMBO\",d_I_VDDIO_COMBO[curSite]);\n TestLog(\"I_VDD_COMBO\",d_I_VDD_COMBO[curSite]);\n i_funcRes[curSite] = i_funcRes0[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T18_21_Current_Consumption_Test_Combo_V1\", T18_21_Current_Consumption_Test_Combo_V1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# Description: Switch on TEMP and measure current consumption\n# Note: Temp is continously running during the current meausurement but the TADC is duty-cycling in\n# test mode (~80%). This test item is not intended to give the maximum (worst-case) in-rush temp current\n# but to implement a failure-part screening for production test\n#############################################################################################################\ncmt('Version info: $Revision: 2 $ $Author: luz3sgh $ $Date: 2024/04/24 07:27:28 GMT $')\nwac('EXT_MODE', 0xc006) # Switch to FCU register page\nwac('OCP_MASK', 0x7800) \nwac('FCU_TEST_CONF',0x6000) # Set temp_test_odr = 3.2KHz\nwac('FCU_TEST_CONF',0x6800) # Set temp_mode to on, run temp even all sensors off\ndly(3e-3) # Wait for regular temp measurement to be finished (if hit) \ncmt('Meaure currents for a minimum averaging period of 2ms')\ngac('I_VDD_TEMP', 'VDD', i_range=500e-6, period=2e-3)\nlog('I_VDD_TEMP')\ngac('I_VDDIO_TEMP', 'VDDIO', i_range=10e-6, period=2e-3)\nlog('I_VDDIO_TEMP')\nwac('FCU_TEST_CONF',0x0000) # Disable force, reset temp odr to auto\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\ndly(100e-6)\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T18_25_Current_Consumption_Test_Temp_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n static double I_VDD_TEMP[xNSitES];\n static double I_VDDIO_TEMP[xNSitES];\n // Auto_Code_Variable_define\n static double v_VDDIO, v_VDD;\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n rdi.enableOre(oreFlag);\n rdi.oreFile(\"./ORE_Files/rdi_ore_T18_25_CURRENT_CONSUMPTION_TEST_TEMP.xml\");\n\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n v_VDDIO = Primary.getLevelSpec().getSpecValue(\"VDDIO\");\n v_VDD = Primary.getLevelSpec().getSpecValue(\"VDD\");\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T18_25_Current_Consumption_Test_Temp_V2_PAT_id\");\n rdi.dc(\"T18_25_Current_Consumption_Test_Temp_V2DC_id0\").label(s_label_name)\n .insertSub(i_comment_line0[0]).pin(\"VDD\").vForce(v_VDD V).iMeas().valueMode(TA::BADC).iRange(1 mA).average(16).measWait(0.1 ms) //I_VDD_TEMP\n .insertSub(i_comment_line0[1]).pin(\"VDDIO\").vForce(v_VDDIO V).iMeas().valueMode(TA::BADC).iRange(1e-05 A).average(16).measWait(2 ms) //I_VDDIO_TEMP\n .insertSub(i_comment_line0[1]).pin(\"VDDIO\").vForce(v_VDDIO V).iRange(40 mA)\n .insertSub(i_comment_line0[1]).pin(\"VDD\").vForce(v_VDD V).iRange(40 mA)\n .execute();\n RDI_END();\n\n // Auto_Code_Execution_Part\n\n\n\n ON_FIRST_INVOCATION_END();\n ARRAY_D JSUB_results_VDDIO;\n JSUB_results_VDDIO = rdi.id(\"T18_25_Current_Consumption_Test_Temp_V2DC_id0\").getMultiValue(\"VDDIO\");\n ARRAY_D JSUB_results_VDD;\n JSUB_results_VDD = rdi.id(\"T18_25_Current_Consumption_Test_Temp_V2DC_id0\").getMultiValue(\"VDD\");\n I_VDD_TEMP[CURRENT_SITE_NUMBER()-1] = JSUB_results_VDD[0];\n I_VDDIO_TEMP[CURRENT_SITE_NUMBER()-1] = JSUB_results_VDDIO[0];\n\n\n // Auto_Code_Retrieve_Data\n \n int Func_result = rdi.id(\"T18_25_Current_Consumption_Test_Temp_V2_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n FuncPrint(\"I_VDD_TEMP\", I_VDD_TEMP[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"I_VDDIO_TEMP\", I_VDDIO_TEMP[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"I_VDD_TEMP\", I_VDD_TEMP[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"I_VDDIO_TEMP\", I_VDDIO_TEMP[CURRENT_SITE_NUMBER()-1]);\n // Auto_Code_Judge_and_log\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T18_25_Current_Consumption_Test_Temp_V2\", T18_25_Current_Consumption_Test_Temp_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: Measure the Combo mode current on VDD, VDDIO\n#############################################################################################################\ncmt('Version info: $Revision: 1 $ $Author: hmf1rt $ $Date: 2024/03/13 13:36:52 GMT $')\nwac('EXT_MODE', 0xc000) # Switch to USR register page\nwac('ACC_CONF', 0x6a48) # Enable ACC in LPM; AFS=32g; acc_avg_num= 2 (avg4) ODR=100; BW=200\nwac('GYR_CONF', 0x6a58) # Enable GYR in LPM; GFS=4K; gyr_avg_num= 2 (avg4) ODR=100; BW=200\ndly(5e-3) # wait some time after configuration changes\ncmt('TOI: The following measurements should be executed in parallel')\ngac('I_VDD_COMBO_LPM', 'VDD', i_range=1e-3, period=100e-3)\ngac('I_VDDIO_COMBO_LPM', 'VDDIO', i_range=10e-6)\nlog('I_VDD_COMBO_LPM')\nlog('I_VDDIO_COMBO_LPM')\n\nwac('ACC_CONF', 0xe24c) # Enable ACC in HPM; set AFS=32g; set ODR=1600; set BW=200\nwac('GYR_CONF', 0xe25c) # Enable GYR in HPM; set GFS=4K; set ODR=1600; set BW=200\n", "output": "/*****************************************************\n * T18_27_Current_Consumption_Test_Combo_LPM_V1, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n * JSH5SGH: use a different approach to capture a current waveform of 100ms.\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T18_27_Current_Consumption_Test_Combo_LPM_V1: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n double\tV_VDD;\n double\tV_VDDIO;\n\nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 2;\n vector i_comment_line[i_split_count];\n\n static double d_I_VDDIO_COMBO_LPM[xNSitES];\n static double d_I_VDD_COMBO_LPM[xNSitES];\n static int i_funcRes0[xNSitES], i_funcRes1[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(d_I_VDDIO_COMBO_LPM, 9.9, xNSitES);\n Func_Init_Var(d_I_VDD_COMBO_LPM, 9.9, xNSitES);\n if (i_split_pat_flag)\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n }\n else\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n for(int i=0; i }\n */\n\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.func().label(s_splited_pat_name[0]).execute();\n\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n\t\t FOR_EACH_SITE_END();\n /* Ori key coments in subpat1 ~~~~~~~~~~~~~~\n add cut_here:\n valid comment[ 0] @ avcline 596: {cmt: TOI: The following measurements should be executed in parallel}\n valid comment[ 0] @ avcline 596: {gac('I_VDD_COMBO_LPM', 'VDD', 0.001, 0.1, True)}\n valid comment[ 0] @ avcline 596: {gac('I_VDDIO_COMBO_LPM', 'VDDIO', 1e-05, 0.0001, True)}\n valid comment[ 0] @ avcline 596: {log('I_VDD_COMBO_LPM', '', '', 0, 0)}\n valid comment[ 1] @ avcline 597: {log('I_VDDIO_COMBO_LPM', '', '', 0, 0)}\n valid comment[ 2] @ avcline 982: {Test End: T18_27_Current_Consumption_Test_Combo_LPM}\n */\n string s_rdi_unit, s_rdi_burstid, s_rdi_dcid;\n SWITCH_VDD(s_rdi_unit, s_rdi_burstid, s_rdi_dcid, 1);\n RDI_UNIT_INIT(s_rdi_unit);\n\n Primary.timing(SPECIFICATION(\"CURR_CONSUMPTION\"));\n FLUSH(TM::APRM);\n\n RDI_BEGIN(mode);\n rdi.burstId(s_rdi_burstid);\n rdi.port(\"VDD_Port\").dc(s_rdi_burstid+rdi.itos(0)).pin(\"VDD\").vForce(V_VDD V).iMeas().iRange(1 mA).samples(1000).capMode(TA::VEC)\n\t\t\t\t\t\t\t\t.valueMode(TA::BADC).samplePeriod(100 us).measWait(10 ms).execute();\n rdi.portSync();\n rdi.port(\"VDDIO_Port\").dc(s_rdi_burstid+rdi.itos(1)).pin(\"VDDIO\").vForce(V_VDDIO V).iMeas().iRange(100 uA).samples(1000).capMode(TA::VEC)\n\t\t\t\t\t\t\t\t.valueMode(TA::BADC).samplePeriod(100 us).measWait(10 ms).execute();\n rdi.portSync();\n rdi.port(\"IO_Port\").func().label(s_splited_pat_name[1]).execute();\n\n RDI_END();\n\n FOR_EACH_SITE_BEGIN();\n i_funcRes1[curSite] = rdi.id(s_rdi_burstid).getBurstPassFail();\n\n double d_AVG, d_STD;\n ARRAY_D ad_jsubresults_VDD = rdi.id(s_rdi_burstid+rdi.itos(0)).getWaveform(\"VDD\");\n ARRAY_D ad_jsubresults_VDDIO = rdi.id(s_rdi_burstid+rdi.itos(1)).getWaveform(\"VDDIO\");\n \n \t DSP_MEAN(ad_jsubresults_VDD, &d_AVG, &d_STD);\n \t d_I_VDD_COMBO_LPM[curSite] = d_AVG;\n FuncPrint(\"I_VDD_COMBO_LPM\", d_I_VDD_COMBO_LPM[curSite]);\n\n \t DSP_MEAN(ad_jsubresults_VDDIO, &d_AVG, &d_STD);\n \t d_I_VDDIO_COMBO_LPM[curSite] = d_AVG;\n FuncPrint(\"I_VDDIO_COMBO_LPM\", d_I_VDDIO_COMBO_LPM[curSite]);\n \n FOR_EACH_SITE_END();\n\t }\n\n ON_FIRST_INVOCATION_END();\n\n TestLog(\"I_VDDIO_COMBO_LPM\",d_I_VDDIO_COMBO_LPM[curSite]);\n TestLog(\"I_VDD_COMBO_LPM\",d_I_VDD_COMBO_LPM[curSite]);\n i_funcRes[curSite] = i_funcRes0[curSite] && i_funcRes1[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T18_27_Current_Consumption_Test_Combo_LPM_V1\", T18_27_Current_Consumption_Test_Combo_LPM_V1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: Measure the ACC mode current on VDD, VDDIO\n#############################################################################################################\ncmt('Version info: $Revision: 1 $ $Author: hmf1rt $ $Date: 2024/03/13 13:36:52 GMT $')\nwac('EXT_MODE', 0xc000) # Switch to USR register page\nwac('ACC_CONF', 0x6a48) # Enable ACC in LPM; AFS=32g; acc_avg_num= 2 (avg4) ODR=100; BW=200\ndly(5e-3) # wait some time after configuration changes\ncmt('TOI: The following measurements should be executed in parallel')\ngac('I_VDD_ACC_LPM', 'VDD', i_range=300e-6, period=100e-3)\ngac('I_VDDIO_ACC_LPM', 'VDDIO', i_range=10e-6)\nlog('I_VDD_ACC_LPM')\nlog('I_VDDIO_ACC_LPM')\nwac('ACC_CONF', 0xe24c) # Enable ACC in HPM; set AFS=32g; set ODR=1600; set BW=200\n", "output": "/*****************************************************\n * T18_29_Current_Consumption_Test_Acc_LPM_V1, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n * JSH5SGH: use a different approach to capture a current waveform of 100ms.\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T18_29_Current_Consumption_Test_Acc_LPM_V1: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n double\tV_VDD;\n double\tV_VDDIO;\n\nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static double d_I_VDDIO_ACC_LPM[xNSitES];\n static double d_I_VDD_ACC_LPM[xNSitES];\n static int i_funcRes0[xNSitES], i_funcRes1[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(d_I_VDDIO_ACC_LPM, 9.9, xNSitES);\n Func_Init_Var(d_I_VDD_ACC_LPM, 9.9, xNSitES);\n if (i_split_pat_flag)\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n }\n else\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n for(int i=0; i }\n */\n\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.func().label(s_splited_pat_name[0]).execute();\n\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n\t\t FOR_EACH_SITE_END();\n /* Ori key coments in subpat1 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 404: {cmt: TOI: The following measurements should be executed in parallel}\n valid comment[ 0] @ avcline 404: {gac('I_VDD_ACC_LPM', 'VDD', 0.0003, 0.1, True)}\n valid comment[ 0] @ avcline 404: {gac('I_VDDIO_ACC_LPM', 'VDDIO', 1e-05, 0.0001, True)}\n valid comment[ 0] @ avcline 404: {log('I_VDD_ACC_LPM', '', '', 0, 0)}\n valid comment[ 1] @ avcline 405: {log('I_VDDIO_ACC_LPM', '', '', 0, 0)}\n valid comment[ 2] @ avcline 598: {Test End: T18_29_Current_Consumption_Test_Acc_LPM}\n */\n string s_rdi_unit, s_rdi_burstid, s_rdi_dcid;\n SWITCH_VDD(s_rdi_unit, s_rdi_burstid, s_rdi_dcid, 1);\n RDI_UNIT_INIT(s_rdi_unit);\n\n Primary.timing(SPECIFICATION(\"CURR_CONSUMPTION\"));\n FLUSH(TM::APRM);\n\n RDI_BEGIN(mode);\n rdi.burstId(s_rdi_burstid);\n rdi.port(\"VDD_Port\").dc(s_rdi_burstid+\"V_VDD\").pin(\"VDD\").vForce(V_VDD V).iMeas().iRange(1 mA).samples(1000).capMode(TA::VEC)\n\t\t\t\t\t\t\t\t.valueMode(TA::BADC).samplePeriod(100 us).measWait(10 ms).execute();\n rdi.portSync();\n rdi.port(\"VDDIO_Port\").dc(s_rdi_burstid+\"V_VDDIO\").pin(\"VDDIO\").vForce(V_VDDIO V).iMeas().iRange(100 uA).samples(1000).capMode(TA::VEC)\n\t\t\t\t\t\t\t\t.valueMode(TA::BADC).samplePeriod(100 us).measWait(10 ms).execute();\n\t rdi.portSync();\n\t rdi.port(\"IO_Port\").func().label(s_splited_pat_name[1]).execute();\n\n RDI_END();\n\n FOR_EACH_SITE_BEGIN();\n i_funcRes1[curSite] = rdi.id(s_rdi_burstid).getBurstPassFail();\n\n double d_AVG, d_STD;\n ARRAY_D ad_jsubresults_VDD = rdi.id(s_rdi_burstid+\"V_VDD\").getWaveform(\"VDD\");\n ARRAY_D ad_jsubresults_VDDIO = rdi.id(s_rdi_burstid+\"V_VDDIO\").getWaveform(\"VDDIO\");\n\n \t DSP_MEAN(ad_jsubresults_VDD, &d_AVG, &d_STD);\n \t d_I_VDD_ACC_LPM[curSite] = d_AVG;\n FuncPrint(\"I_VDD_ACC_LPM\", d_I_VDD_ACC_LPM[curSite]);\n\n \t DSP_MEAN(ad_jsubresults_VDDIO, &d_AVG, &d_STD);\n \t d_I_VDDIO_ACC_LPM[curSite] = d_AVG;\n FuncPrint(\"I_VDDIO_ACC_LPM\", d_I_VDDIO_ACC_LPM[curSite]);\n \n FOR_EACH_SITE_END();\n\t }\n\n ON_FIRST_INVOCATION_END();\n\n TestLog(\"I_VDDIO_ACC_LPM\",\td_I_VDDIO_ACC_LPM[curSite]);\n TestLog(\"I_VDD_ACC_LPM\",\t\td_I_VDD_ACC_LPM[curSite]);\n i_funcRes[curSite] = i_funcRes0[curSite] && i_funcRes1[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T18_29_Current_Consumption_Test_Acc_LPM_V1\", T18_29_Current_Consumption_Test_Acc_LPM_V1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: \n# - Enable common bandgap duty cycle mode\n# - Disable temp measurement\n# - Measure the current consumption\n# - Measure the FOSC\n#############################################################################################################\ncmt('Version info: $Revision: bai430aa_rel/1 $ $Author: hmf1rt $ $Date: 2024/08/05 11:33:31 GMT $')\nwac('EXT_MODE', 0xc000) # Switch to USR register page\ndly(3e-3)\nwac('ACC_CONF', 0x0028) # Diable ACC\ndly(100e-6) \nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('OCP_MASK', 0x0800) # Set masking register\nwr('ANA_TRM_BG', 0x0800) # Enable common banggap duty cycle mode\nrac('ANA_TRM_BG', 0x0800, 0x0800) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('EXT_MODE', 0xc006) # Switch to FCU register page\nwac('FCU_TEST_CONF', 0x8000) # Disable temp sensor\nwac('EXT_MODE', 0xc000) # Switch to USR register page\nwac('ACC_CONF', 0xe22c) # Enable ACC in HPM; set AFS=8g; set ODR=1600; set BW=200\ndly(6e-3) \ngac('I_VDD_ACC_DC', 'VDD', i_range=300e-6, period=1e-3)\ngac('I_VDDIO_ACC_DC', 'VDDIO', i_range=10e-6)\nlog('I_VDD_ACC_DC')\nlog('I_VDDIO_ACC_DC')\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('DTB1',0x004c) # Route fosc_clk to INT1\ndly(100e-6)\ngaf('F_FOSC_DC', 'INT1', f_range=10e6)\nlog('F_FOSC_DC')\nwac('DTB1',0x0000) # Disable DTB1X\nwac('EXT_MODE', 0xc000) # Switch to USR register page\nwac('ACC_CONF', 0x0028) # Diable ACC\ndly(100e-6) \nwac('EXT_MODE', 0xc00d) # Switch to ANA register page\nwac('OCP_MASK', 0x0800) # Set masking register\nwr('ANA_TRM_BG', 0x0000) # Disable common banggap duty cycle mode\nrac('ANA_TRM_BG', 0x0000, 0x0800) # Check register setting\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\nwac('EXT_MODE', 0xc006) # Switch to FCU register page\nwac('FCU_TEST_CONF', 0x0000) # Enable temp sensor\nwac('EXT_MODE', 0xc000) # Switch to USR register page\nwac('ACC_CONF', 0xe24c) # Enable ACC in HPM; set AFS=32g; set ODR=1600; set BW=200\ndly(3e-3) \n", "output": "/*****************************************************\n * T18_32_Current_Consumption_Test_Acc_Duty_Cycle_BGP_R1, description file version Notfound, avc file version Notfound\n * First Editor : jsh5sgh\n * Code generated with autocoding tool V2.9.1, in TOI2 standard way by module write_standard\n * Change History:\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T18_32_Current_Consumption_Test_Acc_Duty_Cycle_BGP_R1: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 2;\n vector i_comment_line[i_split_count];\n\n static double SAMPLE_PERIOD_US;\n static double v_VDDIO, v_VDD;\n static double d_I_VDDIO_ACC_DC[xNSitES];\n static double d_I_VDD_ACC_DC[xNSitES];\n static double d_F_FOSC_DC[xNSitES];\n static int i_funcRes0[xNSitES], i_funcRes1[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(d_I_VDDIO_ACC_DC, 9.9, xNSitES);\n Func_Init_Var(d_I_VDD_ACC_DC, 9.9, xNSitES);\n Func_Init_Var(d_F_FOSC_DC, 9.9, xNSitES);\n v_VDDIO = Primary.getLevelSpec().getSpecValue(\"VDDIO\");\n v_VDD = Primary.getLevelSpec().getSpecValue(\"VDD\");\n\n //!\"CTmsg: cut pattern to 2 parts @ oriAVCvecline [2351]\n //!\"CTmsg: cut pattern to 2 parts @ binarypatline [2341]\n if (i_split_pat_flag)\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n }\n else\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n for(int i=0; i }\n valid comment[ 1] @ avcline 1955: {gac('I_VDD_ACC_DC', 'VDD', 0.0003, 0.001, True)}\n valid comment[ 1] @ avcline 1955: {gac('I_VDDIO_ACC_DC', 'VDDIO', 1e-05, 0.0001, True)}\n valid comment[ 1] @ avcline 1955: {log('I_VDD_ACC_DC', '', '', 0, 0)}\n valid comment[ 2] @ avcline 1956: {log('I_VDDIO_ACC_DC', '', '', 0, 0)}\n */\n string s_rdi_unit, s_rdi_burstid, s_rdi_dcid;\n SWITCH_VDD(s_rdi_unit, s_rdi_burstid, s_rdi_dcid, 0);\n RDI_UNIT_INIT(s_rdi_unit);\n\n RDI_BEGIN(mode);\n rdi.burstId(s_rdi_burstid);\n rdi.dc(s_rdi_dcid).label(s_splited_pat_name[0])\n\t\t\t\t\t\t.insertSub(i_comment_line[0][1]).pin(\"VDD\").vForce(v_VDD).iMeas().valueMode(TA::BADC).iRange(1 mA).average(256).measWait(1 ms) //I_VDD_STANDBY\n\t\t\t\t\t\t.insertSub(i_comment_line[0][1]).pin(\"VDDIO\").vForce(v_VDDIO).iMeas().valueMode(TA::BADC).iRange(10 uA).average(256).measWait(1 ms) //I_VDDIO_STANDBY\n\t\t\t\t\t\t.insertSub(i_comment_line[0][1]).pin(\"VDD\").vForce(v_VDD).iRange(40 mA)\n\t\t\t\t\t\t.insertSub(i_comment_line[0][1]).pin(\"VDDIO\").vForce(v_VDDIO).iRange(40 mA)\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(s_rdi_burstid).getBurstPassFail();\n ARRAY_D ad_jsubresults_VDD = rdi.id(s_rdi_dcid).getMultiValue(\"VDD\");\n ARRAY_D ad_jsubresults_VDDIO = rdi.id(s_rdi_dcid).getMultiValue(\"VDDIO\");\n \n d_I_VDD_ACC_DC[curSite] = ad_jsubresults_VDD[0];\n d_I_VDDIO_ACC_DC[curSite] = ad_jsubresults_VDDIO[0];\n FuncPrint(\"I_VDDIO_ACC_DC\",d_I_VDDIO_ACC_DC[curSite]);\n FuncPrint(\"I_VDD_ACC_DC\",d_I_VDD_ACC_DC[curSite]);\n FuncPrint(\"i_funcRes0\",i_funcRes0[curSite]);\n\n FOR_EACH_SITE_END();\n\n Primary.timing(SPECIFICATION(\"SPI_STD_INT1_FREQ_MEAS\"));\n FLUSH(TM::APRM);\n SAMPLE_PERIOD_US = Primary.getSpecification().getSpecValue(\"per_ns@INT1_Port\") * 1e-03;\n FuncPrint(\"SAMPLE_PERIOD_US\", SAMPLE_PERIOD_US);\n\n /* Ori key coments in subpat1 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 2351: {gaf('F_FOSC_DC', 'INT1', 1e+07, True)}\n valid comment[ 0] @ avcline 2351: {log('F_FOSC_DC', '', '', 0, 0)}\n valid comment[ 1] @ avcline 4481: {Test End: T18_32_Current_Consumption_Test_Acc_Duty_Cycle_BGP}\n */\n SWITCH_VDD(s_rdi_unit, s_rdi_burstid, s_rdi_dcid, 1);\n RDI_BEGIN(mode);\n rdi.burstId(s_rdi_burstid);\n rdi.port(\"Non_INT1_Port\").func().label(s_splited_pat_name[1]).startVec(0).stopVec(i_comment_line[1][0]).execute();\n rdi.portSync();\n rdi.port(\"INT1_Port\").digCap(s_rdi_dcid).pin(\"INT1\").samples(16384).bitPerWord(1).execute();\n rdi.portSync();\n rdi.port(\"Non_INT1_Port\").func().label(s_splited_pat_name[1]).startVec(i_comment_line[1][0]).execute();\n\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes1[curSite] = rdi.id(s_rdi_burstid).getBurstPassFail();\n ARRAY_I ai_F_FOSC_DC = rdi.id(s_rdi_dcid).getVector();\n d_F_FOSC_DC[curSite] = d_Func_Calculate_Freq_ByFFT(ai_F_FOSC_DC,SAMPLE_PERIOD_US)*1e6;\n FuncPrint(\"F_FOSC_DC\",d_F_FOSC_DC[curSite]);\n FuncPrint(\"i_funcRes1\",i_funcRes1[curSite]);\n FOR_EACH_SITE_END();\n\n\n }\n\n ON_FIRST_INVOCATION_END();\n\n TestLog(\"I_VDDIO_ACC_DC\",d_I_VDDIO_ACC_DC[curSite]);\n TestLog(\"I_VDD_ACC_DC\",d_I_VDD_ACC_DC[curSite]);\n TestLog(\"F_FOSC_DC\",d_F_FOSC_DC[curSite]);\n i_funcRes[curSite] = i_funcRes0[curSite] && i_funcRes1[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T18_32_Current_Consumption_Test_Acc_Duty_Cycle_BGP_R1\", T18_32_Current_Consumption_Test_Acc_Duty_Cycle_BGP_R1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "cmt('Version info: $Revision: bai430aa_rel/1 $ $Author: luz3sgh $ $Date: 2024/09/25 06:27:13 GMT $')\n\nwac('EXT_MODE', 0xc00f) # Switch to TST register page\nwac('TM_PIN', 0x0099) # Enable ANAIO1/2; TB1_INP on ANAIO1; TB2_INP on ANAIO2\nwac('OCP_MASK',0x0001) \nwr('FASTSO_CONF',0x0001) # fso_cn set to 1\nrac('FASTSO_CONF',0x0001,0x0001)\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n\n# DC_ICONCHIP_CLK is 6.7567MHz(1/148E-9)\n# V_INT2, V_ASDX both 1V\n\nwac('TM_ADDR', 0x0001) # Enable iconchip test mode\nsav('INT2', 1.0, i_comp=10e-6) # Set voltage V_ANAIO1 on ANAIO1\nsav('ASDX', 1.0, i_comp=10e-6) # Set voltage V_ANAIO2 on ANAIO2\ndly(100e-6)\ngac('I_CAP_NT33', 'INT2', i_range=10e-6)\ngac('I_CAP_N12', 'ASDX', i_range=10e-6)\n# Calculate C_CAP_NT33 = I_CAP_NT33 / (DC_ICONCHIP_CLK * V_INT2)\n# Calculate C_CAP_N12 = I_CAP_N12 / (DC_ICONCHIP_CLK * V_ASDX)\nlog('C_CAP_NT33')\nlog('C_CAP_N12')\n\nwac('TM_ADDR', 0x0101) # Enable iconchip test mode\ndly(100e-6)\ngac('I_CAP_MIM_P', 'INT2', i_range=10e-6)\ngac('I_CAP_MIM_N', 'ASDX', i_range=10e-6)\n# Calculate C_CAP_MIM_P = I_CAP_MIM_P / (DC_ICONCHIP_CLK * V_INT2)\n# Calculate C_CAP_MIM_N = I_CAP_MIM_N / (DC_ICONCHIP_CLK * V_ASDX)\nlog('C_CAP_MIM_P')\nlog('C_CAP_MIM_N')\n\nwac('TM_ADDR', 0x0201) # Enable iconchip test mode\ndly(100e-6)\ngac('I_CAP_MOM13_P', 'INT2', i_range=10e-6)\ngac('I_CAP_MOM13_N', 'ASDX', i_range=10e-6)\n# Calculate C_CAP_MOM13_P = I_CAP_MOM13_P / (DC_ICONCHIP_CLK * V_INT2)\n# Calculate C_CAP_MOM13_N = I_CAP_MOM13_N / (DC_ICONCHIP_CLK * V_ASDX)\nlog('C_CAP_MOM13_P')\nlog('C_CAP_MOM13_N')\n\n\nwac('TM_ADDR', 0x0301) # Enable iconchip test mode\ndly(100e-6)\ngac('I_CAP_MOM17_P', 'INT2', i_range=10e-6)\ngac('I_CAP_MOM17_N', 'ASDX', i_range=10e-6)\n# Calculate C_CAP_MOM17_P = I_CAP_MOM17_P / (DC_ICONCHIP_CLK * V_INT2)\n# Calculate C_CAP_MOM17_N = I_CAP_MOM17_N / (DC_ICONCHIP_CLK * V_ASDX)\nlog('C_CAP_MOM17_P')\nlog('C_CAP_MOM17_N')\n\n# Clean\nuav('INT2')\nuav('ASDX')\nwac('TM_ADDR', 0x0000) # Disable ATM\n\nwac('OCP_MASK',0x0001) \nwr('FASTSO_CONF',0x0000) # fso_cn set to 0\nrac('FASTSO_CONF',0x0000,0x0001)\nwr('OCP_MASK', 0x0000) # Reset masking register\nrac('OCP_MASK', 0xffff) # Check masking register reset\n\nwac('TM_PIN', 0x0000) # Reset pin config\n", "output": "/*****************************************************\n * T19_01_IConchip_Measurement_V5, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T19_01_IConchip_Measurement_V5: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static double d_I_CAP_MIM_N[xNSitES];\n static double d_I_CAP_MIM_P[xNSitES];\n static double d_I_CAP_MOM13_N[xNSitES];\n static double d_I_CAP_MOM13_P[xNSitES];\n static double d_I_CAP_MOM17_N[xNSitES];\n static double d_I_CAP_MOM17_P[xNSitES];\n static double d_I_CAP_N12[xNSitES];\n static double d_I_CAP_NT33[xNSitES];\n\n// static double C_CAP_MIM_N[xNSitES];\n// static double C_CAP_MIM_P[xNSitES];\n static double d_C_CAP_MOM13_N[xNSitES];\n static double d_C_CAP_MOM13_P[xNSitES];\n static double d_C_CAP_MOM17_N[xNSitES];\n static double d_C_CAP_MOM17_P[xNSitES];\n static double d_C_CAP_N12[xNSitES];\n static double d_C_CAP_NT33[xNSitES];\n static int i_funcRes0[xNSitES];\n\n double DC_ICONCHIP_CLK = 1/(148e-9);//1689190.0;\n double V_INT2 = 1.0;\n double V_ASDX = 1.0;\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(C_CAP_MIM_N, 9.9, xNSitES);\n Func_Init_Var(C_CAP_MIM_P, 9.9, xNSitES);\n Func_Init_Var(d_C_CAP_MOM13_N, 9.9, xNSitES);\n Func_Init_Var(d_C_CAP_MOM13_P, 9.9, xNSitES);\n Func_Init_Var(d_C_CAP_MOM17_N, 9.9, xNSitES);\n Func_Init_Var(d_C_CAP_MOM17_P, 9.9, xNSitES);\n Func_Init_Var(d_C_CAP_N12, 9.9, xNSitES);\n Func_Init_Var(d_C_CAP_NT33, 9.9, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T19_01_IConchip_Measurement}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 1] @ avcline 1162: {sav('INT2', 1, 2, 2e-06, False, False)}\n valid comment[ 1] @ avcline 1162: {sav('ASDX', 1, 2, 2e-06, False, False)}\n valid comment[ 2] @ avcline 1172: {gac('I_CAP_NT33', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 2] @ avcline 1172: {gac('I_CAP_N12', 'ASDX', 2e-06, 0.0001, True)}\n valid comment[ 2] @ avcline 1172: {log('C_CAP_NT33', '', '', 0, 0)}\n valid comment[ 3] @ avcline 1173: {log('C_CAP_N12', '', '', 0, 0)}\n valid comment[ 4] @ avcline 1376: {gac('I_CAP_MIM_P', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 4] @ avcline 1376: {gac('I_CAP_MIM_N', 'ASDX', 2e-06, 0.0001, True)}\n valid comment[ 4] @ avcline 1376: {log('C_CAP_MIM_P', '', '', 0, 0)}\n valid comment[ 5] @ avcline 1377: {log('C_CAP_MIM_N', '', '', 0, 0)}\n valid comment[ 6] @ avcline 1580: {gac('I_CAP_MOM13_P', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 6] @ avcline 1580: {gac('I_CAP_MOM13_N', 'ASDX', 2e-06, 0.0001, True)}\n valid comment[ 6] @ avcline 1580: {log('C_CAP_MOM13_P', '', '', 0, 0)}\n valid comment[ 7] @ avcline 1581: {log('C_CAP_MOM13_N', '', '', 0, 0)}\n valid comment[ 8] @ avcline 1784: {gac('I_CAP_MOM17_P', 'INT2', 2e-06, 0.0001, True)}\n valid comment[ 8] @ avcline 1784: {gac('I_CAP_MOM17_N', 'ASDX', 2e-06, 0.0001, True)}\n valid comment[ 8] @ avcline 1784: {log('C_CAP_MOM17_P', '', '', 0, 0)}\n valid comment[ 9] @ avcline 1785: {log('C_CAP_MOM17_N', '', '', 0, 0)}\n valid comment[ 10] @ avcline 1786: {uav('INT2', False)}\n valid comment[ 10] @ avcline 1786: {uav('ASDX', False)}\n valid comment[ 11] @ avcline 2746: {Test End: T19_01_IConchip_Measurement}\n */\n//\t\t rdi.enableOre(oreFlag);\n//\t\t rdi.oreFile(\"./ORE_Files/rdi_ore_T19_01_IConchip_Measurement.xml\");\n rdi.dc().pin(\"VDDIO\").vForce(1.8 V).execute();\n Primary.getLevelSpec().change(\"VDDIO\",1.8);\n FLUSH(TM::APRM);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.port(\"Non_INT1_ASCX_Port\").dc(\"dcid_0\").label(\"T19_01_IConchip_Measurement_V5_AVC5_PY5_Non_INT1_ASCX_Port\")\n .insertSub(i_comment_line[0][1]).pin(\"INT2,ASDX\").vForce(1.0 V)\n .insertSub(i_comment_line[0][2]).pin(\"INT2\").vForce(1.0 V).iMeas().iRange(10 uA).measWait(1 ms).average(32).valueMode(TA::BADC)\n .insertSub(i_comment_line[0][2]).pin(\"ASDX\").vForce(1.0 V).iMeas().iRange(10 uA).measWait(1 ms).average(32).valueMode(TA::BADC)\n// .insertSub(i_comment_line[0][2]).pin(\"INT2,ASDX\").vForce(0 V)\n//\n// .insertSub(i_comment_line[0][4]).pin(\"INT2,ASDX\").vForce(1 V)\n// .insertSub(i_comment_line[0][4]).wait(1 us)\n .insertSub(i_comment_line[0][4]).pin(\"INT2,ASDX\").vForce(1.0 V).iMeas().iRange(10 uA).measWait(1 ms).average(32).valueMode(TA::BADC)\n// .insertSub(i_comment_line[0][4]).pin(\"INT2,ASDX\").vForce(0 V)\n//\n// .insertSub(i_comment_line[0][6]).pin(\"INT2,ASDX\").vForce(1 V)\n// .insertSub(i_comment_line[0][6]).wait(1 us)\n .insertSub(i_comment_line[0][6]).pin(\"INT2,ASDX\").vForce(1.0 V).iMeas().iRange(10 uA).measWait(1 ms).average(32).valueMode(TA::BADC)\n// .insertSub(i_comment_line[0][6]).pin(\"INT2,ASDX\").vForce(0 V)\n//\n// .insertSub(i_comment_line[0][8]).pin(\"INT2,ASDX\").vForce(1 V)\n// .insertSub(i_comment_line[0][8]).wait(1 us)\n .insertSub(i_comment_line[0][8]).pin(\"INT2,ASDX\").vForce(1.0 V).iMeas().iRange(10 uA).measWait(1 ms).average(32).valueMode(TA::BADC)\n// .insertSub(i_comment_line[0][8]).pin(\"INT2,ASDX\").vForce(0 V)\n\n .insertSub(i_comment_line[0][10]).pin(\"INT2,ASDX\").relay(TA::ppmuRly_offALL)////{uav('INT2', False)}\n .execute();\n for (int i=0; i<200; i++)\n {\n \t rdi.port(\"ASCX_Port\").func().label(\"T19_01_IConchip_Measurement_V5_AVC5_PY5_ASCX_Port\").execute();\n }\n\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n ARRAY_D ad_jsubresults_ASDX; ad_jsubresults_ASDX.resize(4); ad_jsubresults_ASDX.init(-9.9);\n ARRAY_D ad_jsubresults_INT2; ad_jsubresults_INT2.resize(4); ad_jsubresults_INT2.init(-9.9);\n ad_jsubresults_ASDX = rdi.id(\"dcid_0\").getMultiValue(\"ASDX\");\n\n ad_jsubresults_INT2 = rdi.id(\"dcid_0\").getMultiValue(\"INT2\");\n\n for (int i=0; i<4; i++)\n {\n \t FuncPrint(\"ad_jsubresults_ASDX_\"+rdi.itos(i),ad_jsubresults_ASDX[i]*1e6);\n \t FuncPrint(\"ad_jsubresults_INT2_\"+rdi.itos(i),ad_jsubresults_INT2[i]*1e6);\n }\n\n d_I_CAP_MIM_N[curSite] = ad_jsubresults_ASDX[1];\n d_I_CAP_MIM_P[curSite] = ad_jsubresults_INT2[1];\n d_I_CAP_MOM13_N[curSite] = ad_jsubresults_ASDX[2];\n d_I_CAP_MOM13_P[curSite] = ad_jsubresults_INT2[2];\n d_I_CAP_MOM17_N[curSite] = ad_jsubresults_ASDX[3];\n d_I_CAP_MOM17_P[curSite] = ad_jsubresults_INT2[3];\n d_I_CAP_N12[curSite] = ad_jsubresults_ASDX[0];\n d_I_CAP_NT33[curSite] = ad_jsubresults_INT2[0];\n\n d_C_CAP_NT33[curSite] = d_I_CAP_NT33[curSite] / (DC_ICONCHIP_CLK * V_INT2);\n d_C_CAP_N12[curSite] = d_I_CAP_N12[curSite] / (DC_ICONCHIP_CLK * V_ASDX);\n\n C_CAP_MIM_P[curSite] = d_I_CAP_MIM_P[curSite] / (DC_ICONCHIP_CLK * V_INT2);\n C_CAP_MIM_N[curSite] = d_I_CAP_MIM_N[curSite] / (DC_ICONCHIP_CLK * V_ASDX);\n\n d_C_CAP_MOM13_P[curSite] = d_I_CAP_MOM13_P[curSite] / (DC_ICONCHIP_CLK * V_INT2);\n d_C_CAP_MOM13_N[curSite] = d_I_CAP_MOM13_N[curSite] / (DC_ICONCHIP_CLK * V_ASDX);\n\n d_C_CAP_MOM17_P[curSite] = d_I_CAP_MOM17_P[curSite] / (DC_ICONCHIP_CLK * V_INT2);\n d_C_CAP_MOM17_N[curSite] = d_I_CAP_MOM17_N[curSite] / (DC_ICONCHIP_CLK * V_ASDX);\n\n FuncPrint(\"d_I_CAP_NT33\",d_I_CAP_NT33[curSite]);\n FuncPrint(\"d_I_CAP_N12\",d_I_CAP_N12[curSite]);\n FuncPrint(\"d_I_CAP_MIM_P\",d_I_CAP_MIM_P[curSite]);\n FuncPrint(\"d_I_CAP_MIM_N\",d_I_CAP_MIM_N[curSite]);\n FuncPrint(\"d_I_CAP_MOM13_P\",d_I_CAP_MOM13_P[curSite]);\n FuncPrint(\"d_I_CAP_MOM13_N\",d_I_CAP_MOM13_N[curSite]);\n FuncPrint(\"d_I_CAP_MOM17_P\",d_I_CAP_MOM17_P[curSite]);\n FuncPrint(\"d_I_CAP_MOM17_N\",d_I_CAP_MOM17_N[curSite]);\n\n FuncPrint(\"d_C_CAP_NT33\",d_C_CAP_NT33[curSite]);\n FuncPrint(\"d_C_CAP_N12\",d_C_CAP_N12[curSite]);\n FuncPrint(\"C_CAP_MIM_P(pf)\",C_CAP_MIM_P[curSite]*1e15);\n FuncPrint(\"C_CAP_MIM_N(pf)\",C_CAP_MIM_N[curSite]*1e15);\n FuncPrint(\"d_C_CAP_MOM13_P\",d_C_CAP_MOM13_P[curSite]);\n FuncPrint(\"d_C_CAP_MOM13_N\",d_C_CAP_MOM13_N[curSite]);\n FuncPrint(\"d_C_CAP_MOM17_P\",d_C_CAP_MOM17_P[curSite]);\n FuncPrint(\"d_C_CAP_MOM17_N\",d_C_CAP_MOM17_N[curSite]);\n\n FOR_EACH_SITE_END();\n\n rdi.dc().pin(\"VDDIO\").vForce(3 V).execute();\n Primary.getLevelSpec().change(\"VDDIO\",3);\n FLUSH(TM::APRM);\n\n ON_FIRST_INVOCATION_END();\n\n TestLog(\"C_CAP_MIM_N\",C_CAP_MIM_N[curSite]);\n TestLog(\"C_CAP_MIM_P\",C_CAP_MIM_P[curSite]);\n TestLog(\"C_CAP_MOM13_N\",d_C_CAP_MOM13_N[curSite]);\n TestLog(\"C_CAP_MOM13_P\",d_C_CAP_MOM13_P[curSite]);\n TestLog(\"C_CAP_MOM17_N\",d_C_CAP_MOM17_N[curSite]);\n TestLog(\"C_CAP_MOM17_P\",d_C_CAP_MOM17_P[curSite]);\n TestLog(\"C_CAP_N12\",d_C_CAP_N12[curSite]);\n TestLog(\"C_CAP_NT33\",d_C_CAP_NT33[curSite]);\n i_funcRes[curSite] = i_funcRes0[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T19_01_IConchip_Measurement_V5\", T19_01_IConchip_Measurement_V5);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "######################################################################################################################\n# description: Write MIMcap measurement to dark OTP\n# Step1: Calcualtion of MIMcap measurement into integer value\n# Step2: Result programmed in dark OTP regID 0xF1\n# - Bits 0..9 used to store the angular 0deg MIMcap measurement with int unsigned in fF (0..1023)\n# - Bits 10..15 used to store the angular 90deg MIMcap measurement deviation from 0deg with int signed in fF (-32..31)\n# - Recovery of 0deg MIMcap measurement: \n# C_CAP_MIM_0 = darkOTPregID(F1) & 0x03ff\n# - Recovery of 90deg MIMcap measurement: \n# C_CAP_MIM_90 = (darkOTPregID(F1) & 0x03ff) + cus(darkOTPregID(F1) >> 10)\n######################################################################################################################\ncmt('Version info: $Revision: 2 $ $Author: luz3sgh $ $Date: 2024/05/28 01:49:22 GMT $')\n# Convert MIMcap measurements to integer values\ncalc('C_CAP_MIM_P', 504.3) # Assign placeholder value for simulation, REPLACE with measurement value\ncalc('C_CAP_MIM_N', 493.1) # Assign placeholder value for simulation, REPLACE with measurement value\ncmt('Get result parameter C_CAP_MIM_P from test item T19.01 and round to nearest integer')\ncalc('NU_CAP_MIM_P', 'C_CAP_MIM_P', 'round') # Get C_CAP_MIM_P from test item T19.01\ncmt('Get result parameter C_CAP_MIM_N from test item T19.01 and round to nearest integer')\ncalc('NU_CAP_MIM_N', 'C_CAP_MIM_N', 'round') # Get C_CAP_MIM_N from test item T19.01\ndly(74e-9)\ncalc('NS_CAP_MIM_DELTA', 'NU_CAP_MIM_N', '-', 'NU_CAP_MIM_P') # Calculate delta between MIM_P and MIM_N\ncmt('This test item is a functional fail if NS_CAP_MIM_DELTA > 31 or NS_CAP_MIM_DELTA < -32')\ncalc('NU_CAP_MIM_DELTA', 'NS_CAP_MIM_DELTA', 'csu', 6) # Convert 6-bit signed to unsigend\ndly(74e-9)\ncalc('NU_CAP_MIM_DELTA_LS', 'NU_CAP_MIM_DELTA', '<<', 10) # Left shift MIM_DELTA to bit 10\ncalc('OTP_MIM_DATA', 'NU_CAP_MIM_DELTA_LS', '+', 'NU_CAP_MIM_P') # Calc OTP program data\n# Program data to OTP\nwac('EXT_MODE', 0xc00d) # Switch to PMU register page\nwcb('nvmotp_power_en',0x1) # Request OTP power\ndly(300e-6) \nwac('EXT_MODE', 0xc00f) # Switch to OTPCTRL register page\nwac('OTP_PROG_EN', 0x0002) # Enable OTP program\nwcb('vddp_sw', 0x1) # Connect VDDP to VDD\nsav('VDD', 3.6, v_range=4.0, i_comp=40e-3)\ndly(1e-3)\nwri('OTP_DATA', 'OTP_MIM_DATA') # Write measurement result to OTP data register\nrac('OTP_STATUS', 0x0001) # Check OTP ready\nwr('OTP_CMD', 0x0005) # Trigger OTP data program\ndly(200e-6) # OTP spec, pgm speed 10us per bit\nwac('OTP_DATA',0xf1) # Set regID for dark OTP \nrac('OTP_STATUS', 0x0001) # Check OTP ready\nwr('OTP_CMD', 0x0006) # Trigger OTP reg_id program\ndly(200e-6) \nrac('OTP_STATUS', 0x0001) # Check OTP ready\nsav('VDD', 1.8, v_range=4.0, i_comp=40e-3)\ndly(1e-3)\nwac('OTP_PROG_EN', 0x0000) # Disable OTP program\nwcb('vddp_sw', 0x0) # Connect VDDP to VDDD_DC\nwac('OTP_DATA', 0x0000) # Reset OTP data register\n# Read data from OTP \nwac('BOOT_RANGE', 0xf1f1) # Set register ID for dark OTP load\nrac('BOOT_STATUS', 0x0001) # Check boot controller ready and error bits\nwr('BOOT_CMD', 0x0001) # Trigger OTP load\ndly(1.2e-3)\nras('OTP_MIM_DATA_RD', 'BOOT_LAST_DATA') # Read and save OTP data\ncmt('This test item is a functional fail if OTP_MIM_DATA_RD != OTP_MIM_DATA')\n# Clean-up \nwac('BOOT_RANGE', 0x0000)\nwac('EXT_MODE', 0xc00d) # Switch to PMU register page\nwcb('nvmotp_power_en',0x0) # Disable OTP power\ndly(100e-6)\n", "output": "/*****************************************************\n * T19_02_IConchip_storage_V2, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T19_02_IConchip_storage_V2: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 3;\n vector i_comment_line[i_split_count];\n\n static int i_OTP_MIM_DATA_RD[xNSitES];\n ARRAY_I aI_Captured_2;\n static int i_OTP_MIM_DATA[xNSitES];\n static int i_WRITE_BACK[xNSitES];\n static int i_vec_Num1[32] = {0};\n static int i_funcRes0[xNSitES], i_funcRes1[xNSitES], i_funcRes2[xNSitES];\n\n static int i_funcComp0[xNSitES],i_funcRD[xNSitES];\n// static double d_C_CAP_MIM_N[xNSitES];\n// static double d_C_CAP_MIM_P[xNSitES];\n static int i_NU_CAP_MIM_N[xNSitES];\n static int i_NU_CAP_MIM_P[xNSitES];\n static int i_NS_CAP_MIM_DELTA[xNSitES];\n static int i_NU_CAP_MIM_DELTA[xNSitES];\n static int i_NU_CAP_MIM_DELTA_LS[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(i_OTP_MIM_DATA_RD, 9, xNSitES);\n Func_Init_Var(i_OTP_MIM_DATA, 9, xNSitES);\n \n //!\"CTmsg: cut pattern to 3 parts @ oriAVCvecline [1305, 2091]\n //!\"CTmsg: cut pattern to 3 parts @ binarypatline [1295, 2081]\n if (i_split_pat_flag)\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n }\n else\n {\n split_pattern(s_label_name,\"cut_here\",\"\",i_split_pat_flag,s_splited_pat_name);\n for(int i=0; i }\n valid comment[ 0] @ avcline 10: {calc('C_CAP_MIM_P', '504.3', '', '')}\n valid comment[ 0] @ avcline 10: {calc('C_CAP_MIM_N', '493.1', '', '')}\n valid comment[ 0] @ avcline 10: {cmt: Get result parameter C_CAP_MIM_P from test item T19.01 and round to nearest integer}\n valid comment[ 0] @ avcline 10: {calc('NU_CAP_MIM_P', 'C_CAP_MIM_P', 'round', '')}\n valid comment[ 0] @ avcline 10: {cmt: Get result parameter C_CAP_MIM_N from test item T19.01 and round to nearest integer}\n valid comment[ 0] @ avcline 10: {calc('NU_CAP_MIM_N', 'C_CAP_MIM_N', 'round', '')}\n valid comment[ 1] @ avcline 11: {calc('NS_CAP_MIM_DELTA', 'NU_CAP_MIM_N', '-', 'NU_CAP_MIM_P')}\n valid comment[ 1] @ avcline 11: {cmt: This test item is a functional fail if NS_CAP_MIM_DELTA > 31 or NS_CAP_MIM_DELTA < -32}\n valid comment[ 1] @ avcline 11: {calc('NU_CAP_MIM_DELTA', 'NS_CAP_MIM_DELTA', 'csu', '6')}\n valid comment[ 2] @ avcline 12: {calc('NU_CAP_MIM_DELTA_LS', 'NU_CAP_MIM_DELTA', '<<', '10')}\n valid comment[ 2] @ avcline 12: {calc('OTP_MIM_DATA', 'NU_CAP_MIM_DELTA_LS', '+', 'NU_CAP_MIM_P')}\n valid comment[ 3] @ avcline 1297: {sav('VDD', 3.6, 4, 0.04, False, False)}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.dc(\"dcid_0\").label(s_splited_pat_name[0])\n .insertSub(i_comment_line[0][3]).pin(\"VDD\").vForce(3.6 V).iRange(40 mA)//{sav('VDD', 3.6, 4, 0.04, False, False)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n\n\n i_NU_CAP_MIM_P[curSite] = int(round((C_CAP_MIM_P[curSite]) * 1e15));\n i_NU_CAP_MIM_N[curSite] = int(round((C_CAP_MIM_N[curSite]) * 1e15));\n\n\t\t\t i_NS_CAP_MIM_DELTA[curSite] = i_NU_CAP_MIM_N[curSite] - i_NU_CAP_MIM_P[curSite];\n\t\t\t if(i_NS_CAP_MIM_DELTA[curSite]>31 || i_NS_CAP_MIM_DELTA[curSite]<-32)\n\t\t\t {\n\t\t\t\t i_funcComp0[curSite] = 0;\n\t\t\t }\n\t\t\t else\n\t\t\t {\n\t\t\t\t i_funcComp0[curSite] = 1;\n\t\t\t }\n\t\t\t i_NU_CAP_MIM_DELTA[curSite] = i_Func_Signed_To_Unsigned(i_NS_CAP_MIM_DELTA[curSite], 6);\n\t\t\t i_NU_CAP_MIM_DELTA_LS[curSite] = i_NU_CAP_MIM_DELTA[curSite] << 10;\n\t\t\t i_OTP_MIM_DATA[curSite] = i_NU_CAP_MIM_DELTA_LS[curSite] + i_NU_CAP_MIM_P[curSite];\n\n FuncPrint(\"C_CAP_MIM_P(pf)\",C_CAP_MIM_P[curSite]*1e15);\n FuncPrint(\"C_CAP_MIM_N(pf)\",C_CAP_MIM_N[curSite]*1e15);\n\t\t\t FuncPrint(\"i_NU_CAP_MIM_P\", i_NU_CAP_MIM_P[curSite]);\n\t\t\t FuncPrint(\"i_NU_CAP_MIM_N\", i_NU_CAP_MIM_N[curSite]);\n\t\t\t FuncPrint(\"i_NS_CAP_MIM_DELTA\", i_NS_CAP_MIM_DELTA[curSite]);\n\t\t\t FuncPrint(\"i_NU_CAP_MIM_DELTA\", i_NU_CAP_MIM_DELTA[curSite]);\n\t\t\t FuncPrint(\"i_NU_CAP_MIM_DELTA_LS\", i_NU_CAP_MIM_DELTA_LS[curSite]);\n\t\t\t FuncPrint(\"OTP_MIM_DATA\", i_OTP_MIM_DATA[curSite]);\n\n\n\n FOR_EACH_SITE_END();\n\n\n /* Ori key coments in subpat1 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 1305: {wri('OTP_DATA', 'OTP_MIM_DATA')}\n */\n static int i_vec_iposition1[32] = {\n 31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,\n 48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63\n };\n for (int i = 0; i < 32; i++)\n {\n i_vec_Num1[i] = i_vec_iposition1[i];\n }\n FOR_EACH_SITE_BEGIN();\n i_WRITE_BACK[curSite] = Switch_High_Low_Bits_16Bits(i_OTP_MIM_DATA[curSite]);\n Func_Vector_Dynamic_Write(s_splited_pat_name[1], \"SDX\", i_vec_Num1, 32, i_WRITE_BACK[curSite], 0, 2); //Notes. TEI check per project\n FuncPrint(\"i_WRITE_BACK\", i_WRITE_BACK[curSite]);\n FOR_EACH_SITE_END();\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id1\");\n rdi.func().label(s_splited_pat_name[1]).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes1[curSite] = rdi.id(\"burst_id1\").getBurstPassFail();\n FuncPrint(\"OTP_MIM_DATA\", i_OTP_MIM_DATA[curSite]);\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n\n /* Ori key coments in subpat2 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 2091: {sav('VDD', 1.8, 4, 0.04, False, False)}\n valid comment[ 1] @ avcline 3224: {ras('OTP_MIM_DATA_RD', 'BOOT_LAST_DATA')}\n valid comment[ 2] @ avcline 3337: {cmt: This test item is a functional fail if OTP_MIM_DATA_RD != OTP_MIM_DATA}\n valid comment[ 3] @ avcline 4081: {Test End: T19_02_IConchip_storage}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id2\");\n rdi.digCap(\"digcapid_2\").vecVarOnly().pin(\"SDO\").capMode(TA::SER).bitPerWord(16).samples(1*16).execute();\n rdi.dc(\"dcid_2\").label(s_splited_pat_name[2])\n .insertSub(i_comment_line[2][0]).pin(\"VDD\").vForce(1.8 V).iRange(40 mA)//{sav('VDD', 1.8, 4, 0.04, False, False)}\n .execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes2[curSite] = rdi.id(\"burst_id2\").getBurstPassFail();\n aI_Captured_2 = rdi.id(\"digcapid_2\").getVector(\"SDO\");\n i_funcRes2[curSite] = rdi.id(\"burst_id2\").getBurstPassFail();\n aI_Captured_2[0] = Switch_High_Low_Bits_16Bits(aI_Captured_2[0]);\n i_OTP_MIM_DATA_RD[curSite] = aI_Captured_2[0];\n FuncPrint(\"OTP_MIM_DATA_RD\",i_OTP_MIM_DATA_RD[curSite]);\n\n if(i_OTP_MIM_DATA_RD[curSite] != i_OTP_MIM_DATA[curSite])\n \t\t {\n \t\t\t i_funcRD[curSite] = 0;\n \t\t }\n \t\t else\n \t\t {\n \t\t\t i_funcRD[curSite] = 1;\n \t\t }\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n\n }\n\n ON_FIRST_INVOCATION_END();\n\n// TestLog(\"OTP_MIM_DATA_RD\",i_OTP_MIM_DATA_RD[curSite]);\n// TestLog(\"OTP_MIM_DATA\", i_OTP_MIM_DATA[curSite]);\n// i_funcRes[curSite] = i_funcRes0[curSite] && i_funcRes1[curSite] && i_funcRes2[curSite];\n i_funcRes[curSite] = i_funcRes0[curSite] && i_funcRes1[curSite] && i_funcRes2[curSite] && i_funcComp0[curSite] && i_funcRD[curSite];\n\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T19_02_IConchip_storage_V2\", T19_02_IConchip_storage_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "from test_sub_functions import *\n\ncmt('Version info: $Revision: 2 $ $Author: hmf1rt $ $Date: 2024/05/27 16:01:07 GMT $')\n\n# Note: This test item expects an uprogrammed OTP (otp_idx=0)\n\notp = [\n#| name |\n#+--------------------------+\n 'TEMP_TRM_OFF_DGAIN' , # n = 0\n 'ANA_TRM_BG' , # n = 1\n 'ANA_TRM_PMU' , # n = 2\n 'ANA_TRM_OSC' , # n = 3\n 'ANA_TRM_RES_PROG0' , # n = 4\n 'ANA_TRM_RES_PROG1' , # n = 5\n 'ANA_TRM_RES_PROG2' , # n = 6\n 'ANA_TRM_CAP_PROG0' , # n = 7\n 'ANA_TRM_CAP_PROG_DRV' , # n = 8\n 'IO_PAD_TRM' # n = 9\n]\n\n# Read data from shadow\nfor n in range (0, len(otp), 1):\n wac('EXT_MODE', 0xc000 + get_reg_page(otp[n])) # Switch to register page\n ras('OTP_PROG_{}'.format(n), otp[n]) # Save register content\n# Program data to OTP\nwac('EXT_MODE', 0xc00d) # Switch to PMU register page\nwcb('nvmotp_power_en',0x1) # Request OTP power\ndly(300e-6) \nwac('EXT_MODE', 0xc00f) # Switch to OTPCTRL register page\nrac('OTP_IDX', 0x0000) # Check for an un-programmed OTP\nwac('OTP_PROG_EN', 0x0002) # Enable OTP program\nwcb('vddp_sw', 0x1) # Connect VDDP to VDD\nsav('VDD', 3.6, v_range=4.0, i_comp=40e-3)\ndly(1e-3)\nfor n in range (0, len(otp), 1):\n wri('OTP_DATA', 'OTP_PROG_{}'.format(n)) # Write register content to OTP data reg\n rac('OTP_STATUS', 0x0001) # Check OTP ready\n wr('OTP_CMD', 0x0005) # Trigger OTP data program\n dly(200e-6) \n wac('OTP_DATA', get_otp_regid(otp[n])) # Write register ID to OTP data reg \n rac('OTP_STATUS', 0x0001) # Check OTP ready\n wr('OTP_CMD', 0x0006) # Trigger OTP reg_id program\n dly(200e-6) \n rac('OTP_STATUS', 0x0001) # Check OTP ready\nsav('VDD', 1.8, v_range=4.0, i_comp=40e-3)\ndly(1e-3)\nwac('OTP_PROG_EN', 0x0000) # Disable OTP program\nwcb('vddp_sw', 0x0) # Connect VDDP to VDDD_DC\nwac('OTP_DATA', 0x0000) # Reset OTP data register\n# Boot OTP to shadow \nwac('EXT_MODE', 0xc00f) # Switch to BOOT register page\nwac('BOOT_RANGE', 0xff00) # Set start and stop range to max\nrac('BOOT_STATUS', 0x0001) # Check boot commmand status\nwr('BOOT_CMD', 0x0001) # Trigger boot from reg_id 1-254\ndly(1.2e-3) \nrac('BOOT_STATUS', 0x0001) # Check boot commmand status\n# Compare prog and read data \nfor n in range (0, len(otp), 1):\n wac('EXT_MODE', 0xc000 + get_reg_page(otp[n])) # Switch to register page\n ras('SHDW_RD_{}'.format(n), otp[n]) # Save register content\n cmt('This test item is a functiona fail if SHDW_RD_{} != OTP_PROG_{}'.format(n,n))\n# Clean-up \nwac('EXT_MODE', 0xc00f) # Switch to OTPCTRL register page\nras('OTP_PROG_STOP_INDEX', 'OTP_IDX') # Read and save OTP index\nlog('OTP_PROG_STOP_INDEX')\nwac('EXT_MODE', 0xc00d) # Switch to PMU register page\nwcb('nvmotp_power_en',0x0) # Disable OTP power\ndly(100e-6)\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T20_01_OTP_program_P1_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n// 'TEMP_TRM_OFF_DGAIN' , # n = 0\n// 'ANA_TRM_BG' , # n = 1\n// 'ANA_TRM_PMU' , # n = 2\n// 'ANA_TRM_OSC' , # n = 3\n// 'ANA_TRM_RES_PROG0' , # n = 4\n// 'ANA_TRM_RES_PROG1' , # n = 5\n// 'ANA_TRM_RES_PROG2' , # n = 6\n// 'ANA_TRM_CAP_PROG0' , # n = 7\n// 'ANA_TRM_CAP_PROG_DRV' , # n = 8\n// 'IO_PAD_TRM' # n = 9\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n INT split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &split_pat_flag);\n vector s_splited_pat_name;\n const int split_count = 12; // Alarm:: split_count need manual confirm.\n s_splited_pat_name.resize(split_count);\n vector i_comment_line[split_count];\n const int Wri_Bit_Length = 33;\n const int Wri_Bit_Position = 31;\n\n static int OTP_PROG[10][xNSitES];\n ARRAY_I OTP_PROG_rtv[10];\n static int SHDW_RD[10][xNSitES];\n static int OTP_PROG_STOP_INDEX[xNSitES];\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n GET_TESTSUITE_NAME(test_name);\n for (int i = 0; i < 10; i++)\n {\n \t OTP_PROG_rtv[i].resize(xNSitES);\n }\n\n if (split_pat_flag)\n {\n split_pattern(s_label_name,\"wri\",split_pat_flag,s_splited_pat_name);\n }\n else\n {\n for (int i = 0; i {0x00..0x19}\n# \n# Determine 2nd character of LotID using alphanumeric coding format\n# Store 2nd character of LotID in variable RUN_TYPE.5:0\n# using {A..Z} --> {0x00..0x19} and {0..9} --> {0x1A..0x23}\n# \n# Determine 3rd, 4th, 5th and 6th character of LotID using alphanumeric coding format\n# Store LotID characters 3-6 in variables LOTID3.5:0, LOTID4.5:0, LOTID5.5:0, LOTID6.5:0\n# using {A..Z} --> {0x00..0x19} and {0..9} --> {0x1A..0x23}\n# Calculate LOT_ID_SER.20:0 = LOTID3 * 36**3 + LOTID4 * 36**2 + LOTID5 * 36 + LOTID6\n# \n# Determine WLT program version number using unsigned binary notation\n# Store WLT program version in variable WLT_PP.7:0 in range {0..255}\n# Note: Increase test program version number with each WLT TP release\n# \n# Determine FT program version number using unsigned binary notation\n# Store FT program version in variable FT_PP.7:0 in range {0..255}\n# Note: Increase test program version number with each FT TP release\n#\n# Calculate ID0 = LOT_ID_SER.15:0\n# Calculate ID1 = RUN_TYPE.5:0 * 1024 + WAFERID.4:0 * 32 + LOT_ID_SER.20:16\n# Calculate ID2 = YCOORD.7:0 * 256 + XCOORD.7:0\n# Calculate ID3 = PROD_ID.4:0 * 256\n# Calculate ID4 = WLT_PP.7:0 * 256 + FT_PP.7:0\n\n# Initialize variables\ncalc('ID0', 0x1) # Assign ID0 variable, replace placeholder 0x1 with calculated value\ncalc('ID1', 0x2) # Assign ID1 variable, replace placeholder 0x2 with calculated value\ncalc('ID2', 0x3) # Assign ID2 variable, replace placeholder 0x3 with calculated value\ncalc('ID3', 0x4) # Assign ID3 variable, replace placeholder 0x4 with calculated value\ncalc('ID4', 0x5) # Assign ID4 variable, replace placeholder 0x5 with calculated value\n\n# Program data to OTP\nwac('EXT_MODE', 0xc00d) # Switch to PMU register page\nwcb('nvmotp_power_en',0x1) # Request OTP power\ndly(300e-6) \nwac('EXT_MODE', 0xc00f) # Switch to OTPCTRL register page\nwac('OTP_PROG_EN', 0x0002) # Enable OTP program\nwcb('vddp_sw', 0x1) # Connect VDDP to VDD\nsav('VDD', 3.6, v_range=4.0, i_comp=40e-3)\ndly(1e-3)\nfor n in range (0, 5, 1):\n wri('OTP_DATA', 'ID{}'.format(n)) # Write calculated value to OTP data reg\n rac('OTP_STATUS', 0x0001) # Check OTP ready\n wr('OTP_CMD', 0x0005) # Trigger OTP data program\n dly(200e-6) \n wac('OTP_DATA', 0x00d0 + n) # Write register ID to OTP data reg \n rac('OTP_STATUS', 0x0001) # Check OTP ready\n wr('OTP_CMD', 0x0006) # Trigger OTP reg_id program\n dly(200e-6) \n rac('OTP_STATUS', 0x0001) # Check OTP ready\nsav('VDD', 1.8, v_range=4.0, i_comp=40e-3)\ndly(1e-3)\nwac('OTP_PROG_EN', 0x0000) # Disable OTP program\nwcb('vddp_sw', 0x0) # Connect VDDP to VDDD_DC\nwac('OTP_DATA', 0x0000) # Reset OTP data register\n# Read data from OTP\nwac('EXT_MODE', 0xc00f) # Switch to BOOT register page\nfor n in range (0, 5, 1):\n wac('BOOT_RANGE', 0xd0d0 + 256*n + n) # Set register ID for dark OTP load\n rac('BOOT_STATUS', 0x0001) # Check boot controller ready and error bits\n wr('BOOT_CMD', 0x0001) # Trigger OTP load\n dly(1.2e-3)\n ras('ID{}_RD'.format(n), 'BOOT_LAST_DATA') # Read and save OTP data\n cmt('This test item is a functional fail if ID{}_RD != ID{}'.format(n,n))\n# Clean-up\nwac('BOOT_RANGE', 0x0000) # Reset boot range register\nwac('EXT_MODE', 0xc00d) # Switch to PMU register page\nwcb('nvmotp_power_en',0x0) # Disable OTP power\ndly(100e-6)\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T20_20_write_serial_ID_V1: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n INT split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &split_pat_flag);\n vector s_splited_pat_name;\n const int split_count = 7; // Alarm:: split_count need manual confirm.\n s_splited_pat_name.resize(split_count);\n vector i_comment_line[split_count];\n const int Wri_Bit_Length = 33;\n const int Wri_Bit_Position = 31;\n\n DOUBLE WLT_PGM_Version;\n\n static int SERIAL_ID[5][xNSitES], SERIAL_ID_RD[5][xNSitES];\n ARRAY_LL SERIAL_ID0_rtv, SERIAL_ID1_rtv, SERIAL_ID2_rtv, SERIAL_ID3_rtv, SERIAL_ID4_rtv;\n static int WAFERID, PROD_ID, RUN_TYPE, LOTID3, LOTID4, LOTID5, LOTID6, WLT_PP, LOT_ID_SER, FT_PP;\n // Auto_Code_Variable_define\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n GET_TESTSUITE_NAME(test_name);\n \t SERIAL_ID0_rtv.resize(xNSitES);\n \t SERIAL_ID1_rtv.resize(xNSitES);\n \t SERIAL_ID2_rtv.resize(xNSitES);\n \t SERIAL_ID3_rtv.resize(xNSitES);\n \t SERIAL_ID4_rtv.resize(xNSitES);\n\n if (split_pat_flag)\n {\n split_pattern(s_label_name,\"wri\",split_pat_flag,s_splited_pat_name);\n }\n else\n {\n for (int i = 0; i>16)&0x1F);\n \t SERIAL_ID[2][CURRENT_SITE_NUMBER()-1] = (YCOORD[CURRENT_SITE_NUMBER()-1]&0xFF) * 256 + (XCOORD[CURRENT_SITE_NUMBER()-1]&0xFF);\n \t SERIAL_ID[3][CURRENT_SITE_NUMBER()-1] = (PROD_ID&0x1F) * 256;\n \t SERIAL_ID[4][CURRENT_SITE_NUMBER()-1]\t= (WLT_PP&0xFF)*256 + (FT_PP&0xFF);\n \t cout << \"Site[\" << CURRENT_SITE_NUMBER() << \"] \" << \"XCOORD=\" << XCOORD[CURRENT_SITE_NUMBER()-1] << \" || YCOORD=\" << YCOORD[CURRENT_SITE_NUMBER()-1] << endl;\n\n \t SERIAL_ID0_rtv[CURRENT_SITE_NUMBER()-1] = extend_Pmode_Herschel(SERIAL_ID[0][CURRENT_SITE_NUMBER()-1], 2);\n \t SERIAL_ID1_rtv[CURRENT_SITE_NUMBER()-1] = extend_Pmode_Herschel(SERIAL_ID[1][CURRENT_SITE_NUMBER()-1], 2);\n \t SERIAL_ID2_rtv[CURRENT_SITE_NUMBER()-1] = extend_Pmode_Herschel(SERIAL_ID[2][CURRENT_SITE_NUMBER()-1], 2);\n \t SERIAL_ID3_rtv[CURRENT_SITE_NUMBER()-1] = extend_Pmode_Herschel(SERIAL_ID[3][CURRENT_SITE_NUMBER()-1], 2);\n \t SERIAL_ID4_rtv[CURRENT_SITE_NUMBER()-1] = extend_Pmode_Herschel(SERIAL_ID[4][CURRENT_SITE_NUMBER()-1], 2);\n\n \t FuncPrint(\"WAFERID\", WAFERID);\n \t FuncPrint(\"PROD_ID\", PROD_ID);\n \t FuncPrint(\"RUN_TYPE\", RUN_TYPE);\n \t FuncPrint(\"LOTID3\", LOTID3);\n \t FuncPrint(\"LOTID4\", LOTID4);\n \t FuncPrint(\"LOTID5\", LOTID5);\n \t FuncPrint(\"LOTID6\", LOTID6);\n \t FuncPrint(\"LOT_ID_SER\", LOT_ID_SER);\n \t FuncPrint(\"WLT_PP\", WLT_PP);\n \t FuncPrint(\"FT_PP\", FT_PP);\n\n \t FuncPrint(\"SERIAL_ID[0]\", SERIAL_ID[0][CURRENT_SITE_NUMBER()-1]);\n \t FuncPrint(\"SERIAL_ID[1]\", SERIAL_ID[1][CURRENT_SITE_NUMBER()-1]);\n \t FuncPrint(\"SERIAL_ID[2]\", SERIAL_ID[2][CURRENT_SITE_NUMBER()-1]);\n \t FuncPrint(\"SERIAL_ID[3]\", SERIAL_ID[3][CURRENT_SITE_NUMBER()-1]);\n \t FuncPrint(\"SERIAL_ID[4]\", SERIAL_ID[4][CURRENT_SITE_NUMBER()-1]);\n\n \t FuncPrint(\"SERIAL_ID0_rtv\", SERIAL_ID0_rtv[CURRENT_SITE_NUMBER()-1]);\n \t FuncPrint(\"SERIAL_ID1_rtv\", SERIAL_ID1_rtv[CURRENT_SITE_NUMBER()-1]);\n \t FuncPrint(\"SERIAL_ID2_rtv\", SERIAL_ID2_rtv[CURRENT_SITE_NUMBER()-1]);\n \t FuncPrint(\"SERIAL_ID3_rtv\", SERIAL_ID3_rtv[CURRENT_SITE_NUMBER()-1]);\n \t FuncPrint(\"SERIAL_ID4_rtv\", SERIAL_ID4_rtv[CURRENT_SITE_NUMBER()-1]);\n FOR_EACH_SITE_END();\n\n \t\t rdi.runTimeVal(\"SERIAL_ID0_rtv\", SERIAL_ID0_rtv);\n \t\t rdi.runTimeVal(\"SERIAL_ID1_rtv\", SERIAL_ID1_rtv);\n \t\t rdi.runTimeVal(\"SERIAL_ID2_rtv\", SERIAL_ID2_rtv);\n \t\t rdi.runTimeVal(\"SERIAL_ID3_rtv\", SERIAL_ID3_rtv);\n \t\t rdi.runTimeVal(\"SERIAL_ID4_rtv\", SERIAL_ID4_rtv);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T20_20_write_serial_ID_V1_PAT_id0\");\n rdi.func().label(s_splited_pat_name[0]).execute();\n rdi.dc().pin(\"VDD\").vForce(3.6 V).iRange(40 mA).execute();\n rdi.wait(1 ms);\n rdi.smartVec().label(s_splited_pat_name[1]).pin(\"SDX\").writeData(\"SERIAL_ID0_rtv\", Wri_Bit_Length, Wri_Bit_Position).execute();\n rdi.smartVec().label(s_splited_pat_name[2]).pin(\"SDX\").writeData(\"SERIAL_ID1_rtv\", Wri_Bit_Length, Wri_Bit_Position).execute();\n rdi.smartVec().label(s_splited_pat_name[3]).pin(\"SDX\").writeData(\"SERIAL_ID2_rtv\", Wri_Bit_Length, Wri_Bit_Position).execute();\n rdi.smartVec().label(s_splited_pat_name[4]).pin(\"SDX\").writeData(\"SERIAL_ID3_rtv\", Wri_Bit_Length, Wri_Bit_Position).execute();\n rdi.smartVec().label(s_splited_pat_name[5]).pin(\"SDX\").writeData(\"SERIAL_ID4_rtv\", Wri_Bit_Length, Wri_Bit_Position).execute();\n rdi.digCap(\"T20_20_write_serial_ID_V1_Digcap_id1\").vecVarOnly().pin(\"SDO\").capMode(TA::SER).samples(16*5).bitPerWord(16).execute();\n rdi.dc().pin(\"VDD\").vForce(1.8 V).iRange(40 mA).execute();\n rdi.func().label(s_splited_pat_name[6]).execute();\n RDI_END();\n\n }\n ON_FIRST_INVOCATION_END();\n // Auto_Code_Retrieve_Data\n \n int Func_result = rdi.id(\"T20_20_write_serial_ID_V1_PAT_id0\").getBurstPassFail();\n\n ARRAY_I Vec=rdi.id(\"T20_20_write_serial_ID_V1_Digcap_id1\").getVector();\n for (int i = 0; i<5; i++)\n {\n \t SERIAL_ID_RD[i][CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[i]);\n \t if ((SERIAL_ID_RD[i][CURRENT_SITE_NUMBER()-1]) != SERIAL_ID[i][CURRENT_SITE_NUMBER()-1]) Func_result=99;\n }\n\n \t FuncPrint(\"SERIAL_ID_RD[0]\", SERIAL_ID_RD[0][CURRENT_SITE_NUMBER()-1]);\n \t FuncPrint(\"SERIAL_ID_RD[1]\", SERIAL_ID_RD[1][CURRENT_SITE_NUMBER()-1]);\n \t FuncPrint(\"SERIAL_ID_RD[2]\", SERIAL_ID_RD[2][CURRENT_SITE_NUMBER()-1]);\n \t FuncPrint(\"SERIAL_ID_RD[3]\", SERIAL_ID_RD[3][CURRENT_SITE_NUMBER()-1]);\n \t FuncPrint(\"SERIAL_ID_RD[4]\", SERIAL_ID_RD[4][CURRENT_SITE_NUMBER()-1]);\n\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n // Auto_Code_Judge_and_log\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T20_20_write_serial_ID_V1\", T20_20_write_serial_ID_V1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "######################################################################################################################\n# Description: Calculation of the CRC checksum over all OTP backed registers\n# Step 1: Read OTP registers content, total 117 registers\n# Step 2: Calculate CRC checksum\n# Step 3: Write CRC checksum to dark OTP\n######################################################################################################################\nfrom test_sub_functions import *\n\ncmt('Version info: $Revision: 5 $ $Author: luz3sgh $ $Date: 2024/05/31 09:05:42 GMT $')\n\ncrc_otp = [\n#| name |\n#+---------------------------------+\n'HIF_TRIM_0', #n =000 Note: OTP RegID = n+1\n'HIF_CONFIG', #n =1\n'MCU_GP_0', #n =2\n'MCU_GP_1', #n =3\n'MCU_GP_2', #n =4\n'INT_CONF', #n =5\n'INT_MAP_HW', #n =6\n'INT_MAP_MCU', #n =7\n'FIFO_WATERMARK', #n =8\n'FIFO_CONF', #n =9\n'FCU_TRIM_0', #n =10\n'FCU_TRIM_1', #n =11\n'FILTER_CONF', #n =12\n'ACC_CONF', #n =13\n'GYR_CONF', #n =14\n'ALT_FILTER_CONF', #n =15\n'ALT_ACC_CONF', #n =16\n'ALT_GYR_CONF', #n =17\n'ALT_CONF', #n =18\n'LEGACY_CONF', #n =19\n'MCU_MEM_MARGIN_TRIM', #n =20\n'MCU_GLOB_CTRL', #n =21\n'ACC_AASR_CONF_0', #n =22\n'ACC_AASR_CONF_1', #n =23\n'IO_PAD_TRM', #n =24\n'IO_INT_CTRL', #n =25\n'IO_IF_CONF', #n =26\n'GYR_TRM_PHI_A0_CH1', #n =27\n'GYR_TRM_PHI_A1_CH1', #n =28\n'GYR_TRM_PHI_A0_CH2', #n =29\n'GYR_TRM_PHI_A1_CH2', #n =30\n'GYR_TRM_PHI_A0_CH3', #n =31\n'GYR_TRM_PHI_A1_CH3', #n =32\n'GYR_TRM_PHI_A2_CH1', #n =33\n'GYR_TRM_PHI_A2_CH2', #n =34\n'GYR_TRM_PHI_A2_CH3', #n =35\n'GYR_TRM_OFF_B0_CH1', #n =36\n'GYR_TRM_OFF_B1_CH1', #n =37\n'GYR_TRM_OFF_B2_CH1_CH2', #n =38\n'GYR_TRM_OFF_B0_CH2', #n =39\n'GYR_TRM_OFF_B1_CH2', #n =40\n'GYR_TRM_OFF_B2_CH2_CH3', #n =41\n'GYR_TRM_OFF_B0_CH3', #n =42\n'GYR_TRM_OFF_B1_CH3', #n =43\n'GYR_TRM_DGAIN_S0_CH1', #n =44\n'GYR_ACC_TRM_DGAIN_S1_CH1', #n =45\n'GYR_TRM_DGAIN_S0_CH2', #n =46\n'GYR_TRM_DGAIN_S1_CH2_CH3', #n =47\n'GYR_TRM_DGAIN_S0_CH3', #n =48\n'ACC_TRM_OFF_B0_CH1', #n =49\n'ACC_TRM_OFF_B1_B2_CH1', #n =50\n'ACC_TRM_OFF_B0_CH2', #n =51\n'ACC_TRM_OFF_B1_B2_CH2', #n =52\n'ACC_TRM_OFF_B0_CH3', #n =53\n'ACC_TRM_OFF_B1_B2_CH3', #n =54\n'ACC_TRM_DGAIN_S0_CH1', #n =55\n'ACC_TRM_DGAIN_S0_CH2', #n =56\n'ACC_TRM_DGAIN_S0_CH3', #n =57\n'ACC_TRM_DGAIN_S1_CH2_CH3', #n =58\n'TEMP_TRM_OFF_DGAIN', #n =59\n'TEMP_TRM_OFF_DT', #n =60\n'TEMP_TRM_BG_OFF_DGAIN_NORM', #n =61\n'ACC_CROSS_SY_CH12', #n =62\n'ACC_CROSS_SY_CH13', #n =63\n'ACC_CROSS_SY_CH21', #n =64\n'ACC_CROSS_SY_CH23', #n =65\n'ACC_CROSS_SY_CH31', #n =66\n'ACC_CROSS_SY_CH32', #n =67\n'ACC_TRM_DGAIN_8G_CH12', #n =68\n'ACC_TRM_DGAIN_8G_CH3', #n =69\n'ACC_TRM_OFF_STEP_8G_CH1', #n =70\n'ACC_TRM_OFF_STEP_8G_CH2', #n =71\n'ACC_TRM_OFF_STEP_8G_CH3', #n =72\n'ACC_TRM_OFF_STEP_ALP_8G_CH1', #n =73\n'ACC_TRM_OFF_STEP_ALP_8G_CH2', #n =74\n'ACC_TRM_OFF_STEP_ALP_8G_CH3', #n =75\n'ACC_TRM_OFF_STEP_ALP_32G_CH1', #n =76\n'ACC_TRM_OFF_STEP_ALP_32G_CH2', #n =77\n'ACC_TRM_OFF_STEP_ALP_32G_CH3', #n =78\n'GYR_CROSS_SY_CH12', #n =79\n'GYR_CROSS_SY_CH13', #n =80\n'GYR_CROSS_SY_CH21', #n =81\n'GYR_CROSS_SY_CH23', #n =82\n'GYR_CROSS_SY_CH31', #n =83\n'GYR_CROSS_SY_CH32', #n =84\n'GYR_QUAD_TRM_CH1', #n =85\n'GYR_QUAD_TRM_CH2', #n =86\n'GYR_QUAD_TRM_CH3', #n =87\n'GYR_ALP_TRM_PHI_CH12', #n =88\n'GYR_ALP_TRM_PHI_CH23', #n =89\n'GYR_ALP_TRM_OFF_CH1', #n =90\n'GYR_ALP_TRM_OFF_CH2', #n =91\n'GYR_ALP_TRM_OFF_CH3', #n =92\n'ANA_TRM_BG', #n =93\n'ANA_TRM_PMU', #n =94\n'ANA_TRM_PMU1', #n =95\n'ANA_TRM_OSC', #n =96\n'ANA_TRM_RES_PROG0', #n =97\n'ANA_TRM_RES_PROG1', #n =98\n'ANA_TRM_RES_PROG2', #n =99\n'ANA_TRM_CAP_PROG0', #n =100\n'ANA_TRM_CAP_PROG_CH1', #n =101\n'ANA_TRM_CAP_PROG_CH2', #n =102\n'ANA_TRM_CAP_PROG_CH3', #n =103\n'ANA_TRM_CAP_PROG_DRV', #n =104\n'ANA_TRM_ACC_CH1', #n =105\n'ANA_TRM_ACC_CH2', #n =106\n'ANA_TRM_ACC_CH3', #n =107\n'GYR_VGM_MON_CTRL', #n =108\n'TEMP_TRM_CTRL', #n =109\n'ACC_TRM_CFB', #n =110\n'ACC_TRM_LOOPG', #n =111\n'ACC_TRM_CTRL', #n =112\n'GYR_TRM_NOTCH12_GRPC', #n =113\n'GYR_TRM_NOTCH3_MISC', #n =114\n'GYR_TRM_BYP_MASH', #n =115\n'DRV_ST_TRM' #n =116, regid 117, 0x7fz \n]\n\n# Trigger soft reset to clear all registers and boot from OTP\nwr('CMD', 0xdeaf) # Trigger soft reset\ndly(3e-3)\nrac('CHIP_ID', 0x0000, 0x0000) # Dummy read to init SPI protocol\ndly(10e-6)\nrac('CHIP_ID', 0x00af, 0x00ff) # Read chip ID (proof for the reset)\ndly(10e-6)\nwr('CMD', 0xBB3A) # 1st command for enabling the extended mode\nwr('CMD', 0x2C62) # 2nd command for enabling the extended mode\nwr('CMD', 0xA576) # 1st command for enabling the super privilege mode\nwr('CMD', 0x34D6) # 2nd command for enabling the super privilege mode\n\n# Read register content (loaded from OTP)\n\nfor n in range (0, len(crc_otp), 1):\n wac('EXT_MODE', 0xc000 + get_reg_page(crc_otp[n])) # Switch to register page\n ras(f'crcdata_{n:03d}_{crc_otp[n]}', crc_otp[n]) # Read register and save data to crcdata_n\n\ncmt('Calculate the CRC-16 CCITT checksum for the 117 data words crcdata_000-116_*')\ncmt('and store in variable CRC_CALC_OTP')\n\ncalc('CRC_CALC_OTP', 0xabcd) # Assign placeholder value for simulation, REPLACE with calculated CRC_CALC_OTP\nlog('CRC_CALC_OTP')\n\n# Switch to USR page and enable ACC\nwac('EXT_MODE', 0xc000) # Switch to USR register page\nwac('ACC_CONF', 0xe24c) # Enable ACC in HPM; set AFS=32g; set ODR=1600; set BW=200\ndly(400e-6)\nrac('ERR_REG', 0x0000) # Check error register\nwac('EXT_MODE', 0xc00d) # Switch to PMU register page\nrac('STATUS_PMOD0', 0x0003, 0x0003) # Check ACC AFE PMU status\n\n# Program CRC_CALC_OTP to dark OTP\nwcb('nvmotp_power_en',0x1) # Request OTP power\ndly(300e-6)\nwac('EXT_MODE', 0xc00f) # Switch to OTPCTRL register page\nwac('OTP_PROG_EN', 0x0002) # Enable OTP program\nwcb('vddp_sw', 0x1) # Connect VDDP to VDD\nsav('VDD', 3.6, v_range=4.0, i_comp=40e-3)\ndly(1e-3)\nwri('OTP_DATA', 'CRC_CALC_OTP') # Write CRC_CALC_OTP to OTP data register\nrac('OTP_STATUS', 0x0001) # Check OTP ready\nwr('OTP_CMD', 0x0005) # Trigger OTP data program\ndly(200e-6) # OTP spec, pgm speed 10us per bit\nwac('OTP_DATA',0xcc) # Set regID for dark OTP\nrac('OTP_STATUS', 0x0001) # Check OTP ready\nwr('OTP_CMD', 0x0006) # Trigger OTP reg_id program\ndly(200e-6)\nrac('OTP_STATUS', 0x0001) # Check OTP ready\nsav('VDD', 1.8, v_range=4.0, i_comp=40e-3)\ndly(1e-3)\nwac('OTP_PROG_EN', 0x0000) # Disable OTP program\nwcb('vddp_sw', 0x0) # Connect VDDP to VDDD_DC\nwac('OTP_DATA', 0x0000) # Reset OTP data register\n# Read data from OTP\nwac('BOOT_RANGE', 0xcccc) # Set register ID for dark OTP load\nrac('BOOT_STATUS', 0x0001) # Check boot controller ready and error bits\nwr('BOOT_CMD', 0x0001) # Trigger OTP load\ndly(1.2e-3)\nras('CRC_CALC_OTP_RD', 'BOOT_LAST_DATA') # Read and save OTP data\ncmt('This test item is a functional fail if CRC_CALC_OTP_RD != CRC_CALC_OTP')\n# Clean-up\nwac('BOOT_RANGE', 0x0000)\nwac('EXT_MODE', 0xc00d) # Switch to PMU register page\nwcb('nvmotp_power_en',0x0) # Disable OTP power\ndly(100e-6)\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T20_22_CRC_write_V5: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n INT split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &split_pat_flag);\n vector s_splited_pat_name;\n const int split_count = 4; // Alarm:: split_count need manual confirm.\n s_splited_pat_name.resize(split_count);\n vector i_comment_line[split_count];\n\n\n static int crcdata[xNSitES][117];\n// static int crcdata_000_HIF_TRIM_0[xNSitES];\n// static int crcdata_001_HIF_CONFIG[xNSitES];\n// static int crcdata_002_MCU_GP_0[xNSitES];\n// static int crcdata_003_MCU_GP_1[xNSitES];\n// static int crcdata_004_MCU_GP_2[xNSitES];\n// static int crcdata_005_INT_CONF[xNSitES];\n// static int crcdata_006_INT_MAP_HW[xNSitES];\n// static int crcdata_007_INT_MAP_MCU[xNSitES];\n// static int crcdata_008_FIFO_WATERMARK[xNSitES];\n// static int crcdata_009_FIFO_CONF[xNSitES];\n// static int crcdata_010_FCU_TRIM_0[xNSitES];\n// static int crcdata_011_FCU_TRIM_1[xNSitES];\n// static int crcdata_012_FILTER_CONF[xNSitES];\n// static int crcdata_013_ACC_CONF[xNSitES];\n// static int crcdata_014_GYR_CONF[xNSitES];\n// static int crcdata_015_ALT_FILTER_CONF[xNSitES];\n// static int crcdata_016_ALT_ACC_CONF[xNSitES];\n// static int crcdata_017_ALT_GYR_CONF[xNSitES];\n// static int crcdata_018_ALT_CONF[xNSitES];\n// static int crcdata_019_LEGACY_CONF[xNSitES];\n// static int crcdata_020_MCU_MEM_MARGIN_TRIM[xNSitES];\n// static int crcdata_021_MCU_GLOB_CTRL[xNSitES];\n// static int crcdata_022_ACC_AASR_CONF_0[xNSitES];\n// static int crcdata_023_ACC_AASR_CONF_1[xNSitES];\n// static int crcdata_024_IO_PAD_TRM[xNSitES];\n// static int crcdata_025_IO_INT_CTRL[xNSitES];\n// static int crcdata_026_IO_IF_CONF[xNSitES];\n// static int crcdata_027_GYR_TRM_PHI_A0_CH1[xNSitES];\n// static int crcdata_028_GYR_TRM_PHI_A1_CH1[xNSitES];\n// static int crcdata_029_GYR_TRM_PHI_A0_CH2[xNSitES];\n// static int crcdata_030_GYR_TRM_PHI_A1_CH2[xNSitES];\n// static int crcdata_031_GYR_TRM_PHI_A0_CH3[xNSitES];\n// static int crcdata_032_GYR_TRM_PHI_A1_CH3[xNSitES];\n// static int crcdata_033_GYR_TRM_PHI_A2_CH1[xNSitES];\n// static int crcdata_034_GYR_TRM_PHI_A2_CH2[xNSitES];\n// static int crcdata_035_GYR_TRM_PHI_A2_CH3[xNSitES];\n// static int crcdata_036_GYR_TRM_OFF_B0_CH1[xNSitES];\n// static int crcdata_037_GYR_TRM_OFF_B1_CH1[xNSitES];\n// static int crcdata_038_GYR_TRM_OFF_B2_CH1_CH2[xNSitES];\n// static int crcdata_039_GYR_TRM_OFF_B0_CH2[xNSitES];\n// static int crcdata_040_GYR_TRM_OFF_B1_CH2[xNSitES];\n// static int crcdata_041_GYR_TRM_OFF_B2_CH2_CH3[xNSitES];\n// static int crcdata_042_GYR_TRM_OFF_B0_CH3[xNSitES];\n// static int crcdata_043_GYR_TRM_OFF_B1_CH3[xNSitES];\n// static int crcdata_044_GYR_TRM_DGAIN_S0_CH1[xNSitES];\n// static int crcdata_045_GYR_ACC_TRM_DGAIN_S1_CH1[xNSitES];\n// static int crcdata_046_GYR_TRM_DGAIN_S0_CH2[xNSitES];\n// static int crcdata_047_GYR_TRM_DGAIN_S1_CH2_CH3[xNSitES];\n// static int crcdata_048_GYR_TRM_DGAIN_S0_CH3[xNSitES];\n// static int crcdata_049_ACC_TRM_OFF_B0_CH1[xNSitES];\n// static int crcdata_050_ACC_TRM_OFF_B1_B2_CH1[xNSitES];\n// static int crcdata_051_ACC_TRM_OFF_B0_CH2[xNSitES];\n// static int crcdata_052_ACC_TRM_OFF_B1_B2_CH2[xNSitES];\n// static int crcdata_053_ACC_TRM_OFF_B0_CH3[xNSitES];\n// static int crcdata_054_ACC_TRM_OFF_B1_B2_CH3[xNSitES];\n// static int crcdata_055_ACC_TRM_DGAIN_S0_CH1[xNSitES];\n// static int crcdata_056_ACC_TRM_DGAIN_S0_CH2[xNSitES];\n// static int crcdata_057_ACC_TRM_DGAIN_S0_CH3[xNSitES];\n// static int crcdata_058_ACC_TRM_DGAIN_S1_CH2_CH3[xNSitES];\n// static int crcdata_059_TEMP_TRM_OFF_DGAIN[xNSitES];\n// static int crcdata_060_TEMP_TRM_OFF_DT[xNSitES];\n// static int crcdata_061_TEMP_TRM_BG_OFF_DGAIN_NORM[xNSitES];\n// static int crcdata_062_ACC_CROSS_SY_CH12[xNSitES];\n// static int crcdata_063_ACC_CROSS_SY_CH13[xNSitES];\n// static int crcdata_064_ACC_CROSS_SY_CH21[xNSitES];\n// static int crcdata_065_ACC_CROSS_SY_CH23[xNSitES];\n// static int crcdata_066_ACC_CROSS_SY_CH31[xNSitES];\n// static int crcdata_067_ACC_CROSS_SY_CH32[xNSitES];\n// static int crcdata_068_ACC_TRM_DGAIN_8G_CH12[xNSitES];\n// static int crcdata_069_ACC_TRM_DGAIN_8G_CH3[xNSitES];\n// static int crcdata_070_ACC_TRM_OFF_STEP_8G_CH1[xNSitES];\n// static int crcdata_071_ACC_TRM_OFF_STEP_8G_CH2[xNSitES];\n// static int crcdata_072_ACC_TRM_OFF_STEP_8G_CH3[xNSitES];\n// static int crcdata_073_ACC_TRM_OFF_STEP_ALP_8G_CH1[xNSitES];\n// static int crcdata_074_ACC_TRM_OFF_STEP_ALP_8G_CH2[xNSitES];\n// static int crcdata_075_ACC_TRM_OFF_STEP_ALP_8G_CH3[xNSitES];\n// static int crcdata_076_ACC_TRM_OFF_STEP_ALP_32G_CH1[xNSitES];\n// static int crcdata_077_ACC_TRM_OFF_STEP_ALP_32G_CH2[xNSitES];\n// static int crcdata_078_ACC_TRM_OFF_STEP_ALP_32G_CH3[xNSitES];\n// static int crcdata_079_GYR_CROSS_SY_CH12[xNSitES];\n// static int crcdata_080_GYR_CROSS_SY_CH13[xNSitES];\n// static int crcdata_081_GYR_CROSS_SY_CH21[xNSitES];\n// static int crcdata_082_GYR_CROSS_SY_CH23[xNSitES];\n// static int crcdata_083_GYR_CROSS_SY_CH31[xNSitES];\n// static int crcdata_084_GYR_CROSS_SY_CH32[xNSitES];\n// static int crcdata_085_GYR_QUAD_TRM_CH1[xNSitES];\n// static int crcdata_086_GYR_QUAD_TRM_CH2[xNSitES];\n// static int crcdata_087_GYR_QUAD_TRM_CH3[xNSitES];\n// static int crcdata_088_GYR_ALP_TRM_PHI_CH12[xNSitES];\n// static int crcdata_089_GYR_ALP_TRM_PHI_CH23[xNSitES];\n// static int crcdata_090_GYR_ALP_TRM_OFF_CH1[xNSitES];\n// static int crcdata_091_GYR_ALP_TRM_OFF_CH2[xNSitES];\n// static int crcdata_092_GYR_ALP_TRM_OFF_CH3[xNSitES];\n// static int crcdata_093_ANA_TRM_BG[xNSitES];\n// static int crcdata_094_ANA_TRM_PMU[xNSitES];\n// static int crcdata_095_ANA_TRM_PMU1[xNSitES];\n// static int crcdata_096_ANA_TRM_OSC[xNSitES];\n// static int crcdata_097_ANA_TRM_RES_PROG0[xNSitES];\n// static int crcdata_098_ANA_TRM_RES_PROG1[xNSitES];\n// static int crcdata_099_ANA_TRM_RES_PROG2[xNSitES];\n// static int crcdata_100_ANA_TRM_CAP_PROG0[xNSitES];\n// static int crcdata_101_ANA_TRM_CAP_PROG_CH1[xNSitES];\n// static int crcdata_102_ANA_TRM_CAP_PROG_CH2[xNSitES];\n// static int crcdata_103_ANA_TRM_CAP_PROG_CH3[xNSitES];\n// static int crcdata_104_ANA_TRM_CAP_PROG_DRV[xNSitES];\n// static int crcdata_105_ANA_TRM_ACC_CH1[xNSitES];\n// static int crcdata_106_ANA_TRM_ACC_CH2[xNSitES];\n// static int crcdata_107_ANA_TRM_ACC_CH3[xNSitES];\n// static int crcdata_108_GYR_VGM_MON_CTRL[xNSitES];\n// static int crcdata_109_TEMP_TRM_CTRL[xNSitES];\n// static int crcdata_110_ACC_TRM_CFB[xNSitES];\n// static int crcdata_111_ACC_TRM_LOOPG[xNSitES];\n// static int crcdata_112_ACC_TRM_CTRL[xNSitES];\n// static int crcdata_113_GYR_TRM_NOTCH12_GRPC[xNSitES];\n// static int crcdata_114_GYR_TRM_NOTCH3_MISC[xNSitES];\n// static int crcdata_115_GYR_TRM_BYP_MASH[xNSitES];\n// static int crcdata_116_DRV_ST_TRM[xNSitES];\n static int CRC_CALC_OTP_RD[xNSitES], CRC_CALC_OTP[xNSitES];\n ARRAY_LL CRC_CALC_OTP_rtv;\n const int Wri_Bit_Length = 33;\n const int Wri_Bit_Position = 31;\n // Auto_Code_Variable_define\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n GET_TESTSUITE_NAME(test_name);\n CRC_CALC_OTP_rtv.resize(xNSitES);\n\n if (split_pat_flag)\n {\n split_pattern(s_label_name,\"wri\",\"sav\",split_pat_flag,s_splited_pat_name);\n }\n else\n {\n for (int i = 0; i i_comment_line0;\n\n// static int crcdata_000_HIF_TRIM_0_check[xNSitES];\n// static int crcdata_001_HIF_CONFIG_check[xNSitES];\n// static int crcdata_002_MCU_GP_0_check[xNSitES];\n// static int crcdata_003_MCU_GP_1_check[xNSitES];\n// static int crcdata_004_MCU_GP_2_check[xNSitES];\n// static int crcdata_005_INT_CONF_check[xNSitES];\n// static int crcdata_006_INT_MAP_HW_check[xNSitES];\n// static int crcdata_007_INT_MAP_MCU_check[xNSitES];\n// static int crcdata_008_FIFO_WATERMARK_check[xNSitES];\n// static int crcdata_009_FIFO_CONF_check[xNSitES];\n// static int crcdata_010_FCU_TRIM_0_check[xNSitES];\n// static int crcdata_011_FCU_TRIM_1_check[xNSitES];\n// static int crcdata_012_FILTER_CONF_check[xNSitES];\n// static int crcdata_013_ACC_CONF_check[xNSitES];\n// static int crcdata_014_GYR_CONF_check[xNSitES];\n// static int crcdata_015_ALT_FILTER_CONF_check[xNSitES];\n// static int crcdata_016_ALT_ACC_CONF_check[xNSitES];\n// static int crcdata_017_ALT_GYR_CONF_check[xNSitES];\n// static int crcdata_018_ALT_CONF_check[xNSitES];\n// static int crcdata_019_LEGACY_CONF_check[xNSitES];\n// static int crcdata_020_MCU_MEM_MARGIN_TRIM_check[xNSitES];\n// static int crcdata_021_MCU_GLOB_CTRL_check[xNSitES];\n// static int crcdata_022_ACC_AASR_CONF_0_check[xNSitES];\n// static int crcdata_023_ACC_AASR_CONF_1_check[xNSitES];\n// static int crcdata_024_IO_PAD_TRM_check[xNSitES];\n// static int crcdata_025_IO_INT_CTRL_check[xNSitES];\n// static int crcdata_026_IO_IF_CONF_check[xNSitES];\n// static int crcdata_027_GYR_TRM_PHI_A0_CH1_check[xNSitES];\n// static int crcdata_028_GYR_TRM_PHI_A1_CH1_check[xNSitES];\n// static int crcdata_029_GYR_TRM_PHI_A0_CH2_check[xNSitES];\n// static int crcdata_030_GYR_TRM_PHI_A1_CH2_check[xNSitES];\n// static int crcdata_031_GYR_TRM_PHI_A0_CH3_check[xNSitES];\n// static int crcdata_032_GYR_TRM_PHI_A1_CH3_check[xNSitES];\n// static int crcdata_033_GYR_TRM_PHI_A2_CH1_check[xNSitES];\n// static int crcdata_034_GYR_TRM_PHI_A2_CH2_check[xNSitES];\n// static int crcdata_035_GYR_TRM_PHI_A2_CH3_check[xNSitES];\n// static int crcdata_036_GYR_TRM_OFF_B0_CH1_check[xNSitES];\n// static int crcdata_037_GYR_TRM_OFF_B1_CH1_check[xNSitES];\n// static int crcdata_038_GYR_TRM_OFF_B2_CH1_CH2_check[xNSitES];\n// static int crcdata_039_GYR_TRM_OFF_B0_CH2_check[xNSitES];\n// static int crcdata_040_GYR_TRM_OFF_B1_CH2_check[xNSitES];\n// static int crcdata_041_GYR_TRM_OFF_B2_CH2_CH3_check[xNSitES];\n// static int crcdata_042_GYR_TRM_OFF_B0_CH3_check[xNSitES];\n// static int crcdata_043_GYR_TRM_OFF_B1_CH3_check[xNSitES];\n// static int crcdata_044_GYR_TRM_DGAIN_S0_CH1_check[xNSitES];\n// static int crcdata_045_GYR_ACC_TRM_DGAIN_S1_CH1_check[xNSitES];\n// static int crcdata_046_GYR_TRM_DGAIN_S0_CH2_check[xNSitES];\n// static int crcdata_047_GYR_TRM_DGAIN_S1_CH2_CH3_check[xNSitES];\n// static int crcdata_048_GYR_TRM_DGAIN_S0_CH3_check[xNSitES];\n// static int crcdata_049_ACC_TRM_OFF_B0_CH1_check[xNSitES];\n// static int crcdata_050_ACC_TRM_OFF_B1_B2_CH1_check[xNSitES];\n// static int crcdata_051_ACC_TRM_OFF_B0_CH2_check[xNSitES];\n// static int crcdata_052_ACC_TRM_OFF_B1_B2_CH2_check[xNSitES];\n// static int crcdata_053_ACC_TRM_OFF_B0_CH3_check[xNSitES];\n// static int crcdata_054_ACC_TRM_OFF_B1_B2_CH3_check[xNSitES];\n// static int crcdata_055_ACC_TRM_DGAIN_S0_CH1_check[xNSitES];\n// static int crcdata_056_ACC_TRM_DGAIN_S0_CH2_check[xNSitES];\n// static int crcdata_057_ACC_TRM_DGAIN_S0_CH3_check[xNSitES];\n// static int crcdata_058_ACC_TRM_DGAIN_S1_CH2_CH3_check[xNSitES];\n// static int crcdata_059_TEMP_TRM_OFF_DGAIN_check[xNSitES];\n// static int crcdata_060_TEMP_TRM_OFF_DT_check[xNSitES];\n// static int crcdata_061_TEMP_TRM_BG_OFF_DGAIN_NORM_check[xNSitES];\n// static int crcdata_062_ACC_CROSS_SY_CH12_check[xNSitES];\n// static int crcdata_063_ACC_CROSS_SY_CH13_check[xNSitES];\n// static int crcdata_064_ACC_CROSS_SY_CH21_check[xNSitES];\n// static int crcdata_065_ACC_CROSS_SY_CH23_check[xNSitES];\n// static int crcdata_066_ACC_CROSS_SY_CH31_check[xNSitES];\n// static int crcdata_067_ACC_CROSS_SY_CH32_check[xNSitES];\n// static int crcdata_068_ACC_TRM_DGAIN_8G_CH12_check[xNSitES];\n// static int crcdata_069_ACC_TRM_DGAIN_8G_CH3_check[xNSitES];\n// static int crcdata_070_ACC_TRM_OFF_STEP_8G_CH1_check[xNSitES];\n// static int crcdata_071_ACC_TRM_OFF_STEP_8G_CH2_check[xNSitES];\n// static int crcdata_072_ACC_TRM_OFF_STEP_8G_CH3_check[xNSitES];\n// static int crcdata_073_ACC_TRM_OFF_STEP_ALP_8G_CH1_check[xNSitES];\n// static int crcdata_074_ACC_TRM_OFF_STEP_ALP_8G_CH2_check[xNSitES];\n// static int crcdata_075_ACC_TRM_OFF_STEP_ALP_8G_CH3_check[xNSitES];\n// static int crcdata_076_ACC_TRM_OFF_STEP_ALP_32G_CH1_check[xNSitES];\n// static int crcdata_077_ACC_TRM_OFF_STEP_ALP_32G_CH2_check[xNSitES];\n// static int crcdata_078_ACC_TRM_OFF_STEP_ALP_32G_CH3_check[xNSitES];\n// static int crcdata_079_GYR_CROSS_SY_CH12_check[xNSitES];\n// static int crcdata_080_GYR_CROSS_SY_CH13_check[xNSitES];\n// static int crcdata_081_GYR_CROSS_SY_CH21_check[xNSitES];\n// static int crcdata_082_GYR_CROSS_SY_CH23_check[xNSitES];\n// static int crcdata_083_GYR_CROSS_SY_CH31_check[xNSitES];\n// static int crcdata_084_GYR_CROSS_SY_CH32_check[xNSitES];\n// static int crcdata_085_GYR_QUAD_TRM_CH1_check[xNSitES];\n// static int crcdata_086_GYR_QUAD_TRM_CH2_check[xNSitES];\n// static int crcdata_087_GYR_QUAD_TRM_CH3_check[xNSitES];\n// static int crcdata_088_GYR_ALP_TRM_PHI_CH12_check[xNSitES];\n// static int crcdata_089_GYR_ALP_TRM_PHI_CH23_check[xNSitES];\n// static int crcdata_090_GYR_ALP_TRM_OFF_CH1_check[xNSitES];\n// static int crcdata_091_GYR_ALP_TRM_OFF_CH2_check[xNSitES];\n// static int crcdata_092_GYR_ALP_TRM_OFF_CH3_check[xNSitES];\n// static int crcdata_093_ANA_TRM_BG_check[xNSitES];\n// static int crcdata_094_ANA_TRM_PMU_check[xNSitES];\n// static int crcdata_095_ANA_TRM_PMU1_check[xNSitES];\n// static int crcdata_096_ANA_TRM_OSC_check[xNSitES];\n// static int crcdata_097_ANA_TRM_RES_PROG0_check[xNSitES];\n// static int crcdata_098_ANA_TRM_RES_PROG1_check[xNSitES];\n// static int crcdata_099_ANA_TRM_RES_PROG2_check[xNSitES];\n// static int crcdata_100_ANA_TRM_CAP_PROG0_check[xNSitES];\n// static int crcdata_101_ANA_TRM_CAP_PROG_CH1_check[xNSitES];\n// static int crcdata_102_ANA_TRM_CAP_PROG_CH2_check[xNSitES];\n// static int crcdata_103_ANA_TRM_CAP_PROG_CH3_check[xNSitES];\n// static int crcdata_104_ANA_TRM_CAP_PROG_DRV_check[xNSitES];\n// static int crcdata_105_ANA_TRM_ACC_CH1_check[xNSitES];\n// static int crcdata_106_ANA_TRM_ACC_CH2_check[xNSitES];\n// static int crcdata_107_ANA_TRM_ACC_CH3_check[xNSitES];\n// static int crcdata_108_GYR_VGM_MON_CTRL_check[xNSitES];\n// static int crcdata_109_TEMP_TRM_CTRL_check[xNSitES];\n// static int crcdata_110_ACC_TRM_CFB_check[xNSitES];\n// static int crcdata_111_ACC_TRM_LOOPG_check[xNSitES];\n// static int crcdata_112_ACC_TRM_CTRL_check[xNSitES];\n// static int crcdata_113_GYR_TRM_NOTCH12_GRPC_check[xNSitES];\n// static int crcdata_114_GYR_TRM_NOTCH3_MISC_check[xNSitES];\n// static int crcdata_115_GYR_TRM_BYP_MASH_check[xNSitES];\n// static int crcdata_116_DRV_ST_TRM_check[xNSitES];\n static int CRC_OTP_RD[xNSitES];\n // Auto_Code_Variable_define\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n rdi.enableOre(oreFlag);\n rdi.oreFile(\"./ORE_Files/rdi_ore_T20_23_CRC_CHECK.xml\");\n\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T20_23_CRC_check_V4_PAT_id\");\n rdi.digCap(\"T20_23_CRC_check_V4_Digcap_id\").label(s_label_name)\n .pin(\"SDO\").capMode(TA::SER).samples(16*118).bitPerWord(16)\n .execute();\n RDI_END();\n\n ON_FIRST_INVOCATION_END();\n\n\t ARRAY_I Vec=rdi.id(\"T20_23_CRC_check_V4_Digcap_id\").getVector();\n\t FuncPrint(\"crcdata_000_HIF_TRIM_0_check\",reverse_ras_result(Vec[0]));\n\t FuncPrint(\"crcdata_001_HIF_CONFIG_check\",reverse_ras_result(Vec[1]));\n\t FuncPrint(\"crcdata_002_MCU_GP_0_check\",reverse_ras_result(Vec[2]));\n\t FuncPrint(\"crcdata_003_MCU_GP_1_check\",reverse_ras_result(Vec[3]));\n\t FuncPrint(\"crcdata_004_MCU_GP_2_check\",reverse_ras_result(Vec[4]));\n\t FuncPrint(\"crcdata_005_INT_CONF_check\",reverse_ras_result(Vec[5]));\n\t FuncPrint(\"crcdata_006_INT_MAP_HW_check\",reverse_ras_result(Vec[6]));\n\t FuncPrint(\"crcdata_007_INT_MAP_MCU_check\",reverse_ras_result(Vec[7]));\n\t FuncPrint(\"crcdata_008_FIFO_WATERMARK_check\",reverse_ras_result(Vec[8]));\n\t FuncPrint(\"crcdata_009_FIFO_CONF_check\",reverse_ras_result(Vec[9]));\n\t FuncPrint(\"crcdata_010_FCU_TRIM_0_check\",reverse_ras_result(Vec[10]));\n\t FuncPrint(\"crcdata_011_FCU_TRIM_1_check\",reverse_ras_result(Vec[11]));\n\t FuncPrint(\"crcdata_012_FILTER_CONF_check\",reverse_ras_result(Vec[12]));\n\t FuncPrint(\"crcdata_013_ACC_CONF_check\",reverse_ras_result(Vec[13]));\n\t FuncPrint(\"crcdata_014_GYR_CONF_check\",reverse_ras_result(Vec[14]));\n\t FuncPrint(\"crcdata_015_ALT_FILTER_CONF_check\",reverse_ras_result(Vec[15]));\n\t FuncPrint(\"crcdata_016_ALT_ACC_CONF_check\",reverse_ras_result(Vec[16]));\n\t FuncPrint(\"crcdata_017_ALT_GYR_CONF_check\",reverse_ras_result(Vec[17]));\n\t FuncPrint(\"crcdata_018_ALT_CONF_check\",reverse_ras_result(Vec[18]));\n\t FuncPrint(\"crcdata_019_LEGACY_CONF_check\",reverse_ras_result(Vec[19]));\n\t FuncPrint(\"crcdata_020_MCU_MEM_MARGIN_TRIM_check\",reverse_ras_result(Vec[20]));\n\t FuncPrint(\"crcdata_021_MCU_GLOB_CTRL_check\",reverse_ras_result(Vec[21]));\n\t FuncPrint(\"crcdata_022_ACC_AASR_CONF_0_check\",reverse_ras_result(Vec[22]));\n\t FuncPrint(\"crcdata_023_ACC_AASR_CONF_1_check\",reverse_ras_result(Vec[23]));\n\t FuncPrint(\"crcdata_024_IO_PAD_TRM_check\",reverse_ras_result(Vec[24]));\n\t FuncPrint(\"crcdata_025_IO_INT_CTRL_check\",reverse_ras_result(Vec[25]));\n\t FuncPrint(\"crcdata_026_IO_IF_CONF_check\",reverse_ras_result(Vec[26]));\n\t FuncPrint(\"crcdata_027_GYR_TRM_PHI_A0_CH1_check\",reverse_ras_result(Vec[27]));\n\t FuncPrint(\"crcdata_028_GYR_TRM_PHI_A1_CH1_check\",reverse_ras_result(Vec[28]));\n\t FuncPrint(\"crcdata_029_GYR_TRM_PHI_A0_CH2_check\",reverse_ras_result(Vec[29]));\n\t FuncPrint(\"crcdata_030_GYR_TRM_PHI_A1_CH2_check\",reverse_ras_result(Vec[30]));\n\t FuncPrint(\"crcdata_031_GYR_TRM_PHI_A0_CH3_check\",reverse_ras_result(Vec[31]));\n\t FuncPrint(\"crcdata_032_GYR_TRM_PHI_A1_CH3_check\",reverse_ras_result(Vec[32]));\n\t FuncPrint(\"crcdata_033_GYR_TRM_PHI_A2_CH1_check\",reverse_ras_result(Vec[33]));\n\t FuncPrint(\"crcdata_034_GYR_TRM_PHI_A2_CH2_check\",reverse_ras_result(Vec[34]));\n\t FuncPrint(\"crcdata_035_GYR_TRM_PHI_A2_CH3_check\",reverse_ras_result(Vec[35]));\n\t FuncPrint(\"crcdata_036_GYR_TRM_OFF_B0_CH1_check\",reverse_ras_result(Vec[36]));\n\t FuncPrint(\"crcdata_037_GYR_TRM_OFF_B1_CH1_check\",reverse_ras_result(Vec[37]));\n\t FuncPrint(\"crcdata_038_GYR_TRM_OFF_B2_CH1_CH2_check\",reverse_ras_result(Vec[38]));\n\t FuncPrint(\"crcdata_039_GYR_TRM_OFF_B0_CH2_check\",reverse_ras_result(Vec[39]));\n\t FuncPrint(\"crcdata_040_GYR_TRM_OFF_B1_CH2_check\",reverse_ras_result(Vec[40]));\n\t FuncPrint(\"crcdata_041_GYR_TRM_OFF_B2_CH2_CH3_check\",reverse_ras_result(Vec[41]));\n\t FuncPrint(\"crcdata_042_GYR_TRM_OFF_B0_CH3_check\",reverse_ras_result(Vec[42]));\n\t FuncPrint(\"crcdata_043_GYR_TRM_OFF_B1_CH3_check\",reverse_ras_result(Vec[43]));\n\t FuncPrint(\"crcdata_044_GYR_TRM_DGAIN_S0_CH1_check\",reverse_ras_result(Vec[44]));\n\t FuncPrint(\"crcdata_045_GYR_ACC_TRM_DGAIN_S1_CH1_check\",reverse_ras_result(Vec[45]));\n\t FuncPrint(\"crcdata_046_GYR_TRM_DGAIN_S0_CH2_check\",reverse_ras_result(Vec[46]));\n\t FuncPrint(\"crcdata_047_GYR_TRM_DGAIN_S1_CH2_CH3_check\",reverse_ras_result(Vec[47]));\n\t FuncPrint(\"crcdata_048_GYR_TRM_DGAIN_S0_CH3_check\",reverse_ras_result(Vec[48]));\n\t FuncPrint(\"crcdata_049_ACC_TRM_OFF_B0_CH1_check\",reverse_ras_result(Vec[49]));\n\t FuncPrint(\"crcdata_050_ACC_TRM_OFF_B1_B2_CH1_check\",reverse_ras_result(Vec[50]));\n\t FuncPrint(\"crcdata_051_ACC_TRM_OFF_B0_CH2_check\",reverse_ras_result(Vec[51]));\n\t FuncPrint(\"crcdata_052_ACC_TRM_OFF_B1_B2_CH2_check\",reverse_ras_result(Vec[52]));\n\t FuncPrint(\"crcdata_053_ACC_TRM_OFF_B0_CH3_check\",reverse_ras_result(Vec[53]));\n\t FuncPrint(\"crcdata_054_ACC_TRM_OFF_B1_B2_CH3_check\",reverse_ras_result(Vec[54]));\n\t FuncPrint(\"crcdata_055_ACC_TRM_DGAIN_S0_CH1_check\",reverse_ras_result(Vec[55]));\n\t FuncPrint(\"crcdata_056_ACC_TRM_DGAIN_S0_CH2_check\",reverse_ras_result(Vec[56]));\n\t FuncPrint(\"crcdata_057_ACC_TRM_DGAIN_S0_CH3_check\",reverse_ras_result(Vec[57]));\n\t FuncPrint(\"crcdata_058_ACC_TRM_DGAIN_S1_CH2_CH3_check\",reverse_ras_result(Vec[58]));\n\t FuncPrint(\"crcdata_059_TEMP_TRM_OFF_DGAIN_check\",reverse_ras_result(Vec[59]));\n\t FuncPrint(\"crcdata_060_TEMP_TRM_OFF_DT_check\",reverse_ras_result(Vec[60]));\n\t FuncPrint(\"crcdata_061_TEMP_TRM_BG_OFF_DGAIN_NORM_check\",reverse_ras_result(Vec[61]));\n\t FuncPrint(\"crcdata_062_ACC_CROSS_SY_CH12_check\",reverse_ras_result(Vec[62]));\n\t FuncPrint(\"crcdata_063_ACC_CROSS_SY_CH13_check\",reverse_ras_result(Vec[63]));\n\t FuncPrint(\"crcdata_064_ACC_CROSS_SY_CH21_check\",reverse_ras_result(Vec[64]));\n\t FuncPrint(\"crcdata_065_ACC_CROSS_SY_CH23_check\",reverse_ras_result(Vec[65]));\n\t FuncPrint(\"crcdata_066_ACC_CROSS_SY_CH31_check\",reverse_ras_result(Vec[66]));\n\t FuncPrint(\"crcdata_067_ACC_CROSS_SY_CH32_check\",reverse_ras_result(Vec[67]));\n\t FuncPrint(\"crcdata_068_ACC_TRM_DGAIN_8G_CH12_check\",reverse_ras_result(Vec[68]));\n\t FuncPrint(\"crcdata_069_ACC_TRM_DGAIN_8G_CH3_check\",reverse_ras_result(Vec[69]));\n\t FuncPrint(\"crcdata_070_ACC_TRM_OFF_STEP_8G_CH1_check\",reverse_ras_result(Vec[70]));\n\t FuncPrint(\"crcdata_071_ACC_TRM_OFF_STEP_8G_CH2_check\",reverse_ras_result(Vec[71]));\n\t FuncPrint(\"crcdata_072_ACC_TRM_OFF_STEP_8G_CH3_check\",reverse_ras_result(Vec[72]));\n\t FuncPrint(\"crcdata_073_ACC_TRM_OFF_STEP_ALP_8G_CH1_check\",reverse_ras_result(Vec[73]));\n\t FuncPrint(\"crcdata_074_ACC_TRM_OFF_STEP_ALP_8G_CH2_check\",reverse_ras_result(Vec[74]));\n\t FuncPrint(\"crcdata_075_ACC_TRM_OFF_STEP_ALP_8G_CH3_check\",reverse_ras_result(Vec[75]));\n\t FuncPrint(\"crcdata_076_ACC_TRM_OFF_STEP_ALP_32G_CH1_check\",reverse_ras_result(Vec[76]));\n\t FuncPrint(\"crcdata_077_ACC_TRM_OFF_STEP_ALP_32G_CH2_check\",reverse_ras_result(Vec[77]));\n\t FuncPrint(\"crcdata_078_ACC_TRM_OFF_STEP_ALP_32G_CH3_check\",reverse_ras_result(Vec[78]));\n\t FuncPrint(\"crcdata_079_GYR_CROSS_SY_CH12_check\",reverse_ras_result(Vec[79]));\n\t FuncPrint(\"crcdata_080_GYR_CROSS_SY_CH13_check\",reverse_ras_result(Vec[80]));\n\t FuncPrint(\"crcdata_081_GYR_CROSS_SY_CH21_check\",reverse_ras_result(Vec[81]));\n\t FuncPrint(\"crcdata_082_GYR_CROSS_SY_CH23_check\",reverse_ras_result(Vec[82]));\n\t FuncPrint(\"crcdata_083_GYR_CROSS_SY_CH31_check\",reverse_ras_result(Vec[83]));\n\t FuncPrint(\"crcdata_084_GYR_CROSS_SY_CH32_check\",reverse_ras_result(Vec[84]));\n\t FuncPrint(\"crcdata_085_GYR_QUAD_TRM_CH1_check\",reverse_ras_result(Vec[85]));\n\t FuncPrint(\"crcdata_086_GYR_QUAD_TRM_CH2_check\",reverse_ras_result(Vec[86]));\n\t FuncPrint(\"crcdata_087_GYR_QUAD_TRM_CH3_check\",reverse_ras_result(Vec[87]));\n\t FuncPrint(\"crcdata_088_GYR_ALP_TRM_PHI_CH12_check\",reverse_ras_result(Vec[88]));\n\t FuncPrint(\"crcdata_089_GYR_ALP_TRM_PHI_CH23_check\",reverse_ras_result(Vec[89]));\n\t FuncPrint(\"crcdata_090_GYR_ALP_TRM_OFF_CH1_check\",reverse_ras_result(Vec[90]));\n\t FuncPrint(\"crcdata_091_GYR_ALP_TRM_OFF_CH2_check\",reverse_ras_result(Vec[91]));\n\t FuncPrint(\"crcdata_092_GYR_ALP_TRM_OFF_CH3_check\",reverse_ras_result(Vec[92]));\n\t FuncPrint(\"crcdata_093_ANA_TRM_BG_check\",reverse_ras_result(Vec[93]));\n\t FuncPrint(\"crcdata_094_ANA_TRM_PMU_check\",reverse_ras_result(Vec[94]));\n\t FuncPrint(\"crcdata_095_ANA_TRM_PMU1_check\",reverse_ras_result(Vec[95]));\n\t FuncPrint(\"crcdata_096_ANA_TRM_OSC_check\",reverse_ras_result(Vec[96]));\n\t FuncPrint(\"crcdata_097_ANA_TRM_RES_PROG0_check\",reverse_ras_result(Vec[97]));\n\t FuncPrint(\"crcdata_098_ANA_TRM_RES_PROG1_check\",reverse_ras_result(Vec[98]));\n\t FuncPrint(\"crcdata_099_ANA_TRM_RES_PROG2_check\",reverse_ras_result(Vec[99]));\n\t FuncPrint(\"crcdata_100_ANA_TRM_CAP_PROG0_check\",reverse_ras_result(Vec[100]));\n\t FuncPrint(\"crcdata_101_ANA_TRM_CAP_PROG_CH1_check\",reverse_ras_result(Vec[101]));\n\t FuncPrint(\"crcdata_102_ANA_TRM_CAP_PROG_CH2_check\",reverse_ras_result(Vec[102]));\n\t FuncPrint(\"crcdata_103_ANA_TRM_CAP_PROG_CH3_check\",reverse_ras_result(Vec[103]));\n\t FuncPrint(\"crcdata_104_ANA_TRM_CAP_PROG_DRV_check\",reverse_ras_result(Vec[104]));\n\t FuncPrint(\"crcdata_105_ANA_TRM_ACC_CH1_check\",reverse_ras_result(Vec[105]));\n\t FuncPrint(\"crcdata_106_ANA_TRM_ACC_CH2_check\",reverse_ras_result(Vec[106]));\n\t FuncPrint(\"crcdata_107_ANA_TRM_ACC_CH3_check\",reverse_ras_result(Vec[107]));\n\t FuncPrint(\"crcdata_108_GYR_VGM_MON_CTRL_check\",reverse_ras_result(Vec[108]));\n\t FuncPrint(\"crcdata_109_TEMP_TRM_CTRL_check\",reverse_ras_result(Vec[109]));\n\t FuncPrint(\"crcdata_110_ACC_TRM_CFB_check\",reverse_ras_result(Vec[110]));\n\t FuncPrint(\"crcdata_111_ACC_TRM_LOOPG_check\",reverse_ras_result(Vec[111]));\n\t FuncPrint(\"crcdata_112_ACC_TRM_CTRL_check\",reverse_ras_result(Vec[112]));\n\t FuncPrint(\"crcdata_113_GYR_TRM_NOTCH12_GRPC_check\",reverse_ras_result(Vec[113]));\n\t FuncPrint(\"crcdata_114_GYR_TRM_NOTCH3_MISC_check\",reverse_ras_result(Vec[114]));\n\t FuncPrint(\"crcdata_115_GYR_TRM_BYP_MASH_check\",reverse_ras_result(Vec[115]));\n\t FuncPrint(\"crcdata_116_DRV_ST_TRM_check\",reverse_ras_result(Vec[116]));\n\t CRC_OTP_RD[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[117]);\n\t FuncPrint(\"CRC_OTP_RD\",CRC_OTP_RD[CURRENT_SITE_NUMBER()-1]);\n\n int Func_result = rdi.id(\"T20_23_CRC_check_V4_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n\n\n ARRAY_I crc_otp(117);\n for (int i = 0; i < 117; i++)\n {\n \t crc_otp[i] = reverse_ras_result(Vec[i]);\n }\n\n if (CRC_OTP_RD[CURRENT_SITE_NUMBER()-1] != CRC_16_CCITT(crc_otp, 117) ) Func_result=99;\n FuncPrint(\"CRC_CHECK_OTP\",CRC_16_CCITT(crc_otp, 117));\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T20_23_CRC_check_V4\", T20_23_CRC_check_V4);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "from test_sub_functions import *\ncmt('Version info: $Revision: 1 $ $Author: hmf1rt $ $Date: 2024/03/13 13:36:52 GMT $')\ngen_dump()\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T20_30_register_dump_V1: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n static int REG_DUMP_CHIP_ID[xNSitES];\n static int REG_DUMP_ERR_REG[xNSitES];\n static int REG_DUMP_HIF_TRIM_0[xNSitES];\n static int REG_DUMP_HIF_CONFIG[xNSitES];\n static int REG_DUMP_I3C_TC_SYNC_TPH[xNSitES];\n static int REG_DUMP_I3C_TC_SYNC_TU[xNSitES];\n static int REG_DUMP_I3C_TC_SYNC_ODR[xNSitES];\n static int REG_DUMP_I3C_TC_SYNC_DT[xNSitES];\n static int REG_DUMP_I3C_TC_SYNC_ST0[xNSitES];\n static int REG_DUMP_I3C_TC_SYNC_ST1[xNSitES];\n static int REG_DUMP_LEG_ERR_REG[xNSitES];\n static int REG_DUMP_REV_ID[xNSitES];\n static int REG_DUMP_OCP_MASK[xNSitES];\n static int REG_DUMP_CMD[xNSitES];\n static int REG_DUMP_EXT_MODE[xNSitES];\n static int REG_DUMP_STATUS[xNSitES];\n static int REG_DUMP_ACC_DATA_X_LSB[xNSitES];\n static int REG_DUMP_ACC_DATA_X_MSB[xNSitES];\n static int REG_DUMP_ACC_DATA_Y_LSB[xNSitES];\n static int REG_DUMP_ACC_DATA_Y_MSB[xNSitES];\n static int REG_DUMP_ACC_DATA_Z_LSB[xNSitES];\n static int REG_DUMP_ACC_DATA_Z_MSB[xNSitES];\n static int REG_DUMP_GYR_DATA_X_LSB[xNSitES];\n static int REG_DUMP_GYR_DATA_X_MSB[xNSitES];\n static int REG_DUMP_GYR_DATA_Y_LSB[xNSitES];\n static int REG_DUMP_GYR_DATA_Y_MSB[xNSitES];\n static int REG_DUMP_GYR_DATA_Z_LSB[xNSitES];\n static int REG_DUMP_GYR_DATA_Z_MSB[xNSitES];\n static int REG_DUMP_TEMP_DATA[xNSitES];\n static int REG_DUMP_SENSORTIME_DATA_LSB[xNSitES];\n static int REG_DUMP_SENSORTIME_DATA_MSB[xNSitES];\n static int REG_DUMP_MUTE[xNSitES];\n static int REG_DUMP_MCU_GP_0[xNSitES];\n static int REG_DUMP_MCU_GP_1[xNSitES];\n static int REG_DUMP_MCU_GP_2[xNSitES];\n static int REG_DUMP_MCU_GP_STATUS[xNSitES];\n static int REG_DUMP_MCU_GP_DIR[xNSitES];\n static int REG_DUMP_SH_MASK[xNSitES];\n static int REG_DUMP_SH_STATUS[xNSitES];\n static int REG_DUMP_SH_TEMP_DATA[xNSitES];\n static int REG_DUMP_SH_ACC_DATA_X_LSB[xNSitES];\n static int REG_DUMP_SH_ACC_DATA_X_MSB[xNSitES];\n static int REG_DUMP_SH_ACC_DATA_Y_LSB[xNSitES];\n static int REG_DUMP_SH_ACC_DATA_Y_MSB[xNSitES];\n static int REG_DUMP_SH_ACC_DATA_Z_LSB[xNSitES];\n static int REG_DUMP_SH_ACC_DATA_Z_MSB[xNSitES];\n static int REG_DUMP_SH_GYR_DATA_X_LSB[xNSitES];\n static int REG_DUMP_SH_GYR_DATA_X_MSB[xNSitES];\n static int REG_DUMP_SH_GYR_DATA_Y_LSB[xNSitES];\n static int REG_DUMP_SH_GYR_DATA_Y_MSB[xNSitES];\n static int REG_DUMP_SH_GYR_DATA_Z_LSB[xNSitES];\n static int REG_DUMP_SH_GYR_DATA_Z_MSB[xNSitES];\n static int REG_DUMP_MCU_ACC_DATA_X_LSB[xNSitES];\n static int REG_DUMP_MCU_ACC_DATA_X_MSB[xNSitES];\n static int REG_DUMP_MCU_ACC_DATA_Y_LSB[xNSitES];\n static int REG_DUMP_MCU_ACC_DATA_Y_MSB[xNSitES];\n static int REG_DUMP_MCU_ACC_DATA_Z_LSB[xNSitES];\n static int REG_DUMP_MCU_ACC_DATA_Z_MSB[xNSitES];\n static int REG_DUMP_MCU_GYR_DATA_X_LSB[xNSitES];\n static int REG_DUMP_MCU_GYR_DATA_X_MSB[xNSitES];\n static int REG_DUMP_MCU_GYR_DATA_Y_LSB[xNSitES];\n static int REG_DUMP_MCU_GYR_DATA_Y_MSB[xNSitES];\n static int REG_DUMP_MCU_GYR_DATA_Z_LSB[xNSitES];\n static int REG_DUMP_MCU_GYR_DATA_Z_MSB[xNSitES];\n static int REG_DUMP_RAW_SENSORTIME_LSB[xNSitES];\n static int REG_DUMP_RAW_SENSORTIME_MSB[xNSitES];\n static int REG_DUMP_LEG_STATUS[xNSitES];\n static int REG_DUMP_LEG_ACC_DATA_X[xNSitES];\n static int REG_DUMP_LEG_ACC_DATA_Y[xNSitES];\n static int REG_DUMP_LEG_ACC_DATA_Z[xNSitES];\n static int REG_DUMP_LEG_GYR_DATA_X[xNSitES];\n static int REG_DUMP_LEG_GYR_DATA_Y[xNSitES];\n static int REG_DUMP_LEG_GYR_DATA_Z[xNSitES];\n static int REG_DUMP_LEG_TEMP_DATA[xNSitES];\n static int REG_DUMP_LEG_SENSORTIME_DATA_LSB[xNSitES];\n static int REG_DUMP_LEG_SENSORTIME_DATA_MSB[xNSitES];\n static int REG_DUMP_SAT_FLAGS[xNSitES];\n static int REG_DUMP_PP_ACTIVE_STATUS[xNSitES];\n static int REG_DUMP_MCU_GP_OIS_0_SYS[xNSitES];\n static int REG_DUMP_MCU_GP_OIS_1_SYS[xNSitES];\n static int REG_DUMP_MCU_GP_OIS_STATUS_SYS[xNSitES];\n static int REG_DUMP_MCU_GP_OIS_DIR[xNSitES];\n static int REG_DUMP_MCU_OIS_STATUS_SYS[xNSitES];\n static int REG_DUMP_MUTE_OIS[xNSitES];\n static int REG_DUMP_SH_MASK_OIS[xNSitES];\n static int REG_DUMP_SH_STATUS_OIS[xNSitES];\n static int REG_DUMP_SH_OIS_ACC_DATA_X[xNSitES];\n static int REG_DUMP_SH_OIS_ACC_DATA_Y[xNSitES];\n static int REG_DUMP_SH_OIS_ACC_DATA_Z[xNSitES];\n static int REG_DUMP_SH_OIS_GYR_DATA_X[xNSitES];\n static int REG_DUMP_SH_OIS_GYR_DATA_Y[xNSitES];\n static int REG_DUMP_SH_OIS_GYR_DATA_Z[xNSitES];\n static int REG_DUMP_INT_STATUS_INT1[xNSitES];\n static int REG_DUMP_INT_STATUS_INT2[xNSitES];\n static int REG_DUMP_INT_STATUS_IBI[xNSitES];\n static int REG_DUMP_INT_CONF[xNSitES];\n static int REG_DUMP_INT_MAP_HW[xNSitES];\n static int REG_DUMP_INT_MAP_MCU[xNSitES];\n static int REG_DUMP_INT_MCU_SET[xNSitES];\n static int REG_DUMP_INT_IBI_MANDATORY[xNSitES];\n static int REG_DUMP_INT_IBI_CCC_GETSTATUS[xNSitES];\n static int REG_DUMP_FIFO_FILL_LVL[xNSitES];\n static int REG_DUMP_FIFO_DATA[xNSitES];\n static int REG_DUMP_FIFO_WATERMARK[xNSitES];\n static int REG_DUMP_FIFO_CONF[xNSitES];\n static int REG_DUMP_FIFO_CTRL[xNSitES];\n static int REG_DUMP_OIS_CONF[xNSitES];\n static int REG_DUMP_FCU_TRIM_0[xNSitES];\n static int REG_DUMP_FCU_TRIM_1[xNSitES];\n static int REG_DUMP_WLT_TEST_CNT[xNSitES];\n static int REG_DUMP_FCU_TEST_CONF[xNSitES];\n static int REG_DUMP_FCU_TEST_CMD[xNSitES];\n static int REG_DUMP_ALT_CMD[xNSitES];\n static int REG_DUMP_MCU_DP_CONF[xNSitES];\n static int REG_DUMP_MCU_PP_CONF[xNSitES];\n static int REG_DUMP_FILTER_CONF[xNSitES];\n static int REG_DUMP_ACC_CONF[xNSitES];\n static int REG_DUMP_GYR_CONF[xNSitES];\n static int REG_DUMP_ALT_FILTER_CONF[xNSitES];\n static int REG_DUMP_ALT_ACC_CONF[xNSitES];\n static int REG_DUMP_ALT_GYR_CONF[xNSitES];\n static int REG_DUMP_ALT_CONF[xNSitES];\n static int REG_DUMP_ALT_STATUS[xNSitES];\n static int REG_DUMP_SELFTEST_STATUS[xNSitES];\n static int REG_DUMP_FCU_DBG_0[xNSitES];\n static int REG_DUMP_FCU_DBG_1[xNSitES];\n static int REG_DUMP_I3C_CCC_GETXTIME[xNSitES];\n static int REG_DUMP_FILTER_STATUS[xNSitES];\n static int REG_DUMP_ACC_STATUS[xNSitES];\n static int REG_DUMP_GYR_STATUS[xNSitES];\n static int REG_DUMP_LEGACY_CONF[xNSitES];\n static int REG_DUMP_PWR_CONF[xNSitES];\n static int REG_DUMP_MCU_PRIV_UNLOCK[xNSitES];\n static int REG_DUMP_MCU_PRIV_STAT[xNSitES];\n static int REG_DUMP_MCU_PRIV_LOCK[xNSitES];\n static int REG_DUMP_MCU_CONF[xNSitES];\n static int REG_DUMP_MCU_CTRL[xNSitES];\n static int REG_DUMP_MCU_INT_STATUS1[xNSitES];\n static int REG_DUMP_MCU_INT_STATUS2[xNSitES];\n static int REG_DUMP_MCU_INT_EN1[xNSitES];\n static int REG_DUMP_MCU_INT_EN2[xNSitES];\n static int REG_DUMP_MCU_INT_DIS1[xNSitES];\n static int REG_DUMP_MCU_INT_DIS2[xNSitES];\n static int REG_DUMP_MCU_GPT_CSR[xNSitES];\n static int REG_DUMP_MCU_GPT_RVR[xNSitES];\n static int REG_DUMP_MCU_GPT_CVR[xNSitES];\n static int REG_DUMP_MCU_DMA_LOB[xNSitES];\n static int REG_DUMP_MCU_DMA_UPB[xNSitES];\n static int REG_DUMP_MCU_SW_STATUS0[xNSitES];\n static int REG_DUMP_MCU_SW_STATUS1[xNSitES];\n static int REG_DUMP_MCU_SW_STATUS2[xNSitES];\n static int REG_DUMP_MCU_SW_STATUS3[xNSitES];\n static int REG_DUMP_MCU_MEM_PWR[xNSitES];\n static int REG_DUMP_MCU_MEM_MARGIN_TRIM[xNSitES];\n static int REG_DUMP_MCU_CMD_FEATURE_TRIG[xNSitES];\n static int REG_DUMP_MCU_GLOB_CTRL[xNSitES];\n static int REG_DUMP_MCU_DMA_CTRL[xNSitES];\n static int REG_DUMP_MCU_DMA_WDATA[xNSitES];\n static int REG_DUMP_MCU_DMA_RDATA[xNSitES];\n static int REG_DUMP_MCU_STATUS[xNSitES];\n static int REG_DUMP_MCU_PC[xNSitES];\n static int REG_DUMP_MCU_SP[xNSitES];\n static int REG_DUMP_MCU_LR[xNSitES];\n static int REG_DUMP_MCU_SR_PIPE[xNSitES];\n static int REG_DUMP_MCU_TEST[xNSitES];\n static int REG_DUMP_MCU_DEBUG[xNSitES];\n static int REG_DUMP_MCU_DMA_DEBUG[xNSitES];\n static int REG_DUMP_LPWUP_EN[xNSitES];\n static int REG_DUMP_LPWUP_CFG[xNSitES];\n static int REG_DUMP_LPWUP_STATUS[xNSitES];\n static int REG_DUMP_ACC_AASR_CONF_0[xNSitES];\n static int REG_DUMP_ACC_AASR_CONF_1[xNSitES];\n static int REG_DUMP_ACC_AASR_STATUS[xNSitES];\n static int REG_DUMP_IO_PAD_TRM[xNSitES];\n static int REG_DUMP_IO_TEST_IF[xNSitES];\n static int REG_DUMP_IO_INT_CTRL[xNSitES];\n static int REG_DUMP_IO_IF_CONF[xNSitES];\n static int REG_DUMP_IO_PAD_STRENGTH[xNSitES];\n static int REG_DUMP_IO_ODR_DEVIATION[xNSitES];\n static int REG_DUMP_INT_IO_PAD_STRENGTH0[xNSitES];\n static int REG_DUMP_INT_IO_PAD_STRENGTH1[xNSitES];\n static int REG_DUMP_GYR_SCB_PHI_A0_CH1[xNSitES];\n static int REG_DUMP_GYR_SCB_PHI_A0_CH2[xNSitES];\n static int REG_DUMP_GYR_SCB_PHI_A0_CH3[xNSitES];\n static int REG_DUMP_GYR_SCB_PHI_A1_CH1[xNSitES];\n static int REG_DUMP_GYR_SCB_PHI_A1_CH2[xNSitES];\n static int REG_DUMP_GYR_SCB_PHI_A1_CH3[xNSitES];\n static int REG_DUMP_GYR_SCB_OFF_B0_CH1[xNSitES];\n static int REG_DUMP_GYR_SCB_OFF_B0_CH2[xNSitES];\n static int REG_DUMP_GYR_SCB_OFF_B0_CH3[xNSitES];\n static int REG_DUMP_GYR_SCB_OFF_B1_CH1[xNSitES];\n static int REG_DUMP_GYR_SCB_OFF_B1_CH2[xNSitES];\n static int REG_DUMP_GYR_SCB_OFF_B1_CH3[xNSitES];\n static int REG_DUMP_GYR_TRM_PHI_A0_CH1[xNSitES];\n static int REG_DUMP_GYR_TRM_PHI_A1_CH1[xNSitES];\n static int REG_DUMP_GYR_TRM_PHI_A0_CH2[xNSitES];\n static int REG_DUMP_GYR_TRM_PHI_A1_CH2[xNSitES];\n static int REG_DUMP_GYR_TRM_PHI_A0_CH3[xNSitES];\n static int REG_DUMP_GYR_TRM_PHI_A1_CH3[xNSitES];\n static int REG_DUMP_GYR_TRM_PHI_A2_CH1[xNSitES];\n static int REG_DUMP_GYR_TRM_PHI_A2_CH2[xNSitES];\n static int REG_DUMP_GYR_TRM_PHI_A2_CH3[xNSitES];\n static int REG_DUMP_GYR_TRM_OFF_B0_CH1[xNSitES];\n static int REG_DUMP_GYR_TRM_OFF_B1_CH1[xNSitES];\n static int REG_DUMP_GYR_TRM_OFF_B2_CH1_CH2[xNSitES];\n static int REG_DUMP_GYR_TRM_OFF_B0_CH2[xNSitES];\n static int REG_DUMP_GYR_TRM_OFF_B1_CH2[xNSitES];\n static int REG_DUMP_GYR_TRM_OFF_B2_CH2_CH3[xNSitES];\n static int REG_DUMP_GYR_TRM_OFF_B0_CH3[xNSitES];\n static int REG_DUMP_GYR_TRM_OFF_B1_CH3[xNSitES];\n static int REG_DUMP_GYR_TRM_DGAIN_S0_CH1[xNSitES];\n static int REG_DUMP_GYR_ACC_TRM_DGAIN_S1_CH1[xNSitES];\n static int REG_DUMP_GYR_TRM_DGAIN_S0_CH2[xNSitES];\n static int REG_DUMP_GYR_TRM_DGAIN_S1_CH2_CH3[xNSitES];\n static int REG_DUMP_GYR_TRM_DGAIN_S0_CH3[xNSitES];\n static int REG_DUMP_ACC_TRM_OFF_B0_CH1[xNSitES];\n static int REG_DUMP_ACC_TRM_OFF_B1_B2_CH1[xNSitES];\n static int REG_DUMP_ACC_TRM_OFF_B0_CH2[xNSitES];\n static int REG_DUMP_ACC_TRM_OFF_B1_B2_CH2[xNSitES];\n static int REG_DUMP_ACC_TRM_OFF_B0_CH3[xNSitES];\n static int REG_DUMP_ACC_TRM_OFF_B1_B2_CH3[xNSitES];\n static int REG_DUMP_ACC_TRM_DGAIN_S0_CH1[xNSitES];\n static int REG_DUMP_ACC_TRM_DGAIN_S0_CH2[xNSitES];\n static int REG_DUMP_ACC_TRM_DGAIN_S0_CH3[xNSitES];\n static int REG_DUMP_ACC_TRM_DGAIN_S1_CH2_CH3[xNSitES];\n static int REG_DUMP_TEMP_TRM_OFF_DGAIN[xNSitES];\n static int REG_DUMP_TEMP_TRM_OFF_DT[xNSitES];\n static int REG_DUMP_TEMP_TRM_BG_OFF_DGAIN_NORM[xNSitES];\n static int REG_DUMP_TEMP_TEST_TADC[xNSitES];\n static int REG_DUMP_TEMP_TEST[xNSitES];\n static int REG_DUMP_TEMP_DT_HI[xNSitES];\n static int REG_DUMP_TEMP_DT_LO[xNSitES];\n static int REG_DUMP_TEMP_FWSPARE0_RO[xNSitES];\n static int REG_DUMP_INTERNAL_TEMP_AXIS_CONF0[xNSitES];\n static int REG_DUMP_INTERNAL_TEMP_AXIS_CONF1[xNSitES];\n static int REG_DUMP_TEMP_AXIS_CONF[xNSitES];\n static int REG_DUMP_GYR_USR_DGAIN_S0_X[xNSitES];\n static int REG_DUMP_GYR_USR_DGAIN_S0_Y[xNSitES];\n static int REG_DUMP_GYR_USR_DGAIN_S0_Z[xNSitES];\n static int REG_DUMP_ACC_USR_DGAIN_S0_X[xNSitES];\n static int REG_DUMP_ACC_USR_DGAIN_S0_Y[xNSitES];\n static int REG_DUMP_ACC_USR_DGAIN_S0_Z[xNSitES];\n static int REG_DUMP_ACC_CROSS_SY_CH12[xNSitES];\n static int REG_DUMP_ACC_CROSS_SY_CH13[xNSitES];\n static int REG_DUMP_ACC_CROSS_SY_CH21[xNSitES];\n static int REG_DUMP_ACC_CROSS_SY_CH23[xNSitES];\n static int REG_DUMP_ACC_CROSS_SY_CH31[xNSitES];\n static int REG_DUMP_ACC_CROSS_SY_CH32[xNSitES];\n static int REG_DUMP_ACC_TRM_DGAIN_8G_CH12[xNSitES];\n static int REG_DUMP_ACC_TRM_DGAIN_8G_CH3[xNSitES];\n static int REG_DUMP_ACC_TRM_OFF_STEP_8G_CH1[xNSitES];\n static int REG_DUMP_ACC_TRM_OFF_STEP_8G_CH2[xNSitES];\n static int REG_DUMP_ACC_TRM_OFF_STEP_8G_CH3[xNSitES];\n static int REG_DUMP_ACC_TRM_OFF_STEP_ALP_8G_CH1[xNSitES];\n static int REG_DUMP_ACC_TRM_OFF_STEP_ALP_8G_CH2[xNSitES];\n static int REG_DUMP_ACC_TRM_OFF_STEP_ALP_8G_CH3[xNSitES];\n static int REG_DUMP_ACC_TRM_OFF_STEP_ALP_32G_CH1[xNSitES];\n static int REG_DUMP_ACC_TRM_OFF_STEP_ALP_32G_CH2[xNSitES];\n static int REG_DUMP_ACC_TRM_OFF_STEP_ALP_32G_CH3[xNSitES];\n static int REG_DUMP_ACC_COMP_CONF[xNSitES];\n static int REG_DUMP_TEMP_ACC_OFF_CH1_MSB[xNSitES];\n static int REG_DUMP_TEMP_ACC_OFF_CH1_LSB[xNSitES];\n static int REG_DUMP_TEMP_ACC_OFF_CH2_MSB[xNSitES];\n static int REG_DUMP_TEMP_ACC_OFF_CH2_LSB[xNSitES];\n static int REG_DUMP_TEMP_ACC_OFF_CH3_MSB[xNSitES];\n static int REG_DUMP_TEMP_ACC_OFF_CH3_LSB[xNSitES];\n static int REG_DUMP_TEMP_ACC_GAIN_CH1_MSB[xNSitES];\n static int REG_DUMP_TEMP_ACC_GAIN_CH1_LSB[xNSitES];\n static int REG_DUMP_TEMP_ACC_GAIN_CH2_MSB[xNSitES];\n static int REG_DUMP_TEMP_ACC_GAIN_CH2_LSB[xNSitES];\n static int REG_DUMP_TEMP_ACC_GAIN_CH3_MSB[xNSitES];\n static int REG_DUMP_TEMP_ACC_GAIN_CH3_LSB[xNSitES];\n static int REG_DUMP_ACC_USR_OFF_32G_X[xNSitES];\n static int REG_DUMP_ACC_USR_OFF_32G_Y[xNSitES];\n static int REG_DUMP_ACC_USR_OFF_32G_Z[xNSitES];\n static int REG_DUMP_ACC_USR_OFF_8G_X[xNSitES];\n static int REG_DUMP_ACC_USR_OFF_8G_Y[xNSitES];\n static int REG_DUMP_ACC_USR_OFF_8G_Z[xNSitES];\n static int REG_DUMP_ACC_COMP_CONF_USR[xNSitES];\n static int REG_DUMP_GYR_CROSS_SY_CH12[xNSitES];\n static int REG_DUMP_GYR_CROSS_SY_CH13[xNSitES];\n static int REG_DUMP_GYR_CROSS_SY_CH21[xNSitES];\n static int REG_DUMP_GYR_CROSS_SY_CH23[xNSitES];\n static int REG_DUMP_GYR_CROSS_SY_CH31[xNSitES];\n static int REG_DUMP_GYR_CROSS_SY_CH32[xNSitES];\n static int REG_DUMP_GYR_QUAD_TRM_CH1[xNSitES];\n static int REG_DUMP_GYR_QUAD_TRM_CH2[xNSitES];\n static int REG_DUMP_GYR_QUAD_TRM_CH3[xNSitES];\n static int REG_DUMP_GYR_COMP_CONF[xNSitES];\n static int REG_DUMP_TEMP_GYR_OFF_CH1_MSB[xNSitES];\n static int REG_DUMP_TEMP_GYR_OFF_CH1_LSB[xNSitES];\n static int REG_DUMP_TEMP_GYR_OFF_CH2_MSB[xNSitES];\n static int REG_DUMP_TEMP_GYR_OFF_CH2_LSB[xNSitES];\n static int REG_DUMP_TEMP_GYR_OFF_CH3_MSB[xNSitES];\n static int REG_DUMP_TEMP_GYR_OFF_CH3_LSB[xNSitES];\n static int REG_DUMP_TEMP_GYR_GAIN_CH1_MSB[xNSitES];\n static int REG_DUMP_TEMP_GYR_GAIN_CH1_LSB[xNSitES];\n static int REG_DUMP_TEMP_GYR_GAIN_CH2_MSB[xNSitES];\n static int REG_DUMP_TEMP_GYR_GAIN_CH2_LSB[xNSitES];\n static int REG_DUMP_TEMP_GYR_GAIN_CH3_MSB[xNSitES];\n static int REG_DUMP_TEMP_GYR_GAIN_CH3_LSB[xNSitES];\n static int REG_DUMP_TEMP_GYR_PHI_CH1_MSB[xNSitES];\n static int REG_DUMP_TEMP_GYR_PHI_CH1_LSB[xNSitES];\n static int REG_DUMP_TEMP_GYR_PHI_CH2_MSB[xNSitES];\n static int REG_DUMP_TEMP_GYR_PHI_CH2_LSB[xNSitES];\n static int REG_DUMP_TEMP_GYR_PHI_CH3_MSB[xNSitES];\n static int REG_DUMP_TEMP_GYR_PHI_CH3_LSB[xNSitES];\n static int REG_DUMP_GYR_ALP_TRM_PHI_CH12[xNSitES];\n static int REG_DUMP_GYR_ALP_TRM_PHI_CH23[xNSitES];\n static int REG_DUMP_GYR_ALP_TRM_OFF_CH1[xNSitES];\n static int REG_DUMP_GYR_ALP_TRM_OFF_CH2[xNSitES];\n static int REG_DUMP_GYR_ALP_TRM_OFF_CH3[xNSitES];\n static int REG_DUMP_GYR_USR_OFF_B0_X[xNSitES];\n static int REG_DUMP_GYR_USR_OFF_B0_Y[xNSitES];\n static int REG_DUMP_GYR_USR_OFF_B0_Z[xNSitES];\n static int REG_DUMP_GYR_COMP_CONF_USR[xNSitES];\n static int REG_DUMP_ANA_TRM_BG[xNSitES];\n static int REG_DUMP_ANA_TRM_PMU[xNSitES];\n static int REG_DUMP_ANA_TRM_PMU1[xNSitES];\n static int REG_DUMP_ANA_TRM_OSC[xNSitES];\n static int REG_DUMP_ANA_TRM_RES_PROG0[xNSitES];\n static int REG_DUMP_ANA_TRM_RES_PROG1[xNSitES];\n static int REG_DUMP_ANA_TRM_RES_PROG2[xNSitES];\n static int REG_DUMP_ANA_TRM_CAP_PROG0[xNSitES];\n static int REG_DUMP_ANA_TRM_CAP_PROG_CH1[xNSitES];\n static int REG_DUMP_ANA_TRM_CAP_PROG_CH2[xNSitES];\n static int REG_DUMP_ANA_TRM_CAP_PROG_CH3[xNSitES];\n static int REG_DUMP_ANA_TRM_CAP_PROG_DRV[xNSitES];\n static int REG_DUMP_ANA_TRM_ACC_CH1[xNSitES];\n static int REG_DUMP_ANA_TRM_ACC_CH2[xNSitES];\n static int REG_DUMP_ANA_TRM_ACC_CH3[xNSitES];\n static int REG_DUMP_ANA_TEST_PWR[xNSitES];\n static int REG_DUMP_GYR_TEST_EN[xNSitES];\n static int REG_DUMP_GYR_TEST_WFR[xNSitES];\n static int REG_DUMP_GYR_TEST_INT_SEL[xNSitES];\n static int REG_DUMP_TEMP_TEST_ADC[xNSitES];\n static int REG_DUMP_GYR_TEST_AA_AI[xNSitES];\n static int REG_DUMP_GYR_TEST_OWR1[xNSitES];\n static int REG_DUMP_GYR_TEST_OWR2[xNSitES];\n static int REG_DUMP_GYR_TEST_OWR_RST[xNSitES];\n static int REG_DUMP_PMU_TEST_OWR[xNSitES];\n static int REG_DUMP_PMU_TEST_DPWR_CTRL[xNSitES];\n static int REG_DUMP_PMU_TEST_MISC[xNSitES];\n static int REG_DUMP_GYR_VGM_MON_CTRL[xNSitES];\n static int REG_DUMP_PMU_ERROR[xNSitES];\n static int REG_DUMP_STATUS_CORE_FSM[xNSitES];\n static int REG_DUMP_STATUS_GYR_FSM[xNSitES];\n static int REG_DUMP_STATUS_PMOD0[xNSitES];\n static int REG_DUMP_STATUS_PMOD1[xNSitES];\n static int REG_DUMP_STATUS_PMOD2[xNSitES];\n static int REG_DUMP_STATUS_PMOD3[xNSitES];\n static int REG_DUMP_STATUS_DPWR[xNSitES];\n static int REG_DUMP_TEMP_TRM_CTRL[xNSitES];\n static int REG_DUMP_TEMP_TEST_FSM[xNSitES];\n static int REG_DUMP_ACC_TRM_CFB[xNSitES];\n static int REG_DUMP_ACC_TRM_LOOPG[xNSitES];\n static int REG_DUMP_ACC_TRM_CTRL[xNSitES];\n static int REG_DUMP_ACC_TEST_ST_CTRL[xNSitES];\n static int REG_DUMP_ACC_TEST_ST_LFSR_SEED[xNSitES];\n static int REG_DUMP_ACC_TEST_ST_LFSR_VAL[xNSitES];\n static int REG_DUMP_ACC_TEST_CTRL[xNSitES];\n static int REG_DUMP_ACC_AFE_AASR_CONF[xNSitES];\n static int REG_DUMP_GYR_TRM_NOTCH12_GRPC[xNSitES];\n static int REG_DUMP_GYR_TRM_NOTCH3_MISC[xNSitES];\n static int REG_DUMP_GYR_TRM_BYP_MASH[xNSitES];\n static int REG_DUMP_GYR_TEST_TOSK[xNSitES];\n static int REG_DUMP_GYR_TEST_QUAD1_LSB[xNSitES];\n static int REG_DUMP_GYR_TEST_QUAD1_MSB[xNSitES];\n static int REG_DUMP_GYR_TEST_QUAD2_LSB[xNSitES];\n static int REG_DUMP_GYR_TEST_QUAD2_MSB[xNSitES];\n static int REG_DUMP_GYR_TEST_QUAD3_LSB[xNSitES];\n static int REG_DUMP_GYR_TEST_QUAD3_MSB[xNSitES];\n static int REG_DUMP_GYR_TEST_FSM[xNSitES];\n static int REG_DUMP_GYR_TEST_FILT[xNSitES];\n static int REG_DUMP_GYR_TEST_IQMOD_SIN1[xNSitES];\n static int REG_DUMP_GYR_TEST_IQMOD_SIN2[xNSitES];\n static int REG_DUMP_GYR_TEST_IQMOD_COS1[xNSitES];\n static int REG_DUMP_GYR_TEST_IQMOD_COS2[xNSitES];\n static int REG_DUMP_GYR_TEST_CLAMP[xNSitES];\n static int REG_DUMP_DRV_ST_TRM[xNSitES];\n static int REG_DUMP_DRV_ST_TEST_STATUS1[xNSitES];\n static int REG_DUMP_DRV_ST_TEST_STATUS2[xNSitES];\n static int REG_DUMP_DRV_ST_TEST_STATUS3[xNSitES];\n static int REG_DUMP_BOOT_RANGE[xNSitES];\n static int REG_DUMP_BOOT_CMD[xNSitES];\n static int REG_DUMP_BOOT_STATUS[xNSitES];\n static int REG_DUMP_BOOT_DBG[xNSitES];\n static int REG_DUMP_BOOT_LAST_DATA[xNSitES];\n static int REG_DUMP_OTP_ADDR[xNSitES];\n static int REG_DUMP_OTP_DATA[xNSitES];\n static int REG_DUMP_OTP_CMD[xNSitES];\n static int REG_DUMP_OTP_IDX[xNSitES];\n static int REG_DUMP_OTP_PROG_EN[xNSitES];\n static int REG_DUMP_OTP_STATUS[xNSitES];\n static int REG_DUMP_OTP_TEST_CFG[xNSitES];\n static int REG_DUMP_OTP_TEST_CLVWR[xNSitES];\n static int REG_DUMP_OTP_TEST_DBG[xNSitES];\n static int REG_DUMP_NVM_DIR_ADDR[xNSitES];\n static int REG_DUMP_NVM_DIR_DATA[xNSitES];\n static int REG_DUMP_NVM_DIR_CMD[xNSitES];\n static int REG_DUMP_NVM_DIR_STATUS[xNSitES];\n static int REG_DUMP_NVM_TEST_NVMCTRL_STATE[xNSitES];\n static int REG_DUMP_NVM_TEST_CTRL[xNSitES];\n static int REG_DUMP_NVM_WRITE_PROT_CTRL[xNSitES];\n static int REG_DUMP_NVM_TEST[xNSitES];\n static int REG_DUMP_DTB3[xNSitES];\n static int REG_DUMP_DTB1[xNSitES];\n static int REG_DUMP_FASTSO_CONF[xNSitES];\n static int REG_DUMP_TEST_SCAN[xNSitES];\n static int REG_DUMP_TEST_I2C_DEL[xNSitES];\n static int REG_DUMP_TM_ADDR[xNSitES];\n static int REG_DUMP_TM_CONF[xNSitES];\n static int REG_DUMP_TM_GYR[xNSitES];\n static int REG_DUMP_TM_TEMP[xNSitES];\n static int REG_DUMP_TM_PIN[xNSitES];\n static int REG_DUMP_TM_PWR[xNSitES];\n static int REG_DUMP_LUT_MEM2REG_IN[xNSitES];\n static int REG_DUMP_LUT_MEM2REG_OUT[xNSitES];\n static int REG_DUMP_LUT_DUMMY[xNSitES];\n static int REG_DUMP_SUP_CRC[xNSitES];\n static int REG_DUMP_SUP_CRC_IN[xNSitES];\n static int REG_DUMP_ARB_FORCE_CTRL[xNSitES];\n // Auto_Code_Variable_define\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T20_30_register_dump_V1_PAT_id\");\n rdi.digCap(\"T20_30_register_dump_V1_Digcap_id\").label(s_label_name)\n .pin(\"SDO\").capMode(TA::SER).samples(16*422).bitPerWord(16)\n .execute();\n RDI_END();\n\n // Auto_Code_Execution_Part\n\n\n\n ON_FIRST_INVOCATION_END();\n ARRAY_I Vec=rdi.id(\"T20_30_register_dump_V1_Digcap_id\").getVector();\n REG_DUMP_CHIP_ID[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[0]);\n REG_DUMP_ERR_REG[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[1]);\n REG_DUMP_HIF_TRIM_0[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[2]);\n REG_DUMP_HIF_CONFIG[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[3]);\n REG_DUMP_I3C_TC_SYNC_TPH[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[4]);\n REG_DUMP_I3C_TC_SYNC_TU[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[5]);\n REG_DUMP_I3C_TC_SYNC_ODR[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[6]);\n REG_DUMP_I3C_TC_SYNC_DT[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[7]);\n REG_DUMP_I3C_TC_SYNC_ST0[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[8]);\n REG_DUMP_I3C_TC_SYNC_ST1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[9]);\n REG_DUMP_LEG_ERR_REG[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[10]);\n REG_DUMP_REV_ID[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[11]);\n REG_DUMP_OCP_MASK[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[12]);\n REG_DUMP_CMD[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[13]);\n REG_DUMP_EXT_MODE[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[14]);\n REG_DUMP_STATUS[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[15]);\n REG_DUMP_ACC_DATA_X_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[16]);\n REG_DUMP_ACC_DATA_X_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[17]);\n REG_DUMP_ACC_DATA_Y_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[18]);\n REG_DUMP_ACC_DATA_Y_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[19]);\n REG_DUMP_ACC_DATA_Z_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[20]);\n REG_DUMP_ACC_DATA_Z_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[21]);\n REG_DUMP_GYR_DATA_X_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[22]);\n REG_DUMP_GYR_DATA_X_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[23]);\n REG_DUMP_GYR_DATA_Y_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[24]);\n REG_DUMP_GYR_DATA_Y_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[25]);\n REG_DUMP_GYR_DATA_Z_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[26]);\n REG_DUMP_GYR_DATA_Z_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[27]);\n REG_DUMP_TEMP_DATA[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[28]);\n REG_DUMP_SENSORTIME_DATA_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[29]);\n REG_DUMP_SENSORTIME_DATA_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[30]);\n REG_DUMP_MUTE[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[31]);\n REG_DUMP_MCU_GP_0[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[32]);\n REG_DUMP_MCU_GP_1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[33]);\n REG_DUMP_MCU_GP_2[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[34]);\n REG_DUMP_MCU_GP_STATUS[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[35]);\n REG_DUMP_MCU_GP_DIR[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[36]);\n REG_DUMP_SH_MASK[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[37]);\n REG_DUMP_SH_STATUS[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[38]);\n REG_DUMP_SH_TEMP_DATA[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[39]);\n REG_DUMP_SH_ACC_DATA_X_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[40]);\n REG_DUMP_SH_ACC_DATA_X_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[41]);\n REG_DUMP_SH_ACC_DATA_Y_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[42]);\n REG_DUMP_SH_ACC_DATA_Y_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[43]);\n REG_DUMP_SH_ACC_DATA_Z_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[44]);\n REG_DUMP_SH_ACC_DATA_Z_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[45]);\n REG_DUMP_SH_GYR_DATA_X_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[46]);\n REG_DUMP_SH_GYR_DATA_X_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[47]);\n REG_DUMP_SH_GYR_DATA_Y_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[48]);\n REG_DUMP_SH_GYR_DATA_Y_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[49]);\n REG_DUMP_SH_GYR_DATA_Z_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[50]);\n REG_DUMP_SH_GYR_DATA_Z_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[51]);\n REG_DUMP_MCU_ACC_DATA_X_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[52]);\n REG_DUMP_MCU_ACC_DATA_X_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[53]);\n REG_DUMP_MCU_ACC_DATA_Y_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[54]);\n REG_DUMP_MCU_ACC_DATA_Y_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[55]);\n REG_DUMP_MCU_ACC_DATA_Z_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[56]);\n REG_DUMP_MCU_ACC_DATA_Z_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[57]);\n REG_DUMP_MCU_GYR_DATA_X_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[58]);\n REG_DUMP_MCU_GYR_DATA_X_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[59]);\n REG_DUMP_MCU_GYR_DATA_Y_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[60]);\n REG_DUMP_MCU_GYR_DATA_Y_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[61]);\n REG_DUMP_MCU_GYR_DATA_Z_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[62]);\n REG_DUMP_MCU_GYR_DATA_Z_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[63]);\n REG_DUMP_RAW_SENSORTIME_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[64]);\n REG_DUMP_RAW_SENSORTIME_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[65]);\n REG_DUMP_LEG_STATUS[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[66]);\n REG_DUMP_LEG_ACC_DATA_X[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[67]);\n REG_DUMP_LEG_ACC_DATA_Y[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[68]);\n REG_DUMP_LEG_ACC_DATA_Z[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[69]);\n REG_DUMP_LEG_GYR_DATA_X[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[70]);\n REG_DUMP_LEG_GYR_DATA_Y[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[71]);\n REG_DUMP_LEG_GYR_DATA_Z[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[72]);\n REG_DUMP_LEG_TEMP_DATA[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[73]);\n REG_DUMP_LEG_SENSORTIME_DATA_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[74]);\n REG_DUMP_LEG_SENSORTIME_DATA_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[75]);\n REG_DUMP_SAT_FLAGS[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[76]);\n REG_DUMP_PP_ACTIVE_STATUS[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[77]);\n REG_DUMP_MCU_GP_OIS_0_SYS[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[78]);\n REG_DUMP_MCU_GP_OIS_1_SYS[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[79]);\n REG_DUMP_MCU_GP_OIS_STATUS_SYS[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[80]);\n REG_DUMP_MCU_GP_OIS_DIR[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[81]);\n REG_DUMP_MCU_OIS_STATUS_SYS[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[82]);\n REG_DUMP_MUTE_OIS[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[83]);\n REG_DUMP_SH_MASK_OIS[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[84]);\n REG_DUMP_SH_STATUS_OIS[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[85]);\n REG_DUMP_SH_OIS_ACC_DATA_X[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[86]);\n REG_DUMP_SH_OIS_ACC_DATA_Y[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[87]);\n REG_DUMP_SH_OIS_ACC_DATA_Z[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[88]);\n REG_DUMP_SH_OIS_GYR_DATA_X[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[89]);\n REG_DUMP_SH_OIS_GYR_DATA_Y[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[90]);\n REG_DUMP_SH_OIS_GYR_DATA_Z[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[91]);\n REG_DUMP_INT_STATUS_INT1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[92]);\n REG_DUMP_INT_STATUS_INT2[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[93]);\n REG_DUMP_INT_STATUS_IBI[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[94]);\n REG_DUMP_INT_CONF[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[95]);\n REG_DUMP_INT_MAP_HW[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[96]);\n REG_DUMP_INT_MAP_MCU[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[97]);\n REG_DUMP_INT_MCU_SET[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[98]);\n REG_DUMP_INT_IBI_MANDATORY[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[99]);\n REG_DUMP_INT_IBI_CCC_GETSTATUS[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[100]);\n REG_DUMP_FIFO_FILL_LVL[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[101]);\n REG_DUMP_FIFO_DATA[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[102]);\n REG_DUMP_FIFO_WATERMARK[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[103]);\n REG_DUMP_FIFO_CONF[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[104]);\n REG_DUMP_FIFO_CTRL[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[105]);\n REG_DUMP_OIS_CONF[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[106]);\n REG_DUMP_FCU_TRIM_0[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[107]);\n REG_DUMP_FCU_TRIM_1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[108]);\n REG_DUMP_WLT_TEST_CNT[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[109]);\n REG_DUMP_FCU_TEST_CONF[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[110]);\n REG_DUMP_FCU_TEST_CMD[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[111]);\n REG_DUMP_ALT_CMD[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[112]);\n REG_DUMP_MCU_DP_CONF[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[113]);\n REG_DUMP_MCU_PP_CONF[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[114]);\n REG_DUMP_FILTER_CONF[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[115]);\n REG_DUMP_ACC_CONF[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[116]);\n REG_DUMP_GYR_CONF[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[117]);\n REG_DUMP_ALT_FILTER_CONF[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[118]);\n REG_DUMP_ALT_ACC_CONF[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[119]);\n REG_DUMP_ALT_GYR_CONF[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[120]);\n REG_DUMP_ALT_CONF[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[121]);\n REG_DUMP_ALT_STATUS[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[122]);\n REG_DUMP_SELFTEST_STATUS[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[123]);\n REG_DUMP_FCU_DBG_0[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[124]);\n REG_DUMP_FCU_DBG_1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[125]);\n REG_DUMP_I3C_CCC_GETXTIME[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[126]);\n REG_DUMP_FILTER_STATUS[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[127]);\n REG_DUMP_ACC_STATUS[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[128]);\n REG_DUMP_GYR_STATUS[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[129]);\n REG_DUMP_LEGACY_CONF[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[130]);\n REG_DUMP_PWR_CONF[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[131]);\n REG_DUMP_MCU_PRIV_UNLOCK[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[132]);\n REG_DUMP_MCU_PRIV_STAT[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[133]);\n REG_DUMP_MCU_PRIV_LOCK[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[134]);\n REG_DUMP_MCU_CONF[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[135]);\n REG_DUMP_MCU_CTRL[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[136]);\n REG_DUMP_MCU_INT_STATUS1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[137]);\n REG_DUMP_MCU_INT_STATUS2[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[138]);\n REG_DUMP_MCU_INT_EN1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[139]);\n REG_DUMP_MCU_INT_EN2[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[140]);\n REG_DUMP_MCU_INT_DIS1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[141]);\n REG_DUMP_MCU_INT_DIS2[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[142]);\n REG_DUMP_MCU_GPT_CSR[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[143]);\n REG_DUMP_MCU_GPT_RVR[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[144]);\n REG_DUMP_MCU_GPT_CVR[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[145]);\n REG_DUMP_MCU_DMA_LOB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[146]);\n REG_DUMP_MCU_DMA_UPB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[147]);\n REG_DUMP_MCU_SW_STATUS0[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[148]);\n REG_DUMP_MCU_SW_STATUS1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[149]);\n REG_DUMP_MCU_SW_STATUS2[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[150]);\n REG_DUMP_MCU_SW_STATUS3[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[151]);\n REG_DUMP_MCU_MEM_PWR[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[152]);\n REG_DUMP_MCU_MEM_MARGIN_TRIM[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[153]);\n REG_DUMP_MCU_CMD_FEATURE_TRIG[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[154]);\n REG_DUMP_MCU_GLOB_CTRL[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[155]);\n REG_DUMP_MCU_DMA_CTRL[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[156]);\n REG_DUMP_MCU_DMA_WDATA[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[157]);\n REG_DUMP_MCU_DMA_RDATA[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[158]);\n REG_DUMP_MCU_STATUS[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[159]);\n REG_DUMP_MCU_PC[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[160]);\n REG_DUMP_MCU_SP[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[161]);\n REG_DUMP_MCU_LR[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[162]);\n REG_DUMP_MCU_SR_PIPE[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[163]);\n REG_DUMP_MCU_TEST[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[164]);\n REG_DUMP_MCU_DEBUG[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[165]);\n REG_DUMP_MCU_DMA_DEBUG[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[166]);\n REG_DUMP_LPWUP_EN[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[167]);\n REG_DUMP_LPWUP_CFG[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[168]);\n REG_DUMP_LPWUP_STATUS[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[169]);\n REG_DUMP_ACC_AASR_CONF_0[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[170]);\n REG_DUMP_ACC_AASR_CONF_1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[171]);\n REG_DUMP_ACC_AASR_STATUS[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[172]);\n REG_DUMP_IO_PAD_TRM[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[173]);\n REG_DUMP_IO_TEST_IF[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[174]);\n REG_DUMP_IO_INT_CTRL[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[175]);\n REG_DUMP_IO_IF_CONF[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[176]);\n REG_DUMP_IO_PAD_STRENGTH[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[177]);\n REG_DUMP_IO_ODR_DEVIATION[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[178]);\n REG_DUMP_INT_IO_PAD_STRENGTH0[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[179]);\n REG_DUMP_INT_IO_PAD_STRENGTH1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[180]);\n REG_DUMP_GYR_SCB_PHI_A0_CH1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[181]);\n REG_DUMP_GYR_SCB_PHI_A0_CH2[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[182]);\n REG_DUMP_GYR_SCB_PHI_A0_CH3[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[183]);\n REG_DUMP_GYR_SCB_PHI_A1_CH1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[184]);\n REG_DUMP_GYR_SCB_PHI_A1_CH2[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[185]);\n REG_DUMP_GYR_SCB_PHI_A1_CH3[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[186]);\n REG_DUMP_GYR_SCB_OFF_B0_CH1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[187]);\n REG_DUMP_GYR_SCB_OFF_B0_CH2[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[188]);\n REG_DUMP_GYR_SCB_OFF_B0_CH3[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[189]);\n REG_DUMP_GYR_SCB_OFF_B1_CH1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[190]);\n REG_DUMP_GYR_SCB_OFF_B1_CH2[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[191]);\n REG_DUMP_GYR_SCB_OFF_B1_CH3[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[192]);\n REG_DUMP_GYR_TRM_PHI_A0_CH1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[193]);\n REG_DUMP_GYR_TRM_PHI_A1_CH1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[194]);\n REG_DUMP_GYR_TRM_PHI_A0_CH2[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[195]);\n REG_DUMP_GYR_TRM_PHI_A1_CH2[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[196]);\n REG_DUMP_GYR_TRM_PHI_A0_CH3[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[197]);\n REG_DUMP_GYR_TRM_PHI_A1_CH3[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[198]);\n REG_DUMP_GYR_TRM_PHI_A2_CH1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[199]);\n REG_DUMP_GYR_TRM_PHI_A2_CH2[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[200]);\n REG_DUMP_GYR_TRM_PHI_A2_CH3[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[201]);\n REG_DUMP_GYR_TRM_OFF_B0_CH1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[202]);\n REG_DUMP_GYR_TRM_OFF_B1_CH1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[203]);\n REG_DUMP_GYR_TRM_OFF_B2_CH1_CH2[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[204]);\n REG_DUMP_GYR_TRM_OFF_B0_CH2[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[205]);\n REG_DUMP_GYR_TRM_OFF_B1_CH2[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[206]);\n REG_DUMP_GYR_TRM_OFF_B2_CH2_CH3[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[207]);\n REG_DUMP_GYR_TRM_OFF_B0_CH3[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[208]);\n REG_DUMP_GYR_TRM_OFF_B1_CH3[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[209]);\n REG_DUMP_GYR_TRM_DGAIN_S0_CH1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[210]);\n REG_DUMP_GYR_ACC_TRM_DGAIN_S1_CH1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[211]);\n REG_DUMP_GYR_TRM_DGAIN_S0_CH2[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[212]);\n REG_DUMP_GYR_TRM_DGAIN_S1_CH2_CH3[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[213]);\n REG_DUMP_GYR_TRM_DGAIN_S0_CH3[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[214]);\n REG_DUMP_ACC_TRM_OFF_B0_CH1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[215]);\n REG_DUMP_ACC_TRM_OFF_B1_B2_CH1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[216]);\n REG_DUMP_ACC_TRM_OFF_B0_CH2[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[217]);\n REG_DUMP_ACC_TRM_OFF_B1_B2_CH2[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[218]);\n REG_DUMP_ACC_TRM_OFF_B0_CH3[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[219]);\n REG_DUMP_ACC_TRM_OFF_B1_B2_CH3[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[220]);\n REG_DUMP_ACC_TRM_DGAIN_S0_CH1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[221]);\n REG_DUMP_ACC_TRM_DGAIN_S0_CH2[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[222]);\n REG_DUMP_ACC_TRM_DGAIN_S0_CH3[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[223]);\n REG_DUMP_ACC_TRM_DGAIN_S1_CH2_CH3[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[224]);\n REG_DUMP_TEMP_TRM_OFF_DGAIN[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[225]);\n REG_DUMP_TEMP_TRM_OFF_DT[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[226]);\n REG_DUMP_TEMP_TRM_BG_OFF_DGAIN_NORM[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[227]);\n REG_DUMP_TEMP_TEST_TADC[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[228]);\n REG_DUMP_TEMP_TEST[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[229]);\n REG_DUMP_TEMP_DT_HI[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[230]);\n REG_DUMP_TEMP_DT_LO[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[231]);\n REG_DUMP_TEMP_FWSPARE0_RO[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[232]);\n REG_DUMP_INTERNAL_TEMP_AXIS_CONF0[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[233]);\n REG_DUMP_INTERNAL_TEMP_AXIS_CONF1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[234]);\n REG_DUMP_TEMP_AXIS_CONF[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[235]);\n REG_DUMP_GYR_USR_DGAIN_S0_X[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[236]);\n REG_DUMP_GYR_USR_DGAIN_S0_Y[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[237]);\n REG_DUMP_GYR_USR_DGAIN_S0_Z[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[238]);\n REG_DUMP_ACC_USR_DGAIN_S0_X[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[239]);\n REG_DUMP_ACC_USR_DGAIN_S0_Y[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[240]);\n REG_DUMP_ACC_USR_DGAIN_S0_Z[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[241]);\n REG_DUMP_ACC_CROSS_SY_CH12[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[242]);\n REG_DUMP_ACC_CROSS_SY_CH13[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[243]);\n REG_DUMP_ACC_CROSS_SY_CH21[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[244]);\n REG_DUMP_ACC_CROSS_SY_CH23[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[245]);\n REG_DUMP_ACC_CROSS_SY_CH31[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[246]);\n REG_DUMP_ACC_CROSS_SY_CH32[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[247]);\n REG_DUMP_ACC_TRM_DGAIN_8G_CH12[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[248]);\n REG_DUMP_ACC_TRM_DGAIN_8G_CH3[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[249]);\n REG_DUMP_ACC_TRM_OFF_STEP_8G_CH1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[250]);\n REG_DUMP_ACC_TRM_OFF_STEP_8G_CH2[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[251]);\n REG_DUMP_ACC_TRM_OFF_STEP_8G_CH3[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[252]);\n REG_DUMP_ACC_TRM_OFF_STEP_ALP_8G_CH1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[253]);\n REG_DUMP_ACC_TRM_OFF_STEP_ALP_8G_CH2[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[254]);\n REG_DUMP_ACC_TRM_OFF_STEP_ALP_8G_CH3[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[255]);\n REG_DUMP_ACC_TRM_OFF_STEP_ALP_32G_CH1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[256]);\n REG_DUMP_ACC_TRM_OFF_STEP_ALP_32G_CH2[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[257]);\n REG_DUMP_ACC_TRM_OFF_STEP_ALP_32G_CH3[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[258]);\n REG_DUMP_ACC_COMP_CONF[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[259]);\n REG_DUMP_TEMP_ACC_OFF_CH1_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[260]);\n REG_DUMP_TEMP_ACC_OFF_CH1_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[261]);\n REG_DUMP_TEMP_ACC_OFF_CH2_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[262]);\n REG_DUMP_TEMP_ACC_OFF_CH2_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[263]);\n REG_DUMP_TEMP_ACC_OFF_CH3_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[264]);\n REG_DUMP_TEMP_ACC_OFF_CH3_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[265]);\n REG_DUMP_TEMP_ACC_GAIN_CH1_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[266]);\n REG_DUMP_TEMP_ACC_GAIN_CH1_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[267]);\n REG_DUMP_TEMP_ACC_GAIN_CH2_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[268]);\n REG_DUMP_TEMP_ACC_GAIN_CH2_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[269]);\n REG_DUMP_TEMP_ACC_GAIN_CH3_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[270]);\n REG_DUMP_TEMP_ACC_GAIN_CH3_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[271]);\n REG_DUMP_ACC_USR_OFF_32G_X[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[272]);\n REG_DUMP_ACC_USR_OFF_32G_Y[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[273]);\n REG_DUMP_ACC_USR_OFF_32G_Z[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[274]);\n REG_DUMP_ACC_USR_OFF_8G_X[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[275]);\n REG_DUMP_ACC_USR_OFF_8G_Y[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[276]);\n REG_DUMP_ACC_USR_OFF_8G_Z[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[277]);\n REG_DUMP_ACC_COMP_CONF_USR[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[278]);\n REG_DUMP_GYR_CROSS_SY_CH12[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[279]);\n REG_DUMP_GYR_CROSS_SY_CH13[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[280]);\n REG_DUMP_GYR_CROSS_SY_CH21[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[281]);\n REG_DUMP_GYR_CROSS_SY_CH23[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[282]);\n REG_DUMP_GYR_CROSS_SY_CH31[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[283]);\n REG_DUMP_GYR_CROSS_SY_CH32[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[284]);\n REG_DUMP_GYR_QUAD_TRM_CH1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[285]);\n REG_DUMP_GYR_QUAD_TRM_CH2[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[286]);\n REG_DUMP_GYR_QUAD_TRM_CH3[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[287]);\n REG_DUMP_GYR_COMP_CONF[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[288]);\n REG_DUMP_TEMP_GYR_OFF_CH1_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[289]);\n REG_DUMP_TEMP_GYR_OFF_CH1_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[290]);\n REG_DUMP_TEMP_GYR_OFF_CH2_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[291]);\n REG_DUMP_TEMP_GYR_OFF_CH2_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[292]);\n REG_DUMP_TEMP_GYR_OFF_CH3_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[293]);\n REG_DUMP_TEMP_GYR_OFF_CH3_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[294]);\n REG_DUMP_TEMP_GYR_GAIN_CH1_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[295]);\n REG_DUMP_TEMP_GYR_GAIN_CH1_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[296]);\n REG_DUMP_TEMP_GYR_GAIN_CH2_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[297]);\n REG_DUMP_TEMP_GYR_GAIN_CH2_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[298]);\n REG_DUMP_TEMP_GYR_GAIN_CH3_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[299]);\n REG_DUMP_TEMP_GYR_GAIN_CH3_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[300]);\n REG_DUMP_TEMP_GYR_PHI_CH1_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[301]);\n REG_DUMP_TEMP_GYR_PHI_CH1_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[302]);\n REG_DUMP_TEMP_GYR_PHI_CH2_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[303]);\n REG_DUMP_TEMP_GYR_PHI_CH2_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[304]);\n REG_DUMP_TEMP_GYR_PHI_CH3_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[305]);\n REG_DUMP_TEMP_GYR_PHI_CH3_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[306]);\n REG_DUMP_GYR_ALP_TRM_PHI_CH12[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[307]);\n REG_DUMP_GYR_ALP_TRM_PHI_CH23[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[308]);\n REG_DUMP_GYR_ALP_TRM_OFF_CH1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[309]);\n REG_DUMP_GYR_ALP_TRM_OFF_CH2[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[310]);\n REG_DUMP_GYR_ALP_TRM_OFF_CH3[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[311]);\n REG_DUMP_GYR_USR_OFF_B0_X[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[312]);\n REG_DUMP_GYR_USR_OFF_B0_Y[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[313]);\n REG_DUMP_GYR_USR_OFF_B0_Z[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[314]);\n REG_DUMP_GYR_COMP_CONF_USR[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[315]);\n REG_DUMP_ANA_TRM_BG[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[316]);\n REG_DUMP_ANA_TRM_PMU[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[317]);\n REG_DUMP_ANA_TRM_PMU1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[318]);\n REG_DUMP_ANA_TRM_OSC[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[319]);\n REG_DUMP_ANA_TRM_RES_PROG0[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[320]);\n REG_DUMP_ANA_TRM_RES_PROG1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[321]);\n REG_DUMP_ANA_TRM_RES_PROG2[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[322]);\n REG_DUMP_ANA_TRM_CAP_PROG0[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[323]);\n REG_DUMP_ANA_TRM_CAP_PROG_CH1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[324]);\n REG_DUMP_ANA_TRM_CAP_PROG_CH2[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[325]);\n REG_DUMP_ANA_TRM_CAP_PROG_CH3[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[326]);\n REG_DUMP_ANA_TRM_CAP_PROG_DRV[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[327]);\n REG_DUMP_ANA_TRM_ACC_CH1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[328]);\n REG_DUMP_ANA_TRM_ACC_CH2[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[329]);\n REG_DUMP_ANA_TRM_ACC_CH3[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[330]);\n REG_DUMP_ANA_TEST_PWR[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[331]);\n REG_DUMP_GYR_TEST_EN[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[332]);\n REG_DUMP_GYR_TEST_WFR[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[333]);\n REG_DUMP_GYR_TEST_INT_SEL[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[334]);\n REG_DUMP_TEMP_TEST_ADC[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[335]);\n REG_DUMP_GYR_TEST_AA_AI[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[336]);\n REG_DUMP_GYR_TEST_OWR1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[337]);\n REG_DUMP_GYR_TEST_OWR2[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[338]);\n REG_DUMP_GYR_TEST_OWR_RST[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[339]);\n REG_DUMP_PMU_TEST_OWR[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[340]);\n REG_DUMP_PMU_TEST_DPWR_CTRL[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[341]);\n REG_DUMP_PMU_TEST_MISC[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[342]);\n REG_DUMP_GYR_VGM_MON_CTRL[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[343]);\n REG_DUMP_PMU_ERROR[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[344]);\n REG_DUMP_STATUS_CORE_FSM[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[345]);\n REG_DUMP_STATUS_GYR_FSM[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[346]);\n REG_DUMP_STATUS_PMOD0[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[347]);\n REG_DUMP_STATUS_PMOD1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[348]);\n REG_DUMP_STATUS_PMOD2[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[349]);\n REG_DUMP_STATUS_PMOD3[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[350]);\n REG_DUMP_STATUS_DPWR[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[351]);\n REG_DUMP_TEMP_TRM_CTRL[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[352]);\n REG_DUMP_TEMP_TEST_FSM[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[353]);\n REG_DUMP_ACC_TRM_CFB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[354]);\n REG_DUMP_ACC_TRM_LOOPG[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[355]);\n REG_DUMP_ACC_TRM_CTRL[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[356]);\n REG_DUMP_ACC_TEST_ST_CTRL[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[357]);\n REG_DUMP_ACC_TEST_ST_LFSR_SEED[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[358]);\n REG_DUMP_ACC_TEST_ST_LFSR_VAL[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[359]);\n REG_DUMP_ACC_TEST_CTRL[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[360]);\n REG_DUMP_ACC_AFE_AASR_CONF[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[361]);\n REG_DUMP_GYR_TRM_NOTCH12_GRPC[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[362]);\n REG_DUMP_GYR_TRM_NOTCH3_MISC[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[363]);\n REG_DUMP_GYR_TRM_BYP_MASH[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[364]);\n REG_DUMP_GYR_TEST_TOSK[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[365]);\n REG_DUMP_GYR_TEST_QUAD1_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[366]);\n REG_DUMP_GYR_TEST_QUAD1_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[367]);\n REG_DUMP_GYR_TEST_QUAD2_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[368]);\n REG_DUMP_GYR_TEST_QUAD2_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[369]);\n REG_DUMP_GYR_TEST_QUAD3_LSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[370]);\n REG_DUMP_GYR_TEST_QUAD3_MSB[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[371]);\n REG_DUMP_GYR_TEST_FSM[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[372]);\n REG_DUMP_GYR_TEST_FILT[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[373]);\n REG_DUMP_GYR_TEST_IQMOD_SIN1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[374]);\n REG_DUMP_GYR_TEST_IQMOD_SIN2[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[375]);\n REG_DUMP_GYR_TEST_IQMOD_COS1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[376]);\n REG_DUMP_GYR_TEST_IQMOD_COS2[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[377]);\n REG_DUMP_GYR_TEST_CLAMP[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[378]);\n REG_DUMP_DRV_ST_TRM[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[379]);\n REG_DUMP_DRV_ST_TEST_STATUS1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[380]);\n REG_DUMP_DRV_ST_TEST_STATUS2[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[381]);\n REG_DUMP_DRV_ST_TEST_STATUS3[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[382]);\n REG_DUMP_BOOT_RANGE[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[383]);\n REG_DUMP_BOOT_CMD[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[384]);\n REG_DUMP_BOOT_STATUS[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[385]);\n REG_DUMP_BOOT_DBG[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[386]);\n REG_DUMP_BOOT_LAST_DATA[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[387]);\n REG_DUMP_OTP_ADDR[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[388]);\n REG_DUMP_OTP_DATA[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[389]);\n REG_DUMP_OTP_CMD[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[390]);\n REG_DUMP_OTP_IDX[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[391]);\n REG_DUMP_OTP_PROG_EN[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[392]);\n REG_DUMP_OTP_STATUS[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[393]);\n REG_DUMP_OTP_TEST_CFG[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[394]);\n REG_DUMP_OTP_TEST_CLVWR[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[395]);\n REG_DUMP_OTP_TEST_DBG[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[396]);\n REG_DUMP_NVM_DIR_ADDR[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[397]);\n REG_DUMP_NVM_DIR_DATA[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[398]);\n REG_DUMP_NVM_DIR_CMD[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[399]);\n REG_DUMP_NVM_DIR_STATUS[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[400]);\n REG_DUMP_NVM_TEST_NVMCTRL_STATE[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[401]);\n REG_DUMP_NVM_TEST_CTRL[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[402]);\n REG_DUMP_NVM_WRITE_PROT_CTRL[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[403]);\n REG_DUMP_NVM_TEST[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[404]);\n REG_DUMP_DTB3[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[405]);\n REG_DUMP_DTB1[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[406]);\n REG_DUMP_FASTSO_CONF[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[407]);\n REG_DUMP_TEST_SCAN[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[408]);\n REG_DUMP_TEST_I2C_DEL[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[409]);\n REG_DUMP_TM_ADDR[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[410]);\n REG_DUMP_TM_CONF[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[411]);\n REG_DUMP_TM_GYR[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[412]);\n REG_DUMP_TM_TEMP[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[413]);\n REG_DUMP_TM_PIN[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[414]);\n REG_DUMP_TM_PWR[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[415]);\n REG_DUMP_LUT_MEM2REG_IN[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[416]);\n REG_DUMP_LUT_MEM2REG_OUT[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[417]);\n REG_DUMP_LUT_DUMMY[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[418]);\n REG_DUMP_SUP_CRC[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[419]);\n REG_DUMP_SUP_CRC_IN[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[420]);\n REG_DUMP_ARB_FORCE_CTRL[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[421]);\n\n // Auto_Code_Retrieve_Data\n \n int Func_result = rdi.id(\"T20_30_register_dump_V1_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n FuncPrint(\"REG_DUMP_CHIP_ID\", REG_DUMP_CHIP_ID[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ERR_REG\", REG_DUMP_ERR_REG[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_HIF_TRIM_0\", REG_DUMP_HIF_TRIM_0[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_HIF_CONFIG\", REG_DUMP_HIF_CONFIG[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_I3C_TC_SYNC_TPH\", REG_DUMP_I3C_TC_SYNC_TPH[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_I3C_TC_SYNC_TU\", REG_DUMP_I3C_TC_SYNC_TU[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_I3C_TC_SYNC_ODR\", REG_DUMP_I3C_TC_SYNC_ODR[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_I3C_TC_SYNC_DT\", REG_DUMP_I3C_TC_SYNC_DT[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_I3C_TC_SYNC_ST0\", REG_DUMP_I3C_TC_SYNC_ST0[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_I3C_TC_SYNC_ST1\", REG_DUMP_I3C_TC_SYNC_ST1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_LEG_ERR_REG\", REG_DUMP_LEG_ERR_REG[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_REV_ID\", REG_DUMP_REV_ID[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_OCP_MASK\", REG_DUMP_OCP_MASK[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_CMD\", REG_DUMP_CMD[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_EXT_MODE\", REG_DUMP_EXT_MODE[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_STATUS\", REG_DUMP_STATUS[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_DATA_X_LSB\", REG_DUMP_ACC_DATA_X_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_DATA_X_MSB\", REG_DUMP_ACC_DATA_X_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_DATA_Y_LSB\", REG_DUMP_ACC_DATA_Y_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_DATA_Y_MSB\", REG_DUMP_ACC_DATA_Y_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_DATA_Z_LSB\", REG_DUMP_ACC_DATA_Z_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_DATA_Z_MSB\", REG_DUMP_ACC_DATA_Z_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_DATA_X_LSB\", REG_DUMP_GYR_DATA_X_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_DATA_X_MSB\", REG_DUMP_GYR_DATA_X_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_DATA_Y_LSB\", REG_DUMP_GYR_DATA_Y_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_DATA_Y_MSB\", REG_DUMP_GYR_DATA_Y_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_DATA_Z_LSB\", REG_DUMP_GYR_DATA_Z_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_DATA_Z_MSB\", REG_DUMP_GYR_DATA_Z_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_DATA\", REG_DUMP_TEMP_DATA[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_SENSORTIME_DATA_LSB\", REG_DUMP_SENSORTIME_DATA_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_SENSORTIME_DATA_MSB\", REG_DUMP_SENSORTIME_DATA_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MUTE\", REG_DUMP_MUTE[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_GP_0\", REG_DUMP_MCU_GP_0[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_GP_1\", REG_DUMP_MCU_GP_1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_GP_2\", REG_DUMP_MCU_GP_2[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_GP_STATUS\", REG_DUMP_MCU_GP_STATUS[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_GP_DIR\", REG_DUMP_MCU_GP_DIR[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_SH_MASK\", REG_DUMP_SH_MASK[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_SH_STATUS\", REG_DUMP_SH_STATUS[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_SH_TEMP_DATA\", REG_DUMP_SH_TEMP_DATA[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_SH_ACC_DATA_X_LSB\", REG_DUMP_SH_ACC_DATA_X_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_SH_ACC_DATA_X_MSB\", REG_DUMP_SH_ACC_DATA_X_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_SH_ACC_DATA_Y_LSB\", REG_DUMP_SH_ACC_DATA_Y_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_SH_ACC_DATA_Y_MSB\", REG_DUMP_SH_ACC_DATA_Y_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_SH_ACC_DATA_Z_LSB\", REG_DUMP_SH_ACC_DATA_Z_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_SH_ACC_DATA_Z_MSB\", REG_DUMP_SH_ACC_DATA_Z_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_SH_GYR_DATA_X_LSB\", REG_DUMP_SH_GYR_DATA_X_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_SH_GYR_DATA_X_MSB\", REG_DUMP_SH_GYR_DATA_X_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_SH_GYR_DATA_Y_LSB\", REG_DUMP_SH_GYR_DATA_Y_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_SH_GYR_DATA_Y_MSB\", REG_DUMP_SH_GYR_DATA_Y_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_SH_GYR_DATA_Z_LSB\", REG_DUMP_SH_GYR_DATA_Z_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_SH_GYR_DATA_Z_MSB\", REG_DUMP_SH_GYR_DATA_Z_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_ACC_DATA_X_LSB\", REG_DUMP_MCU_ACC_DATA_X_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_ACC_DATA_X_MSB\", REG_DUMP_MCU_ACC_DATA_X_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_ACC_DATA_Y_LSB\", REG_DUMP_MCU_ACC_DATA_Y_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_ACC_DATA_Y_MSB\", REG_DUMP_MCU_ACC_DATA_Y_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_ACC_DATA_Z_LSB\", REG_DUMP_MCU_ACC_DATA_Z_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_ACC_DATA_Z_MSB\", REG_DUMP_MCU_ACC_DATA_Z_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_GYR_DATA_X_LSB\", REG_DUMP_MCU_GYR_DATA_X_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_GYR_DATA_X_MSB\", REG_DUMP_MCU_GYR_DATA_X_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_GYR_DATA_Y_LSB\", REG_DUMP_MCU_GYR_DATA_Y_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_GYR_DATA_Y_MSB\", REG_DUMP_MCU_GYR_DATA_Y_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_GYR_DATA_Z_LSB\", REG_DUMP_MCU_GYR_DATA_Z_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_GYR_DATA_Z_MSB\", REG_DUMP_MCU_GYR_DATA_Z_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_RAW_SENSORTIME_LSB\", REG_DUMP_RAW_SENSORTIME_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_RAW_SENSORTIME_MSB\", REG_DUMP_RAW_SENSORTIME_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_LEG_STATUS\", REG_DUMP_LEG_STATUS[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_LEG_ACC_DATA_X\", REG_DUMP_LEG_ACC_DATA_X[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_LEG_ACC_DATA_Y\", REG_DUMP_LEG_ACC_DATA_Y[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_LEG_ACC_DATA_Z\", REG_DUMP_LEG_ACC_DATA_Z[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_LEG_GYR_DATA_X\", REG_DUMP_LEG_GYR_DATA_X[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_LEG_GYR_DATA_Y\", REG_DUMP_LEG_GYR_DATA_Y[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_LEG_GYR_DATA_Z\", REG_DUMP_LEG_GYR_DATA_Z[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_LEG_TEMP_DATA\", REG_DUMP_LEG_TEMP_DATA[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_LEG_SENSORTIME_DATA_LSB\", REG_DUMP_LEG_SENSORTIME_DATA_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_LEG_SENSORTIME_DATA_MSB\", REG_DUMP_LEG_SENSORTIME_DATA_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_SAT_FLAGS\", REG_DUMP_SAT_FLAGS[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_PP_ACTIVE_STATUS\", REG_DUMP_PP_ACTIVE_STATUS[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_GP_OIS_0_SYS\", REG_DUMP_MCU_GP_OIS_0_SYS[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_GP_OIS_1_SYS\", REG_DUMP_MCU_GP_OIS_1_SYS[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_GP_OIS_STATUS_SYS\", REG_DUMP_MCU_GP_OIS_STATUS_SYS[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_GP_OIS_DIR\", REG_DUMP_MCU_GP_OIS_DIR[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_OIS_STATUS_SYS\", REG_DUMP_MCU_OIS_STATUS_SYS[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MUTE_OIS\", REG_DUMP_MUTE_OIS[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_SH_MASK_OIS\", REG_DUMP_SH_MASK_OIS[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_SH_STATUS_OIS\", REG_DUMP_SH_STATUS_OIS[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_SH_OIS_ACC_DATA_X\", REG_DUMP_SH_OIS_ACC_DATA_X[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_SH_OIS_ACC_DATA_Y\", REG_DUMP_SH_OIS_ACC_DATA_Y[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_SH_OIS_ACC_DATA_Z\", REG_DUMP_SH_OIS_ACC_DATA_Z[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_SH_OIS_GYR_DATA_X\", REG_DUMP_SH_OIS_GYR_DATA_X[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_SH_OIS_GYR_DATA_Y\", REG_DUMP_SH_OIS_GYR_DATA_Y[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_SH_OIS_GYR_DATA_Z\", REG_DUMP_SH_OIS_GYR_DATA_Z[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_INT_STATUS_INT1\", REG_DUMP_INT_STATUS_INT1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_INT_STATUS_INT2\", REG_DUMP_INT_STATUS_INT2[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_INT_STATUS_IBI\", REG_DUMP_INT_STATUS_IBI[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_INT_CONF\", REG_DUMP_INT_CONF[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_INT_MAP_HW\", REG_DUMP_INT_MAP_HW[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_INT_MAP_MCU\", REG_DUMP_INT_MAP_MCU[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_INT_MCU_SET\", REG_DUMP_INT_MCU_SET[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_INT_IBI_MANDATORY\", REG_DUMP_INT_IBI_MANDATORY[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_INT_IBI_CCC_GETSTATUS\", REG_DUMP_INT_IBI_CCC_GETSTATUS[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_FIFO_FILL_LVL\", REG_DUMP_FIFO_FILL_LVL[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_FIFO_DATA\", REG_DUMP_FIFO_DATA[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_FIFO_WATERMARK\", REG_DUMP_FIFO_WATERMARK[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_FIFO_CONF\", REG_DUMP_FIFO_CONF[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_FIFO_CTRL\", REG_DUMP_FIFO_CTRL[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_OIS_CONF\", REG_DUMP_OIS_CONF[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_FCU_TRIM_0\", REG_DUMP_FCU_TRIM_0[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_FCU_TRIM_1\", REG_DUMP_FCU_TRIM_1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_WLT_TEST_CNT\", REG_DUMP_WLT_TEST_CNT[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_FCU_TEST_CONF\", REG_DUMP_FCU_TEST_CONF[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_FCU_TEST_CMD\", REG_DUMP_FCU_TEST_CMD[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ALT_CMD\", REG_DUMP_ALT_CMD[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_DP_CONF\", REG_DUMP_MCU_DP_CONF[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_PP_CONF\", REG_DUMP_MCU_PP_CONF[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_FILTER_CONF\", REG_DUMP_FILTER_CONF[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_CONF\", REG_DUMP_ACC_CONF[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_CONF\", REG_DUMP_GYR_CONF[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ALT_FILTER_CONF\", REG_DUMP_ALT_FILTER_CONF[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ALT_ACC_CONF\", REG_DUMP_ALT_ACC_CONF[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ALT_GYR_CONF\", REG_DUMP_ALT_GYR_CONF[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ALT_CONF\", REG_DUMP_ALT_CONF[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ALT_STATUS\", REG_DUMP_ALT_STATUS[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_SELFTEST_STATUS\", REG_DUMP_SELFTEST_STATUS[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_FCU_DBG_0\", REG_DUMP_FCU_DBG_0[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_FCU_DBG_1\", REG_DUMP_FCU_DBG_1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_I3C_CCC_GETXTIME\", REG_DUMP_I3C_CCC_GETXTIME [CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_FILTER_STATUS\", REG_DUMP_FILTER_STATUS[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_STATUS\", REG_DUMP_ACC_STATUS[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_STATUS\", REG_DUMP_GYR_STATUS[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_LEGACY_CONF\", REG_DUMP_LEGACY_CONF[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_PWR_CONF\", REG_DUMP_PWR_CONF[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_PRIV_UNLOCK\", REG_DUMP_MCU_PRIV_UNLOCK[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_PRIV_STAT\", REG_DUMP_MCU_PRIV_STAT[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_PRIV_LOCK\", REG_DUMP_MCU_PRIV_LOCK[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_CONF\", REG_DUMP_MCU_CONF[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_CTRL\", REG_DUMP_MCU_CTRL[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_INT_STATUS1\", REG_DUMP_MCU_INT_STATUS1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_INT_STATUS2\", REG_DUMP_MCU_INT_STATUS2[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_INT_EN1\", REG_DUMP_MCU_INT_EN1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_INT_EN2\", REG_DUMP_MCU_INT_EN2[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_INT_DIS1\", REG_DUMP_MCU_INT_DIS1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_INT_DIS2\", REG_DUMP_MCU_INT_DIS2[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_GPT_CSR\", REG_DUMP_MCU_GPT_CSR[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_GPT_RVR\", REG_DUMP_MCU_GPT_RVR[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_GPT_CVR\", REG_DUMP_MCU_GPT_CVR[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_DMA_LOB\", REG_DUMP_MCU_DMA_LOB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_DMA_UPB\", REG_DUMP_MCU_DMA_UPB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_SW_STATUS0\", REG_DUMP_MCU_SW_STATUS0[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_SW_STATUS1\", REG_DUMP_MCU_SW_STATUS1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_SW_STATUS2\", REG_DUMP_MCU_SW_STATUS2[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_SW_STATUS3\", REG_DUMP_MCU_SW_STATUS3[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_MEM_PWR\", REG_DUMP_MCU_MEM_PWR[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_MEM_MARGIN_TRIM\", REG_DUMP_MCU_MEM_MARGIN_TRIM[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_CMD_FEATURE_TRIG\", REG_DUMP_MCU_CMD_FEATURE_TRIG[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_GLOB_CTRL\", REG_DUMP_MCU_GLOB_CTRL[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_DMA_CTRL\", REG_DUMP_MCU_DMA_CTRL[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_DMA_WDATA\", REG_DUMP_MCU_DMA_WDATA[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_DMA_RDATA\", REG_DUMP_MCU_DMA_RDATA[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_STATUS\", REG_DUMP_MCU_STATUS[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_PC\", REG_DUMP_MCU_PC[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_SP\", REG_DUMP_MCU_SP[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_LR\", REG_DUMP_MCU_LR[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_SR_PIPE\", REG_DUMP_MCU_SR_PIPE[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_TEST\", REG_DUMP_MCU_TEST[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_DEBUG\", REG_DUMP_MCU_DEBUG[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_MCU_DMA_DEBUG\", REG_DUMP_MCU_DMA_DEBUG[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_LPWUP_EN\", REG_DUMP_LPWUP_EN[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_LPWUP_CFG\", REG_DUMP_LPWUP_CFG[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_LPWUP_STATUS\", REG_DUMP_LPWUP_STATUS[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_AASR_CONF_0\", REG_DUMP_ACC_AASR_CONF_0[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_AASR_CONF_1\", REG_DUMP_ACC_AASR_CONF_1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_AASR_STATUS\", REG_DUMP_ACC_AASR_STATUS[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_IO_PAD_TRM\", REG_DUMP_IO_PAD_TRM[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_IO_TEST_IF\", REG_DUMP_IO_TEST_IF[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_IO_INT_CTRL\", REG_DUMP_IO_INT_CTRL[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_IO_IF_CONF\", REG_DUMP_IO_IF_CONF[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_IO_PAD_STRENGTH\", REG_DUMP_IO_PAD_STRENGTH[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_IO_ODR_DEVIATION\", REG_DUMP_IO_ODR_DEVIATION[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_INT_IO_PAD_STRENGTH0\", REG_DUMP_INT_IO_PAD_STRENGTH0[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_INT_IO_PAD_STRENGTH1\", REG_DUMP_INT_IO_PAD_STRENGTH1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_SCB_PHI_A0_CH1\", REG_DUMP_GYR_SCB_PHI_A0_CH1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_SCB_PHI_A0_CH2\", REG_DUMP_GYR_SCB_PHI_A0_CH2[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_SCB_PHI_A0_CH3\", REG_DUMP_GYR_SCB_PHI_A0_CH3[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_SCB_PHI_A1_CH1\", REG_DUMP_GYR_SCB_PHI_A1_CH1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_SCB_PHI_A1_CH2\", REG_DUMP_GYR_SCB_PHI_A1_CH2[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_SCB_PHI_A1_CH3\", REG_DUMP_GYR_SCB_PHI_A1_CH3[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_SCB_OFF_B0_CH1\", REG_DUMP_GYR_SCB_OFF_B0_CH1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_SCB_OFF_B0_CH2\", REG_DUMP_GYR_SCB_OFF_B0_CH2[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_SCB_OFF_B0_CH3\", REG_DUMP_GYR_SCB_OFF_B0_CH3[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_SCB_OFF_B1_CH1\", REG_DUMP_GYR_SCB_OFF_B1_CH1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_SCB_OFF_B1_CH2\", REG_DUMP_GYR_SCB_OFF_B1_CH2[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_SCB_OFF_B1_CH3\", REG_DUMP_GYR_SCB_OFF_B1_CH3[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TRM_PHI_A0_CH1\", REG_DUMP_GYR_TRM_PHI_A0_CH1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TRM_PHI_A1_CH1\", REG_DUMP_GYR_TRM_PHI_A1_CH1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TRM_PHI_A0_CH2\", REG_DUMP_GYR_TRM_PHI_A0_CH2[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TRM_PHI_A1_CH2\", REG_DUMP_GYR_TRM_PHI_A1_CH2[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TRM_PHI_A0_CH3\", REG_DUMP_GYR_TRM_PHI_A0_CH3[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TRM_PHI_A1_CH3\", REG_DUMP_GYR_TRM_PHI_A1_CH3[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TRM_PHI_A2_CH1\", REG_DUMP_GYR_TRM_PHI_A2_CH1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TRM_PHI_A2_CH2\", REG_DUMP_GYR_TRM_PHI_A2_CH2[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TRM_PHI_A2_CH3\", REG_DUMP_GYR_TRM_PHI_A2_CH3[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TRM_OFF_B0_CH1\", REG_DUMP_GYR_TRM_OFF_B0_CH1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TRM_OFF_B1_CH1\", REG_DUMP_GYR_TRM_OFF_B1_CH1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TRM_OFF_B2_CH1_CH2\", REG_DUMP_GYR_TRM_OFF_B2_CH1_CH2[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TRM_OFF_B0_CH2\", REG_DUMP_GYR_TRM_OFF_B0_CH2[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TRM_OFF_B1_CH2\", REG_DUMP_GYR_TRM_OFF_B1_CH2[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TRM_OFF_B2_CH2_CH3\", REG_DUMP_GYR_TRM_OFF_B2_CH2_CH3[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TRM_OFF_B0_CH3\", REG_DUMP_GYR_TRM_OFF_B0_CH3[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TRM_OFF_B1_CH3\", REG_DUMP_GYR_TRM_OFF_B1_CH3[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TRM_DGAIN_S0_CH1\", REG_DUMP_GYR_TRM_DGAIN_S0_CH1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_ACC_TRM_DGAIN_S1_CH1\", REG_DUMP_GYR_ACC_TRM_DGAIN_S1_CH1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TRM_DGAIN_S0_CH2\", REG_DUMP_GYR_TRM_DGAIN_S0_CH2[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TRM_DGAIN_S1_CH2_CH3\", REG_DUMP_GYR_TRM_DGAIN_S1_CH2_CH3[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TRM_DGAIN_S0_CH3\", REG_DUMP_GYR_TRM_DGAIN_S0_CH3[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_TRM_OFF_B0_CH1\", REG_DUMP_ACC_TRM_OFF_B0_CH1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_TRM_OFF_B1_B2_CH1\", REG_DUMP_ACC_TRM_OFF_B1_B2_CH1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_TRM_OFF_B0_CH2\", REG_DUMP_ACC_TRM_OFF_B0_CH2[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_TRM_OFF_B1_B2_CH2\", REG_DUMP_ACC_TRM_OFF_B1_B2_CH2[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_TRM_OFF_B0_CH3\", REG_DUMP_ACC_TRM_OFF_B0_CH3[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_TRM_OFF_B1_B2_CH3\", REG_DUMP_ACC_TRM_OFF_B1_B2_CH3[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_TRM_DGAIN_S0_CH1\", REG_DUMP_ACC_TRM_DGAIN_S0_CH1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_TRM_DGAIN_S0_CH2\", REG_DUMP_ACC_TRM_DGAIN_S0_CH2[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_TRM_DGAIN_S0_CH3\", REG_DUMP_ACC_TRM_DGAIN_S0_CH3[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_TRM_DGAIN_S1_CH2_CH3\", REG_DUMP_ACC_TRM_DGAIN_S1_CH2_CH3[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_TRM_OFF_DGAIN\", REG_DUMP_TEMP_TRM_OFF_DGAIN[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_TRM_OFF_DT\", REG_DUMP_TEMP_TRM_OFF_DT[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_TRM_BG_OFF_DGAIN_NORM\", REG_DUMP_TEMP_TRM_BG_OFF_DGAIN_NORM[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_TEST_TADC\", REG_DUMP_TEMP_TEST_TADC[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_TEST\", REG_DUMP_TEMP_TEST[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_DT_HI\", REG_DUMP_TEMP_DT_HI[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_DT_LO\", REG_DUMP_TEMP_DT_LO[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_FWSPARE0_RO\", REG_DUMP_TEMP_FWSPARE0_RO[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_INTERNAL_TEMP_AXIS_CONF0\", REG_DUMP_INTERNAL_TEMP_AXIS_CONF0[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_INTERNAL_TEMP_AXIS_CONF1\", REG_DUMP_INTERNAL_TEMP_AXIS_CONF1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_AXIS_CONF\", REG_DUMP_TEMP_AXIS_CONF[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_USR_DGAIN_S0_X\", REG_DUMP_GYR_USR_DGAIN_S0_X[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_USR_DGAIN_S0_Y\", REG_DUMP_GYR_USR_DGAIN_S0_Y[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_USR_DGAIN_S0_Z\", REG_DUMP_GYR_USR_DGAIN_S0_Z[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_USR_DGAIN_S0_X\", REG_DUMP_ACC_USR_DGAIN_S0_X[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_USR_DGAIN_S0_Y\", REG_DUMP_ACC_USR_DGAIN_S0_Y[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_USR_DGAIN_S0_Z\", REG_DUMP_ACC_USR_DGAIN_S0_Z[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_CROSS_SY_CH12\", REG_DUMP_ACC_CROSS_SY_CH12[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_CROSS_SY_CH13\", REG_DUMP_ACC_CROSS_SY_CH13[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_CROSS_SY_CH21\", REG_DUMP_ACC_CROSS_SY_CH21[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_CROSS_SY_CH23\", REG_DUMP_ACC_CROSS_SY_CH23[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_CROSS_SY_CH31\", REG_DUMP_ACC_CROSS_SY_CH31[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_CROSS_SY_CH32\", REG_DUMP_ACC_CROSS_SY_CH32[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_TRM_DGAIN_8G_CH12\", REG_DUMP_ACC_TRM_DGAIN_8G_CH12[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_TRM_DGAIN_8G_CH3\", REG_DUMP_ACC_TRM_DGAIN_8G_CH3[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_TRM_OFF_STEP_8G_CH1\", REG_DUMP_ACC_TRM_OFF_STEP_8G_CH1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_TRM_OFF_STEP_8G_CH2\", REG_DUMP_ACC_TRM_OFF_STEP_8G_CH2[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_TRM_OFF_STEP_8G_CH3\", REG_DUMP_ACC_TRM_OFF_STEP_8G_CH3[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_TRM_OFF_STEP_ALP_8G_CH1\", REG_DUMP_ACC_TRM_OFF_STEP_ALP_8G_CH1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_TRM_OFF_STEP_ALP_8G_CH2\", REG_DUMP_ACC_TRM_OFF_STEP_ALP_8G_CH2[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_TRM_OFF_STEP_ALP_8G_CH3\", REG_DUMP_ACC_TRM_OFF_STEP_ALP_8G_CH3[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_TRM_OFF_STEP_ALP_32G_CH1\", REG_DUMP_ACC_TRM_OFF_STEP_ALP_32G_CH1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_TRM_OFF_STEP_ALP_32G_CH2\", REG_DUMP_ACC_TRM_OFF_STEP_ALP_32G_CH2[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_TRM_OFF_STEP_ALP_32G_CH3\", REG_DUMP_ACC_TRM_OFF_STEP_ALP_32G_CH3[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_COMP_CONF\", REG_DUMP_ACC_COMP_CONF[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_ACC_OFF_CH1_MSB\", REG_DUMP_TEMP_ACC_OFF_CH1_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_ACC_OFF_CH1_LSB\", REG_DUMP_TEMP_ACC_OFF_CH1_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_ACC_OFF_CH2_MSB\", REG_DUMP_TEMP_ACC_OFF_CH2_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_ACC_OFF_CH2_LSB\", REG_DUMP_TEMP_ACC_OFF_CH2_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_ACC_OFF_CH3_MSB\", REG_DUMP_TEMP_ACC_OFF_CH3_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_ACC_OFF_CH3_LSB\", REG_DUMP_TEMP_ACC_OFF_CH3_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_ACC_GAIN_CH1_MSB\", REG_DUMP_TEMP_ACC_GAIN_CH1_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_ACC_GAIN_CH1_LSB\", REG_DUMP_TEMP_ACC_GAIN_CH1_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_ACC_GAIN_CH2_MSB\", REG_DUMP_TEMP_ACC_GAIN_CH2_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_ACC_GAIN_CH2_LSB\", REG_DUMP_TEMP_ACC_GAIN_CH2_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_ACC_GAIN_CH3_MSB\", REG_DUMP_TEMP_ACC_GAIN_CH3_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_ACC_GAIN_CH3_LSB\", REG_DUMP_TEMP_ACC_GAIN_CH3_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_USR_OFF_32G_X\", REG_DUMP_ACC_USR_OFF_32G_X[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_USR_OFF_32G_Y\", REG_DUMP_ACC_USR_OFF_32G_Y[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_USR_OFF_32G_Z\", REG_DUMP_ACC_USR_OFF_32G_Z[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_USR_OFF_8G_X\", REG_DUMP_ACC_USR_OFF_8G_X[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_USR_OFF_8G_Y\", REG_DUMP_ACC_USR_OFF_8G_Y[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_USR_OFF_8G_Z\", REG_DUMP_ACC_USR_OFF_8G_Z[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_COMP_CONF_USR\", REG_DUMP_ACC_COMP_CONF_USR[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_CROSS_SY_CH12\", REG_DUMP_GYR_CROSS_SY_CH12[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_CROSS_SY_CH13\", REG_DUMP_GYR_CROSS_SY_CH13[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_CROSS_SY_CH21\", REG_DUMP_GYR_CROSS_SY_CH21[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_CROSS_SY_CH23\", REG_DUMP_GYR_CROSS_SY_CH23[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_CROSS_SY_CH31\", REG_DUMP_GYR_CROSS_SY_CH31[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_CROSS_SY_CH32\", REG_DUMP_GYR_CROSS_SY_CH32[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_QUAD_TRM_CH1\", REG_DUMP_GYR_QUAD_TRM_CH1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_QUAD_TRM_CH2\", REG_DUMP_GYR_QUAD_TRM_CH2[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_QUAD_TRM_CH3\", REG_DUMP_GYR_QUAD_TRM_CH3[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_COMP_CONF\", REG_DUMP_GYR_COMP_CONF[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_GYR_OFF_CH1_MSB\", REG_DUMP_TEMP_GYR_OFF_CH1_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_GYR_OFF_CH1_LSB\", REG_DUMP_TEMP_GYR_OFF_CH1_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_GYR_OFF_CH2_MSB\", REG_DUMP_TEMP_GYR_OFF_CH2_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_GYR_OFF_CH2_LSB\", REG_DUMP_TEMP_GYR_OFF_CH2_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_GYR_OFF_CH3_MSB\", REG_DUMP_TEMP_GYR_OFF_CH3_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_GYR_OFF_CH3_LSB\", REG_DUMP_TEMP_GYR_OFF_CH3_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_GYR_GAIN_CH1_MSB\", REG_DUMP_TEMP_GYR_GAIN_CH1_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_GYR_GAIN_CH1_LSB\", REG_DUMP_TEMP_GYR_GAIN_CH1_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_GYR_GAIN_CH2_MSB\", REG_DUMP_TEMP_GYR_GAIN_CH2_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_GYR_GAIN_CH2_LSB\", REG_DUMP_TEMP_GYR_GAIN_CH2_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_GYR_GAIN_CH3_MSB\", REG_DUMP_TEMP_GYR_GAIN_CH3_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_GYR_GAIN_CH3_LSB\", REG_DUMP_TEMP_GYR_GAIN_CH3_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_GYR_PHI_CH1_MSB\", REG_DUMP_TEMP_GYR_PHI_CH1_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_GYR_PHI_CH1_LSB\", REG_DUMP_TEMP_GYR_PHI_CH1_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_GYR_PHI_CH2_MSB\", REG_DUMP_TEMP_GYR_PHI_CH2_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_GYR_PHI_CH2_LSB\", REG_DUMP_TEMP_GYR_PHI_CH2_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_GYR_PHI_CH3_MSB\", REG_DUMP_TEMP_GYR_PHI_CH3_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_GYR_PHI_CH3_LSB\", REG_DUMP_TEMP_GYR_PHI_CH3_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_ALP_TRM_PHI_CH12\", REG_DUMP_GYR_ALP_TRM_PHI_CH12[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_ALP_TRM_PHI_CH23\", REG_DUMP_GYR_ALP_TRM_PHI_CH23[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_ALP_TRM_OFF_CH1\", REG_DUMP_GYR_ALP_TRM_OFF_CH1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_ALP_TRM_OFF_CH2\", REG_DUMP_GYR_ALP_TRM_OFF_CH2[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_ALP_TRM_OFF_CH3\", REG_DUMP_GYR_ALP_TRM_OFF_CH3[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_USR_OFF_B0_X\", REG_DUMP_GYR_USR_OFF_B0_X[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_USR_OFF_B0_Y\", REG_DUMP_GYR_USR_OFF_B0_Y[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_USR_OFF_B0_Z\", REG_DUMP_GYR_USR_OFF_B0_Z[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_COMP_CONF_USR\", REG_DUMP_GYR_COMP_CONF_USR[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ANA_TRM_BG\", REG_DUMP_ANA_TRM_BG[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ANA_TRM_PMU\", REG_DUMP_ANA_TRM_PMU[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ANA_TRM_PMU1\", REG_DUMP_ANA_TRM_PMU1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ANA_TRM_OSC\", REG_DUMP_ANA_TRM_OSC[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ANA_TRM_RES_PROG0\", REG_DUMP_ANA_TRM_RES_PROG0[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ANA_TRM_RES_PROG1\", REG_DUMP_ANA_TRM_RES_PROG1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ANA_TRM_RES_PROG2\", REG_DUMP_ANA_TRM_RES_PROG2[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ANA_TRM_CAP_PROG0\", REG_DUMP_ANA_TRM_CAP_PROG0[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ANA_TRM_CAP_PROG_CH1\", REG_DUMP_ANA_TRM_CAP_PROG_CH1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ANA_TRM_CAP_PROG_CH2\", REG_DUMP_ANA_TRM_CAP_PROG_CH2[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ANA_TRM_CAP_PROG_CH3\", REG_DUMP_ANA_TRM_CAP_PROG_CH3[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ANA_TRM_CAP_PROG_DRV\", REG_DUMP_ANA_TRM_CAP_PROG_DRV[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ANA_TRM_ACC_CH1\", REG_DUMP_ANA_TRM_ACC_CH1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ANA_TRM_ACC_CH2\", REG_DUMP_ANA_TRM_ACC_CH2[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ANA_TRM_ACC_CH3\", REG_DUMP_ANA_TRM_ACC_CH3[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ANA_TEST_PWR\", REG_DUMP_ANA_TEST_PWR[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TEST_EN\", REG_DUMP_GYR_TEST_EN[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TEST_WFR\", REG_DUMP_GYR_TEST_WFR[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TEST_INT_SEL\", REG_DUMP_GYR_TEST_INT_SEL[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_TEST_ADC\", REG_DUMP_TEMP_TEST_ADC[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TEST_AA_AI\", REG_DUMP_GYR_TEST_AA_AI[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TEST_OWR1\", REG_DUMP_GYR_TEST_OWR1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TEST_OWR2\", REG_DUMP_GYR_TEST_OWR2[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TEST_OWR_RST\", REG_DUMP_GYR_TEST_OWR_RST[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_PMU_TEST_OWR\", REG_DUMP_PMU_TEST_OWR[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_PMU_TEST_DPWR_CTRL\", REG_DUMP_PMU_TEST_DPWR_CTRL[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_PMU_TEST_MISC\", REG_DUMP_PMU_TEST_MISC[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_VGM_MON_CTRL\", REG_DUMP_GYR_VGM_MON_CTRL[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_PMU_ERROR\", REG_DUMP_PMU_ERROR[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_STATUS_CORE_FSM\", REG_DUMP_STATUS_CORE_FSM[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_STATUS_GYR_FSM\", REG_DUMP_STATUS_GYR_FSM[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_STATUS_PMOD0\", REG_DUMP_STATUS_PMOD0[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_STATUS_PMOD1\", REG_DUMP_STATUS_PMOD1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_STATUS_PMOD2\", REG_DUMP_STATUS_PMOD2[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_STATUS_PMOD3\", REG_DUMP_STATUS_PMOD3[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_STATUS_DPWR\", REG_DUMP_STATUS_DPWR[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_TRM_CTRL\", REG_DUMP_TEMP_TRM_CTRL[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEMP_TEST_FSM\", REG_DUMP_TEMP_TEST_FSM[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_TRM_CFB\", REG_DUMP_ACC_TRM_CFB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_TRM_LOOPG\", REG_DUMP_ACC_TRM_LOOPG[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_TRM_CTRL\", REG_DUMP_ACC_TRM_CTRL[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_TEST_ST_CTRL\", REG_DUMP_ACC_TEST_ST_CTRL[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_TEST_ST_LFSR_SEED\", REG_DUMP_ACC_TEST_ST_LFSR_SEED[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_TEST_ST_LFSR_VAL\", REG_DUMP_ACC_TEST_ST_LFSR_VAL[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_TEST_CTRL\", REG_DUMP_ACC_TEST_CTRL[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ACC_AFE_AASR_CONF\", REG_DUMP_ACC_AFE_AASR_CONF[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TRM_NOTCH12_GRPC\", REG_DUMP_GYR_TRM_NOTCH12_GRPC[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TRM_NOTCH3_MISC\", REG_DUMP_GYR_TRM_NOTCH3_MISC[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TRM_BYP_MASH\", REG_DUMP_GYR_TRM_BYP_MASH[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TEST_TOSK\", REG_DUMP_GYR_TEST_TOSK[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TEST_QUAD1_LSB\", REG_DUMP_GYR_TEST_QUAD1_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TEST_QUAD1_MSB\", REG_DUMP_GYR_TEST_QUAD1_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TEST_QUAD2_LSB\", REG_DUMP_GYR_TEST_QUAD2_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TEST_QUAD2_MSB\", REG_DUMP_GYR_TEST_QUAD2_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TEST_QUAD3_LSB\", REG_DUMP_GYR_TEST_QUAD3_LSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TEST_QUAD3_MSB\", REG_DUMP_GYR_TEST_QUAD3_MSB[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TEST_FSM\", REG_DUMP_GYR_TEST_FSM[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TEST_FILT\", REG_DUMP_GYR_TEST_FILT[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TEST_IQMOD_SIN1\", REG_DUMP_GYR_TEST_IQMOD_SIN1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TEST_IQMOD_SIN2\", REG_DUMP_GYR_TEST_IQMOD_SIN2[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TEST_IQMOD_COS1\", REG_DUMP_GYR_TEST_IQMOD_COS1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TEST_IQMOD_COS2\", REG_DUMP_GYR_TEST_IQMOD_COS2[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_GYR_TEST_CLAMP\", REG_DUMP_GYR_TEST_CLAMP[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_DRV_ST_TRM\", REG_DUMP_DRV_ST_TRM[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_DRV_ST_TEST_STATUS1\", REG_DUMP_DRV_ST_TEST_STATUS1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_DRV_ST_TEST_STATUS2\", REG_DUMP_DRV_ST_TEST_STATUS2[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_DRV_ST_TEST_STATUS3\", REG_DUMP_DRV_ST_TEST_STATUS3[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_BOOT_RANGE\", REG_DUMP_BOOT_RANGE[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_BOOT_CMD\", REG_DUMP_BOOT_CMD[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_BOOT_STATUS\", REG_DUMP_BOOT_STATUS[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_BOOT_DBG\", REG_DUMP_BOOT_DBG[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_BOOT_LAST_DATA\", REG_DUMP_BOOT_LAST_DATA[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_OTP_ADDR\", REG_DUMP_OTP_ADDR[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_OTP_DATA\", REG_DUMP_OTP_DATA[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_OTP_CMD\", REG_DUMP_OTP_CMD[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_OTP_IDX\", REG_DUMP_OTP_IDX[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_OTP_PROG_EN\", REG_DUMP_OTP_PROG_EN[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_OTP_STATUS\", REG_DUMP_OTP_STATUS[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_OTP_TEST_CFG\", REG_DUMP_OTP_TEST_CFG[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_OTP_TEST_CLVWR\", REG_DUMP_OTP_TEST_CLVWR[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_OTP_TEST_DBG\", REG_DUMP_OTP_TEST_DBG[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_NVM_DIR_ADDR\", REG_DUMP_NVM_DIR_ADDR[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_NVM_DIR_DATA\", REG_DUMP_NVM_DIR_DATA[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_NVM_DIR_CMD\", REG_DUMP_NVM_DIR_CMD[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_NVM_DIR_STATUS\", REG_DUMP_NVM_DIR_STATUS[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_NVM_TEST_NVMCTRL_STATE\", REG_DUMP_NVM_TEST_NVMCTRL_STATE[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_NVM_TEST_CTRL\", REG_DUMP_NVM_TEST_CTRL[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_NVM_WRITE_PROT_CTRL\", REG_DUMP_NVM_WRITE_PROT_CTRL[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_NVM_TEST\", REG_DUMP_NVM_TEST[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_DTB3\", REG_DUMP_DTB3[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_DTB1\", REG_DUMP_DTB1[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_FASTSO_CONF\", REG_DUMP_FASTSO_CONF[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEST_SCAN\", REG_DUMP_TEST_SCAN[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TEST_I2C_DEL\", REG_DUMP_TEST_I2C_DEL[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TM_ADDR\", REG_DUMP_TM_ADDR[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TM_CONF\", REG_DUMP_TM_CONF[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TM_GYR\", REG_DUMP_TM_GYR[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TM_TEMP\", REG_DUMP_TM_TEMP[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TM_PIN\", REG_DUMP_TM_PIN[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_TM_PWR\", REG_DUMP_TM_PWR[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_LUT_MEM2REG_IN\", REG_DUMP_LUT_MEM2REG_IN[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_LUT_MEM2REG_OUT\", REG_DUMP_LUT_MEM2REG_OUT[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_LUT_DUMMY\", REG_DUMP_LUT_DUMMY[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_SUP_CRC\", REG_DUMP_SUP_CRC[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_SUP_CRC_IN\", REG_DUMP_SUP_CRC_IN[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"REG_DUMP_ARB_FORCE_CTRL\", REG_DUMP_ARB_FORCE_CTRL[CURRENT_SITE_NUMBER()-1]);\n // Auto_Code_Judge_and_log\n\n TestLog(\"REG_DUMP_CHIP_ID\", REG_DUMP_CHIP_ID[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ERR_REG\", REG_DUMP_ERR_REG[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_HIF_TRIM_0\", REG_DUMP_HIF_TRIM_0[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_HIF_CONFIG\", REG_DUMP_HIF_CONFIG[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_I3C_TC_SYNC_TPH\", REG_DUMP_I3C_TC_SYNC_TPH[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_I3C_TC_SYNC_TU\", REG_DUMP_I3C_TC_SYNC_TU[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_I3C_TC_SYNC_ODR\", REG_DUMP_I3C_TC_SYNC_ODR[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_I3C_TC_SYNC_DT\", REG_DUMP_I3C_TC_SYNC_DT[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_I3C_TC_SYNC_ST0\", REG_DUMP_I3C_TC_SYNC_ST0[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_I3C_TC_SYNC_ST1\", REG_DUMP_I3C_TC_SYNC_ST1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_LEG_ERR_REG\", REG_DUMP_LEG_ERR_REG[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_REV_ID\", REG_DUMP_REV_ID[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_OCP_MASK\", REG_DUMP_OCP_MASK[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_CMD\", REG_DUMP_CMD[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_EXT_MODE\", REG_DUMP_EXT_MODE[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_STATUS\", REG_DUMP_STATUS[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_DATA_X_LSB\", REG_DUMP_ACC_DATA_X_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_DATA_X_MSB\", REG_DUMP_ACC_DATA_X_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_DATA_Y_LSB\", REG_DUMP_ACC_DATA_Y_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_DATA_Y_MSB\", REG_DUMP_ACC_DATA_Y_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_DATA_Z_LSB\", REG_DUMP_ACC_DATA_Z_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_DATA_Z_MSB\", REG_DUMP_ACC_DATA_Z_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_DATA_X_LSB\", REG_DUMP_GYR_DATA_X_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_DATA_X_MSB\", REG_DUMP_GYR_DATA_X_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_DATA_Y_LSB\", REG_DUMP_GYR_DATA_Y_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_DATA_Y_MSB\", REG_DUMP_GYR_DATA_Y_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_DATA_Z_LSB\", REG_DUMP_GYR_DATA_Z_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_DATA_Z_MSB\", REG_DUMP_GYR_DATA_Z_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_DATA\", REG_DUMP_TEMP_DATA[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_SENSORTIME_DATA_LSB\", REG_DUMP_SENSORTIME_DATA_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_SENSORTIME_DATA_MSB\", REG_DUMP_SENSORTIME_DATA_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MUTE\", REG_DUMP_MUTE[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_GP_0\", REG_DUMP_MCU_GP_0[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_GP_1\", REG_DUMP_MCU_GP_1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_GP_2\", REG_DUMP_MCU_GP_2[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_GP_STATUS\", REG_DUMP_MCU_GP_STATUS[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_GP_DIR\", REG_DUMP_MCU_GP_DIR[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_SH_MASK\", REG_DUMP_SH_MASK[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_SH_STATUS\", REG_DUMP_SH_STATUS[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_SH_TEMP_DATA\", REG_DUMP_SH_TEMP_DATA[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_SH_ACC_DATA_X_LSB\", REG_DUMP_SH_ACC_DATA_X_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_SH_ACC_DATA_X_MSB\", REG_DUMP_SH_ACC_DATA_X_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_SH_ACC_DATA_Y_LSB\", REG_DUMP_SH_ACC_DATA_Y_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_SH_ACC_DATA_Y_MSB\", REG_DUMP_SH_ACC_DATA_Y_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_SH_ACC_DATA_Z_LSB\", REG_DUMP_SH_ACC_DATA_Z_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_SH_ACC_DATA_Z_MSB\", REG_DUMP_SH_ACC_DATA_Z_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_SH_GYR_DATA_X_LSB\", REG_DUMP_SH_GYR_DATA_X_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_SH_GYR_DATA_X_MSB\", REG_DUMP_SH_GYR_DATA_X_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_SH_GYR_DATA_Y_LSB\", REG_DUMP_SH_GYR_DATA_Y_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_SH_GYR_DATA_Y_MSB\", REG_DUMP_SH_GYR_DATA_Y_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_SH_GYR_DATA_Z_LSB\", REG_DUMP_SH_GYR_DATA_Z_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_SH_GYR_DATA_Z_MSB\", REG_DUMP_SH_GYR_DATA_Z_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_ACC_DATA_X_LSB\", REG_DUMP_MCU_ACC_DATA_X_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_ACC_DATA_X_MSB\", REG_DUMP_MCU_ACC_DATA_X_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_ACC_DATA_Y_LSB\", REG_DUMP_MCU_ACC_DATA_Y_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_ACC_DATA_Y_MSB\", REG_DUMP_MCU_ACC_DATA_Y_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_ACC_DATA_Z_LSB\", REG_DUMP_MCU_ACC_DATA_Z_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_ACC_DATA_Z_MSB\", REG_DUMP_MCU_ACC_DATA_Z_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_GYR_DATA_X_LSB\", REG_DUMP_MCU_GYR_DATA_X_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_GYR_DATA_X_MSB\", REG_DUMP_MCU_GYR_DATA_X_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_GYR_DATA_Y_LSB\", REG_DUMP_MCU_GYR_DATA_Y_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_GYR_DATA_Y_MSB\", REG_DUMP_MCU_GYR_DATA_Y_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_GYR_DATA_Z_LSB\", REG_DUMP_MCU_GYR_DATA_Z_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_GYR_DATA_Z_MSB\", REG_DUMP_MCU_GYR_DATA_Z_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_RAW_SENSORTIME_LSB\", REG_DUMP_RAW_SENSORTIME_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_RAW_SENSORTIME_MSB\", REG_DUMP_RAW_SENSORTIME_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_LEG_STATUS\", REG_DUMP_LEG_STATUS[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_LEG_ACC_DATA_X\", REG_DUMP_LEG_ACC_DATA_X[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_LEG_ACC_DATA_Y\", REG_DUMP_LEG_ACC_DATA_Y[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_LEG_ACC_DATA_Z\", REG_DUMP_LEG_ACC_DATA_Z[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_LEG_GYR_DATA_X\", REG_DUMP_LEG_GYR_DATA_X[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_LEG_GYR_DATA_Y\", REG_DUMP_LEG_GYR_DATA_Y[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_LEG_GYR_DATA_Z\", REG_DUMP_LEG_GYR_DATA_Z[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_LEG_TEMP_DATA\", REG_DUMP_LEG_TEMP_DATA[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_LEG_SENSORTIME_DATA_LSB\", REG_DUMP_LEG_SENSORTIME_DATA_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_LEG_SENSORTIME_DATA_MSB\", REG_DUMP_LEG_SENSORTIME_DATA_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_SAT_FLAGS\", REG_DUMP_SAT_FLAGS[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_PP_ACTIVE_STATUS\", REG_DUMP_PP_ACTIVE_STATUS[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_GP_OIS_0_SYS\", REG_DUMP_MCU_GP_OIS_0_SYS[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_GP_OIS_1_SYS\", REG_DUMP_MCU_GP_OIS_1_SYS[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_GP_OIS_STATUS_SYS\", REG_DUMP_MCU_GP_OIS_STATUS_SYS[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_GP_OIS_DIR\", REG_DUMP_MCU_GP_OIS_DIR[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_OIS_STATUS_SYS\", REG_DUMP_MCU_OIS_STATUS_SYS[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MUTE_OIS\", REG_DUMP_MUTE_OIS[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_SH_MASK_OIS\", REG_DUMP_SH_MASK_OIS[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_SH_STATUS_OIS\", REG_DUMP_SH_STATUS_OIS[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_SH_OIS_ACC_DATA_X\", REG_DUMP_SH_OIS_ACC_DATA_X[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_SH_OIS_ACC_DATA_Y\", REG_DUMP_SH_OIS_ACC_DATA_Y[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_SH_OIS_ACC_DATA_Z\", REG_DUMP_SH_OIS_ACC_DATA_Z[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_SH_OIS_GYR_DATA_X\", REG_DUMP_SH_OIS_GYR_DATA_X[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_SH_OIS_GYR_DATA_Y\", REG_DUMP_SH_OIS_GYR_DATA_Y[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_SH_OIS_GYR_DATA_Z\", REG_DUMP_SH_OIS_GYR_DATA_Z[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_INT_STATUS_INT1\", REG_DUMP_INT_STATUS_INT1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_INT_STATUS_INT2\", REG_DUMP_INT_STATUS_INT2[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_INT_STATUS_IBI\", REG_DUMP_INT_STATUS_IBI[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_INT_CONF\", REG_DUMP_INT_CONF[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_INT_MAP_HW\", REG_DUMP_INT_MAP_HW[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_INT_MAP_MCU\", REG_DUMP_INT_MAP_MCU[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_INT_MCU_SET\", REG_DUMP_INT_MCU_SET[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_INT_IBI_MANDATORY\", REG_DUMP_INT_IBI_MANDATORY[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_INT_IBI_CCC_GETSTATUS\", REG_DUMP_INT_IBI_CCC_GETSTATUS[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_FIFO_FILL_LVL\", REG_DUMP_FIFO_FILL_LVL[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_FIFO_DATA\", REG_DUMP_FIFO_DATA[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_FIFO_WATERMARK\", REG_DUMP_FIFO_WATERMARK[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_FIFO_CONF\", REG_DUMP_FIFO_CONF[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_FIFO_CTRL\", REG_DUMP_FIFO_CTRL[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_OIS_CONF\", REG_DUMP_OIS_CONF[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_FCU_TRIM_0\", REG_DUMP_FCU_TRIM_0[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_FCU_TRIM_1\", REG_DUMP_FCU_TRIM_1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_WLT_TEST_CNT\", REG_DUMP_WLT_TEST_CNT[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_FCU_TEST_CONF\", REG_DUMP_FCU_TEST_CONF[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_FCU_TEST_CMD\", REG_DUMP_FCU_TEST_CMD[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ALT_CMD\", REG_DUMP_ALT_CMD[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_DP_CONF\", REG_DUMP_MCU_DP_CONF[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_PP_CONF\", REG_DUMP_MCU_PP_CONF[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_FILTER_CONF\", REG_DUMP_FILTER_CONF[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_CONF\", REG_DUMP_ACC_CONF[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_CONF\", REG_DUMP_GYR_CONF[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ALT_FILTER_CONF\", REG_DUMP_ALT_FILTER_CONF[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ALT_ACC_CONF\", REG_DUMP_ALT_ACC_CONF[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ALT_GYR_CONF\", REG_DUMP_ALT_GYR_CONF[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ALT_CONF\", REG_DUMP_ALT_CONF[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ALT_STATUS\", REG_DUMP_ALT_STATUS[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_SELFTEST_STATUS\", REG_DUMP_SELFTEST_STATUS[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_FCU_DBG_0\", REG_DUMP_FCU_DBG_0[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_FCU_DBG_1\", REG_DUMP_FCU_DBG_1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_I3C_CCC_GETXTIME\", REG_DUMP_I3C_CCC_GETXTIME [CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_FILTER_STATUS\", REG_DUMP_FILTER_STATUS[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_STATUS\", REG_DUMP_ACC_STATUS[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_STATUS\", REG_DUMP_GYR_STATUS[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_LEGACY_CONF\", REG_DUMP_LEGACY_CONF[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_PWR_CONF\", REG_DUMP_PWR_CONF[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_PRIV_UNLOCK\", REG_DUMP_MCU_PRIV_UNLOCK[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_PRIV_STAT\", REG_DUMP_MCU_PRIV_STAT[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_PRIV_LOCK\", REG_DUMP_MCU_PRIV_LOCK[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_CONF\", REG_DUMP_MCU_CONF[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_CTRL\", REG_DUMP_MCU_CTRL[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_INT_STATUS1\", REG_DUMP_MCU_INT_STATUS1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_INT_STATUS2\", REG_DUMP_MCU_INT_STATUS2[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_INT_EN1\", REG_DUMP_MCU_INT_EN1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_INT_EN2\", REG_DUMP_MCU_INT_EN2[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_INT_DIS1\", REG_DUMP_MCU_INT_DIS1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_INT_DIS2\", REG_DUMP_MCU_INT_DIS2[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_GPT_CSR\", REG_DUMP_MCU_GPT_CSR[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_GPT_RVR\", REG_DUMP_MCU_GPT_RVR[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_GPT_CVR\", REG_DUMP_MCU_GPT_CVR[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_DMA_LOB\", REG_DUMP_MCU_DMA_LOB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_DMA_UPB\", REG_DUMP_MCU_DMA_UPB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_SW_STATUS0\", REG_DUMP_MCU_SW_STATUS0[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_SW_STATUS1\", REG_DUMP_MCU_SW_STATUS1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_SW_STATUS2\", REG_DUMP_MCU_SW_STATUS2[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_SW_STATUS3\", REG_DUMP_MCU_SW_STATUS3[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_MEM_PWR\", REG_DUMP_MCU_MEM_PWR[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_MEM_MARGIN_TRIM\", REG_DUMP_MCU_MEM_MARGIN_TRIM[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_CMD_FEATURE_TRIG\", REG_DUMP_MCU_CMD_FEATURE_TRIG[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_GLOB_CTRL\", REG_DUMP_MCU_GLOB_CTRL[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_DMA_CTRL\", REG_DUMP_MCU_DMA_CTRL[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_DMA_WDATA\", REG_DUMP_MCU_DMA_WDATA[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_DMA_RDATA\", REG_DUMP_MCU_DMA_RDATA[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_STATUS\", REG_DUMP_MCU_STATUS[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_PC\", REG_DUMP_MCU_PC[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_SP\", REG_DUMP_MCU_SP[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_LR\", REG_DUMP_MCU_LR[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_SR_PIPE\", REG_DUMP_MCU_SR_PIPE[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_TEST\", REG_DUMP_MCU_TEST[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_DEBUG\", REG_DUMP_MCU_DEBUG[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_MCU_DMA_DEBUG\", REG_DUMP_MCU_DMA_DEBUG[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_LPWUP_EN\", REG_DUMP_LPWUP_EN[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_LPWUP_CFG\", REG_DUMP_LPWUP_CFG[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_LPWUP_STATUS\", REG_DUMP_LPWUP_STATUS[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_AASR_CONF_0\", REG_DUMP_ACC_AASR_CONF_0[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_AASR_CONF_1\", REG_DUMP_ACC_AASR_CONF_1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_AASR_STATUS\", REG_DUMP_ACC_AASR_STATUS[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_IO_PAD_TRM\", REG_DUMP_IO_PAD_TRM[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_IO_TEST_IF\", REG_DUMP_IO_TEST_IF[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_IO_INT_CTRL\", REG_DUMP_IO_INT_CTRL[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_IO_IF_CONF\", REG_DUMP_IO_IF_CONF[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_IO_PAD_STRENGTH\", REG_DUMP_IO_PAD_STRENGTH[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_IO_ODR_DEVIATION\", REG_DUMP_IO_ODR_DEVIATION[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_INT_IO_PAD_STRENGTH0\", REG_DUMP_INT_IO_PAD_STRENGTH0[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_INT_IO_PAD_STRENGTH1\", REG_DUMP_INT_IO_PAD_STRENGTH1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_SCB_PHI_A0_CH1\", REG_DUMP_GYR_SCB_PHI_A0_CH1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_SCB_PHI_A0_CH2\", REG_DUMP_GYR_SCB_PHI_A0_CH2[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_SCB_PHI_A0_CH3\", REG_DUMP_GYR_SCB_PHI_A0_CH3[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_SCB_PHI_A1_CH1\", REG_DUMP_GYR_SCB_PHI_A1_CH1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_SCB_PHI_A1_CH2\", REG_DUMP_GYR_SCB_PHI_A1_CH2[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_SCB_PHI_A1_CH3\", REG_DUMP_GYR_SCB_PHI_A1_CH3[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_SCB_OFF_B0_CH1\", REG_DUMP_GYR_SCB_OFF_B0_CH1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_SCB_OFF_B0_CH2\", REG_DUMP_GYR_SCB_OFF_B0_CH2[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_SCB_OFF_B0_CH3\", REG_DUMP_GYR_SCB_OFF_B0_CH3[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_SCB_OFF_B1_CH1\", REG_DUMP_GYR_SCB_OFF_B1_CH1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_SCB_OFF_B1_CH2\", REG_DUMP_GYR_SCB_OFF_B1_CH2[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_SCB_OFF_B1_CH3\", REG_DUMP_GYR_SCB_OFF_B1_CH3[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TRM_PHI_A0_CH1\", REG_DUMP_GYR_TRM_PHI_A0_CH1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TRM_PHI_A1_CH1\", REG_DUMP_GYR_TRM_PHI_A1_CH1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TRM_PHI_A0_CH2\", REG_DUMP_GYR_TRM_PHI_A0_CH2[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TRM_PHI_A1_CH2\", REG_DUMP_GYR_TRM_PHI_A1_CH2[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TRM_PHI_A0_CH3\", REG_DUMP_GYR_TRM_PHI_A0_CH3[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TRM_PHI_A1_CH3\", REG_DUMP_GYR_TRM_PHI_A1_CH3[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TRM_PHI_A2_CH1\", REG_DUMP_GYR_TRM_PHI_A2_CH1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TRM_PHI_A2_CH2\", REG_DUMP_GYR_TRM_PHI_A2_CH2[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TRM_PHI_A2_CH3\", REG_DUMP_GYR_TRM_PHI_A2_CH3[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TRM_OFF_B0_CH1\", REG_DUMP_GYR_TRM_OFF_B0_CH1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TRM_OFF_B1_CH1\", REG_DUMP_GYR_TRM_OFF_B1_CH1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TRM_OFF_B2_CH1_CH2\", REG_DUMP_GYR_TRM_OFF_B2_CH1_CH2[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TRM_OFF_B0_CH2\", REG_DUMP_GYR_TRM_OFF_B0_CH2[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TRM_OFF_B1_CH2\", REG_DUMP_GYR_TRM_OFF_B1_CH2[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TRM_OFF_B2_CH2_CH3\", REG_DUMP_GYR_TRM_OFF_B2_CH2_CH3[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TRM_OFF_B0_CH3\", REG_DUMP_GYR_TRM_OFF_B0_CH3[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TRM_OFF_B1_CH3\", REG_DUMP_GYR_TRM_OFF_B1_CH3[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TRM_DGAIN_S0_CH1\", REG_DUMP_GYR_TRM_DGAIN_S0_CH1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_ACC_TRM_DGAIN_S1_CH1\", REG_DUMP_GYR_ACC_TRM_DGAIN_S1_CH1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TRM_DGAIN_S0_CH2\", REG_DUMP_GYR_TRM_DGAIN_S0_CH2[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TRM_DGAIN_S1_CH2_CH3\", REG_DUMP_GYR_TRM_DGAIN_S1_CH2_CH3[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TRM_DGAIN_S0_CH3\", REG_DUMP_GYR_TRM_DGAIN_S0_CH3[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_TRM_OFF_B0_CH1\", REG_DUMP_ACC_TRM_OFF_B0_CH1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_TRM_OFF_B1_B2_CH1\", REG_DUMP_ACC_TRM_OFF_B1_B2_CH1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_TRM_OFF_B0_CH2\", REG_DUMP_ACC_TRM_OFF_B0_CH2[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_TRM_OFF_B1_B2_CH2\", REG_DUMP_ACC_TRM_OFF_B1_B2_CH2[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_TRM_OFF_B0_CH3\", REG_DUMP_ACC_TRM_OFF_B0_CH3[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_TRM_OFF_B1_B2_CH3\", REG_DUMP_ACC_TRM_OFF_B1_B2_CH3[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_TRM_DGAIN_S0_CH1\", REG_DUMP_ACC_TRM_DGAIN_S0_CH1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_TRM_DGAIN_S0_CH2\", REG_DUMP_ACC_TRM_DGAIN_S0_CH2[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_TRM_DGAIN_S0_CH3\", REG_DUMP_ACC_TRM_DGAIN_S0_CH3[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_TRM_DGAIN_S1_CH2_CH3\", REG_DUMP_ACC_TRM_DGAIN_S1_CH2_CH3[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_TRM_OFF_DGAIN\", REG_DUMP_TEMP_TRM_OFF_DGAIN[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_TRM_OFF_DT\", REG_DUMP_TEMP_TRM_OFF_DT[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_TRM_BG_OFF_DGAIN_NORM\", REG_DUMP_TEMP_TRM_BG_OFF_DGAIN_NORM[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_TEST_TADC\", REG_DUMP_TEMP_TEST_TADC[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_TEST\", REG_DUMP_TEMP_TEST[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_DT_HI\", REG_DUMP_TEMP_DT_HI[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_DT_LO\", REG_DUMP_TEMP_DT_LO[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_FWSPARE0_RO\", REG_DUMP_TEMP_FWSPARE0_RO[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_INTERNAL_TEMP_AXIS_CONF0\", REG_DUMP_INTERNAL_TEMP_AXIS_CONF0[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_INTERNAL_TEMP_AXIS_CONF1\", REG_DUMP_INTERNAL_TEMP_AXIS_CONF1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_AXIS_CONF\", REG_DUMP_TEMP_AXIS_CONF[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_USR_DGAIN_S0_X\", REG_DUMP_GYR_USR_DGAIN_S0_X[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_USR_DGAIN_S0_Y\", REG_DUMP_GYR_USR_DGAIN_S0_Y[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_USR_DGAIN_S0_Z\", REG_DUMP_GYR_USR_DGAIN_S0_Z[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_USR_DGAIN_S0_X\", REG_DUMP_ACC_USR_DGAIN_S0_X[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_USR_DGAIN_S0_Y\", REG_DUMP_ACC_USR_DGAIN_S0_Y[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_USR_DGAIN_S0_Z\", REG_DUMP_ACC_USR_DGAIN_S0_Z[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_CROSS_SY_CH12\", REG_DUMP_ACC_CROSS_SY_CH12[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_CROSS_SY_CH13\", REG_DUMP_ACC_CROSS_SY_CH13[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_CROSS_SY_CH21\", REG_DUMP_ACC_CROSS_SY_CH21[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_CROSS_SY_CH23\", REG_DUMP_ACC_CROSS_SY_CH23[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_CROSS_SY_CH31\", REG_DUMP_ACC_CROSS_SY_CH31[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_CROSS_SY_CH32\", REG_DUMP_ACC_CROSS_SY_CH32[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_TRM_DGAIN_8G_CH12\", REG_DUMP_ACC_TRM_DGAIN_8G_CH12[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_TRM_DGAIN_8G_CH3\", REG_DUMP_ACC_TRM_DGAIN_8G_CH3[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_TRM_OFF_STEP_8G_CH1\", REG_DUMP_ACC_TRM_OFF_STEP_8G_CH1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_TRM_OFF_STEP_8G_CH2\", REG_DUMP_ACC_TRM_OFF_STEP_8G_CH2[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_TRM_OFF_STEP_8G_CH3\", REG_DUMP_ACC_TRM_OFF_STEP_8G_CH3[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_TRM_OFF_STEP_ALP_8G_CH1\", REG_DUMP_ACC_TRM_OFF_STEP_ALP_8G_CH1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_TRM_OFF_STEP_ALP_8G_CH2\", REG_DUMP_ACC_TRM_OFF_STEP_ALP_8G_CH2[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_TRM_OFF_STEP_ALP_8G_CH3\", REG_DUMP_ACC_TRM_OFF_STEP_ALP_8G_CH3[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_TRM_OFF_STEP_ALP_32G_CH1\", REG_DUMP_ACC_TRM_OFF_STEP_ALP_32G_CH1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_TRM_OFF_STEP_ALP_32G_CH2\", REG_DUMP_ACC_TRM_OFF_STEP_ALP_32G_CH2[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_TRM_OFF_STEP_ALP_32G_CH3\", REG_DUMP_ACC_TRM_OFF_STEP_ALP_32G_CH3[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_COMP_CONF\", REG_DUMP_ACC_COMP_CONF[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_ACC_OFF_CH1_MSB\", REG_DUMP_TEMP_ACC_OFF_CH1_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_ACC_OFF_CH1_LSB\", REG_DUMP_TEMP_ACC_OFF_CH1_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_ACC_OFF_CH2_MSB\", REG_DUMP_TEMP_ACC_OFF_CH2_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_ACC_OFF_CH2_LSB\", REG_DUMP_TEMP_ACC_OFF_CH2_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_ACC_OFF_CH3_MSB\", REG_DUMP_TEMP_ACC_OFF_CH3_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_ACC_OFF_CH3_LSB\", REG_DUMP_TEMP_ACC_OFF_CH3_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_ACC_GAIN_CH1_MSB\", REG_DUMP_TEMP_ACC_GAIN_CH1_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_ACC_GAIN_CH1_LSB\", REG_DUMP_TEMP_ACC_GAIN_CH1_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_ACC_GAIN_CH2_MSB\", REG_DUMP_TEMP_ACC_GAIN_CH2_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_ACC_GAIN_CH2_LSB\", REG_DUMP_TEMP_ACC_GAIN_CH2_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_ACC_GAIN_CH3_MSB\", REG_DUMP_TEMP_ACC_GAIN_CH3_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_ACC_GAIN_CH3_LSB\", REG_DUMP_TEMP_ACC_GAIN_CH3_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_USR_OFF_32G_X\", REG_DUMP_ACC_USR_OFF_32G_X[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_USR_OFF_32G_Y\", REG_DUMP_ACC_USR_OFF_32G_Y[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_USR_OFF_32G_Z\", REG_DUMP_ACC_USR_OFF_32G_Z[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_USR_OFF_8G_X\", REG_DUMP_ACC_USR_OFF_8G_X[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_USR_OFF_8G_Y\", REG_DUMP_ACC_USR_OFF_8G_Y[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_USR_OFF_8G_Z\", REG_DUMP_ACC_USR_OFF_8G_Z[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_COMP_CONF_USR\", REG_DUMP_ACC_COMP_CONF_USR[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_CROSS_SY_CH12\", REG_DUMP_GYR_CROSS_SY_CH12[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_CROSS_SY_CH13\", REG_DUMP_GYR_CROSS_SY_CH13[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_CROSS_SY_CH21\", REG_DUMP_GYR_CROSS_SY_CH21[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_CROSS_SY_CH23\", REG_DUMP_GYR_CROSS_SY_CH23[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_CROSS_SY_CH31\", REG_DUMP_GYR_CROSS_SY_CH31[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_CROSS_SY_CH32\", REG_DUMP_GYR_CROSS_SY_CH32[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_QUAD_TRM_CH1\", REG_DUMP_GYR_QUAD_TRM_CH1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_QUAD_TRM_CH2\", REG_DUMP_GYR_QUAD_TRM_CH2[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_QUAD_TRM_CH3\", REG_DUMP_GYR_QUAD_TRM_CH3[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_COMP_CONF\", REG_DUMP_GYR_COMP_CONF[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_GYR_OFF_CH1_MSB\", REG_DUMP_TEMP_GYR_OFF_CH1_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_GYR_OFF_CH1_LSB\", REG_DUMP_TEMP_GYR_OFF_CH1_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_GYR_OFF_CH2_MSB\", REG_DUMP_TEMP_GYR_OFF_CH2_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_GYR_OFF_CH2_LSB\", REG_DUMP_TEMP_GYR_OFF_CH2_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_GYR_OFF_CH3_MSB\", REG_DUMP_TEMP_GYR_OFF_CH3_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_GYR_OFF_CH3_LSB\", REG_DUMP_TEMP_GYR_OFF_CH3_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_GYR_GAIN_CH1_MSB\", REG_DUMP_TEMP_GYR_GAIN_CH1_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_GYR_GAIN_CH1_LSB\", REG_DUMP_TEMP_GYR_GAIN_CH1_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_GYR_GAIN_CH2_MSB\", REG_DUMP_TEMP_GYR_GAIN_CH2_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_GYR_GAIN_CH2_LSB\", REG_DUMP_TEMP_GYR_GAIN_CH2_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_GYR_GAIN_CH3_MSB\", REG_DUMP_TEMP_GYR_GAIN_CH3_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_GYR_GAIN_CH3_LSB\", REG_DUMP_TEMP_GYR_GAIN_CH3_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_GYR_PHI_CH1_MSB\", REG_DUMP_TEMP_GYR_PHI_CH1_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_GYR_PHI_CH1_LSB\", REG_DUMP_TEMP_GYR_PHI_CH1_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_GYR_PHI_CH2_MSB\", REG_DUMP_TEMP_GYR_PHI_CH2_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_GYR_PHI_CH2_LSB\", REG_DUMP_TEMP_GYR_PHI_CH2_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_GYR_PHI_CH3_MSB\", REG_DUMP_TEMP_GYR_PHI_CH3_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_GYR_PHI_CH3_LSB\", REG_DUMP_TEMP_GYR_PHI_CH3_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_ALP_TRM_PHI_CH12\", REG_DUMP_GYR_ALP_TRM_PHI_CH12[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_ALP_TRM_PHI_CH23\", REG_DUMP_GYR_ALP_TRM_PHI_CH23[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_ALP_TRM_OFF_CH1\", REG_DUMP_GYR_ALP_TRM_OFF_CH1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_ALP_TRM_OFF_CH2\", REG_DUMP_GYR_ALP_TRM_OFF_CH2[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_ALP_TRM_OFF_CH3\", REG_DUMP_GYR_ALP_TRM_OFF_CH3[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_USR_OFF_B0_X\", REG_DUMP_GYR_USR_OFF_B0_X[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_USR_OFF_B0_Y\", REG_DUMP_GYR_USR_OFF_B0_Y[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_USR_OFF_B0_Z\", REG_DUMP_GYR_USR_OFF_B0_Z[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_COMP_CONF_USR\", REG_DUMP_GYR_COMP_CONF_USR[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ANA_TRM_BG\", REG_DUMP_ANA_TRM_BG[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ANA_TRM_PMU\", REG_DUMP_ANA_TRM_PMU[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ANA_TRM_PMU1\", REG_DUMP_ANA_TRM_PMU1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ANA_TRM_OSC\", REG_DUMP_ANA_TRM_OSC[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ANA_TRM_RES_PROG0\", REG_DUMP_ANA_TRM_RES_PROG0[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ANA_TRM_RES_PROG1\", REG_DUMP_ANA_TRM_RES_PROG1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ANA_TRM_RES_PROG2\", REG_DUMP_ANA_TRM_RES_PROG2[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ANA_TRM_CAP_PROG0\", REG_DUMP_ANA_TRM_CAP_PROG0[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ANA_TRM_CAP_PROG_CH1\", REG_DUMP_ANA_TRM_CAP_PROG_CH1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ANA_TRM_CAP_PROG_CH2\", REG_DUMP_ANA_TRM_CAP_PROG_CH2[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ANA_TRM_CAP_PROG_CH3\", REG_DUMP_ANA_TRM_CAP_PROG_CH3[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ANA_TRM_CAP_PROG_DRV\", REG_DUMP_ANA_TRM_CAP_PROG_DRV[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ANA_TRM_ACC_CH1\", REG_DUMP_ANA_TRM_ACC_CH1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ANA_TRM_ACC_CH2\", REG_DUMP_ANA_TRM_ACC_CH2[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ANA_TRM_ACC_CH3\", REG_DUMP_ANA_TRM_ACC_CH3[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ANA_TEST_PWR\", REG_DUMP_ANA_TEST_PWR[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TEST_EN\", REG_DUMP_GYR_TEST_EN[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TEST_WFR\", REG_DUMP_GYR_TEST_WFR[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TEST_INT_SEL\", REG_DUMP_GYR_TEST_INT_SEL[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_TEST_ADC\", REG_DUMP_TEMP_TEST_ADC[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TEST_AA_AI\", REG_DUMP_GYR_TEST_AA_AI[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TEST_OWR1\", REG_DUMP_GYR_TEST_OWR1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TEST_OWR2\", REG_DUMP_GYR_TEST_OWR2[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TEST_OWR_RST\", REG_DUMP_GYR_TEST_OWR_RST[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_PMU_TEST_OWR\", REG_DUMP_PMU_TEST_OWR[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_PMU_TEST_DPWR_CTRL\", REG_DUMP_PMU_TEST_DPWR_CTRL[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_PMU_TEST_MISC\", REG_DUMP_PMU_TEST_MISC[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_VGM_MON_CTRL\", REG_DUMP_GYR_VGM_MON_CTRL[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_PMU_ERROR\", REG_DUMP_PMU_ERROR[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_STATUS_CORE_FSM\", REG_DUMP_STATUS_CORE_FSM[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_STATUS_GYR_FSM\", REG_DUMP_STATUS_GYR_FSM[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_STATUS_PMOD0\", REG_DUMP_STATUS_PMOD0[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_STATUS_PMOD1\", REG_DUMP_STATUS_PMOD1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_STATUS_PMOD2\", REG_DUMP_STATUS_PMOD2[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_STATUS_PMOD3\", REG_DUMP_STATUS_PMOD3[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_STATUS_DPWR\", REG_DUMP_STATUS_DPWR[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_TRM_CTRL\", REG_DUMP_TEMP_TRM_CTRL[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEMP_TEST_FSM\", REG_DUMP_TEMP_TEST_FSM[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_TRM_CFB\", REG_DUMP_ACC_TRM_CFB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_TRM_LOOPG\", REG_DUMP_ACC_TRM_LOOPG[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_TRM_CTRL\", REG_DUMP_ACC_TRM_CTRL[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_TEST_ST_CTRL\", REG_DUMP_ACC_TEST_ST_CTRL[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_TEST_ST_LFSR_SEED\", REG_DUMP_ACC_TEST_ST_LFSR_SEED[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_TEST_ST_LFSR_VAL\", REG_DUMP_ACC_TEST_ST_LFSR_VAL[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_TEST_CTRL\", REG_DUMP_ACC_TEST_CTRL[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ACC_AFE_AASR_CONF\", REG_DUMP_ACC_AFE_AASR_CONF[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TRM_NOTCH12_GRPC\", REG_DUMP_GYR_TRM_NOTCH12_GRPC[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TRM_NOTCH3_MISC\", REG_DUMP_GYR_TRM_NOTCH3_MISC[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TRM_BYP_MASH\", REG_DUMP_GYR_TRM_BYP_MASH[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TEST_TOSK\", REG_DUMP_GYR_TEST_TOSK[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TEST_QUAD1_LSB\", REG_DUMP_GYR_TEST_QUAD1_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TEST_QUAD1_MSB\", REG_DUMP_GYR_TEST_QUAD1_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TEST_QUAD2_LSB\", REG_DUMP_GYR_TEST_QUAD2_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TEST_QUAD2_MSB\", REG_DUMP_GYR_TEST_QUAD2_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TEST_QUAD3_LSB\", REG_DUMP_GYR_TEST_QUAD3_LSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TEST_QUAD3_MSB\", REG_DUMP_GYR_TEST_QUAD3_MSB[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TEST_FSM\", REG_DUMP_GYR_TEST_FSM[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TEST_FILT\", REG_DUMP_GYR_TEST_FILT[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TEST_IQMOD_SIN1\", REG_DUMP_GYR_TEST_IQMOD_SIN1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TEST_IQMOD_SIN2\", REG_DUMP_GYR_TEST_IQMOD_SIN2[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TEST_IQMOD_COS1\", REG_DUMP_GYR_TEST_IQMOD_COS1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TEST_IQMOD_COS2\", REG_DUMP_GYR_TEST_IQMOD_COS2[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_GYR_TEST_CLAMP\", REG_DUMP_GYR_TEST_CLAMP[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_DRV_ST_TRM\", REG_DUMP_DRV_ST_TRM[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_DRV_ST_TEST_STATUS1\", REG_DUMP_DRV_ST_TEST_STATUS1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_DRV_ST_TEST_STATUS2\", REG_DUMP_DRV_ST_TEST_STATUS2[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_DRV_ST_TEST_STATUS3\", REG_DUMP_DRV_ST_TEST_STATUS3[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_BOOT_RANGE\", REG_DUMP_BOOT_RANGE[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_BOOT_CMD\", REG_DUMP_BOOT_CMD[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_BOOT_STATUS\", REG_DUMP_BOOT_STATUS[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_BOOT_DBG\", REG_DUMP_BOOT_DBG[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_BOOT_LAST_DATA\", REG_DUMP_BOOT_LAST_DATA[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_OTP_ADDR\", REG_DUMP_OTP_ADDR[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_OTP_DATA\", REG_DUMP_OTP_DATA[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_OTP_CMD\", REG_DUMP_OTP_CMD[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_OTP_IDX\", REG_DUMP_OTP_IDX[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_OTP_PROG_EN\", REG_DUMP_OTP_PROG_EN[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_OTP_STATUS\", REG_DUMP_OTP_STATUS[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_OTP_TEST_CFG\", REG_DUMP_OTP_TEST_CFG[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_OTP_TEST_CLVWR\", REG_DUMP_OTP_TEST_CLVWR[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_OTP_TEST_DBG\", REG_DUMP_OTP_TEST_DBG[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_NVM_DIR_ADDR\", REG_DUMP_NVM_DIR_ADDR[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_NVM_DIR_DATA\", REG_DUMP_NVM_DIR_DATA[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_NVM_DIR_CMD\", REG_DUMP_NVM_DIR_CMD[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_NVM_DIR_STATUS\", REG_DUMP_NVM_DIR_STATUS[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_NVM_TEST_NVMCTRL_STATE\", REG_DUMP_NVM_TEST_NVMCTRL_STATE[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_NVM_TEST_CTRL\", REG_DUMP_NVM_TEST_CTRL[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_NVM_WRITE_PROT_CTRL\", REG_DUMP_NVM_WRITE_PROT_CTRL[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_NVM_TEST\", REG_DUMP_NVM_TEST[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_DTB3\", REG_DUMP_DTB3[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_DTB1\", REG_DUMP_DTB1[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_FASTSO_CONF\", REG_DUMP_FASTSO_CONF[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEST_SCAN\", REG_DUMP_TEST_SCAN[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TEST_I2C_DEL\", REG_DUMP_TEST_I2C_DEL[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TM_ADDR\", REG_DUMP_TM_ADDR[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TM_CONF\", REG_DUMP_TM_CONF[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TM_GYR\", REG_DUMP_TM_GYR[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TM_TEMP\", REG_DUMP_TM_TEMP[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TM_PIN\", REG_DUMP_TM_PIN[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_TM_PWR\", REG_DUMP_TM_PWR[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_LUT_MEM2REG_IN\", REG_DUMP_LUT_MEM2REG_IN[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_LUT_MEM2REG_OUT\", REG_DUMP_LUT_MEM2REG_OUT[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_LUT_DUMMY\", REG_DUMP_LUT_DUMMY[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_SUP_CRC\", REG_DUMP_SUP_CRC[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_SUP_CRC_IN\", REG_DUMP_SUP_CRC_IN[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"REG_DUMP_ARB_FORCE_CTRL\", REG_DUMP_ARB_FORCE_CTRL[CURRENT_SITE_NUMBER()-1]);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T20_30_register_dump_V1\", T20_30_register_dump_V1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: Read WLT logbit\n# - Dark OTP, regid 0xCE bit 8 used to store WLT test status infomation\n#############################################################################################################\ncmt('Version info: $Revision: 1 $ $Author: hmf1rt $ $Date: 2024/03/13 13:36:52 GMT $')\nwac('EXT_MODE', 0xc00d) # Switch to PMU register page\nwcb('nvmotp_power_en',0x1) # Request OTP power\ndly(300e-6) \nwac('EXT_MODE', 0xc00f) # Switch to OTPCTRL register page\nwac('OTP_DATA', 0x0000) # Reset OTP data register\n# Read data from OTP \nwac('BOOT_RANGE', 0xcece) # Set register ID for dark OTP load\nrac('BOOT_STATUS', 0x0001) # Check boot controller ready and error bits\nwr('BOOT_CMD', 0x0001) # Trigger OTP load\ndly(1.2e-3)\nras('REG_WLT_LOGBIT', 'BOOT_LAST_DATA') # Read and store data\nlog('REG_WLT_LOGBIT')\n# Clean-up \nwac('BOOT_RANGE', 0x0000)\nwac('EXT_MODE', 0xc00d) # Switch to PMU register page\nwcb('nvmotp_power_en',0x0) # Disable OTP power\ndly(100e-6)\n", "output": "/*****************************************************\n * T20_33_Read_Asic_WLT_Logbit_V1, description file version Notfound, avc file version Notfound\n * First Editor : ayh2sgh\n * Code generated with autocoding tool V2.8.1, in TOI2 standard way by module write_standard\n * Change History:\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\"\n#include \"../Common.hpp\"\nusing namespace std;\n\nclass T20_33_Read_Asic_WLT_Logbit_V1: public testmethod::TestMethod {\n\n protected:\n int i_funcRes[xNSitES];\n \nvirtual void initialize()\n {\n }\n\n virtual void run()\n {\n\t static int iVDD_Spec;\n\t GET_USER_FLAG(\"VDD_Spec\",\t\t\t&iVDD_Spec);\n\t if (iVDD_Spec >1)\n\t\t return;\n\n const string s_label_name = Primary.getLabel();//CodingTool:Till this line by write_xpart_head_pure_func() \n INT i_split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &i_split_pat_flag);\n vector s_splited_pat_name;\n s_splited_pat_name.resize(1);\n s_splited_pat_name[0] = s_label_name;\n const int i_split_count = 1;\n vector i_comment_line[i_split_count];\n\n static int i_REG_WLT_LOGBIT[xNSitES];\n ARRAY_I aI_Captured_0;\n static int i_funcRes0[xNSitES];\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n Func_Init_Var(i_funcRes, 0, xNSitES);\n Func_Init_Var(i_REG_WLT_LOGBIT, 9, xNSitES);\n i_comment_line[0] = search_comment_line_specialOnly(s_label_name, \"search_here\");\n print_key_comment(s_label_name, i_comment_line[0], printFlag);\n\n /* Ori key coments in subpat0 ~~~~~~~~~~~~~~\n valid comment[ 0] @ avcline 10: {Test Start: T20_33_Read_Asic_WLT_Logbit}\n valid comment[ 0] @ avcline 10: {cmt: Version info: }\n valid comment[ 1] @ avcline 1336: {ras('REG_WLT_LOGBIT', 'BOOT_LAST_DATA')}\n valid comment[ 2] @ avcline 1449: {log('REG_WLT_LOGBIT', '', '', 0, 0)}\n valid comment[ 3] @ avcline 2194: {Test End: T20_33_Read_Asic_WLT_Logbit}\n */\n RDI_BEGIN(mode);\n rdi.burstId(\"burst_id0\");\n rdi.digCap(\"digcapid_0\").label(s_splited_pat_name[0]).pin(\"SDO\").capMode(TA::SER).bitPerWord(16).samples(1*16).execute();\n RDI_END();\n FOR_EACH_SITE_BEGIN();\n i_funcRes0[curSite] = rdi.id(\"burst_id0\").getBurstPassFail();\n aI_Captured_0 = rdi.id(\"digcapid_0\").getVector(\"SDO\");\n aI_Captured_0[0] = Switch_High_Low_Bits_16Bits(aI_Captured_0[0]);\n i_REG_WLT_LOGBIT[curSite] = aI_Captured_0[0];\n FuncPrint(\"REG_WLT_LOGBIT\",i_REG_WLT_LOGBIT[curSite]);\n //Add calc code if necessary\n FOR_EACH_SITE_END();\n\n\n ON_FIRST_INVOCATION_END();\n\n TestLog(\"REG_WLT_LOGBIT\",i_REG_WLT_LOGBIT[curSite]);\n i_funcRes[curSite] = i_funcRes0[curSite];\n FuncPrint(\"Func_result\", i_funcRes[curSite]);\n TestLog(\"FUNCTIONAL_TEST\", i_funcRes[curSite]);\n return;//From this line writtern by write_xpart_foot()\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n return;\n }\n\n virtual const string getComment() const \n { string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"03_Char.T20_33_Read_Asic_WLT_Logbit_V1\", T20_33_Read_Asic_WLT_Logbit_V1);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "######################################################################################################################\n# Description: Calculation of the CRC checksum over the dark OTP IDs\n# Step 1: Read dark OTP registers content\n# Step 2: Calculate CRC checksum\n# Step 3: Write CRC checksum to dark OTP\n# Note: The IDs for the CRC checksums of OTP and NVM are included the dark OTP CRC checksum\n######################################################################################################################\nfrom test_sub_functions import *\n\ncmt('Version info: $Revision: 2 $ $Author: luz3sgh $ $Date: 2024/05/31 09:21:26 GMT $')\n\n# Load register table for ASIC only flow from subfunction file: dark_otp_config.py\ndark_otp = [ # DARK_OTP_ASIC defined in test_sub_function/otp_config\n #| OTP ID |name\n #+----------------------+ \n\t(0xcb, 'CRC_NVM'),\n\t(0xcc, 'CRC_OTP'),\n\t(0xce, 'LOGBIT'),\n\t(0xda, 'TB offsets'),\n\t(0xd0, 'SERIAL_ID0'),\n\t(0xd1, 'SERIAL_ID1'),\n\t(0xd2, 'SERIAL_ID2'),\n\t(0xd3, 'SERIAL_ID3'),\n\t(0xd4, 'TEST_PP'),\n\t(0xf1, 'MIM_CAP')\n]\n # add new registers here\n\n# Read programmed dark OTP content\nwac('EXT_MODE', 0xc00d) # Switch to PMU register page\nwcb('nvmotp_power_en',0x1) # Request OTP power\ndly(300e-6) \n# Read data from OTP\nwac('EXT_MODE', 0xc00f) # Switch to BOOT register page\nfor n in range (0, len(dark_otp), 1):\n wac('BOOT_RANGE', 256*dark_otp[n][0] + dark_otp[n][0])# Set register ID for dark OTP load\n rac('BOOT_STATUS', 0x0001) # Check boot controller ready and error bits\n wr('BOOT_CMD', 0x0001) # Trigger OTP load\n dly(1.2e-3) \n ras(f'crcdata_{n:02d}_{dark_otp[n][1]}', 'BOOT_LAST_DATA') # Read register and save data to crcdata_n\n\ncmt('Calculate the CRC-16 CCITT checksum for the {} data words crcdata_00-{:02d}'.format(len(dark_otp),len(dark_otp)-1))\ncmt('and store in variable CRC_CALC_DARKOTP')\n\ncalc('CRC_CALC_DARKOTP', 0xabcd) # Assign placeholder value for simulation, REPLACE with calculated CRC_CALC_DARKOTP\nlog('CRC_CALC_DARKOTP')\n\n# Program CRC_CALC_DARKOTP to OTP \nwac('EXT_MODE', 0xc00d) # Switch to PMU register page\nwcb('nvmotp_power_en',0x1) # Request OTP power\ndly(300e-6) \nwac('EXT_MODE', 0xc00f) # Switch to OTPCTRL register page\nwac('OTP_PROG_EN', 0x0002) # Enable OTP program\nwcb('vddp_sw', 0x1) # Connect VDDP to VDD\nsav('VDD', 3.6, v_range=4.0, i_comp=40e-3)\ndly(1e-3)\nwri('OTP_DATA', 'CRC_CALC_DARKOTP') # Write CRC_CALC_DARKOTP to OTP data register\nrac('OTP_STATUS', 0x0001) # Check OTP ready\nwr('OTP_CMD', 0x0005) # Trigger OTP data program\ndly(200e-6) # OTP spec, pgm speed 10us per bit\nwac('OTP_DATA',0xcd) # Set regID for dark OTP \nrac('OTP_STATUS', 0x0001) # Check OTP ready\nwr('OTP_CMD', 0x0006) # Trigger OTP reg_id program\ndly(200e-6) \nrac('OTP_STATUS', 0x0001) # Check OTP ready\nsav('VDD', 1.8, v_range=4.0, i_comp=40e-3)\ndly(1e-3)\nwac('OTP_PROG_EN', 0x0000) # Disable OTP program\nwcb('vddp_sw', 0x0) # Connect VDDP to VDDD_DC\nwac('OTP_DATA', 0x0000) # Reset OTP data register\n# Read data from OTP \nwac('BOOT_RANGE', 0xcdcd) # Set register ID for dark OTP load\nrac('BOOT_STATUS', 0x0001) # Check boot controller ready and error bits\nwr('BOOT_CMD', 0x0001) # Trigger OTP load\ndly(1.2e-3)\nras('CRC_CALC_DARKOTP_RD', 'BOOT_LAST_DATA') # Read and save OTP data\ncmt('This test item is a functional fail if CRC_CALC_DARKOTP_RD != CRC_CALC_DARKOTP')\n# Clean-up \nwac('BOOT_RANGE', 0x0000)\nwac('EXT_MODE', 0xc00d) # Switch to PMU register page\nwcb('nvmotp_power_en',0x0) # Disable OTP power\ndly(100e-6)\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T20_40_CRC_write_dark_OTP_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n INT split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &split_pat_flag);\n vector s_splited_pat_name;\n const int split_count = 4; // Alarm:: split_count need manual confirm.\n s_splited_pat_name.resize(split_count);\n vector i_comment_line[split_count];\n\n ARRAY_I crcdata(10);\n\n// static int crcdata_00_CRC_NVM[xNSitES];\n// static int crcdata_01_CRC_OTP[xNSitES];\n// static int crcdata_02_LOGBIT[xNSitES];\n// static int crcdata_03_TB_offsets[xNSitES];\n// static int crcdata_04_SERIAL_ID0[xNSitES];\n// static int crcdata_05_SERIAL_ID1[xNSitES];\n// static int crcdata_06_SERIAL_ID2[xNSitES];\n// static int crcdata_07_SERIAL_ID3[xNSitES];\n// static int crcdata_08_TEST_PP[xNSitES];\n// static int crcdata_09_MIM_CAP[xNSitES];\n static int CRC_CALC_DARKOTP_RD[xNSitES], CRC_CALC_DARKOTP[xNSitES];\n // Auto_Code_Variable_define\n ARRAY_LL CRC_CALC_DARKOTP_rtv(xNSitES);\n const int Wri_Bit_Length = 33;\n const int Wri_Bit_Position = 31;\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n GET_TESTSUITE_NAME(test_name);\n if (split_pat_flag)\n {\n \t split_pattern(s_label_name,\"wri\",\"sav\",split_pat_flag,s_splited_pat_name);\n }\n else\n {\n for (int i = 0; i i_comment_line0;\n\n// static int CRCDATA_00_CRC_NVM_CHECK[xNSitES];\n// static int CRCDATA_01_CRC_OTP_CHECK[xNSitES];\n// static int CRCDATA_02_LOGBIT_CHECK[xNSitES];\n// static int CRCDATA_03_TB_offsets_CHECK[xNSitES];\n// static int CRCDATA_04_SERIAL_ID0_CHECK[xNSitES];\n// static int CRCDATA_05_SERIAL_ID1_CHECK[xNSitES];\n// static int CRCDATA_06_SERIAL_ID2_CHECK[xNSitES];\n// static int CRCDATA_07_SERIAL_ID3_CHECK[xNSitES];\n// static int CRCDATA_08_TEST_PP_CHECK[xNSitES];\n// static int CRCDATA_09_MIM_CAP_CHECK[xNSitES];\n static int CRC_DARKOTP_RD[xNSitES];\n // Auto_Code_Variable_define\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T20_41_CRC_CHECK_dark_OTP_V2_PAT_id\");\n rdi.digCap(\"T20_41_CRC_CHECK_dark_OTP_V2_Digcap_id\").label(s_label_name)\n .pin(\"SDO\").capMode(TA::SER).samples(16*11).bitPerWord(16)\n .execute();\n RDI_END();\n\n // Auto_Code_Execution_Part\n\n\n\n ON_FIRST_INVOCATION_END();\n ARRAY_I Vec=rdi.id(\"T20_41_CRC_CHECK_dark_OTP_V2_Digcap_id\").getVector();\n// CRCDATA_00_CRC_NVM_CHECK[CURRENT_SITE_NUMBER()-1] = Vec[0];\n// CRCDATA_01_CRC_OTP_CHECK[CURRENT_SITE_NUMBER()-1] = Vec[1];\n// CRCDATA_02_LOGBIT_CHECK[CURRENT_SITE_NUMBER()-1] = Vec[2];\n// CRCDATA_03_TB_offsets_CHECK[CURRENT_SITE_NUMBER()-1] = Vec[3];\n// CRCDATA_04_SERIAL_ID0_CHECK[CURRENT_SITE_NUMBER()-1] = Vec[4];\n// CRCDATA_05_SERIAL_ID1_CHECK[CURRENT_SITE_NUMBER()-1] = Vec[5];\n// CRCDATA_06_SERIAL_ID2_CHECK[CURRENT_SITE_NUMBER()-1] = Vec[6];\n// CRCDATA_07_SERIAL_ID3_CHECK[CURRENT_SITE_NUMBER()-1] = Vec[7];\n// CRCDATA_08_TEST_PP_CHECK[CURRENT_SITE_NUMBER()-1] = Vec[8];\n// CRCDATA_09_MIM_CAP_CHECK[CURRENT_SITE_NUMBER()-1] = Vec[9];\n CRC_DARKOTP_RD[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[10]);\n\n // Auto_Code_Retrieve_Data\n \n int Func_result = rdi.id(\"T20_41_CRC_CHECK_dark_OTP_V2_PAT_id\").getBurstPassFail();\n\n\n ARRAY_I CRCDATA(10);\n// cout << \"size=\" << CRCDATA.size() << endl;\n // Auto_Code_Judge_and_log\n for (int i=0; i<10; i++)\n {\n \t CRCDATA[i] = reverse_ras_result(Vec[i]);\n }\n\n FuncPrint(\"CRCDATA_00_CRC_NVM_CHECK\", CRCDATA[0]);\n FuncPrint(\"CRCDATA_01_CRC_OTP_CHECK\", CRCDATA[1]);\n FuncPrint(\"CRCDATA_02_LOGBIT_CHECK\", CRCDATA[2]);\n FuncPrint(\"CRCDATA_03_TB_OFFSETS_CHECK\", CRCDATA[3]);\n FuncPrint(\"CRCDATA_04_SERIAL_ID0_CHECK\", CRCDATA[4]);\n FuncPrint(\"CRCDATA_05_SERIAL_ID1_CHECK\", CRCDATA[5]);\n FuncPrint(\"CRCDATA_06_SERIAL_ID2_CHECK\", CRCDATA[6]);\n FuncPrint(\"CRCDATA_07_SERIAL_ID3_CHECK\", CRCDATA[7]);\n FuncPrint(\"CRCDATA_08_TEST_PP_CHECK\", CRCDATA[8]);\n FuncPrint(\"CRCDATA_09_MIM_CAP_CHECK\", CRCDATA[9]);\n FuncPrint(\"CRC_DARKOTP_RD\", CRC_DARKOTP_RD[CURRENT_SITE_NUMBER()-1]);\n\n int CRC_CHECK_DARKOTP = CRC_16_CCITT(CRCDATA, 10);\n FuncPrint(\"CRC_CHECK_DARKOTP\", CRC_CHECK_DARKOTP);\n if (CRC_DARKOTP_RD[CURRENT_SITE_NUMBER()-1] != CRC_CHECK_DARKOTP) Func_result=99;\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n TestLog(\"CRCDATA_00_CRC_NVM_CHECK\", CRCDATA[0]);\n TestLog(\"CRCDATA_01_CRC_OTP_CHECK\", CRCDATA[1]);\n TestLog(\"CRCDATA_02_LOGBIT_CHECK\", CRCDATA[2]);\n TestLog(\"CRCDATA_03_TB OFFSETS_CHECK\", CRCDATA[3]);\n TestLog(\"CRCDATA_04_SERIAL_ID0_CHECK\", CRCDATA[4]);\n TestLog(\"CRCDATA_05_SERIAL_ID1_CHECK\", CRCDATA[5]);\n TestLog(\"CRCDATA_06_SERIAL_ID2_CHECK\", CRCDATA[6]);\n TestLog(\"CRCDATA_07_SERIAL_ID3_CHECK\", CRCDATA[7]);\n TestLog(\"CRCDATA_08_TEST_PP_CHECK\", CRCDATA[8]);\n TestLog(\"CRCDATA_09_MIM_CAP_CHECK\", CRCDATA[9]);\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T20_41_CRC_CHECK_dark_OTP_V2\", T20_41_CRC_CHECK_dark_OTP_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "######################################################################################################################\n# Description: Calculation of the CRC checksum over non-user NVM addresses\n# Step 1: Read NVM content (direcly from IP, total 8 words, 16 bits each)\n# Step 2: Calculate CRC checksum\n# Step 3: Write CRC checksum to dark OTP\n######################################################################################################################\ncmt('Version info: $Revision: 2 $ $Author: luz3sgh $ $Date: 2024/05/30 11:39:54 GMT $')\n\n# Read NVM content from IP (only non-user addresses 0x11-0x1f)\nwac('EXT_MODE', 0xc00d) # Enter pmu page\nwac('PMU_TEST_MISC', 0x0004) # Enable NVM and OTP power\ndly(300e-6) \nwac('EXT_MODE', 0xc00f) # Switch to OTPCTRL register page\nwac('NVM_TEST_CTRL', 0x0002) # Enable IP \nfor n in range(0, 8, 1):\n cmt('Set NVM row address to {} and load data'.format(n))\n wac('NVM_DIR_ADDR', n) # Set NVM row address\n rac('NVM_DIR_STATUS', 0x0001, 0x0003) # Check NVM ready/fail flag\n wr('NVM_DIR_CMD', 0x0001) # Trigger NVM load\n rac('NVM_DIR_STATUS', 0x0001, 0x0003) # Check NVM ready/fail flag\n ras('crcdata_{:02d}'.format(n), 'NVM_DIR_DATA') # Read NVM and save data to crcdata_n \n\ncmt('Calculate the CRC-16 CCITT checksum for the 8 data words crcdata_00-07')\ncmt('and store in variable CRC_CALC_NVM')\n\ncalc('CRC_CALC_NVM', 0xabcd) # Assign placeholder value for simulation, REPLACE with calculated CRC_CALC_NVM\nlog('CRC_CALC_NVM')\n\n# Program CRC_CALC_NVM to OTP \nwac('EXT_MODE', 0xc00d) # Switch to PMU register page\nwcb('nvmotp_power_en',0x1) # Request OTP power\ndly(300e-6)\nwac('EXT_MODE', 0xc00f) # Switch to OTPCTRL register page\nwac('OTP_PROG_EN', 0x0002) # Enable OTP program\nwcb('vddp_sw', 0x1) # Connect VDDP to VDD\nsav('VDD', 3.6, v_range=4.0, i_comp=40e-3)\ndly(1e-3)\nwri('OTP_DATA', 'CRC_CALC_NVM') # Write CRC_CALC_NVM to OTP data register\nrac('OTP_STATUS', 0x0001) # Check OTP ready\nwr('OTP_CMD', 0x0005) # Trigger OTP data program\ndly(200e-6) # OTP spec, pgm speed 10us per bit\nwac('OTP_DATA',0xcb) # Set regID for dark OTP \nrac('OTP_STATUS', 0x0001) # Check OTP ready\nwr('OTP_CMD', 0x0006) # Trigger OTP reg_id program\ndly(200e-6) \nrac('OTP_STATUS', 0x0001) # Check OTP ready\nsav('VDD', 1.8, v_range=4.0, i_comp=40e-3)\ndly(1e-3)\nwac('OTP_PROG_EN', 0x0000) # Disable OTP program\nwcb('vddp_sw', 0x0) # Connect VDDP to VDDD_DC\nwac('OTP_DATA', 0x0000) # Reset OTP data register\n# Read data from OTP \nwac('BOOT_RANGE', 0xcbcb) # Set register ID for dark OTP load\nrac('BOOT_STATUS', 0x0001) # Check boot controller ready and error bits\nwr('BOOT_CMD', 0x0001) # Trigger OTP load\ndly(1.2e-3)\nras('CRC_CALC_NVM_RD', 'BOOT_LAST_DATA') # Read and save OTP data\ncmt('This test item is a functional fail if CRC_CALC_NVM_RD != CRC_CALC_NVM')\n# Clean-up \nwac('BOOT_RANGE', 0x0000)\nwac('EXT_MODE', 0xc00d) # Switch to PMU register page\nwcb('nvmotp_power_en',0x0) # Disable OTP power\ndly(100e-6)\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T20_44_CRC_write_NVM_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n INT split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &split_pat_flag);\n vector s_splited_pat_name;\n const int split_count = 4; // Alarm:: split_count need manual confirm.\n s_splited_pat_name.resize(split_count);\n vector i_comment_line[split_count];\n\n ARRAY_I crcdata(8);\n\n// static int crcdata_00[xNSitES];\n// static int crcdata_01[xNSitES];\n// static int crcdata_02[xNSitES];\n// static int crcdata_03[xNSitES];\n// static int crcdata_04[xNSitES];\n// static int crcdata_05[xNSitES];\n// static int crcdata_06[xNSitES];\n// static int crcdata_07[xNSitES];\n static int CRC_CALC_NVM_RD[xNSitES], CRC_CALC_NVM[xNSitES];\n ARRAY_LL CRC_CALC_NVM_rtv(xNSitES);\n const int Wri_Bit_Length = 33;\n const int Wri_Bit_Position = 31;\n // Auto_Code_Variable_define\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n GET_TESTSUITE_NAME(test_name);\n\n// for (int i=0; i<8; i++)\n// {\n// \t crcdata[i].resize(8);\n// }\n if (split_pat_flag)\n {\n \t split_pattern(s_label_name,\"wri\",\"sav\",split_pat_flag,s_splited_pat_name);\n }\n else\n {\n for (int i = 0; i i_comment_line0;\n\n static int crcdata_8bits[xNSitES][16], crcdata_highbyte[xNSitES][8];\n// static int crcdata_8bits_01[xNSitES];\n// static int crcdata_8bits_02[xNSitES];\n// static int crcdata_8bits_03[xNSitES];\n// static int crcdata_8bits_04[xNSitES];\n// static int crcdata_8bits_05[xNSitES];\n// static int crcdata_8bits_06[xNSitES];\n// static int crcdata_8bits_07[xNSitES];\n// static int crcdata_8bits_08[xNSitES];\n// static int crcdata_8bits_09[xNSitES];\n// static int crcdata_8bits_10[xNSitES];\n// static int crcdata_8bits_11[xNSitES];\n// static int crcdata_8bits_12[xNSitES];\n// static int crcdata_8bits_13[xNSitES];\n// static int crcdata_8bits_14[xNSitES];\n// static int crcdata_8bits_15[xNSitES];\n static int CRC_NVM_RD[xNSitES], CRC_CHECK_NVM[xNSitES];\n ARRAY_I crcdata(8);\n // Auto_Code_Variable_define\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T20_45_CRC_check_NVM_V2_PAT_id\");\n rdi.digCap(\"T20_45_CRC_check_NVM_V2_Digcap_id\").label(s_label_name)\n .pin(\"SDO\").capMode(TA::SER).samples(16*17).bitPerWord(16)\n .execute();\n RDI_END();\n\n // Auto_Code_Execution_Part\n\n\n ON_FIRST_INVOCATION_END();\n ARRAY_I Vec=rdi.id(\"T20_45_CRC_check_NVM_V2_Digcap_id\").getVector();\n for (int i=0; i<16; i++)\n {\n \t crcdata_8bits[CURRENT_SITE_NUMBER()-1][i] = reverse_ras_result(Vec[i]);\n \t FuncPrint(\"crcdata_8bits[\"+rdi.itos(i)+\"]\", crcdata_8bits[CURRENT_SITE_NUMBER()-1][i]);\n }\n CRC_NVM_RD[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[16]);\n\n for (int i=0; i<8; i++)\n {\n \t crcdata_highbyte[CURRENT_SITE_NUMBER()-1][i] = crcdata_8bits[CURRENT_SITE_NUMBER()-1][i*2+1] << 8;\n \t crcdata[i] = crcdata_highbyte[CURRENT_SITE_NUMBER()-1][i] | crcdata_8bits[CURRENT_SITE_NUMBER()-1][i*2];\n \t FuncPrint(\"crcdata[\"+rdi.itos(i)+\"]\", crcdata[i]);\n }\n\n CRC_CHECK_NVM[CURRENT_SITE_NUMBER()-1] = CRC_16_CCITT(crcdata, 8);\n FuncPrint(\"CRC_CHECK_NVM\", CRC_CHECK_NVM[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"CRC_NVM_RD\", CRC_NVM_RD[CURRENT_SITE_NUMBER()-1]);\n\n int Func_result = rdi.id(\"T20_45_CRC_check_NVM_V2_PAT_id\").getBurstPassFail();\n\n\n if (CRC_NVM_RD[CURRENT_SITE_NUMBER()-1] != CRC_CHECK_NVM[CURRENT_SITE_NUMBER()-1]) Func_result=99;\n\n FuncPrint(\"Func_result\", Func_result);\n\n// crcdata_00_highbyte[CURRENT_SITE_NUMBER()-1] = crcdata_8bits_00[CURRENT_SITE_NUMBER()-1] << 8;\n// crcdata_00[CURRENT_SITE_NUMBER()-1] = crcdata_00_highbyte[CURRENT_SITE_NUMBER()-1] | crcdata_8bits_01[CURRENT_SITE_NUMBER()-1];\n// crcdata_01_highbyte[CURRENT_SITE_NUMBER()-1] = crcdata_8bits_02[CURRENT_SITE_NUMBER()-1] << 8;\n// crcdata_01[CURRENT_SITE_NUMBER()-1] = crcdata_01_highbyte[CURRENT_SITE_NUMBER()-1] | crcdata_8bits_03[CURRENT_SITE_NUMBER()-1];\n// crcdata_02_highbyte[CURRENT_SITE_NUMBER()-1] = crcdata_8bits_04[CURRENT_SITE_NUMBER()-1] << 8;\n// crcdata_02[CURRENT_SITE_NUMBER()-1] = crcdata_02_highbyte[CURRENT_SITE_NUMBER()-1] | crcdata_8bits_05[CURRENT_SITE_NUMBER()-1];\n// crcdata_03_highbyte[CURRENT_SITE_NUMBER()-1] = crcdata_8bits_06[CURRENT_SITE_NUMBER()-1] << 8;\n// crcdata_03[CURRENT_SITE_NUMBER()-1] = crcdata_03_highbyte[CURRENT_SITE_NUMBER()-1] | crcdata_8bits_07[CURRENT_SITE_NUMBER()-1];\n// crcdata_04_highbyte[CURRENT_SITE_NUMBER()-1] = crcdata_8bits_08[CURRENT_SITE_NUMBER()-1] << 8;\n// crcdata_04[CURRENT_SITE_NUMBER()-1] = crcdata_04_highbyte[CURRENT_SITE_NUMBER()-1] | crcdata_8bits_09[CURRENT_SITE_NUMBER()-1];\n// crcdata_05_highbyte[CURRENT_SITE_NUMBER()-1] = crcdata_8bits_10[CURRENT_SITE_NUMBER()-1] << 8;\n// crcdata_05[CURRENT_SITE_NUMBER()-1] = crcdata_05_highbyte[CURRENT_SITE_NUMBER()-1] | crcdata_8bits_11[CURRENT_SITE_NUMBER()-1];\n// crcdata_06_highbyte[CURRENT_SITE_NUMBER()-1] = crcdata_8bits_12[CURRENT_SITE_NUMBER()-1] << 8;\n// crcdata_06[CURRENT_SITE_NUMBER()-1] = crcdata_06_highbyte[CURRENT_SITE_NUMBER()-1] | crcdata_8bits_13[CURRENT_SITE_NUMBER()-1];\n// crcdata_07_highbyte[CURRENT_SITE_NUMBER()-1] = crcdata_8bits_14[CURRENT_SITE_NUMBER()-1] << 8;\n// crcdata_07[CURRENT_SITE_NUMBER()-1] = crcdata_07_highbyte[CURRENT_SITE_NUMBER()-1] | crcdata_8bits_15[CURRENT_SITE_NUMBER()-1];\n // Auto_Code_Retrieve_Data\n\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n // Auto_Code_Judge_and_log\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T20_45_CRC_check_NVM_V2\", T20_45_CRC_check_NVM_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: Measure the Combo mode current on VDD, VDDIO\n# - The settings of T01_11_set_device_config_STC_COMBO are used unchanged.\n# ACC in HPM; AFS=32g; ODR=1600; BW=200\n# GYR in HPM; GFS=4K; ODR=1600; BW=200\n#############################################################################################################\ncmt('Version info: $Revision: 2 $ $Author: luz3sgh $ $Date: 2024/07/01 02:08:51 GMT $')\ndly(100e-6)\ngac('I_VDD_COMBO', 'VDD', i_range=1e-3, period=2e-3)\nlog('I_VDD_COMBO')\ngac('I_VDDIO_COMBO', 'VDDIO', i_range=10e-6, period=2e-3)\nlog('I_VDDIO_COMBO')\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T32_01_Current_Consumption_Test_Combo_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n static double v_VDDIO, v_VDD;\n// static double I_VDD_COMBO[xNSitES];\n// static double I_VDDIO_COMBO[xNSitES];\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n v_VDDIO = Primary.getLevelSpec().getSpecValue(\"VDDIO\");\n v_VDD = Primary.getLevelSpec().getSpecValue(\"VDD\");\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T32_01_Current_Consumption_Test_Combo_V2_PAT_id\");\n rdi.dc(\"T32_01_Current_Consumption_Test_Combo_V2DC_id0\").label(s_label_name)\n .insertSub(i_comment_line0[0]).pin(\"VDD\").vForce(v_VDD).iMeas().valueMode(TA::BADC).iRange(0.001 A).average(512).measWait(1 ms) //I_VDD_COMBO\n .insertSub(i_comment_line0[1]).pin(\"VDDIO\").vForce(v_VDDIO).iMeas().valueMode(TA::BADC).iRange(1e-05 A).average(512).measWait(1 ms) //I_VDDIO_COMBO\n .insertSub(i_comment_line0[1]).pin(\"VDD\").vForce(v_VDD).iRange(40 mA)\n .insertSub(i_comment_line0[1]).pin(\"VDDIO\").vForce(v_VDDIO).iRange(40 mA)\n .execute();\n RDI_END();\n\n ON_FIRST_INVOCATION_END();\n\t ARRAY_D JSUB_results_VDD;\n\t JSUB_results_VDD = rdi.id(\"T32_01_Current_Consumption_Test_Combo_V2DC_id0\").getMultiValue(\"VDD\");\n\t ARRAY_D JSUB_results_VDDIO;\n\t JSUB_results_VDDIO = rdi.id(\"T32_01_Current_Consumption_Test_Combo_V2DC_id0\").getMultiValue(\"VDDIO\");\n\t I_VDD_COMBO[CURRENT_SITE_NUMBER()-1] = JSUB_results_VDD[0];\n\t I_VDDIO_COMBO[CURRENT_SITE_NUMBER()-1] = JSUB_results_VDDIO[0];\n\n int Func_result = rdi.id(\"T32_01_Current_Consumption_Test_Combo_V2_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n FuncPrint(\"I_VDD_COMBO\", I_VDD_COMBO[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"I_VDDIO_COMBO\", I_VDDIO_COMBO[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"I_VDD_COMBO\", I_VDD_COMBO[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"I_VDDIO_COMBO\", I_VDDIO_COMBO[CURRENT_SITE_NUMBER()-1]);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T32_01_Current_Consumption_Test_Combo_V2\", T32_01_Current_Consumption_Test_Combo_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: Measure the ACC mode current on VDD, VDDIO\n# - The settings of T01_10_set_device_config_STC_ACC are changed in one parameter: AFS=8g\n# ACC in HPM; AFS=8g; ODR=1600; BW=200\n#############################################################################################################\ncmt('Version info: $Revision: 3 $ $Author: luz3sgh $ $Date: 2024/04/23 11:12:14 GMT $')\nwac('EXT_MODE', 0xc000) # Switch to USR register page\nwac('ACC_CONF', 0xe22c) # e24c->e22c, acc_range=g32 to g8\nwac('EXT_MODE', 0xc006) # Fcu page.\nwac('FCU_TEST_CONF', 0x8000) # temp_test_force_dis set to 1, temp off\ndly(3e-3) # make sure that TEMP is switched off\ngac('I_VDD_ACC_NOTEMP', 'VDD', i_range = 300e-6 )\nlog('I_VDD_ACC_NOTEMP')\ngac('I_VDDIO_ACC_NOTEMP', 'VDDIO', i_range = 10e-6 )\nlog('I_VDDIO_ACC_NOTEMP')\nwac('FCU_TEST_CONF', 0x0000) # reset value\nwac('EXT_MODE', 0xc000) # Switch to USR register page\nwac('ACC_CONF', 0xe24c) # back to stc_acc, acc_range=g32\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T32_02_Current_Consumption_Test_Accel_Without_Temp_V3: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n static double I_VDD_ACC_NOTEMP[xNSitES];\n static double I_VDDIO_ACC_NOTEMP[xNSitES];\n // Auto_Code_Variable_define\n static double v_VDDIO, v_VDD;\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n\n rdi.enableOre(oreFlag);\n rdi.oreFile(\"./ORE_Files/rdi_ore_T32_02_CURRENT_CONSUMPTION_TEST_ACCEL_WITHOUT_TEMP_ASIC_ONLY.xml\");\n\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n v_VDDIO = Primary.getLevelSpec().getSpecValue(\"VDDIO\");\n v_VDD = Primary.getLevelSpec().getSpecValue(\"VDD\");\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T32_02_Current_Consumption_Test_Accel_Without_Temp_V3_PAT_id\");\n rdi.dc(\"T32_02_Current_Consumption_Test_Accel_Without_Temp_V3DC_id0\").label(s_label_name)\n .insertSub(i_comment_line0[0]).pin(\"VDD\").vForce(v_VDD V).iMeas().valueMode(TA::BADC).iRange(1 mA).average(256).measWait(10 ms) //I_VDD_ACC_NOTEMP\n .insertSub(i_comment_line0[1]).pin(\"VDDIO\").vForce(v_VDDIO V).iMeas().valueMode(TA::BADC).iRange(1e-05 A).average(256).measWait(2 ms) //I_VDDIO_ACC_NOTEMP\n .insertSub(i_comment_line0[1]).pin(\"VDDIO\").vForce(v_VDDIO V).iRange(40 mA)\n .insertSub(i_comment_line0[1]).pin(\"VDD\").vForce(v_VDD V).iRange(40 mA)\n .execute();\n RDI_END();\n\n // Auto_Code_Execution_Part\n\n\n\n ON_FIRST_INVOCATION_END();\n ARRAY_D JSUB_results_VDDIO;\n JSUB_results_VDDIO = rdi.id(\"T32_02_Current_Consumption_Test_Accel_Without_Temp_V3DC_id0\").getMultiValue(\"VDDIO\");\n ARRAY_D JSUB_results_VDD;\n JSUB_results_VDD = rdi.id(\"T32_02_Current_Consumption_Test_Accel_Without_Temp_V3DC_id0\").getMultiValue(\"VDD\");\n I_VDD_ACC_NOTEMP[CURRENT_SITE_NUMBER()-1] = JSUB_results_VDD[0];\n I_VDDIO_ACC_NOTEMP[CURRENT_SITE_NUMBER()-1] = JSUB_results_VDDIO[0];\n FuncPrint(\"I_VDD_ACC_NOTEMP\", I_VDD_ACC_NOTEMP[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"I_VDDIO_ACC_NOTEMP\", I_VDDIO_ACC_NOTEMP[CURRENT_SITE_NUMBER()-1]);\n\n // Auto_Code_Retrieve_Data\n \n int Func_result = rdi.id(\"T32_02_Current_Consumption_Test_Accel_Without_Temp_V3_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"I_VDD_ACC_NOTEMP\", I_VDD_ACC_NOTEMP[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"I_VDDIO_ACC_NOTEMP\", I_VDDIO_ACC_NOTEMP[CURRENT_SITE_NUMBER()-1]);\n // Auto_Code_Judge_and_log\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T32_02_Current_Consumption_Test_Accel_Without_Temp_V3\", T32_02_Current_Consumption_Test_Accel_Without_Temp_V3);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: Measure the Combo mode current on VDD, VDDIO\n# Entry condision : STC_COMBO\n# Exit condigison : STC_COMBO\n#- The settings of T01_11_set_device_config_STC_COMBO are used unchanged.\n# ACC in HPM; AFS=32g; ODR=1600; BW=200\n# GYR in HPM; GFS=4K; ODR=1600; BW=200\n# Use I_VDD_COMBO, I_VDDIO_COMBO measured from T_32_01_Current_Consumption_Test_Combo\n#############################################################################################################\ncmt('Version info: $Revision: 2 $ $Author: luz3sgh $ $Date: 2024/07/01 02:46:38 GMT $')\nwac('EXT_MODE',0xc00e) # ACC_AFE page\nwac('ACC_AFE_AASR_CONF',0x000B)\ndly(100e-6)\ngac('I_VDD_COMBO_AASR', 'VDD', i_range=1e-3, period=2e-3)\ncalc('I_VDD_AASR','I_VDD_COMBO_AASR','-','I_VDD_COMBO')\nlog('I_VDD_AASR')\ngac('I_VDDIO_COMBO_AASR', 'VDDIO', i_range=10e-6, period=2e-3)\ncalc('I_VDDIO_AASR','I_VDDIO_COMBO_AASR','-','I_VDDIO_COMBO')\nlog('I_VDDIO_AASR')\nwac('ACC_AFE_AASR_CONF',0x0000)\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T32_03_Current_Consumption_Test_AASR_V2: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n vector i_comment_line0;\n\n static double I_VDD_COMBO_AASR[xNSitES], I_VDD_AASR[xNSitES];\n static double I_VDDIO_COMBO_AASR[xNSitES], I_VDDIO_AASR[xNSitES];\n static double v_VDDIO, v_VDD;\n // Auto_Code_Variable_define\n \n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n i_comment_line0 = search_comment_line(s_label_name);\n print_key_comment(s_label_name, i_comment_line0, printFlag);\n\n v_VDDIO = Primary.getLevelSpec().getSpecValue(\"VDDIO\");\n v_VDD = Primary.getLevelSpec().getSpecValue(\"VDD\");\n\n RDI_BEGIN(mode);\n rdi.burstId(\"T32_03_Current_Consumption_Test_AASR_V2_PAT_id\");\n rdi.dc(\"T32_03_Current_Consumption_Test_AASR_V2DC_id0\").label(s_label_name)\n .insertSub(i_comment_line0[0]).pin(\"VDD\").vForce(v_VDD).iMeas().valueMode(TA::BADC).iRange(0.001 A).average(512).measWait(0.1 ms) //I_VDD_COMBO_AASR\n .insertSub(i_comment_line0[1]).pin(\"VDDIO\").vForce(v_VDDIO).iMeas().valueMode(TA::BADC).iRange(1e-05 A).average(512).measWait(1 ms) //I_VDDIO_COMBO_AASR\n .insertSub(i_comment_line0[1]).pin(\"VDD\").vForce(v_VDD).iRange(40 mA)\n .insertSub(i_comment_line0[1]).pin(\"VDDIO\").vForce(v_VDDIO).iRange(40 mA)\n .execute();\n RDI_END();\n\n ON_FIRST_INVOCATION_END();\n\n\t\tARRAY_D JSUB_results_VDD;\n\t\tJSUB_results_VDD = rdi.id(\"T32_03_Current_Consumption_Test_AASR_V2DC_id0\").getMultiValue(\"VDD\");\n\t\tARRAY_D JSUB_results_VDDIO;\n\t\tJSUB_results_VDDIO = rdi.id(\"T32_03_Current_Consumption_Test_AASR_V2DC_id0\").getMultiValue(\"VDDIO\");\n\t\tI_VDD_COMBO_AASR[CURRENT_SITE_NUMBER()-1] = JSUB_results_VDD[0];\n\t\tI_VDDIO_COMBO_AASR[CURRENT_SITE_NUMBER()-1] = JSUB_results_VDDIO[0];\n\n\t\tI_VDD_AASR[CURRENT_SITE_NUMBER()-1] = I_VDD_COMBO_AASR[CURRENT_SITE_NUMBER()-1] - I_VDD_COMBO[CURRENT_SITE_NUMBER()-1];\n\t\tI_VDDIO_AASR[CURRENT_SITE_NUMBER()-1] = I_VDDIO_COMBO_AASR[CURRENT_SITE_NUMBER()-1] - I_VDDIO_COMBO[CURRENT_SITE_NUMBER()-1];\n\n int Func_result = rdi.id(\"T32_03_Current_Consumption_Test_AASR_V2_PAT_id\").getBurstPassFail();\n FuncPrint(\"Func_result\", Func_result);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n TestLog(\"I_VDD_AASR\", I_VDD_AASR[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"I_VDDIO_AASR\", I_VDDIO_AASR[CURRENT_SITE_NUMBER()-1]);\n\n FuncPrint(\"I_VDD_COMBO_AASR\", I_VDD_COMBO_AASR[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"I_VDDIO_COMBO_AASR\", I_VDDIO_COMBO_AASR[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"I_VDD_COMBO\", I_VDD_COMBO[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"I_VDDIO_COMBO\", I_VDDIO_COMBO[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"I_VDD_AASR\", I_VDD_AASR[CURRENT_SITE_NUMBER()-1]);\n FuncPrint(\"I_VDDIO_AASR\", I_VDDIO_AASR[CURRENT_SITE_NUMBER()-1]);\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T32_03_Current_Consumption_Test_AASR_V2\", T32_03_Current_Consumption_Test_AASR_V2);\n" }, { "instruction": "generate cpp file from given test case python file", "input": "#############################################################################################################\n# description: Set WLT logbit\n# - Dark OTP, regid 0xCE bit 8 used to store WLT test status infomation\n# - Bit8 set to 1 for dies that pass all items before T33_01\n# - Bit8 set to 0 for dies that fail any item before T33_01\n#############################################################################################################\ncmt('Version info: $Revision: 1 $ $Author: hmf1rt $ $Date: 2024/03/13 13:36:52 GMT $')\n# Assign pass/fail bit varable\ncmt('0x1 is a placehlder for simulation. Replace 0x1 with following assignments according to the test flow status:')\ncmt('WLT_STATUS = 0x1 for BIN == 1 parts')\ncmt('WLT_STATUS = 0x0 for BIN != 1 parts')\ncalc('WLT_STATUS', 0x1) # Set WLT_STATUS to 0 or 1 according BIN status\n# Program data to OTP\nwac('EXT_MODE', 0xc00d) # Switch to PMU register page\nwcb('nvmotp_power_en',0x1) # Request OTP power\ndly(300e-6) \nwac('EXT_MODE', 0xc00f) # Switch to OTPCTRL register page\nwac('OTP_PROG_EN', 0x0002) # Enable OTP program\nwcb('vddp_sw', 0x1) # Connect VDDP to VDD\nsav('VDD', 3.6, v_range=4.0, i_comp=40e-3)\ndly(1e-3)\ncalc('WLT_STATUS_8', 'WLT_STATUS', '<<', 8) # Shift WLT status to bit8\nwri('OTP_DATA', 'WLT_STATUS_8') # Write WLT status to OTP data register\nrac('OTP_STATUS', 0x0001) # Check OTP ready\nwr('OTP_CMD', 0x0005) # Trigger OTP data program\ndly(200e-6) # otp spec, pgm speed 10us per bit\nwac('OTP_DATA',0xce) # regid for FT status, dark OTP \nrac('OTP_STATUS', 0x0001) # Check OTP ready\nwr('OTP_CMD', 0x0006) # Trigger OTP reg_id program\ndly(200e-6) \nrac('OTP_STATUS', 0x0001) # Check OTP ready\nsav('VDD', 1.8, v_range=4.0, i_comp=40e-3)\ndly(1e-3)\nwac('OTP_PROG_EN', 0x0000) # Disable OTP program\nwcb('vddp_sw', 0x0) # Connect VDDP to VDDD_DC\nwac('OTP_DATA', 0x0000) # Reset OTP data register\n# Read data from OTP \nwac('BOOT_RANGE', 0xcece) # Set register ID for dark OTP load\nrac('BOOT_STATUS', 0x0001) # Check boot controller ready and error bits\nwr('BOOT_CMD', 0x0001) # Trigger OTP load\ndly(1.2e-3)\nras('WLT_STATUS_8_RD', 'BOOT_LAST_DATA') # Read and save WLT status after OTP load\ncmt('This test item is a functional fail if WLT_STATUS_8_RD != WLT_STATUS_8')\n# Clean-up \nwac('BOOT_RANGE', 0x0000)\nwac('EXT_MODE', 0xc00d) # Switch to PMU register page\nwcb('nvmotp_power_en',0x0) # Disable OTP power\ndly(100e-6)\n", "output": "/*****************************************************\n * Description\n * 1. \n * 2. \n\n * Change History\n * First Editor: GON3SGH\n * \n\n *****************************************************/\n#include \"testmethod.hpp\"\n#include \"mapi.hpp\" \n#include \"../Common.hpp\" \nusing namespace std;\n\nclass T33_01_Set_Asic_WLT_Logbit_V1: public testmethod::TestMethod {\n\nprotected:\n\n virtual void initialize()\n {\n\n }\n\n virtual void run()\n {\n static STRING test_name;\n const string s_label_name = Primary.getLabel();\n INT split_pat_flag;\n GET_USER_FLAG(\"split_pat_flag\", &split_pat_flag);\n vector s_splited_pat_name;\n const int split_count = 4; // Alarm:: split_count need manual confirm.\n s_splited_pat_name.resize(split_count);\n vector i_comment_line[split_count];\n\n static int WLT_STATUS_8_RD[xNSitES],WLT_STATUS[xNSitES],WLT_STATUS_8[xNSitES];\n ARRAY_LL WLT_STATUS_8_rtv(xNSitES);\n string softbin = \"\";\n int hardbin = -1;\n // Auto_Code_Variable_define\n \n const int Wri_Bit_Length = 33;\n const int Wri_Bit_Position = 31;\n\n RDI_INIT();\n\n ON_FIRST_INVOCATION_BEGIN();\n GET_TESTSUITE_NAME(test_name);\n if (split_pat_flag)\n {\n \t split_pattern(s_label_name,\"wri\",\"sav\",split_pat_flag,s_splited_pat_name);\n }\n else\n {\n for (int i = 0; i0 && hardbin>0)\n\t\t\t\t { // fail\n\t\t\t\t\t WLT_STATUS[CURRENT_SITE_NUMBER()-1] = 0;\n\t\t\t\t }\n\t\t\t\t else\n\t\t\t\t {\n\t\t\t\t\t WLT_STATUS[CURRENT_SITE_NUMBER()-1] = 1;\n\t\t\t\t }\n\t\t\t\t WLT_STATUS_8[CURRENT_SITE_NUMBER()-1] = WLT_STATUS[CURRENT_SITE_NUMBER()-1] << 8;\n\t\t\t\t WLT_STATUS_8_rtv[CURRENT_SITE_NUMBER()-1] = extend_Pmode_Herschel(WLT_STATUS_8[CURRENT_SITE_NUMBER()-1], 2);\n\n\t\t\t\t FuncPrint(\"softbin\", softbin);\n\t\t\t\t FuncPrint(\"hardbin\", hardbin);\n\t\t\t\t FuncPrint(\"WLT_STATUS\", WLT_STATUS[CURRENT_SITE_NUMBER()-1]);\n\t\t\t\t FuncPrint(\"WLT_STATUS_8\", WLT_STATUS_8[CURRENT_SITE_NUMBER()-1]);\n\t\t\t\t FuncPrint(\"WLT_STATUS_8_rtv\", WLT_STATUS_8_rtv[CURRENT_SITE_NUMBER()-1]);\n FOR_EACH_SITE_END();\n\n rdi.runTimeVal(\"WLT_STATUS_8_rtv\", WLT_STATUS_8_rtv);\n\n\t\t\t RDI_BEGIN(mode);\n\t\t\t\t rdi.burstId(\"T33_01_Set_Asic_WLT_Logbit_V1_PAT_id0\");\n\t\t\t\t rdi.digCap(\"T33_01_Set_Asic_WLT_Logbit_V1_Digcap_id1\").vecVarOnly().pin(\"SDO\").capMode(TA::SER).samples(16*1).bitPerWord(16).execute();\n\t\t\t\t rdi.func().label(s_splited_pat_name[0]).execute();\n\t\t\t\t rdi.dc().pin(\"VDD\").vForce(3.6).iRange(40 mA).execute();\n\t\t\t\t rdi.func().label(s_splited_pat_name[1]).execute();\n\t\t\t\t rdi.smartVec().label(s_splited_pat_name[2]).pin(\"SDX\").writeData(\"WLT_STATUS_8_rtv\", Wri_Bit_Length, Wri_Bit_Position).execute();\n\t\t\t\t rdi.dc().pin(\"VDD\").vForce(1.8).iRange(40 mA).execute();\n\t\t\t\t rdi.func().label(s_splited_pat_name[3]).execute();\n\t\t\t RDI_END();\n }\n\n ON_FIRST_INVOCATION_END();\n // Auto_Code_Retrieve_Data\n \n int Func_result0 = rdi.id(\"T33_01_Set_Asic_WLT_Logbit_V1_PAT_id0\").getBurstPassFail();\n// int Func_result1 = rdi.id(\"T33_01_Set_Asic_WLT_Logbit_V1_PAT_id1\").getBurstPassFail();\n// int Func_result2 = rdi.id(\"T33_01_Set_Asic_WLT_Logbit_V1_PAT_id2\").getBurstPassFail();\n FuncPrint(\"Func_result0\", Func_result0);\n// FuncPrint(\"Func_result1\", Func_result1);\n// FuncPrint(\"Func_result2\", Func_result2);\n int Func_result = 1 * Func_result0 ;//* Func_result1 * Func_result2;\n\n ARRAY_I Vec=rdi.id(\"T33_01_Set_Asic_WLT_Logbit_V1_Digcap_id1\").getVector();\n WLT_STATUS_8_RD[CURRENT_SITE_NUMBER()-1] = reverse_ras_result(Vec[0]);\n\n if (WLT_STATUS_8_RD[CURRENT_SITE_NUMBER()-1] != WLT_STATUS_8[CURRENT_SITE_NUMBER()-1]) Func_result=99;\n FuncPrint(\"WLT_STATUS_8_RD\", WLT_STATUS_8_RD[CURRENT_SITE_NUMBER()-1]);\n TestLog(\"FUNCTIONAL_TEST\", Func_result);\n\n // Auto_Code_Judge_and_log\n\n return;\n }\n\n virtual void postParameterChange(const string& parameterIdentifier)\n {\n\n return;\n }\n\n virtual const string getComment() const \n {\n string comment = \"_\";\n return comment;\n }\n};\nREGISTER_TESTMETHOD(\"02_Wafer.T33_01_Set_Asic_WLT_Logbit_V1\", T33_01_Set_Asic_WLT_Logbit_V1);\n" } ]