Initial

README.md

@@ -51,10 +51,11 @@ VEGA_AE
 
 ## 4. Fine-Tuning
 
-Run fine-tuning with:
+**Run fine-tuning with:**
 ```
 $ bash run_fine_tuning.sh
 ```
+
 Customize parameters for fine-tuning by modifying following options in the ```run_fine_tuning.sh```.
 ```
   --model_name_or_path ../../saved_models/UnixCoder \
@@ -75,11 +76,11 @@ The fine-tuned model will be saved in ```--output_dir```.
 
 We have provided a fine-tuned model in ```./saved_models/Fine_Tuned_Model```.
 
-We have also provided a script fot function test, which only generates a single function for RI5CY, taking less than 3 minutes with 8 V100 GPU.
+We have also provided a script fot functionality test, which only generates a single function for RI5CY, taking less than 3 minutes with 8 V100 GPU.
 
 
 
-Run function test with:
+**Run functionality test with:**
 
 ```
 $ bash run_function_test.sh
@@ -96,7 +97,7 @@ $ " Finished Function Inferencing : xxx secs"
 
 The inference result will be saved in ```--output_dir/result.jsonl```.
 
-Run code generation with:
+**Run code generation with:**
 
 ```
 $ bash run_test.sh
@@ -145,9 +146,9 @@ We provide the scripts to reproduce each Figure/Table from the paper, along with
 | ./Scripts/Exp/Accuracy/calculate_purple.py 	| Calculate the the percentage of functions accurately synthesized from the statements of various existing targets (Purple Bar in Fig.8). 	| ./Scripts/Exp/Accuracy/fig8_purple.csv          	| Fig.8        	|
 | ./Scripts/Exp/Accuracy/calculate_accuracy.py 	| Calculate the percentage of three types of error.                                                                                       	| ./Scripts/Exp/Accuracy/err_percentage.csv            	| Table.2      	|
 | ./Scripts/Exp/ForkFlow/calculate_forkflow.py 	| Calculate the statement-level accracy of VEGA and ForkFlow.                                                                             	| ./Scripts/Exp/ForkFlow/forkflow_result.csv           	| Fig.9        	|
-| ./Scripts/Exp/ForkFlow/calculate_forkflow.py 	| Calculate the number of accurate statements of VEGA and ForkFlow.                                                                       	| ./Scripts/Exp/ForkFlow/mod_lines.csv 	                | Table.3      	|
-| -                                            	| Recorded time required by Developer A and B to modify the VEGA-generated RISC-V backend.                                                	| ./Scripts/Exp/Correction/Correction_Time.xlsx        	| Table. 4     	|
-| -                                            	| Recorded time required for LLVM-Base (-O0), LLVM-Base (-O3), and LLVM-VEGA (-O3) to pass benchmarks.                                    	| ./Scripts/Exp/Performance/BenchMark.xlsx             	| Fig. 10      	|
+| ./Scripts/Exp/ForkFlow/calculate_forkflow.py 	| Calculate the number of accurate statements of VEGA.                                                                       	| ./Scripts/Exp/ForkFlow/mod_lines.csv 	                | Table.3      	|
+| ./Scripts/Exp/Correction/calculate_correction.py | Calculate time required by two developers to modify the VEGA-generated RISC-V backend.                                                	| ./Scripts/Exp/Correction/Correction.csv        	| Table. 4     	|
+| ./Scripts/Exp/Performance/calculate_perf.py  	| Calculate the speedup of LLVM-Base (-O3),and LLVM-VEGA (-O3) over LLVM-Base (-O0).                                    	| ./Scripts/Exp/Performance/Perf.csv             	| Fig. 10      	|
 ### 6.1 Results for Fig. 7 in Sec. 4.2
 
 In the code generation process, we set a batch size of 256 on 8 Nvidia Tesla V100 GPU (each with 16GB memory), meaning each batch contains 256 statements. Since each batch may include statements from different function modules, we did not directly measure the generation time for each function modules of three targets (RISC-V, RI5CY, xCORE) during execution. Instead, we calculated the average inference time of each batch (25 seconds) and then derived the inference time of each statement (25/256 seconds). With the total number of statements within each function module of each target, we subsequently calculated the total inference time required for each function module of each target.
@@ -296,23 +297,34 @@ $ cat ./Scripts/Exp/ForkFlow/mod_lines.csv
 
 ### 6.6 Results for Table. 4 in Sec. 4.2
 
-The data in Table. 4 record the time required by two developers to modify the VEGA-generated RISC-V backend. As this is a human-based experiment, we can only provide the recorded time for modifying each function within the VEGA-generated RISC-V backend.
+The data in Table. 4 show the time two developers needed to modify the VEGA-generated RISC-V backend. As a human-based experiment, only the recorded modification times for each function are record.
 
-- Results:
+By executing the following script, the time for Developer A and B to modify each function module in the VEGA-generated RISC-V backend will be automatically calculated:
+
+- Command:
+  
 ```
-./Scripts/Exp/Correction/Correction_Time.xlsx
+$ python ./Scripts/Exp/Correction/calculate_correction.py
 ```
 
-This file contains two sheets, each corresponding to the time required by Developer A and Developer B to modify the VEGA-generated RISC-V backend. Each sheet includes four columns: the first three indicate the function module, file, and function name of each function in the VEGA-generated RISC-V backend, while the final column specifies the time spent modifying each function, measured in seconds. By summing the data in each sheet according to function modules, we calculated the total time (in hours) that Developer A and Developer B spent on each module.
+- Results:
+```
+$ cat ./Scripts/Exp/Correction/Correction.csv
+```
 
 ### 6.7 Results for Fig. 10 in Sec. 4.3
 
-Due to restrictions associated with the commercial license, we are unable to provide the source code of the SPEC 2017 CPU benchmark directly used in this experiment. Furthermore, the testing duration for SPEC 2017 CPU is highly time-consuming, requiring approximately 565 hours. To address these constraints, we provide our recorded experimental data, which can be accessed at:
+Due to commercial licensing restrictions, we cannot provide the source code for the SPEC 2017 CPU benchmark used in this experiment. Additionally, testing all benchmarks including SPEC 2017 CPU is time-intensive, requiring around 565 hours in total. To address these constraints, we provide our recorded experimental data.
 
+By executing the following script, the speedup for VEGA-generated LLVM backend (LLVM-VEGA) and the offical LLVM backend (LLVM-Base) will be automatically calculated repectively:
 
-- Results:
+
+- Command:
 ```
-./Scripts/Exp/Performance/BenchMark.xlsx
+$ python ./Scripts/Exp/Performance/calculate_perf.py
 ```
 
-Each sheet in this recorded data is named with the experimental target and benchmark tested, e.g., "RISCV (SPEC 2017CPU)". We recorded the time required for LLVM-Base (-O0), LLVM-Base (-O3), and LLVM-VEGA (-O3) to successfully pass each test case, and  calculated the corresponding speedup ratios respectively.
+- Results:
+```
+$ cat ./Scripts/Exp/Performance/Perf.csv
+```

Scripts/Exp/Correction/Dev_A.csv

@@ -0,0 +1,569 @@
+Module,File,Func,Time (Secs)
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+Scheduling,InstrInfo,verifyInstruction,44
+Scheduling,MachineFunctionInfo,getLibCallStackSize,10
+Scheduling,MachineFunctionInfo,getMoveF64FrameIndex,19
+Scheduling,MachineFunctionInfo,getVarArgsFrameIndex,14
+Scheduling,MachineFunctionInfo,getVarArgsSaveSize,6
+Scheduling,MachineFunctionInfo,MachineFunctionInfo,6
+Scheduling,MachineFunctionInfo,setLibCallStackSize,12
+Scheduling,MachineFunctionInfo,setVarArgsFrameIndex,10
+Scheduling,MachineFunctionInfo,setVarArgsSaveSize,7
+Scheduling,MachineFunctionInfo,useSaveRestoreLibCalls,691
+Scheduling,Subtarget,anchor,2
+Scheduling,Subtarget,enableLinkerRelax,8
+Scheduling,Subtarget,enableMachineScheduler,3
+Scheduling,Subtarget,enableRVCHintInstrs,10
+Scheduling,Subtarget,enableSaveRestore,6
+Scheduling,Subtarget,getCallLowering,9
+Scheduling,Subtarget,getFrameLowering,6
+Scheduling,Subtarget,getInstrInfo,7
+Scheduling,Subtarget,getInstructionSelector,15
+Scheduling,Subtarget,getLegalizerInfo,12
+Scheduling,Subtarget,getRegBankInfo,9
+Scheduling,Subtarget,getRegisterInfo,7
+Scheduling,Subtarget,getSelectionDAGInfo,10
+Scheduling,Subtarget,getTargetABI,9
+Scheduling,Subtarget,getTargetLowering,9
+Scheduling,Subtarget,getXLen,6
+Scheduling,Subtarget,getXLenVT,12
+Scheduling,Subtarget,hasStdExtA,6
+Scheduling,Subtarget,hasStdExtB,1
+Scheduling,Subtarget,hasStdExtC,2
+Scheduling,Subtarget,hasStdExtD,4
+Scheduling,Subtarget,hasStdExtF,3
+Scheduling,Subtarget,hasStdExtM,2
+Scheduling,Subtarget,hasStdExtV,5
+Scheduling,Subtarget,hasStdExtZba,2
+Scheduling,Subtarget,hasStdExtZbb,2
+Scheduling,Subtarget,hasStdExtZbc,2
+Scheduling,Subtarget,hasStdExtZbe,2
+Scheduling,Subtarget,hasStdExtZbf,3
+Scheduling,Subtarget,hasStdExtZbm,2
+Scheduling,Subtarget,hasStdExtZbp,3
+Scheduling,Subtarget,hasStdExtZbproposedc,1
+Scheduling,Subtarget,hasStdExtZbr,1
+Scheduling,Subtarget,hasStdExtZbs,2
+Scheduling,Subtarget,hasStdExtZbt,2
+Scheduling,Subtarget,hasStdExtZfh,2
+Scheduling,Subtarget,hasStdExtZvamo,2
+Scheduling,Subtarget,hasStdExtZvlsseg,3
+Scheduling,Subtarget,initializeSubtargetDependencies,302
+Scheduling,Subtarget,is64Bit,14
+Scheduling,Subtarget,isRegisterReservedByUser,29
+Scheduling,Subtarget,isRV32E,9
+Scheduling,Subtarget,Subtarget,150
+Scheduling,TargetInfo,getThe32Target,18
+Scheduling,TargetInfo,getThe64Target,3
+Scheduling,TargetInfo,LLVMInitializeTargetInfo,11
+Scheduling,TargetMachine,addGlobalInstructionSelect,6
+Scheduling,TargetMachine,addInstSelector,104
+Scheduling,TargetMachine,addIRPasses,14
+Scheduling,TargetMachine,addIRTranslator,19
+Scheduling,TargetMachine,addLegalizeMachineIR,10
+Scheduling,TargetMachine,addPreEmitPass,21
+Scheduling,TargetMachine,addPreEmitPass2,84
+Scheduling,TargetMachine,addPreRegAlloc,150
+Scheduling,TargetMachine,addPreSched2,2
+Scheduling,TargetMachine,addRegBankSelect,18
+Scheduling,TargetMachine,computeDataLayout,45
+Scheduling,TargetMachine,createPassConfig,8
+Scheduling,TargetMachine,getEffectiveRelocModel,6
+Scheduling,TargetMachine,getObjFileLowering,34
+Scheduling,TargetMachine,getSubtargetImpl,99
+Scheduling,TargetMachine,getTargetMachine,27
+Scheduling,TargetMachine,getTargetTransformInfo,20
+Scheduling,TargetMachine,isNoopAddrSpaceCast,77
+Scheduling,TargetMachine,LLVMInitializeTarget,21
+Scheduling,TargetMachine,PassConfig,30
+Scheduling,TargetMachine,TargetMachine,128
+Scheduling,TargetObjectFIle,getModuleMetadata,1158
+Scheduling,TargetObjectFIle,getSectionForConstant,68
+Scheduling,TargetObjectFIle,Initialize,64
+Scheduling,TargetObjectFIle,isConstantInSmallSection,54
+Scheduling,TargetObjectFIle,isGlobalInSmallSection,988
+Scheduling,TargetObjectFIle,isInSmallSection,8
+Scheduling,TargetObjectFIle,SelectSectionForGlobal,45
+Scheduling,TargetTransformInfo,getIntImmCost,255
+Scheduling,TargetTransformInfo,getIntImmCostInst,738
+Scheduling,TargetTransformInfo,getIntImmCostIntrin,51
+Scheduling,TargetTransformInfo,getST,5
+Scheduling,TargetTransformInfo,getTLI,3
+Scheduling,TargetTransformInfo,TTIImpl,46
+Selection,CallLowering,CallLowering,10
+Selection,CallLowering,lowerCall,2
+Selection,CallLowering,lowerFormalArguments,3
+Selection,CallLowering,lowerReturn,135
+Selection,FrameLowering,adjustReg,222
+Selection,FrameLowering,canUseAsEpilogue,461
+Selection,FrameLowering,canUseAsPrologue,232
+Selection,FrameLowering,determineCalleeSaves,808
+Selection,FrameLowering,eliminateCallFramePseudoInstr,41
+Selection,FrameLowering,emitEpilogue,1005
+Selection,FrameLowering,emitPrologue,3037
+Selection,FrameLowering,FrameLowering,29
+Selection,FrameLowering,getFrameIndexReference,1249
+Selection,FrameLowering,hasBP,25
+Selection,FrameLowering,hasFP,63
+Selection,FrameLowering,hasReservedCallFrame,12
+Selection,FrameLowering,processFunctionBeforeFrameFinalized,81
+Selection,FrameLowering,restoreCalleeSavedRegisters,592
+Selection,FrameLowering,spillCalleeSavedRegisters,534
+Selection,InstructionSelector,createInstructionSelector,13
+Selection,InstructionSelector,getName,5
+Selection,InstructionSelector,InstructionSelector,53
+Selection,InstructionSelector,select,31
+Selection,ISelDAGToDAG,createISelDag,8
+Selection,ISelDAGToDAG,DAGToDAGISel,11
+Selection,ISelDAGToDAG,getPassName,1
+Selection,ISelDAGToDAG,MatchSLLIUW,243
+Selection,ISelDAGToDAG,MatchSRLIUW,311
+Selection,ISelDAGToDAG,PostprocessISelDAG,130
+Selection,ISelDAGToDAG,runOnMachineFunction,4
+Selection,ISelDAGToDAG,Select,28532
+Selection,ISelDAGToDAG,SelectAddrFI,8
+Selection,ISelDAGToDAG,SelectInlineAsmMemoryOperand,205
+Selection,ISelDAGToDAG,selectVLOp,164
+Selection,ISelDAGToDAG,selectVSplat,247
+Selection,ISelDAGToDAG,selectVSplatSimm5,1070
+Selection,ISelDAGToDAG,selectVSplatUimm5,385
+Selection,ISelLowering,analyzeInputArgs,322
+Selection,ISelLowering,analyzeOutputArgs,279
+Selection,ISelLowering,CanLowerReturn,460
+Selection,ISelLowering,computeKnownBitsForTargetNode,384
+Selection,ISelLowering,ComputeNumSignBitsForTargetNode,226
+Selection,ISelLowering,convertSelectOfConstantsToMath,25
+Selection,ISelLowering,convertSetCCLogicToBitwiseLogic,9
+Selection,ISelLowering,decomposeMulByConstant,569
+Selection,ISelLowering,EmitInstrWithCustomInserter,382
+Selection,ISelLowering,emitLeadingFence,225
+Selection,ISelLowering,emitMaskedAtomicCmpXchgIntrinsic,273
+Selection,ISelLowering,emitMaskedAtomicRMWIntrinsic,139
+Selection,ISelLowering,emitTrailingFence,184
+Selection,ISelLowering,getAddr,368
+Selection,ISelLowering,getConstraintType,102
+Selection,ISelLowering,getDynamicTLSAddr,213
+Selection,ISelLowering,getExceptionPointerRegister,4
+Selection,ISelLowering,getExceptionSelectorRegister,9
+Selection,ISelLowering,getExtendForAtomicCmpSwapArg,7
+Selection,ISelLowering,getExtendForAtomicOps,5
+Selection,ISelLowering,getInlineAsmMemConstraint,87
+Selection,ISelLowering,getRegForInlineAsmConstraint,1204
+Selection,ISelLowering,getRegisterByName,228
+Selection,ISelLowering,getSetCCResultType,97
+Selection,ISelLowering,getStaticTLSAddr,527
+Selection,ISelLowering,getSubtarget,7
+Selection,ISelLowering,getTargetNodeName,610
+Selection,ISelLowering,getTgtMemIntrinsic,409
+Selection,ISelLowering,hasBitPreservingFPLogic,12
+Selection,ISelLowering,isCheapToSpeculateCtlz,4
+Selection,ISelLowering,isCheapToSpeculateCttz,7
+Selection,ISelLowering,isDesirableToCommuteWithShift,1301
+Selection,ISelLowering,isEligibleForTailCallOptimization,692
+Selection,ISelLowering,isFMAFasterThanFMulAndFAdd,16
+Selection,ISelLowering,isFPImmLegal,33
+Selection,ISelLowering,isLegalAddImmediate,7
+Selection,ISelLowering,isLegalAddressingMode,124
+Selection,ISelLowering,isLegalICmpImmediate,2
+Selection,ISelLowering,isSExtCheaperThanZExt,83
+Selection,ISelLowering,isTruncateFree,105
+Selection,ISelLowering,isTruncateFree2,45
+Selection,ISelLowering,isZExtFree,137
+Selection,ISelLowering,LowerAsmOperandForConstraint,268
+Selection,ISelLowering,LowerBlockAddress,76
+Selection,ISelLowering,LowerCall,1683
+Selection,ISelLowering,LowerConstantPool,11
+Selection,ISelLowering,lowerEXTRACT_VECTOR_ELT,1002
+Selection,ISelLowering,LowerFormalArguments,2016
+Selection,ISelLowering,LowerFRAMEADDR,264
+Selection,ISelLowering,LowerGlobalAddress,161
+Selection,ISelLowering,LowerGlobalTLSAddress,150
+Selection,ISelLowering,lowerINSERT_VECTOR_ELT,736
+Selection,ISelLowering,LowerINTRINSIC_W_CHAIN,2604
+Selection,ISelLowering,LowerINTRINSIC_WO_CHAIN,1364
+Selection,ISelLowering,LowerJumpTable,4
+Selection,ISelLowering,LowerOperation,1857
+Selection,ISelLowering,LowerReturn,1045
+Selection,ISelLowering,LowerRETURNADDR,258
+Selection,ISelLowering,lowerSELECT,293
+Selection,ISelLowering,lowerShiftLeftParts,864
+Selection,ISelLowering,lowerShiftRightParts,464
+Selection,ISelLowering,lowerSPLATVECTOR,1305
+Selection,ISelLowering,LowerVASTART,171
+Selection,ISelLowering,lowerVectorMaskExt,948
+Selection,ISelLowering,lowerVectorMaskTrunc,298
+Selection,ISelLowering,mayBeEmittedAsTailCall,262
+Selection,ISelLowering,NodeType,301
+Selection,ISelLowering,normaliseSetCC,96
+Selection,ISelLowering,PerformDAGCombine,84
+Selection,ISelLowering,ReplaceNodeResults,3901
+Selection,ISelLowering,shouldConsiderGEPOffsetSplit,3
+Selection,ISelLowering,shouldConvertConstantLoadToIntImm,2
+Selection,ISelLowering,shouldExpandAtomicCmpXchgInIR,88
+Selection,ISelLowering,shouldExpandAtomicRMWInIR,85
+Selection,ISelLowering,shouldExpandShift,78
+Selection,ISelLowering,shouldExtendTypeInLibCall,178
+Selection,ISelLowering,shouldInsertFencesForAtomic,6
+Selection,ISelLowering,shouldSignExtendTypeInLibCall,5
+Selection,ISelLowering,TargetLowering,3111
+Selection,ISelLowering,targetShrinkDemandedConstant,1040
+Selection,ISelLowering,validateCCReservedRegs,478
+Selection,LegalizeInfo,LegalizerInfo,12
+Selection,MCInstLower,lowerMachineInstrToMCInst,721
+Selection,MCInstLower,lowerMachineOperandToMCOperand,192
+Selection,MCInstLower,lowerSymbolOperand,254

Scripts/Exp/Correction/Dev_B.csv

@@ -0,0 +1,569 @@
+Module,File,Function,Time (Secs)
+allocation,RegisterBankInfo,RegisterBankInfo,4
+allocation,RegisterInfo,eliminateFrameIndex,583
+allocation,RegisterInfo,getCalleeSavedRegs,51
+allocation,RegisterInfo,getCallPreservedMask,38
+allocation,RegisterInfo,getFrameRegister,6
+allocation,RegisterInfo,getNoPreservedMask,8
+allocation,RegisterInfo,getPointerRegClass,8
+allocation,RegisterInfo,getReservedRegs,112
+allocation,RegisterInfo,hasReservedSpillSlot,534
+allocation,RegisterInfo,isAsmClobberable,13
+allocation,RegisterInfo,isConstantPhysReg,13
+allocation,RegisterInfo,RegisterInfo,18
+allocation,RegisterInfo,requiresFrameIndexScavenging,3
+allocation,RegisterInfo,requiresRegisterScavenging,5
+Assembler,AsmParser,addCSRSystemRegisterOperands,53
+Assembler,AsmParser,addExpr,60
+Assembler,AsmParser,addFenceArgOperands,773
+Assembler,AsmParser,addFRMArgOperands,10
+Assembler,AsmParser,addImmOperands,23
+Assembler,AsmParser,addRegOperands,29
+Assembler,AsmParser,addVTypeIOperands,16
+Assembler,AsmParser,AsmParser,202
+Assembler,AsmParser,classifySymbolRef,548
+Assembler,AsmParser,convertFPR64ToFPR16,40
+Assembler,AsmParser,convertFPR64ToFPR32,25
+Assembler,AsmParser,createImm,88
+Assembler,AsmParser,createReg,50
+Assembler,AsmParser,createSysReg,131
+Assembler,AsmParser,createToken,58
+Assembler,AsmParser,createVType,50
+Assembler,AsmParser,defaultMaskRegOp,651
+Assembler,AsmParser,emitToStreamer,68
+Assembler,AsmParser,evaluateConstantImm,93
+Assembler,AsmParser,generateImmOutOfRangeError,120
+Assembler,AsmParser,getEndLoc,86
+Assembler,AsmParser,getFeatureBits,186
+Assembler,AsmParser,getImm,259
+Assembler,AsmParser,getLoc,81
+Assembler,AsmParser,getReg,38
+Assembler,AsmParser,getRoundingMode,502
+Assembler,AsmParser,getStartLoc,13
+Assembler,AsmParser,getSysReg,33
+Assembler,AsmParser,getTargetStreamer,51
+Assembler,AsmParser,getToken,28
+Assembler,AsmParser,getVType,9
+Assembler,AsmParser,isBareSimmNLsb0,214
+Assembler,AsmParser,isBareSymbol,366
+Assembler,AsmParser,isCallSymbol,58
+Assembler,AsmParser,isCLUIImm,115
+Assembler,AsmParser,isCSRSystemRegister,64
+Assembler,AsmParser,isFenceArg,1626
+Assembler,AsmParser,isFRMArg,697
+Assembler,AsmParser,isGPR,44
+Assembler,AsmParser,isImm,20
+Assembler,AsmParser,isImmXLenLI,338
+Assembler,AsmParser,isMem,5
+Assembler,AsmParser,isPseudoJumpSymbol,44
+Assembler,AsmParser,isReg,20
+Assembler,AsmParser,isRV32E,21
+Assembler,AsmParser,isRV64,13
+Assembler,AsmParser,isRV64-2,11
+Assembler,AsmParser,isSImm10Lsb0000NonZero,44
+Assembler,AsmParser,isSImm12,316
+Assembler,AsmParser,isSImm12Lsb0,128
+Assembler,AsmParser,isSImm13Lsb0,115
+Assembler,AsmParser,isSImm21Lsb0JAL,62
+Assembler,AsmParser,isSImm5,52
+Assembler,AsmParser,isSImm5Plus1,46
+Assembler,AsmParser,isSImm6,29
+Assembler,AsmParser,isSImm6NonZero,44
+Assembler,AsmParser,isSImm9Lsb0,43
+Assembler,AsmParser,isSystemRegister,11
+Assembler,AsmParser,isToken,17
+Assembler,AsmParser,isTPRelAddSymbol,47
+Assembler,AsmParser,isUImm10Lsb00NonZero,50
+Assembler,AsmParser,isUImm20AUIPC,96
+Assembler,AsmParser,isUImm20LUI,46
+Assembler,AsmParser,isUImm5,52
+Assembler,AsmParser,isUImm7Lsb00,27
+Assembler,AsmParser,isUImm8Lsb00,19
+Assembler,AsmParser,isUImm8Lsb000,19
+Assembler,AsmParser,isUImm9Lsb000,25
+Assembler,AsmParser,isUImmLog2XLen,445
+Assembler,AsmParser,isUImmLog2XLenHalf,43
+Assembler,AsmParser,isUImmLog2XLenNonZero,55
+Assembler,AsmParser,isV0Reg,9
+Assembler,AsmParser,isVType,10
+Assembler,AsmParser,isVTypeI,7
+Assembler,AsmParser,KindTy,23
+Assembler,AsmParser,LLVMInitializeAsmParser,8
+Assembler,AsmParser,MatchAndEmitInstruction,4413
+Assembler,AsmParser,matchRegisterNameHelper,243
+Assembler,AsmParser,Operand,12
+Assembler,AsmParser,Operand2,34
+Assembler,AsmParser,parseAtomicMemOp,764
+Assembler,AsmParser,parseBareSymbol,432
+Assembler,AsmParser,parseCallSymbol,1172
+Assembler,AsmParser,parseCSRSyestemRegister,1285
+Assembler,AsmParser,ParseDirective,3966
+Assembler,AsmParser,parseImmediate,1014
+Assembler,AsmParser,ParseInstruction,664
+Assembler,AsmParser,parseJALOffset,315
+Assembler,AsmParser,parseMaskReg,1241
+Assembler,AsmParser,parseMemOpBaseReg,69
+Assembler,AsmParser,parseOperand,106
+Assembler,AsmParser,parseOperandWithModifier,111
+Assembler,AsmParser,parsePseudoJumpSymbol,730
+Assembler,AsmParser,ParseRegister,251
+Assembler,AsmParser,parseRegister2,10
+Assembler,AsmParser,parseVTypeI,425
+Assembler,AsmParser,print,52
+Assembler,AsmParser,setFeatureBits,32
+Assembler,AsmParser,tryParseRegister,19
+Assembler,AsmParser,validateTargetOperandClass,195
+Assembler,AsmPrinter,AsmPrinter,21
+Assembler,AsmPrinter,emitAttributes,107
+Assembler,AsmPrinter,emitEndOfAsmFile,38
+Assembler,AsmPrinter,emitInstruction,11
+Assembler,AsmPrinter,emitStartOfAsmFile,13
+Assembler,AsmPrinter,EmitToStreamer,19
+Assembler,AsmPrinter,getPassName,4
+Assembler,AsmPrinter,LLVMInitializeAsmPrinter,12
+Assembler,AsmPrinter,lowerOperand,330
+Assembler,AsmPrinter,PrintAsmMemoryOperand,44
+Assembler,AsmPrinter,PrintAsmOperand,318
+Assembler,AsmPrinter,runOnMachineFunction,41
+Disassembler,Disassembler,addImplySP,69
+Disassembler,Disassembler,createDisassembler,17
+Disassembler,Disassembler,decodeCLUIImmOperand,69
+Disassembler,Disassembler,DecodeFPR16RegisterClass,27
+Disassembler,Disassembler,DecodeFPR32CRegisterClass,23
+Disassembler,Disassembler,DecodeFPR32RegisterClass,28
+Disassembler,Disassembler,DecodeFPR64CRegisterClass,15
+Disassembler,Disassembler,DecodeFPR64RegisterClass,22
+Disassembler,Disassembler,decodeFRMArg,21
+Disassembler,Disassembler,DecodeGPRCRegisterClass,16
+Disassembler,Disassembler,DecodeGPRNoX0RegisterClass,54
+Disassembler,Disassembler,DecodeGPRNoX0X2RegisterClass,43
+Disassembler,Disassembler,DecodeGPRRegisterClass,50
+Disassembler,Disassembler,decodeRVCInstrRdRs1Rs2,51
+Disassembler,Disassembler,decodeRVCInstrRdRs1UImm,565
+Disassembler,Disassembler,decodeRVCInstrRdRs2,353
+Disassembler,Disassembler,decodeRVCInstrRdSImm,251
+Disassembler,Disassembler,decodeRVCInstrSImm,135
+Disassembler,Disassembler,decodeSImmNonZeroOperand,78
+Disassembler,Disassembler,decodeSImmOperand,42
+Disassembler,Disassembler,decodeSImmOperandAndLsl1,28
+Disassembler,Disassembler,decodeUImmNonZeroOperand,123
+Disassembler,Disassembler,decodeUImmOperand,33
+Disassembler,Disassembler,decodeVMaskReg,148
+Disassembler,Disassembler,DecodeVRRegisterClass,27
+Disassembler,Disassembler,Disassembler,12
+Disassembler,Disassembler,getInstruction,1214
+Disassembler,Disassembler,LLVMInitializeDisassembler,19
+Emission,AsmBackend,~AsmBackend,42
+Emission,AsmBackend,adjustFixupValue,1776
+Emission,AsmBackend,applyFixup,573
+Emission,AsmBackend,AsmBackend,236
+Emission,AsmBackend,createAsmBackend,112
+Emission,AsmBackend,createObjectTargetWriter,80
+Emission,AsmBackend,evaluateTargetFixup,2968
+Emission,AsmBackend,fixupNeedsRelaxation,52
+Emission,AsmBackend,fixupNeedsRelaxationAdvanced,188
+Emission,AsmBackend,getFixupKind,161
+Emission,AsmBackend,getFixupKindInfo,1009
+Emission,AsmBackend,getNumFixupKinds,88
+Emission,AsmBackend,getRelaxedOpcode,346
+Emission,AsmBackend,getTargetABI,54
+Emission,AsmBackend,getTargetOptions,56
+Emission,AsmBackend,mayNeedRelaxation,859
+Emission,AsmBackend,relaxInstruction,1616
+Emission,AsmBackend,requiresDiffExpressionRelocations,260
+Emission,AsmBackend,setForceRelocs,12
+Emission,AsmBackend,shouldForceRelocation,782
+Emission,AsmBackend,shouldInsertExtraNopBytesForCodeAlign,821
+Emission,AsmBackend,shouldInsertFixupForCodeAlign,812
+Emission,AsmBackend,willForceRelocations,13
+Emission,AsmBackend,writeNopData,1613
+Emission,AsmInfo,anchor,135
+Emission,AsmInfo,getExprForFDESymbol,1258
+Emission,AsmInfo,MCAsmInfo,217
+Emission,BaseInfo,ABI,12
+Emission,BaseInfo,computeTargetABI,218
+Emission,BaseInfo,FenceField,11
+Emission,BaseInfo,getTargetABI,16
+Emission,BaseInfo,II,67
+Emission,BaseInfo,OperandType,35
+Emission,BaseInfo,RISCVVSEW,10
+Emission,BaseInfo,RoundingMode,14
+Emission,BaseInfo,roundingModeToString,27
+Emission,BaseInfo,RVVConstraintType,17
+Emission,BaseInfo,stringToRoundingMode,30
+Emission,BaseInfo,validate,13
+Emission,BaseInfo,VLMUL,10
+Emission,BaseInfo,VMTs,51
+Emission,ELFObjectWriter,~ELFObjectWriter,2
+Emission,ELFObjectWriter,createELFObjectWriter,2
+Emission,ELFObjectWriter,ELFObjectWriter,4
+Emission,ELFObjectWriter,getRelocType,944
+Emission,ELFObjectWriter,needsRelocateWithSymbol,3
+Emission,ELFStreamer,AttributeItem,56
+Emission,ELFStreamer,AttributeType,8
+Emission,ELFStreamer,calculateContentSize,94
+Emission,ELFStreamer,emitAttribute,50
+Emission,ELFStreamer,emitDirectiveOptionNoPIC,8
+Emission,ELFStreamer,emitDirectiveOptionNoRelax,11
+Emission,ELFStreamer,emitDirectiveOptionNoRVC,4
+Emission,ELFStreamer,emitDirectiveOptionPIC,3
+Emission,ELFStreamer,emitDirectiveOptionPop,3
+Emission,ELFStreamer,emitDirectiveOptionPush,2
+Emission,ELFStreamer,emitDirectiveOptionRelax,3
+Emission,ELFStreamer,emitDirectiveOptionRVC,2
+Emission,ELFStreamer,emitIntTextAttribute,9
+Emission,ELFStreamer,emitTextAttribute,6
+Emission,ELFStreamer,finishAttributeSection,534
+Emission,ELFStreamer,getAttributeItem,16
+Emission,ELFStreamer,getStreamer,6
+Emission,ELFStreamer,setAttributeItem1,17
+Emission,ELFStreamer,setAttributeItem2,19
+Emission,ELFStreamer,setAttributeItems,30
+Emission,ELFStreamer,TargetELFStreamer,342
+Emission,FixupKind,enumFixups,74
+Emission,InstPrinter,applyTargetSpecificCLOption,38
+Emission,InstPrinter,getRegisterName,25
+Emission,InstPrinter,InstPrinter,27
+Emission,InstPrinter,printAtomicMemOp,59
+Emission,InstPrinter,printBranchOperand,62
+Emission,InstPrinter,printCSRSystemRegister,37
+Emission,InstPrinter,printFenceArg,89
+Emission,InstPrinter,printFRMArg,76
+Emission,InstPrinter,printInst,30
+Emission,InstPrinter,printOperand,57
+Emission,InstPrinter,printRegName,26
+Emission,InstPrinter,printVMaskReg,193
+Emission,InstPrinter,printVTypeI,14
+Emission,MatInt,generateInstSeq,415
+Emission,MatInt,getIntMatCost,275
+Emission,MatInt,structInst,27
+Emission,MCCodeEmitter,~MCCodeEmitter,4
+Emission,MCCodeEmitter,createMCCodeEmitter,36
+Emission,MCCodeEmitter,encodeInstruction,862
+Emission,MCCodeEmitter,getImmOpValue,1772
+Emission,MCCodeEmitter,getImmOpValueAsr1,266
+Emission,MCCodeEmitter,getMachineOpValue,36
+Emission,MCCodeEmitter,getVMaskReg,61
+Emission,MCCodeEmitter,MCCodeEmitter,8
+Emission,MCExpr,classof1,11
+Emission,MCExpr,classof2,8
+Emission,MCExpr,create,6
+Emission,MCExpr,enumVariantKind,24
+Emission,MCExpr,evaluateAsConstant,162
+Emission,MCExpr,evaluateAsInt64,118
+Emission,MCExpr,evaluateAsRelocatableImpl,53
+Emission,MCExpr,findAssociatedFragment,4
+Emission,MCExpr,fixELFSymbolsInTLSFixups,28
+Emission,MCExpr,fixELFSymbolsInTLSFixupsImpl,74
+Emission,MCExpr,getKind,8
+Emission,MCExpr,getPCRelHiFixup,458
+Emission,MCExpr,getSubExpr,4
+Emission,MCExpr,getVariantKindForName,78
+Emission,MCExpr,getVariantKindName,47
+Emission,MCExpr,MCExpr,20
+Emission,MCExpr,printImpl,470
+Emission,MCExpr,visitUsedExpr,6
+Emission,MCTargetDesc,createAsmTargetStreamer,16
+Emission,MCTargetDesc,createInstrAnalysis,6
+Emission,MCTargetDesc,createMCAsmInfo,24
+Emission,MCTargetDesc,createMCInstPrinter,11
+Emission,MCTargetDesc,createMCInstrInfo,10
+Emission,MCTargetDesc,createMCRegisterInfo,9
+Emission,MCTargetDesc,createMCSubtargetInfo,15
+Emission,MCTargetDesc,createNullTargetStreamer,13
+Emission,MCTargetDesc,createObjectTargetStreamer,38
+Emission,MCTargetDesc,evaluateBranch,763
+Emission,MCTargetDesc,InstrAnalysis,43
+Emission,MCTargetDesc,LLVMInitializeTargetMC,84
+Emission,TargetStreamer,emitAttribute,5
+Emission,TargetStreamer,emitAttribute2,9
+Emission,TargetStreamer,emitDirectiveOptionNoPIC,2
+Emission,TargetStreamer,emitDirectiveOptionNoPIC2,5
+Emission,TargetStreamer,emitDirectiveOptionNoRelax,4
+Emission,TargetStreamer,emitDirectiveOptionNoRelax2,5
+Emission,TargetStreamer,emitDirectiveOptionNoRVC,5
+Emission,TargetStreamer,emitDirectiveOptionNoRVC2,3
+Emission,TargetStreamer,emitDirectiveOptionPIC,4
+Emission,TargetStreamer,emitDirectiveOptionPIC2,4
+Emission,TargetStreamer,emitDirectiveOptionPop,5
+Emission,TargetStreamer,emitDirectiveOptionPop2,4
+Emission,TargetStreamer,emitDirectiveOptionPush,4
+Emission,TargetStreamer,emitDirectiveOptionPush2,4
+Emission,TargetStreamer,emitDirectiveOptionRelax,5
+Emission,TargetStreamer,emitDirectiveOptionRelax2,4
+Emission,TargetStreamer,emitDirectiveOptionRVC,5
+Emission,TargetStreamer,emitDirectiveOptionRVC2,4
+Emission,TargetStreamer,emitIntTextAttribute,4
+Emission,TargetStreamer,emitIntTextAttribute2,5
+Emission,TargetStreamer,emitTargetAttributes,739
+Emission,TargetStreamer,emitTextAttribute,3
+Emission,TargetStreamer,emitTextAttribute2,6
+Emission,TargetStreamer,finish,7
+Emission,TargetStreamer,finishAttributeSection,4
+Emission,TargetStreamer,finishAttributeSection2,6
+Emission,TargetStreamer,TargetAsmStreamer,6
+Emission,TargetStreamer,TargetStreamer,9
+Optimization,CleanupVSETVLI,CleanupVSETVLI,12
+Optimization,CleanupVSETVLI,createPass,7
+Optimization,CleanupVSETVLI,getAnalysisUsage,10
+Optimization,CleanupVSETVLI,getPassName,16
+Optimization,CleanupVSETVLI,getRequiredProperties,15
+Optimization,CleanupVSETVLI,runOnMachineBasicBlock,8186
+Optimization,CleanupVSETVLI,runOnMachineFunction,727
+Optimization,ExpandAtomicPseudoInsts,createPass,8
+Optimization,ExpandAtomicPseudoInsts,ExpandAtomicPseudo,12
+Optimization,ExpandAtomicPseudoInsts,expandMBB,879
+Optimization,ExpandAtomicPseudoInsts,expandMI,7297
+Optimization,ExpandAtomicPseudoInsts,getPassName,10
+Optimization,ExpandAtomicPseudoInsts,runOnMachineFunction,96
+Optimization,ExpandPseudoInsts,createPass,8
+Optimization,ExpandPseudoInsts,expandMBB,1571
+Optimization,ExpandPseudoInsts,expandMI,10891
+Optimization,ExpandPseudoInsts,ExpandPseudo,12
+Optimization,ExpandPseudoInsts,getPassName,10
+Optimization,ExpandPseudoInsts,runOnMachineFunction,115
+Optimization,MergeBaseOffset,createPass,15
+Optimization,MergeBaseOffset,getPassName,12
+Optimization,MergeBaseOffset,getRequiredProperties,10
+Optimization,MergeBaseOffset,MergeBaseOffsetOpt,7
+Optimization,MergeBaseOffset,runOnMachineFunction,9213
+Scheduling,InstrInfo,analyzeBranch,145
+Scheduling,InstrInfo,areMemAccessesTriviallyDisjoint,66
+Scheduling,InstrInfo,buildOutlinedFrame,489
+Scheduling,InstrInfo,copyPhysReg,539
+Scheduling,InstrInfo,decomposeMachineOperandsTargetFlags,10
+Scheduling,InstrInfo,getBranchDestBlock,24
+Scheduling,InstrInfo,getInstSizeInBytes,532
+Scheduling,InstrInfo,getMemOperandWithOffsetWidth,39
+Scheduling,InstrInfo,getOutliningCandidateInfo,665
+Scheduling,InstrInfo,getOutliningType,701
+Scheduling,InstrInfo,getSerializableDirectMachineOperandTargetFlags,34
+Scheduling,InstrInfo,insertBranch,82
+Scheduling,InstrInfo,insertIndirectBranch,679
+Scheduling,InstrInfo,insertOutlinedCall,256
+Scheduling,InstrInfo,InstrInfo,13
+Scheduling,InstrInfo,isAsCheapAsAMove,518
+Scheduling,InstrInfo,isBranchOffsetInRange,47
+Scheduling,InstrInfo,isCopyInstrImpl,648
+Scheduling,InstrInfo,isFunctionSafeToOutlineFrom,23
+Scheduling,InstrInfo,isLoadFromStackSlot,94
+Scheduling,InstrInfo,isMBBSafeToOutlineFrom,7
+Scheduling,InstrInfo,isStoreToStackSlot,81
+Scheduling,InstrInfo,loadRegFromStackSlot,121
+Scheduling,InstrInfo,movImm,819
+Scheduling,InstrInfo,parseCondBranch,25
+Scheduling,InstrInfo,removeBranch,40
+Scheduling,InstrInfo,reverseBranchCondition,229
+Scheduling,InstrInfo,storeRegToStackSlot,87
+Scheduling,InstrInfo,verifyInstruction,629
+Scheduling,MachineFunctionInfo,getLibCallStackSize,5
+Scheduling,MachineFunctionInfo,getMoveF64FrameIndex,198
+Scheduling,MachineFunctionInfo,getVarArgsFrameIndex,11
+Scheduling,MachineFunctionInfo,getVarArgsSaveSize,10
+Scheduling,MachineFunctionInfo,MachineFunctionInfo,7
+Scheduling,MachineFunctionInfo,setLibCallStackSize,4
+Scheduling,MachineFunctionInfo,setVarArgsFrameIndex,6
+Scheduling,MachineFunctionInfo,setVarArgsSaveSize,5
+Scheduling,MachineFunctionInfo,useSaveRestoreLibCalls,75
+Scheduling,Subtarget,anchor,6
+Scheduling,Subtarget,enableLinkerRelax,7
+Scheduling,Subtarget,enableMachineScheduler,6
+Scheduling,Subtarget,enableRVCHintInstrs,7
+Scheduling,Subtarget,enableSaveRestore,13
+Scheduling,Subtarget,getCallLowering,4
+Scheduling,Subtarget,getFrameLowering,10
+Scheduling,Subtarget,getInstrInfo,4
+Scheduling,Subtarget,getInstructionSelector,5
+Scheduling,Subtarget,getLegalizerInfo,5
+Scheduling,Subtarget,getRegBankInfo,4
+Scheduling,Subtarget,getRegisterInfo,6
+Scheduling,Subtarget,getSelectionDAGInfo,5
+Scheduling,Subtarget,getTargetABI,8
+Scheduling,Subtarget,getTargetLowering,9
+Scheduling,Subtarget,getXLen,9
+Scheduling,Subtarget,getXLenVT,5
+Scheduling,Subtarget,hasStdExtA,3
+Scheduling,Subtarget,hasStdExtB,2
+Scheduling,Subtarget,hasStdExtC,4
+Scheduling,Subtarget,hasStdExtD,3
+Scheduling,Subtarget,hasStdExtF,3
+Scheduling,Subtarget,hasStdExtM,4
+Scheduling,Subtarget,hasStdExtV,3
+Scheduling,Subtarget,hasStdExtZba,2
+Scheduling,Subtarget,hasStdExtZbb,4
+Scheduling,Subtarget,hasStdExtZbc,3
+Scheduling,Subtarget,hasStdExtZbe,3
+Scheduling,Subtarget,hasStdExtZbf,4
+Scheduling,Subtarget,hasStdExtZbm,5
+Scheduling,Subtarget,hasStdExtZbp,3
+Scheduling,Subtarget,hasStdExtZbproposedc,3
+Scheduling,Subtarget,hasStdExtZbr,4
+Scheduling,Subtarget,hasStdExtZbs,3
+Scheduling,Subtarget,hasStdExtZbt,3
+Scheduling,Subtarget,hasStdExtZfh,4
+Scheduling,Subtarget,hasStdExtZvamo,4
+Scheduling,Subtarget,hasStdExtZvlsseg,3
+Scheduling,Subtarget,initializeSubtargetDependencies,322
+Scheduling,Subtarget,is64Bit,4
+Scheduling,Subtarget,isRegisterReservedByUser,18
+Scheduling,Subtarget,isRV32E,5
+Scheduling,Subtarget,Subtarget,81
+Scheduling,TargetInfo,getThe32Target,17
+Scheduling,TargetInfo,getThe64Target,16
+Scheduling,TargetInfo,LLVMInitializeTargetInfo,15
+Scheduling,TargetMachine,addGlobalInstructionSelect,6
+Scheduling,TargetMachine,addInstSelector,5
+Scheduling,TargetMachine,addIRPasses,7
+Scheduling,TargetMachine,addIRTranslator,5
+Scheduling,TargetMachine,addLegalizeMachineIR,7
+Scheduling,TargetMachine,addPreEmitPass,8
+Scheduling,TargetMachine,addPreEmitPass2,11
+Scheduling,TargetMachine,addPreRegAlloc,8
+Scheduling,TargetMachine,addPreSched2,5
+Scheduling,TargetMachine,addRegBankSelect,4
+Scheduling,TargetMachine,computeDataLayout,20
+Scheduling,TargetMachine,createPassConfig,6
+Scheduling,TargetMachine,getEffectiveRelocModel,5
+Scheduling,TargetMachine,getObjFileLowering,7
+Scheduling,TargetMachine,getSubtargetImpl,56
+Scheduling,TargetMachine,getTargetMachine,17
+Scheduling,TargetMachine,getTargetTransformInfo,7
+Scheduling,TargetMachine,isNoopAddrSpaceCast,8
+Scheduling,TargetMachine,LLVMInitializeTarget,16
+Scheduling,TargetMachine,PassConfig,15
+Scheduling,TargetMachine,TargetMachine,34
+Scheduling,TargetObjectFIle,getModuleMetadata,359
+Scheduling,TargetObjectFIle,getSectionForConstant,21
+Scheduling,TargetObjectFIle,Initialize,28
+Scheduling,TargetObjectFIle,isConstantInSmallSection,16
+Scheduling,TargetObjectFIle,isGlobalInSmallSection,597
+Scheduling,TargetObjectFIle,isInSmallSection,8
+Scheduling,TargetObjectFIle,SelectSectionForGlobal,27
+Scheduling,TargetTransformInfo,getIntImmCost,282
+Scheduling,TargetTransformInfo,getIntImmCostInst,669
+Scheduling,TargetTransformInfo,getIntImmCostIntrin,9
+Scheduling,TargetTransformInfo,getST,6
+Scheduling,TargetTransformInfo,getTLI,5
+Scheduling,TargetTransformInfo,TTIImpl,21
+Selection,CallLowering,CallLowering,5
+Selection,CallLowering,lowerCall,4
+Selection,CallLowering,lowerFormalArguments,9
+Selection,CallLowering,lowerReturn,39
+Selection,FrameLowering,adjustReg,199
+Selection,FrameLowering,canUseAsEpilogue,357
+Selection,FrameLowering,canUseAsPrologue,329
+Selection,FrameLowering,determineCalleeSaves,1004
+Selection,FrameLowering,eliminateCallFramePseudoInstr,38
+Selection,FrameLowering,emitEpilogue,1178
+Selection,FrameLowering,emitPrologue,2777
+Selection,FrameLowering,FrameLowering,23
+Selection,FrameLowering,getFrameIndexReference,1142
+Selection,FrameLowering,hasBP,18
+Selection,FrameLowering,hasFP,48
+Selection,FrameLowering,hasReservedCallFrame,20
+Selection,FrameLowering,processFunctionBeforeFrameFinalized,63
+Selection,FrameLowering,restoreCalleeSavedRegisters,436
+Selection,FrameLowering,spillCalleeSavedRegisters,425
+Selection,InstructionSelector,createInstructionSelector,51
+Selection,InstructionSelector,getName,11
+Selection,InstructionSelector,InstructionSelector,9
+Selection,InstructionSelector,select,15
+Selection,ISelDAGToDAG,createISelDag,47
+Selection,ISelDAGToDAG,DAGToDAGISel,6
+Selection,ISelDAGToDAG,getPassName,5
+Selection,ISelDAGToDAG,MatchSLLIUW,163
+Selection,ISelDAGToDAG,MatchSRLIUW,497
+Selection,ISelDAGToDAG,PostprocessISelDAG,14
+Selection,ISelDAGToDAG,runOnMachineFunction,12
+Selection,ISelDAGToDAG,Select,6381
+Selection,ISelDAGToDAG,SelectAddrFI,16
+Selection,ISelDAGToDAG,SelectInlineAsmMemoryOperand,34
+Selection,ISelDAGToDAG,selectVLOp,105
+Selection,ISelDAGToDAG,selectVSplat,179
+Selection,ISelDAGToDAG,selectVSplatSimm5,210
+Selection,ISelDAGToDAG,selectVSplatUimm5,70
+Selection,ISelLowering,analyzeInputArgs,423
+Selection,ISelLowering,analyzeOutputArgs,245
+Selection,ISelLowering,CanLowerReturn,265
+Selection,ISelLowering,computeKnownBitsForTargetNode,516
+Selection,ISelLowering,ComputeNumSignBitsForTargetNode,307
+Selection,ISelLowering,convertSelectOfConstantsToMath,3
+Selection,ISelLowering,convertSetCCLogicToBitwiseLogic,5
+Selection,ISelLowering,decomposeMulByConstant,342
+Selection,ISelLowering,EmitInstrWithCustomInserter,310
+Selection,ISelLowering,emitLeadingFence,267
+Selection,ISelLowering,emitMaskedAtomicCmpXchgIntrinsic,431
+Selection,ISelLowering,emitMaskedAtomicRMWIntrinsic,315
+Selection,ISelLowering,emitTrailingFence,114
+Selection,ISelLowering,getAddr,365
+Selection,ISelLowering,getConstraintType,26
+Selection,ISelLowering,getDynamicTLSAddr,39
+Selection,ISelLowering,getExceptionPointerRegister,7
+Selection,ISelLowering,getExceptionSelectorRegister,6
+Selection,ISelLowering,getExtendForAtomicCmpSwapArg,6
+Selection,ISelLowering,getExtendForAtomicOps,5
+Selection,ISelLowering,getInlineAsmMemConstraint,12
+Selection,ISelLowering,getRegForInlineAsmConstraint,602
+Selection,ISelLowering,getRegisterByName,372
+Selection,ISelLowering,getSetCCResultType,14
+Selection,ISelLowering,getStaticTLSAddr,354
+Selection,ISelLowering,getSubtarget,6
+Selection,ISelLowering,getTargetNodeName,461
+Selection,ISelLowering,getTgtMemIntrinsic,388
+Selection,ISelLowering,hasBitPreservingFPLogic,10
+Selection,ISelLowering,isCheapToSpeculateCtlz,4
+Selection,ISelLowering,isCheapToSpeculateCttz,6
+Selection,ISelLowering,isDesirableToCommuteWithShift,558
+Selection,ISelLowering,isEligibleForTailCallOptimization,692
+Selection,ISelLowering,isFMAFasterThanFMulAndFAdd,302
+Selection,ISelLowering,isFPImmLegal,24
+Selection,ISelLowering,isLegalAddImmediate,7
+Selection,ISelLowering,isLegalAddressingMode,27
+Selection,ISelLowering,isLegalICmpImmediate,8
+Selection,ISelLowering,isSExtCheaperThanZExt,14
+Selection,ISelLowering,isTruncateFree,34
+Selection,ISelLowering,isTruncateFree2,40
+Selection,ISelLowering,isZExtFree,479
+Selection,ISelLowering,LowerAsmOperandForConstraint,422
+Selection,ISelLowering,LowerBlockAddress,23
+Selection,ISelLowering,LowerCall,5547
+Selection,ISelLowering,LowerConstantPool,19
+Selection,ISelLowering,lowerEXTRACT_VECTOR_ELT,351
+Selection,ISelLowering,LowerFormalArguments,2978
+Selection,ISelLowering,LowerFRAMEADDR,69
+Selection,ISelLowering,LowerGlobalAddress,55
+Selection,ISelLowering,LowerGlobalTLSAddress,52
+Selection,ISelLowering,lowerINSERT_VECTOR_ELT,481
+Selection,ISelLowering,LowerINTRINSIC_W_CHAIN,1953
+Selection,ISelLowering,LowerINTRINSIC_WO_CHAIN,414
+Selection,ISelLowering,LowerJumpTable,46
+Selection,ISelLowering,LowerOperation,1384
+Selection,ISelLowering,LowerReturn,2083
+Selection,ISelLowering,LowerRETURNADDR,206
+Selection,ISelLowering,lowerSELECT,243
+Selection,ISelLowering,lowerShiftLeftParts,478
+Selection,ISelLowering,lowerShiftRightParts,743
+Selection,ISelLowering,lowerSPLATVECTOR,828
+Selection,ISelLowering,LowerVASTART,93
+Selection,ISelLowering,lowerVectorMaskExt,678
+Selection,ISelLowering,lowerVectorMaskTrunc,567
+Selection,ISelLowering,mayBeEmittedAsTailCall,127
+Selection,ISelLowering,NodeType,109
+Selection,ISelLowering,normaliseSetCC,41
+Selection,ISelLowering,PerformDAGCombine,3528
+Selection,ISelLowering,ReplaceNodeResults,5797
+Selection,ISelLowering,shouldConsiderGEPOffsetSplit,6
+Selection,ISelLowering,shouldConvertConstantLoadToIntImm,4
+Selection,ISelLowering,shouldExpandAtomicCmpXchgInIR,69
+Selection,ISelLowering,shouldExpandAtomicRMWInIR,47
+Selection,ISelLowering,shouldExpandShift,15
+Selection,ISelLowering,shouldExtendTypeInLibCall,85
+Selection,ISelLowering,shouldInsertFencesForAtomic,6
+Selection,ISelLowering,shouldSignExtendTypeInLibCall,11
+Selection,ISelLowering,TargetLowering,5993
+Selection,ISelLowering,targetShrinkDemandedConstant,1157
+Selection,ISelLowering,validateCCReservedRegs,182
+Selection,LegalizeInfo,LegalizerInfo,16
+Selection,MCInstLower,lowerMachineInstrToMCInst,774
+Selection,MCInstLower,lowerMachineOperandToMCOperand,129
+Selection,MCInstLower,lowerSymbolOperand,729

Scripts/Exp/Correction/calculate_correction.py

@@ -0,0 +1,34 @@
+import csv
+
+import pathlib
+import time
+
+folder = str(pathlib.Path(__file__).parent.resolve())
+
+def sum_time_by_name(csv_file_path):
+    time_sums = {}
+    
+    with open(folder+csv_file_path, mode='r', encoding='utf-8') as csv_file:
+        csv_reader = csv.reader(csv_file)
+        next(csv_reader)
+        for row in csv_reader:
+            name = row[0].lower()
+            time_seconds = float(row[3])
+            if name not in time_sums.keys():
+                time_sums[name] = time_seconds
+            else:
+                time_sums[name] += time_seconds
+
+    return time_sums
+
+
+result_A = sum_time_by_name("/Dev_A.csv")
+
+result_B = sum_time_by_name("/Dev_B.csv")
+
+with open(folder+"/Correction.csv", mode='w', newline='', encoding='utf-8') as out_file:
+    csv_writer = csv.writer(out_file)
+    for k in result_A.keys():
+        csv_writer.writerow(["Dev A", k, round(result_A[k]/3600.0, 2)])
+    for k in result_B.keys():
+        csv_writer.writerow(["Dev B", k, round(result_B[k]/3600.0, 2)])

Scripts/Exp/Performance/LLVM-RI5CY.csv

@@ -0,0 +1,70 @@
+Case,Time (llvm-base -O0),Time (llvm-base -O3),Time (llvm-vega -O3)
+sequential_bare_test:dct   ,844.21,648.42,639.62
+sequential_bare_test:rijndael,1931.75,1096.92,1086.23
+sequential_bare_test:jacobi-2d-imper,714.09,497.83,488.85
+sequential_bare_test:bitDescriptor,678.27,313.83,308.47
+sequential_bare_test:stencil_vect,678.51,329.75,324.56
+sequential_bare_test:fir,672.44,289.27,291.87
+sequential_bare_test:stencil,377.04,230.43,233.8
+sequential_bare_test:ipm,657.87,297.08,302.72
+sequential_bare_test:towerofhanoi,466.92,285.25,284.08
+sequential_bare_test:crc32,2000.24,1542.23,1532.16
+sequential_bare_test:conv2d,582.98,258.19,262.64
+sequential_bare_test:seidel,469.66,328.91,327.65
+sequential_bare_test:fibonacci,1260.03,539.09,541.86
+sequential_bare_test:gauss-2d,783.3,453.31,444.61
+sequential_bare_test:aes_cbc,1153.49,429.36,430.55
+sequential_bare_test:bubblesort,889.5,350.96,351.36
+sequential_bare_test:fdtd-1d,956.91,800.61,810
+sequential_bare_test:jacobi-1d-imper,971.47,760.41,771.48
+sequential_bare_test:fft,908.42,518.37,510.33
+parallel_bare_tests:parMatrixMul8,2000.23,650.63,658.42
+parallel_bare_tests:conv16,2000.24,1004.25,1011.85
+parallel_bare_tests:parMatrixMul32,2000.19,1001.12,1004.26
+parallel_bare_tests:parWorkload,1899.18,660.17,654.78
+parallel_bare_tests:LU,879.8,370.01,365.92
+parallel_bare_tests:LU/golden,0.1,0.09,0.09
+parallel_bare_tests:multicore/stencil,385.17,238.8,241.14
+parallel_bare_tests:dummypar1,689.37,438.87,441.01
+parallel_bare_tests:Dijkstra/golden,0.1,0.09,0.09
+parallel_bare_tests:Dijkstra,1123.67,415.06,411.39
+parallel_bare_tests:parMatrixMul,743.66,376.12,379.63
+parallel_bare_tests:parMatrixMul16,2000.24,783.8,773.93
+riscv_tests:testBitManipulation,607.23,325.18,330.13
+riscv_tests:testVecCmp,767.9,542.69,541.05
+riscv_tests:testAddSubNorm,515.94,326.46,320.68
+riscv_tests:testMisaligned,565.95,298.21,300.45
+riscv_tests:testALU,554.23,395.23,397.37
+riscv_tests:testMAC3,410.92,373.51,373.46
+riscv_tests:testVecArith,696.61,427.99,434.34
+riscv_tests:testDotMul,807.81,458.03,455.22
+riscv_tests:testVecLogic,580,386.63,381.06
+riscv_tests:testCnt,454.3,261.02,261.72
+riscv_tests:testVecRelat,436.19,262.06,263.42
+riscv_tests:testShufflePack,525.33,309.42,314.76
+riscv_tests:testMUL,931.43,627.89,619.58
+riscv_tests:testMacNorm,653.43,377.64,370.93
+riscv_tests:testVariadic,410,218.87,220.61
+riscv_tests:testMAC,424.92,299.48,303.06
+riscv_tests:testLoadStore,577.88,386.95,394.04
+riscv_tests:testALUExt,466.44,334.77,330.55
+riscv_tests:testBuiltins,1446.37,864.55,851.72
+riscv_tests_soc:testBitManipulation,453.03,254.46,250.59
+riscv_tests_soc:testVecCmp,569.15,441.93,434.14
+riscv_tests_soc:testAddSubNorm,430.51,256.87,257.5
+riscv_tests_soc:testMisaligned,347.48,212.04,210.68
+riscv_tests_soc:testALU,425.94,306.2,305.34
+riscv_tests_soc:testMAC3,473.26,330.32,332.7
+riscv_tests_soc:testVecArith,518.19,313.03,318.73
+riscv_tests_soc:testDotMul,506.14,335.31,334.24
+riscv_tests_soc:testVecLogic,458.08,298.29,300.23
+riscv_tests_soc:testCnt,360.29,227.33,229.18
+riscv_tests_soc:testVecRelat,425.43,240.17,242.62
+riscv_tests_soc:testShufflePack,374.71,241.31,237.55
+riscv_tests_soc:testMUL,696.85,475.79,467.44
+riscv_tests_soc:testMacNorm,490.52,252.67,252.02
+riscv_tests_soc:testVariadic,321.01,182.61,181.01
+riscv_tests_soc:testMAC,309.85,244.54,249.48
+riscv_tests_soc:testLoadStore,409.3,271.1,276.01
+riscv_tests_soc:testALUExt,330.74,245.24,244.64
+riscv_tests_soc:testBuiltins,990.94,537.7,535.43

Scripts/Exp/Performance/LLVM-RISCV.csv

@@ -0,0 +1,29 @@
+Case,Time (llvm-base -O0),Time (llvm-base -O3),Time (llvm-vega -O3)
+500,5178.56,3144.76,3145.74
+502,7883.87,2008.79,2019.97
+505,2723.25,1542.69,1542.35
+508,12052.47,9994.95,10028.14
+510,28679.72,10280.97,10313.44
+511,18407.66,11545.31,11562.5
+519,10790.86,8316.93,8274.9
+520,9441.19,2125.08,2119.07
+523,13872.25,1845.85,1849.23
+525,445.68,126.48,127.38
+526,9304.23,5720.65,5759.43
+531,3919.83,1975.72,1980.25
+538,35220.96,22102.29,22111.76
+541,22602.29,3898.33,3929.8
+544,9927.67,6558.94,6614.82
+557,3601.11,1510.37,1511.34
+600,5274.71,3113.34,3112.05
+602,18135.64,3323.8,3318.74
+605,5477.68,3402.37,3398.17
+619,34229.77,25985.11,25996.42
+620,9480.42,2211.03,2200.93
+623,13689.97,1818.02,1833.97
+625,446.11,125.9,126.92
+631,5368.49,2566.73,2558.85
+638,479666.38,386191.85,389230.12
+641,25586.98,3907.47,3939.14
+644,64732.17,43677.17,43481.06
+657,19857.14,8459.01,8450.12

Scripts/Exp/Performance/LLVM-xCORE.csv

@@ -0,0 +1,23 @@
+Case,Time (llvm-base -O0),Time (llvm-base -O3),Time (llvm-vega -O3)
+crc_32,52.25,15.55,15.62
+picojpeg,117.65,44,44.16
+qrtest,68.68,32.78,32.80 
+tarfind,21.11,8.79,8.83
+libst,105.41,92.83,92.73
+libhuffbench,59.5,21.32,21.44
+nettle-sha256,65.79,46.13,46.25
+nettle-aes,93.82,43.75,43.55
+primecount,61.32,21.66,21.68
+md5,39.8,18.03,17.94
+mont64,124.67,46.69,46.71
+libslre,67.48,36.87,36.77
+libnsichneu,44.34,27.34,27.34
+matmult-int,84.91,39.04,39.85
+libud,111.48,56.27,56.5
+combined,62.89,24.6,24.56
+libwikisort,54.52,27.23,26.94
+libedn,144.46,40.41,40.74
+libstatemate,29.44,21.8,21.85
+basicmath_small,99.8,93.41,92.96
+libminver,117.05,96.42,95.66
+nbody,59.36,53.97,54.07

Scripts/Exp/Performance/calculate_perf.py

@@ -0,0 +1,28 @@
+import csv
+
+import pathlib
+import time
+
+folder = str(pathlib.Path(__file__).parent.resolve())
+
+with open(folder+"/Perf.csv", mode='w', newline='', encoding='utf-8') as out_file:
+    csv_writer = csv.writer(out_file)
+    csv_writer.writerow(["Target", "Case", "LLVM-Base", "LLVM-VEGA"])
+    
+    with open(folder+"/LLVM-RISCV.csv", mode='r', encoding='utf-8') as csv_file:
+        csv_reader = csv.reader(csv_file)
+        next(csv_reader)
+        for row in csv_reader:
+            csv_writer.writerow(["RISCV", row[0], round(float(row[1]) / float(row[2]), 6), round(float(row[1]) / float(row[3]), 6)])
+    
+    with open(folder+"/LLVM-RI5CY.csv", mode='r', encoding='utf-8') as csv_file:
+        csv_reader = csv.reader(csv_file)
+        next(csv_reader)
+        for row in csv_reader:
+            csv_writer.writerow(["RI5CY", row[0], round(float(row[1]) / float(row[2]), 6), round(float(row[1]) / float(row[3]), 6)])
+
+    with open(folder+"/LLVM-xCORE.csv", mode='r', encoding='utf-8') as csv_file:
+        csv_reader = csv.reader(csv_file)
+        next(csv_reader)
+        for row in csv_reader:
+            csv_writer.writerow(["xCORE", row[0], round(float(row[1]) / float(row[2]), 6), round(float(row[1]) / float(row[3]), 6)])