Allocation,RegisterInfo,getCalleeSavedRegs,PULP
Allocation,RegisterInfo,getFrameRegister,PULP
Assembler,AsmParser,isRV64,PULP
Assembler,AsmParser,isRV64-2,PULP
Assembler,AsmParser,isSImm6NonZero,PULP
Assembler,AsmParser,isSImm9Lsb0,PULP
Assembler,AsmParser,parseImmediate,PULP
Assembler,AsmParser,validateTargetOperandClass,PULP
Assembler,AsmPrinter,isSImm12Lsb0,PULP
Disassembler,Disassembler,addImplySP,PULP
Disassembler,Disassembler,DecodePulpV2RegisterClass,PULP
Disassembler,Disassembler,DecodePulpV4RegisterClass,PULP
Disassembler,Disassembler,decodeSImmNonZeroOperand,PULP
Disassembler,Disassembler,decodeUImmNonZeroOperand,PULP
Disassembler,Disassembler,DecodeVRRegisterClass,PULP
Disassembler,Disassembler,LLVMInitializeDisassembler,PULP
Emission,AsmBackend,applyFixup,PULP
Emission,AsmBackend,fixupNeedsRelaxationAdvanced,PULP
Emission,AsmBackend,getFixupKind,PULP
Emission,AsmBackend,getRelaxedOpcode,PULP
Emission,AsmBackend,mayNeedRelaxation,PULP
Emission,AsmInfo,MCAsmInfo,PULP
Emission,BaseInfo,ABI,PULP
Emission,BaseInfo,getTargetABI,PULP
Emission,BaseInfo,stringToRoundingMode,PULP
Emission,BaseInfo,VLMUL,PULP
Emission,ELFObjectWriter,getRelocType,PULP
Emission,ELFStreamer,calculateContentSize,PULP
Emission,ELFStreamer,setAttributeItem1,PULP
Emission,ELFStreamer,setAttributeItem2,PULP
Emission,ELFStreamer,setAttributeItems,PULP
Emission,FixupKind,enumFixups,PULP
Emission,InstPrinter,printBranchOperand,PULP
Emission,MCCodeEmitter,getVMaskReg,PULP
Emission,MCExpr,enumVariantKind,PULP
Emission,MCExpr,printImpl,PULP
Emission,MCTargetDesc,evaluateBranch,PULP
Emission,MCTargetDesc,LLVMInitializeTargetMC,PULP
Optimization,CleanupVSETVLI,getRequiredProperties,PULP
Optimization,MergeBaseOffset,getRequiredProperties,PULP
Optimization,PULPHardWareLoops,containsInvalidInstruction,PULP
Optimization,PULPHardWareLoops,getComparisonKind,PULP
Optimization,PULPHardWareLoops,getNegatedComparison,PULP
Optimization,PULPHardWareLoops,getSwappedComparison,PULP
Optimization,SNITCHFrepLoops,getComparisonKind,PULP
Scheduling,InstrInfo,isFunctionSafeToOutlineFrom,PULP
Scheduling,InstrInfo,isLoadFromStackSlot,PULP
Scheduling,InstrInfo,isMBBSafeToOutlineFrom,PULP
Scheduling,InstrInfo,isStoreToStackSlot,PULP
Scheduling,InstrInfo,loadRegFromStackSlot,PULP
Scheduling,InstrInfo,storeRegToStackSlot,PULP
Scheduling,MachineFunctionInfo,getUsedSSR,PULP
Scheduling,Subtarget,enableLinkerRelax,PULP
Scheduling,Subtarget,enableRVCHintInstrs,PULP
Scheduling,Subtarget,enableSaveRestore,PULP
Scheduling,Subtarget,getXLen,PULP
Scheduling,Subtarget,getXLenVT,PULP
Scheduling,Subtarget,is64Bit,PULP
Scheduling,TargetInfo,LLVMInitializeTargetInfo,PULP
Scheduling,TargetMachine,addPreEmitPass2,PULP
Scheduling,TargetMachine,LLVMInitializeTarget,PULP
Scheduling,TargetObjectFile,getSectionForConstant,PULP
Scheduling,TargetTransformInfo,getIntImmCostIntrin,PULP
Selection,FrameLowering,hasBP,PULP
Selection,FrameLowering,hasFP,PULP
Selection,FrameLowering,hasReservedCallFrame,PULP
Selection,InstructionSelector,InstructionSelector,PULP
Selection,ISelDAGToDAG,SelectAddrFI,PULP
Selection,ISelLowering,getConstraintType,PULP
Selection,ISelLowering,getInlineAsmMemConstraint,PULP
Selection,ISelLowering,getPointerMemTy,PULP
Selection,ISelLowering,getPointerTy,PULP
Selection,ISelLowering,getScalarShiftAmountTy,PULP
Selection,ISelLowering,getTargetNodeName,PULP
Selection,ISelLowering,isLegalAddressingMode,PULP
Selection,ISelLowering,LowerAsmOperandForConstraint,PULP
Selection,ISelLowering,LowerGlobalAddress,PULP
Selection,ISelLowering,LowerGlobalTLSAddress,PULP
Selection,ISelLowering,lowerJumpTable,PULP
Selection,ISelLowering,lowerSELECT,PULP
Selection,ISelLowering,mayBeEmittedAsTailCall,PULP
Selection,ISelLowering,NodeType,PULP
Selection,ISelLowering,shouldExpandAtomicCmpXchgInIR,PULP
Selection,ISelLowering,shouldExpandAtomicRMWInIR,PULP
Selection,ISelLowering,shouldSignExtendTypeInLibCall,PULP
Selection,MCInstLower,lowerMachineOperandToMCOperand,PULP
Selection,MCInstLower,lowerSymbolOperand,PULP
Allocation,RegisterInfo,getCalleeSavedRegs,RISCV
Allocation,RegisterInfo,getFrameRegister,RISCV
Allocation,RegisterInfo,getReservedRegs,RISCV
Assembler,AsmParser,isRV64,RISCV
Assembler,AsmParser,isRV64-2,RISCV
Assembler,AsmParser,isSImm6NonZero,RISCV
Assembler,AsmParser,isSImm9Lsb0,RISCV
Assembler,AsmParser,parseImmediate,RISCV
Assembler,AsmParser,parseOperand,RISCV
Assembler,AsmParser,validateTargetOperandClass,RISCV
Assembler,AsmPrinter,isSImm12Lsb0,RISCV
Disassembler,Disassembler,addImplySP,RISCV
Disassembler,Disassembler,decodeSImmNonZeroOperand,RISCV
Disassembler,Disassembler,decodeUImmNonZeroOperand,RISCV
Disassembler,Disassembler,DecodeVRRegisterClass,RISCV
Disassembler,Disassembler,LLVMInitializeDisassembler,RISCV
Emission,AsmBackend,applyFixup,RISCV
Emission,AsmBackend,fixupNeedsRelaxationAdvanced,RISCV
Emission,AsmBackend,getFixupKind,RISCV
Emission,AsmBackend,getRelaxedOpcode,RISCV
Emission,AsmBackend,mayNeedRelaxation,RISCV
Emission,AsmInfo,MCAsmInfo,RISCV
Emission,BaseInfo,ABI,RISCV
Emission,BaseInfo,getTargetABI,RISCV
Emission,BaseInfo,stringToRoundingMode,RISCV
Emission,BaseInfo,VLMUL,RISCV
Emission,ELFObjectWriter,getRelocType,RISCV
Emission,ELFStreamer,calculateContentSize,RISCV
Emission,ELFStreamer,setAttributeItem1,RISCV
Emission,ELFStreamer,setAttributeItem2,RISCV
Emission,ELFStreamer,setAttributeItems,RISCV
Emission,InstPrinter,printBranchOperand,RISCV
Emission,MCCodeEmitter,getVMaskReg,RISCV
Emission,MCExpr,enumVariantKind,RISCV
Emission,MCExpr,printImpl,RISCV
Emission,MCTargetDesc,LLVMInitializeTargetMC,RISCV
Optimization,CleanupVSETVLI,getRequiredProperties,RISCV
Optimization,CleanupVSETVLI,runOnMachineFunction,RISCV
Optimization,MergeBaseOffset,getRequiredProperties,RISCV
Scheduling,InstrInfo,isFunctionSafeToOutlineFrom,RISCV
Scheduling,InstrInfo,isLoadFromStackSlot,RISCV
Scheduling,InstrInfo,isMBBSafeToOutlineFrom,RISCV
Scheduling,InstrInfo,isStoreToStackSlot,RISCV
Scheduling,InstrInfo,loadRegFromStackSlot,RISCV
Scheduling,InstrInfo,storeRegToStackSlot,RISCV
Scheduling,Subtarget,enableLinkerRelax,RISCV
Scheduling,Subtarget,enableRVCHintInstrs,RISCV
Scheduling,Subtarget,enableSaveRestore,RISCV
Scheduling,Subtarget,getXLen,RISCV
Scheduling,Subtarget,getXLenVT,RISCV
Scheduling,Subtarget,is64Bit,RISCV
Scheduling,TargetInfo,LLVMInitializeTargetInfo,RISCV
Scheduling,TargetMachine,addPreEmitPass2,RISCV
Scheduling,TargetMachine,LLVMInitializeTarget,RISCV
Scheduling,TargetObjectFile,getSectionForConstant,RISCV
Scheduling,TargetTransformInfo,getIntImmCostIntrin,RISCV
Selection,FrameLowering,hasBP,RISCV
Selection,FrameLowering,hasFP,RISCV
Selection,FrameLowering,hasReservedCallFrame,RISCV
Selection,InstructionSelector,InstructionSelector,RISCV
Selection,ISelDAGToDAG,SelectAddrFI,RISCV
Selection,ISelLowering,getConstraintType,RISCV
Selection,ISelLowering,getInlineAsmMemConstraint,RISCV
Selection,ISelLowering,getTargetNodeName,RISCV
Selection,ISelLowering,isLegalAddressingMode,RISCV
Selection,ISelLowering,LowerAsmOperandForConstraint,RISCV
Selection,ISelLowering,LowerGlobalAddress,RISCV
Selection,ISelLowering,LowerGlobalTLSAddress,RISCV
Selection,ISelLowering,lowerJumpTable,RISCV
Selection,ISelLowering,lowerSELECT,RISCV
Selection,ISelLowering,mayBeEmittedAsTailCall,RISCV
Selection,ISelLowering,NodeType,RISCV
Selection,ISelLowering,shouldExpandAtomicCmpXchgInIR,RISCV
Selection,ISelLowering,shouldExpandAtomicRMWInIR,RISCV
Selection,ISelLowering,shouldSignExtendTypeInLibCall,RISCV
Selection,MCInstLower,lowerMachineOperandToMCOperand,RISCV
Selection,MCInstLower,lowerSymbolOperand,RISCV
Emission,MCTargetDesc,LLVMInitializeTargetMC,XCore
Scheduling,InstrInfo,GetCondBranchFromCond,XCore
Scheduling,InstrInfo,GetOppositeBranchCondition,XCore
Scheduling,InstrInfo,IsCondBranch,XCore
Scheduling,TargetMachine,addPreEmitPass,XCore
Selection,ISelLowering,enumNodeType,XCore
Selection,ISelLowering,getTargetNodeName,XCore