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Audio Classification
edge-impulse
tinyml
embedded
cpp
audio
wake-word
kws
keyword-spotting
microphone
synthetic-data
hey-edge
Model card Files
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Commit
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1 Parent(s): e894f08

Publish Edge Impulse model via ModelForge

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Files changed (50) hide show
  1. .gitattributes +1 -0
  2. CMakeLists.txt +14 -0
  3. README.md +1459 -0
  4. README.txt +16 -0
  5. edge-impulse-sdk/.gitignore +13 -0
  6. edge-impulse-sdk/.mbedignore +12 -0
  7. edge-impulse-sdk/CMSIS/Core/Include/cachel1_armv7.h +434 -0
  8. edge-impulse-sdk/CMSIS/Core/Include/cmsis_armcc.h +888 -0
  9. edge-impulse-sdk/CMSIS/Core/Include/cmsis_armclang.h +1503 -0
  10. edge-impulse-sdk/CMSIS/Core/Include/cmsis_armclang_ltm.h +1928 -0
  11. edge-impulse-sdk/CMSIS/Core/Include/cmsis_compiler.h +283 -0
  12. edge-impulse-sdk/CMSIS/Core/Include/cmsis_gcc.h +2217 -0
  13. edge-impulse-sdk/CMSIS/Core/Include/cmsis_iccarm.h +1002 -0
  14. edge-impulse-sdk/CMSIS/Core/Include/cmsis_version.h +39 -0
  15. edge-impulse-sdk/CMSIS/Core/Include/core_armv81mml.h +0 -0
  16. edge-impulse-sdk/CMSIS/Core/Include/core_armv8mbl.h +0 -0
  17. edge-impulse-sdk/CMSIS/Core/Include/core_armv8mml.h +0 -0
  18. edge-impulse-sdk/CMSIS/Core/Include/core_cm0.h +952 -0
  19. edge-impulse-sdk/CMSIS/Core/Include/core_cm0plus.h +1087 -0
  20. edge-impulse-sdk/CMSIS/Core/Include/core_cm1.h +979 -0
  21. edge-impulse-sdk/CMSIS/Core/Include/core_cm23.h +0 -0
  22. edge-impulse-sdk/CMSIS/Core/Include/core_cm3.h +0 -0
  23. edge-impulse-sdk/CMSIS/Core/Include/core_cm33.h +0 -0
  24. edge-impulse-sdk/CMSIS/Core/Include/core_cm35p.h +0 -0
  25. edge-impulse-sdk/CMSIS/Core/Include/core_cm4.h +0 -0
  26. edge-impulse-sdk/CMSIS/Core/Include/core_cm55.h +0 -0
  27. edge-impulse-sdk/CMSIS/Core/Include/core_cm7.h +0 -0
  28. edge-impulse-sdk/CMSIS/Core/Include/core_cm85.h +0 -0
  29. edge-impulse-sdk/CMSIS/Core/Include/core_sc000.h +1030 -0
  30. edge-impulse-sdk/CMSIS/Core/Include/core_sc300.h +0 -0
  31. edge-impulse-sdk/CMSIS/Core/Include/core_starmc1.h +0 -0
  32. edge-impulse-sdk/CMSIS/Core/Include/mpu_armv7.h +275 -0
  33. edge-impulse-sdk/CMSIS/Core/Include/mpu_armv8.h +352 -0
  34. edge-impulse-sdk/CMSIS/Core/Include/pac_armv81.h +206 -0
  35. edge-impulse-sdk/CMSIS/Core/Include/pmu_armv8.h +337 -0
  36. edge-impulse-sdk/CMSIS/Core/Include/tz_context.h +70 -0
  37. edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h +539 -0
  38. edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables_f16.h +132 -0
  39. edge-impulse-sdk/CMSIS/DSP/Include/arm_const_structs.h +86 -0
  40. edge-impulse-sdk/CMSIS/DSP/Include/arm_const_structs_f16.h +77 -0
  41. edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h +753 -0
  42. edge-impulse-sdk/CMSIS/DSP/Include/arm_math.h +225 -0
  43. edge-impulse-sdk/CMSIS/DSP/Include/arm_math_f16.h +59 -0
  44. edge-impulse-sdk/CMSIS/DSP/Include/arm_math_memory.h +206 -0
  45. edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h +616 -0
  46. edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types_f16.h +163 -0
  47. edge-impulse-sdk/CMSIS/DSP/Include/arm_mve_tables.h +231 -0
  48. edge-impulse-sdk/CMSIS/DSP/Include/arm_mve_tables_f16.h +109 -0
  49. edge-impulse-sdk/CMSIS/DSP/Include/arm_sorting.h +200 -0
  50. edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_fft.h +325 -0
.gitattributes CHANGED
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  *.zip filter=lfs diff=lfs merge=lfs -text
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  *.zst filter=lfs diff=lfs merge=lfs -text
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  *tfevents* filter=lfs diff=lfs merge=lfs -text
 
 
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  *.zip filter=lfs diff=lfs merge=lfs -text
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  *.zst filter=lfs diff=lfs merge=lfs -text
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  *tfevents* filter=lfs diff=lfs merge=lfs -text
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+ edge-impulse-sdk/third_party/arc_mli_package/bin/emsdp_em11d_em9d_dfss/release/libmli.a filter=lfs diff=lfs merge=lfs -text
CMakeLists.txt ADDED
@@ -0,0 +1,14 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ cmake_minimum_required(VERSION 3.13.1)
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+
3
+ if(NOT TARGET app)
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+ message(FATAL_ERROR "Please create a target named 'app' (ex: add_executable(app)) before adding this file")
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+ endif()
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+
7
+ include(edge-impulse-sdk/cmake/utils.cmake)
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+ add_subdirectory(edge-impulse-sdk/cmake/zephyr)
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+
10
+ RECURSIVE_FIND_FILE_APPEND(MODEL_SOURCE "tflite-model" "*.cpp")
11
+ target_include_directories(app PRIVATE .)
12
+
13
+ # add all sources to the project
14
+ target_sources(app PRIVATE ${MODEL_SOURCE})
README.md ADDED
@@ -0,0 +1,1459 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ ---
2
+ license: apache-2.0
3
+ tags:
4
+ - edge-impulse
5
+ - tinyml
6
+ - embedded
7
+ - cpp
8
+ - audio
9
+ - wake word
10
+ - kws
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+ - edge impulse
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+ - hey edge
13
+ pipeline_tag: audio-classification
14
+ ---
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+
16
+ # Hey-Edge
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+
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+ Trained via Edge Impulse using synthetic and augmented audio.
19
+
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+ ## Model details
21
+
22
+ | Field | Value |
23
+ |---|---|
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+ | Export type | Edge Impulse C++ library |
25
+ | Modality | audio |
26
+ | Sensor | microphone |
27
+ | Sample frequency | 16000 Hz |
28
+ | Input feature count | 3960 |
29
+
30
+
31
+ ## Files in this repository
32
+
33
+ ```
34
+ CMakeLists.txt
35
+ README.txt
36
+ edge-impulse-sdk/.gitignore
37
+ edge-impulse-sdk/.mbedignore
38
+ edge-impulse-sdk/CMSIS/Core/Include/cachel1_armv7.h
39
+ edge-impulse-sdk/CMSIS/Core/Include/cmsis_armcc.h
40
+ edge-impulse-sdk/CMSIS/Core/Include/cmsis_armclang.h
41
+ edge-impulse-sdk/CMSIS/Core/Include/cmsis_armclang_ltm.h
42
+ edge-impulse-sdk/CMSIS/Core/Include/cmsis_compiler.h
43
+ edge-impulse-sdk/CMSIS/Core/Include/cmsis_gcc.h
44
+ edge-impulse-sdk/CMSIS/Core/Include/cmsis_iccarm.h
45
+ edge-impulse-sdk/CMSIS/Core/Include/cmsis_version.h
46
+ edge-impulse-sdk/CMSIS/Core/Include/core_armv81mml.h
47
+ edge-impulse-sdk/CMSIS/Core/Include/core_armv8mbl.h
48
+ edge-impulse-sdk/CMSIS/Core/Include/core_armv8mml.h
49
+ edge-impulse-sdk/CMSIS/Core/Include/core_cm0.h
50
+ edge-impulse-sdk/CMSIS/Core/Include/core_cm0plus.h
51
+ edge-impulse-sdk/CMSIS/Core/Include/core_cm1.h
52
+ edge-impulse-sdk/CMSIS/Core/Include/core_cm23.h
53
+ edge-impulse-sdk/CMSIS/Core/Include/core_cm3.h
54
+ edge-impulse-sdk/CMSIS/Core/Include/core_cm33.h
55
+ edge-impulse-sdk/CMSIS/Core/Include/core_cm35p.h
56
+ edge-impulse-sdk/CMSIS/Core/Include/core_cm4.h
57
+ edge-impulse-sdk/CMSIS/Core/Include/core_cm55.h
58
+ edge-impulse-sdk/CMSIS/Core/Include/core_cm7.h
59
+ edge-impulse-sdk/CMSIS/Core/Include/core_cm85.h
60
+ edge-impulse-sdk/CMSIS/Core/Include/core_sc000.h
61
+ edge-impulse-sdk/CMSIS/Core/Include/core_sc300.h
62
+ edge-impulse-sdk/CMSIS/Core/Include/core_starmc1.h
63
+ edge-impulse-sdk/CMSIS/Core/Include/mpu_armv7.h
64
+ edge-impulse-sdk/CMSIS/Core/Include/mpu_armv8.h
65
+ edge-impulse-sdk/CMSIS/Core/Include/pac_armv81.h
66
+ edge-impulse-sdk/CMSIS/Core/Include/pmu_armv8.h
67
+ edge-impulse-sdk/CMSIS/Core/Include/tz_context.h
68
+ edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h
69
+ edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables_f16.h
70
+ edge-impulse-sdk/CMSIS/DSP/Include/arm_const_structs.h
71
+ edge-impulse-sdk/CMSIS/DSP/Include/arm_const_structs_f16.h
72
+ edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h
73
+ edge-impulse-sdk/CMSIS/DSP/Include/arm_math.h
74
+ edge-impulse-sdk/CMSIS/DSP/Include/arm_math_f16.h
75
+ edge-impulse-sdk/CMSIS/DSP/Include/arm_math_memory.h
76
+ edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h
77
+ edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types_f16.h
78
+ edge-impulse-sdk/CMSIS/DSP/Include/arm_mve_tables.h
79
+ edge-impulse-sdk/CMSIS/DSP/Include/arm_mve_tables_f16.h
80
+ edge-impulse-sdk/CMSIS/DSP/Include/arm_sorting.h
81
+ edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_fft.h
82
+ edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_filtering.h
83
+ edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math.h
84
+ edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math_f16.h
85
+ edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h
86
+ edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions_f16.h
87
+ edge-impulse-sdk/CMSIS/DSP/Include/dsp/bayes_functions.h
88
+ edge-impulse-sdk/CMSIS/DSP/Include/dsp/bayes_functions_f16.h
89
+ edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions.h
90
+ edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions_f16.h
91
+ edge-impulse-sdk/CMSIS/DSP/Include/dsp/controller_functions.h
92
+ edge-impulse-sdk/CMSIS/DSP/Include/dsp/controller_functions_f16.h
93
+ edge-impulse-sdk/CMSIS/DSP/Include/dsp/debug.h
94
+ edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions.h
95
+ edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions_f16.h
96
+ edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions.h
97
+ edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions_f16.h
98
+ edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h
99
+ edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions_f16.h
100
+ edge-impulse-sdk/CMSIS/DSP/Include/dsp/interpolation_functions.h
101
+ edge-impulse-sdk/CMSIS/DSP/Include/dsp/interpolation_functions_f16.h
102
+ edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h
103
+ edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions_f16.h
104
+ edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_utils.h
105
+ edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h
106
+ edge-impulse-sdk/CMSIS/DSP/Include/dsp/quaternion_math_functions.h
107
+ edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h
108
+ edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions_f16.h
109
+ edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions.h
110
+ edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions_f16.h
111
+ edge-impulse-sdk/CMSIS/DSP/Include/dsp/svm_defines.h
112
+ edge-impulse-sdk/CMSIS/DSP/Include/dsp/svm_functions.h
113
+ edge-impulse-sdk/CMSIS/DSP/Include/dsp/svm_functions_f16.h
114
+ edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h
115
+ edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions_f16.h
116
+ edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h
117
+ edge-impulse-sdk/CMSIS/DSP/PrivateInclude/README.md
118
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f16.c
119
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f32.c
120
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f64.c
121
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q15.c
122
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q31.c
123
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q7.c
124
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f16.c
125
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f32.c
126
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f64.c
127
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q15.c
128
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q31.c
129
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q7.c
130
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_and_u16.c
131
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_and_u32.c
132
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_and_u8.c
133
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_f16.c
134
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137
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_q7.c
138
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f16.c
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+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f32.c
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+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f64.c
141
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q15.c
142
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q31.c
143
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q7.c
144
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f16.c
145
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f32.c
146
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f64.c
147
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q15.c
148
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q31.c
149
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q7.c
150
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f16.c
151
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f32.c
152
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f64.c
153
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q15.c
154
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q31.c
155
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q7.c
156
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157
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_not_u32.c
158
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_not_u8.c
159
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f16.c
160
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f32.c
161
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f64.c
162
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q15.c
163
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q31.c
164
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q7.c
165
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_or_u16.c
166
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_or_u32.c
167
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_or_u8.c
168
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f16.c
169
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f32.c
170
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f64.c
171
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q15.c
172
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q31.c
173
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q7.c
174
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q15.c
175
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q31.c
176
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q7.c
177
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f16.c
178
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f32.c
179
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f64.c
180
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q15.c
181
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q31.c
182
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q7.c
183
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_u16.c
184
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_u32.c
185
+ edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_u8.c
186
+ edge-impulse-sdk/CMSIS/DSP/Source/BayesFunctions/arm_gaussian_naive_bayes_predict_f16.c
187
+ edge-impulse-sdk/CMSIS/DSP/Source/BayesFunctions/arm_gaussian_naive_bayes_predict_f32.c
188
+ edge-impulse-sdk/CMSIS/DSP/Source/CommonTables/arm_common_tables.c
189
+ edge-impulse-sdk/CMSIS/DSP/Source/CommonTables/arm_common_tables_f16.c
190
+ edge-impulse-sdk/CMSIS/DSP/Source/CommonTables/arm_const_structs.c
191
+ edge-impulse-sdk/CMSIS/DSP/Source/CommonTables/arm_const_structs_f16.c
192
+ edge-impulse-sdk/CMSIS/DSP/Source/CommonTables/arm_mve_tables.c
193
+ edge-impulse-sdk/CMSIS/DSP/Source/CommonTables/arm_mve_tables_f16.c
194
+ edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f16.c
195
+ edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c
196
+ edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c
197
+ edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c
198
+ edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f16.c
199
+ edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
200
+ edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
201
+ edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
202
+ edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f16.c
203
+ edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c
204
+ edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f64.c
205
+ edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_fast_q15.c
206
+ edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c
207
+ edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c
208
+ edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f16.c
209
+ edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
210
+ edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f64.c
211
+ edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
212
+ edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
213
+ edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f16.c
214
+ edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
215
+ edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f64.c
216
+ edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
217
+ edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
218
+ edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f16.c
219
+ edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c
220
+ edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c
221
+ edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c
222
+ edge-impulse-sdk/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_f32.c
223
+ edge-impulse-sdk/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q15.c
224
+ edge-impulse-sdk/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q31.c
225
+ edge-impulse-sdk/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_f32.c
226
+ edge-impulse-sdk/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q15.c
227
+ edge-impulse-sdk/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q31.c
228
+ edge-impulse-sdk/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_f32.c
229
+ edge-impulse-sdk/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_q31.c
230
+ edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_boolean_distance.c
231
+ edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_boolean_distance_template.h
232
+ edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_braycurtis_distance_f16.c
233
+ edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_braycurtis_distance_f32.c
234
+ edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_canberra_distance_f16.c
235
+ edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_canberra_distance_f32.c
236
+ edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_chebyshev_distance_f16.c
237
+ edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_chebyshev_distance_f32.c
238
+ edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_chebyshev_distance_f64.c
239
+ edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_cityblock_distance_f16.c
240
+ edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_cityblock_distance_f32.c
241
+ edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_cityblock_distance_f64.c
242
+ edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_correlation_distance_f16.c
243
+ edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_correlation_distance_f32.c
244
+ edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_cosine_distance_f16.c
245
+ edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_cosine_distance_f32.c
246
+ edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_cosine_distance_f64.c
247
+ edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_dice_distance.c
248
+ edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_euclidean_distance_f16.c
249
+ edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_euclidean_distance_f32.c
250
+ edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_euclidean_distance_f64.c
251
+ edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_hamming_distance.c
252
+ edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_jaccard_distance.c
253
+ edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_jensenshannon_distance_f16.c
254
+ edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_jensenshannon_distance_f32.c
255
+ edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_kulsinski_distance.c
256
+ edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_minkowski_distance_f16.c
257
+ edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_minkowski_distance_f32.c
258
+ edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_rogerstanimoto_distance.c
259
+ edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_russellrao_distance.c
260
+ edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_sokalmichener_distance.c
261
+ edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_sokalsneath_distance.c
262
+ edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_yule_distance.c
263
+ edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_f16.c
264
+ edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_f32.c
265
+ edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_q15.c
266
+ edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_q31.c
267
+ edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_cos_f32.c
268
+ edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q15.c
269
+ edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q31.c
270
+ edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_divide_q15.c
271
+ edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_divide_q31.c
272
+ edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_sin_f32.c
273
+ edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q15.c
274
+ edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q31.c
275
+ edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q15.c
276
+ edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q31.c
277
+ edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_vexp_f16.c
278
+ edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_vexp_f32.c
279
+ edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_vexp_f64.c
280
+ edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_vinverse_f16.c
281
+ edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_f16.c
282
+ edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_f32.c
283
+ edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_f64.c
284
+ edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_q15.c
285
+ edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_q31.c
286
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
287
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
288
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f16.c
289
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c
290
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
291
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
292
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f16.c
293
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
294
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
295
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
296
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c
297
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c
298
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f16.c
299
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c
300
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.c
301
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f16.c
302
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
303
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.c
304
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f16.c
305
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.c
306
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f16.c
307
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.c
308
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_f32.c
309
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_opt_q15.c
310
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q15.c
311
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q31.c
312
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q15.c
313
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q7.c
314
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_f32.c
315
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c
316
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q15.c
317
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q31.c
318
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q15.c
319
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q7.c
320
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q15.c
321
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q31.c
322
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q7.c
323
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q15.c
324
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q31.c
325
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q7.c
326
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f16.c
327
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f32.c
328
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f64.c
329
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c
330
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q15.c
331
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q31.c
332
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q15.c
333
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q7.c
334
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q15.c
335
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q31.c
336
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q7.c
337
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_f32.c
338
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c
339
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c
340
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_f32.c
341
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q15.c
342
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q31.c
343
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q15.c
344
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q31.c
345
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f16.c
346
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f32.c
347
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f64.c
348
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q15.c
349
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q31.c
350
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f16.c
351
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f32.c
352
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f64.c
353
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q15.c
354
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q31.c
355
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q7.c
356
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_f32.c
357
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c
358
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c
359
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c
360
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q15.c
361
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q31.c
362
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_f32.c
363
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_f32.c
364
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q15.c
365
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q31.c
366
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q15.c
367
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q31.c
368
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q15.c
369
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q31.c
370
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q7.c
371
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_f32.c
372
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_f32.c
373
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q15.c
374
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q31.c
375
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q7.c
376
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q15.c
377
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q31.c
378
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q7.c
379
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_f32.c
380
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_f32.c
381
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q15.c
382
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q31.c
383
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q15.c
384
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q31.c
385
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_levinson_durbin_f16.c
386
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_levinson_durbin_f32.c
387
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_levinson_durbin_q31.c
388
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_f32.c
389
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_f32.c
390
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q15.c
391
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q31.c
392
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_f32.c
393
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_f32.c
394
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q15.c
395
+ edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q31.c
396
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397
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398
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399
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400
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401
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402
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403
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405
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406
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407
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408
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409
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410
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411
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412
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413
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414
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415
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416
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417
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418
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419
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420
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421
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422
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423
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424
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425
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427
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428
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429
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430
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431
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432
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434
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435
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436
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437
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438
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439
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440
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441
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442
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443
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444
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445
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446
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447
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448
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449
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450
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451
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452
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453
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454
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455
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456
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457
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458
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459
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460
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461
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462
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463
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464
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465
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466
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467
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468
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469
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470
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471
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472
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473
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474
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475
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476
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477
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478
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479
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480
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481
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482
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483
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484
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485
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486
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487
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488
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489
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490
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491
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492
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493
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494
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495
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496
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497
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498
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499
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500
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501
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502
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503
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504
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505
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506
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507
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508
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509
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510
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511
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512
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513
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514
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515
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516
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517
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518
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519
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520
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521
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522
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523
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524
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525
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526
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527
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528
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529
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530
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531
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532
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533
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534
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535
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536
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537
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538
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539
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540
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541
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542
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543
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544
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545
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546
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547
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548
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549
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550
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551
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552
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553
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554
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555
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556
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557
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558
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559
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560
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561
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562
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563
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564
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565
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566
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567
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568
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569
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570
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571
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572
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573
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574
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575
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576
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577
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578
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579
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580
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581
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582
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583
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584
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585
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586
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588
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589
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590
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591
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592
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594
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595
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596
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597
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598
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599
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600
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601
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602
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603
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604
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605
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606
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607
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608
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609
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610
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611
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612
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613
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614
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615
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616
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617
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618
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619
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620
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621
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622
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623
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624
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625
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626
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627
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1354
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1371
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1372
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1373
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+ edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_struct.h
1396
+ edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_table.h
1397
+ edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_util.h
1398
+ edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_vector.h
1399
+ edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_vector_downward.h
1400
+ edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_verifier.h
1401
+ edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/flatbuffers.h
1402
+ edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/flexbuffers.h
1403
+ edge-impulse-sdk/third_party/gemmlowp/LICENSE
1404
+ edge-impulse-sdk/third_party/gemmlowp/fixedpoint/fixedpoint.h
1405
+ edge-impulse-sdk/third_party/gemmlowp/fixedpoint/fixedpoint_neon.h
1406
+ edge-impulse-sdk/third_party/gemmlowp/fixedpoint/fixedpoint_sse.h
1407
+ edge-impulse-sdk/third_party/gemmlowp/internal/detect_platform.h
1408
+ edge-impulse-sdk/third_party/incbin/incbin.h
1409
+ edge-impulse-sdk/third_party/ruy/ruy/profiler/instrumentation.h
1410
+ model-parameters/model_metadata.h
1411
+ model-parameters/model_variables.h
1412
+ tflite-model/tflite_learn_1052106_5_compiled.cpp
1413
+ tflite-model/tflite_learn_1052106_5_compiled.h
1414
+ tflite-model/trained_model_ops_define.h
1415
+ ```
1416
+
1417
+ ## How to run
1418
+
1419
+ ### Build the C++ library
1420
+
1421
+ ```bash
1422
+ pip install huggingface_hub
1423
+ hf download edgeimpulse/Hey-Edge --local-dir ./impulse
1424
+ cd impulse
1425
+ # Standalone example (from the Edge Impulse C++ SDK):
1426
+ make -j
1427
+ ./build/edge-impulse-standalone <features.txt>
1428
+ ```
1429
+
1430
+ The archive contains `edge-impulse-sdk/`, `model-parameters/` and
1431
+ `tflite-model/`. Integrate it into your firmware/app per the Edge Impulse C++
1432
+ inferencing docs: <https://docs.edgeimpulse.com/deploy-your-model/running-your-impulse-locally/deploy-your-impulse-as-a-c-library>
1433
+
1434
+ ### Download from the Hub
1435
+
1436
+ ```bash
1437
+ pip install huggingface_hub
1438
+ # whole repo:
1439
+ hf download edgeimpulse/Hey-Edge --local-dir ./Hey-Edge
1440
+ # or a single file:
1441
+ hf download edgeimpulse/Hey-Edge CMakeLists.txt --local-dir .
1442
+ ```
1443
+
1444
+ ```python
1445
+ from huggingface_hub import hf_hub_download, snapshot_download
1446
+ path = hf_hub_download("edgeimpulse/Hey-Edge", "CMakeLists.txt") # one file
1447
+ folder = snapshot_download("edgeimpulse/Hey-Edge") # whole repo
1448
+ ```
1449
+
1450
+
1451
+ ## About
1452
+
1453
+ This model was exported from [Edge Impulse](https://edgeimpulse.com) and
1454
+ published to the Hub with **ModelForge**. Edge Impulse handles data collection,
1455
+ DSP feature extraction and model training; this repo packages the resulting
1456
+ deployment artifact plus ready-to-run instructions.
1457
+
1458
+ - Edge Impulse deployment docs: <https://docs.edgeimpulse.com/deploy-your-model>
1459
+ - Running impulses locally: <https://docs.edgeimpulse.com/deploy-your-model/running-your-impulse-locally>
README.txt ADDED
@@ -0,0 +1,16 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+
2
+ # Edge Impulse library for Hey Edge - Wake Word / Keyword Spotting (KWS) Model
3
+
4
+ This is a C++ library that lets you run the impulse for "Hey Edge - Wake Word / Keyword Spotting (KWS) Model" (https://studio.edgeimpulse.com/studio/1052106) on any device. It consists of the Edge Impulse inferencing SDK - with implementations of both processing and learning blocks - and your model. You will need to include this library in your project to run your impulse locally.
5
+
6
+ ## Getting Started
7
+
8
+ Please refer to the following documentation to learn how to use this library:
9
+
10
+ * Deploy your model as a C++ library: https://docs.edgeimpulse.com/docs/deploy-your-model-as-a-c-library
11
+ * Running your impulse locally: https://docs.edgeimpulse.com/docs/running-your-impulse-locally-1
12
+ * C++ Inference SDK Library API Reference: https://docs.edgeimpulse.com/reference/inferencing-sdk
13
+
14
+ ## Example Projects
15
+
16
+ For example projects, see 'Running your impulse locally' in the docs (https://docs.edgeimpulse.com/docs/running-your-impulse-locally-1). These pages have examples for virtually any platform under the sun including Linux, Mbed OS, Zephyr, FreeRTOS, and bare-metal on a wide range of platforms. These examples also show how to enable hardware acceleration on Cortex-M, Cortex-A, ARC DSPs and other platforms.
edge-impulse-sdk/.gitignore ADDED
@@ -0,0 +1,13 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ utensor/CTestTestfile.cmake
2
+ utensor/cmake_install.cmake
3
+ utensor/CMakeFiles/
4
+ utensor/Makefile
5
+ utensor/CMakeCache.txt
6
+ utensor.lib
7
+ utensor/libutensor.a
8
+ *.o
9
+ *.d
10
+ doc/
11
+ node_modules/
12
+ package-lock.json
13
+ package.json
edge-impulse-sdk/.mbedignore ADDED
@@ -0,0 +1,12 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ utensor/CMakeFiles/
2
+ tensorflow/lite/micro/mbed/
3
+ porting/arduino/
4
+ porting/espressif/
5
+ porting/himax/
6
+ porting/posix/
7
+ porting/silabs/
8
+ porting/stm32-cubeai/
9
+ porting/zephyr/
10
+ classifier/ei_run_classifier_c*
11
+ third_party/arc_mli_package/
12
+ tensorflow-lite/
edge-impulse-sdk/CMSIS/Core/Include/cachel1_armv7.h ADDED
@@ -0,0 +1,434 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ /******************************************************************************
2
+ * @file cachel1_armv7.h
3
+ * @brief CMSIS Level 1 Cache API for Armv7-M and later
4
+ * @version V1.0.2
5
+ * @date 22. June 2022
6
+ ******************************************************************************/
7
+ /*
8
+ * Copyright (c) 2020-2021 Arm Limited. All rights reserved.
9
+ *
10
+ * SPDX-License-Identifier: Apache-2.0
11
+ *
12
+ * Licensed under the Apache License, Version 2.0 (the License); you may
13
+ * not use this file except in compliance with the License.
14
+ * You may obtain a copy of the License at
15
+ *
16
+ * www.apache.org/licenses/LICENSE-2.0
17
+ *
18
+ * Unless required by applicable law or agreed to in writing, software
19
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21
+ * See the License for the specific language governing permissions and
22
+ * limitations under the License.
23
+ */
24
+
25
+ #if defined ( __ICCARM__ )
26
+ #pragma system_include /* treat file as system include file for MISRA check */
27
+ #elif defined (__clang__)
28
+ #pragma clang system_header /* treat file as system include file */
29
+ #endif
30
+
31
+ #ifndef ARM_CACHEL1_ARMV7_H
32
+ #define ARM_CACHEL1_ARMV7_H
33
+
34
+ /**
35
+ \ingroup CMSIS_Core_FunctionInterface
36
+ \defgroup CMSIS_Core_CacheFunctions Cache Functions
37
+ \brief Functions that configure Instruction and Data cache.
38
+ @{
39
+ */
40
+
41
+ /* Cache Size ID Register Macros */
42
+ #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
43
+ #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
44
+
45
+ #ifndef __SCB_DCACHE_LINE_SIZE
46
+ #define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
47
+ #endif
48
+
49
+ #ifndef __SCB_ICACHE_LINE_SIZE
50
+ #define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
51
+ #endif
52
+
53
+ /**
54
+ \brief Enable I-Cache
55
+ \details Turns on I-Cache
56
+ */
57
+ __STATIC_FORCEINLINE void SCB_EnableICache (void)
58
+ {
59
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
60
+ if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
61
+
62
+ __DSB();
63
+ __ISB();
64
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
65
+ __DSB();
66
+ __ISB();
67
+ SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
68
+ __DSB();
69
+ __ISB();
70
+ #endif
71
+ }
72
+
73
+
74
+ /**
75
+ \brief Disable I-Cache
76
+ \details Turns off I-Cache
77
+ */
78
+ __STATIC_FORCEINLINE void SCB_DisableICache (void)
79
+ {
80
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
81
+ __DSB();
82
+ __ISB();
83
+ SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
84
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
85
+ __DSB();
86
+ __ISB();
87
+ #endif
88
+ }
89
+
90
+
91
+ /**
92
+ \brief Invalidate I-Cache
93
+ \details Invalidates I-Cache
94
+ */
95
+ __STATIC_FORCEINLINE void SCB_InvalidateICache (void)
96
+ {
97
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
98
+ __DSB();
99
+ __ISB();
100
+ SCB->ICIALLU = 0UL;
101
+ __DSB();
102
+ __ISB();
103
+ #endif
104
+ }
105
+
106
+
107
+ /**
108
+ \brief I-Cache Invalidate by address
109
+ \details Invalidates I-Cache for the given address.
110
+ I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
111
+ I-Cache memory blocks which are part of given address + given size are invalidated.
112
+ \param[in] addr address
113
+ \param[in] isize size of memory block (in number of bytes)
114
+ */
115
+ __STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize)
116
+ {
117
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
118
+ if ( isize > 0 ) {
119
+ int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
120
+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
121
+
122
+ __DSB();
123
+
124
+ do {
125
+ SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
126
+ op_addr += __SCB_ICACHE_LINE_SIZE;
127
+ op_size -= __SCB_ICACHE_LINE_SIZE;
128
+ } while ( op_size > 0 );
129
+
130
+ __DSB();
131
+ __ISB();
132
+ }
133
+ #endif
134
+ }
135
+
136
+
137
+ /**
138
+ \brief Enable D-Cache
139
+ \details Turns on D-Cache
140
+ */
141
+ __STATIC_FORCEINLINE void SCB_EnableDCache (void)
142
+ {
143
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
144
+ uint32_t ccsidr;
145
+ uint32_t sets;
146
+ uint32_t ways;
147
+
148
+ if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
149
+
150
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
151
+ __DSB();
152
+
153
+ ccsidr = SCB->CCSIDR;
154
+
155
+ /* invalidate D-Cache */
156
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
157
+ do {
158
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
159
+ do {
160
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
161
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
162
+ #if defined ( __CC_ARM )
163
+ __schedule_barrier();
164
+ #endif
165
+ } while (ways-- != 0U);
166
+ } while(sets-- != 0U);
167
+ __DSB();
168
+
169
+ SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
170
+
171
+ __DSB();
172
+ __ISB();
173
+ #endif
174
+ }
175
+
176
+
177
+ /**
178
+ \brief Disable D-Cache
179
+ \details Turns off D-Cache
180
+ */
181
+ __STATIC_FORCEINLINE void SCB_DisableDCache (void)
182
+ {
183
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
184
+ struct {
185
+ uint32_t ccsidr;
186
+ uint32_t sets;
187
+ uint32_t ways;
188
+ } locals
189
+ #if ((defined(__GNUC__) || defined(__clang__)) && !defined(__OPTIMIZE__))
190
+ __ALIGNED(__SCB_DCACHE_LINE_SIZE)
191
+ #endif
192
+ ;
193
+
194
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
195
+ __DSB();
196
+
197
+ SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
198
+ __DSB();
199
+
200
+ #if ((defined(__GNUC__) || defined(__clang__)) && !defined(__OPTIMIZE__))
201
+ /*
202
+ * For the endless loop issue with GCC and clang with O0.
203
+ * More details, see https://github.com/ARM-software/CMSIS_5/issues/620
204
+ *
205
+ * The issue only happens when local variables are in stack (GCC/clang O0). If
206
+ * local variables are saved in general purpose register, then the function
207
+ * is OK.
208
+ *
209
+ * When local variables are in stack, after disabling the cache, flush the
210
+ * local variables cache line for data consistency.
211
+ */
212
+ /* Clean and invalidate the local variable cache. */
213
+ SCB->DCCIMVAC = (uint32_t)&locals;
214
+ __DSB();
215
+ __ISB();
216
+ #endif
217
+
218
+ locals.ccsidr = SCB->CCSIDR;
219
+ /* clean & invalidate D-Cache */
220
+ locals.sets = (uint32_t)(CCSIDR_SETS(locals.ccsidr));
221
+ do {
222
+ locals.ways = (uint32_t)(CCSIDR_WAYS(locals.ccsidr));
223
+ do {
224
+ SCB->DCCISW = (((locals.sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
225
+ ((locals.ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
226
+ #if defined ( __CC_ARM )
227
+ __schedule_barrier();
228
+ #endif
229
+ } while (locals.ways-- != 0U);
230
+ } while(locals.sets-- != 0U);
231
+
232
+ __DSB();
233
+ __ISB();
234
+ #endif
235
+ }
236
+
237
+
238
+ /**
239
+ \brief Invalidate D-Cache
240
+ \details Invalidates D-Cache
241
+ */
242
+ __STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
243
+ {
244
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
245
+ uint32_t ccsidr;
246
+ uint32_t sets;
247
+ uint32_t ways;
248
+
249
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
250
+ __DSB();
251
+
252
+ ccsidr = SCB->CCSIDR;
253
+
254
+ /* invalidate D-Cache */
255
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
256
+ do {
257
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
258
+ do {
259
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
260
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
261
+ #if defined ( __CC_ARM )
262
+ __schedule_barrier();
263
+ #endif
264
+ } while (ways-- != 0U);
265
+ } while(sets-- != 0U);
266
+
267
+ __DSB();
268
+ __ISB();
269
+ #endif
270
+ }
271
+
272
+
273
+ /**
274
+ \brief Clean D-Cache
275
+ \details Cleans D-Cache
276
+ */
277
+ __STATIC_FORCEINLINE void SCB_CleanDCache (void)
278
+ {
279
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
280
+ uint32_t ccsidr;
281
+ uint32_t sets;
282
+ uint32_t ways;
283
+
284
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
285
+ __DSB();
286
+
287
+ ccsidr = SCB->CCSIDR;
288
+
289
+ /* clean D-Cache */
290
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
291
+ do {
292
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
293
+ do {
294
+ SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
295
+ ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
296
+ #if defined ( __CC_ARM )
297
+ __schedule_barrier();
298
+ #endif
299
+ } while (ways-- != 0U);
300
+ } while(sets-- != 0U);
301
+
302
+ __DSB();
303
+ __ISB();
304
+ #endif
305
+ }
306
+
307
+
308
+ /**
309
+ \brief Clean & Invalidate D-Cache
310
+ \details Cleans and Invalidates D-Cache
311
+ */
312
+ __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
313
+ {
314
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
315
+ uint32_t ccsidr;
316
+ uint32_t sets;
317
+ uint32_t ways;
318
+
319
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
320
+ __DSB();
321
+
322
+ ccsidr = SCB->CCSIDR;
323
+
324
+ /* clean & invalidate D-Cache */
325
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
326
+ do {
327
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
328
+ do {
329
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
330
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
331
+ #if defined ( __CC_ARM )
332
+ __schedule_barrier();
333
+ #endif
334
+ } while (ways-- != 0U);
335
+ } while(sets-- != 0U);
336
+
337
+ __DSB();
338
+ __ISB();
339
+ #endif
340
+ }
341
+
342
+
343
+ /**
344
+ \brief D-Cache Invalidate by address
345
+ \details Invalidates D-Cache for the given address.
346
+ D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
347
+ D-Cache memory blocks which are part of given address + given size are invalidated.
348
+ \param[in] addr address
349
+ \param[in] dsize size of memory block (in number of bytes)
350
+ */
351
+ __STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
352
+ {
353
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
354
+ if ( dsize > 0 ) {
355
+ int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
356
+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
357
+
358
+ __DSB();
359
+
360
+ do {
361
+ SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
362
+ op_addr += __SCB_DCACHE_LINE_SIZE;
363
+ op_size -= __SCB_DCACHE_LINE_SIZE;
364
+ } while ( op_size > 0 );
365
+
366
+ __DSB();
367
+ __ISB();
368
+ }
369
+ #endif
370
+ }
371
+
372
+
373
+ /**
374
+ \brief D-Cache Clean by address
375
+ \details Cleans D-Cache for the given address
376
+ D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
377
+ D-Cache memory blocks which are part of given address + given size are cleaned.
378
+ \param[in] addr address
379
+ \param[in] dsize size of memory block (in number of bytes)
380
+ */
381
+ __STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize)
382
+ {
383
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
384
+ if ( dsize > 0 ) {
385
+ int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
386
+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
387
+
388
+ __DSB();
389
+
390
+ do {
391
+ SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
392
+ op_addr += __SCB_DCACHE_LINE_SIZE;
393
+ op_size -= __SCB_DCACHE_LINE_SIZE;
394
+ } while ( op_size > 0 );
395
+
396
+ __DSB();
397
+ __ISB();
398
+ }
399
+ #endif
400
+ }
401
+
402
+
403
+ /**
404
+ \brief D-Cache Clean and Invalidate by address
405
+ \details Cleans and invalidates D_Cache for the given address
406
+ D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
407
+ D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
408
+ \param[in] addr address (aligned to 32-byte boundary)
409
+ \param[in] dsize size of memory block (in number of bytes)
410
+ */
411
+ __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
412
+ {
413
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
414
+ if ( dsize > 0 ) {
415
+ int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
416
+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
417
+
418
+ __DSB();
419
+
420
+ do {
421
+ SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
422
+ op_addr += __SCB_DCACHE_LINE_SIZE;
423
+ op_size -= __SCB_DCACHE_LINE_SIZE;
424
+ } while ( op_size > 0 );
425
+
426
+ __DSB();
427
+ __ISB();
428
+ }
429
+ #endif
430
+ }
431
+
432
+ /*@} end of CMSIS_Core_CacheFunctions */
433
+
434
+ #endif /* ARM_CACHEL1_ARMV7_H */
edge-impulse-sdk/CMSIS/Core/Include/cmsis_armcc.h ADDED
@@ -0,0 +1,888 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ /**************************************************************************//**
2
+ * @file cmsis_armcc.h
3
+ * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
4
+ * @version V5.3.2
5
+ * @date 27. May 2021
6
+ ******************************************************************************/
7
+ /*
8
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
9
+ *
10
+ * SPDX-License-Identifier: Apache-2.0
11
+ *
12
+ * Licensed under the Apache License, Version 2.0 (the License); you may
13
+ * not use this file except in compliance with the License.
14
+ * You may obtain a copy of the License at
15
+ *
16
+ * www.apache.org/licenses/LICENSE-2.0
17
+ *
18
+ * Unless required by applicable law or agreed to in writing, software
19
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21
+ * See the License for the specific language governing permissions and
22
+ * limitations under the License.
23
+ */
24
+
25
+ #ifndef __CMSIS_ARMCC_H
26
+ #define __CMSIS_ARMCC_H
27
+
28
+
29
+ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
30
+ #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
31
+ #endif
32
+
33
+ /* CMSIS compiler control architecture macros */
34
+ #if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
35
+ (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
36
+ #define __ARM_ARCH_6M__ 1
37
+ #endif
38
+
39
+ #if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
40
+ #define __ARM_ARCH_7M__ 1
41
+ #endif
42
+
43
+ #if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
44
+ #define __ARM_ARCH_7EM__ 1
45
+ #endif
46
+
47
+ /* __ARM_ARCH_8M_BASE__ not applicable */
48
+ /* __ARM_ARCH_8M_MAIN__ not applicable */
49
+ /* __ARM_ARCH_8_1M_MAIN__ not applicable */
50
+
51
+ /* CMSIS compiler control DSP macros */
52
+ #if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
53
+ #define __ARM_FEATURE_DSP 1
54
+ #endif
55
+
56
+ /* CMSIS compiler specific defines */
57
+ #ifndef __ASM
58
+ #define __ASM __asm
59
+ #endif
60
+ #ifndef __INLINE
61
+ #define __INLINE __inline
62
+ #endif
63
+ #ifndef __STATIC_INLINE
64
+ #define __STATIC_INLINE static __inline
65
+ #endif
66
+ #ifndef __STATIC_FORCEINLINE
67
+ #define __STATIC_FORCEINLINE static __forceinline
68
+ #endif
69
+ #ifndef __NO_RETURN
70
+ #define __NO_RETURN __declspec(noreturn)
71
+ #endif
72
+ #ifndef __USED
73
+ #define __USED __attribute__((used))
74
+ #endif
75
+ #ifndef __WEAK
76
+ #define __WEAK __attribute__((weak))
77
+ #endif
78
+ #ifndef __PACKED
79
+ #define __PACKED __attribute__((packed))
80
+ #endif
81
+ #ifndef __PACKED_STRUCT
82
+ #define __PACKED_STRUCT __packed struct
83
+ #endif
84
+ #ifndef __PACKED_UNION
85
+ #define __PACKED_UNION __packed union
86
+ #endif
87
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
88
+ #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
89
+ #endif
90
+ #ifndef __UNALIGNED_UINT16_WRITE
91
+ #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
92
+ #endif
93
+ #ifndef __UNALIGNED_UINT16_READ
94
+ #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
95
+ #endif
96
+ #ifndef __UNALIGNED_UINT32_WRITE
97
+ #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
98
+ #endif
99
+ #ifndef __UNALIGNED_UINT32_READ
100
+ #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
101
+ #endif
102
+ #ifndef __ALIGNED
103
+ #define __ALIGNED(x) __attribute__((aligned(x)))
104
+ #endif
105
+ #ifndef __RESTRICT
106
+ #define __RESTRICT __restrict
107
+ #endif
108
+ #ifndef __COMPILER_BARRIER
109
+ #define __COMPILER_BARRIER() __memory_changed()
110
+ #endif
111
+
112
+ /* ######################### Startup and Lowlevel Init ######################## */
113
+
114
+ #ifndef __PROGRAM_START
115
+ #define __PROGRAM_START __main
116
+ #endif
117
+
118
+ #ifndef __INITIAL_SP
119
+ #define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
120
+ #endif
121
+
122
+ #ifndef __STACK_LIMIT
123
+ #define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
124
+ #endif
125
+
126
+ #ifndef __VECTOR_TABLE
127
+ #define __VECTOR_TABLE __Vectors
128
+ #endif
129
+
130
+ #ifndef __VECTOR_TABLE_ATTRIBUTE
131
+ #define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
132
+ #endif
133
+
134
+ /* ########################## Core Instruction Access ######################### */
135
+ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
136
+ Access to dedicated instructions
137
+ @{
138
+ */
139
+
140
+ /**
141
+ \brief No Operation
142
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
143
+ */
144
+ #define __NOP __nop
145
+
146
+
147
+ /**
148
+ \brief Wait For Interrupt
149
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
150
+ */
151
+ #define __WFI __wfi
152
+
153
+
154
+ /**
155
+ \brief Wait For Event
156
+ \details Wait For Event is a hint instruction that permits the processor to enter
157
+ a low-power state until one of a number of events occurs.
158
+ */
159
+ #define __WFE __wfe
160
+
161
+
162
+ /**
163
+ \brief Send Event
164
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
165
+ */
166
+ #define __SEV __sev
167
+
168
+
169
+ /**
170
+ \brief Instruction Synchronization Barrier
171
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
172
+ so that all instructions following the ISB are fetched from cache or memory,
173
+ after the instruction has been completed.
174
+ */
175
+ #define __ISB() __isb(0xF)
176
+
177
+ /**
178
+ \brief Data Synchronization Barrier
179
+ \details Acts as a special kind of Data Memory Barrier.
180
+ It completes when all explicit memory accesses before this instruction complete.
181
+ */
182
+ #define __DSB() __dsb(0xF)
183
+
184
+ /**
185
+ \brief Data Memory Barrier
186
+ \details Ensures the apparent order of the explicit memory operations before
187
+ and after the instruction, without ensuring their completion.
188
+ */
189
+ #define __DMB() __dmb(0xF)
190
+
191
+
192
+ /**
193
+ \brief Reverse byte order (32 bit)
194
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
195
+ \param [in] value Value to reverse
196
+ \return Reversed value
197
+ */
198
+ #define __REV __rev
199
+
200
+
201
+ /**
202
+ \brief Reverse byte order (16 bit)
203
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
204
+ \param [in] value Value to reverse
205
+ \return Reversed value
206
+ */
207
+ #ifndef __NO_EMBEDDED_ASM
208
+ __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
209
+ {
210
+ rev16 r0, r0
211
+ bx lr
212
+ }
213
+ #endif
214
+
215
+
216
+ /**
217
+ \brief Reverse byte order (16 bit)
218
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
219
+ \param [in] value Value to reverse
220
+ \return Reversed value
221
+ */
222
+ #ifndef __NO_EMBEDDED_ASM
223
+ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
224
+ {
225
+ revsh r0, r0
226
+ bx lr
227
+ }
228
+ #endif
229
+
230
+
231
+ /**
232
+ \brief Rotate Right in unsigned value (32 bit)
233
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
234
+ \param [in] op1 Value to rotate
235
+ \param [in] op2 Number of Bits to rotate
236
+ \return Rotated value
237
+ */
238
+ #define __ROR __ror
239
+
240
+
241
+ /**
242
+ \brief Breakpoint
243
+ \details Causes the processor to enter Debug state.
244
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
245
+ \param [in] value is ignored by the processor.
246
+ If required, a debugger can use it to store additional information about the breakpoint.
247
+ */
248
+ #define __BKPT(value) __breakpoint(value)
249
+
250
+
251
+ /**
252
+ \brief Reverse bit order of value
253
+ \details Reverses the bit order of the given value.
254
+ \param [in] value Value to reverse
255
+ \return Reversed value
256
+ */
257
+ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
258
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
259
+ #define __RBIT __rbit
260
+ #else
261
+ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
262
+ {
263
+ uint32_t result;
264
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
265
+
266
+ result = value; /* r will be reversed bits of v; first get LSB of v */
267
+ for (value >>= 1U; value != 0U; value >>= 1U)
268
+ {
269
+ result <<= 1U;
270
+ result |= value & 1U;
271
+ s--;
272
+ }
273
+ result <<= s; /* shift when v's highest bits are zero */
274
+ return result;
275
+ }
276
+ #endif
277
+
278
+
279
+ /**
280
+ \brief Count leading zeros
281
+ \details Counts the number of leading zeros of a data value.
282
+ \param [in] value Value to count the leading zeros
283
+ \return number of leading zeros in value
284
+ */
285
+ #define __CLZ __clz
286
+
287
+
288
+ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
289
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
290
+
291
+ /**
292
+ \brief LDR Exclusive (8 bit)
293
+ \details Executes a exclusive LDR instruction for 8 bit value.
294
+ \param [in] ptr Pointer to data
295
+ \return value of type uint8_t at (*ptr)
296
+ */
297
+ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
298
+ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
299
+ #else
300
+ #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
301
+ #endif
302
+
303
+
304
+ /**
305
+ \brief LDR Exclusive (16 bit)
306
+ \details Executes a exclusive LDR instruction for 16 bit values.
307
+ \param [in] ptr Pointer to data
308
+ \return value of type uint16_t at (*ptr)
309
+ */
310
+ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
311
+ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
312
+ #else
313
+ #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
314
+ #endif
315
+
316
+
317
+ /**
318
+ \brief LDR Exclusive (32 bit)
319
+ \details Executes a exclusive LDR instruction for 32 bit values.
320
+ \param [in] ptr Pointer to data
321
+ \return value of type uint32_t at (*ptr)
322
+ */
323
+ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
324
+ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
325
+ #else
326
+ #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
327
+ #endif
328
+
329
+
330
+ /**
331
+ \brief STR Exclusive (8 bit)
332
+ \details Executes a exclusive STR instruction for 8 bit values.
333
+ \param [in] value Value to store
334
+ \param [in] ptr Pointer to location
335
+ \return 0 Function succeeded
336
+ \return 1 Function failed
337
+ */
338
+ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
339
+ #define __STREXB(value, ptr) __strex(value, ptr)
340
+ #else
341
+ #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
342
+ #endif
343
+
344
+
345
+ /**
346
+ \brief STR Exclusive (16 bit)
347
+ \details Executes a exclusive STR instruction for 16 bit values.
348
+ \param [in] value Value to store
349
+ \param [in] ptr Pointer to location
350
+ \return 0 Function succeeded
351
+ \return 1 Function failed
352
+ */
353
+ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
354
+ #define __STREXH(value, ptr) __strex(value, ptr)
355
+ #else
356
+ #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
357
+ #endif
358
+
359
+
360
+ /**
361
+ \brief STR Exclusive (32 bit)
362
+ \details Executes a exclusive STR instruction for 32 bit values.
363
+ \param [in] value Value to store
364
+ \param [in] ptr Pointer to location
365
+ \return 0 Function succeeded
366
+ \return 1 Function failed
367
+ */
368
+ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
369
+ #define __STREXW(value, ptr) __strex(value, ptr)
370
+ #else
371
+ #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
372
+ #endif
373
+
374
+
375
+ /**
376
+ \brief Remove the exclusive lock
377
+ \details Removes the exclusive lock which is created by LDREX.
378
+ */
379
+ #define __CLREX __clrex
380
+
381
+
382
+ /**
383
+ \brief Signed Saturate
384
+ \details Saturates a signed value.
385
+ \param [in] value Value to be saturated
386
+ \param [in] sat Bit position to saturate to (1..32)
387
+ \return Saturated value
388
+ */
389
+ #define __SSAT __ssat
390
+
391
+
392
+ /**
393
+ \brief Unsigned Saturate
394
+ \details Saturates an unsigned value.
395
+ \param [in] value Value to be saturated
396
+ \param [in] sat Bit position to saturate to (0..31)
397
+ \return Saturated value
398
+ */
399
+ #define __USAT __usat
400
+
401
+
402
+ /**
403
+ \brief Rotate Right with Extend (32 bit)
404
+ \details Moves each bit of a bitstring right by one bit.
405
+ The carry input is shifted in at the left end of the bitstring.
406
+ \param [in] value Value to rotate
407
+ \return Rotated value
408
+ */
409
+ #ifndef __NO_EMBEDDED_ASM
410
+ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
411
+ {
412
+ rrx r0, r0
413
+ bx lr
414
+ }
415
+ #endif
416
+
417
+
418
+ /**
419
+ \brief LDRT Unprivileged (8 bit)
420
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
421
+ \param [in] ptr Pointer to data
422
+ \return value of type uint8_t at (*ptr)
423
+ */
424
+ #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
425
+
426
+
427
+ /**
428
+ \brief LDRT Unprivileged (16 bit)
429
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
430
+ \param [in] ptr Pointer to data
431
+ \return value of type uint16_t at (*ptr)
432
+ */
433
+ #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
434
+
435
+
436
+ /**
437
+ \brief LDRT Unprivileged (32 bit)
438
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
439
+ \param [in] ptr Pointer to data
440
+ \return value of type uint32_t at (*ptr)
441
+ */
442
+ #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
443
+
444
+
445
+ /**
446
+ \brief STRT Unprivileged (8 bit)
447
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
448
+ \param [in] value Value to store
449
+ \param [in] ptr Pointer to location
450
+ */
451
+ #define __STRBT(value, ptr) __strt(value, ptr)
452
+
453
+
454
+ /**
455
+ \brief STRT Unprivileged (16 bit)
456
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
457
+ \param [in] value Value to store
458
+ \param [in] ptr Pointer to location
459
+ */
460
+ #define __STRHT(value, ptr) __strt(value, ptr)
461
+
462
+
463
+ /**
464
+ \brief STRT Unprivileged (32 bit)
465
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
466
+ \param [in] value Value to store
467
+ \param [in] ptr Pointer to location
468
+ */
469
+ #define __STRT(value, ptr) __strt(value, ptr)
470
+
471
+ #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
472
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
473
+
474
+ /**
475
+ \brief Signed Saturate
476
+ \details Saturates a signed value.
477
+ \param [in] value Value to be saturated
478
+ \param [in] sat Bit position to saturate to (1..32)
479
+ \return Saturated value
480
+ */
481
+ __attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
482
+ {
483
+ if ((sat >= 1U) && (sat <= 32U))
484
+ {
485
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
486
+ const int32_t min = -1 - max ;
487
+ if (val > max)
488
+ {
489
+ return max;
490
+ }
491
+ else if (val < min)
492
+ {
493
+ return min;
494
+ }
495
+ }
496
+ return val;
497
+ }
498
+
499
+ /**
500
+ \brief Unsigned Saturate
501
+ \details Saturates an unsigned value.
502
+ \param [in] value Value to be saturated
503
+ \param [in] sat Bit position to saturate to (0..31)
504
+ \return Saturated value
505
+ */
506
+ __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
507
+ {
508
+ if (sat <= 31U)
509
+ {
510
+ const uint32_t max = ((1U << sat) - 1U);
511
+ if (val > (int32_t)max)
512
+ {
513
+ return max;
514
+ }
515
+ else if (val < 0)
516
+ {
517
+ return 0U;
518
+ }
519
+ }
520
+ return (uint32_t)val;
521
+ }
522
+
523
+ #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
524
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
525
+
526
+ /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
527
+
528
+
529
+ /* ########################### Core Function Access ########################### */
530
+ /** \ingroup CMSIS_Core_FunctionInterface
531
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
532
+ @{
533
+ */
534
+
535
+ /**
536
+ \brief Enable IRQ Interrupts
537
+ \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
538
+ Can only be executed in Privileged modes.
539
+ */
540
+ /* intrinsic void __enable_irq(); */
541
+
542
+
543
+ /**
544
+ \brief Disable IRQ Interrupts
545
+ \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
546
+ Can only be executed in Privileged modes.
547
+ */
548
+ /* intrinsic void __disable_irq(); */
549
+
550
+ /**
551
+ \brief Get Control Register
552
+ \details Returns the content of the Control Register.
553
+ \return Control Register value
554
+ */
555
+ __STATIC_INLINE uint32_t __get_CONTROL(void)
556
+ {
557
+ register uint32_t __regControl __ASM("control");
558
+ return(__regControl);
559
+ }
560
+
561
+
562
+ /**
563
+ \brief Set Control Register
564
+ \details Writes the given value to the Control Register.
565
+ \param [in] control Control Register value to set
566
+ */
567
+ __STATIC_INLINE void __set_CONTROL(uint32_t control)
568
+ {
569
+ register uint32_t __regControl __ASM("control");
570
+ __regControl = control;
571
+ __ISB();
572
+ }
573
+
574
+
575
+ /**
576
+ \brief Get IPSR Register
577
+ \details Returns the content of the IPSR Register.
578
+ \return IPSR Register value
579
+ */
580
+ __STATIC_INLINE uint32_t __get_IPSR(void)
581
+ {
582
+ register uint32_t __regIPSR __ASM("ipsr");
583
+ return(__regIPSR);
584
+ }
585
+
586
+
587
+ /**
588
+ \brief Get APSR Register
589
+ \details Returns the content of the APSR Register.
590
+ \return APSR Register value
591
+ */
592
+ __STATIC_INLINE uint32_t __get_APSR(void)
593
+ {
594
+ register uint32_t __regAPSR __ASM("apsr");
595
+ return(__regAPSR);
596
+ }
597
+
598
+
599
+ /**
600
+ \brief Get xPSR Register
601
+ \details Returns the content of the xPSR Register.
602
+ \return xPSR Register value
603
+ */
604
+ __STATIC_INLINE uint32_t __get_xPSR(void)
605
+ {
606
+ register uint32_t __regXPSR __ASM("xpsr");
607
+ return(__regXPSR);
608
+ }
609
+
610
+
611
+ /**
612
+ \brief Get Process Stack Pointer
613
+ \details Returns the current value of the Process Stack Pointer (PSP).
614
+ \return PSP Register value
615
+ */
616
+ __STATIC_INLINE uint32_t __get_PSP(void)
617
+ {
618
+ register uint32_t __regProcessStackPointer __ASM("psp");
619
+ return(__regProcessStackPointer);
620
+ }
621
+
622
+
623
+ /**
624
+ \brief Set Process Stack Pointer
625
+ \details Assigns the given value to the Process Stack Pointer (PSP).
626
+ \param [in] topOfProcStack Process Stack Pointer value to set
627
+ */
628
+ __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
629
+ {
630
+ register uint32_t __regProcessStackPointer __ASM("psp");
631
+ __regProcessStackPointer = topOfProcStack;
632
+ }
633
+
634
+
635
+ /**
636
+ \brief Get Main Stack Pointer
637
+ \details Returns the current value of the Main Stack Pointer (MSP).
638
+ \return MSP Register value
639
+ */
640
+ __STATIC_INLINE uint32_t __get_MSP(void)
641
+ {
642
+ register uint32_t __regMainStackPointer __ASM("msp");
643
+ return(__regMainStackPointer);
644
+ }
645
+
646
+
647
+ /**
648
+ \brief Set Main Stack Pointer
649
+ \details Assigns the given value to the Main Stack Pointer (MSP).
650
+ \param [in] topOfMainStack Main Stack Pointer value to set
651
+ */
652
+ __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
653
+ {
654
+ register uint32_t __regMainStackPointer __ASM("msp");
655
+ __regMainStackPointer = topOfMainStack;
656
+ }
657
+
658
+
659
+ /**
660
+ \brief Get Priority Mask
661
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
662
+ \return Priority Mask value
663
+ */
664
+ __STATIC_INLINE uint32_t __get_PRIMASK(void)
665
+ {
666
+ register uint32_t __regPriMask __ASM("primask");
667
+ return(__regPriMask);
668
+ }
669
+
670
+
671
+ /**
672
+ \brief Set Priority Mask
673
+ \details Assigns the given value to the Priority Mask Register.
674
+ \param [in] priMask Priority Mask
675
+ */
676
+ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
677
+ {
678
+ register uint32_t __regPriMask __ASM("primask");
679
+ __regPriMask = (priMask);
680
+ }
681
+
682
+
683
+ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
684
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
685
+
686
+ /**
687
+ \brief Enable FIQ
688
+ \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
689
+ Can only be executed in Privileged modes.
690
+ */
691
+ #define __enable_fault_irq __enable_fiq
692
+
693
+
694
+ /**
695
+ \brief Disable FIQ
696
+ \details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
697
+ Can only be executed in Privileged modes.
698
+ */
699
+ #define __disable_fault_irq __disable_fiq
700
+
701
+
702
+ /**
703
+ \brief Get Base Priority
704
+ \details Returns the current value of the Base Priority register.
705
+ \return Base Priority register value
706
+ */
707
+ __STATIC_INLINE uint32_t __get_BASEPRI(void)
708
+ {
709
+ register uint32_t __regBasePri __ASM("basepri");
710
+ return(__regBasePri);
711
+ }
712
+
713
+
714
+ /**
715
+ \brief Set Base Priority
716
+ \details Assigns the given value to the Base Priority register.
717
+ \param [in] basePri Base Priority value to set
718
+ */
719
+ __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
720
+ {
721
+ register uint32_t __regBasePri __ASM("basepri");
722
+ __regBasePri = (basePri & 0xFFU);
723
+ }
724
+
725
+
726
+ /**
727
+ \brief Set Base Priority with condition
728
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
729
+ or the new value increases the BASEPRI priority level.
730
+ \param [in] basePri Base Priority value to set
731
+ */
732
+ __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
733
+ {
734
+ register uint32_t __regBasePriMax __ASM("basepri_max");
735
+ __regBasePriMax = (basePri & 0xFFU);
736
+ }
737
+
738
+
739
+ /**
740
+ \brief Get Fault Mask
741
+ \details Returns the current value of the Fault Mask register.
742
+ \return Fault Mask register value
743
+ */
744
+ __STATIC_INLINE uint32_t __get_FAULTMASK(void)
745
+ {
746
+ register uint32_t __regFaultMask __ASM("faultmask");
747
+ return(__regFaultMask);
748
+ }
749
+
750
+
751
+ /**
752
+ \brief Set Fault Mask
753
+ \details Assigns the given value to the Fault Mask register.
754
+ \param [in] faultMask Fault Mask value to set
755
+ */
756
+ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
757
+ {
758
+ register uint32_t __regFaultMask __ASM("faultmask");
759
+ __regFaultMask = (faultMask & (uint32_t)1U);
760
+ }
761
+
762
+ #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
763
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
764
+
765
+
766
+ /**
767
+ \brief Get FPSCR
768
+ \details Returns the current value of the Floating Point Status/Control register.
769
+ \return Floating Point Status/Control register value
770
+ */
771
+ __STATIC_INLINE uint32_t __get_FPSCR(void)
772
+ {
773
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
774
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
775
+ register uint32_t __regfpscr __ASM("fpscr");
776
+ return(__regfpscr);
777
+ #else
778
+ return(0U);
779
+ #endif
780
+ }
781
+
782
+
783
+ /**
784
+ \brief Set FPSCR
785
+ \details Assigns the given value to the Floating Point Status/Control register.
786
+ \param [in] fpscr Floating Point Status/Control value to set
787
+ */
788
+ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
789
+ {
790
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
791
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
792
+ register uint32_t __regfpscr __ASM("fpscr");
793
+ __regfpscr = (fpscr);
794
+ #else
795
+ (void)fpscr;
796
+ #endif
797
+ }
798
+
799
+
800
+ /*@} end of CMSIS_Core_RegAccFunctions */
801
+
802
+
803
+ /* ################### Compiler specific Intrinsics ########################### */
804
+ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
805
+ Access to dedicated SIMD instructions
806
+ @{
807
+ */
808
+
809
+ #if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
810
+
811
+ #define __SADD8 __sadd8
812
+ #define __QADD8 __qadd8
813
+ #define __SHADD8 __shadd8
814
+ #define __UADD8 __uadd8
815
+ #define __UQADD8 __uqadd8
816
+ #define __UHADD8 __uhadd8
817
+ #define __SSUB8 __ssub8
818
+ #define __QSUB8 __qsub8
819
+ #define __SHSUB8 __shsub8
820
+ #define __USUB8 __usub8
821
+ #define __UQSUB8 __uqsub8
822
+ #define __UHSUB8 __uhsub8
823
+ #define __SADD16 __sadd16
824
+ #define __QADD16 __qadd16
825
+ #define __SHADD16 __shadd16
826
+ #define __UADD16 __uadd16
827
+ #define __UQADD16 __uqadd16
828
+ #define __UHADD16 __uhadd16
829
+ #define __SSUB16 __ssub16
830
+ #define __QSUB16 __qsub16
831
+ #define __SHSUB16 __shsub16
832
+ #define __USUB16 __usub16
833
+ #define __UQSUB16 __uqsub16
834
+ #define __UHSUB16 __uhsub16
835
+ #define __SASX __sasx
836
+ #define __QASX __qasx
837
+ #define __SHASX __shasx
838
+ #define __UASX __uasx
839
+ #define __UQASX __uqasx
840
+ #define __UHASX __uhasx
841
+ #define __SSAX __ssax
842
+ #define __QSAX __qsax
843
+ #define __SHSAX __shsax
844
+ #define __USAX __usax
845
+ #define __UQSAX __uqsax
846
+ #define __UHSAX __uhsax
847
+ #define __USAD8 __usad8
848
+ #define __USADA8 __usada8
849
+ #define __SSAT16 __ssat16
850
+ #define __USAT16 __usat16
851
+ #define __UXTB16 __uxtb16
852
+ #define __UXTAB16 __uxtab16
853
+ #define __SXTB16 __sxtb16
854
+ #define __SXTAB16 __sxtab16
855
+ #define __SMUAD __smuad
856
+ #define __SMUADX __smuadx
857
+ #define __SMLAD __smlad
858
+ #define __SMLADX __smladx
859
+ #define __SMLALD __smlald
860
+ #define __SMLALDX __smlaldx
861
+ #define __SMUSD __smusd
862
+ #define __SMUSDX __smusdx
863
+ #define __SMLSD __smlsd
864
+ #define __SMLSDX __smlsdx
865
+ #define __SMLSLD __smlsld
866
+ #define __SMLSLDX __smlsldx
867
+ #define __SEL __sel
868
+ #define __QADD __qadd
869
+ #define __QSUB __qsub
870
+
871
+ #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
872
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
873
+
874
+ #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
875
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
876
+
877
+ #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
878
+ ((int64_t)(ARG3) << 32U) ) >> 32U))
879
+
880
+ #define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
881
+
882
+ #define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
883
+
884
+ #endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
885
+ /*@} end of group CMSIS_SIMD_intrinsics */
886
+
887
+
888
+ #endif /* __CMSIS_ARMCC_H */
edge-impulse-sdk/CMSIS/Core/Include/cmsis_armclang.h ADDED
@@ -0,0 +1,1503 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ /**************************************************************************//**
2
+ * @file cmsis_armclang.h
3
+ * @brief CMSIS compiler armclang (Arm Compiler 6) header file
4
+ * @version V5.4.4
5
+ * @date 30. May 2022
6
+ ******************************************************************************/
7
+ /*
8
+ * Copyright (c) 2009-2022 Arm Limited. All rights reserved.
9
+ *
10
+ * SPDX-License-Identifier: Apache-2.0
11
+ *
12
+ * Licensed under the Apache License, Version 2.0 (the License); you may
13
+ * not use this file except in compliance with the License.
14
+ * You may obtain a copy of the License at
15
+ *
16
+ * www.apache.org/licenses/LICENSE-2.0
17
+ *
18
+ * Unless required by applicable law or agreed to in writing, software
19
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21
+ * See the License for the specific language governing permissions and
22
+ * limitations under the License.
23
+ */
24
+
25
+ /*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
26
+
27
+ #ifndef __CMSIS_ARMCLANG_H
28
+ #define __CMSIS_ARMCLANG_H
29
+
30
+ #pragma clang system_header /* treat file as system include file */
31
+
32
+ /* CMSIS compiler specific defines */
33
+ #ifndef __ASM
34
+ #define __ASM __asm
35
+ #endif
36
+ #ifndef __INLINE
37
+ #define __INLINE __inline
38
+ #endif
39
+ #ifndef __STATIC_INLINE
40
+ #define __STATIC_INLINE static __inline
41
+ #endif
42
+ #ifndef __STATIC_FORCEINLINE
43
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
44
+ #endif
45
+ #ifndef __NO_RETURN
46
+ #define __NO_RETURN __attribute__((__noreturn__))
47
+ #endif
48
+ #ifndef __USED
49
+ #define __USED __attribute__((used))
50
+ #endif
51
+ #ifndef __WEAK
52
+ #define __WEAK __attribute__((weak))
53
+ #endif
54
+ #ifndef __PACKED
55
+ #define __PACKED __attribute__((packed, aligned(1)))
56
+ #endif
57
+ #ifndef __PACKED_STRUCT
58
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
59
+ #endif
60
+ #ifndef __PACKED_UNION
61
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
62
+ #endif
63
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
64
+ #pragma clang diagnostic push
65
+ #pragma clang diagnostic ignored "-Wpacked"
66
+ /*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
67
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
68
+ #pragma clang diagnostic pop
69
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
70
+ #endif
71
+ #ifndef __UNALIGNED_UINT16_WRITE
72
+ #pragma clang diagnostic push
73
+ #pragma clang diagnostic ignored "-Wpacked"
74
+ /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
75
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
76
+ #pragma clang diagnostic pop
77
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
78
+ #endif
79
+ #ifndef __UNALIGNED_UINT16_READ
80
+ #pragma clang diagnostic push
81
+ #pragma clang diagnostic ignored "-Wpacked"
82
+ /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
83
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
84
+ #pragma clang diagnostic pop
85
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
86
+ #endif
87
+ #ifndef __UNALIGNED_UINT32_WRITE
88
+ #pragma clang diagnostic push
89
+ #pragma clang diagnostic ignored "-Wpacked"
90
+ /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
91
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
92
+ #pragma clang diagnostic pop
93
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
94
+ #endif
95
+ #ifndef __UNALIGNED_UINT32_READ
96
+ #pragma clang diagnostic push
97
+ #pragma clang diagnostic ignored "-Wpacked"
98
+ /*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
99
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
100
+ #pragma clang diagnostic pop
101
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
102
+ #endif
103
+ #ifndef __ALIGNED
104
+ #define __ALIGNED(x) __attribute__((aligned(x)))
105
+ #endif
106
+ #ifndef __RESTRICT
107
+ #define __RESTRICT __restrict
108
+ #endif
109
+ #ifndef __COMPILER_BARRIER
110
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
111
+ #endif
112
+
113
+ /* ######################### Startup and Lowlevel Init ######################## */
114
+
115
+ #ifndef __PROGRAM_START
116
+ #define __PROGRAM_START __main
117
+ #endif
118
+
119
+ #ifndef __INITIAL_SP
120
+ #define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
121
+ #endif
122
+
123
+ #ifndef __STACK_LIMIT
124
+ #define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
125
+ #endif
126
+
127
+ #ifndef __VECTOR_TABLE
128
+ #define __VECTOR_TABLE __Vectors
129
+ #endif
130
+
131
+ #ifndef __VECTOR_TABLE_ATTRIBUTE
132
+ #define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
133
+ #endif
134
+
135
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
136
+ #ifndef __STACK_SEAL
137
+ #define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base
138
+ #endif
139
+
140
+ #ifndef __TZ_STACK_SEAL_SIZE
141
+ #define __TZ_STACK_SEAL_SIZE 8U
142
+ #endif
143
+
144
+ #ifndef __TZ_STACK_SEAL_VALUE
145
+ #define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL
146
+ #endif
147
+
148
+
149
+ __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
150
+ *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
151
+ }
152
+ #endif
153
+
154
+
155
+ /* ########################## Core Instruction Access ######################### */
156
+ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
157
+ Access to dedicated instructions
158
+ @{
159
+ */
160
+
161
+ /* Define macros for porting to both thumb1 and thumb2.
162
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
163
+ * Otherwise, use general registers, specified by constraint "r" */
164
+ #if defined (__thumb__) && !defined (__thumb2__)
165
+ #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
166
+ #define __CMSIS_GCC_RW_REG(r) "+l" (r)
167
+ #define __CMSIS_GCC_USE_REG(r) "l" (r)
168
+ #else
169
+ #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
170
+ #define __CMSIS_GCC_RW_REG(r) "+r" (r)
171
+ #define __CMSIS_GCC_USE_REG(r) "r" (r)
172
+ #endif
173
+
174
+ /**
175
+ \brief No Operation
176
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
177
+ */
178
+ #define __NOP __builtin_arm_nop
179
+
180
+ /**
181
+ \brief Wait For Interrupt
182
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
183
+ */
184
+ #define __WFI __builtin_arm_wfi
185
+
186
+
187
+ /**
188
+ \brief Wait For Event
189
+ \details Wait For Event is a hint instruction that permits the processor to enter
190
+ a low-power state until one of a number of events occurs.
191
+ */
192
+ #define __WFE __builtin_arm_wfe
193
+
194
+
195
+ /**
196
+ \brief Send Event
197
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
198
+ */
199
+ #define __SEV __builtin_arm_sev
200
+
201
+
202
+ /**
203
+ \brief Instruction Synchronization Barrier
204
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
205
+ so that all instructions following the ISB are fetched from cache or memory,
206
+ after the instruction has been completed.
207
+ */
208
+ #define __ISB() __builtin_arm_isb(0xF)
209
+
210
+ /**
211
+ \brief Data Synchronization Barrier
212
+ \details Acts as a special kind of Data Memory Barrier.
213
+ It completes when all explicit memory accesses before this instruction complete.
214
+ */
215
+ #define __DSB() __builtin_arm_dsb(0xF)
216
+
217
+
218
+ /**
219
+ \brief Data Memory Barrier
220
+ \details Ensures the apparent order of the explicit memory operations before
221
+ and after the instruction, without ensuring their completion.
222
+ */
223
+ #define __DMB() __builtin_arm_dmb(0xF)
224
+
225
+
226
+ /**
227
+ \brief Reverse byte order (32 bit)
228
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
229
+ \param [in] value Value to reverse
230
+ \return Reversed value
231
+ */
232
+ #define __REV(value) __builtin_bswap32(value)
233
+
234
+
235
+ /**
236
+ \brief Reverse byte order (16 bit)
237
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
238
+ \param [in] value Value to reverse
239
+ \return Reversed value
240
+ */
241
+ #define __REV16(value) __ROR(__REV(value), 16)
242
+
243
+
244
+ /**
245
+ \brief Reverse byte order (16 bit)
246
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
247
+ \param [in] value Value to reverse
248
+ \return Reversed value
249
+ */
250
+ #define __REVSH(value) (int16_t)__builtin_bswap16(value)
251
+
252
+
253
+ /**
254
+ \brief Rotate Right in unsigned value (32 bit)
255
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
256
+ \param [in] op1 Value to rotate
257
+ \param [in] op2 Number of Bits to rotate
258
+ \return Rotated value
259
+ */
260
+ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
261
+ {
262
+ op2 %= 32U;
263
+ if (op2 == 0U)
264
+ {
265
+ return op1;
266
+ }
267
+ return (op1 >> op2) | (op1 << (32U - op2));
268
+ }
269
+
270
+
271
+ /**
272
+ \brief Breakpoint
273
+ \details Causes the processor to enter Debug state.
274
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
275
+ \param [in] value is ignored by the processor.
276
+ If required, a debugger can use it to store additional information about the breakpoint.
277
+ */
278
+ #define __BKPT(value) __ASM volatile ("bkpt "#value)
279
+
280
+
281
+ /**
282
+ \brief Reverse bit order of value
283
+ \details Reverses the bit order of the given value.
284
+ \param [in] value Value to reverse
285
+ \return Reversed value
286
+ */
287
+ #define __RBIT __builtin_arm_rbit
288
+
289
+ /**
290
+ \brief Count leading zeros
291
+ \details Counts the number of leading zeros of a data value.
292
+ \param [in] value Value to count the leading zeros
293
+ \return number of leading zeros in value
294
+ */
295
+ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
296
+ {
297
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
298
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.
299
+ This guarantees ARM-compatible results if happening to compile on a non-ARM
300
+ target, and ensures the compiler doesn't decide to activate any
301
+ optimisations using the logic "value was passed to __builtin_clz, so it
302
+ is non-zero".
303
+ ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
304
+ single CLZ instruction.
305
+ */
306
+ if (value == 0U)
307
+ {
308
+ return 32U;
309
+ }
310
+ return __builtin_clz(value);
311
+ }
312
+
313
+
314
+ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
315
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
316
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
317
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
318
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
319
+
320
+ /**
321
+ \brief LDR Exclusive (8 bit)
322
+ \details Executes a exclusive LDR instruction for 8 bit value.
323
+ \param [in] ptr Pointer to data
324
+ \return value of type uint8_t at (*ptr)
325
+ */
326
+ #define __LDREXB (uint8_t)__builtin_arm_ldrex
327
+
328
+
329
+ /**
330
+ \brief LDR Exclusive (16 bit)
331
+ \details Executes a exclusive LDR instruction for 16 bit values.
332
+ \param [in] ptr Pointer to data
333
+ \return value of type uint16_t at (*ptr)
334
+ */
335
+ #define __LDREXH (uint16_t)__builtin_arm_ldrex
336
+
337
+
338
+ /**
339
+ \brief LDR Exclusive (32 bit)
340
+ \details Executes a exclusive LDR instruction for 32 bit values.
341
+ \param [in] ptr Pointer to data
342
+ \return value of type uint32_t at (*ptr)
343
+ */
344
+ #define __LDREXW (uint32_t)__builtin_arm_ldrex
345
+
346
+
347
+ /**
348
+ \brief STR Exclusive (8 bit)
349
+ \details Executes a exclusive STR instruction for 8 bit values.
350
+ \param [in] value Value to store
351
+ \param [in] ptr Pointer to location
352
+ \return 0 Function succeeded
353
+ \return 1 Function failed
354
+ */
355
+ #define __STREXB (uint32_t)__builtin_arm_strex
356
+
357
+
358
+ /**
359
+ \brief STR Exclusive (16 bit)
360
+ \details Executes a exclusive STR instruction for 16 bit values.
361
+ \param [in] value Value to store
362
+ \param [in] ptr Pointer to location
363
+ \return 0 Function succeeded
364
+ \return 1 Function failed
365
+ */
366
+ #define __STREXH (uint32_t)__builtin_arm_strex
367
+
368
+
369
+ /**
370
+ \brief STR Exclusive (32 bit)
371
+ \details Executes a exclusive STR instruction for 32 bit values.
372
+ \param [in] value Value to store
373
+ \param [in] ptr Pointer to location
374
+ \return 0 Function succeeded
375
+ \return 1 Function failed
376
+ */
377
+ #define __STREXW (uint32_t)__builtin_arm_strex
378
+
379
+
380
+ /**
381
+ \brief Remove the exclusive lock
382
+ \details Removes the exclusive lock which is created by LDREX.
383
+ */
384
+ #define __CLREX __builtin_arm_clrex
385
+
386
+ #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
387
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
388
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
389
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
390
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
391
+
392
+
393
+ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
394
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
395
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
396
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
397
+
398
+ /**
399
+ \brief Signed Saturate
400
+ \details Saturates a signed value.
401
+ \param [in] value Value to be saturated
402
+ \param [in] sat Bit position to saturate to (1..32)
403
+ \return Saturated value
404
+ */
405
+ #define __SSAT __builtin_arm_ssat
406
+
407
+
408
+ /**
409
+ \brief Unsigned Saturate
410
+ \details Saturates an unsigned value.
411
+ \param [in] value Value to be saturated
412
+ \param [in] sat Bit position to saturate to (0..31)
413
+ \return Saturated value
414
+ */
415
+ #define __USAT __builtin_arm_usat
416
+
417
+
418
+ /**
419
+ \brief Rotate Right with Extend (32 bit)
420
+ \details Moves each bit of a bitstring right by one bit.
421
+ The carry input is shifted in at the left end of the bitstring.
422
+ \param [in] value Value to rotate
423
+ \return Rotated value
424
+ */
425
+ __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
426
+ {
427
+ uint32_t result;
428
+
429
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
430
+ return(result);
431
+ }
432
+
433
+
434
+ /**
435
+ \brief LDRT Unprivileged (8 bit)
436
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
437
+ \param [in] ptr Pointer to data
438
+ \return value of type uint8_t at (*ptr)
439
+ */
440
+ __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
441
+ {
442
+ uint32_t result;
443
+
444
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
445
+ return ((uint8_t) result); /* Add explicit type cast here */
446
+ }
447
+
448
+
449
+ /**
450
+ \brief LDRT Unprivileged (16 bit)
451
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
452
+ \param [in] ptr Pointer to data
453
+ \return value of type uint16_t at (*ptr)
454
+ */
455
+ __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
456
+ {
457
+ uint32_t result;
458
+
459
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
460
+ return ((uint16_t) result); /* Add explicit type cast here */
461
+ }
462
+
463
+
464
+ /**
465
+ \brief LDRT Unprivileged (32 bit)
466
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
467
+ \param [in] ptr Pointer to data
468
+ \return value of type uint32_t at (*ptr)
469
+ */
470
+ __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
471
+ {
472
+ uint32_t result;
473
+
474
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
475
+ return(result);
476
+ }
477
+
478
+
479
+ /**
480
+ \brief STRT Unprivileged (8 bit)
481
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
482
+ \param [in] value Value to store
483
+ \param [in] ptr Pointer to location
484
+ */
485
+ __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
486
+ {
487
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
488
+ }
489
+
490
+
491
+ /**
492
+ \brief STRT Unprivileged (16 bit)
493
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
494
+ \param [in] value Value to store
495
+ \param [in] ptr Pointer to location
496
+ */
497
+ __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
498
+ {
499
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
500
+ }
501
+
502
+
503
+ /**
504
+ \brief STRT Unprivileged (32 bit)
505
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
506
+ \param [in] value Value to store
507
+ \param [in] ptr Pointer to location
508
+ */
509
+ __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
510
+ {
511
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
512
+ }
513
+
514
+ #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
515
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
516
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
517
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
518
+
519
+ /**
520
+ \brief Signed Saturate
521
+ \details Saturates a signed value.
522
+ \param [in] value Value to be saturated
523
+ \param [in] sat Bit position to saturate to (1..32)
524
+ \return Saturated value
525
+ */
526
+ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
527
+ {
528
+ if ((sat >= 1U) && (sat <= 32U))
529
+ {
530
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
531
+ const int32_t min = -1 - max ;
532
+ if (val > max)
533
+ {
534
+ return max;
535
+ }
536
+ else if (val < min)
537
+ {
538
+ return min;
539
+ }
540
+ }
541
+ return val;
542
+ }
543
+
544
+ /**
545
+ \brief Unsigned Saturate
546
+ \details Saturates an unsigned value.
547
+ \param [in] value Value to be saturated
548
+ \param [in] sat Bit position to saturate to (0..31)
549
+ \return Saturated value
550
+ */
551
+ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
552
+ {
553
+ if (sat <= 31U)
554
+ {
555
+ const uint32_t max = ((1U << sat) - 1U);
556
+ if (val > (int32_t)max)
557
+ {
558
+ return max;
559
+ }
560
+ else if (val < 0)
561
+ {
562
+ return 0U;
563
+ }
564
+ }
565
+ return (uint32_t)val;
566
+ }
567
+
568
+ #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
569
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
570
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
571
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
572
+
573
+
574
+ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
575
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
576
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
577
+
578
+ /**
579
+ \brief Load-Acquire (8 bit)
580
+ \details Executes a LDAB instruction for 8 bit value.
581
+ \param [in] ptr Pointer to data
582
+ \return value of type uint8_t at (*ptr)
583
+ */
584
+ __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
585
+ {
586
+ uint32_t result;
587
+
588
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
589
+ return ((uint8_t) result);
590
+ }
591
+
592
+
593
+ /**
594
+ \brief Load-Acquire (16 bit)
595
+ \details Executes a LDAH instruction for 16 bit values.
596
+ \param [in] ptr Pointer to data
597
+ \return value of type uint16_t at (*ptr)
598
+ */
599
+ __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
600
+ {
601
+ uint32_t result;
602
+
603
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
604
+ return ((uint16_t) result);
605
+ }
606
+
607
+
608
+ /**
609
+ \brief Load-Acquire (32 bit)
610
+ \details Executes a LDA instruction for 32 bit values.
611
+ \param [in] ptr Pointer to data
612
+ \return value of type uint32_t at (*ptr)
613
+ */
614
+ __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
615
+ {
616
+ uint32_t result;
617
+
618
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
619
+ return(result);
620
+ }
621
+
622
+
623
+ /**
624
+ \brief Store-Release (8 bit)
625
+ \details Executes a STLB instruction for 8 bit values.
626
+ \param [in] value Value to store
627
+ \param [in] ptr Pointer to location
628
+ */
629
+ __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
630
+ {
631
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
632
+ }
633
+
634
+
635
+ /**
636
+ \brief Store-Release (16 bit)
637
+ \details Executes a STLH instruction for 16 bit values.
638
+ \param [in] value Value to store
639
+ \param [in] ptr Pointer to location
640
+ */
641
+ __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
642
+ {
643
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
644
+ }
645
+
646
+
647
+ /**
648
+ \brief Store-Release (32 bit)
649
+ \details Executes a STL instruction for 32 bit values.
650
+ \param [in] value Value to store
651
+ \param [in] ptr Pointer to location
652
+ */
653
+ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
654
+ {
655
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
656
+ }
657
+
658
+
659
+ /**
660
+ \brief Load-Acquire Exclusive (8 bit)
661
+ \details Executes a LDAB exclusive instruction for 8 bit value.
662
+ \param [in] ptr Pointer to data
663
+ \return value of type uint8_t at (*ptr)
664
+ */
665
+ #define __LDAEXB (uint8_t)__builtin_arm_ldaex
666
+
667
+
668
+ /**
669
+ \brief Load-Acquire Exclusive (16 bit)
670
+ \details Executes a LDAH exclusive instruction for 16 bit values.
671
+ \param [in] ptr Pointer to data
672
+ \return value of type uint16_t at (*ptr)
673
+ */
674
+ #define __LDAEXH (uint16_t)__builtin_arm_ldaex
675
+
676
+
677
+ /**
678
+ \brief Load-Acquire Exclusive (32 bit)
679
+ \details Executes a LDA exclusive instruction for 32 bit values.
680
+ \param [in] ptr Pointer to data
681
+ \return value of type uint32_t at (*ptr)
682
+ */
683
+ #define __LDAEX (uint32_t)__builtin_arm_ldaex
684
+
685
+
686
+ /**
687
+ \brief Store-Release Exclusive (8 bit)
688
+ \details Executes a STLB exclusive instruction for 8 bit values.
689
+ \param [in] value Value to store
690
+ \param [in] ptr Pointer to location
691
+ \return 0 Function succeeded
692
+ \return 1 Function failed
693
+ */
694
+ #define __STLEXB (uint32_t)__builtin_arm_stlex
695
+
696
+
697
+ /**
698
+ \brief Store-Release Exclusive (16 bit)
699
+ \details Executes a STLH exclusive instruction for 16 bit values.
700
+ \param [in] value Value to store
701
+ \param [in] ptr Pointer to location
702
+ \return 0 Function succeeded
703
+ \return 1 Function failed
704
+ */
705
+ #define __STLEXH (uint32_t)__builtin_arm_stlex
706
+
707
+
708
+ /**
709
+ \brief Store-Release Exclusive (32 bit)
710
+ \details Executes a STL exclusive instruction for 32 bit values.
711
+ \param [in] value Value to store
712
+ \param [in] ptr Pointer to location
713
+ \return 0 Function succeeded
714
+ \return 1 Function failed
715
+ */
716
+ #define __STLEX (uint32_t)__builtin_arm_stlex
717
+
718
+ #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
719
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
720
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
721
+
722
+ /** @}*/ /* end of group CMSIS_Core_InstructionInterface */
723
+
724
+
725
+ /* ########################### Core Function Access ########################### */
726
+ /** \ingroup CMSIS_Core_FunctionInterface
727
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
728
+ @{
729
+ */
730
+
731
+ /**
732
+ \brief Enable IRQ Interrupts
733
+ \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
734
+ Can only be executed in Privileged modes.
735
+ */
736
+ #ifndef __ARM_COMPAT_H
737
+ __STATIC_FORCEINLINE void __enable_irq(void)
738
+ {
739
+ __ASM volatile ("cpsie i" : : : "memory");
740
+ }
741
+ #endif
742
+
743
+
744
+ /**
745
+ \brief Disable IRQ Interrupts
746
+ \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
747
+ Can only be executed in Privileged modes.
748
+ */
749
+ #ifndef __ARM_COMPAT_H
750
+ __STATIC_FORCEINLINE void __disable_irq(void)
751
+ {
752
+ __ASM volatile ("cpsid i" : : : "memory");
753
+ }
754
+ #endif
755
+
756
+
757
+ /**
758
+ \brief Get Control Register
759
+ \details Returns the content of the Control Register.
760
+ \return Control Register value
761
+ */
762
+ __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
763
+ {
764
+ uint32_t result;
765
+
766
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
767
+ return(result);
768
+ }
769
+
770
+
771
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
772
+ /**
773
+ \brief Get Control Register (non-secure)
774
+ \details Returns the content of the non-secure Control Register when in secure mode.
775
+ \return non-secure Control Register value
776
+ */
777
+ __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
778
+ {
779
+ uint32_t result;
780
+
781
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
782
+ return(result);
783
+ }
784
+ #endif
785
+
786
+
787
+ /**
788
+ \brief Set Control Register
789
+ \details Writes the given value to the Control Register.
790
+ \param [in] control Control Register value to set
791
+ */
792
+ __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
793
+ {
794
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
795
+ __ISB();
796
+ }
797
+
798
+
799
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
800
+ /**
801
+ \brief Set Control Register (non-secure)
802
+ \details Writes the given value to the non-secure Control Register when in secure state.
803
+ \param [in] control Control Register value to set
804
+ */
805
+ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
806
+ {
807
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
808
+ __ISB();
809
+ }
810
+ #endif
811
+
812
+
813
+ /**
814
+ \brief Get IPSR Register
815
+ \details Returns the content of the IPSR Register.
816
+ \return IPSR Register value
817
+ */
818
+ __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
819
+ {
820
+ uint32_t result;
821
+
822
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
823
+ return(result);
824
+ }
825
+
826
+
827
+ /**
828
+ \brief Get APSR Register
829
+ \details Returns the content of the APSR Register.
830
+ \return APSR Register value
831
+ */
832
+ __STATIC_FORCEINLINE uint32_t __get_APSR(void)
833
+ {
834
+ uint32_t result;
835
+
836
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
837
+ return(result);
838
+ }
839
+
840
+
841
+ /**
842
+ \brief Get xPSR Register
843
+ \details Returns the content of the xPSR Register.
844
+ \return xPSR Register value
845
+ */
846
+ __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
847
+ {
848
+ uint32_t result;
849
+
850
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
851
+ return(result);
852
+ }
853
+
854
+
855
+ /**
856
+ \brief Get Process Stack Pointer
857
+ \details Returns the current value of the Process Stack Pointer (PSP).
858
+ \return PSP Register value
859
+ */
860
+ __STATIC_FORCEINLINE uint32_t __get_PSP(void)
861
+ {
862
+ uint32_t result;
863
+
864
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
865
+ return(result);
866
+ }
867
+
868
+
869
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
870
+ /**
871
+ \brief Get Process Stack Pointer (non-secure)
872
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
873
+ \return PSP Register value
874
+ */
875
+ __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
876
+ {
877
+ uint32_t result;
878
+
879
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
880
+ return(result);
881
+ }
882
+ #endif
883
+
884
+
885
+ /**
886
+ \brief Set Process Stack Pointer
887
+ \details Assigns the given value to the Process Stack Pointer (PSP).
888
+ \param [in] topOfProcStack Process Stack Pointer value to set
889
+ */
890
+ __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
891
+ {
892
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
893
+ }
894
+
895
+
896
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
897
+ /**
898
+ \brief Set Process Stack Pointer (non-secure)
899
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
900
+ \param [in] topOfProcStack Process Stack Pointer value to set
901
+ */
902
+ __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
903
+ {
904
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
905
+ }
906
+ #endif
907
+
908
+
909
+ /**
910
+ \brief Get Main Stack Pointer
911
+ \details Returns the current value of the Main Stack Pointer (MSP).
912
+ \return MSP Register value
913
+ */
914
+ __STATIC_FORCEINLINE uint32_t __get_MSP(void)
915
+ {
916
+ uint32_t result;
917
+
918
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
919
+ return(result);
920
+ }
921
+
922
+
923
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
924
+ /**
925
+ \brief Get Main Stack Pointer (non-secure)
926
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
927
+ \return MSP Register value
928
+ */
929
+ __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
930
+ {
931
+ uint32_t result;
932
+
933
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
934
+ return(result);
935
+ }
936
+ #endif
937
+
938
+
939
+ /**
940
+ \brief Set Main Stack Pointer
941
+ \details Assigns the given value to the Main Stack Pointer (MSP).
942
+ \param [in] topOfMainStack Main Stack Pointer value to set
943
+ */
944
+ __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
945
+ {
946
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
947
+ }
948
+
949
+
950
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
951
+ /**
952
+ \brief Set Main Stack Pointer (non-secure)
953
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
954
+ \param [in] topOfMainStack Main Stack Pointer value to set
955
+ */
956
+ __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
957
+ {
958
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
959
+ }
960
+ #endif
961
+
962
+
963
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
964
+ /**
965
+ \brief Get Stack Pointer (non-secure)
966
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
967
+ \return SP Register value
968
+ */
969
+ __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
970
+ {
971
+ uint32_t result;
972
+
973
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
974
+ return(result);
975
+ }
976
+
977
+
978
+ /**
979
+ \brief Set Stack Pointer (non-secure)
980
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
981
+ \param [in] topOfStack Stack Pointer value to set
982
+ */
983
+ __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
984
+ {
985
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
986
+ }
987
+ #endif
988
+
989
+
990
+ /**
991
+ \brief Get Priority Mask
992
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
993
+ \return Priority Mask value
994
+ */
995
+ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
996
+ {
997
+ uint32_t result;
998
+
999
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
1000
+ return(result);
1001
+ }
1002
+
1003
+
1004
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1005
+ /**
1006
+ \brief Get Priority Mask (non-secure)
1007
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
1008
+ \return Priority Mask value
1009
+ */
1010
+ __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
1011
+ {
1012
+ uint32_t result;
1013
+
1014
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
1015
+ return(result);
1016
+ }
1017
+ #endif
1018
+
1019
+
1020
+ /**
1021
+ \brief Set Priority Mask
1022
+ \details Assigns the given value to the Priority Mask Register.
1023
+ \param [in] priMask Priority Mask
1024
+ */
1025
+ __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
1026
+ {
1027
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
1028
+ }
1029
+
1030
+
1031
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1032
+ /**
1033
+ \brief Set Priority Mask (non-secure)
1034
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
1035
+ \param [in] priMask Priority Mask
1036
+ */
1037
+ __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
1038
+ {
1039
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
1040
+ }
1041
+ #endif
1042
+
1043
+
1044
+ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
1045
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
1046
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1047
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
1048
+ /**
1049
+ \brief Enable FIQ
1050
+ \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
1051
+ Can only be executed in Privileged modes.
1052
+ */
1053
+ __STATIC_FORCEINLINE void __enable_fault_irq(void)
1054
+ {
1055
+ __ASM volatile ("cpsie f" : : : "memory");
1056
+ }
1057
+
1058
+
1059
+ /**
1060
+ \brief Disable FIQ
1061
+ \details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
1062
+ Can only be executed in Privileged modes.
1063
+ */
1064
+ __STATIC_FORCEINLINE void __disable_fault_irq(void)
1065
+ {
1066
+ __ASM volatile ("cpsid f" : : : "memory");
1067
+ }
1068
+
1069
+
1070
+ /**
1071
+ \brief Get Base Priority
1072
+ \details Returns the current value of the Base Priority register.
1073
+ \return Base Priority register value
1074
+ */
1075
+ __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
1076
+ {
1077
+ uint32_t result;
1078
+
1079
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
1080
+ return(result);
1081
+ }
1082
+
1083
+
1084
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1085
+ /**
1086
+ \brief Get Base Priority (non-secure)
1087
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
1088
+ \return Base Priority register value
1089
+ */
1090
+ __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
1091
+ {
1092
+ uint32_t result;
1093
+
1094
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
1095
+ return(result);
1096
+ }
1097
+ #endif
1098
+
1099
+
1100
+ /**
1101
+ \brief Set Base Priority
1102
+ \details Assigns the given value to the Base Priority register.
1103
+ \param [in] basePri Base Priority value to set
1104
+ */
1105
+ __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
1106
+ {
1107
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
1108
+ }
1109
+
1110
+
1111
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1112
+ /**
1113
+ \brief Set Base Priority (non-secure)
1114
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
1115
+ \param [in] basePri Base Priority value to set
1116
+ */
1117
+ __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
1118
+ {
1119
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
1120
+ }
1121
+ #endif
1122
+
1123
+
1124
+ /**
1125
+ \brief Set Base Priority with condition
1126
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
1127
+ or the new value increases the BASEPRI priority level.
1128
+ \param [in] basePri Base Priority value to set
1129
+ */
1130
+ __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
1131
+ {
1132
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
1133
+ }
1134
+
1135
+
1136
+ /**
1137
+ \brief Get Fault Mask
1138
+ \details Returns the current value of the Fault Mask register.
1139
+ \return Fault Mask register value
1140
+ */
1141
+ __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
1142
+ {
1143
+ uint32_t result;
1144
+
1145
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
1146
+ return(result);
1147
+ }
1148
+
1149
+
1150
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1151
+ /**
1152
+ \brief Get Fault Mask (non-secure)
1153
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
1154
+ \return Fault Mask register value
1155
+ */
1156
+ __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
1157
+ {
1158
+ uint32_t result;
1159
+
1160
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
1161
+ return(result);
1162
+ }
1163
+ #endif
1164
+
1165
+
1166
+ /**
1167
+ \brief Set Fault Mask
1168
+ \details Assigns the given value to the Fault Mask register.
1169
+ \param [in] faultMask Fault Mask value to set
1170
+ */
1171
+ __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
1172
+ {
1173
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
1174
+ }
1175
+
1176
+
1177
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1178
+ /**
1179
+ \brief Set Fault Mask (non-secure)
1180
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
1181
+ \param [in] faultMask Fault Mask value to set
1182
+ */
1183
+ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
1184
+ {
1185
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
1186
+ }
1187
+ #endif
1188
+
1189
+ #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
1190
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
1191
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1192
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
1193
+
1194
+
1195
+ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1196
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
1197
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
1198
+
1199
+ /**
1200
+ \brief Get Process Stack Pointer Limit
1201
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1202
+ Stack Pointer Limit register hence zero is returned always in non-secure
1203
+ mode.
1204
+
1205
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
1206
+ \return PSPLIM Register value
1207
+ */
1208
+ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
1209
+ {
1210
+ #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1211
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
1212
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
1213
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
1214
+ return 0U;
1215
+ #else
1216
+ uint32_t result;
1217
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
1218
+ return result;
1219
+ #endif
1220
+ }
1221
+
1222
+ #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
1223
+ /**
1224
+ \brief Get Process Stack Pointer Limit (non-secure)
1225
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1226
+ Stack Pointer Limit register hence zero is returned always in non-secure
1227
+ mode.
1228
+
1229
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
1230
+ \return PSPLIM Register value
1231
+ */
1232
+ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
1233
+ {
1234
+ #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1235
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
1236
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
1237
+ return 0U;
1238
+ #else
1239
+ uint32_t result;
1240
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
1241
+ return result;
1242
+ #endif
1243
+ }
1244
+ #endif
1245
+
1246
+
1247
+ /**
1248
+ \brief Set Process Stack Pointer Limit
1249
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1250
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
1251
+ mode.
1252
+
1253
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
1254
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
1255
+ */
1256
+ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
1257
+ {
1258
+ #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1259
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
1260
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
1261
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
1262
+ (void)ProcStackPtrLimit;
1263
+ #else
1264
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
1265
+ #endif
1266
+ }
1267
+
1268
+
1269
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1270
+ /**
1271
+ \brief Set Process Stack Pointer (non-secure)
1272
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1273
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
1274
+ mode.
1275
+
1276
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
1277
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
1278
+ */
1279
+ __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
1280
+ {
1281
+ #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1282
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
1283
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
1284
+ (void)ProcStackPtrLimit;
1285
+ #else
1286
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
1287
+ #endif
1288
+ }
1289
+ #endif
1290
+
1291
+
1292
+ /**
1293
+ \brief Get Main Stack Pointer Limit
1294
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1295
+ Stack Pointer Limit register hence zero is returned always.
1296
+
1297
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
1298
+ \return MSPLIM Register value
1299
+ */
1300
+ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
1301
+ {
1302
+ #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1303
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
1304
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
1305
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
1306
+ return 0U;
1307
+ #else
1308
+ uint32_t result;
1309
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
1310
+ return result;
1311
+ #endif
1312
+ }
1313
+
1314
+
1315
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1316
+ /**
1317
+ \brief Get Main Stack Pointer Limit (non-secure)
1318
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1319
+ Stack Pointer Limit register hence zero is returned always.
1320
+
1321
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
1322
+ \return MSPLIM Register value
1323
+ */
1324
+ __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
1325
+ {
1326
+ #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1327
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
1328
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
1329
+ return 0U;
1330
+ #else
1331
+ uint32_t result;
1332
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
1333
+ return result;
1334
+ #endif
1335
+ }
1336
+ #endif
1337
+
1338
+
1339
+ /**
1340
+ \brief Set Main Stack Pointer Limit
1341
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1342
+ Stack Pointer Limit register hence the write is silently ignored.
1343
+
1344
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
1345
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
1346
+ */
1347
+ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
1348
+ {
1349
+ #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1350
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
1351
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
1352
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
1353
+ (void)MainStackPtrLimit;
1354
+ #else
1355
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
1356
+ #endif
1357
+ }
1358
+
1359
+
1360
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1361
+ /**
1362
+ \brief Set Main Stack Pointer Limit (non-secure)
1363
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1364
+ Stack Pointer Limit register hence the write is silently ignored.
1365
+
1366
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
1367
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
1368
+ */
1369
+ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
1370
+ {
1371
+ #if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1372
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
1373
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
1374
+ (void)MainStackPtrLimit;
1375
+ #else
1376
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
1377
+ #endif
1378
+ }
1379
+ #endif
1380
+
1381
+ #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1382
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
1383
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
1384
+
1385
+ /**
1386
+ \brief Get FPSCR
1387
+ \details Returns the current value of the Floating Point Status/Control register.
1388
+ \return Floating Point Status/Control register value
1389
+ */
1390
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
1391
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
1392
+ #define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
1393
+ #else
1394
+ #define __get_FPSCR() ((uint32_t)0U)
1395
+ #endif
1396
+
1397
+ /**
1398
+ \brief Set FPSCR
1399
+ \details Assigns the given value to the Floating Point Status/Control register.
1400
+ \param [in] fpscr Floating Point Status/Control value to set
1401
+ */
1402
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
1403
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
1404
+ #define __set_FPSCR __builtin_arm_set_fpscr
1405
+ #else
1406
+ #define __set_FPSCR(fpscr) ((void)(fpscr))
1407
+ #endif
1408
+
1409
+
1410
+ /** @} end of CMSIS_Core_RegAccFunctions */
1411
+
1412
+
1413
+ /* ################### Compiler specific Intrinsics ########################### */
1414
+ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
1415
+ Access to dedicated SIMD instructions
1416
+ @{
1417
+ */
1418
+
1419
+ #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
1420
+
1421
+ #define __SADD8 __builtin_arm_sadd8
1422
+ #define __QADD8 __builtin_arm_qadd8
1423
+ #define __SHADD8 __builtin_arm_shadd8
1424
+ #define __UADD8 __builtin_arm_uadd8
1425
+ #define __UQADD8 __builtin_arm_uqadd8
1426
+ #define __UHADD8 __builtin_arm_uhadd8
1427
+ #define __SSUB8 __builtin_arm_ssub8
1428
+ #define __QSUB8 __builtin_arm_qsub8
1429
+ #define __SHSUB8 __builtin_arm_shsub8
1430
+ #define __USUB8 __builtin_arm_usub8
1431
+ #define __UQSUB8 __builtin_arm_uqsub8
1432
+ #define __UHSUB8 __builtin_arm_uhsub8
1433
+ #define __SADD16 __builtin_arm_sadd16
1434
+ #define __QADD16 __builtin_arm_qadd16
1435
+ #define __SHADD16 __builtin_arm_shadd16
1436
+ #define __UADD16 __builtin_arm_uadd16
1437
+ #define __UQADD16 __builtin_arm_uqadd16
1438
+ #define __UHADD16 __builtin_arm_uhadd16
1439
+ #define __SSUB16 __builtin_arm_ssub16
1440
+ #define __QSUB16 __builtin_arm_qsub16
1441
+ #define __SHSUB16 __builtin_arm_shsub16
1442
+ #define __USUB16 __builtin_arm_usub16
1443
+ #define __UQSUB16 __builtin_arm_uqsub16
1444
+ #define __UHSUB16 __builtin_arm_uhsub16
1445
+ #define __SASX __builtin_arm_sasx
1446
+ #define __QASX __builtin_arm_qasx
1447
+ #define __SHASX __builtin_arm_shasx
1448
+ #define __UASX __builtin_arm_uasx
1449
+ #define __UQASX __builtin_arm_uqasx
1450
+ #define __UHASX __builtin_arm_uhasx
1451
+ #define __SSAX __builtin_arm_ssax
1452
+ #define __QSAX __builtin_arm_qsax
1453
+ #define __SHSAX __builtin_arm_shsax
1454
+ #define __USAX __builtin_arm_usax
1455
+ #define __UQSAX __builtin_arm_uqsax
1456
+ #define __UHSAX __builtin_arm_uhsax
1457
+ #define __USAD8 __builtin_arm_usad8
1458
+ #define __USADA8 __builtin_arm_usada8
1459
+ #define __SSAT16 __builtin_arm_ssat16
1460
+ #define __USAT16 __builtin_arm_usat16
1461
+ #define __UXTB16 __builtin_arm_uxtb16
1462
+ #define __UXTAB16 __builtin_arm_uxtab16
1463
+ #define __SXTB16 __builtin_arm_sxtb16
1464
+ #define __SXTAB16 __builtin_arm_sxtab16
1465
+ #define __SMUAD __builtin_arm_smuad
1466
+ #define __SMUADX __builtin_arm_smuadx
1467
+ #define __SMLAD __builtin_arm_smlad
1468
+ #define __SMLADX __builtin_arm_smladx
1469
+ #define __SMLALD __builtin_arm_smlald
1470
+ #define __SMLALDX __builtin_arm_smlaldx
1471
+ #define __SMUSD __builtin_arm_smusd
1472
+ #define __SMUSDX __builtin_arm_smusdx
1473
+ #define __SMLSD __builtin_arm_smlsd
1474
+ #define __SMLSDX __builtin_arm_smlsdx
1475
+ #define __SMLSLD __builtin_arm_smlsld
1476
+ #define __SMLSLDX __builtin_arm_smlsldx
1477
+ #define __SEL __builtin_arm_sel
1478
+ #define __QADD __builtin_arm_qadd
1479
+ #define __QSUB __builtin_arm_qsub
1480
+
1481
+ #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
1482
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
1483
+
1484
+ #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
1485
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
1486
+
1487
+ #define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
1488
+
1489
+ #define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
1490
+
1491
+ __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
1492
+ {
1493
+ int32_t result;
1494
+
1495
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
1496
+ return(result);
1497
+ }
1498
+
1499
+ #endif /* (__ARM_FEATURE_DSP == 1) */
1500
+ /** @} end of group CMSIS_SIMD_intrinsics */
1501
+
1502
+
1503
+ #endif /* __CMSIS_ARMCLANG_H */
edge-impulse-sdk/CMSIS/Core/Include/cmsis_armclang_ltm.h ADDED
@@ -0,0 +1,1928 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ /**************************************************************************//**
2
+ * @file cmsis_armclang_ltm.h
3
+ * @brief CMSIS compiler armclang (Arm Compiler 6) header file
4
+ * @version V1.5.3
5
+ * @date 27. May 2021
6
+ ******************************************************************************/
7
+ /*
8
+ * Copyright (c) 2018-2021 Arm Limited. All rights reserved.
9
+ *
10
+ * SPDX-License-Identifier: Apache-2.0
11
+ *
12
+ * Licensed under the Apache License, Version 2.0 (the License); you may
13
+ * not use this file except in compliance with the License.
14
+ * You may obtain a copy of the License at
15
+ *
16
+ * www.apache.org/licenses/LICENSE-2.0
17
+ *
18
+ * Unless required by applicable law or agreed to in writing, software
19
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21
+ * See the License for the specific language governing permissions and
22
+ * limitations under the License.
23
+ */
24
+
25
+ /*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
26
+
27
+ #ifndef __CMSIS_ARMCLANG_H
28
+ #define __CMSIS_ARMCLANG_H
29
+
30
+ #pragma clang system_header /* treat file as system include file */
31
+
32
+ /* CMSIS compiler specific defines */
33
+ #ifndef __ASM
34
+ #define __ASM __asm
35
+ #endif
36
+ #ifndef __INLINE
37
+ #define __INLINE __inline
38
+ #endif
39
+ #ifndef __STATIC_INLINE
40
+ #define __STATIC_INLINE static __inline
41
+ #endif
42
+ #ifndef __STATIC_FORCEINLINE
43
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
44
+ #endif
45
+ #ifndef __NO_RETURN
46
+ #define __NO_RETURN __attribute__((__noreturn__))
47
+ #endif
48
+ #ifndef __USED
49
+ #define __USED __attribute__((used))
50
+ #endif
51
+ #ifndef __WEAK
52
+ #define __WEAK __attribute__((weak))
53
+ #endif
54
+ #ifndef __PACKED
55
+ #define __PACKED __attribute__((packed, aligned(1)))
56
+ #endif
57
+ #ifndef __PACKED_STRUCT
58
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
59
+ #endif
60
+ #ifndef __PACKED_UNION
61
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
62
+ #endif
63
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
64
+ #pragma clang diagnostic push
65
+ #pragma clang diagnostic ignored "-Wpacked"
66
+ /*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
67
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
68
+ #pragma clang diagnostic pop
69
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
70
+ #endif
71
+ #ifndef __UNALIGNED_UINT16_WRITE
72
+ #pragma clang diagnostic push
73
+ #pragma clang diagnostic ignored "-Wpacked"
74
+ /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
75
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
76
+ #pragma clang diagnostic pop
77
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
78
+ #endif
79
+ #ifndef __UNALIGNED_UINT16_READ
80
+ #pragma clang diagnostic push
81
+ #pragma clang diagnostic ignored "-Wpacked"
82
+ /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
83
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
84
+ #pragma clang diagnostic pop
85
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
86
+ #endif
87
+ #ifndef __UNALIGNED_UINT32_WRITE
88
+ #pragma clang diagnostic push
89
+ #pragma clang diagnostic ignored "-Wpacked"
90
+ /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
91
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
92
+ #pragma clang diagnostic pop
93
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
94
+ #endif
95
+ #ifndef __UNALIGNED_UINT32_READ
96
+ #pragma clang diagnostic push
97
+ #pragma clang diagnostic ignored "-Wpacked"
98
+ /*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
99
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
100
+ #pragma clang diagnostic pop
101
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
102
+ #endif
103
+ #ifndef __ALIGNED
104
+ #define __ALIGNED(x) __attribute__((aligned(x)))
105
+ #endif
106
+ #ifndef __RESTRICT
107
+ #define __RESTRICT __restrict
108
+ #endif
109
+ #ifndef __COMPILER_BARRIER
110
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
111
+ #endif
112
+
113
+ /* ######################### Startup and Lowlevel Init ######################## */
114
+
115
+ #ifndef __PROGRAM_START
116
+ #define __PROGRAM_START __main
117
+ #endif
118
+
119
+ #ifndef __INITIAL_SP
120
+ #define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
121
+ #endif
122
+
123
+ #ifndef __STACK_LIMIT
124
+ #define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
125
+ #endif
126
+
127
+ #ifndef __VECTOR_TABLE
128
+ #define __VECTOR_TABLE __Vectors
129
+ #endif
130
+
131
+ #ifndef __VECTOR_TABLE_ATTRIBUTE
132
+ #define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
133
+ #endif
134
+
135
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
136
+ #ifndef __STACK_SEAL
137
+ #define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base
138
+ #endif
139
+
140
+ #ifndef __TZ_STACK_SEAL_SIZE
141
+ #define __TZ_STACK_SEAL_SIZE 8U
142
+ #endif
143
+
144
+ #ifndef __TZ_STACK_SEAL_VALUE
145
+ #define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL
146
+ #endif
147
+
148
+
149
+ __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
150
+ *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
151
+ }
152
+ #endif
153
+
154
+
155
+ /* ########################## Core Instruction Access ######################### */
156
+ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
157
+ Access to dedicated instructions
158
+ @{
159
+ */
160
+
161
+ /* Define macros for porting to both thumb1 and thumb2.
162
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
163
+ * Otherwise, use general registers, specified by constraint "r" */
164
+ #if defined (__thumb__) && !defined (__thumb2__)
165
+ #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
166
+ #define __CMSIS_GCC_USE_REG(r) "l" (r)
167
+ #else
168
+ #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
169
+ #define __CMSIS_GCC_USE_REG(r) "r" (r)
170
+ #endif
171
+
172
+ /**
173
+ \brief No Operation
174
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
175
+ */
176
+ #define __NOP __builtin_arm_nop
177
+
178
+ /**
179
+ \brief Wait For Interrupt
180
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
181
+ */
182
+ #define __WFI __builtin_arm_wfi
183
+
184
+
185
+ /**
186
+ \brief Wait For Event
187
+ \details Wait For Event is a hint instruction that permits the processor to enter
188
+ a low-power state until one of a number of events occurs.
189
+ */
190
+ #define __WFE __builtin_arm_wfe
191
+
192
+
193
+ /**
194
+ \brief Send Event
195
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
196
+ */
197
+ #define __SEV __builtin_arm_sev
198
+
199
+
200
+ /**
201
+ \brief Instruction Synchronization Barrier
202
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
203
+ so that all instructions following the ISB are fetched from cache or memory,
204
+ after the instruction has been completed.
205
+ */
206
+ #define __ISB() __builtin_arm_isb(0xF)
207
+
208
+ /**
209
+ \brief Data Synchronization Barrier
210
+ \details Acts as a special kind of Data Memory Barrier.
211
+ It completes when all explicit memory accesses before this instruction complete.
212
+ */
213
+ #define __DSB() __builtin_arm_dsb(0xF)
214
+
215
+
216
+ /**
217
+ \brief Data Memory Barrier
218
+ \details Ensures the apparent order of the explicit memory operations before
219
+ and after the instruction, without ensuring their completion.
220
+ */
221
+ #define __DMB() __builtin_arm_dmb(0xF)
222
+
223
+
224
+ /**
225
+ \brief Reverse byte order (32 bit)
226
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
227
+ \param [in] value Value to reverse
228
+ \return Reversed value
229
+ */
230
+ #define __REV(value) __builtin_bswap32(value)
231
+
232
+
233
+ /**
234
+ \brief Reverse byte order (16 bit)
235
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
236
+ \param [in] value Value to reverse
237
+ \return Reversed value
238
+ */
239
+ #define __REV16(value) __ROR(__REV(value), 16)
240
+
241
+
242
+ /**
243
+ \brief Reverse byte order (16 bit)
244
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
245
+ \param [in] value Value to reverse
246
+ \return Reversed value
247
+ */
248
+ #define __REVSH(value) (int16_t)__builtin_bswap16(value)
249
+
250
+
251
+ /**
252
+ \brief Rotate Right in unsigned value (32 bit)
253
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
254
+ \param [in] op1 Value to rotate
255
+ \param [in] op2 Number of Bits to rotate
256
+ \return Rotated value
257
+ */
258
+ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
259
+ {
260
+ op2 %= 32U;
261
+ if (op2 == 0U)
262
+ {
263
+ return op1;
264
+ }
265
+ return (op1 >> op2) | (op1 << (32U - op2));
266
+ }
267
+
268
+
269
+ /**
270
+ \brief Breakpoint
271
+ \details Causes the processor to enter Debug state.
272
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
273
+ \param [in] value is ignored by the processor.
274
+ If required, a debugger can use it to store additional information about the breakpoint.
275
+ */
276
+ #define __BKPT(value) __ASM volatile ("bkpt "#value)
277
+
278
+
279
+ /**
280
+ \brief Reverse bit order of value
281
+ \details Reverses the bit order of the given value.
282
+ \param [in] value Value to reverse
283
+ \return Reversed value
284
+ */
285
+ #define __RBIT __builtin_arm_rbit
286
+
287
+ /**
288
+ \brief Count leading zeros
289
+ \details Counts the number of leading zeros of a data value.
290
+ \param [in] value Value to count the leading zeros
291
+ \return number of leading zeros in value
292
+ */
293
+ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
294
+ {
295
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
296
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.
297
+ This guarantees ARM-compatible results if happening to compile on a non-ARM
298
+ target, and ensures the compiler doesn't decide to activate any
299
+ optimisations using the logic "value was passed to __builtin_clz, so it
300
+ is non-zero".
301
+ ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
302
+ single CLZ instruction.
303
+ */
304
+ if (value == 0U)
305
+ {
306
+ return 32U;
307
+ }
308
+ return __builtin_clz(value);
309
+ }
310
+
311
+
312
+ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
313
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
314
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
315
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
316
+ /**
317
+ \brief LDR Exclusive (8 bit)
318
+ \details Executes a exclusive LDR instruction for 8 bit value.
319
+ \param [in] ptr Pointer to data
320
+ \return value of type uint8_t at (*ptr)
321
+ */
322
+ #define __LDREXB (uint8_t)__builtin_arm_ldrex
323
+
324
+
325
+ /**
326
+ \brief LDR Exclusive (16 bit)
327
+ \details Executes a exclusive LDR instruction for 16 bit values.
328
+ \param [in] ptr Pointer to data
329
+ \return value of type uint16_t at (*ptr)
330
+ */
331
+ #define __LDREXH (uint16_t)__builtin_arm_ldrex
332
+
333
+
334
+ /**
335
+ \brief LDR Exclusive (32 bit)
336
+ \details Executes a exclusive LDR instruction for 32 bit values.
337
+ \param [in] ptr Pointer to data
338
+ \return value of type uint32_t at (*ptr)
339
+ */
340
+ #define __LDREXW (uint32_t)__builtin_arm_ldrex
341
+
342
+
343
+ /**
344
+ \brief STR Exclusive (8 bit)
345
+ \details Executes a exclusive STR instruction for 8 bit values.
346
+ \param [in] value Value to store
347
+ \param [in] ptr Pointer to location
348
+ \return 0 Function succeeded
349
+ \return 1 Function failed
350
+ */
351
+ #define __STREXB (uint32_t)__builtin_arm_strex
352
+
353
+
354
+ /**
355
+ \brief STR Exclusive (16 bit)
356
+ \details Executes a exclusive STR instruction for 16 bit values.
357
+ \param [in] value Value to store
358
+ \param [in] ptr Pointer to location
359
+ \return 0 Function succeeded
360
+ \return 1 Function failed
361
+ */
362
+ #define __STREXH (uint32_t)__builtin_arm_strex
363
+
364
+
365
+ /**
366
+ \brief STR Exclusive (32 bit)
367
+ \details Executes a exclusive STR instruction for 32 bit values.
368
+ \param [in] value Value to store
369
+ \param [in] ptr Pointer to location
370
+ \return 0 Function succeeded
371
+ \return 1 Function failed
372
+ */
373
+ #define __STREXW (uint32_t)__builtin_arm_strex
374
+
375
+
376
+ /**
377
+ \brief Remove the exclusive lock
378
+ \details Removes the exclusive lock which is created by LDREX.
379
+ */
380
+ #define __CLREX __builtin_arm_clrex
381
+
382
+ #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
383
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
384
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
385
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
386
+
387
+
388
+ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
389
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
390
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
391
+
392
+ /**
393
+ \brief Signed Saturate
394
+ \details Saturates a signed value.
395
+ \param [in] value Value to be saturated
396
+ \param [in] sat Bit position to saturate to (1..32)
397
+ \return Saturated value
398
+ */
399
+ #define __SSAT __builtin_arm_ssat
400
+
401
+
402
+ /**
403
+ \brief Unsigned Saturate
404
+ \details Saturates an unsigned value.
405
+ \param [in] value Value to be saturated
406
+ \param [in] sat Bit position to saturate to (0..31)
407
+ \return Saturated value
408
+ */
409
+ #define __USAT __builtin_arm_usat
410
+
411
+
412
+ /**
413
+ \brief Rotate Right with Extend (32 bit)
414
+ \details Moves each bit of a bitstring right by one bit.
415
+ The carry input is shifted in at the left end of the bitstring.
416
+ \param [in] value Value to rotate
417
+ \return Rotated value
418
+ */
419
+ __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
420
+ {
421
+ uint32_t result;
422
+
423
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
424
+ return(result);
425
+ }
426
+
427
+
428
+ /**
429
+ \brief LDRT Unprivileged (8 bit)
430
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
431
+ \param [in] ptr Pointer to data
432
+ \return value of type uint8_t at (*ptr)
433
+ */
434
+ __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
435
+ {
436
+ uint32_t result;
437
+
438
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
439
+ return ((uint8_t) result); /* Add explicit type cast here */
440
+ }
441
+
442
+
443
+ /**
444
+ \brief LDRT Unprivileged (16 bit)
445
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
446
+ \param [in] ptr Pointer to data
447
+ \return value of type uint16_t at (*ptr)
448
+ */
449
+ __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
450
+ {
451
+ uint32_t result;
452
+
453
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
454
+ return ((uint16_t) result); /* Add explicit type cast here */
455
+ }
456
+
457
+
458
+ /**
459
+ \brief LDRT Unprivileged (32 bit)
460
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
461
+ \param [in] ptr Pointer to data
462
+ \return value of type uint32_t at (*ptr)
463
+ */
464
+ __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
465
+ {
466
+ uint32_t result;
467
+
468
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
469
+ return(result);
470
+ }
471
+
472
+
473
+ /**
474
+ \brief STRT Unprivileged (8 bit)
475
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
476
+ \param [in] value Value to store
477
+ \param [in] ptr Pointer to location
478
+ */
479
+ __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
480
+ {
481
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
482
+ }
483
+
484
+
485
+ /**
486
+ \brief STRT Unprivileged (16 bit)
487
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
488
+ \param [in] value Value to store
489
+ \param [in] ptr Pointer to location
490
+ */
491
+ __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
492
+ {
493
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
494
+ }
495
+
496
+
497
+ /**
498
+ \brief STRT Unprivileged (32 bit)
499
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
500
+ \param [in] value Value to store
501
+ \param [in] ptr Pointer to location
502
+ */
503
+ __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
504
+ {
505
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
506
+ }
507
+
508
+ #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
509
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
510
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
511
+
512
+ /**
513
+ \brief Signed Saturate
514
+ \details Saturates a signed value.
515
+ \param [in] value Value to be saturated
516
+ \param [in] sat Bit position to saturate to (1..32)
517
+ \return Saturated value
518
+ */
519
+ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
520
+ {
521
+ if ((sat >= 1U) && (sat <= 32U))
522
+ {
523
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
524
+ const int32_t min = -1 - max ;
525
+ if (val > max)
526
+ {
527
+ return max;
528
+ }
529
+ else if (val < min)
530
+ {
531
+ return min;
532
+ }
533
+ }
534
+ return val;
535
+ }
536
+
537
+ /**
538
+ \brief Unsigned Saturate
539
+ \details Saturates an unsigned value.
540
+ \param [in] value Value to be saturated
541
+ \param [in] sat Bit position to saturate to (0..31)
542
+ \return Saturated value
543
+ */
544
+ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
545
+ {
546
+ if (sat <= 31U)
547
+ {
548
+ const uint32_t max = ((1U << sat) - 1U);
549
+ if (val > (int32_t)max)
550
+ {
551
+ return max;
552
+ }
553
+ else if (val < 0)
554
+ {
555
+ return 0U;
556
+ }
557
+ }
558
+ return (uint32_t)val;
559
+ }
560
+
561
+ #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
562
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
563
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
564
+
565
+
566
+ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
567
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
568
+ /**
569
+ \brief Load-Acquire (8 bit)
570
+ \details Executes a LDAB instruction for 8 bit value.
571
+ \param [in] ptr Pointer to data
572
+ \return value of type uint8_t at (*ptr)
573
+ */
574
+ __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
575
+ {
576
+ uint32_t result;
577
+
578
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
579
+ return ((uint8_t) result);
580
+ }
581
+
582
+
583
+ /**
584
+ \brief Load-Acquire (16 bit)
585
+ \details Executes a LDAH instruction for 16 bit values.
586
+ \param [in] ptr Pointer to data
587
+ \return value of type uint16_t at (*ptr)
588
+ */
589
+ __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
590
+ {
591
+ uint32_t result;
592
+
593
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
594
+ return ((uint16_t) result);
595
+ }
596
+
597
+
598
+ /**
599
+ \brief Load-Acquire (32 bit)
600
+ \details Executes a LDA instruction for 32 bit values.
601
+ \param [in] ptr Pointer to data
602
+ \return value of type uint32_t at (*ptr)
603
+ */
604
+ __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
605
+ {
606
+ uint32_t result;
607
+
608
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
609
+ return(result);
610
+ }
611
+
612
+
613
+ /**
614
+ \brief Store-Release (8 bit)
615
+ \details Executes a STLB instruction for 8 bit values.
616
+ \param [in] value Value to store
617
+ \param [in] ptr Pointer to location
618
+ */
619
+ __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
620
+ {
621
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
622
+ }
623
+
624
+
625
+ /**
626
+ \brief Store-Release (16 bit)
627
+ \details Executes a STLH instruction for 16 bit values.
628
+ \param [in] value Value to store
629
+ \param [in] ptr Pointer to location
630
+ */
631
+ __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
632
+ {
633
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
634
+ }
635
+
636
+
637
+ /**
638
+ \brief Store-Release (32 bit)
639
+ \details Executes a STL instruction for 32 bit values.
640
+ \param [in] value Value to store
641
+ \param [in] ptr Pointer to location
642
+ */
643
+ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
644
+ {
645
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
646
+ }
647
+
648
+
649
+ /**
650
+ \brief Load-Acquire Exclusive (8 bit)
651
+ \details Executes a LDAB exclusive instruction for 8 bit value.
652
+ \param [in] ptr Pointer to data
653
+ \return value of type uint8_t at (*ptr)
654
+ */
655
+ #define __LDAEXB (uint8_t)__builtin_arm_ldaex
656
+
657
+
658
+ /**
659
+ \brief Load-Acquire Exclusive (16 bit)
660
+ \details Executes a LDAH exclusive instruction for 16 bit values.
661
+ \param [in] ptr Pointer to data
662
+ \return value of type uint16_t at (*ptr)
663
+ */
664
+ #define __LDAEXH (uint16_t)__builtin_arm_ldaex
665
+
666
+
667
+ /**
668
+ \brief Load-Acquire Exclusive (32 bit)
669
+ \details Executes a LDA exclusive instruction for 32 bit values.
670
+ \param [in] ptr Pointer to data
671
+ \return value of type uint32_t at (*ptr)
672
+ */
673
+ #define __LDAEX (uint32_t)__builtin_arm_ldaex
674
+
675
+
676
+ /**
677
+ \brief Store-Release Exclusive (8 bit)
678
+ \details Executes a STLB exclusive instruction for 8 bit values.
679
+ \param [in] value Value to store
680
+ \param [in] ptr Pointer to location
681
+ \return 0 Function succeeded
682
+ \return 1 Function failed
683
+ */
684
+ #define __STLEXB (uint32_t)__builtin_arm_stlex
685
+
686
+
687
+ /**
688
+ \brief Store-Release Exclusive (16 bit)
689
+ \details Executes a STLH exclusive instruction for 16 bit values.
690
+ \param [in] value Value to store
691
+ \param [in] ptr Pointer to location
692
+ \return 0 Function succeeded
693
+ \return 1 Function failed
694
+ */
695
+ #define __STLEXH (uint32_t)__builtin_arm_stlex
696
+
697
+
698
+ /**
699
+ \brief Store-Release Exclusive (32 bit)
700
+ \details Executes a STL exclusive instruction for 32 bit values.
701
+ \param [in] value Value to store
702
+ \param [in] ptr Pointer to location
703
+ \return 0 Function succeeded
704
+ \return 1 Function failed
705
+ */
706
+ #define __STLEX (uint32_t)__builtin_arm_stlex
707
+
708
+ #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
709
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
710
+
711
+ /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
712
+
713
+
714
+ /* ########################### Core Function Access ########################### */
715
+ /** \ingroup CMSIS_Core_FunctionInterface
716
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
717
+ @{
718
+ */
719
+
720
+ /**
721
+ \brief Enable IRQ Interrupts
722
+ \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
723
+ Can only be executed in Privileged modes.
724
+ */
725
+ #ifndef __ARM_COMPAT_H
726
+ __STATIC_FORCEINLINE void __enable_irq(void)
727
+ {
728
+ __ASM volatile ("cpsie i" : : : "memory");
729
+ }
730
+ #endif
731
+
732
+
733
+ /**
734
+ \brief Disable IRQ Interrupts
735
+ \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
736
+ Can only be executed in Privileged modes.
737
+ */
738
+ #ifndef __ARM_COMPAT_H
739
+ __STATIC_FORCEINLINE void __disable_irq(void)
740
+ {
741
+ __ASM volatile ("cpsid i" : : : "memory");
742
+ }
743
+ #endif
744
+
745
+
746
+ /**
747
+ \brief Get Control Register
748
+ \details Returns the content of the Control Register.
749
+ \return Control Register value
750
+ */
751
+ __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
752
+ {
753
+ uint32_t result;
754
+
755
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
756
+ return(result);
757
+ }
758
+
759
+
760
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
761
+ /**
762
+ \brief Get Control Register (non-secure)
763
+ \details Returns the content of the non-secure Control Register when in secure mode.
764
+ \return non-secure Control Register value
765
+ */
766
+ __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
767
+ {
768
+ uint32_t result;
769
+
770
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
771
+ return(result);
772
+ }
773
+ #endif
774
+
775
+
776
+ /**
777
+ \brief Set Control Register
778
+ \details Writes the given value to the Control Register.
779
+ \param [in] control Control Register value to set
780
+ */
781
+ __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
782
+ {
783
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
784
+ __ISB();
785
+ }
786
+
787
+
788
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
789
+ /**
790
+ \brief Set Control Register (non-secure)
791
+ \details Writes the given value to the non-secure Control Register when in secure state.
792
+ \param [in] control Control Register value to set
793
+ */
794
+ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
795
+ {
796
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
797
+ __ISB();
798
+ }
799
+ #endif
800
+
801
+
802
+ /**
803
+ \brief Get IPSR Register
804
+ \details Returns the content of the IPSR Register.
805
+ \return IPSR Register value
806
+ */
807
+ __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
808
+ {
809
+ uint32_t result;
810
+
811
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
812
+ return(result);
813
+ }
814
+
815
+
816
+ /**
817
+ \brief Get APSR Register
818
+ \details Returns the content of the APSR Register.
819
+ \return APSR Register value
820
+ */
821
+ __STATIC_FORCEINLINE uint32_t __get_APSR(void)
822
+ {
823
+ uint32_t result;
824
+
825
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
826
+ return(result);
827
+ }
828
+
829
+
830
+ /**
831
+ \brief Get xPSR Register
832
+ \details Returns the content of the xPSR Register.
833
+ \return xPSR Register value
834
+ */
835
+ __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
836
+ {
837
+ uint32_t result;
838
+
839
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
840
+ return(result);
841
+ }
842
+
843
+
844
+ /**
845
+ \brief Get Process Stack Pointer
846
+ \details Returns the current value of the Process Stack Pointer (PSP).
847
+ \return PSP Register value
848
+ */
849
+ __STATIC_FORCEINLINE uint32_t __get_PSP(void)
850
+ {
851
+ uint32_t result;
852
+
853
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
854
+ return(result);
855
+ }
856
+
857
+
858
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
859
+ /**
860
+ \brief Get Process Stack Pointer (non-secure)
861
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
862
+ \return PSP Register value
863
+ */
864
+ __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
865
+ {
866
+ uint32_t result;
867
+
868
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
869
+ return(result);
870
+ }
871
+ #endif
872
+
873
+
874
+ /**
875
+ \brief Set Process Stack Pointer
876
+ \details Assigns the given value to the Process Stack Pointer (PSP).
877
+ \param [in] topOfProcStack Process Stack Pointer value to set
878
+ */
879
+ __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
880
+ {
881
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
882
+ }
883
+
884
+
885
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
886
+ /**
887
+ \brief Set Process Stack Pointer (non-secure)
888
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
889
+ \param [in] topOfProcStack Process Stack Pointer value to set
890
+ */
891
+ __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
892
+ {
893
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
894
+ }
895
+ #endif
896
+
897
+
898
+ /**
899
+ \brief Get Main Stack Pointer
900
+ \details Returns the current value of the Main Stack Pointer (MSP).
901
+ \return MSP Register value
902
+ */
903
+ __STATIC_FORCEINLINE uint32_t __get_MSP(void)
904
+ {
905
+ uint32_t result;
906
+
907
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
908
+ return(result);
909
+ }
910
+
911
+
912
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
913
+ /**
914
+ \brief Get Main Stack Pointer (non-secure)
915
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
916
+ \return MSP Register value
917
+ */
918
+ __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
919
+ {
920
+ uint32_t result;
921
+
922
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
923
+ return(result);
924
+ }
925
+ #endif
926
+
927
+
928
+ /**
929
+ \brief Set Main Stack Pointer
930
+ \details Assigns the given value to the Main Stack Pointer (MSP).
931
+ \param [in] topOfMainStack Main Stack Pointer value to set
932
+ */
933
+ __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
934
+ {
935
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
936
+ }
937
+
938
+
939
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
940
+ /**
941
+ \brief Set Main Stack Pointer (non-secure)
942
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
943
+ \param [in] topOfMainStack Main Stack Pointer value to set
944
+ */
945
+ __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
946
+ {
947
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
948
+ }
949
+ #endif
950
+
951
+
952
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
953
+ /**
954
+ \brief Get Stack Pointer (non-secure)
955
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
956
+ \return SP Register value
957
+ */
958
+ __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
959
+ {
960
+ uint32_t result;
961
+
962
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
963
+ return(result);
964
+ }
965
+
966
+
967
+ /**
968
+ \brief Set Stack Pointer (non-secure)
969
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
970
+ \param [in] topOfStack Stack Pointer value to set
971
+ */
972
+ __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
973
+ {
974
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
975
+ }
976
+ #endif
977
+
978
+
979
+ /**
980
+ \brief Get Priority Mask
981
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
982
+ \return Priority Mask value
983
+ */
984
+ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
985
+ {
986
+ uint32_t result;
987
+
988
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
989
+ return(result);
990
+ }
991
+
992
+
993
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
994
+ /**
995
+ \brief Get Priority Mask (non-secure)
996
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
997
+ \return Priority Mask value
998
+ */
999
+ __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
1000
+ {
1001
+ uint32_t result;
1002
+
1003
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
1004
+ return(result);
1005
+ }
1006
+ #endif
1007
+
1008
+
1009
+ /**
1010
+ \brief Set Priority Mask
1011
+ \details Assigns the given value to the Priority Mask Register.
1012
+ \param [in] priMask Priority Mask
1013
+ */
1014
+ __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
1015
+ {
1016
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
1017
+ }
1018
+
1019
+
1020
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1021
+ /**
1022
+ \brief Set Priority Mask (non-secure)
1023
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
1024
+ \param [in] priMask Priority Mask
1025
+ */
1026
+ __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
1027
+ {
1028
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
1029
+ }
1030
+ #endif
1031
+
1032
+
1033
+ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
1034
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
1035
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
1036
+ /**
1037
+ \brief Enable FIQ
1038
+ \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
1039
+ Can only be executed in Privileged modes.
1040
+ */
1041
+ __STATIC_FORCEINLINE void __enable_fault_irq(void)
1042
+ {
1043
+ __ASM volatile ("cpsie f" : : : "memory");
1044
+ }
1045
+
1046
+
1047
+ /**
1048
+ \brief Disable FIQ
1049
+ \details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
1050
+ Can only be executed in Privileged modes.
1051
+ */
1052
+ __STATIC_FORCEINLINE void __disable_fault_irq(void)
1053
+ {
1054
+ __ASM volatile ("cpsid f" : : : "memory");
1055
+ }
1056
+
1057
+
1058
+ /**
1059
+ \brief Get Base Priority
1060
+ \details Returns the current value of the Base Priority register.
1061
+ \return Base Priority register value
1062
+ */
1063
+ __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
1064
+ {
1065
+ uint32_t result;
1066
+
1067
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
1068
+ return(result);
1069
+ }
1070
+
1071
+
1072
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1073
+ /**
1074
+ \brief Get Base Priority (non-secure)
1075
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
1076
+ \return Base Priority register value
1077
+ */
1078
+ __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
1079
+ {
1080
+ uint32_t result;
1081
+
1082
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
1083
+ return(result);
1084
+ }
1085
+ #endif
1086
+
1087
+
1088
+ /**
1089
+ \brief Set Base Priority
1090
+ \details Assigns the given value to the Base Priority register.
1091
+ \param [in] basePri Base Priority value to set
1092
+ */
1093
+ __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
1094
+ {
1095
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
1096
+ }
1097
+
1098
+
1099
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1100
+ /**
1101
+ \brief Set Base Priority (non-secure)
1102
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
1103
+ \param [in] basePri Base Priority value to set
1104
+ */
1105
+ __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
1106
+ {
1107
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
1108
+ }
1109
+ #endif
1110
+
1111
+
1112
+ /**
1113
+ \brief Set Base Priority with condition
1114
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
1115
+ or the new value increases the BASEPRI priority level.
1116
+ \param [in] basePri Base Priority value to set
1117
+ */
1118
+ __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
1119
+ {
1120
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
1121
+ }
1122
+
1123
+
1124
+ /**
1125
+ \brief Get Fault Mask
1126
+ \details Returns the current value of the Fault Mask register.
1127
+ \return Fault Mask register value
1128
+ */
1129
+ __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
1130
+ {
1131
+ uint32_t result;
1132
+
1133
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
1134
+ return(result);
1135
+ }
1136
+
1137
+
1138
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1139
+ /**
1140
+ \brief Get Fault Mask (non-secure)
1141
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
1142
+ \return Fault Mask register value
1143
+ */
1144
+ __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
1145
+ {
1146
+ uint32_t result;
1147
+
1148
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
1149
+ return(result);
1150
+ }
1151
+ #endif
1152
+
1153
+
1154
+ /**
1155
+ \brief Set Fault Mask
1156
+ \details Assigns the given value to the Fault Mask register.
1157
+ \param [in] faultMask Fault Mask value to set
1158
+ */
1159
+ __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
1160
+ {
1161
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
1162
+ }
1163
+
1164
+
1165
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1166
+ /**
1167
+ \brief Set Fault Mask (non-secure)
1168
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
1169
+ \param [in] faultMask Fault Mask value to set
1170
+ */
1171
+ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
1172
+ {
1173
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
1174
+ }
1175
+ #endif
1176
+
1177
+ #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
1178
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
1179
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
1180
+
1181
+
1182
+ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1183
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
1184
+
1185
+ /**
1186
+ \brief Get Process Stack Pointer Limit
1187
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1188
+ Stack Pointer Limit register hence zero is returned always in non-secure
1189
+ mode.
1190
+
1191
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
1192
+ \return PSPLIM Register value
1193
+ */
1194
+ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
1195
+ {
1196
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
1197
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
1198
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
1199
+ return 0U;
1200
+ #else
1201
+ uint32_t result;
1202
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
1203
+ return result;
1204
+ #endif
1205
+ }
1206
+
1207
+ #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
1208
+ /**
1209
+ \brief Get Process Stack Pointer Limit (non-secure)
1210
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1211
+ Stack Pointer Limit register hence zero is returned always in non-secure
1212
+ mode.
1213
+
1214
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
1215
+ \return PSPLIM Register value
1216
+ */
1217
+ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
1218
+ {
1219
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
1220
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
1221
+ return 0U;
1222
+ #else
1223
+ uint32_t result;
1224
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
1225
+ return result;
1226
+ #endif
1227
+ }
1228
+ #endif
1229
+
1230
+
1231
+ /**
1232
+ \brief Set Process Stack Pointer Limit
1233
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1234
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
1235
+ mode.
1236
+
1237
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
1238
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
1239
+ */
1240
+ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
1241
+ {
1242
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
1243
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
1244
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
1245
+ (void)ProcStackPtrLimit;
1246
+ #else
1247
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
1248
+ #endif
1249
+ }
1250
+
1251
+
1252
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1253
+ /**
1254
+ \brief Set Process Stack Pointer (non-secure)
1255
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1256
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
1257
+ mode.
1258
+
1259
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
1260
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
1261
+ */
1262
+ __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
1263
+ {
1264
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
1265
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
1266
+ (void)ProcStackPtrLimit;
1267
+ #else
1268
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
1269
+ #endif
1270
+ }
1271
+ #endif
1272
+
1273
+
1274
+ /**
1275
+ \brief Get Main Stack Pointer Limit
1276
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1277
+ Stack Pointer Limit register hence zero is returned always.
1278
+
1279
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
1280
+ \return MSPLIM Register value
1281
+ */
1282
+ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
1283
+ {
1284
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
1285
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
1286
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
1287
+ return 0U;
1288
+ #else
1289
+ uint32_t result;
1290
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
1291
+ return result;
1292
+ #endif
1293
+ }
1294
+
1295
+
1296
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1297
+ /**
1298
+ \brief Get Main Stack Pointer Limit (non-secure)
1299
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1300
+ Stack Pointer Limit register hence zero is returned always.
1301
+
1302
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
1303
+ \return MSPLIM Register value
1304
+ */
1305
+ __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
1306
+ {
1307
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
1308
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
1309
+ return 0U;
1310
+ #else
1311
+ uint32_t result;
1312
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
1313
+ return result;
1314
+ #endif
1315
+ }
1316
+ #endif
1317
+
1318
+
1319
+ /**
1320
+ \brief Set Main Stack Pointer Limit
1321
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1322
+ Stack Pointer Limit register hence the write is silently ignored.
1323
+
1324
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
1325
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
1326
+ */
1327
+ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
1328
+ {
1329
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
1330
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
1331
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
1332
+ (void)MainStackPtrLimit;
1333
+ #else
1334
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
1335
+ #endif
1336
+ }
1337
+
1338
+
1339
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1340
+ /**
1341
+ \brief Set Main Stack Pointer Limit (non-secure)
1342
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1343
+ Stack Pointer Limit register hence the write is silently ignored.
1344
+
1345
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
1346
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
1347
+ */
1348
+ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
1349
+ {
1350
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
1351
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
1352
+ (void)MainStackPtrLimit;
1353
+ #else
1354
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
1355
+ #endif
1356
+ }
1357
+ #endif
1358
+
1359
+ #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1360
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
1361
+
1362
+ /**
1363
+ \brief Get FPSCR
1364
+ \details Returns the current value of the Floating Point Status/Control register.
1365
+ \return Floating Point Status/Control register value
1366
+ */
1367
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
1368
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
1369
+ #define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
1370
+ #else
1371
+ #define __get_FPSCR() ((uint32_t)0U)
1372
+ #endif
1373
+
1374
+ /**
1375
+ \brief Set FPSCR
1376
+ \details Assigns the given value to the Floating Point Status/Control register.
1377
+ \param [in] fpscr Floating Point Status/Control value to set
1378
+ */
1379
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
1380
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
1381
+ #define __set_FPSCR __builtin_arm_set_fpscr
1382
+ #else
1383
+ #define __set_FPSCR(x) ((void)(x))
1384
+ #endif
1385
+
1386
+
1387
+ /*@} end of CMSIS_Core_RegAccFunctions */
1388
+
1389
+
1390
+ /* ################### Compiler specific Intrinsics ########################### */
1391
+ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
1392
+ Access to dedicated SIMD instructions
1393
+ @{
1394
+ */
1395
+
1396
+ #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
1397
+
1398
+ __STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
1399
+ {
1400
+ uint32_t result;
1401
+
1402
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1403
+ return(result);
1404
+ }
1405
+
1406
+ __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
1407
+ {
1408
+ uint32_t result;
1409
+
1410
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1411
+ return(result);
1412
+ }
1413
+
1414
+ __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
1415
+ {
1416
+ uint32_t result;
1417
+
1418
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1419
+ return(result);
1420
+ }
1421
+
1422
+ __STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
1423
+ {
1424
+ uint32_t result;
1425
+
1426
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1427
+ return(result);
1428
+ }
1429
+
1430
+ __STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
1431
+ {
1432
+ uint32_t result;
1433
+
1434
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1435
+ return(result);
1436
+ }
1437
+
1438
+ __STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
1439
+ {
1440
+ uint32_t result;
1441
+
1442
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1443
+ return(result);
1444
+ }
1445
+
1446
+
1447
+ __STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
1448
+ {
1449
+ uint32_t result;
1450
+
1451
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1452
+ return(result);
1453
+ }
1454
+
1455
+ __STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
1456
+ {
1457
+ uint32_t result;
1458
+
1459
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1460
+ return(result);
1461
+ }
1462
+
1463
+ __STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
1464
+ {
1465
+ uint32_t result;
1466
+
1467
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1468
+ return(result);
1469
+ }
1470
+
1471
+ __STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
1472
+ {
1473
+ uint32_t result;
1474
+
1475
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1476
+ return(result);
1477
+ }
1478
+
1479
+ __STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
1480
+ {
1481
+ uint32_t result;
1482
+
1483
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1484
+ return(result);
1485
+ }
1486
+
1487
+ __STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
1488
+ {
1489
+ uint32_t result;
1490
+
1491
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1492
+ return(result);
1493
+ }
1494
+
1495
+
1496
+ __STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
1497
+ {
1498
+ uint32_t result;
1499
+
1500
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1501
+ return(result);
1502
+ }
1503
+
1504
+ __STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
1505
+ {
1506
+ uint32_t result;
1507
+
1508
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1509
+ return(result);
1510
+ }
1511
+
1512
+ __STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
1513
+ {
1514
+ uint32_t result;
1515
+
1516
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1517
+ return(result);
1518
+ }
1519
+
1520
+ __STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
1521
+ {
1522
+ uint32_t result;
1523
+
1524
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1525
+ return(result);
1526
+ }
1527
+
1528
+ __STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
1529
+ {
1530
+ uint32_t result;
1531
+
1532
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1533
+ return(result);
1534
+ }
1535
+
1536
+ __STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
1537
+ {
1538
+ uint32_t result;
1539
+
1540
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1541
+ return(result);
1542
+ }
1543
+
1544
+ __STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
1545
+ {
1546
+ uint32_t result;
1547
+
1548
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1549
+ return(result);
1550
+ }
1551
+
1552
+ __STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
1553
+ {
1554
+ uint32_t result;
1555
+
1556
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1557
+ return(result);
1558
+ }
1559
+
1560
+ __STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
1561
+ {
1562
+ uint32_t result;
1563
+
1564
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1565
+ return(result);
1566
+ }
1567
+
1568
+ __STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
1569
+ {
1570
+ uint32_t result;
1571
+
1572
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1573
+ return(result);
1574
+ }
1575
+
1576
+ __STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
1577
+ {
1578
+ uint32_t result;
1579
+
1580
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1581
+ return(result);
1582
+ }
1583
+
1584
+ __STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
1585
+ {
1586
+ uint32_t result;
1587
+
1588
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1589
+ return(result);
1590
+ }
1591
+
1592
+ __STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
1593
+ {
1594
+ uint32_t result;
1595
+
1596
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1597
+ return(result);
1598
+ }
1599
+
1600
+ __STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
1601
+ {
1602
+ uint32_t result;
1603
+
1604
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1605
+ return(result);
1606
+ }
1607
+
1608
+ __STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
1609
+ {
1610
+ uint32_t result;
1611
+
1612
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1613
+ return(result);
1614
+ }
1615
+
1616
+ __STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
1617
+ {
1618
+ uint32_t result;
1619
+
1620
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1621
+ return(result);
1622
+ }
1623
+
1624
+ __STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
1625
+ {
1626
+ uint32_t result;
1627
+
1628
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1629
+ return(result);
1630
+ }
1631
+
1632
+ __STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
1633
+ {
1634
+ uint32_t result;
1635
+
1636
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1637
+ return(result);
1638
+ }
1639
+
1640
+ __STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
1641
+ {
1642
+ uint32_t result;
1643
+
1644
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1645
+ return(result);
1646
+ }
1647
+
1648
+ __STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
1649
+ {
1650
+ uint32_t result;
1651
+
1652
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1653
+ return(result);
1654
+ }
1655
+
1656
+ __STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
1657
+ {
1658
+ uint32_t result;
1659
+
1660
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1661
+ return(result);
1662
+ }
1663
+
1664
+ __STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
1665
+ {
1666
+ uint32_t result;
1667
+
1668
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1669
+ return(result);
1670
+ }
1671
+
1672
+ __STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
1673
+ {
1674
+ uint32_t result;
1675
+
1676
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1677
+ return(result);
1678
+ }
1679
+
1680
+ __STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
1681
+ {
1682
+ uint32_t result;
1683
+
1684
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1685
+ return(result);
1686
+ }
1687
+
1688
+ __STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
1689
+ {
1690
+ uint32_t result;
1691
+
1692
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1693
+ return(result);
1694
+ }
1695
+
1696
+ __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
1697
+ {
1698
+ uint32_t result;
1699
+
1700
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
1701
+ return(result);
1702
+ }
1703
+
1704
+ #define __SSAT16(ARG1,ARG2) \
1705
+ ({ \
1706
+ int32_t __RES, __ARG1 = (ARG1); \
1707
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
1708
+ __RES; \
1709
+ })
1710
+
1711
+ #define __USAT16(ARG1,ARG2) \
1712
+ ({ \
1713
+ uint32_t __RES, __ARG1 = (ARG1); \
1714
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
1715
+ __RES; \
1716
+ })
1717
+
1718
+ __STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
1719
+ {
1720
+ uint32_t result;
1721
+
1722
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
1723
+ return(result);
1724
+ }
1725
+
1726
+ __STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
1727
+ {
1728
+ uint32_t result;
1729
+
1730
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1731
+ return(result);
1732
+ }
1733
+
1734
+ __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
1735
+ {
1736
+ uint32_t result;
1737
+
1738
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
1739
+ return(result);
1740
+ }
1741
+
1742
+ __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
1743
+ {
1744
+ uint32_t result;
1745
+
1746
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1747
+ return(result);
1748
+ }
1749
+
1750
+ __STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
1751
+ {
1752
+ uint32_t result;
1753
+
1754
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1755
+ return(result);
1756
+ }
1757
+
1758
+ __STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
1759
+ {
1760
+ uint32_t result;
1761
+
1762
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1763
+ return(result);
1764
+ }
1765
+
1766
+ __STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
1767
+ {
1768
+ uint32_t result;
1769
+
1770
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
1771
+ return(result);
1772
+ }
1773
+
1774
+ __STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
1775
+ {
1776
+ uint32_t result;
1777
+
1778
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
1779
+ return(result);
1780
+ }
1781
+
1782
+ __STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
1783
+ {
1784
+ union llreg_u{
1785
+ uint32_t w32[2];
1786
+ uint64_t w64;
1787
+ } llr;
1788
+ llr.w64 = acc;
1789
+
1790
+ #ifndef __ARMEB__ /* Little endian */
1791
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
1792
+ #else /* Big endian */
1793
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
1794
+ #endif
1795
+
1796
+ return(llr.w64);
1797
+ }
1798
+
1799
+ __STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
1800
+ {
1801
+ union llreg_u{
1802
+ uint32_t w32[2];
1803
+ uint64_t w64;
1804
+ } llr;
1805
+ llr.w64 = acc;
1806
+
1807
+ #ifndef __ARMEB__ /* Little endian */
1808
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
1809
+ #else /* Big endian */
1810
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
1811
+ #endif
1812
+
1813
+ return(llr.w64);
1814
+ }
1815
+
1816
+ __STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
1817
+ {
1818
+ uint32_t result;
1819
+
1820
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1821
+ return(result);
1822
+ }
1823
+
1824
+ __STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
1825
+ {
1826
+ uint32_t result;
1827
+
1828
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1829
+ return(result);
1830
+ }
1831
+
1832
+ __STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
1833
+ {
1834
+ uint32_t result;
1835
+
1836
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
1837
+ return(result);
1838
+ }
1839
+
1840
+ __STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
1841
+ {
1842
+ uint32_t result;
1843
+
1844
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
1845
+ return(result);
1846
+ }
1847
+
1848
+ __STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
1849
+ {
1850
+ union llreg_u{
1851
+ uint32_t w32[2];
1852
+ uint64_t w64;
1853
+ } llr;
1854
+ llr.w64 = acc;
1855
+
1856
+ #ifndef __ARMEB__ /* Little endian */
1857
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
1858
+ #else /* Big endian */
1859
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
1860
+ #endif
1861
+
1862
+ return(llr.w64);
1863
+ }
1864
+
1865
+ __STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
1866
+ {
1867
+ union llreg_u{
1868
+ uint32_t w32[2];
1869
+ uint64_t w64;
1870
+ } llr;
1871
+ llr.w64 = acc;
1872
+
1873
+ #ifndef __ARMEB__ /* Little endian */
1874
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
1875
+ #else /* Big endian */
1876
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
1877
+ #endif
1878
+
1879
+ return(llr.w64);
1880
+ }
1881
+
1882
+ __STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
1883
+ {
1884
+ uint32_t result;
1885
+
1886
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1887
+ return(result);
1888
+ }
1889
+
1890
+ __STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
1891
+ {
1892
+ int32_t result;
1893
+
1894
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1895
+ return(result);
1896
+ }
1897
+
1898
+ __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
1899
+ {
1900
+ int32_t result;
1901
+
1902
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1903
+ return(result);
1904
+ }
1905
+
1906
+ #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
1907
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
1908
+
1909
+ #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
1910
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
1911
+
1912
+ #define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
1913
+
1914
+ #define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
1915
+
1916
+ __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
1917
+ {
1918
+ int32_t result;
1919
+
1920
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
1921
+ return(result);
1922
+ }
1923
+
1924
+ #endif /* (__ARM_FEATURE_DSP == 1) */
1925
+ /*@} end of group CMSIS_SIMD_intrinsics */
1926
+
1927
+
1928
+ #endif /* __CMSIS_ARMCLANG_H */
edge-impulse-sdk/CMSIS/Core/Include/cmsis_compiler.h ADDED
@@ -0,0 +1,283 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ /**************************************************************************//**
2
+ * @file cmsis_compiler.h
3
+ * @brief CMSIS compiler generic header file
4
+ * @version V5.1.0
5
+ * @date 09. October 2018
6
+ ******************************************************************************/
7
+ /*
8
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
9
+ *
10
+ * SPDX-License-Identifier: Apache-2.0
11
+ *
12
+ * Licensed under the Apache License, Version 2.0 (the License); you may
13
+ * not use this file except in compliance with the License.
14
+ * You may obtain a copy of the License at
15
+ *
16
+ * www.apache.org/licenses/LICENSE-2.0
17
+ *
18
+ * Unless required by applicable law or agreed to in writing, software
19
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21
+ * See the License for the specific language governing permissions and
22
+ * limitations under the License.
23
+ */
24
+
25
+ #ifndef __CMSIS_COMPILER_H
26
+ #define __CMSIS_COMPILER_H
27
+
28
+ #include <stdint.h>
29
+
30
+ /*
31
+ * Arm Compiler 4/5
32
+ */
33
+ #if defined ( __CC_ARM )
34
+ #include "cmsis_armcc.h"
35
+
36
+
37
+ /*
38
+ * Arm Compiler 6.6 LTM (armclang)
39
+ */
40
+ #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
41
+ #include "cmsis_armclang_ltm.h"
42
+
43
+ /*
44
+ * Arm Compiler above 6.10.1 (armclang)
45
+ */
46
+ #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
47
+ #include "cmsis_armclang.h"
48
+
49
+
50
+ /*
51
+ * GNU Compiler
52
+ */
53
+ #elif defined ( __GNUC__ )
54
+ #include "cmsis_gcc.h"
55
+
56
+
57
+ /*
58
+ * IAR Compiler
59
+ */
60
+ #elif defined ( __ICCARM__ )
61
+ #include <cmsis_iccarm.h>
62
+
63
+
64
+ /*
65
+ * TI Arm Compiler
66
+ */
67
+ #elif defined ( __TI_ARM__ )
68
+ #include <cmsis_ccs.h>
69
+
70
+ #ifndef __ASM
71
+ #define __ASM __asm
72
+ #endif
73
+ #ifndef __INLINE
74
+ #define __INLINE inline
75
+ #endif
76
+ #ifndef __STATIC_INLINE
77
+ #define __STATIC_INLINE static inline
78
+ #endif
79
+ #ifndef __STATIC_FORCEINLINE
80
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
81
+ #endif
82
+ #ifndef __NO_RETURN
83
+ #define __NO_RETURN __attribute__((noreturn))
84
+ #endif
85
+ #ifndef __USED
86
+ #define __USED __attribute__((used))
87
+ #endif
88
+ #ifndef __WEAK
89
+ #define __WEAK __attribute__((weak))
90
+ #endif
91
+ #ifndef __PACKED
92
+ #define __PACKED __attribute__((packed))
93
+ #endif
94
+ #ifndef __PACKED_STRUCT
95
+ #define __PACKED_STRUCT struct __attribute__((packed))
96
+ #endif
97
+ #ifndef __PACKED_UNION
98
+ #define __PACKED_UNION union __attribute__((packed))
99
+ #endif
100
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
101
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
102
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
103
+ #endif
104
+ #ifndef __UNALIGNED_UINT16_WRITE
105
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
106
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
107
+ #endif
108
+ #ifndef __UNALIGNED_UINT16_READ
109
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
110
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
111
+ #endif
112
+ #ifndef __UNALIGNED_UINT32_WRITE
113
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
114
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
115
+ #endif
116
+ #ifndef __UNALIGNED_UINT32_READ
117
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
118
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
119
+ #endif
120
+ #ifndef __ALIGNED
121
+ #define __ALIGNED(x) __attribute__((aligned(x)))
122
+ #endif
123
+ #ifndef __RESTRICT
124
+ #define __RESTRICT __restrict
125
+ #endif
126
+ #ifndef __COMPILER_BARRIER
127
+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
128
+ #define __COMPILER_BARRIER() (void)0
129
+ #endif
130
+
131
+
132
+ /*
133
+ * TASKING Compiler
134
+ */
135
+ #elif defined ( __TASKING__ )
136
+ /*
137
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
138
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
139
+ * Including the CMSIS ones.
140
+ */
141
+
142
+ #ifndef __ASM
143
+ #define __ASM __asm
144
+ #endif
145
+ #ifndef __INLINE
146
+ #define __INLINE inline
147
+ #endif
148
+ #ifndef __STATIC_INLINE
149
+ #define __STATIC_INLINE static inline
150
+ #endif
151
+ #ifndef __STATIC_FORCEINLINE
152
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
153
+ #endif
154
+ #ifndef __NO_RETURN
155
+ #define __NO_RETURN __attribute__((noreturn))
156
+ #endif
157
+ #ifndef __USED
158
+ #define __USED __attribute__((used))
159
+ #endif
160
+ #ifndef __WEAK
161
+ #define __WEAK __attribute__((weak))
162
+ #endif
163
+ #ifndef __PACKED
164
+ #define __PACKED __packed__
165
+ #endif
166
+ #ifndef __PACKED_STRUCT
167
+ #define __PACKED_STRUCT struct __packed__
168
+ #endif
169
+ #ifndef __PACKED_UNION
170
+ #define __PACKED_UNION union __packed__
171
+ #endif
172
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
173
+ struct __packed__ T_UINT32 { uint32_t v; };
174
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
175
+ #endif
176
+ #ifndef __UNALIGNED_UINT16_WRITE
177
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
178
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
179
+ #endif
180
+ #ifndef __UNALIGNED_UINT16_READ
181
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
182
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
183
+ #endif
184
+ #ifndef __UNALIGNED_UINT32_WRITE
185
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
186
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
187
+ #endif
188
+ #ifndef __UNALIGNED_UINT32_READ
189
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
190
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
191
+ #endif
192
+ #ifndef __ALIGNED
193
+ #define __ALIGNED(x) __align(x)
194
+ #endif
195
+ #ifndef __RESTRICT
196
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
197
+ #define __RESTRICT
198
+ #endif
199
+ #ifndef __COMPILER_BARRIER
200
+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
201
+ #define __COMPILER_BARRIER() (void)0
202
+ #endif
203
+
204
+
205
+ /*
206
+ * COSMIC Compiler
207
+ */
208
+ #elif defined ( __CSMC__ )
209
+ #include <cmsis_csm.h>
210
+
211
+ #ifndef __ASM
212
+ #define __ASM _asm
213
+ #endif
214
+ #ifndef __INLINE
215
+ #define __INLINE inline
216
+ #endif
217
+ #ifndef __STATIC_INLINE
218
+ #define __STATIC_INLINE static inline
219
+ #endif
220
+ #ifndef __STATIC_FORCEINLINE
221
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
222
+ #endif
223
+ #ifndef __NO_RETURN
224
+ // NO RETURN is automatically detected hence no warning here
225
+ #define __NO_RETURN
226
+ #endif
227
+ #ifndef __USED
228
+ #warning No compiler specific solution for __USED. __USED is ignored.
229
+ #define __USED
230
+ #endif
231
+ #ifndef __WEAK
232
+ #define __WEAK __weak
233
+ #endif
234
+ #ifndef __PACKED
235
+ #define __PACKED @packed
236
+ #endif
237
+ #ifndef __PACKED_STRUCT
238
+ #define __PACKED_STRUCT @packed struct
239
+ #endif
240
+ #ifndef __PACKED_UNION
241
+ #define __PACKED_UNION @packed union
242
+ #endif
243
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
244
+ @packed struct T_UINT32 { uint32_t v; };
245
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
246
+ #endif
247
+ #ifndef __UNALIGNED_UINT16_WRITE
248
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
249
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
250
+ #endif
251
+ #ifndef __UNALIGNED_UINT16_READ
252
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
253
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
254
+ #endif
255
+ #ifndef __UNALIGNED_UINT32_WRITE
256
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
257
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
258
+ #endif
259
+ #ifndef __UNALIGNED_UINT32_READ
260
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
261
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
262
+ #endif
263
+ #ifndef __ALIGNED
264
+ #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
265
+ #define __ALIGNED(x)
266
+ #endif
267
+ #ifndef __RESTRICT
268
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
269
+ #define __RESTRICT
270
+ #endif
271
+ #ifndef __COMPILER_BARRIER
272
+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
273
+ #define __COMPILER_BARRIER() (void)0
274
+ #endif
275
+
276
+
277
+ #else
278
+ #error Unknown compiler.
279
+ #endif
280
+
281
+
282
+ #endif /* __CMSIS_COMPILER_H */
283
+
edge-impulse-sdk/CMSIS/Core/Include/cmsis_gcc.h ADDED
@@ -0,0 +1,2217 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ /**************************************************************************//**
2
+ * @file cmsis_gcc.h
3
+ * @brief CMSIS compiler GCC header file
4
+ * @version V5.4.1
5
+ * @date 27. May 2021
6
+ ******************************************************************************/
7
+ /*
8
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
9
+ *
10
+ * SPDX-License-Identifier: Apache-2.0
11
+ *
12
+ * Licensed under the Apache License, Version 2.0 (the License); you may
13
+ * not use this file except in compliance with the License.
14
+ * You may obtain a copy of the License at
15
+ *
16
+ * www.apache.org/licenses/LICENSE-2.0
17
+ *
18
+ * Unless required by applicable law or agreed to in writing, software
19
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21
+ * See the License for the specific language governing permissions and
22
+ * limitations under the License.
23
+ */
24
+
25
+ #ifndef __CMSIS_GCC_H
26
+ #define __CMSIS_GCC_H
27
+
28
+ /* ignore some GCC warnings */
29
+ #pragma GCC diagnostic push
30
+ #pragma GCC diagnostic ignored "-Wsign-conversion"
31
+ #pragma GCC diagnostic ignored "-Wconversion"
32
+ #pragma GCC diagnostic ignored "-Wunused-parameter"
33
+
34
+ /* Fallback for __has_builtin */
35
+ #ifndef __has_builtin
36
+ #define __has_builtin(x) (0)
37
+ #endif
38
+
39
+ /* CMSIS compiler specific defines */
40
+ #ifndef __ASM
41
+ #define __ASM __asm
42
+ #endif
43
+ #ifndef __INLINE
44
+ #define __INLINE inline
45
+ #endif
46
+ #ifndef __STATIC_INLINE
47
+ #define __STATIC_INLINE static inline
48
+ #endif
49
+ #ifndef __STATIC_FORCEINLINE
50
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
51
+ #endif
52
+ #ifndef __NO_RETURN
53
+ #define __NO_RETURN __attribute__((__noreturn__))
54
+ #endif
55
+ #ifndef __USED
56
+ #define __USED __attribute__((used))
57
+ #endif
58
+ #ifndef __WEAK
59
+ #define __WEAK __attribute__((weak))
60
+ #endif
61
+ #ifndef __PACKED
62
+ #define __PACKED __attribute__((packed, aligned(1)))
63
+ #endif
64
+ #ifndef __PACKED_STRUCT
65
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
66
+ #endif
67
+ #ifndef __PACKED_UNION
68
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
69
+ #endif
70
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
71
+ #pragma GCC diagnostic push
72
+ #pragma GCC diagnostic ignored "-Wpacked"
73
+ #pragma GCC diagnostic ignored "-Wattributes"
74
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
75
+ #pragma GCC diagnostic pop
76
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
77
+ #endif
78
+ #ifndef __UNALIGNED_UINT16_WRITE
79
+ #pragma GCC diagnostic push
80
+ #pragma GCC diagnostic ignored "-Wpacked"
81
+ #pragma GCC diagnostic ignored "-Wattributes"
82
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
83
+ #pragma GCC diagnostic pop
84
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
85
+ #endif
86
+ #ifndef __UNALIGNED_UINT16_READ
87
+ #pragma GCC diagnostic push
88
+ #pragma GCC diagnostic ignored "-Wpacked"
89
+ #pragma GCC diagnostic ignored "-Wattributes"
90
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
91
+ #pragma GCC diagnostic pop
92
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
93
+ #endif
94
+ #ifndef __UNALIGNED_UINT32_WRITE
95
+ #pragma GCC diagnostic push
96
+ #pragma GCC diagnostic ignored "-Wpacked"
97
+ #pragma GCC diagnostic ignored "-Wattributes"
98
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
99
+ #pragma GCC diagnostic pop
100
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
101
+ #endif
102
+ #ifndef __UNALIGNED_UINT32_READ
103
+ #pragma GCC diagnostic push
104
+ #pragma GCC diagnostic ignored "-Wpacked"
105
+ #pragma GCC diagnostic ignored "-Wattributes"
106
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
107
+ #pragma GCC diagnostic pop
108
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
109
+ #endif
110
+ #ifndef __ALIGNED
111
+ #define __ALIGNED(x) __attribute__((aligned(x)))
112
+ #endif
113
+ #ifndef __RESTRICT
114
+ #define __RESTRICT __restrict
115
+ #endif
116
+ #ifndef __COMPILER_BARRIER
117
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
118
+ #endif
119
+
120
+ /* ######################### Startup and Lowlevel Init ######################## */
121
+
122
+ #ifndef __PROGRAM_START
123
+
124
+ /**
125
+ \brief Initializes data and bss sections
126
+ \details This default implementations initialized all data and additional bss
127
+ sections relying on .copy.table and .zero.table specified properly
128
+ in the used linker script.
129
+
130
+ */
131
+ __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
132
+ {
133
+ extern void _start(void) __NO_RETURN;
134
+
135
+ typedef struct {
136
+ uint32_t const* src;
137
+ uint32_t* dest;
138
+ uint32_t wlen;
139
+ } __copy_table_t;
140
+
141
+ typedef struct {
142
+ uint32_t* dest;
143
+ uint32_t wlen;
144
+ } __zero_table_t;
145
+
146
+ extern const __copy_table_t __copy_table_start__;
147
+ extern const __copy_table_t __copy_table_end__;
148
+ extern const __zero_table_t __zero_table_start__;
149
+ extern const __zero_table_t __zero_table_end__;
150
+
151
+ for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) {
152
+ for(uint32_t i=0u; i<pTable->wlen; ++i) {
153
+ pTable->dest[i] = pTable->src[i];
154
+ }
155
+ }
156
+
157
+ for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) {
158
+ for(uint32_t i=0u; i<pTable->wlen; ++i) {
159
+ pTable->dest[i] = 0u;
160
+ }
161
+ }
162
+
163
+ _start();
164
+ }
165
+
166
+ #define __PROGRAM_START __cmsis_start
167
+ #endif
168
+
169
+ #ifndef __INITIAL_SP
170
+ #define __INITIAL_SP __StackTop
171
+ #endif
172
+
173
+ #ifndef __STACK_LIMIT
174
+ #define __STACK_LIMIT __StackLimit
175
+ #endif
176
+
177
+ #ifndef __VECTOR_TABLE
178
+ #define __VECTOR_TABLE __Vectors
179
+ #endif
180
+
181
+ #ifndef __VECTOR_TABLE_ATTRIBUTE
182
+ #define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors")))
183
+ #endif
184
+
185
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
186
+ #ifndef __STACK_SEAL
187
+ #define __STACK_SEAL __StackSeal
188
+ #endif
189
+
190
+ #ifndef __TZ_STACK_SEAL_SIZE
191
+ #define __TZ_STACK_SEAL_SIZE 8U
192
+ #endif
193
+
194
+ #ifndef __TZ_STACK_SEAL_VALUE
195
+ #define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL
196
+ #endif
197
+
198
+
199
+ __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
200
+ *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
201
+ }
202
+ #endif
203
+
204
+
205
+ /* ########################## Core Instruction Access ######################### */
206
+ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
207
+ Access to dedicated instructions
208
+ @{
209
+ */
210
+
211
+ /* Define macros for porting to both thumb1 and thumb2.
212
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
213
+ * Otherwise, use general registers, specified by constraint "r" */
214
+ #if defined (__thumb__) && !defined (__thumb2__)
215
+ #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
216
+ #define __CMSIS_GCC_RW_REG(r) "+l" (r)
217
+ #define __CMSIS_GCC_USE_REG(r) "l" (r)
218
+ #else
219
+ #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
220
+ #define __CMSIS_GCC_RW_REG(r) "+r" (r)
221
+ #define __CMSIS_GCC_USE_REG(r) "r" (r)
222
+ #endif
223
+
224
+ /**
225
+ \brief No Operation
226
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
227
+ */
228
+ #define __NOP() __ASM volatile ("nop")
229
+
230
+ /**
231
+ \brief Wait For Interrupt
232
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
233
+ */
234
+ #define __WFI() __ASM volatile ("wfi":::"memory")
235
+
236
+
237
+ /**
238
+ \brief Wait For Event
239
+ \details Wait For Event is a hint instruction that permits the processor to enter
240
+ a low-power state until one of a number of events occurs.
241
+ */
242
+ #define __WFE() __ASM volatile ("wfe":::"memory")
243
+
244
+
245
+ /**
246
+ \brief Send Event
247
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
248
+ */
249
+ #define __SEV() __ASM volatile ("sev")
250
+
251
+
252
+ /**
253
+ \brief Instruction Synchronization Barrier
254
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
255
+ so that all instructions following the ISB are fetched from cache or memory,
256
+ after the instruction has been completed.
257
+ */
258
+ __STATIC_FORCEINLINE void __ISB(void)
259
+ {
260
+ __ASM volatile ("isb 0xF":::"memory");
261
+ }
262
+
263
+
264
+ /**
265
+ \brief Data Synchronization Barrier
266
+ \details Acts as a special kind of Data Memory Barrier.
267
+ It completes when all explicit memory accesses before this instruction complete.
268
+ */
269
+ __STATIC_FORCEINLINE void __DSB(void)
270
+ {
271
+ __ASM volatile ("dsb 0xF":::"memory");
272
+ }
273
+
274
+
275
+ /**
276
+ \brief Data Memory Barrier
277
+ \details Ensures the apparent order of the explicit memory operations before
278
+ and after the instruction, without ensuring their completion.
279
+ */
280
+ __STATIC_FORCEINLINE void __DMB(void)
281
+ {
282
+ __ASM volatile ("dmb 0xF":::"memory");
283
+ }
284
+
285
+
286
+ /**
287
+ \brief Reverse byte order (32 bit)
288
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
289
+ \param [in] value Value to reverse
290
+ \return Reversed value
291
+ */
292
+ __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
293
+ {
294
+ #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
295
+ return __builtin_bswap32(value);
296
+ #else
297
+ uint32_t result;
298
+
299
+ __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
300
+ return result;
301
+ #endif
302
+ }
303
+
304
+
305
+ /**
306
+ \brief Reverse byte order (16 bit)
307
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
308
+ \param [in] value Value to reverse
309
+ \return Reversed value
310
+ */
311
+ __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
312
+ {
313
+ uint32_t result;
314
+
315
+ __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
316
+ return result;
317
+ }
318
+
319
+
320
+ /**
321
+ \brief Reverse byte order (16 bit)
322
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
323
+ \param [in] value Value to reverse
324
+ \return Reversed value
325
+ */
326
+ __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
327
+ {
328
+ #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
329
+ return (int16_t)__builtin_bswap16(value);
330
+ #else
331
+ int16_t result;
332
+
333
+ __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
334
+ return result;
335
+ #endif
336
+ }
337
+
338
+
339
+ /**
340
+ \brief Rotate Right in unsigned value (32 bit)
341
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
342
+ \param [in] op1 Value to rotate
343
+ \param [in] op2 Number of Bits to rotate
344
+ \return Rotated value
345
+ */
346
+ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
347
+ {
348
+ op2 %= 32U;
349
+ if (op2 == 0U)
350
+ {
351
+ return op1;
352
+ }
353
+ return (op1 >> op2) | (op1 << (32U - op2));
354
+ }
355
+
356
+
357
+ /**
358
+ \brief Breakpoint
359
+ \details Causes the processor to enter Debug state.
360
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
361
+ \param [in] value is ignored by the processor.
362
+ If required, a debugger can use it to store additional information about the breakpoint.
363
+ */
364
+ #define __BKPT(value) __ASM volatile ("bkpt "#value)
365
+
366
+
367
+ /**
368
+ \brief Reverse bit order of value
369
+ \details Reverses the bit order of the given value.
370
+ \param [in] value Value to reverse
371
+ \return Reversed value
372
+ */
373
+ __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
374
+ {
375
+ uint32_t result;
376
+
377
+ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
378
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
379
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
380
+ __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) );
381
+ #else
382
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
383
+
384
+ result = value; /* r will be reversed bits of v; first get LSB of v */
385
+ for (value >>= 1U; value != 0U; value >>= 1U)
386
+ {
387
+ result <<= 1U;
388
+ result |= value & 1U;
389
+ s--;
390
+ }
391
+ result <<= s; /* shift when v's highest bits are zero */
392
+ #endif
393
+ return result;
394
+ }
395
+
396
+
397
+ /**
398
+ \brief Count leading zeros
399
+ \details Counts the number of leading zeros of a data value.
400
+ \param [in] value Value to count the leading zeros
401
+ \return number of leading zeros in value
402
+ */
403
+ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
404
+ {
405
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
406
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.
407
+ This guarantees ARM-compatible results if happening to compile on a non-ARM
408
+ target, and ensures the compiler doesn't decide to activate any
409
+ optimisations using the logic "value was passed to __builtin_clz, so it
410
+ is non-zero".
411
+ ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
412
+ single CLZ instruction.
413
+ */
414
+ if (value == 0U)
415
+ {
416
+ return 32U;
417
+ }
418
+ return __builtin_clz(value);
419
+ }
420
+
421
+
422
+ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
423
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
424
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
425
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
426
+ /**
427
+ \brief LDR Exclusive (8 bit)
428
+ \details Executes a exclusive LDR instruction for 8 bit value.
429
+ \param [in] ptr Pointer to data
430
+ \return value of type uint8_t at (*ptr)
431
+ */
432
+ __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
433
+ {
434
+ uint32_t result;
435
+
436
+ #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
437
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
438
+ #else
439
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
440
+ accepted by assembler. So has to use following less efficient pattern.
441
+ */
442
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
443
+ #endif
444
+ return ((uint8_t) result); /* Add explicit type cast here */
445
+ }
446
+
447
+
448
+ /**
449
+ \brief LDR Exclusive (16 bit)
450
+ \details Executes a exclusive LDR instruction for 16 bit values.
451
+ \param [in] ptr Pointer to data
452
+ \return value of type uint16_t at (*ptr)
453
+ */
454
+ __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
455
+ {
456
+ uint32_t result;
457
+
458
+ #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
459
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
460
+ #else
461
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
462
+ accepted by assembler. So has to use following less efficient pattern.
463
+ */
464
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
465
+ #endif
466
+ return ((uint16_t) result); /* Add explicit type cast here */
467
+ }
468
+
469
+
470
+ /**
471
+ \brief LDR Exclusive (32 bit)
472
+ \details Executes a exclusive LDR instruction for 32 bit values.
473
+ \param [in] ptr Pointer to data
474
+ \return value of type uint32_t at (*ptr)
475
+ */
476
+ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
477
+ {
478
+ uint32_t result;
479
+
480
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
481
+ return(result);
482
+ }
483
+
484
+
485
+ /**
486
+ \brief STR Exclusive (8 bit)
487
+ \details Executes a exclusive STR instruction for 8 bit values.
488
+ \param [in] value Value to store
489
+ \param [in] ptr Pointer to location
490
+ \return 0 Function succeeded
491
+ \return 1 Function failed
492
+ */
493
+ __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
494
+ {
495
+ uint32_t result;
496
+
497
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
498
+ return(result);
499
+ }
500
+
501
+
502
+ /**
503
+ \brief STR Exclusive (16 bit)
504
+ \details Executes a exclusive STR instruction for 16 bit values.
505
+ \param [in] value Value to store
506
+ \param [in] ptr Pointer to location
507
+ \return 0 Function succeeded
508
+ \return 1 Function failed
509
+ */
510
+ __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
511
+ {
512
+ uint32_t result;
513
+
514
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
515
+ return(result);
516
+ }
517
+
518
+
519
+ /**
520
+ \brief STR Exclusive (32 bit)
521
+ \details Executes a exclusive STR instruction for 32 bit values.
522
+ \param [in] value Value to store
523
+ \param [in] ptr Pointer to location
524
+ \return 0 Function succeeded
525
+ \return 1 Function failed
526
+ */
527
+ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
528
+ {
529
+ uint32_t result;
530
+
531
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
532
+ return(result);
533
+ }
534
+
535
+
536
+ /**
537
+ \brief Remove the exclusive lock
538
+ \details Removes the exclusive lock which is created by LDREX.
539
+ */
540
+ __STATIC_FORCEINLINE void __CLREX(void)
541
+ {
542
+ __ASM volatile ("clrex" ::: "memory");
543
+ }
544
+
545
+ #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
546
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
547
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
548
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
549
+
550
+
551
+ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
552
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
553
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
554
+ /**
555
+ \brief Signed Saturate
556
+ \details Saturates a signed value.
557
+ \param [in] ARG1 Value to be saturated
558
+ \param [in] ARG2 Bit position to saturate to (1..32)
559
+ \return Saturated value
560
+ */
561
+ #define __SSAT(ARG1, ARG2) \
562
+ __extension__ \
563
+ ({ \
564
+ int32_t __RES, __ARG1 = (ARG1); \
565
+ __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
566
+ __RES; \
567
+ })
568
+
569
+
570
+ /**
571
+ \brief Unsigned Saturate
572
+ \details Saturates an unsigned value.
573
+ \param [in] ARG1 Value to be saturated
574
+ \param [in] ARG2 Bit position to saturate to (0..31)
575
+ \return Saturated value
576
+ */
577
+ #define __USAT(ARG1, ARG2) \
578
+ __extension__ \
579
+ ({ \
580
+ uint32_t __RES, __ARG1 = (ARG1); \
581
+ __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
582
+ __RES; \
583
+ })
584
+
585
+
586
+ /**
587
+ \brief Rotate Right with Extend (32 bit)
588
+ \details Moves each bit of a bitstring right by one bit.
589
+ The carry input is shifted in at the left end of the bitstring.
590
+ \param [in] value Value to rotate
591
+ \return Rotated value
592
+ */
593
+ __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
594
+ {
595
+ uint32_t result;
596
+
597
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
598
+ return(result);
599
+ }
600
+
601
+
602
+ /**
603
+ \brief LDRT Unprivileged (8 bit)
604
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
605
+ \param [in] ptr Pointer to data
606
+ \return value of type uint8_t at (*ptr)
607
+ */
608
+ __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
609
+ {
610
+ uint32_t result;
611
+
612
+ #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
613
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
614
+ #else
615
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
616
+ accepted by assembler. So has to use following less efficient pattern.
617
+ */
618
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
619
+ #endif
620
+ return ((uint8_t) result); /* Add explicit type cast here */
621
+ }
622
+
623
+
624
+ /**
625
+ \brief LDRT Unprivileged (16 bit)
626
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
627
+ \param [in] ptr Pointer to data
628
+ \return value of type uint16_t at (*ptr)
629
+ */
630
+ __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
631
+ {
632
+ uint32_t result;
633
+
634
+ #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
635
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
636
+ #else
637
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
638
+ accepted by assembler. So has to use following less efficient pattern.
639
+ */
640
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
641
+ #endif
642
+ return ((uint16_t) result); /* Add explicit type cast here */
643
+ }
644
+
645
+
646
+ /**
647
+ \brief LDRT Unprivileged (32 bit)
648
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
649
+ \param [in] ptr Pointer to data
650
+ \return value of type uint32_t at (*ptr)
651
+ */
652
+ __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
653
+ {
654
+ uint32_t result;
655
+
656
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
657
+ return(result);
658
+ }
659
+
660
+
661
+ /**
662
+ \brief STRT Unprivileged (8 bit)
663
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
664
+ \param [in] value Value to store
665
+ \param [in] ptr Pointer to location
666
+ */
667
+ __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
668
+ {
669
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
670
+ }
671
+
672
+
673
+ /**
674
+ \brief STRT Unprivileged (16 bit)
675
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
676
+ \param [in] value Value to store
677
+ \param [in] ptr Pointer to location
678
+ */
679
+ __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
680
+ {
681
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
682
+ }
683
+
684
+
685
+ /**
686
+ \brief STRT Unprivileged (32 bit)
687
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
688
+ \param [in] value Value to store
689
+ \param [in] ptr Pointer to location
690
+ */
691
+ __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
692
+ {
693
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
694
+ }
695
+
696
+ #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
697
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
698
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
699
+
700
+ /**
701
+ \brief Signed Saturate
702
+ \details Saturates a signed value.
703
+ \param [in] value Value to be saturated
704
+ \param [in] sat Bit position to saturate to (1..32)
705
+ \return Saturated value
706
+ */
707
+ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
708
+ {
709
+ if ((sat >= 1U) && (sat <= 32U))
710
+ {
711
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
712
+ const int32_t min = -1 - max ;
713
+ if (val > max)
714
+ {
715
+ return max;
716
+ }
717
+ else if (val < min)
718
+ {
719
+ return min;
720
+ }
721
+ }
722
+ return val;
723
+ }
724
+
725
+ /**
726
+ \brief Unsigned Saturate
727
+ \details Saturates an unsigned value.
728
+ \param [in] value Value to be saturated
729
+ \param [in] sat Bit position to saturate to (0..31)
730
+ \return Saturated value
731
+ */
732
+ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
733
+ {
734
+ if (sat <= 31U)
735
+ {
736
+ const uint32_t max = ((1U << sat) - 1U);
737
+ if (val > (int32_t)max)
738
+ {
739
+ return max;
740
+ }
741
+ else if (val < 0)
742
+ {
743
+ return 0U;
744
+ }
745
+ }
746
+ return (uint32_t)val;
747
+ }
748
+
749
+ #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
750
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
751
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
752
+
753
+
754
+ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
755
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
756
+ /**
757
+ \brief Load-Acquire (8 bit)
758
+ \details Executes a LDAB instruction for 8 bit value.
759
+ \param [in] ptr Pointer to data
760
+ \return value of type uint8_t at (*ptr)
761
+ */
762
+ __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
763
+ {
764
+ uint32_t result;
765
+
766
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
767
+ return ((uint8_t) result);
768
+ }
769
+
770
+
771
+ /**
772
+ \brief Load-Acquire (16 bit)
773
+ \details Executes a LDAH instruction for 16 bit values.
774
+ \param [in] ptr Pointer to data
775
+ \return value of type uint16_t at (*ptr)
776
+ */
777
+ __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
778
+ {
779
+ uint32_t result;
780
+
781
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
782
+ return ((uint16_t) result);
783
+ }
784
+
785
+
786
+ /**
787
+ \brief Load-Acquire (32 bit)
788
+ \details Executes a LDA instruction for 32 bit values.
789
+ \param [in] ptr Pointer to data
790
+ \return value of type uint32_t at (*ptr)
791
+ */
792
+ __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
793
+ {
794
+ uint32_t result;
795
+
796
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
797
+ return(result);
798
+ }
799
+
800
+
801
+ /**
802
+ \brief Store-Release (8 bit)
803
+ \details Executes a STLB instruction for 8 bit values.
804
+ \param [in] value Value to store
805
+ \param [in] ptr Pointer to location
806
+ */
807
+ __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
808
+ {
809
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
810
+ }
811
+
812
+
813
+ /**
814
+ \brief Store-Release (16 bit)
815
+ \details Executes a STLH instruction for 16 bit values.
816
+ \param [in] value Value to store
817
+ \param [in] ptr Pointer to location
818
+ */
819
+ __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
820
+ {
821
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
822
+ }
823
+
824
+
825
+ /**
826
+ \brief Store-Release (32 bit)
827
+ \details Executes a STL instruction for 32 bit values.
828
+ \param [in] value Value to store
829
+ \param [in] ptr Pointer to location
830
+ */
831
+ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
832
+ {
833
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
834
+ }
835
+
836
+
837
+ /**
838
+ \brief Load-Acquire Exclusive (8 bit)
839
+ \details Executes a LDAB exclusive instruction for 8 bit value.
840
+ \param [in] ptr Pointer to data
841
+ \return value of type uint8_t at (*ptr)
842
+ */
843
+ __STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
844
+ {
845
+ uint32_t result;
846
+
847
+ __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
848
+ return ((uint8_t) result);
849
+ }
850
+
851
+
852
+ /**
853
+ \brief Load-Acquire Exclusive (16 bit)
854
+ \details Executes a LDAH exclusive instruction for 16 bit values.
855
+ \param [in] ptr Pointer to data
856
+ \return value of type uint16_t at (*ptr)
857
+ */
858
+ __STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
859
+ {
860
+ uint32_t result;
861
+
862
+ __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
863
+ return ((uint16_t) result);
864
+ }
865
+
866
+
867
+ /**
868
+ \brief Load-Acquire Exclusive (32 bit)
869
+ \details Executes a LDA exclusive instruction for 32 bit values.
870
+ \param [in] ptr Pointer to data
871
+ \return value of type uint32_t at (*ptr)
872
+ */
873
+ __STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
874
+ {
875
+ uint32_t result;
876
+
877
+ __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
878
+ return(result);
879
+ }
880
+
881
+
882
+ /**
883
+ \brief Store-Release Exclusive (8 bit)
884
+ \details Executes a STLB exclusive instruction for 8 bit values.
885
+ \param [in] value Value to store
886
+ \param [in] ptr Pointer to location
887
+ \return 0 Function succeeded
888
+ \return 1 Function failed
889
+ */
890
+ __STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
891
+ {
892
+ uint32_t result;
893
+
894
+ __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
895
+ return(result);
896
+ }
897
+
898
+
899
+ /**
900
+ \brief Store-Release Exclusive (16 bit)
901
+ \details Executes a STLH exclusive instruction for 16 bit values.
902
+ \param [in] value Value to store
903
+ \param [in] ptr Pointer to location
904
+ \return 0 Function succeeded
905
+ \return 1 Function failed
906
+ */
907
+ __STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
908
+ {
909
+ uint32_t result;
910
+
911
+ __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
912
+ return(result);
913
+ }
914
+
915
+
916
+ /**
917
+ \brief Store-Release Exclusive (32 bit)
918
+ \details Executes a STL exclusive instruction for 32 bit values.
919
+ \param [in] value Value to store
920
+ \param [in] ptr Pointer to location
921
+ \return 0 Function succeeded
922
+ \return 1 Function failed
923
+ */
924
+ __STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
925
+ {
926
+ uint32_t result;
927
+
928
+ __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
929
+ return(result);
930
+ }
931
+
932
+ #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
933
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
934
+
935
+ /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
936
+
937
+
938
+ /* ########################### Core Function Access ########################### */
939
+ /** \ingroup CMSIS_Core_FunctionInterface
940
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
941
+ @{
942
+ */
943
+
944
+ /**
945
+ \brief Enable IRQ Interrupts
946
+ \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
947
+ Can only be executed in Privileged modes.
948
+ */
949
+ // Patched by Edge Impulse, fix for targets that already have __enable_irq
950
+ #ifndef __enable_irq
951
+ __STATIC_FORCEINLINE void __enable_irq(void)
952
+ {
953
+ __ASM volatile ("cpsie i" : : : "memory");
954
+ }
955
+ #endif
956
+
957
+
958
+ /**
959
+ \brief Disable IRQ Interrupts
960
+ \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
961
+ Can only be executed in Privileged modes.
962
+ */
963
+ // Patched by Edge Impulse, fix for targets that already have __disable_irq
964
+ #ifndef __disable_irq
965
+ __STATIC_FORCEINLINE void __disable_irq(void)
966
+ {
967
+ __ASM volatile ("cpsid i" : : : "memory");
968
+ }
969
+ #endif
970
+
971
+
972
+ /**
973
+ \brief Get Control Register
974
+ \details Returns the content of the Control Register.
975
+ \return Control Register value
976
+ */
977
+ __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
978
+ {
979
+ uint32_t result;
980
+
981
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
982
+ return(result);
983
+ }
984
+
985
+
986
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
987
+ /**
988
+ \brief Get Control Register (non-secure)
989
+ \details Returns the content of the non-secure Control Register when in secure mode.
990
+ \return non-secure Control Register value
991
+ */
992
+ __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
993
+ {
994
+ uint32_t result;
995
+
996
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
997
+ return(result);
998
+ }
999
+ #endif
1000
+
1001
+
1002
+ /**
1003
+ \brief Set Control Register
1004
+ \details Writes the given value to the Control Register.
1005
+ \param [in] control Control Register value to set
1006
+ */
1007
+ __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
1008
+ {
1009
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
1010
+ __ISB();
1011
+ }
1012
+
1013
+
1014
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1015
+ /**
1016
+ \brief Set Control Register (non-secure)
1017
+ \details Writes the given value to the non-secure Control Register when in secure state.
1018
+ \param [in] control Control Register value to set
1019
+ */
1020
+ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
1021
+ {
1022
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
1023
+ __ISB();
1024
+ }
1025
+ #endif
1026
+
1027
+
1028
+ /**
1029
+ \brief Get IPSR Register
1030
+ \details Returns the content of the IPSR Register.
1031
+ \return IPSR Register value
1032
+ */
1033
+ __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
1034
+ {
1035
+ uint32_t result;
1036
+
1037
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
1038
+ return(result);
1039
+ }
1040
+
1041
+
1042
+ /**
1043
+ \brief Get APSR Register
1044
+ \details Returns the content of the APSR Register.
1045
+ \return APSR Register value
1046
+ */
1047
+ __STATIC_FORCEINLINE uint32_t __get_APSR(void)
1048
+ {
1049
+ uint32_t result;
1050
+
1051
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
1052
+ return(result);
1053
+ }
1054
+
1055
+
1056
+ /**
1057
+ \brief Get xPSR Register
1058
+ \details Returns the content of the xPSR Register.
1059
+ \return xPSR Register value
1060
+ */
1061
+ __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
1062
+ {
1063
+ uint32_t result;
1064
+
1065
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
1066
+ return(result);
1067
+ }
1068
+
1069
+
1070
+ /**
1071
+ \brief Get Process Stack Pointer
1072
+ \details Returns the current value of the Process Stack Pointer (PSP).
1073
+ \return PSP Register value
1074
+ */
1075
+ __STATIC_FORCEINLINE uint32_t __get_PSP(void)
1076
+ {
1077
+ uint32_t result;
1078
+
1079
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
1080
+ return(result);
1081
+ }
1082
+
1083
+
1084
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1085
+ /**
1086
+ \brief Get Process Stack Pointer (non-secure)
1087
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
1088
+ \return PSP Register value
1089
+ */
1090
+ __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
1091
+ {
1092
+ uint32_t result;
1093
+
1094
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
1095
+ return(result);
1096
+ }
1097
+ #endif
1098
+
1099
+
1100
+ /**
1101
+ \brief Set Process Stack Pointer
1102
+ \details Assigns the given value to the Process Stack Pointer (PSP).
1103
+ \param [in] topOfProcStack Process Stack Pointer value to set
1104
+ */
1105
+ __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
1106
+ {
1107
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
1108
+ }
1109
+
1110
+
1111
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1112
+ /**
1113
+ \brief Set Process Stack Pointer (non-secure)
1114
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
1115
+ \param [in] topOfProcStack Process Stack Pointer value to set
1116
+ */
1117
+ __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
1118
+ {
1119
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
1120
+ }
1121
+ #endif
1122
+
1123
+
1124
+ /**
1125
+ \brief Get Main Stack Pointer
1126
+ \details Returns the current value of the Main Stack Pointer (MSP).
1127
+ \return MSP Register value
1128
+ */
1129
+ __STATIC_FORCEINLINE uint32_t __get_MSP(void)
1130
+ {
1131
+ uint32_t result;
1132
+
1133
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
1134
+ return(result);
1135
+ }
1136
+
1137
+
1138
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1139
+ /**
1140
+ \brief Get Main Stack Pointer (non-secure)
1141
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
1142
+ \return MSP Register value
1143
+ */
1144
+ __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
1145
+ {
1146
+ uint32_t result;
1147
+
1148
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
1149
+ return(result);
1150
+ }
1151
+ #endif
1152
+
1153
+
1154
+ /**
1155
+ \brief Set Main Stack Pointer
1156
+ \details Assigns the given value to the Main Stack Pointer (MSP).
1157
+ \param [in] topOfMainStack Main Stack Pointer value to set
1158
+ */
1159
+ __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
1160
+ {
1161
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
1162
+ }
1163
+
1164
+
1165
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1166
+ /**
1167
+ \brief Set Main Stack Pointer (non-secure)
1168
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
1169
+ \param [in] topOfMainStack Main Stack Pointer value to set
1170
+ */
1171
+ __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
1172
+ {
1173
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
1174
+ }
1175
+ #endif
1176
+
1177
+
1178
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1179
+ /**
1180
+ \brief Get Stack Pointer (non-secure)
1181
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
1182
+ \return SP Register value
1183
+ */
1184
+ __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
1185
+ {
1186
+ uint32_t result;
1187
+
1188
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
1189
+ return(result);
1190
+ }
1191
+
1192
+
1193
+ /**
1194
+ \brief Set Stack Pointer (non-secure)
1195
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
1196
+ \param [in] topOfStack Stack Pointer value to set
1197
+ */
1198
+ __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
1199
+ {
1200
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
1201
+ }
1202
+ #endif
1203
+
1204
+
1205
+ /**
1206
+ \brief Get Priority Mask
1207
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
1208
+ \return Priority Mask value
1209
+ */
1210
+ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
1211
+ {
1212
+ uint32_t result;
1213
+
1214
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
1215
+ return(result);
1216
+ }
1217
+
1218
+
1219
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1220
+ /**
1221
+ \brief Get Priority Mask (non-secure)
1222
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
1223
+ \return Priority Mask value
1224
+ */
1225
+ __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
1226
+ {
1227
+ uint32_t result;
1228
+
1229
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
1230
+ return(result);
1231
+ }
1232
+ #endif
1233
+
1234
+
1235
+ /**
1236
+ \brief Set Priority Mask
1237
+ \details Assigns the given value to the Priority Mask Register.
1238
+ \param [in] priMask Priority Mask
1239
+ */
1240
+ __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
1241
+ {
1242
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
1243
+ }
1244
+
1245
+
1246
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1247
+ /**
1248
+ \brief Set Priority Mask (non-secure)
1249
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
1250
+ \param [in] priMask Priority Mask
1251
+ */
1252
+ __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
1253
+ {
1254
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
1255
+ }
1256
+ #endif
1257
+
1258
+
1259
+ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
1260
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
1261
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
1262
+ /**
1263
+ \brief Enable FIQ
1264
+ \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
1265
+ Can only be executed in Privileged modes.
1266
+ */
1267
+ __STATIC_FORCEINLINE void __enable_fault_irq(void)
1268
+ {
1269
+ __ASM volatile ("cpsie f" : : : "memory");
1270
+ }
1271
+
1272
+
1273
+ /**
1274
+ \brief Disable FIQ
1275
+ \details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
1276
+ Can only be executed in Privileged modes.
1277
+ */
1278
+ __STATIC_FORCEINLINE void __disable_fault_irq(void)
1279
+ {
1280
+ __ASM volatile ("cpsid f" : : : "memory");
1281
+ }
1282
+
1283
+
1284
+ /**
1285
+ \brief Get Base Priority
1286
+ \details Returns the current value of the Base Priority register.
1287
+ \return Base Priority register value
1288
+ */
1289
+ __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
1290
+ {
1291
+ uint32_t result;
1292
+
1293
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
1294
+ return(result);
1295
+ }
1296
+
1297
+
1298
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1299
+ /**
1300
+ \brief Get Base Priority (non-secure)
1301
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
1302
+ \return Base Priority register value
1303
+ */
1304
+ __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
1305
+ {
1306
+ uint32_t result;
1307
+
1308
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
1309
+ return(result);
1310
+ }
1311
+ #endif
1312
+
1313
+
1314
+ /**
1315
+ \brief Set Base Priority
1316
+ \details Assigns the given value to the Base Priority register.
1317
+ \param [in] basePri Base Priority value to set
1318
+ */
1319
+ __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
1320
+ {
1321
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
1322
+ }
1323
+
1324
+
1325
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1326
+ /**
1327
+ \brief Set Base Priority (non-secure)
1328
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
1329
+ \param [in] basePri Base Priority value to set
1330
+ */
1331
+ __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
1332
+ {
1333
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
1334
+ }
1335
+ #endif
1336
+
1337
+
1338
+ /**
1339
+ \brief Set Base Priority with condition
1340
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
1341
+ or the new value increases the BASEPRI priority level.
1342
+ \param [in] basePri Base Priority value to set
1343
+ */
1344
+ __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
1345
+ {
1346
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
1347
+ }
1348
+
1349
+
1350
+ /**
1351
+ \brief Get Fault Mask
1352
+ \details Returns the current value of the Fault Mask register.
1353
+ \return Fault Mask register value
1354
+ */
1355
+ __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
1356
+ {
1357
+ uint32_t result;
1358
+
1359
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
1360
+ return(result);
1361
+ }
1362
+
1363
+
1364
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1365
+ /**
1366
+ \brief Get Fault Mask (non-secure)
1367
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
1368
+ \return Fault Mask register value
1369
+ */
1370
+ __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
1371
+ {
1372
+ uint32_t result;
1373
+
1374
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
1375
+ return(result);
1376
+ }
1377
+ #endif
1378
+
1379
+
1380
+ /**
1381
+ \brief Set Fault Mask
1382
+ \details Assigns the given value to the Fault Mask register.
1383
+ \param [in] faultMask Fault Mask value to set
1384
+ */
1385
+ __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
1386
+ {
1387
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
1388
+ }
1389
+
1390
+
1391
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1392
+ /**
1393
+ \brief Set Fault Mask (non-secure)
1394
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
1395
+ \param [in] faultMask Fault Mask value to set
1396
+ */
1397
+ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
1398
+ {
1399
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
1400
+ }
1401
+ #endif
1402
+
1403
+ #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
1404
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
1405
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
1406
+
1407
+
1408
+ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1409
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
1410
+
1411
+ /**
1412
+ \brief Get Process Stack Pointer Limit
1413
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1414
+ Stack Pointer Limit register hence zero is returned always in non-secure
1415
+ mode.
1416
+
1417
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
1418
+ \return PSPLIM Register value
1419
+ */
1420
+ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
1421
+ {
1422
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
1423
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
1424
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
1425
+ return 0U;
1426
+ #else
1427
+ uint32_t result;
1428
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
1429
+ return result;
1430
+ #endif
1431
+ }
1432
+
1433
+ #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
1434
+ /**
1435
+ \brief Get Process Stack Pointer Limit (non-secure)
1436
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1437
+ Stack Pointer Limit register hence zero is returned always.
1438
+
1439
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
1440
+ \return PSPLIM Register value
1441
+ */
1442
+ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
1443
+ {
1444
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
1445
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
1446
+ return 0U;
1447
+ #else
1448
+ uint32_t result;
1449
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
1450
+ return result;
1451
+ #endif
1452
+ }
1453
+ #endif
1454
+
1455
+
1456
+ /**
1457
+ \brief Set Process Stack Pointer Limit
1458
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1459
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
1460
+ mode.
1461
+
1462
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
1463
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
1464
+ */
1465
+ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
1466
+ {
1467
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
1468
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
1469
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
1470
+ (void)ProcStackPtrLimit;
1471
+ #else
1472
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
1473
+ #endif
1474
+ }
1475
+
1476
+
1477
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1478
+ /**
1479
+ \brief Set Process Stack Pointer (non-secure)
1480
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1481
+ Stack Pointer Limit register hence the write is silently ignored.
1482
+
1483
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
1484
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
1485
+ */
1486
+ __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
1487
+ {
1488
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
1489
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
1490
+ (void)ProcStackPtrLimit;
1491
+ #else
1492
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
1493
+ #endif
1494
+ }
1495
+ #endif
1496
+
1497
+
1498
+ /**
1499
+ \brief Get Main Stack Pointer Limit
1500
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1501
+ Stack Pointer Limit register hence zero is returned always in non-secure
1502
+ mode.
1503
+
1504
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
1505
+ \return MSPLIM Register value
1506
+ */
1507
+ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
1508
+ {
1509
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
1510
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
1511
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
1512
+ return 0U;
1513
+ #else
1514
+ uint32_t result;
1515
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
1516
+ return result;
1517
+ #endif
1518
+ }
1519
+
1520
+
1521
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1522
+ /**
1523
+ \brief Get Main Stack Pointer Limit (non-secure)
1524
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1525
+ Stack Pointer Limit register hence zero is returned always.
1526
+
1527
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
1528
+ \return MSPLIM Register value
1529
+ */
1530
+ __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
1531
+ {
1532
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
1533
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
1534
+ return 0U;
1535
+ #else
1536
+ uint32_t result;
1537
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
1538
+ return result;
1539
+ #endif
1540
+ }
1541
+ #endif
1542
+
1543
+
1544
+ /**
1545
+ \brief Set Main Stack Pointer Limit
1546
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1547
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
1548
+ mode.
1549
+
1550
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
1551
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
1552
+ */
1553
+ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
1554
+ {
1555
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
1556
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
1557
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
1558
+ (void)MainStackPtrLimit;
1559
+ #else
1560
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
1561
+ #endif
1562
+ }
1563
+
1564
+
1565
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1566
+ /**
1567
+ \brief Set Main Stack Pointer Limit (non-secure)
1568
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
1569
+ Stack Pointer Limit register hence the write is silently ignored.
1570
+
1571
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
1572
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
1573
+ */
1574
+ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
1575
+ {
1576
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
1577
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
1578
+ (void)MainStackPtrLimit;
1579
+ #else
1580
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
1581
+ #endif
1582
+ }
1583
+ #endif
1584
+
1585
+ #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
1586
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
1587
+
1588
+
1589
+ /**
1590
+ \brief Get FPSCR
1591
+ \details Returns the current value of the Floating Point Status/Control register.
1592
+ \return Floating Point Status/Control register value
1593
+ */
1594
+ __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
1595
+ {
1596
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
1597
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
1598
+ #if __has_builtin(__builtin_arm_get_fpscr)
1599
+ // Re-enable using built-in when GCC has been fixed
1600
+ // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
1601
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
1602
+ return __builtin_arm_get_fpscr();
1603
+ #else
1604
+ uint32_t result;
1605
+
1606
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
1607
+ return(result);
1608
+ #endif
1609
+ #else
1610
+ return(0U);
1611
+ #endif
1612
+ }
1613
+
1614
+
1615
+ /**
1616
+ \brief Set FPSCR
1617
+ \details Assigns the given value to the Floating Point Status/Control register.
1618
+ \param [in] fpscr Floating Point Status/Control value to set
1619
+ */
1620
+ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
1621
+ {
1622
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
1623
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
1624
+ #if __has_builtin(__builtin_arm_set_fpscr)
1625
+ // Re-enable using built-in when GCC has been fixed
1626
+ // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
1627
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
1628
+ __builtin_arm_set_fpscr(fpscr);
1629
+ #else
1630
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
1631
+ #endif
1632
+ #else
1633
+ (void)fpscr;
1634
+ #endif
1635
+ }
1636
+
1637
+
1638
+ /*@} end of CMSIS_Core_RegAccFunctions */
1639
+
1640
+
1641
+ /* ################### Compiler specific Intrinsics ########################### */
1642
+ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
1643
+ Access to dedicated SIMD instructions
1644
+ @{
1645
+ */
1646
+
1647
+ #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
1648
+
1649
+ __STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
1650
+ {
1651
+ uint32_t result;
1652
+
1653
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1654
+ return(result);
1655
+ }
1656
+
1657
+ __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
1658
+ {
1659
+ uint32_t result;
1660
+
1661
+ __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1662
+ return(result);
1663
+ }
1664
+
1665
+ __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
1666
+ {
1667
+ uint32_t result;
1668
+
1669
+ __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1670
+ return(result);
1671
+ }
1672
+
1673
+ __STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
1674
+ {
1675
+ uint32_t result;
1676
+
1677
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1678
+ return(result);
1679
+ }
1680
+
1681
+ __STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
1682
+ {
1683
+ uint32_t result;
1684
+
1685
+ __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1686
+ return(result);
1687
+ }
1688
+
1689
+ __STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
1690
+ {
1691
+ uint32_t result;
1692
+
1693
+ __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1694
+ return(result);
1695
+ }
1696
+
1697
+
1698
+ __STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
1699
+ {
1700
+ uint32_t result;
1701
+
1702
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1703
+ return(result);
1704
+ }
1705
+
1706
+ __STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
1707
+ {
1708
+ uint32_t result;
1709
+
1710
+ __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1711
+ return(result);
1712
+ }
1713
+
1714
+ __STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
1715
+ {
1716
+ uint32_t result;
1717
+
1718
+ __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1719
+ return(result);
1720
+ }
1721
+
1722
+ __STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
1723
+ {
1724
+ uint32_t result;
1725
+
1726
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1727
+ return(result);
1728
+ }
1729
+
1730
+ __STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
1731
+ {
1732
+ uint32_t result;
1733
+
1734
+ __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1735
+ return(result);
1736
+ }
1737
+
1738
+ __STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
1739
+ {
1740
+ uint32_t result;
1741
+
1742
+ __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1743
+ return(result);
1744
+ }
1745
+
1746
+
1747
+ __STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
1748
+ {
1749
+ uint32_t result;
1750
+
1751
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1752
+ return(result);
1753
+ }
1754
+
1755
+ __STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
1756
+ {
1757
+ uint32_t result;
1758
+
1759
+ __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1760
+ return(result);
1761
+ }
1762
+
1763
+ __STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
1764
+ {
1765
+ uint32_t result;
1766
+
1767
+ __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1768
+ return(result);
1769
+ }
1770
+
1771
+ __STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
1772
+ {
1773
+ uint32_t result;
1774
+
1775
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1776
+ return(result);
1777
+ }
1778
+
1779
+ __STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
1780
+ {
1781
+ uint32_t result;
1782
+
1783
+ __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1784
+ return(result);
1785
+ }
1786
+
1787
+ __STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
1788
+ {
1789
+ uint32_t result;
1790
+
1791
+ __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1792
+ return(result);
1793
+ }
1794
+
1795
+ __STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
1796
+ {
1797
+ uint32_t result;
1798
+
1799
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1800
+ return(result);
1801
+ }
1802
+
1803
+ __STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
1804
+ {
1805
+ uint32_t result;
1806
+
1807
+ __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1808
+ return(result);
1809
+ }
1810
+
1811
+ __STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
1812
+ {
1813
+ uint32_t result;
1814
+
1815
+ __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1816
+ return(result);
1817
+ }
1818
+
1819
+ __STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
1820
+ {
1821
+ uint32_t result;
1822
+
1823
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1824
+ return(result);
1825
+ }
1826
+
1827
+ __STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
1828
+ {
1829
+ uint32_t result;
1830
+
1831
+ __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1832
+ return(result);
1833
+ }
1834
+
1835
+ __STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
1836
+ {
1837
+ uint32_t result;
1838
+
1839
+ __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1840
+ return(result);
1841
+ }
1842
+
1843
+ __STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
1844
+ {
1845
+ uint32_t result;
1846
+
1847
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1848
+ return(result);
1849
+ }
1850
+
1851
+ __STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
1852
+ {
1853
+ uint32_t result;
1854
+
1855
+ __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1856
+ return(result);
1857
+ }
1858
+
1859
+ __STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
1860
+ {
1861
+ uint32_t result;
1862
+
1863
+ __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1864
+ return(result);
1865
+ }
1866
+
1867
+ __STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
1868
+ {
1869
+ uint32_t result;
1870
+
1871
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1872
+ return(result);
1873
+ }
1874
+
1875
+ __STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
1876
+ {
1877
+ uint32_t result;
1878
+
1879
+ __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1880
+ return(result);
1881
+ }
1882
+
1883
+ __STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
1884
+ {
1885
+ uint32_t result;
1886
+
1887
+ __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1888
+ return(result);
1889
+ }
1890
+
1891
+ __STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
1892
+ {
1893
+ uint32_t result;
1894
+
1895
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1896
+ return(result);
1897
+ }
1898
+
1899
+ __STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
1900
+ {
1901
+ uint32_t result;
1902
+
1903
+ __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1904
+ return(result);
1905
+ }
1906
+
1907
+ __STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
1908
+ {
1909
+ uint32_t result;
1910
+
1911
+ __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1912
+ return(result);
1913
+ }
1914
+
1915
+ __STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
1916
+ {
1917
+ uint32_t result;
1918
+
1919
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1920
+ return(result);
1921
+ }
1922
+
1923
+ __STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
1924
+ {
1925
+ uint32_t result;
1926
+
1927
+ __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1928
+ return(result);
1929
+ }
1930
+
1931
+ __STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
1932
+ {
1933
+ uint32_t result;
1934
+
1935
+ __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1936
+ return(result);
1937
+ }
1938
+
1939
+ __STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
1940
+ {
1941
+ uint32_t result;
1942
+
1943
+ __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1944
+ return(result);
1945
+ }
1946
+
1947
+ __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
1948
+ {
1949
+ uint32_t result;
1950
+
1951
+ __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
1952
+ return(result);
1953
+ }
1954
+
1955
+ #define __SSAT16(ARG1, ARG2) \
1956
+ __extension__ \
1957
+ ({ \
1958
+ int32_t __RES, __ARG1 = (ARG1); \
1959
+ __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
1960
+ __RES; \
1961
+ })
1962
+
1963
+ #define __USAT16(ARG1, ARG2) \
1964
+ __extension__ \
1965
+ ({ \
1966
+ uint32_t __RES, __ARG1 = (ARG1); \
1967
+ __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
1968
+ __RES; \
1969
+ })
1970
+
1971
+ __STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
1972
+ {
1973
+ uint32_t result;
1974
+
1975
+ __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
1976
+ return(result);
1977
+ }
1978
+
1979
+ __STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
1980
+ {
1981
+ uint32_t result;
1982
+
1983
+ __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
1984
+ return(result);
1985
+ }
1986
+
1987
+ __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
1988
+ {
1989
+ uint32_t result;
1990
+
1991
+ __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
1992
+ return(result);
1993
+ }
1994
+
1995
+ __STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate)
1996
+ {
1997
+ uint32_t result;
1998
+ if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) {
1999
+ __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) );
2000
+ } else {
2001
+ result = __SXTB16(__ROR(op1, rotate)) ;
2002
+ }
2003
+ return result;
2004
+ }
2005
+
2006
+ __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
2007
+ {
2008
+ uint32_t result;
2009
+
2010
+ __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
2011
+ return(result);
2012
+ }
2013
+
2014
+ __STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate)
2015
+ {
2016
+ uint32_t result;
2017
+ if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) {
2018
+ __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate));
2019
+ } else {
2020
+ result = __SXTAB16(op1, __ROR(op2, rotate));
2021
+ }
2022
+ return result;
2023
+ }
2024
+
2025
+
2026
+ __STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
2027
+ {
2028
+ uint32_t result;
2029
+
2030
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
2031
+ return(result);
2032
+ }
2033
+
2034
+ __STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
2035
+ {
2036
+ uint32_t result;
2037
+
2038
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
2039
+ return(result);
2040
+ }
2041
+
2042
+ __STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
2043
+ {
2044
+ uint32_t result;
2045
+
2046
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
2047
+ return(result);
2048
+ }
2049
+
2050
+ __STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
2051
+ {
2052
+ uint32_t result;
2053
+
2054
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
2055
+ return(result);
2056
+ }
2057
+
2058
+ __STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
2059
+ {
2060
+ union llreg_u{
2061
+ uint32_t w32[2];
2062
+ uint64_t w64;
2063
+ } llr;
2064
+ llr.w64 = acc;
2065
+
2066
+ #ifndef __ARMEB__ /* Little endian */
2067
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
2068
+ #else /* Big endian */
2069
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
2070
+ #endif
2071
+
2072
+ return(llr.w64);
2073
+ }
2074
+
2075
+ __STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
2076
+ {
2077
+ union llreg_u{
2078
+ uint32_t w32[2];
2079
+ uint64_t w64;
2080
+ } llr;
2081
+ llr.w64 = acc;
2082
+
2083
+ #ifndef __ARMEB__ /* Little endian */
2084
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
2085
+ #else /* Big endian */
2086
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
2087
+ #endif
2088
+
2089
+ return(llr.w64);
2090
+ }
2091
+
2092
+ __STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
2093
+ {
2094
+ uint32_t result;
2095
+
2096
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
2097
+ return(result);
2098
+ }
2099
+
2100
+ __STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
2101
+ {
2102
+ uint32_t result;
2103
+
2104
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
2105
+ return(result);
2106
+ }
2107
+
2108
+ __STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
2109
+ {
2110
+ uint32_t result;
2111
+
2112
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
2113
+ return(result);
2114
+ }
2115
+
2116
+ __STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
2117
+ {
2118
+ uint32_t result;
2119
+
2120
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
2121
+ return(result);
2122
+ }
2123
+
2124
+ __STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
2125
+ {
2126
+ union llreg_u{
2127
+ uint32_t w32[2];
2128
+ uint64_t w64;
2129
+ } llr;
2130
+ llr.w64 = acc;
2131
+
2132
+ #ifndef __ARMEB__ /* Little endian */
2133
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
2134
+ #else /* Big endian */
2135
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
2136
+ #endif
2137
+
2138
+ return(llr.w64);
2139
+ }
2140
+
2141
+ __STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
2142
+ {
2143
+ union llreg_u{
2144
+ uint32_t w32[2];
2145
+ uint64_t w64;
2146
+ } llr;
2147
+ llr.w64 = acc;
2148
+
2149
+ #ifndef __ARMEB__ /* Little endian */
2150
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
2151
+ #else /* Big endian */
2152
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
2153
+ #endif
2154
+
2155
+ return(llr.w64);
2156
+ }
2157
+
2158
+ __STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
2159
+ {
2160
+ uint32_t result;
2161
+
2162
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
2163
+ return(result);
2164
+ }
2165
+
2166
+ __STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
2167
+ {
2168
+ int32_t result;
2169
+
2170
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
2171
+ return(result);
2172
+ }
2173
+
2174
+ __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
2175
+ {
2176
+ int32_t result;
2177
+
2178
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
2179
+ return(result);
2180
+ }
2181
+
2182
+
2183
+ #define __PKHBT(ARG1,ARG2,ARG3) \
2184
+ __extension__ \
2185
+ ({ \
2186
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
2187
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
2188
+ __RES; \
2189
+ })
2190
+
2191
+ #define __PKHTB(ARG1,ARG2,ARG3) \
2192
+ __extension__ \
2193
+ ({ \
2194
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
2195
+ if (ARG3 == 0) \
2196
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
2197
+ else \
2198
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
2199
+ __RES; \
2200
+ })
2201
+
2202
+
2203
+ __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
2204
+ {
2205
+ int32_t result;
2206
+
2207
+ __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
2208
+ return(result);
2209
+ }
2210
+
2211
+ #endif /* (__ARM_FEATURE_DSP == 1) */
2212
+ /*@} end of group CMSIS_SIMD_intrinsics */
2213
+
2214
+
2215
+ #pragma GCC diagnostic pop
2216
+
2217
+ #endif /* __CMSIS_GCC_H */
edge-impulse-sdk/CMSIS/Core/Include/cmsis_iccarm.h ADDED
@@ -0,0 +1,1002 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ /**************************************************************************//**
2
+ * @file cmsis_iccarm.h
3
+ * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
4
+ * @version V5.3.0
5
+ * @date 14. April 2021
6
+ ******************************************************************************/
7
+
8
+ //------------------------------------------------------------------------------
9
+ //
10
+ // Copyright (c) 2017-2021 IAR Systems
11
+ // Copyright (c) 2017-2021 Arm Limited. All rights reserved.
12
+ //
13
+ // SPDX-License-Identifier: Apache-2.0
14
+ //
15
+ // Licensed under the Apache License, Version 2.0 (the "License")
16
+ // you may not use this file except in compliance with the License.
17
+ // You may obtain a copy of the License at
18
+ // http://www.apache.org/licenses/LICENSE-2.0
19
+ //
20
+ // Unless required by applicable law or agreed to in writing, software
21
+ // distributed under the License is distributed on an "AS IS" BASIS,
22
+ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23
+ // See the License for the specific language governing permissions and
24
+ // limitations under the License.
25
+ //
26
+ //------------------------------------------------------------------------------
27
+
28
+
29
+ #ifndef __CMSIS_ICCARM_H__
30
+ #define __CMSIS_ICCARM_H__
31
+
32
+ #ifndef __ICCARM__
33
+ #error This file should only be compiled by ICCARM
34
+ #endif
35
+
36
+ #pragma system_include
37
+
38
+ #define __IAR_FT _Pragma("inline=forced") __intrinsic
39
+
40
+ #if (__VER__ >= 8000000)
41
+ #define __ICCARM_V8 1
42
+ #else
43
+ #define __ICCARM_V8 0
44
+ #endif
45
+
46
+ #ifndef __ALIGNED
47
+ #if __ICCARM_V8
48
+ #define __ALIGNED(x) __attribute__((aligned(x)))
49
+ #elif (__VER__ >= 7080000)
50
+ /* Needs IAR language extensions */
51
+ #define __ALIGNED(x) __attribute__((aligned(x)))
52
+ #else
53
+ #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
54
+ #define __ALIGNED(x)
55
+ #endif
56
+ #endif
57
+
58
+
59
+ /* Define compiler macros for CPU architecture, used in CMSIS 5.
60
+ */
61
+ #if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
62
+ /* Macros already defined */
63
+ #else
64
+ #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
65
+ #define __ARM_ARCH_8M_MAIN__ 1
66
+ #elif defined(__ARM8M_BASELINE__)
67
+ #define __ARM_ARCH_8M_BASE__ 1
68
+ #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
69
+ #if __ARM_ARCH == 6
70
+ #define __ARM_ARCH_6M__ 1
71
+ #elif __ARM_ARCH == 7
72
+ #if __ARM_FEATURE_DSP
73
+ #define __ARM_ARCH_7EM__ 1
74
+ #else
75
+ #define __ARM_ARCH_7M__ 1
76
+ #endif
77
+ #endif /* __ARM_ARCH */
78
+ #endif /* __ARM_ARCH_PROFILE == 'M' */
79
+ #endif
80
+
81
+ /* Alternativ core deduction for older ICCARM's */
82
+ #if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
83
+ !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
84
+ #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
85
+ #define __ARM_ARCH_6M__ 1
86
+ #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
87
+ #define __ARM_ARCH_7M__ 1
88
+ #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
89
+ #define __ARM_ARCH_7EM__ 1
90
+ #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
91
+ #define __ARM_ARCH_8M_BASE__ 1
92
+ #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
93
+ #define __ARM_ARCH_8M_MAIN__ 1
94
+ #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
95
+ #define __ARM_ARCH_8M_MAIN__ 1
96
+ #else
97
+ #error "Unknown target."
98
+ #endif
99
+ #endif
100
+
101
+
102
+
103
+ #if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
104
+ #define __IAR_M0_FAMILY 1
105
+ #elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
106
+ #define __IAR_M0_FAMILY 1
107
+ #else
108
+ #define __IAR_M0_FAMILY 0
109
+ #endif
110
+
111
+
112
+ #ifndef __ASM
113
+ #define __ASM __asm
114
+ #endif
115
+
116
+ #ifndef __COMPILER_BARRIER
117
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
118
+ #endif
119
+
120
+ #ifndef __INLINE
121
+ #define __INLINE inline
122
+ #endif
123
+
124
+ #ifndef __NO_RETURN
125
+ #if __ICCARM_V8
126
+ #define __NO_RETURN __attribute__((__noreturn__))
127
+ #else
128
+ #define __NO_RETURN _Pragma("object_attribute=__noreturn")
129
+ #endif
130
+ #endif
131
+
132
+ #ifndef __PACKED
133
+ #if __ICCARM_V8
134
+ #define __PACKED __attribute__((packed, aligned(1)))
135
+ #else
136
+ /* Needs IAR language extensions */
137
+ #define __PACKED __packed
138
+ #endif
139
+ #endif
140
+
141
+ #ifndef __PACKED_STRUCT
142
+ #if __ICCARM_V8
143
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
144
+ #else
145
+ /* Needs IAR language extensions */
146
+ #define __PACKED_STRUCT __packed struct
147
+ #endif
148
+ #endif
149
+
150
+ #ifndef __PACKED_UNION
151
+ #if __ICCARM_V8
152
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
153
+ #else
154
+ /* Needs IAR language extensions */
155
+ #define __PACKED_UNION __packed union
156
+ #endif
157
+ #endif
158
+
159
+ #ifndef __RESTRICT
160
+ #if __ICCARM_V8
161
+ #define __RESTRICT __restrict
162
+ #else
163
+ /* Needs IAR language extensions */
164
+ #define __RESTRICT restrict
165
+ #endif
166
+ #endif
167
+
168
+ #ifndef __STATIC_INLINE
169
+ #define __STATIC_INLINE static inline
170
+ #endif
171
+
172
+ #ifndef __FORCEINLINE
173
+ #define __FORCEINLINE _Pragma("inline=forced")
174
+ #endif
175
+
176
+ #ifndef __STATIC_FORCEINLINE
177
+ #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
178
+ #endif
179
+
180
+ #ifndef __UNALIGNED_UINT16_READ
181
+ #pragma language=save
182
+ #pragma language=extended
183
+ __IAR_FT uint16_t __iar_uint16_read(void const *ptr)
184
+ {
185
+ return *(__packed uint16_t*)(ptr);
186
+ }
187
+ #pragma language=restore
188
+ #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
189
+ #endif
190
+
191
+
192
+ #ifndef __UNALIGNED_UINT16_WRITE
193
+ #pragma language=save
194
+ #pragma language=extended
195
+ __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
196
+ {
197
+ *(__packed uint16_t*)(ptr) = val;;
198
+ }
199
+ #pragma language=restore
200
+ #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
201
+ #endif
202
+
203
+ #ifndef __UNALIGNED_UINT32_READ
204
+ #pragma language=save
205
+ #pragma language=extended
206
+ __IAR_FT uint32_t __iar_uint32_read(void const *ptr)
207
+ {
208
+ return *(__packed uint32_t*)(ptr);
209
+ }
210
+ #pragma language=restore
211
+ #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
212
+ #endif
213
+
214
+ #ifndef __UNALIGNED_UINT32_WRITE
215
+ #pragma language=save
216
+ #pragma language=extended
217
+ __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
218
+ {
219
+ *(__packed uint32_t*)(ptr) = val;;
220
+ }
221
+ #pragma language=restore
222
+ #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
223
+ #endif
224
+
225
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
226
+ #pragma language=save
227
+ #pragma language=extended
228
+ __packed struct __iar_u32 { uint32_t v; };
229
+ #pragma language=restore
230
+ #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
231
+ #endif
232
+
233
+ #ifndef __USED
234
+ #if __ICCARM_V8
235
+ #define __USED __attribute__((used))
236
+ #else
237
+ #define __USED _Pragma("__root")
238
+ #endif
239
+ #endif
240
+
241
+ #undef __WEAK /* undo the definition from DLib_Defaults.h */
242
+ #ifndef __WEAK
243
+ #if __ICCARM_V8
244
+ #define __WEAK __attribute__((weak))
245
+ #else
246
+ #define __WEAK _Pragma("__weak")
247
+ #endif
248
+ #endif
249
+
250
+ #ifndef __PROGRAM_START
251
+ #define __PROGRAM_START __iar_program_start
252
+ #endif
253
+
254
+ #ifndef __INITIAL_SP
255
+ #define __INITIAL_SP CSTACK$$Limit
256
+ #endif
257
+
258
+ #ifndef __STACK_LIMIT
259
+ #define __STACK_LIMIT CSTACK$$Base
260
+ #endif
261
+
262
+ #ifndef __VECTOR_TABLE
263
+ #define __VECTOR_TABLE __vector_table
264
+ #endif
265
+
266
+ #ifndef __VECTOR_TABLE_ATTRIBUTE
267
+ #define __VECTOR_TABLE_ATTRIBUTE @".intvec"
268
+ #endif
269
+
270
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
271
+ #ifndef __STACK_SEAL
272
+ #define __STACK_SEAL STACKSEAL$$Base
273
+ #endif
274
+
275
+ #ifndef __TZ_STACK_SEAL_SIZE
276
+ #define __TZ_STACK_SEAL_SIZE 8U
277
+ #endif
278
+
279
+ #ifndef __TZ_STACK_SEAL_VALUE
280
+ #define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL
281
+ #endif
282
+
283
+ __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
284
+ *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
285
+ }
286
+ #endif
287
+
288
+ #ifndef __ICCARM_INTRINSICS_VERSION__
289
+ #define __ICCARM_INTRINSICS_VERSION__ 0
290
+ #endif
291
+
292
+ #if __ICCARM_INTRINSICS_VERSION__ == 2
293
+
294
+ #if defined(__CLZ)
295
+ #undef __CLZ
296
+ #endif
297
+ #if defined(__REVSH)
298
+ #undef __REVSH
299
+ #endif
300
+ #if defined(__RBIT)
301
+ #undef __RBIT
302
+ #endif
303
+ #if defined(__SSAT)
304
+ #undef __SSAT
305
+ #endif
306
+ #if defined(__USAT)
307
+ #undef __USAT
308
+ #endif
309
+
310
+ #include "iccarm_builtin.h"
311
+
312
+ #define __disable_fault_irq __iar_builtin_disable_fiq
313
+ #define __disable_irq __iar_builtin_disable_interrupt
314
+ #define __enable_fault_irq __iar_builtin_enable_fiq
315
+ #define __enable_irq __iar_builtin_enable_interrupt
316
+ #define __arm_rsr __iar_builtin_rsr
317
+ #define __arm_wsr __iar_builtin_wsr
318
+
319
+
320
+ #define __get_APSR() (__arm_rsr("APSR"))
321
+ #define __get_BASEPRI() (__arm_rsr("BASEPRI"))
322
+ #define __get_CONTROL() (__arm_rsr("CONTROL"))
323
+ #define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
324
+
325
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
326
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
327
+ #define __get_FPSCR() (__arm_rsr("FPSCR"))
328
+ #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
329
+ #else
330
+ #define __get_FPSCR() ( 0 )
331
+ #define __set_FPSCR(VALUE) ((void)VALUE)
332
+ #endif
333
+
334
+ #define __get_IPSR() (__arm_rsr("IPSR"))
335
+ #define __get_MSP() (__arm_rsr("MSP"))
336
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
337
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
338
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
339
+ #define __get_MSPLIM() (0U)
340
+ #else
341
+ #define __get_MSPLIM() (__arm_rsr("MSPLIM"))
342
+ #endif
343
+ #define __get_PRIMASK() (__arm_rsr("PRIMASK"))
344
+ #define __get_PSP() (__arm_rsr("PSP"))
345
+
346
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
347
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
348
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
349
+ #define __get_PSPLIM() (0U)
350
+ #else
351
+ #define __get_PSPLIM() (__arm_rsr("PSPLIM"))
352
+ #endif
353
+
354
+ #define __get_xPSR() (__arm_rsr("xPSR"))
355
+
356
+ #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
357
+ #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
358
+
359
+ __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
360
+ {
361
+ __arm_wsr("CONTROL", control);
362
+ __iar_builtin_ISB();
363
+ }
364
+
365
+ #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
366
+ #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
367
+
368
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
369
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
370
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
371
+ #define __set_MSPLIM(VALUE) ((void)(VALUE))
372
+ #else
373
+ #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
374
+ #endif
375
+ #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
376
+ #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
377
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
378
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
379
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
380
+ #define __set_PSPLIM(VALUE) ((void)(VALUE))
381
+ #else
382
+ #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
383
+ #endif
384
+
385
+ #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
386
+
387
+ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
388
+ {
389
+ __arm_wsr("CONTROL_NS", control);
390
+ __iar_builtin_ISB();
391
+ }
392
+
393
+ #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
394
+ #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
395
+ #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
396
+ #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
397
+ #define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
398
+ #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
399
+ #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
400
+ #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
401
+ #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
402
+ #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
403
+ #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
404
+ #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
405
+
406
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
407
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
408
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
409
+ #define __TZ_get_PSPLIM_NS() (0U)
410
+ #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
411
+ #else
412
+ #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
413
+ #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
414
+ #endif
415
+
416
+ #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
417
+ #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
418
+
419
+ #define __NOP __iar_builtin_no_operation
420
+
421
+ #define __CLZ __iar_builtin_CLZ
422
+ #define __CLREX __iar_builtin_CLREX
423
+
424
+ #define __DMB __iar_builtin_DMB
425
+ #define __DSB __iar_builtin_DSB
426
+ #define __ISB __iar_builtin_ISB
427
+
428
+ #define __LDREXB __iar_builtin_LDREXB
429
+ #define __LDREXH __iar_builtin_LDREXH
430
+ #define __LDREXW __iar_builtin_LDREX
431
+
432
+ #define __RBIT __iar_builtin_RBIT
433
+ #define __REV __iar_builtin_REV
434
+ #define __REV16 __iar_builtin_REV16
435
+
436
+ __IAR_FT int16_t __REVSH(int16_t val)
437
+ {
438
+ return (int16_t) __iar_builtin_REVSH(val);
439
+ }
440
+
441
+ #define __ROR __iar_builtin_ROR
442
+ #define __RRX __iar_builtin_RRX
443
+
444
+ #define __SEV __iar_builtin_SEV
445
+
446
+ #if !__IAR_M0_FAMILY
447
+ #define __SSAT __iar_builtin_SSAT
448
+ #endif
449
+
450
+ #define __STREXB __iar_builtin_STREXB
451
+ #define __STREXH __iar_builtin_STREXH
452
+ #define __STREXW __iar_builtin_STREX
453
+
454
+ #if !__IAR_M0_FAMILY
455
+ #define __USAT __iar_builtin_USAT
456
+ #endif
457
+
458
+ #define __WFE __iar_builtin_WFE
459
+ #define __WFI __iar_builtin_WFI
460
+
461
+ #if __ARM_MEDIA__
462
+ #define __SADD8 __iar_builtin_SADD8
463
+ #define __QADD8 __iar_builtin_QADD8
464
+ #define __SHADD8 __iar_builtin_SHADD8
465
+ #define __UADD8 __iar_builtin_UADD8
466
+ #define __UQADD8 __iar_builtin_UQADD8
467
+ #define __UHADD8 __iar_builtin_UHADD8
468
+ #define __SSUB8 __iar_builtin_SSUB8
469
+ #define __QSUB8 __iar_builtin_QSUB8
470
+ #define __SHSUB8 __iar_builtin_SHSUB8
471
+ #define __USUB8 __iar_builtin_USUB8
472
+ #define __UQSUB8 __iar_builtin_UQSUB8
473
+ #define __UHSUB8 __iar_builtin_UHSUB8
474
+ #define __SADD16 __iar_builtin_SADD16
475
+ #define __QADD16 __iar_builtin_QADD16
476
+ #define __SHADD16 __iar_builtin_SHADD16
477
+ #define __UADD16 __iar_builtin_UADD16
478
+ #define __UQADD16 __iar_builtin_UQADD16
479
+ #define __UHADD16 __iar_builtin_UHADD16
480
+ #define __SSUB16 __iar_builtin_SSUB16
481
+ #define __QSUB16 __iar_builtin_QSUB16
482
+ #define __SHSUB16 __iar_builtin_SHSUB16
483
+ #define __USUB16 __iar_builtin_USUB16
484
+ #define __UQSUB16 __iar_builtin_UQSUB16
485
+ #define __UHSUB16 __iar_builtin_UHSUB16
486
+ #define __SASX __iar_builtin_SASX
487
+ #define __QASX __iar_builtin_QASX
488
+ #define __SHASX __iar_builtin_SHASX
489
+ #define __UASX __iar_builtin_UASX
490
+ #define __UQASX __iar_builtin_UQASX
491
+ #define __UHASX __iar_builtin_UHASX
492
+ #define __SSAX __iar_builtin_SSAX
493
+ #define __QSAX __iar_builtin_QSAX
494
+ #define __SHSAX __iar_builtin_SHSAX
495
+ #define __USAX __iar_builtin_USAX
496
+ #define __UQSAX __iar_builtin_UQSAX
497
+ #define __UHSAX __iar_builtin_UHSAX
498
+ #define __USAD8 __iar_builtin_USAD8
499
+ #define __USADA8 __iar_builtin_USADA8
500
+ #define __SSAT16 __iar_builtin_SSAT16
501
+ #define __USAT16 __iar_builtin_USAT16
502
+ #define __UXTB16 __iar_builtin_UXTB16
503
+ #define __UXTAB16 __iar_builtin_UXTAB16
504
+ #define __SXTB16 __iar_builtin_SXTB16
505
+ #define __SXTAB16 __iar_builtin_SXTAB16
506
+ #define __SMUAD __iar_builtin_SMUAD
507
+ #define __SMUADX __iar_builtin_SMUADX
508
+ #define __SMMLA __iar_builtin_SMMLA
509
+ #define __SMLAD __iar_builtin_SMLAD
510
+ #define __SMLADX __iar_builtin_SMLADX
511
+ #define __SMLALD __iar_builtin_SMLALD
512
+ #define __SMLALDX __iar_builtin_SMLALDX
513
+ #define __SMUSD __iar_builtin_SMUSD
514
+ #define __SMUSDX __iar_builtin_SMUSDX
515
+ #define __SMLSD __iar_builtin_SMLSD
516
+ #define __SMLSDX __iar_builtin_SMLSDX
517
+ #define __SMLSLD __iar_builtin_SMLSLD
518
+ #define __SMLSLDX __iar_builtin_SMLSLDX
519
+ #define __SEL __iar_builtin_SEL
520
+ #define __QADD __iar_builtin_QADD
521
+ #define __QSUB __iar_builtin_QSUB
522
+ #define __PKHBT __iar_builtin_PKHBT
523
+ #define __PKHTB __iar_builtin_PKHTB
524
+ #endif
525
+
526
+ #else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
527
+
528
+ #if __IAR_M0_FAMILY
529
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
530
+ #define __CLZ __cmsis_iar_clz_not_active
531
+ #define __SSAT __cmsis_iar_ssat_not_active
532
+ #define __USAT __cmsis_iar_usat_not_active
533
+ #define __RBIT __cmsis_iar_rbit_not_active
534
+ #define __get_APSR __cmsis_iar_get_APSR_not_active
535
+ #endif
536
+
537
+
538
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
539
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
540
+ #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
541
+ #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
542
+ #endif
543
+
544
+ #ifdef __INTRINSICS_INCLUDED
545
+ #error intrinsics.h is already included previously!
546
+ #endif
547
+
548
+ #include <intrinsics.h>
549
+
550
+ #if __IAR_M0_FAMILY
551
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
552
+ #undef __CLZ
553
+ #undef __SSAT
554
+ #undef __USAT
555
+ #undef __RBIT
556
+ #undef __get_APSR
557
+
558
+ __STATIC_INLINE uint8_t __CLZ(uint32_t data)
559
+ {
560
+ if (data == 0U) { return 32U; }
561
+
562
+ uint32_t count = 0U;
563
+ uint32_t mask = 0x80000000U;
564
+
565
+ while ((data & mask) == 0U)
566
+ {
567
+ count += 1U;
568
+ mask = mask >> 1U;
569
+ }
570
+ return count;
571
+ }
572
+
573
+ __STATIC_INLINE uint32_t __RBIT(uint32_t v)
574
+ {
575
+ uint8_t sc = 31U;
576
+ uint32_t r = v;
577
+ for (v >>= 1U; v; v >>= 1U)
578
+ {
579
+ r <<= 1U;
580
+ r |= v & 1U;
581
+ sc--;
582
+ }
583
+ return (r << sc);
584
+ }
585
+
586
+ __STATIC_INLINE uint32_t __get_APSR(void)
587
+ {
588
+ uint32_t res;
589
+ __asm("MRS %0,APSR" : "=r" (res));
590
+ return res;
591
+ }
592
+
593
+ #endif
594
+
595
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
596
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
597
+ #undef __get_FPSCR
598
+ #undef __set_FPSCR
599
+ #define __get_FPSCR() (0)
600
+ #define __set_FPSCR(VALUE) ((void)VALUE)
601
+ #endif
602
+
603
+ #pragma diag_suppress=Pe940
604
+ #pragma diag_suppress=Pe177
605
+
606
+ #define __enable_irq __enable_interrupt
607
+ #define __disable_irq __disable_interrupt
608
+ #define __NOP __no_operation
609
+
610
+ #define __get_xPSR __get_PSR
611
+
612
+ #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
613
+
614
+ __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
615
+ {
616
+ return __LDREX((unsigned long *)ptr);
617
+ }
618
+
619
+ __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
620
+ {
621
+ return __STREX(value, (unsigned long *)ptr);
622
+ }
623
+ #endif
624
+
625
+
626
+ /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
627
+ #if (__CORTEX_M >= 0x03)
628
+
629
+ __IAR_FT uint32_t __RRX(uint32_t value)
630
+ {
631
+ uint32_t result;
632
+ __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value));
633
+ return(result);
634
+ }
635
+
636
+ __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
637
+ {
638
+ __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
639
+ }
640
+
641
+
642
+ #define __enable_fault_irq __enable_fiq
643
+ #define __disable_fault_irq __disable_fiq
644
+
645
+
646
+ #endif /* (__CORTEX_M >= 0x03) */
647
+
648
+ __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
649
+ {
650
+ return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
651
+ }
652
+
653
+ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
654
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
655
+
656
+ __IAR_FT uint32_t __get_MSPLIM(void)
657
+ {
658
+ uint32_t res;
659
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
660
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
661
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
662
+ res = 0U;
663
+ #else
664
+ __asm volatile("MRS %0,MSPLIM" : "=r" (res));
665
+ #endif
666
+ return res;
667
+ }
668
+
669
+ __IAR_FT void __set_MSPLIM(uint32_t value)
670
+ {
671
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
672
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
673
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
674
+ (void)value;
675
+ #else
676
+ __asm volatile("MSR MSPLIM,%0" :: "r" (value));
677
+ #endif
678
+ }
679
+
680
+ __IAR_FT uint32_t __get_PSPLIM(void)
681
+ {
682
+ uint32_t res;
683
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
684
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
685
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
686
+ res = 0U;
687
+ #else
688
+ __asm volatile("MRS %0,PSPLIM" : "=r" (res));
689
+ #endif
690
+ return res;
691
+ }
692
+
693
+ __IAR_FT void __set_PSPLIM(uint32_t value)
694
+ {
695
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
696
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
697
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
698
+ (void)value;
699
+ #else
700
+ __asm volatile("MSR PSPLIM,%0" :: "r" (value));
701
+ #endif
702
+ }
703
+
704
+ __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
705
+ {
706
+ uint32_t res;
707
+ __asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
708
+ return res;
709
+ }
710
+
711
+ __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
712
+ {
713
+ __asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
714
+ __iar_builtin_ISB();
715
+ }
716
+
717
+ __IAR_FT uint32_t __TZ_get_PSP_NS(void)
718
+ {
719
+ uint32_t res;
720
+ __asm volatile("MRS %0,PSP_NS" : "=r" (res));
721
+ return res;
722
+ }
723
+
724
+ __IAR_FT void __TZ_set_PSP_NS(uint32_t value)
725
+ {
726
+ __asm volatile("MSR PSP_NS,%0" :: "r" (value));
727
+ }
728
+
729
+ __IAR_FT uint32_t __TZ_get_MSP_NS(void)
730
+ {
731
+ uint32_t res;
732
+ __asm volatile("MRS %0,MSP_NS" : "=r" (res));
733
+ return res;
734
+ }
735
+
736
+ __IAR_FT void __TZ_set_MSP_NS(uint32_t value)
737
+ {
738
+ __asm volatile("MSR MSP_NS,%0" :: "r" (value));
739
+ }
740
+
741
+ __IAR_FT uint32_t __TZ_get_SP_NS(void)
742
+ {
743
+ uint32_t res;
744
+ __asm volatile("MRS %0,SP_NS" : "=r" (res));
745
+ return res;
746
+ }
747
+ __IAR_FT void __TZ_set_SP_NS(uint32_t value)
748
+ {
749
+ __asm volatile("MSR SP_NS,%0" :: "r" (value));
750
+ }
751
+
752
+ __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
753
+ {
754
+ uint32_t res;
755
+ __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
756
+ return res;
757
+ }
758
+
759
+ __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
760
+ {
761
+ __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
762
+ }
763
+
764
+ __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
765
+ {
766
+ uint32_t res;
767
+ __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
768
+ return res;
769
+ }
770
+
771
+ __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
772
+ {
773
+ __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
774
+ }
775
+
776
+ __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
777
+ {
778
+ uint32_t res;
779
+ __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
780
+ return res;
781
+ }
782
+
783
+ __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
784
+ {
785
+ __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
786
+ }
787
+
788
+ __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
789
+ {
790
+ uint32_t res;
791
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
792
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
793
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
794
+ res = 0U;
795
+ #else
796
+ __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
797
+ #endif
798
+ return res;
799
+ }
800
+
801
+ __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
802
+ {
803
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
804
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
805
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
806
+ (void)value;
807
+ #else
808
+ __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
809
+ #endif
810
+ }
811
+
812
+ __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
813
+ {
814
+ uint32_t res;
815
+ __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
816
+ return res;
817
+ }
818
+
819
+ __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
820
+ {
821
+ __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
822
+ }
823
+
824
+ #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
825
+
826
+ #endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
827
+
828
+ #define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
829
+
830
+ #if __IAR_M0_FAMILY
831
+ __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
832
+ {
833
+ if ((sat >= 1U) && (sat <= 32U))
834
+ {
835
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
836
+ const int32_t min = -1 - max ;
837
+ if (val > max)
838
+ {
839
+ return max;
840
+ }
841
+ else if (val < min)
842
+ {
843
+ return min;
844
+ }
845
+ }
846
+ return val;
847
+ }
848
+
849
+ __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
850
+ {
851
+ if (sat <= 31U)
852
+ {
853
+ const uint32_t max = ((1U << sat) - 1U);
854
+ if (val > (int32_t)max)
855
+ {
856
+ return max;
857
+ }
858
+ else if (val < 0)
859
+ {
860
+ return 0U;
861
+ }
862
+ }
863
+ return (uint32_t)val;
864
+ }
865
+ #endif
866
+
867
+ #if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
868
+
869
+ __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
870
+ {
871
+ uint32_t res;
872
+ __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
873
+ return ((uint8_t)res);
874
+ }
875
+
876
+ __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
877
+ {
878
+ uint32_t res;
879
+ __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
880
+ return ((uint16_t)res);
881
+ }
882
+
883
+ __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
884
+ {
885
+ uint32_t res;
886
+ __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
887
+ return res;
888
+ }
889
+
890
+ __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
891
+ {
892
+ __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
893
+ }
894
+
895
+ __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
896
+ {
897
+ __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
898
+ }
899
+
900
+ __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
901
+ {
902
+ __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
903
+ }
904
+
905
+ #endif /* (__CORTEX_M >= 0x03) */
906
+
907
+ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
908
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
909
+
910
+
911
+ __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
912
+ {
913
+ uint32_t res;
914
+ __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
915
+ return ((uint8_t)res);
916
+ }
917
+
918
+ __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
919
+ {
920
+ uint32_t res;
921
+ __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
922
+ return ((uint16_t)res);
923
+ }
924
+
925
+ __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
926
+ {
927
+ uint32_t res;
928
+ __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
929
+ return res;
930
+ }
931
+
932
+ __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
933
+ {
934
+ __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
935
+ }
936
+
937
+ __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
938
+ {
939
+ __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
940
+ }
941
+
942
+ __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
943
+ {
944
+ __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
945
+ }
946
+
947
+ __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
948
+ {
949
+ uint32_t res;
950
+ __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
951
+ return ((uint8_t)res);
952
+ }
953
+
954
+ __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
955
+ {
956
+ uint32_t res;
957
+ __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
958
+ return ((uint16_t)res);
959
+ }
960
+
961
+ __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
962
+ {
963
+ uint32_t res;
964
+ __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
965
+ return res;
966
+ }
967
+
968
+ __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
969
+ {
970
+ uint32_t res;
971
+ __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
972
+ return res;
973
+ }
974
+
975
+ __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
976
+ {
977
+ uint32_t res;
978
+ __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
979
+ return res;
980
+ }
981
+
982
+ __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
983
+ {
984
+ uint32_t res;
985
+ __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
986
+ return res;
987
+ }
988
+
989
+ #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
990
+
991
+ #undef __IAR_FT
992
+ #undef __IAR_M0_FAMILY
993
+ #undef __ICCARM_V8
994
+
995
+ #pragma diag_default=Pe940
996
+ #pragma diag_default=Pe177
997
+
998
+ #define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
999
+
1000
+ #define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
1001
+
1002
+ #endif /* __CMSIS_ICCARM_H__ */
edge-impulse-sdk/CMSIS/Core/Include/cmsis_version.h ADDED
@@ -0,0 +1,39 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ /**************************************************************************//**
2
+ * @file cmsis_version.h
3
+ * @brief CMSIS Core(M) Version definitions
4
+ * @version V5.0.5
5
+ * @date 02. February 2022
6
+ ******************************************************************************/
7
+ /*
8
+ * Copyright (c) 2009-2022 ARM Limited. All rights reserved.
9
+ *
10
+ * SPDX-License-Identifier: Apache-2.0
11
+ *
12
+ * Licensed under the Apache License, Version 2.0 (the License); you may
13
+ * not use this file except in compliance with the License.
14
+ * You may obtain a copy of the License at
15
+ *
16
+ * www.apache.org/licenses/LICENSE-2.0
17
+ *
18
+ * Unless required by applicable law or agreed to in writing, software
19
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21
+ * See the License for the specific language governing permissions and
22
+ * limitations under the License.
23
+ */
24
+
25
+ #if defined ( __ICCARM__ )
26
+ #pragma system_include /* treat file as system include file for MISRA check */
27
+ #elif defined (__clang__)
28
+ #pragma clang system_header /* treat file as system include file */
29
+ #endif
30
+
31
+ #ifndef __CMSIS_VERSION_H
32
+ #define __CMSIS_VERSION_H
33
+
34
+ /* CMSIS Version definitions */
35
+ #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
36
+ #define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */
37
+ #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
38
+ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
39
+ #endif
edge-impulse-sdk/CMSIS/Core/Include/core_armv81mml.h ADDED
The diff for this file is too large to render. See raw diff
 
edge-impulse-sdk/CMSIS/Core/Include/core_armv8mbl.h ADDED
The diff for this file is too large to render. See raw diff
 
edge-impulse-sdk/CMSIS/Core/Include/core_armv8mml.h ADDED
The diff for this file is too large to render. See raw diff
 
edge-impulse-sdk/CMSIS/Core/Include/core_cm0.h ADDED
@@ -0,0 +1,952 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ /**************************************************************************//**
2
+ * @file core_cm0.h
3
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
4
+ * @version V5.0.8
5
+ * @date 21. August 2019
6
+ ******************************************************************************/
7
+ /*
8
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
9
+ *
10
+ * SPDX-License-Identifier: Apache-2.0
11
+ *
12
+ * Licensed under the Apache License, Version 2.0 (the License); you may
13
+ * not use this file except in compliance with the License.
14
+ * You may obtain a copy of the License at
15
+ *
16
+ * www.apache.org/licenses/LICENSE-2.0
17
+ *
18
+ * Unless required by applicable law or agreed to in writing, software
19
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21
+ * See the License for the specific language governing permissions and
22
+ * limitations under the License.
23
+ */
24
+
25
+ #if defined ( __ICCARM__ )
26
+ #pragma system_include /* treat file as system include file for MISRA check */
27
+ #elif defined (__clang__)
28
+ #pragma clang system_header /* treat file as system include file */
29
+ #endif
30
+
31
+ #ifndef __CORE_CM0_H_GENERIC
32
+ #define __CORE_CM0_H_GENERIC
33
+
34
+ #include <stdint.h>
35
+
36
+ #ifdef __cplusplus
37
+ extern "C" {
38
+ #endif
39
+
40
+ /**
41
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42
+ CMSIS violates the following MISRA-C:2004 rules:
43
+
44
+ \li Required Rule 8.5, object/function definition in header file.<br>
45
+ Function definitions in header files are used to allow 'inlining'.
46
+
47
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48
+ Unions are used for effective representation of core registers.
49
+
50
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
51
+ Function-like macros are used to allow more efficient code.
52
+ */
53
+
54
+
55
+ /*******************************************************************************
56
+ * CMSIS definitions
57
+ ******************************************************************************/
58
+ /**
59
+ \ingroup Cortex_M0
60
+ @{
61
+ */
62
+
63
+ #include "cmsis_version.h"
64
+
65
+ /* CMSIS CM0 definitions */
66
+ #define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
67
+ #define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
68
+ #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
69
+ __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
70
+
71
+ #define __CORTEX_M (0U) /*!< Cortex-M Core */
72
+
73
+ /** __FPU_USED indicates whether an FPU is used or not.
74
+ This core does not support an FPU at all
75
+ */
76
+ #define __FPU_USED 0U
77
+
78
+ #if defined ( __CC_ARM )
79
+ #if defined __TARGET_FPU_VFP
80
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
81
+ #endif
82
+
83
+ #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
84
+ #if defined __ARM_FP
85
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
86
+ #endif
87
+
88
+ #elif defined ( __GNUC__ )
89
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
90
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
91
+ #endif
92
+
93
+ #elif defined ( __ICCARM__ )
94
+ #if defined __ARMVFP__
95
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
96
+ #endif
97
+
98
+ #elif defined ( __TI_ARM__ )
99
+ #if defined __TI_VFP_SUPPORT__
100
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
101
+ #endif
102
+
103
+ #elif defined ( __TASKING__ )
104
+ #if defined __FPU_VFP__
105
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106
+ #endif
107
+
108
+ #elif defined ( __CSMC__ )
109
+ #if ( __CSMC__ & 0x400U)
110
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
111
+ #endif
112
+
113
+ #endif
114
+
115
+ #include "edge-impulse-sdk/CMSIS/Core/Include/cmsis_compiler.h" /* CMSIS compiler specific defines */
116
+
117
+
118
+ #ifdef __cplusplus
119
+ }
120
+ #endif
121
+
122
+ #endif /* __CORE_CM0_H_GENERIC */
123
+
124
+ #ifndef __CMSIS_GENERIC
125
+
126
+ #ifndef __CORE_CM0_H_DEPENDANT
127
+ #define __CORE_CM0_H_DEPENDANT
128
+
129
+ #ifdef __cplusplus
130
+ extern "C" {
131
+ #endif
132
+
133
+ /* check device defines and use defaults */
134
+ #if defined __CHECK_DEVICE_DEFINES
135
+ #ifndef __CM0_REV
136
+ #define __CM0_REV 0x0000U
137
+ #warning "__CM0_REV not defined in device header file; using default!"
138
+ #endif
139
+
140
+ #ifndef __NVIC_PRIO_BITS
141
+ #define __NVIC_PRIO_BITS 2U
142
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
143
+ #endif
144
+
145
+ #ifndef __Vendor_SysTickConfig
146
+ #define __Vendor_SysTickConfig 0U
147
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
148
+ #endif
149
+ #endif
150
+
151
+ /* IO definitions (access restrictions to peripheral registers) */
152
+ /**
153
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
154
+
155
+ <strong>IO Type Qualifiers</strong> are used
156
+ \li to specify the access to peripheral variables.
157
+ \li for automatic generation of peripheral register debug information.
158
+ */
159
+ #ifdef __cplusplus
160
+ #define __I volatile /*!< Defines 'read only' permissions */
161
+ #else
162
+ #define __I volatile const /*!< Defines 'read only' permissions */
163
+ #endif
164
+ #define __O volatile /*!< Defines 'write only' permissions */
165
+ #define __IO volatile /*!< Defines 'read / write' permissions */
166
+
167
+ /* following defines should be used for structure members */
168
+ #define __IM volatile const /*! Defines 'read only' structure member permissions */
169
+ #define __OM volatile /*! Defines 'write only' structure member permissions */
170
+ #define __IOM volatile /*! Defines 'read / write' structure member permissions */
171
+
172
+ /*@} end of group Cortex_M0 */
173
+
174
+
175
+
176
+ /*******************************************************************************
177
+ * Register Abstraction
178
+ Core Register contain:
179
+ - Core Register
180
+ - Core NVIC Register
181
+ - Core SCB Register
182
+ - Core SysTick Register
183
+ ******************************************************************************/
184
+ /**
185
+ \defgroup CMSIS_core_register Defines and Type Definitions
186
+ \brief Type definitions and defines for Cortex-M processor based devices.
187
+ */
188
+
189
+ /**
190
+ \ingroup CMSIS_core_register
191
+ \defgroup CMSIS_CORE Status and Control Registers
192
+ \brief Core Register type definitions.
193
+ @{
194
+ */
195
+
196
+ /**
197
+ \brief Union type to access the Application Program Status Register (APSR).
198
+ */
199
+ typedef union
200
+ {
201
+ struct
202
+ {
203
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
204
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
205
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
206
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
207
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
208
+ } b; /*!< Structure used for bit access */
209
+ uint32_t w; /*!< Type used for word access */
210
+ } APSR_Type;
211
+
212
+ /* APSR Register Definitions */
213
+ #define APSR_N_Pos 31U /*!< APSR: N Position */
214
+ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
215
+
216
+ #define APSR_Z_Pos 30U /*!< APSR: Z Position */
217
+ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
218
+
219
+ #define APSR_C_Pos 29U /*!< APSR: C Position */
220
+ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
221
+
222
+ #define APSR_V_Pos 28U /*!< APSR: V Position */
223
+ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
224
+
225
+
226
+ /**
227
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
228
+ */
229
+ typedef union
230
+ {
231
+ struct
232
+ {
233
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
234
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
235
+ } b; /*!< Structure used for bit access */
236
+ uint32_t w; /*!< Type used for word access */
237
+ } IPSR_Type;
238
+
239
+ /* IPSR Register Definitions */
240
+ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
241
+ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
242
+
243
+
244
+ /**
245
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
246
+ */
247
+ typedef union
248
+ {
249
+ struct
250
+ {
251
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
252
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
253
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
254
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
255
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
256
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
257
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
258
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
259
+ } b; /*!< Structure used for bit access */
260
+ uint32_t w; /*!< Type used for word access */
261
+ } xPSR_Type;
262
+
263
+ /* xPSR Register Definitions */
264
+ #define xPSR_N_Pos 31U /*!< xPSR: N Position */
265
+ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
266
+
267
+ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
268
+ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
269
+
270
+ #define xPSR_C_Pos 29U /*!< xPSR: C Position */
271
+ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
272
+
273
+ #define xPSR_V_Pos 28U /*!< xPSR: V Position */
274
+ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
275
+
276
+ #define xPSR_T_Pos 24U /*!< xPSR: T Position */
277
+ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
278
+
279
+ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
280
+ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
281
+
282
+
283
+ /**
284
+ \brief Union type to access the Control Registers (CONTROL).
285
+ */
286
+ typedef union
287
+ {
288
+ struct
289
+ {
290
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
291
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
292
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
293
+ } b; /*!< Structure used for bit access */
294
+ uint32_t w; /*!< Type used for word access */
295
+ } CONTROL_Type;
296
+
297
+ /* CONTROL Register Definitions */
298
+ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
299
+ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
300
+
301
+ /*@} end of group CMSIS_CORE */
302
+
303
+
304
+ /**
305
+ \ingroup CMSIS_core_register
306
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
307
+ \brief Type definitions for the NVIC Registers
308
+ @{
309
+ */
310
+
311
+ /**
312
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
313
+ */
314
+ typedef struct
315
+ {
316
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
317
+ uint32_t RESERVED0[31U];
318
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
319
+ uint32_t RESERVED1[31U];
320
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
321
+ uint32_t RESERVED2[31U];
322
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
323
+ uint32_t RESERVED3[31U];
324
+ uint32_t RESERVED4[64U];
325
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
326
+ } NVIC_Type;
327
+
328
+ /*@} end of group CMSIS_NVIC */
329
+
330
+
331
+ /**
332
+ \ingroup CMSIS_core_register
333
+ \defgroup CMSIS_SCB System Control Block (SCB)
334
+ \brief Type definitions for the System Control Block Registers
335
+ @{
336
+ */
337
+
338
+ /**
339
+ \brief Structure type to access the System Control Block (SCB).
340
+ */
341
+ typedef struct
342
+ {
343
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
344
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
345
+ uint32_t RESERVED0;
346
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
347
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
348
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
349
+ uint32_t RESERVED1;
350
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
351
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
352
+ } SCB_Type;
353
+
354
+ /* SCB CPUID Register Definitions */
355
+ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
356
+ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
357
+
358
+ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
359
+ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
360
+
361
+ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
362
+ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
363
+
364
+ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
365
+ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
366
+
367
+ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
368
+ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
369
+
370
+ /* SCB Interrupt Control State Register Definitions */
371
+ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
372
+ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
373
+
374
+ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
375
+ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
376
+
377
+ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
378
+ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
379
+
380
+ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
381
+ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
382
+
383
+ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
384
+ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
385
+
386
+ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
387
+ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
388
+
389
+ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
390
+ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
391
+
392
+ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
393
+ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
394
+
395
+ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
396
+ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
397
+
398
+ /* SCB Application Interrupt and Reset Control Register Definitions */
399
+ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
400
+ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
401
+
402
+ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
403
+ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
404
+
405
+ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
406
+ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
407
+
408
+ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
409
+ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
410
+
411
+ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
412
+ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
413
+
414
+ /* SCB System Control Register Definitions */
415
+ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
416
+ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
417
+
418
+ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
419
+ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
420
+
421
+ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
422
+ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
423
+
424
+ /* SCB Configuration Control Register Definitions */
425
+ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
426
+ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
427
+
428
+ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
429
+ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
430
+
431
+ /* SCB System Handler Control and State Register Definitions */
432
+ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
433
+ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
434
+
435
+ /*@} end of group CMSIS_SCB */
436
+
437
+
438
+ /**
439
+ \ingroup CMSIS_core_register
440
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
441
+ \brief Type definitions for the System Timer Registers.
442
+ @{
443
+ */
444
+
445
+ /**
446
+ \brief Structure type to access the System Timer (SysTick).
447
+ */
448
+ typedef struct
449
+ {
450
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
451
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
452
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
453
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
454
+ } SysTick_Type;
455
+
456
+ /* SysTick Control / Status Register Definitions */
457
+ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
458
+ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
459
+
460
+ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
461
+ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
462
+
463
+ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
464
+ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
465
+
466
+ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
467
+ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
468
+
469
+ /* SysTick Reload Register Definitions */
470
+ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
471
+ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
472
+
473
+ /* SysTick Current Register Definitions */
474
+ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
475
+ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
476
+
477
+ /* SysTick Calibration Register Definitions */
478
+ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
479
+ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
480
+
481
+ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
482
+ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
483
+
484
+ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
485
+ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
486
+
487
+ /*@} end of group CMSIS_SysTick */
488
+
489
+
490
+ /**
491
+ \ingroup CMSIS_core_register
492
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
493
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
494
+ Therefore they are not covered by the Cortex-M0 header file.
495
+ @{
496
+ */
497
+ /*@} end of group CMSIS_CoreDebug */
498
+
499
+
500
+ /**
501
+ \ingroup CMSIS_core_register
502
+ \defgroup CMSIS_core_bitfield Core register bit field macros
503
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
504
+ @{
505
+ */
506
+
507
+ /**
508
+ \brief Mask and shift a bit field value for use in a register bit range.
509
+ \param[in] field Name of the register bit field.
510
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
511
+ \return Masked and shifted value.
512
+ */
513
+ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
514
+
515
+ /**
516
+ \brief Mask and shift a register value to extract a bit filed value.
517
+ \param[in] field Name of the register bit field.
518
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
519
+ \return Masked and shifted bit field value.
520
+ */
521
+ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
522
+
523
+ /*@} end of group CMSIS_core_bitfield */
524
+
525
+
526
+ /**
527
+ \ingroup CMSIS_core_register
528
+ \defgroup CMSIS_core_base Core Definitions
529
+ \brief Definitions for base addresses, unions, and structures.
530
+ @{
531
+ */
532
+
533
+ /* Memory mapping of Core Hardware */
534
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
535
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
536
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
537
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
538
+
539
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
540
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
541
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
542
+
543
+
544
+ /*@} */
545
+
546
+
547
+
548
+ /*******************************************************************************
549
+ * Hardware Abstraction Layer
550
+ Core Function Interface contains:
551
+ - Core NVIC Functions
552
+ - Core SysTick Functions
553
+ - Core Register Access Functions
554
+ ******************************************************************************/
555
+ /**
556
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
557
+ */
558
+
559
+
560
+
561
+ /* ########################## NVIC functions #################################### */
562
+ /**
563
+ \ingroup CMSIS_Core_FunctionInterface
564
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
565
+ \brief Functions that manage interrupts and exceptions via the NVIC.
566
+ @{
567
+ */
568
+
569
+ #ifdef CMSIS_NVIC_VIRTUAL
570
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
571
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
572
+ #endif
573
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
574
+ #else
575
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
576
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
577
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
578
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
579
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
580
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
581
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
582
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
583
+ /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
584
+ #define NVIC_SetPriority __NVIC_SetPriority
585
+ #define NVIC_GetPriority __NVIC_GetPriority
586
+ #define NVIC_SystemReset __NVIC_SystemReset
587
+ #endif /* CMSIS_NVIC_VIRTUAL */
588
+
589
+ #ifdef CMSIS_VECTAB_VIRTUAL
590
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
591
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
592
+ #endif
593
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
594
+ #else
595
+ #define NVIC_SetVector __NVIC_SetVector
596
+ #define NVIC_GetVector __NVIC_GetVector
597
+ #endif /* (CMSIS_VECTAB_VIRTUAL) */
598
+
599
+ #define NVIC_USER_IRQ_OFFSET 16
600
+
601
+
602
+ /* The following EXC_RETURN values are saved the LR on exception entry */
603
+ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
604
+ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
605
+ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
606
+
607
+
608
+ /* Interrupt Priorities are WORD accessible only under Armv6-M */
609
+ /* The following MACROS handle generation of the register offset and byte masks */
610
+ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
611
+ #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
612
+ #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
613
+
614
+ #define __NVIC_SetPriorityGrouping(X) (void)(X)
615
+ #define __NVIC_GetPriorityGrouping() (0U)
616
+
617
+ /**
618
+ \brief Enable Interrupt
619
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
620
+ \param [in] IRQn Device specific interrupt number.
621
+ \note IRQn must not be negative.
622
+ */
623
+ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
624
+ {
625
+ if ((int32_t)(IRQn) >= 0)
626
+ {
627
+ __COMPILER_BARRIER();
628
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
629
+ __COMPILER_BARRIER();
630
+ }
631
+ }
632
+
633
+
634
+ /**
635
+ \brief Get Interrupt Enable status
636
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
637
+ \param [in] IRQn Device specific interrupt number.
638
+ \return 0 Interrupt is not enabled.
639
+ \return 1 Interrupt is enabled.
640
+ \note IRQn must not be negative.
641
+ */
642
+ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
643
+ {
644
+ if ((int32_t)(IRQn) >= 0)
645
+ {
646
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
647
+ }
648
+ else
649
+ {
650
+ return(0U);
651
+ }
652
+ }
653
+
654
+
655
+ /**
656
+ \brief Disable Interrupt
657
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
658
+ \param [in] IRQn Device specific interrupt number.
659
+ \note IRQn must not be negative.
660
+ */
661
+ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
662
+ {
663
+ if ((int32_t)(IRQn) >= 0)
664
+ {
665
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
666
+ __DSB();
667
+ __ISB();
668
+ }
669
+ }
670
+
671
+
672
+ /**
673
+ \brief Get Pending Interrupt
674
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
675
+ \param [in] IRQn Device specific interrupt number.
676
+ \return 0 Interrupt status is not pending.
677
+ \return 1 Interrupt status is pending.
678
+ \note IRQn must not be negative.
679
+ */
680
+ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
681
+ {
682
+ if ((int32_t)(IRQn) >= 0)
683
+ {
684
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
685
+ }
686
+ else
687
+ {
688
+ return(0U);
689
+ }
690
+ }
691
+
692
+
693
+ /**
694
+ \brief Set Pending Interrupt
695
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
696
+ \param [in] IRQn Device specific interrupt number.
697
+ \note IRQn must not be negative.
698
+ */
699
+ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
700
+ {
701
+ if ((int32_t)(IRQn) >= 0)
702
+ {
703
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
704
+ }
705
+ }
706
+
707
+
708
+ /**
709
+ \brief Clear Pending Interrupt
710
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
711
+ \param [in] IRQn Device specific interrupt number.
712
+ \note IRQn must not be negative.
713
+ */
714
+ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
715
+ {
716
+ if ((int32_t)(IRQn) >= 0)
717
+ {
718
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
719
+ }
720
+ }
721
+
722
+
723
+ /**
724
+ \brief Set Interrupt Priority
725
+ \details Sets the priority of a device specific interrupt or a processor exception.
726
+ The interrupt number can be positive to specify a device specific interrupt,
727
+ or negative to specify a processor exception.
728
+ \param [in] IRQn Interrupt number.
729
+ \param [in] priority Priority to set.
730
+ \note The priority cannot be set for every processor exception.
731
+ */
732
+ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
733
+ {
734
+ if ((int32_t)(IRQn) >= 0)
735
+ {
736
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
737
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
738
+ }
739
+ else
740
+ {
741
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
742
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
743
+ }
744
+ }
745
+
746
+
747
+ /**
748
+ \brief Get Interrupt Priority
749
+ \details Reads the priority of a device specific interrupt or a processor exception.
750
+ The interrupt number can be positive to specify a device specific interrupt,
751
+ or negative to specify a processor exception.
752
+ \param [in] IRQn Interrupt number.
753
+ \return Interrupt Priority.
754
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
755
+ */
756
+ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
757
+ {
758
+
759
+ if ((int32_t)(IRQn) >= 0)
760
+ {
761
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
762
+ }
763
+ else
764
+ {
765
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
766
+ }
767
+ }
768
+
769
+
770
+ /**
771
+ \brief Encode Priority
772
+ \details Encodes the priority for an interrupt with the given priority group,
773
+ preemptive priority value, and subpriority value.
774
+ In case of a conflict between priority grouping and available
775
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
776
+ \param [in] PriorityGroup Used priority group.
777
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
778
+ \param [in] SubPriority Subpriority value (starting from 0).
779
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
780
+ */
781
+ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
782
+ {
783
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
784
+ uint32_t PreemptPriorityBits;
785
+ uint32_t SubPriorityBits;
786
+
787
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
788
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
789
+
790
+ return (
791
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
792
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
793
+ );
794
+ }
795
+
796
+
797
+ /**
798
+ \brief Decode Priority
799
+ \details Decodes an interrupt priority value with a given priority group to
800
+ preemptive priority value and subpriority value.
801
+ In case of a conflict between priority grouping and available
802
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
803
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
804
+ \param [in] PriorityGroup Used priority group.
805
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
806
+ \param [out] pSubPriority Subpriority value (starting from 0).
807
+ */
808
+ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
809
+ {
810
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
811
+ uint32_t PreemptPriorityBits;
812
+ uint32_t SubPriorityBits;
813
+
814
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
815
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
816
+
817
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
818
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
819
+ }
820
+
821
+
822
+
823
+ /**
824
+ \brief Set Interrupt Vector
825
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
826
+ The interrupt number can be positive to specify a device specific interrupt,
827
+ or negative to specify a processor exception.
828
+ Address 0 must be mapped to SRAM.
829
+ \param [in] IRQn Interrupt number
830
+ \param [in] vector Address of interrupt handler function
831
+ */
832
+ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
833
+ {
834
+ uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
835
+ *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */
836
+ /* ARM Application Note 321 states that the M0 does not require the architectural barrier */
837
+ }
838
+
839
+
840
+ /**
841
+ \brief Get Interrupt Vector
842
+ \details Reads an interrupt vector from interrupt vector table.
843
+ The interrupt number can be positive to specify a device specific interrupt,
844
+ or negative to specify a processor exception.
845
+ \param [in] IRQn Interrupt number.
846
+ \return Address of interrupt handler function
847
+ */
848
+ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
849
+ {
850
+ uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
851
+ return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */
852
+ }
853
+
854
+
855
+ /**
856
+ \brief System Reset
857
+ \details Initiates a system reset request to reset the MCU.
858
+ */
859
+ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
860
+ {
861
+ __DSB(); /* Ensure all outstanding memory accesses included
862
+ buffered write are completed before reset */
863
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
864
+ SCB_AIRCR_SYSRESETREQ_Msk);
865
+ __DSB(); /* Ensure completion of memory access */
866
+
867
+ for(;;) /* wait until reset */
868
+ {
869
+ __NOP();
870
+ }
871
+ }
872
+
873
+ /*@} end of CMSIS_Core_NVICFunctions */
874
+
875
+
876
+ /* ########################## FPU functions #################################### */
877
+ /**
878
+ \ingroup CMSIS_Core_FunctionInterface
879
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
880
+ \brief Function that provides FPU type.
881
+ @{
882
+ */
883
+
884
+ /**
885
+ \brief get FPU type
886
+ \details returns the FPU type
887
+ \returns
888
+ - \b 0: No FPU
889
+ - \b 1: Single precision FPU
890
+ - \b 2: Double + Single precision FPU
891
+ */
892
+ __STATIC_INLINE uint32_t SCB_GetFPUType(void)
893
+ {
894
+ return 0U; /* No FPU */
895
+ }
896
+
897
+
898
+ /*@} end of CMSIS_Core_FpuFunctions */
899
+
900
+
901
+
902
+ /* ################################## SysTick function ############################################ */
903
+ /**
904
+ \ingroup CMSIS_Core_FunctionInterface
905
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
906
+ \brief Functions that configure the System.
907
+ @{
908
+ */
909
+
910
+ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
911
+
912
+ /**
913
+ \brief System Tick Configuration
914
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
915
+ Counter is in free running mode to generate periodic interrupts.
916
+ \param [in] ticks Number of ticks between two interrupts.
917
+ \return 0 Function succeeded.
918
+ \return 1 Function failed.
919
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
920
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
921
+ must contain a vendor-specific implementation of this function.
922
+ */
923
+ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
924
+ {
925
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
926
+ {
927
+ return (1UL); /* Reload value impossible */
928
+ }
929
+
930
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
931
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
932
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
933
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
934
+ SysTick_CTRL_TICKINT_Msk |
935
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
936
+ return (0UL); /* Function successful */
937
+ }
938
+
939
+ #endif
940
+
941
+ /*@} end of CMSIS_Core_SysTickFunctions */
942
+
943
+
944
+
945
+
946
+ #ifdef __cplusplus
947
+ }
948
+ #endif
949
+
950
+ #endif /* __CORE_CM0_H_DEPENDANT */
951
+
952
+ #endif /* __CMSIS_GENERIC */
edge-impulse-sdk/CMSIS/Core/Include/core_cm0plus.h ADDED
@@ -0,0 +1,1087 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ /**************************************************************************//**
2
+ * @file core_cm0plus.h
3
+ * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
4
+ * @version V5.0.9
5
+ * @date 21. August 2019
6
+ ******************************************************************************/
7
+ /*
8
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
9
+ *
10
+ * SPDX-License-Identifier: Apache-2.0
11
+ *
12
+ * Licensed under the Apache License, Version 2.0 (the License); you may
13
+ * not use this file except in compliance with the License.
14
+ * You may obtain a copy of the License at
15
+ *
16
+ * www.apache.org/licenses/LICENSE-2.0
17
+ *
18
+ * Unless required by applicable law or agreed to in writing, software
19
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21
+ * See the License for the specific language governing permissions and
22
+ * limitations under the License.
23
+ */
24
+
25
+ #if defined ( __ICCARM__ )
26
+ #pragma system_include /* treat file as system include file for MISRA check */
27
+ #elif defined (__clang__)
28
+ #pragma clang system_header /* treat file as system include file */
29
+ #endif
30
+
31
+ #ifndef __CORE_CM0PLUS_H_GENERIC
32
+ #define __CORE_CM0PLUS_H_GENERIC
33
+
34
+ #include <stdint.h>
35
+
36
+ #ifdef __cplusplus
37
+ extern "C" {
38
+ #endif
39
+
40
+ /**
41
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42
+ CMSIS violates the following MISRA-C:2004 rules:
43
+
44
+ \li Required Rule 8.5, object/function definition in header file.<br>
45
+ Function definitions in header files are used to allow 'inlining'.
46
+
47
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48
+ Unions are used for effective representation of core registers.
49
+
50
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
51
+ Function-like macros are used to allow more efficient code.
52
+ */
53
+
54
+
55
+ /*******************************************************************************
56
+ * CMSIS definitions
57
+ ******************************************************************************/
58
+ /**
59
+ \ingroup Cortex-M0+
60
+ @{
61
+ */
62
+
63
+ #include "cmsis_version.h"
64
+
65
+ /* CMSIS CM0+ definitions */
66
+ #define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
67
+ #define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
68
+ #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
69
+ __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
70
+
71
+ #define __CORTEX_M (0U) /*!< Cortex-M Core */
72
+
73
+ /** __FPU_USED indicates whether an FPU is used or not.
74
+ This core does not support an FPU at all
75
+ */
76
+ #define __FPU_USED 0U
77
+
78
+ #if defined ( __CC_ARM )
79
+ #if defined __TARGET_FPU_VFP
80
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
81
+ #endif
82
+
83
+ #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
84
+ #if defined __ARM_FP
85
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
86
+ #endif
87
+
88
+ #elif defined ( __GNUC__ )
89
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
90
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
91
+ #endif
92
+
93
+ #elif defined ( __ICCARM__ )
94
+ #if defined __ARMVFP__
95
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
96
+ #endif
97
+
98
+ #elif defined ( __TI_ARM__ )
99
+ #if defined __TI_VFP_SUPPORT__
100
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
101
+ #endif
102
+
103
+ #elif defined ( __TASKING__ )
104
+ #if defined __FPU_VFP__
105
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106
+ #endif
107
+
108
+ #elif defined ( __CSMC__ )
109
+ #if ( __CSMC__ & 0x400U)
110
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
111
+ #endif
112
+
113
+ #endif
114
+
115
+ #include "edge-impulse-sdk/CMSIS/Core/Include/cmsis_compiler.h" /* CMSIS compiler specific defines */
116
+
117
+
118
+ #ifdef __cplusplus
119
+ }
120
+ #endif
121
+
122
+ #endif /* __CORE_CM0PLUS_H_GENERIC */
123
+
124
+ #ifndef __CMSIS_GENERIC
125
+
126
+ #ifndef __CORE_CM0PLUS_H_DEPENDANT
127
+ #define __CORE_CM0PLUS_H_DEPENDANT
128
+
129
+ #ifdef __cplusplus
130
+ extern "C" {
131
+ #endif
132
+
133
+ /* check device defines and use defaults */
134
+ #if defined __CHECK_DEVICE_DEFINES
135
+ #ifndef __CM0PLUS_REV
136
+ #define __CM0PLUS_REV 0x0000U
137
+ #warning "__CM0PLUS_REV not defined in device header file; using default!"
138
+ #endif
139
+
140
+ #ifndef __MPU_PRESENT
141
+ #define __MPU_PRESENT 0U
142
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
143
+ #endif
144
+
145
+ #ifndef __VTOR_PRESENT
146
+ #define __VTOR_PRESENT 0U
147
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
148
+ #endif
149
+
150
+ #ifndef __NVIC_PRIO_BITS
151
+ #define __NVIC_PRIO_BITS 2U
152
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
153
+ #endif
154
+
155
+ #ifndef __Vendor_SysTickConfig
156
+ #define __Vendor_SysTickConfig 0U
157
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
158
+ #endif
159
+ #endif
160
+
161
+ /* IO definitions (access restrictions to peripheral registers) */
162
+ /**
163
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
164
+
165
+ <strong>IO Type Qualifiers</strong> are used
166
+ \li to specify the access to peripheral variables.
167
+ \li for automatic generation of peripheral register debug information.
168
+ */
169
+ #ifdef __cplusplus
170
+ #define __I volatile /*!< Defines 'read only' permissions */
171
+ #else
172
+ #define __I volatile const /*!< Defines 'read only' permissions */
173
+ #endif
174
+ #define __O volatile /*!< Defines 'write only' permissions */
175
+ #define __IO volatile /*!< Defines 'read / write' permissions */
176
+
177
+ /* following defines should be used for structure members */
178
+ #define __IM volatile const /*! Defines 'read only' structure member permissions */
179
+ #define __OM volatile /*! Defines 'write only' structure member permissions */
180
+ #define __IOM volatile /*! Defines 'read / write' structure member permissions */
181
+
182
+ /*@} end of group Cortex-M0+ */
183
+
184
+
185
+
186
+ /*******************************************************************************
187
+ * Register Abstraction
188
+ Core Register contain:
189
+ - Core Register
190
+ - Core NVIC Register
191
+ - Core SCB Register
192
+ - Core SysTick Register
193
+ - Core MPU Register
194
+ ******************************************************************************/
195
+ /**
196
+ \defgroup CMSIS_core_register Defines and Type Definitions
197
+ \brief Type definitions and defines for Cortex-M processor based devices.
198
+ */
199
+
200
+ /**
201
+ \ingroup CMSIS_core_register
202
+ \defgroup CMSIS_CORE Status and Control Registers
203
+ \brief Core Register type definitions.
204
+ @{
205
+ */
206
+
207
+ /**
208
+ \brief Union type to access the Application Program Status Register (APSR).
209
+ */
210
+ typedef union
211
+ {
212
+ struct
213
+ {
214
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
215
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
216
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
217
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
218
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
219
+ } b; /*!< Structure used for bit access */
220
+ uint32_t w; /*!< Type used for word access */
221
+ } APSR_Type;
222
+
223
+ /* APSR Register Definitions */
224
+ #define APSR_N_Pos 31U /*!< APSR: N Position */
225
+ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
226
+
227
+ #define APSR_Z_Pos 30U /*!< APSR: Z Position */
228
+ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
229
+
230
+ #define APSR_C_Pos 29U /*!< APSR: C Position */
231
+ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
232
+
233
+ #define APSR_V_Pos 28U /*!< APSR: V Position */
234
+ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
235
+
236
+
237
+ /**
238
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
239
+ */
240
+ typedef union
241
+ {
242
+ struct
243
+ {
244
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
245
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
246
+ } b; /*!< Structure used for bit access */
247
+ uint32_t w; /*!< Type used for word access */
248
+ } IPSR_Type;
249
+
250
+ /* IPSR Register Definitions */
251
+ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
252
+ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
253
+
254
+
255
+ /**
256
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
257
+ */
258
+ typedef union
259
+ {
260
+ struct
261
+ {
262
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
263
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
264
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
265
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
266
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
267
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
268
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
269
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
270
+ } b; /*!< Structure used for bit access */
271
+ uint32_t w; /*!< Type used for word access */
272
+ } xPSR_Type;
273
+
274
+ /* xPSR Register Definitions */
275
+ #define xPSR_N_Pos 31U /*!< xPSR: N Position */
276
+ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
277
+
278
+ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
279
+ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
280
+
281
+ #define xPSR_C_Pos 29U /*!< xPSR: C Position */
282
+ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
283
+
284
+ #define xPSR_V_Pos 28U /*!< xPSR: V Position */
285
+ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
286
+
287
+ #define xPSR_T_Pos 24U /*!< xPSR: T Position */
288
+ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
289
+
290
+ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
291
+ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
292
+
293
+
294
+ /**
295
+ \brief Union type to access the Control Registers (CONTROL).
296
+ */
297
+ typedef union
298
+ {
299
+ struct
300
+ {
301
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
302
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
303
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
304
+ } b; /*!< Structure used for bit access */
305
+ uint32_t w; /*!< Type used for word access */
306
+ } CONTROL_Type;
307
+
308
+ /* CONTROL Register Definitions */
309
+ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
310
+ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
311
+
312
+ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
313
+ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
314
+
315
+ /*@} end of group CMSIS_CORE */
316
+
317
+
318
+ /**
319
+ \ingroup CMSIS_core_register
320
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
321
+ \brief Type definitions for the NVIC Registers
322
+ @{
323
+ */
324
+
325
+ /**
326
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
327
+ */
328
+ typedef struct
329
+ {
330
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
331
+ uint32_t RESERVED0[31U];
332
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
333
+ uint32_t RESERVED1[31U];
334
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
335
+ uint32_t RESERVED2[31U];
336
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
337
+ uint32_t RESERVED3[31U];
338
+ uint32_t RESERVED4[64U];
339
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
340
+ } NVIC_Type;
341
+
342
+ /*@} end of group CMSIS_NVIC */
343
+
344
+
345
+ /**
346
+ \ingroup CMSIS_core_register
347
+ \defgroup CMSIS_SCB System Control Block (SCB)
348
+ \brief Type definitions for the System Control Block Registers
349
+ @{
350
+ */
351
+
352
+ /**
353
+ \brief Structure type to access the System Control Block (SCB).
354
+ */
355
+ typedef struct
356
+ {
357
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
358
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
359
+ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
360
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
361
+ #else
362
+ uint32_t RESERVED0;
363
+ #endif
364
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
365
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
366
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
367
+ uint32_t RESERVED1;
368
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
369
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
370
+ } SCB_Type;
371
+
372
+ /* SCB CPUID Register Definitions */
373
+ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
374
+ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
375
+
376
+ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
377
+ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
378
+
379
+ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
380
+ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
381
+
382
+ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
383
+ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
384
+
385
+ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
386
+ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
387
+
388
+ /* SCB Interrupt Control State Register Definitions */
389
+ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
390
+ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
391
+
392
+ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
393
+ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
394
+
395
+ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
396
+ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
397
+
398
+ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
399
+ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
400
+
401
+ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
402
+ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
403
+
404
+ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
405
+ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
406
+
407
+ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
408
+ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
409
+
410
+ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
411
+ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
412
+
413
+ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
414
+ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
415
+
416
+ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
417
+ /* SCB Interrupt Control State Register Definitions */
418
+ #define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
419
+ #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
420
+ #endif
421
+
422
+ /* SCB Application Interrupt and Reset Control Register Definitions */
423
+ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
424
+ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
425
+
426
+ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
427
+ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
428
+
429
+ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
430
+ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
431
+
432
+ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
433
+ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
434
+
435
+ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
436
+ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
437
+
438
+ /* SCB System Control Register Definitions */
439
+ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
440
+ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
441
+
442
+ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
443
+ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
444
+
445
+ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
446
+ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
447
+
448
+ /* SCB Configuration Control Register Definitions */
449
+ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
450
+ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
451
+
452
+ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
453
+ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
454
+
455
+ /* SCB System Handler Control and State Register Definitions */
456
+ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
457
+ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
458
+
459
+ /*@} end of group CMSIS_SCB */
460
+
461
+
462
+ /**
463
+ \ingroup CMSIS_core_register
464
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
465
+ \brief Type definitions for the System Timer Registers.
466
+ @{
467
+ */
468
+
469
+ /**
470
+ \brief Structure type to access the System Timer (SysTick).
471
+ */
472
+ typedef struct
473
+ {
474
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
475
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
476
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
477
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
478
+ } SysTick_Type;
479
+
480
+ /* SysTick Control / Status Register Definitions */
481
+ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
482
+ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
483
+
484
+ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
485
+ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
486
+
487
+ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
488
+ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
489
+
490
+ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
491
+ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
492
+
493
+ /* SysTick Reload Register Definitions */
494
+ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
495
+ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
496
+
497
+ /* SysTick Current Register Definitions */
498
+ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
499
+ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
500
+
501
+ /* SysTick Calibration Register Definitions */
502
+ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
503
+ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
504
+
505
+ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
506
+ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
507
+
508
+ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
509
+ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
510
+
511
+ /*@} end of group CMSIS_SysTick */
512
+
513
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
514
+ /**
515
+ \ingroup CMSIS_core_register
516
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
517
+ \brief Type definitions for the Memory Protection Unit (MPU)
518
+ @{
519
+ */
520
+
521
+ /**
522
+ \brief Structure type to access the Memory Protection Unit (MPU).
523
+ */
524
+ typedef struct
525
+ {
526
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
527
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
528
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
529
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
530
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
531
+ } MPU_Type;
532
+
533
+ #define MPU_TYPE_RALIASES 1U
534
+
535
+ /* MPU Type Register Definitions */
536
+ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
537
+ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
538
+
539
+ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
540
+ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
541
+
542
+ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
543
+ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
544
+
545
+ /* MPU Control Register Definitions */
546
+ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
547
+ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
548
+
549
+ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
550
+ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
551
+
552
+ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
553
+ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
554
+
555
+ /* MPU Region Number Register Definitions */
556
+ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
557
+ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
558
+
559
+ /* MPU Region Base Address Register Definitions */
560
+ #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
561
+ #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
562
+
563
+ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
564
+ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
565
+
566
+ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
567
+ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
568
+
569
+ /* MPU Region Attribute and Size Register Definitions */
570
+ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
571
+ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
572
+
573
+ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
574
+ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
575
+
576
+ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
577
+ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
578
+
579
+ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
580
+ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
581
+
582
+ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
583
+ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
584
+
585
+ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
586
+ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
587
+
588
+ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
589
+ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
590
+
591
+ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
592
+ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
593
+
594
+ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
595
+ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
596
+
597
+ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
598
+ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
599
+
600
+ /*@} end of group CMSIS_MPU */
601
+ #endif
602
+
603
+
604
+ /**
605
+ \ingroup CMSIS_core_register
606
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
607
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
608
+ Therefore they are not covered by the Cortex-M0+ header file.
609
+ @{
610
+ */
611
+ /*@} end of group CMSIS_CoreDebug */
612
+
613
+
614
+ /**
615
+ \ingroup CMSIS_core_register
616
+ \defgroup CMSIS_core_bitfield Core register bit field macros
617
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
618
+ @{
619
+ */
620
+
621
+ /**
622
+ \brief Mask and shift a bit field value for use in a register bit range.
623
+ \param[in] field Name of the register bit field.
624
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
625
+ \return Masked and shifted value.
626
+ */
627
+ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
628
+
629
+ /**
630
+ \brief Mask and shift a register value to extract a bit filed value.
631
+ \param[in] field Name of the register bit field.
632
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
633
+ \return Masked and shifted bit field value.
634
+ */
635
+ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
636
+
637
+ /*@} end of group CMSIS_core_bitfield */
638
+
639
+
640
+ /**
641
+ \ingroup CMSIS_core_register
642
+ \defgroup CMSIS_core_base Core Definitions
643
+ \brief Definitions for base addresses, unions, and structures.
644
+ @{
645
+ */
646
+
647
+ /* Memory mapping of Core Hardware */
648
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
649
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
650
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
651
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
652
+
653
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
654
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
655
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
656
+
657
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
658
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
659
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
660
+ #endif
661
+
662
+ /*@} */
663
+
664
+
665
+
666
+ /*******************************************************************************
667
+ * Hardware Abstraction Layer
668
+ Core Function Interface contains:
669
+ - Core NVIC Functions
670
+ - Core SysTick Functions
671
+ - Core Register Access Functions
672
+ ******************************************************************************/
673
+ /**
674
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
675
+ */
676
+
677
+
678
+
679
+ /* ########################## NVIC functions #################################### */
680
+ /**
681
+ \ingroup CMSIS_Core_FunctionInterface
682
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
683
+ \brief Functions that manage interrupts and exceptions via the NVIC.
684
+ @{
685
+ */
686
+
687
+ #ifdef CMSIS_NVIC_VIRTUAL
688
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
689
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
690
+ #endif
691
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
692
+ #else
693
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
694
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
695
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
696
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
697
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
698
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
699
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
700
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
701
+ /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
702
+ #define NVIC_SetPriority __NVIC_SetPriority
703
+ #define NVIC_GetPriority __NVIC_GetPriority
704
+ #define NVIC_SystemReset __NVIC_SystemReset
705
+ #endif /* CMSIS_NVIC_VIRTUAL */
706
+
707
+ #ifdef CMSIS_VECTAB_VIRTUAL
708
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
709
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
710
+ #endif
711
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
712
+ #else
713
+ #define NVIC_SetVector __NVIC_SetVector
714
+ #define NVIC_GetVector __NVIC_GetVector
715
+ #endif /* (CMSIS_VECTAB_VIRTUAL) */
716
+
717
+ #define NVIC_USER_IRQ_OFFSET 16
718
+
719
+
720
+ /* The following EXC_RETURN values are saved the LR on exception entry */
721
+ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
722
+ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
723
+ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
724
+
725
+
726
+ /* Interrupt Priorities are WORD accessible only under Armv6-M */
727
+ /* The following MACROS handle generation of the register offset and byte masks */
728
+ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
729
+ #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
730
+ #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
731
+
732
+ #define __NVIC_SetPriorityGrouping(X) (void)(X)
733
+ #define __NVIC_GetPriorityGrouping() (0U)
734
+
735
+ /**
736
+ \brief Enable Interrupt
737
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
738
+ \param [in] IRQn Device specific interrupt number.
739
+ \note IRQn must not be negative.
740
+ */
741
+ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
742
+ {
743
+ if ((int32_t)(IRQn) >= 0)
744
+ {
745
+ __COMPILER_BARRIER();
746
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
747
+ __COMPILER_BARRIER();
748
+ }
749
+ }
750
+
751
+
752
+ /**
753
+ \brief Get Interrupt Enable status
754
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
755
+ \param [in] IRQn Device specific interrupt number.
756
+ \return 0 Interrupt is not enabled.
757
+ \return 1 Interrupt is enabled.
758
+ \note IRQn must not be negative.
759
+ */
760
+ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
761
+ {
762
+ if ((int32_t)(IRQn) >= 0)
763
+ {
764
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
765
+ }
766
+ else
767
+ {
768
+ return(0U);
769
+ }
770
+ }
771
+
772
+
773
+ /**
774
+ \brief Disable Interrupt
775
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
776
+ \param [in] IRQn Device specific interrupt number.
777
+ \note IRQn must not be negative.
778
+ */
779
+ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
780
+ {
781
+ if ((int32_t)(IRQn) >= 0)
782
+ {
783
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
784
+ __DSB();
785
+ __ISB();
786
+ }
787
+ }
788
+
789
+
790
+ /**
791
+ \brief Get Pending Interrupt
792
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
793
+ \param [in] IRQn Device specific interrupt number.
794
+ \return 0 Interrupt status is not pending.
795
+ \return 1 Interrupt status is pending.
796
+ \note IRQn must not be negative.
797
+ */
798
+ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
799
+ {
800
+ if ((int32_t)(IRQn) >= 0)
801
+ {
802
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
803
+ }
804
+ else
805
+ {
806
+ return(0U);
807
+ }
808
+ }
809
+
810
+
811
+ /**
812
+ \brief Set Pending Interrupt
813
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
814
+ \param [in] IRQn Device specific interrupt number.
815
+ \note IRQn must not be negative.
816
+ */
817
+ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
818
+ {
819
+ if ((int32_t)(IRQn) >= 0)
820
+ {
821
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
822
+ }
823
+ }
824
+
825
+
826
+ /**
827
+ \brief Clear Pending Interrupt
828
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
829
+ \param [in] IRQn Device specific interrupt number.
830
+ \note IRQn must not be negative.
831
+ */
832
+ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
833
+ {
834
+ if ((int32_t)(IRQn) >= 0)
835
+ {
836
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
837
+ }
838
+ }
839
+
840
+
841
+ /**
842
+ \brief Set Interrupt Priority
843
+ \details Sets the priority of a device specific interrupt or a processor exception.
844
+ The interrupt number can be positive to specify a device specific interrupt,
845
+ or negative to specify a processor exception.
846
+ \param [in] IRQn Interrupt number.
847
+ \param [in] priority Priority to set.
848
+ \note The priority cannot be set for every processor exception.
849
+ */
850
+ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
851
+ {
852
+ if ((int32_t)(IRQn) >= 0)
853
+ {
854
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
855
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
856
+ }
857
+ else
858
+ {
859
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
860
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
861
+ }
862
+ }
863
+
864
+
865
+ /**
866
+ \brief Get Interrupt Priority
867
+ \details Reads the priority of a device specific interrupt or a processor exception.
868
+ The interrupt number can be positive to specify a device specific interrupt,
869
+ or negative to specify a processor exception.
870
+ \param [in] IRQn Interrupt number.
871
+ \return Interrupt Priority.
872
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
873
+ */
874
+ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
875
+ {
876
+
877
+ if ((int32_t)(IRQn) >= 0)
878
+ {
879
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
880
+ }
881
+ else
882
+ {
883
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
884
+ }
885
+ }
886
+
887
+
888
+ /**
889
+ \brief Encode Priority
890
+ \details Encodes the priority for an interrupt with the given priority group,
891
+ preemptive priority value, and subpriority value.
892
+ In case of a conflict between priority grouping and available
893
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
894
+ \param [in] PriorityGroup Used priority group.
895
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
896
+ \param [in] SubPriority Subpriority value (starting from 0).
897
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
898
+ */
899
+ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
900
+ {
901
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
902
+ uint32_t PreemptPriorityBits;
903
+ uint32_t SubPriorityBits;
904
+
905
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
906
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
907
+
908
+ return (
909
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
910
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
911
+ );
912
+ }
913
+
914
+
915
+ /**
916
+ \brief Decode Priority
917
+ \details Decodes an interrupt priority value with a given priority group to
918
+ preemptive priority value and subpriority value.
919
+ In case of a conflict between priority grouping and available
920
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
921
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
922
+ \param [in] PriorityGroup Used priority group.
923
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
924
+ \param [out] pSubPriority Subpriority value (starting from 0).
925
+ */
926
+ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
927
+ {
928
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
929
+ uint32_t PreemptPriorityBits;
930
+ uint32_t SubPriorityBits;
931
+
932
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
933
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
934
+
935
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
936
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
937
+ }
938
+
939
+
940
+ /**
941
+ \brief Set Interrupt Vector
942
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
943
+ The interrupt number can be positive to specify a device specific interrupt,
944
+ or negative to specify a processor exception.
945
+ VTOR must been relocated to SRAM before.
946
+ If VTOR is not present address 0 must be mapped to SRAM.
947
+ \param [in] IRQn Interrupt number
948
+ \param [in] vector Address of interrupt handler function
949
+ */
950
+ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
951
+ {
952
+ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
953
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
954
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
955
+ #else
956
+ uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
957
+ *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */
958
+ #endif
959
+ /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */
960
+ }
961
+
962
+
963
+ /**
964
+ \brief Get Interrupt Vector
965
+ \details Reads an interrupt vector from interrupt vector table.
966
+ The interrupt number can be positive to specify a device specific interrupt,
967
+ or negative to specify a processor exception.
968
+ \param [in] IRQn Interrupt number.
969
+ \return Address of interrupt handler function
970
+ */
971
+ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
972
+ {
973
+ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
974
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
975
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
976
+ #else
977
+ uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
978
+ return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */
979
+ #endif
980
+ }
981
+
982
+
983
+ /**
984
+ \brief System Reset
985
+ \details Initiates a system reset request to reset the MCU.
986
+ */
987
+ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
988
+ {
989
+ __DSB(); /* Ensure all outstanding memory accesses included
990
+ buffered write are completed before reset */
991
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
992
+ SCB_AIRCR_SYSRESETREQ_Msk);
993
+ __DSB(); /* Ensure completion of memory access */
994
+
995
+ for(;;) /* wait until reset */
996
+ {
997
+ __NOP();
998
+ }
999
+ }
1000
+
1001
+ /*@} end of CMSIS_Core_NVICFunctions */
1002
+
1003
+ /* ########################## MPU functions #################################### */
1004
+
1005
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1006
+
1007
+ #include "mpu_armv7.h"
1008
+
1009
+ #endif
1010
+
1011
+ /* ########################## FPU functions #################################### */
1012
+ /**
1013
+ \ingroup CMSIS_Core_FunctionInterface
1014
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
1015
+ \brief Function that provides FPU type.
1016
+ @{
1017
+ */
1018
+
1019
+ /**
1020
+ \brief get FPU type
1021
+ \details returns the FPU type
1022
+ \returns
1023
+ - \b 0: No FPU
1024
+ - \b 1: Single precision FPU
1025
+ - \b 2: Double + Single precision FPU
1026
+ */
1027
+ __STATIC_INLINE uint32_t SCB_GetFPUType(void)
1028
+ {
1029
+ return 0U; /* No FPU */
1030
+ }
1031
+
1032
+
1033
+ /*@} end of CMSIS_Core_FpuFunctions */
1034
+
1035
+
1036
+
1037
+ /* ################################## SysTick function ############################################ */
1038
+ /**
1039
+ \ingroup CMSIS_Core_FunctionInterface
1040
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
1041
+ \brief Functions that configure the System.
1042
+ @{
1043
+ */
1044
+
1045
+ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
1046
+
1047
+ /**
1048
+ \brief System Tick Configuration
1049
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
1050
+ Counter is in free running mode to generate periodic interrupts.
1051
+ \param [in] ticks Number of ticks between two interrupts.
1052
+ \return 0 Function succeeded.
1053
+ \return 1 Function failed.
1054
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
1055
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
1056
+ must contain a vendor-specific implementation of this function.
1057
+ */
1058
+ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1059
+ {
1060
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
1061
+ {
1062
+ return (1UL); /* Reload value impossible */
1063
+ }
1064
+
1065
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
1066
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
1067
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
1068
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1069
+ SysTick_CTRL_TICKINT_Msk |
1070
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1071
+ return (0UL); /* Function successful */
1072
+ }
1073
+
1074
+ #endif
1075
+
1076
+ /*@} end of CMSIS_Core_SysTickFunctions */
1077
+
1078
+
1079
+
1080
+
1081
+ #ifdef __cplusplus
1082
+ }
1083
+ #endif
1084
+
1085
+ #endif /* __CORE_CM0PLUS_H_DEPENDANT */
1086
+
1087
+ #endif /* __CMSIS_GENERIC */
edge-impulse-sdk/CMSIS/Core/Include/core_cm1.h ADDED
@@ -0,0 +1,979 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ /**************************************************************************//**
2
+ * @file core_cm1.h
3
+ * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
4
+ * @version V1.0.1
5
+ * @date 12. November 2018
6
+ ******************************************************************************/
7
+ /*
8
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
9
+ *
10
+ * SPDX-License-Identifier: Apache-2.0
11
+ *
12
+ * Licensed under the Apache License, Version 2.0 (the License); you may
13
+ * not use this file except in compliance with the License.
14
+ * You may obtain a copy of the License at
15
+ *
16
+ * www.apache.org/licenses/LICENSE-2.0
17
+ *
18
+ * Unless required by applicable law or agreed to in writing, software
19
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21
+ * See the License for the specific language governing permissions and
22
+ * limitations under the License.
23
+ */
24
+
25
+ #if defined ( __ICCARM__ )
26
+ #pragma system_include /* treat file as system include file for MISRA check */
27
+ #elif defined (__clang__)
28
+ #pragma clang system_header /* treat file as system include file */
29
+ #endif
30
+
31
+ #ifndef __CORE_CM1_H_GENERIC
32
+ #define __CORE_CM1_H_GENERIC
33
+
34
+ #include <stdint.h>
35
+
36
+ #ifdef __cplusplus
37
+ extern "C" {
38
+ #endif
39
+
40
+ /**
41
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42
+ CMSIS violates the following MISRA-C:2004 rules:
43
+
44
+ \li Required Rule 8.5, object/function definition in header file.<br>
45
+ Function definitions in header files are used to allow 'inlining'.
46
+
47
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48
+ Unions are used for effective representation of core registers.
49
+
50
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
51
+ Function-like macros are used to allow more efficient code.
52
+ */
53
+
54
+
55
+ /*******************************************************************************
56
+ * CMSIS definitions
57
+ ******************************************************************************/
58
+ /**
59
+ \ingroup Cortex_M1
60
+ @{
61
+ */
62
+
63
+ #include "cmsis_version.h"
64
+
65
+ /* CMSIS CM1 definitions */
66
+ #define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
67
+ #define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
68
+ #define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
69
+ __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
70
+
71
+ #define __CORTEX_M (1U) /*!< Cortex-M Core */
72
+
73
+ /** __FPU_USED indicates whether an FPU is used or not.
74
+ This core does not support an FPU at all
75
+ */
76
+ #define __FPU_USED 0U
77
+
78
+ #if defined ( __CC_ARM )
79
+ #if defined __TARGET_FPU_VFP
80
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
81
+ #endif
82
+
83
+ #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
84
+ #if defined __ARM_FP
85
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
86
+ #endif
87
+
88
+ #elif defined ( __GNUC__ )
89
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
90
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
91
+ #endif
92
+
93
+ #elif defined ( __ICCARM__ )
94
+ #if defined __ARMVFP__
95
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
96
+ #endif
97
+
98
+ #elif defined ( __TI_ARM__ )
99
+ #if defined __TI_VFP_SUPPORT__
100
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
101
+ #endif
102
+
103
+ #elif defined ( __TASKING__ )
104
+ #if defined __FPU_VFP__
105
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106
+ #endif
107
+
108
+ #elif defined ( __CSMC__ )
109
+ #if ( __CSMC__ & 0x400U)
110
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
111
+ #endif
112
+
113
+ #endif
114
+
115
+ #include "edge-impulse-sdk/CMSIS/Core/Include/cmsis_compiler.h" /* CMSIS compiler specific defines */
116
+
117
+
118
+ #ifdef __cplusplus
119
+ }
120
+ #endif
121
+
122
+ #endif /* __CORE_CM1_H_GENERIC */
123
+
124
+ #ifndef __CMSIS_GENERIC
125
+
126
+ #ifndef __CORE_CM1_H_DEPENDANT
127
+ #define __CORE_CM1_H_DEPENDANT
128
+
129
+ #ifdef __cplusplus
130
+ extern "C" {
131
+ #endif
132
+
133
+ /* check device defines and use defaults */
134
+ #if defined __CHECK_DEVICE_DEFINES
135
+ #ifndef __CM1_REV
136
+ #define __CM1_REV 0x0100U
137
+ #warning "__CM1_REV not defined in device header file; using default!"
138
+ #endif
139
+
140
+ #ifndef __NVIC_PRIO_BITS
141
+ #define __NVIC_PRIO_BITS 2U
142
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
143
+ #endif
144
+
145
+ #ifndef __Vendor_SysTickConfig
146
+ #define __Vendor_SysTickConfig 0U
147
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
148
+ #endif
149
+ #endif
150
+
151
+ /* IO definitions (access restrictions to peripheral registers) */
152
+ /**
153
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
154
+
155
+ <strong>IO Type Qualifiers</strong> are used
156
+ \li to specify the access to peripheral variables.
157
+ \li for automatic generation of peripheral register debug information.
158
+ */
159
+ #ifdef __cplusplus
160
+ #define __I volatile /*!< Defines 'read only' permissions */
161
+ #else
162
+ #define __I volatile const /*!< Defines 'read only' permissions */
163
+ #endif
164
+ #define __O volatile /*!< Defines 'write only' permissions */
165
+ #define __IO volatile /*!< Defines 'read / write' permissions */
166
+
167
+ /* following defines should be used for structure members */
168
+ #define __IM volatile const /*! Defines 'read only' structure member permissions */
169
+ #define __OM volatile /*! Defines 'write only' structure member permissions */
170
+ #define __IOM volatile /*! Defines 'read / write' structure member permissions */
171
+
172
+ /*@} end of group Cortex_M1 */
173
+
174
+
175
+
176
+ /*******************************************************************************
177
+ * Register Abstraction
178
+ Core Register contain:
179
+ - Core Register
180
+ - Core NVIC Register
181
+ - Core SCB Register
182
+ - Core SysTick Register
183
+ ******************************************************************************/
184
+ /**
185
+ \defgroup CMSIS_core_register Defines and Type Definitions
186
+ \brief Type definitions and defines for Cortex-M processor based devices.
187
+ */
188
+
189
+ /**
190
+ \ingroup CMSIS_core_register
191
+ \defgroup CMSIS_CORE Status and Control Registers
192
+ \brief Core Register type definitions.
193
+ @{
194
+ */
195
+
196
+ /**
197
+ \brief Union type to access the Application Program Status Register (APSR).
198
+ */
199
+ typedef union
200
+ {
201
+ struct
202
+ {
203
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
204
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
205
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
206
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
207
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
208
+ } b; /*!< Structure used for bit access */
209
+ uint32_t w; /*!< Type used for word access */
210
+ } APSR_Type;
211
+
212
+ /* APSR Register Definitions */
213
+ #define APSR_N_Pos 31U /*!< APSR: N Position */
214
+ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
215
+
216
+ #define APSR_Z_Pos 30U /*!< APSR: Z Position */
217
+ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
218
+
219
+ #define APSR_C_Pos 29U /*!< APSR: C Position */
220
+ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
221
+
222
+ #define APSR_V_Pos 28U /*!< APSR: V Position */
223
+ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
224
+
225
+
226
+ /**
227
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
228
+ */
229
+ typedef union
230
+ {
231
+ struct
232
+ {
233
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
234
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
235
+ } b; /*!< Structure used for bit access */
236
+ uint32_t w; /*!< Type used for word access */
237
+ } IPSR_Type;
238
+
239
+ /* IPSR Register Definitions */
240
+ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
241
+ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
242
+
243
+
244
+ /**
245
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
246
+ */
247
+ typedef union
248
+ {
249
+ struct
250
+ {
251
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
252
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
253
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
254
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
255
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
256
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
257
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
258
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
259
+ } b; /*!< Structure used for bit access */
260
+ uint32_t w; /*!< Type used for word access */
261
+ } xPSR_Type;
262
+
263
+ /* xPSR Register Definitions */
264
+ #define xPSR_N_Pos 31U /*!< xPSR: N Position */
265
+ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
266
+
267
+ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
268
+ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
269
+
270
+ #define xPSR_C_Pos 29U /*!< xPSR: C Position */
271
+ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
272
+
273
+ #define xPSR_V_Pos 28U /*!< xPSR: V Position */
274
+ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
275
+
276
+ #define xPSR_T_Pos 24U /*!< xPSR: T Position */
277
+ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
278
+
279
+ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
280
+ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
281
+
282
+
283
+ /**
284
+ \brief Union type to access the Control Registers (CONTROL).
285
+ */
286
+ typedef union
287
+ {
288
+ struct
289
+ {
290
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
291
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
292
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
293
+ } b; /*!< Structure used for bit access */
294
+ uint32_t w; /*!< Type used for word access */
295
+ } CONTROL_Type;
296
+
297
+ /* CONTROL Register Definitions */
298
+ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
299
+ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
300
+
301
+ /*@} end of group CMSIS_CORE */
302
+
303
+
304
+ /**
305
+ \ingroup CMSIS_core_register
306
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
307
+ \brief Type definitions for the NVIC Registers
308
+ @{
309
+ */
310
+
311
+ /**
312
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
313
+ */
314
+ typedef struct
315
+ {
316
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
317
+ uint32_t RESERVED0[31U];
318
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
319
+ uint32_t RSERVED1[31U];
320
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
321
+ uint32_t RESERVED2[31U];
322
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
323
+ uint32_t RESERVED3[31U];
324
+ uint32_t RESERVED4[64U];
325
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
326
+ } NVIC_Type;
327
+
328
+ /*@} end of group CMSIS_NVIC */
329
+
330
+
331
+ /**
332
+ \ingroup CMSIS_core_register
333
+ \defgroup CMSIS_SCB System Control Block (SCB)
334
+ \brief Type definitions for the System Control Block Registers
335
+ @{
336
+ */
337
+
338
+ /**
339
+ \brief Structure type to access the System Control Block (SCB).
340
+ */
341
+ typedef struct
342
+ {
343
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
344
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
345
+ uint32_t RESERVED0;
346
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
347
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
348
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
349
+ uint32_t RESERVED1;
350
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
351
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
352
+ } SCB_Type;
353
+
354
+ /* SCB CPUID Register Definitions */
355
+ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
356
+ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
357
+
358
+ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
359
+ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
360
+
361
+ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
362
+ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
363
+
364
+ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
365
+ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
366
+
367
+ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
368
+ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
369
+
370
+ /* SCB Interrupt Control State Register Definitions */
371
+ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
372
+ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
373
+
374
+ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
375
+ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
376
+
377
+ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
378
+ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
379
+
380
+ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
381
+ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
382
+
383
+ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
384
+ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
385
+
386
+ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
387
+ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
388
+
389
+ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
390
+ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
391
+
392
+ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
393
+ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
394
+
395
+ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
396
+ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
397
+
398
+ /* SCB Application Interrupt and Reset Control Register Definitions */
399
+ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
400
+ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
401
+
402
+ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
403
+ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
404
+
405
+ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
406
+ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
407
+
408
+ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
409
+ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
410
+
411
+ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
412
+ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
413
+
414
+ /* SCB System Control Register Definitions */
415
+ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
416
+ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
417
+
418
+ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
419
+ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
420
+
421
+ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
422
+ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
423
+
424
+ /* SCB Configuration Control Register Definitions */
425
+ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
426
+ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
427
+
428
+ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
429
+ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
430
+
431
+ /* SCB System Handler Control and State Register Definitions */
432
+ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
433
+ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
434
+
435
+ /*@} end of group CMSIS_SCB */
436
+
437
+
438
+ /**
439
+ \ingroup CMSIS_core_register
440
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
441
+ \brief Type definitions for the System Control and ID Register not in the SCB
442
+ @{
443
+ */
444
+
445
+ /**
446
+ \brief Structure type to access the System Control and ID Register not in the SCB.
447
+ */
448
+ typedef struct
449
+ {
450
+ uint32_t RESERVED0[2U];
451
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
452
+ } SCnSCB_Type;
453
+
454
+ /* Auxiliary Control Register Definitions */
455
+ #define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
456
+ #define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
457
+
458
+ #define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
459
+ #define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
460
+
461
+ /*@} end of group CMSIS_SCnotSCB */
462
+
463
+
464
+ /**
465
+ \ingroup CMSIS_core_register
466
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
467
+ \brief Type definitions for the System Timer Registers.
468
+ @{
469
+ */
470
+
471
+ /**
472
+ \brief Structure type to access the System Timer (SysTick).
473
+ */
474
+ typedef struct
475
+ {
476
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
477
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
478
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
479
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
480
+ } SysTick_Type;
481
+
482
+ /* SysTick Control / Status Register Definitions */
483
+ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
484
+ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
485
+
486
+ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
487
+ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
488
+
489
+ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
490
+ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
491
+
492
+ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
493
+ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
494
+
495
+ /* SysTick Reload Register Definitions */
496
+ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
497
+ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
498
+
499
+ /* SysTick Current Register Definitions */
500
+ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
501
+ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
502
+
503
+ /* SysTick Calibration Register Definitions */
504
+ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
505
+ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
506
+
507
+ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
508
+ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
509
+
510
+ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
511
+ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
512
+
513
+ /*@} end of group CMSIS_SysTick */
514
+
515
+
516
+ /**
517
+ \ingroup CMSIS_core_register
518
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
519
+ \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
520
+ Therefore they are not covered by the Cortex-M1 header file.
521
+ @{
522
+ */
523
+ /*@} end of group CMSIS_CoreDebug */
524
+
525
+
526
+ /**
527
+ \ingroup CMSIS_core_register
528
+ \defgroup CMSIS_core_bitfield Core register bit field macros
529
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
530
+ @{
531
+ */
532
+
533
+ /**
534
+ \brief Mask and shift a bit field value for use in a register bit range.
535
+ \param[in] field Name of the register bit field.
536
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
537
+ \return Masked and shifted value.
538
+ */
539
+ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
540
+
541
+ /**
542
+ \brief Mask and shift a register value to extract a bit filed value.
543
+ \param[in] field Name of the register bit field.
544
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
545
+ \return Masked and shifted bit field value.
546
+ */
547
+ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
548
+
549
+ /*@} end of group CMSIS_core_bitfield */
550
+
551
+
552
+ /**
553
+ \ingroup CMSIS_core_register
554
+ \defgroup CMSIS_core_base Core Definitions
555
+ \brief Definitions for base addresses, unions, and structures.
556
+ @{
557
+ */
558
+
559
+ /* Memory mapping of Core Hardware */
560
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
561
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
562
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
563
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
564
+
565
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
566
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
567
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
568
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
569
+
570
+
571
+ /*@} */
572
+
573
+
574
+
575
+ /*******************************************************************************
576
+ * Hardware Abstraction Layer
577
+ Core Function Interface contains:
578
+ - Core NVIC Functions
579
+ - Core SysTick Functions
580
+ - Core Register Access Functions
581
+ ******************************************************************************/
582
+ /**
583
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
584
+ */
585
+
586
+
587
+
588
+ /* ########################## NVIC functions #################################### */
589
+ /**
590
+ \ingroup CMSIS_Core_FunctionInterface
591
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
592
+ \brief Functions that manage interrupts and exceptions via the NVIC.
593
+ @{
594
+ */
595
+
596
+ #ifdef CMSIS_NVIC_VIRTUAL
597
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
598
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
599
+ #endif
600
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
601
+ #else
602
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
603
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
604
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
605
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
606
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
607
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
608
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
609
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
610
+ /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
611
+ #define NVIC_SetPriority __NVIC_SetPriority
612
+ #define NVIC_GetPriority __NVIC_GetPriority
613
+ #define NVIC_SystemReset __NVIC_SystemReset
614
+ #endif /* CMSIS_NVIC_VIRTUAL */
615
+
616
+ #ifdef CMSIS_VECTAB_VIRTUAL
617
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
618
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
619
+ #endif
620
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
621
+ #else
622
+ #define NVIC_SetVector __NVIC_SetVector
623
+ #define NVIC_GetVector __NVIC_GetVector
624
+ #endif /* (CMSIS_VECTAB_VIRTUAL) */
625
+
626
+ #define NVIC_USER_IRQ_OFFSET 16
627
+
628
+
629
+ /* The following EXC_RETURN values are saved the LR on exception entry */
630
+ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
631
+ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
632
+ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
633
+
634
+
635
+ /* Interrupt Priorities are WORD accessible only under Armv6-M */
636
+ /* The following MACROS handle generation of the register offset and byte masks */
637
+ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
638
+ #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
639
+ #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
640
+
641
+ #define __NVIC_SetPriorityGrouping(X) (void)(X)
642
+ #define __NVIC_GetPriorityGrouping() (0U)
643
+
644
+ /**
645
+ \brief Enable Interrupt
646
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
647
+ \param [in] IRQn Device specific interrupt number.
648
+ \note IRQn must not be negative.
649
+ */
650
+ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
651
+ {
652
+ if ((int32_t)(IRQn) >= 0)
653
+ {
654
+ __COMPILER_BARRIER();
655
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
656
+ __COMPILER_BARRIER();
657
+ }
658
+ }
659
+
660
+
661
+ /**
662
+ \brief Get Interrupt Enable status
663
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
664
+ \param [in] IRQn Device specific interrupt number.
665
+ \return 0 Interrupt is not enabled.
666
+ \return 1 Interrupt is enabled.
667
+ \note IRQn must not be negative.
668
+ */
669
+ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
670
+ {
671
+ if ((int32_t)(IRQn) >= 0)
672
+ {
673
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
674
+ }
675
+ else
676
+ {
677
+ return(0U);
678
+ }
679
+ }
680
+
681
+
682
+ /**
683
+ \brief Disable Interrupt
684
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
685
+ \param [in] IRQn Device specific interrupt number.
686
+ \note IRQn must not be negative.
687
+ */
688
+ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
689
+ {
690
+ if ((int32_t)(IRQn) >= 0)
691
+ {
692
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
693
+ __DSB();
694
+ __ISB();
695
+ }
696
+ }
697
+
698
+
699
+ /**
700
+ \brief Get Pending Interrupt
701
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
702
+ \param [in] IRQn Device specific interrupt number.
703
+ \return 0 Interrupt status is not pending.
704
+ \return 1 Interrupt status is pending.
705
+ \note IRQn must not be negative.
706
+ */
707
+ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
708
+ {
709
+ if ((int32_t)(IRQn) >= 0)
710
+ {
711
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
712
+ }
713
+ else
714
+ {
715
+ return(0U);
716
+ }
717
+ }
718
+
719
+
720
+ /**
721
+ \brief Set Pending Interrupt
722
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
723
+ \param [in] IRQn Device specific interrupt number.
724
+ \note IRQn must not be negative.
725
+ */
726
+ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
727
+ {
728
+ if ((int32_t)(IRQn) >= 0)
729
+ {
730
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
731
+ }
732
+ }
733
+
734
+
735
+ /**
736
+ \brief Clear Pending Interrupt
737
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
738
+ \param [in] IRQn Device specific interrupt number.
739
+ \note IRQn must not be negative.
740
+ */
741
+ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
742
+ {
743
+ if ((int32_t)(IRQn) >= 0)
744
+ {
745
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
746
+ }
747
+ }
748
+
749
+
750
+ /**
751
+ \brief Set Interrupt Priority
752
+ \details Sets the priority of a device specific interrupt or a processor exception.
753
+ The interrupt number can be positive to specify a device specific interrupt,
754
+ or negative to specify a processor exception.
755
+ \param [in] IRQn Interrupt number.
756
+ \param [in] priority Priority to set.
757
+ \note The priority cannot be set for every processor exception.
758
+ */
759
+ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
760
+ {
761
+ if ((int32_t)(IRQn) >= 0)
762
+ {
763
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
764
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
765
+ }
766
+ else
767
+ {
768
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
769
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
770
+ }
771
+ }
772
+
773
+
774
+ /**
775
+ \brief Get Interrupt Priority
776
+ \details Reads the priority of a device specific interrupt or a processor exception.
777
+ The interrupt number can be positive to specify a device specific interrupt,
778
+ or negative to specify a processor exception.
779
+ \param [in] IRQn Interrupt number.
780
+ \return Interrupt Priority.
781
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
782
+ */
783
+ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
784
+ {
785
+
786
+ if ((int32_t)(IRQn) >= 0)
787
+ {
788
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
789
+ }
790
+ else
791
+ {
792
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
793
+ }
794
+ }
795
+
796
+
797
+ /**
798
+ \brief Encode Priority
799
+ \details Encodes the priority for an interrupt with the given priority group,
800
+ preemptive priority value, and subpriority value.
801
+ In case of a conflict between priority grouping and available
802
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
803
+ \param [in] PriorityGroup Used priority group.
804
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
805
+ \param [in] SubPriority Subpriority value (starting from 0).
806
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
807
+ */
808
+ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
809
+ {
810
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
811
+ uint32_t PreemptPriorityBits;
812
+ uint32_t SubPriorityBits;
813
+
814
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
815
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
816
+
817
+ return (
818
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
819
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
820
+ );
821
+ }
822
+
823
+
824
+ /**
825
+ \brief Decode Priority
826
+ \details Decodes an interrupt priority value with a given priority group to
827
+ preemptive priority value and subpriority value.
828
+ In case of a conflict between priority grouping and available
829
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
830
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
831
+ \param [in] PriorityGroup Used priority group.
832
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
833
+ \param [out] pSubPriority Subpriority value (starting from 0).
834
+ */
835
+ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
836
+ {
837
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
838
+ uint32_t PreemptPriorityBits;
839
+ uint32_t SubPriorityBits;
840
+
841
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
842
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
843
+
844
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
845
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
846
+ }
847
+
848
+
849
+
850
+ /**
851
+ \brief Set Interrupt Vector
852
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
853
+ The interrupt number can be positive to specify a device specific interrupt,
854
+ or negative to specify a processor exception.
855
+ Address 0 must be mapped to SRAM.
856
+ \param [in] IRQn Interrupt number
857
+ \param [in] vector Address of interrupt handler function
858
+ */
859
+ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
860
+ {
861
+ uint32_t *vectors = (uint32_t *)0x0U;
862
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
863
+ /* ARM Application Note 321 states that the M1 does not require the architectural barrier */
864
+ }
865
+
866
+
867
+ /**
868
+ \brief Get Interrupt Vector
869
+ \details Reads an interrupt vector from interrupt vector table.
870
+ The interrupt number can be positive to specify a device specific interrupt,
871
+ or negative to specify a processor exception.
872
+ \param [in] IRQn Interrupt number.
873
+ \return Address of interrupt handler function
874
+ */
875
+ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
876
+ {
877
+ uint32_t *vectors = (uint32_t *)0x0U;
878
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
879
+ }
880
+
881
+
882
+ /**
883
+ \brief System Reset
884
+ \details Initiates a system reset request to reset the MCU.
885
+ */
886
+ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
887
+ {
888
+ __DSB(); /* Ensure all outstanding memory accesses included
889
+ buffered write are completed before reset */
890
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
891
+ SCB_AIRCR_SYSRESETREQ_Msk);
892
+ __DSB(); /* Ensure completion of memory access */
893
+
894
+ for(;;) /* wait until reset */
895
+ {
896
+ __NOP();
897
+ }
898
+ }
899
+
900
+ /*@} end of CMSIS_Core_NVICFunctions */
901
+
902
+
903
+ /* ########################## FPU functions #################################### */
904
+ /**
905
+ \ingroup CMSIS_Core_FunctionInterface
906
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
907
+ \brief Function that provides FPU type.
908
+ @{
909
+ */
910
+
911
+ /**
912
+ \brief get FPU type
913
+ \details returns the FPU type
914
+ \returns
915
+ - \b 0: No FPU
916
+ - \b 1: Single precision FPU
917
+ - \b 2: Double + Single precision FPU
918
+ */
919
+ __STATIC_INLINE uint32_t SCB_GetFPUType(void)
920
+ {
921
+ return 0U; /* No FPU */
922
+ }
923
+
924
+
925
+ /*@} end of CMSIS_Core_FpuFunctions */
926
+
927
+
928
+
929
+ /* ################################## SysTick function ############################################ */
930
+ /**
931
+ \ingroup CMSIS_Core_FunctionInterface
932
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
933
+ \brief Functions that configure the System.
934
+ @{
935
+ */
936
+
937
+ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
938
+
939
+ /**
940
+ \brief System Tick Configuration
941
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
942
+ Counter is in free running mode to generate periodic interrupts.
943
+ \param [in] ticks Number of ticks between two interrupts.
944
+ \return 0 Function succeeded.
945
+ \return 1 Function failed.
946
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
947
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
948
+ must contain a vendor-specific implementation of this function.
949
+ */
950
+ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
951
+ {
952
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
953
+ {
954
+ return (1UL); /* Reload value impossible */
955
+ }
956
+
957
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
958
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
959
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
960
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
961
+ SysTick_CTRL_TICKINT_Msk |
962
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
963
+ return (0UL); /* Function successful */
964
+ }
965
+
966
+ #endif
967
+
968
+ /*@} end of CMSIS_Core_SysTickFunctions */
969
+
970
+
971
+
972
+
973
+ #ifdef __cplusplus
974
+ }
975
+ #endif
976
+
977
+ #endif /* __CORE_CM1_H_DEPENDANT */
978
+
979
+ #endif /* __CMSIS_GENERIC */
edge-impulse-sdk/CMSIS/Core/Include/core_cm23.h ADDED
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edge-impulse-sdk/CMSIS/Core/Include/core_cm33.h ADDED
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edge-impulse-sdk/CMSIS/Core/Include/core_cm4.h ADDED
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edge-impulse-sdk/CMSIS/Core/Include/core_cm55.h ADDED
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edge-impulse-sdk/CMSIS/Core/Include/core_cm7.h ADDED
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edge-impulse-sdk/CMSIS/Core/Include/core_cm85.h ADDED
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edge-impulse-sdk/CMSIS/Core/Include/core_sc000.h ADDED
@@ -0,0 +1,1030 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ /**************************************************************************//**
2
+ * @file core_sc000.h
3
+ * @brief CMSIS SC000 Core Peripheral Access Layer Header File
4
+ * @version V5.0.7
5
+ * @date 27. March 2020
6
+ ******************************************************************************/
7
+ /*
8
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
9
+ *
10
+ * SPDX-License-Identifier: Apache-2.0
11
+ *
12
+ * Licensed under the Apache License, Version 2.0 (the License); you may
13
+ * not use this file except in compliance with the License.
14
+ * You may obtain a copy of the License at
15
+ *
16
+ * www.apache.org/licenses/LICENSE-2.0
17
+ *
18
+ * Unless required by applicable law or agreed to in writing, software
19
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21
+ * See the License for the specific language governing permissions and
22
+ * limitations under the License.
23
+ */
24
+
25
+ #if defined ( __ICCARM__ )
26
+ #pragma system_include /* treat file as system include file for MISRA check */
27
+ #elif defined (__clang__)
28
+ #pragma clang system_header /* treat file as system include file */
29
+ #endif
30
+
31
+ #ifndef __CORE_SC000_H_GENERIC
32
+ #define __CORE_SC000_H_GENERIC
33
+
34
+ #include <stdint.h>
35
+
36
+ #ifdef __cplusplus
37
+ extern "C" {
38
+ #endif
39
+
40
+ /**
41
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42
+ CMSIS violates the following MISRA-C:2004 rules:
43
+
44
+ \li Required Rule 8.5, object/function definition in header file.<br>
45
+ Function definitions in header files are used to allow 'inlining'.
46
+
47
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48
+ Unions are used for effective representation of core registers.
49
+
50
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
51
+ Function-like macros are used to allow more efficient code.
52
+ */
53
+
54
+
55
+ /*******************************************************************************
56
+ * CMSIS definitions
57
+ ******************************************************************************/
58
+ /**
59
+ \ingroup SC000
60
+ @{
61
+ */
62
+
63
+ #include "cmsis_version.h"
64
+
65
+ /* CMSIS SC000 definitions */
66
+ #define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
67
+ #define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
68
+ #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
69
+ __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
70
+
71
+ #define __CORTEX_SC (000U) /*!< Cortex secure core */
72
+
73
+ /** __FPU_USED indicates whether an FPU is used or not.
74
+ This core does not support an FPU at all
75
+ */
76
+ #define __FPU_USED 0U
77
+
78
+ #if defined ( __CC_ARM )
79
+ #if defined __TARGET_FPU_VFP
80
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
81
+ #endif
82
+
83
+ #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
84
+ #if defined __ARM_FP
85
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
86
+ #endif
87
+
88
+ #elif defined ( __GNUC__ )
89
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
90
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
91
+ #endif
92
+
93
+ #elif defined ( __ICCARM__ )
94
+ #if defined __ARMVFP__
95
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
96
+ #endif
97
+
98
+ #elif defined ( __TI_ARM__ )
99
+ #if defined __TI_VFP_SUPPORT__
100
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
101
+ #endif
102
+
103
+ #elif defined ( __TASKING__ )
104
+ #if defined __FPU_VFP__
105
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106
+ #endif
107
+
108
+ #elif defined ( __CSMC__ )
109
+ #if ( __CSMC__ & 0x400U)
110
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
111
+ #endif
112
+
113
+ #endif
114
+
115
+ #include "edge-impulse-sdk/CMSIS/Core/Include/cmsis_compiler.h" /* CMSIS compiler specific defines */
116
+
117
+
118
+ #ifdef __cplusplus
119
+ }
120
+ #endif
121
+
122
+ #endif /* __CORE_SC000_H_GENERIC */
123
+
124
+ #ifndef __CMSIS_GENERIC
125
+
126
+ #ifndef __CORE_SC000_H_DEPENDANT
127
+ #define __CORE_SC000_H_DEPENDANT
128
+
129
+ #ifdef __cplusplus
130
+ extern "C" {
131
+ #endif
132
+
133
+ /* check device defines and use defaults */
134
+ #if defined __CHECK_DEVICE_DEFINES
135
+ #ifndef __SC000_REV
136
+ #define __SC000_REV 0x0000U
137
+ #warning "__SC000_REV not defined in device header file; using default!"
138
+ #endif
139
+
140
+ #ifndef __MPU_PRESENT
141
+ #define __MPU_PRESENT 0U
142
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
143
+ #endif
144
+
145
+ #ifndef __VTOR_PRESENT
146
+ #define __VTOR_PRESENT 0U
147
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
148
+ #endif
149
+
150
+ #ifndef __NVIC_PRIO_BITS
151
+ #define __NVIC_PRIO_BITS 2U
152
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
153
+ #endif
154
+
155
+ #ifndef __Vendor_SysTickConfig
156
+ #define __Vendor_SysTickConfig 0U
157
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
158
+ #endif
159
+ #endif
160
+
161
+ /* IO definitions (access restrictions to peripheral registers) */
162
+ /**
163
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
164
+
165
+ <strong>IO Type Qualifiers</strong> are used
166
+ \li to specify the access to peripheral variables.
167
+ \li for automatic generation of peripheral register debug information.
168
+ */
169
+ #ifdef __cplusplus
170
+ #define __I volatile /*!< Defines 'read only' permissions */
171
+ #else
172
+ #define __I volatile const /*!< Defines 'read only' permissions */
173
+ #endif
174
+ #define __O volatile /*!< Defines 'write only' permissions */
175
+ #define __IO volatile /*!< Defines 'read / write' permissions */
176
+
177
+ /* following defines should be used for structure members */
178
+ #define __IM volatile const /*! Defines 'read only' structure member permissions */
179
+ #define __OM volatile /*! Defines 'write only' structure member permissions */
180
+ #define __IOM volatile /*! Defines 'read / write' structure member permissions */
181
+
182
+ /*@} end of group SC000 */
183
+
184
+
185
+
186
+ /*******************************************************************************
187
+ * Register Abstraction
188
+ Core Register contain:
189
+ - Core Register
190
+ - Core NVIC Register
191
+ - Core SCB Register
192
+ - Core SysTick Register
193
+ - Core MPU Register
194
+ ******************************************************************************/
195
+ /**
196
+ \defgroup CMSIS_core_register Defines and Type Definitions
197
+ \brief Type definitions and defines for Cortex-M processor based devices.
198
+ */
199
+
200
+ /**
201
+ \ingroup CMSIS_core_register
202
+ \defgroup CMSIS_CORE Status and Control Registers
203
+ \brief Core Register type definitions.
204
+ @{
205
+ */
206
+
207
+ /**
208
+ \brief Union type to access the Application Program Status Register (APSR).
209
+ */
210
+ typedef union
211
+ {
212
+ struct
213
+ {
214
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
215
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
216
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
217
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
218
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
219
+ } b; /*!< Structure used for bit access */
220
+ uint32_t w; /*!< Type used for word access */
221
+ } APSR_Type;
222
+
223
+ /* APSR Register Definitions */
224
+ #define APSR_N_Pos 31U /*!< APSR: N Position */
225
+ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
226
+
227
+ #define APSR_Z_Pos 30U /*!< APSR: Z Position */
228
+ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
229
+
230
+ #define APSR_C_Pos 29U /*!< APSR: C Position */
231
+ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
232
+
233
+ #define APSR_V_Pos 28U /*!< APSR: V Position */
234
+ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
235
+
236
+
237
+ /**
238
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
239
+ */
240
+ typedef union
241
+ {
242
+ struct
243
+ {
244
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
245
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
246
+ } b; /*!< Structure used for bit access */
247
+ uint32_t w; /*!< Type used for word access */
248
+ } IPSR_Type;
249
+
250
+ /* IPSR Register Definitions */
251
+ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
252
+ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
253
+
254
+
255
+ /**
256
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
257
+ */
258
+ typedef union
259
+ {
260
+ struct
261
+ {
262
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
263
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
264
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
265
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
266
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
267
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
268
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
269
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
270
+ } b; /*!< Structure used for bit access */
271
+ uint32_t w; /*!< Type used for word access */
272
+ } xPSR_Type;
273
+
274
+ /* xPSR Register Definitions */
275
+ #define xPSR_N_Pos 31U /*!< xPSR: N Position */
276
+ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
277
+
278
+ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
279
+ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
280
+
281
+ #define xPSR_C_Pos 29U /*!< xPSR: C Position */
282
+ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
283
+
284
+ #define xPSR_V_Pos 28U /*!< xPSR: V Position */
285
+ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
286
+
287
+ #define xPSR_T_Pos 24U /*!< xPSR: T Position */
288
+ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
289
+
290
+ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
291
+ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
292
+
293
+
294
+ /**
295
+ \brief Union type to access the Control Registers (CONTROL).
296
+ */
297
+ typedef union
298
+ {
299
+ struct
300
+ {
301
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
302
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
303
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
304
+ } b; /*!< Structure used for bit access */
305
+ uint32_t w; /*!< Type used for word access */
306
+ } CONTROL_Type;
307
+
308
+ /* CONTROL Register Definitions */
309
+ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
310
+ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
311
+
312
+ /*@} end of group CMSIS_CORE */
313
+
314
+
315
+ /**
316
+ \ingroup CMSIS_core_register
317
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
318
+ \brief Type definitions for the NVIC Registers
319
+ @{
320
+ */
321
+
322
+ /**
323
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
324
+ */
325
+ typedef struct
326
+ {
327
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
328
+ uint32_t RESERVED0[31U];
329
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
330
+ uint32_t RSERVED1[31U];
331
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
332
+ uint32_t RESERVED2[31U];
333
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
334
+ uint32_t RESERVED3[31U];
335
+ uint32_t RESERVED4[64U];
336
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
337
+ } NVIC_Type;
338
+
339
+ /*@} end of group CMSIS_NVIC */
340
+
341
+
342
+ /**
343
+ \ingroup CMSIS_core_register
344
+ \defgroup CMSIS_SCB System Control Block (SCB)
345
+ \brief Type definitions for the System Control Block Registers
346
+ @{
347
+ */
348
+
349
+ /**
350
+ \brief Structure type to access the System Control Block (SCB).
351
+ */
352
+ typedef struct
353
+ {
354
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
355
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
356
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
357
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
358
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
359
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
360
+ uint32_t RESERVED0[1U];
361
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
362
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
363
+ uint32_t RESERVED1[154U];
364
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
365
+ } SCB_Type;
366
+
367
+ /* SCB CPUID Register Definitions */
368
+ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
369
+ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
370
+
371
+ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
372
+ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
373
+
374
+ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
375
+ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
376
+
377
+ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
378
+ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
379
+
380
+ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
381
+ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
382
+
383
+ /* SCB Interrupt Control State Register Definitions */
384
+ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
385
+ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
386
+
387
+ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
388
+ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
389
+
390
+ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
391
+ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
392
+
393
+ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
394
+ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
395
+
396
+ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
397
+ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
398
+
399
+ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
400
+ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
401
+
402
+ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
403
+ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
404
+
405
+ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
406
+ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
407
+
408
+ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
409
+ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
410
+
411
+ /* SCB Interrupt Control State Register Definitions */
412
+ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
413
+ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
414
+
415
+ /* SCB Application Interrupt and Reset Control Register Definitions */
416
+ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
417
+ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
418
+
419
+ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
420
+ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
421
+
422
+ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
423
+ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
424
+
425
+ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
426
+ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
427
+
428
+ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
429
+ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
430
+
431
+ /* SCB System Control Register Definitions */
432
+ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
433
+ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
434
+
435
+ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
436
+ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
437
+
438
+ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
439
+ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
440
+
441
+ /* SCB Configuration Control Register Definitions */
442
+ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
443
+ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
444
+
445
+ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
446
+ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
447
+
448
+ /* SCB System Handler Control and State Register Definitions */
449
+ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
450
+ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
451
+
452
+ /*@} end of group CMSIS_SCB */
453
+
454
+
455
+ /**
456
+ \ingroup CMSIS_core_register
457
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
458
+ \brief Type definitions for the System Control and ID Register not in the SCB
459
+ @{
460
+ */
461
+
462
+ /**
463
+ \brief Structure type to access the System Control and ID Register not in the SCB.
464
+ */
465
+ typedef struct
466
+ {
467
+ uint32_t RESERVED0[2U];
468
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
469
+ } SCnSCB_Type;
470
+
471
+ /* Auxiliary Control Register Definitions */
472
+ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
473
+ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
474
+
475
+ /*@} end of group CMSIS_SCnotSCB */
476
+
477
+
478
+ /**
479
+ \ingroup CMSIS_core_register
480
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
481
+ \brief Type definitions for the System Timer Registers.
482
+ @{
483
+ */
484
+
485
+ /**
486
+ \brief Structure type to access the System Timer (SysTick).
487
+ */
488
+ typedef struct
489
+ {
490
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
491
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
492
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
493
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
494
+ } SysTick_Type;
495
+
496
+ /* SysTick Control / Status Register Definitions */
497
+ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
498
+ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
499
+
500
+ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
501
+ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
502
+
503
+ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
504
+ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
505
+
506
+ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
507
+ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
508
+
509
+ /* SysTick Reload Register Definitions */
510
+ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
511
+ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
512
+
513
+ /* SysTick Current Register Definitions */
514
+ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
515
+ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
516
+
517
+ /* SysTick Calibration Register Definitions */
518
+ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
519
+ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
520
+
521
+ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
522
+ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
523
+
524
+ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
525
+ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
526
+
527
+ /*@} end of group CMSIS_SysTick */
528
+
529
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
530
+ /**
531
+ \ingroup CMSIS_core_register
532
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
533
+ \brief Type definitions for the Memory Protection Unit (MPU)
534
+ @{
535
+ */
536
+
537
+ /**
538
+ \brief Structure type to access the Memory Protection Unit (MPU).
539
+ */
540
+ typedef struct
541
+ {
542
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
543
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
544
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
545
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
546
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
547
+ } MPU_Type;
548
+
549
+ /* MPU Type Register Definitions */
550
+ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
551
+ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
552
+
553
+ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
554
+ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
555
+
556
+ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
557
+ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
558
+
559
+ /* MPU Control Register Definitions */
560
+ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
561
+ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
562
+
563
+ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
564
+ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
565
+
566
+ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
567
+ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
568
+
569
+ /* MPU Region Number Register Definitions */
570
+ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
571
+ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
572
+
573
+ /* MPU Region Base Address Register Definitions */
574
+ #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
575
+ #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
576
+
577
+ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
578
+ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
579
+
580
+ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
581
+ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
582
+
583
+ /* MPU Region Attribute and Size Register Definitions */
584
+ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
585
+ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
586
+
587
+ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
588
+ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
589
+
590
+ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
591
+ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
592
+
593
+ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
594
+ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
595
+
596
+ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
597
+ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
598
+
599
+ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
600
+ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
601
+
602
+ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
603
+ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
604
+
605
+ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
606
+ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
607
+
608
+ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
609
+ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
610
+
611
+ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
612
+ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
613
+
614
+ /*@} end of group CMSIS_MPU */
615
+ #endif
616
+
617
+
618
+ /**
619
+ \ingroup CMSIS_core_register
620
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
621
+ \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
622
+ Therefore they are not covered by the SC000 header file.
623
+ @{
624
+ */
625
+ /*@} end of group CMSIS_CoreDebug */
626
+
627
+
628
+ /**
629
+ \ingroup CMSIS_core_register
630
+ \defgroup CMSIS_core_bitfield Core register bit field macros
631
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
632
+ @{
633
+ */
634
+
635
+ /**
636
+ \brief Mask and shift a bit field value for use in a register bit range.
637
+ \param[in] field Name of the register bit field.
638
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
639
+ \return Masked and shifted value.
640
+ */
641
+ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
642
+
643
+ /**
644
+ \brief Mask and shift a register value to extract a bit filed value.
645
+ \param[in] field Name of the register bit field.
646
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
647
+ \return Masked and shifted bit field value.
648
+ */
649
+ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
650
+
651
+ /*@} end of group CMSIS_core_bitfield */
652
+
653
+
654
+ /**
655
+ \ingroup CMSIS_core_register
656
+ \defgroup CMSIS_core_base Core Definitions
657
+ \brief Definitions for base addresses, unions, and structures.
658
+ @{
659
+ */
660
+
661
+ /* Memory mapping of Core Hardware */
662
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
663
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
664
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
665
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
666
+
667
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
668
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
669
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
670
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
671
+
672
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
673
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
674
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
675
+ #endif
676
+
677
+ /*@} */
678
+
679
+
680
+
681
+ /*******************************************************************************
682
+ * Hardware Abstraction Layer
683
+ Core Function Interface contains:
684
+ - Core NVIC Functions
685
+ - Core SysTick Functions
686
+ - Core Register Access Functions
687
+ ******************************************************************************/
688
+ /**
689
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
690
+ */
691
+
692
+
693
+
694
+ /* ########################## NVIC functions #################################### */
695
+ /**
696
+ \ingroup CMSIS_Core_FunctionInterface
697
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
698
+ \brief Functions that manage interrupts and exceptions via the NVIC.
699
+ @{
700
+ */
701
+
702
+ #ifdef CMSIS_NVIC_VIRTUAL
703
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
704
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
705
+ #endif
706
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
707
+ #else
708
+ /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
709
+ /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
710
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
711
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
712
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
713
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
714
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
715
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
716
+ /*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
717
+ #define NVIC_SetPriority __NVIC_SetPriority
718
+ #define NVIC_GetPriority __NVIC_GetPriority
719
+ #define NVIC_SystemReset __NVIC_SystemReset
720
+ #endif /* CMSIS_NVIC_VIRTUAL */
721
+
722
+ #ifdef CMSIS_VECTAB_VIRTUAL
723
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
724
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
725
+ #endif
726
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
727
+ #else
728
+ #define NVIC_SetVector __NVIC_SetVector
729
+ #define NVIC_GetVector __NVIC_GetVector
730
+ #endif /* (CMSIS_VECTAB_VIRTUAL) */
731
+
732
+ #define NVIC_USER_IRQ_OFFSET 16
733
+
734
+
735
+ /* The following EXC_RETURN values are saved the LR on exception entry */
736
+ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
737
+ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
738
+ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
739
+
740
+
741
+ /* Interrupt Priorities are WORD accessible only under Armv6-M */
742
+ /* The following MACROS handle generation of the register offset and byte masks */
743
+ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
744
+ #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
745
+ #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
746
+
747
+
748
+ /**
749
+ \brief Enable Interrupt
750
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
751
+ \param [in] IRQn Device specific interrupt number.
752
+ \note IRQn must not be negative.
753
+ */
754
+ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
755
+ {
756
+ if ((int32_t)(IRQn) >= 0)
757
+ {
758
+ __COMPILER_BARRIER();
759
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
760
+ __COMPILER_BARRIER();
761
+ }
762
+ }
763
+
764
+
765
+ /**
766
+ \brief Get Interrupt Enable status
767
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
768
+ \param [in] IRQn Device specific interrupt number.
769
+ \return 0 Interrupt is not enabled.
770
+ \return 1 Interrupt is enabled.
771
+ \note IRQn must not be negative.
772
+ */
773
+ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
774
+ {
775
+ if ((int32_t)(IRQn) >= 0)
776
+ {
777
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
778
+ }
779
+ else
780
+ {
781
+ return(0U);
782
+ }
783
+ }
784
+
785
+
786
+ /**
787
+ \brief Disable Interrupt
788
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
789
+ \param [in] IRQn Device specific interrupt number.
790
+ \note IRQn must not be negative.
791
+ */
792
+ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
793
+ {
794
+ if ((int32_t)(IRQn) >= 0)
795
+ {
796
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
797
+ __DSB();
798
+ __ISB();
799
+ }
800
+ }
801
+
802
+
803
+ /**
804
+ \brief Get Pending Interrupt
805
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
806
+ \param [in] IRQn Device specific interrupt number.
807
+ \return 0 Interrupt status is not pending.
808
+ \return 1 Interrupt status is pending.
809
+ \note IRQn must not be negative.
810
+ */
811
+ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
812
+ {
813
+ if ((int32_t)(IRQn) >= 0)
814
+ {
815
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
816
+ }
817
+ else
818
+ {
819
+ return(0U);
820
+ }
821
+ }
822
+
823
+
824
+ /**
825
+ \brief Set Pending Interrupt
826
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
827
+ \param [in] IRQn Device specific interrupt number.
828
+ \note IRQn must not be negative.
829
+ */
830
+ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
831
+ {
832
+ if ((int32_t)(IRQn) >= 0)
833
+ {
834
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
835
+ }
836
+ }
837
+
838
+
839
+ /**
840
+ \brief Clear Pending Interrupt
841
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
842
+ \param [in] IRQn Device specific interrupt number.
843
+ \note IRQn must not be negative.
844
+ */
845
+ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
846
+ {
847
+ if ((int32_t)(IRQn) >= 0)
848
+ {
849
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
850
+ }
851
+ }
852
+
853
+
854
+ /**
855
+ \brief Set Interrupt Priority
856
+ \details Sets the priority of a device specific interrupt or a processor exception.
857
+ The interrupt number can be positive to specify a device specific interrupt,
858
+ or negative to specify a processor exception.
859
+ \param [in] IRQn Interrupt number.
860
+ \param [in] priority Priority to set.
861
+ \note The priority cannot be set for every processor exception.
862
+ */
863
+ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
864
+ {
865
+ if ((int32_t)(IRQn) >= 0)
866
+ {
867
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
868
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
869
+ }
870
+ else
871
+ {
872
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
873
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
874
+ }
875
+ }
876
+
877
+
878
+ /**
879
+ \brief Get Interrupt Priority
880
+ \details Reads the priority of a device specific interrupt or a processor exception.
881
+ The interrupt number can be positive to specify a device specific interrupt,
882
+ or negative to specify a processor exception.
883
+ \param [in] IRQn Interrupt number.
884
+ \return Interrupt Priority.
885
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
886
+ */
887
+ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
888
+ {
889
+
890
+ if ((int32_t)(IRQn) >= 0)
891
+ {
892
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
893
+ }
894
+ else
895
+ {
896
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
897
+ }
898
+ }
899
+
900
+
901
+ /**
902
+ \brief Set Interrupt Vector
903
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
904
+ The interrupt number can be positive to specify a device specific interrupt,
905
+ or negative to specify a processor exception.
906
+ VTOR must been relocated to SRAM before.
907
+ \param [in] IRQn Interrupt number
908
+ \param [in] vector Address of interrupt handler function
909
+ */
910
+ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
911
+ {
912
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
913
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
914
+ /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */
915
+ }
916
+
917
+
918
+ /**
919
+ \brief Get Interrupt Vector
920
+ \details Reads an interrupt vector from interrupt vector table.
921
+ The interrupt number can be positive to specify a device specific interrupt,
922
+ or negative to specify a processor exception.
923
+ \param [in] IRQn Interrupt number.
924
+ \return Address of interrupt handler function
925
+ */
926
+ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
927
+ {
928
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
929
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
930
+ }
931
+
932
+
933
+ /**
934
+ \brief System Reset
935
+ \details Initiates a system reset request to reset the MCU.
936
+ */
937
+ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
938
+ {
939
+ __DSB(); /* Ensure all outstanding memory accesses included
940
+ buffered write are completed before reset */
941
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
942
+ SCB_AIRCR_SYSRESETREQ_Msk);
943
+ __DSB(); /* Ensure completion of memory access */
944
+
945
+ for(;;) /* wait until reset */
946
+ {
947
+ __NOP();
948
+ }
949
+ }
950
+
951
+ /*@} end of CMSIS_Core_NVICFunctions */
952
+
953
+
954
+ /* ########################## FPU functions #################################### */
955
+ /**
956
+ \ingroup CMSIS_Core_FunctionInterface
957
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
958
+ \brief Function that provides FPU type.
959
+ @{
960
+ */
961
+
962
+ /**
963
+ \brief get FPU type
964
+ \details returns the FPU type
965
+ \returns
966
+ - \b 0: No FPU
967
+ - \b 1: Single precision FPU
968
+ - \b 2: Double + Single precision FPU
969
+ */
970
+ __STATIC_INLINE uint32_t SCB_GetFPUType(void)
971
+ {
972
+ return 0U; /* No FPU */
973
+ }
974
+
975
+
976
+ /*@} end of CMSIS_Core_FpuFunctions */
977
+
978
+
979
+
980
+ /* ################################## SysTick function ############################################ */
981
+ /**
982
+ \ingroup CMSIS_Core_FunctionInterface
983
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
984
+ \brief Functions that configure the System.
985
+ @{
986
+ */
987
+
988
+ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
989
+
990
+ /**
991
+ \brief System Tick Configuration
992
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
993
+ Counter is in free running mode to generate periodic interrupts.
994
+ \param [in] ticks Number of ticks between two interrupts.
995
+ \return 0 Function succeeded.
996
+ \return 1 Function failed.
997
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
998
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
999
+ must contain a vendor-specific implementation of this function.
1000
+ */
1001
+ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1002
+ {
1003
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
1004
+ {
1005
+ return (1UL); /* Reload value impossible */
1006
+ }
1007
+
1008
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
1009
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
1010
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
1011
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1012
+ SysTick_CTRL_TICKINT_Msk |
1013
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1014
+ return (0UL); /* Function successful */
1015
+ }
1016
+
1017
+ #endif
1018
+
1019
+ /*@} end of CMSIS_Core_SysTickFunctions */
1020
+
1021
+
1022
+
1023
+
1024
+ #ifdef __cplusplus
1025
+ }
1026
+ #endif
1027
+
1028
+ #endif /* __CORE_SC000_H_DEPENDANT */
1029
+
1030
+ #endif /* __CMSIS_GENERIC */
edge-impulse-sdk/CMSIS/Core/Include/core_sc300.h ADDED
The diff for this file is too large to render. See raw diff
 
edge-impulse-sdk/CMSIS/Core/Include/core_starmc1.h ADDED
The diff for this file is too large to render. See raw diff
 
edge-impulse-sdk/CMSIS/Core/Include/mpu_armv7.h ADDED
@@ -0,0 +1,275 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ /******************************************************************************
2
+ * @file mpu_armv7.h
3
+ * @brief CMSIS MPU API for Armv7-M MPU
4
+ * @version V5.1.2
5
+ * @date 25. May 2020
6
+ ******************************************************************************/
7
+ /*
8
+ * Copyright (c) 2017-2020 Arm Limited. All rights reserved.
9
+ *
10
+ * SPDX-License-Identifier: Apache-2.0
11
+ *
12
+ * Licensed under the Apache License, Version 2.0 (the License); you may
13
+ * not use this file except in compliance with the License.
14
+ * You may obtain a copy of the License at
15
+ *
16
+ * www.apache.org/licenses/LICENSE-2.0
17
+ *
18
+ * Unless required by applicable law or agreed to in writing, software
19
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21
+ * See the License for the specific language governing permissions and
22
+ * limitations under the License.
23
+ */
24
+
25
+ #if defined ( __ICCARM__ )
26
+ #pragma system_include /* treat file as system include file for MISRA check */
27
+ #elif defined (__clang__)
28
+ #pragma clang system_header /* treat file as system include file */
29
+ #endif
30
+
31
+ #ifndef ARM_MPU_ARMV7_H
32
+ #define ARM_MPU_ARMV7_H
33
+
34
+ #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
35
+ #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
36
+ #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
37
+ #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
38
+ #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
39
+ #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
40
+ #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
41
+ #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
42
+ #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
43
+ #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
44
+ #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
45
+ #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
46
+ #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
47
+ #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
48
+ #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
49
+ #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
50
+ #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
51
+ #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
52
+ #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
53
+ #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
54
+ #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
55
+ #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
56
+ #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
57
+ #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
58
+ #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
59
+ #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
60
+ #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
61
+ #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
62
+
63
+ #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
64
+ #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
65
+ #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
66
+ #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
67
+ #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
68
+ #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
69
+
70
+ /** MPU Region Base Address Register Value
71
+ *
72
+ * \param Region The region to be configured, number 0 to 15.
73
+ * \param BaseAddress The base address for the region.
74
+ */
75
+ #define ARM_MPU_RBAR(Region, BaseAddress) \
76
+ (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
77
+ ((Region) & MPU_RBAR_REGION_Msk) | \
78
+ (MPU_RBAR_VALID_Msk))
79
+
80
+ /**
81
+ * MPU Memory Access Attributes
82
+ *
83
+ * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
84
+ * \param IsShareable Region is shareable between multiple bus masters.
85
+ * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
86
+ * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
87
+ */
88
+ #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
89
+ ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
90
+ (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
91
+ (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
92
+ (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
93
+
94
+ /**
95
+ * MPU Region Attribute and Size Register Value
96
+ *
97
+ * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
98
+ * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
99
+ * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
100
+ * \param SubRegionDisable Sub-region disable field.
101
+ * \param Size Region size of the region to be configured, for example 4K, 8K.
102
+ */
103
+ #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
104
+ ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
105
+ (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
106
+ (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
107
+ (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
108
+ (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
109
+ (((MPU_RASR_ENABLE_Msk))))
110
+
111
+ /**
112
+ * MPU Region Attribute and Size Register Value
113
+ *
114
+ * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
115
+ * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
116
+ * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
117
+ * \param IsShareable Region is shareable between multiple bus masters.
118
+ * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
119
+ * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
120
+ * \param SubRegionDisable Sub-region disable field.
121
+ * \param Size Region size of the region to be configured, for example 4K, 8K.
122
+ */
123
+ #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
124
+ ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
125
+
126
+ /**
127
+ * MPU Memory Access Attribute for strongly ordered memory.
128
+ * - TEX: 000b
129
+ * - Shareable
130
+ * - Non-cacheable
131
+ * - Non-bufferable
132
+ */
133
+ #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
134
+
135
+ /**
136
+ * MPU Memory Access Attribute for device memory.
137
+ * - TEX: 000b (if shareable) or 010b (if non-shareable)
138
+ * - Shareable or non-shareable
139
+ * - Non-cacheable
140
+ * - Bufferable (if shareable) or non-bufferable (if non-shareable)
141
+ *
142
+ * \param IsShareable Configures the device memory as shareable or non-shareable.
143
+ */
144
+ #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
145
+
146
+ /**
147
+ * MPU Memory Access Attribute for normal memory.
148
+ * - TEX: 1BBb (reflecting outer cacheability rules)
149
+ * - Shareable or non-shareable
150
+ * - Cacheable or non-cacheable (reflecting inner cacheability rules)
151
+ * - Bufferable or non-bufferable (reflecting inner cacheability rules)
152
+ *
153
+ * \param OuterCp Configures the outer cache policy.
154
+ * \param InnerCp Configures the inner cache policy.
155
+ * \param IsShareable Configures the memory as shareable or non-shareable.
156
+ */
157
+ #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
158
+
159
+ /**
160
+ * MPU Memory Access Attribute non-cacheable policy.
161
+ */
162
+ #define ARM_MPU_CACHEP_NOCACHE 0U
163
+
164
+ /**
165
+ * MPU Memory Access Attribute write-back, write and read allocate policy.
166
+ */
167
+ #define ARM_MPU_CACHEP_WB_WRA 1U
168
+
169
+ /**
170
+ * MPU Memory Access Attribute write-through, no write allocate policy.
171
+ */
172
+ #define ARM_MPU_CACHEP_WT_NWA 2U
173
+
174
+ /**
175
+ * MPU Memory Access Attribute write-back, no write allocate policy.
176
+ */
177
+ #define ARM_MPU_CACHEP_WB_NWA 3U
178
+
179
+
180
+ /**
181
+ * Struct for a single MPU Region
182
+ */
183
+ typedef struct {
184
+ uint32_t RBAR; //!< The region base address register value (RBAR)
185
+ uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
186
+ } ARM_MPU_Region_t;
187
+
188
+ /** Enable the MPU.
189
+ * \param MPU_Control Default access permissions for unconfigured regions.
190
+ */
191
+ __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
192
+ {
193
+ __DMB();
194
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
195
+ #ifdef SCB_SHCSR_MEMFAULTENA_Msk
196
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
197
+ #endif
198
+ __DSB();
199
+ __ISB();
200
+ }
201
+
202
+ /** Disable the MPU.
203
+ */
204
+ __STATIC_INLINE void ARM_MPU_Disable(void)
205
+ {
206
+ __DMB();
207
+ #ifdef SCB_SHCSR_MEMFAULTENA_Msk
208
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
209
+ #endif
210
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
211
+ __DSB();
212
+ __ISB();
213
+ }
214
+
215
+ /** Clear and disable the given MPU region.
216
+ * \param rnr Region number to be cleared.
217
+ */
218
+ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
219
+ {
220
+ MPU->RNR = rnr;
221
+ MPU->RASR = 0U;
222
+ }
223
+
224
+ /** Configure an MPU region.
225
+ * \param rbar Value for RBAR register.
226
+ * \param rasr Value for RASR register.
227
+ */
228
+ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
229
+ {
230
+ MPU->RBAR = rbar;
231
+ MPU->RASR = rasr;
232
+ }
233
+
234
+ /** Configure the given MPU region.
235
+ * \param rnr Region number to be configured.
236
+ * \param rbar Value for RBAR register.
237
+ * \param rasr Value for RASR register.
238
+ */
239
+ __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
240
+ {
241
+ MPU->RNR = rnr;
242
+ MPU->RBAR = rbar;
243
+ MPU->RASR = rasr;
244
+ }
245
+
246
+ /** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load().
247
+ * \param dst Destination data is copied to.
248
+ * \param src Source data is copied from.
249
+ * \param len Amount of data words to be copied.
250
+ */
251
+ __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
252
+ {
253
+ uint32_t i;
254
+ for (i = 0U; i < len; ++i)
255
+ {
256
+ dst[i] = src[i];
257
+ }
258
+ }
259
+
260
+ /** Load the given number of MPU regions from a table.
261
+ * \param table Pointer to the MPU configuration table.
262
+ * \param cnt Amount of regions to be configured.
263
+ */
264
+ __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
265
+ {
266
+ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
267
+ while (cnt > MPU_TYPE_RALIASES) {
268
+ ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
269
+ table += MPU_TYPE_RALIASES;
270
+ cnt -= MPU_TYPE_RALIASES;
271
+ }
272
+ ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
273
+ }
274
+
275
+ #endif
edge-impulse-sdk/CMSIS/Core/Include/mpu_armv8.h ADDED
@@ -0,0 +1,352 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ /******************************************************************************
2
+ * @file mpu_armv8.h
3
+ * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
4
+ * @version V5.1.4
5
+ * @date 30. May 2022
6
+ ******************************************************************************/
7
+ /*
8
+ * Copyright (c) 2017-2022 Arm Limited. All rights reserved.
9
+ *
10
+ * SPDX-License-Identifier: Apache-2.0
11
+ *
12
+ * Licensed under the Apache License, Version 2.0 (the License); you may
13
+ * not use this file except in compliance with the License.
14
+ * You may obtain a copy of the License at
15
+ *
16
+ * www.apache.org/licenses/LICENSE-2.0
17
+ *
18
+ * Unless required by applicable law or agreed to in writing, software
19
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21
+ * See the License for the specific language governing permissions and
22
+ * limitations under the License.
23
+ */
24
+
25
+ #if defined ( __ICCARM__ )
26
+ #pragma system_include /* treat file as system include file for MISRA check */
27
+ #elif defined (__clang__)
28
+ #pragma clang system_header /* treat file as system include file */
29
+ #endif
30
+
31
+ #ifndef ARM_MPU_ARMV8_H
32
+ #define ARM_MPU_ARMV8_H
33
+
34
+ /** \brief Attribute for device memory (outer only) */
35
+ #define ARM_MPU_ATTR_DEVICE ( 0U )
36
+
37
+ /** \brief Attribute for non-cacheable, normal memory */
38
+ #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
39
+
40
+ /** \brief Attribute for normal memory (outer and inner)
41
+ * \param NT Non-Transient: Set to 1 for non-transient data.
42
+ * \param WB Write-Back: Set to 1 to use write-back update policy.
43
+ * \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
44
+ * \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
45
+ */
46
+ #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
47
+ ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
48
+
49
+ /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
50
+ #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
51
+
52
+ /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
53
+ #define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
54
+
55
+ /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
56
+ #define ARM_MPU_ATTR_DEVICE_nGRE (2U)
57
+
58
+ /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
59
+ #define ARM_MPU_ATTR_DEVICE_GRE (3U)
60
+
61
+ /** \brief Memory Attribute
62
+ * \param O Outer memory attributes
63
+ * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
64
+ */
65
+ #define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
66
+
67
+ /** \brief Normal memory non-shareable */
68
+ #define ARM_MPU_SH_NON (0U)
69
+
70
+ /** \brief Normal memory outer shareable */
71
+ #define ARM_MPU_SH_OUTER (2U)
72
+
73
+ /** \brief Normal memory inner shareable */
74
+ #define ARM_MPU_SH_INNER (3U)
75
+
76
+ /** \brief Memory access permissions
77
+ * \param RO Read-Only: Set to 1 for read-only memory.
78
+ * \param NP Non-Privileged: Set to 1 for non-privileged memory.
79
+ */
80
+ #define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
81
+
82
+ /** \brief Region Base Address Register value
83
+ * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
84
+ * \param SH Defines the Shareability domain for this memory region.
85
+ * \param RO Read-Only: Set to 1 for a read-only memory region.
86
+ * \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
87
+ * \param XN eXecute Never: Set to 1 for a non-executable memory region.
88
+ */
89
+ #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
90
+ (((BASE) & MPU_RBAR_BASE_Msk) | \
91
+ (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
92
+ ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
93
+ (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
94
+
95
+ /** \brief Region Limit Address Register value
96
+ * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
97
+ * \param IDX The attribute index to be associated with this memory region.
98
+ */
99
+ #define ARM_MPU_RLAR(LIMIT, IDX) \
100
+ (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
101
+ (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
102
+ (MPU_RLAR_EN_Msk))
103
+
104
+ #if defined(MPU_RLAR_PXN_Pos)
105
+
106
+ /** \brief Region Limit Address Register with PXN value
107
+ * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
108
+ * \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
109
+ * \param IDX The attribute index to be associated with this memory region.
110
+ */
111
+ #define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
112
+ (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
113
+ (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
114
+ (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
115
+ (MPU_RLAR_EN_Msk))
116
+
117
+ #endif
118
+
119
+ /**
120
+ * Struct for a single MPU Region
121
+ */
122
+ typedef struct {
123
+ uint32_t RBAR; /*!< Region Base Address Register value */
124
+ uint32_t RLAR; /*!< Region Limit Address Register value */
125
+ } ARM_MPU_Region_t;
126
+
127
+ /** Enable the MPU.
128
+ * \param MPU_Control Default access permissions for unconfigured regions.
129
+ */
130
+ __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
131
+ {
132
+ __DMB();
133
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
134
+ #ifdef SCB_SHCSR_MEMFAULTENA_Msk
135
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
136
+ #endif
137
+ __DSB();
138
+ __ISB();
139
+ }
140
+
141
+ /** Disable the MPU.
142
+ */
143
+ __STATIC_INLINE void ARM_MPU_Disable(void)
144
+ {
145
+ __DMB();
146
+ #ifdef SCB_SHCSR_MEMFAULTENA_Msk
147
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
148
+ #endif
149
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
150
+ __DSB();
151
+ __ISB();
152
+ }
153
+
154
+ #ifdef MPU_NS
155
+ /** Enable the Non-secure MPU.
156
+ * \param MPU_Control Default access permissions for unconfigured regions.
157
+ */
158
+ __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
159
+ {
160
+ __DMB();
161
+ MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
162
+ #ifdef SCB_SHCSR_MEMFAULTENA_Msk
163
+ SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
164
+ #endif
165
+ __DSB();
166
+ __ISB();
167
+ }
168
+
169
+ /** Disable the Non-secure MPU.
170
+ */
171
+ __STATIC_INLINE void ARM_MPU_Disable_NS(void)
172
+ {
173
+ __DMB();
174
+ #ifdef SCB_SHCSR_MEMFAULTENA_Msk
175
+ SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
176
+ #endif
177
+ MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
178
+ __DSB();
179
+ __ISB();
180
+ }
181
+ #endif
182
+
183
+ /** Set the memory attribute encoding to the given MPU.
184
+ * \param mpu Pointer to the MPU to be configured.
185
+ * \param idx The attribute index to be set [0-7]
186
+ * \param attr The attribute value to be set.
187
+ */
188
+ __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
189
+ {
190
+ const uint8_t reg = idx / 4U;
191
+ const uint32_t pos = ((idx % 4U) * 8U);
192
+ const uint32_t mask = 0xFFU << pos;
193
+
194
+ if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
195
+ return; // invalid index
196
+ }
197
+
198
+ mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
199
+ }
200
+
201
+ /** Set the memory attribute encoding.
202
+ * \param idx The attribute index to be set [0-7]
203
+ * \param attr The attribute value to be set.
204
+ */
205
+ __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
206
+ {
207
+ ARM_MPU_SetMemAttrEx(MPU, idx, attr);
208
+ }
209
+
210
+ #ifdef MPU_NS
211
+ /** Set the memory attribute encoding to the Non-secure MPU.
212
+ * \param idx The attribute index to be set [0-7]
213
+ * \param attr The attribute value to be set.
214
+ */
215
+ __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
216
+ {
217
+ ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
218
+ }
219
+ #endif
220
+
221
+ /** Clear and disable the given MPU region of the given MPU.
222
+ * \param mpu Pointer to MPU to be used.
223
+ * \param rnr Region number to be cleared.
224
+ */
225
+ __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
226
+ {
227
+ mpu->RNR = rnr;
228
+ mpu->RLAR = 0U;
229
+ }
230
+
231
+ /** Clear and disable the given MPU region.
232
+ * \param rnr Region number to be cleared.
233
+ */
234
+ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
235
+ {
236
+ ARM_MPU_ClrRegionEx(MPU, rnr);
237
+ }
238
+
239
+ #ifdef MPU_NS
240
+ /** Clear and disable the given Non-secure MPU region.
241
+ * \param rnr Region number to be cleared.
242
+ */
243
+ __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
244
+ {
245
+ ARM_MPU_ClrRegionEx(MPU_NS, rnr);
246
+ }
247
+ #endif
248
+
249
+ /** Configure the given MPU region of the given MPU.
250
+ * \param mpu Pointer to MPU to be used.
251
+ * \param rnr Region number to be configured.
252
+ * \param rbar Value for RBAR register.
253
+ * \param rlar Value for RLAR register.
254
+ */
255
+ __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
256
+ {
257
+ mpu->RNR = rnr;
258
+ mpu->RBAR = rbar;
259
+ mpu->RLAR = rlar;
260
+ }
261
+
262
+ /** Configure the given MPU region.
263
+ * \param rnr Region number to be configured.
264
+ * \param rbar Value for RBAR register.
265
+ * \param rlar Value for RLAR register.
266
+ */
267
+ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
268
+ {
269
+ ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
270
+ }
271
+
272
+ #ifdef MPU_NS
273
+ /** Configure the given Non-secure MPU region.
274
+ * \param rnr Region number to be configured.
275
+ * \param rbar Value for RBAR register.
276
+ * \param rlar Value for RLAR register.
277
+ */
278
+ __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
279
+ {
280
+ ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
281
+ }
282
+ #endif
283
+
284
+ /** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx()
285
+ * \param dst Destination data is copied to.
286
+ * \param src Source data is copied from.
287
+ * \param len Amount of data words to be copied.
288
+ */
289
+ __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
290
+ {
291
+ uint32_t i;
292
+ for (i = 0U; i < len; ++i)
293
+ {
294
+ dst[i] = src[i];
295
+ }
296
+ }
297
+
298
+ /** Load the given number of MPU regions from a table to the given MPU.
299
+ * \param mpu Pointer to the MPU registers to be used.
300
+ * \param rnr First region number to be configured.
301
+ * \param table Pointer to the MPU configuration table.
302
+ * \param cnt Amount of regions to be configured.
303
+ */
304
+ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
305
+ {
306
+ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
307
+ if (cnt == 1U) {
308
+ mpu->RNR = rnr;
309
+ ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
310
+ } else {
311
+ uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
312
+ uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
313
+
314
+ mpu->RNR = rnrBase;
315
+ while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
316
+ uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
317
+ ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
318
+ table += c;
319
+ cnt -= c;
320
+ rnrOffset = 0U;
321
+ rnrBase += MPU_TYPE_RALIASES;
322
+ mpu->RNR = rnrBase;
323
+ }
324
+
325
+ ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
326
+ }
327
+ }
328
+
329
+ /** Load the given number of MPU regions from a table.
330
+ * \param rnr First region number to be configured.
331
+ * \param table Pointer to the MPU configuration table.
332
+ * \param cnt Amount of regions to be configured.
333
+ */
334
+ __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
335
+ {
336
+ ARM_MPU_LoadEx(MPU, rnr, table, cnt);
337
+ }
338
+
339
+ #ifdef MPU_NS
340
+ /** Load the given number of MPU regions from a table to the Non-secure MPU.
341
+ * \param rnr First region number to be configured.
342
+ * \param table Pointer to the MPU configuration table.
343
+ * \param cnt Amount of regions to be configured.
344
+ */
345
+ __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
346
+ {
347
+ ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
348
+ }
349
+ #endif
350
+
351
+ #endif
352
+
edge-impulse-sdk/CMSIS/Core/Include/pac_armv81.h ADDED
@@ -0,0 +1,206 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ /******************************************************************************
2
+ * @file pac_armv81.h
3
+ * @brief CMSIS PAC key functions for Armv8.1-M PAC extension
4
+ * @version V1.0.0
5
+ * @date 23. March 2022
6
+ ******************************************************************************/
7
+ /*
8
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
9
+ *
10
+ * SPDX-License-Identifier: Apache-2.0
11
+ *
12
+ * Licensed under the Apache License, Version 2.0 (the License); you may
13
+ * not use this file except in compliance with the License.
14
+ * You may obtain a copy of the License at
15
+ *
16
+ * www.apache.org/licenses/LICENSE-2.0
17
+ *
18
+ * Unless required by applicable law or agreed to in writing, software
19
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21
+ * See the License for the specific language governing permissions and
22
+ * limitations under the License.
23
+ */
24
+
25
+ #if defined ( __ICCARM__ )
26
+ #pragma system_include /* treat file as system include file for MISRA check */
27
+ #elif defined (__clang__)
28
+ #pragma clang system_header /* treat file as system include file */
29
+ #endif
30
+
31
+ #ifndef PAC_ARMV81_H
32
+ #define PAC_ARMV81_H
33
+
34
+
35
+ /* ################### PAC Key functions ########################### */
36
+ /**
37
+ \ingroup CMSIS_Core_FunctionInterface
38
+ \defgroup CMSIS_Core_PacKeyFunctions PAC Key functions
39
+ \brief Functions that access the PAC keys.
40
+ @{
41
+ */
42
+
43
+ #if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1))
44
+
45
+ /**
46
+ \brief read the PAC key used for privileged mode
47
+ \details Reads the PAC key stored in the PAC_KEY_P registers.
48
+ \param [out] pPacKey 128bit PAC key
49
+ */
50
+ __STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) {
51
+ __ASM volatile (
52
+ "mrs r1, pac_key_p_0\n"
53
+ "str r1,[%0,#0]\n"
54
+ "mrs r1, pac_key_p_1\n"
55
+ "str r1,[%0,#4]\n"
56
+ "mrs r1, pac_key_p_2\n"
57
+ "str r1,[%0,#8]\n"
58
+ "mrs r1, pac_key_p_3\n"
59
+ "str r1,[%0,#12]\n"
60
+ : : "r" (pPacKey) : "memory", "r1"
61
+ );
62
+ }
63
+
64
+ /**
65
+ \brief write the PAC key used for privileged mode
66
+ \details writes the given PAC key to the PAC_KEY_P registers.
67
+ \param [in] pPacKey 128bit PAC key
68
+ */
69
+ __STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) {
70
+ __ASM volatile (
71
+ "ldr r1,[%0,#0]\n"
72
+ "msr pac_key_p_0, r1\n"
73
+ "ldr r1,[%0,#4]\n"
74
+ "msr pac_key_p_1, r1\n"
75
+ "ldr r1,[%0,#8]\n"
76
+ "msr pac_key_p_2, r1\n"
77
+ "ldr r1,[%0,#12]\n"
78
+ "msr pac_key_p_3, r1\n"
79
+ : : "r" (pPacKey) : "memory", "r1"
80
+ );
81
+ }
82
+
83
+ /**
84
+ \brief read the PAC key used for unprivileged mode
85
+ \details Reads the PAC key stored in the PAC_KEY_U registers.
86
+ \param [out] pPacKey 128bit PAC key
87
+ */
88
+ __STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) {
89
+ __ASM volatile (
90
+ "mrs r1, pac_key_u_0\n"
91
+ "str r1,[%0,#0]\n"
92
+ "mrs r1, pac_key_u_1\n"
93
+ "str r1,[%0,#4]\n"
94
+ "mrs r1, pac_key_u_2\n"
95
+ "str r1,[%0,#8]\n"
96
+ "mrs r1, pac_key_u_3\n"
97
+ "str r1,[%0,#12]\n"
98
+ : : "r" (pPacKey) : "memory", "r1"
99
+ );
100
+ }
101
+
102
+ /**
103
+ \brief write the PAC key used for unprivileged mode
104
+ \details writes the given PAC key to the PAC_KEY_U registers.
105
+ \param [in] pPacKey 128bit PAC key
106
+ */
107
+ __STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) {
108
+ __ASM volatile (
109
+ "ldr r1,[%0,#0]\n"
110
+ "msr pac_key_u_0, r1\n"
111
+ "ldr r1,[%0,#4]\n"
112
+ "msr pac_key_u_1, r1\n"
113
+ "ldr r1,[%0,#8]\n"
114
+ "msr pac_key_u_2, r1\n"
115
+ "ldr r1,[%0,#12]\n"
116
+ "msr pac_key_u_3, r1\n"
117
+ : : "r" (pPacKey) : "memory", "r1"
118
+ );
119
+ }
120
+
121
+ #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
122
+
123
+ /**
124
+ \brief read the PAC key used for privileged mode (non-secure)
125
+ \details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode.
126
+ \param [out] pPacKey 128bit PAC key
127
+ */
128
+ __STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) {
129
+ __ASM volatile (
130
+ "mrs r1, pac_key_p_0_ns\n"
131
+ "str r1,[%0,#0]\n"
132
+ "mrs r1, pac_key_p_1_ns\n"
133
+ "str r1,[%0,#4]\n"
134
+ "mrs r1, pac_key_p_2_ns\n"
135
+ "str r1,[%0,#8]\n"
136
+ "mrs r1, pac_key_p_3_ns\n"
137
+ "str r1,[%0,#12]\n"
138
+ : : "r" (pPacKey) : "memory", "r1"
139
+ );
140
+ }
141
+
142
+ /**
143
+ \brief write the PAC key used for privileged mode (non-secure)
144
+ \details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode.
145
+ \param [in] pPacKey 128bit PAC key
146
+ */
147
+ __STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) {
148
+ __ASM volatile (
149
+ "ldr r1,[%0,#0]\n"
150
+ "msr pac_key_p_0_ns, r1\n"
151
+ "ldr r1,[%0,#4]\n"
152
+ "msr pac_key_p_1_ns, r1\n"
153
+ "ldr r1,[%0,#8]\n"
154
+ "msr pac_key_p_2_ns, r1\n"
155
+ "ldr r1,[%0,#12]\n"
156
+ "msr pac_key_p_3_ns, r1\n"
157
+ : : "r" (pPacKey) : "memory", "r1"
158
+ );
159
+ }
160
+
161
+ /**
162
+ \brief read the PAC key used for unprivileged mode (non-secure)
163
+ \details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode.
164
+ \param [out] pPacKey 128bit PAC key
165
+ */
166
+ __STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) {
167
+ __ASM volatile (
168
+ "mrs r1, pac_key_u_0_ns\n"
169
+ "str r1,[%0,#0]\n"
170
+ "mrs r1, pac_key_u_1_ns\n"
171
+ "str r1,[%0,#4]\n"
172
+ "mrs r1, pac_key_u_2_ns\n"
173
+ "str r1,[%0,#8]\n"
174
+ "mrs r1, pac_key_u_3_ns\n"
175
+ "str r1,[%0,#12]\n"
176
+ : : "r" (pPacKey) : "memory", "r1"
177
+ );
178
+ }
179
+
180
+ /**
181
+ \brief write the PAC key used for unprivileged mode (non-secure)
182
+ \details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode.
183
+ \param [in] pPacKey 128bit PAC key
184
+ */
185
+ __STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) {
186
+ __ASM volatile (
187
+ "ldr r1,[%0,#0]\n"
188
+ "msr pac_key_u_0_ns, r1\n"
189
+ "ldr r1,[%0,#4]\n"
190
+ "msr pac_key_u_1_ns, r1\n"
191
+ "ldr r1,[%0,#8]\n"
192
+ "msr pac_key_u_2_ns, r1\n"
193
+ "ldr r1,[%0,#12]\n"
194
+ "msr pac_key_u_3_ns, r1\n"
195
+ : : "r" (pPacKey) : "memory", "r1"
196
+ );
197
+ }
198
+
199
+ #endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */
200
+
201
+ #endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */
202
+
203
+ /*@} end of CMSIS_Core_PacKeyFunctions */
204
+
205
+
206
+ #endif /* PAC_ARMV81_H */
edge-impulse-sdk/CMSIS/Core/Include/pmu_armv8.h ADDED
@@ -0,0 +1,337 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ /******************************************************************************
2
+ * @file pmu_armv8.h
3
+ * @brief CMSIS PMU API for Armv8.1-M PMU
4
+ * @version V1.0.1
5
+ * @date 15. April 2020
6
+ ******************************************************************************/
7
+ /*
8
+ * Copyright (c) 2020 Arm Limited. All rights reserved.
9
+ *
10
+ * SPDX-License-Identifier: Apache-2.0
11
+ *
12
+ * Licensed under the Apache License, Version 2.0 (the License); you may
13
+ * not use this file except in compliance with the License.
14
+ * You may obtain a copy of the License at
15
+ *
16
+ * www.apache.org/licenses/LICENSE-2.0
17
+ *
18
+ * Unless required by applicable law or agreed to in writing, software
19
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21
+ * See the License for the specific language governing permissions and
22
+ * limitations under the License.
23
+ */
24
+
25
+ #if defined ( __ICCARM__ )
26
+ #pragma system_include /* treat file as system include file for MISRA check */
27
+ #elif defined (__clang__)
28
+ #pragma clang system_header /* treat file as system include file */
29
+ #endif
30
+
31
+ #ifndef ARM_PMU_ARMV8_H
32
+ #define ARM_PMU_ARMV8_H
33
+
34
+ /**
35
+ * \brief PMU Events
36
+ * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events.
37
+ * */
38
+
39
+ #define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */
40
+ #define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */
41
+ #define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */
42
+ #define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */
43
+ #define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */
44
+ #define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */
45
+ #define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */
46
+ #define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */
47
+ #define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */
48
+ #define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */
49
+ #define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */
50
+ #define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */
51
+ #define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */
52
+ #define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */
53
+ #define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */
54
+ #define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */
55
+ #define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */
56
+ #define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */
57
+ #define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */
58
+ #define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */
59
+ #define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */
60
+ #define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */
61
+ #define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */
62
+ #define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */
63
+ #define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */
64
+ #define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */
65
+ #define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */
66
+ #define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */
67
+ #define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */
68
+ #define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */
69
+ #define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */
70
+ #define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */
71
+ #define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */
72
+ #define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */
73
+ #define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */
74
+ #define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */
75
+ #define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */
76
+ #define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */
77
+ #define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */
78
+ #define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */
79
+ #define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */
80
+ #define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */
81
+ #define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */
82
+ #define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */
83
+ #define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */
84
+ #define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */
85
+ #define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */
86
+ #define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */
87
+ #define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */
88
+ #define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */
89
+ #define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */
90
+ #define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */
91
+ #define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */
92
+ #define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */
93
+ #define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */
94
+ #define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */
95
+ #define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */
96
+ #define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */
97
+ #define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */
98
+ #define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */
99
+ #define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */
100
+ #define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */
101
+ #define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */
102
+ #define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */
103
+ #define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */
104
+ #define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */
105
+ #define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */
106
+ #define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */
107
+ #define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */
108
+ #define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */
109
+ #define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */
110
+ #define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */
111
+ #define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */
112
+ #define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */
113
+ #define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */
114
+ #define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */
115
+ #define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */
116
+ #define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */
117
+ #define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */
118
+ #define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */
119
+ #define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */
120
+ #define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */
121
+ #define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */
122
+ #define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */
123
+ #define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */
124
+ #define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */
125
+ #define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */
126
+ #define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */
127
+ #define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */
128
+ #define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */
129
+ #define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */
130
+ #define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */
131
+ #define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */
132
+ #define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */
133
+ #define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */
134
+ #define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */
135
+ #define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */
136
+ #define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */
137
+ #define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */
138
+ #define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */
139
+ #define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */
140
+ #define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */
141
+ #define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */
142
+ #define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */
143
+ #define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */
144
+ #define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */
145
+ #define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */
146
+ #define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */
147
+ #define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */
148
+ #define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */
149
+ #define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */
150
+ #define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */
151
+ #define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */
152
+ #define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */
153
+ #define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */
154
+ #define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */
155
+ #define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */
156
+ #define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */
157
+ #define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */
158
+ #define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */
159
+ #define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */
160
+ #define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */
161
+ #define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */
162
+ #define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */
163
+ #define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */
164
+ #define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */
165
+ #define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */
166
+ #define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */
167
+ #define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */
168
+ #define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */
169
+ #define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */
170
+
171
+ /** \brief PMU Functions */
172
+
173
+ __STATIC_INLINE void ARM_PMU_Enable(void);
174
+ __STATIC_INLINE void ARM_PMU_Disable(void);
175
+
176
+ __STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type);
177
+
178
+ __STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void);
179
+ __STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void);
180
+
181
+ __STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask);
182
+ __STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask);
183
+
184
+ __STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void);
185
+ __STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num);
186
+
187
+ __STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void);
188
+ __STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask);
189
+
190
+ __STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask);
191
+ __STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask);
192
+
193
+ __STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask);
194
+
195
+ /**
196
+ \brief Enable the PMU
197
+ */
198
+ __STATIC_INLINE void ARM_PMU_Enable(void)
199
+ {
200
+ PMU->CTRL |= PMU_CTRL_ENABLE_Msk;
201
+ }
202
+
203
+ /**
204
+ \brief Disable the PMU
205
+ */
206
+ __STATIC_INLINE void ARM_PMU_Disable(void)
207
+ {
208
+ PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk;
209
+ }
210
+
211
+ /**
212
+ \brief Set event to count for PMU eventer counter
213
+ \param [in] num Event counter (0-30) to configure
214
+ \param [in] type Event to count
215
+ */
216
+ __STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type)
217
+ {
218
+ PMU->EVTYPER[num] = type;
219
+ }
220
+
221
+ /**
222
+ \brief Reset cycle counter
223
+ */
224
+ __STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void)
225
+ {
226
+ PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk;
227
+ }
228
+
229
+ /**
230
+ \brief Reset all event counters
231
+ */
232
+ __STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void)
233
+ {
234
+ PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk;
235
+ }
236
+
237
+ /**
238
+ \brief Enable counters
239
+ \param [in] mask Counters to enable
240
+ \note Enables one or more of the following:
241
+ - event counters (0-30)
242
+ - cycle counter
243
+ */
244
+ __STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask)
245
+ {
246
+ PMU->CNTENSET = mask;
247
+ }
248
+
249
+ /**
250
+ \brief Disable counters
251
+ \param [in] mask Counters to enable
252
+ \note Disables one or more of the following:
253
+ - event counters (0-30)
254
+ - cycle counter
255
+ */
256
+ __STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask)
257
+ {
258
+ PMU->CNTENCLR = mask;
259
+ }
260
+
261
+ /**
262
+ \brief Read cycle counter
263
+ \return Cycle count
264
+ */
265
+ __STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void)
266
+ {
267
+ return PMU->CCNTR;
268
+ }
269
+
270
+ /**
271
+ \brief Read event counter
272
+ \param [in] num Event counter (0-30) to read
273
+ \return Event count
274
+ */
275
+ __STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num)
276
+ {
277
+ return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num];
278
+ }
279
+
280
+ /**
281
+ \brief Read counter overflow status
282
+ \return Counter overflow status bits for the following:
283
+ - event counters (0-30)
284
+ - cycle counter
285
+ */
286
+ __STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void)
287
+ {
288
+ return PMU->OVSSET;
289
+ }
290
+
291
+ /**
292
+ \brief Clear counter overflow status
293
+ \param [in] mask Counter overflow status bits to clear
294
+ \note Clears overflow status bits for one or more of the following:
295
+ - event counters (0-30)
296
+ - cycle counter
297
+ */
298
+ __STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask)
299
+ {
300
+ PMU->OVSCLR = mask;
301
+ }
302
+
303
+ /**
304
+ \brief Enable counter overflow interrupt request
305
+ \param [in] mask Counter overflow interrupt request bits to set
306
+ \note Sets overflow interrupt request bits for one or more of the following:
307
+ - event counters (0-30)
308
+ - cycle counter
309
+ */
310
+ __STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask)
311
+ {
312
+ PMU->INTENSET = mask;
313
+ }
314
+
315
+ /**
316
+ \brief Disable counter overflow interrupt request
317
+ \param [in] mask Counter overflow interrupt request bits to clear
318
+ \note Clears overflow interrupt request bits for one or more of the following:
319
+ - event counters (0-30)
320
+ - cycle counter
321
+ */
322
+ __STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask)
323
+ {
324
+ PMU->INTENCLR = mask;
325
+ }
326
+
327
+ /**
328
+ \brief Software increment event counter
329
+ \param [in] mask Counters to increment
330
+ \note Software increment bits for one or more event counters (0-30)
331
+ */
332
+ __STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask)
333
+ {
334
+ PMU->SWINC = mask;
335
+ }
336
+
337
+ #endif
edge-impulse-sdk/CMSIS/Core/Include/tz_context.h ADDED
@@ -0,0 +1,70 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ /******************************************************************************
2
+ * @file tz_context.h
3
+ * @brief Context Management for Armv8-M TrustZone
4
+ * @version V1.0.1
5
+ * @date 10. January 2018
6
+ ******************************************************************************/
7
+ /*
8
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
9
+ *
10
+ * SPDX-License-Identifier: Apache-2.0
11
+ *
12
+ * Licensed under the Apache License, Version 2.0 (the License); you may
13
+ * not use this file except in compliance with the License.
14
+ * You may obtain a copy of the License at
15
+ *
16
+ * www.apache.org/licenses/LICENSE-2.0
17
+ *
18
+ * Unless required by applicable law or agreed to in writing, software
19
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21
+ * See the License for the specific language governing permissions and
22
+ * limitations under the License.
23
+ */
24
+
25
+ #if defined ( __ICCARM__ )
26
+ #pragma system_include /* treat file as system include file for MISRA check */
27
+ #elif defined (__clang__)
28
+ #pragma clang system_header /* treat file as system include file */
29
+ #endif
30
+
31
+ #ifndef TZ_CONTEXT_H
32
+ #define TZ_CONTEXT_H
33
+
34
+ #include <stdint.h>
35
+
36
+ #ifndef TZ_MODULEID_T
37
+ #define TZ_MODULEID_T
38
+ /// \details Data type that identifies secure software modules called by a process.
39
+ typedef uint32_t TZ_ModuleId_t;
40
+ #endif
41
+
42
+ /// \details TZ Memory ID identifies an allocated memory slot.
43
+ typedef uint32_t TZ_MemoryId_t;
44
+
45
+ /// Initialize secure context memory system
46
+ /// \return execution status (1: success, 0: error)
47
+ uint32_t TZ_InitContextSystem_S (void);
48
+
49
+ /// Allocate context memory for calling secure software modules in TrustZone
50
+ /// \param[in] module identifies software modules called from non-secure mode
51
+ /// \return value != 0 id TrustZone memory slot identifier
52
+ /// \return value 0 no memory available or internal error
53
+ TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
54
+
55
+ /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
56
+ /// \param[in] id TrustZone memory slot identifier
57
+ /// \return execution status (1: success, 0: error)
58
+ uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
59
+
60
+ /// Load secure context (called on RTOS thread context switch)
61
+ /// \param[in] id TrustZone memory slot identifier
62
+ /// \return execution status (1: success, 0: error)
63
+ uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
64
+
65
+ /// Store secure context (called on RTOS thread context switch)
66
+ /// \param[in] id TrustZone memory slot identifier
67
+ /// \return execution status (1: success, 0: error)
68
+ uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
69
+
70
+ #endif // TZ_CONTEXT_H
edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h ADDED
@@ -0,0 +1,539 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ /* ----------------------------------------------------------------------
2
+ * Project: CMSIS DSP Library
3
+ * Title: arm_common_tables.h
4
+ * Description: Extern declaration for common tables
5
+ *
6
+ * @version V1.10.0
7
+ * @date 08 July 2021
8
+ *
9
+ * Target Processor: Cortex-M and Cortex-A cores
10
+ * -------------------------------------------------------------------- */
11
+ /*
12
+ * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
13
+ *
14
+ * SPDX-License-Identifier: Apache-2.0
15
+ *
16
+ * Licensed under the Apache License, Version 2.0 (the License); you may
17
+ * not use this file except in compliance with the License.
18
+ * You may obtain a copy of the License at
19
+ *
20
+ * www.apache.org/licenses/LICENSE-2.0
21
+ *
22
+ * Unless required by applicable law or agreed to in writing, software
23
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
24
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25
+ * See the License for the specific language governing permissions and
26
+ * limitations under the License.
27
+ */
28
+
29
+ #ifndef _ARM_COMMON_TABLES_H
30
+ #define _ARM_COMMON_TABLES_H
31
+
32
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h"
33
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions.h"
34
+
35
+ #ifdef __cplusplus
36
+ extern "C"
37
+ {
38
+ #endif
39
+
40
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
41
+ /* Double Precision Float CFFT twiddles */
42
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024)
43
+ extern const uint16_t armBitRevTable[1024];
44
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
45
+
46
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_16)
47
+ extern const uint64_t twiddleCoefF64_16[32];
48
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
49
+
50
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_32)
51
+ extern const uint64_t twiddleCoefF64_32[64];
52
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
53
+
54
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_64)
55
+ extern const uint64_t twiddleCoefF64_64[128];
56
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
57
+
58
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_128)
59
+ extern const uint64_t twiddleCoefF64_128[256];
60
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
61
+
62
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_256)
63
+ extern const uint64_t twiddleCoefF64_256[512];
64
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
65
+
66
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_512)
67
+ extern const uint64_t twiddleCoefF64_512[1024];
68
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
69
+
70
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_1024)
71
+ extern const uint64_t twiddleCoefF64_1024[2048];
72
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
73
+
74
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_2048)
75
+ extern const uint64_t twiddleCoefF64_2048[4096];
76
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
77
+
78
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_4096)
79
+ extern const uint64_t twiddleCoefF64_4096[8192];
80
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
81
+
82
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16)
83
+ extern const float32_t twiddleCoef_16[32];
84
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
85
+
86
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_32)
87
+ extern const float32_t twiddleCoef_32[64];
88
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
89
+
90
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64)
91
+ extern const float32_t twiddleCoef_64[128];
92
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
93
+
94
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_128)
95
+ extern const float32_t twiddleCoef_128[256];
96
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
97
+
98
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256)
99
+ extern const float32_t twiddleCoef_256[512];
100
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
101
+
102
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_512)
103
+ extern const float32_t twiddleCoef_512[1024];
104
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
105
+
106
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024)
107
+ extern const float32_t twiddleCoef_1024[2048];
108
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
109
+
110
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048)
111
+ extern const float32_t twiddleCoef_2048[4096];
112
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
113
+
114
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096)
115
+ extern const float32_t twiddleCoef_4096[8192];
116
+ #define twiddleCoef twiddleCoef_4096
117
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
118
+
119
+ /* Q31 */
120
+
121
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16)
122
+ extern const q31_t twiddleCoef_16_q31[24];
123
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
124
+
125
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32)
126
+ extern const q31_t twiddleCoef_32_q31[48];
127
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
128
+
129
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64)
130
+ extern const q31_t twiddleCoef_64_q31[96];
131
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
132
+
133
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128)
134
+ extern const q31_t twiddleCoef_128_q31[192];
135
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
136
+
137
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256)
138
+ extern const q31_t twiddleCoef_256_q31[384];
139
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
140
+
141
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512)
142
+ extern const q31_t twiddleCoef_512_q31[768];
143
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
144
+
145
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024)
146
+ extern const q31_t twiddleCoef_1024_q31[1536];
147
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
148
+
149
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048)
150
+ extern const q31_t twiddleCoef_2048_q31[3072];
151
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
152
+
153
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096)
154
+ extern const q31_t twiddleCoef_4096_q31[6144];
155
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
156
+
157
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16)
158
+ extern const q15_t twiddleCoef_16_q15[24];
159
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
160
+
161
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32)
162
+ extern const q15_t twiddleCoef_32_q15[48];
163
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
164
+
165
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64)
166
+ extern const q15_t twiddleCoef_64_q15[96];
167
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
168
+
169
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128)
170
+ extern const q15_t twiddleCoef_128_q15[192];
171
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
172
+
173
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256)
174
+ extern const q15_t twiddleCoef_256_q15[384];
175
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
176
+
177
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512)
178
+ extern const q15_t twiddleCoef_512_q15[768];
179
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
180
+
181
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024)
182
+ extern const q15_t twiddleCoef_1024_q15[1536];
183
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
184
+
185
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048)
186
+ extern const q15_t twiddleCoef_2048_q15[3072];
187
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
188
+
189
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096)
190
+ extern const q15_t twiddleCoef_4096_q15[6144];
191
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
192
+
193
+ /* Double Precision Float RFFT twiddles */
194
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_32)
195
+ extern const uint64_t twiddleCoefF64_rfft_32[32];
196
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
197
+
198
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_64)
199
+ extern const uint64_t twiddleCoefF64_rfft_64[64];
200
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
201
+
202
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_128)
203
+ extern const uint64_t twiddleCoefF64_rfft_128[128];
204
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
205
+
206
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_256)
207
+ extern const uint64_t twiddleCoefF64_rfft_256[256];
208
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
209
+
210
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_512)
211
+ extern const uint64_t twiddleCoefF64_rfft_512[512];
212
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
213
+
214
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_1024)
215
+ extern const uint64_t twiddleCoefF64_rfft_1024[1024];
216
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
217
+
218
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_2048)
219
+ extern const uint64_t twiddleCoefF64_rfft_2048[2048];
220
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
221
+
222
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_4096)
223
+ extern const uint64_t twiddleCoefF64_rfft_4096[4096];
224
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
225
+
226
+
227
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32)
228
+ extern const float32_t twiddleCoef_rfft_32[32];
229
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
230
+
231
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64)
232
+ extern const float32_t twiddleCoef_rfft_64[64];
233
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
234
+
235
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128)
236
+ extern const float32_t twiddleCoef_rfft_128[128];
237
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
238
+
239
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256)
240
+ extern const float32_t twiddleCoef_rfft_256[256];
241
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
242
+
243
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512)
244
+ extern const float32_t twiddleCoef_rfft_512[512];
245
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
246
+
247
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024)
248
+ extern const float32_t twiddleCoef_rfft_1024[1024];
249
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
250
+
251
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048)
252
+ extern const float32_t twiddleCoef_rfft_2048[2048];
253
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
254
+
255
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096)
256
+ extern const float32_t twiddleCoef_rfft_4096[4096];
257
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
258
+
259
+
260
+ /* Double precision floating-point bit reversal tables */
261
+
262
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_16)
263
+ #define ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH ((uint16_t)12)
264
+ extern const uint16_t armBitRevIndexTableF64_16[ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH];
265
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
266
+
267
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_32)
268
+ #define ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH ((uint16_t)24)
269
+ extern const uint16_t armBitRevIndexTableF64_32[ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH];
270
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
271
+
272
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_64)
273
+ #define ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH ((uint16_t)56)
274
+ extern const uint16_t armBitRevIndexTableF64_64[ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH];
275
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
276
+
277
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_128)
278
+ #define ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH ((uint16_t)112)
279
+ extern const uint16_t armBitRevIndexTableF64_128[ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH];
280
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
281
+
282
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_256)
283
+ #define ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH ((uint16_t)240)
284
+ extern const uint16_t armBitRevIndexTableF64_256[ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH];
285
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
286
+
287
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_512)
288
+ #define ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH ((uint16_t)480)
289
+ extern const uint16_t armBitRevIndexTableF64_512[ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH];
290
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
291
+
292
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_1024)
293
+ #define ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH ((uint16_t)992)
294
+ extern const uint16_t armBitRevIndexTableF64_1024[ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH];
295
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
296
+
297
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_2048)
298
+ #define ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH ((uint16_t)1984)
299
+ extern const uint16_t armBitRevIndexTableF64_2048[ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH];
300
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
301
+
302
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_4096)
303
+ #define ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH ((uint16_t)4032)
304
+ extern const uint16_t armBitRevIndexTableF64_4096[ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH];
305
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
306
+ /* floating-point bit reversal tables */
307
+
308
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_16)
309
+ #define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
310
+ extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
311
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
312
+
313
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_32)
314
+ #define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
315
+ extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
316
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
317
+
318
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_64)
319
+ #define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
320
+ extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
321
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
322
+
323
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_128)
324
+ #define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
325
+ extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
326
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
327
+
328
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_256)
329
+ #define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
330
+ extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
331
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
332
+
333
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_512)
334
+ #define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
335
+ extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
336
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
337
+
338
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_1024)
339
+ #define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
340
+ extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
341
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
342
+
343
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_2048)
344
+ #define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
345
+ extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
346
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
347
+
348
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_4096)
349
+ #define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
350
+ extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
351
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
352
+
353
+
354
+ /* fixed-point bit reversal tables */
355
+
356
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_16)
357
+ #define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
358
+ extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
359
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
360
+
361
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_32)
362
+ #define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
363
+ extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
364
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
365
+
366
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_64)
367
+ #define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
368
+ extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
369
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
370
+
371
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_128)
372
+ #define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
373
+ extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
374
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
375
+
376
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_256)
377
+ #define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
378
+ extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
379
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
380
+
381
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_512)
382
+ #define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
383
+ extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
384
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
385
+
386
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_1024)
387
+ #define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
388
+ extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
389
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
390
+
391
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_2048)
392
+ #define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
393
+ extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
394
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
395
+
396
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_4096)
397
+ #define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
398
+ extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
399
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
400
+
401
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_F32)
402
+ extern const float32_t realCoefA[8192];
403
+ extern const float32_t realCoefB[8192];
404
+ #endif
405
+
406
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q31)
407
+ extern const q31_t realCoefAQ31[8192];
408
+ extern const q31_t realCoefBQ31[8192];
409
+ #endif
410
+
411
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q15)
412
+ extern const q15_t realCoefAQ15[8192];
413
+ extern const q15_t realCoefBQ15[8192];
414
+ #endif
415
+
416
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_128)
417
+ extern const float32_t Weights_128[256];
418
+ extern const float32_t cos_factors_128[128];
419
+ #endif
420
+
421
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_512)
422
+ extern const float32_t Weights_512[1024];
423
+ extern const float32_t cos_factors_512[512];
424
+ #endif
425
+
426
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_2048)
427
+ extern const float32_t Weights_2048[4096];
428
+ extern const float32_t cos_factors_2048[2048];
429
+ #endif
430
+
431
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_8192)
432
+ extern const float32_t Weights_8192[16384];
433
+ extern const float32_t cos_factors_8192[8192];
434
+ #endif
435
+
436
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_128)
437
+ extern const q15_t WeightsQ15_128[256];
438
+ extern const q15_t cos_factorsQ15_128[128];
439
+ #endif
440
+
441
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_512)
442
+ extern const q15_t WeightsQ15_512[1024];
443
+ extern const q15_t cos_factorsQ15_512[512];
444
+ #endif
445
+
446
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_2048)
447
+ extern const q15_t WeightsQ15_2048[4096];
448
+ extern const q15_t cos_factorsQ15_2048[2048];
449
+ #endif
450
+
451
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_8192)
452
+ extern const q15_t WeightsQ15_8192[16384];
453
+ extern const q15_t cos_factorsQ15_8192[8192];
454
+ #endif
455
+
456
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_128)
457
+ extern const q31_t WeightsQ31_128[256];
458
+ extern const q31_t cos_factorsQ31_128[128];
459
+ #endif
460
+
461
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_512)
462
+ extern const q31_t WeightsQ31_512[1024];
463
+ extern const q31_t cos_factorsQ31_512[512];
464
+ #endif
465
+
466
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_2048)
467
+ extern const q31_t WeightsQ31_2048[4096];
468
+ extern const q31_t cos_factorsQ31_2048[2048];
469
+ #endif
470
+
471
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_8192)
472
+ extern const q31_t WeightsQ31_8192[16384];
473
+ extern const q31_t cos_factorsQ31_8192[8192];
474
+ #endif
475
+
476
+ #endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_TABLES) */
477
+
478
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_ALLOW_TABLES)
479
+
480
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q15)
481
+ extern const q15_t armRecipTableQ15[64];
482
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
483
+
484
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q31)
485
+ extern const q31_t armRecipTableQ31[64];
486
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
487
+
488
+ /* Tables for Fast Math Sine and Cosine */
489
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_F32)
490
+ extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
491
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
492
+
493
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q31)
494
+ extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
495
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
496
+
497
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q15)
498
+ extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
499
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
500
+
501
+ /* Fast vector sqrt */
502
+ #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE)
503
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE)
504
+ extern const q31_t sqrtTable_Q31[256];
505
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
506
+ #endif
507
+
508
+ /* Accurate scalar sqrt */
509
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SQRT_Q31)
510
+ extern const q31_t sqrt_initial_lut_q31[32];
511
+ #endif
512
+
513
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SQRT_Q15)
514
+ extern const q15_t sqrt_initial_lut_q15[16];
515
+ #endif
516
+
517
+ #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE)
518
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE)
519
+ extern const q15_t sqrtTable_Q15[256];
520
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
521
+ #endif
522
+
523
+ #endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_TABLES) */
524
+
525
+ #if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)
526
+ extern const float32_t exp_tab[8];
527
+ extern const float32_t __logf_lut_f32[8];
528
+ #endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) */
529
+
530
+ #if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)
531
+ extern const unsigned char hwLUT[256];
532
+ #endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */
533
+
534
+ #ifdef __cplusplus
535
+ }
536
+ #endif
537
+
538
+ #endif /* ARM_COMMON_TABLES_H */
539
+
edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables_f16.h ADDED
@@ -0,0 +1,132 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ /* ----------------------------------------------------------------------
2
+ * Project: CMSIS DSP Library
3
+ * Title: arm_common_tables_f16.h
4
+ * Description: Extern declaration for common tables
5
+ *
6
+ * @version V1.10.0
7
+ * @date 08 July 2021
8
+ *
9
+ * Target Processor: Cortex-M and Cortex-A cores
10
+ * -------------------------------------------------------------------- */
11
+ /*
12
+ * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
13
+ *
14
+ * SPDX-License-Identifier: Apache-2.0
15
+ *
16
+ * Licensed under the Apache License, Version 2.0 (the License); you may
17
+ * not use this file except in compliance with the License.
18
+ * You may obtain a copy of the License at
19
+ *
20
+ * www.apache.org/licenses/LICENSE-2.0
21
+ *
22
+ * Unless required by applicable law or agreed to in writing, software
23
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
24
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25
+ * See the License for the specific language governing permissions and
26
+ * limitations under the License.
27
+ */
28
+
29
+ #ifndef _ARM_COMMON_TABLES_F16_H
30
+ #define _ARM_COMMON_TABLES_F16_H
31
+
32
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types_f16.h"
33
+
34
+ #ifdef __cplusplus
35
+ extern "C"
36
+ {
37
+ #endif
38
+
39
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
40
+
41
+ /* F16 */
42
+ #if !defined(__CC_ARM) && defined(ARM_FLOAT16_SUPPORTED)
43
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_16)
44
+ extern const float16_t twiddleCoefF16_16[32];
45
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
46
+
47
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_32)
48
+ extern const float16_t twiddleCoefF16_32[64];
49
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
50
+
51
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_64)
52
+ extern const float16_t twiddleCoefF16_64[128];
53
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
54
+
55
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_128)
56
+ extern const float16_t twiddleCoefF16_128[256];
57
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
58
+
59
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_256)
60
+ extern const float16_t twiddleCoefF16_256[512];
61
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
62
+
63
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_512)
64
+ extern const float16_t twiddleCoefF16_512[1024];
65
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
66
+
67
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_1024)
68
+ extern const float16_t twiddleCoefF16_1024[2048];
69
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
70
+
71
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_2048)
72
+ extern const float16_t twiddleCoefF16_2048[4096];
73
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
74
+
75
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_4096)
76
+ extern const float16_t twiddleCoefF16_4096[8192];
77
+ #define twiddleCoefF16 twiddleCoefF16_4096
78
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
79
+
80
+
81
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_32)
82
+ extern const float16_t twiddleCoefF16_rfft_32[32];
83
+ #endif
84
+
85
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_64)
86
+ extern const float16_t twiddleCoefF16_rfft_64[64];
87
+ #endif
88
+
89
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_128)
90
+ extern const float16_t twiddleCoefF16_rfft_128[128];
91
+ #endif
92
+
93
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_256)
94
+ extern const float16_t twiddleCoefF16_rfft_256[256];
95
+ #endif
96
+
97
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_512)
98
+ extern const float16_t twiddleCoefF16_rfft_512[512];
99
+ #endif
100
+
101
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_1024)
102
+ extern const float16_t twiddleCoefF16_rfft_1024[1024];
103
+ #endif
104
+
105
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_2048)
106
+ extern const float16_t twiddleCoefF16_rfft_2048[2048];
107
+ #endif
108
+
109
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_4096)
110
+ extern const float16_t twiddleCoefF16_rfft_4096[4096];
111
+ #endif
112
+
113
+ #endif /* ARMAC5 */
114
+
115
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
116
+
117
+ #if !defined(__CC_ARM) && defined(ARM_FLOAT16_SUPPORTED)
118
+
119
+ #if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)
120
+ extern const float16_t exp_tab_f16[8];
121
+ extern const float16_t __logf_lut_f16[8];
122
+ #endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) */
123
+ #endif
124
+
125
+
126
+ #ifdef __cplusplus
127
+ }
128
+ #endif
129
+
130
+ #endif /* _ARM_COMMON_TABLES_F16_H */
131
+
132
+
edge-impulse-sdk/CMSIS/DSP/Include/arm_const_structs.h ADDED
@@ -0,0 +1,86 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ /* ----------------------------------------------------------------------
2
+ * Project: CMSIS DSP Library
3
+ * Title: arm_const_structs.h
4
+ * Description: Constant structs that are initialized for user convenience.
5
+ * For example, some can be given as arguments to the arm_cfft_f32() function.
6
+ *
7
+ * @version V1.10.0
8
+ * @date 08 July 2021
9
+ *
10
+ * Target Processor: Cortex-M and Cortex-A cores
11
+ * -------------------------------------------------------------------- */
12
+ /*
13
+ * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
14
+ *
15
+ * SPDX-License-Identifier: Apache-2.0
16
+ *
17
+ * Licensed under the Apache License, Version 2.0 (the License); you may
18
+ * not use this file except in compliance with the License.
19
+ * You may obtain a copy of the License at
20
+ *
21
+ * www.apache.org/licenses/LICENSE-2.0
22
+ *
23
+ * Unless required by applicable law or agreed to in writing, software
24
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
25
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
26
+ * See the License for the specific language governing permissions and
27
+ * limitations under the License.
28
+ */
29
+
30
+ #ifndef _ARM_CONST_STRUCTS_H
31
+ #define _ARM_CONST_STRUCTS_H
32
+
33
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h"
34
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h"
35
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h"
36
+
37
+ #ifdef __cplusplus
38
+ extern "C"
39
+ {
40
+ #endif
41
+ extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len16;
42
+ extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len32;
43
+ extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len64;
44
+ extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len128;
45
+ extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len256;
46
+ extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len512;
47
+ extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len1024;
48
+ extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len2048;
49
+ extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len4096;
50
+
51
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
52
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
53
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
54
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
55
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
56
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
57
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
58
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
59
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
60
+
61
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
62
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
63
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
64
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
65
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
66
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
67
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
68
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
69
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
70
+
71
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
72
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
73
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
74
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
75
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
76
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
77
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
78
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
79
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
80
+
81
+ #ifdef __cplusplus
82
+ }
83
+ #endif
84
+
85
+ #endif
86
+
edge-impulse-sdk/CMSIS/DSP/Include/arm_const_structs_f16.h ADDED
@@ -0,0 +1,77 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ /* ----------------------------------------------------------------------
2
+ * Project: CMSIS DSP Library
3
+ * Title: arm_const_structs_f16.h
4
+ * Description: Constant structs that are initialized for user convenience.
5
+ * For example, some can be given as arguments to the arm_cfft_f16() function.
6
+ *
7
+ * @version V1.10.0
8
+ * @date 08 July 2021
9
+ *
10
+ * Target Processor: Cortex-M and Cortex-A cores
11
+ * -------------------------------------------------------------------- */
12
+ /*
13
+ * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
14
+ *
15
+ * SPDX-License-Identifier: Apache-2.0
16
+ *
17
+ * Licensed under the Apache License, Version 2.0 (the License); you may
18
+ * not use this file except in compliance with the License.
19
+ * You may obtain a copy of the License at
20
+ *
21
+ * www.apache.org/licenses/LICENSE-2.0
22
+ *
23
+ * Unless required by applicable law or agreed to in writing, software
24
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
25
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
26
+ * See the License for the specific language governing permissions and
27
+ * limitations under the License.
28
+ */
29
+
30
+ #ifndef _ARM_CONST_STRUCTS_F16_H
31
+ #define _ARM_CONST_STRUCTS_F16_H
32
+
33
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types_f16.h"
34
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h"
35
+ #include "arm_common_tables_f16.h"
36
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions_f16.h"
37
+
38
+ #ifdef __cplusplus
39
+ extern "C"
40
+ {
41
+ #endif
42
+
43
+ #if !defined(__CC_ARM) && defined(ARM_FLOAT16_SUPPORTED)
44
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_16) && defined(ARM_TABLE_BITREVIDX_FLT_16))
45
+ extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len16;
46
+ #endif
47
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_32) && defined(ARM_TABLE_BITREVIDX_FLT_32))
48
+ extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len32;
49
+ #endif
50
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_64) && defined(ARM_TABLE_BITREVIDX_FLT_64))
51
+ extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len64;
52
+ #endif
53
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_128) && defined(ARM_TABLE_BITREVIDX_FLT_128))
54
+ extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len128;
55
+ #endif
56
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_256) && defined(ARM_TABLE_BITREVIDX_FLT_256))
57
+ extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len256;
58
+ #endif
59
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_512) && defined(ARM_TABLE_BITREVIDX_FLT_512))
60
+ extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len512;
61
+ #endif
62
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024))
63
+ extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len1024;
64
+ #endif
65
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048))
66
+ extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len2048;
67
+ #endif
68
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_4096) && defined(ARM_TABLE_BITREVIDX_FLT_4096))
69
+ extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len4096;
70
+ #endif
71
+ #endif
72
+
73
+ #ifdef __cplusplus
74
+ }
75
+ #endif
76
+
77
+ #endif
edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h ADDED
@@ -0,0 +1,753 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ /* ----------------------------------------------------------------------
2
+ * Project: CMSIS DSP Library
3
+ * Title: arm_helium_utils.h
4
+ * Description: Utility functions for Helium development
5
+ *
6
+ * @version V1.10.0
7
+ * @date 08 July 2021
8
+ *
9
+ * Target Processor: Cortex-M and Cortex-A cores
10
+ * -------------------------------------------------------------------- */
11
+ /*
12
+ * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
13
+ *
14
+ * SPDX-License-Identifier: Apache-2.0
15
+ *
16
+ * Licensed under the Apache License, Version 2.0 (the License); you may
17
+ * not use this file except in compliance with the License.
18
+ * You may obtain a copy of the License at
19
+ *
20
+ * www.apache.org/licenses/LICENSE-2.0
21
+ *
22
+ * Unless required by applicable law or agreed to in writing, software
23
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
24
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25
+ * See the License for the specific language governing permissions and
26
+ * limitations under the License.
27
+ */
28
+
29
+ #ifndef _ARM_UTILS_HELIUM_H_
30
+ #define _ARM_UTILS_HELIUM_H_
31
+
32
+
33
+ #ifdef __cplusplus
34
+ extern "C"
35
+ {
36
+ #endif
37
+ /***************************************
38
+
39
+ Definitions available for MVEF and MVEI
40
+
41
+ ***************************************/
42
+ #if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI)) && !defined(ARM_MATH_AUTOVECTORIZE)
43
+
44
+ #define INACTIVELANE 0 /* inactive lane content */
45
+
46
+
47
+ #endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI) */
48
+
49
+ /***************************************
50
+
51
+ Definitions available for MVEF only
52
+
53
+ ***************************************/
54
+ #if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE)
55
+
56
+ __STATIC_FORCEINLINE float32_t vecAddAcrossF32Mve(float32x4_t in)
57
+ {
58
+ float32_t acc;
59
+
60
+ acc = vgetq_lane(in, 0) + vgetq_lane(in, 1) +
61
+ vgetq_lane(in, 2) + vgetq_lane(in, 3);
62
+
63
+ return acc;
64
+ }
65
+
66
+
67
+
68
+
69
+ /* newton initial guess */
70
+ #define INVSQRT_MAGIC_F32 0x5f3759df
71
+ #define INV_NEWTON_INIT_F32 0x7EF127EA
72
+
73
+
74
+ #define INVSQRT_NEWTON_MVE_F32(invSqrt, xHalf, xStart)\
75
+ { \
76
+ float32x4_t tmp; \
77
+ \
78
+ /* tmp = xhalf * x * x */ \
79
+ tmp = vmulq(xStart, xStart); \
80
+ tmp = vmulq(tmp, xHalf); \
81
+ /* (1.5f - xhalf * x * x) */ \
82
+ tmp = vsubq(vdupq_n_f32(1.5f), tmp); \
83
+ /* x = x*(1.5f-xhalf*x*x); */ \
84
+ invSqrt = vmulq(tmp, xStart); \
85
+ }
86
+ #endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) */
87
+
88
+
89
+ /***************************************
90
+
91
+ Definitions available for f16 datatype with HW acceleration only
92
+
93
+ ***************************************/
94
+ #if defined(ARM_FLOAT16_SUPPORTED)
95
+ #if defined (ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE)
96
+
97
+ __STATIC_FORCEINLINE float16_t vecAddAcrossF16Mve(float16x8_t in)
98
+ {
99
+ float16x8_t tmpVec;
100
+ _Float16 acc;
101
+
102
+ tmpVec = (float16x8_t) vrev32q_s16((int16x8_t) in);
103
+ in = vaddq_f16(tmpVec, in);
104
+ tmpVec = (float16x8_t) vrev64q_s32((int32x4_t) in);
105
+ in = vaddq_f16(tmpVec, in);
106
+ acc = (_Float16)vgetq_lane_f16(in, 0) + (_Float16)vgetq_lane_f16(in, 4);
107
+
108
+ return acc;
109
+ }
110
+
111
+ __STATIC_FORCEINLINE float16x8_t __mve_cmplx_sum_intra_vec_f16(
112
+ float16x8_t vecIn)
113
+ {
114
+ float16x8_t vecTmp, vecOut;
115
+ uint32_t tmp;
116
+
117
+ vecTmp = (float16x8_t) vrev64q_s32((int32x4_t) vecIn);
118
+ // TO TRACK : using canonical addition leads to unefficient code generation for f16
119
+ // vecTmp = vecTmp + vecAccCpx0;
120
+ /*
121
+ * Compute
122
+ * re0+re1 | im0+im1 | re0+re1 | im0+im1
123
+ * re2+re3 | im2+im3 | re2+re3 | im2+im3
124
+ */
125
+ vecTmp = vaddq_f16(vecTmp, vecIn);
126
+ vecOut = vecTmp;
127
+ /*
128
+ * shift left, random tmp insertion in bottom
129
+ */
130
+ vecOut = vreinterpretq_f16_s32(vshlcq_s32(vreinterpretq_s32_f16(vecOut) , &tmp, 32));
131
+ /*
132
+ * Compute:
133
+ * DONTCARE | DONTCARE | re0+re1+re0+re1 |im0+im1+im0+im1
134
+ * re0+re1+re2+re3 | im0+im1+im2+im3 | re2+re3+re2+re3 |im2+im3+im2+im3
135
+ */
136
+ vecOut = vaddq_f16(vecOut, vecTmp);
137
+ /*
138
+ * Cmplx sum is in 4rd & 5th f16 elt
139
+ * return full vector
140
+ */
141
+ return vecOut;
142
+ }
143
+
144
+
145
+ #define mve_cmplx_sum_intra_r_i_f16(vec, Re, Im) \
146
+ { \
147
+ float16x8_t vecOut = __mve_cmplx_sum_intra_vec_f16(vec); \
148
+ Re = vgetq_lane(vecOut, 4); \
149
+ Im = vgetq_lane(vecOut, 5); \
150
+ }
151
+
152
+ __STATIC_FORCEINLINE void mve_cmplx_sum_intra_vec_f16(
153
+ float16x8_t vecIn,
154
+ float16_t *pOut)
155
+ {
156
+ float16x8_t vecOut = __mve_cmplx_sum_intra_vec_f16(vecIn);
157
+ /*
158
+ * Cmplx sum is in 4rd & 5th f16 elt
159
+ * use 32-bit extraction
160
+ */
161
+ *(float32_t *) pOut = ((float32x4_t) vecOut)[2];
162
+ }
163
+
164
+
165
+ #define INVSQRT_MAGIC_F16 0x59ba /* ( 0x1ba = 0x3759df >> 13) */
166
+
167
+ /* canonical version of INVSQRT_NEWTON_MVE_F16 leads to bad performance */
168
+ #define INVSQRT_NEWTON_MVE_F16(invSqrt, xHalf, xStart) \
169
+ { \
170
+ float16x8_t tmp; \
171
+ \
172
+ /* tmp = xhalf * x * x */ \
173
+ tmp = vmulq(xStart, xStart); \
174
+ tmp = vmulq(tmp, xHalf); \
175
+ /* (1.5f - xhalf * x * x) */ \
176
+ tmp = vsubq(vdupq_n_f16((float16_t)1.5), tmp); \
177
+ /* x = x*(1.5f-xhalf*x*x); */ \
178
+ invSqrt = vmulq(tmp, xStart); \
179
+ }
180
+
181
+ #endif
182
+ #endif
183
+
184
+ /***************************************
185
+
186
+ Definitions available for MVEI and MVEF only
187
+
188
+ ***************************************/
189
+ #if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI)) && !defined(ARM_MATH_AUTOVECTORIZE)
190
+ /* Following functions are used to transpose matrix in f32 and q31 cases */
191
+ __STATIC_INLINE arm_status arm_mat_trans_32bit_2x2_mve(
192
+ uint32_t * pDataSrc,
193
+ uint32_t * pDataDest)
194
+ {
195
+ static const uint32x4_t vecOffs = { 0, 2, 1, 3 };
196
+ /*
197
+ *
198
+ * | 0 1 | => | 0 2 |
199
+ * | 2 3 | | 1 3 |
200
+ *
201
+ */
202
+ uint32x4_t vecIn = vldrwq_u32((uint32_t const *)pDataSrc);
203
+ vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs, vecIn);
204
+
205
+ return (ARM_MATH_SUCCESS);
206
+ }
207
+
208
+ __STATIC_INLINE arm_status arm_mat_trans_32bit_3x3_mve(
209
+ uint32_t * pDataSrc,
210
+ uint32_t * pDataDest)
211
+ {
212
+ const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
213
+ const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
214
+ /*
215
+ *
216
+ * | 0 1 2 | | 0 3 6 | 4 x 32 flattened version | 0 3 6 1 |
217
+ * | 3 4 5 | => | 1 4 7 | => | 4 7 2 5 |
218
+ * | 6 7 8 | | 2 5 8 | (row major) | 8 . . . |
219
+ *
220
+ */
221
+ uint32x4_t vecIn1 = vldrwq_u32((uint32_t const *) pDataSrc);
222
+ uint32x4_t vecIn2 = vldrwq_u32((uint32_t const *) &pDataSrc[4]);
223
+
224
+ vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs1, vecIn1);
225
+ vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs2, vecIn2);
226
+
227
+ pDataDest[8] = pDataSrc[8];
228
+
229
+ return (ARM_MATH_SUCCESS);
230
+ }
231
+
232
+ __STATIC_INLINE arm_status arm_mat_trans_32bit_4x4_mve(uint32_t * pDataSrc, uint32_t * pDataDest)
233
+ {
234
+ /*
235
+ * 4x4 Matrix transposition
236
+ * is 4 x de-interleave operation
237
+ *
238
+ * 0 1 2 3 0 4 8 12
239
+ * 4 5 6 7 1 5 9 13
240
+ * 8 9 10 11 2 6 10 14
241
+ * 12 13 14 15 3 7 11 15
242
+ */
243
+
244
+ uint32x4x4_t vecIn;
245
+
246
+ vecIn = vld4q((uint32_t const *) pDataSrc);
247
+ vstrwq(pDataDest, vecIn.val[0]);
248
+ pDataDest += 4;
249
+ vstrwq(pDataDest, vecIn.val[1]);
250
+ pDataDest += 4;
251
+ vstrwq(pDataDest, vecIn.val[2]);
252
+ pDataDest += 4;
253
+ vstrwq(pDataDest, vecIn.val[3]);
254
+
255
+ return (ARM_MATH_SUCCESS);
256
+ }
257
+
258
+
259
+ __STATIC_INLINE arm_status arm_mat_trans_32bit_generic_mve(
260
+ uint16_t srcRows,
261
+ uint16_t srcCols,
262
+ uint32_t * pDataSrc,
263
+ uint32_t * pDataDest)
264
+ {
265
+ uint32x4_t vecOffs;
266
+ uint32_t i;
267
+ uint32_t blkCnt;
268
+ uint32_t const *pDataC;
269
+ uint32_t *pDataDestR;
270
+ uint32x4_t vecIn;
271
+
272
+ vecOffs = vidupq_u32((uint32_t)0, 1);
273
+ vecOffs = vecOffs * srcCols;
274
+
275
+ i = srcCols;
276
+ do
277
+ {
278
+ pDataC = (uint32_t const *) pDataSrc;
279
+ pDataDestR = pDataDest;
280
+
281
+ blkCnt = srcRows >> 2;
282
+ while (blkCnt > 0U)
283
+ {
284
+ vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs);
285
+ vstrwq(pDataDestR, vecIn);
286
+ pDataDestR += 4;
287
+ pDataC = pDataC + srcCols * 4;
288
+ /*
289
+ * Decrement the blockSize loop counter
290
+ */
291
+ blkCnt--;
292
+ }
293
+
294
+ /*
295
+ * tail
296
+ */
297
+ blkCnt = srcRows & 3;
298
+ if (blkCnt > 0U)
299
+ {
300
+ mve_pred16_t p0 = vctp32q(blkCnt);
301
+ vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs);
302
+ vstrwq_p(pDataDestR, vecIn, p0);
303
+ }
304
+
305
+ pDataSrc += 1;
306
+ pDataDest += srcRows;
307
+ }
308
+ while (--i);
309
+
310
+ return (ARM_MATH_SUCCESS);
311
+ }
312
+
313
+ __STATIC_INLINE arm_status arm_mat_cmplx_trans_32bit(
314
+ uint16_t srcRows,
315
+ uint16_t srcCols,
316
+ uint32_t *pDataSrc,
317
+ uint16_t dstRows,
318
+ uint16_t dstCols,
319
+ uint32_t *pDataDest)
320
+ {
321
+ uint32_t i;
322
+ uint32_t const *pDataC;
323
+ uint32_t *pDataRow;
324
+ uint32_t *pDataDestR, *pDataDestRow;
325
+ uint32x4_t vecOffsRef, vecOffsCur;
326
+ uint32_t blkCnt;
327
+ uint32x4_t vecIn;
328
+
329
+ #ifdef ARM_MATH_MATRIX_CHECK
330
+ /*
331
+ * Check for matrix mismatch condition
332
+ */
333
+ if ((srcRows != dstCols) || (srcCols != dstRows))
334
+ {
335
+ /*
336
+ * Set status as ARM_MATH_SIZE_MISMATCH
337
+ */
338
+ return ARM_MATH_SIZE_MISMATCH;
339
+ }
340
+ #else
341
+ (void)dstRows;
342
+ (void)dstCols;
343
+ #endif
344
+
345
+ /* 2x2, 3x3 and 4x4 specialization to be added */
346
+
347
+ vecOffsRef[0] = 0;
348
+ vecOffsRef[1] = 1;
349
+ vecOffsRef[2] = srcCols << 1;
350
+ vecOffsRef[3] = (srcCols << 1) + 1;
351
+
352
+ pDataRow = pDataSrc;
353
+ pDataDestRow = pDataDest;
354
+ i = srcCols;
355
+ do
356
+ {
357
+ pDataC = (uint32_t const *) pDataRow;
358
+ pDataDestR = pDataDestRow;
359
+ vecOffsCur = vecOffsRef;
360
+
361
+ blkCnt = (srcRows * CMPLX_DIM) >> 2;
362
+ while (blkCnt > 0U)
363
+ {
364
+ vecIn = vldrwq_gather_shifted_offset(pDataC, vecOffsCur);
365
+ vstrwq(pDataDestR, vecIn);
366
+ pDataDestR += 4;
367
+ vecOffsCur = vaddq(vecOffsCur, (srcCols << 2));
368
+ /*
369
+ * Decrement the blockSize loop counter
370
+ */
371
+ blkCnt--;
372
+ }
373
+ /*
374
+ * tail
375
+ * (will be merged thru tail predication)
376
+ */
377
+ blkCnt = (srcRows * CMPLX_DIM) & 3;
378
+ if (blkCnt > 0U)
379
+ {
380
+ mve_pred16_t p0 = vctp32q(blkCnt);
381
+ vecIn = vldrwq_gather_shifted_offset(pDataC, vecOffsCur);
382
+ vstrwq_p(pDataDestR, vecIn, p0);
383
+ }
384
+
385
+ pDataRow += CMPLX_DIM;
386
+ pDataDestRow += (srcRows * CMPLX_DIM);
387
+ }
388
+ while (--i);
389
+
390
+ return (ARM_MATH_SUCCESS);
391
+ }
392
+
393
+ __STATIC_INLINE arm_status arm_mat_trans_16bit_2x2(uint16_t * pDataSrc, uint16_t * pDataDest)
394
+ {
395
+ pDataDest[0] = pDataSrc[0];
396
+ pDataDest[3] = pDataSrc[3];
397
+ pDataDest[2] = pDataSrc[1];
398
+ pDataDest[1] = pDataSrc[2];
399
+
400
+ return (ARM_MATH_SUCCESS);
401
+ }
402
+
403
+ __STATIC_INLINE arm_status arm_mat_trans_16bit_3x3_mve(uint16_t * pDataSrc, uint16_t * pDataDest)
404
+ {
405
+ static const uint16_t stridesTr33[8] = { 0, 3, 6, 1, 4, 7, 2, 5 };
406
+ uint16x8_t vecOffs1;
407
+ uint16x8_t vecIn1;
408
+ /*
409
+ *
410
+ * | 0 1 2 | | 0 3 6 | 8 x 16 flattened version | 0 3 6 1 4 7 2 5 |
411
+ * | 3 4 5 | => | 1 4 7 | => | 8 . . . . . . . |
412
+ * | 6 7 8 | | 2 5 8 | (row major)
413
+ *
414
+ */
415
+ vecOffs1 = vldrhq_u16((uint16_t const *) stridesTr33);
416
+ vecIn1 = vldrhq_u16((uint16_t const *) pDataSrc);
417
+
418
+ vstrhq_scatter_shifted_offset_u16(pDataDest, vecOffs1, vecIn1);
419
+
420
+ pDataDest[8] = pDataSrc[8];
421
+
422
+ return (ARM_MATH_SUCCESS);
423
+ }
424
+
425
+
426
+ __STATIC_INLINE arm_status arm_mat_trans_16bit_4x4_mve(uint16_t * pDataSrc, uint16_t * pDataDest)
427
+ {
428
+ static const uint16_t stridesTr44_1[8] = { 0, 4, 8, 12, 1, 5, 9, 13 };
429
+ static const uint16_t stridesTr44_2[8] = { 2, 6, 10, 14, 3, 7, 11, 15 };
430
+ uint16x8_t vecOffs1, vecOffs2;
431
+ uint16x8_t vecIn1, vecIn2;
432
+ uint16_t const * pDataSrcVec = (uint16_t const *) pDataSrc;
433
+
434
+ /*
435
+ * 4x4 Matrix transposition
436
+ *
437
+ * | 0 1 2 3 | | 0 4 8 12 | 8 x 16 flattened version
438
+ * | 4 5 6 7 | => | 1 5 9 13 | => [0 4 8 12 1 5 9 13]
439
+ * | 8 9 10 11 | | 2 6 10 14 | [2 6 10 14 3 7 11 15]
440
+ * | 12 13 14 15 | | 3 7 11 15 |
441
+ */
442
+
443
+ vecOffs1 = vldrhq_u16((uint16_t const *) stridesTr44_1);
444
+ vecOffs2 = vldrhq_u16((uint16_t const *) stridesTr44_2);
445
+ vecIn1 = vldrhq_u16(pDataSrcVec);
446
+ pDataSrcVec += 8;
447
+ vecIn2 = vldrhq_u16(pDataSrcVec);
448
+
449
+ vstrhq_scatter_shifted_offset_u16(pDataDest, vecOffs1, vecIn1);
450
+ vstrhq_scatter_shifted_offset_u16(pDataDest, vecOffs2, vecIn2);
451
+
452
+
453
+ return (ARM_MATH_SUCCESS);
454
+ }
455
+
456
+
457
+
458
+ __STATIC_INLINE arm_status arm_mat_trans_16bit_generic(
459
+ uint16_t srcRows,
460
+ uint16_t srcCols,
461
+ uint16_t * pDataSrc,
462
+ uint16_t * pDataDest)
463
+ {
464
+ uint16x8_t vecOffs;
465
+ uint32_t i;
466
+ uint32_t blkCnt;
467
+ uint16_t const *pDataC;
468
+ uint16_t *pDataDestR;
469
+ uint16x8_t vecIn;
470
+
471
+ vecOffs = vidupq_u16((uint32_t)0, 1);
472
+ vecOffs = vecOffs * srcCols;
473
+
474
+ i = srcCols;
475
+ while(i > 0U)
476
+ {
477
+ pDataC = (uint16_t const *) pDataSrc;
478
+ pDataDestR = pDataDest;
479
+
480
+ blkCnt = srcRows >> 3;
481
+ while (blkCnt > 0U)
482
+ {
483
+ vecIn = vldrhq_gather_shifted_offset_u16(pDataC, vecOffs);
484
+ vstrhq_u16(pDataDestR, vecIn);
485
+ pDataDestR += 8;
486
+ pDataC = pDataC + srcCols * 8;
487
+ /*
488
+ * Decrement the blockSize loop counter
489
+ */
490
+ blkCnt--;
491
+ }
492
+
493
+ /*
494
+ * tail
495
+ */
496
+ blkCnt = srcRows & 7;
497
+ if (blkCnt > 0U)
498
+ {
499
+ mve_pred16_t p0 = vctp16q(blkCnt);
500
+ vecIn = vldrhq_gather_shifted_offset_u16(pDataC, vecOffs);
501
+ vstrhq_p_u16(pDataDestR, vecIn, p0);
502
+ }
503
+ pDataSrc += 1;
504
+ pDataDest += srcRows;
505
+ i--;
506
+ }
507
+
508
+ return (ARM_MATH_SUCCESS);
509
+ }
510
+
511
+
512
+ __STATIC_INLINE arm_status arm_mat_cmplx_trans_16bit(
513
+ uint16_t srcRows,
514
+ uint16_t srcCols,
515
+ uint16_t *pDataSrc,
516
+ uint16_t dstRows,
517
+ uint16_t dstCols,
518
+ uint16_t *pDataDest)
519
+ {
520
+ static const uint16_t loadCmplxCol[8] = { 0, 0, 1, 1, 2, 2, 3, 3 };
521
+ int i;
522
+ uint16x8_t vecOffsRef, vecOffsCur;
523
+ uint16_t const *pDataC;
524
+ uint16_t *pDataRow;
525
+ uint16_t *pDataDestR, *pDataDestRow;
526
+ uint32_t blkCnt;
527
+ uint16x8_t vecIn;
528
+
529
+ #ifdef ARM_MATH_MATRIX_CHECK
530
+ /*
531
+ * Check for matrix mismatch condition
532
+ */
533
+ if ((srcRows != dstCols) || (srcCols != dstRows))
534
+ {
535
+ /*
536
+ * Set status as ARM_MATH_SIZE_MISMATCH
537
+ */
538
+ return ARM_MATH_SIZE_MISMATCH;
539
+ }
540
+ #else
541
+ (void)dstRows;
542
+ (void)dstCols;
543
+ #endif
544
+
545
+ /*
546
+ * 2x2, 3x3 and 4x4 specialization to be added
547
+ */
548
+
549
+
550
+ /*
551
+ * build [0, 1, 2xcol, 2xcol+1, 4xcol, 4xcol+1, 6xcol, 6xcol+1]
552
+ */
553
+ vecOffsRef = vldrhq_u16((uint16_t const *) loadCmplxCol);
554
+ vecOffsRef = vmulq(vecOffsRef, (uint16_t) (srcCols * CMPLX_DIM))
555
+ + viwdupq_u16((uint32_t)0, (uint16_t) 2, 1);
556
+
557
+ pDataRow = pDataSrc;
558
+ pDataDestRow = pDataDest;
559
+ i = srcCols;
560
+ do
561
+ {
562
+ pDataC = (uint16_t const *) pDataRow;
563
+ pDataDestR = pDataDestRow;
564
+ vecOffsCur = vecOffsRef;
565
+
566
+ blkCnt = (srcRows * CMPLX_DIM) >> 3;
567
+ while (blkCnt > 0U)
568
+ {
569
+ vecIn = vldrhq_gather_shifted_offset(pDataC, vecOffsCur);
570
+ vstrhq(pDataDestR, vecIn);
571
+ pDataDestR+= 8; // VEC_LANES_U16
572
+ vecOffsCur = vaddq(vecOffsCur, (srcCols << 3));
573
+ /*
574
+ * Decrement the blockSize loop counter
575
+ */
576
+ blkCnt--;
577
+ }
578
+ /*
579
+ * tail
580
+ * (will be merged thru tail predication)
581
+ */
582
+ blkCnt = (srcRows * CMPLX_DIM) & 0x7;
583
+ if (blkCnt > 0U)
584
+ {
585
+ mve_pred16_t p0 = vctp16q(blkCnt);
586
+ vecIn = vldrhq_gather_shifted_offset(pDataC, vecOffsCur);
587
+ vstrhq_p(pDataDestR, vecIn, p0);
588
+ }
589
+
590
+ pDataRow += CMPLX_DIM;
591
+ pDataDestRow += (srcRows * CMPLX_DIM);
592
+ }
593
+ while (--i);
594
+
595
+ return (ARM_MATH_SUCCESS);
596
+ }
597
+ #endif /* MVEF and MVEI */
598
+
599
+ /***************************************
600
+
601
+ Definitions available for MVEI only
602
+
603
+ ***************************************/
604
+ #if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI)) && !defined(ARM_MATH_AUTOVECTORIZE)
605
+
606
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h"
607
+
608
+ #define MVE_ASRL_SAT16(acc, shift) ((sqrshrl_sat48(acc, -(32-shift)) >> 32) & 0xffffffff)
609
+ #define MVE_ASRL_SAT32(acc, shift) ((sqrshrl(acc, -(32-shift)) >> 32) & 0xffffffff)
610
+
611
+
612
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE)
613
+ __STATIC_INLINE q31x4_t FAST_VSQRT_Q31(q31x4_t vecIn)
614
+ {
615
+ q63x2_t vecTmpLL;
616
+ q31x4_t vecTmp0, vecTmp1;
617
+ q31_t scale;
618
+ q63_t tmp64;
619
+ q31x4_t vecNrm, vecDst, vecIdx, vecSignBits;
620
+
621
+
622
+ vecSignBits = vclsq(vecIn);
623
+ vecSignBits = vbicq_n_s32(vecSignBits, 1);
624
+ /*
625
+ * in = in << no_of_sign_bits;
626
+ */
627
+ vecNrm = vshlq(vecIn, vecSignBits);
628
+ /*
629
+ * index = in >> 24;
630
+ */
631
+ vecIdx = vecNrm >> 24;
632
+ vecIdx = vecIdx << 1;
633
+
634
+ vecTmp0 = vldrwq_gather_shifted_offset_s32(sqrtTable_Q31, (uint32x4_t)vecIdx);
635
+
636
+ vecIdx = vecIdx + 1;
637
+
638
+ vecTmp1 = vldrwq_gather_shifted_offset_s32(sqrtTable_Q31, (uint32x4_t)vecIdx);
639
+
640
+ vecTmp1 = vqrdmulhq(vecTmp1, vecNrm);
641
+ vecTmp0 = vecTmp0 - vecTmp1;
642
+ vecTmp1 = vqrdmulhq(vecTmp0, vecTmp0);
643
+ vecTmp1 = vqrdmulhq(vecNrm, vecTmp1);
644
+ vecTmp1 = vdupq_n_s32(0x18000000) - vecTmp1;
645
+ vecTmp0 = vqrdmulhq(vecTmp0, vecTmp1);
646
+ vecTmpLL = vmullbq_int(vecNrm, vecTmp0);
647
+
648
+ /*
649
+ * scale elements 0, 2
650
+ */
651
+ scale = 26 + (vecSignBits[0] >> 1);
652
+ tmp64 = asrl(vecTmpLL[0], scale);
653
+ vecDst[0] = (q31_t) tmp64;
654
+
655
+ scale = 26 + (vecSignBits[2] >> 1);
656
+ tmp64 = asrl(vecTmpLL[1], scale);
657
+ vecDst[2] = (q31_t) tmp64;
658
+
659
+ vecTmpLL = vmulltq_int(vecNrm, vecTmp0);
660
+
661
+ /*
662
+ * scale elements 1, 3
663
+ */
664
+ scale = 26 + (vecSignBits[1] >> 1);
665
+ tmp64 = asrl(vecTmpLL[0], scale);
666
+ vecDst[1] = (q31_t) tmp64;
667
+
668
+ scale = 26 + (vecSignBits[3] >> 1);
669
+ tmp64 = asrl(vecTmpLL[1], scale);
670
+ vecDst[3] = (q31_t) tmp64;
671
+ /*
672
+ * set negative values to 0
673
+ */
674
+ vecDst = vdupq_m(vecDst, 0, vcmpltq_n_s32(vecIn, 0));
675
+
676
+ return vecDst;
677
+ }
678
+ #endif
679
+
680
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE)
681
+ __STATIC_INLINE q15x8_t FAST_VSQRT_Q15(q15x8_t vecIn)
682
+ {
683
+ q31x4_t vecTmpLev, vecTmpLodd, vecSignL;
684
+ q15x8_t vecTmp0, vecTmp1;
685
+ q15x8_t vecNrm, vecDst, vecIdx, vecSignBits;
686
+
687
+ vecDst = vuninitializedq_s16();
688
+
689
+ vecSignBits = vclsq(vecIn);
690
+ vecSignBits = vbicq_n_s16(vecSignBits, 1);
691
+ /*
692
+ * in = in << no_of_sign_bits;
693
+ */
694
+ vecNrm = vshlq(vecIn, vecSignBits);
695
+
696
+ vecIdx = vecNrm >> 8;
697
+ vecIdx = vecIdx << 1;
698
+
699
+ vecTmp0 = vldrhq_gather_shifted_offset_s16(sqrtTable_Q15, (uint16x8_t)vecIdx);
700
+
701
+ vecIdx = vecIdx + 1;
702
+
703
+ vecTmp1 = vldrhq_gather_shifted_offset_s16(sqrtTable_Q15, (uint16x8_t)vecIdx);
704
+
705
+ vecTmp1 = vqrdmulhq(vecTmp1, vecNrm);
706
+ vecTmp0 = vecTmp0 - vecTmp1;
707
+ vecTmp1 = vqrdmulhq(vecTmp0, vecTmp0);
708
+ vecTmp1 = vqrdmulhq(vecNrm, vecTmp1);
709
+ vecTmp1 = vdupq_n_s16(0x1800) - vecTmp1;
710
+ vecTmp0 = vqrdmulhq(vecTmp0, vecTmp1);
711
+
712
+ vecSignBits = vecSignBits >> 1;
713
+
714
+ vecTmpLev = vmullbq_int(vecNrm, vecTmp0);
715
+ vecTmpLodd = vmulltq_int(vecNrm, vecTmp0);
716
+
717
+ vecTmp0 = vecSignBits + 10;
718
+ /*
719
+ * negate sign to apply register based vshl
720
+ */
721
+ vecTmp0 = -vecTmp0;
722
+
723
+ /*
724
+ * shift even elements
725
+ */
726
+ vecSignL = vmovlbq(vecTmp0);
727
+ vecTmpLev = vshlq(vecTmpLev, vecSignL);
728
+ /*
729
+ * shift odd elements
730
+ */
731
+ vecSignL = vmovltq(vecTmp0);
732
+ vecTmpLodd = vshlq(vecTmpLodd, vecSignL);
733
+ /*
734
+ * merge and narrow odd and even parts
735
+ */
736
+ vecDst = vmovnbq_s32(vecDst, vecTmpLev);
737
+ vecDst = vmovntq_s32(vecDst, vecTmpLodd);
738
+ /*
739
+ * set negative values to 0
740
+ */
741
+ vecDst = vdupq_m(vecDst, 0, vcmpltq_n_s16(vecIn, 0));
742
+
743
+ return vecDst;
744
+ }
745
+ #endif
746
+
747
+ #endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI) */
748
+
749
+ #ifdef __cplusplus
750
+ }
751
+ #endif
752
+
753
+ #endif
edge-impulse-sdk/CMSIS/DSP/Include/arm_math.h ADDED
@@ -0,0 +1,225 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ /******************************************************************************
2
+ * @file arm_math.h
3
+ * @brief Public header file for CMSIS DSP Library
4
+ * @version V1.10.0
5
+ * @date 08 July 2021
6
+ * Target Processor: Cortex-M and Cortex-A cores
7
+ ******************************************************************************/
8
+ /*
9
+ * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
10
+ *
11
+ * SPDX-License-Identifier: Apache-2.0
12
+ *
13
+ * Licensed under the Apache License, Version 2.0 (the License); you may
14
+ * not use this file except in compliance with the License.
15
+ * You may obtain a copy of the License at
16
+ *
17
+ * www.apache.org/licenses/LICENSE-2.0
18
+ *
19
+ * Unless required by applicable law or agreed to in writing, software
20
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
21
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22
+ * See the License for the specific language governing permissions and
23
+ * limitations under the License.
24
+ */
25
+
26
+ /**
27
+ \mainpage CMSIS DSP Software Library
28
+ *
29
+ * \section intro Introduction
30
+ *
31
+ * This user manual describes the CMSIS DSP software library,
32
+ * a suite of common signal processing functions for use on Cortex-M and Cortex-A processor
33
+ * based devices.
34
+ *
35
+ * The library is divided into a number of functions each covering a specific category:
36
+ * - \ref groupMath "Basic math functions"
37
+ * - \ref groupFastMath "Fast math functions"
38
+ * - \ref groupCmplxMath "Complex math functions"
39
+ * - \ref groupFilters "Filtering functions"
40
+ * - \ref groupMatrix "Matrix functions"
41
+ * - \ref groupTransforms "Transform functions"
42
+ * - \ref groupController "Motor control functions"
43
+ * - \ref groupStats "Statistical functions"
44
+ * - \ref groupSupport "Support functions"
45
+ * - \ref groupInterpolation "Interpolation functions"
46
+ * - \ref groupSVM "Support Vector Machine functions (SVM)"
47
+ * - \ref groupBayes "Bayes classifier functions"
48
+ * - \ref groupDistance "Distance functions"
49
+ * - \ref groupQuaternionMath "Quaternion functions"
50
+ *
51
+ * The library has generally separate functions for operating on 8-bit integers, 16-bit integers,
52
+ * 32-bit integer and 32-bit floating-point values.
53
+ *
54
+ * The library is providing vectorized versions of most algorthms for Helium
55
+ * and of most f32 algorithms for Neon.
56
+ *
57
+ * When using a vectorized version, provide a little bit of padding after the end of
58
+ * a buffer (3 words) because the vectorized code may read a little bit after the end
59
+ * of a buffer. You don't have to modify your buffers but just ensure that the
60
+ * end of buffer + padding is not outside of a memory region.
61
+ *
62
+ * \section using Using the Library
63
+ *
64
+ * The library is released in source form. It is strongly advised to compile the library using -Ofast to
65
+ * have the best performances.
66
+ *
67
+ * The library functions are declared in the public file `arm_math.h` which is placed in the `Include` folder.
68
+ * Simply include this file. If you don't want to include everything, you can also rely
69
+ * on headers in `Include/dsp` folder and use only what you need.
70
+ *
71
+ * \section example Examples
72
+ *
73
+ * The library ships with a number of examples which demonstrate how to use the library functions. Please refer to \ref groupExamples.
74
+ *
75
+ * \section toolchain Toolchain Support
76
+ *
77
+ * The library is now tested on Fast Models building with cmake.
78
+ * Core M0, M4, M7, M33, M55, A32 are tested.
79
+ *
80
+ *
81
+ * \section preprocessor Preprocessor Macros
82
+ *
83
+ * Each library project has different preprocessor macros.
84
+ *
85
+ * - `ARM_MATH_BIG_ENDIAN`:
86
+ * - Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
87
+ * .
88
+ * - `ARM_MATH_MATRIX_CHECK`:
89
+ * - Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
90
+ * .
91
+ * - `ARM_MATH_ROUNDING`:
92
+ * - Define macro ARM_MATH_ROUNDING for rounding on support functions
93
+ * .
94
+ * - `ARM_MATH_LOOPUNROLL`:
95
+ * - Define macro ARM_MATH_LOOPUNROLL to enable manual loop unrolling in DSP functions
96
+ * .
97
+ * - `ARM_MATH_NEON`:
98
+ * - Define macro ARM_MATH_NEON to enable Neon versions of the DSP functions.
99
+ * It is not enabled by default when Neon is available because performances are
100
+ * dependent on the compiler and target architecture.
101
+ * .
102
+ * - `ARM_MATH_NEON_EXPERIMENTAL`:
103
+ * - Define macro ARM_MATH_NEON_EXPERIMENTAL to enable experimental Neon versions of
104
+ * of some DSP functions. Experimental Neon versions currently do not have better
105
+ * performances than the scalar versions.
106
+ * .
107
+ * - `ARM_MATH_HELIUM`:
108
+ * - It implies the flags ARM_MATH_MVEF and ARM_MATH_MVEI and ARM_MATH_MVE_FLOAT16.
109
+ * .
110
+ * - `ARM_MATH_HELIUM_EXPERIMENTAL`:
111
+ * - Only taken into account when ARM_MATH_MVEF, ARM_MATH_MVEI or ARM_MATH_MVE_FLOAT16 are defined.
112
+ * Enable some vector versions which may have worse performance than scalar
113
+ * depending on the core / compiler configuration.
114
+ * .
115
+ * - `ARM_MATH_MVEF`:
116
+ * - Select Helium versions of the f32 algorithms.
117
+ * It implies ARM_MATH_FLOAT16 and ARM_MATH_MVEI.
118
+ * .
119
+ * - `ARM_MATH_MVEI`:
120
+ * - Select Helium versions of the int and fixed point algorithms.
121
+ * .
122
+ * - `ARM_MATH_MVE_FLOAT16`:
123
+ * - MVE Float16 implementations of some algorithms (Requires MVE extension).
124
+ * .
125
+ * - `DISABLEFLOAT16`:
126
+ * - Disable float16 algorithms when __fp16 is not supported for a
127
+ * specific compiler / core configuration.
128
+ * This is only valid for scalar. When vector architecture is
129
+ * supporting f16 then it can't be disabled.
130
+ * .
131
+ * - `ARM_MATH_AUTOVECTORIZE`:
132
+ * - With Helium or Neon, disable the use of vectorized code with C intrinsics
133
+ * and use pure C instead. The vectorization is then done by the compiler.
134
+ *
135
+ * \section pack CMSIS-DSP in ARM::CMSIS Pack
136
+ *
137
+ * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
138
+ * |File/Folder |Content |
139
+ * |---------------------------------|------------------------------------------------------------------------|
140
+ * |\b CMSIS\\Documentation\\DSP | This documentation |
141
+ * |\b CMSIS\\DSP\\Examples | Example projects demonstrating the usage of the library functions |
142
+ * |\b CMSIS\\DSP\\ComputeLibrary | Small Neon kernels when building on Cortex-A
143
+ * |\b CMSIS\\DSP\\Include | include files for using and building the lib
144
+ * |\b CMSIS\\DSP\\PrivateInclude | private include files for building the lib |
145
+ * |\b CMSIS\\DSP\\Source | source files |
146
+ *
147
+ * \section rev Revision History of CMSIS-DSP
148
+ * Please refer to \ref ChangeLog_pg.
149
+ *
150
+ * \section license License
151
+ *
152
+ * The CMSIS-DSP is provided free of charge under the <a href="LICENSE.txt">Apache 2.0 License</a>.
153
+ */
154
+
155
+
156
+
157
+
158
+
159
+
160
+
161
+
162
+
163
+
164
+
165
+ /**
166
+ * @defgroup groupExamples Examples
167
+ */
168
+
169
+
170
+
171
+
172
+
173
+ #ifndef _ARM_MATH_H
174
+ #define _ARM_MATH_H
175
+
176
+
177
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h"
178
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_memory.h"
179
+
180
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h"
181
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h"
182
+
183
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h"
184
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/interpolation_functions.h"
185
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/bayes_functions.h"
186
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h"
187
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions.h"
188
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h"
189
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/controller_functions.h"
190
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions.h"
191
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions.h"
192
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/svm_functions.h"
193
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions.h"
194
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h"
195
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h"
196
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/quaternion_math_functions.h"
197
+
198
+
199
+
200
+ #ifdef __cplusplus
201
+ extern "C"
202
+ {
203
+ #endif
204
+
205
+
206
+
207
+
208
+ //#define TABLE_SPACING_Q31 0x400000
209
+ //#define TABLE_SPACING_Q15 0x80
210
+
211
+
212
+
213
+
214
+
215
+ #ifdef __cplusplus
216
+ }
217
+ #endif
218
+
219
+
220
+ #endif /* _ARM_MATH_H */
221
+
222
+ /**
223
+ *
224
+ * End of file.
225
+ */
edge-impulse-sdk/CMSIS/DSP/Include/arm_math_f16.h ADDED
@@ -0,0 +1,59 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ /******************************************************************************
2
+ * @file arm_math_f16.h
3
+ * @brief Public header file for f16 function of the CMSIS DSP Library
4
+ * @version V1.10.0
5
+ * @date 08 July 2021
6
+ * Target Processor: Cortex-M and Cortex-A cores
7
+ ******************************************************************************/
8
+ /*
9
+ * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
10
+ *
11
+ * SPDX-License-Identifier: Apache-2.0
12
+ *
13
+ * Licensed under the Apache License, Version 2.0 (the License); you may
14
+ * not use this file except in compliance with the License.
15
+ * You may obtain a copy of the License at
16
+ *
17
+ * www.apache.org/licenses/LICENSE-2.0
18
+ *
19
+ * Unless required by applicable law or agreed to in writing, software
20
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
21
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22
+ * See the License for the specific language governing permissions and
23
+ * limitations under the License.
24
+ */
25
+
26
+ #ifndef _ARM_MATH_F16_H
27
+ #define _ARM_MATH_F16_H
28
+
29
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math.h"
30
+
31
+ #ifdef __cplusplus
32
+ extern "C"
33
+ {
34
+ #endif
35
+
36
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types_f16.h"
37
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h"
38
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h"
39
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions_f16.h"
40
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/interpolation_functions_f16.h"
41
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/bayes_functions_f16.h"
42
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions_f16.h"
43
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions_f16.h"
44
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions_f16.h"
45
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/controller_functions_f16.h"
46
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions_f16.h"
47
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions_f16.h"
48
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/svm_functions_f16.h"
49
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions_f16.h"
50
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions_f16.h"
51
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions_f16.h"
52
+
53
+ #ifdef __cplusplus
54
+ }
55
+ #endif
56
+
57
+ #endif /* _ARM_MATH_F16_H */
58
+
59
+
edge-impulse-sdk/CMSIS/DSP/Include/arm_math_memory.h ADDED
@@ -0,0 +1,206 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ /******************************************************************************
2
+ * @file arm_math_memory.h
3
+ * @brief Public header file for CMSIS DSP Library
4
+ * @version V1.10.0
5
+ * @date 08 July 2021
6
+ * Target Processor: Cortex-M and Cortex-A cores
7
+ ******************************************************************************/
8
+ /*
9
+ * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
10
+ *
11
+ * SPDX-License-Identifier: Apache-2.0
12
+ *
13
+ * Licensed under the Apache License, Version 2.0 (the License); you may
14
+ * not use this file except in compliance with the License.
15
+ * You may obtain a copy of the License at
16
+ *
17
+ * www.apache.org/licenses/LICENSE-2.0
18
+ *
19
+ * Unless required by applicable law or agreed to in writing, software
20
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
21
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22
+ * See the License for the specific language governing permissions and
23
+ * limitations under the License.
24
+ */
25
+
26
+ #ifndef _ARM_MATH_MEMORY_H_
27
+
28
+ #define _ARM_MATH_MEMORY_H_
29
+
30
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h"
31
+
32
+
33
+ #ifdef __cplusplus
34
+ extern "C"
35
+ {
36
+ #endif
37
+
38
+ /**
39
+ @brief definition to read/write two 16 bit values.
40
+ @deprecated
41
+ */
42
+ #if defined ( __CC_ARM )
43
+ #define __SIMD32_TYPE int32_t __packed
44
+ #elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
45
+ #define __SIMD32_TYPE int32_t
46
+ #elif defined ( __GNUC__ )
47
+ #define __SIMD32_TYPE int32_t
48
+ #elif defined ( __ICCARM__ )
49
+ #define __SIMD32_TYPE int32_t __packed
50
+ #elif defined ( __TI_ARM__ )
51
+ #define __SIMD32_TYPE int32_t
52
+ #elif defined ( __CSMC__ )
53
+ #define __SIMD32_TYPE int32_t
54
+ #elif defined ( __TASKING__ )
55
+ #define __SIMD32_TYPE __un(aligned) int32_t
56
+ #elif defined(_MSC_VER )
57
+ #define __SIMD32_TYPE int32_t
58
+ #else
59
+ #error Unknown compiler
60
+ #endif
61
+
62
+ #define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
63
+ #define __SIMD32_CONST(addr) ( (__SIMD32_TYPE * ) (addr))
64
+ #define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE * ) (addr))
65
+ #define __SIMD64(addr) (*( int64_t **) & (addr))
66
+
67
+
68
+ /* SIMD replacement */
69
+
70
+
71
+ /**
72
+ @brief Read 2 Q15 from Q15 pointer.
73
+ @param[in] pQ15 points to input value
74
+ @return Q31 value
75
+ */
76
+ __STATIC_FORCEINLINE q31_t read_q15x2 (
77
+ q15_t const * pQ15)
78
+ {
79
+ q31_t val;
80
+
81
+ #ifdef __ARM_FEATURE_UNALIGNED
82
+ memcpy (&val, pQ15, 4);
83
+ #else
84
+ val = (pQ15[1] << 16) | (pQ15[0] & 0x0FFFF) ;
85
+ #endif
86
+
87
+ return (val);
88
+ }
89
+
90
+ /**
91
+ @brief Read 2 Q15 from Q15 pointer and increment pointer afterwards.
92
+ @param[in] pQ15 points to input value
93
+ @return Q31 value
94
+ */
95
+ #define read_q15x2_ia(pQ15) read_q15x2((*(pQ15) += 2) - 2)
96
+
97
+ /**
98
+ @brief Read 2 Q15 from Q15 pointer and decrement pointer afterwards.
99
+ @param[in] pQ15 points to input value
100
+ @return Q31 value
101
+ */
102
+ #define read_q15x2_da(pQ15) read_q15x2((*(pQ15) -= 2) + 2)
103
+
104
+ /**
105
+ @brief Write 2 Q15 to Q15 pointer and increment pointer afterwards.
106
+ @param[in] pQ15 points to input value
107
+ @param[in] value Q31 value
108
+ @return none
109
+ */
110
+ __STATIC_FORCEINLINE void write_q15x2_ia (
111
+ q15_t ** pQ15,
112
+ q31_t value)
113
+ {
114
+ q31_t val = value;
115
+ #ifdef __ARM_FEATURE_UNALIGNED
116
+ memcpy (*pQ15, &val, 4);
117
+ #else
118
+ (*pQ15)[0] = (q15_t)(val & 0x0FFFF);
119
+ (*pQ15)[1] = (q15_t)((val >> 16) & 0x0FFFF);
120
+ #endif
121
+
122
+ *pQ15 += 2;
123
+ }
124
+
125
+ /**
126
+ @brief Write 2 Q15 to Q15 pointer.
127
+ @param[in] pQ15 points to input value
128
+ @param[in] value Q31 value
129
+ @return none
130
+ */
131
+ __STATIC_FORCEINLINE void write_q15x2 (
132
+ q15_t * pQ15,
133
+ q31_t value)
134
+ {
135
+ q31_t val = value;
136
+
137
+ #ifdef __ARM_FEATURE_UNALIGNED
138
+ memcpy (pQ15, &val, 4);
139
+ #else
140
+ pQ15[0] = (q15_t)(val & 0x0FFFF);
141
+ pQ15[1] = (q15_t)(val >> 16);
142
+ #endif
143
+ }
144
+
145
+
146
+ /**
147
+ @brief Read 4 Q7 from Q7 pointer
148
+ @param[in] pQ7 points to input value
149
+ @return Q31 value
150
+ */
151
+ __STATIC_FORCEINLINE q31_t read_q7x4 (
152
+ q7_t const * pQ7)
153
+ {
154
+ q31_t val;
155
+
156
+ #ifdef __ARM_FEATURE_UNALIGNED
157
+ memcpy (&val, pQ7, 4);
158
+ #else
159
+ val =((pQ7[3] & 0x0FF) << 24) | ((pQ7[2] & 0x0FF) << 16) | ((pQ7[1] & 0x0FF) << 8) | (pQ7[0] & 0x0FF);
160
+ #endif
161
+ return (val);
162
+ }
163
+
164
+ /**
165
+ @brief Read 4 Q7 from Q7 pointer and increment pointer afterwards.
166
+ @param[in] pQ7 points to input value
167
+ @return Q31 value
168
+ */
169
+ #define read_q7x4_ia(pQ7) read_q7x4((*(pQ7) += 4) - 4)
170
+
171
+ /**
172
+ @brief Read 4 Q7 from Q7 pointer and decrement pointer afterwards.
173
+ @param[in] pQ7 points to input value
174
+ @return Q31 value
175
+ */
176
+ #define read_q7x4_da(pQ7) read_q7x4((*(pQ7) -= 4) + 4)
177
+
178
+ /**
179
+ @brief Write 4 Q7 to Q7 pointer and increment pointer afterwards.
180
+ @param[in] pQ7 points to input value
181
+ @param[in] value Q31 value
182
+ @return none
183
+ */
184
+ __STATIC_FORCEINLINE void write_q7x4_ia (
185
+ q7_t ** pQ7,
186
+ q31_t value)
187
+ {
188
+ q31_t val = value;
189
+ #ifdef __ARM_FEATURE_UNALIGNED
190
+ memcpy (*pQ7, &val, 4);
191
+ #else
192
+ (*pQ7)[0] = (q7_t)(val & 0x0FF);
193
+ (*pQ7)[1] = (q7_t)((val >> 8) & 0x0FF);
194
+ (*pQ7)[2] = (q7_t)((val >> 16) & 0x0FF);
195
+ (*pQ7)[3] = (q7_t)((val >> 24) & 0x0FF);
196
+
197
+ #endif
198
+ *pQ7 += 4;
199
+ }
200
+
201
+
202
+ #ifdef __cplusplus
203
+ }
204
+ #endif
205
+
206
+ #endif /*ifndef _ARM_MATH_MEMORY_H_ */
edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h ADDED
@@ -0,0 +1,616 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ /******************************************************************************
2
+ * @file arm_math_types.h
3
+ * @brief Public header file for CMSIS DSP Library
4
+ * @version V1.10.0
5
+ * @date 08 July 2021
6
+ * Target Processor: Cortex-M and Cortex-A cores
7
+ ******************************************************************************/
8
+ /*
9
+ * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
10
+ *
11
+ * SPDX-License-Identifier: Apache-2.0
12
+ *
13
+ * Licensed under the Apache License, Version 2.0 (the License); you may
14
+ * not use this file except in compliance with the License.
15
+ * You may obtain a copy of the License at
16
+ *
17
+ * www.apache.org/licenses/LICENSE-2.0
18
+ *
19
+ * Unless required by applicable law or agreed to in writing, software
20
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
21
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22
+ * See the License for the specific language governing permissions and
23
+ * limitations under the License.
24
+ */
25
+
26
+ #ifndef _ARM_MATH_TYPES_H_
27
+
28
+ #define _ARM_MATH_TYPES_H_
29
+
30
+ #ifdef __cplusplus
31
+ extern "C"
32
+ {
33
+ #endif
34
+
35
+ /* Compiler specific diagnostic adjustment */
36
+ #if defined ( __CC_ARM )
37
+
38
+ #elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
39
+
40
+ #elif defined ( __APPLE_CC__ )
41
+ #pragma GCC diagnostic ignored "-Wold-style-cast"
42
+
43
+ #elif defined ( __GNUC__ )
44
+ #pragma GCC diagnostic push
45
+ #pragma GCC diagnostic ignored "-Wsign-conversion"
46
+ #pragma GCC diagnostic ignored "-Wconversion"
47
+ #pragma GCC diagnostic ignored "-Wunused-parameter"
48
+
49
+ #elif defined ( __ICCARM__ )
50
+
51
+ #elif defined ( __TI_ARM__ )
52
+
53
+ #elif defined ( __CSMC__ )
54
+
55
+ #elif defined ( __TASKING__ )
56
+
57
+ #elif defined ( _MSC_VER )
58
+
59
+ #else
60
+ #error Unknown compiler
61
+ #endif
62
+
63
+
64
+ /* Included for instrinsics definitions */
65
+ #if defined (_MSC_VER )
66
+ #include <stdint.h>
67
+ #define __STATIC_FORCEINLINE static __forceinline
68
+ #define __STATIC_INLINE static __inline
69
+ #define __ALIGNED(x) __declspec(align(x))
70
+ #elif defined ( __APPLE_CC__ )
71
+ #include <stdint.h>
72
+ #define __ALIGNED(x) __attribute__((aligned(x)))
73
+ #define __STATIC_FORCEINLINE static inline __attribute__((always_inline))
74
+ #define __STATIC_INLINE static inline
75
+ #elif defined (__GNUC_PYTHON__)
76
+ #include <stdint.h>
77
+ #define __ALIGNED(x) __attribute__((aligned(x)))
78
+ #define __STATIC_FORCEINLINE static inline __attribute__((always_inline))
79
+ #define __STATIC_INLINE static inline
80
+
81
+ #else
82
+ #include "edge-impulse-sdk/CMSIS/Core/Include/cmsis_compiler.h"
83
+ #endif
84
+
85
+
86
+
87
+ #include <string.h>
88
+ #include <math.h>
89
+ #include <float.h>
90
+ #include <limits.h>
91
+
92
+ /* evaluate ARM DSP feature */
93
+ #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
94
+ #define ARM_MATH_DSP 1
95
+ #endif
96
+
97
+ #if defined(ARM_MATH_NEON)
98
+ #if defined(_MSC_VER) && defined(_M_ARM64EC)
99
+ #include <arm64_neon.h>
100
+ #else
101
+ #include <arm_neon.h>
102
+ #endif
103
+ #if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && __ARM_FEATURE_FP16_VECTOR_ARITHMETIC
104
+ #if !defined(ARM_MATH_NEON_FLOAT16)
105
+ #define ARM_MATH_NEON_FLOAT16
106
+ #endif
107
+ #endif
108
+ #endif
109
+
110
+ #if !defined(ARM_MATH_AUTOVECTORIZE)
111
+
112
+
113
+ #if defined(__ARM_FEATURE_MVE)
114
+ #if __ARM_FEATURE_MVE
115
+ #if !defined(ARM_MATH_MVEI)
116
+ #define ARM_MATH_MVEI
117
+ #endif
118
+ #endif
119
+
120
+ #if (__ARM_FEATURE_MVE & 2)
121
+ #if !defined(ARM_MATH_MVEF)
122
+ #define ARM_MATH_MVEF
123
+ #endif
124
+ #if !defined(ARM_MATH_MVE_FLOAT16)
125
+ #define ARM_MATH_MVE_FLOAT16
126
+ #endif
127
+ #endif
128
+
129
+ #endif /*defined(__ARM_FEATURE_MVE)*/
130
+ #endif /*!defined(ARM_MATH_AUTOVECTORIZE)*/
131
+
132
+
133
+ #if defined (ARM_MATH_HELIUM)
134
+ #if !defined(ARM_MATH_MVEF)
135
+ #define ARM_MATH_MVEF
136
+ #endif
137
+
138
+ #if !defined(ARM_MATH_MVEI)
139
+ #define ARM_MATH_MVEI
140
+ #endif
141
+
142
+ #if !defined(ARM_MATH_MVE_FLOAT16)
143
+ #define ARM_MATH_MVE_FLOAT16
144
+ #endif
145
+ #endif
146
+
147
+
148
+
149
+ #if defined ( __CC_ARM )
150
+ /* Enter low optimization region - place directly above function definition */
151
+ #if defined( __ARM_ARCH_7EM__ )
152
+ #define LOW_OPTIMIZATION_ENTER \
153
+ _Pragma ("push") \
154
+ _Pragma ("O1")
155
+ #else
156
+ #define LOW_OPTIMIZATION_ENTER
157
+ #endif
158
+
159
+ /* Exit low optimization region - place directly after end of function definition */
160
+ #if defined ( __ARM_ARCH_7EM__ )
161
+ #define LOW_OPTIMIZATION_EXIT \
162
+ _Pragma ("pop")
163
+ #else
164
+ #define LOW_OPTIMIZATION_EXIT
165
+ #endif
166
+
167
+ /* Enter low optimization region - place directly above function definition */
168
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
169
+
170
+ /* Exit low optimization region - place directly after end of function definition */
171
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
172
+
173
+ #elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
174
+ #define LOW_OPTIMIZATION_ENTER
175
+ #define LOW_OPTIMIZATION_EXIT
176
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
177
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
178
+
179
+ #elif defined ( __APPLE_CC__ )
180
+ #define LOW_OPTIMIZATION_ENTER
181
+ #define LOW_OPTIMIZATION_EXIT
182
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
183
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
184
+
185
+ #elif defined ( __GNUC__ )
186
+ #define LOW_OPTIMIZATION_ENTER \
187
+ __attribute__(( optimize("-O1") ))
188
+ #define LOW_OPTIMIZATION_EXIT
189
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
190
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
191
+
192
+ #elif defined ( __ICCARM__ )
193
+ /* Enter low optimization region - place directly above function definition */
194
+ #if defined ( __ARM_ARCH_7EM__ )
195
+ #define LOW_OPTIMIZATION_ENTER \
196
+ _Pragma ("optimize=low")
197
+ #else
198
+ #define LOW_OPTIMIZATION_ENTER
199
+ #endif
200
+
201
+ /* Exit low optimization region - place directly after end of function definition */
202
+ #define LOW_OPTIMIZATION_EXIT
203
+
204
+ /* Enter low optimization region - place directly above function definition */
205
+ #if defined ( __ARM_ARCH_7EM__ )
206
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
207
+ _Pragma ("optimize=low")
208
+ #else
209
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
210
+ #endif
211
+
212
+ /* Exit low optimization region - place directly after end of function definition */
213
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
214
+
215
+ #elif defined ( __TI_ARM__ )
216
+ #define LOW_OPTIMIZATION_ENTER
217
+ #define LOW_OPTIMIZATION_EXIT
218
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
219
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
220
+
221
+ #elif defined ( __CSMC__ )
222
+ #define LOW_OPTIMIZATION_ENTER
223
+ #define LOW_OPTIMIZATION_EXIT
224
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
225
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
226
+
227
+ #elif defined ( __TASKING__ )
228
+ #define LOW_OPTIMIZATION_ENTER
229
+ #define LOW_OPTIMIZATION_EXIT
230
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
231
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
232
+
233
+ #elif defined ( _MSC_VER ) || defined(__GNUC_PYTHON__)
234
+ #define LOW_OPTIMIZATION_ENTER
235
+ #define LOW_OPTIMIZATION_EXIT
236
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
237
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
238
+ #endif
239
+
240
+
241
+
242
+ /* Compiler specific diagnostic adjustment */
243
+ #if defined ( __CC_ARM )
244
+
245
+ #elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
246
+
247
+ #elif defined ( __APPLE_CC__ )
248
+
249
+ #elif defined ( __GNUC__ )
250
+ #pragma GCC diagnostic pop
251
+
252
+ #elif defined ( __ICCARM__ )
253
+
254
+ #elif defined ( __TI_ARM__ )
255
+
256
+ #elif defined ( __CSMC__ )
257
+
258
+ #elif defined ( __TASKING__ )
259
+
260
+ #elif defined ( _MSC_VER )
261
+
262
+ #else
263
+ #error Unknown compiler
264
+ #endif
265
+
266
+ #ifdef __cplusplus
267
+ }
268
+ #endif
269
+
270
+ #if defined(__ARM_FEATURE_MVE) && __ARM_FEATURE_MVE
271
+ #include <arm_mve.h>
272
+ #endif
273
+
274
+ #ifdef __cplusplus
275
+ extern "C"
276
+ {
277
+ #endif
278
+
279
+ /**
280
+ * @brief 8-bit fractional data type in 1.7 format.
281
+ */
282
+ typedef int8_t q7_t;
283
+
284
+ /**
285
+ * @brief 16-bit fractional data type in 1.15 format.
286
+ */
287
+ typedef int16_t q15_t;
288
+
289
+ /**
290
+ * @brief 32-bit fractional data type in 1.31 format.
291
+ */
292
+ typedef int32_t q31_t;
293
+
294
+ /**
295
+ * @brief 64-bit fractional data type in 1.63 format.
296
+ */
297
+ typedef int64_t q63_t;
298
+
299
+ /**
300
+ * @brief 32-bit floating-point type definition.
301
+ */
302
+ #if !defined(__ICCARM__) || !(__ARM_FEATURE_MVE & 2)
303
+ typedef float float32_t;
304
+ #endif
305
+
306
+ /**
307
+ * @brief 64-bit floating-point type definition.
308
+ */
309
+ typedef double float64_t;
310
+
311
+ /**
312
+ * @brief vector types
313
+ */
314
+ #if defined(ARM_MATH_NEON) || (defined (ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE))
315
+ /**
316
+ * @brief 64-bit fractional 128-bit vector data type in 1.63 format
317
+ */
318
+ typedef int64x2_t q63x2_t;
319
+
320
+ /**
321
+ * @brief 32-bit fractional 128-bit vector data type in 1.31 format.
322
+ */
323
+ typedef int32x4_t q31x4_t;
324
+
325
+ /**
326
+ * @brief 16-bit fractional 128-bit vector data type with 16-bit alignment in 1.15 format.
327
+ */
328
+ typedef __ALIGNED(2) int16x8_t q15x8_t;
329
+
330
+ /**
331
+ * @brief 8-bit fractional 128-bit vector data type with 8-bit alignment in 1.7 format.
332
+ */
333
+ typedef __ALIGNED(1) int8x16_t q7x16_t;
334
+
335
+ /**
336
+ * @brief 32-bit fractional 128-bit vector pair data type in 1.31 format.
337
+ */
338
+ typedef int32x4x2_t q31x4x2_t;
339
+
340
+ /**
341
+ * @brief 32-bit fractional 128-bit vector quadruplet data type in 1.31 format.
342
+ */
343
+ typedef int32x4x4_t q31x4x4_t;
344
+
345
+ /**
346
+ * @brief 16-bit fractional 128-bit vector pair data type in 1.15 format.
347
+ */
348
+ typedef int16x8x2_t q15x8x2_t;
349
+
350
+ /**
351
+ * @brief 16-bit fractional 128-bit vector quadruplet data type in 1.15 format.
352
+ */
353
+ typedef int16x8x4_t q15x8x4_t;
354
+
355
+ /**
356
+ * @brief 8-bit fractional 128-bit vector pair data type in 1.7 format.
357
+ */
358
+ typedef int8x16x2_t q7x16x2_t;
359
+
360
+ /**
361
+ * @brief 8-bit fractional 128-bit vector quadruplet data type in 1.7 format.
362
+ */
363
+ typedef int8x16x4_t q7x16x4_t;
364
+
365
+ /**
366
+ * @brief 32-bit fractional data type in 9.23 format.
367
+ */
368
+ typedef int32_t q23_t;
369
+
370
+ /**
371
+ * @brief 32-bit fractional 128-bit vector data type in 9.23 format.
372
+ */
373
+ typedef int32x4_t q23x4_t;
374
+
375
+ /**
376
+ * @brief 64-bit status 128-bit vector data type.
377
+ */
378
+ typedef int64x2_t status64x2_t;
379
+
380
+ /**
381
+ * @brief 32-bit status 128-bit vector data type.
382
+ */
383
+ typedef int32x4_t status32x4_t;
384
+
385
+ /**
386
+ * @brief 16-bit status 128-bit vector data type.
387
+ */
388
+ typedef int16x8_t status16x8_t;
389
+
390
+ /**
391
+ * @brief 8-bit status 128-bit vector data type.
392
+ */
393
+ typedef int8x16_t status8x16_t;
394
+
395
+
396
+ #endif
397
+
398
+ #if defined(ARM_MATH_NEON) || (defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)) /* floating point vector*/
399
+ /**
400
+ * @brief 32-bit floating-point 128-bit vector type
401
+ */
402
+ typedef float32x4_t f32x4_t;
403
+
404
+ /**
405
+ * @brief 32-bit floating-point 128-bit vector pair data type
406
+ */
407
+ typedef float32x4x2_t f32x4x2_t;
408
+
409
+ /**
410
+ * @brief 32-bit floating-point 128-bit vector quadruplet data type
411
+ */
412
+ typedef float32x4x4_t f32x4x4_t;
413
+
414
+ /**
415
+ * @brief 32-bit ubiquitous 128-bit vector data type
416
+ */
417
+ typedef union _any32x4_t
418
+ {
419
+ float32x4_t f;
420
+ int32x4_t i;
421
+ } any32x4_t;
422
+
423
+ #endif
424
+
425
+ #if defined(ARM_MATH_NEON)
426
+ /**
427
+ * @brief 32-bit fractional 64-bit vector data type in 1.31 format.
428
+ */
429
+ typedef int32x2_t q31x2_t;
430
+
431
+ /**
432
+ * @brief 16-bit fractional 64-bit vector data type in 1.15 format.
433
+ */
434
+ typedef __ALIGNED(2) int16x4_t q15x4_t;
435
+
436
+ /**
437
+ * @brief 8-bit fractional 64-bit vector data type in 1.7 format.
438
+ */
439
+ typedef __ALIGNED(1) int8x8_t q7x8_t;
440
+
441
+ /**
442
+ * @brief 32-bit float 64-bit vector data type.
443
+ */
444
+ typedef float32x2_t f32x2_t;
445
+
446
+ /**
447
+ * @brief 32-bit floating-point 128-bit vector triplet data type
448
+ */
449
+ typedef float32x4x3_t f32x4x3_t;
450
+
451
+
452
+ /**
453
+ * @brief 32-bit fractional 128-bit vector triplet data type in 1.31 format
454
+ */
455
+ typedef int32x4x3_t q31x4x3_t;
456
+
457
+ /**
458
+ * @brief 16-bit fractional 128-bit vector triplet data type in 1.15 format
459
+ */
460
+ typedef int16x8x3_t q15x8x3_t;
461
+
462
+ /**
463
+ * @brief 8-bit fractional 128-bit vector triplet data type in 1.7 format
464
+ */
465
+ typedef int8x16x3_t q7x16x3_t;
466
+
467
+ /**
468
+ * @brief 32-bit floating-point 64-bit vector pair data type
469
+ */
470
+ typedef float32x2x2_t f32x2x2_t;
471
+
472
+ /**
473
+ * @brief 32-bit floating-point 64-bit vector triplet data type
474
+ */
475
+ typedef float32x2x3_t f32x2x3_t;
476
+
477
+ /**
478
+ * @brief 32-bit floating-point 64-bit vector quadruplet data type
479
+ */
480
+ typedef float32x2x4_t f32x2x4_t;
481
+
482
+
483
+ /**
484
+ * @brief 32-bit fractional 64-bit vector pair data type in 1.31 format
485
+ */
486
+ typedef int32x2x2_t q31x2x2_t;
487
+
488
+ /**
489
+ * @brief 32-bit fractional 64-bit vector triplet data type in 1.31 format
490
+ */
491
+ typedef int32x2x3_t q31x2x3_t;
492
+
493
+ /**
494
+ * @brief 32-bit fractional 64-bit vector quadruplet data type in 1.31 format
495
+ */
496
+ typedef int32x4x3_t q31x2x4_t;
497
+
498
+ /**
499
+ * @brief 16-bit fractional 64-bit vector pair data type in 1.15 format
500
+ */
501
+ typedef int16x4x2_t q15x4x2_t;
502
+
503
+ /**
504
+ * @brief 16-bit fractional 64-bit vector triplet data type in 1.15 format
505
+ */
506
+ typedef int16x4x2_t q15x4x3_t;
507
+
508
+ /**
509
+ * @brief 16-bit fractional 64-bit vector quadruplet data type in 1.15 format
510
+ */
511
+ typedef int16x4x3_t q15x4x4_t;
512
+
513
+ /**
514
+ * @brief 8-bit fractional 64-bit vector pair data type in 1.7 format
515
+ */
516
+ typedef int8x8x2_t q7x8x2_t;
517
+
518
+ /**
519
+ * @brief 8-bit fractional 64-bit vector triplet data type in 1.7 format
520
+ */
521
+ typedef int8x8x3_t q7x8x3_t;
522
+
523
+ /**
524
+ * @brief 8-bit fractional 64-bit vector quadruplet data type in 1.7 format
525
+ */
526
+ typedef int8x8x4_t q7x8x4_t;
527
+
528
+ /**
529
+ * @brief 32-bit ubiquitous 64-bit vector data type
530
+ */
531
+ typedef union _any32x2_t
532
+ {
533
+ float32x2_t f;
534
+ int32x2_t i;
535
+ } any32x2_t;
536
+
537
+
538
+ /**
539
+ * @brief 32-bit status 64-bit vector data type.
540
+ */
541
+ typedef int32x4_t status32x2_t;
542
+
543
+ /**
544
+ * @brief 16-bit status 64-bit vector data type.
545
+ */
546
+ typedef int16x8_t status16x4_t;
547
+
548
+ /**
549
+ * @brief 8-bit status 64-bit vector data type.
550
+ */
551
+ typedef int8x16_t status8x8_t;
552
+
553
+ #endif
554
+
555
+
556
+
557
+
558
+
559
+ #define F64_MAX ((float64_t)DBL_MAX)
560
+ #define F32_MAX ((float32_t)FLT_MAX)
561
+
562
+
563
+
564
+ #define F64_MIN (-DBL_MAX)
565
+ #define F32_MIN (-FLT_MAX)
566
+
567
+
568
+
569
+ #define F64_ABSMAX ((float64_t)DBL_MAX)
570
+ #define F32_ABSMAX ((float32_t)FLT_MAX)
571
+
572
+
573
+
574
+ #define F64_ABSMIN ((float64_t)0.0)
575
+ #define F32_ABSMIN ((float32_t)0.0)
576
+
577
+
578
+ #define Q31_MAX ((q31_t)(0x7FFFFFFFL))
579
+ #define Q15_MAX ((q15_t)(0x7FFF))
580
+ #define Q7_MAX ((q7_t)(0x7F))
581
+ #define Q31_MIN ((q31_t)(0x80000000L))
582
+ #define Q15_MIN ((q15_t)(0x8000))
583
+ #define Q7_MIN ((q7_t)(0x80))
584
+
585
+ #define Q31_ABSMAX ((q31_t)(0x7FFFFFFFL))
586
+ #define Q15_ABSMAX ((q15_t)(0x7FFF))
587
+ #define Q7_ABSMAX ((q7_t)(0x7F))
588
+ #define Q31_ABSMIN ((q31_t)0)
589
+ #define Q15_ABSMIN ((q15_t)0)
590
+ #define Q7_ABSMIN ((q7_t)0)
591
+
592
+ /* Dimension C vector space */
593
+ #define CMPLX_DIM 2
594
+
595
+ /**
596
+ * @brief Error status returned by some functions in the library.
597
+ */
598
+
599
+ typedef enum
600
+ {
601
+ ARM_MATH_SUCCESS = 0, /**< No error */
602
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
603
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
604
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation */
605
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
606
+ ARM_MATH_SINGULAR = -5, /**< Input matrix is singular and cannot be inverted */
607
+ ARM_MATH_TEST_FAILURE = -6, /**< Test Failed */
608
+ ARM_MATH_DECOMPOSITION_FAILURE = -7 /**< Decomposition Failed */
609
+ } arm_status;
610
+
611
+
612
+ #ifdef __cplusplus
613
+ }
614
+ #endif
615
+
616
+ #endif /*ifndef _ARM_MATH_TYPES_H_ */
edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types_f16.h ADDED
@@ -0,0 +1,163 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ /******************************************************************************
2
+ * @file arm_math_types_f16.h
3
+ * @brief Public header file for f16 function of the CMSIS DSP Library
4
+ * @version V1.10.0
5
+ * @date 08 July 2021
6
+ * Target Processor: Cortex-M and Cortex-A cores
7
+ ******************************************************************************/
8
+ /*
9
+ * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
10
+ *
11
+ * SPDX-License-Identifier: Apache-2.0
12
+ *
13
+ * Licensed under the Apache License, Version 2.0 (the License); you may
14
+ * not use this file except in compliance with the License.
15
+ * You may obtain a copy of the License at
16
+ *
17
+ * www.apache.org/licenses/LICENSE-2.0
18
+ *
19
+ * Unless required by applicable law or agreed to in writing, software
20
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
21
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22
+ * See the License for the specific language governing permissions and
23
+ * limitations under the License.
24
+ */
25
+
26
+ #ifndef _ARM_MATH_TYPES_F16_H
27
+ #define _ARM_MATH_TYPES_F16_H
28
+
29
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h"
30
+
31
+ #ifdef __cplusplus
32
+ extern "C"
33
+ {
34
+ #endif
35
+
36
+ #if !defined( __CC_ARM )
37
+
38
+ /**
39
+ * @brief 16-bit floating-point type definition.
40
+ * This is already defined in arm_mve.h
41
+ *
42
+ * This is not fully supported on ARM AC5.
43
+ */
44
+
45
+ /*
46
+
47
+ Check if the type __fp16 is available.
48
+ If it is not available, f16 version of the kernels
49
+ won't be built.
50
+
51
+ */
52
+ #if !(__ARM_FEATURE_MVE & 2)
53
+ #if !defined(DISABLEFLOAT16)
54
+ #if defined(__ARM_FP16_FORMAT_IEEE) || defined(__ARM_FP16_FORMAT_ALTERNATIVE)
55
+ typedef __fp16 float16_t;
56
+ #define ARM_FLOAT16_SUPPORTED
57
+ #endif
58
+ #endif
59
+ #else
60
+ /* When Vector float16, this flag is always defined and can't be disabled */
61
+ #define ARM_FLOAT16_SUPPORTED
62
+ #endif
63
+
64
+ #if defined(ARM_MATH_NEON) || (defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)) /* floating point vector*/
65
+
66
+ #if defined(ARM_MATH_MVE_FLOAT16) || defined(ARM_MATH_NEON_FLOAT16)
67
+
68
+ /**
69
+ * @brief 16-bit floating-point 128-bit vector data type
70
+ */
71
+ typedef __ALIGNED(2) float16x8_t f16x8_t;
72
+
73
+ /**
74
+ * @brief 16-bit floating-point 128-bit vector pair data type
75
+ */
76
+ typedef float16x8x2_t f16x8x2_t;
77
+
78
+ /**
79
+ * @brief 16-bit floating-point 128-bit vector quadruplet data type
80
+ */
81
+ typedef float16x8x4_t f16x8x4_t;
82
+
83
+ /**
84
+ * @brief 16-bit ubiquitous 128-bit vector data type
85
+ */
86
+ typedef union _any16x8_t
87
+ {
88
+ float16x8_t f;
89
+ int16x8_t i;
90
+ } any16x8_t;
91
+ #endif
92
+
93
+ #endif
94
+
95
+ #if defined(ARM_MATH_NEON)
96
+
97
+
98
+ #if defined(ARM_MATH_NEON_FLOAT16)
99
+ /**
100
+ * @brief 16-bit float 64-bit vector data type.
101
+ */
102
+ typedef __ALIGNED(2) float16x4_t f16x4_t;
103
+
104
+ /**
105
+ * @brief 16-bit floating-point 128-bit vector triplet data type
106
+ */
107
+ typedef float16x8x3_t f16x8x3_t;
108
+
109
+ /**
110
+ * @brief 16-bit floating-point 64-bit vector pair data type
111
+ */
112
+ typedef float16x4x2_t f16x4x2_t;
113
+
114
+ /**
115
+ * @brief 16-bit floating-point 64-bit vector triplet data type
116
+ */
117
+ typedef float16x4x3_t f16x4x3_t;
118
+
119
+ /**
120
+ * @brief 16-bit floating-point 64-bit vector quadruplet data type
121
+ */
122
+ typedef float16x4x4_t f16x4x4_t;
123
+
124
+ /**
125
+ * @brief 16-bit ubiquitous 64-bit vector data type
126
+ */
127
+ typedef union _any16x4_t
128
+ {
129
+ float16x4_t f;
130
+ int16x4_t i;
131
+ } any16x4_t;
132
+ #endif
133
+
134
+ #endif
135
+
136
+
137
+
138
+ #if defined(ARM_FLOAT16_SUPPORTED)
139
+
140
+ #if defined(__ICCARM__)
141
+
142
+ #define F16INFINITY ((float16_t) INFINITY)
143
+
144
+ #else
145
+
146
+ #define F16INFINITY ((float16_t)__builtin_inf())
147
+
148
+ #endif
149
+
150
+ #define F16_MAX ((float16_t)__FLT16_MAX__)
151
+ #define F16_MIN (-(_Float16)__FLT16_MAX__)
152
+
153
+ #define F16_ABSMAX ((float16_t)__FLT16_MAX__)
154
+ #define F16_ABSMIN ((float16_t)0.0f16)
155
+
156
+ #endif /* ARM_FLOAT16_SUPPORTED*/
157
+ #endif /* !defined( __CC_ARM ) */
158
+
159
+ #ifdef __cplusplus
160
+ }
161
+ #endif
162
+
163
+ #endif /* _ARM_MATH_F16_H */
edge-impulse-sdk/CMSIS/DSP/Include/arm_mve_tables.h ADDED
@@ -0,0 +1,231 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ /* ----------------------------------------------------------------------
2
+ * Project: CMSIS DSP Library
3
+ * Title: arm_mve_tables.h
4
+ * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc
5
+ * used for MVE implementation only
6
+ *
7
+ * @version V1.10.0
8
+ * @date 04 October 2021
9
+ *
10
+ * Target Processor: Cortex-M and Cortex-A cores
11
+ * -------------------------------------------------------------------- */
12
+ /*
13
+ * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
14
+ *
15
+ * SPDX-License-Identifier: Apache-2.0
16
+ *
17
+ * Licensed under the Apache License, Version 2.0 (the License); you may
18
+ * not use this file except in compliance with the License.
19
+ * You may obtain a copy of the License at
20
+ *
21
+ * www.apache.org/licenses/LICENSE-2.0
22
+ *
23
+ * Unless required by applicable law or agreed to in writing, software
24
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
25
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
26
+ * See the License for the specific language governing permissions and
27
+ * limitations under the License.
28
+ */
29
+
30
+ #ifndef _ARM_MVE_TABLES_H
31
+ #define _ARM_MVE_TABLES_H
32
+
33
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h"
34
+
35
+ #ifdef __cplusplus
36
+ extern "C"
37
+ {
38
+ #endif
39
+
40
+
41
+
42
+
43
+ #if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
44
+
45
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
46
+
47
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) || defined(ARM_TABLE_TWIDDLECOEF_F32_32)
48
+
49
+ extern uint32_t rearranged_twiddle_tab_stride1_arr_16_f32[2];
50
+ extern uint32_t rearranged_twiddle_tab_stride2_arr_16_f32[2];
51
+ extern uint32_t rearranged_twiddle_tab_stride3_arr_16_f32[2];
52
+ extern float32_t rearranged_twiddle_stride1_16_f32[8];
53
+ extern float32_t rearranged_twiddle_stride2_16_f32[8];
54
+ extern float32_t rearranged_twiddle_stride3_16_f32[8];
55
+ #endif
56
+
57
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) || defined(ARM_TABLE_TWIDDLECOEF_F32_128)
58
+
59
+ extern uint32_t rearranged_twiddle_tab_stride1_arr_64_f32[3];
60
+ extern uint32_t rearranged_twiddle_tab_stride2_arr_64_f32[3];
61
+ extern uint32_t rearranged_twiddle_tab_stride3_arr_64_f32[3];
62
+ extern float32_t rearranged_twiddle_stride1_64_f32[40];
63
+ extern float32_t rearranged_twiddle_stride2_64_f32[40];
64
+ extern float32_t rearranged_twiddle_stride3_64_f32[40];
65
+ #endif
66
+
67
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) || defined(ARM_TABLE_TWIDDLECOEF_F32_512)
68
+
69
+ extern uint32_t rearranged_twiddle_tab_stride1_arr_256_f32[4];
70
+ extern uint32_t rearranged_twiddle_tab_stride2_arr_256_f32[4];
71
+ extern uint32_t rearranged_twiddle_tab_stride3_arr_256_f32[4];
72
+ extern float32_t rearranged_twiddle_stride1_256_f32[168];
73
+ extern float32_t rearranged_twiddle_stride2_256_f32[168];
74
+ extern float32_t rearranged_twiddle_stride3_256_f32[168];
75
+ #endif
76
+
77
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048)
78
+
79
+ extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_f32[5];
80
+ extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_f32[5];
81
+ extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_f32[5];
82
+ extern float32_t rearranged_twiddle_stride1_1024_f32[680];
83
+ extern float32_t rearranged_twiddle_stride2_1024_f32[680];
84
+ extern float32_t rearranged_twiddle_stride3_1024_f32[680];
85
+ #endif
86
+
87
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) || defined(ARM_TABLE_TWIDDLECOEF_F32_8192)
88
+
89
+ extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_f32[6];
90
+ extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_f32[6];
91
+ extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_f32[6];
92
+ extern float32_t rearranged_twiddle_stride1_4096_f32[2728];
93
+ extern float32_t rearranged_twiddle_stride2_4096_f32[2728];
94
+ extern float32_t rearranged_twiddle_stride3_4096_f32[2728];
95
+ #endif
96
+
97
+
98
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
99
+
100
+ #endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */
101
+
102
+
103
+
104
+ #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE)
105
+
106
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
107
+
108
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32)
109
+
110
+ extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q31[2];
111
+ extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q31[2];
112
+ extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q31[2];
113
+ extern q31_t rearranged_twiddle_stride1_16_q31[8];
114
+ extern q31_t rearranged_twiddle_stride2_16_q31[8];
115
+ extern q31_t rearranged_twiddle_stride3_16_q31[8];
116
+ #endif
117
+
118
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128)
119
+
120
+ extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q31[3];
121
+ extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q31[3];
122
+ extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q31[3];
123
+ extern q31_t rearranged_twiddle_stride1_64_q31[40];
124
+ extern q31_t rearranged_twiddle_stride2_64_q31[40];
125
+ extern q31_t rearranged_twiddle_stride3_64_q31[40];
126
+ #endif
127
+
128
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512)
129
+
130
+ extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q31[4];
131
+ extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q31[4];
132
+ extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q31[4];
133
+ extern q31_t rearranged_twiddle_stride1_256_q31[168];
134
+ extern q31_t rearranged_twiddle_stride2_256_q31[168];
135
+ extern q31_t rearranged_twiddle_stride3_256_q31[168];
136
+ #endif
137
+
138
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048)
139
+
140
+ extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q31[5];
141
+ extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q31[5];
142
+ extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q31[5];
143
+ extern q31_t rearranged_twiddle_stride1_1024_q31[680];
144
+ extern q31_t rearranged_twiddle_stride2_1024_q31[680];
145
+ extern q31_t rearranged_twiddle_stride3_1024_q31[680];
146
+ #endif
147
+
148
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q31_8192)
149
+
150
+ extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q31[6];
151
+ extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q31[6];
152
+ extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q31[6];
153
+ extern q31_t rearranged_twiddle_stride1_4096_q31[2728];
154
+ extern q31_t rearranged_twiddle_stride2_4096_q31[2728];
155
+ extern q31_t rearranged_twiddle_stride3_4096_q31[2728];
156
+ #endif
157
+
158
+
159
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
160
+
161
+ #endif /* defined(ARM_MATH_MVEI) */
162
+
163
+
164
+
165
+ #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE)
166
+
167
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
168
+
169
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32)
170
+
171
+ extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q15[2];
172
+ extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q15[2];
173
+ extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q15[2];
174
+ extern q15_t rearranged_twiddle_stride1_16_q15[8];
175
+ extern q15_t rearranged_twiddle_stride2_16_q15[8];
176
+ extern q15_t rearranged_twiddle_stride3_16_q15[8];
177
+ #endif
178
+
179
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128)
180
+
181
+ extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q15[3];
182
+ extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q15[3];
183
+ extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q15[3];
184
+ extern q15_t rearranged_twiddle_stride1_64_q15[40];
185
+ extern q15_t rearranged_twiddle_stride2_64_q15[40];
186
+ extern q15_t rearranged_twiddle_stride3_64_q15[40];
187
+ #endif
188
+
189
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512)
190
+
191
+ extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q15[4];
192
+ extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q15[4];
193
+ extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q15[4];
194
+ extern q15_t rearranged_twiddle_stride1_256_q15[168];
195
+ extern q15_t rearranged_twiddle_stride2_256_q15[168];
196
+ extern q15_t rearranged_twiddle_stride3_256_q15[168];
197
+ #endif
198
+
199
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048)
200
+
201
+ extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q15[5];
202
+ extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q15[5];
203
+ extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q15[5];
204
+ extern q15_t rearranged_twiddle_stride1_1024_q15[680];
205
+ extern q15_t rearranged_twiddle_stride2_1024_q15[680];
206
+ extern q15_t rearranged_twiddle_stride3_1024_q15[680];
207
+ #endif
208
+
209
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q15_8192)
210
+
211
+ extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q15[6];
212
+ extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q15[6];
213
+ extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q15[6];
214
+ extern q15_t rearranged_twiddle_stride1_4096_q15[2728];
215
+ extern q15_t rearranged_twiddle_stride2_4096_q15[2728];
216
+ extern q15_t rearranged_twiddle_stride3_4096_q15[2728];
217
+ #endif
218
+
219
+
220
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
221
+
222
+ #endif /* defined(ARM_MATH_MVEI) */
223
+
224
+
225
+
226
+ #ifdef __cplusplus
227
+ }
228
+ #endif
229
+
230
+ #endif /*_ARM_MVE_TABLES_H*/
231
+
edge-impulse-sdk/CMSIS/DSP/Include/arm_mve_tables_f16.h ADDED
@@ -0,0 +1,109 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ /* ----------------------------------------------------------------------
2
+ * Project: CMSIS DSP Library
3
+ * Title: arm_mve_tables_f16.h
4
+ * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc
5
+ * used for MVE implementation only
6
+ *
7
+ * @version V1.10.0
8
+ * @date 04 October 2021
9
+ *
10
+ * Target Processor: Cortex-M and Cortex-A cores
11
+ * -------------------------------------------------------------------- */
12
+ /*
13
+ * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
14
+ *
15
+ * SPDX-License-Identifier: Apache-2.0
16
+ *
17
+ * Licensed under the Apache License, Version 2.0 (the License); you may
18
+ * not use this file except in compliance with the License.
19
+ * You may obtain a copy of the License at
20
+ *
21
+ * www.apache.org/licenses/LICENSE-2.0
22
+ *
23
+ * Unless required by applicable law or agreed to in writing, software
24
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
25
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
26
+ * See the License for the specific language governing permissions and
27
+ * limitations under the License.
28
+ */
29
+
30
+ #ifndef _ARM_MVE_TABLES_F16_H
31
+ #define _ARM_MVE_TABLES_F16_H
32
+
33
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types_f16.h"
34
+
35
+ #ifdef __cplusplus
36
+ extern "C"
37
+ {
38
+ #endif
39
+
40
+
41
+
42
+
43
+ #if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE)
44
+
45
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
46
+
47
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_16) || defined(ARM_TABLE_TWIDDLECOEF_F16_32)
48
+
49
+ extern uint32_t rearranged_twiddle_tab_stride1_arr_16_f16[2];
50
+ extern uint32_t rearranged_twiddle_tab_stride2_arr_16_f16[2];
51
+ extern uint32_t rearranged_twiddle_tab_stride3_arr_16_f16[2];
52
+ extern float16_t rearranged_twiddle_stride1_16_f16[8];
53
+ extern float16_t rearranged_twiddle_stride2_16_f16[8];
54
+ extern float16_t rearranged_twiddle_stride3_16_f16[8];
55
+ #endif
56
+
57
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_64) || defined(ARM_TABLE_TWIDDLECOEF_F16_128)
58
+
59
+ extern uint32_t rearranged_twiddle_tab_stride1_arr_64_f16[3];
60
+ extern uint32_t rearranged_twiddle_tab_stride2_arr_64_f16[3];
61
+ extern uint32_t rearranged_twiddle_tab_stride3_arr_64_f16[3];
62
+ extern float16_t rearranged_twiddle_stride1_64_f16[40];
63
+ extern float16_t rearranged_twiddle_stride2_64_f16[40];
64
+ extern float16_t rearranged_twiddle_stride3_64_f16[40];
65
+ #endif
66
+
67
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_256) || defined(ARM_TABLE_TWIDDLECOEF_F16_512)
68
+
69
+ extern uint32_t rearranged_twiddle_tab_stride1_arr_256_f16[4];
70
+ extern uint32_t rearranged_twiddle_tab_stride2_arr_256_f16[4];
71
+ extern uint32_t rearranged_twiddle_tab_stride3_arr_256_f16[4];
72
+ extern float16_t rearranged_twiddle_stride1_256_f16[168];
73
+ extern float16_t rearranged_twiddle_stride2_256_f16[168];
74
+ extern float16_t rearranged_twiddle_stride3_256_f16[168];
75
+ #endif
76
+
77
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_1024) || defined(ARM_TABLE_TWIDDLECOEF_F16_2048)
78
+
79
+ extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_f16[5];
80
+ extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_f16[5];
81
+ extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_f16[5];
82
+ extern float16_t rearranged_twiddle_stride1_1024_f16[680];
83
+ extern float16_t rearranged_twiddle_stride2_1024_f16[680];
84
+ extern float16_t rearranged_twiddle_stride3_1024_f16[680];
85
+ #endif
86
+
87
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_4096) || defined(ARM_TABLE_TWIDDLECOEF_F16_8192)
88
+
89
+ extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_f16[6];
90
+ extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_f16[6];
91
+ extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_f16[6];
92
+ extern float16_t rearranged_twiddle_stride1_4096_f16[2728];
93
+ extern float16_t rearranged_twiddle_stride2_4096_f16[2728];
94
+ extern float16_t rearranged_twiddle_stride3_4096_f16[2728];
95
+ #endif
96
+
97
+
98
+ #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
99
+
100
+ #endif /* defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) */
101
+
102
+
103
+
104
+ #ifdef __cplusplus
105
+ }
106
+ #endif
107
+
108
+ #endif /*_ARM_MVE_TABLES_F16_H*/
109
+
edge-impulse-sdk/CMSIS/DSP/Include/arm_sorting.h ADDED
@@ -0,0 +1,200 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ /******************************************************************************
2
+ * @file arm_sorting.h
3
+ * @brief Private header file for CMSIS DSP Library
4
+ * @version V1.7.0
5
+ * @date 2019
6
+ ******************************************************************************/
7
+ /*
8
+ * Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved.
9
+ *
10
+ * SPDX-License-Identifier: Apache-2.0
11
+ *
12
+ * Licensed under the Apache License, Version 2.0 (the License); you may
13
+ * not use this file except in compliance with the License.
14
+ * You may obtain a copy of the License at
15
+ *
16
+ * www.apache.org/licenses/LICENSE-2.0
17
+ *
18
+ * Unless required by applicable law or agreed to in writing, software
19
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21
+ * See the License for the specific language governing permissions and
22
+ * limitations under the License.
23
+ */
24
+
25
+ #ifndef _ARM_SORTING_H_
26
+ #define _ARM_SORTING_H_
27
+
28
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math.h"
29
+
30
+ #ifdef __cplusplus
31
+ extern "C"
32
+ {
33
+ #endif
34
+
35
+ /**
36
+ * @param[in] S points to an instance of the sorting structure.
37
+ * @param[in] pSrc points to the block of input data.
38
+ * @param[out] pDst points to the block of output data.
39
+ * @param[in] blockSize number of samples to process.
40
+ */
41
+ void arm_bubble_sort_f32(
42
+ const arm_sort_instance_f32 * S,
43
+ float32_t * pSrc,
44
+ float32_t * pDst,
45
+ uint32_t blockSize);
46
+
47
+ /**
48
+ * @param[in] S points to an instance of the sorting structure.
49
+ * @param[in] pSrc points to the block of input data.
50
+ * @param[out] pDst points to the block of output data.
51
+ * @param[in] blockSize number of samples to process.
52
+ */
53
+ void arm_heap_sort_f32(
54
+ const arm_sort_instance_f32 * S,
55
+ float32_t * pSrc,
56
+ float32_t * pDst,
57
+ uint32_t blockSize);
58
+
59
+ /**
60
+ * @param[in] S points to an instance of the sorting structure.
61
+ * @param[in] pSrc points to the block of input data.
62
+ * @param[out] pDst points to the block of output data.
63
+ * @param[in] blockSize number of samples to process.
64
+ */
65
+ void arm_insertion_sort_f32(
66
+ const arm_sort_instance_f32 * S,
67
+ float32_t *pSrc,
68
+ float32_t* pDst,
69
+ uint32_t blockSize);
70
+
71
+ /**
72
+ * @param[in] S points to an instance of the sorting structure.
73
+ * @param[in] pSrc points to the block of input data.
74
+ * @param[out] pDst points to the block of output data
75
+ * @param[in] blockSize number of samples to process.
76
+ */
77
+ void arm_quick_sort_f32(
78
+ const arm_sort_instance_f32 * S,
79
+ float32_t * pSrc,
80
+ float32_t * pDst,
81
+ uint32_t blockSize);
82
+
83
+ /**
84
+ * @param[in] S points to an instance of the sorting structure.
85
+ * @param[in] pSrc points to the block of input data.
86
+ * @param[out] pDst points to the block of output data
87
+ * @param[in] blockSize number of samples to process.
88
+ */
89
+ void arm_selection_sort_f32(
90
+ const arm_sort_instance_f32 * S,
91
+ float32_t * pSrc,
92
+ float32_t * pDst,
93
+ uint32_t blockSize);
94
+
95
+ /**
96
+ * @param[in] S points to an instance of the sorting structure.
97
+ * @param[in] pSrc points to the block of input data.
98
+ * @param[out] pDst points to the block of output data
99
+ * @param[in] blockSize number of samples to process.
100
+ */
101
+ void arm_bitonic_sort_f32(
102
+ const arm_sort_instance_f32 * S,
103
+ float32_t * pSrc,
104
+ float32_t * pDst,
105
+ uint32_t blockSize);
106
+
107
+ #if defined(ARM_MATH_NEON)
108
+
109
+ #define vtrn256_128q(a, b) \
110
+ do { \
111
+ float32x4_t vtrn128_temp = a.val[1]; \
112
+ a.val[1] = b.val[0]; \
113
+ b.val[0] = vtrn128_temp ; \
114
+ } while (0)
115
+
116
+ #define vtrn128_64q(a, b) \
117
+ do { \
118
+ float32x2_t ab, cd, ef, gh; \
119
+ ab = vget_low_f32(a); \
120
+ ef = vget_low_f32(b); \
121
+ cd = vget_high_f32(a); \
122
+ gh = vget_high_f32(b); \
123
+ a = vcombine_f32(ab, ef); \
124
+ b = vcombine_f32(cd, gh); \
125
+ } while (0)
126
+
127
+ #define vtrn256_64q(a, b) \
128
+ do { \
129
+ float32x2_t a_0, a_1, a_2, a_3; \
130
+ float32x2_t b_0, b_1, b_2, b_3; \
131
+ a_0 = vget_low_f32(a.val[0]); \
132
+ a_1 = vget_high_f32(a.val[0]); \
133
+ a_2 = vget_low_f32(a.val[1]); \
134
+ a_3 = vget_high_f32(a.val[1]); \
135
+ b_0 = vget_low_f32(b.val[0]); \
136
+ b_1 = vget_high_f32(b.val[0]); \
137
+ b_2 = vget_low_f32(b.val[1]); \
138
+ b_3 = vget_high_f32(b.val[1]); \
139
+ a.val[0] = vcombine_f32(a_0, b_0); \
140
+ a.val[1] = vcombine_f32(a_2, b_2); \
141
+ b.val[0] = vcombine_f32(a_1, b_1); \
142
+ b.val[1] = vcombine_f32(a_3, b_3); \
143
+ } while (0)
144
+
145
+ #define vtrn128_32q(a, b) \
146
+ do { \
147
+ float32x4x2_t vtrn32_tmp = vtrnq_f32((a), (b)); \
148
+ (a) = vtrn32_tmp.val[0]; \
149
+ (b) = vtrn32_tmp.val[1]; \
150
+ } while (0)
151
+
152
+ #define vtrn256_32q(a, b) \
153
+ do { \
154
+ float32x4x2_t vtrn32_tmp_1 = vtrnq_f32((a.val[0]), (b.val[0])); \
155
+ float32x4x2_t vtrn32_tmp_2 = vtrnq_f32((a.val[1]), (b.val[1])); \
156
+ a.val[0] = vtrn32_tmp_1.val[0]; \
157
+ a.val[1] = vtrn32_tmp_2.val[0]; \
158
+ b.val[0] = vtrn32_tmp_1.val[1]; \
159
+ b.val[1] = vtrn32_tmp_2.val[1]; \
160
+ } while (0)
161
+
162
+ #define vminmaxq(a, b) \
163
+ do { \
164
+ float32x4_t minmax_tmp = (a); \
165
+ (a) = vminq_f32((a), (b)); \
166
+ (b) = vmaxq_f32(minmax_tmp, (b)); \
167
+ } while (0)
168
+
169
+ #define vminmax256q(a, b) \
170
+ do { \
171
+ float32x4x2_t minmax256_tmp = (a); \
172
+ a.val[0] = vminq_f32(a.val[0], b.val[0]); \
173
+ a.val[1] = vminq_f32(a.val[1], b.val[1]); \
174
+ b.val[0] = vmaxq_f32(minmax256_tmp.val[0], b.val[0]); \
175
+ b.val[1] = vmaxq_f32(minmax256_tmp.val[1], b.val[1]); \
176
+ } while (0)
177
+
178
+ #define vrev128q_f32(a) \
179
+ vcombine_f32(vrev64_f32(vget_high_f32(a)), vrev64_f32(vget_low_f32(a)))
180
+
181
+ #define vrev256q_f32(a) \
182
+ do { \
183
+ float32x4_t rev_tmp = vcombine_f32(vrev64_f32(vget_high_f32(a.val[0])), vrev64_f32(vget_low_f32(a.val[0]))); \
184
+ a.val[0] = vcombine_f32(vrev64_f32(vget_high_f32(a.val[1])), vrev64_f32(vget_low_f32(a.val[1]))); \
185
+ a.val[1] = rev_tmp; \
186
+ } while (0)
187
+
188
+ #define vldrev128q_f32(a, p) \
189
+ do { \
190
+ a = vld1q_f32(p); \
191
+ a = vrev128q_f32(a); \
192
+ } while (0)
193
+
194
+ #endif /* ARM_MATH_NEON */
195
+
196
+ #ifdef __cplusplus
197
+ }
198
+ #endif
199
+
200
+ #endif /* _ARM_SORTING_H */
edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_fft.h ADDED
@@ -0,0 +1,325 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ /******************************************************************************
2
+ * @file arm_vec_fft.h
3
+ * @brief Private header file for CMSIS DSP Library
4
+ * @version V1.7.0
5
+ * @date 07. January 2020
6
+ ******************************************************************************/
7
+ /*
8
+ * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
9
+ *
10
+ * SPDX-License-Identifier: Apache-2.0
11
+ *
12
+ * Licensed under the Apache License, Version 2.0 (the License); you may
13
+ * not use this file except in compliance with the License.
14
+ * You may obtain a copy of the License at
15
+ *
16
+ * www.apache.org/licenses/LICENSE-2.0
17
+ *
18
+ * Unless required by applicable law or agreed to in writing, software
19
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21
+ * See the License for the specific language governing permissions and
22
+ * limitations under the License.
23
+ */
24
+
25
+ #ifndef _ARM_VEC_FFT_H_
26
+ #define _ARM_VEC_FFT_H_
27
+
28
+ #include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math.h"
29
+ #include "arm_helium_utils.h"
30
+
31
+ #ifdef __cplusplus
32
+ extern "C"
33
+ {
34
+ #endif
35
+
36
+ #if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)
37
+
38
+ #define MVE_CMPLX_ADD_A_ixB(A, B) vcaddq_rot90(A,B)
39
+ #define MVE_CMPLX_SUB_A_ixB(A,B) vcaddq_rot270(A,B)
40
+ #define MVE_CMPLX_MULT_FLT_AxB(A,B) vcmlaq_rot90(vcmulq(A, B), A, B)
41
+ #define MVE_CMPLX_MULT_FLT_Conj_AxB(A,B) vcmlaq_rot270(vcmulq(A, B), A, B)
42
+
43
+ #define MVE_CMPLX_MULT_FX_AxB(A,B,TyA) vqdmladhxq(vqdmlsdhq((TyA)vuninitializedq_s32(), A, B), A, B)
44
+ #define MVE_CMPLX_MULT_FX_AxConjB(A,B,TyA) vqdmladhq(vqdmlsdhxq((TyA)vuninitializedq_s32(), A, B), A, B)
45
+
46
+ #define MVE_CMPLX_ADD_FX_A_ixB(A, B) vhcaddq_rot90(A,B)
47
+ #define MVE_CMPLX_SUB_FX_A_ixB(A,B) vhcaddq_rot270(A,B)
48
+
49
+
50
+ /**
51
+ @brief In-place 32 bit reversal function for helium
52
+ @param[in,out] pSrc points to in-place buffer of unknown 32-bit data type
53
+ @param[in] bitRevLen bit reversal table length
54
+ @param[in] pBitRevTab points to bit reversal table
55
+ @return none
56
+ */
57
+
58
+ __STATIC_INLINE void arm_bitreversal_32_inpl_mve(
59
+ uint32_t *pSrc,
60
+ const uint16_t bitRevLen,
61
+ const uint16_t *pBitRevTab)
62
+
63
+ {
64
+ uint64_t *src = (uint64_t *) pSrc;
65
+ int32_t blkCnt; /* loop counters */
66
+ uint32x4_t bitRevTabOff;
67
+ uint32x4_t one = vdupq_n_u32(1);
68
+ uint64x2_t inLow, inHigh;
69
+ uint64x2_t bitRevOff1Low, bitRevOff0Low;
70
+ uint64x2_t bitRevOff1High, bitRevOff0High;
71
+
72
+ /* load scheduling to increase gather load idx update / gather load distance */
73
+ bitRevTabOff = vldrhq_u32(pBitRevTab);
74
+ pBitRevTab += 4;
75
+
76
+ bitRevOff0Low = vmullbq_int_u32(bitRevTabOff, one);
77
+ bitRevOff0High = vmulltq_int_u32(bitRevTabOff, one);
78
+
79
+
80
+ blkCnt = bitRevLen / 8;
81
+ while (blkCnt > 0) {
82
+ bitRevTabOff = vldrhq_u32(pBitRevTab);
83
+ pBitRevTab += 4;
84
+
85
+ /* 64-bit index expansion */
86
+ bitRevOff1Low = vmullbq_int_u32(bitRevTabOff, one);
87
+ bitRevOff1High = vmulltq_int_u32(bitRevTabOff, one);
88
+
89
+ inLow = vldrdq_gather_offset_u64(src, bitRevOff0Low);
90
+ inHigh = vldrdq_gather_offset_u64(src, bitRevOff0High);
91
+
92
+ vstrdq_scatter_offset_u64(src, bitRevOff0Low, inHigh);
93
+ vstrdq_scatter_offset_u64(src, bitRevOff0High, inLow);
94
+
95
+
96
+ /* unrolled */
97
+ bitRevTabOff = vldrhq_u32(pBitRevTab);
98
+ pBitRevTab += 4;
99
+
100
+ bitRevOff0Low = vmullbq_int_u32(bitRevTabOff, one);
101
+ bitRevOff0High = vmulltq_int_u32(bitRevTabOff, one);
102
+
103
+ inLow = vldrdq_gather_offset_u64(src, bitRevOff1Low);
104
+ inHigh = vldrdq_gather_offset_u64(src, bitRevOff1High);
105
+
106
+ vstrdq_scatter_offset_u64(src, bitRevOff1Low, inHigh);
107
+ vstrdq_scatter_offset_u64(src, bitRevOff1High, inLow);
108
+
109
+ /*
110
+ * Decrement the blockSize loop counter
111
+ */
112
+ blkCnt--;
113
+ }
114
+
115
+ if (bitRevLen & 7) {
116
+ /* FFT size = 16 */
117
+ inLow = vldrdq_gather_offset_u64(src, bitRevOff0Low);
118
+ inHigh = vldrdq_gather_offset_u64(src, bitRevOff0High);
119
+
120
+ vstrdq_scatter_offset_u64(src, bitRevOff0Low, inHigh);
121
+ vstrdq_scatter_offset_u64(src, bitRevOff0High, inLow);
122
+ }
123
+ }
124
+
125
+
126
+
127
+ /**
128
+ @brief In-place 16 bit reversal function for helium
129
+ @param[in,out] pSrc points to in-place buffer of unknown 16-bit data type
130
+ @param[in] bitRevLen bit reversal table length
131
+ @param[in] pBitRevTab points to bit reversal table
132
+ @return none
133
+ */
134
+
135
+ __STATIC_INLINE void arm_bitreversal_16_inpl_mve(
136
+ uint16_t *pSrc,
137
+ const uint16_t bitRevLen,
138
+ const uint16_t *pBitRevTab)
139
+
140
+ {
141
+ uint32_t *src = (uint32_t *) pSrc;
142
+ int32_t blkCnt; /* loop counters */
143
+ uint32x4_t bitRevTabOff;
144
+ uint16x8_t one = vdupq_n_u16(1);
145
+ uint32x4_t bitRevOff1Low, bitRevOff0Low;
146
+ uint32x4_t bitRevOff1High, bitRevOff0High;
147
+ uint32x4_t inLow, inHigh;
148
+
149
+ /* load scheduling to increase gather load idx update / gather load distance */
150
+ bitRevTabOff = vldrhq_u16(pBitRevTab);
151
+ pBitRevTab += 8;
152
+
153
+ bitRevOff0Low = vmullbq_int_u16((uint16x8_t)bitRevTabOff, one);
154
+ bitRevOff0High = vmulltq_int_u16((uint16x8_t)bitRevTabOff, one);
155
+ bitRevOff0Low = vshrq_n_u16((uint16x8_t)bitRevOff0Low, 3);
156
+ bitRevOff0High = vshrq_n_u16((uint16x8_t)bitRevOff0High, 3);
157
+
158
+ blkCnt = (bitRevLen / 16);
159
+ while (blkCnt > 0) {
160
+ bitRevTabOff = vldrhq_u16(pBitRevTab);
161
+ pBitRevTab += 8;
162
+
163
+ bitRevOff1Low = vmullbq_int_u16((uint16x8_t)bitRevTabOff, one);
164
+ bitRevOff1High = vmulltq_int_u16((uint16x8_t)bitRevTabOff, one);
165
+ bitRevOff1Low = vshrq_n_u16((uint16x8_t)bitRevOff1Low, 3);
166
+ bitRevOff1High = vshrq_n_u16((uint16x8_t)bitRevOff1High, 3);
167
+
168
+ inLow = vldrwq_gather_shifted_offset_u32(src, bitRevOff0Low);
169
+ inHigh = vldrwq_gather_shifted_offset_u32(src, bitRevOff0High);
170
+
171
+ vstrwq_scatter_shifted_offset_u32(src, bitRevOff0Low, inHigh);
172
+ vstrwq_scatter_shifted_offset_u32(src, bitRevOff0High, inLow);
173
+
174
+ /* loop unrolling */
175
+ bitRevTabOff = vldrhq_u16(pBitRevTab);
176
+ pBitRevTab += 8;
177
+
178
+ bitRevOff0Low = vmullbq_int_u16((uint16x8_t)bitRevTabOff, one);
179
+ bitRevOff0High = vmulltq_int_u16((uint16x8_t)bitRevTabOff, one);
180
+ bitRevOff0Low = vshrq_n_u16((uint16x8_t)bitRevOff0Low, 3);
181
+ bitRevOff0High = vshrq_n_u16((uint16x8_t)bitRevOff0High, 3);
182
+
183
+ inLow = vldrwq_gather_shifted_offset_u32(src, bitRevOff1Low);
184
+ inHigh = vldrwq_gather_shifted_offset_u32(src, bitRevOff1High);
185
+
186
+ vstrwq_scatter_shifted_offset_u32(src, bitRevOff1Low, inHigh);
187
+ vstrwq_scatter_shifted_offset_u32(src, bitRevOff1High, inLow);
188
+
189
+ blkCnt--;
190
+ }
191
+
192
+ /* tail handling */
193
+ blkCnt = bitRevLen & 0xf;
194
+ if (blkCnt == 8) {
195
+ inLow = vldrwq_gather_shifted_offset_u32(src, bitRevOff0Low);
196
+ inHigh = vldrwq_gather_shifted_offset_u32(src, bitRevOff0High);
197
+
198
+ vstrwq_scatter_shifted_offset_u32(src, bitRevOff0Low, inHigh);
199
+ vstrwq_scatter_shifted_offset_u32(src, bitRevOff0High, inLow);
200
+ } else if (blkCnt == 12) {
201
+ /* FFT 16 special case */
202
+ mve_pred16_t p = vctp16q(4);
203
+
204
+ bitRevTabOff = vldrhq_z_u16(pBitRevTab, p);
205
+
206
+ inLow = vldrwq_gather_shifted_offset_u32(src, bitRevOff0Low);
207
+ inHigh = vldrwq_gather_shifted_offset_u32(src, bitRevOff0High);
208
+
209
+ vstrwq_scatter_shifted_offset_u32(src, bitRevOff0Low, inHigh);
210
+ vstrwq_scatter_shifted_offset_u32(src, bitRevOff0High, inLow);
211
+
212
+ bitRevOff0Low = vmullbq_int_u16((uint16x8_t)bitRevTabOff, one);
213
+ bitRevOff0High = vmulltq_int_u16((uint16x8_t)bitRevTabOff, one);
214
+ bitRevOff0Low = vshrq_n_u16((uint16x8_t)bitRevOff0Low, 3);
215
+ bitRevOff0High = vshrq_n_u16((uint16x8_t)bitRevOff0High, 3);
216
+
217
+ inLow = vldrwq_gather_shifted_offset_z_u32(src, bitRevOff0Low, p);
218
+ inHigh = vldrwq_gather_shifted_offset_z_u32(src, bitRevOff0High, p);
219
+
220
+ vstrwq_scatter_shifted_offset_p_u32(src, bitRevOff0Low, inHigh, p);
221
+ vstrwq_scatter_shifted_offset_p_u32(src, bitRevOff0High, inLow, p);
222
+ }
223
+ }
224
+
225
+ /**
226
+ @brief Out-of-place 32 bit reversal function for helium
227
+ @param[out] pDst points to destination buffer of unknown 32-bit data type
228
+ @param[in] pSrc points to input buffer of unknown 32-bit data type
229
+ @param[in] fftLen FFT length
230
+ @return none
231
+ */
232
+ __STATIC_INLINE void arm_bitreversal_32_outpl_mve(void *pDst, void *pSrc, uint32_t fftLen)
233
+ {
234
+ uint32x4_t idxOffs0, idxOffs1, bitRevOffs0, bitRevOffs1;
235
+ uint32_t bitRevPos, blkCnt;
236
+ uint32_t *pDst32 = (uint32_t *) pDst;
237
+
238
+ /* fwd indexes */
239
+ idxOffs0 = vdupq_n_u32(0);
240
+ idxOffs1 = vdupq_n_u32(0);
241
+ idxOffs0[0] = 0; idxOffs0[2] = 4;
242
+ idxOffs1[0] = 8; idxOffs1[2] = 12;
243
+
244
+ bitRevPos = (31 - __CLZ(fftLen)) + 5;
245
+ blkCnt = fftLen >> 2;
246
+
247
+ /* issued earlier to increase gather load idx update / gather load distance */
248
+ /* bit-reverse fwd indexes */
249
+ bitRevOffs0 = vbrsrq(idxOffs0, bitRevPos);
250
+ bitRevOffs1 = vbrsrq(idxOffs1, bitRevPos);
251
+ while (blkCnt > 0) {
252
+ uint64x2_t vecIn;
253
+
254
+ vecIn = vldrdq_gather_offset_u64(pSrc, (uint64x2_t) bitRevOffs0);
255
+ idxOffs0 = idxOffs0 + 16;
256
+ vst1q(pDst32, (uint32x4_t) vecIn);
257
+ pDst32 += 4;
258
+ bitRevOffs0 = vbrsrq(idxOffs0, bitRevPos);
259
+
260
+ vecIn = vldrdq_gather_offset_u64(pSrc, (uint64x2_t) bitRevOffs1);
261
+ idxOffs1 = idxOffs1 + 16;
262
+ vst1q(pDst32, (uint32x4_t) vecIn);
263
+ pDst32 += 4;
264
+ bitRevOffs1 = vbrsrq(idxOffs1, bitRevPos);
265
+
266
+ blkCnt--;
267
+ }
268
+ }
269
+
270
+
271
+ /**
272
+ @brief Out-of-place 16 bit reversal function for helium
273
+ @param[out] pDst points to destination buffer of unknown 16-bit data type
274
+ @param[in] pSrc points to input buffer of unknown 16-bit data type
275
+ @param[in] fftLen FFT length
276
+ @return none
277
+ */
278
+
279
+ __STATIC_INLINE void arm_bitreversal_16_outpl_mve(void *pDst, void *pSrc, uint32_t fftLen)
280
+ {
281
+ uint32x4_t idxOffs0, idxOffs1, bitRevOffs0, bitRevOffs1;
282
+ uint32_t bitRevPos, blkCnt;
283
+ uint16_t *pDst16 = (uint16_t *) pDst;
284
+ uint32_t incrIdx = 0;
285
+
286
+ /* fwd indexes */
287
+ idxOffs0 = vidupq_wb_u32(&incrIdx, 4); // {0, 4, 8, 12}
288
+ idxOffs1 = vidupq_wb_u32(&incrIdx, 4); // {16, 20, 24, 28}
289
+
290
+ bitRevPos = (31 - __CLZ(fftLen)) + 4;
291
+ blkCnt = fftLen >> 3;
292
+
293
+ /* issued earlier to increase gather load idx update / gather load distance */
294
+ /* bit-reverse fwd indexes */
295
+ bitRevOffs0 = vbrsrq(idxOffs0, bitRevPos);
296
+ bitRevOffs1 = vbrsrq(idxOffs1, bitRevPos);
297
+ while (blkCnt > 0) {
298
+ uint32x4_t vecIn;
299
+
300
+ vecIn = vldrwq_gather_offset_s32(pSrc, bitRevOffs0);
301
+ idxOffs0 = idxOffs0 + 32;
302
+ vst1q(pDst16, (uint16x8_t) vecIn);
303
+ pDst16 += 8;
304
+ bitRevOffs0 = vbrsrq(idxOffs0, bitRevPos);
305
+
306
+ vecIn = vldrwq_gather_offset_s32(pSrc, bitRevOffs1);
307
+ idxOffs1 = idxOffs1 + 32;
308
+ vst1q(pDst16, (uint16x8_t) vecIn);
309
+ pDst16 += 8;
310
+ bitRevOffs1 = vbrsrq(idxOffs1, bitRevPos);
311
+
312
+ blkCnt--;
313
+ }
314
+ }
315
+
316
+
317
+ #endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)*/
318
+
319
+
320
+ #ifdef __cplusplus
321
+ }
322
+ #endif
323
+
324
+
325
+ #endif /* _ARM_VEC_FFT_H_ */