Upload DistilBertForSequenceClassification

config.json

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+{
+  "_name_or_path": "distilbert-base-uncased",
+  "activation": "gelu",
+  "architectures": [
+    "DistilBertForSequenceClassification"
+  ],
+  "attention_dropout": 0.1,
+  "dim": 768,
+  "dropout": 0.1,
+  "hidden_dim": 3072,
+  "id2label": {
+    "0": "Misc",
+    "1": "UART_RX",
+    "2": "Diff_N",
+    "3": "I2C_SCL",
+    "4": "Ethernet_RXD0",
+    "5": "I2C_SDA",
+    "6": "SD_D1",
+    "7": "QSPI_SCK",
+    "8": "Diff_P",
+    "9": "Ethernet_diff_N",
+    "10": "Ethernet_MDC",
+    "11": "Ethernet_diff_P",
+    "12": "SD_D7",
+    "13": "Ethernet_RXD3",
+    "14": "Ethernet_TXD2",
+    "15": "USB_diff_N",
+    "16": "Ethernet_RXER",
+    "17": "USB_diff_P",
+    "18": "CAN_diff_N",
+    "19": "SD_D5",
+    "20": "Jtag_CLK",
+    "21": "SD_D2",
+    "22": "SPI_MOSI",
+    "23": "SPI_SCK",
+    "24": "UART_TX",
+    "25": "QSPI_CS",
+    "26": "Ethernet_TXCLK",
+    "27": "QSPI_IO1",
+    "28": "I3C_SCL",
+    "29": "LIN_TX",
+    "30": "CAN_diff_P",
+    "31": "Clock",
+    "32": "SPI_MISO",
+    "33": "Ethernet_RXD1",
+    "34": "LIN_RX",
+    "35": "QSPI_IO3",
+    "36": "Ethernet_TXD1",
+    "37": "SD_D0",
+    "38": "Ethernet_RXD2",
+    "39": "CAN_DIG_RX",
+    "40": "SD_CMD",
+    "41": "SD_CLK",
+    "42": "I3C_SDA",
+    "43": "SD_D6",
+    "44": "Ethernet_TXD0",
+    "45": "SD_D3",
+    "46": "Ethernet_CRS",
+    "47": "Ethernet_TXD3",
+    "48": "Ethernet_MDIO",
+    "49": "Ethernet_RXDV",
+    "50": "Ethernet_COL",
+    "51": "Jtag_TDI",
+    "52": "Ethernet_RXCLK",
+    "53": "CAN_DIG_TX",
+    "54": "Jtag_TMS",
+    "55": "QSPI_IO6",
+    "56": "Jtag_TDO",
+    "57": "QSPI_IO2",
+    "58": "SPI_CS",
+    "59": "Ethernet_TXER",
+    "60": "QSPI_IO0",
+    "61": "QSPI_IO5",
+    "62": "QSPI_IO7",
+    "63": "QSPI_IO4",
+    "64": "SD_D4"
+  },
+  "initializer_range": 0.02,
+  "label2id": {
+    "CAN_DIG_RX": 39,
+    "CAN_DIG_TX": 53,
+    "CAN_diff_N": 18,
+    "CAN_diff_P": 30,
+    "Clock": 31,
+    "Diff_N": 2,
+    "Diff_P": 8,
+    "Ethernet_COL": 50,
+    "Ethernet_CRS": 46,
+    "Ethernet_MDC": 10,
+    "Ethernet_MDIO": 48,
+    "Ethernet_RXCLK": 52,
+    "Ethernet_RXD0": 4,
+    "Ethernet_RXD1": 33,
+    "Ethernet_RXD2": 38,
+    "Ethernet_RXD3": 13,
+    "Ethernet_RXDV": 49,
+    "Ethernet_RXER": 16,
+    "Ethernet_TXCLK": 26,
+    "Ethernet_TXD0": 44,
+    "Ethernet_TXD1": 36,
+    "Ethernet_TXD2": 14,
+    "Ethernet_TXD3": 47,
+    "Ethernet_TXER": 59,
+    "Ethernet_diff_N": 9,
+    "Ethernet_diff_P": 11,
+    "I2C_SCL": 3,
+    "I2C_SDA": 5,
+    "I3C_SCL": 28,
+    "I3C_SDA": 42,
+    "Jtag_CLK": 20,
+    "Jtag_TDI": 51,
+    "Jtag_TDO": 56,
+    "Jtag_TMS": 54,
+    "LIN_RX": 34,
+    "LIN_TX": 29,
+    "Misc": 0,
+    "QSPI_CS": 25,
+    "QSPI_IO0": 60,
+    "QSPI_IO1": 27,
+    "QSPI_IO2": 57,
+    "QSPI_IO3": 35,
+    "QSPI_IO4": 63,
+    "QSPI_IO5": 61,
+    "QSPI_IO6": 55,
+    "QSPI_IO7": 62,
+    "QSPI_SCK": 7,
+    "SD_CLK": 41,
+    "SD_CMD": 40,
+    "SD_D0": 37,
+    "SD_D1": 6,
+    "SD_D2": 21,
+    "SD_D3": 45,
+    "SD_D4": 64,
+    "SD_D5": 19,
+    "SD_D6": 43,
+    "SD_D7": 12,
+    "SPI_CS": 58,
+    "SPI_MISO": 32,
+    "SPI_MOSI": 22,
+    "SPI_SCK": 23,
+    "UART_RX": 1,
+    "UART_TX": 24,
+    "USB_diff_N": 15,
+    "USB_diff_P": 17
+  },
+  "max_position_embeddings": 512,
+  "model_type": "distilbert",
+  "n_heads": 12,
+  "n_layers": 6,
+  "pad_token_id": 0,
+  "problem_type": "single_label_classification",
+  "qa_dropout": 0.1,
+  "seq_classif_dropout": 0.2,
+  "sinusoidal_pos_embds": false,
+  "tie_weights_": true,
+  "torch_dtype": "float32",
+  "transformers_version": "4.29.2",
+  "vocab_size": 30522
+}

pytorch_model.bin

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+version https://git-lfs.github.com/spec/v1
+oid sha256:da5e75937d95103f87e121edcb52a71904c34e5609d78eb499626aa0c139de90
+size 268049325