sync 91d990483a17
Browse files- README.md +14 -10
- build/webgpu/bench.json +0 -1
- build/webgpu/depth-to-space-nchw-coarsened4.wgsl.jinja +14 -17
- build/webgpu/manifest.json +69 -94
- build/webgpu/metadata.json +15 -8
- build/webgpu/space-depth-permute.wgsl.jinja +27 -30
- build/webgpu/test.json +6 -7
README.md
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@@ -18,15 +18,15 @@ See the [ONNX `DepthToSpace` spec](https://onnx.ai/onnx/operators/onnx__DepthToS
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## Inputs
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| Name |
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| --- | --- | --- | --- | --- | --- |
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| `input` | `
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## Outputs
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| Name |
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| --- | --- | --- | --- | --- | --- |
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| `output` | `
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## Attributes
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@@ -34,8 +34,8 @@ Attributes and default values (overridable per request):
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| Attribute | Default | Description |
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| --- | --- | --- |
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| `mode` | `"DCR"` | Element ordering within each block: `DCR`, the default depth-column-row order, or `CRD`, the column-row-depth order. |
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| `blocksize` | — | Side length of the spatial blocks; input channels are divided by `blocksize * blocksize`. |
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## Type constraints
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@@ -45,7 +45,7 @@ Attributes and default values (overridable per request):
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## Files
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- [`metadata.json`](build/webgpu/metadata.json) — kernel metadata (id, digests, provenance)
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- [`manifest.json`](build/webgpu/manifest.json) — the op contract (source of truth)
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- [`test.json`](build/webgpu/test.json) — correctness cases
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- [`bench.json`](build/webgpu/bench.json) — benchmark + tuning cases
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@@ -54,10 +54,14 @@ Attributes and default values (overridable per request):
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## Use with `@huggingface/kernels`
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The `version: 1` option selects the published kernel contract; it is independent of any operator opset, contrib `since_version`, or model version.
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Replace each `*Data` placeholder with a typed array containing the corresponding input data.
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## Inputs
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| Name | Logical dtype | Rank | Shape | Description | Presence |
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| --- | --- | --- | --- | --- | --- |
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| `input` | `T` | `4` | — | 4-D input tensor of shape `[N, C, H, W]`. | required |
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## Outputs
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| Name | Logical dtype | Rank | Shape | Description | Presence |
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| --- | --- | --- | --- | --- | --- |
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| `output` | `T` | `4` | derived | 4-D output tensor of shape `[N, C/(blocksize*blocksize), H*blocksize, W*blocksize]`. | required |
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## Attributes
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| Attribute | Default | Description |
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| --- | --- | --- |
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| `blocksize` | — | Side length of the spatial blocks; input channels are divided by `blocksize * blocksize`. |
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| `mode` | `"DCR"` | Element ordering within each block: `DCR`, the default depth-column-row order, or `CRD`, the column-row-depth order. |
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## Type constraints
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## Files
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- [`metadata.json`](build/webgpu/metadata.json) — kernel metadata (id, digests, per-variant templates, provenance)
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- [`manifest.json`](build/webgpu/manifest.json) — the op contract (source of truth)
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- [`test.json`](build/webgpu/test.json) — correctness cases
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- [`bench.json`](build/webgpu/bench.json) — benchmark + tuning cases
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## Use with `@huggingface/kernels`
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```sh
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npm install --save-exact @huggingface/kernels@0.0.1-preview.2
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```
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Required output shapes and logical data types are inferred from the supplied inputs and attributes; result tensors are allocated automatically.
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The `version: 1` option selects the published kernel contract; it is independent of any operator opset, contrib `since_version`, or model version.
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It follows the `v1` branch as fixes land. To pin exact artifact bytes, pass a 40-character commit `revision` instead of `version`.
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Replace each `*Data` placeholder with a typed array containing the corresponding input data.
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build/webgpu/bench.json
CHANGED
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@@ -1,5 +1,4 @@
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{
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"op": "ai.onnx.DepthToSpace",
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"cases": [
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{
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"name": "nchw_1x256x64x64",
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{
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"cases": [
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{
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"name": "nchw_1x256x64x64",
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build/webgpu/depth-to-space-nchw-coarsened4.wgsl.jinja
CHANGED
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@@ -1,26 +1,23 @@
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{% if usesF16 %}
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enable f16;
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{% endif %}
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{{ env.wgsl.resourceDeclarations }}
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// Four adjacent output columns share N/C/H decoding and the block-row lookup.
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// Keeping scalar bindings makes this valid for odd output widths; only the last
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// group in each row is predicated.
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//
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const GROUPS: u32 = {{
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const OUT_W_GROUPS: u32 = max(1u, {{
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const OUT_W: u32 = max(1u, {{
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const OUT_H: u32 = max(1u, {{
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const OUT_C: u32 = max(1u, {{
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const IN_C: u32 = {{
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const IN_H: u32 = {{
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const IN_W: u32 = {{
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const BS: u32 = {{
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const WG: u32 = {{ tunables.WORKGROUP_SIZE }}u;
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@compute @workgroup_size({{ tunables.WORKGROUP_SIZE }})
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-
fn main(@builtin(global_invocation_id) gid: vec3<u32>
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let q = gid.x + gid.y *
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if (q >= GROUPS) { return; }
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let owBase = (q % OUT_W_GROUPS) * 4u;
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@@ -38,7 +35,7 @@ fn main(@builtin(global_invocation_id) gid: vec3<u32>, @builtin(num_workgroups)
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if (ow < OUT_W) {
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let bw = ow % BS;
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let iw = ow / BS;
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{% if
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let ic = (oc * BS + bh) * BS + bw;
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{% else %}
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let ic = (bh * BS + bw) * OUT_C + oc;
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{{ env.wgsl.resourceDeclarations }}
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// Four adjacent output columns share N/C/H decoding and the block-row lookup.
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// Keeping scalar bindings makes this valid for odd output widths; only the last
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// group in each row is predicated. Every division and modulo operation uses a
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// static dimension as its divisor.
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const GROUPS: u32 = {{ groups }}u;
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const OUT_W_GROUPS: u32 = max(1u, {{ outWGroups }}u);
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const OUT_W: u32 = max(1u, {{ outW }}u);
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const OUT_H: u32 = max(1u, {{ outH }}u);
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const OUT_C: u32 = max(1u, {{ outC }}u);
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const IN_C: u32 = {{ inC }}u;
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const IN_H: u32 = {{ inH }}u;
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const IN_W: u32 = {{ inW }}u;
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const BS: u32 = {{ blocksize }}u;
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const WG: u32 = {{ tunables.WORKGROUP_SIZE }}u;
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@compute @workgroup_size({{ tunables.WORKGROUP_SIZE }})
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fn main(@builtin(global_invocation_id) gid: vec3<u32>) {
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let q = gid.x + gid.y * {{ DISPATCH_FOLD_WIDTH }}u * WG;
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if (q >= GROUPS) { return; }
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let owBase = (q % OUT_W_GROUPS) * 4u;
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if (ow < OUT_W) {
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let bw = ow % BS;
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let iw = ow / BS;
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{% if modeSpec == "CRD" %}
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let ic = (oc * BS + bh) * BS + bw;
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{% else %}
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let ic = (bh * BS + bw) * OUT_C + oc;
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build/webgpu/manifest.json
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@@ -2,141 +2,116 @@
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"domain": "ai.onnx",
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"name": "DepthToSpace",
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"sinceVersion": 13,
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"
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"
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{
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"role": "output",
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"dtype": "T",
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"rank": 4,
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"description": "4-D output tensor of shape `[N, C/(blocksize*blocksize), H*blocksize, W*blocksize]`.",
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"shape": ["dim(shapes.input, 0)", "dim(shapes.input, 1) / (attrs.blocksize * attrs.blocksize)", "dim(shapes.input, 2) * attrs.blocksize", "dim(shapes.input, 3) * attrs.blocksize"]
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}
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],
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"attributes": { "mode": "DCR" },
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"attributeDescriptions": {
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"blocksize": "Side length of the spatial blocks; input channels are divided by `blocksize * blocksize`.",
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"mode": "Element ordering within each block: `DCR`, the default depth-column-row order, or `CRD`, the column-row-depth order."
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},
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"attributeConstraints": { "blocksize": { "required": true }, "mode": { "values": ["DCR", "CRD"] } },
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"typeConstraints": { "T": ["float32", "float16", "int32", "int16", "int8", "uint32", "uint8", "bool"] },
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"
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"input": { "kind": "tensor", "semantic": "input", "role": "input" },
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"output": { "kind": "tensor", "semantic": "output", "role": "output" }
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},
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"tunables": { "WORKGROUP_SIZE": 256 },
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"derive": {
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"shapeContract": "attrs.blocksize > 0 and ranks.input == 4 and ranks.output == 4 and dim(shapes.output, 0) == dim(shapes.input, 0) and dim(shapes.output, 1) * attrs.blocksize * attrs.blocksize == dim(shapes.input, 1) and dim(shapes.output, 2) == dim(shapes.input, 2) * attrs.blocksize and dim(shapes.output, 3) == dim(shapes.input, 3) * attrs.blocksize and f16Ok(dtypes.T)"
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-
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"constants": { "scalar": "dtypes.T", "usesF16": "dtypes.T == \"f16\"" },
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"bindingSets": {
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"io": [
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{
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"name": "input",
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"arg": "input",
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"semantic": "input",
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"buffer": { "type": "read-only-storage" },
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"elementType": "$scalar"
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},
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{
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"name": "output",
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"arg": "output",
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"semantic": "output",
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"buffer": { "type": "storage" },
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"elementType": "$outputElement"
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}
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]
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},
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"variants": [
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{
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"id": "nchw_vec4",
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"priority": 20,
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"when": ["
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"
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"passes": [
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{
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"id": "main",
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"name": "DepthToSpace",
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"
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"
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"inW": "dim(shapes.input, 3)"
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}
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},
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"bindings": "
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"dispatch": {
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}
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]
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},
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{
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"id": "nchw_const",
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"priority": 10,
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"
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"constants": { "outputElement": "dtypes.T" },
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"passes": [
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{
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"id": "main",
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"name": "DepthToSpace",
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"
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"
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"inW": "dim(shapes.input, 3)"
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}
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},
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"bindings": "
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"dispatch": {
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}
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]
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},
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{
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"id": "nchw_coarsened4",
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"priority": 15,
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"when": ["
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"
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"passes": [
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{
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"id": "main",
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"name": "DepthToSpace.Coarsened4",
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"
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"
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"inW": "dim(shapes.input, 3)"
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}
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},
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"bindings": "
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"dispatch": {
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"
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"
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}
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}
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]
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"domain": "ai.onnx",
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"name": "DepthToSpace",
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"sinceVersion": 13,
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+
"inputs": { "input": { "dtype": "T", "rank": 4 } },
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"outputs": {
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"output": {
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"dtype": "T",
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"rank": 4,
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"shape": ["dim(shapes.input, 0)", "dim(shapes.input, 1) / (attrs.blocksize * attrs.blocksize)", "dim(shapes.input, 2) * attrs.blocksize", "dim(shapes.input, 3) * attrs.blocksize"]
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}
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},
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+
"attributes": { "mode": { "default": "DCR" }, "blocksize": {} },
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"attributeConstraints": { "blocksize": { "required": true }, "mode": { "values": ["DCR", "CRD"] } },
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"typeConstraints": { "T": ["float32", "float16", "int32", "int16", "int8", "uint32", "uint8", "bool"] },
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+
"tunables": { "WORKGROUP_SIZE": { "default": 256 } },
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"derive": {
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+
"shapeContract": "attrs.blocksize > 0 and ranks.input == 4 and ranks.output == 4 and dim(shapes.output, 0) == dim(shapes.input, 0) and dim(shapes.output, 1) * attrs.blocksize * attrs.blocksize == dim(shapes.input, 1) and dim(shapes.output, 2) == dim(shapes.input, 2) * attrs.blocksize and dim(shapes.output, 3) == dim(shapes.input, 3) * attrs.blocksize and f16Ok(dtypes.T)",
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"scalar": "dtypes.T"
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},
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"when": ["shapeContract"],
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"bindings": { "output": { "buffer": "storage", "elementType": "$outputElement" } },
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"variants": [
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{
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| 25 |
"id": "nchw_vec4",
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"priority": 20,
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| 27 |
+
"when": ["dim(shapes.output, 3) % 4 == 0"],
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| 28 |
+
"derive": { "outputElement": "\"vec4<\" ~ dtypes.T ~ \">\"", "vectorScalar": "\"vec4<\" ~ dtypes.T ~ \">\"" },
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"passes": [
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| 30 |
{
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| 31 |
"id": "main",
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"name": "DepthToSpace",
|
| 33 |
+
"shader": "space-depth-permute.wgsl.jinja",
|
| 34 |
+
"derive": {
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| 35 |
+
"direction": "\"depthToSpace\"",
|
| 36 |
+
"modeSpec": "attrs.mode",
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| 37 |
+
"vectorizedSpec": true,
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| 38 |
+
"blocksize": "attrs.blocksize",
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| 39 |
+
"count": "numel(shapes.output) / 4",
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| 40 |
+
"outWUnits": "dim(shapes.output, 3) / 4",
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| 41 |
+
"outH": "dim(shapes.output, 2)",
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| 42 |
+
"outC": "dim(shapes.output, 1)",
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"inC": "dim(shapes.input, 1)",
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"inH": "dim(shapes.input, 2)",
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"inW": "dim(shapes.input, 3)"
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},
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"bindings": ["input", "output"],
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+
"dispatch": {
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+
"x": "min(ceilDiv((numel(shapes.output) / 4), (tunables.WORKGROUP_SIZE)), 65535)",
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| 50 |
+
"y": "ceilDiv(ceilDiv((numel(shapes.output) / 4), (tunables.WORKGROUP_SIZE)), 65535)",
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+
"z": 1
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+
}
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}
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]
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},
|
| 56 |
{
|
| 57 |
"id": "nchw_const",
|
| 58 |
"priority": 10,
|
| 59 |
+
"derive": { "outputElement": "dtypes.T" },
|
|
|
|
| 60 |
"passes": [
|
| 61 |
{
|
| 62 |
"id": "main",
|
| 63 |
"name": "DepthToSpace",
|
| 64 |
+
"shader": "space-depth-permute.wgsl.jinja",
|
| 65 |
+
"derive": {
|
| 66 |
+
"direction": "\"depthToSpace\"",
|
| 67 |
+
"modeSpec": "attrs.mode",
|
| 68 |
+
"vectorizedSpec": false,
|
| 69 |
+
"blocksize": "attrs.blocksize",
|
| 70 |
+
"count": "numel(shapes.output)",
|
| 71 |
+
"outWUnits": "dim(shapes.output, 3)",
|
| 72 |
+
"outC": "dim(shapes.output, 1)",
|
| 73 |
+
"outH": "dim(shapes.output, 2)",
|
| 74 |
+
"outW": "dim(shapes.output, 3)",
|
| 75 |
+
"inC": "dim(shapes.input, 1)",
|
| 76 |
+
"inH": "dim(shapes.input, 2)",
|
| 77 |
+
"inW": "dim(shapes.input, 3)"
|
|
|
|
|
|
|
| 78 |
},
|
| 79 |
+
"bindings": ["input", "output"],
|
| 80 |
+
"dispatch": {
|
| 81 |
+
"x": "min(ceilDiv((numel(shapes.output)), (tunables.WORKGROUP_SIZE)), 65535)",
|
| 82 |
+
"y": "ceilDiv(ceilDiv((numel(shapes.output)), (tunables.WORKGROUP_SIZE)), 65535)",
|
| 83 |
+
"z": 1
|
| 84 |
+
}
|
| 85 |
}
|
| 86 |
]
|
| 87 |
},
|
| 88 |
{
|
| 89 |
"id": "nchw_coarsened4",
|
| 90 |
"priority": 15,
|
| 91 |
+
"when": ["dim(shapes.output, 3) % 4 != 0", "numel(shapes.output) >= 4096"],
|
| 92 |
+
"derive": { "outputElement": "dtypes.T" },
|
| 93 |
"passes": [
|
| 94 |
{
|
| 95 |
"id": "main",
|
| 96 |
"name": "DepthToSpace.Coarsened4",
|
| 97 |
+
"shader": "depth-to-space-nchw-coarsened4.wgsl.jinja",
|
| 98 |
+
"derive": {
|
| 99 |
+
"modeSpec": "attrs.mode",
|
| 100 |
+
"blocksize": "attrs.blocksize",
|
| 101 |
+
"groups": "dim(shapes.output, 0) * dim(shapes.output, 1) * dim(shapes.output, 2) * ceil(dim(shapes.output, 3) / 4)",
|
| 102 |
+
"outWGroups": "ceil(dim(shapes.output, 3) / 4)",
|
| 103 |
+
"outC": "dim(shapes.output, 1)",
|
| 104 |
+
"outH": "dim(shapes.output, 2)",
|
| 105 |
+
"outW": "dim(shapes.output, 3)",
|
| 106 |
+
"inC": "dim(shapes.input, 1)",
|
| 107 |
+
"inH": "dim(shapes.input, 2)",
|
| 108 |
+
"inW": "dim(shapes.input, 3)"
|
|
|
|
|
|
|
| 109 |
},
|
| 110 |
+
"bindings": ["input", "output"],
|
| 111 |
"dispatch": {
|
| 112 |
+
"x": "min(ceilDiv((dim(shapes.output, 0) * dim(shapes.output, 1) * dim(shapes.output, 2) * ceil(dim(shapes.output, 3) / 4)), (tunables.WORKGROUP_SIZE)), 65535)",
|
| 113 |
+
"y": "ceilDiv(ceilDiv((dim(shapes.output, 0) * dim(shapes.output, 1) * dim(shapes.output, 2) * ceil(dim(shapes.output, 3) / 4)), (tunables.WORKGROUP_SIZE)), 65535)",
|
| 114 |
+
"z": 1
|
| 115 |
}
|
| 116 |
}
|
| 117 |
]
|
build/webgpu/metadata.json
CHANGED
|
@@ -1,19 +1,26 @@
|
|
| 1 |
{
|
| 2 |
"name": "ai.onnx.DepthToSpace",
|
| 3 |
-
"id": "
|
| 4 |
"version": 1,
|
| 5 |
"license": "Apache-2.0",
|
| 6 |
"backend": { "type": "webgpu" },
|
| 7 |
"digest": {
|
| 8 |
"algorithm": "sha256",
|
| 9 |
"files": {
|
| 10 |
-
"bench.json": "
|
| 11 |
-
"depth-to-space-nchw-coarsened4.wgsl.jinja": "
|
| 12 |
-
"manifest.json": "
|
| 13 |
-
"space-depth-permute.wgsl.jinja": "
|
| 14 |
-
"test.json": "
|
| 15 |
}
|
| 16 |
},
|
| 17 |
-
"provenance": { "kernel": { "sha": "
|
| 18 |
-
"webgpu": {
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 19 |
}
|
|
|
|
| 1 |
{
|
| 2 |
"name": "ai.onnx.DepthToSpace",
|
| 3 |
+
"id": "_ai_onnx_depthtospace_webgpu_af18dda",
|
| 4 |
"version": 1,
|
| 5 |
"license": "Apache-2.0",
|
| 6 |
"backend": { "type": "webgpu" },
|
| 7 |
"digest": {
|
| 8 |
"algorithm": "sha256",
|
| 9 |
"files": {
|
| 10 |
+
"bench.json": "JU/Zd5udt4ll47K2EnVjXxjt0sEh9KmpBf5fZnZrXFY=",
|
| 11 |
+
"depth-to-space-nchw-coarsened4.wgsl.jinja": "4xGeu/kV7B8e2wY47sCv1CFLAhW7NbhUkNFAO8N01jw=",
|
| 12 |
+
"manifest.json": "4syDCQ7+CYWnOP8y3nQeAL0uF3R0PuXa2WGfqCUwI5I=",
|
| 13 |
+
"space-depth-permute.wgsl.jinja": "AdqL6I5mdEY/Q+Pd8AMR7O4/IasCj9BhRd+8QDccF5A=",
|
| 14 |
+
"test.json": "hs7y38XH3BuXDsaABYqenTgiC4pdBPPan6x4uUc0EU0="
|
| 15 |
}
|
| 16 |
},
|
| 17 |
+
"provenance": { "kernel": { "sha": "91d990483a174128daf7673f3f37a7c890493ae1", "dirty": false } },
|
| 18 |
+
"webgpu": {
|
| 19 |
+
"manifestSpec": "2.0",
|
| 20 |
+
"variants": {
|
| 21 |
+
"nchw_vec4": ["space-depth-permute.wgsl.jinja"],
|
| 22 |
+
"nchw_const": ["space-depth-permute.wgsl.jinja"],
|
| 23 |
+
"nchw_coarsened4": ["depth-to-space-nchw-coarsened4.wgsl.jinja"]
|
| 24 |
+
}
|
| 25 |
+
}
|
| 26 |
}
|
build/webgpu/space-depth-permute.wgsl.jinja
CHANGED
|
@@ -1,55 +1,52 @@
|
|
| 1 |
{% macro flat_index_2d(name="i", bound="params.count", guardInline=false, note="dispatch-limit") %}
|
| 2 |
{% if note == "dispatch-limit" %}
|
| 3 |
-
// 2D-folded flat index: gid.y carries the high bits past the
|
| 4 |
-
//
|
| 5 |
{% elif note == "limit" %}
|
| 6 |
-
// 2D-folded flat index: gid.y carries the high bits past the
|
| 7 |
-
//
|
| 8 |
{% elif note == "device-axis" %}
|
| 9 |
-
// The flat dispatch is folded across x/y at
|
| 10 |
-
//
|
| 11 |
{% elif note == "vec4-limit" %}
|
| 12 |
-
// 2D-folded flat vec4 index: gid.y carries the high bits past the
|
| 13 |
-
//
|
| 14 |
{% elif note == "element-limit" %}
|
| 15 |
// 2D-folded flat element index: gid.y carries the high bits past the
|
| 16 |
-
//
|
| 17 |
{% elif note == "dispatch" %}
|
| 18 |
-
// 2D-folded flat index: gid.y carries the high bits past the
|
| 19 |
-
//
|
| 20 |
{% endif %}
|
| 21 |
{% if bound == "" %}
|
| 22 |
-
let {{ name }} = gid.x + gid.y *
|
| 23 |
{%- elif guardInline %}
|
| 24 |
-
let {{ name }} = gid.x + gid.y *
|
| 25 |
if ({{ name }} >= {{ bound }}) { return; }
|
| 26 |
{%- else %}
|
| 27 |
-
let {{ name }} = gid.x + gid.y *
|
| 28 |
if ({{ name }} >= {{ bound }}) {
|
| 29 |
return;
|
| 30 |
}
|
| 31 |
{%- endif %}
|
| 32 |
{% endmacro %}
|
| 33 |
|
| 34 |
-
{% if usesF16 %}
|
| 35 |
-
enable f16;
|
| 36 |
-
{% endif %}
|
| 37 |
{{ env.wgsl.resourceDeclarations }}
|
| 38 |
|
| 39 |
// Specializing all geometry lets division and modulo lower to constant
|
| 40 |
// multiply-high/shift sequences. max(1) keeps zero-sized tensors compilable;
|
| 41 |
// they dispatch no work.
|
| 42 |
-
const COUNT: u32 = {{
|
| 43 |
-
const OUT_W_UNITS: u32 = max(1u, {{
|
| 44 |
-
const OUT_H: u32 = max(1u, {{
|
| 45 |
-
const OUT_C: u32 = max(1u, {{
|
| 46 |
-
const IN_C: u32 = max(1u, {{
|
| 47 |
-
const IN_H: u32 = {{
|
| 48 |
-
const IN_W: u32 = {{
|
| 49 |
-
const BLOCK_SIZE: u32 = {{
|
| 50 |
|
| 51 |
@compute @workgroup_size({{ tunables.WORKGROUP_SIZE }})
|
| 52 |
-
fn main(@builtin(global_invocation_id) gid: vec3<u32>
|
| 53 |
{{ flat_index_2d("out_unit", "COUNT", note="") }}
|
| 54 |
|
| 55 |
let ow_unit = out_unit % OUT_W_UNITS;
|
|
@@ -58,14 +55,14 @@ fn main(@builtin(global_invocation_id) gid: vec3<u32>, @builtin(num_workgroups)
|
|
| 58 |
remaining /= OUT_H;
|
| 59 |
let oc = remaining % OUT_C;
|
| 60 |
let n = remaining / OUT_C;
|
| 61 |
-
let ow_base = ow_unit * {{ 4 if
|
| 62 |
-
{% for lane in range(4 if
|
| 63 |
let ow{{ lane }} = ow_base + {{ lane }}u;
|
| 64 |
let bh{{ lane }} = oh % BLOCK_SIZE;
|
| 65 |
let bw{{ lane }} = ow{{ lane }} % BLOCK_SIZE;
|
| 66 |
let ih{{ lane }} = oh / BLOCK_SIZE;
|
| 67 |
let iw{{ lane }} = ow{{ lane }} / BLOCK_SIZE;
|
| 68 |
-
{% if
|
| 69 |
let ic{{ lane }} = (oc * BLOCK_SIZE + bh{{ lane }}) * BLOCK_SIZE + bw{{ lane }};
|
| 70 |
{% else %}
|
| 71 |
let ic{{ lane }} = (bh{{ lane }} * BLOCK_SIZE + bw{{ lane }}) * OUT_C + oc;
|
|
@@ -73,7 +70,7 @@ fn main(@builtin(global_invocation_id) gid: vec3<u32>, @builtin(num_workgroups)
|
|
| 73 |
let value{{ lane }} = input[((n * IN_C + ic{{ lane }}) * IN_H + ih{{ lane }}) * IN_W + iw{{ lane }}];
|
| 74 |
{% endfor %}
|
| 75 |
|
| 76 |
-
{% if
|
| 77 |
output[out_unit] = {{ vectorScalar }}(value0, value1, value2, value3);
|
| 78 |
{% else %}
|
| 79 |
output[out_unit] = value0;
|
|
|
|
| 1 |
{% macro flat_index_2d(name="i", bound="params.count", guardInline=false, note="dispatch-limit") %}
|
| 2 |
{% if note == "dispatch-limit" %}
|
| 3 |
+
// 2D-folded flat index: gid.y carries the high bits past the dispatch's
|
| 4 |
+
// per-axis workgroup fold width (outputs > 16.7M elements).
|
| 5 |
{% elif note == "limit" %}
|
| 6 |
+
// 2D-folded flat index: gid.y carries the high bits past the dispatch's
|
| 7 |
+
// per-axis workgroup fold width.
|
| 8 |
{% elif note == "device-axis" %}
|
| 9 |
+
// The flat dispatch is folded across x/y at a fixed per-axis workgroup
|
| 10 |
+
// width; gid.y carries the high portion of the output index.
|
| 11 |
{% elif note == "vec4-limit" %}
|
| 12 |
+
// 2D-folded flat vec4 index: gid.y carries the high bits past the dispatch's
|
| 13 |
+
// per-axis workgroup fold width (the dispatch caps x and spills into y).
|
| 14 |
{% elif note == "element-limit" %}
|
| 15 |
// 2D-folded flat element index: gid.y carries the high bits past the
|
| 16 |
+
// dispatch's per-axis workgroup fold width.
|
| 17 |
{% elif note == "dispatch" %}
|
| 18 |
+
// 2D-folded flat index: gid.y carries the high bits past the dispatch's
|
| 19 |
+
// per-axis workgroup fold width.
|
| 20 |
{% endif %}
|
| 21 |
{% if bound == "" %}
|
| 22 |
+
let {{ name }} = gid.x + gid.y * {{ DISPATCH_FOLD_WIDTH }}u * {{ tunables.WORKGROUP_SIZE }}u;
|
| 23 |
{%- elif guardInline %}
|
| 24 |
+
let {{ name }} = gid.x + gid.y * {{ DISPATCH_FOLD_WIDTH }}u * {{ tunables.WORKGROUP_SIZE }}u;
|
| 25 |
if ({{ name }} >= {{ bound }}) { return; }
|
| 26 |
{%- else %}
|
| 27 |
+
let {{ name }} = gid.x + gid.y * {{ DISPATCH_FOLD_WIDTH }}u * {{ tunables.WORKGROUP_SIZE }}u;
|
| 28 |
if ({{ name }} >= {{ bound }}) {
|
| 29 |
return;
|
| 30 |
}
|
| 31 |
{%- endif %}
|
| 32 |
{% endmacro %}
|
| 33 |
|
|
|
|
|
|
|
|
|
|
| 34 |
{{ env.wgsl.resourceDeclarations }}
|
| 35 |
|
| 36 |
// Specializing all geometry lets division and modulo lower to constant
|
| 37 |
// multiply-high/shift sequences. max(1) keeps zero-sized tensors compilable;
|
| 38 |
// they dispatch no work.
|
| 39 |
+
const COUNT: u32 = {{ count }}u;
|
| 40 |
+
const OUT_W_UNITS: u32 = max(1u, {{ outWUnits }}u);
|
| 41 |
+
const OUT_H: u32 = max(1u, {{ outH }}u);
|
| 42 |
+
const OUT_C: u32 = max(1u, {{ outC }}u);
|
| 43 |
+
const IN_C: u32 = max(1u, {{ inC }}u);
|
| 44 |
+
const IN_H: u32 = {{ inH }}u;
|
| 45 |
+
const IN_W: u32 = {{ inW }}u;
|
| 46 |
+
const BLOCK_SIZE: u32 = {{ blocksize }}u;
|
| 47 |
|
| 48 |
@compute @workgroup_size({{ tunables.WORKGROUP_SIZE }})
|
| 49 |
+
fn main(@builtin(global_invocation_id) gid: vec3<u32>) {
|
| 50 |
{{ flat_index_2d("out_unit", "COUNT", note="") }}
|
| 51 |
|
| 52 |
let ow_unit = out_unit % OUT_W_UNITS;
|
|
|
|
| 55 |
remaining /= OUT_H;
|
| 56 |
let oc = remaining % OUT_C;
|
| 57 |
let n = remaining / OUT_C;
|
| 58 |
+
let ow_base = ow_unit * {{ 4 if vectorizedSpec else 1 }}u;
|
| 59 |
+
{% for lane in range(4 if vectorizedSpec else 1) %}
|
| 60 |
let ow{{ lane }} = ow_base + {{ lane }}u;
|
| 61 |
let bh{{ lane }} = oh % BLOCK_SIZE;
|
| 62 |
let bw{{ lane }} = ow{{ lane }} % BLOCK_SIZE;
|
| 63 |
let ih{{ lane }} = oh / BLOCK_SIZE;
|
| 64 |
let iw{{ lane }} = ow{{ lane }} / BLOCK_SIZE;
|
| 65 |
+
{% if modeSpec == "CRD" %}
|
| 66 |
let ic{{ lane }} = (oc * BLOCK_SIZE + bh{{ lane }}) * BLOCK_SIZE + bw{{ lane }};
|
| 67 |
{% else %}
|
| 68 |
let ic{{ lane }} = (bh{{ lane }} * BLOCK_SIZE + bw{{ lane }}) * OUT_C + oc;
|
|
|
|
| 70 |
let value{{ lane }} = input[((n * IN_C + ic{{ lane }}) * IN_H + ih{{ lane }}) * IN_W + iw{{ lane }}];
|
| 71 |
{% endfor %}
|
| 72 |
|
| 73 |
+
{% if vectorizedSpec %}
|
| 74 |
output[out_unit] = {{ vectorScalar }}(value0, value1, value2, value3);
|
| 75 |
{% else %}
|
| 76 |
output[out_unit] = value0;
|
build/webgpu/test.json
CHANGED
|
@@ -1,5 +1,4 @@
|
|
| 1 |
{
|
| 2 |
-
"op": "ai.onnx.DepthToSpace",
|
| 3 |
"fixtureArrays": {
|
| 4 |
"dcr_input_input": [0, 1, 2, 3, 10, 11, 12, 13, 20, 21, 22, 23, 30, 31, 32, 33],
|
| 5 |
"onnx_backend_dcr_1x8x2x3_input_input": [0, 1, 2, 3, 4, 5, 9, 10, 11, 12, 13, 14, 18, 19, 20, 21, 22, 23, 27, 28, 29, 30, 31, 32, 36, 37, 38, 39, 40, 41, 45, 46, 47, 48, 49, 50, 54, 55, 56, 57, 58, 59, 63, 64, 65, 66, 67, 68],
|
|
@@ -69,7 +68,7 @@
|
|
| 69 |
{
|
| 70 |
"name": "dcr_high_channel_vec4_1x256x4x4",
|
| 71 |
"provenance": {
|
| 72 |
-
"notes": "
|
| 73 |
},
|
| 74 |
"attrs": { "blocksize": 2, "mode": "DCR" },
|
| 75 |
"inputs": {
|
|
@@ -84,7 +83,7 @@
|
|
| 84 |
{
|
| 85 |
"name": "crd_high_channel_vec4_1x256x4x4",
|
| 86 |
"provenance": {
|
| 87 |
-
"notes": "
|
| 88 |
},
|
| 89 |
"attrs": { "blocksize": 2, "mode": "CRD" },
|
| 90 |
"inputs": {
|
|
@@ -195,7 +194,7 @@
|
|
| 195 |
"provenance": {
|
| 196 |
"source": "onnxruntime/test/providers/cpu/tensor/space_depth_ops_test.cc",
|
| 197 |
"test": "TensorOpTest.DepthToSpaceTest_3<uint8_t>",
|
| 198 |
-
"notes": "
|
| 199 |
},
|
| 200 |
"inputs": {
|
| 201 |
"input": {
|
|
@@ -353,7 +352,7 @@
|
|
| 353 |
"provenance": {
|
| 354 |
"source": "onnxruntime/test/providers/cpu/tensor/space_depth_ops_test.cc",
|
| 355 |
"test": "TensorOpTest.DepthToSpaceTest_4",
|
| 356 |
-
"notes": "
|
| 357 |
},
|
| 358 |
"inputs": {
|
| 359 |
"input": {
|
|
@@ -377,7 +376,7 @@
|
|
| 377 |
"provenance": {
|
| 378 |
"source": "onnxruntime/test/providers/cpu/tensor/space_depth_ops_test.cc",
|
| 379 |
"test": "TensorOpTest.DepthToSpaceTest_5",
|
| 380 |
-
"notes": "
|
| 381 |
},
|
| 382 |
"inputs": {
|
| 383 |
"input": {
|
|
@@ -497,7 +496,7 @@
|
|
| 497 |
"name": "ort_standard_int16_dcr_extremes",
|
| 498 |
"provenance": {
|
| 499 |
"source": "onnx/docs/Operators.md#DepthToSpace",
|
| 500 |
-
"notes": "
|
| 501 |
},
|
| 502 |
"attrs": { "blocksize": 2, "mode": "DCR" },
|
| 503 |
"inputs": {
|
|
|
|
| 1 |
{
|
|
|
|
| 2 |
"fixtureArrays": {
|
| 3 |
"dcr_input_input": [0, 1, 2, 3, 10, 11, 12, 13, 20, 21, 22, 23, 30, 31, 32, 33],
|
| 4 |
"onnx_backend_dcr_1x8x2x3_input_input": [0, 1, 2, 3, 4, 5, 9, 10, 11, 12, 13, 14, 18, 19, 20, 21, 22, 23, 27, 28, 29, 30, 31, 32, 36, 37, 38, 39, 40, 41, 45, 46, 47, 48, 49, 50, 54, 55, 56, 57, 58, 59, 63, 64, 65, 66, 67, 68],
|
|
|
|
| 68 |
{
|
| 69 |
"name": "dcr_high_channel_vec4_1x256x4x4",
|
| 70 |
"provenance": {
|
| 71 |
+
"notes": "A compact high-channel DCR input exercises the vec4 channel-heavy mapping without benchmark-scale spatial dimensions."
|
| 72 |
},
|
| 73 |
"attrs": { "blocksize": 2, "mode": "DCR" },
|
| 74 |
"inputs": {
|
|
|
|
| 83 |
{
|
| 84 |
"name": "crd_high_channel_vec4_1x256x4x4",
|
| 85 |
"provenance": {
|
| 86 |
+
"notes": "A compact high-channel CRD input exercises the vec4 channel-heavy mapping without benchmark-scale spatial dimensions."
|
| 87 |
},
|
| 88 |
"attrs": { "blocksize": 2, "mode": "CRD" },
|
| 89 |
"inputs": {
|
|
|
|
| 194 |
"provenance": {
|
| 195 |
"source": "onnxruntime/test/providers/cpu/tensor/space_depth_ops_test.cc",
|
| 196 |
"test": "TensorOpTest.DepthToSpaceTest_3<uint8_t>",
|
| 197 |
+
"notes": "A compact logical uint8 input exercises the default DCR channel-to-space mapping."
|
| 198 |
},
|
| 199 |
"inputs": {
|
| 200 |
"input": {
|
|
|
|
| 352 |
"provenance": {
|
| 353 |
"source": "onnxruntime/test/providers/cpu/tensor/space_depth_ops_test.cc",
|
| 354 |
"test": "TensorOpTest.DepthToSpaceTest_4",
|
| 355 |
+
"notes": "Logical uint8 values are stored in 32-bit slots while preserving the typed source case."
|
| 356 |
},
|
| 357 |
"inputs": {
|
| 358 |
"input": {
|
|
|
|
| 376 |
"provenance": {
|
| 377 |
"source": "onnxruntime/test/providers/cpu/tensor/space_depth_ops_test.cc",
|
| 378 |
"test": "TensorOpTest.DepthToSpaceTest_5",
|
| 379 |
+
"notes": "Logical uint8 values are stored in 32-bit slots while preserving the typed source case."
|
| 380 |
},
|
| 381 |
"inputs": {
|
| 382 |
"input": {
|
|
|
|
| 496 |
"name": "ort_standard_int16_dcr_extremes",
|
| 497 |
"provenance": {
|
| 498 |
"source": "onnx/docs/Operators.md#DepthToSpace",
|
| 499 |
+
"notes": "Both int16 extrema exercise the package's widened int32 storage while preserving logical signed values."
|
| 500 |
},
|
| 501 |
"attrs": { "blocksize": 2, "mode": "DCR" },
|
| 502 |
"inputs": {
|