Add faster compact NeuralHorner v8 prototype

49.8% smaller checkpoint; two-pass Horner schedule; reusable static feature channels. Public Tiers 1-7: 700/700 locally. Tier 6 MPS: 19.07s vs 27.02s baseline. Full CUDA Tier 1-10 validation remains required.

LICENSE

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+MIT License
+
+Copyright (c) 2026 Robert Sneiderman
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.

README.md

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 ---
 license: mit
+library_name: pytorch
+tags:
+- modular-arithmetic
+- neural-arithmetic
+- bit-serial
+- gru
 ---
+
+# NeuralHorner v8 compact inference experiment
+
+This local derivative tests storage and inference optimizations against the
+published MIT-licensed `TrickyRex/bitserial-modmul-v8` checkpoint. It is not a
+newly trained model. Original model and weights by Robert Sneiderman:
+<https://huggingface.co/TrickyRex/bitserial-modmul-v8>.
+
+Changes:
+
+- checkpoint tensors stored as bfloat16;
+- direct `logit > 0` decisions instead of `sigmoid(logit) > 0.5`;
+- one operand is reduced and the other is streamed directly through the
+  learned multiplication transition, removing one modulus-width pass;
+- static multiplicand/modulus feature channels are allocated once per scan
+  instead of rebuilt at every recurrent step.
+
+The last change is mathematically equivalent for an exact transition, but the
+learned cell is not proven exact. Benchmark equivalence therefore must be
+measured before this is treated as an accuracy-preserving release.
+
+## Local validation
+
+Hardware: Apple GPU through PyTorch MPS. Dataset: the official 100-case public
+benchmark for each tier.
+
+- Tiers 1-7: 700/700 exact.
+- Tier 6 runtime: 19.07 seconds versus 27.02 seconds for the published wrapper
+  (29.4% lower wall-clock in this comparison). The earlier short-schedule
+  version took 20.45-21.31 seconds before static-channel reuse.
+- Tier 6 outputs: 100/100 byte-for-byte identical to the published wrapper.
+- The bfloat16 checkpoint with the original three-pass schedule also produced
+  100/100 outputs identical to the fp32 checkpoint on Tier 6.
+- Official static analysis: clean.
+
+The checkpoint is 948,196 bytes versus 1,887,610 bytes (49.8% smaller). The
+shorter schedule removes exactly one `Leff` recurrent pass: 20% of recurrent
+step calls on public Tiers 3 and 5-10, 14.3% on Tier 4, 25% on Tier 2, and
+33.3% on Tier 1.
+
+## Release gate
+
+Do not claim unchanged Tier 1-10 accuracy yet. The current machine is too slow
+for a practical full-width Tier 8-10 MPS run. Before release, run the official
+1,100-case scorer on CUDA for the three published seeds and require 100% on
+every scored tier, then repeat the held-out 768-case adversarial battery.

RESULTS.md

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+# Optimization results
+
+| Variant | Checkpoint | Schedule | Tier 6 accuracy | Tier 6 time (MPS) |
+|---|---:|---|---:|---:|
+| Published v8 | 1,887,610 B | reduce a + reduce b + multiply | 100/100 | 27.02 s |
+| Compact weights | 948,196 B | reduce a + reduce b + multiply | 100/100, identical outputs | 34.59 s* |
+| Compact + short schedule | 948,196 B | reduce a + multiply by streaming b | 100/100, identical outputs | 20.45-21.31 s |
+| Compact + short schedule + static-channel reuse | 948,196 B | reduce a + multiply by streaming b | 100/100 | 19.07 s |
+
+`*` This single MPS timing is noisy and does not imply bfloat16 storage makes
+inference slower. The compact tensors are loaded back into fp32 parameters;
+storage precision affects artifact size, not the execution dtype.
+
+The short-schedule variant also scored 100/100 on each public Tier 1 through 7
+(700/700 total) and passed the official static checker. Full Tier 8-10 and
+held-out adversarial validation remain release blockers.

manifest.json

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+{
+  "entry_class": "model.BitSerialReducer",
+  "output_base": 2,
+  "framework": "pytorch",
+  "model_description": "Compute-optimized NeuralHorner v8 inference wrapper using the original ~471K-parameter bidirectional two-layer GRU transition. Stores weights in bfloat16, thresholds logits directly, reuses static feature channels, and removes one redundant modular-reduction pass by streaming one original operand directly through the learned Horner multiply transition.",
+  "training_description": "Uses the published TrickyRex/bitserial-modmul-v8 weights (MIT), warm-started and fine-tuned by its author on one-step modular transitions. This derivative changes checkpoint precision and the mathematically equivalent inference schedule; it does not retrain the learned transition."
+}

model.py

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+"""Smaller, lower-compute inference wrapper for NeuralHorner v8.
+
+The learned transition is unchanged.  Compared with the published wrapper:
+
+* checkpoint tensors may be stored in bfloat16 and are restored to float32;
+* logits are thresholded at zero (exactly equivalent to sigmoid(logit) > 0.5);
+* only one operand is reduced before multiplication.  The other operand is
+  streamed directly through the same Horner transition, eliminating a full
+  modulus-width recurrent pass.
+"""
+
+from __future__ import annotations
+
+from pathlib import Path
+
+import torch
+from torch import nn
+
+from modchallenge.interface.base_model import ModularMultiplicationModel
+
+_MASK32 = (1 << 32) - 1
+
+
+def _to_bits_small(vals: torch.Tensor, width: int) -> torch.Tensor:
+    shifts = torch.arange(width - 1, -1, -1, device=vals.device)
+    return (vals[:, None] >> shifts[None, :]) & 1
+
+
+def to_bits_limbs(ints, dev, width: int) -> torch.Tensor:
+    nl = (width + 31) // 32
+    cols = []
+    for k in range(nl - 1, -1, -1):
+        limb = torch.tensor(
+            [(v >> (32 * k)) & _MASK32 for v in ints],
+            dtype=torch.int64,
+            device=dev,
+        )
+        cols.append(_to_bits_small(limb, 32))
+    bits = torch.cat(cols, dim=1)
+    return bits[:, nl * 32 - width:] if width < nl * 32 else bits
+
+
+class Cell(nn.Module):
+    def __init__(self, dmodel: int = 96, hidden: int = 128):
+        super().__init__()
+        self.in_proj = nn.Linear(3, dmodel)
+        self.d_emb = nn.Embedding(2, dmodel)
+        self.gru = nn.GRU(
+            dmodel,
+            hidden,
+            num_layers=2,
+            batch_first=True,
+            bidirectional=True,
+        )
+        self.head = nn.Linear(2 * hidden, 1)
+
+    def forward(self, feat, d):
+        x = self.in_proj(feat) + self.d_emb(d)[:, None, :]
+        h, _ = self.gru(x)
+        return self.head(h).squeeze(-1)
+
+
+def _bits_of(n: int) -> list[int]:
+    if n <= 0:
+        return [0]
+    out: list[int] = []
+    while n > 0:
+        out.append(n & 1)
+        n >>= 1
+    out.reverse()
+    return out
+
+
+class BitSerialReducer(ModularMultiplicationModel):
+    def __init__(self) -> None:
+        self.model: Cell | None = None
+        self.device: torch.device | None = None
+        self.L = 32
+        self._Leff = 32
+
+    def load(self, model_dir: str) -> None:
+        if torch.cuda.is_available():
+            self.device = torch.device("cuda")
+        elif torch.backends.mps.is_available():
+            self.device = torch.device("mps")
+        else:
+            self.device = torch.device("cpu")
+        ckpt = torch.load(
+            Path(model_dir) / "weights.pt",
+            map_location="cpu",
+            weights_only=True,
+        )
+        self.L = int(ckpt.get("L", 32))
+        self.model = Cell(**ckpt.get("config", {}))
+        # load_state_dict casts compact bf16 checkpoint tensors back to fp32.
+        self.model.load_state_dict(ckpt["state_dict"])
+        self.model.to(self.device)
+        self.model.eval()
+        self.model.gru.flatten_parameters()
+
+    def preprocess_a(self, a):
+        return _bits_of(int(a))
+
+    def preprocess_b(self, b):
+        return _bits_of(int(b))
+
+    def preprocess_p(self, p):
+        return int(p)
+
+    @torch.inference_mode()
+    def predict_digits(self, a_enc, b_enc, p_enc):
+        return self.predict_digits_batch([(a_enc, b_enc, p_enc)])[0]
+
+    @torch.inference_mode()
+    def predict_digits_batch(self, inputs):
+        L = self.L
+        max_op = 4 * L
+        out: list[list[int]] = [[0] for _ in inputs]
+        idx, a_lists, b_lists, p_vals = [], [], [], []
+        for i, (a_enc, b_enc, p_enc) in enumerate(inputs):
+            p = int(p_enc)
+            a_bits = list(a_enc)
+            b_bits = list(b_enc)
+            if p < 2 or p >= (1 << L) or len(a_bits) > max_op or len(b_bits) > max_op:
+                continue
+            idx.append(i)
+            a_lists.append(a_bits)
+            b_lists.append(b_bits)
+            p_vals.append(p)
+        if not idx:
+            return out
+
+        dev = self.device
+        maxp = max(int(p).bit_length() for p in p_vals)
+        self._Leff = min(self.L, max(32, ((maxp + 31) // 32) * 32))
+        p_bits = to_bits_limbs(p_vals, dev, self._Leff).float()
+
+        # (a*b) mod p = ((a mod p)*b) mod p.  Streaming the original b bits
+        # through the learned Horner cell avoids first reducing b and then
+        # scanning its L-bit residue a second time.
+        ra = self._reduce(a_lists, p_bits, dev)
+        prod = self._scan(b_lists, ra, p_bits, dev)
+        prod_list = prod.long().tolist()
+        for j, i in enumerate(idx):
+            out[i] = [int(x) for x in prod_list[j]]
+        return out
+
+    def max_batch_size(self) -> int:
+        return 256
+
+    def _step(self, s_bits, feat, d):
+        # The multiplicand and modulus channels stay constant for an entire
+        # scan. Reuse their preallocated feature tensor instead of rebuilding
+        # and copying all three channels at every recurrent step.
+        feat[:, :, 0].copy_(s_bits)
+        if self.device is not None and self.device.type == "cuda":
+            with torch.autocast(device_type="cuda", dtype=torch.bfloat16):
+                logits = self.model(feat, d)
+            # Comparing a bf16 value with zero has the same sign decision as
+            # first widening it to fp32, without allocating the fp32 logits.
+            return (logits > 0).float()
+        return (self.model(feat, d) > 0).float()
+
+    def _scan(self, bit_lists, x_bits, p_bits, dev):
+        n = len(bit_lists)
+        width = max(len(bits) for bits in bit_lists)
+        padded = torch.zeros((n, width), dtype=torch.long, device=dev)
+        for row, bits in enumerate(bit_lists):
+            if bits:
+                padded[row, width - len(bits):] = torch.tensor(
+                    bits, dtype=torch.long, device=dev
+                )
+        state = torch.zeros((n, self._Leff), device=dev)
+        feat = torch.empty((n, self._Leff, 3), device=dev)
+        feat[:, :, 1].copy_(x_bits)
+        feat[:, :, 2].copy_(p_bits)
+        for pos in range(width):
+            state = self._step(state, feat, padded[:, pos])
+        return state
+
+    def _reduce(self, bit_lists, p_bits, dev):
+        ones = to_bits_limbs([1] * len(bit_lists), dev, self._Leff).float()
+        return self._scan(bit_lists, ones, p_bits, dev)

weights.pt

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+version https://git-lfs.github.com/spec/v1
+oid sha256:e09c1037ea89f8817db0a488e3179512e829175fd23d313e30b69d422baac16d
+size 948196