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| /----------------------------------------------------------------------------\
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| | yosys -- Yosys Open SYnthesis Suite |
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| | Copyright (C) 2012 - 2026 Claire Xenia Wolf <claire@yosyshq.com> |
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| | Distributed under an ISC-like license, type "license" to see terms |
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| \----------------------------------------------------------------------------/
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| Yosys 0.63+222 (git sha1 a4b6a8c58-dirty, x86_64-w64-mingw32-g++ 13.2.1 -O3)
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|
|
| -- Executing script file `synth.ys' --
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|
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| 1. Executing Verilog-2005 frontend: person_classifier_1p.v
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| Parsing Verilog input from `person_classifier_1p.v' to AST representation.
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| Generating RTLIL representation for module `\person_classifier_1p'.
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| Successfully finished Verilog frontend.
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|
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| 2. Executing HIERARCHY pass (managing design hierarchy).
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|
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| 2.1. Analyzing design hierarchy..
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| Top module: \person_classifier_1p
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|
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| 2.2. Analyzing design hierarchy..
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| Top module: \person_classifier_1p
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| Removed 0 unused modules.
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|
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| 3. Executing PROC pass (convert processes to netlists).
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|
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| 3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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| Cleaned up 0 empty switches.
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|
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| 3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
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| Removed a total of 0 dead cases.
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|
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| 3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
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| Removed 0 redundant assignments.
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| Promoted 0 assignments to connections.
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|
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| 3.4. Executing PROC_INIT pass (extract init attributes).
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|
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| 3.5. Executing PROC_ARST pass (detect async resets in processes).
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|
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| 3.6. Executing PROC_ROM pass (convert switches to ROMs).
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| Converted 0 switches.
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| 3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
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|
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| 3.8. Executing PROC_DLATCH pass (convert process syncs to latches).
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|
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| 3.9. Executing PROC_DFF pass (convert process syncs to FFs).
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|
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| 3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
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| 3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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| Cleaned up 0 empty switches.
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| 3.12. Executing OPT_EXPR pass (perform const folding).
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| Optimizing module person_classifier_1p.
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|
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| 4. Executing OPT pass (performing simple optimizations).
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| 4.1. Executing OPT_EXPR pass (perform const folding).
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| Optimizing module person_classifier_1p.
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|
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| 4.2. Executing OPT_MERGE pass (detect identical cells).
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| Finding identical cells in module `\person_classifier_1p'.
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| Computing hashes of 40 cells of `\person_classifier_1p'.
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| Finding duplicate cells in `\person_classifier_1p'.
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| Removed a total of 0 cells.
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|
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| 4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
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| Running muxtree optimizer on module \person_classifier_1p..
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| Creating internal representation of mux trees.
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| No muxes found in this module.
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| Removed 0 multiplexer ports.
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| 4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
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| Optimizing cells in module \person_classifier_1p.
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| Performed a total of 0 changes.
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| 4.5. Executing OPT_MERGE pass (detect identical cells).
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| Finding identical cells in module `\person_classifier_1p'.
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| Computing hashes of 40 cells of `\person_classifier_1p'.
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| Finding duplicate cells in `\person_classifier_1p'.
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| Removed a total of 0 cells.
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| 4.6. Executing OPT_DFF pass (perform DFF optimizations).
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|
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| 4.7. Executing OPT_CLEAN pass (remove unused cells and wires).
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| Finding unused cells or wires in module \person_classifier_1p..
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| Removed 0 unused cells and 4 unused wires.
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| <suppressed ~1 debug messages>
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| 4.8. Executing OPT_EXPR pass (perform const folding).
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| Optimizing module person_classifier_1p.
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| 4.9. Rerunning OPT passes. (Maybe there is more to do..)
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| 4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
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| Running muxtree optimizer on module \person_classifier_1p..
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| Creating internal representation of mux trees.
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| No muxes found in this module.
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| Removed 0 multiplexer ports.
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| 4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
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| Optimizing cells in module \person_classifier_1p.
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| Performed a total of 0 changes.
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| 4.12. Executing OPT_MERGE pass (detect identical cells).
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| Finding identical cells in module `\person_classifier_1p'.
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| Computing hashes of 40 cells of `\person_classifier_1p'.
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| Finding duplicate cells in `\person_classifier_1p'.
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| Removed a total of 0 cells.
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| 4.13. Executing OPT_DFF pass (perform DFF optimizations).
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| 4.14. Executing OPT_CLEAN pass (remove unused cells and wires).
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| Finding unused cells or wires in module \person_classifier_1p..
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| 4.15. Executing OPT_EXPR pass (perform const folding).
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| Optimizing module person_classifier_1p.
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| 4.16. Finished fast OPT passes. (There is nothing left to do.)
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| 5. Executing FLATTEN pass (flatten design).
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| 6. Executing OPT_CLEAN pass (remove unused cells and wires).
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| Finding unused cells or wires in module \person_classifier_1p..
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| 7. Executing SYNTH pass.
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| 7.1. Executing HIERARCHY pass (managing design hierarchy).
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| 7.1.1. Analyzing design hierarchy..
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| Top module: \person_classifier_1p
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| 7.1.2. Analyzing design hierarchy..
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| Top module: \person_classifier_1p
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| Removed 0 unused modules.
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| 7.2. Executing PROC pass (convert processes to netlists).
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| 7.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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| Cleaned up 0 empty switches.
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| 7.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
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| Removed a total of 0 dead cases.
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| 7.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
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| Removed 0 redundant assignments.
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| Promoted 0 assignments to connections.
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| 7.2.4. Executing PROC_INIT pass (extract init attributes).
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|
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| 7.2.5. Executing PROC_ARST pass (detect async resets in processes).
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| 7.2.6. Executing PROC_ROM pass (convert switches to ROMs).
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| Converted 0 switches.
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| 7.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
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|
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| 7.2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
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|
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| 7.2.9. Executing PROC_DFF pass (convert process syncs to FFs).
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|
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| 7.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
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|
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| 7.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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| Cleaned up 0 empty switches.
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| 7.2.12. Executing OPT_EXPR pass (perform const folding).
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| Optimizing module person_classifier_1p.
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| 7.3. Executing OPT_EXPR pass (perform const folding).
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| Optimizing module person_classifier_1p.
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|
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| 7.4. Executing OPT_CLEAN pass (remove unused cells and wires).
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| Finding unused cells or wires in module \person_classifier_1p..
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| 7.5. Executing CHECK pass (checking for obvious problems).
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| Checking module person_classifier_1p...
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| Found and reported 0 problems.
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| 7.6. Executing OPT pass (performing simple optimizations).
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| 7.6.1. Executing OPT_EXPR pass (perform const folding).
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| Optimizing module person_classifier_1p.
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| 7.6.2. Executing OPT_MERGE pass (detect identical cells).
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| Finding identical cells in module `\person_classifier_1p'.
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| Computing hashes of 40 cells of `\person_classifier_1p'.
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| Finding duplicate cells in `\person_classifier_1p'.
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| Removed a total of 0 cells.
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| 7.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
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| Running muxtree optimizer on module \person_classifier_1p..
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| Creating internal representation of mux trees.
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| No muxes found in this module.
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| Removed 0 multiplexer ports.
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| 7.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
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| Optimizing cells in module \person_classifier_1p.
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| Performed a total of 0 changes.
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| 7.6.5. Executing OPT_MERGE pass (detect identical cells).
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| Finding identical cells in module `\person_classifier_1p'.
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| Computing hashes of 40 cells of `\person_classifier_1p'.
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| Finding duplicate cells in `\person_classifier_1p'.
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| Removed a total of 0 cells.
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| 7.6.6. Executing OPT_DFF pass (perform DFF optimizations).
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|
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| 7.6.7. Executing OPT_CLEAN pass (remove unused cells and wires).
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| Finding unused cells or wires in module \person_classifier_1p..
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|
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| 7.6.8. Executing OPT_EXPR pass (perform const folding).
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| Optimizing module person_classifier_1p.
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| 7.6.9. Finished fast OPT passes. (There is nothing left to do.)
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| 7.7. Executing FSM pass (extract and optimize FSM).
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| 7.7.1. Executing FSM_DETECT pass (finding FSMs in design).
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| 7.7.2. Executing FSM_EXTRACT pass (extracting FSM from design).
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| 7.7.3. Executing FSM_OPT pass (simple optimizations of FSMs).
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|
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| 7.7.4. Executing OPT_CLEAN pass (remove unused cells and wires).
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| Finding unused cells or wires in module \person_classifier_1p..
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| 7.7.5. Executing FSM_OPT pass (simple optimizations of FSMs).
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| 7.7.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
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| 7.7.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
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| 7.7.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
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| 7.8. Executing OPT pass (performing simple optimizations).
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| 7.8.1. Executing OPT_EXPR pass (perform const folding).
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| Optimizing module person_classifier_1p.
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|
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| 7.8.2. Executing OPT_MERGE pass (detect identical cells).
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| Finding identical cells in module `\person_classifier_1p'.
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| Computing hashes of 40 cells of `\person_classifier_1p'.
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| Finding duplicate cells in `\person_classifier_1p'.
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| Removed a total of 0 cells.
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|
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| 7.8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
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| Running muxtree optimizer on module \person_classifier_1p..
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| Creating internal representation of mux trees.
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| No muxes found in this module.
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| Removed 0 multiplexer ports.
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|
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| 7.8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
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| Optimizing cells in module \person_classifier_1p.
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| Performed a total of 0 changes.
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|
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| 7.8.5. Executing OPT_MERGE pass (detect identical cells).
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| Finding identical cells in module `\person_classifier_1p'.
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| Computing hashes of 40 cells of `\person_classifier_1p'.
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| Finding duplicate cells in `\person_classifier_1p'.
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| Removed a total of 0 cells.
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|
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| 7.8.6. Executing OPT_DFF pass (perform DFF optimizations).
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|
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| 7.8.7. Executing OPT_CLEAN pass (remove unused cells and wires).
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| Finding unused cells or wires in module \person_classifier_1p..
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|
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| 7.8.8. Executing OPT_EXPR pass (perform const folding).
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| Optimizing module person_classifier_1p.
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| 7.8.9. Finished fast OPT passes. (There is nothing left to do.)
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| 7.9. Executing WREDUCE pass (reducing word size of cells).
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| Converting cell person_classifier_1p.$add$person_classifier_1p.v:24$1 ($add) from unsigned to signed.
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| Removed top 8 bits (of 16) from port A of cell person_classifier_1p.$add$person_classifier_1p.v:24$1 ($add).
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| Removed top 8 bits (of 16) from port B of cell person_classifier_1p.$add$person_classifier_1p.v:24$1 ($add).
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| Removed top 7 bits (of 16) from port Y of cell person_classifier_1p.$add$person_classifier_1p.v:24$1 ($add).
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| Converting cell person_classifier_1p.$add$person_classifier_1p.v:24$2 ($add) from unsigned to signed.
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| Removed top 7 bits (of 16) from port A of cell person_classifier_1p.$add$person_classifier_1p.v:24$2 ($add).
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| Removed top 8 bits (of 16) from port B of cell person_classifier_1p.$add$person_classifier_1p.v:24$2 ($add).
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| Removed top 6 bits (of 16) from port Y of cell person_classifier_1p.$add$person_classifier_1p.v:24$2 ($add).
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| Converting cell person_classifier_1p.$add$person_classifier_1p.v:24$3 ($add) from unsigned to signed.
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| Removed top 6 bits (of 16) from port A of cell person_classifier_1p.$add$person_classifier_1p.v:24$3 ($add).
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| Removed top 8 bits (of 16) from port B of cell person_classifier_1p.$add$person_classifier_1p.v:24$3 ($add).
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| Removed top 5 bits (of 16) from port Y of cell person_classifier_1p.$add$person_classifier_1p.v:24$3 ($add).
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| Converting cell person_classifier_1p.$add$person_classifier_1p.v:24$4 ($add) from unsigned to signed.
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| Removed top 5 bits (of 16) from port A of cell person_classifier_1p.$add$person_classifier_1p.v:24$4 ($add).
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| Removed top 8 bits (of 16) from port B of cell person_classifier_1p.$add$person_classifier_1p.v:24$4 ($add).
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| Removed top 4 bits (of 16) from port Y of cell person_classifier_1p.$add$person_classifier_1p.v:24$4 ($add).
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| Converting cell person_classifier_1p.$add$person_classifier_1p.v:24$5 ($add) from unsigned to signed.
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| Removed top 4 bits (of 16) from port A of cell person_classifier_1p.$add$person_classifier_1p.v:24$5 ($add).
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| Removed top 8 bits (of 16) from port B of cell person_classifier_1p.$add$person_classifier_1p.v:24$5 ($add).
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| Removed top 3 bits (of 16) from port Y of cell person_classifier_1p.$add$person_classifier_1p.v:24$5 ($add).
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| Converting cell person_classifier_1p.$add$person_classifier_1p.v:24$6 ($add) from unsigned to signed.
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| Removed top 3 bits (of 16) from port A of cell person_classifier_1p.$add$person_classifier_1p.v:24$6 ($add).
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| Removed top 8 bits (of 16) from port B of cell person_classifier_1p.$add$person_classifier_1p.v:24$6 ($add).
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| Removed top 2 bits (of 16) from port Y of cell person_classifier_1p.$add$person_classifier_1p.v:24$6 ($add).
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| Converting cell person_classifier_1p.$add$person_classifier_1p.v:24$7 ($add) from unsigned to signed.
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| Removed top 2 bits (of 16) from port A of cell person_classifier_1p.$add$person_classifier_1p.v:24$7 ($add).
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| Removed top 8 bits (of 16) from port B of cell person_classifier_1p.$add$person_classifier_1p.v:24$7 ($add).
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| Removed top 1 bits (of 16) from port Y of cell person_classifier_1p.$add$person_classifier_1p.v:24$7 ($add).
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| Converting cell person_classifier_1p.$add$person_classifier_1p.v:24$8 ($add) from unsigned to signed.
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| Removed top 1 bits (of 16) from port A of cell person_classifier_1p.$add$person_classifier_1p.v:24$8 ($add).
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| Removed top 8 bits (of 16) from port B of cell person_classifier_1p.$add$person_classifier_1p.v:24$8 ($add).
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| Converting cell person_classifier_1p.$add$person_classifier_1p.v:31$20 ($add) from unsigned to signed.
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| Removed top 8 bits (of 16) from port A of cell person_classifier_1p.$add$person_classifier_1p.v:31$20 ($add).
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| Removed top 8 bits (of 16) from port B of cell person_classifier_1p.$add$person_classifier_1p.v:31$20 ($add).
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| Removed top 7 bits (of 16) from port Y of cell person_classifier_1p.$add$person_classifier_1p.v:31$20 ($add).
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| Converting cell person_classifier_1p.$add$person_classifier_1p.v:31$21 ($add) from unsigned to signed.
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| Removed top 7 bits (of 16) from port A of cell person_classifier_1p.$add$person_classifier_1p.v:31$21 ($add).
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| Removed top 8 bits (of 16) from port B of cell person_classifier_1p.$add$person_classifier_1p.v:31$21 ($add).
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| Removed top 6 bits (of 16) from port Y of cell person_classifier_1p.$add$person_classifier_1p.v:31$21 ($add).
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| Converting cell person_classifier_1p.$add$person_classifier_1p.v:31$22 ($add) from unsigned to signed.
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| Removed top 6 bits (of 16) from port A of cell person_classifier_1p.$add$person_classifier_1p.v:31$22 ($add).
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| Removed top 8 bits (of 16) from port B of cell person_classifier_1p.$add$person_classifier_1p.v:31$22 ($add).
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| Removed top 5 bits (of 16) from port Y of cell person_classifier_1p.$add$person_classifier_1p.v:31$22 ($add).
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| Converting cell person_classifier_1p.$add$person_classifier_1p.v:31$23 ($add) from unsigned to signed.
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| Removed top 5 bits (of 16) from port A of cell person_classifier_1p.$add$person_classifier_1p.v:31$23 ($add).
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| Removed top 8 bits (of 16) from port B of cell person_classifier_1p.$add$person_classifier_1p.v:31$23 ($add).
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| Removed top 4 bits (of 16) from port Y of cell person_classifier_1p.$add$person_classifier_1p.v:31$23 ($add).
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| Converting cell person_classifier_1p.$add$person_classifier_1p.v:31$24 ($add) from unsigned to signed.
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| Removed top 4 bits (of 16) from port A of cell person_classifier_1p.$add$person_classifier_1p.v:31$24 ($add).
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| Removed top 8 bits (of 16) from port B of cell person_classifier_1p.$add$person_classifier_1p.v:31$24 ($add).
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| Removed top 3 bits (of 16) from port Y of cell person_classifier_1p.$add$person_classifier_1p.v:31$24 ($add).
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| Converting cell person_classifier_1p.$add$person_classifier_1p.v:31$25 ($add) from unsigned to signed.
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| Removed top 3 bits (of 16) from port A of cell person_classifier_1p.$add$person_classifier_1p.v:31$25 ($add).
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| Removed top 8 bits (of 16) from port B of cell person_classifier_1p.$add$person_classifier_1p.v:31$25 ($add).
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| Removed top 2 bits (of 16) from port Y of cell person_classifier_1p.$add$person_classifier_1p.v:31$25 ($add).
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| Converting cell person_classifier_1p.$add$person_classifier_1p.v:31$26 ($add) from unsigned to signed.
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| Removed top 2 bits (of 16) from port A of cell person_classifier_1p.$add$person_classifier_1p.v:31$26 ($add).
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| Removed top 8 bits (of 16) from port B of cell person_classifier_1p.$add$person_classifier_1p.v:31$26 ($add).
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| Removed top 1 bits (of 16) from port Y of cell person_classifier_1p.$add$person_classifier_1p.v:31$26 ($add).
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| Converting cell person_classifier_1p.$add$person_classifier_1p.v:31$27 ($add) from unsigned to signed.
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| Removed top 1 bits (of 16) from port A of cell person_classifier_1p.$add$person_classifier_1p.v:31$27 ($add).
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| Removed top 8 bits (of 16) from port B of cell person_classifier_1p.$add$person_classifier_1p.v:31$27 ($add).
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|
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| 7.10. Executing PEEPOPT pass (run peephole optimizers).
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|
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| 7.11. Executing OPT_CLEAN pass (remove unused cells and wires).
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| Finding unused cells or wires in module \person_classifier_1p..
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|
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| 7.12. Executing ALUMACC pass (create $alu and $macc cells).
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| Extracting $alu and $macc cells in module person_classifier_1p:
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| creating $macc model for $sub$person_classifier_1p.v:37$39 ($sub).
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| creating $macc model for $add$person_classifier_1p.v:31$38 ($add).
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| creating $macc model for $add$person_classifier_1p.v:31$37 ($add).
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| creating $macc model for $add$person_classifier_1p.v:31$36 ($add).
|
| creating $macc model for $add$person_classifier_1p.v:31$35 ($add).
|
| creating $macc model for $add$person_classifier_1p.v:31$34 ($add).
|
| creating $macc model for $add$person_classifier_1p.v:31$33 ($add).
|
| creating $macc model for $add$person_classifier_1p.v:31$32 ($add).
|
| creating $macc model for $add$person_classifier_1p.v:31$31 ($add).
|
| creating $macc model for $add$person_classifier_1p.v:31$30 ($add).
|
| creating $macc model for $add$person_classifier_1p.v:31$29 ($add).
|
| creating $macc model for $add$person_classifier_1p.v:31$28 ($add).
|
| creating $macc model for $add$person_classifier_1p.v:31$27 ($add).
|
| creating $macc model for $add$person_classifier_1p.v:31$26 ($add).
|
| creating $macc model for $add$person_classifier_1p.v:31$25 ($add).
|
| creating $macc model for $add$person_classifier_1p.v:31$24 ($add).
|
| creating $macc model for $add$person_classifier_1p.v:31$23 ($add).
|
| creating $macc model for $add$person_classifier_1p.v:31$22 ($add).
|
| creating $macc model for $add$person_classifier_1p.v:31$21 ($add).
|
| creating $macc model for $add$person_classifier_1p.v:31$20 ($add).
|
| creating $macc model for $add$person_classifier_1p.v:24$19 ($add).
|
| creating $macc model for $add$person_classifier_1p.v:24$18 ($add).
|
| creating $macc model for $add$person_classifier_1p.v:24$17 ($add).
|
| creating $macc model for $add$person_classifier_1p.v:24$16 ($add).
|
| creating $macc model for $add$person_classifier_1p.v:24$15 ($add).
|
| creating $macc model for $add$person_classifier_1p.v:24$14 ($add).
|
| creating $macc model for $add$person_classifier_1p.v:24$13 ($add).
|
| creating $macc model for $add$person_classifier_1p.v:24$12 ($add).
|
| creating $macc model for $add$person_classifier_1p.v:24$11 ($add).
|
| creating $macc model for $add$person_classifier_1p.v:24$10 ($add).
|
| creating $macc model for $add$person_classifier_1p.v:24$9 ($add).
|
| creating $macc model for $add$person_classifier_1p.v:24$8 ($add).
|
| creating $macc model for $add$person_classifier_1p.v:24$7 ($add).
|
| creating $macc model for $add$person_classifier_1p.v:24$6 ($add).
|
| creating $macc model for $add$person_classifier_1p.v:24$5 ($add).
|
| creating $macc model for $add$person_classifier_1p.v:24$4 ($add).
|
| creating $macc model for $add$person_classifier_1p.v:24$3 ($add).
|
| creating $macc model for $add$person_classifier_1p.v:24$2 ($add).
|
| creating $macc model for $add$person_classifier_1p.v:24$1 ($add).
|
| merging $macc model for $add$person_classifier_1p.v:24$1 into $add$person_classifier_1p.v:24$2.
|
| merging $macc model for $add$person_classifier_1p.v:24$2 into $add$person_classifier_1p.v:24$3.
|
| merging $macc model for $add$person_classifier_1p.v:24$3 into $add$person_classifier_1p.v:24$4.
|
| merging $macc model for $add$person_classifier_1p.v:24$4 into $add$person_classifier_1p.v:24$5.
|
| merging $macc model for $add$person_classifier_1p.v:24$5 into $add$person_classifier_1p.v:24$6.
|
| merging $macc model for $add$person_classifier_1p.v:24$6 into $add$person_classifier_1p.v:24$7.
|
| merging $macc model for $add$person_classifier_1p.v:24$7 into $add$person_classifier_1p.v:24$8.
|
| merging $macc model for $add$person_classifier_1p.v:24$8 into $add$person_classifier_1p.v:24$9.
|
| merging $macc model for $add$person_classifier_1p.v:24$9 into $add$person_classifier_1p.v:24$10.
|
| merging $macc model for $add$person_classifier_1p.v:24$10 into $add$person_classifier_1p.v:24$11.
|
| merging $macc model for $add$person_classifier_1p.v:24$11 into $add$person_classifier_1p.v:24$12.
|
| merging $macc model for $add$person_classifier_1p.v:24$12 into $add$person_classifier_1p.v:24$13.
|
| merging $macc model for $add$person_classifier_1p.v:24$13 into $add$person_classifier_1p.v:24$14.
|
| merging $macc model for $add$person_classifier_1p.v:24$14 into $add$person_classifier_1p.v:24$15.
|
| merging $macc model for $add$person_classifier_1p.v:24$15 into $add$person_classifier_1p.v:24$16.
|
| merging $macc model for $add$person_classifier_1p.v:24$16 into $add$person_classifier_1p.v:24$17.
|
| merging $macc model for $add$person_classifier_1p.v:24$17 into $add$person_classifier_1p.v:24$18.
|
| merging $macc model for $add$person_classifier_1p.v:24$18 into $add$person_classifier_1p.v:24$19.
|
| merging $macc model for $add$person_classifier_1p.v:31$20 into $add$person_classifier_1p.v:31$21.
|
| merging $macc model for $add$person_classifier_1p.v:31$21 into $add$person_classifier_1p.v:31$22.
|
| merging $macc model for $add$person_classifier_1p.v:31$22 into $add$person_classifier_1p.v:31$23.
|
| merging $macc model for $add$person_classifier_1p.v:31$23 into $add$person_classifier_1p.v:31$24.
|
| merging $macc model for $add$person_classifier_1p.v:31$24 into $add$person_classifier_1p.v:31$25.
|
| merging $macc model for $add$person_classifier_1p.v:31$25 into $add$person_classifier_1p.v:31$26.
|
| merging $macc model for $add$person_classifier_1p.v:31$26 into $add$person_classifier_1p.v:31$27.
|
| merging $macc model for $add$person_classifier_1p.v:31$27 into $add$person_classifier_1p.v:31$28.
|
| merging $macc model for $add$person_classifier_1p.v:31$28 into $add$person_classifier_1p.v:31$29.
|
| merging $macc model for $add$person_classifier_1p.v:31$29 into $add$person_classifier_1p.v:31$30.
|
| merging $macc model for $add$person_classifier_1p.v:31$30 into $add$person_classifier_1p.v:31$31.
|
| merging $macc model for $add$person_classifier_1p.v:31$31 into $add$person_classifier_1p.v:31$32.
|
| merging $macc model for $add$person_classifier_1p.v:31$32 into $add$person_classifier_1p.v:31$33.
|
| merging $macc model for $add$person_classifier_1p.v:31$33 into $add$person_classifier_1p.v:31$34.
|
| merging $macc model for $add$person_classifier_1p.v:31$34 into $add$person_classifier_1p.v:31$35.
|
| merging $macc model for $add$person_classifier_1p.v:31$35 into $add$person_classifier_1p.v:31$36.
|
| merging $macc model for $add$person_classifier_1p.v:31$36 into $add$person_classifier_1p.v:31$37.
|
| merging $macc model for $add$person_classifier_1p.v:31$37 into $add$person_classifier_1p.v:31$38.
|
| merging $macc model for $add$person_classifier_1p.v:24$19 into $sub$person_classifier_1p.v:37$39.
|
| merging $macc model for $add$person_classifier_1p.v:31$38 into $sub$person_classifier_1p.v:37$39.
|
| creating $macc cell for $sub$person_classifier_1p.v:37$39: $auto$alumacc.cc:382:replace_macc$41
|
| creating $alu model for $gt$person_classifier_1p.v:38$40 ($gt): new $alu
|
| creating $alu cell for $gt$person_classifier_1p.v:38$40: $auto$alumacc.cc:512:replace_alu$43
|
| created 1 $alu and 1 $macc cells.
|
|
|
| 7.13. Executing SHARE pass (SAT-based resource sharing).
|
|
|
| 7.14. Executing OPT pass (performing simple optimizations).
|
|
|
| 7.14.1. Executing OPT_EXPR pass (perform const folding).
|
| Optimizing module person_classifier_1p.
|
|
|
| 7.14.2. Executing OPT_MERGE pass (detect identical cells).
|
| Finding identical cells in module `\person_classifier_1p'.
|
| Computing hashes of 45 cells of `\person_classifier_1p'.
|
| Finding duplicate cells in `\person_classifier_1p'.
|
| Removed a total of 0 cells.
|
|
|
| 7.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
| Running muxtree optimizer on module \person_classifier_1p..
|
| Creating internal representation of mux trees.
|
| No muxes found in this module.
|
| Removed 0 multiplexer ports.
|
|
|
| 7.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
| Optimizing cells in module \person_classifier_1p.
|
| Performed a total of 0 changes.
|
|
|
| 7.14.5. Executing OPT_MERGE pass (detect identical cells).
|
| Finding identical cells in module `\person_classifier_1p'.
|
| Computing hashes of 45 cells of `\person_classifier_1p'.
|
| Finding duplicate cells in `\person_classifier_1p'.
|
| Removed a total of 0 cells.
|
|
|
| 7.14.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
| 7.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
| Finding unused cells or wires in module \person_classifier_1p..
|
| Removed 38 unused cells and 39 unused wires.
|
| <suppressed ~41 debug messages>
|
|
|
| 7.14.8. Executing OPT_EXPR pass (perform const folding).
|
| Optimizing module person_classifier_1p.
|
|
|
| 7.14.9. Rerunning OPT passes. (Maybe there is more to do..)
|
|
|
| 7.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
| Running muxtree optimizer on module \person_classifier_1p..
|
| Creating internal representation of mux trees.
|
| No muxes found in this module.
|
| Removed 0 multiplexer ports.
|
|
|
| 7.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
| Optimizing cells in module \person_classifier_1p.
|
| Performed a total of 0 changes.
|
|
|
| 7.14.12. Executing OPT_MERGE pass (detect identical cells).
|
| Finding identical cells in module `\person_classifier_1p'.
|
| Computing hashes of 7 cells of `\person_classifier_1p'.
|
| Finding duplicate cells in `\person_classifier_1p'.
|
| Removed a total of 0 cells.
|
|
|
| 7.14.13. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
| 7.14.14. Executing OPT_CLEAN pass (remove unused cells and wires).
|
| Finding unused cells or wires in module \person_classifier_1p..
|
|
|
| 7.14.15. Executing OPT_EXPR pass (perform const folding).
|
| Optimizing module person_classifier_1p.
|
|
|
| 7.14.16. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
| 7.15. Executing MEMORY pass.
|
|
|
| 7.15.1. Executing OPT_MEM pass (optimize memories).
|
| Performed a total of 0 transformations.
|
|
|
| 7.15.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
|
| Performed a total of 0 transformations.
|
|
|
| 7.15.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
|
|
|
| 7.15.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
|
|
|
| 7.15.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
|
|
|
| 7.15.6. Executing OPT_CLEAN pass (remove unused cells and wires).
|
| Finding unused cells or wires in module \person_classifier_1p..
|
|
|
| 7.15.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
|
|
|
| 7.15.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
|
| Performed a total of 0 transformations.
|
|
|
| 7.15.9. Executing OPT_CLEAN pass (remove unused cells and wires).
|
| Finding unused cells or wires in module \person_classifier_1p..
|
|
|
| 7.15.10. Executing MEMORY_COLLECT pass (generating $mem cells).
|
|
|
| 7.16. Executing OPT_CLEAN pass (remove unused cells and wires).
|
| Finding unused cells or wires in module \person_classifier_1p..
|
|
|
| 7.17. Executing OPT pass (performing simple optimizations).
|
|
|
| 7.17.1. Executing OPT_EXPR pass (perform const folding).
|
| Optimizing module person_classifier_1p.
|
|
|
| 7.17.2. Executing OPT_MERGE pass (detect identical cells).
|
| Finding identical cells in module `\person_classifier_1p'.
|
| Computing hashes of 7 cells of `\person_classifier_1p'.
|
| Finding duplicate cells in `\person_classifier_1p'.
|
| Removed a total of 0 cells.
|
|
|
| 7.17.3. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
| 7.17.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
| Finding unused cells or wires in module \person_classifier_1p..
|
|
|
| 7.17.5. Finished fast OPT passes.
|
|
|
| 7.18. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
|
|
|
| 7.19. Executing OPT pass (performing simple optimizations).
|
|
|
| 7.19.1. Executing OPT_EXPR pass (perform const folding).
|
| Optimizing module person_classifier_1p.
|
|
|
| 7.19.2. Executing OPT_MERGE pass (detect identical cells).
|
| Finding identical cells in module `\person_classifier_1p'.
|
| Computing hashes of 7 cells of `\person_classifier_1p'.
|
| Finding duplicate cells in `\person_classifier_1p'.
|
| Removed a total of 0 cells.
|
|
|
| 7.19.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
| Running muxtree optimizer on module \person_classifier_1p..
|
| Creating internal representation of mux trees.
|
| No muxes found in this module.
|
| Removed 0 multiplexer ports.
|
|
|
| 7.19.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
| Optimizing cells in module \person_classifier_1p.
|
| Performed a total of 0 changes.
|
|
|
| 7.19.5. Executing OPT_MERGE pass (detect identical cells).
|
| Finding identical cells in module `\person_classifier_1p'.
|
| Computing hashes of 7 cells of `\person_classifier_1p'.
|
| Finding duplicate cells in `\person_classifier_1p'.
|
| Removed a total of 0 cells.
|
|
|
| 7.19.6. Executing OPT_SHARE pass.
|
|
|
| 7.19.7. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
| 7.19.8. Executing OPT_CLEAN pass (remove unused cells and wires).
|
| Finding unused cells or wires in module \person_classifier_1p..
|
|
|
| 7.19.9. Executing OPT_EXPR pass (perform const folding).
|
| Optimizing module person_classifier_1p.
|
|
|
| 7.19.10. Finished fast OPT passes. (There is nothing left to do.)
|
|
|
| 7.20. Executing TECHMAP pass (map to technology primitives).
|
|
|
| 7.20.1. Executing Verilog-2005 frontend: D:\oss-cad-suite\bin\../share/yosys/techmap.v
|
| Parsing Verilog input from `D:\oss-cad-suite\bin\../share/yosys/techmap.v' to AST representation.
|
| Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
| Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
| Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
| Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
| Generating RTLIL representation for module `\_90_simplemap_various'.
|
| Generating RTLIL representation for module `\_90_simplemap_registers'.
|
| Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
| Generating RTLIL representation for module `\_90_shift_shiftx'.
|
| Generating RTLIL representation for module `\_90_fa'.
|
| Generating RTLIL representation for module `\_90_lcu_brent_kung'.
|
| Generating RTLIL representation for module `\_90_alu'.
|
| Generating RTLIL representation for module `\_90_macc'.
|
| Generating RTLIL representation for module `\_90_alumacc'.
|
| Generating RTLIL representation for module `$__div_mod_u'.
|
| Generating RTLIL representation for module `$__div_mod_trunc'.
|
| Generating RTLIL representation for module `\_90_div'.
|
| Generating RTLIL representation for module `\_90_mod'.
|
| Generating RTLIL representation for module `$__div_mod_floor'.
|
| Generating RTLIL representation for module `\_90_divfloor'.
|
| Generating RTLIL representation for module `\_90_modfloor'.
|
| Generating RTLIL representation for module `\_90_pow'.
|
| Generating RTLIL representation for module `\_90_pmux'.
|
| Generating RTLIL representation for module `\_90_demux'.
|
| Generating RTLIL representation for module `\_90_lut'.
|
| Generating RTLIL representation for module `$connect'.
|
| Generating RTLIL representation for module `$input_port'.
|
| Successfully finished Verilog frontend.
|
|
|
| 7.20.2. Continuing TECHMAP pass.
|
| Using extmapper simplemap for cells of type $not.
|
| Using extmapper simplemap for cells of type $or.
|
| Using extmapper simplemap for cells of type $reduce_and.
|
| Using extmapper simplemap for cells of type $xor.
|
| Using template $paramod$d4c0c20b0ee59f495e14575c4397dc0a6dd9e8e6\_90_alu for cells of type $alu.
|
| Using extmapper maccmap for cells of type $macc_v2.
|
| add \f00 (8 bits, signed)
|
| sub \f20 (8 bits, signed)
|
| add { \f19 [7] \f19 [7] \f19 [7] \f19 [7] \f19 [7] \f19 [7] \f19 [7] \f19 [7] \f19 } (16 bits, unsigned)
|
| add { \f18 [7] \f18 [7] \f18 [7] \f18 [7] \f18 [7] \f18 [7] \f18 [7] \f18 [7] \f18 } (16 bits, unsigned)
|
| add { \f17 [7] \f17 [7] \f17 [7] \f17 [7] \f17 [7] \f17 [7] \f17 [7] \f17 [7] \f17 } (16 bits, unsigned)
|
| add { \f16 [7] \f16 [7] \f16 [7] \f16 [7] \f16 [7] \f16 [7] \f16 [7] \f16 [7] \f16 } (16 bits, unsigned)
|
| add { \f15 [7] \f15 [7] \f15 [7] \f15 [7] \f15 [7] \f15 [7] \f15 [7] \f15 [7] \f15 } (16 bits, unsigned)
|
| add { \f14 [7] \f14 [7] \f14 [7] \f14 [7] \f14 [7] \f14 [7] \f14 [7] \f14 [7] \f14 } (16 bits, unsigned)
|
| add { \f13 [7] \f13 [7] \f13 [7] \f13 [7] \f13 [7] \f13 [7] \f13 [7] \f13 [7] \f13 } (16 bits, unsigned)
|
| add { \f12 [7] \f12 [7] \f12 [7] \f12 [7] \f12 [7] \f12 [7] \f12 [7] \f12 [7] \f12 } (16 bits, unsigned)
|
| add { \f11 [7] \f11 [7] \f11 [7] \f11 [7] \f11 [7] \f11 [7] \f11 [7] \f11 [7] \f11 } (16 bits, unsigned)
|
| add { \f10 [7] \f10 [7] \f10 [7] \f10 [7] \f10 [7] \f10 [7] \f10 [7] \f10 [7] \f10 } (16 bits, unsigned)
|
| add { \f09 [7] \f09 [7] \f09 [7] \f09 [7] \f09 [7] \f09 [7] \f09 [7] \f09 [7] \f09 } (16 bits, unsigned)
|
| add \f08 (8 bits, signed)
|
| add \f07 (8 bits, signed)
|
| add \f06 (8 bits, signed)
|
| add \f05 (8 bits, signed)
|
| add \f04 (8 bits, signed)
|
| add \f03 (8 bits, signed)
|
| add \f02 (8 bits, signed)
|
| add \f01 (8 bits, signed)
|
| sub { \f39 [7] \f39 [7] \f39 [7] \f39 [7] \f39 [7] \f39 [7] \f39 [7] \f39 [7] \f39 } (16 bits, unsigned)
|
| sub { \f38 [7] \f38 [7] \f38 [7] \f38 [7] \f38 [7] \f38 [7] \f38 [7] \f38 [7] \f38 } (16 bits, unsigned)
|
| sub { \f37 [7] \f37 [7] \f37 [7] \f37 [7] \f37 [7] \f37 [7] \f37 [7] \f37 [7] \f37 } (16 bits, unsigned)
|
| sub { \f36 [7] \f36 [7] \f36 [7] \f36 [7] \f36 [7] \f36 [7] \f36 [7] \f36 [7] \f36 } (16 bits, unsigned)
|
| sub { \f35 [7] \f35 [7] \f35 [7] \f35 [7] \f35 [7] \f35 [7] \f35 [7] \f35 [7] \f35 } (16 bits, unsigned)
|
| sub { \f34 [7] \f34 [7] \f34 [7] \f34 [7] \f34 [7] \f34 [7] \f34 [7] \f34 [7] \f34 } (16 bits, unsigned)
|
| sub { \f33 [7] \f33 [7] \f33 [7] \f33 [7] \f33 [7] \f33 [7] \f33 [7] \f33 [7] \f33 } (16 bits, unsigned)
|
| sub { \f32 [7] \f32 [7] \f32 [7] \f32 [7] \f32 [7] \f32 [7] \f32 [7] \f32 [7] \f32 } (16 bits, unsigned)
|
| sub { \f31 [7] \f31 [7] \f31 [7] \f31 [7] \f31 [7] \f31 [7] \f31 [7] \f31 [7] \f31 } (16 bits, unsigned)
|
| sub { \f30 [7] \f30 [7] \f30 [7] \f30 [7] \f30 [7] \f30 [7] \f30 [7] \f30 [7] \f30 } (16 bits, unsigned)
|
| sub { \f29 [7] \f29 [7] \f29 [7] \f29 [7] \f29 [7] \f29 [7] \f29 [7] \f29 [7] \f29 } (16 bits, unsigned)
|
| sub \f28 (8 bits, signed)
|
| sub \f27 (8 bits, signed)
|
| sub \f26 (8 bits, signed)
|
| sub \f25 (8 bits, signed)
|
| sub \f24 (8 bits, signed)
|
| sub \f23 (8 bits, signed)
|
| sub \f22 (8 bits, signed)
|
| sub \f21 (8 bits, signed)
|
| packed 20 (2) bits / 1 words into adder tree
|
| Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000010000 for cells of type $fa.
|
| Using template $paramod$6df0329addda9228fcc2546de2aaf14ad26c98e1\_90_alu for cells of type $alu.
|
| Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000010000 for cells of type $lcu.
|
| Using extmapper simplemap for cells of type $pos.
|
| Using extmapper simplemap for cells of type $mux.
|
| Using extmapper simplemap for cells of type $and.
|
| No more expansions possible.
|
| <suppressed ~659 debug messages>
|
|
|
| 7.21. Executing OPT pass (performing simple optimizations).
|
|
|
| 7.21.1. Executing OPT_EXPR pass (perform const folding).
|
| Optimizing module person_classifier_1p.
|
| <suppressed ~217 debug messages>
|
|
|
| 7.21.2. Executing OPT_MERGE pass (detect identical cells).
|
| Finding identical cells in module `\person_classifier_1p'.
|
| Computing hashes of 3553 cells of `\person_classifier_1p'.
|
| Finding duplicate cells in `\person_classifier_1p'.
|
| Computing hashes of 3290 cells of `\person_classifier_1p'.
|
| Finding duplicate cells in `\person_classifier_1p'.
|
| Computing hashes of 3079 cells of `\person_classifier_1p'.
|
| Finding duplicate cells in `\person_classifier_1p'.
|
| Computing hashes of 2918 cells of `\person_classifier_1p'.
|
| Finding duplicate cells in `\person_classifier_1p'.
|
| Computing hashes of 2806 cells of `\person_classifier_1p'.
|
| Finding duplicate cells in `\person_classifier_1p'.
|
| Computing hashes of 2680 cells of `\person_classifier_1p'.
|
| Finding duplicate cells in `\person_classifier_1p'.
|
| Computing hashes of 2582 cells of `\person_classifier_1p'.
|
| Finding duplicate cells in `\person_classifier_1p'.
|
| Computing hashes of 2523 cells of `\person_classifier_1p'.
|
| Finding duplicate cells in `\person_classifier_1p'.
|
| Computing hashes of 2451 cells of `\person_classifier_1p'.
|
| Finding duplicate cells in `\person_classifier_1p'.
|
| Computing hashes of 2391 cells of `\person_classifier_1p'.
|
| Finding duplicate cells in `\person_classifier_1p'.
|
| Computing hashes of 2357 cells of `\person_classifier_1p'.
|
| Finding duplicate cells in `\person_classifier_1p'.
|
| Computing hashes of 2317 cells of `\person_classifier_1p'.
|
| Finding duplicate cells in `\person_classifier_1p'.
|
| Computing hashes of 2282 cells of `\person_classifier_1p'.
|
| Finding duplicate cells in `\person_classifier_1p'.
|
| Computing hashes of 2267 cells of `\person_classifier_1p'.
|
| Finding duplicate cells in `\person_classifier_1p'.
|
| Computing hashes of 2251 cells of `\person_classifier_1p'.
|
| Finding duplicate cells in `\person_classifier_1p'.
|
| Computing hashes of 2235 cells of `\person_classifier_1p'.
|
| Finding duplicate cells in `\person_classifier_1p'.
|
| Computing hashes of 2227 cells of `\person_classifier_1p'.
|
| Finding duplicate cells in `\person_classifier_1p'.
|
| Computing hashes of 2215 cells of `\person_classifier_1p'.
|
| Finding duplicate cells in `\person_classifier_1p'.
|
| Computing hashes of 2203 cells of `\person_classifier_1p'.
|
| Finding duplicate cells in `\person_classifier_1p'.
|
| Computing hashes of 2197 cells of `\person_classifier_1p'.
|
| Finding duplicate cells in `\person_classifier_1p'.
|
| Computing hashes of 2193 cells of `\person_classifier_1p'.
|
| Finding duplicate cells in `\person_classifier_1p'.
|
| Computing hashes of 2189 cells of `\person_classifier_1p'.
|
| Finding duplicate cells in `\person_classifier_1p'.
|
| Computing hashes of 2187 cells of `\person_classifier_1p'.
|
| Finding duplicate cells in `\person_classifier_1p'.
|
| Computing hashes of 2185 cells of `\person_classifier_1p'.
|
| Finding duplicate cells in `\person_classifier_1p'.
|
| Computing hashes of 2183 cells of `\person_classifier_1p'.
|
| Finding duplicate cells in `\person_classifier_1p'.
|
| Computing hashes of 2182 cells of `\person_classifier_1p'.
|
| Finding duplicate cells in `\person_classifier_1p'.
|
| <suppressed ~4113 debug messages>
|
| Removed a total of 1371 cells.
|
|
|
| 7.21.3. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
| 7.21.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
| Finding unused cells or wires in module \person_classifier_1p..
|
| Removed 58 unused cells and 495 unused wires.
|
| <suppressed ~59 debug messages>
|
|
|
| 7.21.5. Finished fast OPT passes.
|
|
|
| 7.22. Executing ABC pass (technology mapping using ABC).
|
|
|
| 7.22.1. Extracting gate netlist of module `\person_classifier_1p' to `<abc-temp-dir>/input.blif'..
|
|
|
| 7.22.1.1. Executed ABC.
|
| Extracted 2124 gates and 2460 wires to a netlist network with 336 inputs and 1 outputs.
|
| Running ABC script: <abc-temp-dir>/abc.script
|
| ABC: ======== ABC command line "source <abc-temp-dir>/abc.script"
|
| ABC: + read_blif <abc-temp-dir>/input.blif
|
| ABC: + read_library <abc-temp-dir>/stdcells.genlib
|
| ABC: + strash
|
| ABC: + &get -n
|
| ABC: + &fraig -x
|
| ABC: + &put
|
| ABC: + scorr
|
| ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
|
| ABC: + dc2
|
| ABC: + dretime
|
| ABC: + strash
|
| ABC: + &get -n
|
| ABC: + &dch -f
|
| ABC: + &nf
|
| ABC: + &put
|
| ABC: + write_blif <abc-temp-dir>/output.blif
|
|
|
| 7.22.1.2. Re-integrating ABC results.
|
| ABC RESULTS: AND cells: 113
|
| ABC RESULTS: ANDNOT cells: 42
|
| ABC RESULTS: MUX cells: 13
|
| ABC RESULTS: NAND cells: 774
|
| ABC RESULTS: NOR cells: 31
|
| ABC RESULTS: NOT cells: 4
|
| ABC RESULTS: OR cells: 193
|
| ABC RESULTS: ORNOT cells: 10
|
| ABC RESULTS: XNOR cells: 202
|
| ABC RESULTS: XOR cells: 497
|
| ABC RESULTS: internal signals: 2123
|
| ABC RESULTS: input signals: 336
|
| ABC RESULTS: output signals: 1
|
| Removing temp directory.
|
| Removing global temp directory.
|
|
|
| 7.23. Executing OPT pass (performing simple optimizations).
|
|
|
| 7.23.1. Executing OPT_EXPR pass (perform const folding).
|
| Optimizing module person_classifier_1p.
|
| <suppressed ~2 debug messages>
|
|
|
| 7.23.2. Executing OPT_MERGE pass (detect identical cells).
|
| Finding identical cells in module `\person_classifier_1p'.
|
| Computing hashes of 1879 cells of `\person_classifier_1p'.
|
| Finding duplicate cells in `\person_classifier_1p'.
|
| Removed a total of 0 cells.
|
|
|
| 7.23.3. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
| 7.23.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
| Finding unused cells or wires in module \person_classifier_1p..
|
| Removed 0 unused cells and 626 unused wires.
|
| <suppressed ~2 debug messages>
|
|
|
| 7.23.5. Finished fast OPT passes.
|
|
|
| 7.24. Executing HIERARCHY pass (managing design hierarchy).
|
| Attribute `top' found on module `person_classifier_1p'. Setting top module to person_classifier_1p.
|
|
|
| 7.24.1. Analyzing design hierarchy..
|
| Top module: \person_classifier_1p
|
|
|
| 7.24.2. Analyzing design hierarchy..
|
| Top module: \person_classifier_1p
|
| Removed 0 unused modules.
|
|
|
| 7.25. Printing statistics.
|
|
|
| === person_classifier_1p ===
|
|
|
| +----------Local Count, excluding submodules.
|
| |
|
| 1920 wires
|
| 2215 wire bits
|
| 42 public wires
|
| 337 public wire bits
|
| 42 ports
|
| 337 port bits
|
| 1879 cells
|
| 42 $_ANDNOT_
|
| 113 $_AND_
|
| 13 $_MUX_
|
| 774 $_NAND_
|
| 31 $_NOR_
|
| 4 $_NOT_
|
| 10 $_ORNOT_
|
| 193 $_OR_
|
| 202 $_XNOR_
|
| 497 $_XOR_
|
|
|
| 7.26. Executing CHECK pass (checking for obvious problems).
|
| Checking module person_classifier_1p...
|
| Found and reported 0 problems.
|
|
|
| 8. Executing ABC pass (technology mapping using ABC).
|
|
|
| 8.1. Extracting gate netlist of module `\person_classifier_1p' to `<abc-temp-dir>/input.blif'..
|
|
|
| 8.1.1. Executed ABC.
|
| Extracted 1879 gates and 2215 wires to a netlist network with 336 inputs and 1 outputs.
|
| Running ABC script: <abc-temp-dir>/abc.script
|
| ABC: ======== ABC command line "source <abc-temp-dir>/abc.script"
|
| ABC: + read_blif <abc-temp-dir>/input.blif
|
| ABC: + read_library <abc-temp-dir>/stdcells.genlib
|
| ABC: + strash
|
| ABC: + &get -n
|
| ABC: + &fraig -x
|
| ABC: + &put
|
| ABC: + scorr
|
| ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
|
| ABC: + dc2
|
| ABC: + dretime
|
| ABC: + strash
|
| ABC: + &get -n
|
| ABC: + &dch -f
|
| ABC: + &nf
|
| ABC: + &put
|
| ABC: + write_blif <abc-temp-dir>/output.blif
|
|
|
| 8.1.2. Re-integrating ABC results.
|
| ABC RESULTS: AND cells: 1172
|
| ABC RESULTS: NOT cells: 1318
|
| ABC RESULTS: XOR cells: 730
|
| ABC RESULTS: internal signals: 1878
|
| ABC RESULTS: input signals: 336
|
| ABC RESULTS: output signals: 1
|
| Removing temp directory.
|
| Removing global temp directory.
|
|
|
| 9. Executing OPT_CLEAN pass (remove unused cells and wires).
|
| Finding unused cells or wires in module \person_classifier_1p..
|
| Removed 0 unused cells and 2215 unused wires.
|
| <suppressed ~1 debug messages>
|
|
|
| 10. Printing statistics.
|
|
|
| === person_classifier_1p ===
|
|
|
| +----------Local Count, excluding submodules.
|
| |
|
| 3261 wires
|
| 3556 wire bits
|
| 42 public wires
|
| 337 public wire bits
|
| 42 ports
|
| 337 port bits
|
| 3220 cells
|
| 1172 $_AND_
|
| 1318 $_NOT_
|
| 730 $_XOR_
|
|
|
| 11. Executing Verilog backend.
|
|
|
| 11.1. Executing BMUXMAP pass.
|
|
|
| 11.2. Executing DEMUXMAP pass.
|
| Dumping module `\person_classifier_1p'.
|
|
|
| End of script. Logfile hash: b1bbd57796
|
| Yosys 0.63+222 (git sha1 a4b6a8c58-dirty, x86_64-w64-mingw32-g++ 13.2.1 -O3)
|
| Time spent: 1
|
|
|
