Add execution model to README, remove tensors.txt and todo.md

- Add architecture diagram and instruction set table
- Add design principles
- Remove tensors.txt
- Integrate todo.md content into README

README.md

@@ -39,6 +39,83 @@ A complete 8-bit processor where every operation—from Boolean logic to arithme
 
 ---
 
+## Execution Model
+
+A self-contained, autonomous computational machine:
+- **Pure tensor computation**: State in, state out
+- **Frozen circuits**: Integer weights, Heaviside activation
+- **ACT execution**: Internal loop until HALT
+- **No external orchestration**: One forward pass = complete program execution
+
+```
+            ┌─────────────────────────────┐
+            │      Initial State          │
+            │  [PC|Regs|Flags|Memory...]  │
+            └─────────────┬───────────────┘
+                          ▼
+            ┌─────────────────────────────┐
+            │                             │
+            │   Threshold Circuit Layer   │
+            │                             │
+            │  ┌───────────────────────┐  │
+            │  │   Fetch: PC → Instr   │  │
+            │  ├───────────────────────┤  │
+            │  │   Decode: Opcode/Ops  │  │
+            │  ├───────────────────────┤  │
+            │  │   Execute: ALU/Mem    │  │
+            │  ├───────────────────────┤  │
+            │  │   Writeback: Results  │  │
+            │  ├───────────────────────┤  │
+            │  │   PC Update           │  │
+            │  └───────────┬───────────┘  │
+            │              │              │
+            │         ┌────▼────┐         │
+            │         │ HALTED? │         │
+            │         └────┬────┘         │
+            │              │              │
+            │         no ──┴── yes        │
+            │          │       │          │
+            │          ▼       ▼          │
+            │       [loop]   [exit]       │
+            │                             │
+            └─────────────┬───────────────┘
+                          ▼
+            ┌─────────────────────────────┐
+            │       Final State           │
+            │  [PC|Regs|Flags|Memory...]  │
+            └─────────────────────────────┘
+```
+
+### Instruction Set
+
+| Opcode | Mnemonic | Operation |
+|--------|----------|-----------|
+| 0x0 | ADD | R[d] = R[a] + R[b] |
+| 0x1 | SUB | R[d] = R[a] - R[b] |
+| 0x2 | AND | R[d] = R[a] & R[b] |
+| 0x3 | OR | R[d] = R[a] \| R[b] |
+| 0x4 | XOR | R[d] = R[a] ^ R[b] |
+| 0x5 | SHL | R[d] = R[a] << 1 |
+| 0x6 | SHR | R[d] = R[a] >> 1 |
+| 0x7 | MUL | R[d] = R[a] * R[b] |
+| 0x8 | DIV | R[d] = R[a] / R[b] |
+| 0x9 | CMP | flags = R[a] - R[b] |
+| 0xA | LOAD | R[d] = M[addr] |
+| 0xB | STORE | M[addr] = R[s] |
+| 0xC | JMP | PC = addr |
+| 0xD | JZ/JNZ | PC = addr if flag |
+| 0xE | CALL | push PC; PC = addr |
+| 0xF | HALT | stop execution |
+
+### Design Principles
+
+1. **Autonomy**: Machine runs without external logic
+2. **Purity**: forward(state) → state', no side effects
+3. **Transparency**: All weights inspectable, all operations traceable
+4. **Universality**: Turing complete, runs arbitrary programs
+
+---
+
 ## Background
 
 ### Threshold Logic

tensors.txt

@@ -1,3 +0,0 @@
-version https://git-lfs.github.com/spec/v1
-oid sha256:e01c8089229853c66c3d0e77b504a09fddd7e6e78c56018818c90f41c5a2a43e
-size 44592750

todo.md

@@ -1,174 +0,0 @@
-# Threshold Logic Neural Turing Machine
-
-## Core Vision
-
-A self-contained, autonomous computational machine:
-- **Pure tensor computation**: State in, state out
-- **Frozen verified circuits**: Exhaustively tested, can't compute wrong
-- **ACT execution**: Internal loop until HALT
-- **No external orchestration**: One forward pass = complete program execution
-
-The machine runs. Callers just provide initial state and collect results.
-
-## Architecture
-
-```
-            ┌─────────────────────────────┐
-            │      Initial State          │
-            │  [PC|Regs|Flags|Memory...]  │
-            └─────────────┬───────────────┘
-                          ▼
-            ┌─────────────────────────────┐
-            │                             │
-            │   Threshold Circuit Layer   │
-            │                             │
-            │  ┌───────────────────────┐  │
-            │  │   Fetch: PC → Instr   │  │
-            │  ├───────────────────────┤  │
-            │  │   Decode: Opcode/Ops  │  │
-            │  ├───────────────────────┤  │
-            │  │   Execute: ALU/Mem    │  │
-            │  ├───────────────────────┤  │
-            │  │   Writeback: Results  │  │
-            │  ├───────────────────────┤  │
-            │  │   PC Update           │  │
-            │  └───────────┬───────────┘  │
-            │              │              │
-            │         ┌────▼────┐         │
-            │         │ HALTED? │         │
-            │         └────┬────┘         │
-            │              │              │
-            │         no ──┴── yes        │
-            │          │       │          │
-            │          ▼       ▼          │
-            │       [loop]   [exit]       │
-            │                             │
-            └─────────────┬───────────────┘
-                          ▼
-            ┌─────────────────────────────┐
-            │       Final State           │
-            │  [PC|Regs|Flags|Memory...]  │
-            └─────────────────────────────┘
-```
-
-## Memory Architecture
-
-### State Tensor Layout
-```
-┌────────┬──────────┬───────┬────────┬─────────────────────┐
-│ PC [16] │ Regs[32] │Flags[4│Ctrl[4] │ Memory [N × 8]      │
-└────────┴──────────┴───────┴────────┴─────────────────────┘
-    16   +   32     +   4   +   4    +   N × 8   bits
-```
-
-### Memory Hierarchy
-| Level | Size | Tensors | Access |
-|-------|------|---------|--------|
-| Registers | 4 × 8-bit | Direct wiring | Immediate |
-| Main memory | 64KB | ~1.6M | 16-bit addressed |
-
-### Full 64KB Configuration
-- Address space: 0x0000 - 0xFFFF
-- Routing circuits: ~1.64M tensors
-- State tensor: 88 + 524,288 = 524,376 bits per instance
-
-## Phase 1: Memory Infrastructure
-
-64KB memory circuits are implemented and pass comprehensive eval.
-
-| Component | Description | Tensors | Status |
-|-----------|-------------|---------|--------|
-| Address Decoder 16-bit | 16-bit → 65536 one-hot | 2 (packed) | Done |
-| Memory Read MUX 64K | 65536-to-1 × 8 bits | 4 (packed) | Done |
-| Memory Write Demux | Route write to address | 4 (packed) | Done |
-| Memory Cell Logic | Conditional update | 6 (packed) | Done |
-
-## Phase 2: Execution Engine
-
-| Component | Description | Status |
-|-----------|-------------|--------|
-| Instruction Fetch | PC → Memory → IR | Done |
-| Operand Fetch | Decode → Register/Memory Read | Done |
-| ALU Dispatch | Opcode → Operation Select | Done |
-| Result Writeback | Route to destination | Done |
-| Flag Update | Compute Z/N/C/V | Done |
-| PC Advance | Increment or Jump | Done |
-| Halt Detection | HALT opcode → stop | Done |
-
-## Phase 3: ACT Integration
-
-Threshold runtime available in cpu/threshold_cpu.py (cycle + ACT loop + state I/O).
-
-| Component | Description | Status |
-|-----------|-------------|--------|
-| Cycle Block | All Phase 2 as single layer | Done |
-| Recurrence Wrapper | Loop until halt signal | Done |
-| Max Cycles Guard | Prevent infinite loops | Done |
-| State I/O | Pack/unpack state tensor | Done |
-
-## Instruction Set
-
-| Opcode | Mnemonic | Operation | Status |
-|--------|----------|-----------|--------|
-| 0x0 | ADD | R[d] = R[a] + R[b] | Done |
-| 0x1 | SUB | R[d] = R[a] - R[b] | Done |
-| 0x2 | AND | R[d] = R[a] & R[b] | Done |
-| 0x3 | OR | R[d] = R[a] \| R[b] | Done |
-| 0x4 | XOR | R[d] = R[a] ^ R[b] | Done |
-| 0x5 | SHL | R[d] = R[a] << 1 | Done |
-| 0x6 | SHR | R[d] = R[a] >> 1 | Done |
-| 0x7 | MUL | R[d] = R[a] * R[b] | Done |
-| 0x8 | DIV | R[d] = R[a] / R[b] | Done |
-| 0x9 | CMP | flags = R[a] - R[b] | Done |
-| 0xA | LOAD | R[d] = M[addr] | Done |
-| 0xB | STORE | M[addr] = R[s] | Done |
-| 0xC | JMP | PC = addr | Done |
-| 0xD | JZ/JNZ | PC = addr if flag | Done |
-| 0xE | CALL | push PC; PC = addr | Done |
-| 0xF | HALT | stop execution | Done |
-
-## Completed Circuits
-
-### Arithmetic (2,756 tensors)
-- ADD, SUB, MUL, DIV, NEG
-- ADC, SBC (with carry)
-- CMP (compare, sets flags)
-
-### Bit Operations (62 tensors)
-- ASR (arithmetic shift right)
-- ROL, ROR (rotate through carry)
-- SHL, SHR (from original)
-
-### Control (306 tensors)
-- NOP, HALT
-- PC Increment, PC Load MUX
-- Register MUX 4-to-1
-- Instruction Decoder 4-to-16
-
-### Original Model (~3,100 tensors)
-- Boolean gates (AND, OR, XOR, NOT, NAND, NOR)
-- Ripple carry adders (2/4/8-bit)
-- 8×8 multiplier
-- Comparators, threshold gates
-- Conditional jumps
-
-**Current: 6,296 tensors (packed memory)**
-**Parameters: 8,267,667**
-
-## Applications
-
-The machine is general-purpose. Possible callers:
-
-1. **Direct invocation**: Load state, call forward(), read result
-2. **LLM coprocessor**: Embedded layer for exact computation
-3. **Neuromorphic deployment**: Map to spiking hardware
-4. **Verified computation**: Provably correct execution
-5. **Educational**: Transparent, inspectable CPU
-
-## Design Principles
-
-1. **Autonomy**: Machine runs without external logic
-2. **Purity**: forward(state) → state', no side effects
-3. **Verification**: Every circuit exhaustively tested
-4. **Transparency**: All weights inspectable, all operations traceable
-5. **Universality**: Turing complete, runs arbitrary programs