infer_inputs_for_gate: handle bit-cascade and ternary modular patterns

Adds pattern matchers covering every gate name family the bit-cascade
migration introduced:

arithmetic.cmp{N}bit.bit{i}.{gt,lt,eq.layer1.and,eq.layer1.nor,eq}
arithmetic.cmp{N}bit.cascade.eq_prefix.bit{i}
arithmetic.cmp{N}bit.cascade.{gt,lt}.bit{i}
arithmetic.{greaterthan,lessthan,equality,greaterorequal,lessorequal}{N}bit
arithmetic.{greaterorequal,lessorequal}{N}bit.{not_lt,not_gt}

alu.alu{N}bit.div.stage{S}.cmp_bc.* (same internal cascade structure)
alu.alu{N}bit.div.stage{S}.cmp(.not_lt)?

float{16,32}.cmp.mag_bc.* + mag_a_{gt,lt,ge,le}_b + mag_eq.and
float{16,32}.add.exp_cmp_bc.* + exp_cmp.{a_gt_b,a_lt_b}
float{16,32}.div.mant_div.stage{S}.cmp_bc.*
float{16,32}.div.mant_div.stage{S}.cmp(.not_lt)?

modular.mod{N}.eq.k{k}.bit{i}.match
modular.mod{N}.eq.k{k}.all
modular.mod{N} (final OR over per-multiple equality detectors)

Two helper functions: _infer_bit_cascade walks one cascade tree given
its prefix and per-bit input name templates; _infer_compare_final
handles the public output gates emitted by add_bit_cascade_compare
(N-input OR for gt/lt, N-input AND for eq, NOT-then-buffer for ge/le).

Test build of an 8-bit small variant after this change: cmd_inputs
reports Empty=0, where it previously produced thousands of gates with
no routing metadata. Stale entries from the seed file still persist
because cmd_inputs only adds .inputs (it doesn't overwrite); refreshing
those requires either a fresh build_all pass or a separate flag to drop
existing .inputs before regeneration.

build.py

@@ -2679,9 +2679,198 @@ def infer_combinational_inputs(gate: str, reg: SignalRegistry, tensors: Dict[str
     return []
 
 
+def _infer_bit_cascade(gate: str, reg: SignalRegistry, cmp_prefix: str,
+                       a_template: str, b_template: str) -> List[int] | None:
+    """If `gate` is part of the bit-cascade comparator at `cmp_prefix`, return
+    its inputs. `a_template` / `b_template` are format strings like
+    "$a[{}]" / "$b[{}]" that produce the per-bit input signal names. Returns
+    None if `gate` isn't a member of this cascade.
+    """
+    if not gate.startswith(cmp_prefix + "."):
+        return None
+    suffix = gate[len(cmp_prefix) + 1:]
+
+    m = re.match(r"^bit(\d+)(?:\.(.+))?$", suffix)
+    if m:
+        i = int(m.group(1))
+        sub = m.group(2) or ""
+        a_sig = a_template.format(i)
+        b_sig = b_template.format(i)
+        if sub in ("gt", "lt", "eq.layer1.and", "eq.layer1.nor"):
+            reg.register(a_sig)
+            reg.register(b_sig)
+            return [reg.get_id(a_sig), reg.get_id(b_sig)]
+        if sub == "eq":
+            return [
+                reg.register(f"{cmp_prefix}.bit{i}.eq.layer1.and"),
+                reg.register(f"{cmp_prefix}.bit{i}.eq.layer1.nor"),
+            ]
+
+    m = re.match(r"^cascade\.eq_prefix\.bit(\d+)$", suffix)
+    if m:
+        i = int(m.group(1))
+        return [reg.register(f"{cmp_prefix}.bit{j}.eq") for j in range(i)]
+
+    m = re.match(r"^cascade\.(gt|lt)\.bit(\d+)$", suffix)
+    if m:
+        kind = m.group(1)
+        i = int(m.group(2))
+        return [
+            reg.register(f"{cmp_prefix}.cascade.eq_prefix.bit{i}"),
+            reg.register(f"{cmp_prefix}.bit{i}.{kind}"),
+        ]
+    return None
+
+
+def _infer_compare_final(gate: str, reg: SignalRegistry, cmp_prefix: str,
+                         out_gt: str, out_lt: str, out_ge: str, out_le: str,
+                         out_eq: str, bits: int) -> List[int] | None:
+    """Inputs for the final outputs of an add_bit_cascade_compare emit:
+    out_gt/out_lt are N-input ORs; out_eq is N-input AND; ge/le are
+    NOT-then-buffer chains over lt/gt.
+    """
+    if gate == out_gt:
+        return ([reg.register(f"{cmp_prefix}.bit0.gt")]
+                + [reg.register(f"{cmp_prefix}.cascade.gt.bit{i}") for i in range(1, bits)])
+    if gate == out_lt:
+        return ([reg.register(f"{cmp_prefix}.bit0.lt")]
+                + [reg.register(f"{cmp_prefix}.cascade.lt.bit{i}") for i in range(1, bits)])
+    if gate == out_eq:
+        return [reg.register(f"{cmp_prefix}.bit{i}.eq") for i in range(bits)]
+    if gate == f"{out_ge}.not_lt":
+        return [reg.register(out_lt)]
+    if gate == out_ge:
+        return [reg.register(f"{out_ge}.not_lt")]
+    if gate == f"{out_le}.not_gt":
+        return [reg.register(out_gt)]
+    if gate == out_le:
+        return [reg.register(f"{out_le}.not_gt")]
+    return None
+
+
+def _infer_threshold_computer_bit_cascade(gate: str, reg: SignalRegistry) -> List[int] | None:
+    """Match every bit-cascade location used in this codebase: integer
+    comparators, integer division stage cmps, float magnitude comparators,
+    float exp_cmp, and float division mantissa cmps.
+    """
+    # Integer arithmetic.cmp{N}bit.* + the public greaterthan/lessthan/etc.
+    m = re.match(r"^arithmetic\.cmp(\d+)bit\..+", gate)
+    if m:
+        bits = int(m.group(1))
+        return _infer_bit_cascade(gate, reg, f"arithmetic.cmp{bits}bit", "$a[{}]", "$b[{}]")
+
+    m = re.match(r"^arithmetic\.(greaterthan|lessthan|equality|greaterorequal|lessorequal)(\d+)bit(\.not_lt|\.not_gt)?$", gate)
+    if m:
+        bits = int(m.group(2))
+        return _infer_compare_final(
+            gate, reg, f"arithmetic.cmp{bits}bit",
+            f"arithmetic.greaterthan{bits}bit", f"arithmetic.lessthan{bits}bit",
+            f"arithmetic.greaterorequal{bits}bit", f"arithmetic.lessorequal{bits}bit",
+            f"arithmetic.equality{bits}bit", bits,
+        )
+
+    # Integer division stage cmps: alu.alu{N}bit.div.stage{S}.cmp_bc.* + .cmp + .cmp.not_lt
+    m = re.match(r"^alu\.alu(\d+)bit\.div\.stage(\d+)\.cmp_bc\..+", gate)
+    if m:
+        bits, stage = int(m.group(1)), int(m.group(2))
+        cp = f"alu.alu{bits}bit.div.stage{stage}.cmp_bc"
+        return _infer_bit_cascade(gate, reg, cp, "$rem[{}]", "$div[{}]")
+
+    m = re.match(r"^alu\.alu(\d+)bit\.div\.stage(\d+)\.cmp(\.not_lt)?$", gate)
+    if m:
+        bits, stage = int(m.group(1)), int(m.group(2))
+        cp = f"alu.alu{bits}bit.div.stage{stage}.cmp_bc"
+        cmp_name = f"alu.alu{bits}bit.div.stage{stage}.cmp"
+        if gate == f"{cmp_name}.not_lt":
+            return [reg.register(f"{cp}.lt")]
+        if gate == cmp_name:
+            return [reg.register(f"{cmp_name}.not_lt")]
+
+    # Float magnitude comparators: float{16,32}.cmp.mag_bc.* + final outputs
+    m = re.match(r"^(float16|float32)\.cmp\.mag_bc\..+", gate)
+    if m:
+        family = m.group(1)
+        bits = 15 if family == "float16" else 31
+        return _infer_bit_cascade(gate, reg, f"{family}.cmp.mag_bc",
+                                  f"${family}_mag_a[{{}}]", f"${family}_mag_b[{{}}]")
+
+    m = re.match(r"^(float16|float32)\.cmp\.(mag_a_gt_b|mag_a_lt_b|mag_a_ge_b|mag_a_le_b|mag_eq\.and)(\.not_lt|\.not_gt)?$", gate)
+    if m:
+        family = m.group(1)
+        bits = 15 if family == "float16" else 31
+        return _infer_compare_final(
+            gate, reg, f"{family}.cmp.mag_bc",
+            f"{family}.cmp.mag_a_gt_b", f"{family}.cmp.mag_a_lt_b",
+            f"{family}.cmp.mag_a_ge_b", f"{family}.cmp.mag_a_le_b",
+            f"{family}.cmp.mag_eq.and", bits,
+        )
+
+    # Float add exp_cmp: float{16,32}.add.exp_cmp_bc.* + a_gt_b / a_lt_b
+    m = re.match(r"^(float16|float32)\.add\.exp_cmp_bc\..+", gate)
+    if m:
+        family = m.group(1)
+        bits = 5 if family == "float16" else 8
+        return _infer_bit_cascade(gate, reg, f"{family}.add.exp_cmp_bc",
+                                  f"${family}_exp_a[{{}}]", f"${family}_exp_b[{{}}]")
+
+    m = re.match(r"^(float16|float32)\.add\.exp_cmp\.(a_gt_b|a_lt_b)$", gate)
+    if m:
+        family = m.group(1)
+        bits = 5 if family == "float16" else 8
+        cp = f"{family}.add.exp_cmp_bc"
+        kind = m.group(2)
+        short = "gt" if kind == "a_gt_b" else "lt"
+        return ([reg.register(f"{cp}.bit0.{short}")]
+                + [reg.register(f"{cp}.cascade.{short}.bit{i}") for i in range(1, bits)])
+
+    # Float div mantissa stage cmps
+    m = re.match(r"^(float16|float32)\.div\.mant_div\.stage(\d+)\.cmp_bc\..+", gate)
+    if m:
+        family, stage = m.group(1), int(m.group(2))
+        cp = f"{family}.div.mant_div.stage{stage}.cmp_bc"
+        return _infer_bit_cascade(gate, reg, cp, "$mant_rem[{}]", "$mant_div[{}]")
+
+    m = re.match(r"^(float16|float32)\.div\.mant_div\.stage(\d+)\.cmp(\.not_lt)?$", gate)
+    if m:
+        family, stage = m.group(1), int(m.group(2))
+        cp = f"{family}.div.mant_div.stage{stage}.cmp_bc"
+        cmp_name = f"{family}.div.mant_div.stage{stage}.cmp"
+        if gate == f"{cmp_name}.not_lt":
+            return [reg.register(f"{cp}.lt")]
+        if gate == cmp_name:
+            return [reg.register(f"{cmp_name}.not_lt")]
+
+    # Modular ternary: per-multiple equality detectors + final OR
+    m = re.match(r"^modular\.mod(\d+)\.eq\.k(\d+)\.bit(\d+)\.match$", gate)
+    if m:
+        bit_i = int(m.group(3))
+        sig = f"$x[{bit_i}]"
+        reg.register(sig)
+        return [reg.get_id(sig)]
+    m = re.match(r"^modular\.mod(\d+)\.eq\.k(\d+)\.all$", gate)
+    if m:
+        mod, k = int(m.group(1)), int(m.group(2))
+        prefix = f"modular.mod{mod}.eq.k{k}"
+        return [reg.register(f"{prefix}.bit{i}.match") for i in range(8)]
+    m = re.match(r"^modular\.mod(\d+)$", gate)
+    if m:
+        mod = int(m.group(1))
+        multiples = list(range(0, 256, mod))
+        return [reg.register(f"modular.mod{mod}.eq.k{k}.all") for k in multiples]
+
+    return None
+
+
 def infer_inputs_for_gate(gate: str, reg: SignalRegistry, tensors: Dict[str, torch.Tensor]) -> List[int]:
     if gate.startswith('manifest.'):
         return []
+    # Bit-cascade comparators (integer + float + div) and ternary modular detectors.
+    # These are the gates emitted by add_bit_cascade_compare and the ternary
+    # modular rebuild in quantize.py; cover them up front so they don't fall
+    # through to the generic per-family handlers below.
+    bc = _infer_threshold_computer_bit_cascade(gate, reg)
+    if bc is not None:
+        return bc
     if gate.startswith('boolean.'):
         return infer_boolean_inputs(gate, reg)
     if gate.startswith('arithmetic.'):