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@@ -35,3 +35,4 @@ saved_model/**/* filter=lfs diff=lfs merge=lfs -text
 *tfevents* filter=lfs diff=lfs merge=lfs -text
 __pycache__/iron_eval.cpython-312.pyc filter=lfs diff=lfs merge=lfs -text
 __pycache__/iron_eval.cpython-311.pyc filter=lfs diff=lfs merge=lfs -text
+eval/__pycache__/comprehensive_eval.cpython-312.pyc filter=lfs diff=lfs merge=lfs -text

eval/__pycache__/comprehensive_eval.cpython-312.pyc

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+version https://git-lfs.github.com/spec/v1
+oid sha256:8ccad37bd62a22e29a842384c0ed5a23cadfde2f662aa979bd946c67f8385b01
+size 165009

generate_routing.py

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+"""
+Generate routing.json for the 8-bit threshold computer.
+Maps each gate to its input sources.
+"""
+
+import json
+from safetensors import safe_open
+from collections import defaultdict
+
+def get_all_gates(tensors_path):
+    """Extract all unique gate paths from tensors file."""
+    gates = set()
+    with safe_open(tensors_path, framework='pt') as f:
+        for key in f.keys():
+            if key.endswith('.weight'):
+                gates.add(key[:-7])
+            elif key.endswith('.bias'):
+                gates.add(key[:-5])
+            else:
+                gates.add(key)
+    return sorted(gates)
+
+
+def generate_boolean_routing():
+    """Generate routing for boolean gates."""
+    routing = {}
+
+    # Single-layer 2-input gates
+    for gate in ['and', 'or', 'nand', 'nor', 'implies']:
+        routing[f'boolean.{gate}'] = {
+            'inputs': ['$a', '$b'],
+            'type': 'single_layer'
+        }
+
+    # NOT gate (1 input)
+    routing['boolean.not'] = {
+        'inputs': ['$a'],
+        'type': 'single_layer'
+    }
+
+    # Two-layer gates (XOR, XNOR, BIIMPLIES)
+    for gate in ['xor', 'xnor', 'biimplies']:
+        routing[f'boolean.{gate}'] = {
+            'inputs': ['$a', '$b'],
+            'type': 'two_layer_neuron',
+            'internal': {
+                'layer1.neuron1': ['$a', '$b'],
+                'layer1.neuron2': ['$a', '$b'],
+                'layer2': ['layer1.neuron1', 'layer1.neuron2']
+            },
+            'output': 'layer2'
+        }
+
+    return routing
+
+
+def generate_arithmetic_halfadder_routing():
+    """Generate routing for half adder."""
+    return {
+        'arithmetic.halfadder': {
+            'inputs': ['$a', '$b'],
+            'type': 'composite',
+            'internal': {
+                # Sum is XOR(a, b)
+                'sum.layer1.or': ['$a', '$b'],
+                'sum.layer1.nand': ['$a', '$b'],
+                'sum.layer2': ['sum.layer1.or', 'sum.layer1.nand'],
+                # Carry is AND(a, b)
+                'carry': ['$a', '$b']
+            },
+            'outputs': {
+                'sum': 'sum.layer2',
+                'carry': 'carry'
+            }
+        }
+    }
+
+
+def generate_arithmetic_fulladder_routing():
+    """Generate routing for full adder."""
+    return {
+        'arithmetic.fulladder': {
+            'inputs': ['$a', '$b', '$cin'],
+            'type': 'composite',
+            'internal': {
+                # HA1: a + b
+                'ha1.sum.layer1.or': ['$a', '$b'],
+                'ha1.sum.layer1.nand': ['$a', '$b'],
+                'ha1.sum.layer2': ['ha1.sum.layer1.or', 'ha1.sum.layer1.nand'],
+                'ha1.carry': ['$a', '$b'],
+                # HA2: ha1.sum + cin
+                'ha2.sum.layer1.or': ['ha1.sum.layer2', '$cin'],
+                'ha2.sum.layer1.nand': ['ha1.sum.layer2', '$cin'],
+                'ha2.sum.layer2': ['ha2.sum.layer1.or', 'ha2.sum.layer1.nand'],
+                'ha2.carry': ['ha1.sum.layer2', '$cin'],
+                # Carry out
+                'carry_or': ['ha1.carry', 'ha2.carry']
+            },
+            'outputs': {
+                'sum': 'ha2.sum.layer2',
+                'cout': 'carry_or'
+            }
+        }
+    }
+
+
+def generate_ripplecarry_routing(bits):
+    """Generate routing for N-bit ripple carry adder."""
+    name = f'arithmetic.ripplecarry{bits}bit'
+    internal = {}
+
+    for i in range(bits):
+        prefix = f'fa{i}'
+        if i == 0:
+            cin = '#0'  # First carry in is 0
+        else:
+            cin = f'fa{i-1}.carry_or'
+
+        a_bit = f'$a[{i}]'
+        b_bit = f'$b[{i}]'
+
+        # Full adder structure
+        internal[f'{prefix}.ha1.sum.layer1.or'] = [a_bit, b_bit]
+        internal[f'{prefix}.ha1.sum.layer1.nand'] = [a_bit, b_bit]
+        internal[f'{prefix}.ha1.sum.layer2'] = [f'{prefix}.ha1.sum.layer1.or', f'{prefix}.ha1.sum.layer1.nand']
+        internal[f'{prefix}.ha1.carry'] = [a_bit, b_bit]
+
+        internal[f'{prefix}.ha2.sum.layer1.or'] = [f'{prefix}.ha1.sum.layer2', cin]
+        internal[f'{prefix}.ha2.sum.layer1.nand'] = [f'{prefix}.ha1.sum.layer2', cin]
+        internal[f'{prefix}.ha2.sum.layer2'] = [f'{prefix}.ha2.sum.layer1.or', f'{prefix}.ha2.sum.layer1.nand']
+        internal[f'{prefix}.ha2.carry'] = [f'{prefix}.ha1.sum.layer2', cin]
+
+        internal[f'{prefix}.carry_or'] = [f'{prefix}.ha1.carry', f'{prefix}.ha2.carry']
+
+    outputs = {f'sum[{i}]': f'fa{i}.ha2.sum.layer2' for i in range(bits)}
+    outputs['cout'] = f'fa{bits-1}.carry_or'
+
+    return {
+        name: {
+            'inputs': [f'$a[0:{bits-1}]', f'$b[0:{bits-1}]'],
+            'type': 'ripple_carry',
+            'internal': internal,
+            'outputs': outputs
+        }
+    }
+
+
+def generate_comparator_routing():
+    """Generate routing for 8-bit comparators."""
+    routing = {}
+
+    # These are single-layer weighted comparators
+    for name in ['greaterthan8bit', 'lessthan8bit', 'greaterorequal8bit', 'lessorequal8bit']:
+        routing[f'arithmetic.{name}'] = {
+            'inputs': ['$a[0:7]', '$b[0:7]'],
+            'type': 'weighted_comparator',
+            'internal': {
+                'comparator': ['$a[0:7]', '$b[0:7]']  # Difference weighted by position
+            },
+            'output': 'comparator'
+        }
+
+    return routing
+
+
+def generate_threshold_routing():
+    """Generate routing for threshold gates."""
+    routing = {}
+
+    # k-of-8 gates
+    for name in ['oneoutof8', 'twooutof8', 'threeoutof8', 'fouroutof8',
+                 'fiveoutof8', 'sixoutof8', 'sevenoutof8', 'alloutof8']:
+        routing[f'threshold.{name}'] = {
+            'inputs': ['$x[0:7]'],
+            'type': 'threshold_gate',
+            'internal': {
+                '': ['$x[0]', '$x[1]', '$x[2]', '$x[3]', '$x[4]', '$x[5]', '$x[6]', '$x[7]']
+            }
+        }
+
+    # Majority/minority
+    routing['threshold.majority'] = {
+        'inputs': ['$x[0:7]'],
+        'type': 'threshold_gate',
+        'internal': {'': ['$x[0:7]']}
+    }
+    routing['threshold.minority'] = {
+        'inputs': ['$x[0:7]'],
+        'type': 'threshold_gate',
+        'internal': {'': ['$x[0:7]']}
+    }
+
+    # atleastk, atmostk, exactlyk for 4-bit
+    routing['threshold.atleastk_4'] = {
+        'inputs': ['$x[0:3]'],
+        'type': 'threshold_gate'
+    }
+    routing['threshold.atmostk_4'] = {
+        'inputs': ['$x[0:3]'],
+        'type': 'threshold_gate'
+    }
+    routing['threshold.exactlyk_4'] = {
+        'inputs': ['$x[0:3]'],
+        'type': 'composite',
+        'internal': {
+            'atleast': ['$x[0:3]'],
+            'atmost': ['$x[0:3]'],
+            'and': ['atleast', 'atmost']
+        },
+        'output': 'and'
+    }
+
+    return routing
+
+
+def generate_modular_routing():
+    """Generate routing for modular arithmetic circuits."""
+    routing = {}
+
+    # Powers of 2 are single-layer
+    for mod in [2, 4, 8]:
+        routing[f'modular.mod{mod}'] = {
+            'inputs': ['$x[0:7]'],
+            'type': 'single_layer',
+            'internal': {'': ['$x[0:7]']}
+        }
+
+    # Non-powers of 2 use 3-layer detection
+    for mod in [3, 5, 6, 7, 9, 10, 11, 12]:
+        # Count detectors (values divisible by mod in range 0-255)
+        num_detectors = len([v for v in range(256) if v % mod == 0])
+
+        internal = {}
+        layer2_inputs = []
+
+        for idx in range(num_detectors):
+            internal[f'layer1.geq{idx}'] = ['$x[0:7]']
+            internal[f'layer1.leq{idx}'] = ['$x[0:7]']
+            internal[f'layer2.eq{idx}'] = [f'layer1.geq{idx}', f'layer1.leq{idx}']
+            layer2_inputs.append(f'layer2.eq{idx}')
+
+        internal['layer3.or'] = layer2_inputs
+
+        routing[f'modular.mod{mod}'] = {
+            'inputs': ['$x[0:7]'],
+            'type': 'modular_detector',
+            'internal': internal,
+            'output': 'layer3.or'
+        }
+
+    return routing
+
+
+def generate_equality_routing():
+    """Generate routing for 8-bit equality circuit."""
+    internal = {}
+    xnor_outputs = []
+
+    for i in range(8):
+        # Each XNOR compares bit i of a and b
+        internal[f'xnor{i}.layer1.and'] = [f'$a[{i}]', f'$b[{i}]']
+        internal[f'xnor{i}.layer1.nor'] = [f'$a[{i}]', f'$b[{i}]']
+        internal[f'xnor{i}.layer2'] = [f'xnor{i}.layer1.and', f'xnor{i}.layer1.nor']
+        xnor_outputs.append(f'xnor{i}.layer2')
+
+    # Final AND of all XNORs
+    internal['and'] = xnor_outputs
+
+    return {
+        'arithmetic.equality8bit': {
+            'inputs': ['$a[0:7]', '$b[0:7]'],
+            'type': 'equality',
+            'internal': internal,
+            'output': 'and'
+        }
+    }
+
+
+def generate_neg8bit_routing():
+    """Generate routing for 8-bit negation (two's complement)."""
+    internal = {}
+
+    # NOT gates for each bit
+    for i in range(8):
+        internal[f'not{i}'] = [f'$x[{i}]']
+
+    # Add 1 using half/full adders (simplified view)
+    # Bit 0: XOR(not0, 1) = NOT(not0) = x0, carry = not0
+    internal['sum0'] = ['not0']  # Actually just passes through for +1
+    internal['carry0'] = ['not0']
+
+    # Remaining bits use XOR with carry propagation
+    for i in range(1, 8):
+        prev_carry = f'carry{i-1}' if i > 1 else 'carry0'
+        internal[f'xor{i}.layer1.nand'] = [f'not{i}', prev_carry]
+        internal[f'xor{i}.layer1.or'] = [f'not{i}', prev_carry]
+        internal[f'xor{i}.layer2'] = [f'xor{i}.layer1.nand', f'xor{i}.layer1.or']
+        internal[f'and{i}'] = [f'not{i}', prev_carry]
+
+    internal['overflow'] = ['not7', 'carry6'] if 8 > 1 else ['not0']
+
+    return {
+        'arithmetic.neg8bit': {
+            'inputs': ['$x[0:7]'],
+            'type': 'negation',
+            'internal': internal,
+            'outputs': {f'out[{i}]': f'xor{i}.layer2' if i > 0 else 'sum0' for i in range(8)}
+        }
+    }
+
+
+def generate_multiplier2x2_routing():
+    """Generate routing for 2x2 multiplier."""
+    internal = {}
+
+    # Partial products (AND gates)
+    for a in range(2):
+        for b in range(2):
+            internal[f'and{a}{b}'] = [f'$a[{a}]', f'$b[{b}]']
+
+    # Product bits:
+    # p0 = a0*b0
+    # p1 = a1*b0 + a0*b1
+    # p2 = a1*b1 + carry from p1
+    # p3 = carry from p2
+
+    # Half adder for bit 1
+    internal['ha0.sum.layer1.or'] = ['and10', 'and01']
+    internal['ha0.sum.layer1.nand'] = ['and10', 'and01']
+    internal['ha0.sum.layer2'] = ['ha0.sum.layer1.or', 'ha0.sum.layer1.nand']
+    internal['ha0.carry'] = ['and10', 'and01']
+
+    # Full adder for bit 2
+    internal['fa0.ha1.sum.layer1.or'] = ['and11', 'ha0.carry']
+    internal['fa0.ha1.sum.layer1.nand'] = ['and11', 'ha0.carry']
+    internal['fa0.ha1.sum.layer2'] = ['fa0.ha1.sum.layer1.or', 'fa0.ha1.sum.layer1.nand']
+    internal['fa0.ha1.carry'] = ['and11', 'ha0.carry']
+    internal['fa0.ha2.sum.layer1.or'] = ['fa0.ha1.sum.layer2', '#0']
+    internal['fa0.ha2.sum.layer1.nand'] = ['fa0.ha1.sum.layer2', '#0']
+    internal['fa0.ha2.sum.layer2'] = ['fa0.ha2.sum.layer1.or', 'fa0.ha2.sum.layer1.nand']
+    internal['fa0.ha2.carry'] = ['fa0.ha1.sum.layer2', '#0']
+    internal['fa0.carry_or'] = ['fa0.ha1.carry', 'fa0.ha2.carry']
+
+    return {
+        'arithmetic.multiplier2x2': {
+            'inputs': ['$a[0:1]', '$b[0:1]'],
+            'type': 'multiplier',
+            'internal': internal,
+            'outputs': {
+                'p[0]': 'and00',
+                'p[1]': 'ha0.sum.layer2',
+                'p[2]': 'fa0.ha2.sum.layer2',
+                'p[3]': 'fa0.carry_or'
+            }
+        }
+    }
+
+
+def generate_pattern_routing():
+    """Generate routing for pattern recognition circuits."""
+    routing = {}
+
+    # Simple threshold-based patterns
+    for name in ['popcount', 'allzeros', 'allones', 'leadingones', 'trailingones', 'runlength']:
+        routing[f'pattern_recognition.{name}'] = {
+            'inputs': ['$x[0:7]'],
+            'type': 'weighted_sum'
+        }
+
+    # One-hot detector (atleast1 AND atmost1)
+    routing['pattern_recognition.onehotdetector'] = {
+        'inputs': ['$x[0:7]'],
+        'type': 'composite',
+        'internal': {
+            'atleast1': ['$x[0:7]'],
+            'atmost1': ['$x[0:7]'],
+            'and': ['atleast1', 'atmost1']
+        },
+        'output': 'and'
+    }
+
+    # Alternating pattern (2 pattern matchers)
+    routing['pattern_recognition.alternating8bit'] = {
+        'inputs': ['$x[0:7]'],
+        'type': 'composite',
+        'internal': {
+            'pattern1': ['$x[0:7]'],  # 10101010
+            'pattern2': ['$x[0:7]']   # 01010101
+        }
+    }
+
+    # Hamming distance (XOR + popcount)
+    routing['pattern_recognition.hammingdistance8bit'] = {
+        'inputs': ['$a[0:7]', '$b[0:7]'],
+        'type': 'composite',
+        'internal': {
+            'xor': ['$a[0:7]', '$b[0:7]'],
+            'popcount': ['xor']
+        },
+        'output': 'popcount'
+    }
+
+    # Symmetry detector (4 XNORs + AND)
+    routing['pattern_recognition.symmetry8bit'] = {
+        'inputs': ['$x[0:7]'],
+        'type': 'composite',
+        'internal': {
+            'xnor0': ['$x[0]', '$x[7]'],
+            'xnor1': ['$x[1]', '$x[6]'],
+            'xnor2': ['$x[2]', '$x[5]'],
+            'xnor3': ['$x[3]', '$x[4]'],
+            'and': ['xnor0', 'xnor1', 'xnor2', 'xnor3']
+        },
+        'output': 'and'
+    }
+
+    return routing
+
+
+def generate_manifest_routing():
+    """Generate routing for manifest (constants, no actual routing)."""
+    return {
+        'manifest.alu_operations': {'type': 'constant', 'value': 16},
+        'manifest.flags': {'type': 'constant', 'value': 4},
+        'manifest.instruction_width': {'type': 'constant', 'value': 16},
+        'manifest.memory_bytes': {'type': 'constant', 'value': 256},
+        'manifest.pc_width': {'type': 'constant', 'value': 8},
+        'manifest.register_width': {'type': 'constant', 'value': 8},
+        'manifest.registers': {'type': 'constant', 'value': 4},
+        'manifest.turing_complete': {'type': 'constant', 'value': 1},
+        'manifest.version': {'type': 'constant', 'value': 1}
+    }
+
+
+def generate_multiplier8x8_routing():
+    """Generate routing for 8x8 multiplier."""
+    internal = {}
+
+    # Partial products: 64 AND gates (8x8)
+    for row in range(8):
+        for col in range(8):
+            internal[f'pp.r{row}.c{col}'] = [f'$a[{col}]', f'$b[{row}]']
+
+    # Stage adders: 7 stages, each stage adds one row of partial products
+    # Stage i adds row i+1, result width grows from 9 to 15 bits
+    for stage in range(7):
+        row_idx = stage + 1
+        shift = row_idx
+        sum_width = 8 + stage + 1  # 9, 10, 11, 12, 13, 14, 15
+
+        for bit in range(sum_width):
+            prefix = f'stage{stage}.bit{bit}'
+
+            # Determine inputs for this bit position
+            if bit < shift:
+                # Below shift: comes from previous result only
+                if stage == 0:
+                    prev = f'pp.r0.c{bit}' if bit < 8 else '#0'
+                else:
+                    prev = f'stage{stage-1}.bit{bit}.ha2.sum' if bit < 8 + stage else '#0'
+                pp_bit = '#0'
+            elif bit <= shift + 7:
+                # In range of partial products
+                if stage == 0:
+                    prev = f'pp.r0.c{bit}' if bit < 8 else '#0'
+                else:
+                    prev = f'stage{stage-1}.bit{bit}.ha2.sum' if bit < 8 + stage else f'stage{stage-1}.bit{8+stage-1}.carry_or'
+                pp_bit = f'pp.r{row_idx}.c{bit-shift}'
+            else:
+                # Above partial product range
+                prev = f'stage{stage-1}.bit{bit-1}.carry_or' if stage > 0 else '#0'
+                pp_bit = '#0'
+
+            # Carry from previous bit
+            if bit == 0:
+                cin = '#0'
+            else:
+                cin = f'stage{stage}.bit{bit-1}.carry_or'
+
+            # Full adder structure
+            internal[f'{prefix}.ha1.sum.layer1.or'] = [prev, pp_bit]
+            internal[f'{prefix}.ha1.sum.layer1.nand'] = [prev, pp_bit]
+            internal[f'{prefix}.ha1.sum.layer2'] = [f'{prefix}.ha1.sum.layer1.or', f'{prefix}.ha1.sum.layer1.nand']
+            internal[f'{prefix}.ha1.carry'] = [prev, pp_bit]
+
+            internal[f'{prefix}.ha2.sum.layer1.or'] = [f'{prefix}.ha1.sum.layer2', cin]
+            internal[f'{prefix}.ha2.sum.layer1.nand'] = [f'{prefix}.ha1.sum.layer2', cin]
+            internal[f'{prefix}.ha2.sum.layer2'] = [f'{prefix}.ha2.sum.layer1.or', f'{prefix}.ha2.sum.layer1.nand']
+            internal[f'{prefix}.ha2.carry'] = [f'{prefix}.ha1.sum.layer2', cin]
+
+            internal[f'{prefix}.carry_or'] = [f'{prefix}.ha1.carry', f'{prefix}.ha2.carry']
+
+    # Outputs: 16 bits
+    outputs = {}
+    for i in range(8):
+        outputs[f'p[{i}]'] = f'pp.r0.c{i}' if i < 8 else f'stage6.bit{i}.ha2.sum.layer2'
+    for i in range(8, 16):
+        outputs[f'p[{i}]'] = f'stage6.bit{i}.ha2.sum.layer2' if i < 15 else 'stage6.bit14.carry_or'
+
+    return {
+        'arithmetic.multiplier8x8': {
+            'inputs': ['$a[0:7]', '$b[0:7]'],
+            'type': 'multiplier',
+            'internal': internal,
+            'outputs': outputs
+        }
+    }
+
+
+def generate_div8bit_routing():
+    """Generate routing for 8-bit restoring division."""
+    internal = {}
+
+    for stage in range(8):
+        prefix = f'stage{stage}'
+
+        # Previous remainder (from previous stage or initial 0)
+        if stage == 0:
+            prev_rem = ['#0'] * 8
+        else:
+            prev_rem = [f'stage{stage-1}.mux{i}' for i in range(8)]
+
+        # Shift left and bring in dividend bit
+        for bit in range(8):
+            if bit < 7:
+                internal[f'{prefix}.shift.bit{bit}'] = [prev_rem[bit + 1]]
+            else:
+                internal[f'{prefix}.shift.bit{bit}'] = [f'$dividend[{7-stage}]']
+
+        # OR dividend bit into LSB
+        internal[f'{prefix}.or_dividend'] = [f'{prefix}.shift.bit7', f'$dividend[{7-stage}]']
+
+        # NOT divisor for subtraction
+        for bit in range(8):
+            internal[f'{prefix}.sub.notd{bit}'] = [f'$divisor[{bit}]']
+
+        # Subtractor: 8 full adders
+        for bit in range(8):
+            fa_prefix = f'{prefix}.sub.fa{bit}'
+            shifted = f'{prefix}.shift.bit{bit}'
+            notd = f'{prefix}.sub.notd{bit}'
+
+            if bit == 0:
+                cin = '#1'  # +1 for two's complement
+            else:
+                cin = f'{prefix}.sub.fa{bit-1}.or_carry'
+
+            # XOR1: shifted ^ notd
+            internal[f'{fa_prefix}.xor1.layer1.nand'] = [shifted, notd]
+            internal[f'{fa_prefix}.xor1.layer1.or'] = [shifted, notd]
+            internal[f'{fa_prefix}.xor1.layer2'] = [f'{fa_prefix}.xor1.layer1.nand', f'{fa_prefix}.xor1.layer1.or']
+
+            # XOR2: xor1 ^ cin
+            internal[f'{fa_prefix}.xor2.layer1.nand'] = [f'{fa_prefix}.xor1.layer2', cin]
+            internal[f'{fa_prefix}.xor2.layer1.or'] = [f'{fa_prefix}.xor1.layer2', cin]
+            internal[f'{fa_prefix}.xor2.layer2'] = [f'{fa_prefix}.xor2.layer1.nand', f'{fa_prefix}.xor2.layer1.or']
+
+            # AND1, AND2, OR_carry
+            internal[f'{fa_prefix}.and1'] = [shifted, notd]
+            internal[f'{fa_prefix}.and2'] = [f'{fa_prefix}.xor1.layer2', cin]
+            internal[f'{fa_prefix}.or_carry'] = [f'{fa_prefix}.and1', f'{fa_prefix}.and2']
+
+        # Comparator: check if subtraction result >= 0 (carry out = 1 means no borrow)
+        internal[f'{prefix}.cmp'] = [f'{prefix}.sub.fa7.or_carry']
+
+        # MUX: select subtracted value if cmp=1, else keep original
+        for bit in range(8):
+            mux_prefix = f'{prefix}.mux{bit}'
+            original = f'{prefix}.shift.bit{bit}'
+            subtracted = f'{prefix}.sub.fa{bit}.xor2.layer2'
+            sel = f'{prefix}.cmp'
+
+            internal[f'{mux_prefix}.not_sel'] = [sel]
+            internal[f'{mux_prefix}.and0'] = [original, f'{mux_prefix}.not_sel']
+            internal[f'{mux_prefix}.and1'] = [subtracted, sel]
+            internal[f'{mux_prefix}.or'] = [f'{mux_prefix}.and0', f'{mux_prefix}.and1']
+
+    # Quotient outputs: cmp values from each stage
+    for i in range(8):
+        internal[f'quotient{i}'] = [f'stage{i}.cmp']
+
+    # Remainder outputs: final mux values
+    for i in range(8):
+        internal[f'remainder{i}'] = [f'stage7.mux{i}.or']
+
+    return {
+        'arithmetic.div8bit': {
+            'inputs': ['$dividend[0:7]', '$divisor[0:7]'],
+            'type': 'divider',
+            'internal': internal,
+            'outputs': {
+                'quotient': [f'quotient{i}' for i in range(8)],
+                'remainder': [f'remainder{i}' for i in range(8)]
+            }
+        }
+    }
+
+
+def generate_adc_sbc_routing():
+    """Generate routing for ADC and SBC circuits."""
+    routing = {}
+
+    # ADC: Add with Carry (8-bit)
+    internal_adc = {}
+    for i in range(8):
+        fa_prefix = f'fa{i}'
+        a_bit = f'$a[{i}]'
+        b_bit = f'$b[{i}]'
+        cin = '$cin' if i == 0 else f'fa{i-1}.or_carry'
+
+        internal_adc[f'{fa_prefix}.xor1.layer1.nand'] = [a_bit, b_bit]
+        internal_adc[f'{fa_prefix}.xor1.layer1.or'] = [a_bit, b_bit]
+        internal_adc[f'{fa_prefix}.xor1.layer2'] = [f'{fa_prefix}.xor1.layer1.nand', f'{fa_prefix}.xor1.layer1.or']
+
+        internal_adc[f'{fa_prefix}.xor2.layer1.nand'] = [f'{fa_prefix}.xor1.layer2', cin]
+        internal_adc[f'{fa_prefix}.xor2.layer1.or'] = [f'{fa_prefix}.xor1.layer2', cin]
+        internal_adc[f'{fa_prefix}.xor2.layer2'] = [f'{fa_prefix}.xor2.layer1.nand', f'{fa_prefix}.xor2.layer1.or']
+
+        internal_adc[f'{fa_prefix}.and1'] = [a_bit, b_bit]
+        internal_adc[f'{fa_prefix}.and2'] = [f'{fa_prefix}.xor1.layer2', cin]
+        internal_adc[f'{fa_prefix}.or_carry'] = [f'{fa_prefix}.and1', f'{fa_prefix}.and2']
+
+    routing['arithmetic.adc8bit'] = {
+        'inputs': ['$a[0:7]', '$b[0:7]', '$cin'],
+        'type': 'adder_with_carry',
+        'internal': internal_adc
+    }
+
+    # SBC: Subtract with Carry (A - B - borrow)
+    internal_sbc = {}
+    for i in range(8):
+        internal_sbc[f'notb{i}'] = [f'$b[{i}]']
+
+    for i in range(8):
+        fa_prefix = f'fa{i}'
+        a_bit = f'$a[{i}]'
+        notb_bit = f'notb{i}'
+        cin = '$cin' if i == 0 else f'fa{i-1}.or_carry'
+
+        internal_sbc[f'{fa_prefix}.xor1.layer1.nand'] = [a_bit, notb_bit]
+        internal_sbc[f'{fa_prefix}.xor1.layer1.or'] = [a_bit, notb_bit]
+        internal_sbc[f'{fa_prefix}.xor1.layer2'] = [f'{fa_prefix}.xor1.layer1.nand', f'{fa_prefix}.xor1.layer1.or']
+
+        internal_sbc[f'{fa_prefix}.xor2.layer1.nand'] = [f'{fa_prefix}.xor1.layer2', cin]
+        internal_sbc[f'{fa_prefix}.xor2.layer1.or'] = [f'{fa_prefix}.xor1.layer2', cin]
+        internal_sbc[f'{fa_prefix}.xor2.layer2'] = [f'{fa_prefix}.xor2.layer1.nand', f'{fa_prefix}.xor2.layer1.or']
+
+        internal_sbc[f'{fa_prefix}.and1'] = [a_bit, notb_bit]
+        internal_sbc[f'{fa_prefix}.and2'] = [f'{fa_prefix}.xor1.layer2', cin]
+        internal_sbc[f'{fa_prefix}.or_carry'] = [f'{fa_prefix}.and1', f'{fa_prefix}.and2']
+
+    routing['arithmetic.sbc8bit'] = {
+        'inputs': ['$a[0:7]', '$b[0:7]', '$cin'],
+        'type': 'subtractor_with_carry',
+        'internal': internal_sbc
+    }
+
+    # SUB: Subtract (A - B), carry_in forced to 1
+    internal_sub = {'carry_in': ['#1']}
+    for i in range(8):
+        internal_sub[f'notb{i}'] = [f'$b[{i}]']
+
+    for i in range(8):
+        fa_prefix = f'fa{i}'
+        a_bit = f'$a[{i}]'
+        notb_bit = f'notb{i}'
+        cin = 'carry_in' if i == 0 else f'fa{i-1}.or_carry'
+
+        internal_sub[f'{fa_prefix}.xor1.layer1.nand'] = [a_bit, notb_bit]
+        internal_sub[f'{fa_prefix}.xor1.layer1.or'] = [a_bit, notb_bit]
+        internal_sub[f'{fa_prefix}.xor1.layer2'] = [f'{fa_prefix}.xor1.layer1.nand', f'{fa_prefix}.xor1.layer1.or']
+
+        internal_sub[f'{fa_prefix}.xor2.layer1.nand'] = [f'{fa_prefix}.xor1.layer2', cin]
+        internal_sub[f'{fa_prefix}.xor2.layer1.or'] = [f'{fa_prefix}.xor1.layer2', cin]
+        internal_sub[f'{fa_prefix}.xor2.layer2'] = [f'{fa_prefix}.xor2.layer1.nand', f'{fa_prefix}.xor2.layer1.or']
+
+        internal_sub[f'{fa_prefix}.and1'] = [a_bit, notb_bit]
+        internal_sub[f'{fa_prefix}.and2'] = [f'{fa_prefix}.xor1.layer2', cin]
+        internal_sub[f'{fa_prefix}.or_carry'] = [f'{fa_prefix}.and1', f'{fa_prefix}.and2']
+
+    routing['arithmetic.sub8bit'] = {
+        'inputs': ['$a[0:7]', '$b[0:7]'],
+        'type': 'subtractor',
+        'internal': internal_sub
+    }
+
+    # CMP: Compare (like SUB but only sets flags)
+    internal_cmp = {}
+    for i in range(8):
+        internal_cmp[f'notb{i}'] = [f'$b[{i}]']
+
+    for i in range(8):
+        fa_prefix = f'fa{i}'
+        a_bit = f'$a[{i}]'
+        notb_bit = f'notb{i}'
+        cin = '#1' if i == 0 else f'fa{i-1}.or_carry'
+
+        internal_cmp[f'{fa_prefix}.xor1.layer1.nand'] = [a_bit, notb_bit]
+        internal_cmp[f'{fa_prefix}.xor1.layer1.or'] = [a_bit, notb_bit]
+        internal_cmp[f'{fa_prefix}.xor1.layer2'] = [f'{fa_prefix}.xor1.layer1.nand', f'{fa_prefix}.xor1.layer1.or']
+
+        internal_cmp[f'{fa_prefix}.xor2.layer1.nand'] = [f'{fa_prefix}.xor1.layer2', cin]
+        internal_cmp[f'{fa_prefix}.xor2.layer1.or'] = [f'{fa_prefix}.xor1.layer2', cin]
+        internal_cmp[f'{fa_prefix}.xor2.layer2'] = [f'{fa_prefix}.xor2.layer1.nand', f'{fa_prefix}.xor2.layer1.or']
+
+        internal_cmp[f'{fa_prefix}.and1'] = [a_bit, notb_bit]
+        internal_cmp[f'{fa_prefix}.and2'] = [f'{fa_prefix}.xor1.layer2', cin]
+        internal_cmp[f'{fa_prefix}.or_carry'] = [f'{fa_prefix}.and1', f'{fa_prefix}.and2']
+
+    # Flags
+    internal_cmp['flags.zero_or'] = [f'fa{i}.xor2.layer2' for i in range(8)]
+    internal_cmp['flags.zero'] = ['flags.zero_or']
+    internal_cmp['flags.negative'] = ['fa7.xor2.layer2']
+    internal_cmp['flags.carry'] = ['fa7.or_carry']
+
+    routing['arithmetic.cmp8bit'] = {
+        'inputs': ['$a[0:7]', '$b[0:7]'],
+        'type': 'compare',
+        'internal': internal_cmp
+    }
+
+    return routing
+
+
+def generate_rotate_routing():
+    """Generate routing for ROL and ROR circuits."""
+    routing = {}
+
+    # ROL: Rotate Left (bit 7 goes to carry, carry goes to bit 0)
+    internal_rol = {}
+    for i in range(8):
+        if i == 0:
+            internal_rol[f'bit{i}'] = ['$cin']
+        else:
+            internal_rol[f'bit{i}'] = [f'$x[{i-1}]']
+    internal_rol['cout'] = ['$x[7]']
+
+    routing['arithmetic.rol8bit'] = {
+        'inputs': ['$x[0:7]', '$cin'],
+        'type': 'rotate',
+        'internal': internal_rol
+    }
+
+    # ROR: Rotate Right (bit 0 goes to carry, carry goes to bit 7)
+    internal_ror = {}
+    for i in range(8):
+        if i == 7:
+            internal_ror[f'bit{i}'] = ['$cin']
+        else:
+            internal_ror[f'bit{i}'] = [f'$x[{i+1}]']
+    internal_ror['cout'] = ['$x[0]']
+
+    routing['arithmetic.ror8bit'] = {
+        'inputs': ['$x[0:7]', '$cin'],
+        'type': 'rotate',
+        'internal': internal_ror
+    }
+
+    return routing
+
+
+def generate_combinational_routing():
+    """Generate routing for combinational circuits."""
+    routing = {}
+
+    # 3-to-8 Decoder
+    internal_dec = {}
+    for out in range(8):
+        # out = sel[2]*4 + sel[1]*2 + sel[0]
+        # Each output is AND of (possibly inverted) select lines
+        internal_dec[f'out{out}'] = ['$sel[0]', '$sel[1]', '$sel[2]']
+
+    routing['combinational.decoder3to8'] = {
+        'inputs': ['$sel[0:2]'],
+        'type': 'decoder',
+        'internal': internal_dec
+    }
+
+    # 8-to-3 Encoder
+    internal_enc = {}
+    for bit in range(3):
+        internal_enc[f'bit{bit}'] = ['$x[0:7]']
+
+    routing['combinational.encoder8to3'] = {
+        'inputs': ['$x[0:7]'],
+        'type': 'encoder',
+        'internal': internal_enc
+    }
+
+    # 2-to-1 MUX
+    routing['combinational.multiplexer2to1'] = {
+        'inputs': ['$a', '$b', '$sel'],
+        'type': 'mux',
+        'internal': {
+            'not_s': ['$sel'],
+            'and0': ['$a', 'not_s'],
+            'and1': ['$b', '$sel'],
+            'or': ['and0', 'and1']
+        },
+        'output': 'or'
+    }
+
+    # 4-to-1 MUX
+    routing['combinational.multiplexer4to1'] = {
+        'inputs': ['$x[0:3]', '$sel[0:1]'],
+        'type': 'mux',
+        'internal': {'select': ['$x[0:3]', '$sel[0:1]']}
+    }
+
+    # 8-to-1 MUX
+    routing['combinational.multiplexer8to1'] = {
+        'inputs': ['$x[0:7]', '$sel[0:2]'],
+        'type': 'mux',
+        'internal': {'select': ['$x[0:7]', '$sel[0:2]']}
+    }
+
+    # 1-to-2 DEMUX
+    routing['combinational.demultiplexer1to2'] = {
+        'inputs': ['$x', '$sel'],
+        'type': 'demux',
+        'internal': {
+            'and0': ['$x', '$sel'],  # sel inverted internally
+            'and1': ['$x', '$sel']
+        }
+    }
+
+    # 1-to-4 DEMUX
+    routing['combinational.demultiplexer1to4'] = {
+        'inputs': ['$x', '$sel[0:1]'],
+        'type': 'demux',
+        'internal': {'decode': ['$x', '$sel[0:1]']}
+    }
+
+    # 1-to-8 DEMUX
+    routing['combinational.demultiplexer1to8'] = {
+        'inputs': ['$x', '$sel[0:2]'],
+        'type': 'demux',
+        'internal': {'decode': ['$x', '$sel[0:2]']}
+    }
+
+    # Barrel Shifter
+    routing['combinational.barrelshifter8bit'] = {
+        'inputs': ['$x[0:7]', '$shift[0:2]'],
+        'type': 'barrel_shifter',
+        'internal': {'shift': ['$x[0:7]', '$shift[0:2]']}
+    }
+
+    # Priority Encoder
+    routing['combinational.priorityencoder8bit'] = {
+        'inputs': ['$x[0:7]'],
+        'type': 'priority_encoder',
+        'internal': {'priority': ['$x[0:7]']}
+    }
+
+    # Register MUX 4-to-1 (8-bit wide)
+    internal_regmux = {'not_s0': ['$sel[0]'], 'not_s1': ['$sel[1]']}
+    for bit in range(8):
+        for and_idx in range(4):
+            sel0 = 'not_s0' if (and_idx & 1) == 0 else '$sel[0]'
+            sel1 = 'not_s1' if (and_idx & 2) == 0 else '$sel[1]'
+            internal_regmux[f'bit{bit}.and{and_idx}'] = [f'$r{and_idx}[{bit}]', sel0, sel1]
+        internal_regmux[f'bit{bit}.or'] = [f'bit{bit}.and{i}' for i in range(4)]
+
+    routing['combinational.regmux4to1'] = {
+        'inputs': ['$r0[0:7]', '$r1[0:7]', '$r2[0:7]', '$r3[0:7]', '$sel[0:1]'],
+        'type': 'register_mux',
+        'internal': internal_regmux
+    }
+
+    return routing
+
+
+def generate_control_routing():
+    """Generate routing for control circuits."""
+    routing = {}
+
+    # Instruction Decoder (4-bit to 16 one-hot)
+    internal_dec = {}
+    for op in range(16):
+        internal_dec[f'decode{op}'] = ['$opcode[0:3]']
+    for op in range(4):
+        internal_dec[f'not_op{op}'] = [f'$opcode[{op}]']
+    internal_dec['is_alu'] = ['$opcode[0:3]']
+    internal_dec['is_control'] = ['$opcode[0:3]']
+
+    routing['control.decoder'] = {
+        'inputs': ['$opcode[0:3]'],
+        'type': 'instruction_decoder',
+        'internal': internal_dec
+    }
+
+    # Jump (unconditional)
+    internal_jump = {}
+    for bit in range(8):
+        internal_jump[f'bit{bit}'] = [f'$target[{bit}]']
+
+    routing['control.jump'] = {
+        'inputs': ['$target[0:7]'],
+        'type': 'jump',
+        'internal': internal_jump
+    }
+
+    # Conditional Jump (generic template)
+    def make_cond_jump(name, flag):
+        internal = {}
+        for bit in range(8):
+            internal[f'bit{bit}.not_sel'] = [f'${flag}']
+            internal[f'bit{bit}.and_a'] = [f'$pc[{bit}]', f'bit{bit}.not_sel']
+            internal[f'bit{bit}.and_b'] = [f'$target[{bit}]', f'${flag}']
+            internal[f'bit{bit}.or'] = [f'bit{bit}.and_a', f'bit{bit}.and_b']
+
+        routing[f'control.{name}'] = {
+            'inputs': ['$pc[0:7]', '$target[0:7]', f'${flag}'],
+            'type': 'conditional_jump',
+            'internal': internal
+        }
+
+    make_cond_jump('conditionaljump', 'cond')
+    make_cond_jump('jc', 'carry')
+    make_cond_jump('jn', 'negative')
+    make_cond_jump('jz', 'zero')
+    make_cond_jump('jv', 'overflow')
+    make_cond_jump('jnc', 'not_carry')
+    make_cond_jump('jnz', 'not_zero')
+    make_cond_jump('jnv', 'not_overflow')
+    make_cond_jump('jp', 'positive')
+
+    # CALL and RET
+    routing['control.call'] = {
+        'inputs': ['$target[0:7]'],
+        'type': 'call',
+        'internal': {'jump': ['$target[0:7]'], 'push': ['$pc[0:7]']}
+    }
+
+    routing['control.ret'] = {
+        'inputs': ['$stack_top[0:7]'],
+        'type': 'return',
+        'internal': {'jump': ['$stack_top[0:7]'], 'pop': ['#1']}
+    }
+
+    # PUSH and POP
+    routing['control.push'] = {
+        'inputs': ['$value[0:7]', '$sp[0:7]'],
+        'type': 'push',
+        'internal': {'sp_dec': ['$sp[0:7]'], 'store': ['$value[0:7]']}
+    }
+
+    routing['control.pop'] = {
+        'inputs': ['$sp[0:7]'],
+        'type': 'pop',
+        'internal': {'load': ['$sp[0:7]'], 'sp_inc': ['$sp[0:7]']}
+    }
+
+    # SP increment/decrement
+    routing['control.sp_dec'] = {'inputs': ['$sp[0:7]'], 'type': 'sp_dec', 'internal': {'uses': ['$sp[0:7]']}}
+    routing['control.sp_inc'] = {'inputs': ['$sp[0:7]'], 'type': 'sp_inc', 'internal': {'uses': ['$sp[0:7]']}}
+
+    # PC Increment
+    internal_pc_inc = {'sum0': ['$pc[0]'], 'carry0': ['$pc[0]'], 'overflow': ['$pc[7]']}
+    for bit in range(1, 8):
+        prev_carry = f'carry{bit-1}' if bit > 1 else 'carry0'
+        internal_pc_inc[f'xor{bit}.layer1.nand'] = [f'$pc[{bit}]', prev_carry]
+        internal_pc_inc[f'xor{bit}.layer1.or'] = [f'$pc[{bit}]', prev_carry]
+        internal_pc_inc[f'xor{bit}.layer2'] = [f'xor{bit}.layer1.nand', f'xor{bit}.layer1.or']
+        internal_pc_inc[f'and{bit}'] = [f'$pc[{bit}]', prev_carry]
+
+    routing['control.pc_inc'] = {
+        'inputs': ['$pc[0:7]'],
+        'type': 'pc_increment',
+        'internal': internal_pc_inc
+    }
+
+    # PC Load (mux between PC+1 and jump target)
+    internal_pc_load = {'not_jump': ['$jump']}
+    for bit in range(8):
+        internal_pc_load[f'bit{bit}.and_pc'] = [f'$pc_inc[{bit}]', 'not_jump']
+        internal_pc_load[f'bit{bit}.and_jump'] = [f'$target[{bit}]', '$jump']
+        internal_pc_load[f'bit{bit}.or'] = [f'bit{bit}.and_pc', f'bit{bit}.and_jump']
+
+    routing['control.pc_load'] = {
+        'inputs': ['$pc_inc[0:7]', '$target[0:7]', '$jump'],
+        'type': 'pc_load',
+        'internal': internal_pc_load
+    }
+
+    # HALT
+    internal_halt = {'signal': ['$halt']}
+    for flag in ['flag_c', 'flag_n', 'flag_v', 'flag_z']:
+        internal_halt[flag] = [f'${flag}']
+    for bit in range(8):
+        internal_halt[f'pc.bit{bit}'] = [f'$pc[{bit}]']
+        internal_halt[f'value.bit{bit}'] = [f'$value[{bit}]']
+
+    routing['control.halt'] = {
+        'inputs': ['$halt', '$flag_c', '$flag_n', '$flag_v', '$flag_z', '$pc[0:7]', '$value[0:7]'],
+        'type': 'halt',
+        'internal': internal_halt
+    }
+
+    # NOP
+    internal_nop = {'output': ['#1']}
+    for bit in range(8):
+        internal_nop[f'bit{bit}'] = [f'$x[{bit}]']
+    for flag in ['flag_c', 'flag_n', 'flag_v', 'flag_z']:
+        internal_nop[flag] = [f'${flag}']
+
+    routing['control.nop'] = {
+        'inputs': ['$x[0:7]', '$flag_c', '$flag_n', '$flag_v', '$flag_z'],
+        'type': 'nop',
+        'internal': internal_nop
+    }
+
+    return routing
+
+
+def generate_error_detection_routing():
+    """Generate routing for error detection circuits."""
+    routing = {}
+
+    # Even Parity Checker
+    routing['error_detection.evenparitychecker'] = {
+        'inputs': ['$x[0:7]'],
+        'type': 'parity',
+        'internal': {'': ['$x[0:7]']}
+    }
+
+    # Odd Parity Checker
+    routing['error_detection.oddparitychecker'] = {
+        'inputs': ['$x[0:7]'],
+        'type': 'parity',
+        'internal': {
+            'parity': ['$x[0:7]'],
+            'not': ['parity']
+        }
+    }
+
+    # Checksum
+    routing['error_detection.checksum8bit'] = {
+        'inputs': ['$x[0:7]'],
+        'type': 'checksum',
+        'internal': {'sum': ['$x[0:7]']}
+    }
+
+    # CRC
+    routing['error_detection.crc4'] = {
+        'inputs': ['$data[0:7]'],
+        'type': 'crc',
+        'internal': {'divisor': ['#1', '#0', '#0', '#1', '#1']}
+    }
+
+    routing['error_detection.crc8'] = {
+        'inputs': ['$data[0:7]'],
+        'type': 'crc',
+        'internal': {'divisor': ['#1', '#0', '#0', '#0', '#0', '#0', '#1', '#1', '#1']}
+    }
+
+    # Hamming Encode (4 data bits -> 7 code bits)
+    routing['error_detection.hammingencode4bit'] = {
+        'inputs': ['$d[0:3]'],
+        'type': 'hamming_encode',
+        'internal': {
+            'p0': ['$d[0:3]'],
+            'p1': ['$d[0:3]'],
+            'p2': ['$d[0:3]'],
+            'p3': ['$d[0:3]']
+        }
+    }
+
+    # Hamming Decode (7 code bits -> syndrome)
+    routing['error_detection.hammingdecode7bit'] = {
+        'inputs': ['$c[0:6]'],
+        'type': 'hamming_decode',
+        'internal': {
+            's1': ['$c[0:6]'],
+            's2': ['$c[0:6]'],
+            's3': ['$c[0:6]']
+        }
+    }
+
+    # Hamming Syndrome
+    routing['error_detection.hammingsyndrome'] = {
+        'inputs': ['$c[0:6]'],
+        'type': 'hamming_syndrome',
+        'internal': {
+            's1': ['$c[0:6]'],
+            's2': ['$c[0:6]'],
+            's3': ['$c[0:6]']
+        }
+    }
+
+    # Longitudinal Parity
+    routing['error_detection.longitudinalparity'] = {
+        'inputs': ['$data'],
+        'type': 'longitudinal_parity',
+        'internal': {
+            'col_parity': ['$data'],
+            'row_parity': ['$data']
+        }
+    }
+
+    # Parity Checker (3-stage XOR tree)
+    internal_parity_check = {}
+    for stage in range(1, 4):
+        num_xors = 4 if stage == 1 else (2 if stage == 2 else 1)
+        for i in range(num_xors):
+            prefix = f'stage{stage}.xor{i}'
+            internal_parity_check[f'{prefix}.layer1.nand'] = [f'$stage{stage}_in[{2*i}]', f'$stage{stage}_in[{2*i+1}]']
+            internal_parity_check[f'{prefix}.layer1.or'] = [f'$stage{stage}_in[{2*i}]', f'$stage{stage}_in[{2*i+1}]']
+            internal_parity_check[f'{prefix}.layer2'] = [f'{prefix}.layer1.nand', f'{prefix}.layer1.or']
+    internal_parity_check['output.not'] = ['stage3.xor0.layer2']
+
+    routing['error_detection.paritychecker8bit'] = {
+        'inputs': ['$x[0:7]'],
+        'type': 'parity_tree',
+        'internal': internal_parity_check
+    }
+
+    # Parity Generator (same structure as checker)
+    routing['error_detection.paritygenerator8bit'] = {
+        'inputs': ['$x[0:7]'],
+        'type': 'parity_tree',
+        'internal': internal_parity_check.copy()
+    }
+
+    return routing
+
+
+def generate_alu_routing():
+    """Generate routing for ALU circuits."""
+    routing = {}
+
+    # ALU Control (opcode to operation select)
+    internal_ctrl = {}
+    for op in range(16):
+        internal_ctrl[f'op{op}'] = ['$opcode[0:3]']
+
+    routing['alu.alucontrol'] = {
+        'inputs': ['$opcode[0:3]'],
+        'type': 'alu_control',
+        'internal': internal_ctrl
+    }
+
+    # ALU Flags
+    routing['alu.aluflags'] = {
+        'inputs': ['$result[0:7]', '$carry', '$overflow'],
+        'type': 'alu_flags',
+        'internal': {
+            'zero': ['$result[0:7]'],
+            'negative': ['$result[7]'],
+            'carry': ['$carry'],
+            'overflow': ['$overflow']
+        }
+    }
+
+    # ALU 8-bit operations
+    routing['alu.alu8bit.and'] = {
+        'inputs': ['$a[0:7]', '$b[0:7]'],
+        'type': 'bitwise_and',
+        'internal': {f'bit{i}': [f'$a[{i}]', f'$b[{i}]'] for i in range(8)}
+    }
+
+    routing['alu.alu8bit.or'] = {
+        'inputs': ['$a[0:7]', '$b[0:7]'],
+        'type': 'bitwise_or',
+        'internal': {f'bit{i}': [f'$a[{i}]', f'$b[{i}]'] for i in range(8)}
+    }
+
+    routing['alu.alu8bit.not'] = {
+        'inputs': ['$a[0:7]'],
+        'type': 'bitwise_not',
+        'internal': {f'bit{i}': [f'$a[{i}]'] for i in range(8)}
+    }
+
+    # XOR with two-layer structure
+    internal_xor = {}
+    for i in range(8):
+        internal_xor[f'layer1.nand.bit{i}'] = [f'$a[{i}]', f'$b[{i}]']
+        internal_xor[f'layer1.or.bit{i}'] = [f'$a[{i}]', f'$b[{i}]']
+        internal_xor[f'layer2.bit{i}'] = [f'layer1.nand.bit{i}', f'layer1.or.bit{i}']
+
+    routing['alu.alu8bit.xor'] = {
+        'inputs': ['$a[0:7]', '$b[0:7]'],
+        'type': 'bitwise_xor',
+        'internal': internal_xor
+    }
+
+    # Shifts
+    routing['alu.alu8bit.shl'] = {
+        'inputs': ['$a[0:7]'],
+        'type': 'shift_left',
+        'internal': {'': ['$a[0:7]']}
+    }
+
+    routing['alu.alu8bit.shr'] = {
+        'inputs': ['$a[0:7]'],
+        'type': 'shift_right',
+        'internal': {'': ['$a[0:7]']}
+    }
+
+    # ADD (references ripple carry)
+    routing['alu.alu8bit.add'] = {
+        'inputs': ['$a[0:7]', '$b[0:7]'],
+        'type': 'add',
+        'internal': {'': ['$a[0:7]', '$b[0:7]']}
+    }
+
+    # Output MUX
+    routing['alu.alu8bit.output_mux'] = {
+        'inputs': ['$results[0:15]', '$opcode[0:3]'],
+        'type': 'output_mux',
+        'internal': {'': ['$results[0:15]', '$opcode[0:3]']}
+    }
+
+    return routing
+
+
+def generate_div8bit_routing():
+    """Generate routing for 8-bit restoring division circuit."""
+    internal = {}
+
+    for stage in range(8):
+        prefix = f'stage{stage}'
+
+        # Previous stage remainder (or 0 for stage 0)
+        if stage == 0:
+            prev_rem = ['#0'] * 8
+        else:
+            prev_rem = [f'stage{stage-1}.mux{i}.or' for i in range(8)]
+
+        # Dividend bit for this stage (MSB first)
+        dividend_bit = f'$dividend[{7-stage}]'
+
+        # Shift: shift remainder left, bring in dividend bit at LSB
+        for bit in range(8):
+            if bit == 0:
+                internal[f'{prefix}.shift.bit{bit}'] = [dividend_bit]
+            else:
+                internal[f'{prefix}.shift.bit{bit}'] = [prev_rem[bit - 1] if stage > 0 else '#0']
+
+        shifted = [f'{prefix}.shift.bit{i}' for i in range(8)]
+
+        # NOT divisor for two's complement subtraction
+        for bit in range(8):
+            internal[f'{prefix}.sub.notd{bit}'] = [f'$divisor[{bit}]']
+
+        not_divisor = [f'{prefix}.sub.notd{i}' for i in range(8)]
+
+        # Subtractor: 8 full adders computing shifted - divisor (LSB to MSB)
+        carry = '#1'  # +1 for two's complement
+        for bit in range(8):  # LSB (bit 0) to MSB (bit 7)
+            fa_prefix = f'{prefix}.sub.fa{bit}'
+            a = shifted[bit]
+            b = not_divisor[bit]
+
+            internal[f'{fa_prefix}.xor1.layer1.or'] = [a, b]
+            internal[f'{fa_prefix}.xor1.layer1.nand'] = [a, b]
+            internal[f'{fa_prefix}.xor1.layer2'] = [f'{fa_prefix}.xor1.layer1.or', f'{fa_prefix}.xor1.layer1.nand']
+
+            internal[f'{fa_prefix}.xor2.layer1.or'] = [f'{fa_prefix}.xor1.layer2', carry]
+            internal[f'{fa_prefix}.xor2.layer1.nand'] = [f'{fa_prefix}.xor1.layer2', carry]
+            internal[f'{fa_prefix}.xor2.layer2'] = [f'{fa_prefix}.xor2.layer1.or', f'{fa_prefix}.xor2.layer1.nand']
+
+            internal[f'{fa_prefix}.and1'] = [a, b]
+            internal[f'{fa_prefix}.and2'] = [f'{fa_prefix}.xor1.layer2', carry]
+            internal[f'{fa_prefix}.or_carry'] = [f'{fa_prefix}.and1', f'{fa_prefix}.and2']
+
+            carry = f'{fa_prefix}.or_carry'
+
+        sub_result = [f'{prefix}.sub.fa{i}.xor2.layer2' for i in range(8)]
+
+        # Comparator: carry out from MSB (fa7) = 1 means no borrow (shifted >= divisor)
+        internal[f'{prefix}.cmp'] = [f'{prefix}.sub.fa7.or_carry']
+
+        cmp_out = f'{prefix}.cmp'
+
+        # OR dividend (combine shifted LSB with dividend bit)
+        internal[f'{prefix}.or_dividend'] = [shifted[7], dividend_bit]
+
+        # MUX: select sub_result if cmp=1 (no borrow), else shifted
+        for bit in range(8):
+            mux_prefix = f'{prefix}.mux{bit}'
+            internal[f'{mux_prefix}.not_sel'] = [cmp_out]
+            internal[f'{mux_prefix}.and0'] = [shifted[bit], f'{mux_prefix}.not_sel']
+            internal[f'{mux_prefix}.and1'] = [sub_result[bit], cmp_out]
+            internal[f'{mux_prefix}.or'] = [f'{mux_prefix}.and0', f'{mux_prefix}.and1']
+
+    # Output quotient bits (cmp outputs from each stage)
+    for i in range(8):
+        internal[f'quotient{i}'] = [f'stage{i}.cmp']
+
+    # Output remainder bits (final mux outputs)
+    for i in range(8):
+        internal[f'remainder{i}'] = [f'stage7.mux{i}.or']
+
+    outputs = {f'quotient[{i}]': f'quotient{i}' for i in range(8)}
+    outputs.update({f'remainder[{i}]': f'remainder{i}' for i in range(8)})
+
+    return {
+        'arithmetic.div8bit': {
+            'inputs': ['$dividend[0:7]', '$divisor[0:7]'],
+            'type': 'restoring_division',
+            'internal': internal,
+            'outputs': outputs
+        }
+    }
+
+
+def main():
+    routing = {
+        'version': 1,
+        'description': 'Routing information for 8-bit threshold computer',
+        'circuits': {}
+    }
+
+    # Generate routing for each category
+    print('Generating routing...')
+
+    print('  Boolean gates')
+    routing['circuits'].update(generate_boolean_routing())
+
+    print('  Half adder')
+    routing['circuits'].update(generate_arithmetic_halfadder_routing())
+
+    print('  Full adder')
+    routing['circuits'].update(generate_arithmetic_fulladder_routing())
+
+    print('  Ripple carry adders')
+    routing['circuits'].update(generate_ripplecarry_routing(2))
+    routing['circuits'].update(generate_ripplecarry_routing(4))
+    routing['circuits'].update(generate_ripplecarry_routing(8))
+
+    print('  Comparators')
+    routing['circuits'].update(generate_comparator_routing())
+
+    print('  Equality')
+    routing['circuits'].update(generate_equality_routing())
+
+    print('  Negation')
+    routing['circuits'].update(generate_neg8bit_routing())
+
+    print('  2x2 Multiplier')
+    routing['circuits'].update(generate_multiplier2x2_routing())
+
+    print('  8-bit Division')
+    routing['circuits'].update(generate_div8bit_routing())
+
+    print('  Threshold gates')
+    routing['circuits'].update(generate_threshold_routing())
+
+    print('  Modular arithmetic')
+    routing['circuits'].update(generate_modular_routing())
+
+    print('  Pattern recognition')
+    routing['circuits'].update(generate_pattern_routing())
+
+    print('  Manifest')
+    routing['circuits'].update(generate_manifest_routing())
+
+    # Save to file
+    with open('routing.json', 'w') as f:
+        json.dump(routing, f, indent=2)
+
+    print(f'\nGenerated routing for {len(routing["circuits"])} circuits')
+    print('Saved to routing.json')
+
+    # Show what's missing
+    all_gates = get_all_gates('neural_computer.safetensors')
+    covered = set()
+    for circuit_path in routing['circuits'].keys():
+        # Add the circuit itself and all internal gates
+        covered.add(circuit_path)
+        circuit = routing['circuits'][circuit_path]
+        if 'internal' in circuit:
+            for gate in circuit['internal'].keys():
+                if gate:
+                    covered.add(f'{circuit_path}.{gate}')
+
+    missing = [g for g in all_gates if not any(g.startswith(c) for c in routing['circuits'].keys())]
+    if missing:
+        print(f'\nMissing circuits ({len(missing)}):')
+        # Group by category
+        by_cat = defaultdict(list)
+        for g in missing:
+            cat = g.split('.')[0]
+            by_cat[cat].append(g)
+        for cat in sorted(by_cat.keys()):
+            print(f'  {cat}: {len(by_cat[cat])} gates')
+            for g in by_cat[cat][:5]:
+                print(f'    - {g}')
+            if len(by_cat[cat]) > 5:
+                print(f'    ... and {len(by_cat[cat])-5} more')
+
+
+if __name__ == '__main__':
+    main()

routing_schema.md

@@ -0,0 +1,103 @@
+# Routing Schema for 8-bit Threshold Computer
+
+## Overview
+
+The routing file (`routing.json`) defines how gates are interconnected. Each entry maps a gate path to its input sources.
+
+## Schema Format
+
+```json
+{
+  "version": 1,
+  "external_inputs": {
+    "circuit_path": ["input_name", ...]
+  },
+  "routing": {
+    "gate_path": ["source1", "source2", ...]
+  }
+}
+```
+
+## Input Source Types
+
+1. **External input**: `"$input_name"` - Named input to the circuit
+   - Example: `"$a"`, `"$b"`, `"$cin"`
+
+2. **Gate output**: `"path.to.gate"` - Output of another gate
+   - Example: `"ha1.sum"`, `"layer1.or"`
+
+3. **Bit extraction**: `"$input[i]"` - Single bit from multi-bit input
+   - Example: `"$a[0]"` (LSB), `"$a[7]"` (MSB for 8-bit)
+
+4. **Constant**: `"#0"` or `"#1"` - Fixed value
+   - Example: `"#1"` for carry-in in two's complement
+
+5. **Relative reference**: `"../sibling.gate"` - Reference to sibling in hierarchy
+   - Example: `"../fa0.cout"` from fa1
+
+## Circuit Types
+
+### Single-Layer Gates
+Gates with just `.weight` and `.bias`:
+```json
+"boolean.and": ["$a", "$b"]
+```
+
+### Two-Layer Gates (XOR, XNOR)
+Gates decomposed into layer1 + layer2:
+```json
+"boolean.xor.layer1.or": ["$a", "$b"],
+"boolean.xor.layer1.nand": ["$a", "$b"],
+"boolean.xor.layer2": ["layer1.or", "layer1.nand"]
+```
+
+### Hierarchical Circuits
+Complex circuits with sub-components:
+```json
+"arithmetic.fulladder": {
+  "external_inputs": ["$a", "$b", "$cin"],
+  "gates": {
+    "ha1.sum.layer1.or": ["$a", "$b"],
+    "ha1.sum.layer1.nand": ["$a", "$b"],
+    "ha1.sum.layer2": ["ha1.sum.layer1.or", "ha1.sum.layer1.nand"],
+    "ha1.carry": ["$a", "$b"],
+    "ha2.sum.layer1.or": ["ha1.sum", "$cin"],
+    "ha2.sum.layer1.nand": ["ha1.sum", "$cin"],
+    "ha2.sum.layer2": ["ha2.sum.layer1.or", "ha2.sum.layer1.nand"],
+    "ha2.carry": ["ha1.sum", "$cin"],
+    "carry_or": ["ha1.carry", "ha2.carry"]
+  },
+  "outputs": {
+    "sum": "ha2.sum",
+    "cout": "carry_or"
+  }
+}
+```
+
+### Bit-Indexed Circuits
+Circuits operating on multi-bit values:
+```json
+"arithmetic.ripplecarry8bit": {
+  "external_inputs": ["$a[0:7]", "$b[0:7]"],
+  "gates": {
+    "fa0": {"inputs": ["$a[0]", "$b[0]", "#0"], "type": "fulladder"},
+    "fa1": {"inputs": ["$a[1]", "$b[1]", "fa0.cout"], "type": "fulladder"},
+    ...
+  }
+}
+```
+
+## Naming Conventions
+
+- External inputs: `$name` or `$name[bit]`
+- Constants: `#0`, `#1`
+- Internal gates: relative path from circuit root
+- Outputs: named in `outputs` section
+
+## Validation Rules
+
+1. Every gate in routing must exist in tensors file
+2. Every tensor must have routing entry
+3. Input count must match weight dimensions
+4. No circular dependencies (DAG only)
+5. All referenced sources must exist