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README.md

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+---
+license: mit
+tags:
+- threshold-logic
+- neuromorphic
+- computer-architecture
+- coq
+- turing-complete
+---
+
+# 8bit-threshold-computer
+
+A complete 8-bit computer implemented entirely in threshold logic neurons. All computation uses weighted sums with Heaviside step activation - no traditional logic gates.
+
+## Architecture
+
+| Component | Specification |
+|-----------|---------------|
+| Registers | 4 × 8-bit (R0, R1, R2, R3) |
+| Memory | 256 bytes |
+| Program Counter | 8-bit |
+| Instruction Width | 16-bit |
+| ALU Operations | 16 |
+| Status Flags | Z, N, C, V |
+| Circuits | 93 verified |
+| Parameters | 2,377 |
+
+## Instruction Set
+
+### ALU Operations (opcode 0-12)
+| Op | Mnemonic | Operation |
+|----|----------|-----------|
+| 0 | ADD | dest = src1 + src2 |
+| 1 | SUB | dest = src1 - src2 |
+| 2 | AND | dest = src1 & src2 |
+| 3 | OR | dest = src1 \| src2 |
+| 4 | XOR | dest = src1 ^ src2 |
+| 5 | NOT | dest = ~src1 |
+| 6 | SHL | dest = src1 << 1 |
+| 7 | SHR | dest = src1 >> 1 |
+| 8 | INC | dest = src1 + 1 |
+| 9 | DEC | dest = src1 - 1 |
+| 10 | CMP | flags = src1 - src2 |
+| 11 | NEG | dest = -src1 |
+| 12 | MOV | dest = src1 |
+| 13 | LDI | dest = immediate |
+
+### Control Flow (opcode 14)
+| Cond | Mnemonic | Condition |
+|------|----------|-----------|
+| 0 | JMP | unconditional |
+| 1 | JZ | Z = 1 |
+| 2 | JNZ | Z = 0 |
+| 3 | JC | C = 1 |
+| 4 | JNC | C = 0 |
+| 5 | JN | N = 1 |
+| 6 | JP | N = 0 |
+| 7 | JV | V = 1 |
+
+### Extended Operations (opcode 15)
+| Sub | Mnemonic | Operation |
+|-----|----------|-----------|
+| 0 | NOP | no operation |
+| 1 | LD | load from memory |
+| 2 | ST | store to memory |
+| 3 | PUSH | push to stack |
+| 4 | POP | pop from stack |
+| 5 | CALL | call subroutine |
+| 6 | RET | return |
+
+## Usage
+
+```python
+from safetensors.torch import load_file
+
+weights = load_file("neural_computer.safetensors")
+
+# All operations use threshold neurons:
+#   output = 1 if sum(weight * input) + bias >= 0 else 0
+```
+
+## Example Programs
+
+**Sum 1 to 10:**
+```asm
+LDI R0, 0      ; sum = 0
+LDI R1, 10     ; counter = 10
+ADD R0, R0, R1 ; sum += counter
+DEC R1, R1     ; counter--
+JNZ 4          ; loop if counter > 0
+; Result: R0 = 55
+```
+
+**Fibonacci:**
+```asm
+LDI R0, 1      ; fib(n-2)
+LDI R1, 1      ; fib(n-1)
+LDI R2, 6      ; iterations
+ADD R3, R0, R1 ; fib(n) = fib(n-2) + fib(n-1)
+MOV R0, R1
+MOV R1, R3
+DEC R2, R2
+JNZ 6
+; Result: R1 = 21 (fib(8))
+```
+
+## Verification
+
+Circuit weights derived from Coq proofs. Each circuit proven correct using:
+1. **Exhaustive verification** - all inputs tested
+2. **Universal quantification** - symbolic proofs
+3. **Algebraic characterization** - weight pattern correctness
+
+Note: The extraction from Coq to weights is not itself formally verified. The proofs establish correctness of the circuit specifications; the weights are a faithful transcription.
+
+## Circuit Categories
+
+| Category | Count | Examples |
+|----------|-------|----------|
+| Boolean | 9 | AND, OR, XOR, NAND, NOR |
+| Modular | 11 | MOD-2 through MOD-12 |
+| Threshold | 13 | Majority, k-out-of-n |
+| Arithmetic | 17 | Adders, comparators |
+| Error | 11 | Parity, Hamming, CRC |
+| Pattern | 10 | PopCount, symmetry |
+| Combinational | 10 | Mux, encoder, decoder |
+| ALU | 3 | Flags, control, ALU8Bit |
+| Control | 9 | Jump, conditional, stack |
+
+## Hardware Compatibility
+
+Designed for neuromorphic processors:
+- Intel Loihi
+- IBM TrueNorth
+- BrainChip Akida
+
+All weights are integers. All activations are Heaviside step.
+
+## Citation
+
+```bibtex
+@software{threshold_computer_2025,
+  title={8bit-threshold-computer: Turing-Complete Threshold Logic Computer},
+  author={Norton, Charles},
+  url={https://huggingface.co/phanerozoic/8bit-threshold-computer},
+  year={2025}
+}
+```
+
+## Links
+
+- [GitHub Repository](https://github.com/CharlesCNorton/coq-circuits)
+- [Coq Proofs](https://github.com/CharlesCNorton/coq-circuits/tree/main/coq)