Remove duplicate function definitions in build.py

build.py

@@ -378,108 +378,6 @@ def add_expr_paren(tensors: Dict[str, torch.Tensor]) -> None:
             add_full_adder(tensors, f"{prefix}.mul.acc.s{stage}.fa{bit}")
 
 
-def add_expr_paren(tensors: Dict[str, torch.Tensor]) -> None:
-    """Add expression circuit for (A + B) × C (parenthetical grouping).
-
-    Computes (A + B) × C where parentheses override default precedence.
-
-    Structure:
-    - Stage 1: Add A + B (8 full adders) → temp
-    - Stage 2: Multiply temp × C using shift-add algorithm
-      - 8 mask stages: mask[i] = temp AND C[i] (8 AND gates each)
-      - 7 accumulator adders to sum shifted masked values
-
-    Inputs: $a[0-7], $b[0-7], $c[0-7] (MSB-first, 8-bit each)
-    Output: 8-bit result of (A + B) × C, wrapping on overflow
-
-    Total: 8 full adders (add) + 64 AND gates + 7×8 full adders (mul) = ~640 gates
-    """
-    prefix = "arithmetic.expr_paren"
-
-    # Stage 1: Add A + B → temp
-    for bit in range(8):
-        add_full_adder(tensors, f"{prefix}.add.fa{bit}")
-
-    # Stage 2: Multiply temp × C using shift-add
-    # Mask AND gates: mask[stage][bit] = temp[bit] AND C[stage]
-    for stage in range(8):
-        for bit in range(8):
-            add_gate(tensors, f"{prefix}.mul.mask.s{stage}.b{bit}", [1.0, 1.0], [-2.0])
-
-    # Accumulator adders for shift-add multiplication
-    for stage in range(1, 8):  # 7 accumulator adders
-        for bit in range(8):
-            add_full_adder(tensors, f"{prefix}.mul.acc.s{stage}.fa{bit}")
-
-
-def add_expr_paren(tensors: Dict[str, torch.Tensor]) -> None:
-    """Add expression circuit for (A + B) × C (parenthetical grouping).
-
-    Computes (A + B) × C where addition is evaluated first due to parentheses.
-
-    Structure:
-    - Stage 1: Add A + B (8-bit ripple carry adder)
-    - Stage 2: Multiply sum × C using shift-add algorithm
-      - 8 mask stages: mask[i] = sum AND C[i] (8 AND gates each)
-      - 7 accumulator adders to sum masked values
-
-    Inputs: $a[0-7], $b[0-7], $c[0-7] (MSB-first, 8-bit each)
-    Output: 8-bit result of (A + B) × C, wrapping on overflow
-
-    Total: 8 full adders (add) + 64 AND gates + 56 full adders (mul) = ~640 gates
-    """
-    prefix = "arithmetic.expr_paren"
-
-    # Stage 1: Add A + B
-    for bit in range(8):
-        add_full_adder(tensors, f"{prefix}.add.fa{bit}")
-
-    # Stage 2: Multiply sum × C using shift-add
-    # Mask AND gates: mask[stage][bit] = sum[bit] AND C[stage]
-    for stage in range(8):
-        for bit in range(8):
-            add_gate(tensors, f"{prefix}.mul.mask.s{stage}.b{bit}", [1.0, 1.0], [-2.0])
-
-    # Accumulator adders for shift-add multiplication
-    for stage in range(1, 8):  # 7 accumulator adders
-        for bit in range(8):
-            add_full_adder(tensors, f"{prefix}.mul.acc.s{stage}.fa{bit}")
-
-
-def add_expr_paren_add_mul(tensors: Dict[str, torch.Tensor]) -> None:
-    """Add expression circuit for (A + B) × C (parenthetical grouping).
-
-    Computes (A + B) × C where parentheses override default precedence.
-
-    Structure:
-    - Stage 1: Add A + B (8-bit ripple carry) → temp
-    - Stage 2: Multiply temp × C using shift-add algorithm
-      - 8 mask stages: mask[i] = temp AND C[i]
-      - 7 accumulator adders to sum masked values
-
-    Inputs: $a[0-7], $b[0-7], $c[0-7] (MSB-first, 8-bit each)
-    Output: 8-bit result of (A + B) × C, wrapping on overflow
-
-    Total: 8 full adders (add) + 64 AND gates + 56 full adders (mul) = ~640 gates
-    """
-    prefix = "arithmetic.expr_paren_add_mul"
-
-    # Stage 1: Add A + B → temp
-    for bit in range(8):
-        add_full_adder(tensors, f"{prefix}.add.fa{bit}")
-
-    # Stage 2: Multiply temp × C using shift-add
-    # Mask AND gates: mask[stage][bit] = temp[bit] AND C[stage]
-    for stage in range(8):
-        for bit in range(8):
-            add_gate(tensors, f"{prefix}.mul.mask.s{stage}.b{bit}", [1.0, 1.0], [-2.0])
-
-    # Accumulator adders for multiplication
-    for stage in range(1, 8):  # 7 accumulator adders
-        for bit in range(8):
-            add_full_adder(tensors, f"{prefix}.mul.acc.s{stage}.fa{bit}")
-
-
 def add_add3(tensors: Dict[str, torch.Tensor]) -> None:
     """Add 3-operand 8-bit adder circuit.
 
@@ -1220,236 +1118,6 @@ def infer_expr_paren_inputs(gate: str, reg: SignalRegistry) -> List[int]:
     return []
 
 
-def infer_expr_paren_inputs(gate: str, reg: SignalRegistry) -> List[int]:
-    """Infer inputs for (A + B) × C expression circuit (parenthetical grouping).
-
-    Circuit structure:
-    - Add stage: add.fa[bit] computes A[bit] + B[bit]
-    - Mask stage: mask.s[stage].b[bit] = sum[bit] AND C[stage]
-    - Accumulator stages 1-7: acc.s[stage] = acc.s[stage-1] + (mask.s[stage] << stage)
-
-    Bit ordering: MSB-first externally, LSB-first internally (fa0 = LSB, fa7 = MSB)
-    """
-    prefix = "arithmetic.expr_paren"
-
-    # Register all inputs
-    for i in range(8):
-        reg.register(f"$a[{i}]")
-        reg.register(f"$b[{i}]")
-        reg.register(f"$c[{i}]")
-
-    # Add stage: A + B
-    if '.add.fa' in gate and '.mul.' not in gate:
-        m = re.search(r'\.fa(\d+)\.', gate)
-        if not m:
-            return []
-        bit = int(m.group(1))
-
-        # A and B inputs (MSB-first to positional)
-        a_input = reg.get_id(f"$a[{7-bit}]")
-        b_input = reg.get_id(f"$b[{7-bit}]")
-
-        # Carry input
-        if bit == 0:
-            cin = reg.get_id("#0")
-        else:
-            cin = reg.register(f"{prefix}.add.fa{bit-1}.carry_or")
-
-        fa_prefix = f"{prefix}.add.fa{bit}"
-
-        if '.ha1.sum.layer1' in gate:
-            return [a_input, b_input]
-        if '.ha1.sum.layer2' in gate:
-            return [reg.register(f"{fa_prefix}.ha1.sum.layer1.or"), reg.register(f"{fa_prefix}.ha1.sum.layer1.nand")]
-        if '.ha1.carry' in gate and '.layer' not in gate:
-            return [a_input, b_input]
-        if '.ha2.sum.layer1' in gate:
-            return [reg.register(f"{fa_prefix}.ha1.sum.layer2"), cin]
-        if '.ha2.sum.layer2' in gate:
-            return [reg.register(f"{fa_prefix}.ha2.sum.layer1.or"), reg.register(f"{fa_prefix}.ha2.sum.layer1.nand")]
-        if '.ha2.carry' in gate and '.layer' not in gate:
-            return [reg.register(f"{fa_prefix}.ha1.sum.layer2"), cin]
-        if '.carry_or' in gate:
-            return [reg.register(f"{fa_prefix}.ha1.carry"), reg.register(f"{fa_prefix}.ha2.carry")]
-        return []
-
-    # Mask AND gates: mask.s[stage].b[bit] = sum[bit] AND C[stage]
-    if '.mul.mask.' in gate:
-        m = re.search(r'\.s(\d+)\.b(\d+)', gate)
-        if m:
-            stage = int(m.group(1))
-            bit = int(m.group(2))
-            # sum[bit] is the output of add.fa[bit]
-            sum_input = reg.register(f"{prefix}.add.fa{bit}.ha2.sum.layer2")
-            # C[stage] in MSB-first
-            c_input = reg.get_id(f"$c[{7-stage}]")
-            return [sum_input, c_input]
-        return []
-
-    # Accumulator adders: acc.s[stage].fa[bit]
-    if '.mul.acc.' in gate:
-        m = re.search(r'\.s(\d+)\.fa(\d+)\.', gate)
-        if not m:
-            return []
-        stage = int(m.group(1))  # 1-7
-        bit = int(m.group(2))    # 0-7
-
-        # A input: previous stage output
-        if stage == 1:
-            # First accumulator: A = mask.s0.b[bit] (AND gate output)
-            a_input = reg.register(f"{prefix}.mul.mask.s0.b{bit}")
-        else:
-            # Later stages: A = previous accumulator sum
-            a_input = reg.register(f"{prefix}.mul.acc.s{stage-1}.fa{bit}.ha2.sum.layer2")
-
-        # B input: (mask.s[stage] << stage)[bit]
-        if bit < stage:
-            b_input = reg.get_id("#0")
-        else:
-            b_input = reg.register(f"{prefix}.mul.mask.s{stage}.b{bit-stage}")
-
-        # Carry input
-        if bit == 0:
-            cin = reg.get_id("#0")
-        else:
-            cin = reg.register(f"{prefix}.mul.acc.s{stage}.fa{bit-1}.carry_or")
-
-        fa_prefix = f"{prefix}.mul.acc.s{stage}.fa{bit}"
-
-        if '.ha1.sum.layer1' in gate:
-            return [a_input, b_input]
-        if '.ha1.sum.layer2' in gate:
-            return [reg.register(f"{fa_prefix}.ha1.sum.layer1.or"), reg.register(f"{fa_prefix}.ha1.sum.layer1.nand")]
-        if '.ha1.carry' in gate and '.layer' not in gate:
-            return [a_input, b_input]
-        if '.ha2.sum.layer1' in gate:
-            return [reg.register(f"{fa_prefix}.ha1.sum.layer2"), cin]
-        if '.ha2.sum.layer2' in gate:
-            return [reg.register(f"{fa_prefix}.ha2.sum.layer1.or"), reg.register(f"{fa_prefix}.ha2.sum.layer1.nand")]
-        if '.ha2.carry' in gate and '.layer' not in gate:
-            return [reg.register(f"{fa_prefix}.ha1.sum.layer2"), cin]
-        if '.carry_or' in gate:
-            return [reg.register(f"{fa_prefix}.ha1.carry"), reg.register(f"{fa_prefix}.ha2.carry")]
-        return []
-
-    return []
-
-
-def infer_expr_paren_add_mul_inputs(gate: str, reg: SignalRegistry) -> List[int]:
-    """Infer inputs for (A + B) × C expression circuit (parenthetical grouping).
-
-    Circuit structure:
-    - Add stage: A + B → temp (8-bit ripple carry)
-    - Mask stage: mask.s[stage].b[bit] = temp[bit] AND C[stage]
-    - Accumulator stages 1-7: acc.s[stage] = acc.s[stage-1] + (mask.s[stage] << stage)
-
-    Bit ordering: MSB-first externally, LSB-first internally (fa0 = LSB, fa7 = MSB)
-    """
-    prefix = "arithmetic.expr_paren_add_mul"
-
-    # Register all inputs
-    for i in range(8):
-        reg.register(f"$a[{i}]")
-        reg.register(f"$b[{i}]")
-        reg.register(f"$c[{i}]")
-
-    # Add stage: A + B → temp
-    if '.add.fa' in gate and '.mul.' not in gate:
-        m = re.search(r'\.fa(\d+)\.', gate)
-        if not m:
-            return []
-        bit = int(m.group(1))
-
-        # A input: $a[7-bit] (MSB-first to positional bit)
-        a_input = reg.get_id(f"$a[{7-bit}]")
-        # B input: $b[7-bit]
-        b_input = reg.get_id(f"$b[{7-bit}]")
-        # Carry input
-        if bit == 0:
-            cin = reg.get_id("#0")
-        else:
-            cin = reg.register(f"{prefix}.add.fa{bit-1}.carry_or")
-
-        fa_prefix = f"{prefix}.add.fa{bit}"
-
-        if '.ha1.sum.layer1' in gate:
-            return [a_input, b_input]
-        if '.ha1.sum.layer2' in gate:
-            return [reg.register(f"{fa_prefix}.ha1.sum.layer1.or"), reg.register(f"{fa_prefix}.ha1.sum.layer1.nand")]
-        if '.ha1.carry' in gate and '.layer' not in gate:
-            return [a_input, b_input]
-        if '.ha2.sum.layer1' in gate:
-            return [reg.register(f"{fa_prefix}.ha1.sum.layer2"), cin]
-        if '.ha2.sum.layer2' in gate:
-            return [reg.register(f"{fa_prefix}.ha2.sum.layer1.or"), reg.register(f"{fa_prefix}.ha2.sum.layer1.nand")]
-        if '.ha2.carry' in gate and '.layer' not in gate:
-            return [reg.register(f"{fa_prefix}.ha1.sum.layer2"), cin]
-        if '.carry_or' in gate:
-            return [reg.register(f"{fa_prefix}.ha1.carry"), reg.register(f"{fa_prefix}.ha2.carry")]
-        return []
-
-    # Mask AND gates: mask.s[stage].b[bit] = temp[bit] AND C[stage]
-    if '.mul.mask.' in gate:
-        m = re.search(r'\.s(\d+)\.b(\d+)', gate)
-        if m:
-            stage = int(m.group(1))
-            bit = int(m.group(2))
-            # temp[bit] is the sum output from add stage
-            temp_bit = reg.register(f"{prefix}.add.fa{bit}.ha2.sum.layer2")
-            # C[stage] in MSB-first
-            c_input = reg.get_id(f"$c[{7-stage}]")
-            return [temp_bit, c_input]
-        return []
-
-    # Accumulator adders: acc.s[stage].fa[bit]
-    if '.mul.acc.' in gate:
-        m = re.search(r'\.s(\d+)\.fa(\d+)\.', gate)
-        if not m:
-            return []
-        stage = int(m.group(1))  # 1-7
-        bit = int(m.group(2))    # 0-7
-
-        # A input: previous stage output
-        if stage == 1:
-            # First accumulator: A = mask.s0.b[bit] (AND gate output)
-            a_input = reg.register(f"{prefix}.mul.mask.s0.b{bit}")
-        else:
-            # Later stages: A = previous accumulator sum
-            a_input = reg.register(f"{prefix}.mul.acc.s{stage-1}.fa{bit}.ha2.sum.layer2")
-
-        # B input: (mask.s[stage] << stage)[bit]
-        if bit < stage:
-            b_input = reg.get_id("#0")
-        else:
-            b_input = reg.register(f"{prefix}.mul.mask.s{stage}.b{bit-stage}")
-
-        # Carry input
-        if bit == 0:
-            cin = reg.get_id("#0")
-        else:
-            cin = reg.register(f"{prefix}.mul.acc.s{stage}.fa{bit-1}.carry_or")
-
-        fa_prefix = f"{prefix}.mul.acc.s{stage}.fa{bit}"
-
-        if '.ha1.sum.layer1' in gate:
-            return [a_input, b_input]
-        if '.ha1.sum.layer2' in gate:
-            return [reg.register(f"{fa_prefix}.ha1.sum.layer1.or"), reg.register(f"{fa_prefix}.ha1.sum.layer1.nand")]
-        if '.ha1.carry' in gate and '.layer' not in gate:
-            return [a_input, b_input]
-        if '.ha2.sum.layer1' in gate:
-            return [reg.register(f"{fa_prefix}.ha1.sum.layer2"), cin]
-        if '.ha2.sum.layer2' in gate:
-            return [reg.register(f"{fa_prefix}.ha2.sum.layer1.or"), reg.register(f"{fa_prefix}.ha2.sum.layer1.nand")]
-        if '.ha2.carry' in gate and '.layer' not in gate:
-            return [reg.register(f"{fa_prefix}.ha1.sum.layer2"), cin]
-        if '.carry_or' in gate:
-            return [reg.register(f"{fa_prefix}.ha1.carry"), reg.register(f"{fa_prefix}.ha2.carry")]
-        return []
-
-    return []
-
-
 def infer_add3_inputs(gate: str, reg: SignalRegistry) -> List[int]:
     """Infer inputs for 3-operand adder: A + B + C."""
     prefix = "arithmetic.add3_8bit"