Remove Python fallbacks, add Extension Roadmap

- Replace SHL/SHR/MUL/DIV with NotImplementedError in both ref_step() and ThresholdCPU.step()
- Add detailed 11-item Extension Roadmap documenting circuit status and requirements

README.md

@@ -449,10 +449,27 @@ The interface generalizes to **all** 65,536 8-bit additions once trained—no me
 
 ### Extension Roadmap
 
-- **Additional operations**: Subtraction, multiplication, division, bitwise ops, comparisons
-- **Multi-operand**: "15 + 27 + 33 =" via accumulator pattern
-- **Larger widths**: 16-bit, 32-bit via chained circuits
-- **Symbolic integration**: Natural language problems → extract operands → compute → generate answer
+1. **8-bit addition (0-255)** — Ripple carry adder using 8 chained full adders. Each full adder is 2 half adders + OR gate, built from XOR (2-layer) and AND (1-layer) threshold gates. Circuit exists and passes all 65,536 input combinations.
+
+2. **8-bit subtraction (0-255)** — Two's complement via NOT gates on second operand + carry-in of 1. Reuses adder circuit. Handles negative results as unsigned wrap (200 - 250 = 206). Circuit exists and verified.
+
+3. **8-bit multiplication** — Requires array of AND gates for partial products + adder tree to sum them. 8×8 produces 16-bit result; can truncate to low 8 bits or preserve full width. Circuit NOT yet implemented.
+
+4. **8-bit division with remainder** — Restoring or non-restoring division via subtract-and-shift. Produces 8-bit quotient + 8-bit remainder. Most complex circuit; ~64 subtractors + muxes. NOT yet implemented.
+
+5. **Bitwise AND, OR, XOR, NOT** — 8 parallel single-layer threshold gates per operation. AND: w=[1,1], b=-2. OR: w=[1,1], b=-1. XOR: 2-layer (OR+NAND→AND). All circuits exist and verified.
+
+6. **Bit shifts (left, right)** — Hardwired routing, not computation. SHL: bit[i] → bit[i-1], inject 0 at LSB. SHR: bit[i] → bit[i+1], inject 0 at MSB. Can implement as identity gates with shifted wiring. NOT yet implemented.
+
+7. **Comparisons (>, <, >=, <=, ==)** — Single-layer threshold gates on 16 inputs (8 bits from A, 8 from B). Learned weights encode lexicographic comparison. All 5 comparators exist and verified on 48 test pairs.
+
+8. **Divisibility testing (mod 2-12)** — Powers of 2 (mod 2,4,8): single-layer, check relevant bits. Non-powers (mod 3,5,6,7,9,10,11,12): multi-layer circuits encoding residue classes. All 11 circuits exist and exhaustively verified 0-255.
+
+9. **Multi-operand expressions (15 + 27 + 33)** — Accumulator pattern: result = 0; for each operand, result = ADD(result, operand). Router must fire multiple times per input sequence. Requires stateful dispatch or unrolled circuit.
+
+10. **Order of operations (5 + 3 × 2 = 11)** — Parse expression into tree, evaluate depth-first. MUL before ADD. Requires either: (a) expression parser producing evaluation order, or (b) learned routing that implicitly respects precedence.
+
+11. **Parenthetical expressions ((5 + 3) × 2 = 16)** — Explicit grouping overrides precedence. Parser must recognize parens and build correct tree. Evaluation proceeds innermost-out. Adds complexity to extraction layer.
 
 ---
 

threshold_cpu.py

@@ -193,22 +193,13 @@ def ref_step(state: CPUState) -> CPUState:
     elif opcode == 0x4:
         result = a ^ b
     elif opcode == 0x5:
-        carry = 1 if (a & 0x80) else 0
-        result = (a << 1) & 0xFF
+        raise NotImplementedError("SHL: threshold circuit not implemented")
     elif opcode == 0x6:
-        carry = 1 if (a & 0x01) else 0
-        result = (a >> 1) & 0xFF
+        raise NotImplementedError("SHR: threshold circuit not implemented")
     elif opcode == 0x7:
-        full = a * b
-        result = full & 0xFF
-        carry = 1 if full > 0xFF else 0
+        raise NotImplementedError("MUL: threshold circuit not implemented")
     elif opcode == 0x8:
-        if b == 0:
-            result = 0
-            carry = 1
-            overflow = 1
-        else:
-            result = (a // b) & 0xFF
+        raise NotImplementedError("DIV: threshold circuit not implemented")
     elif opcode == 0x9:
         result, carry, overflow = alu_sub(a, b)
         write_result = False
@@ -583,22 +574,13 @@ class ThresholdCPU:
         elif opcode == 0x4:
             result = self.alu.bitwise_xor(a, b)
         elif opcode == 0x5:
-            carry = 1 if (a & 0x80) else 0
-            result = (a << 1) & 0xFF
+            raise NotImplementedError("SHL: threshold circuit not implemented")
         elif opcode == 0x6:
-            carry = 1 if (a & 0x01) else 0
-            result = (a >> 1) & 0xFF
+            raise NotImplementedError("SHR: threshold circuit not implemented")
         elif opcode == 0x7:
-            full = a * b
-            result = full & 0xFF
-            carry = 1 if full > 0xFF else 0
+            raise NotImplementedError("MUL: threshold circuit not implemented")
         elif opcode == 0x8:
-            if b == 0:
-                result = 0
-                carry = 1
-                overflow = 1
-            else:
-                result = (a // b) & 0xFF
+            raise NotImplementedError("DIV: threshold circuit not implemented")
         elif opcode == 0x9:
             result, carry, overflow = self.alu.sub(a, b)
             write_result = False