Update roadmap

todo.md

@@ -1,148 +1,173 @@
 # Threshold Logic Neural Turing Machine
 
-## Vision
+## Core Vision
 
-A verified computational coprocessor embedded in transformer architecture:
-- **Frozen circuits**: Exhaustively tested threshold logic (can't compute wrong)
-- **ACT execution**: Runs until HALT within single forward pass
-- **Dual memory**: Hidden state integration + dedicated 64KB address space
-- **LLM integration**: Router/Extract/Inject learned, computation exact
+A self-contained, autonomous computational machine:
+- **Pure tensor computation**: State in, state out
+- **Frozen verified circuits**: Exhaustively tested, can't compute wrong
+- **ACT execution**: Internal loop until HALT
+- **No external orchestration**: One forward pass = complete program execution
 
-## Architecture Overview
+The machine runs. Callers just provide initial state and collect results.
+
+## Architecture
 
 ```
-┌─────────────────────────────────────────────────────────────┐
-│                    Transformer Layer                        │
-│  ┌──────────────┐  ┌──────────────┐  ┌──────────────────┐  │
-│  │  Attention   │  │     MLP      │  │  ThresholdCPU    │  │
-│  │              │  │              │  │  (ACT-style)     │  │
-│  │              │  │              │  │                  │  │
-│  │              │  │              │  │ ┌──────────────┐ │  │
-│  │              │  │              │  │ │Router (learn)│ │  │
-│  │              │  │              │  │ ├──────────────┤ │  │
-│  │              │  │              │  │ │Extract (learn│ │  │
-│  │              │  │              │  │ ├──────────────┤ │  │
-│  │              │  │              │  │ │CPU (frozen)  │ │  │
-│  │              │  │              │  │ │ ↻ until HALT │ │  │
-│  │              │  │              │  │ ├──────────────┤ │  │
-│  │              │  │              │  │ │Inject (learn)│ │  │
-│  │              │  │              │  │ └──────────────┘ │  │
-│  └──────┬───────┘  └──────┬───────┘  └────────┬─────────┘  │
-│         └─────────────────┴───────────────────┘            │
-│                           ↓                                 │
-│                    Residual + CPU State                     │
-└─────────────────────────────────────────────────────────────┘
+            ┌─────────────────────────────┐
+            │      Initial State          │
+            │  [PC|Regs|Flags|Memory...]  │
+            └─────────────┬───────────────┘
+                          ▼
+            ┌─────────────────────────────┐
+            │                             │
+            │   Threshold Circuit Layer   │
+            │                             │
+            │  ┌───────────────────────┐  │
+            │  │   Fetch: PC → Instr   │  │
+            │  ├───────────────────────┤  │
+            │  │   Decode: Opcode/Ops  │  │
+            │  ├───────────────────────┤  │
+            │  │   Execute: ALU/Mem    │  │
+            │  ├───────────────────────┤  │
+            │  │   Writeback: Results  │  │
+            │  ├───────────────────────┤  │
+            │  │   PC Update           │  │
+            │  └───────────┬───────────┘  │
+            │              │              │
+            │         ┌────▼────┐         │
+            │         │ HALTED? │         │
+            │         └────┬────┘         │
+            │              │              │
+            │         no ──┴── yes        │
+            │          │       │          │
+            │          ▼       ▼          ��
+            │       [loop]   [exit]       │
+            │                             │
+            └─────────────┬───────────────┘
+                          ▼
+            ┌─────────────────────────────┐
+            │       Final State           │
+            │  [PC|Regs|Flags|Memory...]  │
+            └─────────────────────────────┘
 ```
 
 ## Memory Architecture
 
-### Hidden State Integration (Hot Memory)
-Reserve dimensions of residual stream for CPU state:
-```
-dims 0-511:     CPU memory (512 bits = 64 bytes hot cache)
-dims 512-543:   Registers (32 bits = 4 × 8-bit)
-dims 544-551:   PC (8 bits)
-dims 552-555:   Flags (4 bits: Z, N, C, V)
-dims 556-559:   Control (halt, interrupt, etc.)
-dims 560-959:   Normal embeddings (400 dims)
-```
-
-### Dedicated Memory Bank (Cold Storage)
-Full 64KB addressable memory via routing circuits:
+### State Tensor Layout
 ```
-Address space:  0x0000 - 0xFFFF (65,536 bytes)
-Tensors:        ~1.6M (routing overhead)
-Access:         Via 16-bit address decoder + mux/demux
+┌────────┬──────────┬───────┬────────┬─────────────────────┐
+│ PC [8] │ Regs[32] │Flags[4│Ctrl[4] │ Memory [N × 8]      │
+└────────┴──────────┴───────┴────────┴─────────────────────┘
+    8    +   32     +   4   +   4    +   N × 8   bits
 ```
 
 ### Memory Hierarchy
-| Level | Size | Access | Use Case |
-|-------|------|--------|----------|
-| Registers | 4 × 8-bit | Direct | Operands, accumulators |
-| Hot cache | 64 bytes | Embedded in hidden state | Stack, scratch |
-| Cold bank | 64KB | Circuit-routed | Programs, data, heap |
+| Level | Size | Tensors | Access |
+|-------|------|---------|--------|
+| Registers | 4 × 8-bit | Direct wiring | Immediate |
+| Hot cache | 256 bytes | ~6,400 | 8-bit addressed |
+| Cold bank | 64KB | ~1.6M | 16-bit addressed |
+
+### Full 64KB Configuration
+- Address space: 0x0000 - 0xFFFF
+- Routing circuits: ~1.64M tensors
+- State tensor: 48 + 524,288 = 524,336 bits per instance
 
 ## Phase 1: Memory Infrastructure
 
 | Component | Description | Tensors | Status |
 |-----------|-------------|---------|--------|
+| Address Decoder 8-bit | 8-bit → 256 one-hot | ~520 | Pending |
 | Address Decoder 16-bit | 16-bit → 65536 one-hot | ~65,600 | Pending |
-| Memory Read MUX | 65536-to-1 × 8 bits | ~524,288 | Pending |
-| Memory Write Demux | Route to addressed byte | ~524,288 | Pending |
-| Memory Cell Logic | Conditional update per byte | ~524,288 | Pending |
-| Bank Controller | Page/bank switching | ~1,000 | Pending |
-
-**Estimated Phase 1 total: ~1.64M tensors**
+| Memory Read MUX 256 | 256-to-1 × 8 bits | ~2,048 | Pending |
+| Memory Read MUX 64K | 65536-to-1 × 8 bits | ~524,288 | Pending |
+| Memory Write Demux | Route write to address | ~524,288 | Pending |
+| Memory Cell Logic | Conditional update | ~524,288 | Pending |
 
-## Phase 2: ACT Execution Engine
+## Phase 2: Execution Engine
 
 | Component | Description | Status |
 |-----------|-------------|--------|
-| Cycle Block | One fetch/decode/execute iteration | Pending |
-| Halt Detector | HALT instruction → stop signal | Pending |
-| Cycle Counter | Track pondering steps | Pending |
-| State Checkpointing | Save state for gradient flow | Pending |
-
-## Phase 3: LLM Integration Layers
-
-| Component | Description | Trainable | Status |
-|-----------|-------------|-----------|--------|
-| Router | Detect computation need | Yes | Pending |
-| State Extractor | Embeddings → CPU state | Yes | Pending |
-| State Injector | CPU state → embedding delta | Yes | Pending |
-| KV Cache Binding | CPU state persists with cache | No | Pending |
-
-## Phase 4: Instruction Set
-
-| Category | Instructions | Status |
-|----------|--------------|--------|
-| Arithmetic | ADD, SUB, MUL, DIV, NEG, ADC, SBC | Done |
-| Logic | AND, OR, XOR, NOT, shifts, rotates | Done |
-| Compare | CMP (sets flags) | Done |
-| Control | JMP, Jcc (conditional), CALL, RET | Partial |
-| Memory | LOAD, STORE (8/16-bit addressing) | Pending |
-| Stack | PUSH, POP | Partial |
-| System | NOP, HALT | Done |
-
-## Completed Building Blocks
-
-### Arithmetic Core (2,756 tensors)
-- NEG: 76 tensors, 256/256 tests
-- SUB: 162 tensors, 65536/65536 tests
-- ADC: 144 tensors, 131072/131072 tests
-- SBC: 160 tensors, 131072/131072 tests
-- DIV: 1984 tensors, 65280/65280 tests
-- CMP: 168 tensors, 65536/65536 tests
-- ASR/ROL/ROR: 62 tensors total
-
-### Control Core (306 tensors)
-- NOP: 24 tensors, 4096/4096 tests
-- HALT: 42 tensors, 24576/24576 tests
-- PC Incrementer: 62 tensors, 256/256 tests
-- PC Load MUX: 50 tensors, 1536/1536 tests
-- Register MUX: 84 tensors, 1036/1036 tests
-- Instruction Decoder: 44 tensors, 16/16 tests
-
-### Original Model
-- Boolean gates, adders, multiplier, comparators
-- Threshold gates, pattern recognition
-- Modular arithmetic, error detection
-- ~3,100 tensors
-
-**Current total: 6,184 tensors**
-**Projected with 64KB memory: ~1.65M tensors**
+| Instruction Fetch | PC → Memory → IR | Pending |
+| Operand Fetch | Decode → Register/Memory Read | Pending |
+| ALU Dispatch | Opcode → Operation Select | Pending |
+| Result Writeback | Route to destination | Pending |
+| Flag Update | Compute Z/N/C/V | Partial |
+| PC Advance | Increment or Jump | Done |
+| Halt Detection | HALT opcode → stop | Done |
 
-## Design Principles
-
-1. **Frozen correctness**: Circuit weights never change, exhaustively verified
-2. **Learned interface**: Router/Extract/Inject are trainable, CPU is not
-3. **Functional state**: Memory flows through as data, not mutated weights
-4. **Halting semantics**: HALT instruction terminates ACT loop
-5. **Composable**: Each circuit tested in isolation, composed at runtime
+## Phase 3: ACT Integration
 
-## Key Insight
+| Component | Description | Status |
+|-----------|-------------|--------|
+| Cycle Block | All Phase 2 as single layer | Pending |
+| Recurrence Wrapper | Loop until halt signal | Pending |
+| Max Cycles Guard | Prevent infinite loops | Pending |
+| State I/O | Pack/unpack state tensor | Pending |
+
+## Instruction Set
+
+| Opcode | Mnemonic | Operation | Status |
+|--------|----------|-----------|--------|
+| 0x0 | ADD | R[d] = R[a] + R[b] | Done |
+| 0x1 | SUB | R[d] = R[a] - R[b] | Done |
+| 0x2 | AND | R[d] = R[a] & R[b] | Done |
+| 0x3 | OR | R[d] = R[a] \| R[b] | Done |
+| 0x4 | XOR | R[d] = R[a] ^ R[b] | Done |
+| 0x5 | SHL | R[d] = R[a] << 1 | Done |
+| 0x6 | SHR | R[d] = R[a] >> 1 | Done |
+| 0x7 | MUL | R[d] = R[a] * R[b] | Done |
+| 0x8 | DIV | R[d] = R[a] / R[b] | Done |
+| 0x9 | CMP | flags = R[a] - R[b] | Done |
+| 0xA | LOAD | R[d] = M[addr] | Pending |
+| 0xB | STORE | M[addr] = R[s] | Pending |
+| 0xC | JMP | PC = addr | Partial |
+| 0xD | JZ/JNZ | PC = addr if flag | Done |
+| 0xE | CALL | push PC; PC = addr | Partial |
+| 0xF | HALT | stop execution | Done |
+
+## Completed Circuits
+
+### Arithmetic (2,756 tensors)
+- ADD, SUB, MUL, DIV, NEG
+- ADC, SBC (with carry)
+- CMP (compare, sets flags)
+
+### Bit Operations (62 tensors)
+- ASR (arithmetic shift right)
+- ROL, ROR (rotate through carry)
+- SHL, SHR (from original)
+
+### Control (306 tensors)
+- NOP, HALT
+- PC Increment, PC Load MUX
+- Register MUX 4-to-1
+- Instruction Decoder 4-to-16
+
+### Original Model (~3,100 tensors)
+- Boolean gates (AND, OR, XOR, NOT, NAND, NOR)
+- Ripple carry adders (2/4/8-bit)
+- 8×8 multiplier
+- Comparators, threshold gates
+- Conditional jumps
+
+**Current: 6,184 tensors**
+**Projected: ~1.65M tensors (with 64KB memory)**
+
+## Applications
+
+The machine is general-purpose. Possible callers:
+
+1. **Direct invocation**: Load state, call forward(), read result
+2. **LLM coprocessor**: Embedded layer for exact computation
+3. **Neuromorphic deployment**: Map to spiking hardware
+4. **Verified computation**: Provably correct execution
+5. **Educational**: Transparent, inspectable CPU
 
-The LLM learns **when** to compute and **how** to format input/output.
-The CPU defines **what** computation means - exactly, verifiably, always.
+## Design Principles
 
-This is not a learned calculator. This is a proven calculator with a learned interface.
+1. **Autonomy**: Machine runs without external logic
+2. **Purity**: forward(state) → state', no side effects
+3. **Verification**: Every circuit exhaustively tested
+4. **Transparency**: All weights inspectable, all operations traceable
+5. **Universality**: Turing complete, runs arbitrary programs