Add memory circuits and CPU state layout

README.md

@@ -17,8 +17,8 @@ tags:
 Every logic gate is a threshold neuron: `output = 1 if (Σ wᵢxᵢ + b) ≥ 0 else 0`
 
 ```
-Tensors:    3,122
-Parameters: 5,648
+Tensors:    24,200
+Parameters: 40,323
 ```
 
 ---
@@ -85,15 +85,16 @@ The weights in this repository implement a complete 8-bit computer: registers, A
 | Arithmetic | 18 | Half/full adder, 2/4/8-bit ripple carry, comparators |
 | ALU | 3 | 8-bit ALU, control decoder, flag computation |
 | Combinational | 10 | MUX (2:1, 4:1, 8:1), DEMUX, encoders, decoders |
-| Control Flow | 16 | JMP, conditional jumps, CALL, RET, PUSH, POP |
-| Error Detection | 11 | Parity (XOR tree), checksum, CRC, Hamming |
-| Modular | 11 | Divisibility by 2-12 (multi-layer for non-powers-of-2) |
-| Threshold | 13 | k-of-n gates, majority, minority, exactly-k |
-| Pattern | 10 | Popcount, leading/trailing ones, symmetry |
+| Control Flow | 16 | JMP, conditional jumps, CALL, RET, PUSH, POP |
+| Error Detection | 11 | Parity (XOR tree), checksum, CRC, Hamming |
+| Modular | 11 | Divisibility by 2-12 (multi-layer for non-powers-of-2) |
+| Threshold | 13 | k-of-n gates, majority, minority, exactly-k |
+| Pattern | 10 | Popcount, leading/trailing ones, symmetry |
+| Memory | 3 | 8-bit addr decoder, 256x8 read mux, write cell update |
 
 ---
 
-## Usage
+## Usage
 
 ```python
 import torch
@@ -112,11 +113,44 @@ for a, b_in in [(0,0), (0,1), (1,0), (1,1)]:
     inp = torch.tensor([a, b_in], dtype=torch.float32)
     out = heaviside(inp @ w + b)
     print(f"AND({a}, {b_in}) = {int(out.item())}")
-```
-
----
-
-## Verification
+```
+
+---
+
+## State Tensor Layout
+
+All multi-bit fields are **MSB-first** (index 0 is the most-significant bit).
+
+```
+[ PC[8] | IR[16] | R0[8] R1[8] R2[8] R3[8] | FLAGS[4] | SP[8] | CTRL[4] | MEM[256][8] ]
+```
+
+Flags are ordered as: `Z, N, C, V`.
+
+Control bits are ordered as: `HALT, MEM_WE, MEM_RE, RESERVED`.
+
+Total state size: `2120` bits.
+
+---
+
+## Instruction Encoding (16-bit)
+
+All instruction bits are **MSB-first**.
+
+```
+15..12  11..10  9..8  7..0
+opcode  rd      rs    imm8
+```
+
+Interpretation:
+- **R-type**: `rd = rd op rs` (imm8 ignored).
+- **I-type**: `rd = op rd, imm8` (rs ignored).
+- **Jumps/Calls**: `imm8` is the absolute target address.
+- **LOAD/STORE**: `imm8` is the absolute memory address.
+
+---
+
+## Verification
 
 The model includes `iron_eval.py` which exhaustively tests all circuits:
 
@@ -175,7 +209,7 @@ All weights are integers. All activations are Heaviside step. Designed for:
 
 | File | Description |
 |------|-------------|
-| `neural_computer.safetensors` | 3,122 tensors, 5,648 parameters |
+| `neural_computer.safetensors` | 24,200 tensors, 40,323 parameters |
 | `iron_eval.py` | Comprehensive test suite |
 | `prune_weights.py` | Weight optimization tool |
 

cpu/cycle.py

@@ -0,0 +1,137 @@
+"""
+Reference CPU cycle (software) for the threshold computer.
+Implements fetch/decode/execute over the state layout.
+"""
+
+from __future__ import annotations
+
+from typing import Tuple
+
+from .state import CPUState
+
+
+def decode_ir(ir: int) -> Tuple[int, int, int, int]:
+    opcode = (ir >> 12) & 0xF
+    rd = (ir >> 10) & 0x3
+    rs = (ir >> 8) & 0x3
+    imm8 = ir & 0xFF
+    return opcode, rd, rs, imm8
+
+
+def _flags_from_result(result: int, carry: int, overflow: int) -> Tuple[int, int, int, int]:
+    z = 1 if result == 0 else 0
+    n = 1 if (result & 0x80) else 0
+    c = 1 if carry else 0
+    v = 1 if overflow else 0
+    return z, n, c, v
+
+
+def _alu_add(a: int, b: int) -> Tuple[int, int, int]:
+    full = a + b
+    result = full & 0xFF
+    carry = 1 if full > 0xFF else 0
+    overflow = 1 if (((a ^ result) & (b ^ result)) & 0x80) else 0
+    return result, carry, overflow
+
+
+def _alu_sub(a: int, b: int) -> Tuple[int, int, int]:
+    full = (a - b) & 0x1FF
+    result = full & 0xFF
+    carry = 1 if a >= b else 0
+    overflow = 1 if (((a ^ b) & (a ^ result)) & 0x80) else 0
+    return result, carry, overflow
+
+
+def step(state: CPUState) -> CPUState:
+    if state.ctrl[0] == 1:  # HALT
+        return state.copy()
+
+    s = state.copy()
+
+    # Fetch: two bytes, big-endian
+    hi = s.mem[s.pc]
+    lo = s.mem[(s.pc + 1) & 0xFF]
+    s.ir = ((hi & 0xFF) << 8) | (lo & 0xFF)
+    next_pc = (s.pc + 2) & 0xFF
+
+    opcode, rd, rs, imm8 = decode_ir(s.ir)
+    a = s.regs[rd]
+    b = s.regs[rs]
+
+    write_result = True
+    result = a
+    carry = 0
+    overflow = 0
+
+    if opcode == 0x0:  # ADD
+        result, carry, overflow = _alu_add(a, b)
+    elif opcode == 0x1:  # SUB
+        result, carry, overflow = _alu_sub(a, b)
+    elif opcode == 0x2:  # AND
+        result = a & b
+    elif opcode == 0x3:  # OR
+        result = a | b
+    elif opcode == 0x4:  # XOR
+        result = a ^ b
+    elif opcode == 0x5:  # SHL
+        carry = 1 if (a & 0x80) else 0
+        result = (a << 1) & 0xFF
+    elif opcode == 0x6:  # SHR
+        carry = 1 if (a & 0x01) else 0
+        result = (a >> 1) & 0xFF
+    elif opcode == 0x7:  # MUL
+        full = a * b
+        result = full & 0xFF
+        carry = 1 if full > 0xFF else 0
+    elif opcode == 0x8:  # DIV
+        if b == 0:
+            result = 0
+            carry = 1
+            overflow = 1
+        else:
+            result = (a // b) & 0xFF
+    elif opcode == 0x9:  # CMP
+        result, carry, overflow = _alu_sub(a, b)
+        write_result = False
+    elif opcode == 0xA:  # LOAD
+        result = s.mem[imm8]
+    elif opcode == 0xB:  # STORE
+        s.mem[imm8] = b & 0xFF
+        write_result = False
+    elif opcode == 0xC:  # JMP
+        s.pc = imm8 & 0xFF
+        write_result = False
+    elif opcode == 0xD:  # JZ
+        if s.flags[0] == 1:
+            s.pc = imm8 & 0xFF
+        else:
+            s.pc = next_pc
+        write_result = False
+    elif opcode == 0xE:  # CALL
+        s.sp = (s.sp - 1) & 0xFF
+        s.mem[s.sp] = next_pc
+        s.pc = imm8 & 0xFF
+        write_result = False
+    elif opcode == 0xF:  # HALT
+        s.ctrl[0] = 1
+        write_result = False
+
+    if opcode <= 0x9 or opcode in (0xA, 0x7, 0x8):
+        s.flags = list(_flags_from_result(result, carry, overflow))
+
+    if write_result:
+        s.regs[rd] = result & 0xFF
+
+    if opcode not in (0xC, 0xD, 0xE):
+        s.pc = next_pc
+
+    return s
+
+
+def run_until_halt(state: CPUState, max_cycles: int = 256) -> Tuple[CPUState, int]:
+    s = state.copy()
+    for i in range(max_cycles):
+        if s.ctrl[0] == 1:
+            return s, i
+        s = step(s)
+    return s, max_cycles

cpu/state.py

@@ -0,0 +1,103 @@
+"""
+State layout helpers for the 8-bit threshold computer.
+All multi-bit fields are MSB-first.
+"""
+
+from __future__ import annotations
+
+from dataclasses import dataclass
+from typing import List
+
+FLAG_NAMES = ["Z", "N", "C", "V"]
+CTRL_NAMES = ["HALT", "MEM_WE", "MEM_RE", "RESERVED"]
+
+PC_BITS = 8
+IR_BITS = 16
+REG_BITS = 8
+REG_COUNT = 4
+FLAG_BITS = 4
+SP_BITS = 8
+CTRL_BITS = 4
+MEM_BYTES = 256
+MEM_BITS = MEM_BYTES * 8
+
+STATE_BITS = PC_BITS + IR_BITS + (REG_BITS * REG_COUNT) + FLAG_BITS + SP_BITS + CTRL_BITS + MEM_BITS
+
+
+def int_to_bits(value: int, width: int) -> List[int]:
+    return [(value >> (width - 1 - i)) & 1 for i in range(width)]
+
+
+def bits_to_int(bits: List[int]) -> int:
+    value = 0
+    for bit in bits:
+        value = (value << 1) | int(bit)
+    return value
+
+
+@dataclass
+class CPUState:
+    pc: int
+    ir: int
+    regs: List[int]
+    flags: List[int]
+    sp: int
+    ctrl: List[int]
+    mem: List[int]
+
+    def copy(self) -> "CPUState":
+        return CPUState(
+            pc=int(self.pc),
+            ir=int(self.ir),
+            regs=[int(r) for r in self.regs],
+            flags=[int(f) for f in self.flags],
+            sp=int(self.sp),
+            ctrl=[int(c) for c in self.ctrl],
+            mem=[int(m) for m in self.mem],
+        )
+
+
+def pack_state(state: CPUState) -> List[int]:
+    bits: List[int] = []
+    bits.extend(int_to_bits(state.pc, PC_BITS))
+    bits.extend(int_to_bits(state.ir, IR_BITS))
+    for reg in state.regs:
+        bits.extend(int_to_bits(reg, REG_BITS))
+    bits.extend([int(f) for f in state.flags])
+    bits.extend(int_to_bits(state.sp, SP_BITS))
+    bits.extend([int(c) for c in state.ctrl])
+    for byte in state.mem:
+        bits.extend(int_to_bits(byte, REG_BITS))
+    return bits
+
+
+def unpack_state(bits: List[int]) -> CPUState:
+    if len(bits) != STATE_BITS:
+        raise ValueError(f"Expected {STATE_BITS} bits, got {len(bits)}")
+
+    idx = 0
+    pc = bits_to_int(bits[idx:idx + PC_BITS])
+    idx += PC_BITS
+    ir = bits_to_int(bits[idx:idx + IR_BITS])
+    idx += IR_BITS
+
+    regs = []
+    for _ in range(REG_COUNT):
+        regs.append(bits_to_int(bits[idx:idx + REG_BITS]))
+        idx += REG_BITS
+
+    flags = [int(b) for b in bits[idx:idx + FLAG_BITS]]
+    idx += FLAG_BITS
+
+    sp = bits_to_int(bits[idx:idx + SP_BITS])
+    idx += SP_BITS
+
+    ctrl = [int(b) for b in bits[idx:idx + CTRL_BITS]]
+    idx += CTRL_BITS
+
+    mem = []
+    for _ in range(MEM_BYTES):
+        mem.append(bits_to_int(bits[idx:idx + REG_BITS]))
+        idx += REG_BITS
+
+    return CPUState(pc=pc, ir=ir, regs=regs, flags=flags, sp=sp, ctrl=ctrl, mem=mem)

eval/build_memory.py

@@ -0,0 +1,107 @@
+"""
+Generate memory and fetch/load/store buffers for the 8-bit threshold computer.
+Updates neural_computer.safetensors and tensors.txt in-place.
+"""
+
+from __future__ import annotations
+
+from pathlib import Path
+from typing import Dict, Iterable, List
+
+import torch
+from safetensors import safe_open
+from safetensors.torch import save_file
+
+
+MODEL_PATH = Path(__file__).resolve().parent.parent / "neural_computer.safetensors"
+MANIFEST_PATH = Path(__file__).resolve().parent.parent / "tensors.txt"
+
+
+def load_tensors(path: Path) -> Dict[str, torch.Tensor]:
+    tensors: Dict[str, torch.Tensor] = {}
+    with safe_open(str(path), framework="pt") as f:
+        for name in f.keys():
+            tensors[name] = f.get_tensor(name).float().cpu().clone()
+    return tensors
+
+
+def add_gate(tensors: Dict[str, torch.Tensor], name: str, weight: Iterable[float], bias: Iterable[float]) -> None:
+    w_key = f"{name}.weight"
+    b_key = f"{name}.bias"
+    if w_key in tensors or b_key in tensors:
+        raise ValueError(f"Gate already exists: {name}")
+    tensors[w_key] = torch.tensor(list(weight), dtype=torch.float32)
+    tensors[b_key] = torch.tensor(list(bias), dtype=torch.float32)
+
+
+def add_decoder_8to256(tensors: Dict[str, torch.Tensor]) -> None:
+    for addr in range(256):
+        bits = [(addr >> (7 - i)) & 1 for i in range(8)]  # MSB-first
+        weights = [1.0 if bit == 1 else -1.0 for bit in bits]
+        bias = -float(sum(bits))
+        add_gate(tensors, f"memory.addr_decode.out{addr}", weights, [bias])
+
+
+def add_memory_read_mux(tensors: Dict[str, torch.Tensor]) -> None:
+    # AND each mem bit with its address select, then OR across all addresses.
+    for bit in range(8):
+        for addr in range(256):
+            add_gate(tensors, f"memory.read.bit{bit}.and{addr}", [1.0, 1.0], [-2.0])
+        add_gate(tensors, f"memory.read.bit{bit}.or", [1.0] * 256, [-1.0])
+
+
+def add_memory_write_cells(tensors: Dict[str, torch.Tensor]) -> None:
+    # write_sel = addr_select AND write_enable
+    # new_bit = (NOT write_sel AND old_bit) OR (write_sel AND write_data_bit)
+    for addr in range(256):
+        add_gate(tensors, f"memory.write.sel.addr{addr}", [1.0, 1.0], [-2.0])
+        add_gate(tensors, f"memory.write.nsel.addr{addr}", [-1.0], [0.0])
+        for bit in range(8):
+            add_gate(tensors, f"memory.write.addr{addr}.bit{bit}.and_old", [1.0, 1.0], [-2.0])
+            add_gate(tensors, f"memory.write.addr{addr}.bit{bit}.and_new", [1.0, 1.0], [-2.0])
+            add_gate(tensors, f"memory.write.addr{addr}.bit{bit}.or", [1.0, 1.0], [-1.0])
+
+
+def add_fetch_load_store_buffers(tensors: Dict[str, torch.Tensor]) -> None:
+    # Buffer gates: output = input (weight=1, bias=-1)
+    for bit in range(16):
+        add_gate(tensors, f"control.fetch.ir.bit{bit}", [1.0], [-1.0])
+    for bit in range(8):
+        add_gate(tensors, f"control.load.bit{bit}", [1.0], [-1.0])
+        add_gate(tensors, f"control.store.bit{bit}", [1.0], [-1.0])
+        add_gate(tensors, f"control.mem_addr.bit{bit}", [1.0], [-1.0])
+
+
+def update_manifest(tensors: Dict[str, torch.Tensor]) -> None:
+    # Bump manifest version to reflect memory integration.
+    key = "manifest.version"
+    if key not in tensors:
+        tensors[key] = torch.tensor([2.0], dtype=torch.float32)
+        return
+    tensors[key] = torch.tensor([2.0], dtype=torch.float32)
+
+
+def write_manifest(path: Path, tensors: Dict[str, torch.Tensor]) -> None:
+    lines: List[str] = []
+    lines.append("# Tensor Manifest")
+    lines.append(f"# Total: {len(tensors)} tensors")
+    for name in sorted(tensors.keys()):
+        t = tensors[name]
+        values = ", ".join(f"{v:.1f}" for v in t.flatten().tolist())
+        lines.append(f"{name}: shape={list(t.shape)}, values=[{values}]")
+    path.write_text("\n".join(lines) + "\n", encoding="utf-8")
+
+
+def main() -> None:
+    tensors = load_tensors(MODEL_PATH)
+    add_decoder_8to256(tensors)
+    add_memory_read_mux(tensors)
+    add_memory_write_cells(tensors)
+    add_fetch_load_store_buffers(tensors)
+    update_manifest(tensors)
+    save_file(tensors, str(MODEL_PATH))
+    write_manifest(MANIFEST_PATH, tensors)
+
+
+if __name__ == "__main__":
+    main()

eval/comprehensive_eval.py

@@ -1896,17 +1896,17 @@ class CircuitEvaluator:
 
     def test_manifest(self) -> TestResult:
         """Test manifest metadata tensors."""
-        manifest_tensors = [
-            ('manifest.alu_operations', 16),
-            ('manifest.flags', 4),
-            ('manifest.instruction_width', 16),
-            ('manifest.memory_bytes', 256),
-            ('manifest.pc_width', 8),
-            ('manifest.register_width', 8),
-            ('manifest.registers', 4),
-            ('manifest.turing_complete', 1),
-            ('manifest.version', 1),
-        ]
+        manifest_tensors = [
+            ('manifest.alu_operations', 16),
+            ('manifest.flags', 4),
+            ('manifest.instruction_width', 16),
+            ('manifest.memory_bytes', 256),
+            ('manifest.pc_width', 8),
+            ('manifest.register_width', 8),
+            ('manifest.registers', 4),
+            ('manifest.turing_complete', 1),
+            ('manifest.version', 2),
+        ]
 
         failures = []
         passed = 0
@@ -2182,9 +2182,9 @@ class CircuitEvaluator:
 
         return TestResult('control.negated_conditional_jumps', passed, passed, [])
 
-    def test_control_parity_jumps(self) -> TestResult:
-        """Test parity-based conditional jumps (jp, jnp - jump positive/not positive)."""
-        passed = 0
+    def test_control_parity_jumps(self) -> TestResult:
+        """Test parity-based conditional jumps (jp, jnp - jump positive/not positive)."""
+        passed = 0
 
         for jump_type in ['jp', 'jnp', 'jpe', 'jpo']:  # parity even/odd variants
             for bit in range(8):
@@ -2193,9 +2193,161 @@ class CircuitEvaluator:
                         self.reg.get(f'control.{jump_type}.bit{bit}.{comp}.weight')
                         self.reg.get(f'control.{jump_type}.bit{bit}.{comp}.bias')
                         passed += 2
-
-        return TestResult('control.parity_jumps', passed, passed, [])
-
+
+        return TestResult('control.parity_jumps', passed, passed, [])
+
+    # =========================================================================
+    # MEMORY CIRCUITS
+    # =========================================================================
+
+    def test_memory_decoder_8to256(self) -> TestResult:
+        """Test 8-to-256 address decoder exhaustively."""
+        failures = []
+        passed = 0
+        total = 256 * 256
+
+        for addr in range(256):
+            addr_bits = torch.tensor([(addr >> (7 - i)) & 1 for i in range(8)],
+                                     device=self.device, dtype=torch.float32)
+
+            for out_idx in range(256):
+                w = self.reg.get(f'memory.addr_decode.out{out_idx}.weight')
+                b = self.reg.get(f'memory.addr_decode.out{out_idx}.bias')
+                output = heaviside((addr_bits * w).sum() + b).item()
+                expected = 1.0 if out_idx == addr else 0.0
+
+                if output == expected:
+                    passed += 1
+                elif len(failures) < 20:
+                    failures.append(((addr, out_idx), expected, output))
+
+        return TestResult('memory.addr_decode', passed, total, failures)
+
+    def test_memory_read_mux(self) -> TestResult:
+        """Test 256-byte memory read mux for a few representative addresses."""
+        failures = []
+        passed = 0
+        total = 0
+
+        mem = [(addr * 37) & 0xFF for addr in range(256)]
+        test_addrs = [0, 1, 2, 127, 255]
+
+        for addr in test_addrs:
+            addr_bits = torch.tensor([(addr >> (7 - i)) & 1 for i in range(8)],
+                                     device=self.device, dtype=torch.float32)
+
+            selects = []
+            for out_idx in range(256):
+                w = self.reg.get(f'memory.addr_decode.out{out_idx}.weight')
+                b = self.reg.get(f'memory.addr_decode.out{out_idx}.bias')
+                selects.append(heaviside((addr_bits * w).sum() + b).item())
+
+            for bit in range(8):
+                and_vals = []
+                for out_idx in range(256):
+                    mem_bit = float((mem[out_idx] >> (7 - bit)) & 1)
+                    inp = torch.tensor([mem_bit, selects[out_idx]], device=self.device)
+                    w = self.reg.get(f'memory.read.bit{bit}.and{out_idx}.weight')
+                    b = self.reg.get(f'memory.read.bit{bit}.and{out_idx}.bias')
+                    and_vals.append(heaviside((inp * w).sum() + b).item())
+
+                or_inp = torch.tensor(and_vals, device=self.device)
+                w_or = self.reg.get(f'memory.read.bit{bit}.or.weight')
+                b_or = self.reg.get(f'memory.read.bit{bit}.or.bias')
+                output = heaviside((or_inp * w_or).sum() + b_or).item()
+                expected = float((mem[addr] >> (7 - bit)) & 1)
+
+                total += 1
+                if output == expected:
+                    passed += 1
+                elif len(failures) < 20:
+                    failures.append(((addr, bit), expected, output))
+
+        return TestResult('memory.read', passed, total, failures)
+
+    def test_memory_write_cells(self) -> TestResult:
+        """Test memory cell update logic with and without write enable."""
+        failures = []
+        passed = 0
+        total = 0
+
+        mem = [(addr * 13 + 7) & 0xFF for addr in range(256)]
+        test_cases = [
+            (0xA5, 42, 1.0),
+            (0x3C, 200, 0.0),
+        ]
+
+        for write_data, write_addr, write_en in test_cases:
+            addr_bits = torch.tensor([(write_addr >> (7 - i)) & 1 for i in range(8)],
+                                     device=self.device, dtype=torch.float32)
+
+            decodes = []
+            for out_idx in range(256):
+                w = self.reg.get(f'memory.addr_decode.out{out_idx}.weight')
+                b = self.reg.get(f'memory.addr_decode.out{out_idx}.bias')
+                decodes.append(heaviside((addr_bits * w).sum() + b).item())
+
+            for out_idx in range(256):
+                sel_inp = torch.tensor([decodes[out_idx], write_en], device=self.device)
+                w_sel = self.reg.get(f'memory.write.sel.addr{out_idx}.weight')
+                b_sel = self.reg.get(f'memory.write.sel.addr{out_idx}.bias')
+                sel = heaviside((sel_inp * w_sel).sum() + b_sel).item()
+
+                w_nsel = self.reg.get(f'memory.write.nsel.addr{out_idx}.weight')
+                b_nsel = self.reg.get(f'memory.write.nsel.addr{out_idx}.bias')
+                nsel = heaviside(sel * w_nsel + b_nsel).item()
+
+                for bit in range(8):
+                    old_bit = float((mem[out_idx] >> (7 - bit)) & 1)
+                    data_bit = float((write_data >> (7 - bit)) & 1)
+
+                    inp_old = torch.tensor([old_bit, nsel], device=self.device)
+                    w_old = self.reg.get(f'memory.write.addr{out_idx}.bit{bit}.and_old.weight')
+                    b_old = self.reg.get(f'memory.write.addr{out_idx}.bit{bit}.and_old.bias')
+                    and_old = heaviside((inp_old * w_old).sum() + b_old).item()
+
+                    inp_new = torch.tensor([data_bit, sel], device=self.device)
+                    w_new = self.reg.get(f'memory.write.addr{out_idx}.bit{bit}.and_new.weight')
+                    b_new = self.reg.get(f'memory.write.addr{out_idx}.bit{bit}.and_new.bias')
+                    and_new = heaviside((inp_new * w_new).sum() + b_new).item()
+
+                    inp_or = torch.tensor([and_old, and_new], device=self.device)
+                    w_or = self.reg.get(f'memory.write.addr{out_idx}.bit{bit}.or.weight')
+                    b_or = self.reg.get(f'memory.write.addr{out_idx}.bit{bit}.or.bias')
+                    output = heaviside((inp_or * w_or).sum() + b_or).item()
+
+                    expected = data_bit if (write_en == 1.0 and out_idx == write_addr) else old_bit
+
+                    total += 1
+                    if output == expected:
+                        passed += 1
+                    elif len(failures) < 20:
+                        failures.append(((out_idx, bit), expected, output))
+
+        return TestResult('memory.write', passed, total, failures)
+
+    def test_control_fetch_load_store(self) -> TestResult:
+        """Test fetch/load/store buffer gate existence."""
+        passed = 0
+        total = 0
+
+        for bit in range(16):
+            total += 2
+            if self.reg.has(f'control.fetch.ir.bit{bit}.weight'):
+                self.reg.get(f'control.fetch.ir.bit{bit}.weight')
+                self.reg.get(f'control.fetch.ir.bit{bit}.bias')
+                passed += 2
+
+        for bit in range(8):
+            for name in ['control.load', 'control.store', 'control.mem_addr']:
+                total += 2
+                if self.reg.has(f'{name}.bit{bit}.weight'):
+                    self.reg.get(f'{name}.bit{bit}.weight')
+                    self.reg.get(f'{name}.bit{bit}.bias')
+                    passed += 2
+
+        return TestResult('control.fetch_load_store', passed, total, [])
+
     # =========================================================================
     # ARITHMETIC - ADDITIONAL CIRCUITS
     # =========================================================================
@@ -2850,14 +3002,22 @@ class ComprehensiveEvaluator:
         self._run_test(self.evaluator.test_control_register_mux, verbose)
         self._run_test(self.evaluator.test_control_halt, verbose)
         self._run_test(self.evaluator.test_control_pc_load, verbose)
-        self._run_test(self.evaluator.test_control_nop, verbose)
-        self._run_test(self.evaluator.test_control_conditional_jumps, verbose)
-        self._run_test(self.evaluator.test_control_negated_conditional_jumps, verbose)
-        self._run_test(self.evaluator.test_control_parity_jumps, verbose)
-
-        # Error detection
-        if verbose:
-            print("\n=== ERROR DETECTION ===")
+        self._run_test(self.evaluator.test_control_nop, verbose)
+        self._run_test(self.evaluator.test_control_conditional_jumps, verbose)
+        self._run_test(self.evaluator.test_control_negated_conditional_jumps, verbose)
+        self._run_test(self.evaluator.test_control_parity_jumps, verbose)
+
+        # Memory
+        if verbose:
+            print("\n=== MEMORY ===")
+        self._run_test(self.evaluator.test_memory_decoder_8to256, verbose)
+        self._run_test(self.evaluator.test_memory_read_mux, verbose)
+        self._run_test(self.evaluator.test_memory_write_cells, verbose)
+        self._run_test(self.evaluator.test_control_fetch_load_store, verbose)
+
+        # Error detection
+        if verbose:
+            print("\n=== ERROR DETECTION ===")
         self._run_test(self.evaluator.test_even_parity, verbose)
         self._run_test(self.evaluator.test_odd_parity, verbose)
         self._run_test(self.evaluator.test_checksum_8bit, verbose)

eval/cpu_cycle_test.py

@@ -0,0 +1,56 @@
+"""
+Basic CPU cycle smoke test.
+"""
+
+import sys
+from pathlib import Path
+
+sys.path.append(str(Path(__file__).resolve().parent.parent))
+
+from cpu.cycle import run_until_halt
+from cpu.state import CPUState
+
+
+def encode(opcode: int, rd: int, rs: int, imm8: int) -> int:
+    return ((opcode & 0xF) << 12) | ((rd & 0x3) << 10) | ((rs & 0x3) << 8) | (imm8 & 0xFF)
+
+
+def write_instr(mem, addr, instr):
+    mem[addr & 0xFF] = (instr >> 8) & 0xFF
+    mem[(addr + 1) & 0xFF] = instr & 0xFF
+
+
+def main() -> None:
+    mem = [0] * 256
+
+    write_instr(mem, 0x00, encode(0xA, 0, 0, 0x10))  # LOAD R0, [0x10]
+    write_instr(mem, 0x02, encode(0xA, 1, 0, 0x11))  # LOAD R1, [0x11]
+    write_instr(mem, 0x04, encode(0x0, 0, 1, 0x00))  # ADD R0, R1
+    write_instr(mem, 0x06, encode(0xB, 0, 0, 0x12))  # STORE R0 -> [0x12]
+    write_instr(mem, 0x08, encode(0xF, 0, 0, 0x00))  # HALT
+
+    mem[0x10] = 5
+    mem[0x11] = 7
+
+    state = CPUState(
+        pc=0,
+        ir=0,
+        regs=[0, 0, 0, 0],
+        flags=[0, 0, 0, 0],
+        sp=0xFF,
+        ctrl=[0, 0, 0, 0],
+        mem=mem,
+    )
+
+    final, cycles = run_until_halt(state, max_cycles=20)
+
+    assert final.ctrl[0] == 1, "HALT flag not set"
+    assert final.regs[0] == 12, f"R0 expected 12, got {final.regs[0]}"
+    assert final.mem[0x12] == 12, f"MEM[0x12] expected 12, got {final.mem[0x12]}"
+    assert cycles <= 10, f"Unexpected cycle count: {cycles}"
+
+    print("cpu_cycle_test: ok")
+
+
+if __name__ == "__main__":
+    main()

eval/iron_eval.py

@@ -3154,17 +3154,17 @@ class BatchedFitnessEvaluator:
         scores = torch.zeros(pop_size, device=self.device)
         total_tests = 0
 
-        manifest_tensors = [
-            ('manifest.alu_operations', 16),
-            ('manifest.flags', 4),
-            ('manifest.instruction_width', 16),
-            ('manifest.memory_bytes', 256),
-            ('manifest.pc_width', 8),
-            ('manifest.register_width', 8),
-            ('manifest.registers', 4),
-            ('manifest.turing_complete', 1),
-            ('manifest.version', 1),
-        ]
+        manifest_tensors = [
+            ('manifest.alu_operations', 16),
+            ('manifest.flags', 4),
+            ('manifest.instruction_width', 16),
+            ('manifest.memory_bytes', 256),
+            ('manifest.pc_width', 8),
+            ('manifest.register_width', 8),
+            ('manifest.registers', 4),
+            ('manifest.turing_complete', 1),
+            ('manifest.version', 2),
+        ]
 
         for tensor_name, expected_value in manifest_tensors:
             w = pop[tensor_name].view(pop_size, -1)

llm/guide.md

@@ -102,7 +102,7 @@ Total circuit depth: ~32 threshold layers (8 FAs × 4 layers each).
 
 ## 3. Circuit Inventory
 
-The `neural_computer.safetensors` contains 3,122 tensors / 5,648 parameters implementing:
+The `neural_computer.safetensors` contains 24,200 tensors / 40,323 parameters implementing:
 
 | Category | Circuits | Tensors |
 |----------|----------|---------|
@@ -459,7 +459,7 @@ Circuit computation adds ~5-10% overhead:
 - BitInjector: 1 linear layer (16→960)
 - Router: 2 linear layers
 
-The circuits have only 5,648 parameters total—negligible versus the 361M in the base model.
+The circuits have only 40,323 parameters total—negligible versus the 361M in the base model.
 
 ### 9.3 Generalization
 
@@ -547,7 +547,7 @@ Model: [extracts 127, 128] [routes to circuit] [gets 255]
 
 ```
 8bit-threshold-computer/
-├── neural_computer.safetensors    # Frozen circuits (3,122 tensors)
+├── neural_computer.safetensors    # Frozen circuits (24,200 tensors)
 ├── circuit_llm.py                 # Integration architecture
 ├── train_circuit_interface.py     # Training loop
 ├── iron_eval.py                   # Circuit verification (6,590 tests)

neural_computer.safetensors

@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:6c5e11ab199ce8548681595ff4a417a6634f62c2189749ef0d6a4cdb4a384a59
-size 683804
+oid sha256:9c40d35edb9ed7d37c0454b3aacde3d8effc68dfbc707b68ae1feb585836581f
+size 2525316

routing/generate_routing.py

@@ -417,19 +417,19 @@ def generate_pattern_routing():
     return routing
 
 
-def generate_manifest_routing():
-    """Generate routing for manifest (constants, no actual routing)."""
-    return {
-        'manifest.alu_operations': {'type': 'constant', 'value': 16},
-        'manifest.flags': {'type': 'constant', 'value': 4},
-        'manifest.instruction_width': {'type': 'constant', 'value': 16},
-        'manifest.memory_bytes': {'type': 'constant', 'value': 256},
-        'manifest.pc_width': {'type': 'constant', 'value': 8},
-        'manifest.register_width': {'type': 'constant', 'value': 8},
-        'manifest.registers': {'type': 'constant', 'value': 4},
-        'manifest.turing_complete': {'type': 'constant', 'value': 1},
-        'manifest.version': {'type': 'constant', 'value': 1}
-    }
+def generate_manifest_routing():
+    """Generate routing for manifest (constants, no actual routing)."""
+    return {
+        'manifest.alu_operations': {'type': 'constant', 'value': 16},
+        'manifest.flags': {'type': 'constant', 'value': 4},
+        'manifest.instruction_width': {'type': 'constant', 'value': 16},
+        'manifest.memory_bytes': {'type': 'constant', 'value': 256},
+        'manifest.pc_width': {'type': 'constant', 'value': 8},
+        'manifest.register_width': {'type': 'constant', 'value': 8},
+        'manifest.registers': {'type': 'constant', 'value': 4},
+        'manifest.turing_complete': {'type': 'constant', 'value': 1},
+        'manifest.version': {'type': 'constant', 'value': 2}
+    }
 
 
 def generate_multiplier8x8_routing():
@@ -870,9 +870,9 @@ def generate_combinational_routing():
     return routing
 
 
-def generate_control_routing():
-    """Generate routing for control circuits."""
-    routing = {}
+def generate_control_routing():
+    """Generate routing for control circuits."""
+    routing = {}
 
     # Instruction Decoder (4-bit to 16 one-hot)
     internal_dec = {}
@@ -1004,18 +1004,99 @@ def generate_control_routing():
     for flag in ['flag_c', 'flag_n', 'flag_v', 'flag_z']:
         internal_nop[flag] = [f'${flag}']
 
-    routing['control.nop'] = {
-        'inputs': ['$x[0:7]', '$flag_c', '$flag_n', '$flag_v', '$flag_z'],
-        'type': 'nop',
-        'internal': internal_nop
-    }
-
-    return routing
-
-
-def generate_error_detection_routing():
-    """Generate routing for error detection circuits."""
-    routing = {}
+    routing['control.nop'] = {
+        'inputs': ['$x[0:7]', '$flag_c', '$flag_n', '$flag_v', '$flag_z'],
+        'type': 'nop',
+        'internal': internal_nop
+    }
+
+    # Fetch/load/store buffer gates
+    internal_fetch = {f'bit{bit}': [f'$data[{bit}]'] for bit in range(16)}
+    routing['control.fetch.ir'] = {
+        'inputs': ['$data[0:15]'],
+        'type': 'buffer',
+        'internal': internal_fetch
+    }
+
+    internal_load = {f'bit{bit}': [f'$data[{bit}]'] for bit in range(8)}
+    routing['control.load'] = {
+        'inputs': ['$data[0:7]'],
+        'type': 'buffer',
+        'internal': internal_load
+    }
+
+    internal_store = {f'bit{bit}': [f'$data[{bit}]'] for bit in range(8)}
+    routing['control.store'] = {
+        'inputs': ['$data[0:7]'],
+        'type': 'buffer',
+        'internal': internal_store
+    }
+
+    internal_mem_addr = {f'bit{bit}': [f'$addr[{bit}]'] for bit in range(8)}
+    routing['control.mem_addr'] = {
+        'inputs': ['$addr[0:7]'],
+        'type': 'buffer',
+        'internal': internal_mem_addr
+    }
+
+    return routing
+
+
+def generate_memory_routing():
+    """Generate routing for memory decoder, read mux, and write cell update."""
+    routing = {}
+
+    addr_bits = [f'$addr[{i}]' for i in range(8)]
+    internal_dec = {f'out{addr}': addr_bits for addr in range(256)}
+    routing['memory.addr_decode'] = {
+        'inputs': ['$addr[0:7]'],
+        'type': 'decoder',
+        'internal': internal_dec
+    }
+
+    internal_read = {}
+    for bit in range(8):
+        for addr in range(256):
+            internal_read[f'bit{bit}.and{addr}'] = [f'$mem[{addr}][{bit}]', f'$sel[{addr}]']
+        internal_read[f'bit{bit}.or'] = [f'bit{bit}.and{i}' for i in range(256)]
+
+    routing['memory.read'] = {
+        'inputs': ['$mem[0:255][0:7]', '$sel[0:255]'],
+        'type': 'read_mux',
+        'internal': internal_read,
+        'outputs': {f'bit{bit}': f'bit{bit}.or' for bit in range(8)}
+    }
+
+    internal_write = {}
+    for addr in range(256):
+        internal_write[f'sel.addr{addr}'] = [f'$sel[{addr}]', '$we']
+        internal_write[f'nsel.addr{addr}'] = [f'sel.addr{addr}']
+        for bit in range(8):
+            internal_write[f'addr{addr}.bit{bit}.and_old'] = [f'$mem[{addr}][{bit}]', f'nsel.addr{addr}']
+            internal_write[f'addr{addr}.bit{bit}.and_new'] = [f'$write_data[{bit}]', f'sel.addr{addr}']
+            internal_write[f'addr{addr}.bit{bit}.or'] = [
+                f'addr{addr}.bit{bit}.and_old',
+                f'addr{addr}.bit{bit}.and_new'
+            ]
+
+    outputs = {
+        f'mem[{addr}][{bit}]': f'addr{addr}.bit{bit}.or'
+        for addr in range(256) for bit in range(8)
+    }
+
+    routing['memory.write'] = {
+        'inputs': ['$mem[0:255][0:7]', '$write_data[0:7]', '$sel[0:255]', '$we'],
+        'type': 'write_mux',
+        'internal': internal_write,
+        'outputs': outputs
+    }
+
+    return routing
+
+
+def generate_error_detection_routing():
+    """Generate routing for error detection circuits."""
+    routing = {}
 
     # Even Parity Checker
     routing['error_detection.evenparitychecker'] = {
@@ -1338,14 +1419,38 @@ def main():
     print('  Negation')
     routing['circuits'].update(generate_neg8bit_routing())
 
-    print('  2x2 Multiplier')
-    routing['circuits'].update(generate_multiplier2x2_routing())
-
-    print('  8-bit Division')
-    routing['circuits'].update(generate_div8bit_routing())
-
-    print('  Threshold gates')
-    routing['circuits'].update(generate_threshold_routing())
+    print('  2x2 Multiplier')
+    routing['circuits'].update(generate_multiplier2x2_routing())
+
+    print('  8x8 Multiplier')
+    routing['circuits'].update(generate_multiplier8x8_routing())
+
+    print('  8-bit Division')
+    routing['circuits'].update(generate_div8bit_routing())
+
+    print('  ADC/SBC')
+    routing['circuits'].update(generate_adc_sbc_routing())
+
+    print('  Rotate')
+    routing['circuits'].update(generate_rotate_routing())
+
+    print('  Combinational')
+    routing['circuits'].update(generate_combinational_routing())
+
+    print('  Control')
+    routing['circuits'].update(generate_control_routing())
+
+    print('  Memory')
+    routing['circuits'].update(generate_memory_routing())
+
+    print('  Error detection')
+    routing['circuits'].update(generate_error_detection_routing())
+
+    print('  ALU')
+    routing['circuits'].update(generate_alu_routing())
+
+    print('  Threshold gates')
+    routing['circuits'].update(generate_threshold_routing())
 
     print('  Modular arithmetic')
     routing['circuits'].update(generate_modular_routing())

routing/routing_schema.md

@@ -32,8 +32,11 @@ The routing file (`routing.json`) defines how gates are interconnected. Each ent
 4. **Constant**: `"#0"` or `"#1"` - Fixed value
    - Example: `"#1"` for carry-in in two's complement
 
-5. **Relative reference**: `"../sibling.gate"` - Reference to sibling in hierarchy
-   - Example: `"../fa0.cout"` from fa1
+5. **Relative reference**: `"../sibling.gate"` - Reference to sibling in hierarchy
+   - Example: `"../fa0.cout"` from fa1
+
+6. **Memory indexing**: `"$mem[addr][bit]"` or `"$sel[addr]"` - Addressed memory bit or one-hot select line
+   - Example: `"$mem[42][3]"` (addr 42, bit 3), `"$sel[42]"`
 
 ## Circuit Types
 

todo.md

@@ -151,7 +151,7 @@ The machine runs. Callers just provide initial state and collect results.
 - Comparators, threshold gates
 - Conditional jumps
 
-**Current: 6,184 tensors**
+**Current: 24,200 tensors**
 **Projected: ~1.65M tensors (with 64KB memory)**
 
 ## Applications