phanerozoic
/

8bit-threshold-computer

@@ -1,48 +1,32 @@
-# 8bit-threshold-computer-10166
-**A Turing-complete 8-bit CPU implemented as threshold logic gates.**
-This is the original, uncompressed model containing 10,166 bits of information.
-```
-Parameters: 2,392
-Unique Weights: 19
-Information: 10,166 bits
-```
 ---
-## Naming Convention
-The number in the repo name represents the **information content in bits**:
 ```
-Bits = Parameters × log₂(Unique Weights)
-     = 2,392 × log₂(19)
-     = 2,392 × 4.25
-     = 10,166 bits
 ```
-This naming scheme allows direct comparison of model complexity across the family:
-| Model | Parameters | Unique Weights | Bits | Compression |
-|-------|------------|----------------|------|-------------|
-| **8bit-threshold-computer-10166** | 2,392 | 19 | **10,166** | Original |
-| [8bit-threshold-computer-1640](https://huggingface.co/phanerozoic/8bit-threshold-computer-1640) | 386 | 19 | 1,640 | Pattern deduplication |
-| [8bit-threshold-computer-772](https://huggingface.co/phanerozoic/8bit-threshold-computer-772) | 386 | 4 | 772 | Evolutionary minimization |
-Lower bits = more compressed = same computation in less information.
 ---
 ## What Is This?
-A complete 8-bit processor where every logic gate is implemented as a threshold neuron:
-```
-output = 1  if  (Σ wᵢxᵢ + b) ≥ 0
-         0  otherwise
-```
 | Component | Specification |
 |-----------|---------------|
@@ -52,96 +36,122 @@ output = 1  if  (Σ wᵢxᵢ + b) ≥ 0
 | Flags | Zero, Negative, Carry, Overflow |
 | Control | JMP, JZ, JNZ, JC, JNC, JN, JP, JV, JNV, CALL, RET, PUSH, POP |
-**Turing complete.** Verified against 95 programs including loops, recursion, and self-modification.
 ---
-## Model Structure
-This model stores each circuit component as a separate tensor:
-| Metric | Value |
-|--------|-------|
-| Total tensors | 1,194 |
-| Total parameters | 2,392 |
-| Unique weight values | 19 |
-| File size | 119,960 bytes (~120 KB) |
-### Weight Vocabulary
 ```python
-[-8, -7, -6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 8, 16, 32, 64, 128, 256]
-```
-These 19 values are sufficient to implement all Boolean logic and arithmetic circuits.
----
-## Circuit Categories
-The 1,194 tensors implement 93 distinct circuit types:
-| Category | Circuits | Examples |
-|----------|----------|----------|
-| Boolean | 10 | AND, OR, NOT, NAND, NOR, XOR, XNOR, IMPLIES, BIIMPLIES |
-| Arithmetic | 18 | Half adder, full adder, 2/4/8-bit ripple carry, comparators |
-| ALU | 8 | 8-bit ADD, SUB, AND, OR, XOR, NOT, SHL, SHR + control |
-| Combinational | 12 | MUX (2:1, 4:1, 8:1), DEMUX, encoders, decoders, barrel shifter |
-| Control Flow | 15 | JMP, conditional jumps (8 types), CALL, RET, PUSH, POP |
-| Error Detection | 12 | Parity, checksum, CRC-4/8, Hamming encode/decode |
-| Threshold | 10 | k-of-n gates, majority, minority |
-| Pattern Recognition | 8 | Popcount, leading/trailing ones, symmetry detection |
 ---
-## Files
-| File | Description |
-|------|-------------|
-| `neural_computer.safetensors` | All 1,194 circuit tensors (120 KB) |
-| `turing_completeness_test.py` | Verification suite |
----
-## Usage
-```python
-from safetensors.torch import load_file
-# Load model
-tensors = load_file("neural_computer.safetensors")
-print(f"Tensors: {len(tensors)}")
-# Output: Tensors: 1194
-# Check weight vocabulary
-all_weights = set()
-for t in tensors.values():
-    all_weights.update(t.flatten().tolist())
-print(f"Unique weights: {len(all_weights)}")
-# Output: Unique weights: 19
 ```
 ---
-## Compression Opportunity
-Many of the 1,194 tensors are **duplicates** — the same weight pattern reused across different circuits. This model can be compressed via:
-1. **Pattern deduplication** → [8bit-threshold-computer-1640](https://huggingface.co/phanerozoic/8bit-threshold-computer-1640)
-2. **Weight vocabulary minimization** → [8bit-threshold-computer-772](https://huggingface.co/phanerozoic/8bit-threshold-computer-772)
 ---
 ## Citation
 ```bibtex
-@misc{8bit-threshold-computer-10166,
-  title={8bit-threshold-computer-10166: A Threshold Logic CPU},
-  author={phanerozoic},
-  year={2026},
   howpublished={Hugging Face},
-  url={https://huggingface.co/phanerozoic/8bit-threshold-computer-10166}
 }
 ```
@@ -153,11 +163,7 @@ MIT
 ---
-## See Also
-- [8bit-threshold-computer-1640](https://huggingface.co/phanerozoic/8bit-threshold-computer-1640) — Pattern-deduplicated (6.2× smaller)
-- [8bit-threshold-computer-772](https://huggingface.co/phanerozoic/8bit-threshold-computer-772) — Evolutionarily minimized (13.2× smaller)
----
-*2,392 parameters. 19 weights. 10,166 bits. The original.*

+---
+license: mit
+tags:
+- threshold-logic
+- neuromorphic
+- computer-architecture
+- turing-complete
+- loihi
+- truenorth
+- akida
 ---
+# 8bit-threshold-computer
+**A Turing-complete 8-bit CPU implemented entirely as threshold logic gates.**
+Every logic gate is a threshold neuron: `output = 1 if (Σ wᵢxᵢ + b) ≥ 0 else 0`
 ```
+Tensors:    1,482
+Parameters: 3,188
+Tests:      4,416/4,416 passing
 ```
 ---
 ## What Is This?
+A complete 8-bit processor where every operation—from Boolean logic to arithmetic to control flow—is implemented using only weighted sums and step functions. No traditional gates.
 | Component | Specification |
 |-----------|---------------|
 | Flags | Zero, Negative, Carry, Overflow |
 | Control | JMP, JZ, JNZ, JC, JNC, JN, JP, JV, JNV, CALL, RET, PUSH, POP |
+**Turing complete.** Verified with loops, conditionals, recursion, and self-modification.
 ---
+## Circuit Categories
+| Category | Circuits | Examples |
+|----------|----------|----------|
+| Boolean | 9 | AND, OR, NOT, NAND, NOR, XOR, XNOR, IMPLIES, BIIMPLIES |
+| Arithmetic | 18 | Half/full adder, 2/4/8-bit ripple carry, comparators |
+| ALU | 3 | 8-bit ALU, control decoder, flag computation |
+| Combinational | 10 | MUX (2:1, 4:1, 8:1), DEMUX, encoders, decoders |
+| Control Flow | 16 | JMP, conditional jumps, CALL, RET, PUSH, POP |
+| Error Detection | 11 | Parity (XOR tree), checksum, CRC, Hamming |
+| Modular | 11 | Divisibility by 2-12 (multi-layer for non-powers-of-2) |
+| Threshold | 13 | k-of-n gates, majority, minority, exactly-k |
+| Pattern | 10 | Popcount, leading/trailing ones, symmetry |
+---
+## Usage
 ```python
+import torch
+from safetensors.torch import load_file
+tensors = load_file("neural_computer.safetensors")
+def heaviside(x):
+    return (x >= 0).float()
+# AND gate: fires when both inputs are 1
+w = tensors['boolean.and.weight']  # [1, 1]
+b = tensors['boolean.and.bias']    # [-2]
+for a, b_in in [(0,0), (0,1), (1,0), (1,1)]:
+    inp = torch.tensor([a, b_in], dtype=torch.float32)
+    out = heaviside(inp @ w + b)
+    print(f"AND({a}, {b_in}) = {int(out.item())}")
+```
 ---
+## Verification
+The model includes `iron_eval.py` which exhaustively tests all circuits:
+```bash
+python iron_eval.py
+# Output: Fitness: 1.000000 (4416/4416 tests passing)
+```
+### Verification Status
+| Category | Status | Notes |
+|----------|--------|-------|
+| Boolean gates | Coq-derived | Original formal proofs |
+| Arithmetic | Coq-derived | Adders, comparators |
+| ALU | Coq-derived | All 16 operations |
+| Control flow | Coq-derived | Jumps, stack ops |
+| Threshold | Coq-derived | k-of-n gates |
+| **Modular (mod 3,5,6,7,9,10,11,12)** | **Hand-verified** | Multi-layer circuits added manually |
+| **Parity** | **Hand-verified** | XOR tree structure added manually |
+| Modular (mod 2,4,8) | Exact | Single-layer, trivial |
+The modular arithmetic circuits for non-powers-of-2 and the parity circuits were hand-constructed because:
+- Divisibility by 3, 5, etc. is **not linearly separable** in binary
+- 8-bit parity (XOR of all bits) requires a tree of XOR gates
+These circuits pass exhaustive testing but lack formal proofs.
+---
+## Tensor Naming Convention
+```
+{category}.{circuit}[.{layer}][.{component}].{weight|bias}
+Examples:
+  boolean.and.weight
+  boolean.xor.layer1.neuron1.weight
+  arithmetic.ripplecarry8bit.fa7.ha2.sum.layer1.or.weight
+  modular.mod5.layer2.eq3.weight
+  error_detection.paritychecker8bit.stage2.xor1.layer1.nand.bias
 ```
 ---
+## Hardware Compatibility
+All weights are integers. All activations are Heaviside step. Designed for:
+- **Intel Loihi** — Neuromorphic research chip
+- **IBM TrueNorth** — 1M neuron chip
+- **BrainChip Akida** — Edge neuromorphic processor
+---
+## Files
+| File | Description |
+|------|-------------|
+| `neural_computer.safetensors` | All 1,482 circuit tensors (~152 KB) |
+| `iron_eval.py` | Comprehensive test suite (4,416 tests) |
 ---
 ## Citation
 ```bibtex
+@misc{8bit-threshold-computer,
+  title={8bit-threshold-computer: A Turing-Complete Threshold Logic CPU},
+  author={Norton, Charles},
+  year={2025},
   howpublished={Hugging Face},
+  url={https://huggingface.co/phanerozoic/8bit-threshold-computer}
 }
 ```
 ---
+## Links
+- [Coq Proofs](https://github.com/CharlesCNorton/coq-circuits) — Original formal verification
+- [HuggingFace](https://huggingface.co/phanerozoic) — Other models