Add Register File MUX - 84 tensors, 1036/1036 tests pass

neural_computer.safetensors

@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:7c1a8b089563359bb305ebb5586620f0ea128ae2efbb6fab60b0de049fbb0144
-size 659380
+oid sha256:311454049f55ce50e7fb59c9fb8f02c36a939b589cd829a28804feadc1601489
+size 668428

tensors.txt

@@ -1,5 +1,5 @@
 # Tensor Manifest
-# Total: 5944 tensors
+# Total: 6028 tensors
 
 alu.alu8bit.add.bias: shape=[1], values=[0.0]
 alu.alu8bit.add.weight: shape=[16], values=[1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0]
@@ -4871,6 +4871,90 @@ combinational.multiplexer2to1.or.weight: shape=[2], values=[1.0, 1.0]
 combinational.multiplexer4to1.select: shape=[6], values=[1.0, 1.0, 1.0, 1.0, 1.0, 1.0]
 combinational.multiplexer8to1.select: shape=[11], values=[1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0]
 combinational.priorityencoder8bit.priority: shape=[8], values=[128.0, 64.0, 32.0, 16.0, 8.0, 4.0, 2.0, 1.0]
+combinational.regmux4to1.bit0.and0.bias: shape=[1], values=[-3.0]
+combinational.regmux4to1.bit0.and0.weight: shape=[3], values=[1.0, 1.0, 1.0]
+combinational.regmux4to1.bit0.and1.bias: shape=[1], values=[-3.0]
+combinational.regmux4to1.bit0.and1.weight: shape=[3], values=[1.0, 1.0, 1.0]
+combinational.regmux4to1.bit0.and2.bias: shape=[1], values=[-3.0]
+combinational.regmux4to1.bit0.and2.weight: shape=[3], values=[1.0, 1.0, 1.0]
+combinational.regmux4to1.bit0.and3.bias: shape=[1], values=[-3.0]
+combinational.regmux4to1.bit0.and3.weight: shape=[3], values=[1.0, 1.0, 1.0]
+combinational.regmux4to1.bit0.or.bias: shape=[1], values=[-1.0]
+combinational.regmux4to1.bit0.or.weight: shape=[4], values=[1.0, 1.0, 1.0, 1.0]
+combinational.regmux4to1.bit1.and0.bias: shape=[1], values=[-3.0]
+combinational.regmux4to1.bit1.and0.weight: shape=[3], values=[1.0, 1.0, 1.0]
+combinational.regmux4to1.bit1.and1.bias: shape=[1], values=[-3.0]
+combinational.regmux4to1.bit1.and1.weight: shape=[3], values=[1.0, 1.0, 1.0]
+combinational.regmux4to1.bit1.and2.bias: shape=[1], values=[-3.0]
+combinational.regmux4to1.bit1.and2.weight: shape=[3], values=[1.0, 1.0, 1.0]
+combinational.regmux4to1.bit1.and3.bias: shape=[1], values=[-3.0]
+combinational.regmux4to1.bit1.and3.weight: shape=[3], values=[1.0, 1.0, 1.0]
+combinational.regmux4to1.bit1.or.bias: shape=[1], values=[-1.0]
+combinational.regmux4to1.bit1.or.weight: shape=[4], values=[1.0, 1.0, 1.0, 1.0]
+combinational.regmux4to1.bit2.and0.bias: shape=[1], values=[-3.0]
+combinational.regmux4to1.bit2.and0.weight: shape=[3], values=[1.0, 1.0, 1.0]
+combinational.regmux4to1.bit2.and1.bias: shape=[1], values=[-3.0]
+combinational.regmux4to1.bit2.and1.weight: shape=[3], values=[1.0, 1.0, 1.0]
+combinational.regmux4to1.bit2.and2.bias: shape=[1], values=[-3.0]
+combinational.regmux4to1.bit2.and2.weight: shape=[3], values=[1.0, 1.0, 1.0]
+combinational.regmux4to1.bit2.and3.bias: shape=[1], values=[-3.0]
+combinational.regmux4to1.bit2.and3.weight: shape=[3], values=[1.0, 1.0, 1.0]
+combinational.regmux4to1.bit2.or.bias: shape=[1], values=[-1.0]
+combinational.regmux4to1.bit2.or.weight: shape=[4], values=[1.0, 1.0, 1.0, 1.0]
+combinational.regmux4to1.bit3.and0.bias: shape=[1], values=[-3.0]
+combinational.regmux4to1.bit3.and0.weight: shape=[3], values=[1.0, 1.0, 1.0]
+combinational.regmux4to1.bit3.and1.bias: shape=[1], values=[-3.0]
+combinational.regmux4to1.bit3.and1.weight: shape=[3], values=[1.0, 1.0, 1.0]
+combinational.regmux4to1.bit3.and2.bias: shape=[1], values=[-3.0]
+combinational.regmux4to1.bit3.and2.weight: shape=[3], values=[1.0, 1.0, 1.0]
+combinational.regmux4to1.bit3.and3.bias: shape=[1], values=[-3.0]
+combinational.regmux4to1.bit3.and3.weight: shape=[3], values=[1.0, 1.0, 1.0]
+combinational.regmux4to1.bit3.or.bias: shape=[1], values=[-1.0]
+combinational.regmux4to1.bit3.or.weight: shape=[4], values=[1.0, 1.0, 1.0, 1.0]
+combinational.regmux4to1.bit4.and0.bias: shape=[1], values=[-3.0]
+combinational.regmux4to1.bit4.and0.weight: shape=[3], values=[1.0, 1.0, 1.0]
+combinational.regmux4to1.bit4.and1.bias: shape=[1], values=[-3.0]
+combinational.regmux4to1.bit4.and1.weight: shape=[3], values=[1.0, 1.0, 1.0]
+combinational.regmux4to1.bit4.and2.bias: shape=[1], values=[-3.0]
+combinational.regmux4to1.bit4.and2.weight: shape=[3], values=[1.0, 1.0, 1.0]
+combinational.regmux4to1.bit4.and3.bias: shape=[1], values=[-3.0]
+combinational.regmux4to1.bit4.and3.weight: shape=[3], values=[1.0, 1.0, 1.0]
+combinational.regmux4to1.bit4.or.bias: shape=[1], values=[-1.0]
+combinational.regmux4to1.bit4.or.weight: shape=[4], values=[1.0, 1.0, 1.0, 1.0]
+combinational.regmux4to1.bit5.and0.bias: shape=[1], values=[-3.0]
+combinational.regmux4to1.bit5.and0.weight: shape=[3], values=[1.0, 1.0, 1.0]
+combinational.regmux4to1.bit5.and1.bias: shape=[1], values=[-3.0]
+combinational.regmux4to1.bit5.and1.weight: shape=[3], values=[1.0, 1.0, 1.0]
+combinational.regmux4to1.bit5.and2.bias: shape=[1], values=[-3.0]
+combinational.regmux4to1.bit5.and2.weight: shape=[3], values=[1.0, 1.0, 1.0]
+combinational.regmux4to1.bit5.and3.bias: shape=[1], values=[-3.0]
+combinational.regmux4to1.bit5.and3.weight: shape=[3], values=[1.0, 1.0, 1.0]
+combinational.regmux4to1.bit5.or.bias: shape=[1], values=[-1.0]
+combinational.regmux4to1.bit5.or.weight: shape=[4], values=[1.0, 1.0, 1.0, 1.0]
+combinational.regmux4to1.bit6.and0.bias: shape=[1], values=[-3.0]
+combinational.regmux4to1.bit6.and0.weight: shape=[3], values=[1.0, 1.0, 1.0]
+combinational.regmux4to1.bit6.and1.bias: shape=[1], values=[-3.0]
+combinational.regmux4to1.bit6.and1.weight: shape=[3], values=[1.0, 1.0, 1.0]
+combinational.regmux4to1.bit6.and2.bias: shape=[1], values=[-3.0]
+combinational.regmux4to1.bit6.and2.weight: shape=[3], values=[1.0, 1.0, 1.0]
+combinational.regmux4to1.bit6.and3.bias: shape=[1], values=[-3.0]
+combinational.regmux4to1.bit6.and3.weight: shape=[3], values=[1.0, 1.0, 1.0]
+combinational.regmux4to1.bit6.or.bias: shape=[1], values=[-1.0]
+combinational.regmux4to1.bit6.or.weight: shape=[4], values=[1.0, 1.0, 1.0, 1.0]
+combinational.regmux4to1.bit7.and0.bias: shape=[1], values=[-3.0]
+combinational.regmux4to1.bit7.and0.weight: shape=[3], values=[1.0, 1.0, 1.0]
+combinational.regmux4to1.bit7.and1.bias: shape=[1], values=[-3.0]
+combinational.regmux4to1.bit7.and1.weight: shape=[3], values=[1.0, 1.0, 1.0]
+combinational.regmux4to1.bit7.and2.bias: shape=[1], values=[-3.0]
+combinational.regmux4to1.bit7.and2.weight: shape=[3], values=[1.0, 1.0, 1.0]
+combinational.regmux4to1.bit7.and3.bias: shape=[1], values=[-3.0]
+combinational.regmux4to1.bit7.and3.weight: shape=[3], values=[1.0, 1.0, 1.0]
+combinational.regmux4to1.bit7.or.bias: shape=[1], values=[-1.0]
+combinational.regmux4to1.bit7.or.weight: shape=[4], values=[1.0, 1.0, 1.0, 1.0]
+combinational.regmux4to1.not_s0.bias: shape=[1], values=[0.0]
+combinational.regmux4to1.not_s0.weight: shape=[1], values=[-1.0]
+combinational.regmux4to1.not_s1.bias: shape=[1], values=[0.0]
+combinational.regmux4to1.not_s1.weight: shape=[1], values=[-1.0]
 control.call.jump: shape=[1], values=[1.0]
 control.call.push: shape=[1], values=[1.0]
 control.conditionaljump.bit0.and_a.bias: shape=[1], values=[-2.0]

todo.md

@@ -9,7 +9,7 @@
 | NEG                     | Two's complement negate     | DONE - 76 tensors, 256/256 tests pass |
 | Program Counter         | PC register + increment     | Missing                        |
 | PC Load                 | Load PC from jump target    | Missing                        |
-| Register File MUX       | Select 1-of-4 GPRs          | Missing                        |
+| Register File MUX       | Select 1-of-4 GPRs          | DONE - 84 tensors, 1036/1036 tests pass |
 | Register Write Enable   | Write back to register      | Missing                        |
 | Memory Address Register | MAR latch                   | Missing                        |
 | Memory Data Register    | MDR latch                   | Missing                        |