Update README: reflect implemented MUL, DIV, SHL, SHR, comparators

README.md

@@ -17,8 +17,8 @@ tags:
 Every logic gate is a threshold neuron: `output = 1 if (Σ wᵢxᵢ + b) ≥ 0 else 0`
 
 ```
-Tensors:    9,429
-Parameters: 8,286,614
+Tensors:    10,399
+Parameters: 8,288,256
 ```
 
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@@ -453,15 +453,15 @@ The interface generalizes to **all** 65,536 8-bit additions once trained—no me
 
 2. **8-bit subtraction (0-255)** — Two's complement via NOT gates on second operand + carry-in of 1. Reuses adder circuit. Handles negative results as unsigned wrap (200 - 250 = 206). Circuit exists and verified.
 
-3. **8-bit multiplication** — Requires array of AND gates for partial products + adder tree to sum them. 8×8 produces 16-bit result; can truncate to low 8 bits or preserve full width. Circuit NOT yet implemented.
+3. **8-bit multiplication** — 64 AND gates for partial products P[i][j] = A[i] AND B[j]. Uses shift-add accumulation via existing 8-bit adder. Returns low 8 bits of 16-bit result. Circuit exists and verified.
 
-4. **8-bit division with remainder** — Restoring or non-restoring division via subtract-and-shift. Produces 8-bit quotient + 8-bit remainder. Most complex circuit; ~64 subtractors + muxes. NOT yet implemented.
+4. **8-bit division with remainder** — Restoring division with 8 stages. Each stage uses comparison gate (A >= B) and conditional mux. Returns quotient and remainder. Circuit exists and verified.
 
 5. **Bitwise AND, OR, XOR, NOT** — 8 parallel single-layer threshold gates per operation. AND: w=[1,1], b=-2. OR: w=[1,1], b=-1. XOR: 2-layer (OR+NAND→AND). All circuits exist and verified.
 
-6. **Bit shifts (left, right)** — Hardwired routing, not computation. SHL: bit[i] → bit[i-1], inject 0 at LSB. SHR: bit[i] → bit[i+1], inject 0 at MSB. Can implement as identity gates with shifted wiring. NOT yet implemented.
+6. **Bit shifts (left, right)** — Identity gates (w=2, b=-1) with shifted wiring. SHL: out[i] = in[i+1], inject 0 at LSB. SHR: out[i] = in[i-1], inject 0 at MSB. Circuits exist and verified.
 
-7. **Comparisons (>, <, >=, <=, ==)** — Single-layer threshold gates on 16 inputs (8 bits from A, 8 from B). Learned weights encode lexicographic comparison. All 5 comparators exist and verified on 48 test pairs.
+7. **Comparisons (>, <, >=, <=, ==)** — GT, LT, GE, LE: single-layer weighted sum (positional weights 128..1). EQ: two-layer (GE AND LE). All 5 comparators exist and verified.
 
 8. **Divisibility testing (mod 2-12)** — Powers of 2 (mod 2,4,8): single-layer, check relevant bits. Non-powers (mod 3,5,6,7,9,10,11,12): multi-layer circuits encoding residue classes. All 11 circuits exist and exhaustively verified 0-255.
 
@@ -477,10 +477,10 @@ The interface generalizes to **all** 65,536 8-bit additions once trained—no me
 
 | File | Description |
 |------|-------------|
-| `neural_computer.safetensors` | 9,429 tensors, 8,286,614 parameters |
+| `neural_computer.safetensors` | 10,399 tensors, 8,288,256 parameters |
 | `threshold_cpu.py` | CPU state, reference cycle, threshold runtime |
-| `eval.py` | Unified evaluation suite (5,282 tests, GPU-batched) |
-| `build.py` | Build tools for memory circuits and .inputs tensors |
+| `eval.py` | Unified evaluation suite (5,884 tests, GPU-batched) |
+| `build.py` | Build tools for memory, ALU, and .inputs tensors |
 | `prune_weights.py` | Weight magnitude pruning |
 
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