Update README: reflect implemented MUL, DIV, SHL, SHR, comparators

Add SHL, SHR, MUL, DIV, and comparator circuits

Remove Python fallbacks, add Extension Roadmap

Remove completed TODO section from README

Wire all 8 conditional jumps into CPU via imm8[2:0] encoding

Remove eval/ folder, move prune_weights.py to root

Add unified eval.py consolidating iron_eval and comprehensive_eval

Remove routing/ folder, add schema docs to build.py

Add unified build.py with .inputs metadata for all gates

Consolidate CPU into threshold_cpu.py at root

Consolidate routing modules into single routing.py

Add execution model to README, remove tensors.txt and todo.md

Integrate LLM guide into README, remove llm folder

Consolidate LLM modules into single core.py

Consolidate CPU modules into single core.py

Revert "Unify eval files into single eval.py with 100% tensor coverage"

Unify eval files into single eval.py with 100% tensor coverage

Merge origin/main

Sync local state

Remove pycache files

Remove tracked pycache files

Sync packed memory + 16-bit addressing

Add packed memory routing and 16-bit addressing

Add memory circuits and CPU state layout

Add memory circuits and CPU state layout

Delete routing_schema.md with huggingface_hub

Delete routing.json with huggingface_hub

Delete generate_routing.py with huggingface_hub

Upload routing/routing_schema.md with huggingface_hub

Upload routing/routing.json with huggingface_hub

Upload routing/generate_routing.py with huggingface_hub

Upload folder using huggingface_hub

Add comprehensive evaluator with 97% tensor coverage

Upload folder using huggingface_hub

Update roadmap

Roadmap: Threshold Logic Neural Turing Machine with 64KB memory + LLM integration

Update roadmap: self-contained tensor CPU architecture

Add Instruction Decoder - 44 tensors, 16/16 tests pass

Add PC Load MUX - 50 tensors, 1536/1536 tests pass

Add PC Incrementer - 62 tensors, 256/256 tests pass

Add Register File MUX - 84 tensors, 1036/1036 tests pass

Add HALT circuit - 42 tensors, 24576/24576 tests pass

Add NOP circuit - 24 tensors, 4096/4096 tests pass

Add DIV circuit (8-bit division) - 1984 tensors, 65280/65280 tests pass

Add ROR circuit (rotate right through carry) - 18 tensors, 512/512 tests pass

Add ROL circuit (rotate left through carry) - 18 tensors, 512/512 tests pass

Add ASR circuit (arithmetic shift right) - 26 tensors, 256/256 tests pass

Add CMP circuit (compare with flags) - 168 tensors, 65536/65536 tests pass

Add SBC circuit (subtract with borrow) - 160 tensors, 131072/131072 tests pass

Add ADC circuit (add with carry) - 144 tensors, 131072/131072 tests pass