Fix signal registry to use actual gate names instead of canonical aliases

Problem: The signal registry used canonical names (e.g., 'ha1.sum', 'cout')
but the actual gates have different names (e.g., 'ha1.sum.layer2', 'carry_or').
This caused eval to fail when storing gate outputs because name_to_id lookups
returned None for the actual gate names.

Changes to build.py:

1. infer_fulladder_inputs():
- Changed ha1.sum -> ha1.sum.layer2
- The XOR gate's final output is layer2, not a bare 'sum'

2. infer_ripplecarry_inputs():
- Changed fa{idx-1}.cout -> fa{idx-1}.carry_or
- The carry output gate is named carry_or, not cout
- Changed ha1.sum -> ha1.sum.layer2
- Added .or_carry to carry gate detection (some circuits use this variant)

3. infer_multiplier_inputs():
- Changed bit{bit-1}.cout -> bit{bit-1}.carry_or
- Changed ha1.sum -> ha1.sum.layer2
- Added .or_carry to carry gate detection

4. main():
- Added registry.register(gate) after inferring inputs
- This ensures every gate with inferred inputs is registered
- Allows eval to store outputs under the gate's own name

The underlying issue: Multi-layer gates (XOR implemented as OR+NAND->AND)
have their output at 'layer2', but downstream gates were looking for the
parent name. Similarly, full adder carry outputs are 'carry_or' gates but
were referenced as 'cout'.

This is a step toward fixing the 33% tensor coverage issue where eval
could not trace through internal gates due to signal ID mismatches.

.gitignore

@@ -0,0 +1 @@
+__pycache__/

arithmetic.safetensors

@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:cd147a9a27df47020615265d1c0a62b10cd4839d2a6252b1f19c8c2dbf83790d
-size 3062104
+oid sha256:213723982da54ff6c68e0db8976cd41c88eabf2a112e7cbb56fa7aab60684ae5
+size 3026232

build.py

@@ -130,7 +130,8 @@ def infer_fulladder_inputs(gate: str, prefix: str, registry: SignalRegistry) ->
         return [or_out, nand_out]
 
     # HA2 inputs (ha1.sum output + cin)
-    ha1_sum = registry.register(f"{prefix}.ha1.sum")
+    # Use full gate name for ha1.sum output (which is ha1.sum.layer2)
+    ha1_sum = registry.register(f"{prefix}.ha1.sum.layer2")
 
     if '.ha2.sum.layer1' in gate or '.ha2.carry' in gate:
         return [ha1_sum, registry.get_id(f"{prefix}.$cin")]
@@ -169,7 +170,8 @@ def infer_ripplecarry_inputs(gate: str, prefix: str, bits: int, registry: Signal
     if fa_idx == 0:
         cin = registry.register("#0")
     else:
-        cin = registry.register(f"{prefix}.fa{fa_idx-1}.cout")
+        # Carry output is from carry_or gate
+        cin = registry.register(f"{prefix}.fa{fa_idx-1}.carry_or")
 
     # Register this FA's external inputs
     a_bit = registry.get_id(f"{prefix}.$a[{fa_idx}]")
@@ -185,7 +187,7 @@ def infer_ripplecarry_inputs(gate: str, prefix: str, bits: int, registry: Signal
         nand_out = registry.register(f"{parent}.layer1.nand")
         return [or_out, nand_out]
 
-    ha1_sum = registry.register(f"{fa_prefix}.ha1.sum")
+    ha1_sum = registry.register(f"{fa_prefix}.ha1.sum.layer2")
 
     if '.ha2.sum.layer1' in gate or '.ha2.carry' in gate:
         return [ha1_sum, cin]
@@ -196,7 +198,7 @@ def infer_ripplecarry_inputs(gate: str, prefix: str, bits: int, registry: Signal
         nand_out = registry.register(f"{parent}.layer1.nand")
         return [or_out, nand_out]
 
-    if '.carry_or' in gate:
+    if '.carry_or' in gate or '.or_carry' in gate:
         ha1_carry = registry.register(f"{fa_prefix}.ha1.carry")
         ha2_carry = registry.register(f"{fa_prefix}.ha2.carry")
         return [ha1_carry, ha2_carry]
@@ -625,7 +627,7 @@ def infer_multiplier_inputs(gate: str, registry: SignalRegistry) -> List[int]:
         if bit == 0:
             carry_in = registry.get_id("#0")
         else:
-            carry_in = registry.register(f"{prefix}.stage{stage}.bit{bit-1}.cout")
+            carry_in = registry.register(f"{prefix}.stage{stage}.bit{bit-1}.carry_or")
 
         if '.ha1.sum.layer1' in gate or '.ha1.carry' in gate:
             return [prev_bit, pp_bit]
@@ -633,7 +635,7 @@ def infer_multiplier_inputs(gate: str, registry: SignalRegistry) -> List[int]:
             return [registry.register(f"{stage_prefix}.ha1.sum.layer1.or"),
                     registry.register(f"{stage_prefix}.ha1.sum.layer1.nand")]
 
-        ha1_sum = registry.register(f"{stage_prefix}.ha1.sum")
+        ha1_sum = registry.register(f"{stage_prefix}.ha1.sum.layer2")
 
         if '.ha2.sum.layer1' in gate or '.ha2.carry' in gate:
             return [ha1_sum, carry_in]
@@ -641,7 +643,7 @@ def infer_multiplier_inputs(gate: str, registry: SignalRegistry) -> List[int]:
             return [registry.register(f"{stage_prefix}.ha2.sum.layer1.or"),
                     registry.register(f"{stage_prefix}.ha2.sum.layer1.nand")]
 
-        if '.carry_or' in gate:
+        if '.carry_or' in gate or '.or_carry' in gate:
             return [registry.register(f"{stage_prefix}.ha1.carry"),
                     registry.register(f"{stage_prefix}.ha2.carry")]
 
@@ -6952,6 +6954,8 @@ def main():
         inputs = infer_inputs_for_gate(gate, registry, routing)
         if inputs:
             gate_inputs[gate] = inputs
+            # Register the gate itself so eval can store its output
+            registry.register(gate)
         else:
             missing_inputs.append(gate)