neural_attractor: an energy-based threshold computer where computation is relaxation to a ground state and the program is the coupling matrix. No program counter, no clock, no forward-only execution: clamp any subset of wires and relax. AND/OR/NOT energy gadgets (each zero iff the gate relation holds) make it universal by construction; forward evaluation is exact, and clamping outputs runs circuits backward (an 8x8 multiplier compiled to couplings factors 35=5x7, 143=11x13) or solves SAT. Module, tests, artifact builder, and the shipped coupling matrix.

8-bit computer decode and PC sequencing as threshold gates: a 4-to-16 opcode one-hot decoder and a next-PC network (PC+2/PC+4 increment chains plus a priority mux over PC+2, PC+4, the conditional-jump mux, and the direct target). The runtime dispatches on the gate one-hots and takes the next PC from the mux instead of Python slicing and PC+2. Full 10/10 CPU suite passes; all variants rebuilt. Completes decode/PC-as-gates across every runtime (rv32, subleq, 8-bit computer).

rv32 decode and PC sequencing as threshold gates: an opcode-class detector network (exact 7-bit match per class), sign-extended immediate generation muxed over the I/S/B/U/J formats, and a next-PC mux (PC+4 / PC+imm / (rs1+imm)&~1). The threshold CPU reads these gate outputs for dispatch, immediates, and the next PC instead of slicing the instruction word in Python; verified in isolation and by the full RV32 lockstep suite plus randomized programs.

float FMA: fused multiply-add with a single rounding (F extension). A composed gate netlist (pre-normalize a/b/c, full product, dual sticky align shifters into a max-exponent field, cancellation-correct signed-magnitude add, normalize, one round-to-nearest-even, gradual underflow, full specials) for float16 and float32, validated bit-exact against the single-rounding oracle. FMADD/FMSUB/FNMADD/FNMSUB.S wired into the RV32 assembler, reference, and threshold CPU (gate-computed, lockstep-verified); composed FMA test in the eval suite; all variants and neural_rv32 rebuilt.

remove the superseded standalone float normalize stages from the core generators and their structure checks; the composed pipelines carry their own normalizers

float div: full IEEE subnormal support (pre-normalize both operands, then right-shift the aligned quotient by max(0,1-er) for gradual underflow); oracle validated bit-exact against numpy; all float variants rebuilt. add/mul/div subnormals now complete.

float mul: full IEEE subnormal support via a unified right-shift renormalizer (right-shift the product by F+1-min(nlz,exp_base)); oracle validated bit-exact against numpy over all classes including deep underflow; all float variants rebuilt

float add: full IEEE subnormal support (subnormal operands and gradual-underflow results) via effective exponent, implicit-bit selection, and a clamped normalize shift; oracle validated bit-exact against numpy float32/float16

rv32: FCVT.W.S honors the instruction rounding-mode field (RNE/RTZ/RDN/RUP/RMM), verified against an exact rational reference across all modes

neural_reflect: condense its README section to the family's house style; remove the version tag from the module and the model manifest

neural_reflect: host a complete SUBLEQ machine (32-byte memory, fetch-execute loop) inside the interpreter, its memory accessed through indexed addressing

neural_reflect: interpret the SUBLEQ datapath from stored gates; index-read scaling, a compiler from family nets, self-reproduction, self-rewrite, and sequential-state programs

neural_reflect: universal netlist interpreter with indexed addressing, two banks, and a compiler from family nets

Add neural_reflect: a threshold interpreter whose state holds its own weights

Move source library into src/; repoint module, tool, and README paths