8-bit computer decode and PC sequencing as threshold gates: a 4-to-16 opcode one-hot decoder and a next-PC network (PC+2/PC+4 increment chains plus a priority mux over PC+2, PC+4, the conditional-jump mux, and the direct target). The runtime dispatches on the gate one-hots and takes the next PC from the mux instead of Python slicing and PC+2. Full 10/10 CPU suite passes; all variants rebuilt. Completes decode/PC-as-gates across every runtime (rv32, subleq, 8-bit computer).

float FMA: fused multiply-add with a single rounding (F extension). A composed gate netlist (pre-normalize a/b/c, full product, dual sticky align shifters into a max-exponent field, cancellation-correct signed-magnitude add, normalize, one round-to-nearest-even, gradual underflow, full specials) for float16 and float32, validated bit-exact against the single-rounding oracle. FMADD/FMSUB/FNMADD/FNMSUB.S wired into the RV32 assembler, reference, and threshold CPU (gate-computed, lockstep-verified); composed FMA test in the eval suite; all variants and neural_rv32 rebuilt.

remove the superseded standalone float normalize stages from the core generators and their structure checks; the composed pipelines carry their own normalizers

rv32: FCVT.W.S honors the instruction rounding-mode field (RNE/RTZ/RDN/RUP/RMM), verified against an exact rational reference across all modes

Add neural_matrix8 and neural_subleq8io (universal constructor); move dev scripts to tools/

8-bit threshold-logic CPU family: ternary-weight gate networks from a one-instruction SUBLEQ machine to an RV32IM plus F-subset RISC-V processor that runs stock-compiler C; composed IEEE-754 float pipelines with round-to-nearest-even bit-exact to hardware and metadata-driven verification; fully-wired rv32 datapath, FCVT int/float conversions, single gate-routed CPU runtime, leveled fast evaluation; single-file docs and consolidated machine runtime; strict-ternary build