neural_tile: a self-assembling tile computer in the abstract tile assembly model. A tile binds at a site when the summed strength of its matching glues reaches tau, which is the Heaviside gate H(strength.match - tau), so growth is governed by threshold neurons. Verified: the binding decision equals the gate; a general 2-input rule-tile set grows value(x,y)=f(W,S) for f in XOR/AND/OR (529 tiles each, checked against the recurrence, XOR = Sierpinski/Rule 90); a binary counter grows one integer per row (8-bit, 255 rows, row y encodes y) with carry by cooperative binding; both directed (deterministic). Turing-universal at tau=2 (Winfree 1998). Ships variants/neural_tile.safetensors (glue tables + binding-gate weights); eval_all skips it; README section and counts updated (9 standalone machines, 28-file family).

neural_ca: a reversible cellular-automaton computer with no processor. One fixed Margolus block rule (rotate 180, diagonal pairs swap) applied identically to every 2x2 block of a lattice, alternating partition each step. The rule is a self-inverse permutation of the 16 block states, so the whole lattice update is a bijection; verified reversible over random lattices, particle-conserving, with ballistic single-particle motion and deflecting reversible collisions (the billiard-ball model, Turing-universal by Margolus 1984). The rule is Heaviside threshold gates and compiles to a 6-layer ternary matrix tile that is a permutation with a 0.5 margin; that one tile applied to every block is one whole-lattice step, shipped as variants/neural_ca.safetensors. eval_all skips it; README adds the section and updates counts (8 standalone machines, 27-file family round-trip).

Give neural_attractor and neural_reversible a machine metadata field and eval_all skip entries, so python src/eval_all.py variants/ skips them cleanly instead of erroring (it scores fitness variants and skips standalone machines by that field). README sync: list both new machines in the variant table, intro, and repository layout; correct the standalone-machine count (5->7), the eval_all skip count (four->seven), and the universal-constructor family round-trip (23->26 files, 551->971 MB, both new files codec-verified byte-identical).

neural_reversible: ship the reversible arithmetic core as variants/neural_reversible.safetensors (8-bit in-place adder as a reversible gate sequence plus the Heaviside weights realizing each gate); builder round-trips it and confirms the loaded circuit is a bijection computing b<-a+b

neural_attractor: an energy-based threshold computer where computation is relaxation to a ground state and the program is the coupling matrix. No program counter, no clock, no forward-only execution: clamp any subset of wires and relax. AND/OR/NOT energy gadgets (each zero iff the gate relation holds) make it universal by construction; forward evaluation is exact, and clamping outputs runs circuits backward (an 8x8 multiplier compiled to couplings factors 35=5x7, 143=11x13) or solves SAT. Module, tests, artifact builder, and the shipped coupling matrix.

8-bit computer decode and PC sequencing as threshold gates: a 4-to-16 opcode one-hot decoder and a next-PC network (PC+2/PC+4 increment chains plus a priority mux over PC+2, PC+4, the conditional-jump mux, and the direct target). The runtime dispatches on the gate one-hots and takes the next PC from the mux instead of Python slicing and PC+2. Full 10/10 CPU suite passes; all variants rebuilt. Completes decode/PC-as-gates across every runtime (rv32, subleq, 8-bit computer).

rv32 decode and PC sequencing as threshold gates: an opcode-class detector network (exact 7-bit match per class), sign-extended immediate generation muxed over the I/S/B/U/J formats, and a next-PC mux (PC+4 / PC+imm / (rs1+imm)&~1). The threshold CPU reads these gate outputs for dispatch, immediates, and the next PC instead of slicing the instruction word in Python; verified in isolation and by the full RV32 lockstep suite plus randomized programs.

float FMA: fused multiply-add with a single rounding (F extension). A composed gate netlist (pre-normalize a/b/c, full product, dual sticky align shifters into a max-exponent field, cancellation-correct signed-magnitude add, normalize, one round-to-nearest-even, gradual underflow, full specials) for float16 and float32, validated bit-exact against the single-rounding oracle. FMADD/FMSUB/FNMADD/FNMSUB.S wired into the RV32 assembler, reference, and threshold CPU (gate-computed, lockstep-verified); composed FMA test in the eval suite; all variants and neural_rv32 rebuilt.

float div: full IEEE subnormal support (pre-normalize both operands, then right-shift the aligned quotient by max(0,1-er) for gradual underflow); oracle validated bit-exact against numpy; all float variants rebuilt. add/mul/div subnormals now complete.

float mul: full IEEE subnormal support via a unified right-shift renormalizer (right-shift the product by F+1-min(nlz,exp_base)); oracle validated bit-exact against numpy over all classes including deep underflow; all float variants rebuilt

rebuild all float variants and the canonical model with the subnormal-aware add pipeline

neural_reflect: condense its README section to the family's house style; remove the version tag from the module and the model manifest

neural_reflect: interpret the SUBLEQ datapath from stored gates; index-read scaling, a compiler from family nets, self-reproduction, self-rewrite, and sequential-state programs

neural_reflect: universal netlist interpreter with indexed addressing, two banks, and a compiler from family nets

Add neural_reflect: a threshold interpreter whose state holds its own weights

Add neural_matrix8 and neural_subleq8io (universal constructor); move dev scripts to tools/

8-bit threshold-logic CPU family: ternary-weight gate networks from a one-instruction SUBLEQ machine to an RV32IM plus F-subset RISC-V processor that runs stock-compiler C; composed IEEE-754 float pipelines with round-to-nearest-even bit-exact to hardware and metadata-driven verification; fully-wired rv32 datapath, FCVT int/float conversions, single gate-routed CPU runtime, leveled fast evaluation; single-file docs and consolidated machine runtime; strict-ternary build