File size: 3,821 Bytes
76f4679 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 | ---
license: mit
tags:
- pytorch
- safetensors
- threshold-logic
- neuromorphic
- multiplexer
---
# threshold-mux2
2:1 multiplexer. The fundamental building block for data selection, routing one of two inputs to the output based on a select signal.
## Circuit
```
d0 d1
│ │
│ │ s (select)
│ │ │
├───────┼───────┤
│ │ │
▼ │ │
┌───────┐ │ │
│ sel0 │◄──┼───────┤
│d0∧¬s │ │ │
└───────┘ │ │
│ ▼ │
│ ┌───────┐ │
│ │ sel1 │◄──┘
│ │ d1∧s │
│ └───────┘
│ │
└───┬───┘
▼
┌───────┐
│ OR │
└───────┘
│
▼
output
```
## Truth Table
| s | d0 | d1 | out | Description |
|---|----|----|-----|-------------|
| 0 | 0 | 0 | 0 | Select d0 (0) |
| 0 | 0 | 1 | 0 | Select d0 (0) |
| 0 | 1 | 0 | 1 | Select d0 (1) |
| 0 | 1 | 1 | 1 | Select d0 (1) |
| 1 | 0 | 0 | 0 | Select d1 (0) |
| 1 | 0 | 1 | 1 | Select d1 (1) |
| 1 | 1 | 0 | 0 | Select d1 (0) |
| 1 | 1 | 1 | 1 | Select d1 (1) |
Formula: `out = (d0 AND NOT s) OR (d1 AND s)`
## Mechanism
**Layer 1 - Selection Gates:**
The circuit uses two AND-with-complement gates that fire only when their respective data input is selected:
| Gate | Weights [d0, d1, s] | Bias | Function |
|------|---------------------|------|----------|
| sel0 | [1, 0, -1] | -1 | d0 AND NOT(s) |
| sel1 | [0, 1, 1] | -2 | d1 AND s |
**sel0** fires when d0=1 AND s=0:
- The negative weight on s means s=1 inhibits firing
- Bias -1 requires d0=1 to reach threshold when s=0
**sel1** fires when d1=1 AND s=1:
- Both d1 and s must be 1 to overcome bias -2
**Layer 2 - Output:**
Simple OR gate combines the two selection paths.
## Architecture
| Component | Weights | Bias | Function |
|-----------|---------|------|----------|
| sel0 | [1, 0, -1] | -1 | d0 AND NOT(s) |
| sel1 | [0, 1, 1] | -2 | d1 AND s |
| or | [1, 1] | -1 | OR(sel0, sel1) |
## Parameters
| | |
|---|---|
| Inputs | 3 (d0, d1, s) |
| Outputs | 1 |
| Neurons | 3 |
| Layers | 2 |
| Parameters | 11 |
| Magnitude | 10 |
## Building Larger Multiplexers
The MUX2 is the primitive for constructing larger multiplexers:
```
MUX4 = MUX2(MUX2(d0,d1,s0), MUX2(d2,d3,s0), s1)
MUX8 = MUX2(MUX4(d0-d3), MUX4(d4-d7), s2)
MUX16 = MUX2(MUX8(d0-d7), MUX8(d8-d15), s3)
```
Each doubling adds one layer of MUX2 gates.
## Usage
```python
from safetensors.torch import load_file
import torch
w = load_file('model.safetensors')
def mux2(d0, d1, s):
inp = torch.tensor([float(d0), float(d1), float(s)])
# Layer 1: Selection
sel0 = int((inp @ w['sel0.weight'].T + w['sel0.bias'] >= 0).item())
sel1 = int((inp @ w['sel1.weight'].T + w['sel1.bias'] >= 0).item())
# Layer 2: Combine
l1 = torch.tensor([float(sel0), float(sel1)])
return int((l1 @ w['or.weight'].T + w['or.bias'] >= 0).item())
# Examples
print(mux2(1, 0, 0)) # 1 (selects d0)
print(mux2(1, 0, 1)) # 0 (selects d1)
print(mux2(0, 1, 1)) # 1 (selects d1)
```
## Applications
- Data routing in ALUs
- Register file read ports
- Conditional assignment in hardware
- Building blocks for barrel shifters
- Crossbar switches
## Files
```
threshold-mux2/
├── model.safetensors
├── model.py
├── create_safetensors.py
├── config.json
└── README.md
```
## License
MIT
|