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myproject_prj/solution1/syn/verilog/myproject_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_s.v

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+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+
+`timescale 1 ns / 1 ps 
+
+module myproject_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_s (
+        ap_clk,
+        ap_rst,
+        ap_start,
+        start_full_n,
+        ap_done,
+        ap_continue,
+        ap_idle,
+        ap_ready,
+        start_out,
+        start_write,
+        layer56_out_dout,
+        layer56_out_num_data_valid,
+        layer56_out_fifo_cap,
+        layer56_out_empty_n,
+        layer56_out_read,
+        layer35_out_din,
+        layer35_out_num_data_valid,
+        layer35_out_fifo_cap,
+        layer35_out_full_n,
+        layer35_out_write
+);
+
+parameter    ap_ST_fsm_state1 = 3'd1;
+parameter    ap_ST_fsm_state2 = 3'd2;
+parameter    ap_ST_fsm_state3 = 3'd4;
+
+input   ap_clk;
+input   ap_rst;
+input   ap_start;
+input   start_full_n;
+output   ap_done;
+input   ap_continue;
+output   ap_idle;
+output   ap_ready;
+output   start_out;
+output   start_write;
+input  [383:0] layer56_out_dout;
+input  [13:0] layer56_out_num_data_valid;
+input  [13:0] layer56_out_fifo_cap;
+input   layer56_out_empty_n;
+output   layer56_out_read;
+output  [327:0] layer35_out_din;
+input  [12:0] layer35_out_num_data_valid;
+input  [12:0] layer35_out_fifo_cap;
+input   layer35_out_full_n;
+output   layer35_out_write;
+
+reg ap_done;
+reg ap_idle;
+reg start_write;
+reg layer35_out_write;
+
+reg    real_start;
+reg    start_once_reg;
+reg    ap_done_reg;
+(* fsm_encoding = "none" *) reg   [2:0] ap_CS_fsm;
+wire    ap_CS_fsm_state1;
+reg    internal_ap_ready;
+reg    layer56_out_blk_n;
+wire    ap_CS_fsm_state2;
+wire   [0:0] icmp_ln52_fu_1252_p2;
+wire   [15:0] trunc_ln58_fu_1264_p1;
+reg   [15:0] trunc_ln58_reg_1537;
+reg    ap_block_state2;
+reg   [15:0] trunc_ln58_s_reg_1542;
+reg   [15:0] trunc_ln58_10_reg_1547;
+reg   [15:0] trunc_ln58_11_reg_1552;
+reg   [15:0] trunc_ln58_12_reg_1557;
+reg   [15:0] trunc_ln58_13_reg_1562;
+reg   [15:0] trunc_ln58_14_reg_1567;
+reg   [15:0] trunc_ln58_15_reg_1572;
+reg   [15:0] trunc_ln58_16_reg_1577;
+reg   [15:0] trunc_ln58_17_reg_1582;
+reg   [15:0] trunc_ln58_18_reg_1587;
+reg   [15:0] trunc_ln58_19_reg_1592;
+reg   [15:0] trunc_ln58_20_reg_1597;
+reg   [15:0] trunc_ln58_21_reg_1602;
+reg   [15:0] trunc_ln58_22_reg_1607;
+reg   [15:0] trunc_ln58_23_reg_1612;
+reg   [15:0] trunc_ln58_24_reg_1617;
+reg   [15:0] trunc_ln58_25_reg_1622;
+reg   [15:0] trunc_ln58_26_reg_1627;
+reg   [15:0] trunc_ln58_27_reg_1632;
+reg   [15:0] trunc_ln58_28_reg_1637;
+reg   [15:0] trunc_ln58_29_reg_1642;
+reg   [15:0] trunc_ln58_30_reg_1647;
+reg   [15:0] trunc_ln58_31_reg_1652;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_ap_start;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_ap_done;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_ap_idle;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_ap_ready;
+wire   [327:0] grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_layer35_out_din;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_layer35_out_write;
+reg    grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_ap_start_reg;
+reg    ap_block_state2_ignore_call27;
+wire    ap_CS_fsm_state3;
+reg   [12:0] indvar_flatten_fu_666;
+wire   [12:0] add_ln52_fu_1258_p2;
+reg    ap_block_state1;
+reg    layer56_out_read_local;
+reg   [2:0] ap_NS_fsm;
+reg    ap_ST_fsm_state1_blk;
+reg    ap_ST_fsm_state2_blk;
+reg    ap_ST_fsm_state3_blk;
+wire    ap_ce_reg;
+
+// power-on initialization
+initial begin
+#0 start_once_reg = 1'b0;
+#0 ap_done_reg = 1'b0;
+#0 ap_CS_fsm = 3'd1;
+#0 grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_ap_start_reg = 1'b0;
+#0 indvar_flatten_fu_666 = 13'd0;
+end
+
+myproject_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676(
+    .ap_clk(ap_clk),
+    .ap_rst(ap_rst),
+    .ap_start(grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_ap_start),
+    .ap_done(grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_ap_done),
+    .ap_idle(grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_ap_idle),
+    .ap_ready(grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_ap_ready),
+    .p_read(trunc_ln58_reg_1537),
+    .p_read1(trunc_ln58_s_reg_1542),
+    .p_read2(trunc_ln58_10_reg_1547),
+    .p_read3(trunc_ln58_11_reg_1552),
+    .p_read4(trunc_ln58_12_reg_1557),
+    .p_read5(trunc_ln58_13_reg_1562),
+    .p_read6(trunc_ln58_14_reg_1567),
+    .p_read7(trunc_ln58_15_reg_1572),
+    .p_read8(trunc_ln58_16_reg_1577),
+    .p_read9(trunc_ln58_17_reg_1582),
+    .p_read10(trunc_ln58_18_reg_1587),
+    .p_read11(trunc_ln58_19_reg_1592),
+    .p_read12(trunc_ln58_20_reg_1597),
+    .p_read13(trunc_ln58_21_reg_1602),
+    .p_read14(trunc_ln58_22_reg_1607),
+    .p_read15(trunc_ln58_23_reg_1612),
+    .p_read16(trunc_ln58_24_reg_1617),
+    .p_read17(trunc_ln58_25_reg_1622),
+    .p_read18(trunc_ln58_26_reg_1627),
+    .p_read19(trunc_ln58_27_reg_1632),
+    .p_read20(trunc_ln58_28_reg_1637),
+    .p_read21(trunc_ln58_29_reg_1642),
+    .p_read22(trunc_ln58_30_reg_1647),
+    .p_read23(trunc_ln58_31_reg_1652),
+    .layer35_out_din(grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_layer35_out_din),
+    .layer35_out_num_data_valid(13'd0),
+    .layer35_out_fifo_cap(13'd0),
+    .layer35_out_full_n(layer35_out_full_n),
+    .layer35_out_write(grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_layer35_out_write)
+);
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_CS_fsm <= ap_ST_fsm_state1;
+    end else begin
+        ap_CS_fsm <= ap_NS_fsm;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_done_reg <= 1'b0;
+    end else begin
+        if ((ap_continue == 1'b1)) begin
+            ap_done_reg <= 1'b0;
+        end else if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_1252_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+            ap_done_reg <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_ap_start_reg <= 1'b0;
+    end else begin
+        if (((1'b0 == ap_block_state2_ignore_call27) & (icmp_ln52_fu_1252_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+            grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_ap_start_reg <= 1'b1;
+        end else if ((grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_ap_ready == 1'b1)) begin
+            grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_ap_start_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        start_once_reg <= 1'b0;
+    end else begin
+        if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin
+            start_once_reg <= 1'b1;
+        end else if ((internal_ap_ready == 1'b1)) begin
+            start_once_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_state1) & (1'b1 == ap_CS_fsm_state1))) begin
+        indvar_flatten_fu_666 <= 13'd0;
+    end else if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_1252_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        indvar_flatten_fu_666 <= add_ln52_fu_1258_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_state2) & (1'b1 == ap_CS_fsm_state2))) begin
+        trunc_ln58_10_reg_1547 <= {{layer56_out_dout[47:32]}};
+        trunc_ln58_11_reg_1552 <= {{layer56_out_dout[63:48]}};
+        trunc_ln58_12_reg_1557 <= {{layer56_out_dout[79:64]}};
+        trunc_ln58_13_reg_1562 <= {{layer56_out_dout[95:80]}};
+        trunc_ln58_14_reg_1567 <= {{layer56_out_dout[111:96]}};
+        trunc_ln58_15_reg_1572 <= {{layer56_out_dout[127:112]}};
+        trunc_ln58_16_reg_1577 <= {{layer56_out_dout[143:128]}};
+        trunc_ln58_17_reg_1582 <= {{layer56_out_dout[159:144]}};
+        trunc_ln58_18_reg_1587 <= {{layer56_out_dout[175:160]}};
+        trunc_ln58_19_reg_1592 <= {{layer56_out_dout[191:176]}};
+        trunc_ln58_20_reg_1597 <= {{layer56_out_dout[207:192]}};
+        trunc_ln58_21_reg_1602 <= {{layer56_out_dout[223:208]}};
+        trunc_ln58_22_reg_1607 <= {{layer56_out_dout[239:224]}};
+        trunc_ln58_23_reg_1612 <= {{layer56_out_dout[255:240]}};
+        trunc_ln58_24_reg_1617 <= {{layer56_out_dout[271:256]}};
+        trunc_ln58_25_reg_1622 <= {{layer56_out_dout[287:272]}};
+        trunc_ln58_26_reg_1627 <= {{layer56_out_dout[303:288]}};
+        trunc_ln58_27_reg_1632 <= {{layer56_out_dout[319:304]}};
+        trunc_ln58_28_reg_1637 <= {{layer56_out_dout[335:320]}};
+        trunc_ln58_29_reg_1642 <= {{layer56_out_dout[351:336]}};
+        trunc_ln58_30_reg_1647 <= {{layer56_out_dout[367:352]}};
+        trunc_ln58_31_reg_1652 <= {{layer56_out_dout[383:368]}};
+        trunc_ln58_reg_1537 <= trunc_ln58_fu_1264_p1;
+        trunc_ln58_s_reg_1542 <= {{layer56_out_dout[31:16]}};
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_block_state1)) begin
+        ap_ST_fsm_state1_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state1_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_block_state2)) begin
+        ap_ST_fsm_state2_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state2_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_ap_done == 1'b0)) begin
+        ap_ST_fsm_state3_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state3_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_1252_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+        ap_done = 1'b1;
+    end else begin
+        ap_done = ap_done_reg;
+    end
+end
+
+always @ (*) begin
+    if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
+        ap_idle = 1'b1;
+    end else begin
+        ap_idle = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_1252_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+        internal_ap_ready = 1'b1;
+    end else begin
+        internal_ap_ready = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state3)) begin
+        layer35_out_write = grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_layer35_out_write;
+    end else begin
+        layer35_out_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln52_fu_1252_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        layer56_out_blk_n = layer56_out_empty_n;
+    end else begin
+        layer56_out_blk_n = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_1252_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        layer56_out_read_local = 1'b1;
+    end else begin
+        layer56_out_read_local = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((start_once_reg == 1'b0) & (start_full_n == 1'b0))) begin
+        real_start = 1'b0;
+    end else begin
+        real_start = ap_start;
+    end
+end
+
+always @ (*) begin
+    if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin
+        start_write = 1'b1;
+    end else begin
+        start_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    case (ap_CS_fsm)
+        ap_ST_fsm_state1 : begin
+            if (((1'b0 == ap_block_state1) & (1'b1 == ap_CS_fsm_state1))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end
+        end
+        ap_ST_fsm_state2 : begin
+            if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_1252_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end else if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_1252_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end
+        end
+        ap_ST_fsm_state3 : begin
+            if (((1'b1 == ap_CS_fsm_state3) & (grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_ap_done == 1'b1))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end
+        end
+        default : begin
+            ap_NS_fsm = 'bx;
+        end
+    endcase
+end
+
+assign add_ln52_fu_1258_p2 = (indvar_flatten_fu_666 + 13'd1);
+
+assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
+
+assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
+
+assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2];
+
+always @ (*) begin
+    ap_block_state1 = ((real_start == 1'b0) | (ap_done_reg == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_state2 = ((icmp_ln52_fu_1252_p2 == 1'd0) & (layer56_out_empty_n == 1'b0));
+end
+
+always @ (*) begin
+    ap_block_state2_ignore_call27 = ((icmp_ln52_fu_1252_p2 == 1'd0) & (layer56_out_empty_n == 1'b0));
+end
+
+assign ap_ready = internal_ap_ready;
+
+assign grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_ap_start = grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_ap_start_reg;
+
+assign icmp_ln52_fu_1252_p2 = ((indvar_flatten_fu_666 == 13'd4356) ? 1'b1 : 1'b0);
+
+assign layer35_out_din = grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_layer35_out_din;
+
+assign layer56_out_read = layer56_out_read_local;
+
+assign start_out = real_start;
+
+assign trunc_ln58_fu_1264_p1 = layer56_out_dout[15:0];
+
+endmodule //myproject_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_s

myproject_prj/solution1/syn/verilog/myproject_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_s.v

@@ -0,0 +1,373 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+
+`timescale 1 ns / 1 ps 
+
+module myproject_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_s (
+        ap_clk,
+        ap_rst,
+        ap_start,
+        start_full_n,
+        ap_done,
+        ap_continue,
+        ap_idle,
+        ap_ready,
+        start_out,
+        start_write,
+        layer48_out_dout,
+        layer48_out_num_data_valid,
+        layer48_out_fifo_cap,
+        layer48_out_empty_n,
+        layer48_out_read,
+        layer12_out_din,
+        layer12_out_num_data_valid,
+        layer12_out_fifo_cap,
+        layer12_out_full_n,
+        layer12_out_write
+);
+
+parameter    ap_ST_fsm_state1 = 3'd1;
+parameter    ap_ST_fsm_state2 = 3'd2;
+parameter    ap_ST_fsm_state3 = 3'd4;
+
+input   ap_clk;
+input   ap_rst;
+input   ap_start;
+input   start_full_n;
+output   ap_done;
+input   ap_continue;
+output   ap_idle;
+output   ap_ready;
+output   start_out;
+output   start_write;
+input  [255:0] layer48_out_dout;
+input  [9:0] layer48_out_num_data_valid;
+input  [9:0] layer48_out_fifo_cap;
+input   layer48_out_empty_n;
+output   layer48_out_read;
+output  [1311:0] layer12_out_din;
+input  [8:0] layer12_out_num_data_valid;
+input  [8:0] layer12_out_fifo_cap;
+input   layer12_out_full_n;
+output   layer12_out_write;
+
+reg ap_done;
+reg ap_idle;
+reg start_write;
+reg layer12_out_write;
+
+reg    real_start;
+reg    start_once_reg;
+reg    ap_done_reg;
+(* fsm_encoding = "none" *) reg   [2:0] ap_CS_fsm;
+wire    ap_CS_fsm_state1;
+reg    internal_ap_ready;
+reg    layer48_out_blk_n;
+wire    ap_CS_fsm_state2;
+wire   [0:0] icmp_ln52_fu_864_p2;
+wire   [15:0] trunc_ln58_fu_876_p1;
+reg   [15:0] trunc_ln58_reg_1061;
+reg    ap_block_state2;
+reg   [15:0] trunc_ln58_s_reg_1066;
+reg   [15:0] trunc_ln58_226_reg_1071;
+reg   [15:0] trunc_ln58_227_reg_1076;
+reg   [15:0] trunc_ln58_228_reg_1081;
+reg   [15:0] trunc_ln58_229_reg_1086;
+reg   [15:0] trunc_ln58_230_reg_1091;
+reg   [15:0] trunc_ln58_231_reg_1096;
+reg   [15:0] trunc_ln58_232_reg_1101;
+reg   [15:0] trunc_ln58_233_reg_1106;
+reg   [15:0] trunc_ln58_234_reg_1111;
+reg   [15:0] trunc_ln58_235_reg_1116;
+reg   [15:0] trunc_ln58_236_reg_1121;
+reg   [15:0] trunc_ln58_237_reg_1126;
+reg   [15:0] trunc_ln58_238_reg_1131;
+reg   [15:0] trunc_ln58_239_reg_1136;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_470_ap_start;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_470_ap_done;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_470_ap_idle;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_470_ap_ready;
+wire   [1311:0] grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_470_layer12_out_din;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_470_layer12_out_write;
+reg    grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_470_ap_start_reg;
+reg    ap_block_state2_ignore_call19;
+wire    ap_CS_fsm_state3;
+reg   [8:0] indvar_flatten_fu_460;
+wire   [8:0] add_ln52_fu_870_p2;
+reg    ap_block_state1;
+reg    layer48_out_read_local;
+reg   [2:0] ap_NS_fsm;
+reg    ap_ST_fsm_state1_blk;
+reg    ap_ST_fsm_state2_blk;
+reg    ap_ST_fsm_state3_blk;
+wire    ap_ce_reg;
+
+// power-on initialization
+initial begin
+#0 start_once_reg = 1'b0;
+#0 ap_done_reg = 1'b0;
+#0 ap_CS_fsm = 3'd1;
+#0 grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_470_ap_start_reg = 1'b0;
+#0 indvar_flatten_fu_460 = 9'd0;
+end
+
+myproject_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_470(
+    .ap_clk(ap_clk),
+    .ap_rst(ap_rst),
+    .ap_start(grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_470_ap_start),
+    .ap_done(grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_470_ap_done),
+    .ap_idle(grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_470_ap_idle),
+    .ap_ready(grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_470_ap_ready),
+    .p_read(trunc_ln58_reg_1061),
+    .p_read1(trunc_ln58_s_reg_1066),
+    .p_read2(trunc_ln58_226_reg_1071),
+    .p_read3(trunc_ln58_227_reg_1076),
+    .p_read4(trunc_ln58_228_reg_1081),
+    .p_read5(trunc_ln58_229_reg_1086),
+    .p_read6(trunc_ln58_230_reg_1091),
+    .p_read7(trunc_ln58_231_reg_1096),
+    .p_read8(trunc_ln58_232_reg_1101),
+    .p_read9(trunc_ln58_233_reg_1106),
+    .p_read10(trunc_ln58_234_reg_1111),
+    .p_read11(trunc_ln58_235_reg_1116),
+    .p_read12(trunc_ln58_236_reg_1121),
+    .p_read13(trunc_ln58_237_reg_1126),
+    .p_read14(trunc_ln58_238_reg_1131),
+    .p_read15(trunc_ln58_239_reg_1136),
+    .layer12_out_din(grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_470_layer12_out_din),
+    .layer12_out_num_data_valid(9'd0),
+    .layer12_out_fifo_cap(9'd0),
+    .layer12_out_full_n(layer12_out_full_n),
+    .layer12_out_write(grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_470_layer12_out_write)
+);
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_CS_fsm <= ap_ST_fsm_state1;
+    end else begin
+        ap_CS_fsm <= ap_NS_fsm;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_done_reg <= 1'b0;
+    end else begin
+        if ((ap_continue == 1'b1)) begin
+            ap_done_reg <= 1'b0;
+        end else if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_864_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+            ap_done_reg <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_470_ap_start_reg <= 1'b0;
+    end else begin
+        if (((1'b0 == ap_block_state2_ignore_call19) & (icmp_ln52_fu_864_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+            grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_470_ap_start_reg <= 1'b1;
+        end else if ((grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_470_ap_ready == 1'b1)) begin
+            grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_470_ap_start_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        start_once_reg <= 1'b0;
+    end else begin
+        if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin
+            start_once_reg <= 1'b1;
+        end else if ((internal_ap_ready == 1'b1)) begin
+            start_once_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_state1) & (1'b1 == ap_CS_fsm_state1))) begin
+        indvar_flatten_fu_460 <= 9'd0;
+    end else if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_864_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        indvar_flatten_fu_460 <= add_ln52_fu_870_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_state2) & (1'b1 == ap_CS_fsm_state2))) begin
+        trunc_ln58_226_reg_1071 <= {{layer48_out_dout[47:32]}};
+        trunc_ln58_227_reg_1076 <= {{layer48_out_dout[63:48]}};
+        trunc_ln58_228_reg_1081 <= {{layer48_out_dout[79:64]}};
+        trunc_ln58_229_reg_1086 <= {{layer48_out_dout[95:80]}};
+        trunc_ln58_230_reg_1091 <= {{layer48_out_dout[111:96]}};
+        trunc_ln58_231_reg_1096 <= {{layer48_out_dout[127:112]}};
+        trunc_ln58_232_reg_1101 <= {{layer48_out_dout[143:128]}};
+        trunc_ln58_233_reg_1106 <= {{layer48_out_dout[159:144]}};
+        trunc_ln58_234_reg_1111 <= {{layer48_out_dout[175:160]}};
+        trunc_ln58_235_reg_1116 <= {{layer48_out_dout[191:176]}};
+        trunc_ln58_236_reg_1121 <= {{layer48_out_dout[207:192]}};
+        trunc_ln58_237_reg_1126 <= {{layer48_out_dout[223:208]}};
+        trunc_ln58_238_reg_1131 <= {{layer48_out_dout[239:224]}};
+        trunc_ln58_239_reg_1136 <= {{layer48_out_dout[255:240]}};
+        trunc_ln58_reg_1061 <= trunc_ln58_fu_876_p1;
+        trunc_ln58_s_reg_1066 <= {{layer48_out_dout[31:16]}};
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_block_state1)) begin
+        ap_ST_fsm_state1_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state1_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_block_state2)) begin
+        ap_ST_fsm_state2_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state2_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_470_ap_done == 1'b0)) begin
+        ap_ST_fsm_state3_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state3_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_864_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+        ap_done = 1'b1;
+    end else begin
+        ap_done = ap_done_reg;
+    end
+end
+
+always @ (*) begin
+    if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
+        ap_idle = 1'b1;
+    end else begin
+        ap_idle = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_864_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+        internal_ap_ready = 1'b1;
+    end else begin
+        internal_ap_ready = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state3)) begin
+        layer12_out_write = grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_470_layer12_out_write;
+    end else begin
+        layer12_out_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln52_fu_864_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        layer48_out_blk_n = layer48_out_empty_n;
+    end else begin
+        layer48_out_blk_n = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_864_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        layer48_out_read_local = 1'b1;
+    end else begin
+        layer48_out_read_local = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((start_once_reg == 1'b0) & (start_full_n == 1'b0))) begin
+        real_start = 1'b0;
+    end else begin
+        real_start = ap_start;
+    end
+end
+
+always @ (*) begin
+    if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin
+        start_write = 1'b1;
+    end else begin
+        start_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    case (ap_CS_fsm)
+        ap_ST_fsm_state1 : begin
+            if (((1'b0 == ap_block_state1) & (1'b1 == ap_CS_fsm_state1))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end
+        end
+        ap_ST_fsm_state2 : begin
+            if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_864_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end else if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_864_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end
+        end
+        ap_ST_fsm_state3 : begin
+            if (((1'b1 == ap_CS_fsm_state3) & (grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_470_ap_done == 1'b1))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end
+        end
+        default : begin
+            ap_NS_fsm = 'bx;
+        end
+    endcase
+end
+
+assign add_ln52_fu_870_p2 = (indvar_flatten_fu_460 + 9'd1);
+
+assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
+
+assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
+
+assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2];
+
+always @ (*) begin
+    ap_block_state1 = ((real_start == 1'b0) | (ap_done_reg == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_state2 = ((icmp_ln52_fu_864_p2 == 1'd0) & (layer48_out_empty_n == 1'b0));
+end
+
+always @ (*) begin
+    ap_block_state2_ignore_call19 = ((icmp_ln52_fu_864_p2 == 1'd0) & (layer48_out_empty_n == 1'b0));
+end
+
+assign ap_ready = internal_ap_ready;
+
+assign grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_470_ap_start = grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_470_ap_start_reg;
+
+assign icmp_ln52_fu_864_p2 = ((indvar_flatten_fu_460 == 9'd324) ? 1'b1 : 1'b0);
+
+assign layer12_out_din = grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_470_layer12_out_din;
+
+assign layer48_out_read = layer48_out_read_local;
+
+assign start_out = real_start;
+
+assign trunc_ln58_fu_876_p1 = layer48_out_dout[15:0];
+
+endmodule //myproject_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_s

myproject_prj/solution1/syn/verilog/myproject_conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_s.v

@@ -0,0 +1,517 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+
+`timescale 1 ns / 1 ps 
+
+module myproject_conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_s (
+        ap_clk,
+        ap_rst,
+        ap_start,
+        start_full_n,
+        ap_done,
+        ap_continue,
+        ap_idle,
+        ap_ready,
+        start_out,
+        start_write,
+        layer51_out_dout,
+        layer51_out_num_data_valid,
+        layer51_out_fifo_cap,
+        layer51_out_empty_n,
+        layer51_out_read,
+        layer19_out_din,
+        layer19_out_num_data_valid,
+        layer19_out_fifo_cap,
+        layer19_out_full_n,
+        layer19_out_write
+);
+
+parameter    ap_ST_fsm_state1 = 3'd1;
+parameter    ap_ST_fsm_state2 = 3'd2;
+parameter    ap_ST_fsm_state3 = 3'd4;
+
+input   ap_clk;
+input   ap_rst;
+input   ap_start;
+input   start_full_n;
+output   ap_done;
+input   ap_continue;
+output   ap_idle;
+output   ap_ready;
+output   start_out;
+output   start_write;
+input  [1023:0] layer51_out_dout;
+input  [7:0] layer51_out_num_data_valid;
+input  [7:0] layer51_out_fifo_cap;
+input   layer51_out_empty_n;
+output   layer51_out_read;
+output  [2751:0] layer19_out_din;
+input  [6:0] layer19_out_num_data_valid;
+input  [6:0] layer19_out_fifo_cap;
+input   layer19_out_full_n;
+output   layer19_out_write;
+
+reg ap_done;
+reg ap_idle;
+reg start_write;
+reg layer19_out_write;
+
+reg    real_start;
+reg    start_once_reg;
+reg    ap_done_reg;
+(* fsm_encoding = "none" *) reg   [2:0] ap_CS_fsm;
+wire    ap_CS_fsm_state1;
+reg    internal_ap_ready;
+reg    layer51_out_blk_n;
+wire    ap_CS_fsm_state2;
+wire   [0:0] icmp_ln52_fu_3216_p2;
+wire   [15:0] trunc_ln58_fu_3228_p1;
+reg   [15:0] trunc_ln58_reg_3941;
+reg    ap_block_state2;
+reg   [15:0] trunc_ln58_s_reg_3946;
+reg   [15:0] trunc_ln58_46_reg_3951;
+reg   [15:0] trunc_ln58_47_reg_3956;
+reg   [15:0] trunc_ln58_48_reg_3961;
+reg   [15:0] trunc_ln58_49_reg_3966;
+reg   [15:0] trunc_ln58_50_reg_3971;
+reg   [15:0] trunc_ln58_51_reg_3976;
+reg   [15:0] trunc_ln58_52_reg_3981;
+reg   [15:0] trunc_ln58_53_reg_3986;
+reg   [15:0] trunc_ln58_54_reg_3991;
+reg   [15:0] trunc_ln58_55_reg_3996;
+reg   [15:0] trunc_ln58_56_reg_4001;
+reg   [15:0] trunc_ln58_57_reg_4006;
+reg   [15:0] trunc_ln58_58_reg_4011;
+reg   [15:0] trunc_ln58_59_reg_4016;
+reg   [15:0] trunc_ln58_60_reg_4021;
+reg   [15:0] trunc_ln58_61_reg_4026;
+reg   [15:0] trunc_ln58_62_reg_4031;
+reg   [15:0] trunc_ln58_63_reg_4036;
+reg   [15:0] trunc_ln58_64_reg_4041;
+reg   [15:0] trunc_ln58_65_reg_4046;
+reg   [15:0] trunc_ln58_66_reg_4051;
+reg   [15:0] trunc_ln58_67_reg_4056;
+reg   [15:0] trunc_ln58_68_reg_4061;
+reg   [15:0] trunc_ln58_69_reg_4066;
+reg   [15:0] trunc_ln58_70_reg_4071;
+reg   [15:0] trunc_ln58_71_reg_4076;
+reg   [15:0] trunc_ln58_72_reg_4081;
+reg   [15:0] trunc_ln58_73_reg_4086;
+reg   [15:0] trunc_ln58_74_reg_4091;
+reg   [15:0] trunc_ln58_75_reg_4096;
+reg   [15:0] trunc_ln58_76_reg_4101;
+reg   [15:0] trunc_ln58_77_reg_4106;
+reg   [15:0] trunc_ln58_78_reg_4111;
+reg   [15:0] trunc_ln58_79_reg_4116;
+reg   [15:0] trunc_ln58_80_reg_4121;
+reg   [15:0] trunc_ln58_81_reg_4126;
+reg   [15:0] trunc_ln58_82_reg_4131;
+reg   [15:0] trunc_ln58_83_reg_4136;
+reg   [15:0] trunc_ln58_84_reg_4141;
+reg   [15:0] trunc_ln58_85_reg_4146;
+reg   [15:0] trunc_ln58_86_reg_4151;
+reg   [15:0] trunc_ln58_87_reg_4156;
+reg   [15:0] trunc_ln58_88_reg_4161;
+reg   [15:0] trunc_ln58_89_reg_4166;
+reg   [15:0] trunc_ln58_90_reg_4171;
+reg   [15:0] trunc_ln58_91_reg_4176;
+reg   [15:0] trunc_ln58_92_reg_4181;
+reg   [15:0] trunc_ln58_93_reg_4186;
+reg   [15:0] trunc_ln58_94_reg_4191;
+reg   [15:0] trunc_ln58_95_reg_4196;
+reg   [15:0] trunc_ln58_96_reg_4201;
+reg   [15:0] trunc_ln58_97_reg_4206;
+reg   [15:0] trunc_ln58_98_reg_4211;
+reg   [15:0] trunc_ln58_99_reg_4216;
+reg   [15:0] trunc_ln58_100_reg_4221;
+reg   [15:0] trunc_ln58_101_reg_4226;
+reg   [15:0] trunc_ln58_102_reg_4231;
+reg   [15:0] trunc_ln58_103_reg_4236;
+reg   [15:0] trunc_ln58_104_reg_4241;
+reg   [15:0] trunc_ln58_105_reg_4246;
+reg   [15:0] trunc_ln58_106_reg_4251;
+reg   [15:0] trunc_ln58_107_reg_4256;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1718_ap_start;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1718_ap_done;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1718_ap_idle;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1718_ap_ready;
+wire   [2751:0] grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1718_layer19_out_din;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1718_layer19_out_write;
+reg    grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1718_ap_start_reg;
+reg    ap_block_state2_ignore_call67;
+wire    ap_CS_fsm_state3;
+reg   [6:0] indvar_flatten_fu_1708;
+wire   [6:0] add_ln52_fu_3222_p2;
+reg    ap_block_state1;
+reg    layer51_out_read_local;
+reg   [2:0] ap_NS_fsm;
+reg    ap_ST_fsm_state1_blk;
+reg    ap_ST_fsm_state2_blk;
+reg    ap_ST_fsm_state3_blk;
+wire    ap_ce_reg;
+
+// power-on initialization
+initial begin
+#0 start_once_reg = 1'b0;
+#0 ap_done_reg = 1'b0;
+#0 ap_CS_fsm = 3'd1;
+#0 grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1718_ap_start_reg = 1'b0;
+#0 indvar_flatten_fu_1708 = 7'd0;
+end
+
+myproject_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1718(
+    .ap_clk(ap_clk),
+    .ap_rst(ap_rst),
+    .ap_start(grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1718_ap_start),
+    .ap_done(grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1718_ap_done),
+    .ap_idle(grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1718_ap_idle),
+    .ap_ready(grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1718_ap_ready),
+    .p_read(trunc_ln58_reg_3941),
+    .p_read1(trunc_ln58_s_reg_3946),
+    .p_read2(trunc_ln58_46_reg_3951),
+    .p_read3(trunc_ln58_47_reg_3956),
+    .p_read4(trunc_ln58_48_reg_3961),
+    .p_read5(trunc_ln58_49_reg_3966),
+    .p_read6(trunc_ln58_50_reg_3971),
+    .p_read7(trunc_ln58_51_reg_3976),
+    .p_read8(trunc_ln58_52_reg_3981),
+    .p_read9(trunc_ln58_53_reg_3986),
+    .p_read10(trunc_ln58_54_reg_3991),
+    .p_read11(trunc_ln58_55_reg_3996),
+    .p_read12(trunc_ln58_56_reg_4001),
+    .p_read13(trunc_ln58_57_reg_4006),
+    .p_read14(trunc_ln58_58_reg_4011),
+    .p_read15(trunc_ln58_59_reg_4016),
+    .p_read16(trunc_ln58_60_reg_4021),
+    .p_read17(trunc_ln58_61_reg_4026),
+    .p_read18(trunc_ln58_62_reg_4031),
+    .p_read19(trunc_ln58_63_reg_4036),
+    .p_read20(trunc_ln58_64_reg_4041),
+    .p_read21(trunc_ln58_65_reg_4046),
+    .p_read22(trunc_ln58_66_reg_4051),
+    .p_read23(trunc_ln58_67_reg_4056),
+    .p_read24(trunc_ln58_68_reg_4061),
+    .p_read25(trunc_ln58_69_reg_4066),
+    .p_read26(trunc_ln58_70_reg_4071),
+    .p_read27(trunc_ln58_71_reg_4076),
+    .p_read28(trunc_ln58_72_reg_4081),
+    .p_read29(trunc_ln58_73_reg_4086),
+    .p_read30(trunc_ln58_74_reg_4091),
+    .p_read31(trunc_ln58_75_reg_4096),
+    .p_read32(trunc_ln58_76_reg_4101),
+    .p_read33(trunc_ln58_77_reg_4106),
+    .p_read34(trunc_ln58_78_reg_4111),
+    .p_read35(trunc_ln58_79_reg_4116),
+    .p_read36(trunc_ln58_80_reg_4121),
+    .p_read37(trunc_ln58_81_reg_4126),
+    .p_read38(trunc_ln58_82_reg_4131),
+    .p_read39(trunc_ln58_83_reg_4136),
+    .p_read40(trunc_ln58_84_reg_4141),
+    .p_read41(trunc_ln58_85_reg_4146),
+    .p_read42(trunc_ln58_86_reg_4151),
+    .p_read43(trunc_ln58_87_reg_4156),
+    .p_read44(trunc_ln58_88_reg_4161),
+    .p_read45(trunc_ln58_89_reg_4166),
+    .p_read46(trunc_ln58_90_reg_4171),
+    .p_read47(trunc_ln58_91_reg_4176),
+    .p_read48(trunc_ln58_92_reg_4181),
+    .p_read49(trunc_ln58_93_reg_4186),
+    .p_read50(trunc_ln58_94_reg_4191),
+    .p_read51(trunc_ln58_95_reg_4196),
+    .p_read52(trunc_ln58_96_reg_4201),
+    .p_read53(trunc_ln58_97_reg_4206),
+    .p_read54(trunc_ln58_98_reg_4211),
+    .p_read55(trunc_ln58_99_reg_4216),
+    .p_read56(trunc_ln58_100_reg_4221),
+    .p_read57(trunc_ln58_101_reg_4226),
+    .p_read58(trunc_ln58_102_reg_4231),
+    .p_read59(trunc_ln58_103_reg_4236),
+    .p_read60(trunc_ln58_104_reg_4241),
+    .p_read61(trunc_ln58_105_reg_4246),
+    .p_read62(trunc_ln58_106_reg_4251),
+    .p_read63(trunc_ln58_107_reg_4256),
+    .layer19_out_din(grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1718_layer19_out_din),
+    .layer19_out_num_data_valid(7'd0),
+    .layer19_out_fifo_cap(7'd0),
+    .layer19_out_full_n(layer19_out_full_n),
+    .layer19_out_write(grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1718_layer19_out_write)
+);
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_CS_fsm <= ap_ST_fsm_state1;
+    end else begin
+        ap_CS_fsm <= ap_NS_fsm;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_done_reg <= 1'b0;
+    end else begin
+        if ((ap_continue == 1'b1)) begin
+            ap_done_reg <= 1'b0;
+        end else if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_3216_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+            ap_done_reg <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1718_ap_start_reg <= 1'b0;
+    end else begin
+        if (((1'b0 == ap_block_state2_ignore_call67) & (icmp_ln52_fu_3216_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+            grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1718_ap_start_reg <= 1'b1;
+        end else if ((grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1718_ap_ready == 1'b1)) begin
+            grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1718_ap_start_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        start_once_reg <= 1'b0;
+    end else begin
+        if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin
+            start_once_reg <= 1'b1;
+        end else if ((internal_ap_ready == 1'b1)) begin
+            start_once_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_state1) & (1'b1 == ap_CS_fsm_state1))) begin
+        indvar_flatten_fu_1708 <= 7'd0;
+    end else if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_3216_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        indvar_flatten_fu_1708 <= add_ln52_fu_3222_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_state2) & (1'b1 == ap_CS_fsm_state2))) begin
+        trunc_ln58_100_reg_4221 <= {{layer51_out_dout[911:896]}};
+        trunc_ln58_101_reg_4226 <= {{layer51_out_dout[927:912]}};
+        trunc_ln58_102_reg_4231 <= {{layer51_out_dout[943:928]}};
+        trunc_ln58_103_reg_4236 <= {{layer51_out_dout[959:944]}};
+        trunc_ln58_104_reg_4241 <= {{layer51_out_dout[975:960]}};
+        trunc_ln58_105_reg_4246 <= {{layer51_out_dout[991:976]}};
+        trunc_ln58_106_reg_4251 <= {{layer51_out_dout[1007:992]}};
+        trunc_ln58_107_reg_4256 <= {{layer51_out_dout[1023:1008]}};
+        trunc_ln58_46_reg_3951 <= {{layer51_out_dout[47:32]}};
+        trunc_ln58_47_reg_3956 <= {{layer51_out_dout[63:48]}};
+        trunc_ln58_48_reg_3961 <= {{layer51_out_dout[79:64]}};
+        trunc_ln58_49_reg_3966 <= {{layer51_out_dout[95:80]}};
+        trunc_ln58_50_reg_3971 <= {{layer51_out_dout[111:96]}};
+        trunc_ln58_51_reg_3976 <= {{layer51_out_dout[127:112]}};
+        trunc_ln58_52_reg_3981 <= {{layer51_out_dout[143:128]}};
+        trunc_ln58_53_reg_3986 <= {{layer51_out_dout[159:144]}};
+        trunc_ln58_54_reg_3991 <= {{layer51_out_dout[175:160]}};
+        trunc_ln58_55_reg_3996 <= {{layer51_out_dout[191:176]}};
+        trunc_ln58_56_reg_4001 <= {{layer51_out_dout[207:192]}};
+        trunc_ln58_57_reg_4006 <= {{layer51_out_dout[223:208]}};
+        trunc_ln58_58_reg_4011 <= {{layer51_out_dout[239:224]}};
+        trunc_ln58_59_reg_4016 <= {{layer51_out_dout[255:240]}};
+        trunc_ln58_60_reg_4021 <= {{layer51_out_dout[271:256]}};
+        trunc_ln58_61_reg_4026 <= {{layer51_out_dout[287:272]}};
+        trunc_ln58_62_reg_4031 <= {{layer51_out_dout[303:288]}};
+        trunc_ln58_63_reg_4036 <= {{layer51_out_dout[319:304]}};
+        trunc_ln58_64_reg_4041 <= {{layer51_out_dout[335:320]}};
+        trunc_ln58_65_reg_4046 <= {{layer51_out_dout[351:336]}};
+        trunc_ln58_66_reg_4051 <= {{layer51_out_dout[367:352]}};
+        trunc_ln58_67_reg_4056 <= {{layer51_out_dout[383:368]}};
+        trunc_ln58_68_reg_4061 <= {{layer51_out_dout[399:384]}};
+        trunc_ln58_69_reg_4066 <= {{layer51_out_dout[415:400]}};
+        trunc_ln58_70_reg_4071 <= {{layer51_out_dout[431:416]}};
+        trunc_ln58_71_reg_4076 <= {{layer51_out_dout[447:432]}};
+        trunc_ln58_72_reg_4081 <= {{layer51_out_dout[463:448]}};
+        trunc_ln58_73_reg_4086 <= {{layer51_out_dout[479:464]}};
+        trunc_ln58_74_reg_4091 <= {{layer51_out_dout[495:480]}};
+        trunc_ln58_75_reg_4096 <= {{layer51_out_dout[511:496]}};
+        trunc_ln58_76_reg_4101 <= {{layer51_out_dout[527:512]}};
+        trunc_ln58_77_reg_4106 <= {{layer51_out_dout[543:528]}};
+        trunc_ln58_78_reg_4111 <= {{layer51_out_dout[559:544]}};
+        trunc_ln58_79_reg_4116 <= {{layer51_out_dout[575:560]}};
+        trunc_ln58_80_reg_4121 <= {{layer51_out_dout[591:576]}};
+        trunc_ln58_81_reg_4126 <= {{layer51_out_dout[607:592]}};
+        trunc_ln58_82_reg_4131 <= {{layer51_out_dout[623:608]}};
+        trunc_ln58_83_reg_4136 <= {{layer51_out_dout[639:624]}};
+        trunc_ln58_84_reg_4141 <= {{layer51_out_dout[655:640]}};
+        trunc_ln58_85_reg_4146 <= {{layer51_out_dout[671:656]}};
+        trunc_ln58_86_reg_4151 <= {{layer51_out_dout[687:672]}};
+        trunc_ln58_87_reg_4156 <= {{layer51_out_dout[703:688]}};
+        trunc_ln58_88_reg_4161 <= {{layer51_out_dout[719:704]}};
+        trunc_ln58_89_reg_4166 <= {{layer51_out_dout[735:720]}};
+        trunc_ln58_90_reg_4171 <= {{layer51_out_dout[751:736]}};
+        trunc_ln58_91_reg_4176 <= {{layer51_out_dout[767:752]}};
+        trunc_ln58_92_reg_4181 <= {{layer51_out_dout[783:768]}};
+        trunc_ln58_93_reg_4186 <= {{layer51_out_dout[799:784]}};
+        trunc_ln58_94_reg_4191 <= {{layer51_out_dout[815:800]}};
+        trunc_ln58_95_reg_4196 <= {{layer51_out_dout[831:816]}};
+        trunc_ln58_96_reg_4201 <= {{layer51_out_dout[847:832]}};
+        trunc_ln58_97_reg_4206 <= {{layer51_out_dout[863:848]}};
+        trunc_ln58_98_reg_4211 <= {{layer51_out_dout[879:864]}};
+        trunc_ln58_99_reg_4216 <= {{layer51_out_dout[895:880]}};
+        trunc_ln58_reg_3941 <= trunc_ln58_fu_3228_p1;
+        trunc_ln58_s_reg_3946 <= {{layer51_out_dout[31:16]}};
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_block_state1)) begin
+        ap_ST_fsm_state1_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state1_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_block_state2)) begin
+        ap_ST_fsm_state2_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state2_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1718_ap_done == 1'b0)) begin
+        ap_ST_fsm_state3_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state3_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_3216_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+        ap_done = 1'b1;
+    end else begin
+        ap_done = ap_done_reg;
+    end
+end
+
+always @ (*) begin
+    if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
+        ap_idle = 1'b1;
+    end else begin
+        ap_idle = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_3216_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+        internal_ap_ready = 1'b1;
+    end else begin
+        internal_ap_ready = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state3)) begin
+        layer19_out_write = grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1718_layer19_out_write;
+    end else begin
+        layer19_out_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln52_fu_3216_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        layer51_out_blk_n = layer51_out_empty_n;
+    end else begin
+        layer51_out_blk_n = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_3216_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        layer51_out_read_local = 1'b1;
+    end else begin
+        layer51_out_read_local = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((start_once_reg == 1'b0) & (start_full_n == 1'b0))) begin
+        real_start = 1'b0;
+    end else begin
+        real_start = ap_start;
+    end
+end
+
+always @ (*) begin
+    if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin
+        start_write = 1'b1;
+    end else begin
+        start_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    case (ap_CS_fsm)
+        ap_ST_fsm_state1 : begin
+            if (((1'b0 == ap_block_state1) & (1'b1 == ap_CS_fsm_state1))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end
+        end
+        ap_ST_fsm_state2 : begin
+            if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_3216_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end else if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_3216_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end
+        end
+        ap_ST_fsm_state3 : begin
+            if (((grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1718_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state3))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end
+        end
+        default : begin
+            ap_NS_fsm = 'bx;
+        end
+    endcase
+end
+
+assign add_ln52_fu_3222_p2 = (indvar_flatten_fu_1708 + 7'd1);
+
+assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
+
+assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
+
+assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2];
+
+always @ (*) begin
+    ap_block_state1 = ((real_start == 1'b0) | (ap_done_reg == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_state2 = ((icmp_ln52_fu_3216_p2 == 1'd0) & (layer51_out_empty_n == 1'b0));
+end
+
+always @ (*) begin
+    ap_block_state2_ignore_call67 = ((icmp_ln52_fu_3216_p2 == 1'd0) & (layer51_out_empty_n == 1'b0));
+end
+
+assign ap_ready = internal_ap_ready;
+
+assign grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1718_ap_start = grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1718_ap_start_reg;
+
+assign icmp_ln52_fu_3216_p2 = ((indvar_flatten_fu_1708 == 7'd100) ? 1'b1 : 1'b0);
+
+assign layer19_out_din = grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1718_layer19_out_din;
+
+assign layer51_out_read = layer51_out_read_local;
+
+assign start_out = real_start;
+
+assign trunc_ln58_fu_3228_p1 = layer51_out_dout[15:0];
+
+endmodule //myproject_conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_s

myproject_prj/solution1/syn/verilog/myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_oudEe.v

@@ -0,0 +1,42 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1 ns / 1 ps
+module myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_oudEe (
+    address0, ce0, q0, 
+    reset, clk);
+
+parameter DataWidth = 3;
+parameter AddressWidth = 7;
+parameter AddressRange = 72;
+ 
+input[AddressWidth-1:0] address0;
+input ce0;
+output reg[DataWidth-1:0] q0;
+
+input reset;
+input clk;
+
+ 
+reg [DataWidth-1:0] rom0[0:AddressRange-1];
+
+
+initial begin
+     
+    $readmemh("./myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_oudEe.dat", rom0);
+end
+
+  
+always @(posedge clk) 
+begin 
+    if (ce0) 
+    begin
+        q0 <= rom0[address0];
+    end
+end
+
+
+endmodule
+

myproject_prj/solution1/syn/verilog/myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s_outidx_5_ROM_dkF.dat

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myproject_prj/solution1/syn/verilog/myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s_w14_ROM_NP_BRdlF.dat

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myproject_prj/solution1/syn/verilog/myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s_w14_ROM_NP_BRdlF.v

@@ -0,0 +1,42 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1 ns / 1 ps
+module myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s_w14_ROM_NP_BRdlF (
+    address0, ce0, q0, 
+    reset, clk);
+
+parameter DataWidth = 250;
+parameter AddressWidth = 10;
+parameter AddressRange = 576;
+ 
+input[AddressWidth-1:0] address0;
+input ce0;
+output reg[DataWidth-1:0] q0;
+
+input reset;
+input clk;
+
+ 
+(* rom_style = "block" *)reg [DataWidth-1:0] rom0[0:AddressRange-1];
+
+
+initial begin
+     
+    $readmemh("./myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s_w14_ROM_NP_BRdlF.dat", rom0);
+end
+
+  
+always @(posedge clk) 
+begin 
+    if (ce0) 
+    begin
+        q0 <= rom0[address0];
+    end
+end
+
+
+endmodule
+

myproject_prj/solution1/syn/verilog/myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config19_mult_s_outidx_7_ROM_g0b.v

@@ -0,0 +1,42 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1 ns / 1 ps
+module myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config19_mult_s_outidx_7_ROM_g0b (
+    address0, ce0, q0, 
+    reset, clk);
+
+parameter DataWidth = 1;
+parameter AddressWidth = 11;
+parameter AddressRange = 1152;
+ 
+input[AddressWidth-1:0] address0;
+input ce0;
+output reg[DataWidth-1:0] q0;
+
+input reset;
+input clk;
+
+ 
+reg [DataWidth-1:0] rom0[0:AddressRange-1];
+
+
+initial begin
+     
+    $readmemh("./myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config19_mult_s_outidx_7_ROM_g0b.dat", rom0);
+end
+
+  
+always @(posedge clk) 
+begin 
+    if (ce0) 
+    begin
+        q0 <= rom0[address0];
+    end
+end
+
+
+endmodule
+

myproject_prj/solution1/syn/verilog/myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s_w37_ROM_NP_BRoic.dat

@@ -0,0 +1,144 @@
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myproject_prj/solution1/syn/verilog/myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s.v

@@ -0,0 +1,663 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+
+`timescale 1 ns / 1 ps 
+
+module myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s (
+        ap_clk,
+        ap_rst,
+        ap_start,
+        ap_done,
+        ap_idle,
+        ap_ready,
+        data_0_val,
+        data_1_val,
+        data_2_val,
+        data_3_val,
+        data_4_val,
+        data_5_val,
+        data_6_val,
+        data_7_val,
+        ap_return
+);
+
+parameter    ap_ST_fsm_pp0_stage0 = 1'd1;
+
+input   ap_clk;
+input   ap_rst;
+input   ap_start;
+output   ap_done;
+output   ap_idle;
+output   ap_ready;
+input  [15:0] data_0_val;
+input  [15:0] data_1_val;
+input  [15:0] data_2_val;
+input  [15:0] data_3_val;
+input  [15:0] data_4_val;
+input  [15:0] data_5_val;
+input  [15:0] data_6_val;
+input  [15:0] data_7_val;
+output  [29:0] ap_return;
+
+reg ap_idle;
+reg[29:0] ap_return;
+
+(* fsm_encoding = "none" *) reg   [0:0] ap_CS_fsm;
+wire    ap_CS_fsm_pp0_stage0;
+wire    ap_enable_reg_pp0_iter0;
+reg    ap_enable_reg_pp0_iter1;
+reg    ap_idle_pp0;
+wire    ap_block_pp0_stage0_subdone;
+wire   [0:0] icmp_ln46_fu_464_p2;
+reg    ap_condition_exit_pp0_iter0_stage0;
+wire    ap_loop_exit_ready;
+reg    ap_ready_int;
+reg   [0:0] do_init_reg_128;
+reg   [2:0] phi_ln46_reg_247;
+reg   [15:0] data_0_val4_phi_reg_260;
+reg   [15:0] data_1_val5_phi_reg_273;
+reg   [15:0] data_2_val6_phi_reg_286;
+reg   [15:0] data_3_val7_phi_reg_299;
+reg   [15:0] data_4_val8_phi_reg_312;
+reg   [15:0] data_5_val9_phi_reg_325;
+reg   [15:0] data_6_val10_phi_reg_338;
+reg   [15:0] data_7_val11_phi_reg_351;
+reg   [29:0] res_02_reg_364;
+wire   [15:0] a_fu_378_p19;
+reg  signed [15:0] a_reg_488;
+wire    ap_block_pp0_stage0_11001;
+wire   [11:0] w_fu_418_p19;
+reg  signed [11:0] w_reg_493;
+wire   [2:0] w_index_fu_458_p2;
+reg   [2:0] w_index_reg_498;
+reg   [0:0] icmp_ln46_reg_503;
+wire  signed [29:0] grp_fu_479_p3;
+reg   [0:0] ap_phi_mux_do_init_phi_fu_131_p6;
+wire    ap_loop_init;
+wire    ap_block_pp0_stage0;
+reg   [2:0] ap_phi_mux_phi_ln46_phi_fu_250_p6;
+reg   [15:0] ap_phi_mux_data_0_val4_phi_phi_fu_264_p4;
+wire   [15:0] ap_phi_reg_pp0_iter0_data_0_val4_phi_reg_260;
+reg   [15:0] ap_phi_mux_data_1_val5_phi_phi_fu_277_p4;
+wire   [15:0] ap_phi_reg_pp0_iter0_data_1_val5_phi_reg_273;
+reg   [15:0] ap_phi_mux_data_2_val6_phi_phi_fu_290_p4;
+wire   [15:0] ap_phi_reg_pp0_iter0_data_2_val6_phi_reg_286;
+reg   [15:0] ap_phi_mux_data_3_val7_phi_phi_fu_303_p4;
+wire   [15:0] ap_phi_reg_pp0_iter0_data_3_val7_phi_reg_299;
+reg   [15:0] ap_phi_mux_data_4_val8_phi_phi_fu_316_p4;
+wire   [15:0] ap_phi_reg_pp0_iter0_data_4_val8_phi_reg_312;
+reg   [15:0] ap_phi_mux_data_5_val9_phi_phi_fu_329_p4;
+wire   [15:0] ap_phi_reg_pp0_iter0_data_5_val9_phi_reg_325;
+reg   [15:0] ap_phi_mux_data_6_val10_phi_phi_fu_342_p4;
+wire   [15:0] ap_phi_reg_pp0_iter0_data_6_val10_phi_reg_338;
+reg   [15:0] ap_phi_mux_data_7_val11_phi_phi_fu_355_p4;
+wire   [15:0] ap_phi_reg_pp0_iter0_data_7_val11_phi_reg_351;
+reg  signed [29:0] ap_phi_mux_res_02_phi_fu_368_p6;
+reg    ap_loop_init_pp0_iter1_reg;
+wire   [15:0] a_fu_378_p17;
+wire   [11:0] w_fu_418_p17;
+reg   [29:0] ap_return_preg;
+reg    ap_done_reg;
+wire    ap_continue_int;
+reg    ap_done_int;
+reg    ap_loop_exit_ready_pp0_iter1_reg;
+reg   [0:0] ap_NS_fsm;
+reg    ap_idle_pp0_0to0;
+reg    ap_reset_idle_pp0;
+wire    ap_enable_pp0;
+wire    ap_start_int;
+wire    ap_ready_sig;
+wire    ap_done_sig;
+reg    ap_condition_101;
+reg    ap_condition_107;
+wire   [2:0] a_fu_378_p1;
+wire   [2:0] a_fu_378_p3;
+wire   [2:0] a_fu_378_p5;
+wire   [2:0] a_fu_378_p7;
+wire  signed [2:0] a_fu_378_p9;
+wire  signed [2:0] a_fu_378_p11;
+wire  signed [2:0] a_fu_378_p13;
+wire  signed [2:0] a_fu_378_p15;
+wire   [2:0] w_fu_418_p1;
+wire   [2:0] w_fu_418_p3;
+wire   [2:0] w_fu_418_p5;
+wire   [2:0] w_fu_418_p7;
+wire  signed [2:0] w_fu_418_p9;
+wire  signed [2:0] w_fu_418_p11;
+wire  signed [2:0] w_fu_418_p13;
+wire  signed [2:0] w_fu_418_p15;
+wire    ap_ce_reg;
+
+// power-on initialization
+initial begin
+#0 ap_CS_fsm = 1'd1;
+#0 ap_enable_reg_pp0_iter1 = 1'b0;
+#0 ap_return_preg = 30'd0;
+#0 ap_done_reg = 1'b0;
+end
+
+(* dissolve_hierarchy = "yes" *) myproject_sparsemux_17_3_16_1_1 #(
+    .ID( 1 ),
+    .NUM_STAGE( 1 ),
+    .CASE0( 3'h0 ),
+    .din0_WIDTH( 16 ),
+    .CASE1( 3'h1 ),
+    .din1_WIDTH( 16 ),
+    .CASE2( 3'h2 ),
+    .din2_WIDTH( 16 ),
+    .CASE3( 3'h3 ),
+    .din3_WIDTH( 16 ),
+    .CASE4( 3'h4 ),
+    .din4_WIDTH( 16 ),
+    .CASE5( 3'h5 ),
+    .din5_WIDTH( 16 ),
+    .CASE6( 3'h6 ),
+    .din6_WIDTH( 16 ),
+    .CASE7( 3'h7 ),
+    .din7_WIDTH( 16 ),
+    .def_WIDTH( 16 ),
+    .sel_WIDTH( 3 ),
+    .dout_WIDTH( 16 ))
+sparsemux_17_3_16_1_1_U8778(
+    .din0(ap_phi_mux_data_0_val4_phi_phi_fu_264_p4),
+    .din1(ap_phi_mux_data_1_val5_phi_phi_fu_277_p4),
+    .din2(ap_phi_mux_data_2_val6_phi_phi_fu_290_p4),
+    .din3(ap_phi_mux_data_3_val7_phi_phi_fu_303_p4),
+    .din4(ap_phi_mux_data_4_val8_phi_phi_fu_316_p4),
+    .din5(ap_phi_mux_data_5_val9_phi_phi_fu_329_p4),
+    .din6(ap_phi_mux_data_6_val10_phi_phi_fu_342_p4),
+    .din7(ap_phi_mux_data_7_val11_phi_phi_fu_355_p4),
+    .def(a_fu_378_p17),
+    .sel(ap_phi_mux_phi_ln46_phi_fu_250_p6),
+    .dout(a_fu_378_p19)
+);
+
+(* dissolve_hierarchy = "yes" *) myproject_sparsemux_17_3_12_1_1 #(
+    .ID( 1 ),
+    .NUM_STAGE( 1 ),
+    .CASE0( 3'h0 ),
+    .din0_WIDTH( 12 ),
+    .CASE1( 3'h1 ),
+    .din1_WIDTH( 12 ),
+    .CASE2( 3'h2 ),
+    .din2_WIDTH( 12 ),
+    .CASE3( 3'h3 ),
+    .din3_WIDTH( 12 ),
+    .CASE4( 3'h4 ),
+    .din4_WIDTH( 12 ),
+    .CASE5( 3'h5 ),
+    .din5_WIDTH( 12 ),
+    .CASE6( 3'h6 ),
+    .din6_WIDTH( 12 ),
+    .CASE7( 3'h7 ),
+    .din7_WIDTH( 12 ),
+    .def_WIDTH( 12 ),
+    .sel_WIDTH( 3 ),
+    .dout_WIDTH( 12 ))
+sparsemux_17_3_12_1_1_U8779(
+    .din0(12'd3452),
+    .din1(12'd978),
+    .din2(12'd3298),
+    .din3(12'd3581),
+    .din4(12'd3649),
+    .din5(12'd624),
+    .din6(12'd3542),
+    .din7(12'd2852),
+    .def(w_fu_418_p17),
+    .sel(ap_phi_mux_phi_ln46_phi_fu_250_p6),
+    .dout(w_fu_418_p19)
+);
+
+myproject_mac_muladd_16s_12s_30s_30_1_1 #(
+    .ID( 1 ),
+    .NUM_STAGE( 1 ),
+    .din0_WIDTH( 16 ),
+    .din1_WIDTH( 12 ),
+    .din2_WIDTH( 30 ),
+    .dout_WIDTH( 30 ))
+mac_muladd_16s_12s_30s_30_1_1_U8780(
+    .din0(a_reg_488),
+    .din1(w_reg_493),
+    .din2(ap_phi_mux_res_02_phi_fu_368_p6),
+    .dout(grp_fu_479_p3)
+);
+
+myproject_flow_control_loop_pipe_no_ap_cont flow_control_loop_pipe_no_ap_cont_U(
+    .ap_clk(ap_clk),
+    .ap_rst(ap_rst),
+    .ap_start(ap_start),
+    .ap_ready(ap_ready_sig),
+    .ap_done(ap_done_sig),
+    .ap_start_int(ap_start_int),
+    .ap_loop_init(ap_loop_init),
+    .ap_ready_int(ap_ready_int),
+    .ap_loop_exit_ready(ap_condition_exit_pp0_iter0_stage0),
+    .ap_loop_exit_done(ap_done_int),
+    .ap_continue_int(ap_continue_int),
+    .ap_done_int(ap_done_int)
+);
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_CS_fsm <= ap_ST_fsm_pp0_stage0;
+    end else begin
+        ap_CS_fsm <= ap_NS_fsm;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_done_reg <= 1'b0;
+    end else begin
+        if ((ap_continue_int == 1'b1)) begin
+            ap_done_reg <= 1'b0;
+        end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_loop_exit_ready_pp0_iter1_reg == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+            ap_done_reg <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_enable_reg_pp0_iter1 <= 1'b0;
+    end else begin
+        if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+            ap_enable_reg_pp0_iter1 <= ap_start_int;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_return_preg <= 30'd0;
+    end else begin
+        if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln46_reg_503 == 1'd1))) begin
+            ap_return_preg <= grp_fu_479_p3;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_pp0_stage0)) begin
+        if (((ap_loop_exit_ready == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin
+            ap_loop_exit_ready_pp0_iter1_reg <= 1'b0;
+        end else if ((1'b0 == ap_block_pp0_stage0_11001)) begin
+            ap_loop_exit_ready_pp0_iter1_reg <= ap_loop_exit_ready;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_condition_101)) begin
+        if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd0)) begin
+            data_0_val4_phi_reg_260 <= data_0_val4_phi_reg_260;
+        end else if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd1)) begin
+            data_0_val4_phi_reg_260 <= data_0_val;
+        end else if (~(icmp_ln46_fu_464_p2 == 1'd1)) begin
+            data_0_val4_phi_reg_260 <= ap_phi_reg_pp0_iter0_data_0_val4_phi_reg_260;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_condition_101)) begin
+        if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd0)) begin
+            data_1_val5_phi_reg_273 <= data_1_val5_phi_reg_273;
+        end else if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd1)) begin
+            data_1_val5_phi_reg_273 <= data_1_val;
+        end else if (~(icmp_ln46_fu_464_p2 == 1'd1)) begin
+            data_1_val5_phi_reg_273 <= ap_phi_reg_pp0_iter0_data_1_val5_phi_reg_273;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_condition_101)) begin
+        if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd0)) begin
+            data_2_val6_phi_reg_286 <= data_2_val6_phi_reg_286;
+        end else if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd1)) begin
+            data_2_val6_phi_reg_286 <= data_2_val;
+        end else if (~(icmp_ln46_fu_464_p2 == 1'd1)) begin
+            data_2_val6_phi_reg_286 <= ap_phi_reg_pp0_iter0_data_2_val6_phi_reg_286;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_condition_101)) begin
+        if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd0)) begin
+            data_3_val7_phi_reg_299 <= data_3_val7_phi_reg_299;
+        end else if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd1)) begin
+            data_3_val7_phi_reg_299 <= data_3_val;
+        end else if (~(icmp_ln46_fu_464_p2 == 1'd1)) begin
+            data_3_val7_phi_reg_299 <= ap_phi_reg_pp0_iter0_data_3_val7_phi_reg_299;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_condition_101)) begin
+        if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd0)) begin
+            data_4_val8_phi_reg_312 <= data_4_val8_phi_reg_312;
+        end else if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd1)) begin
+            data_4_val8_phi_reg_312 <= data_4_val;
+        end else if (~(icmp_ln46_fu_464_p2 == 1'd1)) begin
+            data_4_val8_phi_reg_312 <= ap_phi_reg_pp0_iter0_data_4_val8_phi_reg_312;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_condition_101)) begin
+        if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd0)) begin
+            data_5_val9_phi_reg_325 <= data_5_val9_phi_reg_325;
+        end else if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd1)) begin
+            data_5_val9_phi_reg_325 <= data_5_val;
+        end else if (~(icmp_ln46_fu_464_p2 == 1'd1)) begin
+            data_5_val9_phi_reg_325 <= ap_phi_reg_pp0_iter0_data_5_val9_phi_reg_325;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_condition_101)) begin
+        if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd0)) begin
+            data_6_val10_phi_reg_338 <= data_6_val10_phi_reg_338;
+        end else if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd1)) begin
+            data_6_val10_phi_reg_338 <= data_6_val;
+        end else if (~(icmp_ln46_fu_464_p2 == 1'd1)) begin
+            data_6_val10_phi_reg_338 <= ap_phi_reg_pp0_iter0_data_6_val10_phi_reg_338;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_condition_101)) begin
+        if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd0)) begin
+            data_7_val11_phi_reg_351 <= data_7_val11_phi_reg_351;
+        end else if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd1)) begin
+            data_7_val11_phi_reg_351 <= data_7_val;
+        end else if (~(icmp_ln46_fu_464_p2 == 1'd1)) begin
+            data_7_val11_phi_reg_351 <= ap_phi_reg_pp0_iter0_data_7_val11_phi_reg_351;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln46_reg_503 == 1'd0))) begin
+        do_init_reg_128 <= 1'd0;
+    end else if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln46_reg_503 == 1'd1)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_loop_init == 1'b1)))) begin
+        do_init_reg_128 <= 1'd1;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln46_reg_503 == 1'd0))) begin
+        phi_ln46_reg_247 <= w_index_reg_498;
+    end else if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln46_reg_503 == 1'd1)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_loop_init == 1'b1)))) begin
+        phi_ln46_reg_247 <= 3'd0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_condition_107)) begin
+        if ((icmp_ln46_reg_503 == 1'd1)) begin
+            res_02_reg_364 <= 30'd1073627136;
+        end else if ((icmp_ln46_reg_503 == 1'd0)) begin
+            res_02_reg_364 <= grp_fu_479_p3;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        a_reg_488 <= a_fu_378_p19;
+        ap_loop_init_pp0_iter1_reg <= ap_loop_init;
+        icmp_ln46_reg_503 <= icmp_ln46_fu_464_p2;
+        w_reg_493 <= w_fu_418_p19;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        w_index_reg_498 <= w_index_fu_458_p2;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln46_fu_464_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        ap_condition_exit_pp0_iter0_stage0 = 1'b1;
+    end else begin
+        ap_condition_exit_pp0_iter0_stage0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_loop_exit_ready_pp0_iter1_reg == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        ap_done_int = 1'b1;
+    end else begin
+        ap_done_int = ap_done_reg;
+    end
+end
+
+always @ (*) begin
+    if (((ap_start_int == 1'b0) & (ap_idle_pp0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        ap_idle = 1'b1;
+    end else begin
+        ap_idle = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin
+        ap_idle_pp0 = 1'b1;
+    end else begin
+        ap_idle_pp0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((ap_enable_reg_pp0_iter0 == 1'b0)) begin
+        ap_idle_pp0_0to0 = 1'b1;
+    end else begin
+        ap_idle_pp0_0to0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd0)) begin
+        ap_phi_mux_data_0_val4_phi_phi_fu_264_p4 = data_0_val4_phi_reg_260;
+    end else if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd1)) begin
+        ap_phi_mux_data_0_val4_phi_phi_fu_264_p4 = data_0_val;
+    end else begin
+        ap_phi_mux_data_0_val4_phi_phi_fu_264_p4 = ap_phi_reg_pp0_iter0_data_0_val4_phi_reg_260;
+    end
+end
+
+always @ (*) begin
+    if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd0)) begin
+        ap_phi_mux_data_1_val5_phi_phi_fu_277_p4 = data_1_val5_phi_reg_273;
+    end else if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd1)) begin
+        ap_phi_mux_data_1_val5_phi_phi_fu_277_p4 = data_1_val;
+    end else begin
+        ap_phi_mux_data_1_val5_phi_phi_fu_277_p4 = ap_phi_reg_pp0_iter0_data_1_val5_phi_reg_273;
+    end
+end
+
+always @ (*) begin
+    if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd0)) begin
+        ap_phi_mux_data_2_val6_phi_phi_fu_290_p4 = data_2_val6_phi_reg_286;
+    end else if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd1)) begin
+        ap_phi_mux_data_2_val6_phi_phi_fu_290_p4 = data_2_val;
+    end else begin
+        ap_phi_mux_data_2_val6_phi_phi_fu_290_p4 = ap_phi_reg_pp0_iter0_data_2_val6_phi_reg_286;
+    end
+end
+
+always @ (*) begin
+    if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd0)) begin
+        ap_phi_mux_data_3_val7_phi_phi_fu_303_p4 = data_3_val7_phi_reg_299;
+    end else if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd1)) begin
+        ap_phi_mux_data_3_val7_phi_phi_fu_303_p4 = data_3_val;
+    end else begin
+        ap_phi_mux_data_3_val7_phi_phi_fu_303_p4 = ap_phi_reg_pp0_iter0_data_3_val7_phi_reg_299;
+    end
+end
+
+always @ (*) begin
+    if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd0)) begin
+        ap_phi_mux_data_4_val8_phi_phi_fu_316_p4 = data_4_val8_phi_reg_312;
+    end else if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd1)) begin
+        ap_phi_mux_data_4_val8_phi_phi_fu_316_p4 = data_4_val;
+    end else begin
+        ap_phi_mux_data_4_val8_phi_phi_fu_316_p4 = ap_phi_reg_pp0_iter0_data_4_val8_phi_reg_312;
+    end
+end
+
+always @ (*) begin
+    if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd0)) begin
+        ap_phi_mux_data_5_val9_phi_phi_fu_329_p4 = data_5_val9_phi_reg_325;
+    end else if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd1)) begin
+        ap_phi_mux_data_5_val9_phi_phi_fu_329_p4 = data_5_val;
+    end else begin
+        ap_phi_mux_data_5_val9_phi_phi_fu_329_p4 = ap_phi_reg_pp0_iter0_data_5_val9_phi_reg_325;
+    end
+end
+
+always @ (*) begin
+    if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd0)) begin
+        ap_phi_mux_data_6_val10_phi_phi_fu_342_p4 = data_6_val10_phi_reg_338;
+    end else if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd1)) begin
+        ap_phi_mux_data_6_val10_phi_phi_fu_342_p4 = data_6_val;
+    end else begin
+        ap_phi_mux_data_6_val10_phi_phi_fu_342_p4 = ap_phi_reg_pp0_iter0_data_6_val10_phi_reg_338;
+    end
+end
+
+always @ (*) begin
+    if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd0)) begin
+        ap_phi_mux_data_7_val11_phi_phi_fu_355_p4 = data_7_val11_phi_reg_351;
+    end else if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd1)) begin
+        ap_phi_mux_data_7_val11_phi_phi_fu_355_p4 = data_7_val;
+    end else begin
+        ap_phi_mux_data_7_val11_phi_phi_fu_355_p4 = ap_phi_reg_pp0_iter0_data_7_val11_phi_reg_351;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln46_reg_503 == 1'd0))) begin
+        ap_phi_mux_do_init_phi_fu_131_p6 = 1'd0;
+    end else if ((((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_loop_init == 1'b1)) | ((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln46_reg_503 == 1'd1)))) begin
+        ap_phi_mux_do_init_phi_fu_131_p6 = 1'd1;
+    end else begin
+        ap_phi_mux_do_init_phi_fu_131_p6 = do_init_reg_128;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln46_reg_503 == 1'd0))) begin
+        ap_phi_mux_phi_ln46_phi_fu_250_p6 = w_index_reg_498;
+    end else if ((((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_loop_init == 1'b1)) | ((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln46_reg_503 == 1'd1)))) begin
+        ap_phi_mux_phi_ln46_phi_fu_250_p6 = 3'd0;
+    end else begin
+        ap_phi_mux_phi_ln46_phi_fu_250_p6 = phi_ln46_reg_247;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_loop_init_pp0_iter1_reg == 1'b1))) begin
+        ap_phi_mux_res_02_phi_fu_368_p6 = 30'd1073627136;
+    end else begin
+        ap_phi_mux_res_02_phi_fu_368_p6 = res_02_reg_364;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        ap_ready_int = 1'b1;
+    end else begin
+        ap_ready_int = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_start_int == 1'b0) & (ap_idle_pp0_0to0 == 1'b1))) begin
+        ap_reset_idle_pp0 = 1'b1;
+    end else begin
+        ap_reset_idle_pp0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln46_reg_503 == 1'd1))) begin
+        ap_return = grp_fu_479_p3;
+    end else begin
+        ap_return = ap_return_preg;
+    end
+end
+
+always @ (*) begin
+    case (ap_CS_fsm)
+        ap_ST_fsm_pp0_stage0 : begin
+            ap_NS_fsm = ap_ST_fsm_pp0_stage0;
+        end
+        default : begin
+            ap_NS_fsm = 'bx;
+        end
+    endcase
+end
+
+assign a_fu_378_p17 = 'bx;
+
+assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd0];
+
+assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1);
+
+assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1);
+
+assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_condition_101 = ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0));
+end
+
+always @ (*) begin
+    ap_condition_107 = ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0));
+end
+
+assign ap_done = ap_done_sig;
+
+assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1);
+
+assign ap_enable_reg_pp0_iter0 = ap_start_int;
+
+assign ap_loop_exit_ready = ap_condition_exit_pp0_iter0_stage0;
+
+assign ap_phi_reg_pp0_iter0_data_0_val4_phi_reg_260 = 'bx;
+
+assign ap_phi_reg_pp0_iter0_data_1_val5_phi_reg_273 = 'bx;
+
+assign ap_phi_reg_pp0_iter0_data_2_val6_phi_reg_286 = 'bx;
+
+assign ap_phi_reg_pp0_iter0_data_3_val7_phi_reg_299 = 'bx;
+
+assign ap_phi_reg_pp0_iter0_data_4_val8_phi_reg_312 = 'bx;
+
+assign ap_phi_reg_pp0_iter0_data_5_val9_phi_reg_325 = 'bx;
+
+assign ap_phi_reg_pp0_iter0_data_6_val10_phi_reg_338 = 'bx;
+
+assign ap_phi_reg_pp0_iter0_data_7_val11_phi_reg_351 = 'bx;
+
+assign ap_ready = ap_ready_sig;
+
+assign icmp_ln46_fu_464_p2 = ((ap_phi_mux_phi_ln46_phi_fu_250_p6 == 3'd7) ? 1'b1 : 1'b0);
+
+assign w_fu_418_p17 = 'bx;
+
+assign w_index_fu_458_p2 = (ap_phi_mux_phi_ln46_phi_fu_250_p6 + 3'd1);
+
+endmodule //myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s

myproject_prj/solution1/syn/verilog/myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s_w7_ROMUhA.v

@@ -0,0 +1,42 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1 ns / 1 ps
+module myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s_w7_ROMUhA (
+    address0, ce0, q0, 
+    reset, clk);
+
+parameter DataWidth = 250;
+parameter AddressWidth = 7;
+parameter AddressRange = 72;
+ 
+input[AddressWidth-1:0] address0;
+input ce0;
+output reg[DataWidth-1:0] q0;
+
+input reset;
+input clk;
+
+ 
+(* rom_style = "block" *)reg [DataWidth-1:0] rom0[0:AddressRange-1];
+
+
+initial begin
+     
+    $readmemh("./myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s_w7_ROMUhA.dat", rom0);
+end
+
+  
+always @(posedge clk) 
+begin 
+    if (ce0) 
+    begin
+        q0 <= rom0[address0];
+    end
+end
+
+
+endmodule
+

myproject_prj/solution1/syn/verilog/myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s_w12_Rceu.v

@@ -0,0 +1,42 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1 ns / 1 ps
+module myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s_w12_Rceu (
+    address0, ce0, q0, 
+    reset, clk);
+
+parameter DataWidth = 1018;
+parameter AddressWidth = 7;
+parameter AddressRange = 72;
+ 
+input[AddressWidth-1:0] address0;
+input ce0;
+output reg[DataWidth-1:0] q0;
+
+input reset;
+input clk;
+
+ 
+(* rom_style = "block" *)reg [DataWidth-1:0] rom0[0:AddressRange-1];
+
+
+initial begin
+     
+    $readmemh("./myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s_w12_Rceu.dat", rom0);
+end
+
+  
+always @(posedge clk) 
+begin 
+    if (ce0) 
+    begin
+        q0 <= rom0[address0];
+    end
+end
+
+
+endmodule
+

myproject_prj/solution1/syn/verilog/myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s_w12_Rcgu.v

@@ -0,0 +1,42 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1 ns / 1 ps
+module myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s_w12_Rcgu (
+    address0, ce0, q0, 
+    reset, clk);
+
+parameter DataWidth = 506;
+parameter AddressWidth = 8;
+parameter AddressRange = 144;
+ 
+input[AddressWidth-1:0] address0;
+input ce0;
+output reg[DataWidth-1:0] q0;
+
+input reset;
+input clk;
+
+ 
+(* rom_style = "block" *)reg [DataWidth-1:0] rom0[0:AddressRange-1];
+
+
+initial begin
+     
+    $readmemh("./myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s_w12_Rcgu.dat", rom0);
+end
+
+  
+always @(posedge clk) 
+begin 
+    if (ce0) 
+    begin
+        q0 <= rom0[address0];
+    end
+end
+
+
+endmodule
+

myproject_prj/solution1/syn/verilog/myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config31_mult_s_w31_Rnbc.v

@@ -0,0 +1,42 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1 ns / 1 ps
+module myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config31_mult_s_w31_Rnbc (
+    address0, ce0, q0, 
+    reset, clk);
+
+parameter DataWidth = 505;
+parameter AddressWidth = 7;
+parameter AddressRange = 72;
+ 
+input[AddressWidth-1:0] address0;
+input ce0;
+output reg[DataWidth-1:0] q0;
+
+input reset;
+input clk;
+
+ 
+(* rom_style = "block" *)reg [DataWidth-1:0] rom0[0:AddressRange-1];
+
+
+initial begin
+     
+    $readmemh("./myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config31_mult_s_w31_Rnbc.dat", rom0);
+end
+
+  
+always @(posedge clk) 
+begin 
+    if (ce0) 
+    begin
+        q0 <= rom0[address0];
+    end
+end
+
+
+endmodule
+

myproject_prj/solution1/syn/verilog/myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config31_mult_s_w31_Rndc.dat

@@ -0,0 +1,144 @@
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+01C003D000EFF95FFC6FFFBFFC9FF23000E0005FFAA0009FFD2FFED0014FF6C
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+1FFFFEA0027FFFF0008FF920050FF83FFC9FFBFFFFFFFE7FFCF0052003F0054
+1D500130004FFC7FF69FFE60018006F00190040FF96FFE500350017000900BD
+1EA004800240014FFB70003FF5DFFD5FFB3FFE00006003E001AFFFF0047007D
+1FE00090025FF51FFDCFFF7FED601040048FFDDFECBFF9F00A7004AFFCDFFA5
+1AAFFED0049FFC4FF8CFFF6FFAB017201E0FFEFFFD6FFCC0006001FFFFEFFBD
+0EDFFC5FFC7FFDFFFA1FFEBFF98FF9D0039003400410010FFC2FFE1FFD10004
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+1C300080014FFC6FFBEFFF2FF3900FE0168FFEFFFC6FFE10041000A0005000F
+1DCFF7BFFC20014000E00230061FF7BFFAC002A0035FFE2FFBBFFDEFFF40098
+03FFFEC0012FFC5006A0019007BFFFFFFD8005B007A0009001B00320046FF35
+0140041FFFEFFA5FFA20011FFDBFEE9FFA2FFF7FFC00005FFD7FFEC0000FF6A
+1EB00000006001CFF8A000D0038FFF4008FFFEA0028001300140011FFCD0048
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+03EFFE70026FFEFFFE9FFC4001DFFD80015FF9C0024FFEEFFFE005A0013FFE6
+1EDFFF5FFDCFFC2FF3FFFE9FFF600AEFFE50034FFB3FFA8009E0034FFF7005A
+1F0006A002C0041FFAFFF91FF67FF8A007FFFE4FFF4003F002300070029FF4D
+1FF0022FFDAFF60FF88002FFFA200B6FF60FFE1FF88FFD7008C0020FFAC002F
+00EFFAE0031FF98FFDFFFD200530091FFC800260008FFD900130049FFF80023
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myproject_prj/solution1/syn/verilog/myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s_w9_ROMbrm.v

@@ -0,0 +1,42 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1 ns / 1 ps
+module myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s_w9_ROMbrm (
+    address0, ce0, q0, 
+    reset, clk);
+
+parameter DataWidth = 506;
+parameter AddressWidth = 7;
+parameter AddressRange = 72;
+ 
+input[AddressWidth-1:0] address0;
+input ce0;
+output reg[DataWidth-1:0] q0;
+
+input reset;
+input clk;
+
+ 
+(* rom_style = "block" *)reg [DataWidth-1:0] rom0[0:AddressRange-1];
+
+
+initial begin
+     
+    $readmemh("./myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s_w9_ROMbrm.dat", rom0);
+end
+
+  
+always @(posedge clk) 
+begin 
+    if (ce0) 
+    begin
+        q0 <= rom0[address0];
+    end
+end
+
+
+endmodule
+

myproject_prj/solution1/syn/verilog/myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s_w9_ROMbtn.dat

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myproject_prj/solution1/syn/verilog/myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s_w9_ROMbtn.v

@@ -0,0 +1,42 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1 ns / 1 ps
+module myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s_w9_ROMbtn (
+    address0, ce0, q0, 
+    reset, clk);
+
+parameter DataWidth = 251;
+parameter AddressWidth = 8;
+parameter AddressRange = 144;
+ 
+input[AddressWidth-1:0] address0;
+input ce0;
+output reg[DataWidth-1:0] q0;
+
+input reset;
+input clk;
+
+ 
+(* rom_style = "block" *)reg [DataWidth-1:0] rom0[0:AddressRange-1];
+
+
+initial begin
+     
+    $readmemh("./myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s_w9_ROMbtn.dat", rom0);
+end
+
+  
+always @(posedge clk) 
+begin 
+    if (ce0) 
+    begin
+        q0 <= rom0[address0];
+    end
+end
+
+
+endmodule
+

myproject_prj/solution1/syn/verilog/myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s_w14_RdjF.v

@@ -0,0 +1,42 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1 ns / 1 ps
+module myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s_w14_RdjF (
+    address0, ce0, q0, 
+    reset, clk);
+
+parameter DataWidth = 1018;
+parameter AddressWidth = 8;
+parameter AddressRange = 144;
+ 
+input[AddressWidth-1:0] address0;
+input ce0;
+output reg[DataWidth-1:0] q0;
+
+input reset;
+input clk;
+
+ 
+(* rom_style = "block" *)reg [DataWidth-1:0] rom0[0:AddressRange-1];
+
+
+initial begin
+     
+    $readmemh("./myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s_w14_RdjF.dat", rom0);
+end
+
+  
+always @(posedge clk) 
+begin 
+    if (ce0) 
+    begin
+        q0 <= rom0[address0];
+    end
+end
+
+
+endmodule
+

myproject_prj/solution1/syn/verilog/myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config17_mult_s_w17_ReSV.dat

@@ -0,0 +1,144 @@
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myproject_prj/solution1/syn/verilog/myproject_fifo_w1024_d64_A.v

@@ -0,0 +1,237 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+//RAW latency 2 
+
+module myproject_fifo_w1024_d64_A
+#(parameter
+    MEM_STYLE    = "auto",
+    DATA_WIDTH   = 1024,
+    ADDR_WIDTH   = 6,
+    DEPTH        = 64)
+(
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+    
+    // read 
+    output wire [ADDR_WIDTH:0]   if_num_data_valid, // for FRP
+    output wire [ADDR_WIDTH:0]   if_fifo_cap,       // for FRP
+
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+localparam 
+    MEM_DEPTH    = DEPTH - 1,
+    MEM_AWIDTH   = clog2(MEM_DEPTH);
+//------------------------Local signal-------------------
+    reg  [MEM_AWIDTH-1:0] waddr;
+    reg  [MEM_AWIDTH-1:0] raddr;
+    wire [MEM_AWIDTH-1:0] wnext;
+    wire [MEM_AWIDTH-1:0] rnext;
+    wire                  push;
+    wire                  pop;
+    reg  [MEM_AWIDTH:0]   mOutPtr;
+    reg                   empty_n = 1'b0;
+    reg                   full_n = 1'b1;
+    // has num_data_valid? 
+    wire                  num_extra_words;//yes
+    reg  [ADDR_WIDTH:0]   num_data_valid; //yes 
+
+    wire                  pop_dout;
+    reg  [ADDR_WIDTH:0]   num_data_cnt;
+    reg                   dout_vld = 1'b0;
+
+//------------------------Instantiation------------------
+    myproject_fifo_w1024_d64_A_ram 
+    #(  .MEM_STYLE  (MEM_STYLE),
+        .DATA_WIDTH (DATA_WIDTH),
+        .ADDR_WIDTH (MEM_AWIDTH),
+        .DEPTH      (MEM_DEPTH)
+    ) U_myproject_fifo_w1024_d64_A_ram (
+        .clk        (clk),
+        .reset      (reset),
+        .we         (push),
+        .waddr      (waddr),
+        .din        (if_din),
+        .raddr      (raddr),
+        .rden       (pop),
+        .dout       (if_dout)
+    );
+
+//------------------------Task and function--------------
+    function integer clog2;
+        input integer x;
+        integer n, m;
+    begin
+        n = 1;
+        m = 2;
+        while (m < x) begin
+            n = n + 1;
+            m = m * 2;
+        end
+        clog2 = n;
+    end
+    endfunction
+//------------------------Body---------------------------
+    // num_data_valid 
+    assign if_num_data_valid = num_data_valid;
+    assign if_fifo_cap = DEPTH;
+
+    // almost full/empty 
+
+    // program full/empty 
+
+    assign if_full_n  = full_n;
+    assign if_empty_n = dout_vld;
+
+    assign push       = full_n & if_write_ce & if_write;
+    assign pop        = empty_n & (pop_dout | ~dout_vld);
+    assign pop_dout   = dout_vld & if_read_ce & if_read;
+    
+    assign wnext      = !push                    ? waddr :
+                        (waddr == MEM_DEPTH - 1) ? 1'b0  :
+                        waddr + 1'b1;
+    assign rnext      = !pop                     ? raddr :
+                        (raddr == MEM_DEPTH - 1) ? 1'b0  :
+                        raddr + 1'b1;
+
+    // waddr
+    always @(posedge clk) begin
+        if (reset)
+            waddr <= {MEM_AWIDTH{1'b0}};
+        else
+            waddr <= wnext;
+    end
+
+    // raddr
+    always @(posedge clk) begin
+        if (reset)
+            raddr <= {MEM_AWIDTH{1'b0}};
+        else
+            raddr <= rnext;
+    end
+
+    // mOutPtr
+    always @(posedge clk) begin
+        if (reset)
+            mOutPtr <= {MEM_AWIDTH+1{1'b0}};
+        else if (push & ~pop)
+            mOutPtr <= mOutPtr + 1'b1;
+        else if (~push & pop)
+            mOutPtr <= mOutPtr - 1'b1;
+    end
+
+    // full_n 
+    always @(posedge clk) begin
+        if (reset)
+            full_n <= 1'b1;
+        else if ((push & ~pop_dout) && (num_data_cnt == DEPTH - 1))
+            full_n <= 1'b0;
+        else if (~push & pop_dout)
+            full_n <= 1'b1;
+    end
+
+    // empty_n
+    always @(posedge clk) begin
+        if (reset)
+            empty_n <= 1'b0;
+        else if (push & ~pop)
+            empty_n <= 1'b1;
+        else if ((~push & pop) && (mOutPtr == 1))
+            empty_n <= 1'b0;
+    end
+
+    // almost_full_n 
+
+    // almost_empty_n 
+
+    // prog_full_n 
+
+    // prog_empty_n 
+
+    // num_data_cnt
+    always @(posedge clk) begin
+        if (reset)
+            num_data_cnt <= {ADDR_WIDTH+1{1'b0}};
+        else if ( push & ~pop_dout)
+            num_data_cnt <= num_data_cnt + 1'b1;
+        else if (~push & pop_dout)
+            num_data_cnt <= num_data_cnt - 1'b1;
+    end
+
+    // num_data_valid 
+    assign num_extra_words = (dout_vld & ~pop_dout) ? 1 : 0;
+                             
+    always @(posedge clk) begin
+        if (reset)
+            num_data_valid <= {ADDR_WIDTH+1{1'b0}};
+        else if (empty_n | (dout_vld & ~pop_dout))
+            num_data_valid <= push + mOutPtr + num_extra_words;
+        else
+            num_data_valid <= num_extra_words;
+    end // 
+
+    // dout_vld
+    always @(posedge clk) begin
+        if (reset)
+            dout_vld <= 1'b0;
+        else if (pop)
+            dout_vld <= 1'b1;
+        else if (pop_dout)
+            dout_vld <= 1'b0;
+    end
+
+endmodule
+
+
+module myproject_fifo_w1024_d64_A_ram
+#(parameter
+    MEM_STYLE   = "auto",
+    DATA_WIDTH  = 1024,
+    ADDR_WIDTH  = 6,
+    DEPTH       = 64)
+(
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  we,
+    input  wire [ADDR_WIDTH-1:0] waddr,
+    input  wire [DATA_WIDTH-1:0] din,
+    input  wire [ADDR_WIDTH-1:0] raddr,
+    input  wire                  rden,
+    output wire [DATA_WIDTH-1:0] dout
+);
+
+    (* ram_style = MEM_STYLE *)
+    reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+    reg  [DATA_WIDTH-1:0] mem_reg;
+
+    always @(posedge clk) begin
+        if (we)
+            mem[waddr] <= din;
+    end
+
+    always @(posedge clk) begin
+        if (reset)
+            mem_reg <= 0;
+        else if (rden)
+            mem_reg <= mem[raddr];
+    end
+    
+    assign dout = mem_reg;
+
+endmodule

myproject_prj/solution1/syn/verilog/myproject_fifo_w1312_d256_A.v

@@ -0,0 +1,237 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+//RAW latency 2 
+
+module myproject_fifo_w1312_d256_A
+#(parameter
+    MEM_STYLE    = "auto",
+    DATA_WIDTH   = 1312,
+    ADDR_WIDTH   = 8,
+    DEPTH        = 256)
+(
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+    
+    // read 
+    output wire [ADDR_WIDTH:0]   if_num_data_valid, // for FRP
+    output wire [ADDR_WIDTH:0]   if_fifo_cap,       // for FRP
+
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+localparam 
+    MEM_DEPTH    = DEPTH - 1,
+    MEM_AWIDTH   = clog2(MEM_DEPTH);
+//------------------------Local signal-------------------
+    reg  [MEM_AWIDTH-1:0] waddr;
+    reg  [MEM_AWIDTH-1:0] raddr;
+    wire [MEM_AWIDTH-1:0] wnext;
+    wire [MEM_AWIDTH-1:0] rnext;
+    wire                  push;
+    wire                  pop;
+    reg  [MEM_AWIDTH:0]   mOutPtr;
+    reg                   empty_n = 1'b0;
+    reg                   full_n = 1'b1;
+    // has num_data_valid? 
+    wire                  num_extra_words;//yes
+    reg  [ADDR_WIDTH:0]   num_data_valid; //yes 
+
+    wire                  pop_dout;
+    reg  [ADDR_WIDTH:0]   num_data_cnt;
+    reg                   dout_vld = 1'b0;
+
+//------------------------Instantiation------------------
+    myproject_fifo_w1312_d256_A_ram 
+    #(  .MEM_STYLE  (MEM_STYLE),
+        .DATA_WIDTH (DATA_WIDTH),
+        .ADDR_WIDTH (MEM_AWIDTH),
+        .DEPTH      (MEM_DEPTH)
+    ) U_myproject_fifo_w1312_d256_A_ram (
+        .clk        (clk),
+        .reset      (reset),
+        .we         (push),
+        .waddr      (waddr),
+        .din        (if_din),
+        .raddr      (raddr),
+        .rden       (pop),
+        .dout       (if_dout)
+    );
+
+//------------------------Task and function--------------
+    function integer clog2;
+        input integer x;
+        integer n, m;
+    begin
+        n = 1;
+        m = 2;
+        while (m < x) begin
+            n = n + 1;
+            m = m * 2;
+        end
+        clog2 = n;
+    end
+    endfunction
+//------------------------Body---------------------------
+    // num_data_valid 
+    assign if_num_data_valid = num_data_valid;
+    assign if_fifo_cap = DEPTH;
+
+    // almost full/empty 
+
+    // program full/empty 
+
+    assign if_full_n  = full_n;
+    assign if_empty_n = dout_vld;
+
+    assign push       = full_n & if_write_ce & if_write;
+    assign pop        = empty_n & (pop_dout | ~dout_vld);
+    assign pop_dout   = dout_vld & if_read_ce & if_read;
+    
+    assign wnext      = !push                    ? waddr :
+                        (waddr == MEM_DEPTH - 1) ? 1'b0  :
+                        waddr + 1'b1;
+    assign rnext      = !pop                     ? raddr :
+                        (raddr == MEM_DEPTH - 1) ? 1'b0  :
+                        raddr + 1'b1;
+
+    // waddr
+    always @(posedge clk) begin
+        if (reset)
+            waddr <= {MEM_AWIDTH{1'b0}};
+        else
+            waddr <= wnext;
+    end
+
+    // raddr
+    always @(posedge clk) begin
+        if (reset)
+            raddr <= {MEM_AWIDTH{1'b0}};
+        else
+            raddr <= rnext;
+    end
+
+    // mOutPtr
+    always @(posedge clk) begin
+        if (reset)
+            mOutPtr <= {MEM_AWIDTH+1{1'b0}};
+        else if (push & ~pop)
+            mOutPtr <= mOutPtr + 1'b1;
+        else if (~push & pop)
+            mOutPtr <= mOutPtr - 1'b1;
+    end
+
+    // full_n 
+    always @(posedge clk) begin
+        if (reset)
+            full_n <= 1'b1;
+        else if ((push & ~pop_dout) && (num_data_cnt == DEPTH - 1))
+            full_n <= 1'b0;
+        else if (~push & pop_dout)
+            full_n <= 1'b1;
+    end
+
+    // empty_n
+    always @(posedge clk) begin
+        if (reset)
+            empty_n <= 1'b0;
+        else if (push & ~pop)
+            empty_n <= 1'b1;
+        else if ((~push & pop) && (mOutPtr == 1))
+            empty_n <= 1'b0;
+    end
+
+    // almost_full_n 
+
+    // almost_empty_n 
+
+    // prog_full_n 
+
+    // prog_empty_n 
+
+    // num_data_cnt
+    always @(posedge clk) begin
+        if (reset)
+            num_data_cnt <= {ADDR_WIDTH+1{1'b0}};
+        else if ( push & ~pop_dout)
+            num_data_cnt <= num_data_cnt + 1'b1;
+        else if (~push & pop_dout)
+            num_data_cnt <= num_data_cnt - 1'b1;
+    end
+
+    // num_data_valid 
+    assign num_extra_words = (dout_vld & ~pop_dout) ? 1 : 0;
+                             
+    always @(posedge clk) begin
+        if (reset)
+            num_data_valid <= {ADDR_WIDTH+1{1'b0}};
+        else if (empty_n | (dout_vld & ~pop_dout))
+            num_data_valid <= push + mOutPtr + num_extra_words;
+        else
+            num_data_valid <= num_extra_words;
+    end // 
+
+    // dout_vld
+    always @(posedge clk) begin
+        if (reset)
+            dout_vld <= 1'b0;
+        else if (pop)
+            dout_vld <= 1'b1;
+        else if (pop_dout)
+            dout_vld <= 1'b0;
+    end
+
+endmodule
+
+
+module myproject_fifo_w1312_d256_A_ram
+#(parameter
+    MEM_STYLE   = "auto",
+    DATA_WIDTH  = 1312,
+    ADDR_WIDTH  = 8,
+    DEPTH       = 256)
+(
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  we,
+    input  wire [ADDR_WIDTH-1:0] waddr,
+    input  wire [DATA_WIDTH-1:0] din,
+    input  wire [ADDR_WIDTH-1:0] raddr,
+    input  wire                  rden,
+    output wire [DATA_WIDTH-1:0] dout
+);
+
+    (* ram_style = MEM_STYLE *)
+    reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+    reg  [DATA_WIDTH-1:0] mem_reg;
+
+    always @(posedge clk) begin
+        if (we)
+            mem[waddr] <= din;
+    end
+
+    always @(posedge clk) begin
+        if (reset)
+            mem_reg <= 0;
+        else if (rden)
+            mem_reg <= mem[raddr];
+    end
+    
+    assign dout = mem_reg;
+
+endmodule

myproject_prj/solution1/syn/verilog/myproject_fifo_w1376_d256_A.v

@@ -0,0 +1,237 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+//RAW latency 2 
+
+module myproject_fifo_w1376_d256_A
+#(parameter
+    MEM_STYLE    = "auto",
+    DATA_WIDTH   = 1376,
+    ADDR_WIDTH   = 8,
+    DEPTH        = 256)
+(
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+    
+    // read 
+    output wire [ADDR_WIDTH:0]   if_num_data_valid, // for FRP
+    output wire [ADDR_WIDTH:0]   if_fifo_cap,       // for FRP
+
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+localparam 
+    MEM_DEPTH    = DEPTH - 1,
+    MEM_AWIDTH   = clog2(MEM_DEPTH);
+//------------------------Local signal-------------------
+    reg  [MEM_AWIDTH-1:0] waddr;
+    reg  [MEM_AWIDTH-1:0] raddr;
+    wire [MEM_AWIDTH-1:0] wnext;
+    wire [MEM_AWIDTH-1:0] rnext;
+    wire                  push;
+    wire                  pop;
+    reg  [MEM_AWIDTH:0]   mOutPtr;
+    reg                   empty_n = 1'b0;
+    reg                   full_n = 1'b1;
+    // has num_data_valid? 
+    wire                  num_extra_words;//yes
+    reg  [ADDR_WIDTH:0]   num_data_valid; //yes 
+
+    wire                  pop_dout;
+    reg  [ADDR_WIDTH:0]   num_data_cnt;
+    reg                   dout_vld = 1'b0;
+
+//------------------------Instantiation------------------
+    myproject_fifo_w1376_d256_A_ram 
+    #(  .MEM_STYLE  (MEM_STYLE),
+        .DATA_WIDTH (DATA_WIDTH),
+        .ADDR_WIDTH (MEM_AWIDTH),
+        .DEPTH      (MEM_DEPTH)
+    ) U_myproject_fifo_w1376_d256_A_ram (
+        .clk        (clk),
+        .reset      (reset),
+        .we         (push),
+        .waddr      (waddr),
+        .din        (if_din),
+        .raddr      (raddr),
+        .rden       (pop),
+        .dout       (if_dout)
+    );
+
+//------------------------Task and function--------------
+    function integer clog2;
+        input integer x;
+        integer n, m;
+    begin
+        n = 1;
+        m = 2;
+        while (m < x) begin
+            n = n + 1;
+            m = m * 2;
+        end
+        clog2 = n;
+    end
+    endfunction
+//------------------------Body---------------------------
+    // num_data_valid 
+    assign if_num_data_valid = num_data_valid;
+    assign if_fifo_cap = DEPTH;
+
+    // almost full/empty 
+
+    // program full/empty 
+
+    assign if_full_n  = full_n;
+    assign if_empty_n = dout_vld;
+
+    assign push       = full_n & if_write_ce & if_write;
+    assign pop        = empty_n & (pop_dout | ~dout_vld);
+    assign pop_dout   = dout_vld & if_read_ce & if_read;
+    
+    assign wnext      = !push                    ? waddr :
+                        (waddr == MEM_DEPTH - 1) ? 1'b0  :
+                        waddr + 1'b1;
+    assign rnext      = !pop                     ? raddr :
+                        (raddr == MEM_DEPTH - 1) ? 1'b0  :
+                        raddr + 1'b1;
+
+    // waddr
+    always @(posedge clk) begin
+        if (reset)
+            waddr <= {MEM_AWIDTH{1'b0}};
+        else
+            waddr <= wnext;
+    end
+
+    // raddr
+    always @(posedge clk) begin
+        if (reset)
+            raddr <= {MEM_AWIDTH{1'b0}};
+        else
+            raddr <= rnext;
+    end
+
+    // mOutPtr
+    always @(posedge clk) begin
+        if (reset)
+            mOutPtr <= {MEM_AWIDTH+1{1'b0}};
+        else if (push & ~pop)
+            mOutPtr <= mOutPtr + 1'b1;
+        else if (~push & pop)
+            mOutPtr <= mOutPtr - 1'b1;
+    end
+
+    // full_n 
+    always @(posedge clk) begin
+        if (reset)
+            full_n <= 1'b1;
+        else if ((push & ~pop_dout) && (num_data_cnt == DEPTH - 1))
+            full_n <= 1'b0;
+        else if (~push & pop_dout)
+            full_n <= 1'b1;
+    end
+
+    // empty_n
+    always @(posedge clk) begin
+        if (reset)
+            empty_n <= 1'b0;
+        else if (push & ~pop)
+            empty_n <= 1'b1;
+        else if ((~push & pop) && (mOutPtr == 1))
+            empty_n <= 1'b0;
+    end
+
+    // almost_full_n 
+
+    // almost_empty_n 
+
+    // prog_full_n 
+
+    // prog_empty_n 
+
+    // num_data_cnt
+    always @(posedge clk) begin
+        if (reset)
+            num_data_cnt <= {ADDR_WIDTH+1{1'b0}};
+        else if ( push & ~pop_dout)
+            num_data_cnt <= num_data_cnt + 1'b1;
+        else if (~push & pop_dout)
+            num_data_cnt <= num_data_cnt - 1'b1;
+    end
+
+    // num_data_valid 
+    assign num_extra_words = (dout_vld & ~pop_dout) ? 1 : 0;
+                             
+    always @(posedge clk) begin
+        if (reset)
+            num_data_valid <= {ADDR_WIDTH+1{1'b0}};
+        else if (empty_n | (dout_vld & ~pop_dout))
+            num_data_valid <= push + mOutPtr + num_extra_words;
+        else
+            num_data_valid <= num_extra_words;
+    end // 
+
+    // dout_vld
+    always @(posedge clk) begin
+        if (reset)
+            dout_vld <= 1'b0;
+        else if (pop)
+            dout_vld <= 1'b1;
+        else if (pop_dout)
+            dout_vld <= 1'b0;
+    end
+
+endmodule
+
+
+module myproject_fifo_w1376_d256_A_ram
+#(parameter
+    MEM_STYLE   = "auto",
+    DATA_WIDTH  = 1376,
+    ADDR_WIDTH  = 8,
+    DEPTH       = 256)
+(
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  we,
+    input  wire [ADDR_WIDTH-1:0] waddr,
+    input  wire [DATA_WIDTH-1:0] din,
+    input  wire [ADDR_WIDTH-1:0] raddr,
+    input  wire                  rden,
+    output wire [DATA_WIDTH-1:0] dout
+);
+
+    (* ram_style = MEM_STYLE *)
+    reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+    reg  [DATA_WIDTH-1:0] mem_reg;
+
+    always @(posedge clk) begin
+        if (we)
+            mem[waddr] <= din;
+    end
+
+    always @(posedge clk) begin
+        if (reset)
+            mem_reg <= 0;
+        else if (rden)
+            mem_reg <= mem[raddr];
+    end
+    
+    assign dout = mem_reg;
+
+endmodule

myproject_prj/solution1/syn/verilog/myproject_fifo_w1536_d256_A.v

@@ -0,0 +1,237 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+//RAW latency 2 
+
+module myproject_fifo_w1536_d256_A
+#(parameter
+    MEM_STYLE    = "auto",
+    DATA_WIDTH   = 1536,
+    ADDR_WIDTH   = 8,
+    DEPTH        = 256)
+(
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+    
+    // read 
+    output wire [ADDR_WIDTH:0]   if_num_data_valid, // for FRP
+    output wire [ADDR_WIDTH:0]   if_fifo_cap,       // for FRP
+
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+localparam 
+    MEM_DEPTH    = DEPTH - 1,
+    MEM_AWIDTH   = clog2(MEM_DEPTH);
+//------------------------Local signal-------------------
+    reg  [MEM_AWIDTH-1:0] waddr;
+    reg  [MEM_AWIDTH-1:0] raddr;
+    wire [MEM_AWIDTH-1:0] wnext;
+    wire [MEM_AWIDTH-1:0] rnext;
+    wire                  push;
+    wire                  pop;
+    reg  [MEM_AWIDTH:0]   mOutPtr;
+    reg                   empty_n = 1'b0;
+    reg                   full_n = 1'b1;
+    // has num_data_valid? 
+    wire                  num_extra_words;//yes
+    reg  [ADDR_WIDTH:0]   num_data_valid; //yes 
+
+    wire                  pop_dout;
+    reg  [ADDR_WIDTH:0]   num_data_cnt;
+    reg                   dout_vld = 1'b0;
+
+//------------------------Instantiation------------------
+    myproject_fifo_w1536_d256_A_ram 
+    #(  .MEM_STYLE  (MEM_STYLE),
+        .DATA_WIDTH (DATA_WIDTH),
+        .ADDR_WIDTH (MEM_AWIDTH),
+        .DEPTH      (MEM_DEPTH)
+    ) U_myproject_fifo_w1536_d256_A_ram (
+        .clk        (clk),
+        .reset      (reset),
+        .we         (push),
+        .waddr      (waddr),
+        .din        (if_din),
+        .raddr      (raddr),
+        .rden       (pop),
+        .dout       (if_dout)
+    );
+
+//------------------------Task and function--------------
+    function integer clog2;
+        input integer x;
+        integer n, m;
+    begin
+        n = 1;
+        m = 2;
+        while (m < x) begin
+            n = n + 1;
+            m = m * 2;
+        end
+        clog2 = n;
+    end
+    endfunction
+//------------------------Body---------------------------
+    // num_data_valid 
+    assign if_num_data_valid = num_data_valid;
+    assign if_fifo_cap = DEPTH;
+
+    // almost full/empty 
+
+    // program full/empty 
+
+    assign if_full_n  = full_n;
+    assign if_empty_n = dout_vld;
+
+    assign push       = full_n & if_write_ce & if_write;
+    assign pop        = empty_n & (pop_dout | ~dout_vld);
+    assign pop_dout   = dout_vld & if_read_ce & if_read;
+    
+    assign wnext      = !push                    ? waddr :
+                        (waddr == MEM_DEPTH - 1) ? 1'b0  :
+                        waddr + 1'b1;
+    assign rnext      = !pop                     ? raddr :
+                        (raddr == MEM_DEPTH - 1) ? 1'b0  :
+                        raddr + 1'b1;
+
+    // waddr
+    always @(posedge clk) begin
+        if (reset)
+            waddr <= {MEM_AWIDTH{1'b0}};
+        else
+            waddr <= wnext;
+    end
+
+    // raddr
+    always @(posedge clk) begin
+        if (reset)
+            raddr <= {MEM_AWIDTH{1'b0}};
+        else
+            raddr <= rnext;
+    end
+
+    // mOutPtr
+    always @(posedge clk) begin
+        if (reset)
+            mOutPtr <= {MEM_AWIDTH+1{1'b0}};
+        else if (push & ~pop)
+            mOutPtr <= mOutPtr + 1'b1;
+        else if (~push & pop)
+            mOutPtr <= mOutPtr - 1'b1;
+    end
+
+    // full_n 
+    always @(posedge clk) begin
+        if (reset)
+            full_n <= 1'b1;
+        else if ((push & ~pop_dout) && (num_data_cnt == DEPTH - 1))
+            full_n <= 1'b0;
+        else if (~push & pop_dout)
+            full_n <= 1'b1;
+    end
+
+    // empty_n
+    always @(posedge clk) begin
+        if (reset)
+            empty_n <= 1'b0;
+        else if (push & ~pop)
+            empty_n <= 1'b1;
+        else if ((~push & pop) && (mOutPtr == 1))
+            empty_n <= 1'b0;
+    end
+
+    // almost_full_n 
+
+    // almost_empty_n 
+
+    // prog_full_n 
+
+    // prog_empty_n 
+
+    // num_data_cnt
+    always @(posedge clk) begin
+        if (reset)
+            num_data_cnt <= {ADDR_WIDTH+1{1'b0}};
+        else if ( push & ~pop_dout)
+            num_data_cnt <= num_data_cnt + 1'b1;
+        else if (~push & pop_dout)
+            num_data_cnt <= num_data_cnt - 1'b1;
+    end
+
+    // num_data_valid 
+    assign num_extra_words = (dout_vld & ~pop_dout) ? 1 : 0;
+                             
+    always @(posedge clk) begin
+        if (reset)
+            num_data_valid <= {ADDR_WIDTH+1{1'b0}};
+        else if (empty_n | (dout_vld & ~pop_dout))
+            num_data_valid <= push + mOutPtr + num_extra_words;
+        else
+            num_data_valid <= num_extra_words;
+    end // 
+
+    // dout_vld
+    always @(posedge clk) begin
+        if (reset)
+            dout_vld <= 1'b0;
+        else if (pop)
+            dout_vld <= 1'b1;
+        else if (pop_dout)
+            dout_vld <= 1'b0;
+    end
+
+endmodule
+
+
+module myproject_fifo_w1536_d256_A_ram
+#(parameter
+    MEM_STYLE   = "auto",
+    DATA_WIDTH  = 1536,
+    ADDR_WIDTH  = 8,
+    DEPTH       = 256)
+(
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  we,
+    input  wire [ADDR_WIDTH-1:0] waddr,
+    input  wire [DATA_WIDTH-1:0] din,
+    input  wire [ADDR_WIDTH-1:0] raddr,
+    input  wire                  rden,
+    output wire [DATA_WIDTH-1:0] dout
+);
+
+    (* ram_style = MEM_STYLE *)
+    reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+    reg  [DATA_WIDTH-1:0] mem_reg;
+
+    always @(posedge clk) begin
+        if (we)
+            mem[waddr] <= din;
+    end
+
+    always @(posedge clk) begin
+        if (reset)
+            mem_reg <= 0;
+        else if (rden)
+            mem_reg <= mem[raddr];
+    end
+    
+    assign dout = mem_reg;
+
+endmodule

myproject_prj/solution1/syn/verilog/myproject_fifo_w16_d4096_A.v

@@ -0,0 +1,237 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+//RAW latency 2 
+
+module myproject_fifo_w16_d4096_A
+#(parameter
+    MEM_STYLE    = "auto",
+    DATA_WIDTH   = 16,
+    ADDR_WIDTH   = 12,
+    DEPTH        = 4096)
+(
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+    
+    // read 
+    output wire [ADDR_WIDTH:0]   if_num_data_valid, // for FRP
+    output wire [ADDR_WIDTH:0]   if_fifo_cap,       // for FRP
+
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+localparam 
+    MEM_DEPTH    = DEPTH - 1,
+    MEM_AWIDTH   = clog2(MEM_DEPTH);
+//------------------------Local signal-------------------
+    reg  [MEM_AWIDTH-1:0] waddr;
+    reg  [MEM_AWIDTH-1:0] raddr;
+    wire [MEM_AWIDTH-1:0] wnext;
+    wire [MEM_AWIDTH-1:0] rnext;
+    wire                  push;
+    wire                  pop;
+    reg  [MEM_AWIDTH:0]   mOutPtr;
+    reg                   empty_n = 1'b0;
+    reg                   full_n = 1'b1;
+    // has num_data_valid? 
+    wire                  num_extra_words;//yes
+    reg  [ADDR_WIDTH:0]   num_data_valid; //yes 
+
+    wire                  pop_dout;
+    reg  [ADDR_WIDTH:0]   num_data_cnt;
+    reg                   dout_vld = 1'b0;
+
+//------------------------Instantiation------------------
+    myproject_fifo_w16_d4096_A_ram 
+    #(  .MEM_STYLE  (MEM_STYLE),
+        .DATA_WIDTH (DATA_WIDTH),
+        .ADDR_WIDTH (MEM_AWIDTH),
+        .DEPTH      (MEM_DEPTH)
+    ) U_myproject_fifo_w16_d4096_A_ram (
+        .clk        (clk),
+        .reset      (reset),
+        .we         (push),
+        .waddr      (waddr),
+        .din        (if_din),
+        .raddr      (raddr),
+        .rden       (pop),
+        .dout       (if_dout)
+    );
+
+//------------------------Task and function--------------
+    function integer clog2;
+        input integer x;
+        integer n, m;
+    begin
+        n = 1;
+        m = 2;
+        while (m < x) begin
+            n = n + 1;
+            m = m * 2;
+        end
+        clog2 = n;
+    end
+    endfunction
+//------------------------Body---------------------------
+    // num_data_valid 
+    assign if_num_data_valid = num_data_valid;
+    assign if_fifo_cap = DEPTH;
+
+    // almost full/empty 
+
+    // program full/empty 
+
+    assign if_full_n  = full_n;
+    assign if_empty_n = dout_vld;
+
+    assign push       = full_n & if_write_ce & if_write;
+    assign pop        = empty_n & (pop_dout | ~dout_vld);
+    assign pop_dout   = dout_vld & if_read_ce & if_read;
+    
+    assign wnext      = !push                    ? waddr :
+                        (waddr == MEM_DEPTH - 1) ? 1'b0  :
+                        waddr + 1'b1;
+    assign rnext      = !pop                     ? raddr :
+                        (raddr == MEM_DEPTH - 1) ? 1'b0  :
+                        raddr + 1'b1;
+
+    // waddr
+    always @(posedge clk) begin
+        if (reset)
+            waddr <= {MEM_AWIDTH{1'b0}};
+        else
+            waddr <= wnext;
+    end
+
+    // raddr
+    always @(posedge clk) begin
+        if (reset)
+            raddr <= {MEM_AWIDTH{1'b0}};
+        else
+            raddr <= rnext;
+    end
+
+    // mOutPtr
+    always @(posedge clk) begin
+        if (reset)
+            mOutPtr <= {MEM_AWIDTH+1{1'b0}};
+        else if (push & ~pop)
+            mOutPtr <= mOutPtr + 1'b1;
+        else if (~push & pop)
+            mOutPtr <= mOutPtr - 1'b1;
+    end
+
+    // full_n 
+    always @(posedge clk) begin
+        if (reset)
+            full_n <= 1'b1;
+        else if ((push & ~pop_dout) && (num_data_cnt == DEPTH - 1))
+            full_n <= 1'b0;
+        else if (~push & pop_dout)
+            full_n <= 1'b1;
+    end
+
+    // empty_n
+    always @(posedge clk) begin
+        if (reset)
+            empty_n <= 1'b0;
+        else if (push & ~pop)
+            empty_n <= 1'b1;
+        else if ((~push & pop) && (mOutPtr == 1))
+            empty_n <= 1'b0;
+    end
+
+    // almost_full_n 
+
+    // almost_empty_n 
+
+    // prog_full_n 
+
+    // prog_empty_n 
+
+    // num_data_cnt
+    always @(posedge clk) begin
+        if (reset)
+            num_data_cnt <= {ADDR_WIDTH+1{1'b0}};
+        else if ( push & ~pop_dout)
+            num_data_cnt <= num_data_cnt + 1'b1;
+        else if (~push & pop_dout)
+            num_data_cnt <= num_data_cnt - 1'b1;
+    end
+
+    // num_data_valid 
+    assign num_extra_words = (dout_vld & ~pop_dout) ? 1 : 0;
+                             
+    always @(posedge clk) begin
+        if (reset)
+            num_data_valid <= {ADDR_WIDTH+1{1'b0}};
+        else if (empty_n | (dout_vld & ~pop_dout))
+            num_data_valid <= push + mOutPtr + num_extra_words;
+        else
+            num_data_valid <= num_extra_words;
+    end // 
+
+    // dout_vld
+    always @(posedge clk) begin
+        if (reset)
+            dout_vld <= 1'b0;
+        else if (pop)
+            dout_vld <= 1'b1;
+        else if (pop_dout)
+            dout_vld <= 1'b0;
+    end
+
+endmodule
+
+
+module myproject_fifo_w16_d4096_A_ram
+#(parameter
+    MEM_STYLE   = "auto",
+    DATA_WIDTH  = 16,
+    ADDR_WIDTH  = 12,
+    DEPTH       = 4096)
+(
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  we,
+    input  wire [ADDR_WIDTH-1:0] waddr,
+    input  wire [DATA_WIDTH-1:0] din,
+    input  wire [ADDR_WIDTH-1:0] raddr,
+    input  wire                  rden,
+    output wire [DATA_WIDTH-1:0] dout
+);
+
+    (* ram_style = MEM_STYLE *)
+    reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+    reg  [DATA_WIDTH-1:0] mem_reg;
+
+    always @(posedge clk) begin
+        if (we)
+            mem[waddr] <= din;
+    end
+
+    always @(posedge clk) begin
+        if (reset)
+            mem_reg <= 0;
+        else if (rden)
+            mem_reg <= mem[raddr];
+    end
+    
+    assign dout = mem_reg;
+
+endmodule

myproject_prj/solution1/syn/verilog/myproject_fifo_w16_d64_S.v

@@ -0,0 +1,155 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+//RAW latency 1 
+
+module myproject_fifo_w16_d64_S
+#(parameter
+    MEM_STYLE    = "shiftReg",
+    DATA_WIDTH   = 16,
+    ADDR_WIDTH   = 6,
+    DEPTH        = 64)
+(
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+    
+    // read 
+    output wire [ADDR_WIDTH:0]   if_num_data_valid, // for FRP
+    output wire [ADDR_WIDTH:0]   if_fifo_cap,       // for FRP
+
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+localparam 
+    SRL_DEPTH    = DEPTH,
+    SRL_AWIDTH   = ADDR_WIDTH;
+//------------------------Local signal-------------------
+    reg  [SRL_AWIDTH-1:0] addr;
+    wire                  push;
+    wire                  pop;
+    reg  [SRL_AWIDTH:0]   mOutPtr;
+    reg                   empty_n = 1'b0;
+    reg                   full_n = 1'b1; 
+
+//------------------------Instantiation------------------
+    myproject_fifo_w16_d64_S_ShiftReg 
+    #(  .DATA_WIDTH (DATA_WIDTH),
+        .ADDR_WIDTH (SRL_AWIDTH),
+        .DEPTH      (SRL_DEPTH))
+    U_myproject_fifo_w16_d64_S_ShiftReg (
+        .clk        (clk),
+        .we         (push),
+        .addr       (addr),
+        .din        (if_din),
+        .dout       (if_dout)
+    );
+//------------------------Task and function--------------
+
+//------------------------Body---------------------------
+    // num_data_valid 
+    assign if_num_data_valid = mOutPtr;
+    assign if_fifo_cap       = DEPTH;
+
+    // almost full/empty 
+
+    // program full/empty 
+
+    assign if_full_n  = full_n; 
+    assign if_empty_n = empty_n;
+
+    assign push       = full_n & if_write_ce & if_write;
+    assign pop        = empty_n & if_read_ce & if_read;
+
+    // addr
+    always @(posedge clk) begin
+        if (reset)
+            addr <= {SRL_AWIDTH{1'b0}};
+        else if (push & ~pop && empty_n)
+            addr <= addr + 1'b1;
+        else if (~push & pop && (mOutPtr != 1))
+            addr <= addr - 1'b1;
+    end
+
+    // mOutPtr
+    always @(posedge clk) begin
+        if (reset)
+            mOutPtr <= {SRL_AWIDTH+1{1'b0}};
+        else if (push & ~pop)
+            mOutPtr <= mOutPtr + 1'b1;
+        else if (~push & pop)
+            mOutPtr <= mOutPtr - 1'b1;
+    end
+
+    // full_n
+    always @(posedge clk) begin
+        if (reset)
+            full_n <= 1'b1;
+        else if ((push & ~pop) && (mOutPtr == DEPTH - 1))
+            full_n <= 1'b0;
+        else if (~push & pop)
+            full_n <= 1'b1;
+    end
+
+    // empty_n
+    always @(posedge clk) begin
+        if (reset)
+            empty_n <= 1'b0;
+        else if (push & ~pop)
+            empty_n <= 1'b1;
+        else if ((~push & pop) && (mOutPtr == 1))
+            empty_n <= 1'b0;
+    end
+
+    // almost_full_n 
+
+    // almost_empty_n 
+
+    // prog_full_n 
+ 
+    // prog_empty_n 
+
+endmodule  
+
+
+module myproject_fifo_w16_d64_S_ShiftReg
+#(parameter
+    DATA_WIDTH  = 16,
+    ADDR_WIDTH  = 6,
+    DEPTH       = 64)
+(
+    input  wire                  clk,
+    input  wire                  we,
+    input  wire [ADDR_WIDTH-1:0] addr,
+    input  wire [DATA_WIDTH-1:0] din,
+    output wire [DATA_WIDTH-1:0] dout
+);
+
+    reg [DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
+    integer i;
+
+    always @(posedge clk) begin
+        if (we) begin
+            for (i=0; i<DEPTH-1; i=i+1)
+                SRL_SIG[i+1] <= SRL_SIG[i];
+            SRL_SIG[0] <= din;
+        end
+    end
+
+    assign dout = SRL_SIG[addr];
+
+endmodule

myproject_prj/solution1/syn/verilog/myproject_fifo_w256_d1156_A.v

@@ -0,0 +1,237 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+//RAW latency 2 
+
+module myproject_fifo_w256_d1156_A
+#(parameter
+    MEM_STYLE    = "auto",
+    DATA_WIDTH   = 256,
+    ADDR_WIDTH   = 11,
+    DEPTH        = 1156)
+(
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+    
+    // read 
+    output wire [ADDR_WIDTH:0]   if_num_data_valid, // for FRP
+    output wire [ADDR_WIDTH:0]   if_fifo_cap,       // for FRP
+
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+localparam 
+    MEM_DEPTH    = DEPTH - 1,
+    MEM_AWIDTH   = clog2(MEM_DEPTH);
+//------------------------Local signal-------------------
+    reg  [MEM_AWIDTH-1:0] waddr;
+    reg  [MEM_AWIDTH-1:0] raddr;
+    wire [MEM_AWIDTH-1:0] wnext;
+    wire [MEM_AWIDTH-1:0] rnext;
+    wire                  push;
+    wire                  pop;
+    reg  [MEM_AWIDTH:0]   mOutPtr;
+    reg                   empty_n = 1'b0;
+    reg                   full_n = 1'b1;
+    // has num_data_valid? 
+    wire                  num_extra_words;//yes
+    reg  [ADDR_WIDTH:0]   num_data_valid; //yes 
+
+    wire                  pop_dout;
+    reg  [ADDR_WIDTH:0]   num_data_cnt;
+    reg                   dout_vld = 1'b0;
+
+//------------------------Instantiation------------------
+    myproject_fifo_w256_d1156_A_ram 
+    #(  .MEM_STYLE  (MEM_STYLE),
+        .DATA_WIDTH (DATA_WIDTH),
+        .ADDR_WIDTH (MEM_AWIDTH),
+        .DEPTH      (MEM_DEPTH)
+    ) U_myproject_fifo_w256_d1156_A_ram (
+        .clk        (clk),
+        .reset      (reset),
+        .we         (push),
+        .waddr      (waddr),
+        .din        (if_din),
+        .raddr      (raddr),
+        .rden       (pop),
+        .dout       (if_dout)
+    );
+
+//------------------------Task and function--------------
+    function integer clog2;
+        input integer x;
+        integer n, m;
+    begin
+        n = 1;
+        m = 2;
+        while (m < x) begin
+            n = n + 1;
+            m = m * 2;
+        end
+        clog2 = n;
+    end
+    endfunction
+//------------------------Body---------------------------
+    // num_data_valid 
+    assign if_num_data_valid = num_data_valid;
+    assign if_fifo_cap = DEPTH;
+
+    // almost full/empty 
+
+    // program full/empty 
+
+    assign if_full_n  = full_n;
+    assign if_empty_n = dout_vld;
+
+    assign push       = full_n & if_write_ce & if_write;
+    assign pop        = empty_n & (pop_dout | ~dout_vld);
+    assign pop_dout   = dout_vld & if_read_ce & if_read;
+    
+    assign wnext      = !push                    ? waddr :
+                        (waddr == MEM_DEPTH - 1) ? 1'b0  :
+                        waddr + 1'b1;
+    assign rnext      = !pop                     ? raddr :
+                        (raddr == MEM_DEPTH - 1) ? 1'b0  :
+                        raddr + 1'b1;
+
+    // waddr
+    always @(posedge clk) begin
+        if (reset)
+            waddr <= {MEM_AWIDTH{1'b0}};
+        else
+            waddr <= wnext;
+    end
+
+    // raddr
+    always @(posedge clk) begin
+        if (reset)
+            raddr <= {MEM_AWIDTH{1'b0}};
+        else
+            raddr <= rnext;
+    end
+
+    // mOutPtr
+    always @(posedge clk) begin
+        if (reset)
+            mOutPtr <= {MEM_AWIDTH+1{1'b0}};
+        else if (push & ~pop)
+            mOutPtr <= mOutPtr + 1'b1;
+        else if (~push & pop)
+            mOutPtr <= mOutPtr - 1'b1;
+    end
+
+    // full_n 
+    always @(posedge clk) begin
+        if (reset)
+            full_n <= 1'b1;
+        else if ((push & ~pop_dout) && (num_data_cnt == DEPTH - 1))
+            full_n <= 1'b0;
+        else if (~push & pop_dout)
+            full_n <= 1'b1;
+    end
+
+    // empty_n
+    always @(posedge clk) begin
+        if (reset)
+            empty_n <= 1'b0;
+        else if (push & ~pop)
+            empty_n <= 1'b1;
+        else if ((~push & pop) && (mOutPtr == 1))
+            empty_n <= 1'b0;
+    end
+
+    // almost_full_n 
+
+    // almost_empty_n 
+
+    // prog_full_n 
+
+    // prog_empty_n 
+
+    // num_data_cnt
+    always @(posedge clk) begin
+        if (reset)
+            num_data_cnt <= {ADDR_WIDTH+1{1'b0}};
+        else if ( push & ~pop_dout)
+            num_data_cnt <= num_data_cnt + 1'b1;
+        else if (~push & pop_dout)
+            num_data_cnt <= num_data_cnt - 1'b1;
+    end
+
+    // num_data_valid 
+    assign num_extra_words = (dout_vld & ~pop_dout) ? 1 : 0;
+                             
+    always @(posedge clk) begin
+        if (reset)
+            num_data_valid <= {ADDR_WIDTH+1{1'b0}};
+        else if (empty_n | (dout_vld & ~pop_dout))
+            num_data_valid <= push + mOutPtr + num_extra_words;
+        else
+            num_data_valid <= num_extra_words;
+    end // 
+
+    // dout_vld
+    always @(posedge clk) begin
+        if (reset)
+            dout_vld <= 1'b0;
+        else if (pop)
+            dout_vld <= 1'b1;
+        else if (pop_dout)
+            dout_vld <= 1'b0;
+    end
+
+endmodule
+
+
+module myproject_fifo_w256_d1156_A_ram
+#(parameter
+    MEM_STYLE   = "auto",
+    DATA_WIDTH  = 256,
+    ADDR_WIDTH  = 11,
+    DEPTH       = 1156)
+(
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  we,
+    input  wire [ADDR_WIDTH-1:0] waddr,
+    input  wire [DATA_WIDTH-1:0] din,
+    input  wire [ADDR_WIDTH-1:0] raddr,
+    input  wire                  rden,
+    output wire [DATA_WIDTH-1:0] dout
+);
+
+    (* ram_style = MEM_STYLE *)
+    reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+    reg  [DATA_WIDTH-1:0] mem_reg;
+
+    always @(posedge clk) begin
+        if (we)
+            mem[waddr] <= din;
+    end
+
+    always @(posedge clk) begin
+        if (reset)
+            mem_reg <= 0;
+        else if (rden)
+            mem_reg <= mem[raddr];
+    end
+    
+    assign dout = mem_reg;
+
+endmodule

myproject_prj/solution1/syn/verilog/myproject_fifo_w320_d4096_A.v

@@ -0,0 +1,237 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+//RAW latency 2 
+
+module myproject_fifo_w320_d4096_A
+#(parameter
+    MEM_STYLE    = "auto",
+    DATA_WIDTH   = 320,
+    ADDR_WIDTH   = 12,
+    DEPTH        = 4096)
+(
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+    
+    // read 
+    output wire [ADDR_WIDTH:0]   if_num_data_valid, // for FRP
+    output wire [ADDR_WIDTH:0]   if_fifo_cap,       // for FRP
+
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+localparam 
+    MEM_DEPTH    = DEPTH - 1,
+    MEM_AWIDTH   = clog2(MEM_DEPTH);
+//------------------------Local signal-------------------
+    reg  [MEM_AWIDTH-1:0] waddr;
+    reg  [MEM_AWIDTH-1:0] raddr;
+    wire [MEM_AWIDTH-1:0] wnext;
+    wire [MEM_AWIDTH-1:0] rnext;
+    wire                  push;
+    wire                  pop;
+    reg  [MEM_AWIDTH:0]   mOutPtr;
+    reg                   empty_n = 1'b0;
+    reg                   full_n = 1'b1;
+    // has num_data_valid? 
+    wire                  num_extra_words;//yes
+    reg  [ADDR_WIDTH:0]   num_data_valid; //yes 
+
+    wire                  pop_dout;
+    reg  [ADDR_WIDTH:0]   num_data_cnt;
+    reg                   dout_vld = 1'b0;
+
+//------------------------Instantiation------------------
+    myproject_fifo_w320_d4096_A_ram 
+    #(  .MEM_STYLE  (MEM_STYLE),
+        .DATA_WIDTH (DATA_WIDTH),
+        .ADDR_WIDTH (MEM_AWIDTH),
+        .DEPTH      (MEM_DEPTH)
+    ) U_myproject_fifo_w320_d4096_A_ram (
+        .clk        (clk),
+        .reset      (reset),
+        .we         (push),
+        .waddr      (waddr),
+        .din        (if_din),
+        .raddr      (raddr),
+        .rden       (pop),
+        .dout       (if_dout)
+    );
+
+//------------------------Task and function--------------
+    function integer clog2;
+        input integer x;
+        integer n, m;
+    begin
+        n = 1;
+        m = 2;
+        while (m < x) begin
+            n = n + 1;
+            m = m * 2;
+        end
+        clog2 = n;
+    end
+    endfunction
+//------------------------Body---------------------------
+    // num_data_valid 
+    assign if_num_data_valid = num_data_valid;
+    assign if_fifo_cap = DEPTH;
+
+    // almost full/empty 
+
+    // program full/empty 
+
+    assign if_full_n  = full_n;
+    assign if_empty_n = dout_vld;
+
+    assign push       = full_n & if_write_ce & if_write;
+    assign pop        = empty_n & (pop_dout | ~dout_vld);
+    assign pop_dout   = dout_vld & if_read_ce & if_read;
+    
+    assign wnext      = !push                    ? waddr :
+                        (waddr == MEM_DEPTH - 1) ? 1'b0  :
+                        waddr + 1'b1;
+    assign rnext      = !pop                     ? raddr :
+                        (raddr == MEM_DEPTH - 1) ? 1'b0  :
+                        raddr + 1'b1;
+
+    // waddr
+    always @(posedge clk) begin
+        if (reset)
+            waddr <= {MEM_AWIDTH{1'b0}};
+        else
+            waddr <= wnext;
+    end
+
+    // raddr
+    always @(posedge clk) begin
+        if (reset)
+            raddr <= {MEM_AWIDTH{1'b0}};
+        else
+            raddr <= rnext;
+    end
+
+    // mOutPtr
+    always @(posedge clk) begin
+        if (reset)
+            mOutPtr <= {MEM_AWIDTH+1{1'b0}};
+        else if (push & ~pop)
+            mOutPtr <= mOutPtr + 1'b1;
+        else if (~push & pop)
+            mOutPtr <= mOutPtr - 1'b1;
+    end
+
+    // full_n 
+    always @(posedge clk) begin
+        if (reset)
+            full_n <= 1'b1;
+        else if ((push & ~pop_dout) && (num_data_cnt == DEPTH - 1))
+            full_n <= 1'b0;
+        else if (~push & pop_dout)
+            full_n <= 1'b1;
+    end
+
+    // empty_n
+    always @(posedge clk) begin
+        if (reset)
+            empty_n <= 1'b0;
+        else if (push & ~pop)
+            empty_n <= 1'b1;
+        else if ((~push & pop) && (mOutPtr == 1))
+            empty_n <= 1'b0;
+    end
+
+    // almost_full_n 
+
+    // almost_empty_n 
+
+    // prog_full_n 
+
+    // prog_empty_n 
+
+    // num_data_cnt
+    always @(posedge clk) begin
+        if (reset)
+            num_data_cnt <= {ADDR_WIDTH+1{1'b0}};
+        else if ( push & ~pop_dout)
+            num_data_cnt <= num_data_cnt + 1'b1;
+        else if (~push & pop_dout)
+            num_data_cnt <= num_data_cnt - 1'b1;
+    end
+
+    // num_data_valid 
+    assign num_extra_words = (dout_vld & ~pop_dout) ? 1 : 0;
+                             
+    always @(posedge clk) begin
+        if (reset)
+            num_data_valid <= {ADDR_WIDTH+1{1'b0}};
+        else if (empty_n | (dout_vld & ~pop_dout))
+            num_data_valid <= push + mOutPtr + num_extra_words;
+        else
+            num_data_valid <= num_extra_words;
+    end // 
+
+    // dout_vld
+    always @(posedge clk) begin
+        if (reset)
+            dout_vld <= 1'b0;
+        else if (pop)
+            dout_vld <= 1'b1;
+        else if (pop_dout)
+            dout_vld <= 1'b0;
+    end
+
+endmodule
+
+
+module myproject_fifo_w320_d4096_A_ram
+#(parameter
+    MEM_STYLE   = "auto",
+    DATA_WIDTH  = 320,
+    ADDR_WIDTH  = 12,
+    DEPTH       = 4096)
+(
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  we,
+    input  wire [ADDR_WIDTH-1:0] waddr,
+    input  wire [DATA_WIDTH-1:0] din,
+    input  wire [ADDR_WIDTH-1:0] raddr,
+    input  wire                  rden,
+    output wire [DATA_WIDTH-1:0] dout
+);
+
+    (* ram_style = MEM_STYLE *)
+    reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+    reg  [DATA_WIDTH-1:0] mem_reg;
+
+    always @(posedge clk) begin
+        if (we)
+            mem[waddr] <= din;
+    end
+
+    always @(posedge clk) begin
+        if (reset)
+            mem_reg <= 0;
+        else if (rden)
+            mem_reg <= mem[raddr];
+    end
+    
+    assign dout = mem_reg;
+
+endmodule

myproject_prj/solution1/syn/verilog/myproject_fifo_w328_d4096_A.v

@@ -0,0 +1,237 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+//RAW latency 2 
+
+module myproject_fifo_w328_d4096_A
+#(parameter
+    MEM_STYLE    = "auto",
+    DATA_WIDTH   = 328,
+    ADDR_WIDTH   = 12,
+    DEPTH        = 4096)
+(
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+    
+    // read 
+    output wire [ADDR_WIDTH:0]   if_num_data_valid, // for FRP
+    output wire [ADDR_WIDTH:0]   if_fifo_cap,       // for FRP
+
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+localparam 
+    MEM_DEPTH    = DEPTH - 1,
+    MEM_AWIDTH   = clog2(MEM_DEPTH);
+//------------------------Local signal-------------------
+    reg  [MEM_AWIDTH-1:0] waddr;
+    reg  [MEM_AWIDTH-1:0] raddr;
+    wire [MEM_AWIDTH-1:0] wnext;
+    wire [MEM_AWIDTH-1:0] rnext;
+    wire                  push;
+    wire                  pop;
+    reg  [MEM_AWIDTH:0]   mOutPtr;
+    reg                   empty_n = 1'b0;
+    reg                   full_n = 1'b1;
+    // has num_data_valid? 
+    wire                  num_extra_words;//yes
+    reg  [ADDR_WIDTH:0]   num_data_valid; //yes 
+
+    wire                  pop_dout;
+    reg  [ADDR_WIDTH:0]   num_data_cnt;
+    reg                   dout_vld = 1'b0;
+
+//------------------------Instantiation------------------
+    myproject_fifo_w328_d4096_A_ram 
+    #(  .MEM_STYLE  (MEM_STYLE),
+        .DATA_WIDTH (DATA_WIDTH),
+        .ADDR_WIDTH (MEM_AWIDTH),
+        .DEPTH      (MEM_DEPTH)
+    ) U_myproject_fifo_w328_d4096_A_ram (
+        .clk        (clk),
+        .reset      (reset),
+        .we         (push),
+        .waddr      (waddr),
+        .din        (if_din),
+        .raddr      (raddr),
+        .rden       (pop),
+        .dout       (if_dout)
+    );
+
+//------------------------Task and function--------------
+    function integer clog2;
+        input integer x;
+        integer n, m;
+    begin
+        n = 1;
+        m = 2;
+        while (m < x) begin
+            n = n + 1;
+            m = m * 2;
+        end
+        clog2 = n;
+    end
+    endfunction
+//------------------------Body---------------------------
+    // num_data_valid 
+    assign if_num_data_valid = num_data_valid;
+    assign if_fifo_cap = DEPTH;
+
+    // almost full/empty 
+
+    // program full/empty 
+
+    assign if_full_n  = full_n;
+    assign if_empty_n = dout_vld;
+
+    assign push       = full_n & if_write_ce & if_write;
+    assign pop        = empty_n & (pop_dout | ~dout_vld);
+    assign pop_dout   = dout_vld & if_read_ce & if_read;
+    
+    assign wnext      = !push                    ? waddr :
+                        (waddr == MEM_DEPTH - 1) ? 1'b0  :
+                        waddr + 1'b1;
+    assign rnext      = !pop                     ? raddr :
+                        (raddr == MEM_DEPTH - 1) ? 1'b0  :
+                        raddr + 1'b1;
+
+    // waddr
+    always @(posedge clk) begin
+        if (reset)
+            waddr <= {MEM_AWIDTH{1'b0}};
+        else
+            waddr <= wnext;
+    end
+
+    // raddr
+    always @(posedge clk) begin
+        if (reset)
+            raddr <= {MEM_AWIDTH{1'b0}};
+        else
+            raddr <= rnext;
+    end
+
+    // mOutPtr
+    always @(posedge clk) begin
+        if (reset)
+            mOutPtr <= {MEM_AWIDTH+1{1'b0}};
+        else if (push & ~pop)
+            mOutPtr <= mOutPtr + 1'b1;
+        else if (~push & pop)
+            mOutPtr <= mOutPtr - 1'b1;
+    end
+
+    // full_n 
+    always @(posedge clk) begin
+        if (reset)
+            full_n <= 1'b1;
+        else if ((push & ~pop_dout) && (num_data_cnt == DEPTH - 1))
+            full_n <= 1'b0;
+        else if (~push & pop_dout)
+            full_n <= 1'b1;
+    end
+
+    // empty_n
+    always @(posedge clk) begin
+        if (reset)
+            empty_n <= 1'b0;
+        else if (push & ~pop)
+            empty_n <= 1'b1;
+        else if ((~push & pop) && (mOutPtr == 1))
+            empty_n <= 1'b0;
+    end
+
+    // almost_full_n 
+
+    // almost_empty_n 
+
+    // prog_full_n 
+
+    // prog_empty_n 
+
+    // num_data_cnt
+    always @(posedge clk) begin
+        if (reset)
+            num_data_cnt <= {ADDR_WIDTH+1{1'b0}};
+        else if ( push & ~pop_dout)
+            num_data_cnt <= num_data_cnt + 1'b1;
+        else if (~push & pop_dout)
+            num_data_cnt <= num_data_cnt - 1'b1;
+    end
+
+    // num_data_valid 
+    assign num_extra_words = (dout_vld & ~pop_dout) ? 1 : 0;
+                             
+    always @(posedge clk) begin
+        if (reset)
+            num_data_valid <= {ADDR_WIDTH+1{1'b0}};
+        else if (empty_n | (dout_vld & ~pop_dout))
+            num_data_valid <= push + mOutPtr + num_extra_words;
+        else
+            num_data_valid <= num_extra_words;
+    end // 
+
+    // dout_vld
+    always @(posedge clk) begin
+        if (reset)
+            dout_vld <= 1'b0;
+        else if (pop)
+            dout_vld <= 1'b1;
+        else if (pop_dout)
+            dout_vld <= 1'b0;
+    end
+
+endmodule
+
+
+module myproject_fifo_w328_d4096_A_ram
+#(parameter
+    MEM_STYLE   = "auto",
+    DATA_WIDTH  = 328,
+    ADDR_WIDTH  = 12,
+    DEPTH       = 4096)
+(
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  we,
+    input  wire [ADDR_WIDTH-1:0] waddr,
+    input  wire [DATA_WIDTH-1:0] din,
+    input  wire [ADDR_WIDTH-1:0] raddr,
+    input  wire                  rden,
+    output wire [DATA_WIDTH-1:0] dout
+);
+
+    (* ram_style = MEM_STYLE *)
+    reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+    reg  [DATA_WIDTH-1:0] mem_reg;
+
+    always @(posedge clk) begin
+        if (we)
+            mem[waddr] <= din;
+    end
+
+    always @(posedge clk) begin
+        if (reset)
+            mem_reg <= 0;
+        else if (rden)
+            mem_reg <= mem[raddr];
+    end
+    
+    assign dout = mem_reg;
+
+endmodule

myproject_prj/solution1/syn/verilog/myproject_fifo_w36_d4096_A.v

@@ -0,0 +1,237 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+//RAW latency 2 
+
+module myproject_fifo_w36_d4096_A
+#(parameter
+    MEM_STYLE    = "auto",
+    DATA_WIDTH   = 36,
+    ADDR_WIDTH   = 12,
+    DEPTH        = 4096)
+(
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+    
+    // read 
+    output wire [ADDR_WIDTH:0]   if_num_data_valid, // for FRP
+    output wire [ADDR_WIDTH:0]   if_fifo_cap,       // for FRP
+
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+localparam 
+    MEM_DEPTH    = DEPTH - 1,
+    MEM_AWIDTH   = clog2(MEM_DEPTH);
+//------------------------Local signal-------------------
+    reg  [MEM_AWIDTH-1:0] waddr;
+    reg  [MEM_AWIDTH-1:0] raddr;
+    wire [MEM_AWIDTH-1:0] wnext;
+    wire [MEM_AWIDTH-1:0] rnext;
+    wire                  push;
+    wire                  pop;
+    reg  [MEM_AWIDTH:0]   mOutPtr;
+    reg                   empty_n = 1'b0;
+    reg                   full_n = 1'b1;
+    // has num_data_valid? 
+    wire                  num_extra_words;//yes
+    reg  [ADDR_WIDTH:0]   num_data_valid; //yes 
+
+    wire                  pop_dout;
+    reg  [ADDR_WIDTH:0]   num_data_cnt;
+    reg                   dout_vld = 1'b0;
+
+//------------------------Instantiation------------------
+    myproject_fifo_w36_d4096_A_ram 
+    #(  .MEM_STYLE  (MEM_STYLE),
+        .DATA_WIDTH (DATA_WIDTH),
+        .ADDR_WIDTH (MEM_AWIDTH),
+        .DEPTH      (MEM_DEPTH)
+    ) U_myproject_fifo_w36_d4096_A_ram (
+        .clk        (clk),
+        .reset      (reset),
+        .we         (push),
+        .waddr      (waddr),
+        .din        (if_din),
+        .raddr      (raddr),
+        .rden       (pop),
+        .dout       (if_dout)
+    );
+
+//------------------------Task and function--------------
+    function integer clog2;
+        input integer x;
+        integer n, m;
+    begin
+        n = 1;
+        m = 2;
+        while (m < x) begin
+            n = n + 1;
+            m = m * 2;
+        end
+        clog2 = n;
+    end
+    endfunction
+//------------------------Body---------------------------
+    // num_data_valid 
+    assign if_num_data_valid = num_data_valid;
+    assign if_fifo_cap = DEPTH;
+
+    // almost full/empty 
+
+    // program full/empty 
+
+    assign if_full_n  = full_n;
+    assign if_empty_n = dout_vld;
+
+    assign push       = full_n & if_write_ce & if_write;
+    assign pop        = empty_n & (pop_dout | ~dout_vld);
+    assign pop_dout   = dout_vld & if_read_ce & if_read;
+    
+    assign wnext      = !push                    ? waddr :
+                        (waddr == MEM_DEPTH - 1) ? 1'b0  :
+                        waddr + 1'b1;
+    assign rnext      = !pop                     ? raddr :
+                        (raddr == MEM_DEPTH - 1) ? 1'b0  :
+                        raddr + 1'b1;
+
+    // waddr
+    always @(posedge clk) begin
+        if (reset)
+            waddr <= {MEM_AWIDTH{1'b0}};
+        else
+            waddr <= wnext;
+    end
+
+    // raddr
+    always @(posedge clk) begin
+        if (reset)
+            raddr <= {MEM_AWIDTH{1'b0}};
+        else
+            raddr <= rnext;
+    end
+
+    // mOutPtr
+    always @(posedge clk) begin
+        if (reset)
+            mOutPtr <= {MEM_AWIDTH+1{1'b0}};
+        else if (push & ~pop)
+            mOutPtr <= mOutPtr + 1'b1;
+        else if (~push & pop)
+            mOutPtr <= mOutPtr - 1'b1;
+    end
+
+    // full_n 
+    always @(posedge clk) begin
+        if (reset)
+            full_n <= 1'b1;
+        else if ((push & ~pop_dout) && (num_data_cnt == DEPTH - 1))
+            full_n <= 1'b0;
+        else if (~push & pop_dout)
+            full_n <= 1'b1;
+    end
+
+    // empty_n
+    always @(posedge clk) begin
+        if (reset)
+            empty_n <= 1'b0;
+        else if (push & ~pop)
+            empty_n <= 1'b1;
+        else if ((~push & pop) && (mOutPtr == 1))
+            empty_n <= 1'b0;
+    end
+
+    // almost_full_n 
+
+    // almost_empty_n 
+
+    // prog_full_n 
+
+    // prog_empty_n 
+
+    // num_data_cnt
+    always @(posedge clk) begin
+        if (reset)
+            num_data_cnt <= {ADDR_WIDTH+1{1'b0}};
+        else if ( push & ~pop_dout)
+            num_data_cnt <= num_data_cnt + 1'b1;
+        else if (~push & pop_dout)
+            num_data_cnt <= num_data_cnt - 1'b1;
+    end
+
+    // num_data_valid 
+    assign num_extra_words = (dout_vld & ~pop_dout) ? 1 : 0;
+                             
+    always @(posedge clk) begin
+        if (reset)
+            num_data_valid <= {ADDR_WIDTH+1{1'b0}};
+        else if (empty_n | (dout_vld & ~pop_dout))
+            num_data_valid <= push + mOutPtr + num_extra_words;
+        else
+            num_data_valid <= num_extra_words;
+    end // 
+
+    // dout_vld
+    always @(posedge clk) begin
+        if (reset)
+            dout_vld <= 1'b0;
+        else if (pop)
+            dout_vld <= 1'b1;
+        else if (pop_dout)
+            dout_vld <= 1'b0;
+    end
+
+endmodule
+
+
+module myproject_fifo_w36_d4096_A_ram
+#(parameter
+    MEM_STYLE   = "auto",
+    DATA_WIDTH  = 36,
+    ADDR_WIDTH  = 12,
+    DEPTH       = 4096)
+(
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  we,
+    input  wire [ADDR_WIDTH-1:0] waddr,
+    input  wire [DATA_WIDTH-1:0] din,
+    input  wire [ADDR_WIDTH-1:0] raddr,
+    input  wire                  rden,
+    output wire [DATA_WIDTH-1:0] dout
+);
+
+    (* ram_style = MEM_STYLE *)
+    reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+    reg  [DATA_WIDTH-1:0] mem_reg;
+
+    always @(posedge clk) begin
+        if (we)
+            mem[waddr] <= din;
+    end
+
+    always @(posedge clk) begin
+        if (reset)
+            mem_reg <= 0;
+        else if (rden)
+            mem_reg <= mem[raddr];
+    end
+    
+    assign dout = mem_reg;
+
+endmodule

myproject_prj/solution1/syn/verilog/myproject_fifo_w384_d4096_A.v

@@ -0,0 +1,237 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+//RAW latency 2 
+
+module myproject_fifo_w384_d4096_A
+#(parameter
+    MEM_STYLE    = "auto",
+    DATA_WIDTH   = 384,
+    ADDR_WIDTH   = 12,
+    DEPTH        = 4096)
+(
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+    
+    // read 
+    output wire [ADDR_WIDTH:0]   if_num_data_valid, // for FRP
+    output wire [ADDR_WIDTH:0]   if_fifo_cap,       // for FRP
+
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+localparam 
+    MEM_DEPTH    = DEPTH - 1,
+    MEM_AWIDTH   = clog2(MEM_DEPTH);
+//------------------------Local signal-------------------
+    reg  [MEM_AWIDTH-1:0] waddr;
+    reg  [MEM_AWIDTH-1:0] raddr;
+    wire [MEM_AWIDTH-1:0] wnext;
+    wire [MEM_AWIDTH-1:0] rnext;
+    wire                  push;
+    wire                  pop;
+    reg  [MEM_AWIDTH:0]   mOutPtr;
+    reg                   empty_n = 1'b0;
+    reg                   full_n = 1'b1;
+    // has num_data_valid? 
+    wire                  num_extra_words;//yes
+    reg  [ADDR_WIDTH:0]   num_data_valid; //yes 
+
+    wire                  pop_dout;
+    reg  [ADDR_WIDTH:0]   num_data_cnt;
+    reg                   dout_vld = 1'b0;
+
+//------------------------Instantiation------------------
+    myproject_fifo_w384_d4096_A_ram 
+    #(  .MEM_STYLE  (MEM_STYLE),
+        .DATA_WIDTH (DATA_WIDTH),
+        .ADDR_WIDTH (MEM_AWIDTH),
+        .DEPTH      (MEM_DEPTH)
+    ) U_myproject_fifo_w384_d4096_A_ram (
+        .clk        (clk),
+        .reset      (reset),
+        .we         (push),
+        .waddr      (waddr),
+        .din        (if_din),
+        .raddr      (raddr),
+        .rden       (pop),
+        .dout       (if_dout)
+    );
+
+//------------------------Task and function--------------
+    function integer clog2;
+        input integer x;
+        integer n, m;
+    begin
+        n = 1;
+        m = 2;
+        while (m < x) begin
+            n = n + 1;
+            m = m * 2;
+        end
+        clog2 = n;
+    end
+    endfunction
+//------------------------Body---------------------------
+    // num_data_valid 
+    assign if_num_data_valid = num_data_valid;
+    assign if_fifo_cap = DEPTH;
+
+    // almost full/empty 
+
+    // program full/empty 
+
+    assign if_full_n  = full_n;
+    assign if_empty_n = dout_vld;
+
+    assign push       = full_n & if_write_ce & if_write;
+    assign pop        = empty_n & (pop_dout | ~dout_vld);
+    assign pop_dout   = dout_vld & if_read_ce & if_read;
+    
+    assign wnext      = !push                    ? waddr :
+                        (waddr == MEM_DEPTH - 1) ? 1'b0  :
+                        waddr + 1'b1;
+    assign rnext      = !pop                     ? raddr :
+                        (raddr == MEM_DEPTH - 1) ? 1'b0  :
+                        raddr + 1'b1;
+
+    // waddr
+    always @(posedge clk) begin
+        if (reset)
+            waddr <= {MEM_AWIDTH{1'b0}};
+        else
+            waddr <= wnext;
+    end
+
+    // raddr
+    always @(posedge clk) begin
+        if (reset)
+            raddr <= {MEM_AWIDTH{1'b0}};
+        else
+            raddr <= rnext;
+    end
+
+    // mOutPtr
+    always @(posedge clk) begin
+        if (reset)
+            mOutPtr <= {MEM_AWIDTH+1{1'b0}};
+        else if (push & ~pop)
+            mOutPtr <= mOutPtr + 1'b1;
+        else if (~push & pop)
+            mOutPtr <= mOutPtr - 1'b1;
+    end
+
+    // full_n 
+    always @(posedge clk) begin
+        if (reset)
+            full_n <= 1'b1;
+        else if ((push & ~pop_dout) && (num_data_cnt == DEPTH - 1))
+            full_n <= 1'b0;
+        else if (~push & pop_dout)
+            full_n <= 1'b1;
+    end
+
+    // empty_n
+    always @(posedge clk) begin
+        if (reset)
+            empty_n <= 1'b0;
+        else if (push & ~pop)
+            empty_n <= 1'b1;
+        else if ((~push & pop) && (mOutPtr == 1))
+            empty_n <= 1'b0;
+    end
+
+    // almost_full_n 
+
+    // almost_empty_n 
+
+    // prog_full_n 
+
+    // prog_empty_n 
+
+    // num_data_cnt
+    always @(posedge clk) begin
+        if (reset)
+            num_data_cnt <= {ADDR_WIDTH+1{1'b0}};
+        else if ( push & ~pop_dout)
+            num_data_cnt <= num_data_cnt + 1'b1;
+        else if (~push & pop_dout)
+            num_data_cnt <= num_data_cnt - 1'b1;
+    end
+
+    // num_data_valid 
+    assign num_extra_words = (dout_vld & ~pop_dout) ? 1 : 0;
+                             
+    always @(posedge clk) begin
+        if (reset)
+            num_data_valid <= {ADDR_WIDTH+1{1'b0}};
+        else if (empty_n | (dout_vld & ~pop_dout))
+            num_data_valid <= push + mOutPtr + num_extra_words;
+        else
+            num_data_valid <= num_extra_words;
+    end // 
+
+    // dout_vld
+    always @(posedge clk) begin
+        if (reset)
+            dout_vld <= 1'b0;
+        else if (pop)
+            dout_vld <= 1'b1;
+        else if (pop_dout)
+            dout_vld <= 1'b0;
+    end
+
+endmodule
+
+
+module myproject_fifo_w384_d4096_A_ram
+#(parameter
+    MEM_STYLE   = "auto",
+    DATA_WIDTH  = 384,
+    ADDR_WIDTH  = 12,
+    DEPTH       = 4096)
+(
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  we,
+    input  wire [ADDR_WIDTH-1:0] waddr,
+    input  wire [DATA_WIDTH-1:0] din,
+    input  wire [ADDR_WIDTH-1:0] raddr,
+    input  wire                  rden,
+    output wire [DATA_WIDTH-1:0] dout
+);
+
+    (* ram_style = MEM_STYLE *)
+    reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+    reg  [DATA_WIDTH-1:0] mem_reg;
+
+    always @(posedge clk) begin
+        if (we)
+            mem[waddr] <= din;
+    end
+
+    always @(posedge clk) begin
+        if (reset)
+            mem_reg <= 0;
+        else if (rden)
+            mem_reg <= mem[raddr];
+    end
+    
+    assign dout = mem_reg;
+
+endmodule

myproject_prj/solution1/syn/verilog/myproject_fifo_w512_d256_A.v

@@ -0,0 +1,237 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+//RAW latency 2 
+
+module myproject_fifo_w512_d256_A
+#(parameter
+    MEM_STYLE    = "auto",
+    DATA_WIDTH   = 512,
+    ADDR_WIDTH   = 8,
+    DEPTH        = 256)
+(
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+    
+    // read 
+    output wire [ADDR_WIDTH:0]   if_num_data_valid, // for FRP
+    output wire [ADDR_WIDTH:0]   if_fifo_cap,       // for FRP
+
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+localparam 
+    MEM_DEPTH    = DEPTH - 1,
+    MEM_AWIDTH   = clog2(MEM_DEPTH);
+//------------------------Local signal-------------------
+    reg  [MEM_AWIDTH-1:0] waddr;
+    reg  [MEM_AWIDTH-1:0] raddr;
+    wire [MEM_AWIDTH-1:0] wnext;
+    wire [MEM_AWIDTH-1:0] rnext;
+    wire                  push;
+    wire                  pop;
+    reg  [MEM_AWIDTH:0]   mOutPtr;
+    reg                   empty_n = 1'b0;
+    reg                   full_n = 1'b1;
+    // has num_data_valid? 
+    wire                  num_extra_words;//yes
+    reg  [ADDR_WIDTH:0]   num_data_valid; //yes 
+
+    wire                  pop_dout;
+    reg  [ADDR_WIDTH:0]   num_data_cnt;
+    reg                   dout_vld = 1'b0;
+
+//------------------------Instantiation------------------
+    myproject_fifo_w512_d256_A_ram 
+    #(  .MEM_STYLE  (MEM_STYLE),
+        .DATA_WIDTH (DATA_WIDTH),
+        .ADDR_WIDTH (MEM_AWIDTH),
+        .DEPTH      (MEM_DEPTH)
+    ) U_myproject_fifo_w512_d256_A_ram (
+        .clk        (clk),
+        .reset      (reset),
+        .we         (push),
+        .waddr      (waddr),
+        .din        (if_din),
+        .raddr      (raddr),
+        .rden       (pop),
+        .dout       (if_dout)
+    );
+
+//------------------------Task and function--------------
+    function integer clog2;
+        input integer x;
+        integer n, m;
+    begin
+        n = 1;
+        m = 2;
+        while (m < x) begin
+            n = n + 1;
+            m = m * 2;
+        end
+        clog2 = n;
+    end
+    endfunction
+//------------------------Body---------------------------
+    // num_data_valid 
+    assign if_num_data_valid = num_data_valid;
+    assign if_fifo_cap = DEPTH;
+
+    // almost full/empty 
+
+    // program full/empty 
+
+    assign if_full_n  = full_n;
+    assign if_empty_n = dout_vld;
+
+    assign push       = full_n & if_write_ce & if_write;
+    assign pop        = empty_n & (pop_dout | ~dout_vld);
+    assign pop_dout   = dout_vld & if_read_ce & if_read;
+    
+    assign wnext      = !push                    ? waddr :
+                        (waddr == MEM_DEPTH - 1) ? 1'b0  :
+                        waddr + 1'b1;
+    assign rnext      = !pop                     ? raddr :
+                        (raddr == MEM_DEPTH - 1) ? 1'b0  :
+                        raddr + 1'b1;
+
+    // waddr
+    always @(posedge clk) begin
+        if (reset)
+            waddr <= {MEM_AWIDTH{1'b0}};
+        else
+            waddr <= wnext;
+    end
+
+    // raddr
+    always @(posedge clk) begin
+        if (reset)
+            raddr <= {MEM_AWIDTH{1'b0}};
+        else
+            raddr <= rnext;
+    end
+
+    // mOutPtr
+    always @(posedge clk) begin
+        if (reset)
+            mOutPtr <= {MEM_AWIDTH+1{1'b0}};
+        else if (push & ~pop)
+            mOutPtr <= mOutPtr + 1'b1;
+        else if (~push & pop)
+            mOutPtr <= mOutPtr - 1'b1;
+    end
+
+    // full_n 
+    always @(posedge clk) begin
+        if (reset)
+            full_n <= 1'b1;
+        else if ((push & ~pop_dout) && (num_data_cnt == DEPTH - 1))
+            full_n <= 1'b0;
+        else if (~push & pop_dout)
+            full_n <= 1'b1;
+    end
+
+    // empty_n
+    always @(posedge clk) begin
+        if (reset)
+            empty_n <= 1'b0;
+        else if (push & ~pop)
+            empty_n <= 1'b1;
+        else if ((~push & pop) && (mOutPtr == 1))
+            empty_n <= 1'b0;
+    end
+
+    // almost_full_n 
+
+    // almost_empty_n 
+
+    // prog_full_n 
+
+    // prog_empty_n 
+
+    // num_data_cnt
+    always @(posedge clk) begin
+        if (reset)
+            num_data_cnt <= {ADDR_WIDTH+1{1'b0}};
+        else if ( push & ~pop_dout)
+            num_data_cnt <= num_data_cnt + 1'b1;
+        else if (~push & pop_dout)
+            num_data_cnt <= num_data_cnt - 1'b1;
+    end
+
+    // num_data_valid 
+    assign num_extra_words = (dout_vld & ~pop_dout) ? 1 : 0;
+                             
+    always @(posedge clk) begin
+        if (reset)
+            num_data_valid <= {ADDR_WIDTH+1{1'b0}};
+        else if (empty_n | (dout_vld & ~pop_dout))
+            num_data_valid <= push + mOutPtr + num_extra_words;
+        else
+            num_data_valid <= num_extra_words;
+    end // 
+
+    // dout_vld
+    always @(posedge clk) begin
+        if (reset)
+            dout_vld <= 1'b0;
+        else if (pop)
+            dout_vld <= 1'b1;
+        else if (pop_dout)
+            dout_vld <= 1'b0;
+    end
+
+endmodule
+
+
+module myproject_fifo_w512_d256_A_ram
+#(parameter
+    MEM_STYLE   = "auto",
+    DATA_WIDTH  = 512,
+    ADDR_WIDTH  = 8,
+    DEPTH       = 256)
+(
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  we,
+    input  wire [ADDR_WIDTH-1:0] waddr,
+    input  wire [DATA_WIDTH-1:0] din,
+    input  wire [ADDR_WIDTH-1:0] raddr,
+    input  wire                  rden,
+    output wire [DATA_WIDTH-1:0] dout
+);
+
+    (* ram_style = MEM_STYLE *)
+    reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+    reg  [DATA_WIDTH-1:0] mem_reg;
+
+    always @(posedge clk) begin
+        if (we)
+            mem[waddr] <= din;
+    end
+
+    always @(posedge clk) begin
+        if (reset)
+            mem_reg <= 0;
+        else if (rden)
+            mem_reg <= mem[raddr];
+    end
+    
+    assign dout = mem_reg;
+
+endmodule

myproject_prj/solution1/syn/verilog/myproject_fifo_w768_d1024_A.v

@@ -0,0 +1,237 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+//RAW latency 2 
+
+module myproject_fifo_w768_d1024_A
+#(parameter
+    MEM_STYLE    = "auto",
+    DATA_WIDTH   = 768,
+    ADDR_WIDTH   = 10,
+    DEPTH        = 1024)
+(
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+    
+    // read 
+    output wire [ADDR_WIDTH:0]   if_num_data_valid, // for FRP
+    output wire [ADDR_WIDTH:0]   if_fifo_cap,       // for FRP
+
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+localparam 
+    MEM_DEPTH    = DEPTH - 1,
+    MEM_AWIDTH   = clog2(MEM_DEPTH);
+//------------------------Local signal-------------------
+    reg  [MEM_AWIDTH-1:0] waddr;
+    reg  [MEM_AWIDTH-1:0] raddr;
+    wire [MEM_AWIDTH-1:0] wnext;
+    wire [MEM_AWIDTH-1:0] rnext;
+    wire                  push;
+    wire                  pop;
+    reg  [MEM_AWIDTH:0]   mOutPtr;
+    reg                   empty_n = 1'b0;
+    reg                   full_n = 1'b1;
+    // has num_data_valid? 
+    wire                  num_extra_words;//yes
+    reg  [ADDR_WIDTH:0]   num_data_valid; //yes 
+
+    wire                  pop_dout;
+    reg  [ADDR_WIDTH:0]   num_data_cnt;
+    reg                   dout_vld = 1'b0;
+
+//------------------------Instantiation------------------
+    myproject_fifo_w768_d1024_A_ram 
+    #(  .MEM_STYLE  (MEM_STYLE),
+        .DATA_WIDTH (DATA_WIDTH),
+        .ADDR_WIDTH (MEM_AWIDTH),
+        .DEPTH      (MEM_DEPTH)
+    ) U_myproject_fifo_w768_d1024_A_ram (
+        .clk        (clk),
+        .reset      (reset),
+        .we         (push),
+        .waddr      (waddr),
+        .din        (if_din),
+        .raddr      (raddr),
+        .rden       (pop),
+        .dout       (if_dout)
+    );
+
+//------------------------Task and function--------------
+    function integer clog2;
+        input integer x;
+        integer n, m;
+    begin
+        n = 1;
+        m = 2;
+        while (m < x) begin
+            n = n + 1;
+            m = m * 2;
+        end
+        clog2 = n;
+    end
+    endfunction
+//------------------------Body---------------------------
+    // num_data_valid 
+    assign if_num_data_valid = num_data_valid;
+    assign if_fifo_cap = DEPTH;
+
+    // almost full/empty 
+
+    // program full/empty 
+
+    assign if_full_n  = full_n;
+    assign if_empty_n = dout_vld;
+
+    assign push       = full_n & if_write_ce & if_write;
+    assign pop        = empty_n & (pop_dout | ~dout_vld);
+    assign pop_dout   = dout_vld & if_read_ce & if_read;
+    
+    assign wnext      = !push                    ? waddr :
+                        (waddr == MEM_DEPTH - 1) ? 1'b0  :
+                        waddr + 1'b1;
+    assign rnext      = !pop                     ? raddr :
+                        (raddr == MEM_DEPTH - 1) ? 1'b0  :
+                        raddr + 1'b1;
+
+    // waddr
+    always @(posedge clk) begin
+        if (reset)
+            waddr <= {MEM_AWIDTH{1'b0}};
+        else
+            waddr <= wnext;
+    end
+
+    // raddr
+    always @(posedge clk) begin
+        if (reset)
+            raddr <= {MEM_AWIDTH{1'b0}};
+        else
+            raddr <= rnext;
+    end
+
+    // mOutPtr
+    always @(posedge clk) begin
+        if (reset)
+            mOutPtr <= {MEM_AWIDTH+1{1'b0}};
+        else if (push & ~pop)
+            mOutPtr <= mOutPtr + 1'b1;
+        else if (~push & pop)
+            mOutPtr <= mOutPtr - 1'b1;
+    end
+
+    // full_n 
+    always @(posedge clk) begin
+        if (reset)
+            full_n <= 1'b1;
+        else if ((push & ~pop_dout) && (num_data_cnt == DEPTH - 1))
+            full_n <= 1'b0;
+        else if (~push & pop_dout)
+            full_n <= 1'b1;
+    end
+
+    // empty_n
+    always @(posedge clk) begin
+        if (reset)
+            empty_n <= 1'b0;
+        else if (push & ~pop)
+            empty_n <= 1'b1;
+        else if ((~push & pop) && (mOutPtr == 1))
+            empty_n <= 1'b0;
+    end
+
+    // almost_full_n 
+
+    // almost_empty_n 
+
+    // prog_full_n 
+
+    // prog_empty_n 
+
+    // num_data_cnt
+    always @(posedge clk) begin
+        if (reset)
+            num_data_cnt <= {ADDR_WIDTH+1{1'b0}};
+        else if ( push & ~pop_dout)
+            num_data_cnt <= num_data_cnt + 1'b1;
+        else if (~push & pop_dout)
+            num_data_cnt <= num_data_cnt - 1'b1;
+    end
+
+    // num_data_valid 
+    assign num_extra_words = (dout_vld & ~pop_dout) ? 1 : 0;
+                             
+    always @(posedge clk) begin
+        if (reset)
+            num_data_valid <= {ADDR_WIDTH+1{1'b0}};
+        else if (empty_n | (dout_vld & ~pop_dout))
+            num_data_valid <= push + mOutPtr + num_extra_words;
+        else
+            num_data_valid <= num_extra_words;
+    end // 
+
+    // dout_vld
+    always @(posedge clk) begin
+        if (reset)
+            dout_vld <= 1'b0;
+        else if (pop)
+            dout_vld <= 1'b1;
+        else if (pop_dout)
+            dout_vld <= 1'b0;
+    end
+
+endmodule
+
+
+module myproject_fifo_w768_d1024_A_ram
+#(parameter
+    MEM_STYLE   = "auto",
+    DATA_WIDTH  = 768,
+    ADDR_WIDTH  = 10,
+    DEPTH       = 1024)
+(
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  we,
+    input  wire [ADDR_WIDTH-1:0] waddr,
+    input  wire [DATA_WIDTH-1:0] din,
+    input  wire [ADDR_WIDTH-1:0] raddr,
+    input  wire                  rden,
+    output wire [DATA_WIDTH-1:0] dout
+);
+
+    (* ram_style = MEM_STYLE *)
+    reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+    reg  [DATA_WIDTH-1:0] mem_reg;
+
+    always @(posedge clk) begin
+        if (we)
+            mem[waddr] <= din;
+    end
+
+    always @(posedge clk) begin
+        if (reset)
+            mem_reg <= 0;
+        else if (rden)
+            mem_reg <= mem[raddr];
+    end
+    
+    assign dout = mem_reg;
+
+endmodule

myproject_prj/solution1/syn/verilog/myproject_flow_control_loop_pipe_no_ap_cont.v

@@ -0,0 +1,104 @@
+// ==============================================================
+// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2024.1 (64-bit)
+// Tool Version Limit: 2024.05
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// 
+// ==============================================================
+
+`timescale 1 ns / 1 ps
+
+module myproject_flow_control_loop_pipe_no_ap_cont(
+        ap_clk,
+        ap_rst,
+        ap_start,
+        ap_ready,
+        ap_done,
+        ap_start_int,
+        ap_ready_int,
+        ap_done_int,
+        ap_continue_int,
+        ap_loop_init,
+        ap_loop_exit_ready,
+        ap_loop_exit_done
+);
+
+input   ap_clk;
+input   ap_rst;
+
+//Block level handshake with outside loop
+input   ap_start;
+output  ap_ready;
+output  ap_done;
+
+//Block level handshake with loop body
+output  ap_start_int;
+input   ap_ready_int;
+input   ap_done_int;
+output  ap_continue_int;
+
+//Init live in variables
+output   ap_loop_init;
+reg ap_loop_init;
+reg ap_done;
+reg ap_done_cache;
+
+//Exit signal from loop body
+input   ap_loop_exit_ready;
+input   ap_loop_exit_done;
+
+// power-on initialization
+initial begin
+#0 ap_loop_init = 1'b1;
+#0 ap_done_cache = 1'b0;
+end
+
+assign ap_start_int = ap_start;
+
+assign ap_continue_int = 1'b1;
+
+assign ap_ready = ap_loop_exit_ready;
+
+//ap_loop_init is valid for the first II
+//of the first loop run so as to enable
+//the init block ops which are pushed into
+//the first state of the pipeline region
+always @ (posedge ap_clk)
+begin
+    if (ap_rst == 1'b1) begin
+        ap_loop_init <= 1'b1;
+    end else if(ap_loop_exit_ready == 1'b1) begin
+        ap_loop_init <= 1'b1;
+    end else if(ap_ready_int == 1'b1) begin
+        ap_loop_init <= 1'b0;
+    end
+end
+
+// if no ap_continue port and current module is not top module, 
+// ap_done handshakes with ap_start. Internally, flow control sends out 
+// ap_conintue_int = 1'b1 so the ap_done_int is asserted high for 1 clock cycle.
+// ap_done_cache is used to record ap_done_int, and de-assert if ap_start_int
+// is asserted, so DUT can start the next run
+always @(posedge ap_clk)
+begin
+    if (ap_rst == 1'b1) begin
+        ap_done_cache <= 1'b0;
+    end else if (ap_done_int == 1'b1) begin
+        ap_done_cache <= 1'b1;
+    end else if (ap_start_int == 1'b1) begin
+        ap_done_cache <= 1'b0;
+    end
+end
+
+// if no ap_continue port and current module is not top module, ap_done handshakes with ap_start
+always @(*)
+begin
+    if ((ap_done_int == 1'b1) || ((ap_done_cache == 1'b1) && (ap_start_int == 1'b0))) begin
+        ap_done = 1'b1;
+    end else begin
+        ap_done = 1'b0;
+    end
+end
+
+endmodule
+        

myproject_prj/solution1/syn/verilog/myproject_flow_control_loop_pipe_sequential_init.v

@@ -0,0 +1,107 @@
+// ==============================================================
+// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2024.1 (64-bit)
+// Tool Version Limit: 2024.05
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// 
+// ==============================================================
+
+`timescale 1 ns / 1 ps
+
+module myproject_flow_control_loop_pipe_sequential_init(
+        ap_clk,
+        ap_rst,
+        ap_start,
+        ap_ready,
+        ap_done,
+        ap_start_int,
+        ap_ready_int,
+        ap_done_int,
+        ap_continue_int,
+        ap_loop_init,
+        ap_loop_exit_ready,
+        ap_loop_exit_done
+);
+
+input   ap_clk;
+input   ap_rst;
+
+//Block level handshake with outside loop
+input   ap_start;
+output  ap_ready;
+output  ap_done;
+
+//Block level handshake with loop body
+output  ap_start_int;
+input   ap_ready_int;
+input   ap_done_int;
+output  ap_continue_int;
+
+//Init live in variables
+output   ap_loop_init;
+wire     ap_loop_init;
+reg ap_loop_init_int;
+reg ap_done;
+reg ap_done_cache;
+
+//Exit signal from loop body
+input   ap_loop_exit_ready;
+input   ap_loop_exit_done;
+
+// power-on initialization
+initial begin
+#0 ap_loop_init_int = 1'b1;
+#0 ap_done_cache = 1'b0;
+end
+
+assign ap_start_int = ap_start;
+
+assign ap_continue_int = 1'b1;
+
+assign ap_ready = ap_loop_exit_ready;
+
+//ap_loop_init is valid for the first II
+//of the first loop run so as to enable
+//the init block ops which are pushed into
+//the first state of the pipeline region
+always @ (posedge ap_clk)
+begin
+    if (ap_rst == 1'b1) begin
+        ap_loop_init_int <= 1'b1;
+    end else if(ap_loop_exit_done == 1'b1) begin
+        ap_loop_init_int <= 1'b1;
+    end else if(ap_ready_int == 1'b1) begin
+        ap_loop_init_int <= 1'b0;
+    end
+end
+
+assign ap_loop_init = ap_loop_init_int & ap_start;
+
+// if no ap_continue port and current module is not top module, 
+// ap_done handshakes with ap_start. Internally, flow control sends out 
+// ap_conintue_int = 1'b1 so the ap_done_int is asserted high for 1 clock cycle.
+// ap_done_cache is used to record ap_done_int, and de-assert if ap_start_int
+// is asserted, so DUT can start the next run
+always @(posedge ap_clk)
+begin
+    if (ap_rst == 1'b1) begin
+        ap_done_cache <= 1'b0;
+    end else if (ap_done_int == 1'b1) begin
+        ap_done_cache <= 1'b1;
+    end else if (ap_start_int == 1'b1) begin
+        ap_done_cache <= 1'b0;
+    end
+end
+
+// if no ap_continue port and current module is not top module, ap_done handshakes with ap_start
+always @(*)
+begin
+    if ((ap_done_int == 1'b1) || ((ap_done_cache == 1'b1) && (ap_start_int == 1'b0))) begin
+        ap_done = 1'b1;
+    end else begin
+        ap_done = 1'b0;
+    end
+end
+
+endmodule
+        

myproject_prj/solution1/syn/verilog/myproject_mac_muladd_16s_10s_33s_33_1_1.v

@@ -0,0 +1,66 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+//   
+//   
+//   
+`timescale 1 ns / 1 ps
+// 
+module myproject_mac_muladd_16s_10s_33s_33_1_1_DSP48_0(
+    input  [16 - 1:0] in0,
+    input  [10 - 1:0] in1,
+    input  [33 - 1:0] in2,
+    output [33 - 1:0]  dout);
+
+wire signed [27 - 1:0]     a;
+wire signed [18 - 1:0]     b;
+wire signed [48 - 1:0]     c;
+wire signed [45 - 1:0]     m;
+wire signed [48 - 1:0]     p;
+
+assign a  = $signed(in0);
+assign b  = $signed(in1);
+assign c  = $signed(in2);
+
+assign m  = a * b;
+// 
+assign p  = m + c;
+// 
+assign dout = p;
+
+endmodule
+// 
+
+module myproject_mac_muladd_16s_10s_33s_33_1_1(
+// 
+    din0,
+    din1,
+    din2,
+    dout);
+
+parameter ID = 32'd1;
+parameter NUM_STAGE = 32'd1;
+parameter din0_WIDTH = 32'd1;
+parameter din1_WIDTH = 32'd1;
+parameter din2_WIDTH = 32'd1;
+parameter dout_WIDTH = 32'd1;
+// 
+input[din0_WIDTH - 1:0] din0;
+input[din1_WIDTH - 1:0] din1;
+input[din2_WIDTH - 1:0] din2;
+output[dout_WIDTH - 1:0] dout;
+
+
+myproject_mac_muladd_16s_10s_33s_33_1_1_DSP48_0 myproject_mac_muladd_16s_10s_33s_33_1_1_DSP48_0_U(
+// 
+    .in0( din0 ),
+    .in1( din1 ),
+    .in2( din2 ),
+    .dout( dout ));
+
+endmodule
+
+

myproject_prj/solution1/syn/verilog/myproject_mac_muladd_16s_16s_33s_33_1_1.v

@@ -0,0 +1,66 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+//   
+//   
+//   
+`timescale 1 ns / 1 ps
+// 
+module myproject_mac_muladd_16s_16s_33s_33_1_1_DSP48_0(
+    input  [16 - 1:0] in0,
+    input  [16 - 1:0] in1,
+    input  [33 - 1:0] in2,
+    output [33 - 1:0]  dout);
+
+wire signed [27 - 1:0]     a;
+wire signed [18 - 1:0]     b;
+wire signed [48 - 1:0]     c;
+wire signed [45 - 1:0]     m;
+wire signed [48 - 1:0]     p;
+
+assign a  = $signed(in0);
+assign b  = $signed(in1);
+assign c  = $signed(in2);
+
+assign m  = a * b;
+// 
+assign p  = m + c;
+// 
+assign dout = p;
+
+endmodule
+// 
+
+module myproject_mac_muladd_16s_16s_33s_33_1_1(
+// 
+    din0,
+    din1,
+    din2,
+    dout);
+
+parameter ID = 32'd1;
+parameter NUM_STAGE = 32'd1;
+parameter din0_WIDTH = 32'd1;
+parameter din1_WIDTH = 32'd1;
+parameter din2_WIDTH = 32'd1;
+parameter dout_WIDTH = 32'd1;
+// 
+input[din0_WIDTH - 1:0] din0;
+input[din1_WIDTH - 1:0] din1;
+input[din2_WIDTH - 1:0] din2;
+output[dout_WIDTH - 1:0] dout;
+
+
+myproject_mac_muladd_16s_16s_33s_33_1_1_DSP48_0 myproject_mac_muladd_16s_16s_33s_33_1_1_DSP48_0_U(
+// 
+    .in0( din0 ),
+    .in1( din1 ),
+    .in2( din2 ),
+    .dout( dout ));
+
+endmodule
+
+

myproject_prj/solution1/syn/verilog/myproject_mac_muladd_16s_16s_40s_41_1_1.v

@@ -0,0 +1,66 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+//   
+//   
+//   
+`timescale 1 ns / 1 ps
+// 
+module myproject_mac_muladd_16s_16s_40s_41_1_1_DSP48_0(
+    input  [16 - 1:0] in0,
+    input  [16 - 1:0] in1,
+    input  [40 - 1:0] in2,
+    output [41 - 1:0]  dout);
+
+wire signed [27 - 1:0]     a;
+wire signed [18 - 1:0]     b;
+wire signed [48 - 1:0]     c;
+wire signed [45 - 1:0]     m;
+wire signed [48 - 1:0]     p;
+
+assign a  = $signed(in0);
+assign b  = $signed(in1);
+assign c  = $signed(in2);
+
+assign m  = a * b;
+// 
+assign p  = m + c;
+// 
+assign dout = p;
+
+endmodule
+// 
+
+module myproject_mac_muladd_16s_16s_40s_41_1_1(
+// 
+    din0,
+    din1,
+    din2,
+    dout);
+
+parameter ID = 32'd1;
+parameter NUM_STAGE = 32'd1;
+parameter din0_WIDTH = 32'd1;
+parameter din1_WIDTH = 32'd1;
+parameter din2_WIDTH = 32'd1;
+parameter dout_WIDTH = 32'd1;
+// 
+input[din0_WIDTH - 1:0] din0;
+input[din1_WIDTH - 1:0] din1;
+input[din2_WIDTH - 1:0] din2;
+output[dout_WIDTH - 1:0] dout;
+
+
+myproject_mac_muladd_16s_16s_40s_41_1_1_DSP48_0 myproject_mac_muladd_16s_16s_40s_41_1_1_DSP48_0_U(
+// 
+    .in0( din0 ),
+    .in1( din1 ),
+    .in2( din2 ),
+    .dout( dout ));
+
+endmodule
+
+

myproject_prj/solution1/syn/verilog/myproject_mac_muladd_16s_16s_41s_42_1_1.v

@@ -0,0 +1,66 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+//   
+//   
+//   
+`timescale 1 ns / 1 ps
+// 
+module myproject_mac_muladd_16s_16s_41s_42_1_1_DSP48_0(
+    input  [16 - 1:0] in0,
+    input  [16 - 1:0] in1,
+    input  [41 - 1:0] in2,
+    output [42 - 1:0]  dout);
+
+wire signed [27 - 1:0]     a;
+wire signed [18 - 1:0]     b;
+wire signed [48 - 1:0]     c;
+wire signed [45 - 1:0]     m;
+wire signed [48 - 1:0]     p;
+
+assign a  = $signed(in0);
+assign b  = $signed(in1);
+assign c  = $signed(in2);
+
+assign m  = a * b;
+// 
+assign p  = m + c;
+// 
+assign dout = p;
+
+endmodule
+// 
+
+module myproject_mac_muladd_16s_16s_41s_42_1_1(
+// 
+    din0,
+    din1,
+    din2,
+    dout);
+
+parameter ID = 32'd1;
+parameter NUM_STAGE = 32'd1;
+parameter din0_WIDTH = 32'd1;
+parameter din1_WIDTH = 32'd1;
+parameter din2_WIDTH = 32'd1;
+parameter dout_WIDTH = 32'd1;
+// 
+input[din0_WIDTH - 1:0] din0;
+input[din1_WIDTH - 1:0] din1;
+input[din2_WIDTH - 1:0] din2;
+output[dout_WIDTH - 1:0] dout;
+
+
+myproject_mac_muladd_16s_16s_41s_42_1_1_DSP48_0 myproject_mac_muladd_16s_16s_41s_42_1_1_DSP48_0_U(
+// 
+    .in0( din0 ),
+    .in1( din1 ),
+    .in2( din2 ),
+    .dout( dout ));
+
+endmodule
+
+

myproject_prj/solution1/syn/verilog/myproject_mac_muladd_16s_9s_31s_31_1_1.v

@@ -0,0 +1,66 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+//   
+//   
+//   
+`timescale 1 ns / 1 ps
+// 
+module myproject_mac_muladd_16s_9s_31s_31_1_1_DSP48_0(
+    input  [16 - 1:0] in0,
+    input  [9 - 1:0] in1,
+    input  [31 - 1:0] in2,
+    output [31 - 1:0]  dout);
+
+wire signed [27 - 1:0]     a;
+wire signed [18 - 1:0]     b;
+wire signed [48 - 1:0]     c;
+wire signed [45 - 1:0]     m;
+wire signed [48 - 1:0]     p;
+
+assign a  = $signed(in0);
+assign b  = $signed(in1);
+assign c  = $signed(in2);
+
+assign m  = a * b;
+// 
+assign p  = m + c;
+// 
+assign dout = p;
+
+endmodule
+// 
+
+module myproject_mac_muladd_16s_9s_31s_31_1_1(
+// 
+    din0,
+    din1,
+    din2,
+    dout);
+
+parameter ID = 32'd1;
+parameter NUM_STAGE = 32'd1;
+parameter din0_WIDTH = 32'd1;
+parameter din1_WIDTH = 32'd1;
+parameter din2_WIDTH = 32'd1;
+parameter dout_WIDTH = 32'd1;
+// 
+input[din0_WIDTH - 1:0] din0;
+input[din1_WIDTH - 1:0] din1;
+input[din2_WIDTH - 1:0] din2;
+output[dout_WIDTH - 1:0] dout;
+
+
+myproject_mac_muladd_16s_9s_31s_31_1_1_DSP48_0 myproject_mac_muladd_16s_9s_31s_31_1_1_DSP48_0_U(
+// 
+    .in0( din0 ),
+    .in1( din1 ),
+    .in2( din2 ),
+    .dout( dout ));
+
+endmodule
+
+

myproject_prj/solution1/syn/verilog/myproject_mac_muladd_16s_9s_34s_34_1_1.v

@@ -0,0 +1,66 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+//   
+//   
+//   
+`timescale 1 ns / 1 ps
+// 
+module myproject_mac_muladd_16s_9s_34s_34_1_1_DSP48_0(
+    input  [16 - 1:0] in0,
+    input  [9 - 1:0] in1,
+    input  [34 - 1:0] in2,
+    output [34 - 1:0]  dout);
+
+wire signed [27 - 1:0]     a;
+wire signed [18 - 1:0]     b;
+wire signed [48 - 1:0]     c;
+wire signed [45 - 1:0]     m;
+wire signed [48 - 1:0]     p;
+
+assign a  = $signed(in0);
+assign b  = $signed(in1);
+assign c  = $signed(in2);
+
+assign m  = a * b;
+// 
+assign p  = m + c;
+// 
+assign dout = p;
+
+endmodule
+// 
+
+module myproject_mac_muladd_16s_9s_34s_34_1_1(
+// 
+    din0,
+    din1,
+    din2,
+    dout);
+
+parameter ID = 32'd1;
+parameter NUM_STAGE = 32'd1;
+parameter din0_WIDTH = 32'd1;
+parameter din1_WIDTH = 32'd1;
+parameter din2_WIDTH = 32'd1;
+parameter dout_WIDTH = 32'd1;
+// 
+input[din0_WIDTH - 1:0] din0;
+input[din1_WIDTH - 1:0] din1;
+input[din2_WIDTH - 1:0] din2;
+output[dout_WIDTH - 1:0] dout;
+
+
+myproject_mac_muladd_16s_9s_34s_34_1_1_DSP48_0 myproject_mac_muladd_16s_9s_34s_34_1_1_DSP48_0_U(
+// 
+    .in0( din0 ),
+    .in1( din1 ),
+    .in2( din2 ),
+    .dout( dout ));
+
+endmodule
+
+

myproject_prj/solution1/syn/verilog/myproject_mac_muladd_16s_9s_41s_42_1_1.v

@@ -0,0 +1,66 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+//   
+//   
+//   
+`timescale 1 ns / 1 ps
+// 
+module myproject_mac_muladd_16s_9s_41s_42_1_1_DSP48_0(
+    input  [16 - 1:0] in0,
+    input  [9 - 1:0] in1,
+    input  [41 - 1:0] in2,
+    output [42 - 1:0]  dout);
+
+wire signed [27 - 1:0]     a;
+wire signed [18 - 1:0]     b;
+wire signed [48 - 1:0]     c;
+wire signed [45 - 1:0]     m;
+wire signed [48 - 1:0]     p;
+
+assign a  = $signed(in0);
+assign b  = $signed(in1);
+assign c  = $signed(in2);
+
+assign m  = a * b;
+// 
+assign p  = m + c;
+// 
+assign dout = p;
+
+endmodule
+// 
+
+module myproject_mac_muladd_16s_9s_41s_42_1_1(
+// 
+    din0,
+    din1,
+    din2,
+    dout);
+
+parameter ID = 32'd1;
+parameter NUM_STAGE = 32'd1;
+parameter din0_WIDTH = 32'd1;
+parameter din1_WIDTH = 32'd1;
+parameter din2_WIDTH = 32'd1;
+parameter dout_WIDTH = 32'd1;
+// 
+input[din0_WIDTH - 1:0] din0;
+input[din1_WIDTH - 1:0] din1;
+input[din2_WIDTH - 1:0] din2;
+output[dout_WIDTH - 1:0] dout;
+
+
+myproject_mac_muladd_16s_9s_41s_42_1_1_DSP48_0 myproject_mac_muladd_16s_9s_41s_42_1_1_DSP48_0_U(
+// 
+    .in0( din0 ),
+    .in1( din1 ),
+    .in2( din2 ),
+    .dout( dout ));
+
+endmodule
+
+

myproject_prj/solution1/syn/verilog/myproject_mac_muladd_16s_9s_43s_44_1_1.v

@@ -0,0 +1,66 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+//   
+//   
+//   
+`timescale 1 ns / 1 ps
+// 
+module myproject_mac_muladd_16s_9s_43s_44_1_1_DSP48_0(
+    input  [16 - 1:0] in0,
+    input  [9 - 1:0] in1,
+    input  [43 - 1:0] in2,
+    output [44 - 1:0]  dout);
+
+wire signed [27 - 1:0]     a;
+wire signed [18 - 1:0]     b;
+wire signed [48 - 1:0]     c;
+wire signed [45 - 1:0]     m;
+wire signed [48 - 1:0]     p;
+
+assign a  = $signed(in0);
+assign b  = $signed(in1);
+assign c  = $signed(in2);
+
+assign m  = a * b;
+// 
+assign p  = m + c;
+// 
+assign dout = p;
+
+endmodule
+// 
+
+module myproject_mac_muladd_16s_9s_43s_44_1_1(
+// 
+    din0,
+    din1,
+    din2,
+    dout);
+
+parameter ID = 32'd1;
+parameter NUM_STAGE = 32'd1;
+parameter din0_WIDTH = 32'd1;
+parameter din1_WIDTH = 32'd1;
+parameter din2_WIDTH = 32'd1;
+parameter dout_WIDTH = 32'd1;
+// 
+input[din0_WIDTH - 1:0] din0;
+input[din1_WIDTH - 1:0] din1;
+input[din2_WIDTH - 1:0] din2;
+output[dout_WIDTH - 1:0] dout;
+
+
+myproject_mac_muladd_16s_9s_43s_44_1_1_DSP48_0 myproject_mac_muladd_16s_9s_43s_44_1_1_DSP48_0_U(
+// 
+    .in0( din0 ),
+    .in1( din1 ),
+    .in2( din2 ),
+    .dout( dout ));
+
+endmodule
+
+

myproject_prj/solution1/syn/verilog/myproject_mul_16s_16s_32_1_1.v

@@ -0,0 +1,75 @@
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1 ns / 1 ps
+
+ module myproject_mul_16s_16s_32_1_1(din0, din1, dout);
+parameter ID = 1;
+parameter NUM_STAGE = 0;
+parameter din0_WIDTH = 14;
+parameter din1_WIDTH = 12;
+parameter dout_WIDTH = 26;
+
+input [din0_WIDTH - 1 : 0] din0; 
+input [din1_WIDTH - 1 : 0] din1; 
+output [dout_WIDTH - 1 : 0] dout;
+
+wire signed [dout_WIDTH - 1 : 0] tmp_product;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+assign tmp_product = $signed(din0) * $signed(din1);
+
+
+
+
+
+
+
+
+assign dout = tmp_product;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+endmodule