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myproject_prj/solution1/.autopilot/.autopilot_exit

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+21:51:13
+04/05/2026

myproject_prj/solution1/.autopilot/db/compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s.verbose.rpt.xml

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+<profile>
+
+<section name = "Vitis HLS Report for 'compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s'" level="0">
+<item name = "Date">Sun Apr  5 21:50:00 2026
+</item>
+<item name = "Version">2024.1 (Build 5069499 on May 21 2024)</item>
+<item name = "Project">myproject_prj</item>
+<item name = "Solution">solution1 (Vivado IP Flow Target)</item>
+<item name = "Product family">virtexuplusHBM</item>
+<item name = "Target device">xcvu47p-fsvh2892-2L-e</item>
+</section>
+
+<section name = "Performance Estimates" level="0">
+<item name = "Timing">
+<section name = "" level="1">
+<item name = "Summary"><table name="" hasTotal="0">
+<keys size="4">Clock, Target, Estimated, Uncertainty</keys>
+<column name="ap_clk">4.00 ns, 2.533 ns, 1.35 ns</column>
+</table>
+</item>
+</section>
+</item>
+<item name = "Latency">
+<section name = "" level="1">
+<item name = "Summary"><table name="" hasTotal="0">
+<keys size="8">, min, max, min, max, min, max, Type</keys>
+<column name="">2, 437, 8.000 ns, 1.748 us, 2, 437, no</column>
+</table>
+</item>
+<item name = "Detail">
+<section name = "" level="1">
+<item name = "Instance"><table name="" hasTotal="0">
+<keys size="9">Instance, Module, min, max, min, max, min, max, Type</keys>
+<column name="call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_fu_1501">shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s, 0, 0, 0 ns, 0 ns, 1, 1, yes</column>
+<column name="grp_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s_fu_2657">dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s, 433, 434, 1.732 us, 1.736 us, 432, 432, loop rewind stp(delay=0 clock cycles(s))</column>
+</table>
+</item>
+<item name = "Loop"><table name="" hasTotal="0">
+<keys size="8">Loop Name, min, max, Latency, achieved, target, Count, Pipelined</keys>
+</table>
+</item>
+</section>
+</item>
+</section>
+</item>
+</section>
+
+<section name = "Utilization Estimates" level="0">
+<item name = "Summary"><table name="" hasTotal="1">
+<keys size="6">Name, BRAM_18K, DSP, FF, LUT, URAM</keys>
+<column name="DSP">-, -, -, -, -</column>
+<column name="Expression">-, -, 0, 501, -</column>
+<column name="FIFO">-, -, -, -, -</column>
+<column name="Instance">8, 16, 21568, 20130, -</column>
+<column name="Memory">-, -, -, -, -</column>
+<column name="Multiplexer">-, -, 0, 76, -</column>
+<column name="Register">-, -, 7719, -, -</column>
+<specialColumn name="Available SLR">1344, 3008, 869120, 434560, 320</specialColumn>
+<specialColumn name="Utilization SLR (%)">~0, ~0, 3, 4, 0</specialColumn>
+<specialColumn name="Available">4032, 9024, 2607360, 1303680, 960</specialColumn>
+<specialColumn name="Utilization (%)">~0, ~0, 1, 1, 0</specialColumn>
+</table>
+</item>
+<item name = "Detail">
+<section name = "" level="1">
+<item name = "Instance"><table name="" hasTotal="1">
+<keys size="7">Instance, Module, BRAM_18K, DSP, FF, LUT, URAM</keys>
+<column name="grp_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s_fu_2657">dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s, 8, 16, 15423, 14466, 0</column>
+<column name="call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_fu_1501">shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s, 0, 0, 6145, 5664, 0</column>
+</table>
+</item>
+<item name = "DSP"><table name="" hasTotal="0">
+<keys size="3">Instance, Module, Expression</keys>
+</table>
+</item>
+<item name = "Memory"><table name="" hasTotal="1">
+<keys size="10">Memory, Module, BRAM_18K, FF, LUT, URAM, Words, Bits, Banks, W*Bits*Banks</keys>
+</table>
+</item>
+<item name = "FIFO"><table name="" hasTotal="1">
+<keys size="8">Name, BRAM_18K, FF, LUT, URAM, Depth, Bits, Size:D*B</keys>
+</table>
+</item>
+<item name = "Expression"><table name="" hasTotal="1">
+<keys size="7">Variable Name, Operation, DSP, FF, LUT, Bitwidth P0, Bitwidth P1</keys>
+<column name="add_ln303_fu_3684_p2">+, 0, 0, 39, 32, 1</column>
+<column name="add_ln307_fu_3731_p2">+, 0, 0, 39, 32, 1</column>
+<column name="add_ln313_fu_3753_p2">+, 0, 0, 39, 32, 1</column>
+<column name="add_ln318_fu_3701_p2">+, 0, 0, 39, 32, 1</column>
+<column name="and_ln284_5_fu_3593_p2">and, 0, 0, 2, 1, 1</column>
+<column name="and_ln284_fu_3587_p2">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_state4">and, 0, 0, 2, 1, 1</column>
+<column name="ap_condition_3183">and, 0, 0, 2, 1, 1</column>
+<column name="ap_predicate_op88_write_state4">and, 0, 0, 2, 1, 1</column>
+<column name="icmp_ln284_13_fu_3549_p2">icmp, 0, 0, 39, 32, 2</column>
+<column name="icmp_ln284_14_fu_3565_p2">icmp, 0, 0, 38, 31, 1</column>
+<column name="icmp_ln284_15_fu_3581_p2">icmp, 0, 0, 38, 31, 1</column>
+<column name="icmp_ln284_fu_3531_p2">icmp, 0, 0, 39, 32, 2</column>
+<column name="icmp_ln303_fu_3689_p2">icmp, 0, 0, 39, 32, 6</column>
+<column name="icmp_ln307_fu_3736_p2">icmp, 0, 0, 39, 32, 6</column>
+<column name="icmp_ln313_fu_3748_p2">icmp, 0, 0, 39, 32, 2</column>
+<column name="select_ln313_fu_3758_p3">select, 0, 0, 32, 1, 2</column>
+<column name="select_ln318_fu_3706_p3">select, 0, 0, 32, 1, 2</column>
+</table>
+</item>
+<item name = "Multiplexer"><table name="" hasTotal="1">
+<keys size="5">Name, LUT, Input Size, Bits, Total Bits</keys>
+<column name="ap_NS_fsm">26, 5, 1, 5</column>
+<column name="ap_phi_mux_storemerge_phi_fu_1494_p4">14, 3, 32, 96</column>
+<column name="layer29_out_blk_n">9, 2, 1, 2</column>
+<column name="pX_1">9, 2, 32, 64</column>
+<column name="pY_1">9, 2, 32, 64</column>
+<column name="sX_1">9, 2, 32, 64</column>
+</table>
+</item>
+<item name = "Register"><table name="" hasTotal="1">
+<keys size="5">Name, FF, LUT, Bits, Const Bits</keys>
+<column name="and_ln284_5_reg_3796">1, 0, 1, 0</column>
+<column name="ap_CS_fsm">4, 0, 4, 0</column>
+<column name="grp_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s_fu_2657_ap_start_reg">1, 0, 1, 0</column>
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+<column name="pY_1">32, 0, 32, 0</column>
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+<column name="p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6160">16, 0, 16, 0</column>
+<column name="p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6161">16, 0, 16, 0</column>
+<column name="p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6162">16, 0, 16, 0</column>
+<column name="p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6163">16, 0, 16, 0</column>
+<column name="p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6164">16, 0, 16, 0</column>
+<column name="p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6165">16, 0, 16, 0</column>
+<column name="p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6166">16, 0, 16, 0</column>
+<column name="p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6168">16, 0, 16, 0</column>
+<column name="p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6169">16, 0, 16, 0</column>
+<column name="p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6170">16, 0, 16, 0</column>
+<column name="p_ZZN4nnet24compute_output_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9_6171">16, 0, 16, 0</column>
+<column name="res_out_184_reg_3850">42, 0, 42, 0</column>
+<column name="res_out_185_reg_3855">42, 0, 42, 0</column>
+<column name="res_out_186_reg_3860">42, 0, 42, 0</column>
+<column name="res_out_187_reg_3865">42, 0, 42, 0</column>
+<column name="res_out_188_reg_3870">42, 0, 42, 0</column>
+<column name="res_out_189_reg_3875">42, 0, 42, 0</column>
+<column name="res_out_1_reg_3805">42, 0, 42, 0</column>
+<column name="res_out_2_reg_3810">42, 0, 42, 0</column>
+<column name="res_out_3_reg_3815">42, 0, 42, 0</column>
+<column name="res_out_4_reg_3820">42, 0, 42, 0</column>
+<column name="res_out_5_reg_3825">42, 0, 42, 0</column>
+<column name="res_out_6_reg_3830">42, 0, 42, 0</column>
+<column name="res_out_7_reg_3835">42, 0, 42, 0</column>
+<column name="res_out_8_reg_3840">42, 0, 42, 0</column>
+<column name="res_out_9_reg_3845">42, 0, 42, 0</column>
+<column name="res_out_reg_3800">42, 0, 42, 0</column>
+<column name="sX_1">32, 0, 32, 0</column>
+<column name="sY_1">32, 0, 32, 0</column>
+<column name="void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_50">16, 0, 16, 0</column>
+<column name="void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_51">16, 0, 16, 0</column>
+<column name="void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_52">16, 0, 16, 0</column>
+<column name="void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_53">16, 0, 16, 0</column>
+<column name="void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_54">16, 0, 16, 0</column>
+<column name="void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_55">16, 0, 16, 0</column>
+<column name="void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_56">16, 0, 16, 0</column>
+<column name="void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_57">16, 0, 16, 0</column>
+<column name="void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_58">16, 0, 16, 0</column>
+<column name="void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_59">16, 0, 16, 0</column>
+</table>
+</item>
+</section>
+</item>
+</section>
+
+<section name = "Interface" level="0">
+<item name = "Summary"><table name="" hasTotal="0">
+<keys size="6">RTL Ports, Dir, Bits, Protocol, Source Object, C Type</keys>
+<column name="ap_clk">in, 1, ap_ctrl_hs, compute_output_buffer_2d&lt;array,array&lt;ap_fixed&lt;42,22,5,3,0&gt;,16u&gt;,config29&gt;, return value</column>
+<column name="ap_rst">in, 1, ap_ctrl_hs, compute_output_buffer_2d&lt;array,array&lt;ap_fixed&lt;42,22,5,3,0&gt;,16u&gt;,config29&gt;, return value</column>
+<column name="ap_start">in, 1, ap_ctrl_hs, compute_output_buffer_2d&lt;array,array&lt;ap_fixed&lt;42,22,5,3,0&gt;,16u&gt;,config29&gt;, return value</column>
+<column name="ap_done">out, 1, ap_ctrl_hs, compute_output_buffer_2d&lt;array,array&lt;ap_fixed&lt;42,22,5,3,0&gt;,16u&gt;,config29&gt;, return value</column>
+<column name="ap_idle">out, 1, ap_ctrl_hs, compute_output_buffer_2d&lt;array,array&lt;ap_fixed&lt;42,22,5,3,0&gt;,16u&gt;,config29&gt;, return value</column>
+<column name="ap_ready">out, 1, ap_ctrl_hs, compute_output_buffer_2d&lt;array,array&lt;ap_fixed&lt;42,22,5,3,0&gt;,16u&gt;,config29&gt;, return value</column>
+<column name="p_read">in, 16, ap_none, p_read, scalar</column>
+<column name="p_read1">in, 16, ap_none, p_read1, scalar</column>
+<column name="p_read2">in, 16, ap_none, p_read2, scalar</column>
+<column name="p_read3">in, 16, ap_none, p_read3, scalar</column>
+<column name="p_read4">in, 16, ap_none, p_read4, scalar</column>
+<column name="p_read5">in, 16, ap_none, p_read5, scalar</column>
+<column name="p_read6">in, 16, ap_none, p_read6, scalar</column>
+<column name="p_read7">in, 16, ap_none, p_read7, scalar</column>
+<column name="p_read8">in, 16, ap_none, p_read8, scalar</column>
+<column name="p_read9">in, 16, ap_none, p_read9, scalar</column>
+<column name="p_read10">in, 16, ap_none, p_read10, scalar</column>
+<column name="p_read11">in, 16, ap_none, p_read11, scalar</column>
+<column name="p_read12">in, 16, ap_none, p_read12, scalar</column>
+<column name="p_read13">in, 16, ap_none, p_read13, scalar</column>
+<column name="p_read14">in, 16, ap_none, p_read14, scalar</column>
+<column name="p_read15">in, 16, ap_none, p_read15, scalar</column>
+<column name="p_read16">in, 16, ap_none, p_read16, scalar</column>
+<column name="p_read17">in, 16, ap_none, p_read17, scalar</column>
+<column name="p_read18">in, 16, ap_none, p_read18, scalar</column>
+<column name="p_read19">in, 16, ap_none, p_read19, scalar</column>
+<column name="p_read20">in, 16, ap_none, p_read20, scalar</column>
+<column name="p_read21">in, 16, ap_none, p_read21, scalar</column>
+<column name="p_read22">in, 16, ap_none, p_read22, scalar</column>
+<column name="p_read23">in, 16, ap_none, p_read23, scalar</column>
+<column name="p_read24">in, 16, ap_none, p_read24, scalar</column>
+<column name="p_read25">in, 16, ap_none, p_read25, scalar</column>
+<column name="p_read26">in, 16, ap_none, p_read26, scalar</column>
+<column name="p_read27">in, 16, ap_none, p_read27, scalar</column>
+<column name="p_read28">in, 16, ap_none, p_read28, scalar</column>
+<column name="p_read29">in, 16, ap_none, p_read29, scalar</column>
+<column name="p_read30">in, 16, ap_none, p_read30, scalar</column>
+<column name="p_read31">in, 16, ap_none, p_read31, scalar</column>
+<column name="p_read32">in, 16, ap_none, p_read32, scalar</column>
+<column name="p_read33">in, 16, ap_none, p_read33, scalar</column>
+<column name="p_read34">in, 16, ap_none, p_read34, scalar</column>
+<column name="p_read35">in, 16, ap_none, p_read35, scalar</column>
+<column name="p_read36">in, 16, ap_none, p_read36, scalar</column>
+<column name="p_read37">in, 16, ap_none, p_read37, scalar</column>
+<column name="p_read38">in, 16, ap_none, p_read38, scalar</column>
+<column name="p_read39">in, 16, ap_none, p_read39, scalar</column>
+<column name="p_read40">in, 16, ap_none, p_read40, scalar</column>
+<column name="p_read41">in, 16, ap_none, p_read41, scalar</column>
+<column name="p_read42">in, 16, ap_none, p_read42, scalar</column>
+<column name="p_read43">in, 16, ap_none, p_read43, scalar</column>
+<column name="p_read44">in, 16, ap_none, p_read44, scalar</column>
+<column name="p_read45">in, 16, ap_none, p_read45, scalar</column>
+<column name="p_read46">in, 16, ap_none, p_read46, scalar</column>
+<column name="p_read47">in, 16, ap_none, p_read47, scalar</column>
+<column name="layer29_out_din">out, 672, ap_fifo, layer29_out, pointer</column>
+<column name="layer29_out_num_data_valid">in, 11, ap_fifo, layer29_out, pointer</column>
+<column name="layer29_out_fifo_cap">in, 11, ap_fifo, layer29_out, pointer</column>
+<column name="layer29_out_full_n">in, 1, ap_fifo, layer29_out, pointer</column>
+<column name="layer29_out_write">out, 1, ap_fifo, layer29_out, pointer</column>
+</table>
+</item>
+</section>
+</profile>

myproject_prj/solution1/.autopilot/db/conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_s.compgen.tcl

@@ -0,0 +1,103 @@
+# This script segment is generated automatically by AutoPilot
+
+# clear list
+if {${::AESL::PGuard_autoexp_gen}} {
+    cg_default_interface_gen_dc_begin
+    cg_default_interface_gen_bundle_begin
+    AESL_LIB_XILADAPTER::native_axis_begin
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 38 \
+    name layer44_out \
+    type fifo \
+    dir I \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_layer44_out \
+    op interface \
+    ports { layer44_out_dout { I 16 vector } layer44_out_num_data_valid { I 14 vector } layer44_out_fifo_cap { I 14 vector } layer44_out_empty_n { I 1 bit } layer44_out_read { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 39 \
+    name layer2_out \
+    type fifo \
+    dir O \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_layer2_out \
+    op interface \
+    ports { layer2_out_din { O 296 vector } layer2_out_num_data_valid { I 13 vector } layer2_out_fifo_cap { I 13 vector } layer2_out_full_n { I 1 bit } layer2_out_write { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id -1 \
+    name ap_ctrl \
+    type ap_ctrl \
+    reset_level 1 \
+    sync_rst true \
+    corename ap_ctrl \
+    op interface \
+    ports { ap_start { I 1 bit } ap_ready { O 1 bit } ap_done { O 1 bit } ap_idle { O 1 bit } ap_continue { I 1 bit } } \
+} "
+}
+
+
+# Adapter definition:
+set PortName ap_clk
+set DataWd 1 
+if {${::AESL::PGuard_autoexp_gen}} {
+if {[info proc cg_default_interface_gen_clock] == "cg_default_interface_gen_clock"} {
+eval "cg_default_interface_gen_clock { \
+    id -2 \
+    name ${PortName} \
+    reset_level 1 \
+    sync_rst true \
+    corename apif_ap_clk \
+    data_wd ${DataWd} \
+    op interface \
+}"
+} else {
+puts "@W \[IMPL-113\] Cannot find bus interface model in the library. Ignored generation of bus interface for '${PortName}'"
+}
+}
+
+
+# Adapter definition:
+set PortName ap_rst
+set DataWd 1 
+if {${::AESL::PGuard_autoexp_gen}} {
+if {[info proc cg_default_interface_gen_reset] == "cg_default_interface_gen_reset"} {
+eval "cg_default_interface_gen_reset { \
+    id -3 \
+    name ${PortName} \
+    reset_level 1 \
+    sync_rst true \
+    corename apif_ap_rst \
+    data_wd ${DataWd} \
+    op interface \
+}"
+} else {
+puts "@W \[IMPL-114\] Cannot find bus interface model in the library. Ignored generation of bus interface for '${PortName}'"
+}
+}
+
+
+
+# merge
+if {${::AESL::PGuard_autoexp_gen}} {
+    cg_default_interface_gen_dc_end
+    cg_default_interface_gen_bundle_end
+    AESL_LIB_XILADAPTER::native_axis_end
+}
+
+

myproject_prj/solution1/.autopilot/db/conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_s.compgen.tcl

@@ -0,0 +1,103 @@
+# This script segment is generated automatically by AutoPilot
+
+# clear list
+if {${::AESL::PGuard_autoexp_gen}} {
+    cg_default_interface_gen_dc_begin
+    cg_default_interface_gen_bundle_begin
+    AESL_LIB_XILADAPTER::native_axis_begin
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 1913 \
+    name layer49_out \
+    type fifo \
+    dir I \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_layer49_out \
+    op interface \
+    ports { layer49_out_dout { I 512 vector } layer49_out_num_data_valid { I 10 vector } layer49_out_fifo_cap { I 10 vector } layer49_out_empty_n { I 1 bit } layer49_out_read { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 1914 \
+    name layer14_out \
+    type fifo \
+    dir O \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_layer14_out \
+    op interface \
+    ports { layer14_out_din { O 1344 vector } layer14_out_num_data_valid { I 9 vector } layer14_out_fifo_cap { I 9 vector } layer14_out_full_n { I 1 bit } layer14_out_write { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id -1 \
+    name ap_ctrl \
+    type ap_ctrl \
+    reset_level 1 \
+    sync_rst true \
+    corename ap_ctrl \
+    op interface \
+    ports { ap_start { I 1 bit } ap_ready { O 1 bit } ap_done { O 1 bit } ap_idle { O 1 bit } ap_continue { I 1 bit } } \
+} "
+}
+
+
+# Adapter definition:
+set PortName ap_clk
+set DataWd 1 
+if {${::AESL::PGuard_autoexp_gen}} {
+if {[info proc cg_default_interface_gen_clock] == "cg_default_interface_gen_clock"} {
+eval "cg_default_interface_gen_clock { \
+    id -2 \
+    name ${PortName} \
+    reset_level 1 \
+    sync_rst true \
+    corename apif_ap_clk \
+    data_wd ${DataWd} \
+    op interface \
+}"
+} else {
+puts "@W \[IMPL-113\] Cannot find bus interface model in the library. Ignored generation of bus interface for '${PortName}'"
+}
+}
+
+
+# Adapter definition:
+set PortName ap_rst
+set DataWd 1 
+if {${::AESL::PGuard_autoexp_gen}} {
+if {[info proc cg_default_interface_gen_reset] == "cg_default_interface_gen_reset"} {
+eval "cg_default_interface_gen_reset { \
+    id -3 \
+    name ${PortName} \
+    reset_level 1 \
+    sync_rst true \
+    corename apif_ap_rst \
+    data_wd ${DataWd} \
+    op interface \
+}"
+} else {
+puts "@W \[IMPL-114\] Cannot find bus interface model in the library. Ignored generation of bus interface for '${PortName}'"
+}
+}
+
+
+
+# merge
+if {${::AESL::PGuard_autoexp_gen}} {
+    cg_default_interface_gen_dc_end
+    cg_default_interface_gen_bundle_end
+    AESL_LIB_XILADAPTER::native_axis_end
+}
+
+

myproject_prj/solution1/.autopilot/db/relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_s.compgen.dataonly.tcl

@@ -0,0 +1,2 @@
+# This script segment is generated automatically by AutoPilot
+

myproject_prj/solution1/.autopilot/db/shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s.compgen.tcl

@@ -0,0 +1,1298 @@
+# This script segment is generated automatically by AutoPilot
+
+if {${::AESL::PGuard_rtl_comp_handler}} {
+	::AP::rtl_comp_handler myproject_shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_void_pooling2d_cl_bun BINDTYPE {storage} TYPE {shiftreg} IMPL {auto} LATENCY 1 ALLOW_PRAGMA 1
+}
+
+
+# clear list
+if {${::AESL::PGuard_autoexp_gen}} {
+    cg_default_interface_gen_dc_begin
+    cg_default_interface_gen_bundle_begin
+    AESL_LIB_XILADAPTER::native_axis_begin
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 808 \
+    name p_read \
+    type other \
+    dir I \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_read \
+    op interface \
+    ports { p_read { I 16 vector } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 809 \
+    name p_read1 \
+    type other \
+    dir I \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_read1 \
+    op interface \
+    ports { p_read1 { I 16 vector } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 810 \
+    name p_read2 \
+    type other \
+    dir I \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_read2 \
+    op interface \
+    ports { p_read2 { I 16 vector } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 811 \
+    name p_read3 \
+    type other \
+    dir I \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_read3 \
+    op interface \
+    ports { p_read3 { I 16 vector } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 812 \
+    name p_read4 \
+    type other \
+    dir I \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_read4 \
+    op interface \
+    ports { p_read4 { I 16 vector } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 813 \
+    name p_read5 \
+    type other \
+    dir I \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_read5 \
+    op interface \
+    ports { p_read5 { I 16 vector } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 814 \
+    name p_read6 \
+    type other \
+    dir I \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_read6 \
+    op interface \
+    ports { p_read6 { I 16 vector } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 815 \
+    name p_read7 \
+    type other \
+    dir I \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_read7 \
+    op interface \
+    ports { p_read7 { I 16 vector } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 816 \
+    name p_read8 \
+    type other \
+    dir I \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_read8 \
+    op interface \
+    ports { p_read8 { I 16 vector } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 817 \
+    name p_read9 \
+    type other \
+    dir I \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_read9 \
+    op interface \
+    ports { p_read9 { I 16 vector } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 818 \
+    name p_read10 \
+    type other \
+    dir I \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_read10 \
+    op interface \
+    ports { p_read10 { I 16 vector } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 819 \
+    name p_read11 \
+    type other \
+    dir I \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_read11 \
+    op interface \
+    ports { p_read11 { I 16 vector } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 820 \
+    name p_read12 \
+    type other \
+    dir I \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_read12 \
+    op interface \
+    ports { p_read12 { I 16 vector } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 821 \
+    name p_read13 \
+    type other \
+    dir I \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_read13 \
+    op interface \
+    ports { p_read13 { I 16 vector } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 822 \
+    name p_read14 \
+    type other \
+    dir I \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_read14 \
+    op interface \
+    ports { p_read14 { I 16 vector } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 823 \
+    name p_read15 \
+    type other \
+    dir I \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_read15 \
+    op interface \
+    ports { p_read15 { I 16 vector } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 824 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_199 \
+    type other \
+    dir IO \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_199 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_199_i { I 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_199_o { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_199_o_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 825 \
+    name void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_20 \
+    type other \
+    dir O \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_20 \
+    op interface \
+    ports { void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_20 { O 16 vector } void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_20_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 826 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_200 \
+    type other \
+    dir IO \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_200 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_200_i { I 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_200_o { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_200_o_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 827 \
+    name void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_21 \
+    type other \
+    dir O \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_21 \
+    op interface \
+    ports { void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_21 { O 16 vector } void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_21_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 828 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_201 \
+    type other \
+    dir IO \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_201 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_201_i { I 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_201_o { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_201_o_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 829 \
+    name void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_22 \
+    type other \
+    dir O \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_22 \
+    op interface \
+    ports { void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_22 { O 16 vector } void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_22_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 830 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_202 \
+    type other \
+    dir IO \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_202 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_202_i { I 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_202_o { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_202_o_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 831 \
+    name void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_23 \
+    type other \
+    dir O \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_23 \
+    op interface \
+    ports { void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_23 { O 16 vector } void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_23_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 832 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_203 \
+    type other \
+    dir IO \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_203 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_203_i { I 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_203_o { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_203_o_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 833 \
+    name void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_24 \
+    type other \
+    dir O \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_24 \
+    op interface \
+    ports { void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_24 { O 16 vector } void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_24_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 834 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_204 \
+    type other \
+    dir IO \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_204 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_204_i { I 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_204_o { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_204_o_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 835 \
+    name void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_25 \
+    type other \
+    dir O \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_25 \
+    op interface \
+    ports { void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_25 { O 16 vector } void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_25_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 836 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_205 \
+    type other \
+    dir IO \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_205 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_205_i { I 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_205_o { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_205_o_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 837 \
+    name void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_26 \
+    type other \
+    dir O \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_26 \
+    op interface \
+    ports { void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_26 { O 16 vector } void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_26_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 838 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_206 \
+    type other \
+    dir IO \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_206 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_206_i { I 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_206_o { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_206_o_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 839 \
+    name void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_27 \
+    type other \
+    dir O \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_27 \
+    op interface \
+    ports { void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_27 { O 16 vector } void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_27_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 840 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_207 \
+    type other \
+    dir IO \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_207 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_207_i { I 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_207_o { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_207_o_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 841 \
+    name void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_28 \
+    type other \
+    dir O \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_28 \
+    op interface \
+    ports { void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_28 { O 16 vector } void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_28_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 842 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_208 \
+    type other \
+    dir IO \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_208 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_208_i { I 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_208_o { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_208_o_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 843 \
+    name void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_29 \
+    type other \
+    dir O \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_29 \
+    op interface \
+    ports { void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_29 { O 16 vector } void_compute_pool_buffer_2d_array_const_ap_shift_reg_n_filt_stream_kernel_29_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 844 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_209 \
+    type other \
+    dir IO \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_209 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_209_i { I 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_209_o { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_209_o_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 845 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_193 \
+    type other \
+    dir O \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_193 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_193 { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_193_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 846 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_210 \
+    type other \
+    dir IO \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_210 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_210_i { I 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_210_o { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_210_o_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 847 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_194 \
+    type other \
+    dir O \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_194 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_194 { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_194_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 848 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_211 \
+    type other \
+    dir IO \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_211 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_211_i { I 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_211_o { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_211_o_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 849 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_195 \
+    type other \
+    dir O \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_195 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_195 { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_195_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 850 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_212 \
+    type other \
+    dir IO \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_212 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_212_i { I 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_212_o { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_212_o_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 851 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_196 \
+    type other \
+    dir O \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_196 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_196 { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_196_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 852 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_213 \
+    type other \
+    dir IO \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_213 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_213_i { I 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_213_o { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_213_o_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 853 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_197 \
+    type other \
+    dir O \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_197 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_197 { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_197_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 854 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_214 \
+    type other \
+    dir IO \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_214 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_214_i { I 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_214_o { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_214_o_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 855 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_198 \
+    type other \
+    dir O \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_198 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_198 { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_198_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 856 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_231 \
+    type other \
+    dir IO \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_231 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_231_i { I 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_231_o { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_231_o_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 857 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_215 \
+    type other \
+    dir O \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_215 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_215 { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_215_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 858 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_232 \
+    type other \
+    dir IO \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_232 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_232_i { I 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_232_o { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_232_o_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 859 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_216 \
+    type other \
+    dir O \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_216 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_216 { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_216_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 860 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_233 \
+    type other \
+    dir IO \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_233 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_233_i { I 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_233_o { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_233_o_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 861 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_217 \
+    type other \
+    dir O \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_217 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_217 { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_217_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 862 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_234 \
+    type other \
+    dir IO \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_234 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_234_i { I 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_234_o { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_234_o_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 863 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_218 \
+    type other \
+    dir O \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_218 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_218 { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_218_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 864 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_235 \
+    type other \
+    dir IO \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_235 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_235_i { I 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_235_o { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_235_o_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 865 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_219 \
+    type other \
+    dir O \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_219 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_219 { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_219_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 866 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_236 \
+    type other \
+    dir IO \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_236 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_236_i { I 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_236_o { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_236_o_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 867 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_220 \
+    type other \
+    dir O \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_220 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_220 { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_220_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 868 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_237 \
+    type other \
+    dir IO \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_237 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_237_i { I 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_237_o { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_237_o_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 869 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_221 \
+    type other \
+    dir O \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_221 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_221 { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_221_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 870 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_238 \
+    type other \
+    dir IO \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_238 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_238_i { I 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_238_o { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_238_o_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 871 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_222 \
+    type other \
+    dir O \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_222 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_222 { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_222_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 872 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_239 \
+    type other \
+    dir IO \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_239 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_239_i { I 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_239_o { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_239_o_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 873 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_223 \
+    type other \
+    dir O \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_223 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_223 { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_223_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 874 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_240 \
+    type other \
+    dir IO \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_240 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_240_i { I 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_240_o { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_240_o_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 875 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_224 \
+    type other \
+    dir O \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_224 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_224 { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_224_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 876 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_241 \
+    type other \
+    dir IO \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_241 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_241_i { I 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_241_o { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_241_o_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 877 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_225 \
+    type other \
+    dir O \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_225 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_225 { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_225_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 878 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_242 \
+    type other \
+    dir IO \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_242 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_242_i { I 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_242_o { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_242_o_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 879 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_226 \
+    type other \
+    dir O \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_226 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_226 { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_226_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 880 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_243 \
+    type other \
+    dir IO \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_243 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_243_i { I 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_243_o { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_243_o_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 881 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_227 \
+    type other \
+    dir O \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_227 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_227 { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_227_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 882 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_244 \
+    type other \
+    dir IO \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_244 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_244_i { I 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_244_o { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_244_o_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 883 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_228 \
+    type other \
+    dir O \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_228 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_228 { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_228_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 884 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_245 \
+    type other \
+    dir IO \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_245 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_245_i { I 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_245_o { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_245_o_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 885 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_229 \
+    type other \
+    dir O \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_229 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_229 { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_229_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 886 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_246 \
+    type other \
+    dir IO \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_246 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_246_i { I 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_246_o { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_246_o_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 887 \
+    name p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_230 \
+    type other \
+    dir O \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_230 \
+    op interface \
+    ports { p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_230 { O 16 vector } p_ZZN4nnet22compute_pool_buffer_2dINS_5arrayI8ap_fixedILi16ELi6EL9ap_q_mode5EL9ap_230_ap_vld { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id -1 \
+    name ap_ctrl \
+    type ap_ctrl \
+    reset_level 1 \
+    sync_rst true \
+    corename ap_ctrl \
+    op interface \
+    ports { ap_start { I 1 bit } ap_ready { O 1 bit } ap_done { O 1 bit } ap_idle { O 1 bit } } \
+} "
+}
+
+
+# Adapter definition:
+set PortName ap_clk
+set DataWd 1 
+if {${::AESL::PGuard_autoexp_gen}} {
+if {[info proc cg_default_interface_gen_clock] == "cg_default_interface_gen_clock"} {
+eval "cg_default_interface_gen_clock { \
+    id -2 \
+    name ${PortName} \
+    reset_level 1 \
+    sync_rst true \
+    corename apif_ap_clk \
+    data_wd ${DataWd} \
+    op interface \
+}"
+} else {
+puts "@W \[IMPL-113\] Cannot find bus interface model in the library. Ignored generation of bus interface for '${PortName}'"
+}
+}
+
+
+# Adapter definition:
+set PortName ap_rst
+set DataWd 1 
+if {${::AESL::PGuard_autoexp_gen}} {
+if {[info proc cg_default_interface_gen_reset] == "cg_default_interface_gen_reset"} {
+eval "cg_default_interface_gen_reset { \
+    id -3 \
+    name ${PortName} \
+    reset_level 1 \
+    sync_rst true \
+    corename apif_ap_rst \
+    data_wd ${DataWd} \
+    op interface \
+}"
+} else {
+puts "@W \[IMPL-114\] Cannot find bus interface model in the library. Ignored generation of bus interface for '${PortName}'"
+}
+}
+
+
+# Adapter definition:
+set PortName ap_ce
+set DataWd 1 
+if {${::AESL::PGuard_autoexp_gen}} {
+if {[info proc cg_default_interface_gen_ce] == "cg_default_interface_gen_ce"} {
+eval "cg_default_interface_gen_ce { \
+    id -4 \
+    name ${PortName} \
+    reset_level 1 \
+    sync_rst true \
+    corename apif_ap_ce \
+    data_wd ${DataWd} \
+    op interface \
+}"
+} else {
+puts "@W \[IMPL-113\] Cannot find bus interface model in the library. Ignored generation of bus interface for '${PortName}'"
+}
+}
+
+
+
+# merge
+if {${::AESL::PGuard_autoexp_gen}} {
+    cg_default_interface_gen_dc_end
+    cg_default_interface_gen_bundle_end
+    AESL_LIB_XILADAPTER::native_axis_end
+}
+
+

myproject_prj/solution1/.autopilot/db/sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_s.compgen.dataonly.tcl

@@ -0,0 +1,2 @@
+# This script segment is generated automatically by AutoPilot
+

myproject_prj/solution1/.autopilot/db/zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config44_s.sched.adb

@@ -0,0 +1,949 @@
+<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
+<!DOCTYPE boost_serialization>
+<boost_serialization signature="serialization::archive" version="17">
+<syndb class_id="0" tracking_level="0" version="0">
+	<userIPLatency>-1</userIPLatency>
+	<userIPName></userIPName>
+	<cdfg class_id="1" tracking_level="1" version="0" object_id="_0">
+		<name>zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config44_s</name>
+		<module_structure>Sequential</module_structure>
+		<ret_bitwidth>0</ret_bitwidth>
+		<ports class_id="2" tracking_level="0" version="0">
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+			<item_version>0</item_version>
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+						<type>1</type>
+						<id>1</id>
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+						<fileName></fileName>
+						<fileDirectory></fileDirectory>
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+						<contextFuncName></contextFuncName>
+						<contextNormFuncName></contextNormFuncName>
+						<inlineStackInfo class_id="6" tracking_level="0" version="0">
+							<count>0</count>
+							<item_version>0</item_version>
+						</inlineStackInfo>
+						<originalName>data</originalName>
+						<rtlName></rtlName>
+						<control></control>
+						<opType></opType>
+						<implIndex></implIndex>
+						<coreName></coreName>
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+						<storageDepth>0</storageDepth>
+						<coreId>4294967295</coreId>
+						<rtlModuleName></rtlModuleName>
+					</Obj>
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+				</Value>
+				<direction>0</direction>
+				<if_type>0</if_type>
+				<array_size>0</array_size>
+				<bit_vecs class_id="7" tracking_level="0" version="0">
+					<count>0</count>
+					<item_version>0</item_version>
+				</bit_vecs>
+			</item>
+			<item class_id_reference="3" object_id="_2">
+				<Value>
+					<Obj>
+						<type>1</type>
+						<id>2</id>
+						<name>layer44_out</name>
+						<fileName></fileName>
+						<fileDirectory></fileDirectory>
+						<lineNumber>0</lineNumber>
+						<contextFuncName></contextFuncName>
+						<contextNormFuncName></contextNormFuncName>
+						<inlineStackInfo>
+							<count>0</count>
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+						</inlineStackInfo>
+						<originalName></originalName>
+						<rtlName></rtlName>
+						<control></control>
+						<opType></opType>
+						<implIndex></implIndex>
+						<coreName></coreName>
+						<isStorage>0</isStorage>
+						<storageDepth>0</storageDepth>
+						<coreId>4294967295</coreId>
+						<rtlModuleName></rtlModuleName>
+					</Obj>
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+				</Value>
+				<direction>1</direction>
+				<if_type>3</if_type>
+				<array_size>0</array_size>
+				<bit_vecs>
+					<count>0</count>
+					<item_version>0</item_version>
+				</bit_vecs>
+			</item>
+		</ports>
+		<nodes class_id="8" tracking_level="0" version="0">
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+						<contextFuncName></contextFuncName>
+						<contextNormFuncName></contextNormFuncName>
+						<inlineStackInfo>
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+						</inlineStackInfo>
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+						<opType></opType>
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+						<coreName></coreName>
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+						<storageDepth>0</storageDepth>
+						<coreId>4294967295</coreId>
+						<rtlModuleName></rtlModuleName>
+					</Obj>
+					<bitwidth>32</bitwidth>
+				</Value>
+				<oprand_edges>
+					<count>1</count>
+					<item_version>0</item_version>
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+				</oprand_edges>
+				<opcode>wait</opcode>
+				<m_Display>0</m_Display>
+				<m_isOnCriticalPath>0</m_isOnCriticalPath>
+				<m_isLCDNode>0</m_isLCDNode>
+				<m_isStartOfPath>0</m_isStartOfPath>
+				<m_delay>0.00</m_delay>
+				<m_topoIndex>1</m_topoIndex>
+				<m_clusterGroupNumber>-1</m_clusterGroupNumber>
+			</item>
+			<item class_id_reference="9" object_id="_4">
+				<Value>
+					<Obj>
+						<type>0</type>
+						<id>6</id>
+						<name>_ln0</name>
+						<fileName></fileName>
+						<fileDirectory></fileDirectory>
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+						<contextFuncName></contextFuncName>
+						<contextNormFuncName></contextNormFuncName>
+						<inlineStackInfo>
+							<count>0</count>
+							<item_version>0</item_version>
+						</inlineStackInfo>
+						<originalName></originalName>
+						<rtlName></rtlName>
+						<control></control>
+						<opType></opType>
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+						<coreName></coreName>
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+						<rtlModuleName></rtlModuleName>
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+				<opcode>call</opcode>
+				<m_Display>0</m_Display>
+				<m_isOnCriticalPath>0</m_isOnCriticalPath>
+				<m_isLCDNode>0</m_isLCDNode>
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+				<m_delay>0.00</m_delay>
+				<m_topoIndex>2</m_topoIndex>
+				<m_clusterGroupNumber>-1</m_clusterGroupNumber>
+			</item>
+			<item class_id_reference="9" object_id="_5">
+				<Value>
+					<Obj>
+						<type>0</type>
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+						<name>empty_105</name>
+						<fileName></fileName>
+						<fileDirectory></fileDirectory>
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+						<contextFuncName></contextFuncName>
+						<contextNormFuncName></contextNormFuncName>
+						<inlineStackInfo>
+							<count>0</count>
+							<item_version>0</item_version>
+						</inlineStackInfo>
+						<originalName></originalName>
+						<rtlName></rtlName>
+						<control></control>
+						<opType></opType>
+						<implIndex></implIndex>
+						<coreName></coreName>
+						<isStorage>0</isStorage>
+						<storageDepth>0</storageDepth>
+						<coreId>4294967295</coreId>
+						<rtlModuleName></rtlModuleName>
+					</Obj>
+					<bitwidth>32</bitwidth>
+				</Value>
+				<oprand_edges>
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+					<item_version>0</item_version>
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+					<item>84</item>
+				</oprand_edges>
+				<opcode>wait</opcode>
+				<m_Display>0</m_Display>
+				<m_isOnCriticalPath>0</m_isOnCriticalPath>
+				<m_isLCDNode>0</m_isLCDNode>
+				<m_isStartOfPath>0</m_isStartOfPath>
+				<m_delay>0.00</m_delay>
+				<m_topoIndex>3</m_topoIndex>
+				<m_clusterGroupNumber>-1</m_clusterGroupNumber>
+			</item>
+			<item class_id_reference="9" object_id="_6">
+				<Value>
+					<Obj>
+						<type>0</type>
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+						<name>empty_106</name>
+						<fileName></fileName>
+						<fileDirectory></fileDirectory>
+						<lineNumber>0</lineNumber>
+						<contextFuncName></contextFuncName>
+						<contextNormFuncName></contextNormFuncName>
+						<inlineStackInfo>
+							<count>0</count>
+							<item_version>0</item_version>
+						</inlineStackInfo>
+						<originalName></originalName>
+						<rtlName></rtlName>
+						<control></control>
+						<opType></opType>
+						<implIndex></implIndex>
+						<coreName></coreName>
+						<isStorage>0</isStorage>
+						<storageDepth>0</storageDepth>
+						<coreId>4294967295</coreId>
+						<rtlModuleName></rtlModuleName>
+					</Obj>
+					<bitwidth>32</bitwidth>
+				</Value>
+				<oprand_edges>
+					<count>2</count>
+					<item_version>0</item_version>
+					<item>21</item>
+					<item>80</item>
+				</oprand_edges>
+				<opcode>wait</opcode>
+				<m_Display>0</m_Display>
+				<m_isOnCriticalPath>0</m_isOnCriticalPath>
+				<m_isLCDNode>0</m_isLCDNode>
+				<m_isStartOfPath>0</m_isStartOfPath>
+				<m_delay>0.00</m_delay>
+				<m_topoIndex>4</m_topoIndex>
+				<m_clusterGroupNumber>-1</m_clusterGroupNumber>
+			</item>
+			<item class_id_reference="9" object_id="_7">
+				<Value>
+					<Obj>
+						<type>0</type>
+						<id>9</id>
+						<name>_ln0</name>
+						<fileName></fileName>
+						<fileDirectory></fileDirectory>
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+						<contextFuncName></contextFuncName>
+						<contextNormFuncName></contextNormFuncName>
+						<inlineStackInfo>
+							<count>0</count>
+							<item_version>0</item_version>
+						</inlineStackInfo>
+						<originalName></originalName>
+						<rtlName></rtlName>
+						<control></control>
+						<opType></opType>
+						<implIndex></implIndex>
+						<coreName></coreName>
+						<isStorage>0</isStorage>
+						<storageDepth>0</storageDepth>
+						<coreId>4294967295</coreId>
+						<rtlModuleName></rtlModuleName>
+					</Obj>
+					<bitwidth>0</bitwidth>
+				</Value>
+				<oprand_edges>
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+					<item_version>0</item_version>
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+					<item>85</item>
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+					<item>90</item>
+				</oprand_edges>
+				<opcode>call</opcode>
+				<m_Display>0</m_Display>
+				<m_isOnCriticalPath>0</m_isOnCriticalPath>
+				<m_isLCDNode>0</m_isLCDNode>
+				<m_isStartOfPath>0</m_isStartOfPath>
+				<m_delay>0.07</m_delay>
+				<m_topoIndex>5</m_topoIndex>
+				<m_clusterGroupNumber>-1</m_clusterGroupNumber>
+			</item>
+			<item class_id_reference="9" object_id="_8">
+				<Value>
+					<Obj>
+						<type>0</type>
+						<id>10</id>
+						<name>empty_107</name>
+						<fileName></fileName>
+						<fileDirectory></fileDirectory>
+						<lineNumber>0</lineNumber>
+						<contextFuncName></contextFuncName>
+						<contextNormFuncName></contextNormFuncName>
+						<inlineStackInfo>
+							<count>0</count>
+							<item_version>0</item_version>
+						</inlineStackInfo>
+						<originalName></originalName>
+						<rtlName></rtlName>
+						<control></control>
+						<opType></opType>
+						<implIndex></implIndex>
+						<coreName></coreName>
+						<isStorage>0</isStorage>
+						<storageDepth>0</storageDepth>
+						<coreId>4294967295</coreId>
+						<rtlModuleName></rtlModuleName>
+					</Obj>
+					<bitwidth>32</bitwidth>
+				</Value>
+				<oprand_edges>
+					<count>3</count>
+					<item_version>0</item_version>
+					<item>26</item>
+					<item>81</item>
+					<item>86</item>
+				</oprand_edges>
+				<opcode>wait</opcode>
+				<m_Display>0</m_Display>
+				<m_isOnCriticalPath>0</m_isOnCriticalPath>
+				<m_isLCDNode>0</m_isLCDNode>
+				<m_isStartOfPath>0</m_isStartOfPath>
+				<m_delay>0.00</m_delay>
+				<m_topoIndex>6</m_topoIndex>
+				<m_clusterGroupNumber>-1</m_clusterGroupNumber>
+			</item>
+			<item class_id_reference="9" object_id="_9">
+				<Value>
+					<Obj>
+						<type>0</type>
+						<id>11</id>
+						<name>empty_108</name>
+						<fileName></fileName>
+						<fileDirectory></fileDirectory>
+						<lineNumber>0</lineNumber>
+						<contextFuncName></contextFuncName>
+						<contextNormFuncName></contextNormFuncName>
+						<inlineStackInfo>
+							<count>0</count>
+							<item_version>0</item_version>
+						</inlineStackInfo>
+						<originalName></originalName>
+						<rtlName></rtlName>
+						<control></control>
+						<opType></opType>
+						<implIndex></implIndex>
+						<coreName></coreName>
+						<isStorage>0</isStorage>
+						<storageDepth>0</storageDepth>
+						<coreId>4294967295</coreId>
+						<rtlModuleName></rtlModuleName>
+					</Obj>
+					<bitwidth>32</bitwidth>
+				</Value>
+				<oprand_edges>
+					<count>2</count>
+					<item_version>0</item_version>
+					<item>27</item>
+					<item>82</item>
+				</oprand_edges>
+				<opcode>wait</opcode>
+				<m_Display>0</m_Display>
+				<m_isOnCriticalPath>0</m_isOnCriticalPath>
+				<m_isLCDNode>0</m_isLCDNode>
+				<m_isStartOfPath>0</m_isStartOfPath>
+				<m_delay>0.00</m_delay>
+				<m_topoIndex>7</m_topoIndex>
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+	<dp_regname_phi>
+		<count>0</count>
+		<item_version>0</item_version>
+	</dp_regname_phi>
+	<dp_port_io_nodes class_id="36" tracking_level="0" version="0">
+		<count>0</count>
+		<item_version>0</item_version>
+	</dp_port_io_nodes>
+	<port2core>
+		<count>0</count>
+		<item_version>0</item_version>
+	</port2core>
+	<node2core>
+		<count>0</count>
+		<item_version>0</item_version>
+	</node2core>
+</syndb>
+</boost_serialization>
+

myproject_prj/solution1/.autopilot/db/zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_s.compgen.dataonly.tcl

@@ -0,0 +1,2 @@
+# This script segment is generated automatically by AutoPilot
+

myproject_prj/solution1/.autopilot/db/zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_s.bind.adb.xml

@@ -0,0 +1,421 @@
+<stg><name>zeropad2d_cl<array,array<ap_fixed<16,6,5,3,0>,16u>,config55></name>
+
+
+<trans_list>
+
+<trans id="23" from="1" to="2">
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+</trans>
+
+<trans id="24" from="2" to="3">
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+</trans>
+
+<trans id="25" from="3" to="4">
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+</trans>
+
+<trans id="26" from="4" to="5">
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+</trans>
+
+<trans id="27" from="5" to="6">
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+</trans>
+
+<trans id="28" from="6" to="7">
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+</trans>
+
+<trans id="29" from="7" to="8">
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+</trans>
+</trans_list>
+
+
+
+<state_list>
+
+<state id="1" st_id="1">
+
+<operation id="9" st_id="1" stage="1" lat="1">
+<core>NULL</core>
+<MemPortIdVec></MemPortIdVec>
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+
+<Node id="5" bw="32" op_0_bw="32">
+<![CDATA[
+entry:2 %empty = wait i32 @_ssdm_op_Wait
+
+]]></Node>
+<StgValue><ssdm name="empty"/></StgValue>
+</operation>
+
+<operation id="10" st_id="1" stage="2" lat="2">
+<core></core>
+<MemPortIdVec></MemPortIdVec>
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+
+<Node id="6" bw="0" op_0_bw="0" op_1_bw="256" op_2_bw="0">
+<![CDATA[
+entry:3 %call_ln0 = call void @zeropad2d_cl<array,array<ap_fixed,16u>,config55>_Pipeline_PadTopWidth, i256 %layer55_out
+
+]]></Node>
+<StgValue><ssdm name="call_ln0"/></StgValue>
+</operation>
+</state>
+
+<state id="2" st_id="2">
+
+<operation id="11" st_id="2" stage="1" lat="2">
+<core></core>
+<MemPortIdVec></MemPortIdVec>
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+
+<Node id="6" bw="0" op_0_bw="0" op_1_bw="256" op_2_bw="0">
+<![CDATA[
+entry:3 %call_ln0 = call void @zeropad2d_cl<array,array<ap_fixed,16u>,config55>_Pipeline_PadTopWidth, i256 %layer55_out
+
+]]></Node>
+<StgValue><ssdm name="call_ln0"/></StgValue>
+</operation>
+</state>
+
+<state id="3" st_id="3">
+
+<operation id="12" st_id="3" stage="1" lat="1">
+<core>NULL</core>
+<MemPortIdVec></MemPortIdVec>
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+
+<Node id="7" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="0">
+<![CDATA[
+entry:4 %empty_137 = wait i32 @_ssdm_op_Wait
+
+]]></Node>
+<StgValue><ssdm name="empty_137"/></StgValue>
+</operation>
+</state>
+
+<state id="4" st_id="4">
+
+<operation id="13" st_id="4" stage="1" lat="1">
+<core>NULL</core>
+<MemPortIdVec></MemPortIdVec>
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+
+<Node id="8" bw="32" op_0_bw="32" op_1_bw="0">
+<![CDATA[
+entry:5 %empty_138 = wait i32 @_ssdm_op_Wait
+
+]]></Node>
+<StgValue><ssdm name="empty_138"/></StgValue>
+</operation>
+
+<operation id="14" st_id="4" stage="2" lat="2">
+<core></core>
+<MemPortIdVec></MemPortIdVec>
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+
+<Node id="9" bw="0" op_0_bw="0" op_1_bw="256" op_2_bw="256" op_3_bw="0" op_4_bw="0" op_5_bw="0">
+<![CDATA[
+entry:6 %call_ln0 = call void @zeropad2d_cl<array,array<ap_fixed<16,6,5,3,0>,16u>,config55>_Pipeline_PadMain, i256 %layer55_out, i256 %layer30_out
+
+]]></Node>
+<StgValue><ssdm name="call_ln0"/></StgValue>
+</operation>
+</state>
+
+<state id="5" st_id="5">
+
+<operation id="15" st_id="5" stage="1" lat="2">
+<core></core>
+<MemPortIdVec></MemPortIdVec>
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+
+<Node id="9" bw="0" op_0_bw="0" op_1_bw="256" op_2_bw="256" op_3_bw="0" op_4_bw="0" op_5_bw="0">
+<![CDATA[
+entry:6 %call_ln0 = call void @zeropad2d_cl<array,array<ap_fixed<16,6,5,3,0>,16u>,config55>_Pipeline_PadMain, i256 %layer55_out, i256 %layer30_out
+
+]]></Node>
+<StgValue><ssdm name="call_ln0"/></StgValue>
+</operation>
+</state>
+
+<state id="6" st_id="6">
+
+<operation id="16" st_id="6" stage="1" lat="1">
+<core>NULL</core>
+<MemPortIdVec></MemPortIdVec>
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+
+<Node id="10" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="0">
+<![CDATA[
+entry:7 %empty_139 = wait i32 @_ssdm_op_Wait
+
+]]></Node>
+<StgValue><ssdm name="empty_139"/></StgValue>
+</operation>
+</state>
+
+<state id="7" st_id="7">
+
+<operation id="17" st_id="7" stage="1" lat="1">
+<core>NULL</core>
+<MemPortIdVec></MemPortIdVec>
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+
+<Node id="11" bw="32" op_0_bw="32" op_1_bw="0">
+<![CDATA[
+entry:8 %empty_140 = wait i32 @_ssdm_op_Wait
+
+]]></Node>
+<StgValue><ssdm name="empty_140"/></StgValue>
+</operation>
+
+<operation id="18" st_id="7" stage="2" lat="2">
+<core></core>
+<MemPortIdVec></MemPortIdVec>
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+
+<Node id="12" bw="0" op_0_bw="0" op_1_bw="256" op_2_bw="0" op_3_bw="0" op_4_bw="0">
+<![CDATA[
+entry:9 %call_ln0 = call void @zeropad2d_cl<array,array<ap_fixed,16u>,config55>_Pipeline_PadBottomWidth, i256 %layer55_out
+
+]]></Node>
+<StgValue><ssdm name="call_ln0"/></StgValue>
+</operation>
+</state>
+
+<state id="8" st_id="8">
+
+<operation id="19" st_id="8" stage="1" lat="1">
+<core>NULL</core>
+<MemPortIdVec></MemPortIdVec>
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+
+<Node id="3" bw="0" op_0_bw="0" op_1_bw="256" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32" op_19_bw="32">
+<![CDATA[
+entry:0 %specinterface_ln0 = specinterface void @_ssdm_op_SpecInterface, i256 %layer55_out, void @empty_8, i32 0, i32 0, void @empty_9, i32 0, i32 0, void @empty_9, void @empty_9, void @empty_9, i32 0, i32 0, i32 0, i32 0, void @empty_9, void @empty_9, i32 4294967295, i32 0, i32 0
+
+]]></Node>
+<StgValue><ssdm name="specinterface_ln0"/></StgValue>
+</operation>
+
+<operation id="20" st_id="8" stage="1" lat="1">
+<core>NULL</core>
+<MemPortIdVec></MemPortIdVec>
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+
+<Node id="4" bw="0" op_0_bw="0" op_1_bw="256" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32" op_19_bw="32">
+<![CDATA[
+entry:1 %specinterface_ln0 = specinterface void @_ssdm_op_SpecInterface, i256 %layer30_out, void @empty_8, i32 0, i32 0, void @empty_9, i32 0, i32 0, void @empty_9, void @empty_9, void @empty_9, i32 0, i32 0, i32 0, i32 0, void @empty_9, void @empty_9, i32 4294967295, i32 0, i32 0
+
+]]></Node>
+<StgValue><ssdm name="specinterface_ln0"/></StgValue>
+</operation>
+
+<operation id="21" st_id="8" stage="1" lat="2">
+<core></core>
+<MemPortIdVec></MemPortIdVec>
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+
+<Node id="12" bw="0" op_0_bw="0" op_1_bw="256" op_2_bw="0" op_3_bw="0" op_4_bw="0">
+<![CDATA[
+entry:9 %call_ln0 = call void @zeropad2d_cl<array,array<ap_fixed,16u>,config55>_Pipeline_PadBottomWidth, i256 %layer55_out
+
+]]></Node>
+<StgValue><ssdm name="call_ln0"/></StgValue>
+</operation>
+
+<operation id="22" st_id="8" stage="1" lat="1">
+<core>NULL</core>
+<MemPortIdVec></MemPortIdVec>
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+
+<Node id="13" bw="0">
+<![CDATA[
+entry:10 %ret_ln81 = ret
+
+]]></Node>
+<StgValue><ssdm name="ret_ln81"/></StgValue>
+</operation>
+</state>
+</state_list>
+
+
+<ports>
+<port id="30" name="layer30_out" dir="0" iftype="3">
+<core>NULL</core><StgValue><ssdm name="layer30_out"/></StgValue>
+</port>
+<port id="31" name="layer55_out" dir="1" iftype="3">
+<core>NULL</core><StgValue><ssdm name="layer55_out"/></StgValue>
+</port>
+</ports>
+
+
+<dataflows>
+<dataflow id="33" from="_ssdm_op_Wait" to="empty" fromId="32" toId="9">
+</dataflow>
+<dataflow id="35" from="zeropad2d_cl<array,array<ap_fixed,16u>,config55>_Pipeline_PadTopWidth" to="call_ln0" fromId="34" toId="10">
+</dataflow>
+<dataflow id="36" from="layer55_out" to="call_ln0" fromId="31" toId="10">
+</dataflow>
+<dataflow id="37" from="zeropad2d_cl<array,array<ap_fixed,16u>,config55>_Pipeline_PadTopWidth" to="call_ln0" fromId="34" toId="11">
+</dataflow>
+<dataflow id="38" from="layer55_out" to="call_ln0" fromId="31" toId="11">
+</dataflow>
+<dataflow id="39" from="_ssdm_op_Wait" to="empty_137" fromId="32" toId="12">
+</dataflow>
+<dataflow id="40" from="_ssdm_op_Wait" to="empty_138" fromId="32" toId="13">
+</dataflow>
+<dataflow id="42" from="zeropad2d_cl<array,array<ap_fixed<16,6,5,3,0>,16u>,config55>_Pipeline_PadMain" to="call_ln0" fromId="41" toId="14">
+</dataflow>
+<dataflow id="43" from="layer55_out" to="call_ln0" fromId="31" toId="14">
+</dataflow>
+<dataflow id="44" from="layer30_out" to="call_ln0" fromId="30" toId="14">
+</dataflow>
+<dataflow id="45" from="zeropad2d_cl<array,array<ap_fixed<16,6,5,3,0>,16u>,config55>_Pipeline_PadMain" to="call_ln0" fromId="41" toId="15">
+</dataflow>
+<dataflow id="46" from="layer55_out" to="call_ln0" fromId="31" toId="15">
+</dataflow>
+<dataflow id="47" from="layer30_out" to="call_ln0" fromId="30" toId="15">
+</dataflow>
+<dataflow id="48" from="_ssdm_op_Wait" to="empty_139" fromId="32" toId="16">
+</dataflow>
+<dataflow id="49" from="_ssdm_op_Wait" to="empty_140" fromId="32" toId="17">
+</dataflow>
+<dataflow id="51" from="zeropad2d_cl<array,array<ap_fixed,16u>,config55>_Pipeline_PadBottomWidth" to="call_ln0" fromId="50" toId="18">
+</dataflow>
+<dataflow id="52" from="layer55_out" to="call_ln0" fromId="31" toId="18">
+</dataflow>
+<dataflow id="54" from="_ssdm_op_SpecInterface" to="specinterface_ln0" fromId="53" toId="19">
+</dataflow>
+<dataflow id="55" from="layer55_out" to="specinterface_ln0" fromId="31" toId="19">
+</dataflow>
+<dataflow id="57" from="empty_8" to="specinterface_ln0" fromId="56" toId="19">
+</dataflow>
+<dataflow id="59" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="19">
+</dataflow>
+<dataflow id="60" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="19">
+</dataflow>
+<dataflow id="62" from="empty_9" to="specinterface_ln0" fromId="61" toId="19">
+</dataflow>
+<dataflow id="63" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="19">
+</dataflow>
+<dataflow id="64" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="19">
+</dataflow>
+<dataflow id="65" from="empty_9" to="specinterface_ln0" fromId="61" toId="19">
+</dataflow>
+<dataflow id="66" from="empty_9" to="specinterface_ln0" fromId="61" toId="19">
+</dataflow>
+<dataflow id="67" from="empty_9" to="specinterface_ln0" fromId="61" toId="19">
+</dataflow>
+<dataflow id="68" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="19">
+</dataflow>
+<dataflow id="69" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="19">
+</dataflow>
+<dataflow id="70" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="19">
+</dataflow>
+<dataflow id="71" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="19">
+</dataflow>
+<dataflow id="72" from="empty_9" to="specinterface_ln0" fromId="61" toId="19">
+</dataflow>
+<dataflow id="73" from="empty_9" to="specinterface_ln0" fromId="61" toId="19">
+</dataflow>
+<dataflow id="75" from="StgValue_74" to="specinterface_ln0" fromId="74" toId="19">
+</dataflow>
+<dataflow id="76" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="19">
+</dataflow>
+<dataflow id="77" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="19">
+</dataflow>
+<dataflow id="78" from="_ssdm_op_SpecInterface" to="specinterface_ln0" fromId="53" toId="20">
+</dataflow>
+<dataflow id="79" from="layer30_out" to="specinterface_ln0" fromId="30" toId="20">
+</dataflow>
+<dataflow id="80" from="empty_8" to="specinterface_ln0" fromId="56" toId="20">
+</dataflow>
+<dataflow id="81" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="20">
+</dataflow>
+<dataflow id="82" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="20">
+</dataflow>
+<dataflow id="83" from="empty_9" to="specinterface_ln0" fromId="61" toId="20">
+</dataflow>
+<dataflow id="84" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="20">
+</dataflow>
+<dataflow id="85" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="20">
+</dataflow>
+<dataflow id="86" from="empty_9" to="specinterface_ln0" fromId="61" toId="20">
+</dataflow>
+<dataflow id="87" from="empty_9" to="specinterface_ln0" fromId="61" toId="20">
+</dataflow>
+<dataflow id="88" from="empty_9" to="specinterface_ln0" fromId="61" toId="20">
+</dataflow>
+<dataflow id="89" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="20">
+</dataflow>
+<dataflow id="90" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="20">
+</dataflow>
+<dataflow id="91" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="20">
+</dataflow>
+<dataflow id="92" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="20">
+</dataflow>
+<dataflow id="93" from="empty_9" to="specinterface_ln0" fromId="61" toId="20">
+</dataflow>
+<dataflow id="94" from="empty_9" to="specinterface_ln0" fromId="61" toId="20">
+</dataflow>
+<dataflow id="95" from="StgValue_74" to="specinterface_ln0" fromId="74" toId="20">
+</dataflow>
+<dataflow id="96" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="20">
+</dataflow>
+<dataflow id="97" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="20">
+</dataflow>
+<dataflow id="98" from="zeropad2d_cl<array,array<ap_fixed,16u>,config55>_Pipeline_PadBottomWidth" to="call_ln0" fromId="50" toId="21">
+</dataflow>
+<dataflow id="99" from="layer55_out" to="call_ln0" fromId="31" toId="21">
+</dataflow>
+</dataflows>
+
+
+</stg>

myproject_prj/solution1/.autopilot/db/zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config58_Pipeline_PadMain.verbose.rpt.xml

@@ -0,0 +1,207 @@
+<profile>
+
+<section name = "Vitis HLS Report for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config58_Pipeline_PadMain'" level="0">
+<item name = "Date">Tue Mar 31 03:37:11 2026
+</item>
+<item name = "Version">2024.1 (Build 5069499 on May 21 2024)</item>
+<item name = "Project">myproject_prj</item>
+<item name = "Solution">solution1 (Vivado IP Flow Target)</item>
+<item name = "Product family">virtexuplusHBM</item>
+<item name = "Target device">xcvu47p-fsvh2892-2L-e</item>
+</section>
+
+<section name = "Performance Estimates" level="0">
+<item name = "Timing">
+<section name = "" level="1">
+<item name = "Summary"><table name="" hasTotal="0">
+<keys size="4">Clock, Target, Estimated, Uncertainty</keys>
+<column name="ap_clk">5.00 ns, 1.480 ns, 1.35 ns</column>
+</table>
+</item>
+</section>
+</item>
+<item name = "Latency">
+<section name = "" level="1">
+<item name = "Summary"><table name="" hasTotal="0">
+<keys size="8">, min, max, min, max, min, max, Type</keys>
+<column name="">4226, 4226, 21.130 us, 21.130 us, 4225, 4225, loop auto-rewind stp(delay=0 clock cycles(s))</column>
+</table>
+</item>
+<item name = "Detail">
+<section name = "" level="1">
+<item name = "Instance"><table name="" hasTotal="0">
+<keys size="9">Instance, Module, min, max, min, max, min, max, Type</keys>
+</table>
+</item>
+<item name = "Loop"><table name="" hasTotal="0">
+<keys size="8">Loop Name, min, max, Latency, achieved, target, Count, Pipelined</keys>
+<column name="- PadMain">4224, 4224, 67, 66, 1, 64, yes</column>
+</table>
+</item>
+</section>
+</item>
+</section>
+</item>
+</section>
+
+<section name = "Utilization Estimates" level="0">
+<item name = "Summary"><table name="" hasTotal="1">
+<keys size="6">Name, BRAM_18K, DSP, FF, LUT, URAM</keys>
+<column name="DSP">-, -, -, -, -</column>
+<column name="Expression">-, -, 0, 167, -</column>
+<column name="FIFO">-, -, -, -, -</column>
+<column name="Instance">-, -, -, -, -</column>
+<column name="Memory">-, -, -, -, -</column>
+<column name="Multiplexer">-, -, 0, 378, -</column>
+<column name="Register">-, -, 461, -, -</column>
+<specialColumn name="Available SLR">1344, 3008, 869120, 434560, 320</specialColumn>
+<specialColumn name="Utilization SLR (%)">0, 0, ~0, ~0, 0</specialColumn>
+<specialColumn name="Available">4032, 9024, 2607360, 1303680, 960</specialColumn>
+<specialColumn name="Utilization (%)">0, 0, ~0, ~0, 0</specialColumn>
+</table>
+</item>
+<item name = "Detail">
+<section name = "" level="1">
+<item name = "Instance"><table name="" hasTotal="1">
+<keys size="7">Instance, Module, BRAM_18K, DSP, FF, LUT, URAM</keys>
+</table>
+</item>
+<item name = "DSP"><table name="" hasTotal="0">
+<keys size="3">Instance, Module, Expression</keys>
+</table>
+</item>
+<item name = "Memory"><table name="" hasTotal="1">
+<keys size="10">Memory, Module, BRAM_18K, FF, LUT, URAM, Words, Bits, Banks, W*Bits*Banks</keys>
+</table>
+</item>
+<item name = "FIFO"><table name="" hasTotal="1">
+<keys size="8">Name, BRAM_18K, FF, LUT, URAM, Depth, Bits, Size:D*B</keys>
+</table>
+</item>
+<item name = "Expression"><table name="" hasTotal="1">
+<keys size="7">Variable Name, Operation, DSP, FF, LUT, Bitwidth P0, Bitwidth P1</keys>
+<column name="i_20_fu_75_p2">+, 0, 0, 14, 7, 1</column>
+<column name="ap_block_pp0_stage0_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage10_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage11_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage12_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage13_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage14_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage15_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage16_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage17_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage18_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage19_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage1_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage20_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage21_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage22_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage23_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage24_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage25_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage26_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage27_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage28_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage29_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage2_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage30_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage31_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage32_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage33_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage34_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage35_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage36_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage37_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage38_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage39_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage3_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage40_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage41_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage42_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage43_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage44_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage45_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage46_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage47_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage48_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage49_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage4_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage50_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage51_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage52_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage53_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage54_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage55_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage56_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage57_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage58_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage59_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage5_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage60_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage61_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage62_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage63_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage64_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage65_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage6_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage7_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage8_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_pp0_stage9_01001">and, 0, 0, 2, 1, 1</column>
+<column name="ap_block_state66_pp0_stage65_iter0">and, 0, 0, 2, 1, 1</column>
+<column name="icmp_ln59_fu_69_p2">icmp, 0, 0, 15, 7, 8</column>
+<column name="ap_block_state10_pp0_stage9_iter0">or, 0, 0, 2, 1, 1</column>
+<column name="ap_enable_pp0">xor, 0, 0, 2, 1, 2</column>
+</table>
+</item>
+<item name = "Multiplexer"><table name="" hasTotal="1">
+<keys size="5">Name, LUT, Input Size, Bits, Total Bits</keys>
+<column name="ap_NS_fsm">292, 67, 1, 67</column>
+<column name="ap_done_int">9, 2, 1, 2</column>
+<column name="ap_enable_reg_pp0_iter0">9, 2, 1, 2</column>
+<column name="ap_enable_reg_pp0_iter0_reg">9, 2, 1, 2</column>
+<column name="ap_enable_reg_pp0_iter1">9, 2, 1, 2</column>
+<column name="ap_sig_allocacmp_i_19">9, 2, 7, 14</column>
+<column name="i_fu_38">9, 2, 7, 14</column>
+<column name="layer34_out_blk_n">9, 2, 1, 2</column>
+<column name="layer58_out_blk_n">9, 2, 1, 2</column>
+<column name="layer58_out_din_local">14, 3, 384, 1152</column>
+</table>
+</item>
+<item name = "Register"><table name="" hasTotal="1">
+<keys size="5">Name, FF, LUT, Bits, Const Bits</keys>
+<column name="ap_CS_fsm">66, 0, 66, 0</column>
+<column name="ap_done_reg">1, 0, 1, 0</column>
+<column name="ap_enable_reg_pp0_iter0_reg">1, 0, 1, 0</column>
+<column name="ap_enable_reg_pp0_iter1">1, 0, 1, 0</column>
+<column name="i_fu_38">7, 0, 7, 0</column>
+<column name="icmp_ln59_reg_93">1, 0, 1, 0</column>
+<column name="reg_56">384, 0, 384, 0</column>
+</table>
+</item>
+</section>
+</item>
+</section>
+
+<section name = "Interface" level="0">
+<item name = "Summary"><table name="" hasTotal="0">
+<keys size="6">RTL Ports, Dir, Bits, Protocol, Source Object, C Type</keys>
+<column name="ap_clk">in, 1, ap_ctrl_hs, zeropad2d_cl&lt;array,array&lt;ap_fixed&lt;16,6,5,3,0&gt;,24u&gt;,config58&gt;_Pipeline_PadMain, return value</column>
+<column name="ap_rst">in, 1, ap_ctrl_hs, zeropad2d_cl&lt;array,array&lt;ap_fixed&lt;16,6,5,3,0&gt;,24u&gt;,config58&gt;_Pipeline_PadMain, return value</column>
+<column name="ap_start">in, 1, ap_ctrl_hs, zeropad2d_cl&lt;array,array&lt;ap_fixed&lt;16,6,5,3,0&gt;,24u&gt;,config58&gt;_Pipeline_PadMain, return value</column>
+<column name="ap_done">out, 1, ap_ctrl_hs, zeropad2d_cl&lt;array,array&lt;ap_fixed&lt;16,6,5,3,0&gt;,24u&gt;,config58&gt;_Pipeline_PadMain, return value</column>
+<column name="ap_idle">out, 1, ap_ctrl_hs, zeropad2d_cl&lt;array,array&lt;ap_fixed&lt;16,6,5,3,0&gt;,24u&gt;,config58&gt;_Pipeline_PadMain, return value</column>
+<column name="ap_ready">out, 1, ap_ctrl_hs, zeropad2d_cl&lt;array,array&lt;ap_fixed&lt;16,6,5,3,0&gt;,24u&gt;,config58&gt;_Pipeline_PadMain, return value</column>
+<column name="layer58_out_din">out, 384, ap_fifo, layer58_out, pointer</column>
+<column name="layer58_out_num_data_valid">in, 14, ap_fifo, layer58_out, pointer</column>
+<column name="layer58_out_fifo_cap">in, 14, ap_fifo, layer58_out, pointer</column>
+<column name="layer58_out_full_n">in, 1, ap_fifo, layer58_out, pointer</column>
+<column name="layer58_out_write">out, 1, ap_fifo, layer58_out, pointer</column>
+<column name="layer34_out_dout">in, 384, ap_fifo, layer34_out, pointer</column>
+<column name="layer34_out_num_data_valid">in, 13, ap_fifo, layer34_out, pointer</column>
+<column name="layer34_out_fifo_cap">in, 13, ap_fifo, layer34_out, pointer</column>
+<column name="layer34_out_empty_n">in, 1, ap_fifo, layer34_out, pointer</column>
+<column name="layer34_out_read">out, 1, ap_fifo, layer34_out, pointer</column>
+</table>
+</item>
+</section>
+</profile>

myproject_prj/solution1/.autopilot/db/zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_s.bind.adb.xml

@@ -0,0 +1,421 @@
+<stg><name>zeropad2d_cl<array,array<ap_fixed<16,6,5,3,0>,32u>,config49></name>
+
+
+<trans_list>
+
+<trans id="23" from="1" to="2">
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+</trans>
+
+<trans id="24" from="2" to="3">
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+</trans>
+
+<trans id="25" from="3" to="4">
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+</trans>
+
+<trans id="26" from="4" to="5">
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+</trans>
+
+<trans id="27" from="5" to="6">
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+</trans>
+
+<trans id="28" from="6" to="7">
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+</trans>
+
+<trans id="29" from="7" to="8">
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+</trans>
+</trans_list>
+
+
+
+<state_list>
+
+<state id="1" st_id="1">
+
+<operation id="9" st_id="1" stage="1" lat="1">
+<core>NULL</core>
+<MemPortIdVec></MemPortIdVec>
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+
+<Node id="5" bw="32" op_0_bw="32">
+<![CDATA[
+entry:2 %empty = wait i32 @_ssdm_op_Wait
+
+]]></Node>
+<StgValue><ssdm name="empty"/></StgValue>
+</operation>
+
+<operation id="10" st_id="1" stage="2" lat="2">
+<core></core>
+<MemPortIdVec></MemPortIdVec>
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+
+<Node id="6" bw="0" op_0_bw="0" op_1_bw="512" op_2_bw="0">
+<![CDATA[
+entry:3 %call_ln0 = call void @zeropad2d_cl<array,array<ap_fixed,32u>,config49>_Pipeline_PadTopWidth, i512 %layer49_out
+
+]]></Node>
+<StgValue><ssdm name="call_ln0"/></StgValue>
+</operation>
+</state>
+
+<state id="2" st_id="2">
+
+<operation id="11" st_id="2" stage="1" lat="2">
+<core></core>
+<MemPortIdVec></MemPortIdVec>
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+
+<Node id="6" bw="0" op_0_bw="0" op_1_bw="512" op_2_bw="0">
+<![CDATA[
+entry:3 %call_ln0 = call void @zeropad2d_cl<array,array<ap_fixed,32u>,config49>_Pipeline_PadTopWidth, i512 %layer49_out
+
+]]></Node>
+<StgValue><ssdm name="call_ln0"/></StgValue>
+</operation>
+</state>
+
+<state id="3" st_id="3">
+
+<operation id="12" st_id="3" stage="1" lat="1">
+<core>NULL</core>
+<MemPortIdVec></MemPortIdVec>
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+
+<Node id="7" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="0">
+<![CDATA[
+entry:4 %empty_129 = wait i32 @_ssdm_op_Wait
+
+]]></Node>
+<StgValue><ssdm name="empty_129"/></StgValue>
+</operation>
+</state>
+
+<state id="4" st_id="4">
+
+<operation id="13" st_id="4" stage="1" lat="1">
+<core>NULL</core>
+<MemPortIdVec></MemPortIdVec>
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+
+<Node id="8" bw="32" op_0_bw="32" op_1_bw="0">
+<![CDATA[
+entry:5 %empty_130 = wait i32 @_ssdm_op_Wait
+
+]]></Node>
+<StgValue><ssdm name="empty_130"/></StgValue>
+</operation>
+
+<operation id="14" st_id="4" stage="2" lat="2">
+<core></core>
+<MemPortIdVec></MemPortIdVec>
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+
+<Node id="9" bw="0" op_0_bw="0" op_1_bw="512" op_2_bw="512" op_3_bw="0" op_4_bw="0" op_5_bw="0">
+<![CDATA[
+entry:6 %call_ln0 = call void @zeropad2d_cl<array,array<ap_fixed<16,6,5,3,0>,32u>,config49>_Pipeline_PadMain, i512 %layer49_out, i512 %layer13_out
+
+]]></Node>
+<StgValue><ssdm name="call_ln0"/></StgValue>
+</operation>
+</state>
+
+<state id="5" st_id="5">
+
+<operation id="15" st_id="5" stage="1" lat="2">
+<core></core>
+<MemPortIdVec></MemPortIdVec>
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+
+<Node id="9" bw="0" op_0_bw="0" op_1_bw="512" op_2_bw="512" op_3_bw="0" op_4_bw="0" op_5_bw="0">
+<![CDATA[
+entry:6 %call_ln0 = call void @zeropad2d_cl<array,array<ap_fixed<16,6,5,3,0>,32u>,config49>_Pipeline_PadMain, i512 %layer49_out, i512 %layer13_out
+
+]]></Node>
+<StgValue><ssdm name="call_ln0"/></StgValue>
+</operation>
+</state>
+
+<state id="6" st_id="6">
+
+<operation id="16" st_id="6" stage="1" lat="1">
+<core>NULL</core>
+<MemPortIdVec></MemPortIdVec>
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+
+<Node id="10" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="0">
+<![CDATA[
+entry:7 %empty_131 = wait i32 @_ssdm_op_Wait
+
+]]></Node>
+<StgValue><ssdm name="empty_131"/></StgValue>
+</operation>
+</state>
+
+<state id="7" st_id="7">
+
+<operation id="17" st_id="7" stage="1" lat="1">
+<core>NULL</core>
+<MemPortIdVec></MemPortIdVec>
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+
+<Node id="11" bw="32" op_0_bw="32" op_1_bw="0">
+<![CDATA[
+entry:8 %empty_132 = wait i32 @_ssdm_op_Wait
+
+]]></Node>
+<StgValue><ssdm name="empty_132"/></StgValue>
+</operation>
+
+<operation id="18" st_id="7" stage="2" lat="2">
+<core></core>
+<MemPortIdVec></MemPortIdVec>
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+
+<Node id="12" bw="0" op_0_bw="0" op_1_bw="512" op_2_bw="0" op_3_bw="0" op_4_bw="0">
+<![CDATA[
+entry:9 %call_ln0 = call void @zeropad2d_cl<array,array<ap_fixed,32u>,config49>_Pipeline_PadBottomWidth, i512 %layer49_out
+
+]]></Node>
+<StgValue><ssdm name="call_ln0"/></StgValue>
+</operation>
+</state>
+
+<state id="8" st_id="8">
+
+<operation id="19" st_id="8" stage="1" lat="1">
+<core>NULL</core>
+<MemPortIdVec></MemPortIdVec>
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+
+<Node id="3" bw="0" op_0_bw="0" op_1_bw="512" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32" op_19_bw="32">
+<![CDATA[
+entry:0 %specinterface_ln0 = specinterface void @_ssdm_op_SpecInterface, i512 %layer49_out, void @empty_8, i32 0, i32 0, void @empty_9, i32 0, i32 0, void @empty_9, void @empty_9, void @empty_9, i32 0, i32 0, i32 0, i32 0, void @empty_9, void @empty_9, i32 4294967295, i32 0, i32 0
+
+]]></Node>
+<StgValue><ssdm name="specinterface_ln0"/></StgValue>
+</operation>
+
+<operation id="20" st_id="8" stage="1" lat="1">
+<core>NULL</core>
+<MemPortIdVec></MemPortIdVec>
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+
+<Node id="4" bw="0" op_0_bw="0" op_1_bw="512" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32" op_19_bw="32">
+<![CDATA[
+entry:1 %specinterface_ln0 = specinterface void @_ssdm_op_SpecInterface, i512 %layer13_out, void @empty_8, i32 0, i32 0, void @empty_9, i32 0, i32 0, void @empty_9, void @empty_9, void @empty_9, i32 0, i32 0, i32 0, i32 0, void @empty_9, void @empty_9, i32 4294967295, i32 0, i32 0
+
+]]></Node>
+<StgValue><ssdm name="specinterface_ln0"/></StgValue>
+</operation>
+
+<operation id="21" st_id="8" stage="1" lat="2">
+<core></core>
+<MemPortIdVec></MemPortIdVec>
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+
+<Node id="12" bw="0" op_0_bw="0" op_1_bw="512" op_2_bw="0" op_3_bw="0" op_4_bw="0">
+<![CDATA[
+entry:9 %call_ln0 = call void @zeropad2d_cl<array,array<ap_fixed,32u>,config49>_Pipeline_PadBottomWidth, i512 %layer49_out
+
+]]></Node>
+<StgValue><ssdm name="call_ln0"/></StgValue>
+</operation>
+
+<operation id="22" st_id="8" stage="1" lat="1">
+<core>NULL</core>
+<MemPortIdVec></MemPortIdVec>
+<condition id="-1">
+<or_exp><and_exp></and_exp></or_exp>
+</condition>
+
+<Node id="13" bw="0">
+<![CDATA[
+entry:10 %ret_ln81 = ret
+
+]]></Node>
+<StgValue><ssdm name="ret_ln81"/></StgValue>
+</operation>
+</state>
+</state_list>
+
+
+<ports>
+<port id="30" name="layer13_out" dir="0" iftype="3">
+<core>NULL</core><StgValue><ssdm name="layer13_out"/></StgValue>
+</port>
+<port id="31" name="layer49_out" dir="1" iftype="3">
+<core>NULL</core><StgValue><ssdm name="layer49_out"/></StgValue>
+</port>
+</ports>
+
+
+<dataflows>
+<dataflow id="33" from="_ssdm_op_Wait" to="empty" fromId="32" toId="9">
+</dataflow>
+<dataflow id="35" from="zeropad2d_cl<array,array<ap_fixed,32u>,config49>_Pipeline_PadTopWidth" to="call_ln0" fromId="34" toId="10">
+</dataflow>
+<dataflow id="36" from="layer49_out" to="call_ln0" fromId="31" toId="10">
+</dataflow>
+<dataflow id="37" from="zeropad2d_cl<array,array<ap_fixed,32u>,config49>_Pipeline_PadTopWidth" to="call_ln0" fromId="34" toId="11">
+</dataflow>
+<dataflow id="38" from="layer49_out" to="call_ln0" fromId="31" toId="11">
+</dataflow>
+<dataflow id="39" from="_ssdm_op_Wait" to="empty_129" fromId="32" toId="12">
+</dataflow>
+<dataflow id="40" from="_ssdm_op_Wait" to="empty_130" fromId="32" toId="13">
+</dataflow>
+<dataflow id="42" from="zeropad2d_cl<array,array<ap_fixed<16,6,5,3,0>,32u>,config49>_Pipeline_PadMain" to="call_ln0" fromId="41" toId="14">
+</dataflow>
+<dataflow id="43" from="layer49_out" to="call_ln0" fromId="31" toId="14">
+</dataflow>
+<dataflow id="44" from="layer13_out" to="call_ln0" fromId="30" toId="14">
+</dataflow>
+<dataflow id="45" from="zeropad2d_cl<array,array<ap_fixed<16,6,5,3,0>,32u>,config49>_Pipeline_PadMain" to="call_ln0" fromId="41" toId="15">
+</dataflow>
+<dataflow id="46" from="layer49_out" to="call_ln0" fromId="31" toId="15">
+</dataflow>
+<dataflow id="47" from="layer13_out" to="call_ln0" fromId="30" toId="15">
+</dataflow>
+<dataflow id="48" from="_ssdm_op_Wait" to="empty_131" fromId="32" toId="16">
+</dataflow>
+<dataflow id="49" from="_ssdm_op_Wait" to="empty_132" fromId="32" toId="17">
+</dataflow>
+<dataflow id="51" from="zeropad2d_cl<array,array<ap_fixed,32u>,config49>_Pipeline_PadBottomWidth" to="call_ln0" fromId="50" toId="18">
+</dataflow>
+<dataflow id="52" from="layer49_out" to="call_ln0" fromId="31" toId="18">
+</dataflow>
+<dataflow id="54" from="_ssdm_op_SpecInterface" to="specinterface_ln0" fromId="53" toId="19">
+</dataflow>
+<dataflow id="55" from="layer49_out" to="specinterface_ln0" fromId="31" toId="19">
+</dataflow>
+<dataflow id="57" from="empty_8" to="specinterface_ln0" fromId="56" toId="19">
+</dataflow>
+<dataflow id="59" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="19">
+</dataflow>
+<dataflow id="60" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="19">
+</dataflow>
+<dataflow id="62" from="empty_9" to="specinterface_ln0" fromId="61" toId="19">
+</dataflow>
+<dataflow id="63" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="19">
+</dataflow>
+<dataflow id="64" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="19">
+</dataflow>
+<dataflow id="65" from="empty_9" to="specinterface_ln0" fromId="61" toId="19">
+</dataflow>
+<dataflow id="66" from="empty_9" to="specinterface_ln0" fromId="61" toId="19">
+</dataflow>
+<dataflow id="67" from="empty_9" to="specinterface_ln0" fromId="61" toId="19">
+</dataflow>
+<dataflow id="68" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="19">
+</dataflow>
+<dataflow id="69" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="19">
+</dataflow>
+<dataflow id="70" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="19">
+</dataflow>
+<dataflow id="71" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="19">
+</dataflow>
+<dataflow id="72" from="empty_9" to="specinterface_ln0" fromId="61" toId="19">
+</dataflow>
+<dataflow id="73" from="empty_9" to="specinterface_ln0" fromId="61" toId="19">
+</dataflow>
+<dataflow id="75" from="StgValue_74" to="specinterface_ln0" fromId="74" toId="19">
+</dataflow>
+<dataflow id="76" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="19">
+</dataflow>
+<dataflow id="77" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="19">
+</dataflow>
+<dataflow id="78" from="_ssdm_op_SpecInterface" to="specinterface_ln0" fromId="53" toId="20">
+</dataflow>
+<dataflow id="79" from="layer13_out" to="specinterface_ln0" fromId="30" toId="20">
+</dataflow>
+<dataflow id="80" from="empty_8" to="specinterface_ln0" fromId="56" toId="20">
+</dataflow>
+<dataflow id="81" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="20">
+</dataflow>
+<dataflow id="82" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="20">
+</dataflow>
+<dataflow id="83" from="empty_9" to="specinterface_ln0" fromId="61" toId="20">
+</dataflow>
+<dataflow id="84" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="20">
+</dataflow>
+<dataflow id="85" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="20">
+</dataflow>
+<dataflow id="86" from="empty_9" to="specinterface_ln0" fromId="61" toId="20">
+</dataflow>
+<dataflow id="87" from="empty_9" to="specinterface_ln0" fromId="61" toId="20">
+</dataflow>
+<dataflow id="88" from="empty_9" to="specinterface_ln0" fromId="61" toId="20">
+</dataflow>
+<dataflow id="89" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="20">
+</dataflow>
+<dataflow id="90" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="20">
+</dataflow>
+<dataflow id="91" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="20">
+</dataflow>
+<dataflow id="92" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="20">
+</dataflow>
+<dataflow id="93" from="empty_9" to="specinterface_ln0" fromId="61" toId="20">
+</dataflow>
+<dataflow id="94" from="empty_9" to="specinterface_ln0" fromId="61" toId="20">
+</dataflow>
+<dataflow id="95" from="StgValue_74" to="specinterface_ln0" fromId="74" toId="20">
+</dataflow>
+<dataflow id="96" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="20">
+</dataflow>
+<dataflow id="97" from="StgValue_58" to="specinterface_ln0" fromId="58" toId="20">
+</dataflow>
+<dataflow id="98" from="zeropad2d_cl<array,array<ap_fixed,32u>,config49>_Pipeline_PadBottomWidth" to="call_ln0" fromId="50" toId="21">
+</dataflow>
+<dataflow id="99" from="layer49_out" to="call_ln0" fromId="31" toId="21">
+</dataflow>
+</dataflows>
+
+
+</stg>

myproject_prj/solution1/.autopilot/db/zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config52_s.compgen.tcl

@@ -0,0 +1,103 @@
+# This script segment is generated automatically by AutoPilot
+
+# clear list
+if {${::AESL::PGuard_autoexp_gen}} {
+    cg_default_interface_gen_dc_begin
+    cg_default_interface_gen_bundle_begin
+    AESL_LIB_XILADAPTER::native_axis_begin
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 2277 \
+    name layer16_out \
+    type fifo \
+    dir I \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_layer16_out \
+    op interface \
+    ports { layer16_out_dout { I 512 vector } layer16_out_num_data_valid { I 7 vector } layer16_out_fifo_cap { I 7 vector } layer16_out_empty_n { I 1 bit } layer16_out_read { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 2278 \
+    name layer52_out \
+    type fifo \
+    dir O \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_layer52_out \
+    op interface \
+    ports { layer52_out_din { O 512 vector } layer52_out_num_data_valid { I 8 vector } layer52_out_fifo_cap { I 8 vector } layer52_out_full_n { I 1 bit } layer52_out_write { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id -1 \
+    name ap_ctrl \
+    type ap_ctrl \
+    reset_level 1 \
+    sync_rst true \
+    corename ap_ctrl \
+    op interface \
+    ports { ap_start { I 1 bit } ap_ready { O 1 bit } ap_done { O 1 bit } ap_idle { O 1 bit } ap_continue { I 1 bit } } \
+} "
+}
+
+
+# Adapter definition:
+set PortName ap_clk
+set DataWd 1 
+if {${::AESL::PGuard_autoexp_gen}} {
+if {[info proc cg_default_interface_gen_clock] == "cg_default_interface_gen_clock"} {
+eval "cg_default_interface_gen_clock { \
+    id -2 \
+    name ${PortName} \
+    reset_level 1 \
+    sync_rst true \
+    corename apif_ap_clk \
+    data_wd ${DataWd} \
+    op interface \
+}"
+} else {
+puts "@W \[IMPL-113\] Cannot find bus interface model in the library. Ignored generation of bus interface for '${PortName}'"
+}
+}
+
+
+# Adapter definition:
+set PortName ap_rst
+set DataWd 1 
+if {${::AESL::PGuard_autoexp_gen}} {
+if {[info proc cg_default_interface_gen_reset] == "cg_default_interface_gen_reset"} {
+eval "cg_default_interface_gen_reset { \
+    id -3 \
+    name ${PortName} \
+    reset_level 1 \
+    sync_rst true \
+    corename apif_ap_rst \
+    data_wd ${DataWd} \
+    op interface \
+}"
+} else {
+puts "@W \[IMPL-114\] Cannot find bus interface model in the library. Ignored generation of bus interface for '${PortName}'"
+}
+}
+
+
+
+# merge
+if {${::AESL::PGuard_autoexp_gen}} {
+    cg_default_interface_gen_dc_end
+    cg_default_interface_gen_bundle_end
+    AESL_LIB_XILADAPTER::native_axis_end
+}
+
+

myproject_prj/solution1/.autopilot/db/zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config55_Pipeline_PadMain.verbose.sched.rpt.xml

@@ -0,0 +1,46 @@
+<profile>
+
+<section name = "Vitis HLS Report for 'zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config55_Pipeline_PadMain'" level="0">
+<item name = "Date">Tue Mar 31 03:26:46 2026
+</item>
+<item name = "Version">2024.1 (Build 5069499 on May 21 2024)</item>
+<item name = "Project">myproject_prj</item>
+<item name = "Solution">solution1 (Vivado IP Flow Target)</item>
+<item name = "Product family">virtexuplusHBM</item>
+<item name = "Target device">xcvu47p-fsvh2892-2L-e</item>
+</section>
+
+<section name = "Performance Estimates" level="0">
+<item name = "Timing">
+<section name = "" level="1">
+<item name = "Summary"><table name="" hasTotal="0">
+<keys size="4">Clock, Target, Estimated, Uncertainty</keys>
+<column name="ap_clk">5.00 ns, 1.481 ns, 1.35 ns</column>
+</table>
+</item>
+</section>
+</item>
+<item name = "Latency">
+<section name = "" level="1">
+<item name = "Summary"><table name="" hasTotal="0">
+<keys size="8">, min, max, min, max, min, max, Type</keys>
+<column name="">290, 290, 1.450 us, 1.450 us, 289, 289, loop auto-rewind stp(delay=0 clock cycles(s))</column>
+</table>
+</item>
+<item name = "Detail">
+<section name = "" level="1">
+<item name = "Instance"><table name="" hasTotal="0">
+<keys size="9">Instance, Module, min, max, min, max, min, max, Type</keys>
+</table>
+</item>
+<item name = "Loop"><table name="" hasTotal="0">
+<keys size="8">Loop Name, min, max, Latency, achieved, target, Count, Pipelined</keys>
+<column name="- PadMain">288, 288, 19, 18, 1, 16, yes</column>
+</table>
+</item>
+</section>
+</item>
+</section>
+</item>
+</section>
+</profile>

myproject_prj/solution1/.autopilot/db/zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadTopWidth.verbose.rpt

@@ -0,0 +1,591 @@
+
+
+================================================================
+== Vitis HLS Report for 'zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadTopWidth'
+================================================================
+* Date:           Sun Apr  5 21:50:01 2026
+
+* Version:        2024.1 (Build 5069499 on May 21 2024)
+* Project:        myproject_prj
+* Solution:       solution1 (Vivado IP Flow Target)
+* Product family: virtexuplusHBM
+* Target device:  xcvu47p-fsvh2892-2L-e
+
+
+================================================================
+== Performance Estimates
+================================================================
++ Timing: 
+    * Summary: 
+    +--------+---------+----------+------------+
+    |  Clock |  Target | Estimated| Uncertainty|
+    +--------+---------+----------+------------+
+    |ap_clk  |  4.00 ns|  1.480 ns|     1.35 ns|
+    +--------+---------+----------+------------+
+
++ Latency: 
+    * Summary: 
+    +---------+---------+----------+----------+-----+-----+-----------------------------------------------+
+    |  Latency (cycles) |  Latency (absolute) |  Interval |                    Pipeline                   |
+    |   min   |   max   |    min   |    max   | min | max |                      Type                     |
+    +---------+---------+----------+----------+-----+-----+-----------------------------------------------+
+    |       36|       36|  0.144 us|  0.144 us|   35|   35|  loop auto-rewind stp(delay=0 clock cycles(s))|
+    +---------+---------+----------+----------+-----+-----+-----------------------------------------------+
+
+    + Detail: 
+        * Instance: 
+        N/A
+
+        * Loop: 
+        +---------------+---------+---------+----------+-----------+-----------+------+----------+
+        |               |  Latency (cycles) | Iteration|  Initiation Interval  | Trip |          |
+        |   Loop Name   |   min   |   max   |  Latency |  achieved |   target  | Count| Pipelined|
+        +---------------+---------+---------+----------+-----------+-----------+------+----------+
+        |- PadTopWidth  |       34|       34|         2|          1|          1|    34|       yes|
+        +---------------+---------+---------+----------+-----------+-----------+------+----------+
+
+
+
+================================================================
+== Utilization Estimates
+================================================================
+* Summary: 
++---------------------+---------+------+---------+---------+-----+
+|         Name        | BRAM_18K|  DSP |    FF   |   LUT   | URAM|
++---------------------+---------+------+---------+---------+-----+
+|DSP                  |        -|     -|        -|        -|    -|
+|Expression           |        -|     -|        0|       30|    -|
+|FIFO                 |        -|     -|        -|        -|    -|
+|Instance             |        -|     -|        -|        -|    -|
+|Memory               |        -|     -|        -|        -|    -|
+|Multiplexer          |        -|     -|        0|       45|    -|
+|Register             |        -|     -|        9|        -|    -|
++---------------------+---------+------+---------+---------+-----+
+|Total                |        0|     0|        9|       75|    0|
++---------------------+---------+------+---------+---------+-----+
+|Available SLR        |     1344|  3008|   869120|   434560|  320|
++---------------------+---------+------+---------+---------+-----+
+|Utilization SLR (%)  |        0|     0|       ~0|       ~0|    0|
++---------------------+---------+------+---------+---------+-----+
+|Available            |     4032|  9024|  2607360|  1303680|  960|
++---------------------+---------+------+---------+---------+-----+
+|Utilization (%)      |        0|     0|       ~0|       ~0|    0|
++---------------------+---------+------+---------+---------+-----+
+
++ Detail: 
+    * Instance: 
+    N/A
+
+    * DSP: 
+    N/A
+
+    * Memory: 
+    N/A
+
+    * FIFO: 
+    N/A
+
+    * Expression: 
+    +---------------------------+----------+----+---+----+------------+------------+
+    |       Variable Name       | Operation| DSP| FF| LUT| Bitwidth P0| Bitwidth P1|
+    +---------------------------+----------+----+---+----+------------+------------+
+    |j_35_fu_60_p2              |         +|   0|  0|  13|           6|           1|
+    |ap_block_pp0_stage0_01001  |       and|   0|  0|   2|           1|           1|
+    |icmp_ln53_fu_54_p2         |      icmp|   0|  0|  13|           6|           6|
+    |ap_enable_pp0              |       xor|   0|  0|   2|           1|           2|
+    +---------------------------+----------+----+---+----+------------+------------+
+    |Total                      |          |   0|  0|  30|          14|          10|
+    +---------------------------+----------+----+---+----+------------+------------+
+
+    * Multiplexer: 
+    +-------------------------+----+-----------+-----+-----------+
+    |           Name          | LUT| Input Size| Bits| Total Bits|
+    +-------------------------+----+-----------+-----+-----------+
+    |ap_done_int              |   9|          2|    1|          2|
+    |ap_enable_reg_pp0_iter1  |   9|          2|    1|          2|
+    |ap_sig_allocacmp_j_34    |   9|          2|    6|         12|
+    |j_fu_34                  |   9|          2|    6|         12|
+    |layer55_out_blk_n        |   9|          2|    1|          2|
+    +-------------------------+----+-----------+-----+-----------+
+    |Total                    |  45|         10|   15|         30|
+    +-------------------------+----+-----------+-----+-----------+
+
+    * Register: 
+    +-------------------------+---+----+-----+-----------+
+    |           Name          | FF| LUT| Bits| Const Bits|
+    +-------------------------+---+----+-----+-----------+
+    |ap_CS_fsm                |  1|   0|    1|          0|
+    |ap_done_reg              |  1|   0|    1|          0|
+    |ap_enable_reg_pp0_iter1  |  1|   0|    1|          0|
+    |j_fu_34                  |  6|   0|    6|          0|
+    +-------------------------+---+----+-----+-----------+
+    |Total                    |  9|   0|    9|          0|
+    +-------------------------+---+----+-----+-----------+
+
+
+
+================================================================
+== Interface
+================================================================
+* Summary: 
++----------------------------+-----+-----+------------+-----------------------------------------------------------------------+--------------+
+|          RTL Ports         | Dir | Bits|  Protocol  |                             Source Object                             |    C Type    |
++----------------------------+-----+-----+------------+-----------------------------------------------------------------------+--------------+
+|ap_clk                      |   in|    1|  ap_ctrl_hs|  zeropad2d_cl<array,array<ap_fixed,16u>,config55>_Pipeline_PadTopWidth|  return value|
+|ap_rst                      |   in|    1|  ap_ctrl_hs|  zeropad2d_cl<array,array<ap_fixed,16u>,config55>_Pipeline_PadTopWidth|  return value|
+|ap_start                    |   in|    1|  ap_ctrl_hs|  zeropad2d_cl<array,array<ap_fixed,16u>,config55>_Pipeline_PadTopWidth|  return value|
+|ap_done                     |  out|    1|  ap_ctrl_hs|  zeropad2d_cl<array,array<ap_fixed,16u>,config55>_Pipeline_PadTopWidth|  return value|
+|ap_idle                     |  out|    1|  ap_ctrl_hs|  zeropad2d_cl<array,array<ap_fixed,16u>,config55>_Pipeline_PadTopWidth|  return value|
+|ap_ready                    |  out|    1|  ap_ctrl_hs|  zeropad2d_cl<array,array<ap_fixed,16u>,config55>_Pipeline_PadTopWidth|  return value|
+|layer55_out_din             |  out|  256|     ap_fifo|                                                            layer55_out|       pointer|
+|layer55_out_num_data_valid  |   in|   12|     ap_fifo|                                                            layer55_out|       pointer|
+|layer55_out_fifo_cap        |   in|   12|     ap_fifo|                                                            layer55_out|       pointer|
+|layer55_out_full_n          |   in|    1|     ap_fifo|                                                            layer55_out|       pointer|
+|layer55_out_write           |  out|    1|     ap_fifo|                                                            layer55_out|       pointer|
++----------------------------+-----+-----+------------+-----------------------------------------------------------------------+--------------+
+
+============================================================
++ Verbose Summary: Synthesis Manager
+============================================================
+InlineROM: 1
+ExposeGlobal: 0
+============================================================
++ Verbose Summary: CDFG Model
+============================================================
+IsTopModel: 0
+ResetActiveHigh: 1
+IsCombinational: 2
+IsDatapathOnly: 2
+HasWiredReturn: 1
+HasMFsm: 2
+HasVarLatency: 1
+IsPipeline: 0
+IsRtlPipelined: 0
+IsInstanceOverlapped: 0
+IsDontTouch: 0
+HasImplIP: 0
+IsGatedGlobalClock: 0
+
++ Individual pipeline summary: 
+  * Pipeline-0: initiation interval (II) = 1, depth = 2
+
+
+============================================================
++ Verbose Summary: Schedule
+============================================================
+* Number of FSM states : 2
+* Pipeline : 1
+  Pipeline-0 : II = 1, D = 2, States = { 1 2 }
+* Dataflow Pipeline: 0
+
+* FSM state transitions: 
+1 --> 2 
+2 --> 
+
+* FSM state operations: 
+
+State 1 <SV = 0> <Delay = 1.48>
+ST_1 : Operation 5 [1/1] (0.00ns)   --->   "%j = alloca i32 1" [firmware/nnet_utils/nnet_padding_stream.h:53]   --->   Operation 5 'alloca' 'j' <Predicate = true> <Delay = 0.00>
+ST_1 : Operation 6 [1/1] (0.00ns)   --->   "%specinterface_ln0 = specinterface void @_ssdm_op_SpecInterface, i256 %layer55_out, void @empty_8, i32 0, i32 0, void @empty_9, i32 0, i32 0, void @empty_9, void @empty_9, void @empty_9, i32 0, i32 0, i32 0, i32 0, void @empty_9, void @empty_9, i32 4294967295, i32 0, i32 0"   --->   Operation 6 'specinterface' 'specinterface_ln0' <Predicate = true> <Delay = 0.00>
+ST_1 : Operation 7 [1/1] (0.38ns)   --->   "%store_ln53 = store i6 0, i6 %j" [firmware/nnet_utils/nnet_padding_stream.h:53]   --->   Operation 7 'store' 'store_ln53' <Predicate = true> <Delay = 0.38>
+ST_1 : Operation 8 [1/1] (0.00ns)   --->   "%br_ln0 = br void %for.inc"   --->   Operation 8 'br' 'br_ln0' <Predicate = true> <Delay = 0.00>
+ST_1 : Operation 9 [1/1] (0.00ns)   --->   "%j_34 = load i6 %j" [firmware/nnet_utils/nnet_padding_stream.h:53]   --->   Operation 9 'load' 'j_34' <Predicate = true> <Delay = 0.00>
+ST_1 : Operation 10 [1/1] (0.70ns)   --->   "%icmp_ln53 = icmp_eq  i6 %j_34, i6 34" [firmware/nnet_utils/nnet_padding_stream.h:53]   --->   Operation 10 'icmp' 'icmp_ln53' <Predicate = true> <Delay = 0.70> <CoreInst = "Cmp">   --->   Core 9 'Cmp' <Latency = 0> <II = 1> <Delay = 0.70> <FuncUnit> <Opcode : 'seteq' 'setne' 'setle' 'setge' 'setlt' 'setgt'> <InPorts = 2> <OutPorts = 1>
+ST_1 : Operation 11 [1/1] (0.70ns)   --->   "%j_35 = add i6 %j_34, i6 1" [firmware/nnet_utils/nnet_padding_stream.h:53]   --->   Operation 11 'add' 'j_35' <Predicate = true> <Delay = 0.70> <CoreInst = "Adder">   --->   Core 1 'Adder' <Latency = 0> <II = 1> <Delay = 0.70> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
+ST_1 : Operation 12 [1/1] (0.00ns)   --->   "%br_ln53 = br i1 %icmp_ln53, void %for.inc.split, void %PadLeft.preheader.exitStub" [firmware/nnet_utils/nnet_padding_stream.h:53]   --->   Operation 12 'br' 'br_ln53' <Predicate = true> <Delay = 0.00>
+ST_1 : Operation 13 [1/1] (0.38ns)   --->   "%store_ln53 = store i6 %j_35, i6 %j" [firmware/nnet_utils/nnet_padding_stream.h:53]   --->   Operation 13 'store' 'store_ln53' <Predicate = (!icmp_ln53)> <Delay = 0.38>
+ST_1 : Operation 19 [1/1] (0.38ns)   --->   "%ret_ln0 = ret"   --->   Operation 19 'ret' 'ret_ln0' <Predicate = (icmp_ln53)> <Delay = 0.38>
+
+State 2 <SV = 1> <Delay = 0.98>
+ST_2 : Operation 14 [1/1] (0.00ns)   --->   "%specpipeline_ln53 = specpipeline void @_ssdm_op_SpecPipeline, i32 4294967295, i32 0, i32 0, i32 0, void @empty_9" [firmware/nnet_utils/nnet_padding_stream.h:53]   --->   Operation 14 'specpipeline' 'specpipeline_ln53' <Predicate = true> <Delay = 0.00>
+ST_2 : Operation 15 [1/1] (0.00ns)   --->   "%speclooptripcount_ln53 = speclooptripcount void @_ssdm_op_SpecLoopTripCount, i64 34, i64 34, i64 34" [firmware/nnet_utils/nnet_padding_stream.h:53]   --->   Operation 15 'speclooptripcount' 'speclooptripcount_ln53' <Predicate = true> <Delay = 0.00>
+ST_2 : Operation 16 [1/1] (0.00ns)   --->   "%specloopname_ln53 = specloopname void @_ssdm_op_SpecLoopName, void @empty_4" [firmware/nnet_utils/nnet_padding_stream.h:53]   --->   Operation 16 'specloopname' 'specloopname_ln53' <Predicate = true> <Delay = 0.00>
+ST_2 : Operation 17 [1/1] (0.98ns)   --->   "%write_ln15 = write void @_ssdm_op_Write.ap_fifo.volatile.i256P0A, i256 %layer55_out, i256 0" [firmware/nnet_utils/nnet_padding_stream.h:15->firmware/nnet_utils/nnet_padding_stream.h:54]   --->   Operation 17 'write' 'write_ln15' <Predicate = true> <Delay = 0.98> <CoreInst = "FIFO">   --->   Core 77 'FIFO' <Latency = 0> <II = 1> <Delay = 0.98> <Storage> <Opcode : 'read' 'write' 'nbread' 'nbwrite'> <Ports = 0> <Width = 256> <Depth = 1156> <FIFO>
+ST_2 : Operation 18 [1/1] (0.00ns)   --->   "%br_ln53 = br void %for.inc" [firmware/nnet_utils/nnet_padding_stream.h:53]   --->   Operation 18 'br' 'br_ln53' <Predicate = true> <Delay = 0.00>
+
+
+============================================================
++ Verbose Summary: Binding
+============================================================
+STG Binding: 
+---------------- STG Properties BEGIN ----------------
+- Is combinational: 0
+- Is one-state seq: 0
+- Is datapath-only: 0
+- Is pipelined: 0
+- Is top level: 0
+Port [ Return ] is wired: 1; IO mode=ap_ctrl_hs:ce=0
+Port [ layer55_out]:  wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=1; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
+---------------- STG Properties END ------------------
+
+---------------- Datapath Model BEGIN ----------------
+
+<LifeTime>
+<method=bitvector/>
+j                      (alloca           ) [ 010]
+specinterface_ln0      (specinterface    ) [ 000]
+store_ln53             (store            ) [ 000]
+br_ln0                 (br               ) [ 000]
+j_34                   (load             ) [ 000]
+icmp_ln53              (icmp             ) [ 010]
+j_35                   (add              ) [ 000]
+br_ln53                (br               ) [ 000]
+store_ln53             (store            ) [ 000]
+specpipeline_ln53      (specpipeline     ) [ 000]
+speclooptripcount_ln53 (speclooptripcount) [ 000]
+specloopname_ln53      (specloopname     ) [ 000]
+write_ln15             (write            ) [ 000]
+br_ln53                (br               ) [ 000]
+ret_ln0                (ret              ) [ 000]
+</LifeTime>
+
+<model>
+
+<comp_list>
+<comp id="0" class="1000" name="layer55_out">
+<pin_list>
+<pin id="1" dir="1" index="0" bw="1" slack="0"/>
+</pin_list>
+<bind>
+<StgValue><ssdm name="layer55_out"/></StgValue>
+</bind>
+</comp>
+
+<comp id="2" class="1001" name="const_2">
+<pin_list>
+<pin id="3" dir="1" index="0" bw="1" slack="0"/>
+</pin_list>
+<bind>
+<StgValue><ssdm name=""/></StgValue>
+</bind>
+</comp>
+
+<comp id="4" class="1001" name="const_4">
+<pin_list>
+<pin id="5" dir="1" index="0" bw="1" slack="2147483647"/>
+</pin_list>
+<bind>
+<StgValue><ssdm name="_ssdm_op_SpecInterface"/></StgValue>
+</bind>
+</comp>
+
+<comp id="6" class="1001" name="const_6">
+<pin_list>
+<pin id="7" dir="1" index="0" bw="1" slack="2147483647"/>
+</pin_list>
+<bind>
+<StgValue><ssdm name="empty_8"/></StgValue>
+</bind>
+</comp>
+
+<comp id="8" class="1001" name="const_8">
+<pin_list>
+<pin id="9" dir="1" index="0" bw="1" slack="2147483647"/>
+</pin_list>
+<bind>
+<StgValue><ssdm name=""/></StgValue>
+</bind>
+</comp>
+
+<comp id="10" class="1001" name="const_10">
+<pin_list>
+<pin id="11" dir="1" index="0" bw="1" slack="2147483647"/>
+</pin_list>
+<bind>
+<StgValue><ssdm name="empty_9"/></StgValue>
+</bind>
+</comp>
+
+<comp id="12" class="1001" name="const_12">
+<pin_list>
+<pin id="13" dir="1" index="0" bw="1" slack="2147483647"/>
+</pin_list>
+<bind>
+<StgValue><ssdm name=""/></StgValue>
+</bind>
+</comp>
+
+<comp id="14" class="1001" name="const_14">
+<pin_list>
+<pin id="15" dir="1" index="0" bw="1" slack="0"/>
+</pin_list>
+<bind>
+<StgValue><ssdm name=""/></StgValue>
+</bind>
+</comp>
+
+<comp id="16" class="1001" name="const_16">
+<pin_list>
+<pin id="17" dir="1" index="0" bw="1" slack="0"/>
+</pin_list>
+<bind>
+<StgValue><ssdm name=""/></StgValue>
+</bind>
+</comp>
+
+<comp id="18" class="1001" name="const_18">
+<pin_list>
+<pin id="19" dir="1" index="0" bw="1" slack="0"/>
+</pin_list>
+<bind>
+<StgValue><ssdm name=""/></StgValue>
+</bind>
+</comp>
+
+<comp id="20" class="1001" name="const_20">
+<pin_list>
+<pin id="21" dir="1" index="0" bw="1" slack="2147483647"/>
+</pin_list>
+<bind>
+<StgValue><ssdm name="_ssdm_op_SpecPipeline"/></StgValue>
+</bind>
+</comp>
+
+<comp id="22" class="1001" name="const_22">
+<pin_list>
+<pin id="23" dir="1" index="0" bw="1" slack="2147483647"/>
+</pin_list>
+<bind>
+<StgValue><ssdm name="_ssdm_op_SpecLoopTripCount"/></StgValue>
+</bind>
+</comp>
+
+<comp id="24" class="1001" name="const_24">
+<pin_list>
+<pin id="25" dir="1" index="0" bw="1" slack="2147483647"/>
+</pin_list>
+<bind>
+<StgValue><ssdm name=""/></StgValue>
+</bind>
+</comp>
+
+<comp id="26" class="1001" name="const_26">
+<pin_list>
+<pin id="27" dir="1" index="0" bw="1" slack="2147483647"/>
+</pin_list>
+<bind>
+<StgValue><ssdm name="_ssdm_op_SpecLoopName"/></StgValue>
+</bind>
+</comp>
+
+<comp id="28" class="1001" name="const_28">
+<pin_list>
+<pin id="29" dir="1" index="0" bw="1" slack="2147483647"/>
+</pin_list>
+<bind>
+<StgValue><ssdm name="empty_4"/></StgValue>
+</bind>
+</comp>
+
+<comp id="30" class="1001" name="const_30">
+<pin_list>
+<pin id="31" dir="1" index="0" bw="1" slack="0"/>
+</pin_list>
+<bind>
+<StgValue><ssdm name="_ssdm_op_Write.ap_fifo.volatile.i256P0A"/></StgValue>
+</bind>
+</comp>
+
+<comp id="32" class="1001" name="const_32">
+<pin_list>
+<pin id="33" dir="1" index="0" bw="1" slack="0"/>
+</pin_list>
+<bind>
+<StgValue><ssdm name=""/></StgValue>
+</bind>
+</comp>
+
+<comp id="34" class="1004" name="j_fu_34">
+<pin_list>
+<pin id="35" dir="0" index="0" bw="1" slack="0"/>
+<pin id="36" dir="1" index="1" bw="6" slack="0"/>
+</pin_list>
+<bind>
+<opcode="alloca(26) " fcode="alloca"/>
+<opset="j/1 "/>
+</bind>
+</comp>
+
+<comp id="38" class="1004" name="write_ln15_write_fu_38">
+<pin_list>
+<pin id="39" dir="0" index="0" bw="0" slack="0"/>
+<pin id="40" dir="0" index="1" bw="256" slack="0"/>
+<pin id="41" dir="0" index="2" bw="1" slack="0"/>
+<pin id="42" dir="1" index="3" bw="0" slack="2147483647"/>
+</pin_list>
+<bind>
+<opcode="write(1151) " fcode="write"/>
+<opset="write_ln15/2 "/>
+</bind>
+</comp>
+
+<comp id="46" class="1004" name="store_ln53_store_fu_46">
+<pin_list>
+<pin id="47" dir="0" index="0" bw="1" slack="0"/>
+<pin id="48" dir="0" index="1" bw="6" slack="0"/>
+<pin id="49" dir="1" index="2" bw="0" slack="2147483647"/>
+</pin_list>
+<bind>
+<opcode="store(28) " fcode="store"/>
+<opset="store_ln53/1 "/>
+</bind>
+</comp>
+
+<comp id="51" class="1004" name="j_34_load_fu_51">
+<pin_list>
+<pin id="52" dir="0" index="0" bw="6" slack="0"/>
+<pin id="53" dir="1" index="1" bw="6" slack="0"/>
+</pin_list>
+<bind>
+<opcode="load(27) " fcode="load"/>
+<opset="j_34/1 "/>
+</bind>
+</comp>
+
+<comp id="54" class="1004" name="icmp_ln53_fu_54">
+<pin_list>
+<pin id="55" dir="0" index="0" bw="6" slack="0"/>
+<pin id="56" dir="0" index="1" bw="6" slack="0"/>
+<pin id="57" dir="1" index="2" bw="1" slack="2147483647"/>
+</pin_list>
+<bind>
+<opcode="icmp(45) " fcode="icmp"/>
+<opset="icmp_ln53/1 "/>
+</bind>
+</comp>
+
+<comp id="60" class="1004" name="j_35_fu_60">
+<pin_list>
+<pin id="61" dir="0" index="0" bw="6" slack="0"/>
+<pin id="62" dir="0" index="1" bw="1" slack="0"/>
+<pin id="63" dir="1" index="2" bw="6" slack="0"/>
+</pin_list>
+<bind>
+<opcode="add(8) " fcode="add"/>
+<opset="j_35/1 "/>
+</bind>
+</comp>
+
+<comp id="66" class="1004" name="store_ln53_store_fu_66">
+<pin_list>
+<pin id="67" dir="0" index="0" bw="6" slack="0"/>
+<pin id="68" dir="0" index="1" bw="6" slack="0"/>
+<pin id="69" dir="1" index="2" bw="0" slack="2147483647"/>
+</pin_list>
+<bind>
+<opcode="store(28) " fcode="store"/>
+<opset="store_ln53/1 "/>
+</bind>
+</comp>
+
+<comp id="71" class="1005" name="j_reg_71">
+<pin_list>
+<pin id="72" dir="0" index="0" bw="6" slack="0"/>
+<pin id="73" dir="1" index="1" bw="6" slack="0"/>
+</pin_list>
+<bind>
+<opset="j "/>
+</bind>
+</comp>
+
+</comp_list>
+
+<net_list>
+<net id="37"><net_src comp="2" pin="0"/><net_sink comp="34" pin=0"/></net>
+
+<net id="43"><net_src comp="30" pin="0"/><net_sink comp="38" pin=0"/></net>
+
+<net id="44"><net_src comp="0" pin="0"/><net_sink comp="38" pin=1"/></net>
+
+<net id="45"><net_src comp="32" pin="0"/><net_sink comp="38" pin=2"/></net>
+
+<net id="50"><net_src comp="14" pin="0"/><net_sink comp="46" pin=0"/></net>
+
+<net id="58"><net_src comp="51" pin="1"/><net_sink comp="54" pin=0"/></net>
+
+<net id="59"><net_src comp="16" pin="0"/><net_sink comp="54" pin=1"/></net>
+
+<net id="64"><net_src comp="51" pin="1"/><net_sink comp="60" pin=0"/></net>
+
+<net id="65"><net_src comp="18" pin="0"/><net_sink comp="60" pin=1"/></net>
+
+<net id="70"><net_src comp="60" pin="2"/><net_sink comp="66" pin=0"/></net>
+
+<net id="74"><net_src comp="34" pin="1"/><net_sink comp="71" pin=0"/></net>
+
+<net id="75"><net_src comp="71" pin="1"/><net_sink comp="46" pin=1"/></net>
+
+<net id="76"><net_src comp="71" pin="1"/><net_sink comp="51" pin=0"/></net>
+
+<net id="77"><net_src comp="71" pin="1"/><net_sink comp="66" pin=1"/></net>
+
+</net_list>
+
+</model> 
+---------------- Datapath Model END ------------------
+
+* FSMD analyzer results:
+  - Output states:
+	Port: layer55_out | {2 }
+ - Input state : 
+	Port: zeropad2d_cl<array,array<ap_fixed,16u>,config55>_Pipeline_PadTopWidth : layer55_out | {}
+  - Chain level:
+	State 1
+		store_ln53 : 1
+		j_34 : 1
+		icmp_ln53 : 2
+		j_35 : 2
+		br_ln53 : 3
+		store_ln53 : 3
+	State 2
+
+
+============================================================
++ Verbose Summary: Datapath Resource usage 
+============================================================
+
+* Functional unit list:
+|----------|------------------------|---------|---------|
+| Operation|     Functional Unit    |    FF   |   LUT   |
+|----------|------------------------|---------|---------|
+|   icmp   |     icmp_ln53_fu_54    |    0    |    13   |
+|----------|------------------------|---------|---------|
+|    add   |       j_35_fu_60       |    0    |    13   |
+|----------|------------------------|---------|---------|
+|   write  | write_ln15_write_fu_38 |    0    |    0    |
+|----------|------------------------|---------|---------|
+|   Total  |                        |    0    |    26   |
+|----------|------------------------|---------|---------|
+
+Memories:
+N/A
+
+* Register list:
++--------+--------+
+|        |   FF   |
++--------+--------+
+|j_reg_71|    6   |
++--------+--------+
+|  Total |    6   |
++--------+--------+
+
+* Multiplexer (MUX) list: 
+|--------|------|------|------|--------|
+|  Comp  |  Pin | Size |  BW  | S x BW |
+|--------|------|------|------|--------|
+|  Total |      |      |      |    0   |
+|--------|------|------|------|--------|
+
+
+
+* Summary:
++-----------+--------+--------+
+|           |   FF   |   LUT  |
++-----------+--------+--------+
+|  Function |    0   |   26   |
+|   Memory  |    -   |    -   |
+|Multiplexer|    -   |    -   |
+|  Register |    6   |    -   |
++-----------+--------+--------+
+|   Total   |    6   |   26   |
++-----------+--------+--------+

myproject_prj/solution1/.autopilot/db/zeropad2d_cl_array_array_ap_fixed_16u_config57_Pipeline_PadBottomWidth.bind.adb

@@ -0,0 +1,1704 @@
+<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
+<!DOCTYPE boost_serialization>
+<boost_serialization signature="serialization::archive" version="17">
+<syndb class_id="0" tracking_level="0" version="0">
+	<userIPLatency>-1</userIPLatency>
+	<userIPName></userIPName>
+	<cdfg class_id="1" tracking_level="1" version="0" object_id="_0">
+		<name>zeropad2d_cl_array_array_ap_fixed_16u_config57_Pipeline_PadBottomWidth</name>
+		<module_structure>Sequential</module_structure>
+		<ret_bitwidth>0</ret_bitwidth>
+		<ports class_id="2" tracking_level="0" version="0">
+			<count>1</count>
+			<item_version>0</item_version>
+			<item class_id="3" tracking_level="1" version="0" object_id="_1">
+				<Value class_id="4" tracking_level="0" version="0">
+					<Obj class_id="5" tracking_level="0" version="0">
+						<type>1</type>
+						<id>1</id>
+						<name>layer57_out</name>
+						<fileName></fileName>
+						<fileDirectory></fileDirectory>
+						<lineNumber>0</lineNumber>
+						<contextFuncName></contextFuncName>
+						<contextNormFuncName></contextNormFuncName>
+						<inlineStackInfo class_id="6" tracking_level="0" version="0">
+							<count>0</count>
+							<item_version>0</item_version>
+						</inlineStackInfo>
+						<originalName></originalName>
+						<rtlName></rtlName>
+						<control></control>
+						<opType></opType>
+						<implIndex></implIndex>
+						<coreName>FIFO</coreName>
+						<isStorage>0</isStorage>
+						<storageDepth>0</storageDepth>
+						<coreId>4294967295</coreId>
+						<rtlModuleName></rtlModuleName>
+					</Obj>
+					<bitwidth>256</bitwidth>
+				</Value>
+				<direction>1</direction>
+				<if_type>3</if_type>
+				<array_size>0</array_size>
+				<bit_vecs class_id="7" tracking_level="0" version="0">
+					<count>0</count>
+					<item_version>0</item_version>
+				</bit_vecs>
+			</item>
+		</ports>
+		<nodes class_id="8" tracking_level="0" version="0">
+			<count>11</count>
+			<item_version>0</item_version>
+			<item class_id="9" tracking_level="1" version="0" object_id="_2">
+				<Value>
+					<Obj>
+						<type>0</type>
+						<id>2</id>
+						<name>j_34</name>
+						<fileName>firmware/nnet_utils/nnet_padding_stream.h</fileName>
+						<fileDirectory>/home/ubuntu/lithobench/hls4ml_mini_unet</fileDirectory>
+						<lineNumber>77</lineNumber>
+						<contextFuncName>zeropad2d_cl&amp;lt;nnet::array&amp;lt;ap_fixed&amp;lt;16, 6, AP_TRN, AP_WRAP, 0&amp;gt;, 16&amp;gt;, nnet::array&amp;lt;ap_fixed&amp;lt;16, 6, AP_TRN, AP_WRAP, 0&amp;gt;, 16&amp;gt;, config57&amp;gt;</contextFuncName>
+						<contextNormFuncName>zeropad2d_cl_nnet_array_ap_fixed_16_6_AP_TRN_AP_WRAP_0_16_nnet_array_ap_fixed_16_6_AP_TRN_AP_WRAP_0_16_config57_s</contextNormFuncName>
+						<inlineStackInfo>
+							<count>1</count>
+							<item_version>0</item_version>
+							<item class_id="10" tracking_level="0" version="0">
+								<first>/home/ubuntu/lithobench/hls4ml_mini_unet</first>
+								<second class_id="11" tracking_level="0" version="0">
+									<count>1</count>
+									<item_version>0</item_version>
+									<item class_id="12" tracking_level="0" version="0">
+										<first class_id="13" tracking_level="0" version="0">
+											<first>firmware/nnet_utils/nnet_padding_stream.h</first>
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+				<source_obj>18</source_obj>
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+			<item class_id_reference="20" object_id="_44">
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+				<is_back_edge>0</is_back_edge>
+			</item>
+			<item class_id_reference="20" object_id="_45">
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+				<edge_type>4</edge_type>
+				<source_obj>7</source_obj>
+				<sink_obj>16</sink_obj>
+				<is_back_edge>0</is_back_edge>
+			</item>
+		</edges>
+	</cdfg>
+	<cdfg_regions class_id="21" tracking_level="0" version="0">
+		<count>4</count>
+		<item_version>0</item_version>
+		<item class_id="22" tracking_level="1" version="0" object_id="_46">
+			<mId>1</mId>
+			<mTag>zeropad2d_cl&lt;array,array&lt;ap_fixed,16u&gt;,config57&gt;_Pipeline_PadBottomWidth</mTag>
+			<mNormTag>zeropad2d_cl_array_array_ap_fixed_16u_config57_Pipeline_PadBottomWidth</mNormTag>
+			<mType>0</mType>
+			<sub_regions>
+				<count>3</count>
+				<item_version>0</item_version>
+				<item>2</item>
+				<item>3</item>
+				<item>4</item>
+			</sub_regions>
+			<basic_blocks>
+				<count>0</count>
+				<item_version>0</item_version>
+			</basic_blocks>
+			<mII>-1</mII>
+			<mDepth>-1</mDepth>
+			<mMinTripCount>-1</mMinTripCount>
+			<mMaxTripCount>-1</mMaxTripCount>
+			<mMinLatency>36</mMinLatency>
+			<mMaxLatency>36</mMaxLatency>
+			<mIsDfPipe>0</mIsDfPipe>
+			<mDfPipe class_id="-1"></mDfPipe>
+		</item>
+		<item class_id_reference="22" object_id="_47">
+			<mId>2</mId>
+			<mTag>Entry</mTag>
+			<mNormTag>Entry</mNormTag>
+			<mType>0</mType>
+			<sub_regions>
+				<count>0</count>
+				<item_version>0</item_version>
+			</sub_regions>
+			<basic_blocks>
+				<count>1</count>
+				<item_version>0</item_version>
+				<item>6</item>
+			</basic_blocks>
+			<mII>-1</mII>
+			<mDepth>-1</mDepth>
+			<mMinTripCount>-1</mMinTripCount>
+			<mMaxTripCount>-1</mMaxTripCount>
+			<mMinLatency>0</mMinLatency>
+			<mMaxLatency>0</mMaxLatency>
+			<mIsDfPipe>0</mIsDfPipe>
+			<mDfPipe class_id="-1"></mDfPipe>
+		</item>
+		<item class_id_reference="22" object_id="_48">
+			<mId>3</mId>
+			<mTag>PadBottomWidth</mTag>
+			<mNormTag>PadBottomWidth</mNormTag>
+			<mType>1</mType>
+			<sub_regions>
+				<count>0</count>
+				<item_version>0</item_version>
+			</sub_regions>
+			<basic_blocks>
+				<count>2</count>
+				<item_version>0</item_version>
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+				<item>18</item>
+			</basic_blocks>
+			<mII>1</mII>
+			<mDepth>2</mDepth>
+			<mMinTripCount>34</mMinTripCount>
+			<mMaxTripCount>34</mMaxTripCount>
+			<mMinLatency>34</mMinLatency>
+			<mMaxLatency>34</mMaxLatency>
+			<mIsDfPipe>0</mIsDfPipe>
+			<mDfPipe class_id="-1"></mDfPipe>
+		</item>
+		<item class_id_reference="22" object_id="_49">
+			<mId>4</mId>
+			<mTag>Return</mTag>
+			<mNormTag>Return</mNormTag>
+			<mType>0</mType>
+			<sub_regions>
+				<count>0</count>
+				<item_version>0</item_version>
+			</sub_regions>
+			<basic_blocks>
+				<count>1</count>
+				<item_version>0</item_version>
+				<item>20</item>
+			</basic_blocks>
+			<mII>-1</mII>
+			<mDepth>-1</mDepth>
+			<mMinTripCount>-1</mMinTripCount>
+			<mMaxTripCount>-1</mMaxTripCount>
+			<mMinLatency>0</mMinLatency>
+			<mMaxLatency>0</mMaxLatency>
+			<mIsDfPipe>0</mIsDfPipe>
+			<mDfPipe class_id="-1"></mDfPipe>
+		</item>
+	</cdfg_regions>
+	<fsm class_id="24" tracking_level="1" version="0" object_id="_50">
+		<states class_id="25" tracking_level="0" version="0">
+			<count>2</count>
+			<item_version>0</item_version>
+			<item class_id="26" tracking_level="1" version="0" object_id="_51">
+				<id>1</id>
+				<operations class_id="27" tracking_level="0" version="0">
+					<count>10</count>
+					<item_version>0</item_version>
+					<item class_id="28" tracking_level="1" version="0" object_id="_52">
+						<id>2</id>
+						<stage>1</stage>
+						<latency>1</latency>
+					</item>
+					<item class_id_reference="28" object_id="_53">
+						<id>3</id>
+						<stage>1</stage>
+						<latency>1</latency>
+					</item>
+					<item class_id_reference="28" object_id="_54">
+						<id>4</id>
+						<stage>1</stage>
+						<latency>1</latency>
+					</item>
+					<item class_id_reference="28" object_id="_55">
+						<id>5</id>
+						<stage>1</stage>
+						<latency>1</latency>
+					</item>
+					<item class_id_reference="28" object_id="_56">
+						<id>7</id>
+						<stage>1</stage>
+						<latency>1</latency>
+					</item>
+					<item class_id_reference="28" object_id="_57">
+						<id>8</id>
+						<stage>1</stage>
+						<latency>1</latency>
+					</item>
+					<item class_id_reference="28" object_id="_58">
+						<id>9</id>
+						<stage>1</stage>
+						<latency>1</latency>
+					</item>
+					<item class_id_reference="28" object_id="_59">
+						<id>10</id>
+						<stage>1</stage>
+						<latency>1</latency>
+					</item>
+					<item class_id_reference="28" object_id="_60">
+						<id>16</id>
+						<stage>1</stage>
+						<latency>1</latency>
+					</item>
+					<item class_id_reference="28" object_id="_61">
+						<id>19</id>
+						<stage>1</stage>
+						<latency>1</latency>
+					</item>
+				</operations>
+			</item>
+			<item class_id_reference="26" object_id="_62">
+				<id>2</id>
+				<operations>
+					<count>5</count>
+					<item_version>0</item_version>
+					<item class_id_reference="28" object_id="_63">
+						<id>12</id>
+						<stage>1</stage>
+						<latency>1</latency>
+					</item>
+					<item class_id_reference="28" object_id="_64">
+						<id>13</id>
+						<stage>1</stage>
+						<latency>1</latency>
+					</item>
+					<item class_id_reference="28" object_id="_65">
+						<id>14</id>
+						<stage>1</stage>
+						<latency>1</latency>
+					</item>
+					<item class_id_reference="28" object_id="_66">
+						<id>15</id>
+						<stage>1</stage>
+						<latency>1</latency>
+					</item>
+					<item class_id_reference="28" object_id="_67">
+						<id>17</id>
+						<stage>1</stage>
+						<latency>1</latency>
+					</item>
+				</operations>
+			</item>
+		</states>
+		<transitions class_id="29" tracking_level="0" version="0">
+			<count>1</count>
+			<item_version>0</item_version>
+			<item class_id="30" tracking_level="1" version="0" object_id="_68">
+				<inState>1</inState>
+				<outState>2</outState>
+				<condition class_id="31" tracking_level="0" version="0">
+					<id>-1</id>
+					<sop class_id="32" tracking_level="0" version="0">
+						<count>1</count>
+						<item_version>0</item_version>
+						<item class_id="33" tracking_level="0" version="0">
+							<count>0</count>
+							<item_version>0</item_version>
+						</item>
+					</sop>
+				</condition>
+			</item>
+		</transitions>
+	</fsm>
+	<res class_id="-1"></res>
+	<node_label_latency class_id="35" tracking_level="0" version="0">
+		<count>11</count>
+		<item_version>0</item_version>
+		<item class_id="36" tracking_level="0" version="0">
+			<first>2</first>
+			<second class_id="37" tracking_level="0" version="0">
+				<first>0</first>
+				<second>0</second>
+			</second>
+		</item>
+		<item>
+			<first>4</first>
+			<second>
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+			</second>
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+			<first>10</first>
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+		</item>
+		<item>
+			<first>16</first>
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+		</item>
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+		</item>
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+			<second>
+				<first>0</first>
+				<second>0</second>
+			</second>
+		</item>
+	</node_label_latency>
+	<bblk_ent_exit class_id="38" tracking_level="0" version="0">
+		<count>4</count>
+		<item_version>0</item_version>
+		<item class_id="39" tracking_level="0" version="0">
+			<first>6</first>
+			<second class_id="40" tracking_level="0" version="0">
+				<first>0</first>
+				<second>0</second>
+			</second>
+		</item>
+		<item>
+			<first>11</first>
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+				<second>1</second>
+			</second>
+		</item>
+		<item>
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+				<first>1</first>
+				<second>2</second>
+			</second>
+		</item>
+		<item>
+			<first>20</first>
+			<second>
+				<first>2</first>
+				<second>2</second>
+			</second>
+		</item>
+	</bblk_ent_exit>
+	<regions class_id="41" tracking_level="0" version="0">
+		<count>1</count>
+		<item_version>0</item_version>
+		<item class_id="42" tracking_level="1" version="0" object_id="_69">
+			<region_name>PadBottomWidth</region_name>
+			<basic_blocks>
+				<count>2</count>
+				<item_version>0</item_version>
+				<item>11</item>
+				<item>18</item>
+			</basic_blocks>
+			<nodes>
+				<count>0</count>
+				<item_version>0</item_version>
+			</nodes>
+			<anchor_node>-1</anchor_node>
+			<region_type>8</region_type>
+			<interval>1</interval>
+			<pipe_depth>2</pipe_depth>
+			<mDBIIViolationVec class_id="43" tracking_level="0" version="0">
+				<count>0</count>
+				<item_version>0</item_version>
+			</mDBIIViolationVec>
+		</item>
+	</regions>
+	<dp_fu_nodes class_id="44" tracking_level="0" version="0">
+		<count>7</count>
+		<item_version>0</item_version>
+		<item class_id="45" tracking_level="0" version="0">
+			<first>34</first>
+			<second>
+				<count>1</count>
+				<item_version>0</item_version>
+				<item>2</item>
+			</second>
+		</item>
+		<item>
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+			<second>
+				<count>1</count>
+				<item_version>0</item_version>
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+			</second>
+		</item>
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+		</item>
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+				<item_version>0</item_version>
+				<item>8</item>
+			</second>
+		</item>
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+				<item_version>0</item_version>
+				<item>9</item>
+			</second>
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+			<second>
+				<count>1</count>
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+			</second>
+		</item>
+	</dp_fu_nodes>
+	<dp_fu_nodes_expression class_id="47" tracking_level="0" version="0">
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+		<item_version>0</item_version>
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+		</item>
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+		</item>
+		<item>
+			<first>j_36_fu_60</first>
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+				<count>1</count>
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+		</item>
+	</dp_fu_nodes_expression>
+	<dp_fu_nodes_module>
+		<count>0</count>
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+	</dp_fu_nodes_module>
+	<dp_fu_nodes_io>
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+			<first>j_load_fu_51</first>
+			<second>
+				<count>1</count>
+				<item_version>0</item_version>
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+			</second>
+		</item>
+		<item>
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+				<count>1</count>
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+		<item>
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+			<second>
+				<count>1</count>
+				<item_version>0</item_version>
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+			</second>
+		</item>
+	</dp_fu_nodes_io>
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+		<count>0</count>
+		<item_version>0</item_version>
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+	</dp_mem_port_nodes>
+	<dp_reg_nodes>
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+			<second>
+				<count>1</count>
+				<item_version>0</item_version>
+				<item>2</item>
+			</second>
+		</item>
+	</dp_reg_nodes>
+	<dp_regname_nodes>
+		<count>1</count>
+		<item_version>0</item_version>
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+			<first>j_34_reg_71</first>
+			<second>
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+				<item_version>0</item_version>
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+			</second>
+		</item>
+	</dp_regname_nodes>
+	<dp_reg_phi>
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+	</dp_reg_phi>
+	<dp_regname_phi>
+		<count>0</count>
+		<item_version>0</item_version>
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+	<dp_port_io_nodes class_id="50" tracking_level="0" version="0">
+		<count>1</count>
+		<item_version>0</item_version>
+		<item class_id="51" tracking_level="0" version="0">
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+					<second>
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+						<item_version>0</item_version>
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+				</item>
+			</second>
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+		<item_version>0</item_version>
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+			<first>1</first>
+			<second>
+				<first>666</first>
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+		</item>
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+		<item_version>0</item_version>
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+			<first>8</first>
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+				<first>526</first>
+				<second>0</second>
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+		</item>
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+				<first>8</first>
+				<second>4</second>
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+		</item>
+		<item>
+			<first>15</first>
+			<second>
+				<first>666</first>
+				<second>7</second>
+			</second>
+		</item>
+	</node2core>
+</syndb>
+</boost_serialization>
+

myproject_prj/solution1/.autopilot/db/zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadBottomWidth.compgen.tcl

@@ -0,0 +1,109 @@
+# This script segment is generated automatically by AutoPilot
+
+# clear list
+if {${::AESL::PGuard_autoexp_gen}} {
+    cg_default_interface_gen_dc_begin
+    cg_default_interface_gen_bundle_begin
+    AESL_LIB_XILADAPTER::native_axis_begin
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id 6079 \
+    name layer53_out \
+    type fifo \
+    dir O \
+    reset_level 1 \
+    sync_rst true \
+    corename dc_layer53_out \
+    op interface \
+    ports { layer53_out_din { O 512 vector } layer53_out_num_data_valid { I 10 vector } layer53_out_fifo_cap { I 10 vector } layer53_out_full_n { I 1 bit } layer53_out_write { O 1 bit } } \
+} "
+}
+
+# Direct connection:
+if {${::AESL::PGuard_autoexp_gen}} {
+eval "cg_default_interface_gen_dc { \
+    id -1 \
+    name ap_ctrl \
+    type ap_ctrl \
+    reset_level 1 \
+    sync_rst true \
+    corename ap_ctrl \
+    op interface \
+    ports { ap_start { I 1 bit } ap_ready { O 1 bit } ap_done { O 1 bit } ap_idle { O 1 bit } } \
+} "
+}
+
+
+# Adapter definition:
+set PortName ap_clk
+set DataWd 1 
+if {${::AESL::PGuard_autoexp_gen}} {
+if {[info proc cg_default_interface_gen_clock] == "cg_default_interface_gen_clock"} {
+eval "cg_default_interface_gen_clock { \
+    id -2 \
+    name ${PortName} \
+    reset_level 1 \
+    sync_rst true \
+    corename apif_ap_clk \
+    data_wd ${DataWd} \
+    op interface \
+}"
+} else {
+puts "@W \[IMPL-113\] Cannot find bus interface model in the library. Ignored generation of bus interface for '${PortName}'"
+}
+}
+
+
+# Adapter definition:
+set PortName ap_rst
+set DataWd 1 
+if {${::AESL::PGuard_autoexp_gen}} {
+if {[info proc cg_default_interface_gen_reset] == "cg_default_interface_gen_reset"} {
+eval "cg_default_interface_gen_reset { \
+    id -3 \
+    name ${PortName} \
+    reset_level 1 \
+    sync_rst true \
+    corename apif_ap_rst \
+    data_wd ${DataWd} \
+    op interface \
+}"
+} else {
+puts "@W \[IMPL-114\] Cannot find bus interface model in the library. Ignored generation of bus interface for '${PortName}'"
+}
+}
+
+
+
+# merge
+if {${::AESL::PGuard_autoexp_gen}} {
+    cg_default_interface_gen_dc_end
+    cg_default_interface_gen_bundle_end
+    AESL_LIB_XILADAPTER::native_axis_end
+}
+
+
+# flow_control definition:
+set InstName myproject_flow_control_loop_pipe_sequential_init_U
+set CompName myproject_flow_control_loop_pipe_sequential_init
+set name flow_control_loop_pipe_sequential_init
+if {${::AESL::PGuard_autocg_gen} && ${::AESL::PGuard_autocg_ipmgen}} {
+if {[info proc ::AESL_LIB_VIRTEX::xil_gen_UPC_flow_control] == "::AESL_LIB_VIRTEX::xil_gen_UPC_flow_control"} {
+eval "::AESL_LIB_VIRTEX::xil_gen_UPC_flow_control { \
+    name ${name} \
+    prefix myproject_ \
+}"
+} else {
+puts "@W \[IMPL-107\] Cannot find ::AESL_LIB_VIRTEX::xil_gen_UPC_flow_control, check your platform lib"
+}
+}
+
+
+if {${::AESL::PGuard_rtl_comp_handler}} {
+	::AP::rtl_comp_handler $CompName BINDTYPE interface TYPE internal_upc_flow_control INSTNAME $InstName
+}
+
+

myproject_prj/solution1/.autopilot/db/zeropad2d_cl_array_array_ap_fixed_32u_config55_Pipeline_PadTopWidth.verbose.rpt.xml

@@ -0,0 +1,127 @@
+<profile>
+
+<section name = "Vitis HLS Report for 'zeropad2d_cl_array_array_ap_fixed_32u_config55_Pipeline_PadTopWidth'" level="0">
+<item name = "Date">Tue Mar 31 03:35:58 2026
+</item>
+<item name = "Version">2024.1 (Build 5069499 on May 21 2024)</item>
+<item name = "Project">myproject_prj</item>
+<item name = "Solution">solution1 (Vivado IP Flow Target)</item>
+<item name = "Product family">virtexuplusHBM</item>
+<item name = "Target device">xcvu47p-fsvh2892-2L-e</item>
+</section>
+
+<section name = "Performance Estimates" level="0">
+<item name = "Timing">
+<section name = "" level="1">
+<item name = "Summary"><table name="" hasTotal="0">
+<keys size="4">Clock, Target, Estimated, Uncertainty</keys>
+<column name="ap_clk">5.00 ns, 1.481 ns, 1.35 ns</column>
+</table>
+</item>
+</section>
+</item>
+<item name = "Latency">
+<section name = "" level="1">
+<item name = "Summary"><table name="" hasTotal="0">
+<keys size="8">, min, max, min, max, min, max, Type</keys>
+<column name="">20, 20, 0.100 us, 0.100 us, 19, 19, loop auto-rewind stp(delay=0 clock cycles(s))</column>
+</table>
+</item>
+<item name = "Detail">
+<section name = "" level="1">
+<item name = "Instance"><table name="" hasTotal="0">
+<keys size="9">Instance, Module, min, max, min, max, min, max, Type</keys>
+</table>
+</item>
+<item name = "Loop"><table name="" hasTotal="0">
+<keys size="8">Loop Name, min, max, Latency, achieved, target, Count, Pipelined</keys>
+<column name="- PadTopWidth">18, 18, 2, 1, 1, 18, yes</column>
+</table>
+</item>
+</section>
+</item>
+</section>
+</item>
+</section>
+
+<section name = "Utilization Estimates" level="0">
+<item name = "Summary"><table name="" hasTotal="1">
+<keys size="6">Name, BRAM_18K, DSP, FF, LUT, URAM</keys>
+<column name="DSP">-, -, -, -, -</column>
+<column name="Expression">-, -, 0, 28, -</column>
+<column name="FIFO">-, -, -, -, -</column>
+<column name="Instance">-, -, -, -, -</column>
+<column name="Memory">-, -, -, -, -</column>
+<column name="Multiplexer">-, -, 0, 45, -</column>
+<column name="Register">-, -, 8, -, -</column>
+<specialColumn name="Available SLR">1344, 3008, 869120, 434560, 320</specialColumn>
+<specialColumn name="Utilization SLR (%)">0, 0, ~0, ~0, 0</specialColumn>
+<specialColumn name="Available">4032, 9024, 2607360, 1303680, 960</specialColumn>
+<specialColumn name="Utilization (%)">0, 0, ~0, ~0, 0</specialColumn>
+</table>
+</item>
+<item name = "Detail">
+<section name = "" level="1">
+<item name = "Instance"><table name="" hasTotal="1">
+<keys size="7">Instance, Module, BRAM_18K, DSP, FF, LUT, URAM</keys>
+</table>
+</item>
+<item name = "DSP"><table name="" hasTotal="0">
+<keys size="3">Instance, Module, Expression</keys>
+</table>
+</item>
+<item name = "Memory"><table name="" hasTotal="1">
+<keys size="10">Memory, Module, BRAM_18K, FF, LUT, URAM, Words, Bits, Banks, W*Bits*Banks</keys>
+</table>
+</item>
+<item name = "FIFO"><table name="" hasTotal="1">
+<keys size="8">Name, BRAM_18K, FF, LUT, URAM, Depth, Bits, Size:D*B</keys>
+</table>
+</item>
+<item name = "Expression"><table name="" hasTotal="1">
+<keys size="7">Variable Name, Operation, DSP, FF, LUT, Bitwidth P0, Bitwidth P1</keys>
+<column name="j_22_fu_60_p2">+, 0, 0, 12, 5, 1</column>
+<column name="ap_block_pp0_stage0_01001">and, 0, 0, 2, 1, 1</column>
+<column name="icmp_ln53_fu_54_p2">icmp, 0, 0, 12, 5, 5</column>
+<column name="ap_enable_pp0">xor, 0, 0, 2, 1, 2</column>
+</table>
+</item>
+<item name = "Multiplexer"><table name="" hasTotal="1">
+<keys size="5">Name, LUT, Input Size, Bits, Total Bits</keys>
+<column name="ap_done_int">9, 2, 1, 2</column>
+<column name="ap_enable_reg_pp0_iter1">9, 2, 1, 2</column>
+<column name="ap_sig_allocacmp_j_21">9, 2, 5, 10</column>
+<column name="j_fu_34">9, 2, 5, 10</column>
+<column name="layer55_out_blk_n">9, 2, 1, 2</column>
+</table>
+</item>
+<item name = "Register"><table name="" hasTotal="1">
+<keys size="5">Name, FF, LUT, Bits, Const Bits</keys>
+<column name="ap_CS_fsm">1, 0, 1, 0</column>
+<column name="ap_done_reg">1, 0, 1, 0</column>
+<column name="ap_enable_reg_pp0_iter1">1, 0, 1, 0</column>
+<column name="j_fu_34">5, 0, 5, 0</column>
+</table>
+</item>
+</section>
+</item>
+</section>
+
+<section name = "Interface" level="0">
+<item name = "Summary"><table name="" hasTotal="0">
+<keys size="6">RTL Ports, Dir, Bits, Protocol, Source Object, C Type</keys>
+<column name="ap_clk">in, 1, ap_ctrl_hs, zeropad2d_cl&lt;array,array&lt;ap_fixed,32u&gt;,config55&gt;_Pipeline_PadTopWidth, return value</column>
+<column name="ap_rst">in, 1, ap_ctrl_hs, zeropad2d_cl&lt;array,array&lt;ap_fixed,32u&gt;,config55&gt;_Pipeline_PadTopWidth, return value</column>
+<column name="ap_start">in, 1, ap_ctrl_hs, zeropad2d_cl&lt;array,array&lt;ap_fixed,32u&gt;,config55&gt;_Pipeline_PadTopWidth, return value</column>
+<column name="ap_done">out, 1, ap_ctrl_hs, zeropad2d_cl&lt;array,array&lt;ap_fixed,32u&gt;,config55&gt;_Pipeline_PadTopWidth, return value</column>
+<column name="ap_idle">out, 1, ap_ctrl_hs, zeropad2d_cl&lt;array,array&lt;ap_fixed,32u&gt;,config55&gt;_Pipeline_PadTopWidth, return value</column>
+<column name="ap_ready">out, 1, ap_ctrl_hs, zeropad2d_cl&lt;array,array&lt;ap_fixed,32u&gt;,config55&gt;_Pipeline_PadTopWidth, return value</column>
+<column name="layer55_out_din">out, 512, ap_fifo, layer55_out, pointer</column>
+<column name="layer55_out_num_data_valid">in, 10, ap_fifo, layer55_out, pointer</column>
+<column name="layer55_out_fifo_cap">in, 10, ap_fifo, layer55_out, pointer</column>
+<column name="layer55_out_full_n">in, 1, ap_fifo, layer55_out, pointer</column>
+<column name="layer55_out_write">out, 1, ap_fifo, layer55_out, pointer</column>
+</table>
+</item>
+</section>
+</profile>

myproject_prj/solution1/.autopilot/db/zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadBottomWidth.compgen.dataonly.tcl

@@ -0,0 +1,2 @@
+# This script segment is generated automatically by AutoPilot
+

myproject_prj/solution1/.debug/myproject.protoinst

@@ -0,0 +1,1545 @@
+{
+	"version": "1.0",
+	"modules": {
+		"myproject": {
+			"proto_instances": {
+				"/AESL_inst_myproject_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst_n"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_U0/clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_U0/clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_U0/clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_U0/concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_U0/grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18/grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_U0/concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_U0/grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_fu_18/grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_fu_18_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_U0/concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_U0/grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s_fu_18/grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s_fu_18_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_U0/conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config9_s_fu_468/call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_fu_541/call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config9_s_fu_541_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config9_s_fu_468/grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config9_s_fu_468_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_config9_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config9_s_fu_468/grp_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s_fu_929/grp_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s_fu_929_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_U0/conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s_fu_78/call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93/call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s_fu_78/grp_compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s_fu_78_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s_fu_78/grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121/grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_U0/conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676/call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_fu_781/call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_24u_config35_s_fu_781_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676/grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676/grp_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s_fu_1361/grp_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config35_mult_s_fu_1361_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_U0/conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s_fu_262/call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_fu_303/call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config7_s_fu_303_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s_fu_262/grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s_fu_262_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s_fu_262/grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s_fu_499/grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config7_mult_s_fu_499_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_U0/conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s_fu_262/call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_fu_303/call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config37_s_fu_303_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s_fu_262/grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s_fu_262_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s_fu_262/grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s_fu_499/grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config37_mult_s_fu_499_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_U0/conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s_fu_262/call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_fu_303/call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config4_s_fu_303_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s_fu_262/grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s_fu_262_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s_fu_262/grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_fu_499/grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_fu_499_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_U0/conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s_fu_470/call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_fu_543/call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config31_s_fu_543_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s_fu_470/grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s_fu_470_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s_fu_470/grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config31_mult_s_fu_931/grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config31_mult_s_fu_931_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_U0/conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_470/call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_fu_543/call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config12_s_fu_543_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_470/grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_470_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_470/grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s_fu_931/grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config12_mult_s_fu_931_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_U0/conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s_fu_1300/call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_fu_1501/call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_48u_config29_s_fu_1501_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s_fu_1300/grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s_fu_1300_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s_fu_1300/grp_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s_fu_2657/grp_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config29_mult_s_fu_2657_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_U0/conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s_fu_886/call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_fu_1023/call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config14_s_fu_1023_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s_fu_886/grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s_fu_886_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s_fu_886/grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s_fu_1795/grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s_fu_1795_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_U0/conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s_fu_886/call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_fu_1023/call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config25_s_fu_1023_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s_fu_886/grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s_fu_886_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config25_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config25_s_fu_886/grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s_fu_1795/grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config25_mult_s_fu_1795_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_U0/conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s_fu_886/call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_fu_1023/call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_fu_1023_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s_fu_886/grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s_fu_886_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s_fu_886/grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config17_mult_s_fu_1795/grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config17_mult_s_fu_1795_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_U0/conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s_fu_2548/call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_fu_2941/call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_96u_config23_s_fu_2941_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s_fu_2548/grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s_fu_2548_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_32u_config23_s_fu_2548/grp_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s_fu_5249/grp_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_43_23_5_3_0_config23_mult_s_fu_5249_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_U0/conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1718/call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_fu_1983/call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_64u_config19_s_fu_1983_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1718/grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1718_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_U0/grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1718/grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config19_mult_s_fu_3523/grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config19_mult_s_fu_3523_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_U0/grp_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s_fu_83/grp_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s_fu_83_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_U0/pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config58_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_U0/call_ln52_shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_fu_188/call_ln52_shift_line_buffer_array_ap_fixed_16_6_5_3_0_8u_config6_s_fu_188_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_U0/pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_U0/call_ln52_shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_fu_300/call_ln52_shift_line_buffer_array_ap_fixed_16_6_5_3_0_16u_config11_s_fu_300_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_U0/pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_U0/call_ln52_shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_fu_524/call_ln52_shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config16_s_fu_524_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_U0/pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config16_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_U0/relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config10_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_U0/relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_U0/relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_U0/relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config8_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_U0/relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_U0/relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config15_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_U0/relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config24_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_U0/relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_U0/relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_U0/relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_U0/relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config36_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_U0/relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config38_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_U0/relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_U0/relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config5_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_U0/resize_nearest_array_ap_fixed_16_6_5_3_0_16u_config33_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_U0/resize_nearest_array_ap_fixed_16_6_5_3_0_32u_config27_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_U0/resize_nearest_array_ap_fixed_16_6_5_3_0_64u_config21_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_U0/sigmoid_array_array_ap_fixed_16_6_5_3_0_1u_sigmoid_config40_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config44_U0/grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain_fu_34/grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadMain_fu_34_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config44_U0/grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadTopWidth_fu_28/grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_1u_config44_Pipeline_PadTopWidth_fu_28_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config44_U0/grp_zeropad2d_cl_array_array_ap_fixed_1u_config44_Pipeline_PadBottomWidth_fu_42/grp_zeropad2d_cl_array_array_ap_fixed_1u_config44_Pipeline_PadBottomWidth_fu_42_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config44_U0/zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config44_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_U0/grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain_fu_28/grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadMain_fu_28_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_U0/grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadTopWidth_fu_22/grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config45_Pipeline_PadTopWidth_fu_22_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_U0/grp_zeropad2d_cl_array_array_ap_fixed_8u_config45_Pipeline_PadBottomWidth_fu_36/grp_zeropad2d_cl_array_array_ap_fixed_8u_config45_Pipeline_PadBottomWidth_fu_36_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_U0/zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config45_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config46_U0/grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain_fu_28/grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadMain_fu_28_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config46_U0/grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadTopWidth_fu_22/grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config46_Pipeline_PadTopWidth_fu_22_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config46_U0/grp_zeropad2d_cl_array_array_ap_fixed_8u_config46_Pipeline_PadBottomWidth_fu_36/grp_zeropad2d_cl_array_array_ap_fixed_8u_config46_Pipeline_PadBottomWidth_fu_36_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config46_U0/zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config46_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config57_U0/grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain_fu_28/grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadMain_fu_28_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config57_U0/grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadTopWidth_fu_22/grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config57_Pipeline_PadTopWidth_fu_22_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config57_U0/grp_zeropad2d_cl_array_array_ap_fixed_8u_config57_Pipeline_PadBottomWidth_fu_36/grp_zeropad2d_cl_array_array_ap_fixed_8u_config57_Pipeline_PadBottomWidth_fu_36_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config57_U0/zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config57_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_U0/grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain_fu_28/grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_Pipeline_PadMain_fu_28_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_U0/grp_zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadBottomWidth_fu_36/grp_zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadBottomWidth_fu_36_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_U0/grp_zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadTopWidth_fu_22/grp_zeropad2d_cl_array_array_ap_fixed_16u_config47_Pipeline_PadTopWidth_fu_22_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_U0/zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config47_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_U0/grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain_fu_28/grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_Pipeline_PadMain_fu_28_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_U0/grp_zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadBottomWidth_fu_36/grp_zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadBottomWidth_fu_36_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_U0/grp_zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadTopWidth_fu_22/grp_zeropad2d_cl_array_array_ap_fixed_16u_config48_Pipeline_PadTopWidth_fu_22_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_U0/zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config48_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_U0/grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain_fu_28/grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_Pipeline_PadMain_fu_28_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_U0/grp_zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadBottomWidth_fu_36/grp_zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadBottomWidth_fu_36_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_U0/grp_zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadTopWidth_fu_22/grp_zeropad2d_cl_array_array_ap_fixed_16u_config55_Pipeline_PadTopWidth_fu_22_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_U0/zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config55_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_U0/grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain_fu_28/grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_Pipeline_PadMain_fu_28_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_U0/grp_zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadBottomWidth_fu_36/grp_zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadBottomWidth_fu_36_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_U0/grp_zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth_fu_22/grp_zeropad2d_cl_array_array_ap_fixed_24u_config56_Pipeline_PadTopWidth_fu_22_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_U0/zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_24u_config56_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_U0/grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain_fu_28/grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_Pipeline_PadMain_fu_28_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_U0/grp_zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadBottomWidth_fu_36/grp_zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadBottomWidth_fu_36_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_U0/grp_zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadTopWidth_fu_22/grp_zeropad2d_cl_array_array_ap_fixed_32u_config49_Pipeline_PadTopWidth_fu_22_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_U0/zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_U0/grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain_fu_28/grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_Pipeline_PadMain_fu_28_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_U0/grp_zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadBottomWidth_fu_36/grp_zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadBottomWidth_fu_36_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_U0/grp_zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadTopWidth_fu_22/grp_zeropad2d_cl_array_array_ap_fixed_32u_config50_Pipeline_PadTopWidth_fu_22_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_U0/zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_U0/grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain_fu_28/grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_Pipeline_PadMain_fu_28_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_U0/grp_zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadBottomWidth_fu_36/grp_zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadBottomWidth_fu_36_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_U0/grp_zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadTopWidth_fu_22/grp_zeropad2d_cl_array_array_ap_fixed_32u_config53_Pipeline_PadTopWidth_fu_22_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_U0/zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config53_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_U0/grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain_fu_28/grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_Pipeline_PadMain_fu_28_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_U0/grp_zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadBottomWidth_fu_36/grp_zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadBottomWidth_fu_36_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_U0/grp_zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadTopWidth_fu_22/grp_zeropad2d_cl_array_array_ap_fixed_48u_config54_Pipeline_PadTopWidth_fu_22_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_U0/zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config54_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_U0/grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain_fu_28/grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_Pipeline_PadMain_fu_28_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_U0/grp_zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadBottomWidth_fu_36/grp_zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadBottomWidth_fu_36_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_U0/grp_zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadTopWidth_fu_22/grp_zeropad2d_cl_array_array_ap_fixed_64u_config51_Pipeline_PadTopWidth_fu_22_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_U0/zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config51_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_U0/grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain_fu_28/grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_Pipeline_PadMain_fu_28_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_U0/grp_zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadBottomWidth_fu_36/grp_zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadBottomWidth_fu_36_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_U0/grp_zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadTopWidth_fu_22/grp_zeropad2d_cl_array_array_ap_fixed_96u_config52_Pipeline_PadTopWidth_fu_22_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				},
+				"zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_U0/zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config52_U0_activity": {
+					"interface": "xilinx.com:interface:internal_hls_dataflow:1.0",
+					"ports": {
+						"AP_CLK": { "actual": "ap_clk"},
+						"AP_CONTINUE": { "actual": "ap_continue"},
+						"AP_DONE": { "actual": "ap_done"},
+						"AP_READY": { "actual": "ap_ready"},
+						"AP_RESET": { "actual": "ap_rst"},
+						"AP_START": { "actual": "ap_start"}
+					}
+				}
+			}
+		}
+	}
+}

myproject_prj/solution1/syn/verilog/myproject_compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s.v

@@ -0,0 +1,505 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+
+`timescale 1 ns / 1 ps 
+
+module myproject_compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s (
+        ap_clk,
+        ap_rst,
+        ap_start,
+        ap_done,
+        ap_idle,
+        ap_ready,
+        in_elem_0_0_0_0_0_val,
+        layer2_out_din,
+        layer2_out_num_data_valid,
+        layer2_out_fifo_cap,
+        layer2_out_full_n,
+        layer2_out_write
+);
+
+parameter    ap_ST_fsm_state1 = 3'd1;
+parameter    ap_ST_fsm_state2 = 3'd2;
+parameter    ap_ST_fsm_state3 = 3'd4;
+
+input   ap_clk;
+input   ap_rst;
+input   ap_start;
+output   ap_done;
+output   ap_idle;
+output   ap_ready;
+input  [15:0] in_elem_0_0_0_0_0_val;
+output  [295:0] layer2_out_din;
+input  [12:0] layer2_out_num_data_valid;
+input  [12:0] layer2_out_fifo_cap;
+input   layer2_out_full_n;
+output   layer2_out_write;
+
+reg ap_done;
+reg ap_idle;
+reg ap_ready;
+
+(* fsm_encoding = "none" *) reg   [2:0] ap_CS_fsm;
+wire    ap_CS_fsm_state1;
+reg   [15:0] void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_175;
+reg   [15:0] void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_176;
+reg   [15:0] void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_172;
+reg   [15:0] void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_173;
+reg   [15:0] void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_169;
+reg   [15:0] void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_170;
+reg   [15:0] void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_174;
+reg   [15:0] void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_171;
+reg   [15:0] void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_168;
+reg   [31:0] sX_7;
+reg   [31:0] sY_7;
+reg   [31:0] pY_7;
+reg   [31:0] pX_7;
+reg    layer2_out_blk_n;
+wire    ap_CS_fsm_state3;
+reg   [0:0] icmp_ln284_reg_370;
+reg   [0:0] and_ln284_10_reg_384;
+wire   [0:0] icmp_ln284_fu_151_p2;
+wire    ap_CS_fsm_state2;
+wire   [0:0] and_ln284_10_fu_213_p2;
+reg    call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_ap_start;
+wire    call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_ap_done;
+wire    call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_ap_idle;
+wire    call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_ap_ready;
+wire   [15:0] call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_175_o;
+wire    call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_175_o_ap_vld;
+wire   [15:0] call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_176;
+wire    call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_176_ap_vld;
+wire   [15:0] call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_172_o;
+wire    call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_172_o_ap_vld;
+wire   [15:0] call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_173;
+wire    call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_173_ap_vld;
+wire   [15:0] call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_169_o;
+wire    call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_169_o_ap_vld;
+wire   [15:0] call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_170;
+wire    call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_170_ap_vld;
+wire   [15:0] call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_174_o;
+wire    call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_174_o_ap_vld;
+wire   [15:0] call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_171_o;
+wire    call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_171_o_ap_vld;
+wire   [15:0] call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_168_o;
+wire    call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_168_o_ap_vld;
+wire    grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_start;
+wire    grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_done;
+wire    grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_idle;
+wire    grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_ready;
+wire   [36:0] grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_return_0;
+wire   [36:0] grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_return_1;
+wire   [36:0] grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_return_2;
+wire   [36:0] grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_return_3;
+wire   [36:0] grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_return_4;
+wire   [36:0] grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_return_5;
+wire   [36:0] grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_return_6;
+wire   [36:0] grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_return_7;
+wire   [31:0] select_ln313_fu_346_p3;
+reg   [31:0] ap_phi_mux_storemerge_phi_fu_86_p4;
+reg    ap_predicate_op32_write_state3;
+reg    ap_block_state3;
+reg    ap_predicate_op22_call_state3;
+reg    ap_block_state3_on_subcall_done;
+wire   [0:0] icmp_ln303_fu_277_p2;
+wire   [0:0] icmp_ln307_fu_324_p2;
+reg    grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_start_reg;
+wire   [31:0] select_ln318_fu_294_p3;
+wire   [31:0] add_ln307_fu_319_p2;
+wire   [31:0] add_ln303_fu_272_p2;
+wire   [295:0] p_0_fu_251_p9;
+reg    layer2_out_write_local;
+wire   [30:0] tmp_31_fu_175_p4;
+wire   [30:0] tmp_32_fu_191_p4;
+wire   [0:0] icmp_ln284_34_fu_185_p2;
+wire   [0:0] icmp_ln284_35_fu_201_p2;
+wire   [0:0] and_ln284_fu_207_p2;
+wire   [0:0] icmp_ln284_28_fu_169_p2;
+wire   [31:0] add_ln318_fu_289_p2;
+wire   [0:0] icmp_ln313_fu_336_p2;
+wire   [31:0] add_ln313_fu_341_p2;
+reg   [2:0] ap_NS_fsm;
+reg    ap_ST_fsm_state1_blk;
+wire    ap_ST_fsm_state2_blk;
+reg    ap_ST_fsm_state3_blk;
+reg    ap_condition_138;
+reg    ap_condition_184;
+wire    ap_ce_reg;
+
+// power-on initialization
+initial begin
+#0 ap_CS_fsm = 3'd1;
+#0 void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_175 = 16'd0;
+#0 void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_176 = 16'd0;
+#0 void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_172 = 16'd0;
+#0 void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_173 = 16'd0;
+#0 void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_169 = 16'd0;
+#0 void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_170 = 16'd0;
+#0 void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_174 = 16'd0;
+#0 void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_171 = 16'd0;
+#0 void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_168 = 16'd0;
+#0 sX_7 = 32'd0;
+#0 sY_7 = 32'd0;
+#0 pY_7 = 32'd0;
+#0 pX_7 = 32'd0;
+#0 grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_start_reg = 1'b0;
+end
+
+myproject_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93(
+    .ap_clk(ap_clk),
+    .ap_rst(ap_rst),
+    .ap_start(call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_ap_start),
+    .ap_done(call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_ap_done),
+    .ap_idle(call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_ap_idle),
+    .ap_ready(call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_ap_ready),
+    .in_elem_0_0_0_0_0_val(in_elem_0_0_0_0_0_val),
+    .void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_175_i(void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_175),
+    .void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_175_o(call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_175_o),
+    .void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_175_o_ap_vld(call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_175_o_ap_vld),
+    .void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_176(call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_176),
+    .void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_176_ap_vld(call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_176_ap_vld),
+    .void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_172_i(void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_172),
+    .void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_172_o(call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_172_o),
+    .void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_172_o_ap_vld(call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_172_o_ap_vld),
+    .void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_173(call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_173),
+    .void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_173_ap_vld(call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_173_ap_vld),
+    .void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_169_i(void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_169),
+    .void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_169_o(call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_169_o),
+    .void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_169_o_ap_vld(call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_169_o_ap_vld),
+    .void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_170(call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_170),
+    .void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_170_ap_vld(call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_170_ap_vld),
+    .void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_174_i(void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_174),
+    .void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_174_o(call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_174_o),
+    .void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_174_o_ap_vld(call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_174_o_ap_vld),
+    .void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_171_i(void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_171),
+    .void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_171_o(call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_171_o),
+    .void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_171_o_ap_vld(call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_171_o_ap_vld),
+    .void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_168_i(void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_168),
+    .void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_168_o(call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_168_o),
+    .void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_168_o_ap_vld(call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_168_o_ap_vld)
+);
+
+myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121(
+    .ap_clk(ap_clk),
+    .ap_rst(ap_rst),
+    .ap_start(grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_start),
+    .ap_done(grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_done),
+    .ap_idle(grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_idle),
+    .ap_ready(grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_ready),
+    .void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_176(void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_176),
+    .void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_175(void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_175),
+    .void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_174(void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_174),
+    .void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_173(void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_173),
+    .void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_172(void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_172),
+    .void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_171(void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_171),
+    .void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_170(void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_170),
+    .void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_169(void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_169),
+    .void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_168(void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_168),
+    .ap_return_0(grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_return_0),
+    .ap_return_1(grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_return_1),
+    .ap_return_2(grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_return_2),
+    .ap_return_3(grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_return_3),
+    .ap_return_4(grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_return_4),
+    .ap_return_5(grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_return_5),
+    .ap_return_6(grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_return_6),
+    .ap_return_7(grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_return_7)
+);
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_CS_fsm <= ap_ST_fsm_state1;
+    end else begin
+        ap_CS_fsm <= ap_NS_fsm;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_start_reg <= 1'b0;
+    end else begin
+        if (((icmp_ln284_fu_151_p2 == 1'd1) & (1'd1 == and_ln284_10_fu_213_p2) & (1'b1 == ap_CS_fsm_state2))) begin
+            grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_start_reg <= 1'b1;
+        end else if ((grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_ready == 1'b1)) begin
+            grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_start_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_condition_138)) begin
+        if ((icmp_ln303_fu_277_p2 == 1'd1)) begin
+            pX_7 <= 32'd0;
+        end else if ((icmp_ln303_fu_277_p2 == 1'd0)) begin
+            pX_7 <= add_ln303_fu_272_p2;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_condition_184)) begin
+        if ((icmp_ln307_fu_324_p2 == 1'd1)) begin
+            pY_7 <= 32'd0;
+        end else if ((icmp_ln307_fu_324_p2 == 1'd0)) begin
+            pY_7 <= add_ln307_fu_319_p2;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_condition_138)) begin
+        if ((icmp_ln303_fu_277_p2 == 1'd1)) begin
+            sX_7 <= 32'd0;
+        end else if ((icmp_ln303_fu_277_p2 == 1'd0)) begin
+            sX_7 <= select_ln318_fu_294_p3;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_state2)) begin
+        and_ln284_10_reg_384 <= and_ln284_10_fu_213_p2;
+        icmp_ln284_reg_370 <= icmp_ln284_fu_151_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((~((1'b1 == ap_block_state3_on_subcall_done) | (1'b1 == ap_block_state3)) & (1'b1 == ap_CS_fsm_state3) & (icmp_ln303_fu_277_p2 == 1'd1))) begin
+        sY_7 <= ap_phi_mux_storemerge_phi_fu_86_p4;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_168_o_ap_vld == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_168 <= call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_168_o;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_169_o_ap_vld == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_169 <= call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_169_o;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_170_ap_vld == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_170 <= call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_170;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_171_o_ap_vld == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_171 <= call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_171_o;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_172_o_ap_vld == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_172 <= call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_172_o;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_173_ap_vld == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_173 <= call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_173;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_174_o_ap_vld == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_174 <= call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_174_o;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_175_o_ap_vld == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_175 <= call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_175_o;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_176_ap_vld == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_176 <= call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_176;
+    end
+end
+
+always @ (*) begin
+    if ((ap_start == 1'b0)) begin
+        ap_ST_fsm_state1_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state1_blk = 1'b0;
+    end
+end
+
+assign ap_ST_fsm_state2_blk = 1'b0;
+
+always @ (*) begin
+    if (((1'b1 == ap_block_state3_on_subcall_done) | (1'b1 == ap_block_state3))) begin
+        ap_ST_fsm_state3_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state3_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((~((1'b1 == ap_block_state3_on_subcall_done) | (1'b1 == ap_block_state3)) & (1'b1 == ap_CS_fsm_state3)) | ((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1)))) begin
+        ap_done = 1'b1;
+    end else begin
+        ap_done = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
+        ap_idle = 1'b1;
+    end else begin
+        ap_idle = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state3) & (icmp_ln303_fu_277_p2 == 1'd1))) begin
+        if ((icmp_ln307_fu_324_p2 == 1'd1)) begin
+            ap_phi_mux_storemerge_phi_fu_86_p4 = 32'd0;
+        end else if ((icmp_ln307_fu_324_p2 == 1'd0)) begin
+            ap_phi_mux_storemerge_phi_fu_86_p4 = select_ln313_fu_346_p3;
+        end else begin
+            ap_phi_mux_storemerge_phi_fu_86_p4 = 'bx;
+        end
+    end else begin
+        ap_phi_mux_storemerge_phi_fu_86_p4 = 'bx;
+    end
+end
+
+always @ (*) begin
+    if ((~((1'b1 == ap_block_state3_on_subcall_done) | (1'b1 == ap_block_state3)) & (1'b1 == ap_CS_fsm_state3))) begin
+        ap_ready = 1'b1;
+    end else begin
+        ap_ready = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+        call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_ap_start = 1'b1;
+    end else begin
+        call_ln281_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_fu_93_ap_start = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'd1 == and_ln284_10_reg_384) & (icmp_ln284_reg_370 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin
+        layer2_out_blk_n = layer2_out_full_n;
+    end else begin
+        layer2_out_blk_n = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if ((~((1'b1 == ap_block_state3_on_subcall_done) | (1'b1 == ap_block_state3)) & (1'b1 == ap_CS_fsm_state3) & (ap_predicate_op32_write_state3 == 1'b1))) begin
+        layer2_out_write_local = 1'b1;
+    end else begin
+        layer2_out_write_local = 1'b0;
+    end
+end
+
+always @ (*) begin
+    case (ap_CS_fsm)
+        ap_ST_fsm_state1 : begin
+            if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end
+        end
+        ap_ST_fsm_state2 : begin
+            ap_NS_fsm = ap_ST_fsm_state3;
+        end
+        ap_ST_fsm_state3 : begin
+            if ((~((1'b1 == ap_block_state3_on_subcall_done) | (1'b1 == ap_block_state3)) & (1'b1 == ap_CS_fsm_state3))) begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end
+        end
+        default : begin
+            ap_NS_fsm = 'bx;
+        end
+    endcase
+end
+
+assign add_ln303_fu_272_p2 = (pX_7 + 32'd1);
+
+assign add_ln307_fu_319_p2 = (pY_7 + 32'd1);
+
+assign add_ln313_fu_341_p2 = (sY_7 + 32'd1);
+
+assign add_ln318_fu_289_p2 = (sX_7 + 32'd1);
+
+assign and_ln284_10_fu_213_p2 = (icmp_ln284_28_fu_169_p2 & and_ln284_fu_207_p2);
+
+assign and_ln284_fu_207_p2 = (icmp_ln284_35_fu_201_p2 & icmp_ln284_34_fu_185_p2);
+
+assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
+
+assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
+
+assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2];
+
+always @ (*) begin
+    ap_block_state3 = ((layer2_out_full_n == 1'b0) & (ap_predicate_op32_write_state3 == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_state3_on_subcall_done = ((grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_done == 1'b0) & (ap_predicate_op22_call_state3 == 1'b1));
+end
+
+always @ (*) begin
+    ap_condition_138 = (~((1'b1 == ap_block_state3_on_subcall_done) | (1'b1 == ap_block_state3)) & (1'b1 == ap_CS_fsm_state3));
+end
+
+always @ (*) begin
+    ap_condition_184 = (~((1'b1 == ap_block_state3_on_subcall_done) | (1'b1 == ap_block_state3)) & (1'b1 == ap_CS_fsm_state3) & (icmp_ln303_fu_277_p2 == 1'd1));
+end
+
+always @ (*) begin
+    ap_predicate_op22_call_state3 = ((1'd1 == and_ln284_10_reg_384) & (icmp_ln284_reg_370 == 1'd1));
+end
+
+always @ (*) begin
+    ap_predicate_op32_write_state3 = ((1'd1 == and_ln284_10_reg_384) & (icmp_ln284_reg_370 == 1'd1));
+end
+
+assign grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_start = grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_start_reg;
+
+assign icmp_ln284_28_fu_169_p2 = ((sY_7 == 32'd2) ? 1'b1 : 1'b0);
+
+assign icmp_ln284_34_fu_185_p2 = (($signed(tmp_31_fu_175_p4) > $signed(31'd0)) ? 1'b1 : 1'b0);
+
+assign icmp_ln284_35_fu_201_p2 = (($signed(tmp_32_fu_191_p4) > $signed(31'd0)) ? 1'b1 : 1'b0);
+
+assign icmp_ln284_fu_151_p2 = ((sX_7 == 32'd2) ? 1'b1 : 1'b0);
+
+assign icmp_ln303_fu_277_p2 = ((add_ln303_fu_272_p2 == 32'd66) ? 1'b1 : 1'b0);
+
+assign icmp_ln307_fu_324_p2 = ((add_ln307_fu_319_p2 == 32'd66) ? 1'b1 : 1'b0);
+
+assign icmp_ln313_fu_336_p2 = ((sY_7 == 32'd2) ? 1'b1 : 1'b0);
+
+assign layer2_out_din = p_0_fu_251_p9;
+
+assign layer2_out_write = layer2_out_write_local;
+
+assign p_0_fu_251_p9 = {{{{{{{{grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_return_7}, {grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_return_6}}, {grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_return_5}}, {grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_return_4}}, {grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_return_3}}, {grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_return_2}}, {grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_return_1}}, {grp_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_fu_121_ap_return_0}};
+
+assign select_ln313_fu_346_p3 = ((icmp_ln313_fu_336_p2[0:0] == 1'b1) ? 32'd2 : add_ln313_fu_341_p2);
+
+assign select_ln318_fu_294_p3 = ((icmp_ln284_reg_370[0:0] == 1'b1) ? 32'd2 : add_ln318_fu_289_p2);
+
+assign tmp_31_fu_175_p4 = {{pY_7[31:1]}};
+
+assign tmp_32_fu_191_p4 = {{pX_7[31:1]}};
+
+endmodule //myproject_compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s

myproject_prj/solution1/syn/verilog/myproject_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s.v

@@ -0,0 +1,294 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+
+`timescale 1 ns / 1 ps 
+
+module myproject_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s (
+        ap_clk,
+        ap_rst,
+        ap_start,
+        start_full_n,
+        ap_done,
+        ap_continue,
+        ap_idle,
+        ap_ready,
+        start_out,
+        start_write,
+        layer33_out_dout,
+        layer33_out_num_data_valid,
+        layer33_out_fifo_cap,
+        layer33_out_empty_n,
+        layer33_out_read,
+        layer41_cpy2_dout,
+        layer41_cpy2_num_data_valid,
+        layer41_cpy2_fifo_cap,
+        layer41_cpy2_empty_n,
+        layer41_cpy2_read,
+        layer34_out_din,
+        layer34_out_num_data_valid,
+        layer34_out_fifo_cap,
+        layer34_out_full_n,
+        layer34_out_write
+);
+
+parameter    ap_ST_fsm_state1 = 2'd1;
+parameter    ap_ST_fsm_state2 = 2'd2;
+
+input   ap_clk;
+input   ap_rst;
+input   ap_start;
+input   start_full_n;
+output   ap_done;
+input   ap_continue;
+output   ap_idle;
+output   ap_ready;
+output   start_out;
+output   start_write;
+input  [255:0] layer33_out_dout;
+input  [12:0] layer33_out_num_data_valid;
+input  [12:0] layer33_out_fifo_cap;
+input   layer33_out_empty_n;
+output   layer33_out_read;
+input  [127:0] layer41_cpy2_dout;
+input  [12:0] layer41_cpy2_num_data_valid;
+input  [12:0] layer41_cpy2_fifo_cap;
+input   layer41_cpy2_empty_n;
+output   layer41_cpy2_read;
+output  [383:0] layer34_out_din;
+input  [12:0] layer34_out_num_data_valid;
+input  [12:0] layer34_out_fifo_cap;
+input   layer34_out_full_n;
+output   layer34_out_write;
+
+reg ap_done;
+reg ap_idle;
+reg start_write;
+reg layer33_out_read;
+reg layer41_cpy2_read;
+reg layer34_out_write;
+
+reg    real_start;
+reg    start_once_reg;
+reg    ap_done_reg;
+(* fsm_encoding = "none" *) reg   [1:0] ap_CS_fsm;
+wire    ap_CS_fsm_state1;
+reg    internal_ap_ready;
+wire    grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_start;
+wire    grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_done;
+wire    grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_idle;
+wire    grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_ready;
+wire    grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_layer33_out_read;
+wire    grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_layer41_cpy2_read;
+wire   [383:0] grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_layer34_out_din;
+wire    grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_layer34_out_write;
+reg    grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_start_reg;
+reg    ap_block_state1_ignore_call3;
+wire    ap_CS_fsm_state2;
+reg   [1:0] ap_NS_fsm;
+reg    ap_block_state1;
+reg    ap_ST_fsm_state1_blk;
+reg    ap_ST_fsm_state2_blk;
+wire    ap_ce_reg;
+
+// power-on initialization
+initial begin
+#0 start_once_reg = 1'b0;
+#0 ap_done_reg = 1'b0;
+#0 ap_CS_fsm = 2'd1;
+#0 grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_start_reg = 1'b0;
+end
+
+myproject_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18(
+    .ap_clk(ap_clk),
+    .ap_rst(ap_rst),
+    .ap_start(grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_start),
+    .ap_done(grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_done),
+    .ap_idle(grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_idle),
+    .ap_ready(grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_ready),
+    .layer33_out_dout(layer33_out_dout),
+    .layer33_out_num_data_valid(13'd0),
+    .layer33_out_fifo_cap(13'd0),
+    .layer33_out_empty_n(layer33_out_empty_n),
+    .layer33_out_read(grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_layer33_out_read),
+    .layer41_cpy2_dout(layer41_cpy2_dout),
+    .layer41_cpy2_num_data_valid(13'd0),
+    .layer41_cpy2_fifo_cap(13'd0),
+    .layer41_cpy2_empty_n(layer41_cpy2_empty_n),
+    .layer41_cpy2_read(grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_layer41_cpy2_read),
+    .layer34_out_din(grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_layer34_out_din),
+    .layer34_out_num_data_valid(13'd0),
+    .layer34_out_fifo_cap(13'd0),
+    .layer34_out_full_n(layer34_out_full_n),
+    .layer34_out_write(grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_layer34_out_write)
+);
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_CS_fsm <= ap_ST_fsm_state1;
+    end else begin
+        ap_CS_fsm <= ap_NS_fsm;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_done_reg <= 1'b0;
+    end else begin
+        if ((ap_continue == 1'b1)) begin
+            ap_done_reg <= 1'b0;
+        end else if (((grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state2))) begin
+            ap_done_reg <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_start_reg <= 1'b0;
+    end else begin
+        if (((1'b0 == ap_block_state1_ignore_call3) & (1'b1 == ap_CS_fsm_state1))) begin
+            grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_start_reg <= 1'b1;
+        end else if ((grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_ready == 1'b1)) begin
+            grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_start_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        start_once_reg <= 1'b0;
+    end else begin
+        if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin
+            start_once_reg <= 1'b1;
+        end else if ((internal_ap_ready == 1'b1)) begin
+            start_once_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_block_state1)) begin
+        ap_ST_fsm_state1_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state1_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_done == 1'b0)) begin
+        ap_ST_fsm_state2_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state2_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state2))) begin
+        ap_done = 1'b1;
+    end else begin
+        ap_done = ap_done_reg;
+    end
+end
+
+always @ (*) begin
+    if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
+        ap_idle = 1'b1;
+    end else begin
+        ap_idle = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state2))) begin
+        internal_ap_ready = 1'b1;
+    end else begin
+        internal_ap_ready = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state2)) begin
+        layer33_out_read = grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_layer33_out_read;
+    end else begin
+        layer33_out_read = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state2)) begin
+        layer34_out_write = grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_layer34_out_write;
+    end else begin
+        layer34_out_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state2)) begin
+        layer41_cpy2_read = grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_layer41_cpy2_read;
+    end else begin
+        layer41_cpy2_read = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((start_full_n == 1'b0) & (start_once_reg == 1'b0))) begin
+        real_start = 1'b0;
+    end else begin
+        real_start = ap_start;
+    end
+end
+
+always @ (*) begin
+    if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin
+        start_write = 1'b1;
+    end else begin
+        start_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    case (ap_CS_fsm)
+        ap_ST_fsm_state1 : begin
+            if (((1'b0 == ap_block_state1) & (1'b1 == ap_CS_fsm_state1))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end
+        end
+        ap_ST_fsm_state2 : begin
+            if (((grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state2))) begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end
+        end
+        default : begin
+            ap_NS_fsm = 'bx;
+        end
+    endcase
+end
+
+assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
+
+assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
+
+always @ (*) begin
+    ap_block_state1 = ((real_start == 1'b0) | (ap_done_reg == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_state1_ignore_call3 = ((real_start == 1'b0) | (ap_done_reg == 1'b1));
+end
+
+assign ap_ready = internal_ap_ready;
+
+assign grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_start = grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_start_reg;
+
+assign layer34_out_din = grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_layer34_out_din;
+
+assign start_out = real_start;
+
+endmodule //myproject_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s

myproject_prj/solution1/syn/verilog/myproject_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s.v

@@ -0,0 +1,294 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+
+`timescale 1 ns / 1 ps 
+
+module myproject_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s (
+        ap_clk,
+        ap_rst,
+        ap_start,
+        start_full_n,
+        ap_done,
+        ap_continue,
+        ap_idle,
+        ap_ready,
+        start_out,
+        start_write,
+        layer27_out_dout,
+        layer27_out_num_data_valid,
+        layer27_out_fifo_cap,
+        layer27_out_empty_n,
+        layer27_out_read,
+        layer42_cpy2_dout,
+        layer42_cpy2_num_data_valid,
+        layer42_cpy2_fifo_cap,
+        layer42_cpy2_empty_n,
+        layer42_cpy2_read,
+        layer28_out_din,
+        layer28_out_num_data_valid,
+        layer28_out_fifo_cap,
+        layer28_out_full_n,
+        layer28_out_write
+);
+
+parameter    ap_ST_fsm_state1 = 2'd1;
+parameter    ap_ST_fsm_state2 = 2'd2;
+
+input   ap_clk;
+input   ap_rst;
+input   ap_start;
+input   start_full_n;
+output   ap_done;
+input   ap_continue;
+output   ap_idle;
+output   ap_ready;
+output   start_out;
+output   start_write;
+input  [511:0] layer27_out_dout;
+input  [10:0] layer27_out_num_data_valid;
+input  [10:0] layer27_out_fifo_cap;
+input   layer27_out_empty_n;
+output   layer27_out_read;
+input  [255:0] layer42_cpy2_dout;
+input  [10:0] layer42_cpy2_num_data_valid;
+input  [10:0] layer42_cpy2_fifo_cap;
+input   layer42_cpy2_empty_n;
+output   layer42_cpy2_read;
+output  [767:0] layer28_out_din;
+input  [10:0] layer28_out_num_data_valid;
+input  [10:0] layer28_out_fifo_cap;
+input   layer28_out_full_n;
+output   layer28_out_write;
+
+reg ap_done;
+reg ap_idle;
+reg start_write;
+reg layer27_out_read;
+reg layer42_cpy2_read;
+reg layer28_out_write;
+
+reg    real_start;
+reg    start_once_reg;
+reg    ap_done_reg;
+(* fsm_encoding = "none" *) reg   [1:0] ap_CS_fsm;
+wire    ap_CS_fsm_state1;
+reg    internal_ap_ready;
+wire    grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_fu_18_ap_start;
+wire    grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_fu_18_ap_done;
+wire    grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_fu_18_ap_idle;
+wire    grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_fu_18_ap_ready;
+wire    grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_fu_18_layer27_out_read;
+wire    grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_fu_18_layer42_cpy2_read;
+wire   [767:0] grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_fu_18_layer28_out_din;
+wire    grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_fu_18_layer28_out_write;
+reg    grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_fu_18_ap_start_reg;
+reg    ap_block_state1_ignore_call3;
+wire    ap_CS_fsm_state2;
+reg   [1:0] ap_NS_fsm;
+reg    ap_block_state1;
+reg    ap_ST_fsm_state1_blk;
+reg    ap_ST_fsm_state2_blk;
+wire    ap_ce_reg;
+
+// power-on initialization
+initial begin
+#0 start_once_reg = 1'b0;
+#0 ap_done_reg = 1'b0;
+#0 ap_CS_fsm = 2'd1;
+#0 grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_fu_18_ap_start_reg = 1'b0;
+end
+
+myproject_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_fu_18(
+    .ap_clk(ap_clk),
+    .ap_rst(ap_rst),
+    .ap_start(grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_fu_18_ap_start),
+    .ap_done(grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_fu_18_ap_done),
+    .ap_idle(grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_fu_18_ap_idle),
+    .ap_ready(grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_fu_18_ap_ready),
+    .layer27_out_dout(layer27_out_dout),
+    .layer27_out_num_data_valid(11'd0),
+    .layer27_out_fifo_cap(11'd0),
+    .layer27_out_empty_n(layer27_out_empty_n),
+    .layer27_out_read(grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_fu_18_layer27_out_read),
+    .layer42_cpy2_dout(layer42_cpy2_dout),
+    .layer42_cpy2_num_data_valid(11'd0),
+    .layer42_cpy2_fifo_cap(11'd0),
+    .layer42_cpy2_empty_n(layer42_cpy2_empty_n),
+    .layer42_cpy2_read(grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_fu_18_layer42_cpy2_read),
+    .layer28_out_din(grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_fu_18_layer28_out_din),
+    .layer28_out_num_data_valid(11'd0),
+    .layer28_out_fifo_cap(11'd0),
+    .layer28_out_full_n(layer28_out_full_n),
+    .layer28_out_write(grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_fu_18_layer28_out_write)
+);
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_CS_fsm <= ap_ST_fsm_state1;
+    end else begin
+        ap_CS_fsm <= ap_NS_fsm;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_done_reg <= 1'b0;
+    end else begin
+        if ((ap_continue == 1'b1)) begin
+            ap_done_reg <= 1'b0;
+        end else if (((grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_fu_18_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state2))) begin
+            ap_done_reg <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_fu_18_ap_start_reg <= 1'b0;
+    end else begin
+        if (((1'b0 == ap_block_state1_ignore_call3) & (1'b1 == ap_CS_fsm_state1))) begin
+            grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_fu_18_ap_start_reg <= 1'b1;
+        end else if ((grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_fu_18_ap_ready == 1'b1)) begin
+            grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_fu_18_ap_start_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        start_once_reg <= 1'b0;
+    end else begin
+        if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin
+            start_once_reg <= 1'b1;
+        end else if ((internal_ap_ready == 1'b1)) begin
+            start_once_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_block_state1)) begin
+        ap_ST_fsm_state1_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state1_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_fu_18_ap_done == 1'b0)) begin
+        ap_ST_fsm_state2_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state2_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_fu_18_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state2))) begin
+        ap_done = 1'b1;
+    end else begin
+        ap_done = ap_done_reg;
+    end
+end
+
+always @ (*) begin
+    if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
+        ap_idle = 1'b1;
+    end else begin
+        ap_idle = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_fu_18_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state2))) begin
+        internal_ap_ready = 1'b1;
+    end else begin
+        internal_ap_ready = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state2)) begin
+        layer27_out_read = grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_fu_18_layer27_out_read;
+    end else begin
+        layer27_out_read = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state2)) begin
+        layer28_out_write = grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_fu_18_layer28_out_write;
+    end else begin
+        layer28_out_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state2)) begin
+        layer42_cpy2_read = grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_fu_18_layer42_cpy2_read;
+    end else begin
+        layer42_cpy2_read = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((start_full_n == 1'b0) & (start_once_reg == 1'b0))) begin
+        real_start = 1'b0;
+    end else begin
+        real_start = ap_start;
+    end
+end
+
+always @ (*) begin
+    if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin
+        start_write = 1'b1;
+    end else begin
+        start_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    case (ap_CS_fsm)
+        ap_ST_fsm_state1 : begin
+            if (((1'b0 == ap_block_state1) & (1'b1 == ap_CS_fsm_state1))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end
+        end
+        ap_ST_fsm_state2 : begin
+            if (((grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_fu_18_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state2))) begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end
+        end
+        default : begin
+            ap_NS_fsm = 'bx;
+        end
+    endcase
+end
+
+assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
+
+assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
+
+always @ (*) begin
+    ap_block_state1 = ((real_start == 1'b0) | (ap_done_reg == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_state1_ignore_call3 = ((real_start == 1'b0) | (ap_done_reg == 1'b1));
+end
+
+assign ap_ready = internal_ap_ready;
+
+assign grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_fu_18_ap_start = grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_fu_18_ap_start_reg;
+
+assign layer28_out_din = grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s_fu_18_layer28_out_din;
+
+assign start_out = real_start;
+
+endmodule //myproject_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_48u_config28_s

myproject_prj/solution1/syn/verilog/myproject_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s.v

@@ -0,0 +1,294 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+
+`timescale 1 ns / 1 ps 
+
+module myproject_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s (
+        ap_clk,
+        ap_rst,
+        ap_start,
+        start_full_n,
+        ap_done,
+        ap_continue,
+        ap_idle,
+        ap_ready,
+        start_out,
+        start_write,
+        layer21_out_dout,
+        layer21_out_num_data_valid,
+        layer21_out_fifo_cap,
+        layer21_out_empty_n,
+        layer21_out_read,
+        layer43_cpy2_dout,
+        layer43_cpy2_num_data_valid,
+        layer43_cpy2_fifo_cap,
+        layer43_cpy2_empty_n,
+        layer43_cpy2_read,
+        layer22_out_din,
+        layer22_out_num_data_valid,
+        layer22_out_fifo_cap,
+        layer22_out_full_n,
+        layer22_out_write
+);
+
+parameter    ap_ST_fsm_state1 = 2'd1;
+parameter    ap_ST_fsm_state2 = 2'd2;
+
+input   ap_clk;
+input   ap_rst;
+input   ap_start;
+input   start_full_n;
+output   ap_done;
+input   ap_continue;
+output   ap_idle;
+output   ap_ready;
+output   start_out;
+output   start_write;
+input  [1023:0] layer21_out_dout;
+input  [8:0] layer21_out_num_data_valid;
+input  [8:0] layer21_out_fifo_cap;
+input   layer21_out_empty_n;
+output   layer21_out_read;
+input  [511:0] layer43_cpy2_dout;
+input  [8:0] layer43_cpy2_num_data_valid;
+input  [8:0] layer43_cpy2_fifo_cap;
+input   layer43_cpy2_empty_n;
+output   layer43_cpy2_read;
+output  [1535:0] layer22_out_din;
+input  [8:0] layer22_out_num_data_valid;
+input  [8:0] layer22_out_fifo_cap;
+input   layer22_out_full_n;
+output   layer22_out_write;
+
+reg ap_done;
+reg ap_idle;
+reg start_write;
+reg layer21_out_read;
+reg layer43_cpy2_read;
+reg layer22_out_write;
+
+reg    real_start;
+reg    start_once_reg;
+reg    ap_done_reg;
+(* fsm_encoding = "none" *) reg   [1:0] ap_CS_fsm;
+wire    ap_CS_fsm_state1;
+reg    internal_ap_ready;
+wire    grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s_fu_18_ap_start;
+wire    grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s_fu_18_ap_done;
+wire    grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s_fu_18_ap_idle;
+wire    grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s_fu_18_ap_ready;
+wire    grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s_fu_18_layer21_out_read;
+wire    grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s_fu_18_layer43_cpy2_read;
+wire   [1535:0] grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s_fu_18_layer22_out_din;
+wire    grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s_fu_18_layer22_out_write;
+reg    grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s_fu_18_ap_start_reg;
+reg    ap_block_state1_ignore_call3;
+wire    ap_CS_fsm_state2;
+reg   [1:0] ap_NS_fsm;
+reg    ap_block_state1;
+reg    ap_ST_fsm_state1_blk;
+reg    ap_ST_fsm_state2_blk;
+wire    ap_ce_reg;
+
+// power-on initialization
+initial begin
+#0 start_once_reg = 1'b0;
+#0 ap_done_reg = 1'b0;
+#0 ap_CS_fsm = 2'd1;
+#0 grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s_fu_18_ap_start_reg = 1'b0;
+end
+
+myproject_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s_fu_18(
+    .ap_clk(ap_clk),
+    .ap_rst(ap_rst),
+    .ap_start(grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s_fu_18_ap_start),
+    .ap_done(grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s_fu_18_ap_done),
+    .ap_idle(grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s_fu_18_ap_idle),
+    .ap_ready(grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s_fu_18_ap_ready),
+    .layer21_out_dout(layer21_out_dout),
+    .layer21_out_num_data_valid(9'd0),
+    .layer21_out_fifo_cap(9'd0),
+    .layer21_out_empty_n(layer21_out_empty_n),
+    .layer21_out_read(grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s_fu_18_layer21_out_read),
+    .layer43_cpy2_dout(layer43_cpy2_dout),
+    .layer43_cpy2_num_data_valid(9'd0),
+    .layer43_cpy2_fifo_cap(9'd0),
+    .layer43_cpy2_empty_n(layer43_cpy2_empty_n),
+    .layer43_cpy2_read(grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s_fu_18_layer43_cpy2_read),
+    .layer22_out_din(grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s_fu_18_layer22_out_din),
+    .layer22_out_num_data_valid(9'd0),
+    .layer22_out_fifo_cap(9'd0),
+    .layer22_out_full_n(layer22_out_full_n),
+    .layer22_out_write(grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s_fu_18_layer22_out_write)
+);
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_CS_fsm <= ap_ST_fsm_state1;
+    end else begin
+        ap_CS_fsm <= ap_NS_fsm;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_done_reg <= 1'b0;
+    end else begin
+        if ((ap_continue == 1'b1)) begin
+            ap_done_reg <= 1'b0;
+        end else if (((grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s_fu_18_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state2))) begin
+            ap_done_reg <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s_fu_18_ap_start_reg <= 1'b0;
+    end else begin
+        if (((1'b0 == ap_block_state1_ignore_call3) & (1'b1 == ap_CS_fsm_state1))) begin
+            grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s_fu_18_ap_start_reg <= 1'b1;
+        end else if ((grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s_fu_18_ap_ready == 1'b1)) begin
+            grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s_fu_18_ap_start_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        start_once_reg <= 1'b0;
+    end else begin
+        if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin
+            start_once_reg <= 1'b1;
+        end else if ((internal_ap_ready == 1'b1)) begin
+            start_once_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_block_state1)) begin
+        ap_ST_fsm_state1_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state1_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s_fu_18_ap_done == 1'b0)) begin
+        ap_ST_fsm_state2_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state2_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s_fu_18_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state2))) begin
+        ap_done = 1'b1;
+    end else begin
+        ap_done = ap_done_reg;
+    end
+end
+
+always @ (*) begin
+    if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
+        ap_idle = 1'b1;
+    end else begin
+        ap_idle = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s_fu_18_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state2))) begin
+        internal_ap_ready = 1'b1;
+    end else begin
+        internal_ap_ready = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state2)) begin
+        layer21_out_read = grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s_fu_18_layer21_out_read;
+    end else begin
+        layer21_out_read = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state2)) begin
+        layer22_out_write = grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s_fu_18_layer22_out_write;
+    end else begin
+        layer22_out_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state2)) begin
+        layer43_cpy2_read = grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s_fu_18_layer43_cpy2_read;
+    end else begin
+        layer43_cpy2_read = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((start_full_n == 1'b0) & (start_once_reg == 1'b0))) begin
+        real_start = 1'b0;
+    end else begin
+        real_start = ap_start;
+    end
+end
+
+always @ (*) begin
+    if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin
+        start_write = 1'b1;
+    end else begin
+        start_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    case (ap_CS_fsm)
+        ap_ST_fsm_state1 : begin
+            if (((1'b0 == ap_block_state1) & (1'b1 == ap_CS_fsm_state1))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end
+        end
+        ap_ST_fsm_state2 : begin
+            if (((grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s_fu_18_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state2))) begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end
+        end
+        default : begin
+            ap_NS_fsm = 'bx;
+        end
+    endcase
+end
+
+assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
+
+assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
+
+always @ (*) begin
+    ap_block_state1 = ((real_start == 1'b0) | (ap_done_reg == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_state1_ignore_call3 = ((real_start == 1'b0) | (ap_done_reg == 1'b1));
+end
+
+assign ap_ready = internal_ap_ready;
+
+assign grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s_fu_18_ap_start = grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s_fu_18_ap_start_reg;
+
+assign layer22_out_din = grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s_fu_18_layer22_out_din;
+
+assign start_out = real_start;
+
+endmodule //myproject_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_96u_config22_s

myproject_prj/solution1/syn/verilog/myproject_conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_s.v

@@ -0,0 +1,325 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+
+`timescale 1 ns / 1 ps 
+
+module myproject_conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_s (
+        ap_clk,
+        ap_rst,
+        ap_start,
+        start_full_n,
+        ap_done,
+        ap_continue,
+        ap_idle,
+        ap_ready,
+        start_out,
+        start_write,
+        layer44_out_dout,
+        layer44_out_num_data_valid,
+        layer44_out_fifo_cap,
+        layer44_out_empty_n,
+        layer44_out_read,
+        layer2_out_din,
+        layer2_out_num_data_valid,
+        layer2_out_fifo_cap,
+        layer2_out_full_n,
+        layer2_out_write
+);
+
+parameter    ap_ST_fsm_state1 = 3'd1;
+parameter    ap_ST_fsm_state2 = 3'd2;
+parameter    ap_ST_fsm_state3 = 3'd4;
+
+input   ap_clk;
+input   ap_rst;
+input   ap_start;
+input   start_full_n;
+output   ap_done;
+input   ap_continue;
+output   ap_idle;
+output   ap_ready;
+output   start_out;
+output   start_write;
+input  [15:0] layer44_out_dout;
+input  [13:0] layer44_out_num_data_valid;
+input  [13:0] layer44_out_fifo_cap;
+input   layer44_out_empty_n;
+output   layer44_out_read;
+output  [295:0] layer2_out_din;
+input  [12:0] layer2_out_num_data_valid;
+input  [12:0] layer2_out_fifo_cap;
+input   layer2_out_full_n;
+output   layer2_out_write;
+
+reg ap_done;
+reg ap_idle;
+reg start_write;
+reg layer2_out_write;
+
+reg    real_start;
+reg    start_once_reg;
+reg    ap_done_reg;
+(* fsm_encoding = "none" *) reg   [2:0] ap_CS_fsm;
+wire    ap_CS_fsm_state1;
+reg    internal_ap_ready;
+reg    layer44_out_blk_n;
+wire    ap_CS_fsm_state2;
+wire   [0:0] icmp_ln52_fu_128_p2;
+reg   [15:0] layer44_out_read_reg_155;
+reg    ap_block_state2;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s_fu_78_ap_start;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s_fu_78_ap_done;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s_fu_78_ap_idle;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s_fu_78_ap_ready;
+wire   [295:0] grp_compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s_fu_78_layer2_out_din;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s_fu_78_layer2_out_write;
+reg    grp_compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s_fu_78_ap_start_reg;
+reg    ap_block_state2_ignore_call3;
+wire    ap_CS_fsm_state3;
+reg   [12:0] indvar_flatten_fu_68;
+wire   [12:0] add_ln52_fu_134_p2;
+reg    ap_block_state1;
+reg    layer44_out_read_local;
+reg   [2:0] ap_NS_fsm;
+reg    ap_ST_fsm_state1_blk;
+reg    ap_ST_fsm_state2_blk;
+reg    ap_ST_fsm_state3_blk;
+wire    ap_ce_reg;
+
+// power-on initialization
+initial begin
+#0 start_once_reg = 1'b0;
+#0 ap_done_reg = 1'b0;
+#0 ap_CS_fsm = 3'd1;
+#0 grp_compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s_fu_78_ap_start_reg = 1'b0;
+#0 indvar_flatten_fu_68 = 13'd0;
+end
+
+myproject_compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s grp_compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s_fu_78(
+    .ap_clk(ap_clk),
+    .ap_rst(ap_rst),
+    .ap_start(grp_compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s_fu_78_ap_start),
+    .ap_done(grp_compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s_fu_78_ap_done),
+    .ap_idle(grp_compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s_fu_78_ap_idle),
+    .ap_ready(grp_compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s_fu_78_ap_ready),
+    .in_elem_0_0_0_0_0_val(layer44_out_read_reg_155),
+    .layer2_out_din(grp_compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s_fu_78_layer2_out_din),
+    .layer2_out_num_data_valid(13'd0),
+    .layer2_out_fifo_cap(13'd0),
+    .layer2_out_full_n(layer2_out_full_n),
+    .layer2_out_write(grp_compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s_fu_78_layer2_out_write)
+);
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_CS_fsm <= ap_ST_fsm_state1;
+    end else begin
+        ap_CS_fsm <= ap_NS_fsm;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_done_reg <= 1'b0;
+    end else begin
+        if ((ap_continue == 1'b1)) begin
+            ap_done_reg <= 1'b0;
+        end else if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_128_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+            ap_done_reg <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        grp_compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s_fu_78_ap_start_reg <= 1'b0;
+    end else begin
+        if (((1'b0 == ap_block_state2_ignore_call3) & (icmp_ln52_fu_128_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+            grp_compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s_fu_78_ap_start_reg <= 1'b1;
+        end else if ((grp_compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s_fu_78_ap_ready == 1'b1)) begin
+            grp_compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s_fu_78_ap_start_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        start_once_reg <= 1'b0;
+    end else begin
+        if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin
+            start_once_reg <= 1'b1;
+        end else if ((internal_ap_ready == 1'b1)) begin
+            start_once_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_state1) & (1'b1 == ap_CS_fsm_state1))) begin
+        indvar_flatten_fu_68 <= 13'd0;
+    end else if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_128_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        indvar_flatten_fu_68 <= add_ln52_fu_134_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_state2) & (1'b1 == ap_CS_fsm_state2))) begin
+        layer44_out_read_reg_155 <= layer44_out_dout;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_block_state1)) begin
+        ap_ST_fsm_state1_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state1_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_block_state2)) begin
+        ap_ST_fsm_state2_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state2_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((grp_compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s_fu_78_ap_done == 1'b0)) begin
+        ap_ST_fsm_state3_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state3_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_128_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+        ap_done = 1'b1;
+    end else begin
+        ap_done = ap_done_reg;
+    end
+end
+
+always @ (*) begin
+    if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
+        ap_idle = 1'b1;
+    end else begin
+        ap_idle = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_128_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+        internal_ap_ready = 1'b1;
+    end else begin
+        internal_ap_ready = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state3)) begin
+        layer2_out_write = grp_compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s_fu_78_layer2_out_write;
+    end else begin
+        layer2_out_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln52_fu_128_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        layer44_out_blk_n = layer44_out_empty_n;
+    end else begin
+        layer44_out_blk_n = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_128_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        layer44_out_read_local = 1'b1;
+    end else begin
+        layer44_out_read_local = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((start_once_reg == 1'b0) & (start_full_n == 1'b0))) begin
+        real_start = 1'b0;
+    end else begin
+        real_start = ap_start;
+    end
+end
+
+always @ (*) begin
+    if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin
+        start_write = 1'b1;
+    end else begin
+        start_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    case (ap_CS_fsm)
+        ap_ST_fsm_state1 : begin
+            if (((1'b0 == ap_block_state1) & (1'b1 == ap_CS_fsm_state1))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end
+        end
+        ap_ST_fsm_state2 : begin
+            if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_128_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end else if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_128_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end
+        end
+        ap_ST_fsm_state3 : begin
+            if (((grp_compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s_fu_78_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state3))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end
+        end
+        default : begin
+            ap_NS_fsm = 'bx;
+        end
+    endcase
+end
+
+assign add_ln52_fu_134_p2 = (indvar_flatten_fu_68 + 13'd1);
+
+assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
+
+assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
+
+assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2];
+
+always @ (*) begin
+    ap_block_state1 = ((real_start == 1'b0) | (ap_done_reg == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_state2 = ((icmp_ln52_fu_128_p2 == 1'd0) & (layer44_out_empty_n == 1'b0));
+end
+
+always @ (*) begin
+    ap_block_state2_ignore_call3 = ((icmp_ln52_fu_128_p2 == 1'd0) & (layer44_out_empty_n == 1'b0));
+end
+
+assign ap_ready = internal_ap_ready;
+
+assign grp_compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s_fu_78_ap_start = grp_compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s_fu_78_ap_start_reg;
+
+assign icmp_ln52_fu_128_p2 = ((indvar_flatten_fu_68 == 13'd4356) ? 1'b1 : 1'b0);
+
+assign layer2_out_din = grp_compute_output_buffer_2d_array_array_ap_fixed_37_17_5_3_0_8u_config2_s_fu_78_layer2_out_din;
+
+assign layer44_out_read = layer44_out_read_local;
+
+assign start_out = real_start;
+
+endmodule //myproject_conv_2d_cl_array_ap_fixed_1u_array_ap_fixed_37_17_5_3_0_8u_config2_s

myproject_prj/solution1/syn/verilog/myproject_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_s.v

@@ -0,0 +1,349 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+
+`timescale 1 ns / 1 ps 
+
+module myproject_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_s (
+        ap_clk,
+        ap_rst,
+        ap_start,
+        start_full_n,
+        ap_done,
+        ap_continue,
+        ap_idle,
+        ap_ready,
+        start_out,
+        start_write,
+        layer57_out_dout,
+        layer57_out_num_data_valid,
+        layer57_out_fifo_cap,
+        layer57_out_empty_n,
+        layer57_out_read,
+        layer37_out_din,
+        layer37_out_num_data_valid,
+        layer37_out_fifo_cap,
+        layer37_out_full_n,
+        layer37_out_write
+);
+
+parameter    ap_ST_fsm_state1 = 3'd1;
+parameter    ap_ST_fsm_state2 = 3'd2;
+parameter    ap_ST_fsm_state3 = 3'd4;
+
+input   ap_clk;
+input   ap_rst;
+input   ap_start;
+input   start_full_n;
+output   ap_done;
+input   ap_continue;
+output   ap_idle;
+output   ap_ready;
+output   start_out;
+output   start_write;
+input  [127:0] layer57_out_dout;
+input  [13:0] layer57_out_num_data_valid;
+input  [13:0] layer57_out_fifo_cap;
+input   layer57_out_empty_n;
+output   layer57_out_read;
+output  [319:0] layer37_out_din;
+input  [12:0] layer37_out_num_data_valid;
+input  [12:0] layer37_out_fifo_cap;
+input   layer37_out_full_n;
+output   layer37_out_write;
+
+reg ap_done;
+reg ap_idle;
+reg start_write;
+reg layer37_out_write;
+
+reg    real_start;
+reg    start_once_reg;
+reg    ap_done_reg;
+(* fsm_encoding = "none" *) reg   [2:0] ap_CS_fsm;
+wire    ap_CS_fsm_state1;
+reg    internal_ap_ready;
+reg    layer57_out_blk_n;
+wire    ap_CS_fsm_state2;
+wire   [0:0] icmp_ln52_fu_472_p2;
+wire   [15:0] trunc_ln58_fu_484_p1;
+reg   [15:0] trunc_ln58_reg_581;
+reg    ap_block_state2;
+reg   [15:0] trunc_ln58_s_reg_586;
+reg   [15:0] trunc_ln58_7_reg_591;
+reg   [15:0] trunc_ln58_8_reg_596;
+reg   [15:0] trunc_ln58_9_reg_601;
+reg   [15:0] trunc_ln58_1_reg_606;
+reg   [15:0] trunc_ln58_2_reg_611;
+reg   [15:0] trunc_ln58_3_reg_616;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s_fu_262_ap_start;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s_fu_262_ap_done;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s_fu_262_ap_idle;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s_fu_262_ap_ready;
+wire   [319:0] grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s_fu_262_layer37_out_din;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s_fu_262_layer37_out_write;
+reg    grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s_fu_262_ap_start_reg;
+reg    ap_block_state2_ignore_call11;
+wire    ap_CS_fsm_state3;
+reg   [12:0] indvar_flatten_fu_252;
+wire   [12:0] add_ln52_fu_478_p2;
+reg    ap_block_state1;
+reg    layer57_out_read_local;
+reg   [2:0] ap_NS_fsm;
+reg    ap_ST_fsm_state1_blk;
+reg    ap_ST_fsm_state2_blk;
+reg    ap_ST_fsm_state3_blk;
+wire    ap_ce_reg;
+
+// power-on initialization
+initial begin
+#0 start_once_reg = 1'b0;
+#0 ap_done_reg = 1'b0;
+#0 ap_CS_fsm = 3'd1;
+#0 grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s_fu_262_ap_start_reg = 1'b0;
+#0 indvar_flatten_fu_252 = 13'd0;
+end
+
+myproject_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s_fu_262(
+    .ap_clk(ap_clk),
+    .ap_rst(ap_rst),
+    .ap_start(grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s_fu_262_ap_start),
+    .ap_done(grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s_fu_262_ap_done),
+    .ap_idle(grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s_fu_262_ap_idle),
+    .ap_ready(grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s_fu_262_ap_ready),
+    .p_read(trunc_ln58_reg_581),
+    .p_read1(trunc_ln58_s_reg_586),
+    .p_read2(trunc_ln58_7_reg_591),
+    .p_read3(trunc_ln58_8_reg_596),
+    .p_read4(trunc_ln58_9_reg_601),
+    .p_read5(trunc_ln58_1_reg_606),
+    .p_read6(trunc_ln58_2_reg_611),
+    .p_read7(trunc_ln58_3_reg_616),
+    .layer37_out_din(grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s_fu_262_layer37_out_din),
+    .layer37_out_num_data_valid(13'd0),
+    .layer37_out_fifo_cap(13'd0),
+    .layer37_out_full_n(layer37_out_full_n),
+    .layer37_out_write(grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s_fu_262_layer37_out_write)
+);
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_CS_fsm <= ap_ST_fsm_state1;
+    end else begin
+        ap_CS_fsm <= ap_NS_fsm;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_done_reg <= 1'b0;
+    end else begin
+        if ((ap_continue == 1'b1)) begin
+            ap_done_reg <= 1'b0;
+        end else if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_472_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+            ap_done_reg <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s_fu_262_ap_start_reg <= 1'b0;
+    end else begin
+        if (((1'b0 == ap_block_state2_ignore_call11) & (icmp_ln52_fu_472_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+            grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s_fu_262_ap_start_reg <= 1'b1;
+        end else if ((grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s_fu_262_ap_ready == 1'b1)) begin
+            grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s_fu_262_ap_start_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        start_once_reg <= 1'b0;
+    end else begin
+        if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin
+            start_once_reg <= 1'b1;
+        end else if ((internal_ap_ready == 1'b1)) begin
+            start_once_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_state1) & (1'b1 == ap_CS_fsm_state1))) begin
+        indvar_flatten_fu_252 <= 13'd0;
+    end else if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_472_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        indvar_flatten_fu_252 <= add_ln52_fu_478_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_state2) & (1'b1 == ap_CS_fsm_state2))) begin
+        trunc_ln58_1_reg_606 <= {{layer57_out_dout[95:80]}};
+        trunc_ln58_2_reg_611 <= {{layer57_out_dout[111:96]}};
+        trunc_ln58_3_reg_616 <= {{layer57_out_dout[127:112]}};
+        trunc_ln58_7_reg_591 <= {{layer57_out_dout[47:32]}};
+        trunc_ln58_8_reg_596 <= {{layer57_out_dout[63:48]}};
+        trunc_ln58_9_reg_601 <= {{layer57_out_dout[79:64]}};
+        trunc_ln58_reg_581 <= trunc_ln58_fu_484_p1;
+        trunc_ln58_s_reg_586 <= {{layer57_out_dout[31:16]}};
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_block_state1)) begin
+        ap_ST_fsm_state1_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state1_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_block_state2)) begin
+        ap_ST_fsm_state2_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state2_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s_fu_262_ap_done == 1'b0)) begin
+        ap_ST_fsm_state3_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state3_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_472_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+        ap_done = 1'b1;
+    end else begin
+        ap_done = ap_done_reg;
+    end
+end
+
+always @ (*) begin
+    if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
+        ap_idle = 1'b1;
+    end else begin
+        ap_idle = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_472_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+        internal_ap_ready = 1'b1;
+    end else begin
+        internal_ap_ready = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state3)) begin
+        layer37_out_write = grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s_fu_262_layer37_out_write;
+    end else begin
+        layer37_out_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln52_fu_472_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        layer57_out_blk_n = layer57_out_empty_n;
+    end else begin
+        layer57_out_blk_n = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_472_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        layer57_out_read_local = 1'b1;
+    end else begin
+        layer57_out_read_local = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((start_once_reg == 1'b0) & (start_full_n == 1'b0))) begin
+        real_start = 1'b0;
+    end else begin
+        real_start = ap_start;
+    end
+end
+
+always @ (*) begin
+    if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin
+        start_write = 1'b1;
+    end else begin
+        start_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    case (ap_CS_fsm)
+        ap_ST_fsm_state1 : begin
+            if (((1'b0 == ap_block_state1) & (1'b1 == ap_CS_fsm_state1))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end
+        end
+        ap_ST_fsm_state2 : begin
+            if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_472_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end else if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_472_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end
+        end
+        ap_ST_fsm_state3 : begin
+            if (((grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s_fu_262_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state3))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end
+        end
+        default : begin
+            ap_NS_fsm = 'bx;
+        end
+    endcase
+end
+
+assign add_ln52_fu_478_p2 = (indvar_flatten_fu_252 + 13'd1);
+
+assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
+
+assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
+
+assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2];
+
+always @ (*) begin
+    ap_block_state1 = ((real_start == 1'b0) | (ap_done_reg == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_state2 = ((icmp_ln52_fu_472_p2 == 1'd0) & (layer57_out_empty_n == 1'b0));
+end
+
+always @ (*) begin
+    ap_block_state2_ignore_call11 = ((icmp_ln52_fu_472_p2 == 1'd0) & (layer57_out_empty_n == 1'b0));
+end
+
+assign ap_ready = internal_ap_ready;
+
+assign grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s_fu_262_ap_start = grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s_fu_262_ap_start_reg;
+
+assign icmp_ln52_fu_472_p2 = ((indvar_flatten_fu_252 == 13'd4356) ? 1'b1 : 1'b0);
+
+assign layer37_out_din = grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config37_s_fu_262_layer37_out_din;
+
+assign layer57_out_read = layer57_out_read_local;
+
+assign start_out = real_start;
+
+assign trunc_ln58_fu_484_p1 = layer57_out_dout[15:0];
+
+endmodule //myproject_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37_s

myproject_prj/solution1/syn/verilog/myproject_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_s.v

@@ -0,0 +1,349 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+
+`timescale 1 ns / 1 ps 
+
+module myproject_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_s (
+        ap_clk,
+        ap_rst,
+        ap_start,
+        start_full_n,
+        ap_done,
+        ap_continue,
+        ap_idle,
+        ap_ready,
+        start_out,
+        start_write,
+        layer45_out_dout,
+        layer45_out_num_data_valid,
+        layer45_out_fifo_cap,
+        layer45_out_empty_n,
+        layer45_out_read,
+        layer4_out_din,
+        layer4_out_num_data_valid,
+        layer4_out_fifo_cap,
+        layer4_out_full_n,
+        layer4_out_write
+);
+
+parameter    ap_ST_fsm_state1 = 3'd1;
+parameter    ap_ST_fsm_state2 = 3'd2;
+parameter    ap_ST_fsm_state3 = 3'd4;
+
+input   ap_clk;
+input   ap_rst;
+input   ap_start;
+input   start_full_n;
+output   ap_done;
+input   ap_continue;
+output   ap_idle;
+output   ap_ready;
+output   start_out;
+output   start_write;
+input  [127:0] layer45_out_dout;
+input  [13:0] layer45_out_num_data_valid;
+input  [13:0] layer45_out_fifo_cap;
+input   layer45_out_empty_n;
+output   layer45_out_read;
+output  [319:0] layer4_out_din;
+input  [12:0] layer4_out_num_data_valid;
+input  [12:0] layer4_out_fifo_cap;
+input   layer4_out_full_n;
+output   layer4_out_write;
+
+reg ap_done;
+reg ap_idle;
+reg start_write;
+reg layer4_out_write;
+
+reg    real_start;
+reg    start_once_reg;
+reg    ap_done_reg;
+(* fsm_encoding = "none" *) reg   [2:0] ap_CS_fsm;
+wire    ap_CS_fsm_state1;
+reg    internal_ap_ready;
+reg    layer45_out_blk_n;
+wire    ap_CS_fsm_state2;
+wire   [0:0] icmp_ln52_fu_472_p2;
+wire   [15:0] trunc_ln58_fu_484_p1;
+reg   [15:0] trunc_ln58_reg_581;
+reg    ap_block_state2;
+reg   [15:0] trunc_ln58_s_reg_586;
+reg   [15:0] trunc_ln58_1_reg_591;
+reg   [15:0] trunc_ln58_2_reg_596;
+reg   [15:0] trunc_ln58_3_reg_601;
+reg   [15:0] trunc_ln58_4_reg_606;
+reg   [15:0] trunc_ln58_5_reg_611;
+reg   [15:0] trunc_ln58_6_reg_616;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s_fu_262_ap_start;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s_fu_262_ap_done;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s_fu_262_ap_idle;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s_fu_262_ap_ready;
+wire   [319:0] grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s_fu_262_layer4_out_din;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s_fu_262_layer4_out_write;
+reg    grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s_fu_262_ap_start_reg;
+reg    ap_block_state2_ignore_call11;
+wire    ap_CS_fsm_state3;
+reg   [12:0] indvar_flatten_fu_252;
+wire   [12:0] add_ln52_fu_478_p2;
+reg    ap_block_state1;
+reg    layer45_out_read_local;
+reg   [2:0] ap_NS_fsm;
+reg    ap_ST_fsm_state1_blk;
+reg    ap_ST_fsm_state2_blk;
+reg    ap_ST_fsm_state3_blk;
+wire    ap_ce_reg;
+
+// power-on initialization
+initial begin
+#0 start_once_reg = 1'b0;
+#0 ap_done_reg = 1'b0;
+#0 ap_CS_fsm = 3'd1;
+#0 grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s_fu_262_ap_start_reg = 1'b0;
+#0 indvar_flatten_fu_252 = 13'd0;
+end
+
+myproject_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s_fu_262(
+    .ap_clk(ap_clk),
+    .ap_rst(ap_rst),
+    .ap_start(grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s_fu_262_ap_start),
+    .ap_done(grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s_fu_262_ap_done),
+    .ap_idle(grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s_fu_262_ap_idle),
+    .ap_ready(grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s_fu_262_ap_ready),
+    .p_read(trunc_ln58_reg_581),
+    .p_read1(trunc_ln58_s_reg_586),
+    .p_read2(trunc_ln58_1_reg_591),
+    .p_read3(trunc_ln58_2_reg_596),
+    .p_read4(trunc_ln58_3_reg_601),
+    .p_read5(trunc_ln58_4_reg_606),
+    .p_read6(trunc_ln58_5_reg_611),
+    .p_read7(trunc_ln58_6_reg_616),
+    .layer4_out_din(grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s_fu_262_layer4_out_din),
+    .layer4_out_num_data_valid(13'd0),
+    .layer4_out_fifo_cap(13'd0),
+    .layer4_out_full_n(layer4_out_full_n),
+    .layer4_out_write(grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s_fu_262_layer4_out_write)
+);
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_CS_fsm <= ap_ST_fsm_state1;
+    end else begin
+        ap_CS_fsm <= ap_NS_fsm;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_done_reg <= 1'b0;
+    end else begin
+        if ((ap_continue == 1'b1)) begin
+            ap_done_reg <= 1'b0;
+        end else if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_472_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+            ap_done_reg <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s_fu_262_ap_start_reg <= 1'b0;
+    end else begin
+        if (((1'b0 == ap_block_state2_ignore_call11) & (icmp_ln52_fu_472_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+            grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s_fu_262_ap_start_reg <= 1'b1;
+        end else if ((grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s_fu_262_ap_ready == 1'b1)) begin
+            grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s_fu_262_ap_start_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        start_once_reg <= 1'b0;
+    end else begin
+        if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin
+            start_once_reg <= 1'b1;
+        end else if ((internal_ap_ready == 1'b1)) begin
+            start_once_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_state1) & (1'b1 == ap_CS_fsm_state1))) begin
+        indvar_flatten_fu_252 <= 13'd0;
+    end else if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_472_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        indvar_flatten_fu_252 <= add_ln52_fu_478_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_state2) & (1'b1 == ap_CS_fsm_state2))) begin
+        trunc_ln58_1_reg_591 <= {{layer45_out_dout[47:32]}};
+        trunc_ln58_2_reg_596 <= {{layer45_out_dout[63:48]}};
+        trunc_ln58_3_reg_601 <= {{layer45_out_dout[79:64]}};
+        trunc_ln58_4_reg_606 <= {{layer45_out_dout[95:80]}};
+        trunc_ln58_5_reg_611 <= {{layer45_out_dout[111:96]}};
+        trunc_ln58_6_reg_616 <= {{layer45_out_dout[127:112]}};
+        trunc_ln58_reg_581 <= trunc_ln58_fu_484_p1;
+        trunc_ln58_s_reg_586 <= {{layer45_out_dout[31:16]}};
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_block_state1)) begin
+        ap_ST_fsm_state1_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state1_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_block_state2)) begin
+        ap_ST_fsm_state2_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state2_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s_fu_262_ap_done == 1'b0)) begin
+        ap_ST_fsm_state3_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state3_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_472_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+        ap_done = 1'b1;
+    end else begin
+        ap_done = ap_done_reg;
+    end
+end
+
+always @ (*) begin
+    if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
+        ap_idle = 1'b1;
+    end else begin
+        ap_idle = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_472_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+        internal_ap_ready = 1'b1;
+    end else begin
+        internal_ap_ready = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln52_fu_472_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        layer45_out_blk_n = layer45_out_empty_n;
+    end else begin
+        layer45_out_blk_n = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_472_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        layer45_out_read_local = 1'b1;
+    end else begin
+        layer45_out_read_local = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state3)) begin
+        layer4_out_write = grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s_fu_262_layer4_out_write;
+    end else begin
+        layer4_out_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((start_once_reg == 1'b0) & (start_full_n == 1'b0))) begin
+        real_start = 1'b0;
+    end else begin
+        real_start = ap_start;
+    end
+end
+
+always @ (*) begin
+    if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin
+        start_write = 1'b1;
+    end else begin
+        start_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    case (ap_CS_fsm)
+        ap_ST_fsm_state1 : begin
+            if (((1'b0 == ap_block_state1) & (1'b1 == ap_CS_fsm_state1))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end
+        end
+        ap_ST_fsm_state2 : begin
+            if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_472_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end else if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_472_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end
+        end
+        ap_ST_fsm_state3 : begin
+            if (((grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s_fu_262_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state3))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end
+        end
+        default : begin
+            ap_NS_fsm = 'bx;
+        end
+    endcase
+end
+
+assign add_ln52_fu_478_p2 = (indvar_flatten_fu_252 + 13'd1);
+
+assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
+
+assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
+
+assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2];
+
+always @ (*) begin
+    ap_block_state1 = ((real_start == 1'b0) | (ap_done_reg == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_state2 = ((icmp_ln52_fu_472_p2 == 1'd0) & (layer45_out_empty_n == 1'b0));
+end
+
+always @ (*) begin
+    ap_block_state2_ignore_call11 = ((icmp_ln52_fu_472_p2 == 1'd0) & (layer45_out_empty_n == 1'b0));
+end
+
+assign ap_ready = internal_ap_ready;
+
+assign grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s_fu_262_ap_start = grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s_fu_262_ap_start_reg;
+
+assign icmp_ln52_fu_472_p2 = ((indvar_flatten_fu_252 == 13'd4356) ? 1'b1 : 1'b0);
+
+assign layer45_out_read = layer45_out_read_local;
+
+assign layer4_out_din = grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_8u_config4_s_fu_262_layer4_out_din;
+
+assign start_out = real_start;
+
+assign trunc_ln58_fu_484_p1 = layer45_out_dout[15:0];
+
+endmodule //myproject_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config4_s

myproject_prj/solution1/syn/verilog/myproject_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_s.v

@@ -0,0 +1,469 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+
+`timescale 1 ns / 1 ps 
+
+module myproject_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_s (
+        ap_clk,
+        ap_rst,
+        ap_start,
+        start_full_n,
+        ap_done,
+        ap_continue,
+        ap_idle,
+        ap_ready,
+        start_out,
+        start_write,
+        layer54_out_dout,
+        layer54_out_num_data_valid,
+        layer54_out_fifo_cap,
+        layer54_out_empty_n,
+        layer54_out_read,
+        layer29_out_din,
+        layer29_out_num_data_valid,
+        layer29_out_fifo_cap,
+        layer29_out_full_n,
+        layer29_out_write
+);
+
+parameter    ap_ST_fsm_state1 = 3'd1;
+parameter    ap_ST_fsm_state2 = 3'd2;
+parameter    ap_ST_fsm_state3 = 3'd4;
+
+input   ap_clk;
+input   ap_rst;
+input   ap_start;
+input   start_full_n;
+output   ap_done;
+input   ap_continue;
+output   ap_idle;
+output   ap_ready;
+output   start_out;
+output   start_write;
+input  [767:0] layer54_out_dout;
+input  [11:0] layer54_out_num_data_valid;
+input  [11:0] layer54_out_fifo_cap;
+input   layer54_out_empty_n;
+output   layer54_out_read;
+output  [671:0] layer29_out_din;
+input  [10:0] layer29_out_num_data_valid;
+input  [10:0] layer29_out_fifo_cap;
+input   layer29_out_full_n;
+output   layer29_out_write;
+
+reg ap_done;
+reg ap_idle;
+reg start_write;
+reg layer29_out_write;
+
+reg    real_start;
+reg    start_once_reg;
+reg    ap_done_reg;
+(* fsm_encoding = "none" *) reg   [2:0] ap_CS_fsm;
+wire    ap_CS_fsm_state1;
+reg    internal_ap_ready;
+reg    layer54_out_blk_n;
+wire    ap_CS_fsm_state2;
+wire   [0:0] icmp_ln52_fu_2428_p2;
+wire   [15:0] trunc_ln58_fu_2440_p1;
+reg   [15:0] trunc_ln58_reg_2977;
+reg    ap_block_state2;
+reg   [15:0] trunc_ln58_180_reg_2982;
+reg   [15:0] trunc_ln58_181_reg_2987;
+reg   [15:0] trunc_ln58_182_reg_2992;
+reg   [15:0] trunc_ln58_183_reg_2997;
+reg   [15:0] trunc_ln58_184_reg_3002;
+reg   [15:0] trunc_ln58_185_reg_3007;
+reg   [15:0] trunc_ln58_186_reg_3012;
+reg   [15:0] trunc_ln58_187_reg_3017;
+reg   [15:0] trunc_ln58_188_reg_3022;
+reg   [15:0] trunc_ln58_189_reg_3027;
+reg   [15:0] trunc_ln58_190_reg_3032;
+reg   [15:0] trunc_ln58_191_reg_3037;
+reg   [15:0] trunc_ln58_192_reg_3042;
+reg   [15:0] trunc_ln58_193_reg_3047;
+reg   [15:0] trunc_ln58_194_reg_3052;
+reg   [15:0] trunc_ln58_195_reg_3057;
+reg   [15:0] trunc_ln58_196_reg_3062;
+reg   [15:0] trunc_ln58_197_reg_3067;
+reg   [15:0] trunc_ln58_198_reg_3072;
+reg   [15:0] trunc_ln58_199_reg_3077;
+reg   [15:0] trunc_ln58_200_reg_3082;
+reg   [15:0] trunc_ln58_201_reg_3087;
+reg   [15:0] trunc_ln58_202_reg_3092;
+reg   [15:0] trunc_ln58_203_reg_3097;
+reg   [15:0] trunc_ln58_204_reg_3102;
+reg   [15:0] trunc_ln58_205_reg_3107;
+reg   [15:0] trunc_ln58_206_reg_3112;
+reg   [15:0] trunc_ln58_s_reg_3117;
+reg   [15:0] trunc_ln58_207_reg_3122;
+reg   [15:0] trunc_ln58_208_reg_3127;
+reg   [15:0] trunc_ln58_209_reg_3132;
+reg   [15:0] trunc_ln58_210_reg_3137;
+reg   [15:0] trunc_ln58_211_reg_3142;
+reg   [15:0] trunc_ln58_212_reg_3147;
+reg   [15:0] trunc_ln58_213_reg_3152;
+reg   [15:0] trunc_ln58_214_reg_3157;
+reg   [15:0] trunc_ln58_215_reg_3162;
+reg   [15:0] trunc_ln58_216_reg_3167;
+reg   [15:0] trunc_ln58_217_reg_3172;
+reg   [15:0] trunc_ln58_218_reg_3177;
+reg   [15:0] trunc_ln58_219_reg_3182;
+reg   [15:0] trunc_ln58_220_reg_3187;
+reg   [15:0] trunc_ln58_221_reg_3192;
+reg   [15:0] trunc_ln58_222_reg_3197;
+reg   [15:0] trunc_ln58_223_reg_3202;
+reg   [15:0] trunc_ln58_224_reg_3207;
+reg   [15:0] trunc_ln58_225_reg_3212;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s_fu_1300_ap_start;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s_fu_1300_ap_done;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s_fu_1300_ap_idle;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s_fu_1300_ap_ready;
+wire   [671:0] grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s_fu_1300_layer29_out_din;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s_fu_1300_layer29_out_write;
+reg    grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s_fu_1300_ap_start_reg;
+reg    ap_block_state2_ignore_call51;
+wire    ap_CS_fsm_state3;
+reg   [10:0] indvar_flatten_fu_1290;
+wire   [10:0] add_ln52_fu_2434_p2;
+reg    ap_block_state1;
+reg    layer54_out_read_local;
+reg   [2:0] ap_NS_fsm;
+reg    ap_ST_fsm_state1_blk;
+reg    ap_ST_fsm_state2_blk;
+reg    ap_ST_fsm_state3_blk;
+wire    ap_ce_reg;
+
+// power-on initialization
+initial begin
+#0 start_once_reg = 1'b0;
+#0 ap_done_reg = 1'b0;
+#0 ap_CS_fsm = 3'd1;
+#0 grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s_fu_1300_ap_start_reg = 1'b0;
+#0 indvar_flatten_fu_1290 = 11'd0;
+end
+
+myproject_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s_fu_1300(
+    .ap_clk(ap_clk),
+    .ap_rst(ap_rst),
+    .ap_start(grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s_fu_1300_ap_start),
+    .ap_done(grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s_fu_1300_ap_done),
+    .ap_idle(grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s_fu_1300_ap_idle),
+    .ap_ready(grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s_fu_1300_ap_ready),
+    .p_read(trunc_ln58_reg_2977),
+    .p_read1(trunc_ln58_180_reg_2982),
+    .p_read2(trunc_ln58_181_reg_2987),
+    .p_read3(trunc_ln58_182_reg_2992),
+    .p_read4(trunc_ln58_183_reg_2997),
+    .p_read5(trunc_ln58_184_reg_3002),
+    .p_read6(trunc_ln58_185_reg_3007),
+    .p_read7(trunc_ln58_186_reg_3012),
+    .p_read8(trunc_ln58_187_reg_3017),
+    .p_read9(trunc_ln58_188_reg_3022),
+    .p_read10(trunc_ln58_189_reg_3027),
+    .p_read11(trunc_ln58_190_reg_3032),
+    .p_read12(trunc_ln58_191_reg_3037),
+    .p_read13(trunc_ln58_192_reg_3042),
+    .p_read14(trunc_ln58_193_reg_3047),
+    .p_read15(trunc_ln58_194_reg_3052),
+    .p_read16(trunc_ln58_195_reg_3057),
+    .p_read17(trunc_ln58_196_reg_3062),
+    .p_read18(trunc_ln58_197_reg_3067),
+    .p_read19(trunc_ln58_198_reg_3072),
+    .p_read20(trunc_ln58_199_reg_3077),
+    .p_read21(trunc_ln58_200_reg_3082),
+    .p_read22(trunc_ln58_201_reg_3087),
+    .p_read23(trunc_ln58_202_reg_3092),
+    .p_read24(trunc_ln58_203_reg_3097),
+    .p_read25(trunc_ln58_204_reg_3102),
+    .p_read26(trunc_ln58_205_reg_3107),
+    .p_read27(trunc_ln58_206_reg_3112),
+    .p_read28(trunc_ln58_s_reg_3117),
+    .p_read29(trunc_ln58_207_reg_3122),
+    .p_read30(trunc_ln58_208_reg_3127),
+    .p_read31(trunc_ln58_209_reg_3132),
+    .p_read32(trunc_ln58_210_reg_3137),
+    .p_read33(trunc_ln58_211_reg_3142),
+    .p_read34(trunc_ln58_212_reg_3147),
+    .p_read35(trunc_ln58_213_reg_3152),
+    .p_read36(trunc_ln58_214_reg_3157),
+    .p_read37(trunc_ln58_215_reg_3162),
+    .p_read38(trunc_ln58_216_reg_3167),
+    .p_read39(trunc_ln58_217_reg_3172),
+    .p_read40(trunc_ln58_218_reg_3177),
+    .p_read41(trunc_ln58_219_reg_3182),
+    .p_read42(trunc_ln58_220_reg_3187),
+    .p_read43(trunc_ln58_221_reg_3192),
+    .p_read44(trunc_ln58_222_reg_3197),
+    .p_read45(trunc_ln58_223_reg_3202),
+    .p_read46(trunc_ln58_224_reg_3207),
+    .p_read47(trunc_ln58_225_reg_3212),
+    .layer29_out_din(grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s_fu_1300_layer29_out_din),
+    .layer29_out_num_data_valid(11'd0),
+    .layer29_out_fifo_cap(11'd0),
+    .layer29_out_full_n(layer29_out_full_n),
+    .layer29_out_write(grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s_fu_1300_layer29_out_write)
+);
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_CS_fsm <= ap_ST_fsm_state1;
+    end else begin
+        ap_CS_fsm <= ap_NS_fsm;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_done_reg <= 1'b0;
+    end else begin
+        if ((ap_continue == 1'b1)) begin
+            ap_done_reg <= 1'b0;
+        end else if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_2428_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+            ap_done_reg <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s_fu_1300_ap_start_reg <= 1'b0;
+    end else begin
+        if (((1'b0 == ap_block_state2_ignore_call51) & (icmp_ln52_fu_2428_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+            grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s_fu_1300_ap_start_reg <= 1'b1;
+        end else if ((grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s_fu_1300_ap_ready == 1'b1)) begin
+            grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s_fu_1300_ap_start_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        start_once_reg <= 1'b0;
+    end else begin
+        if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin
+            start_once_reg <= 1'b1;
+        end else if ((internal_ap_ready == 1'b1)) begin
+            start_once_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_state1) & (1'b1 == ap_CS_fsm_state1))) begin
+        indvar_flatten_fu_1290 <= 11'd0;
+    end else if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_2428_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        indvar_flatten_fu_1290 <= add_ln52_fu_2434_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_state2) & (1'b1 == ap_CS_fsm_state2))) begin
+        trunc_ln58_180_reg_2982 <= {{layer54_out_dout[31:16]}};
+        trunc_ln58_181_reg_2987 <= {{layer54_out_dout[47:32]}};
+        trunc_ln58_182_reg_2992 <= {{layer54_out_dout[63:48]}};
+        trunc_ln58_183_reg_2997 <= {{layer54_out_dout[79:64]}};
+        trunc_ln58_184_reg_3002 <= {{layer54_out_dout[95:80]}};
+        trunc_ln58_185_reg_3007 <= {{layer54_out_dout[111:96]}};
+        trunc_ln58_186_reg_3012 <= {{layer54_out_dout[127:112]}};
+        trunc_ln58_187_reg_3017 <= {{layer54_out_dout[143:128]}};
+        trunc_ln58_188_reg_3022 <= {{layer54_out_dout[159:144]}};
+        trunc_ln58_189_reg_3027 <= {{layer54_out_dout[175:160]}};
+        trunc_ln58_190_reg_3032 <= {{layer54_out_dout[191:176]}};
+        trunc_ln58_191_reg_3037 <= {{layer54_out_dout[207:192]}};
+        trunc_ln58_192_reg_3042 <= {{layer54_out_dout[223:208]}};
+        trunc_ln58_193_reg_3047 <= {{layer54_out_dout[239:224]}};
+        trunc_ln58_194_reg_3052 <= {{layer54_out_dout[255:240]}};
+        trunc_ln58_195_reg_3057 <= {{layer54_out_dout[271:256]}};
+        trunc_ln58_196_reg_3062 <= {{layer54_out_dout[287:272]}};
+        trunc_ln58_197_reg_3067 <= {{layer54_out_dout[303:288]}};
+        trunc_ln58_198_reg_3072 <= {{layer54_out_dout[319:304]}};
+        trunc_ln58_199_reg_3077 <= {{layer54_out_dout[335:320]}};
+        trunc_ln58_200_reg_3082 <= {{layer54_out_dout[351:336]}};
+        trunc_ln58_201_reg_3087 <= {{layer54_out_dout[367:352]}};
+        trunc_ln58_202_reg_3092 <= {{layer54_out_dout[383:368]}};
+        trunc_ln58_203_reg_3097 <= {{layer54_out_dout[399:384]}};
+        trunc_ln58_204_reg_3102 <= {{layer54_out_dout[415:400]}};
+        trunc_ln58_205_reg_3107 <= {{layer54_out_dout[431:416]}};
+        trunc_ln58_206_reg_3112 <= {{layer54_out_dout[447:432]}};
+        trunc_ln58_207_reg_3122 <= {{layer54_out_dout[479:464]}};
+        trunc_ln58_208_reg_3127 <= {{layer54_out_dout[495:480]}};
+        trunc_ln58_209_reg_3132 <= {{layer54_out_dout[511:496]}};
+        trunc_ln58_210_reg_3137 <= {{layer54_out_dout[527:512]}};
+        trunc_ln58_211_reg_3142 <= {{layer54_out_dout[543:528]}};
+        trunc_ln58_212_reg_3147 <= {{layer54_out_dout[559:544]}};
+        trunc_ln58_213_reg_3152 <= {{layer54_out_dout[575:560]}};
+        trunc_ln58_214_reg_3157 <= {{layer54_out_dout[591:576]}};
+        trunc_ln58_215_reg_3162 <= {{layer54_out_dout[607:592]}};
+        trunc_ln58_216_reg_3167 <= {{layer54_out_dout[623:608]}};
+        trunc_ln58_217_reg_3172 <= {{layer54_out_dout[639:624]}};
+        trunc_ln58_218_reg_3177 <= {{layer54_out_dout[655:640]}};
+        trunc_ln58_219_reg_3182 <= {{layer54_out_dout[671:656]}};
+        trunc_ln58_220_reg_3187 <= {{layer54_out_dout[687:672]}};
+        trunc_ln58_221_reg_3192 <= {{layer54_out_dout[703:688]}};
+        trunc_ln58_222_reg_3197 <= {{layer54_out_dout[719:704]}};
+        trunc_ln58_223_reg_3202 <= {{layer54_out_dout[735:720]}};
+        trunc_ln58_224_reg_3207 <= {{layer54_out_dout[751:736]}};
+        trunc_ln58_225_reg_3212 <= {{layer54_out_dout[767:752]}};
+        trunc_ln58_reg_2977 <= trunc_ln58_fu_2440_p1;
+        trunc_ln58_s_reg_3117 <= {{layer54_out_dout[463:448]}};
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_block_state1)) begin
+        ap_ST_fsm_state1_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state1_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_block_state2)) begin
+        ap_ST_fsm_state2_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state2_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s_fu_1300_ap_done == 1'b0)) begin
+        ap_ST_fsm_state3_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state3_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_2428_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+        ap_done = 1'b1;
+    end else begin
+        ap_done = ap_done_reg;
+    end
+end
+
+always @ (*) begin
+    if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
+        ap_idle = 1'b1;
+    end else begin
+        ap_idle = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_2428_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+        internal_ap_ready = 1'b1;
+    end else begin
+        internal_ap_ready = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state3)) begin
+        layer29_out_write = grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s_fu_1300_layer29_out_write;
+    end else begin
+        layer29_out_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln52_fu_2428_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        layer54_out_blk_n = layer54_out_empty_n;
+    end else begin
+        layer54_out_blk_n = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_2428_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        layer54_out_read_local = 1'b1;
+    end else begin
+        layer54_out_read_local = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((start_once_reg == 1'b0) & (start_full_n == 1'b0))) begin
+        real_start = 1'b0;
+    end else begin
+        real_start = ap_start;
+    end
+end
+
+always @ (*) begin
+    if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin
+        start_write = 1'b1;
+    end else begin
+        start_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    case (ap_CS_fsm)
+        ap_ST_fsm_state1 : begin
+            if (((1'b0 == ap_block_state1) & (1'b1 == ap_CS_fsm_state1))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end
+        end
+        ap_ST_fsm_state2 : begin
+            if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_2428_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end else if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_2428_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end
+        end
+        ap_ST_fsm_state3 : begin
+            if (((1'b1 == ap_CS_fsm_state3) & (grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s_fu_1300_ap_done == 1'b1))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end
+        end
+        default : begin
+            ap_NS_fsm = 'bx;
+        end
+    endcase
+end
+
+assign add_ln52_fu_2434_p2 = (indvar_flatten_fu_1290 + 11'd1);
+
+assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
+
+assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
+
+assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2];
+
+always @ (*) begin
+    ap_block_state1 = ((real_start == 1'b0) | (ap_done_reg == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_state2 = ((icmp_ln52_fu_2428_p2 == 1'd0) & (layer54_out_empty_n == 1'b0));
+end
+
+always @ (*) begin
+    ap_block_state2_ignore_call51 = ((icmp_ln52_fu_2428_p2 == 1'd0) & (layer54_out_empty_n == 1'b0));
+end
+
+assign ap_ready = internal_ap_ready;
+
+assign grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s_fu_1300_ap_start = grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s_fu_1300_ap_start_reg;
+
+assign icmp_ln52_fu_2428_p2 = ((indvar_flatten_fu_1290 == 11'd1156) ? 1'b1 : 1'b0);
+
+assign layer29_out_din = grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_16u_config29_s_fu_1300_layer29_out_din;
+
+assign layer54_out_read = layer54_out_read_local;
+
+assign start_out = real_start;
+
+assign trunc_ln58_fu_2440_p1 = layer54_out_dout[15:0];
+
+endmodule //myproject_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_16u_config29_s

myproject_prj/solution1/syn/verilog/myproject_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_s.v

@@ -0,0 +1,421 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+
+`timescale 1 ns / 1 ps 
+
+module myproject_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_s (
+        ap_clk,
+        ap_rst,
+        ap_start,
+        start_full_n,
+        ap_done,
+        ap_continue,
+        ap_idle,
+        ap_ready,
+        start_out,
+        start_write,
+        layer49_out_dout,
+        layer49_out_num_data_valid,
+        layer49_out_fifo_cap,
+        layer49_out_empty_n,
+        layer49_out_read,
+        layer14_out_din,
+        layer14_out_num_data_valid,
+        layer14_out_fifo_cap,
+        layer14_out_full_n,
+        layer14_out_write
+);
+
+parameter    ap_ST_fsm_state1 = 3'd1;
+parameter    ap_ST_fsm_state2 = 3'd2;
+parameter    ap_ST_fsm_state3 = 3'd4;
+
+input   ap_clk;
+input   ap_rst;
+input   ap_start;
+input   start_full_n;
+output   ap_done;
+input   ap_continue;
+output   ap_idle;
+output   ap_ready;
+output   start_out;
+output   start_write;
+input  [511:0] layer49_out_dout;
+input  [9:0] layer49_out_num_data_valid;
+input  [9:0] layer49_out_fifo_cap;
+input   layer49_out_empty_n;
+output   layer49_out_read;
+output  [1343:0] layer14_out_din;
+input  [8:0] layer14_out_num_data_valid;
+input  [8:0] layer14_out_fifo_cap;
+input   layer14_out_full_n;
+output   layer14_out_write;
+
+reg ap_done;
+reg ap_idle;
+reg start_write;
+reg layer14_out_write;
+
+reg    real_start;
+reg    start_once_reg;
+reg    ap_done_reg;
+(* fsm_encoding = "none" *) reg   [2:0] ap_CS_fsm;
+wire    ap_CS_fsm_state1;
+reg    internal_ap_ready;
+reg    layer49_out_blk_n;
+wire    ap_CS_fsm_state2;
+wire   [0:0] icmp_ln52_fu_1648_p2;
+wire   [15:0] trunc_ln58_fu_1660_p1;
+reg   [15:0] trunc_ln58_reg_2021;
+reg    ap_block_state2;
+reg   [15:0] trunc_ln58_s_reg_2026;
+reg   [15:0] trunc_ln58_168_reg_2031;
+reg   [15:0] trunc_ln58_169_reg_2036;
+reg   [15:0] trunc_ln58_170_reg_2041;
+reg   [15:0] trunc_ln58_171_reg_2046;
+reg   [15:0] trunc_ln58_172_reg_2051;
+reg   [15:0] trunc_ln58_173_reg_2056;
+reg   [15:0] trunc_ln58_174_reg_2061;
+reg   [15:0] trunc_ln58_175_reg_2066;
+reg   [15:0] trunc_ln58_176_reg_2071;
+reg   [15:0] trunc_ln58_177_reg_2076;
+reg   [15:0] trunc_ln58_178_reg_2081;
+reg   [15:0] trunc_ln58_179_reg_2086;
+reg   [15:0] trunc_ln58_180_reg_2091;
+reg   [15:0] trunc_ln58_181_reg_2096;
+reg   [15:0] trunc_ln58_182_reg_2101;
+reg   [15:0] trunc_ln58_183_reg_2106;
+reg   [15:0] trunc_ln58_184_reg_2111;
+reg   [15:0] trunc_ln58_185_reg_2116;
+reg   [15:0] trunc_ln58_186_reg_2121;
+reg   [15:0] trunc_ln58_187_reg_2126;
+reg   [15:0] trunc_ln58_188_reg_2131;
+reg   [15:0] trunc_ln58_189_reg_2136;
+reg   [15:0] trunc_ln58_190_reg_2141;
+reg   [15:0] trunc_ln58_191_reg_2146;
+reg   [15:0] trunc_ln58_192_reg_2151;
+reg   [15:0] trunc_ln58_193_reg_2156;
+reg   [15:0] trunc_ln58_194_reg_2161;
+reg   [15:0] trunc_ln58_195_reg_2166;
+reg   [15:0] trunc_ln58_196_reg_2171;
+reg   [15:0] trunc_ln58_197_reg_2176;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s_fu_886_ap_start;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s_fu_886_ap_done;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s_fu_886_ap_idle;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s_fu_886_ap_ready;
+wire   [1343:0] grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s_fu_886_layer14_out_din;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s_fu_886_layer14_out_write;
+reg    grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s_fu_886_ap_start_reg;
+reg    ap_block_state2_ignore_call35;
+wire    ap_CS_fsm_state3;
+reg   [8:0] indvar_flatten_fu_876;
+wire   [8:0] add_ln52_fu_1654_p2;
+reg    ap_block_state1;
+reg    layer49_out_read_local;
+reg   [2:0] ap_NS_fsm;
+reg    ap_ST_fsm_state1_blk;
+reg    ap_ST_fsm_state2_blk;
+reg    ap_ST_fsm_state3_blk;
+wire    ap_ce_reg;
+
+// power-on initialization
+initial begin
+#0 start_once_reg = 1'b0;
+#0 ap_done_reg = 1'b0;
+#0 ap_CS_fsm = 3'd1;
+#0 grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s_fu_886_ap_start_reg = 1'b0;
+#0 indvar_flatten_fu_876 = 9'd0;
+end
+
+myproject_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s_fu_886(
+    .ap_clk(ap_clk),
+    .ap_rst(ap_rst),
+    .ap_start(grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s_fu_886_ap_start),
+    .ap_done(grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s_fu_886_ap_done),
+    .ap_idle(grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s_fu_886_ap_idle),
+    .ap_ready(grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s_fu_886_ap_ready),
+    .p_read(trunc_ln58_reg_2021),
+    .p_read1(trunc_ln58_s_reg_2026),
+    .p_read2(trunc_ln58_168_reg_2031),
+    .p_read3(trunc_ln58_169_reg_2036),
+    .p_read4(trunc_ln58_170_reg_2041),
+    .p_read5(trunc_ln58_171_reg_2046),
+    .p_read6(trunc_ln58_172_reg_2051),
+    .p_read7(trunc_ln58_173_reg_2056),
+    .p_read8(trunc_ln58_174_reg_2061),
+    .p_read9(trunc_ln58_175_reg_2066),
+    .p_read10(trunc_ln58_176_reg_2071),
+    .p_read11(trunc_ln58_177_reg_2076),
+    .p_read12(trunc_ln58_178_reg_2081),
+    .p_read13(trunc_ln58_179_reg_2086),
+    .p_read14(trunc_ln58_180_reg_2091),
+    .p_read15(trunc_ln58_181_reg_2096),
+    .p_read16(trunc_ln58_182_reg_2101),
+    .p_read17(trunc_ln58_183_reg_2106),
+    .p_read18(trunc_ln58_184_reg_2111),
+    .p_read19(trunc_ln58_185_reg_2116),
+    .p_read20(trunc_ln58_186_reg_2121),
+    .p_read21(trunc_ln58_187_reg_2126),
+    .p_read22(trunc_ln58_188_reg_2131),
+    .p_read23(trunc_ln58_189_reg_2136),
+    .p_read24(trunc_ln58_190_reg_2141),
+    .p_read25(trunc_ln58_191_reg_2146),
+    .p_read26(trunc_ln58_192_reg_2151),
+    .p_read27(trunc_ln58_193_reg_2156),
+    .p_read28(trunc_ln58_194_reg_2161),
+    .p_read29(trunc_ln58_195_reg_2166),
+    .p_read30(trunc_ln58_196_reg_2171),
+    .p_read31(trunc_ln58_197_reg_2176),
+    .layer14_out_din(grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s_fu_886_layer14_out_din),
+    .layer14_out_num_data_valid(9'd0),
+    .layer14_out_fifo_cap(9'd0),
+    .layer14_out_full_n(layer14_out_full_n),
+    .layer14_out_write(grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s_fu_886_layer14_out_write)
+);
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_CS_fsm <= ap_ST_fsm_state1;
+    end else begin
+        ap_CS_fsm <= ap_NS_fsm;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_done_reg <= 1'b0;
+    end else begin
+        if ((ap_continue == 1'b1)) begin
+            ap_done_reg <= 1'b0;
+        end else if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_1648_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+            ap_done_reg <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s_fu_886_ap_start_reg <= 1'b0;
+    end else begin
+        if (((1'b0 == ap_block_state2_ignore_call35) & (icmp_ln52_fu_1648_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+            grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s_fu_886_ap_start_reg <= 1'b1;
+        end else if ((grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s_fu_886_ap_ready == 1'b1)) begin
+            grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s_fu_886_ap_start_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        start_once_reg <= 1'b0;
+    end else begin
+        if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin
+            start_once_reg <= 1'b1;
+        end else if ((internal_ap_ready == 1'b1)) begin
+            start_once_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_state1) & (1'b1 == ap_CS_fsm_state1))) begin
+        indvar_flatten_fu_876 <= 9'd0;
+    end else if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_1648_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        indvar_flatten_fu_876 <= add_ln52_fu_1654_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_state2) & (1'b1 == ap_CS_fsm_state2))) begin
+        trunc_ln58_168_reg_2031 <= {{layer49_out_dout[47:32]}};
+        trunc_ln58_169_reg_2036 <= {{layer49_out_dout[63:48]}};
+        trunc_ln58_170_reg_2041 <= {{layer49_out_dout[79:64]}};
+        trunc_ln58_171_reg_2046 <= {{layer49_out_dout[95:80]}};
+        trunc_ln58_172_reg_2051 <= {{layer49_out_dout[111:96]}};
+        trunc_ln58_173_reg_2056 <= {{layer49_out_dout[127:112]}};
+        trunc_ln58_174_reg_2061 <= {{layer49_out_dout[143:128]}};
+        trunc_ln58_175_reg_2066 <= {{layer49_out_dout[159:144]}};
+        trunc_ln58_176_reg_2071 <= {{layer49_out_dout[175:160]}};
+        trunc_ln58_177_reg_2076 <= {{layer49_out_dout[191:176]}};
+        trunc_ln58_178_reg_2081 <= {{layer49_out_dout[207:192]}};
+        trunc_ln58_179_reg_2086 <= {{layer49_out_dout[223:208]}};
+        trunc_ln58_180_reg_2091 <= {{layer49_out_dout[239:224]}};
+        trunc_ln58_181_reg_2096 <= {{layer49_out_dout[255:240]}};
+        trunc_ln58_182_reg_2101 <= {{layer49_out_dout[271:256]}};
+        trunc_ln58_183_reg_2106 <= {{layer49_out_dout[287:272]}};
+        trunc_ln58_184_reg_2111 <= {{layer49_out_dout[303:288]}};
+        trunc_ln58_185_reg_2116 <= {{layer49_out_dout[319:304]}};
+        trunc_ln58_186_reg_2121 <= {{layer49_out_dout[335:320]}};
+        trunc_ln58_187_reg_2126 <= {{layer49_out_dout[351:336]}};
+        trunc_ln58_188_reg_2131 <= {{layer49_out_dout[367:352]}};
+        trunc_ln58_189_reg_2136 <= {{layer49_out_dout[383:368]}};
+        trunc_ln58_190_reg_2141 <= {{layer49_out_dout[399:384]}};
+        trunc_ln58_191_reg_2146 <= {{layer49_out_dout[415:400]}};
+        trunc_ln58_192_reg_2151 <= {{layer49_out_dout[431:416]}};
+        trunc_ln58_193_reg_2156 <= {{layer49_out_dout[447:432]}};
+        trunc_ln58_194_reg_2161 <= {{layer49_out_dout[463:448]}};
+        trunc_ln58_195_reg_2166 <= {{layer49_out_dout[479:464]}};
+        trunc_ln58_196_reg_2171 <= {{layer49_out_dout[495:480]}};
+        trunc_ln58_197_reg_2176 <= {{layer49_out_dout[511:496]}};
+        trunc_ln58_reg_2021 <= trunc_ln58_fu_1660_p1;
+        trunc_ln58_s_reg_2026 <= {{layer49_out_dout[31:16]}};
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_block_state1)) begin
+        ap_ST_fsm_state1_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state1_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_block_state2)) begin
+        ap_ST_fsm_state2_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state2_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s_fu_886_ap_done == 1'b0)) begin
+        ap_ST_fsm_state3_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state3_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_1648_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+        ap_done = 1'b1;
+    end else begin
+        ap_done = ap_done_reg;
+    end
+end
+
+always @ (*) begin
+    if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
+        ap_idle = 1'b1;
+    end else begin
+        ap_idle = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_1648_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+        internal_ap_ready = 1'b1;
+    end else begin
+        internal_ap_ready = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state3)) begin
+        layer14_out_write = grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s_fu_886_layer14_out_write;
+    end else begin
+        layer14_out_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln52_fu_1648_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        layer49_out_blk_n = layer49_out_empty_n;
+    end else begin
+        layer49_out_blk_n = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_1648_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        layer49_out_read_local = 1'b1;
+    end else begin
+        layer49_out_read_local = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((start_once_reg == 1'b0) & (start_full_n == 1'b0))) begin
+        real_start = 1'b0;
+    end else begin
+        real_start = ap_start;
+    end
+end
+
+always @ (*) begin
+    if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin
+        start_write = 1'b1;
+    end else begin
+        start_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    case (ap_CS_fsm)
+        ap_ST_fsm_state1 : begin
+            if (((1'b0 == ap_block_state1) & (1'b1 == ap_CS_fsm_state1))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end
+        end
+        ap_ST_fsm_state2 : begin
+            if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_1648_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end else if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_1648_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end
+        end
+        ap_ST_fsm_state3 : begin
+            if (((1'b1 == ap_CS_fsm_state3) & (grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s_fu_886_ap_done == 1'b1))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end
+        end
+        default : begin
+            ap_NS_fsm = 'bx;
+        end
+    endcase
+end
+
+assign add_ln52_fu_1654_p2 = (indvar_flatten_fu_876 + 9'd1);
+
+assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
+
+assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
+
+assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2];
+
+always @ (*) begin
+    ap_block_state1 = ((real_start == 1'b0) | (ap_done_reg == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_state2 = ((icmp_ln52_fu_1648_p2 == 1'd0) & (layer49_out_empty_n == 1'b0));
+end
+
+always @ (*) begin
+    ap_block_state2_ignore_call35 = ((icmp_ln52_fu_1648_p2 == 1'd0) & (layer49_out_empty_n == 1'b0));
+end
+
+assign ap_ready = internal_ap_ready;
+
+assign grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s_fu_886_ap_start = grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s_fu_886_ap_start_reg;
+
+assign icmp_ln52_fu_1648_p2 = ((indvar_flatten_fu_876 == 9'd324) ? 1'b1 : 1'b0);
+
+assign layer14_out_din = grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_32u_config14_s_fu_886_layer14_out_din;
+
+assign layer49_out_read = layer49_out_read_local;
+
+assign start_out = real_start;
+
+assign trunc_ln58_fu_1660_p1 = layer49_out_dout[15:0];
+
+endmodule //myproject_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_32u_config14_s

myproject_prj/solution1/syn/verilog/myproject_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_s.v

@@ -0,0 +1,421 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+
+`timescale 1 ns / 1 ps 
+
+module myproject_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_s (
+        ap_clk,
+        ap_rst,
+        ap_start,
+        start_full_n,
+        ap_done,
+        ap_continue,
+        ap_idle,
+        ap_ready,
+        start_out,
+        start_write,
+        layer50_out_dout,
+        layer50_out_num_data_valid,
+        layer50_out_fifo_cap,
+        layer50_out_empty_n,
+        layer50_out_read,
+        layer17_out_din,
+        layer17_out_num_data_valid,
+        layer17_out_fifo_cap,
+        layer17_out_full_n,
+        layer17_out_write
+);
+
+parameter    ap_ST_fsm_state1 = 3'd1;
+parameter    ap_ST_fsm_state2 = 3'd2;
+parameter    ap_ST_fsm_state3 = 3'd4;
+
+input   ap_clk;
+input   ap_rst;
+input   ap_start;
+input   start_full_n;
+output   ap_done;
+input   ap_continue;
+output   ap_idle;
+output   ap_ready;
+output   start_out;
+output   start_write;
+input  [511:0] layer50_out_dout;
+input  [7:0] layer50_out_num_data_valid;
+input  [7:0] layer50_out_fifo_cap;
+input   layer50_out_empty_n;
+output   layer50_out_read;
+output  [2687:0] layer17_out_din;
+input  [6:0] layer17_out_num_data_valid;
+input  [6:0] layer17_out_fifo_cap;
+input   layer17_out_full_n;
+output   layer17_out_write;
+
+reg ap_done;
+reg ap_idle;
+reg start_write;
+reg layer17_out_write;
+
+reg    real_start;
+reg    start_once_reg;
+reg    ap_done_reg;
+(* fsm_encoding = "none" *) reg   [2:0] ap_CS_fsm;
+wire    ap_CS_fsm_state1;
+reg    internal_ap_ready;
+reg    layer50_out_blk_n;
+wire    ap_CS_fsm_state2;
+wire   [0:0] icmp_ln52_fu_1648_p2;
+wire   [15:0] trunc_ln58_fu_1660_p1;
+reg   [15:0] trunc_ln58_reg_2021;
+reg    ap_block_state2;
+reg   [15:0] trunc_ln58_s_reg_2026;
+reg   [15:0] trunc_ln58_108_reg_2031;
+reg   [15:0] trunc_ln58_109_reg_2036;
+reg   [15:0] trunc_ln58_110_reg_2041;
+reg   [15:0] trunc_ln58_111_reg_2046;
+reg   [15:0] trunc_ln58_112_reg_2051;
+reg   [15:0] trunc_ln58_113_reg_2056;
+reg   [15:0] trunc_ln58_114_reg_2061;
+reg   [15:0] trunc_ln58_115_reg_2066;
+reg   [15:0] trunc_ln58_116_reg_2071;
+reg   [15:0] trunc_ln58_117_reg_2076;
+reg   [15:0] trunc_ln58_118_reg_2081;
+reg   [15:0] trunc_ln58_119_reg_2086;
+reg   [15:0] trunc_ln58_120_reg_2091;
+reg   [15:0] trunc_ln58_121_reg_2096;
+reg   [15:0] trunc_ln58_122_reg_2101;
+reg   [15:0] trunc_ln58_123_reg_2106;
+reg   [15:0] trunc_ln58_124_reg_2111;
+reg   [15:0] trunc_ln58_125_reg_2116;
+reg   [15:0] trunc_ln58_126_reg_2121;
+reg   [15:0] trunc_ln58_127_reg_2126;
+reg   [15:0] trunc_ln58_128_reg_2131;
+reg   [15:0] trunc_ln58_129_reg_2136;
+reg   [15:0] trunc_ln58_130_reg_2141;
+reg   [15:0] trunc_ln58_131_reg_2146;
+reg   [15:0] trunc_ln58_132_reg_2151;
+reg   [15:0] trunc_ln58_133_reg_2156;
+reg   [15:0] trunc_ln58_134_reg_2161;
+reg   [15:0] trunc_ln58_135_reg_2166;
+reg   [15:0] trunc_ln58_136_reg_2171;
+reg   [15:0] trunc_ln58_137_reg_2176;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s_fu_886_ap_start;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s_fu_886_ap_done;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s_fu_886_ap_idle;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s_fu_886_ap_ready;
+wire   [2687:0] grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s_fu_886_layer17_out_din;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s_fu_886_layer17_out_write;
+reg    grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s_fu_886_ap_start_reg;
+reg    ap_block_state2_ignore_call35;
+wire    ap_CS_fsm_state3;
+reg   [6:0] indvar_flatten_fu_876;
+wire   [6:0] add_ln52_fu_1654_p2;
+reg    ap_block_state1;
+reg    layer50_out_read_local;
+reg   [2:0] ap_NS_fsm;
+reg    ap_ST_fsm_state1_blk;
+reg    ap_ST_fsm_state2_blk;
+reg    ap_ST_fsm_state3_blk;
+wire    ap_ce_reg;
+
+// power-on initialization
+initial begin
+#0 start_once_reg = 1'b0;
+#0 ap_done_reg = 1'b0;
+#0 ap_CS_fsm = 3'd1;
+#0 grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s_fu_886_ap_start_reg = 1'b0;
+#0 indvar_flatten_fu_876 = 7'd0;
+end
+
+myproject_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s_fu_886(
+    .ap_clk(ap_clk),
+    .ap_rst(ap_rst),
+    .ap_start(grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s_fu_886_ap_start),
+    .ap_done(grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s_fu_886_ap_done),
+    .ap_idle(grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s_fu_886_ap_idle),
+    .ap_ready(grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s_fu_886_ap_ready),
+    .p_read(trunc_ln58_reg_2021),
+    .p_read1(trunc_ln58_s_reg_2026),
+    .p_read2(trunc_ln58_108_reg_2031),
+    .p_read3(trunc_ln58_109_reg_2036),
+    .p_read4(trunc_ln58_110_reg_2041),
+    .p_read5(trunc_ln58_111_reg_2046),
+    .p_read6(trunc_ln58_112_reg_2051),
+    .p_read7(trunc_ln58_113_reg_2056),
+    .p_read8(trunc_ln58_114_reg_2061),
+    .p_read9(trunc_ln58_115_reg_2066),
+    .p_read10(trunc_ln58_116_reg_2071),
+    .p_read11(trunc_ln58_117_reg_2076),
+    .p_read12(trunc_ln58_118_reg_2081),
+    .p_read13(trunc_ln58_119_reg_2086),
+    .p_read14(trunc_ln58_120_reg_2091),
+    .p_read15(trunc_ln58_121_reg_2096),
+    .p_read16(trunc_ln58_122_reg_2101),
+    .p_read17(trunc_ln58_123_reg_2106),
+    .p_read18(trunc_ln58_124_reg_2111),
+    .p_read19(trunc_ln58_125_reg_2116),
+    .p_read20(trunc_ln58_126_reg_2121),
+    .p_read21(trunc_ln58_127_reg_2126),
+    .p_read22(trunc_ln58_128_reg_2131),
+    .p_read23(trunc_ln58_129_reg_2136),
+    .p_read24(trunc_ln58_130_reg_2141),
+    .p_read25(trunc_ln58_131_reg_2146),
+    .p_read26(trunc_ln58_132_reg_2151),
+    .p_read27(trunc_ln58_133_reg_2156),
+    .p_read28(trunc_ln58_134_reg_2161),
+    .p_read29(trunc_ln58_135_reg_2166),
+    .p_read30(trunc_ln58_136_reg_2171),
+    .p_read31(trunc_ln58_137_reg_2176),
+    .layer17_out_din(grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s_fu_886_layer17_out_din),
+    .layer17_out_num_data_valid(7'd0),
+    .layer17_out_fifo_cap(7'd0),
+    .layer17_out_full_n(layer17_out_full_n),
+    .layer17_out_write(grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s_fu_886_layer17_out_write)
+);
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_CS_fsm <= ap_ST_fsm_state1;
+    end else begin
+        ap_CS_fsm <= ap_NS_fsm;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_done_reg <= 1'b0;
+    end else begin
+        if ((ap_continue == 1'b1)) begin
+            ap_done_reg <= 1'b0;
+        end else if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_1648_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+            ap_done_reg <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s_fu_886_ap_start_reg <= 1'b0;
+    end else begin
+        if (((1'b0 == ap_block_state2_ignore_call35) & (icmp_ln52_fu_1648_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+            grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s_fu_886_ap_start_reg <= 1'b1;
+        end else if ((grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s_fu_886_ap_ready == 1'b1)) begin
+            grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s_fu_886_ap_start_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        start_once_reg <= 1'b0;
+    end else begin
+        if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin
+            start_once_reg <= 1'b1;
+        end else if ((internal_ap_ready == 1'b1)) begin
+            start_once_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_state1) & (1'b1 == ap_CS_fsm_state1))) begin
+        indvar_flatten_fu_876 <= 7'd0;
+    end else if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_1648_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        indvar_flatten_fu_876 <= add_ln52_fu_1654_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_state2) & (1'b1 == ap_CS_fsm_state2))) begin
+        trunc_ln58_108_reg_2031 <= {{layer50_out_dout[47:32]}};
+        trunc_ln58_109_reg_2036 <= {{layer50_out_dout[63:48]}};
+        trunc_ln58_110_reg_2041 <= {{layer50_out_dout[79:64]}};
+        trunc_ln58_111_reg_2046 <= {{layer50_out_dout[95:80]}};
+        trunc_ln58_112_reg_2051 <= {{layer50_out_dout[111:96]}};
+        trunc_ln58_113_reg_2056 <= {{layer50_out_dout[127:112]}};
+        trunc_ln58_114_reg_2061 <= {{layer50_out_dout[143:128]}};
+        trunc_ln58_115_reg_2066 <= {{layer50_out_dout[159:144]}};
+        trunc_ln58_116_reg_2071 <= {{layer50_out_dout[175:160]}};
+        trunc_ln58_117_reg_2076 <= {{layer50_out_dout[191:176]}};
+        trunc_ln58_118_reg_2081 <= {{layer50_out_dout[207:192]}};
+        trunc_ln58_119_reg_2086 <= {{layer50_out_dout[223:208]}};
+        trunc_ln58_120_reg_2091 <= {{layer50_out_dout[239:224]}};
+        trunc_ln58_121_reg_2096 <= {{layer50_out_dout[255:240]}};
+        trunc_ln58_122_reg_2101 <= {{layer50_out_dout[271:256]}};
+        trunc_ln58_123_reg_2106 <= {{layer50_out_dout[287:272]}};
+        trunc_ln58_124_reg_2111 <= {{layer50_out_dout[303:288]}};
+        trunc_ln58_125_reg_2116 <= {{layer50_out_dout[319:304]}};
+        trunc_ln58_126_reg_2121 <= {{layer50_out_dout[335:320]}};
+        trunc_ln58_127_reg_2126 <= {{layer50_out_dout[351:336]}};
+        trunc_ln58_128_reg_2131 <= {{layer50_out_dout[367:352]}};
+        trunc_ln58_129_reg_2136 <= {{layer50_out_dout[383:368]}};
+        trunc_ln58_130_reg_2141 <= {{layer50_out_dout[399:384]}};
+        trunc_ln58_131_reg_2146 <= {{layer50_out_dout[415:400]}};
+        trunc_ln58_132_reg_2151 <= {{layer50_out_dout[431:416]}};
+        trunc_ln58_133_reg_2156 <= {{layer50_out_dout[447:432]}};
+        trunc_ln58_134_reg_2161 <= {{layer50_out_dout[463:448]}};
+        trunc_ln58_135_reg_2166 <= {{layer50_out_dout[479:464]}};
+        trunc_ln58_136_reg_2171 <= {{layer50_out_dout[495:480]}};
+        trunc_ln58_137_reg_2176 <= {{layer50_out_dout[511:496]}};
+        trunc_ln58_reg_2021 <= trunc_ln58_fu_1660_p1;
+        trunc_ln58_s_reg_2026 <= {{layer50_out_dout[31:16]}};
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_block_state1)) begin
+        ap_ST_fsm_state1_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state1_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_block_state2)) begin
+        ap_ST_fsm_state2_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state2_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s_fu_886_ap_done == 1'b0)) begin
+        ap_ST_fsm_state3_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state3_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_1648_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+        ap_done = 1'b1;
+    end else begin
+        ap_done = ap_done_reg;
+    end
+end
+
+always @ (*) begin
+    if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
+        ap_idle = 1'b1;
+    end else begin
+        ap_idle = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_1648_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+        internal_ap_ready = 1'b1;
+    end else begin
+        internal_ap_ready = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state3)) begin
+        layer17_out_write = grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s_fu_886_layer17_out_write;
+    end else begin
+        layer17_out_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln52_fu_1648_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        layer50_out_blk_n = layer50_out_empty_n;
+    end else begin
+        layer50_out_blk_n = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_1648_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        layer50_out_read_local = 1'b1;
+    end else begin
+        layer50_out_read_local = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((start_once_reg == 1'b0) & (start_full_n == 1'b0))) begin
+        real_start = 1'b0;
+    end else begin
+        real_start = ap_start;
+    end
+end
+
+always @ (*) begin
+    if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin
+        start_write = 1'b1;
+    end else begin
+        start_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    case (ap_CS_fsm)
+        ap_ST_fsm_state1 : begin
+            if (((1'b0 == ap_block_state1) & (1'b1 == ap_CS_fsm_state1))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end
+        end
+        ap_ST_fsm_state2 : begin
+            if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_1648_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end else if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_1648_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end
+        end
+        ap_ST_fsm_state3 : begin
+            if (((1'b1 == ap_CS_fsm_state3) & (grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s_fu_886_ap_done == 1'b1))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end
+        end
+        default : begin
+            ap_NS_fsm = 'bx;
+        end
+    endcase
+end
+
+assign add_ln52_fu_1654_p2 = (indvar_flatten_fu_876 + 7'd1);
+
+assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
+
+assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
+
+assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2];
+
+always @ (*) begin
+    ap_block_state1 = ((real_start == 1'b0) | (ap_done_reg == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_state2 = ((icmp_ln52_fu_1648_p2 == 1'd0) & (layer50_out_empty_n == 1'b0));
+end
+
+always @ (*) begin
+    ap_block_state2_ignore_call35 = ((icmp_ln52_fu_1648_p2 == 1'd0) & (layer50_out_empty_n == 1'b0));
+end
+
+assign ap_ready = internal_ap_ready;
+
+assign grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s_fu_886_ap_start = grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s_fu_886_ap_start_reg;
+
+assign icmp_ln52_fu_1648_p2 = ((indvar_flatten_fu_876 == 7'd100) ? 1'b1 : 1'b0);
+
+assign layer17_out_din = grp_compute_output_buffer_2d_array_array_ap_fixed_42_22_5_3_0_64u_config17_s_fu_886_layer17_out_din;
+
+assign layer50_out_read = layer50_out_read_local;
+
+assign start_out = real_start;
+
+assign trunc_ln58_fu_1660_p1 = layer50_out_dout[15:0];
+
+endmodule //myproject_conv_2d_cl_array_array_ap_fixed_42_22_5_3_0_64u_config17_s

myproject_prj/solution1/syn/verilog/myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_oudEe.dat

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