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myproject_prj/solution1/impl/verilog/myproject_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_s.v

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+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+
+`timescale 1 ns / 1 ps 
+
+module myproject_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_s (
+        ap_clk,
+        ap_rst,
+        ap_start,
+        start_full_n,
+        ap_done,
+        ap_continue,
+        ap_idle,
+        ap_ready,
+        start_out,
+        start_write,
+        layer58_out_dout,
+        layer58_out_num_data_valid,
+        layer58_out_fifo_cap,
+        layer58_out_empty_n,
+        layer58_out_read,
+        layer35_out_din,
+        layer35_out_num_data_valid,
+        layer35_out_fifo_cap,
+        layer35_out_full_n,
+        layer35_out_write
+);
+
+parameter    ap_ST_fsm_state1 = 3'd1;
+parameter    ap_ST_fsm_state2 = 3'd2;
+parameter    ap_ST_fsm_state3 = 3'd4;
+
+input   ap_clk;
+input   ap_rst;
+input   ap_start;
+input   start_full_n;
+output   ap_done;
+input   ap_continue;
+output   ap_idle;
+output   ap_ready;
+output   start_out;
+output   start_write;
+input  [383:0] layer58_out_dout;
+input  [13:0] layer58_out_num_data_valid;
+input  [13:0] layer58_out_fifo_cap;
+input   layer58_out_empty_n;
+output   layer58_out_read;
+output  [327:0] layer35_out_din;
+input  [12:0] layer35_out_num_data_valid;
+input  [12:0] layer35_out_fifo_cap;
+input   layer35_out_full_n;
+output   layer35_out_write;
+
+reg ap_done;
+reg ap_idle;
+reg start_write;
+reg layer35_out_write;
+
+reg    real_start;
+reg    start_once_reg;
+reg    ap_done_reg;
+(* fsm_encoding = "none" *) reg   [2:0] ap_CS_fsm;
+wire    ap_CS_fsm_state1;
+reg    internal_ap_ready;
+reg    layer58_out_blk_n;
+wire    ap_CS_fsm_state2;
+wire   [0:0] icmp_ln52_fu_1252_p2;
+wire   [15:0] trunc_ln58_fu_1264_p1;
+reg   [15:0] trunc_ln58_reg_1537;
+reg    ap_block_state2;
+reg   [15:0] trunc_ln58_s_reg_1542;
+reg   [15:0] trunc_ln58_10_reg_1547;
+reg   [15:0] trunc_ln58_11_reg_1552;
+reg   [15:0] trunc_ln58_12_reg_1557;
+reg   [15:0] trunc_ln58_13_reg_1562;
+reg   [15:0] trunc_ln58_14_reg_1567;
+reg   [15:0] trunc_ln58_15_reg_1572;
+reg   [15:0] trunc_ln58_16_reg_1577;
+reg   [15:0] trunc_ln58_17_reg_1582;
+reg   [15:0] trunc_ln58_18_reg_1587;
+reg   [15:0] trunc_ln58_19_reg_1592;
+reg   [15:0] trunc_ln58_20_reg_1597;
+reg   [15:0] trunc_ln58_21_reg_1602;
+reg   [15:0] trunc_ln58_22_reg_1607;
+reg   [15:0] trunc_ln58_23_reg_1612;
+reg   [15:0] trunc_ln58_24_reg_1617;
+reg   [15:0] trunc_ln58_25_reg_1622;
+reg   [15:0] trunc_ln58_26_reg_1627;
+reg   [15:0] trunc_ln58_27_reg_1632;
+reg   [15:0] trunc_ln58_28_reg_1637;
+reg   [15:0] trunc_ln58_29_reg_1642;
+reg   [15:0] trunc_ln58_30_reg_1647;
+reg   [15:0] trunc_ln58_31_reg_1652;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_ap_start;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_ap_done;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_ap_idle;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_ap_ready;
+wire   [327:0] grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_layer35_out_din;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_layer35_out_write;
+reg    grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_ap_start_reg;
+reg    ap_block_state2_ignore_call27;
+wire    ap_CS_fsm_state3;
+reg   [12:0] indvar_flatten_fu_666;
+wire   [12:0] add_ln52_fu_1258_p2;
+reg    ap_block_state1;
+reg    layer58_out_read_local;
+reg   [2:0] ap_NS_fsm;
+reg    ap_ST_fsm_state1_blk;
+reg    ap_ST_fsm_state2_blk;
+reg    ap_ST_fsm_state3_blk;
+wire    ap_ce_reg;
+
+// power-on initialization
+initial begin
+#0 start_once_reg = 1'b0;
+#0 ap_done_reg = 1'b0;
+#0 ap_CS_fsm = 3'd1;
+#0 grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_ap_start_reg = 1'b0;
+#0 indvar_flatten_fu_666 = 13'd0;
+end
+
+myproject_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676(
+    .ap_clk(ap_clk),
+    .ap_rst(ap_rst),
+    .ap_start(grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_ap_start),
+    .ap_done(grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_ap_done),
+    .ap_idle(grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_ap_idle),
+    .ap_ready(grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_ap_ready),
+    .p_read(trunc_ln58_reg_1537),
+    .p_read1(trunc_ln58_s_reg_1542),
+    .p_read2(trunc_ln58_10_reg_1547),
+    .p_read3(trunc_ln58_11_reg_1552),
+    .p_read4(trunc_ln58_12_reg_1557),
+    .p_read5(trunc_ln58_13_reg_1562),
+    .p_read6(trunc_ln58_14_reg_1567),
+    .p_read7(trunc_ln58_15_reg_1572),
+    .p_read8(trunc_ln58_16_reg_1577),
+    .p_read9(trunc_ln58_17_reg_1582),
+    .p_read10(trunc_ln58_18_reg_1587),
+    .p_read11(trunc_ln58_19_reg_1592),
+    .p_read12(trunc_ln58_20_reg_1597),
+    .p_read13(trunc_ln58_21_reg_1602),
+    .p_read14(trunc_ln58_22_reg_1607),
+    .p_read15(trunc_ln58_23_reg_1612),
+    .p_read16(trunc_ln58_24_reg_1617),
+    .p_read17(trunc_ln58_25_reg_1622),
+    .p_read18(trunc_ln58_26_reg_1627),
+    .p_read19(trunc_ln58_27_reg_1632),
+    .p_read20(trunc_ln58_28_reg_1637),
+    .p_read21(trunc_ln58_29_reg_1642),
+    .p_read22(trunc_ln58_30_reg_1647),
+    .p_read23(trunc_ln58_31_reg_1652),
+    .layer35_out_din(grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_layer35_out_din),
+    .layer35_out_num_data_valid(13'd0),
+    .layer35_out_fifo_cap(13'd0),
+    .layer35_out_full_n(layer35_out_full_n),
+    .layer35_out_write(grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_layer35_out_write)
+);
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_CS_fsm <= ap_ST_fsm_state1;
+    end else begin
+        ap_CS_fsm <= ap_NS_fsm;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_done_reg <= 1'b0;
+    end else begin
+        if ((ap_continue == 1'b1)) begin
+            ap_done_reg <= 1'b0;
+        end else if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_1252_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+            ap_done_reg <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_ap_start_reg <= 1'b0;
+    end else begin
+        if (((1'b0 == ap_block_state2_ignore_call27) & (icmp_ln52_fu_1252_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+            grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_ap_start_reg <= 1'b1;
+        end else if ((grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_ap_ready == 1'b1)) begin
+            grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_ap_start_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        start_once_reg <= 1'b0;
+    end else begin
+        if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin
+            start_once_reg <= 1'b1;
+        end else if ((internal_ap_ready == 1'b1)) begin
+            start_once_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_state1) & (1'b1 == ap_CS_fsm_state1))) begin
+        indvar_flatten_fu_666 <= 13'd0;
+    end else if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_1252_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        indvar_flatten_fu_666 <= add_ln52_fu_1258_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_state2) & (1'b1 == ap_CS_fsm_state2))) begin
+        trunc_ln58_10_reg_1547 <= {{layer58_out_dout[47:32]}};
+        trunc_ln58_11_reg_1552 <= {{layer58_out_dout[63:48]}};
+        trunc_ln58_12_reg_1557 <= {{layer58_out_dout[79:64]}};
+        trunc_ln58_13_reg_1562 <= {{layer58_out_dout[95:80]}};
+        trunc_ln58_14_reg_1567 <= {{layer58_out_dout[111:96]}};
+        trunc_ln58_15_reg_1572 <= {{layer58_out_dout[127:112]}};
+        trunc_ln58_16_reg_1577 <= {{layer58_out_dout[143:128]}};
+        trunc_ln58_17_reg_1582 <= {{layer58_out_dout[159:144]}};
+        trunc_ln58_18_reg_1587 <= {{layer58_out_dout[175:160]}};
+        trunc_ln58_19_reg_1592 <= {{layer58_out_dout[191:176]}};
+        trunc_ln58_20_reg_1597 <= {{layer58_out_dout[207:192]}};
+        trunc_ln58_21_reg_1602 <= {{layer58_out_dout[223:208]}};
+        trunc_ln58_22_reg_1607 <= {{layer58_out_dout[239:224]}};
+        trunc_ln58_23_reg_1612 <= {{layer58_out_dout[255:240]}};
+        trunc_ln58_24_reg_1617 <= {{layer58_out_dout[271:256]}};
+        trunc_ln58_25_reg_1622 <= {{layer58_out_dout[287:272]}};
+        trunc_ln58_26_reg_1627 <= {{layer58_out_dout[303:288]}};
+        trunc_ln58_27_reg_1632 <= {{layer58_out_dout[319:304]}};
+        trunc_ln58_28_reg_1637 <= {{layer58_out_dout[335:320]}};
+        trunc_ln58_29_reg_1642 <= {{layer58_out_dout[351:336]}};
+        trunc_ln58_30_reg_1647 <= {{layer58_out_dout[367:352]}};
+        trunc_ln58_31_reg_1652 <= {{layer58_out_dout[383:368]}};
+        trunc_ln58_reg_1537 <= trunc_ln58_fu_1264_p1;
+        trunc_ln58_s_reg_1542 <= {{layer58_out_dout[31:16]}};
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_block_state1)) begin
+        ap_ST_fsm_state1_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state1_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_block_state2)) begin
+        ap_ST_fsm_state2_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state2_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_ap_done == 1'b0)) begin
+        ap_ST_fsm_state3_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state3_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_1252_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+        ap_done = 1'b1;
+    end else begin
+        ap_done = ap_done_reg;
+    end
+end
+
+always @ (*) begin
+    if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
+        ap_idle = 1'b1;
+    end else begin
+        ap_idle = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_1252_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+        internal_ap_ready = 1'b1;
+    end else begin
+        internal_ap_ready = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state3)) begin
+        layer35_out_write = grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_layer35_out_write;
+    end else begin
+        layer35_out_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln52_fu_1252_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        layer58_out_blk_n = layer58_out_empty_n;
+    end else begin
+        layer58_out_blk_n = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_1252_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        layer58_out_read_local = 1'b1;
+    end else begin
+        layer58_out_read_local = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((start_once_reg == 1'b0) & (start_full_n == 1'b0))) begin
+        real_start = 1'b0;
+    end else begin
+        real_start = ap_start;
+    end
+end
+
+always @ (*) begin
+    if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin
+        start_write = 1'b1;
+    end else begin
+        start_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    case (ap_CS_fsm)
+        ap_ST_fsm_state1 : begin
+            if (((1'b0 == ap_block_state1) & (1'b1 == ap_CS_fsm_state1))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end
+        end
+        ap_ST_fsm_state2 : begin
+            if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_1252_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end else if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_1252_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end
+        end
+        ap_ST_fsm_state3 : begin
+            if (((1'b1 == ap_CS_fsm_state3) & (grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_ap_done == 1'b1))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end
+        end
+        default : begin
+            ap_NS_fsm = 'bx;
+        end
+    endcase
+end
+
+assign add_ln52_fu_1258_p2 = (indvar_flatten_fu_666 + 13'd1);
+
+assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
+
+assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
+
+assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2];
+
+always @ (*) begin
+    ap_block_state1 = ((real_start == 1'b0) | (ap_done_reg == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_state2 = ((icmp_ln52_fu_1252_p2 == 1'd0) & (layer58_out_empty_n == 1'b0));
+end
+
+always @ (*) begin
+    ap_block_state2_ignore_call27 = ((icmp_ln52_fu_1252_p2 == 1'd0) & (layer58_out_empty_n == 1'b0));
+end
+
+assign ap_ready = internal_ap_ready;
+
+assign grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_ap_start = grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_ap_start_reg;
+
+assign icmp_ln52_fu_1252_p2 = ((indvar_flatten_fu_666 == 13'd4356) ? 1'b1 : 1'b0);
+
+assign layer35_out_din = grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_8u_config35_s_fu_676_layer35_out_din;
+
+assign layer58_out_read = layer58_out_read_local;
+
+assign start_out = real_start;
+
+assign trunc_ln58_fu_1264_p1 = layer58_out_dout[15:0];
+
+endmodule //myproject_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config35_s

myproject_prj/solution1/impl/verilog/myproject_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_s.v

@@ -0,0 +1,373 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+
+`timescale 1 ns / 1 ps 
+
+module myproject_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_s (
+        ap_clk,
+        ap_rst,
+        ap_start,
+        start_full_n,
+        ap_done,
+        ap_continue,
+        ap_idle,
+        ap_ready,
+        start_out,
+        start_write,
+        layer50_out_dout,
+        layer50_out_num_data_valid,
+        layer50_out_fifo_cap,
+        layer50_out_empty_n,
+        layer50_out_read,
+        layer12_out_din,
+        layer12_out_num_data_valid,
+        layer12_out_fifo_cap,
+        layer12_out_full_n,
+        layer12_out_write
+);
+
+parameter    ap_ST_fsm_state1 = 3'd1;
+parameter    ap_ST_fsm_state2 = 3'd2;
+parameter    ap_ST_fsm_state3 = 3'd4;
+
+input   ap_clk;
+input   ap_rst;
+input   ap_start;
+input   start_full_n;
+output   ap_done;
+input   ap_continue;
+output   ap_idle;
+output   ap_ready;
+output   start_out;
+output   start_write;
+input  [255:0] layer50_out_dout;
+input  [9:0] layer50_out_num_data_valid;
+input  [9:0] layer50_out_fifo_cap;
+input   layer50_out_empty_n;
+output   layer50_out_read;
+output  [1311:0] layer12_out_din;
+input  [8:0] layer12_out_num_data_valid;
+input  [8:0] layer12_out_fifo_cap;
+input   layer12_out_full_n;
+output   layer12_out_write;
+
+reg ap_done;
+reg ap_idle;
+reg start_write;
+reg layer12_out_write;
+
+reg    real_start;
+reg    start_once_reg;
+reg    ap_done_reg;
+(* fsm_encoding = "none" *) reg   [2:0] ap_CS_fsm;
+wire    ap_CS_fsm_state1;
+reg    internal_ap_ready;
+reg    layer50_out_blk_n;
+wire    ap_CS_fsm_state2;
+wire   [0:0] icmp_ln52_fu_860_p2;
+wire   [15:0] trunc_ln58_fu_872_p1;
+reg   [15:0] trunc_ln58_reg_1057;
+reg    ap_block_state2;
+reg   [15:0] trunc_ln58_s_reg_1062;
+reg   [15:0] trunc_ln58_226_reg_1067;
+reg   [15:0] trunc_ln58_227_reg_1072;
+reg   [15:0] trunc_ln58_228_reg_1077;
+reg   [15:0] trunc_ln58_229_reg_1082;
+reg   [15:0] trunc_ln58_230_reg_1087;
+reg   [15:0] trunc_ln58_231_reg_1092;
+reg   [15:0] trunc_ln58_232_reg_1097;
+reg   [15:0] trunc_ln58_233_reg_1102;
+reg   [15:0] trunc_ln58_234_reg_1107;
+reg   [15:0] trunc_ln58_235_reg_1112;
+reg   [15:0] trunc_ln58_236_reg_1117;
+reg   [15:0] trunc_ln58_237_reg_1122;
+reg   [15:0] trunc_ln58_238_reg_1127;
+reg   [15:0] trunc_ln58_239_reg_1132;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_468_ap_start;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_468_ap_done;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_468_ap_idle;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_468_ap_ready;
+wire   [1311:0] grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_468_layer12_out_din;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_468_layer12_out_write;
+reg    grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_468_ap_start_reg;
+reg    ap_block_state2_ignore_call19;
+wire    ap_CS_fsm_state3;
+reg   [8:0] indvar_flatten_fu_458;
+wire   [8:0] add_ln52_fu_866_p2;
+reg    ap_block_state1;
+reg    layer50_out_read_local;
+reg   [2:0] ap_NS_fsm;
+reg    ap_ST_fsm_state1_blk;
+reg    ap_ST_fsm_state2_blk;
+reg    ap_ST_fsm_state3_blk;
+wire    ap_ce_reg;
+
+// power-on initialization
+initial begin
+#0 start_once_reg = 1'b0;
+#0 ap_done_reg = 1'b0;
+#0 ap_CS_fsm = 3'd1;
+#0 grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_468_ap_start_reg = 1'b0;
+#0 indvar_flatten_fu_458 = 9'd0;
+end
+
+myproject_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_468(
+    .ap_clk(ap_clk),
+    .ap_rst(ap_rst),
+    .ap_start(grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_468_ap_start),
+    .ap_done(grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_468_ap_done),
+    .ap_idle(grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_468_ap_idle),
+    .ap_ready(grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_468_ap_ready),
+    .p_read(trunc_ln58_reg_1057),
+    .p_read1(trunc_ln58_s_reg_1062),
+    .p_read2(trunc_ln58_226_reg_1067),
+    .p_read3(trunc_ln58_227_reg_1072),
+    .p_read4(trunc_ln58_228_reg_1077),
+    .p_read5(trunc_ln58_229_reg_1082),
+    .p_read6(trunc_ln58_230_reg_1087),
+    .p_read7(trunc_ln58_231_reg_1092),
+    .p_read8(trunc_ln58_232_reg_1097),
+    .p_read9(trunc_ln58_233_reg_1102),
+    .p_read10(trunc_ln58_234_reg_1107),
+    .p_read11(trunc_ln58_235_reg_1112),
+    .p_read12(trunc_ln58_236_reg_1117),
+    .p_read13(trunc_ln58_237_reg_1122),
+    .p_read14(trunc_ln58_238_reg_1127),
+    .p_read15(trunc_ln58_239_reg_1132),
+    .layer12_out_din(grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_468_layer12_out_din),
+    .layer12_out_num_data_valid(9'd0),
+    .layer12_out_fifo_cap(9'd0),
+    .layer12_out_full_n(layer12_out_full_n),
+    .layer12_out_write(grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_468_layer12_out_write)
+);
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_CS_fsm <= ap_ST_fsm_state1;
+    end else begin
+        ap_CS_fsm <= ap_NS_fsm;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_done_reg <= 1'b0;
+    end else begin
+        if ((ap_continue == 1'b1)) begin
+            ap_done_reg <= 1'b0;
+        end else if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_860_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+            ap_done_reg <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_468_ap_start_reg <= 1'b0;
+    end else begin
+        if (((1'b0 == ap_block_state2_ignore_call19) & (icmp_ln52_fu_860_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+            grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_468_ap_start_reg <= 1'b1;
+        end else if ((grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_468_ap_ready == 1'b1)) begin
+            grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_468_ap_start_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        start_once_reg <= 1'b0;
+    end else begin
+        if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin
+            start_once_reg <= 1'b1;
+        end else if ((internal_ap_ready == 1'b1)) begin
+            start_once_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_state1) & (1'b1 == ap_CS_fsm_state1))) begin
+        indvar_flatten_fu_458 <= 9'd0;
+    end else if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_860_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        indvar_flatten_fu_458 <= add_ln52_fu_866_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_state2) & (1'b1 == ap_CS_fsm_state2))) begin
+        trunc_ln58_226_reg_1067 <= {{layer50_out_dout[47:32]}};
+        trunc_ln58_227_reg_1072 <= {{layer50_out_dout[63:48]}};
+        trunc_ln58_228_reg_1077 <= {{layer50_out_dout[79:64]}};
+        trunc_ln58_229_reg_1082 <= {{layer50_out_dout[95:80]}};
+        trunc_ln58_230_reg_1087 <= {{layer50_out_dout[111:96]}};
+        trunc_ln58_231_reg_1092 <= {{layer50_out_dout[127:112]}};
+        trunc_ln58_232_reg_1097 <= {{layer50_out_dout[143:128]}};
+        trunc_ln58_233_reg_1102 <= {{layer50_out_dout[159:144]}};
+        trunc_ln58_234_reg_1107 <= {{layer50_out_dout[175:160]}};
+        trunc_ln58_235_reg_1112 <= {{layer50_out_dout[191:176]}};
+        trunc_ln58_236_reg_1117 <= {{layer50_out_dout[207:192]}};
+        trunc_ln58_237_reg_1122 <= {{layer50_out_dout[223:208]}};
+        trunc_ln58_238_reg_1127 <= {{layer50_out_dout[239:224]}};
+        trunc_ln58_239_reg_1132 <= {{layer50_out_dout[255:240]}};
+        trunc_ln58_reg_1057 <= trunc_ln58_fu_872_p1;
+        trunc_ln58_s_reg_1062 <= {{layer50_out_dout[31:16]}};
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_block_state1)) begin
+        ap_ST_fsm_state1_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state1_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_block_state2)) begin
+        ap_ST_fsm_state2_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state2_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_468_ap_done == 1'b0)) begin
+        ap_ST_fsm_state3_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state3_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_860_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+        ap_done = 1'b1;
+    end else begin
+        ap_done = ap_done_reg;
+    end
+end
+
+always @ (*) begin
+    if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
+        ap_idle = 1'b1;
+    end else begin
+        ap_idle = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_860_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+        internal_ap_ready = 1'b1;
+    end else begin
+        internal_ap_ready = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state3)) begin
+        layer12_out_write = grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_468_layer12_out_write;
+    end else begin
+        layer12_out_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln52_fu_860_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        layer50_out_blk_n = layer50_out_empty_n;
+    end else begin
+        layer50_out_blk_n = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_860_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        layer50_out_read_local = 1'b1;
+    end else begin
+        layer50_out_read_local = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((start_once_reg == 1'b0) & (start_full_n == 1'b0))) begin
+        real_start = 1'b0;
+    end else begin
+        real_start = ap_start;
+    end
+end
+
+always @ (*) begin
+    if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin
+        start_write = 1'b1;
+    end else begin
+        start_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    case (ap_CS_fsm)
+        ap_ST_fsm_state1 : begin
+            if (((1'b0 == ap_block_state1) & (1'b1 == ap_CS_fsm_state1))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end
+        end
+        ap_ST_fsm_state2 : begin
+            if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_860_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end else if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_860_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end
+        end
+        ap_ST_fsm_state3 : begin
+            if (((1'b1 == ap_CS_fsm_state3) & (grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_468_ap_done == 1'b1))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end
+        end
+        default : begin
+            ap_NS_fsm = 'bx;
+        end
+    endcase
+end
+
+assign add_ln52_fu_866_p2 = (indvar_flatten_fu_458 + 9'd1);
+
+assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
+
+assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
+
+assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2];
+
+always @ (*) begin
+    ap_block_state1 = ((real_start == 1'b0) | (ap_done_reg == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_state2 = ((icmp_ln52_fu_860_p2 == 1'd0) & (layer50_out_empty_n == 1'b0));
+end
+
+always @ (*) begin
+    ap_block_state2_ignore_call19 = ((icmp_ln52_fu_860_p2 == 1'd0) & (layer50_out_empty_n == 1'b0));
+end
+
+assign ap_ready = internal_ap_ready;
+
+assign grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_468_ap_start = grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_468_ap_start_reg;
+
+assign icmp_ln52_fu_860_p2 = ((indvar_flatten_fu_458 == 9'd324) ? 1'b1 : 1'b0);
+
+assign layer12_out_din = grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_32u_config12_s_fu_468_layer12_out_din;
+
+assign layer50_out_read = layer50_out_read_local;
+
+assign start_out = real_start;
+
+assign trunc_ln58_fu_872_p1 = layer50_out_dout[15:0];
+
+endmodule //myproject_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_s

myproject_prj/solution1/impl/verilog/myproject_conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_s.v

@@ -0,0 +1,517 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+
+`timescale 1 ns / 1 ps 
+
+module myproject_conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_s (
+        ap_clk,
+        ap_rst,
+        ap_start,
+        start_full_n,
+        ap_done,
+        ap_continue,
+        ap_idle,
+        ap_ready,
+        start_out,
+        start_write,
+        layer53_out_dout,
+        layer53_out_num_data_valid,
+        layer53_out_fifo_cap,
+        layer53_out_empty_n,
+        layer53_out_read,
+        layer19_out_din,
+        layer19_out_num_data_valid,
+        layer19_out_fifo_cap,
+        layer19_out_full_n,
+        layer19_out_write
+);
+
+parameter    ap_ST_fsm_state1 = 3'd1;
+parameter    ap_ST_fsm_state2 = 3'd2;
+parameter    ap_ST_fsm_state3 = 3'd4;
+
+input   ap_clk;
+input   ap_rst;
+input   ap_start;
+input   start_full_n;
+output   ap_done;
+input   ap_continue;
+output   ap_idle;
+output   ap_ready;
+output   start_out;
+output   start_write;
+input  [1023:0] layer53_out_dout;
+input  [7:0] layer53_out_num_data_valid;
+input  [7:0] layer53_out_fifo_cap;
+input   layer53_out_empty_n;
+output   layer53_out_read;
+output  [2751:0] layer19_out_din;
+input  [6:0] layer19_out_num_data_valid;
+input  [6:0] layer19_out_fifo_cap;
+input   layer19_out_full_n;
+output   layer19_out_write;
+
+reg ap_done;
+reg ap_idle;
+reg start_write;
+reg layer19_out_write;
+
+reg    real_start;
+reg    start_once_reg;
+reg    ap_done_reg;
+(* fsm_encoding = "none" *) reg   [2:0] ap_CS_fsm;
+wire    ap_CS_fsm_state1;
+reg    internal_ap_ready;
+reg    layer53_out_blk_n;
+wire    ap_CS_fsm_state2;
+wire   [0:0] icmp_ln52_fu_3212_p2;
+wire   [15:0] trunc_ln58_fu_3224_p1;
+reg   [15:0] trunc_ln58_reg_3937;
+reg    ap_block_state2;
+reg   [15:0] trunc_ln58_s_reg_3942;
+reg   [15:0] trunc_ln58_46_reg_3947;
+reg   [15:0] trunc_ln58_47_reg_3952;
+reg   [15:0] trunc_ln58_48_reg_3957;
+reg   [15:0] trunc_ln58_49_reg_3962;
+reg   [15:0] trunc_ln58_50_reg_3967;
+reg   [15:0] trunc_ln58_51_reg_3972;
+reg   [15:0] trunc_ln58_52_reg_3977;
+reg   [15:0] trunc_ln58_53_reg_3982;
+reg   [15:0] trunc_ln58_54_reg_3987;
+reg   [15:0] trunc_ln58_55_reg_3992;
+reg   [15:0] trunc_ln58_56_reg_3997;
+reg   [15:0] trunc_ln58_57_reg_4002;
+reg   [15:0] trunc_ln58_58_reg_4007;
+reg   [15:0] trunc_ln58_59_reg_4012;
+reg   [15:0] trunc_ln58_60_reg_4017;
+reg   [15:0] trunc_ln58_61_reg_4022;
+reg   [15:0] trunc_ln58_62_reg_4027;
+reg   [15:0] trunc_ln58_63_reg_4032;
+reg   [15:0] trunc_ln58_64_reg_4037;
+reg   [15:0] trunc_ln58_65_reg_4042;
+reg   [15:0] trunc_ln58_66_reg_4047;
+reg   [15:0] trunc_ln58_67_reg_4052;
+reg   [15:0] trunc_ln58_68_reg_4057;
+reg   [15:0] trunc_ln58_69_reg_4062;
+reg   [15:0] trunc_ln58_70_reg_4067;
+reg   [15:0] trunc_ln58_71_reg_4072;
+reg   [15:0] trunc_ln58_72_reg_4077;
+reg   [15:0] trunc_ln58_73_reg_4082;
+reg   [15:0] trunc_ln58_74_reg_4087;
+reg   [15:0] trunc_ln58_75_reg_4092;
+reg   [15:0] trunc_ln58_76_reg_4097;
+reg   [15:0] trunc_ln58_77_reg_4102;
+reg   [15:0] trunc_ln58_78_reg_4107;
+reg   [15:0] trunc_ln58_79_reg_4112;
+reg   [15:0] trunc_ln58_80_reg_4117;
+reg   [15:0] trunc_ln58_81_reg_4122;
+reg   [15:0] trunc_ln58_82_reg_4127;
+reg   [15:0] trunc_ln58_83_reg_4132;
+reg   [15:0] trunc_ln58_84_reg_4137;
+reg   [15:0] trunc_ln58_85_reg_4142;
+reg   [15:0] trunc_ln58_86_reg_4147;
+reg   [15:0] trunc_ln58_87_reg_4152;
+reg   [15:0] trunc_ln58_88_reg_4157;
+reg   [15:0] trunc_ln58_89_reg_4162;
+reg   [15:0] trunc_ln58_90_reg_4167;
+reg   [15:0] trunc_ln58_91_reg_4172;
+reg   [15:0] trunc_ln58_92_reg_4177;
+reg   [15:0] trunc_ln58_93_reg_4182;
+reg   [15:0] trunc_ln58_94_reg_4187;
+reg   [15:0] trunc_ln58_95_reg_4192;
+reg   [15:0] trunc_ln58_96_reg_4197;
+reg   [15:0] trunc_ln58_97_reg_4202;
+reg   [15:0] trunc_ln58_98_reg_4207;
+reg   [15:0] trunc_ln58_99_reg_4212;
+reg   [15:0] trunc_ln58_100_reg_4217;
+reg   [15:0] trunc_ln58_101_reg_4222;
+reg   [15:0] trunc_ln58_102_reg_4227;
+reg   [15:0] trunc_ln58_103_reg_4232;
+reg   [15:0] trunc_ln58_104_reg_4237;
+reg   [15:0] trunc_ln58_105_reg_4242;
+reg   [15:0] trunc_ln58_106_reg_4247;
+reg   [15:0] trunc_ln58_107_reg_4252;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1716_ap_start;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1716_ap_done;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1716_ap_idle;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1716_ap_ready;
+wire   [2751:0] grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1716_layer19_out_din;
+wire    grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1716_layer19_out_write;
+reg    grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1716_ap_start_reg;
+reg    ap_block_state2_ignore_call67;
+wire    ap_CS_fsm_state3;
+reg   [6:0] indvar_flatten_fu_1706;
+wire   [6:0] add_ln52_fu_3218_p2;
+reg    ap_block_state1;
+reg    layer53_out_read_local;
+reg   [2:0] ap_NS_fsm;
+reg    ap_ST_fsm_state1_blk;
+reg    ap_ST_fsm_state2_blk;
+reg    ap_ST_fsm_state3_blk;
+wire    ap_ce_reg;
+
+// power-on initialization
+initial begin
+#0 start_once_reg = 1'b0;
+#0 ap_done_reg = 1'b0;
+#0 ap_CS_fsm = 3'd1;
+#0 grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1716_ap_start_reg = 1'b0;
+#0 indvar_flatten_fu_1706 = 7'd0;
+end
+
+myproject_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1716(
+    .ap_clk(ap_clk),
+    .ap_rst(ap_rst),
+    .ap_start(grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1716_ap_start),
+    .ap_done(grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1716_ap_done),
+    .ap_idle(grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1716_ap_idle),
+    .ap_ready(grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1716_ap_ready),
+    .p_read(trunc_ln58_reg_3937),
+    .p_read1(trunc_ln58_s_reg_3942),
+    .p_read2(trunc_ln58_46_reg_3947),
+    .p_read3(trunc_ln58_47_reg_3952),
+    .p_read4(trunc_ln58_48_reg_3957),
+    .p_read5(trunc_ln58_49_reg_3962),
+    .p_read6(trunc_ln58_50_reg_3967),
+    .p_read7(trunc_ln58_51_reg_3972),
+    .p_read8(trunc_ln58_52_reg_3977),
+    .p_read9(trunc_ln58_53_reg_3982),
+    .p_read10(trunc_ln58_54_reg_3987),
+    .p_read11(trunc_ln58_55_reg_3992),
+    .p_read12(trunc_ln58_56_reg_3997),
+    .p_read13(trunc_ln58_57_reg_4002),
+    .p_read14(trunc_ln58_58_reg_4007),
+    .p_read15(trunc_ln58_59_reg_4012),
+    .p_read16(trunc_ln58_60_reg_4017),
+    .p_read17(trunc_ln58_61_reg_4022),
+    .p_read18(trunc_ln58_62_reg_4027),
+    .p_read19(trunc_ln58_63_reg_4032),
+    .p_read20(trunc_ln58_64_reg_4037),
+    .p_read21(trunc_ln58_65_reg_4042),
+    .p_read22(trunc_ln58_66_reg_4047),
+    .p_read23(trunc_ln58_67_reg_4052),
+    .p_read24(trunc_ln58_68_reg_4057),
+    .p_read25(trunc_ln58_69_reg_4062),
+    .p_read26(trunc_ln58_70_reg_4067),
+    .p_read27(trunc_ln58_71_reg_4072),
+    .p_read28(trunc_ln58_72_reg_4077),
+    .p_read29(trunc_ln58_73_reg_4082),
+    .p_read30(trunc_ln58_74_reg_4087),
+    .p_read31(trunc_ln58_75_reg_4092),
+    .p_read32(trunc_ln58_76_reg_4097),
+    .p_read33(trunc_ln58_77_reg_4102),
+    .p_read34(trunc_ln58_78_reg_4107),
+    .p_read35(trunc_ln58_79_reg_4112),
+    .p_read36(trunc_ln58_80_reg_4117),
+    .p_read37(trunc_ln58_81_reg_4122),
+    .p_read38(trunc_ln58_82_reg_4127),
+    .p_read39(trunc_ln58_83_reg_4132),
+    .p_read40(trunc_ln58_84_reg_4137),
+    .p_read41(trunc_ln58_85_reg_4142),
+    .p_read42(trunc_ln58_86_reg_4147),
+    .p_read43(trunc_ln58_87_reg_4152),
+    .p_read44(trunc_ln58_88_reg_4157),
+    .p_read45(trunc_ln58_89_reg_4162),
+    .p_read46(trunc_ln58_90_reg_4167),
+    .p_read47(trunc_ln58_91_reg_4172),
+    .p_read48(trunc_ln58_92_reg_4177),
+    .p_read49(trunc_ln58_93_reg_4182),
+    .p_read50(trunc_ln58_94_reg_4187),
+    .p_read51(trunc_ln58_95_reg_4192),
+    .p_read52(trunc_ln58_96_reg_4197),
+    .p_read53(trunc_ln58_97_reg_4202),
+    .p_read54(trunc_ln58_98_reg_4207),
+    .p_read55(trunc_ln58_99_reg_4212),
+    .p_read56(trunc_ln58_100_reg_4217),
+    .p_read57(trunc_ln58_101_reg_4222),
+    .p_read58(trunc_ln58_102_reg_4227),
+    .p_read59(trunc_ln58_103_reg_4232),
+    .p_read60(trunc_ln58_104_reg_4237),
+    .p_read61(trunc_ln58_105_reg_4242),
+    .p_read62(trunc_ln58_106_reg_4247),
+    .p_read63(trunc_ln58_107_reg_4252),
+    .layer19_out_din(grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1716_layer19_out_din),
+    .layer19_out_num_data_valid(7'd0),
+    .layer19_out_fifo_cap(7'd0),
+    .layer19_out_full_n(layer19_out_full_n),
+    .layer19_out_write(grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1716_layer19_out_write)
+);
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_CS_fsm <= ap_ST_fsm_state1;
+    end else begin
+        ap_CS_fsm <= ap_NS_fsm;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_done_reg <= 1'b0;
+    end else begin
+        if ((ap_continue == 1'b1)) begin
+            ap_done_reg <= 1'b0;
+        end else if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_3212_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+            ap_done_reg <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1716_ap_start_reg <= 1'b0;
+    end else begin
+        if (((1'b0 == ap_block_state2_ignore_call67) & (icmp_ln52_fu_3212_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+            grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1716_ap_start_reg <= 1'b1;
+        end else if ((grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1716_ap_ready == 1'b1)) begin
+            grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1716_ap_start_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        start_once_reg <= 1'b0;
+    end else begin
+        if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin
+            start_once_reg <= 1'b1;
+        end else if ((internal_ap_ready == 1'b1)) begin
+            start_once_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_state1) & (1'b1 == ap_CS_fsm_state1))) begin
+        indvar_flatten_fu_1706 <= 7'd0;
+    end else if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_3212_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        indvar_flatten_fu_1706 <= add_ln52_fu_3218_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_state2) & (1'b1 == ap_CS_fsm_state2))) begin
+        trunc_ln58_100_reg_4217 <= {{layer53_out_dout[911:896]}};
+        trunc_ln58_101_reg_4222 <= {{layer53_out_dout[927:912]}};
+        trunc_ln58_102_reg_4227 <= {{layer53_out_dout[943:928]}};
+        trunc_ln58_103_reg_4232 <= {{layer53_out_dout[959:944]}};
+        trunc_ln58_104_reg_4237 <= {{layer53_out_dout[975:960]}};
+        trunc_ln58_105_reg_4242 <= {{layer53_out_dout[991:976]}};
+        trunc_ln58_106_reg_4247 <= {{layer53_out_dout[1007:992]}};
+        trunc_ln58_107_reg_4252 <= {{layer53_out_dout[1023:1008]}};
+        trunc_ln58_46_reg_3947 <= {{layer53_out_dout[47:32]}};
+        trunc_ln58_47_reg_3952 <= {{layer53_out_dout[63:48]}};
+        trunc_ln58_48_reg_3957 <= {{layer53_out_dout[79:64]}};
+        trunc_ln58_49_reg_3962 <= {{layer53_out_dout[95:80]}};
+        trunc_ln58_50_reg_3967 <= {{layer53_out_dout[111:96]}};
+        trunc_ln58_51_reg_3972 <= {{layer53_out_dout[127:112]}};
+        trunc_ln58_52_reg_3977 <= {{layer53_out_dout[143:128]}};
+        trunc_ln58_53_reg_3982 <= {{layer53_out_dout[159:144]}};
+        trunc_ln58_54_reg_3987 <= {{layer53_out_dout[175:160]}};
+        trunc_ln58_55_reg_3992 <= {{layer53_out_dout[191:176]}};
+        trunc_ln58_56_reg_3997 <= {{layer53_out_dout[207:192]}};
+        trunc_ln58_57_reg_4002 <= {{layer53_out_dout[223:208]}};
+        trunc_ln58_58_reg_4007 <= {{layer53_out_dout[239:224]}};
+        trunc_ln58_59_reg_4012 <= {{layer53_out_dout[255:240]}};
+        trunc_ln58_60_reg_4017 <= {{layer53_out_dout[271:256]}};
+        trunc_ln58_61_reg_4022 <= {{layer53_out_dout[287:272]}};
+        trunc_ln58_62_reg_4027 <= {{layer53_out_dout[303:288]}};
+        trunc_ln58_63_reg_4032 <= {{layer53_out_dout[319:304]}};
+        trunc_ln58_64_reg_4037 <= {{layer53_out_dout[335:320]}};
+        trunc_ln58_65_reg_4042 <= {{layer53_out_dout[351:336]}};
+        trunc_ln58_66_reg_4047 <= {{layer53_out_dout[367:352]}};
+        trunc_ln58_67_reg_4052 <= {{layer53_out_dout[383:368]}};
+        trunc_ln58_68_reg_4057 <= {{layer53_out_dout[399:384]}};
+        trunc_ln58_69_reg_4062 <= {{layer53_out_dout[415:400]}};
+        trunc_ln58_70_reg_4067 <= {{layer53_out_dout[431:416]}};
+        trunc_ln58_71_reg_4072 <= {{layer53_out_dout[447:432]}};
+        trunc_ln58_72_reg_4077 <= {{layer53_out_dout[463:448]}};
+        trunc_ln58_73_reg_4082 <= {{layer53_out_dout[479:464]}};
+        trunc_ln58_74_reg_4087 <= {{layer53_out_dout[495:480]}};
+        trunc_ln58_75_reg_4092 <= {{layer53_out_dout[511:496]}};
+        trunc_ln58_76_reg_4097 <= {{layer53_out_dout[527:512]}};
+        trunc_ln58_77_reg_4102 <= {{layer53_out_dout[543:528]}};
+        trunc_ln58_78_reg_4107 <= {{layer53_out_dout[559:544]}};
+        trunc_ln58_79_reg_4112 <= {{layer53_out_dout[575:560]}};
+        trunc_ln58_80_reg_4117 <= {{layer53_out_dout[591:576]}};
+        trunc_ln58_81_reg_4122 <= {{layer53_out_dout[607:592]}};
+        trunc_ln58_82_reg_4127 <= {{layer53_out_dout[623:608]}};
+        trunc_ln58_83_reg_4132 <= {{layer53_out_dout[639:624]}};
+        trunc_ln58_84_reg_4137 <= {{layer53_out_dout[655:640]}};
+        trunc_ln58_85_reg_4142 <= {{layer53_out_dout[671:656]}};
+        trunc_ln58_86_reg_4147 <= {{layer53_out_dout[687:672]}};
+        trunc_ln58_87_reg_4152 <= {{layer53_out_dout[703:688]}};
+        trunc_ln58_88_reg_4157 <= {{layer53_out_dout[719:704]}};
+        trunc_ln58_89_reg_4162 <= {{layer53_out_dout[735:720]}};
+        trunc_ln58_90_reg_4167 <= {{layer53_out_dout[751:736]}};
+        trunc_ln58_91_reg_4172 <= {{layer53_out_dout[767:752]}};
+        trunc_ln58_92_reg_4177 <= {{layer53_out_dout[783:768]}};
+        trunc_ln58_93_reg_4182 <= {{layer53_out_dout[799:784]}};
+        trunc_ln58_94_reg_4187 <= {{layer53_out_dout[815:800]}};
+        trunc_ln58_95_reg_4192 <= {{layer53_out_dout[831:816]}};
+        trunc_ln58_96_reg_4197 <= {{layer53_out_dout[847:832]}};
+        trunc_ln58_97_reg_4202 <= {{layer53_out_dout[863:848]}};
+        trunc_ln58_98_reg_4207 <= {{layer53_out_dout[879:864]}};
+        trunc_ln58_99_reg_4212 <= {{layer53_out_dout[895:880]}};
+        trunc_ln58_reg_3937 <= trunc_ln58_fu_3224_p1;
+        trunc_ln58_s_reg_3942 <= {{layer53_out_dout[31:16]}};
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_block_state1)) begin
+        ap_ST_fsm_state1_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state1_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_block_state2)) begin
+        ap_ST_fsm_state2_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state2_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1716_ap_done == 1'b0)) begin
+        ap_ST_fsm_state3_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state3_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_3212_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+        ap_done = 1'b1;
+    end else begin
+        ap_done = ap_done_reg;
+    end
+end
+
+always @ (*) begin
+    if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
+        ap_idle = 1'b1;
+    end else begin
+        ap_idle = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_3212_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+        internal_ap_ready = 1'b1;
+    end else begin
+        internal_ap_ready = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state3)) begin
+        layer19_out_write = grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1716_layer19_out_write;
+    end else begin
+        layer19_out_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln52_fu_3212_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        layer53_out_blk_n = layer53_out_empty_n;
+    end else begin
+        layer53_out_blk_n = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_3212_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+        layer53_out_read_local = 1'b1;
+    end else begin
+        layer53_out_read_local = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((start_once_reg == 1'b0) & (start_full_n == 1'b0))) begin
+        real_start = 1'b0;
+    end else begin
+        real_start = ap_start;
+    end
+end
+
+always @ (*) begin
+    if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin
+        start_write = 1'b1;
+    end else begin
+        start_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    case (ap_CS_fsm)
+        ap_ST_fsm_state1 : begin
+            if (((1'b0 == ap_block_state1) & (1'b1 == ap_CS_fsm_state1))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end
+        end
+        ap_ST_fsm_state2 : begin
+            if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_3212_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end else if (((1'b0 == ap_block_state2) & (icmp_ln52_fu_3212_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state2))) begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end
+        end
+        ap_ST_fsm_state3 : begin
+            if (((grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1716_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state3))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end
+        end
+        default : begin
+            ap_NS_fsm = 'bx;
+        end
+    endcase
+end
+
+assign add_ln52_fu_3218_p2 = (indvar_flatten_fu_1706 + 7'd1);
+
+assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
+
+assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
+
+assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2];
+
+always @ (*) begin
+    ap_block_state1 = ((real_start == 1'b0) | (ap_done_reg == 1'b1));
+end
+
+always @ (*) begin
+    ap_block_state2 = ((icmp_ln52_fu_3212_p2 == 1'd0) & (layer53_out_empty_n == 1'b0));
+end
+
+always @ (*) begin
+    ap_block_state2_ignore_call67 = ((icmp_ln52_fu_3212_p2 == 1'd0) & (layer53_out_empty_n == 1'b0));
+end
+
+assign ap_ready = internal_ap_ready;
+
+assign grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1716_ap_start = grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1716_ap_start_reg;
+
+assign icmp_ln52_fu_3212_p2 = ((indvar_flatten_fu_1706 == 7'd100) ? 1'b1 : 1'b0);
+
+assign layer19_out_din = grp_compute_output_buffer_2d_array_array_ap_fixed_43_23_5_3_0_64u_config19_s_fu_1716_layer19_out_din;
+
+assign layer53_out_read = layer53_out_read_local;
+
+assign start_out = real_start;
+
+assign trunc_ln58_fu_3224_p1 = layer53_out_dout[15:0];
+
+endmodule //myproject_conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_64u_config19_s

myproject_prj/solution1/impl/verilog/myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_oudEe.v

@@ -0,0 +1,42 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1 ns / 1 ps
+module myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_oudEe (
+    address0, ce0, q0, 
+    reset, clk);
+
+parameter DataWidth = 3;
+parameter AddressWidth = 7;
+parameter AddressRange = 72;
+ 
+input[AddressWidth-1:0] address0;
+input ce0;
+output reg[DataWidth-1:0] q0;
+
+input reset;
+input clk;
+
+ 
+reg [DataWidth-1:0] rom0[0:AddressRange-1];
+
+
+initial begin
+     
+    $readmemh("./myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_37_17_5_3_0_config2_mult_s_oudEe.dat", rom0);
+end
+
+  
+always @(posedge clk) 
+begin 
+    if (ce0) 
+    begin
+        q0 <= rom0[address0];
+    end
+end
+
+
+endmodule
+

myproject_prj/solution1/impl/verilog/myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s_w14_ROM_NP_BRdlF.dat

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myproject_prj/solution1/impl/verilog/myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s_w14_ROM_NP_BRdlF.v

@@ -0,0 +1,42 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1 ns / 1 ps
+module myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s_w14_ROM_NP_BRdlF (
+    address0, ce0, q0, 
+    reset, clk);
+
+parameter DataWidth = 250;
+parameter AddressWidth = 10;
+parameter AddressRange = 576;
+ 
+input[AddressWidth-1:0] address0;
+input ce0;
+output reg[DataWidth-1:0] q0;
+
+input reset;
+input clk;
+
+ 
+(* rom_style = "block" *)reg [DataWidth-1:0] rom0[0:AddressRange-1];
+
+
+initial begin
+     
+    $readmemh("./myproject_dense_resource_rf_gt_nin_rem0_ap_fixed_ap_fixed_config14_mult_s_w14_ROM_NP_BRdlF.dat", rom0);
+end
+
+  
+always @(posedge clk) 
+begin 
+    if (ce0) 
+    begin
+        q0 <= rom0[address0];
+    end
+end
+
+
+endmodule
+

myproject_prj/solution1/impl/verilog/myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s.v

@@ -0,0 +1,648 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+
+`timescale 1 ns / 1 ps 
+
+module myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s (
+        ap_clk,
+        ap_rst,
+        ap_start,
+        ap_done,
+        ap_idle,
+        ap_ready,
+        data_0_val,
+        data_1_val,
+        data_2_val,
+        data_3_val,
+        data_4_val,
+        data_5_val,
+        data_6_val,
+        data_7_val,
+        ap_return
+);
+
+parameter    ap_ST_fsm_pp0_stage0 = 1'd1;
+
+input   ap_clk;
+input   ap_rst;
+input   ap_start;
+output   ap_done;
+output   ap_idle;
+output   ap_ready;
+input  [15:0] data_0_val;
+input  [15:0] data_1_val;
+input  [15:0] data_2_val;
+input  [15:0] data_3_val;
+input  [15:0] data_4_val;
+input  [15:0] data_5_val;
+input  [15:0] data_6_val;
+input  [15:0] data_7_val;
+output  [29:0] ap_return;
+
+reg ap_idle;
+reg[29:0] ap_return;
+
+(* fsm_encoding = "none" *) reg   [0:0] ap_CS_fsm;
+wire    ap_CS_fsm_pp0_stage0;
+wire    ap_enable_reg_pp0_iter0;
+reg    ap_enable_reg_pp0_iter1;
+reg    ap_idle_pp0;
+wire    ap_block_pp0_stage0_subdone;
+wire   [0:0] icmp_ln46_fu_385_p2;
+reg    ap_condition_exit_pp0_iter0_stage0;
+wire    ap_loop_exit_ready;
+reg    ap_ready_int;
+reg   [0:0] do_init_reg_128;
+reg   [2:0] phi_ln46_reg_143;
+reg   [15:0] data_0_val4_rewind_reg_157;
+reg   [15:0] data_1_val5_rewind_reg_171;
+reg   [15:0] data_2_val6_rewind_reg_185;
+reg   [15:0] data_3_val7_rewind_reg_199;
+reg   [15:0] data_4_val8_rewind_reg_213;
+reg   [15:0] data_5_val9_rewind_reg_227;
+reg   [15:0] data_6_val10_rewind_reg_241;
+reg   [15:0] data_7_val11_rewind_reg_255;
+reg   [29:0] res_02_reg_269;
+wire    ap_block_pp0_stage0_11001;
+wire   [2:0] w_index_fu_379_p2;
+reg   [2:0] w_index_reg_531;
+reg   [0:0] icmp_ln46_reg_536;
+wire  signed [29:0] grp_fu_482_p3;
+reg   [0:0] ap_phi_mux_do_init_phi_fu_131_p6;
+wire    ap_loop_init;
+wire    ap_block_pp0_stage0;
+reg   [2:0] ap_phi_mux_phi_ln46_phi_fu_146_p6;
+reg   [15:0] ap_phi_mux_data_0_val4_phi_phi_fu_287_p4;
+reg   [15:0] ap_phi_mux_data_1_val5_phi_phi_fu_299_p4;
+reg   [15:0] ap_phi_mux_data_2_val6_phi_phi_fu_311_p4;
+reg   [15:0] ap_phi_mux_data_3_val7_phi_phi_fu_323_p4;
+reg   [15:0] ap_phi_mux_data_4_val8_phi_phi_fu_335_p4;
+reg   [15:0] ap_phi_mux_data_5_val9_phi_phi_fu_347_p4;
+reg   [15:0] ap_phi_mux_data_6_val10_phi_phi_fu_359_p4;
+reg   [15:0] ap_phi_mux_data_7_val11_phi_phi_fu_371_p4;
+reg  signed [29:0] ap_phi_mux_res_02_phi_fu_273_p6;
+reg    ap_loop_init_pp0_iter1_reg;
+wire   [15:0] ap_phi_reg_pp0_iter0_data_0_val4_phi_reg_283;
+reg   [15:0] ap_phi_reg_pp0_iter1_data_0_val4_phi_reg_283;
+wire   [15:0] ap_phi_reg_pp0_iter0_data_1_val5_phi_reg_295;
+reg   [15:0] ap_phi_reg_pp0_iter1_data_1_val5_phi_reg_295;
+wire   [15:0] ap_phi_reg_pp0_iter0_data_2_val6_phi_reg_307;
+reg   [15:0] ap_phi_reg_pp0_iter1_data_2_val6_phi_reg_307;
+wire   [15:0] ap_phi_reg_pp0_iter0_data_3_val7_phi_reg_319;
+reg   [15:0] ap_phi_reg_pp0_iter1_data_3_val7_phi_reg_319;
+wire   [15:0] ap_phi_reg_pp0_iter0_data_4_val8_phi_reg_331;
+reg   [15:0] ap_phi_reg_pp0_iter1_data_4_val8_phi_reg_331;
+wire   [15:0] ap_phi_reg_pp0_iter0_data_5_val9_phi_reg_343;
+reg   [15:0] ap_phi_reg_pp0_iter1_data_5_val9_phi_reg_343;
+wire   [15:0] ap_phi_reg_pp0_iter0_data_6_val10_phi_reg_355;
+reg   [15:0] ap_phi_reg_pp0_iter1_data_6_val10_phi_reg_355;
+wire   [15:0] ap_phi_reg_pp0_iter0_data_7_val11_phi_reg_367;
+reg   [15:0] ap_phi_reg_pp0_iter1_data_7_val11_phi_reg_367;
+wire   [15:0] a_fu_391_p17;
+wire   [11:0] w_fu_431_p17;
+wire  signed [15:0] a_fu_391_p19;
+wire  signed [11:0] w_fu_431_p19;
+reg   [29:0] ap_return_preg;
+reg    ap_done_reg;
+wire    ap_continue_int;
+reg    ap_done_int;
+reg    ap_loop_exit_ready_pp0_iter1_reg;
+reg   [0:0] ap_NS_fsm;
+reg    ap_idle_pp0_0to0;
+reg    ap_reset_idle_pp0;
+wire    ap_enable_pp0;
+wire    ap_start_int;
+wire    ap_ready_sig;
+wire    ap_done_sig;
+reg    ap_condition_113;
+reg    ap_condition_119;
+wire   [2:0] a_fu_391_p1;
+wire   [2:0] a_fu_391_p3;
+wire   [2:0] a_fu_391_p5;
+wire   [2:0] a_fu_391_p7;
+wire  signed [2:0] a_fu_391_p9;
+wire  signed [2:0] a_fu_391_p11;
+wire  signed [2:0] a_fu_391_p13;
+wire  signed [2:0] a_fu_391_p15;
+wire   [2:0] w_fu_431_p1;
+wire   [2:0] w_fu_431_p3;
+wire   [2:0] w_fu_431_p5;
+wire   [2:0] w_fu_431_p7;
+wire  signed [2:0] w_fu_431_p9;
+wire  signed [2:0] w_fu_431_p11;
+wire  signed [2:0] w_fu_431_p13;
+wire  signed [2:0] w_fu_431_p15;
+wire    ap_ce_reg;
+
+// power-on initialization
+initial begin
+#0 ap_CS_fsm = 1'd1;
+#0 ap_enable_reg_pp0_iter1 = 1'b0;
+#0 ap_return_preg = 30'd0;
+#0 ap_done_reg = 1'b0;
+end
+
+(* dissolve_hierarchy = "yes" *) myproject_sparsemux_17_3_16_1_1 #(
+    .ID( 1 ),
+    .NUM_STAGE( 1 ),
+    .CASE0( 3'h0 ),
+    .din0_WIDTH( 16 ),
+    .CASE1( 3'h1 ),
+    .din1_WIDTH( 16 ),
+    .CASE2( 3'h2 ),
+    .din2_WIDTH( 16 ),
+    .CASE3( 3'h3 ),
+    .din3_WIDTH( 16 ),
+    .CASE4( 3'h4 ),
+    .din4_WIDTH( 16 ),
+    .CASE5( 3'h5 ),
+    .din5_WIDTH( 16 ),
+    .CASE6( 3'h6 ),
+    .din6_WIDTH( 16 ),
+    .CASE7( 3'h7 ),
+    .din7_WIDTH( 16 ),
+    .def_WIDTH( 16 ),
+    .sel_WIDTH( 3 ),
+    .dout_WIDTH( 16 ))
+sparsemux_17_3_16_1_1_U10337(
+    .din0(ap_phi_mux_data_0_val4_phi_phi_fu_287_p4),
+    .din1(ap_phi_mux_data_1_val5_phi_phi_fu_299_p4),
+    .din2(ap_phi_mux_data_2_val6_phi_phi_fu_311_p4),
+    .din3(ap_phi_mux_data_3_val7_phi_phi_fu_323_p4),
+    .din4(ap_phi_mux_data_4_val8_phi_phi_fu_335_p4),
+    .din5(ap_phi_mux_data_5_val9_phi_phi_fu_347_p4),
+    .din6(ap_phi_mux_data_6_val10_phi_phi_fu_359_p4),
+    .din7(ap_phi_mux_data_7_val11_phi_phi_fu_371_p4),
+    .def(a_fu_391_p17),
+    .sel(phi_ln46_reg_143),
+    .dout(a_fu_391_p19)
+);
+
+(* dissolve_hierarchy = "yes" *) myproject_sparsemux_17_3_12_1_1 #(
+    .ID( 1 ),
+    .NUM_STAGE( 1 ),
+    .CASE0( 3'h0 ),
+    .din0_WIDTH( 12 ),
+    .CASE1( 3'h1 ),
+    .din1_WIDTH( 12 ),
+    .CASE2( 3'h2 ),
+    .din2_WIDTH( 12 ),
+    .CASE3( 3'h3 ),
+    .din3_WIDTH( 12 ),
+    .CASE4( 3'h4 ),
+    .din4_WIDTH( 12 ),
+    .CASE5( 3'h5 ),
+    .din5_WIDTH( 12 ),
+    .CASE6( 3'h6 ),
+    .din6_WIDTH( 12 ),
+    .CASE7( 3'h7 ),
+    .din7_WIDTH( 12 ),
+    .def_WIDTH( 12 ),
+    .sel_WIDTH( 3 ),
+    .dout_WIDTH( 12 ))
+sparsemux_17_3_12_1_1_U10338(
+    .din0(12'd3452),
+    .din1(12'd978),
+    .din2(12'd3298),
+    .din3(12'd3581),
+    .din4(12'd3649),
+    .din5(12'd624),
+    .din6(12'd3542),
+    .din7(12'd2852),
+    .def(w_fu_431_p17),
+    .sel(phi_ln46_reg_143),
+    .dout(w_fu_431_p19)
+);
+
+myproject_mac_muladd_16s_12s_30s_30_1_1 #(
+    .ID( 1 ),
+    .NUM_STAGE( 1 ),
+    .din0_WIDTH( 16 ),
+    .din1_WIDTH( 12 ),
+    .din2_WIDTH( 30 ),
+    .dout_WIDTH( 30 ))
+mac_muladd_16s_12s_30s_30_1_1_U10339(
+    .din0(a_fu_391_p19),
+    .din1(w_fu_431_p19),
+    .din2(ap_phi_mux_res_02_phi_fu_273_p6),
+    .dout(grp_fu_482_p3)
+);
+
+myproject_flow_control_loop_pipe_no_ap_cont flow_control_loop_pipe_no_ap_cont_U(
+    .ap_clk(ap_clk),
+    .ap_rst(ap_rst),
+    .ap_start(ap_start),
+    .ap_ready(ap_ready_sig),
+    .ap_done(ap_done_sig),
+    .ap_start_int(ap_start_int),
+    .ap_loop_init(ap_loop_init),
+    .ap_ready_int(ap_ready_int),
+    .ap_loop_exit_ready(ap_condition_exit_pp0_iter0_stage0),
+    .ap_loop_exit_done(ap_done_int),
+    .ap_continue_int(ap_continue_int),
+    .ap_done_int(ap_done_int)
+);
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_CS_fsm <= ap_ST_fsm_pp0_stage0;
+    end else begin
+        ap_CS_fsm <= ap_NS_fsm;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_done_reg <= 1'b0;
+    end else begin
+        if ((ap_continue_int == 1'b1)) begin
+            ap_done_reg <= 1'b0;
+        end else if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_loop_exit_ready_pp0_iter1_reg == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+            ap_done_reg <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_enable_reg_pp0_iter1 <= 1'b0;
+    end else begin
+        if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+            ap_enable_reg_pp0_iter1 <= ap_start_int;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_return_preg <= 30'd0;
+    end else begin
+        if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln46_reg_536 == 1'd1))) begin
+            ap_return_preg <= grp_fu_482_p3;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_CS_fsm_pp0_stage0)) begin
+        if (((ap_loop_exit_ready == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone))) begin
+            ap_loop_exit_ready_pp0_iter1_reg <= 1'b0;
+        end else if ((1'b0 == ap_block_pp0_stage0_11001)) begin
+            ap_loop_exit_ready_pp0_iter1_reg <= ap_loop_exit_ready;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_condition_113)) begin
+        if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd1)) begin
+            ap_phi_reg_pp0_iter1_data_0_val4_phi_reg_283 <= data_0_val;
+        end else if ((1'b1 == 1'b1)) begin
+            ap_phi_reg_pp0_iter1_data_0_val4_phi_reg_283 <= ap_phi_reg_pp0_iter0_data_0_val4_phi_reg_283;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_condition_113)) begin
+        if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd1)) begin
+            ap_phi_reg_pp0_iter1_data_1_val5_phi_reg_295 <= data_1_val;
+        end else if ((1'b1 == 1'b1)) begin
+            ap_phi_reg_pp0_iter1_data_1_val5_phi_reg_295 <= ap_phi_reg_pp0_iter0_data_1_val5_phi_reg_295;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_condition_113)) begin
+        if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd1)) begin
+            ap_phi_reg_pp0_iter1_data_2_val6_phi_reg_307 <= data_2_val;
+        end else if ((1'b1 == 1'b1)) begin
+            ap_phi_reg_pp0_iter1_data_2_val6_phi_reg_307 <= ap_phi_reg_pp0_iter0_data_2_val6_phi_reg_307;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_condition_113)) begin
+        if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd1)) begin
+            ap_phi_reg_pp0_iter1_data_3_val7_phi_reg_319 <= data_3_val;
+        end else if ((1'b1 == 1'b1)) begin
+            ap_phi_reg_pp0_iter1_data_3_val7_phi_reg_319 <= ap_phi_reg_pp0_iter0_data_3_val7_phi_reg_319;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_condition_113)) begin
+        if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd1)) begin
+            ap_phi_reg_pp0_iter1_data_4_val8_phi_reg_331 <= data_4_val;
+        end else if ((1'b1 == 1'b1)) begin
+            ap_phi_reg_pp0_iter1_data_4_val8_phi_reg_331 <= ap_phi_reg_pp0_iter0_data_4_val8_phi_reg_331;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_condition_113)) begin
+        if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd1)) begin
+            ap_phi_reg_pp0_iter1_data_5_val9_phi_reg_343 <= data_5_val;
+        end else if ((1'b1 == 1'b1)) begin
+            ap_phi_reg_pp0_iter1_data_5_val9_phi_reg_343 <= ap_phi_reg_pp0_iter0_data_5_val9_phi_reg_343;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_condition_113)) begin
+        if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd1)) begin
+            ap_phi_reg_pp0_iter1_data_6_val10_phi_reg_355 <= data_6_val;
+        end else if ((1'b1 == 1'b1)) begin
+            ap_phi_reg_pp0_iter1_data_6_val10_phi_reg_355 <= ap_phi_reg_pp0_iter0_data_6_val10_phi_reg_355;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_condition_113)) begin
+        if ((ap_phi_mux_do_init_phi_fu_131_p6 == 1'd1)) begin
+            ap_phi_reg_pp0_iter1_data_7_val11_phi_reg_367 <= data_7_val;
+        end else if ((1'b1 == 1'b1)) begin
+            ap_phi_reg_pp0_iter1_data_7_val11_phi_reg_367 <= ap_phi_reg_pp0_iter0_data_7_val11_phi_reg_367;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln46_reg_536 == 1'd0))) begin
+        do_init_reg_128 <= 1'd0;
+    end else if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln46_reg_536 == 1'd1)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_loop_init == 1'b1)))) begin
+        do_init_reg_128 <= 1'd1;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln46_reg_536 == 1'd0))) begin
+        phi_ln46_reg_143 <= w_index_reg_531;
+    end else if ((((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln46_reg_536 == 1'd1)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_CS_fsm_pp0_stage0) & (ap_loop_init == 1'b1)))) begin
+        phi_ln46_reg_143 <= 3'd0;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if ((1'b1 == ap_condition_119)) begin
+        if ((icmp_ln46_reg_536 == 1'd1)) begin
+            res_02_reg_269 <= 30'd1073627136;
+        end else if ((icmp_ln46_reg_536 == 1'd0)) begin
+            res_02_reg_269 <= grp_fu_482_p3;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        ap_loop_init_pp0_iter1_reg <= ap_loop_init;
+        icmp_ln46_reg_536 <= icmp_ln46_fu_385_p2;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln46_reg_536 == 1'd0))) begin
+        data_0_val4_rewind_reg_157 <= ap_phi_mux_data_0_val4_phi_phi_fu_287_p4;
+        data_1_val5_rewind_reg_171 <= ap_phi_mux_data_1_val5_phi_phi_fu_299_p4;
+        data_2_val6_rewind_reg_185 <= ap_phi_mux_data_2_val6_phi_phi_fu_311_p4;
+        data_3_val7_rewind_reg_199 <= ap_phi_mux_data_3_val7_phi_phi_fu_323_p4;
+        data_4_val8_rewind_reg_213 <= ap_phi_mux_data_4_val8_phi_phi_fu_335_p4;
+        data_5_val9_rewind_reg_227 <= ap_phi_mux_data_5_val9_phi_phi_fu_347_p4;
+        data_6_val10_rewind_reg_241 <= ap_phi_mux_data_6_val10_phi_phi_fu_359_p4;
+        data_7_val11_rewind_reg_255 <= ap_phi_mux_data_7_val11_phi_phi_fu_371_p4;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        w_index_reg_531 <= w_index_fu_379_p2;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln46_fu_385_p2 == 1'd1) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        ap_condition_exit_pp0_iter0_stage0 = 1'b1;
+    end else begin
+        ap_condition_exit_pp0_iter0_stage0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_loop_exit_ready_pp0_iter1_reg == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        ap_done_int = 1'b1;
+    end else begin
+        ap_done_int = ap_done_reg;
+    end
+end
+
+always @ (*) begin
+    if (((ap_start_int == 1'b0) & (ap_idle_pp0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        ap_idle = 1'b1;
+    end else begin
+        ap_idle = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0))) begin
+        ap_idle_pp0 = 1'b1;
+    end else begin
+        ap_idle_pp0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((ap_enable_reg_pp0_iter0 == 1'b0)) begin
+        ap_idle_pp0_0to0 = 1'b1;
+    end else begin
+        ap_idle_pp0_0to0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((do_init_reg_128 == 1'd0)) begin
+        ap_phi_mux_data_0_val4_phi_phi_fu_287_p4 = data_0_val4_rewind_reg_157;
+    end else begin
+        ap_phi_mux_data_0_val4_phi_phi_fu_287_p4 = ap_phi_reg_pp0_iter1_data_0_val4_phi_reg_283;
+    end
+end
+
+always @ (*) begin
+    if ((do_init_reg_128 == 1'd0)) begin
+        ap_phi_mux_data_1_val5_phi_phi_fu_299_p4 = data_1_val5_rewind_reg_171;
+    end else begin
+        ap_phi_mux_data_1_val5_phi_phi_fu_299_p4 = ap_phi_reg_pp0_iter1_data_1_val5_phi_reg_295;
+    end
+end
+
+always @ (*) begin
+    if ((do_init_reg_128 == 1'd0)) begin
+        ap_phi_mux_data_2_val6_phi_phi_fu_311_p4 = data_2_val6_rewind_reg_185;
+    end else begin
+        ap_phi_mux_data_2_val6_phi_phi_fu_311_p4 = ap_phi_reg_pp0_iter1_data_2_val6_phi_reg_307;
+    end
+end
+
+always @ (*) begin
+    if ((do_init_reg_128 == 1'd0)) begin
+        ap_phi_mux_data_3_val7_phi_phi_fu_323_p4 = data_3_val7_rewind_reg_199;
+    end else begin
+        ap_phi_mux_data_3_val7_phi_phi_fu_323_p4 = ap_phi_reg_pp0_iter1_data_3_val7_phi_reg_319;
+    end
+end
+
+always @ (*) begin
+    if ((do_init_reg_128 == 1'd0)) begin
+        ap_phi_mux_data_4_val8_phi_phi_fu_335_p4 = data_4_val8_rewind_reg_213;
+    end else begin
+        ap_phi_mux_data_4_val8_phi_phi_fu_335_p4 = ap_phi_reg_pp0_iter1_data_4_val8_phi_reg_331;
+    end
+end
+
+always @ (*) begin
+    if ((do_init_reg_128 == 1'd0)) begin
+        ap_phi_mux_data_5_val9_phi_phi_fu_347_p4 = data_5_val9_rewind_reg_227;
+    end else begin
+        ap_phi_mux_data_5_val9_phi_phi_fu_347_p4 = ap_phi_reg_pp0_iter1_data_5_val9_phi_reg_343;
+    end
+end
+
+always @ (*) begin
+    if ((do_init_reg_128 == 1'd0)) begin
+        ap_phi_mux_data_6_val10_phi_phi_fu_359_p4 = data_6_val10_rewind_reg_241;
+    end else begin
+        ap_phi_mux_data_6_val10_phi_phi_fu_359_p4 = ap_phi_reg_pp0_iter1_data_6_val10_phi_reg_355;
+    end
+end
+
+always @ (*) begin
+    if ((do_init_reg_128 == 1'd0)) begin
+        ap_phi_mux_data_7_val11_phi_phi_fu_371_p4 = data_7_val11_rewind_reg_255;
+    end else begin
+        ap_phi_mux_data_7_val11_phi_phi_fu_371_p4 = ap_phi_reg_pp0_iter1_data_7_val11_phi_reg_367;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln46_reg_536 == 1'd0))) begin
+        ap_phi_mux_do_init_phi_fu_131_p6 = 1'd0;
+    end else if ((((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_loop_init == 1'b1)) | ((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln46_reg_536 == 1'd1)))) begin
+        ap_phi_mux_do_init_phi_fu_131_p6 = 1'd1;
+    end else begin
+        ap_phi_mux_do_init_phi_fu_131_p6 = do_init_reg_128;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln46_reg_536 == 1'd0))) begin
+        ap_phi_mux_phi_ln46_phi_fu_146_p6 = w_index_reg_531;
+    end else if ((((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_loop_init == 1'b1)) | ((1'b0 == ap_block_pp0_stage0) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln46_reg_536 == 1'd1)))) begin
+        ap_phi_mux_phi_ln46_phi_fu_146_p6 = 3'd0;
+    end else begin
+        ap_phi_mux_phi_ln46_phi_fu_146_p6 = phi_ln46_reg_143;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_loop_init_pp0_iter1_reg == 1'b1))) begin
+        ap_phi_mux_res_02_phi_fu_273_p6 = 30'd1073627136;
+    end else begin
+        ap_phi_mux_res_02_phi_fu_273_p6 = res_02_reg_269;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
+        ap_ready_int = 1'b1;
+    end else begin
+        ap_ready_int = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_start_int == 1'b0) & (ap_idle_pp0_0to0 == 1'b1))) begin
+        ap_reset_idle_pp0 = 1'b1;
+    end else begin
+        ap_reset_idle_pp0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (icmp_ln46_reg_536 == 1'd1))) begin
+        ap_return = grp_fu_482_p3;
+    end else begin
+        ap_return = ap_return_preg;
+    end
+end
+
+always @ (*) begin
+    case (ap_CS_fsm)
+        ap_ST_fsm_pp0_stage0 : begin
+            ap_NS_fsm = ap_ST_fsm_pp0_stage0;
+        end
+        default : begin
+            ap_NS_fsm = 'bx;
+        end
+    endcase
+end
+
+assign a_fu_391_p17 = 'bx;
+
+assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd0];
+
+assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1);
+
+assign ap_block_pp0_stage0_11001 = ~(1'b1 == 1'b1);
+
+assign ap_block_pp0_stage0_subdone = ~(1'b1 == 1'b1);
+
+always @ (*) begin
+    ap_condition_113 = ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0));
+end
+
+always @ (*) begin
+    ap_condition_119 = ((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0));
+end
+
+assign ap_done = ap_done_sig;
+
+assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1);
+
+assign ap_enable_reg_pp0_iter0 = ap_start_int;
+
+assign ap_loop_exit_ready = ap_condition_exit_pp0_iter0_stage0;
+
+assign ap_phi_reg_pp0_iter0_data_0_val4_phi_reg_283 = 'bx;
+
+assign ap_phi_reg_pp0_iter0_data_1_val5_phi_reg_295 = 'bx;
+
+assign ap_phi_reg_pp0_iter0_data_2_val6_phi_reg_307 = 'bx;
+
+assign ap_phi_reg_pp0_iter0_data_3_val7_phi_reg_319 = 'bx;
+
+assign ap_phi_reg_pp0_iter0_data_4_val8_phi_reg_331 = 'bx;
+
+assign ap_phi_reg_pp0_iter0_data_5_val9_phi_reg_343 = 'bx;
+
+assign ap_phi_reg_pp0_iter0_data_6_val10_phi_reg_355 = 'bx;
+
+assign ap_phi_reg_pp0_iter0_data_7_val11_phi_reg_367 = 'bx;
+
+assign ap_ready = ap_ready_sig;
+
+assign icmp_ln46_fu_385_p2 = ((ap_phi_mux_phi_ln46_phi_fu_146_p6 == 3'd7) ? 1'b1 : 1'b0);
+
+assign w_fu_431_p17 = 'bx;
+
+assign w_index_fu_379_p2 = (ap_phi_mux_phi_ln46_phi_fu_146_p6 + 3'd1);
+
+endmodule //myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_36_16_5_3_0_config58_mult_s

myproject_prj/solution1/impl/verilog/myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s_w12_Rcgu.v

@@ -0,0 +1,42 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1 ns / 1 ps
+module myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s_w12_Rcgu (
+    address0, ce0, q0, 
+    reset, clk);
+
+parameter DataWidth = 506;
+parameter AddressWidth = 8;
+parameter AddressRange = 144;
+ 
+input[AddressWidth-1:0] address0;
+input ce0;
+output reg[DataWidth-1:0] q0;
+
+input reset;
+input clk;
+
+ 
+(* rom_style = "block" *)reg [DataWidth-1:0] rom0[0:AddressRange-1];
+
+
+initial begin
+     
+    $readmemh("./myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config12_mult_s_w12_Rcgu.dat", rom0);
+end
+
+  
+always @(posedge clk) 
+begin 
+    if (ce0) 
+    begin
+        q0 <= rom0[address0];
+    end
+end
+
+
+endmodule
+

myproject_prj/solution1/impl/verilog/myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s_w9_ROMbrm.v

@@ -0,0 +1,42 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1 ns / 1 ps
+module myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s_w9_ROMbrm (
+    address0, ce0, q0, 
+    reset, clk);
+
+parameter DataWidth = 506;
+parameter AddressWidth = 7;
+parameter AddressRange = 72;
+ 
+input[AddressWidth-1:0] address0;
+input ce0;
+output reg[DataWidth-1:0] q0;
+
+input reset;
+input clk;
+
+ 
+(* rom_style = "block" *)reg [DataWidth-1:0] rom0[0:AddressRange-1];
+
+
+initial begin
+     
+    $readmemh("./myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s_w9_ROMbrm.dat", rom0);
+end
+
+  
+always @(posedge clk) 
+begin 
+    if (ce0) 
+    begin
+        q0 <= rom0[address0];
+    end
+end
+
+
+endmodule
+

myproject_prj/solution1/impl/verilog/myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s_w9_ROMbtn.v

@@ -0,0 +1,42 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1 ns / 1 ps
+module myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s_w9_ROMbtn (
+    address0, ce0, q0, 
+    reset, clk);
+
+parameter DataWidth = 251;
+parameter AddressWidth = 8;
+parameter AddressRange = 144;
+ 
+input[AddressWidth-1:0] address0;
+input ce0;
+output reg[DataWidth-1:0] q0;
+
+input reset;
+input clk;
+
+ 
+(* rom_style = "block" *)reg [DataWidth-1:0] rom0[0:AddressRange-1];
+
+
+initial begin
+     
+    $readmemh("./myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_41_21_5_3_0_config9_mult_s_w9_ROMbtn.dat", rom0);
+end
+
+  
+always @(posedge clk) 
+begin 
+    if (ce0) 
+    begin
+        q0 <= rom0[address0];
+    end
+end
+
+
+endmodule
+

myproject_prj/solution1/impl/verilog/myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s_w14_RdjF.v

@@ -0,0 +1,42 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1 ns / 1 ps
+module myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s_w14_RdjF (
+    address0, ce0, q0, 
+    reset, clk);
+
+parameter DataWidth = 1018;
+parameter AddressWidth = 8;
+parameter AddressRange = 144;
+ 
+input[AddressWidth-1:0] address0;
+input ce0;
+output reg[DataWidth-1:0] q0;
+
+input reset;
+input clk;
+
+ 
+(* rom_style = "block" *)reg [DataWidth-1:0] rom0[0:AddressRange-1];
+
+
+initial begin
+     
+    $readmemh("./myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_42_22_5_3_0_config14_mult_s_w14_RdjF.dat", rom0);
+end
+
+  
+always @(posedge clk) 
+begin 
+    if (ce0) 
+    begin
+        q0 <= rom0[address0];
+    end
+end
+
+
+endmodule
+

myproject_prj/solution1/impl/verilog/myproject_fifo_w1376_d256_A.v

@@ -0,0 +1,237 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+//RAW latency 2 
+
+module myproject_fifo_w1376_d256_A
+#(parameter
+    MEM_STYLE    = "auto",
+    DATA_WIDTH   = 1376,
+    ADDR_WIDTH   = 8,
+    DEPTH        = 256)
+(
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+    
+    // read 
+    output wire [ADDR_WIDTH:0]   if_num_data_valid, // for FRP
+    output wire [ADDR_WIDTH:0]   if_fifo_cap,       // for FRP
+
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+localparam 
+    MEM_DEPTH    = DEPTH - 1,
+    MEM_AWIDTH   = clog2(MEM_DEPTH);
+//------------------------Local signal-------------------
+    reg  [MEM_AWIDTH-1:0] waddr;
+    reg  [MEM_AWIDTH-1:0] raddr;
+    wire [MEM_AWIDTH-1:0] wnext;
+    wire [MEM_AWIDTH-1:0] rnext;
+    wire                  push;
+    wire                  pop;
+    reg  [MEM_AWIDTH:0]   mOutPtr;
+    reg                   empty_n = 1'b0;
+    reg                   full_n = 1'b1;
+    // has num_data_valid? 
+    wire                  num_extra_words;//yes
+    reg  [ADDR_WIDTH:0]   num_data_valid; //yes 
+
+    wire                  pop_dout;
+    reg  [ADDR_WIDTH:0]   num_data_cnt;
+    reg                   dout_vld = 1'b0;
+
+//------------------------Instantiation------------------
+    myproject_fifo_w1376_d256_A_ram 
+    #(  .MEM_STYLE  (MEM_STYLE),
+        .DATA_WIDTH (DATA_WIDTH),
+        .ADDR_WIDTH (MEM_AWIDTH),
+        .DEPTH      (MEM_DEPTH)
+    ) U_myproject_fifo_w1376_d256_A_ram (
+        .clk        (clk),
+        .reset      (reset),
+        .we         (push),
+        .waddr      (waddr),
+        .din        (if_din),
+        .raddr      (raddr),
+        .rden       (pop),
+        .dout       (if_dout)
+    );
+
+//------------------------Task and function--------------
+    function integer clog2;
+        input integer x;
+        integer n, m;
+    begin
+        n = 1;
+        m = 2;
+        while (m < x) begin
+            n = n + 1;
+            m = m * 2;
+        end
+        clog2 = n;
+    end
+    endfunction
+//------------------------Body---------------------------
+    // num_data_valid 
+    assign if_num_data_valid = num_data_valid;
+    assign if_fifo_cap = DEPTH;
+
+    // almost full/empty 
+
+    // program full/empty 
+
+    assign if_full_n  = full_n;
+    assign if_empty_n = dout_vld;
+
+    assign push       = full_n & if_write_ce & if_write;
+    assign pop        = empty_n & (pop_dout | ~dout_vld);
+    assign pop_dout   = dout_vld & if_read_ce & if_read;
+    
+    assign wnext      = !push                    ? waddr :
+                        (waddr == MEM_DEPTH - 1) ? 1'b0  :
+                        waddr + 1'b1;
+    assign rnext      = !pop                     ? raddr :
+                        (raddr == MEM_DEPTH - 1) ? 1'b0  :
+                        raddr + 1'b1;
+
+    // waddr
+    always @(posedge clk) begin
+        if (reset)
+            waddr <= {MEM_AWIDTH{1'b0}};
+        else
+            waddr <= wnext;
+    end
+
+    // raddr
+    always @(posedge clk) begin
+        if (reset)
+            raddr <= {MEM_AWIDTH{1'b0}};
+        else
+            raddr <= rnext;
+    end
+
+    // mOutPtr
+    always @(posedge clk) begin
+        if (reset)
+            mOutPtr <= {MEM_AWIDTH+1{1'b0}};
+        else if (push & ~pop)
+            mOutPtr <= mOutPtr + 1'b1;
+        else if (~push & pop)
+            mOutPtr <= mOutPtr - 1'b1;
+    end
+
+    // full_n 
+    always @(posedge clk) begin
+        if (reset)
+            full_n <= 1'b1;
+        else if ((push & ~pop_dout) && (num_data_cnt == DEPTH - 1))
+            full_n <= 1'b0;
+        else if (~push & pop_dout)
+            full_n <= 1'b1;
+    end
+
+    // empty_n
+    always @(posedge clk) begin
+        if (reset)
+            empty_n <= 1'b0;
+        else if (push & ~pop)
+            empty_n <= 1'b1;
+        else if ((~push & pop) && (mOutPtr == 1))
+            empty_n <= 1'b0;
+    end
+
+    // almost_full_n 
+
+    // almost_empty_n 
+
+    // prog_full_n 
+
+    // prog_empty_n 
+
+    // num_data_cnt
+    always @(posedge clk) begin
+        if (reset)
+            num_data_cnt <= {ADDR_WIDTH+1{1'b0}};
+        else if ( push & ~pop_dout)
+            num_data_cnt <= num_data_cnt + 1'b1;
+        else if (~push & pop_dout)
+            num_data_cnt <= num_data_cnt - 1'b1;
+    end
+
+    // num_data_valid 
+    assign num_extra_words = (dout_vld & ~pop_dout) ? 1 : 0;
+                             
+    always @(posedge clk) begin
+        if (reset)
+            num_data_valid <= {ADDR_WIDTH+1{1'b0}};
+        else if (empty_n | (dout_vld & ~pop_dout))
+            num_data_valid <= push + mOutPtr + num_extra_words;
+        else
+            num_data_valid <= num_extra_words;
+    end // 
+
+    // dout_vld
+    always @(posedge clk) begin
+        if (reset)
+            dout_vld <= 1'b0;
+        else if (pop)
+            dout_vld <= 1'b1;
+        else if (pop_dout)
+            dout_vld <= 1'b0;
+    end
+
+endmodule
+
+
+module myproject_fifo_w1376_d256_A_ram
+#(parameter
+    MEM_STYLE   = "auto",
+    DATA_WIDTH  = 1376,
+    ADDR_WIDTH  = 8,
+    DEPTH       = 256)
+(
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  we,
+    input  wire [ADDR_WIDTH-1:0] waddr,
+    input  wire [DATA_WIDTH-1:0] din,
+    input  wire [ADDR_WIDTH-1:0] raddr,
+    input  wire                  rden,
+    output wire [DATA_WIDTH-1:0] dout
+);
+
+    (* ram_style = MEM_STYLE *)
+    reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+    reg  [DATA_WIDTH-1:0] mem_reg;
+
+    always @(posedge clk) begin
+        if (we)
+            mem[waddr] <= din;
+    end
+
+    always @(posedge clk) begin
+        if (reset)
+            mem_reg <= 0;
+        else if (rden)
+            mem_reg <= mem[raddr];
+    end
+    
+    assign dout = mem_reg;
+
+endmodule

myproject_prj/solution1/impl/verilog/myproject_fifo_w1536_d256_A.v

@@ -0,0 +1,237 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+//RAW latency 2 
+
+module myproject_fifo_w1536_d256_A
+#(parameter
+    MEM_STYLE    = "auto",
+    DATA_WIDTH   = 1536,
+    ADDR_WIDTH   = 8,
+    DEPTH        = 256)
+(
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+    
+    // read 
+    output wire [ADDR_WIDTH:0]   if_num_data_valid, // for FRP
+    output wire [ADDR_WIDTH:0]   if_fifo_cap,       // for FRP
+
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+localparam 
+    MEM_DEPTH    = DEPTH - 1,
+    MEM_AWIDTH   = clog2(MEM_DEPTH);
+//------------------------Local signal-------------------
+    reg  [MEM_AWIDTH-1:0] waddr;
+    reg  [MEM_AWIDTH-1:0] raddr;
+    wire [MEM_AWIDTH-1:0] wnext;
+    wire [MEM_AWIDTH-1:0] rnext;
+    wire                  push;
+    wire                  pop;
+    reg  [MEM_AWIDTH:0]   mOutPtr;
+    reg                   empty_n = 1'b0;
+    reg                   full_n = 1'b1;
+    // has num_data_valid? 
+    wire                  num_extra_words;//yes
+    reg  [ADDR_WIDTH:0]   num_data_valid; //yes 
+
+    wire                  pop_dout;
+    reg  [ADDR_WIDTH:0]   num_data_cnt;
+    reg                   dout_vld = 1'b0;
+
+//------------------------Instantiation------------------
+    myproject_fifo_w1536_d256_A_ram 
+    #(  .MEM_STYLE  (MEM_STYLE),
+        .DATA_WIDTH (DATA_WIDTH),
+        .ADDR_WIDTH (MEM_AWIDTH),
+        .DEPTH      (MEM_DEPTH)
+    ) U_myproject_fifo_w1536_d256_A_ram (
+        .clk        (clk),
+        .reset      (reset),
+        .we         (push),
+        .waddr      (waddr),
+        .din        (if_din),
+        .raddr      (raddr),
+        .rden       (pop),
+        .dout       (if_dout)
+    );
+
+//------------------------Task and function--------------
+    function integer clog2;
+        input integer x;
+        integer n, m;
+    begin
+        n = 1;
+        m = 2;
+        while (m < x) begin
+            n = n + 1;
+            m = m * 2;
+        end
+        clog2 = n;
+    end
+    endfunction
+//------------------------Body---------------------------
+    // num_data_valid 
+    assign if_num_data_valid = num_data_valid;
+    assign if_fifo_cap = DEPTH;
+
+    // almost full/empty 
+
+    // program full/empty 
+
+    assign if_full_n  = full_n;
+    assign if_empty_n = dout_vld;
+
+    assign push       = full_n & if_write_ce & if_write;
+    assign pop        = empty_n & (pop_dout | ~dout_vld);
+    assign pop_dout   = dout_vld & if_read_ce & if_read;
+    
+    assign wnext      = !push                    ? waddr :
+                        (waddr == MEM_DEPTH - 1) ? 1'b0  :
+                        waddr + 1'b1;
+    assign rnext      = !pop                     ? raddr :
+                        (raddr == MEM_DEPTH - 1) ? 1'b0  :
+                        raddr + 1'b1;
+
+    // waddr
+    always @(posedge clk) begin
+        if (reset)
+            waddr <= {MEM_AWIDTH{1'b0}};
+        else
+            waddr <= wnext;
+    end
+
+    // raddr
+    always @(posedge clk) begin
+        if (reset)
+            raddr <= {MEM_AWIDTH{1'b0}};
+        else
+            raddr <= rnext;
+    end
+
+    // mOutPtr
+    always @(posedge clk) begin
+        if (reset)
+            mOutPtr <= {MEM_AWIDTH+1{1'b0}};
+        else if (push & ~pop)
+            mOutPtr <= mOutPtr + 1'b1;
+        else if (~push & pop)
+            mOutPtr <= mOutPtr - 1'b1;
+    end
+
+    // full_n 
+    always @(posedge clk) begin
+        if (reset)
+            full_n <= 1'b1;
+        else if ((push & ~pop_dout) && (num_data_cnt == DEPTH - 1))
+            full_n <= 1'b0;
+        else if (~push & pop_dout)
+            full_n <= 1'b1;
+    end
+
+    // empty_n
+    always @(posedge clk) begin
+        if (reset)
+            empty_n <= 1'b0;
+        else if (push & ~pop)
+            empty_n <= 1'b1;
+        else if ((~push & pop) && (mOutPtr == 1))
+            empty_n <= 1'b0;
+    end
+
+    // almost_full_n 
+
+    // almost_empty_n 
+
+    // prog_full_n 
+
+    // prog_empty_n 
+
+    // num_data_cnt
+    always @(posedge clk) begin
+        if (reset)
+            num_data_cnt <= {ADDR_WIDTH+1{1'b0}};
+        else if ( push & ~pop_dout)
+            num_data_cnt <= num_data_cnt + 1'b1;
+        else if (~push & pop_dout)
+            num_data_cnt <= num_data_cnt - 1'b1;
+    end
+
+    // num_data_valid 
+    assign num_extra_words = (dout_vld & ~pop_dout) ? 1 : 0;
+                             
+    always @(posedge clk) begin
+        if (reset)
+            num_data_valid <= {ADDR_WIDTH+1{1'b0}};
+        else if (empty_n | (dout_vld & ~pop_dout))
+            num_data_valid <= push + mOutPtr + num_extra_words;
+        else
+            num_data_valid <= num_extra_words;
+    end // 
+
+    // dout_vld
+    always @(posedge clk) begin
+        if (reset)
+            dout_vld <= 1'b0;
+        else if (pop)
+            dout_vld <= 1'b1;
+        else if (pop_dout)
+            dout_vld <= 1'b0;
+    end
+
+endmodule
+
+
+module myproject_fifo_w1536_d256_A_ram
+#(parameter
+    MEM_STYLE   = "auto",
+    DATA_WIDTH  = 1536,
+    ADDR_WIDTH  = 8,
+    DEPTH       = 256)
+(
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  we,
+    input  wire [ADDR_WIDTH-1:0] waddr,
+    input  wire [DATA_WIDTH-1:0] din,
+    input  wire [ADDR_WIDTH-1:0] raddr,
+    input  wire                  rden,
+    output wire [DATA_WIDTH-1:0] dout
+);
+
+    (* ram_style = MEM_STYLE *)
+    reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+    reg  [DATA_WIDTH-1:0] mem_reg;
+
+    always @(posedge clk) begin
+        if (we)
+            mem[waddr] <= din;
+    end
+
+    always @(posedge clk) begin
+        if (reset)
+            mem_reg <= 0;
+        else if (rden)
+            mem_reg <= mem[raddr];
+    end
+    
+    assign dout = mem_reg;
+
+endmodule

myproject_prj/solution1/impl/verilog/myproject_fifo_w16_d4096_A.v

@@ -0,0 +1,237 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+//RAW latency 2 
+
+module myproject_fifo_w16_d4096_A
+#(parameter
+    MEM_STYLE    = "auto",
+    DATA_WIDTH   = 16,
+    ADDR_WIDTH   = 12,
+    DEPTH        = 4096)
+(
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+    
+    // read 
+    output wire [ADDR_WIDTH:0]   if_num_data_valid, // for FRP
+    output wire [ADDR_WIDTH:0]   if_fifo_cap,       // for FRP
+
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+localparam 
+    MEM_DEPTH    = DEPTH - 1,
+    MEM_AWIDTH   = clog2(MEM_DEPTH);
+//------------------------Local signal-------------------
+    reg  [MEM_AWIDTH-1:0] waddr;
+    reg  [MEM_AWIDTH-1:0] raddr;
+    wire [MEM_AWIDTH-1:0] wnext;
+    wire [MEM_AWIDTH-1:0] rnext;
+    wire                  push;
+    wire                  pop;
+    reg  [MEM_AWIDTH:0]   mOutPtr;
+    reg                   empty_n = 1'b0;
+    reg                   full_n = 1'b1;
+    // has num_data_valid? 
+    wire                  num_extra_words;//yes
+    reg  [ADDR_WIDTH:0]   num_data_valid; //yes 
+
+    wire                  pop_dout;
+    reg  [ADDR_WIDTH:0]   num_data_cnt;
+    reg                   dout_vld = 1'b0;
+
+//------------------------Instantiation------------------
+    myproject_fifo_w16_d4096_A_ram 
+    #(  .MEM_STYLE  (MEM_STYLE),
+        .DATA_WIDTH (DATA_WIDTH),
+        .ADDR_WIDTH (MEM_AWIDTH),
+        .DEPTH      (MEM_DEPTH)
+    ) U_myproject_fifo_w16_d4096_A_ram (
+        .clk        (clk),
+        .reset      (reset),
+        .we         (push),
+        .waddr      (waddr),
+        .din        (if_din),
+        .raddr      (raddr),
+        .rden       (pop),
+        .dout       (if_dout)
+    );
+
+//------------------------Task and function--------------
+    function integer clog2;
+        input integer x;
+        integer n, m;
+    begin
+        n = 1;
+        m = 2;
+        while (m < x) begin
+            n = n + 1;
+            m = m * 2;
+        end
+        clog2 = n;
+    end
+    endfunction
+//------------------------Body---------------------------
+    // num_data_valid 
+    assign if_num_data_valid = num_data_valid;
+    assign if_fifo_cap = DEPTH;
+
+    // almost full/empty 
+
+    // program full/empty 
+
+    assign if_full_n  = full_n;
+    assign if_empty_n = dout_vld;
+
+    assign push       = full_n & if_write_ce & if_write;
+    assign pop        = empty_n & (pop_dout | ~dout_vld);
+    assign pop_dout   = dout_vld & if_read_ce & if_read;
+    
+    assign wnext      = !push                    ? waddr :
+                        (waddr == MEM_DEPTH - 1) ? 1'b0  :
+                        waddr + 1'b1;
+    assign rnext      = !pop                     ? raddr :
+                        (raddr == MEM_DEPTH - 1) ? 1'b0  :
+                        raddr + 1'b1;
+
+    // waddr
+    always @(posedge clk) begin
+        if (reset)
+            waddr <= {MEM_AWIDTH{1'b0}};
+        else
+            waddr <= wnext;
+    end
+
+    // raddr
+    always @(posedge clk) begin
+        if (reset)
+            raddr <= {MEM_AWIDTH{1'b0}};
+        else
+            raddr <= rnext;
+    end
+
+    // mOutPtr
+    always @(posedge clk) begin
+        if (reset)
+            mOutPtr <= {MEM_AWIDTH+1{1'b0}};
+        else if (push & ~pop)
+            mOutPtr <= mOutPtr + 1'b1;
+        else if (~push & pop)
+            mOutPtr <= mOutPtr - 1'b1;
+    end
+
+    // full_n 
+    always @(posedge clk) begin
+        if (reset)
+            full_n <= 1'b1;
+        else if ((push & ~pop_dout) && (num_data_cnt == DEPTH - 1))
+            full_n <= 1'b0;
+        else if (~push & pop_dout)
+            full_n <= 1'b1;
+    end
+
+    // empty_n
+    always @(posedge clk) begin
+        if (reset)
+            empty_n <= 1'b0;
+        else if (push & ~pop)
+            empty_n <= 1'b1;
+        else if ((~push & pop) && (mOutPtr == 1))
+            empty_n <= 1'b0;
+    end
+
+    // almost_full_n 
+
+    // almost_empty_n 
+
+    // prog_full_n 
+
+    // prog_empty_n 
+
+    // num_data_cnt
+    always @(posedge clk) begin
+        if (reset)
+            num_data_cnt <= {ADDR_WIDTH+1{1'b0}};
+        else if ( push & ~pop_dout)
+            num_data_cnt <= num_data_cnt + 1'b1;
+        else if (~push & pop_dout)
+            num_data_cnt <= num_data_cnt - 1'b1;
+    end
+
+    // num_data_valid 
+    assign num_extra_words = (dout_vld & ~pop_dout) ? 1 : 0;
+                             
+    always @(posedge clk) begin
+        if (reset)
+            num_data_valid <= {ADDR_WIDTH+1{1'b0}};
+        else if (empty_n | (dout_vld & ~pop_dout))
+            num_data_valid <= push + mOutPtr + num_extra_words;
+        else
+            num_data_valid <= num_extra_words;
+    end // 
+
+    // dout_vld
+    always @(posedge clk) begin
+        if (reset)
+            dout_vld <= 1'b0;
+        else if (pop)
+            dout_vld <= 1'b1;
+        else if (pop_dout)
+            dout_vld <= 1'b0;
+    end
+
+endmodule
+
+
+module myproject_fifo_w16_d4096_A_ram
+#(parameter
+    MEM_STYLE   = "auto",
+    DATA_WIDTH  = 16,
+    ADDR_WIDTH  = 12,
+    DEPTH       = 4096)
+(
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  we,
+    input  wire [ADDR_WIDTH-1:0] waddr,
+    input  wire [DATA_WIDTH-1:0] din,
+    input  wire [ADDR_WIDTH-1:0] raddr,
+    input  wire                  rden,
+    output wire [DATA_WIDTH-1:0] dout
+);
+
+    (* ram_style = MEM_STYLE *)
+    reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+    reg  [DATA_WIDTH-1:0] mem_reg;
+
+    always @(posedge clk) begin
+        if (we)
+            mem[waddr] <= din;
+    end
+
+    always @(posedge clk) begin
+        if (reset)
+            mem_reg <= 0;
+        else if (rden)
+            mem_reg <= mem[raddr];
+    end
+    
+    assign dout = mem_reg;
+
+endmodule

myproject_prj/solution1/impl/verilog/myproject_fifo_w16_d64_S.v

@@ -0,0 +1,155 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+//RAW latency 1 
+
+module myproject_fifo_w16_d64_S
+#(parameter
+    MEM_STYLE    = "shiftReg",
+    DATA_WIDTH   = 16,
+    ADDR_WIDTH   = 6,
+    DEPTH        = 64)
+(
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+    
+    // read 
+    output wire [ADDR_WIDTH:0]   if_num_data_valid, // for FRP
+    output wire [ADDR_WIDTH:0]   if_fifo_cap,       // for FRP
+
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+localparam 
+    SRL_DEPTH    = DEPTH,
+    SRL_AWIDTH   = ADDR_WIDTH;
+//------------------------Local signal-------------------
+    reg  [SRL_AWIDTH-1:0] addr;
+    wire                  push;
+    wire                  pop;
+    reg  [SRL_AWIDTH:0]   mOutPtr;
+    reg                   empty_n = 1'b0;
+    reg                   full_n = 1'b1; 
+
+//------------------------Instantiation------------------
+    myproject_fifo_w16_d64_S_ShiftReg 
+    #(  .DATA_WIDTH (DATA_WIDTH),
+        .ADDR_WIDTH (SRL_AWIDTH),
+        .DEPTH      (SRL_DEPTH))
+    U_myproject_fifo_w16_d64_S_ShiftReg (
+        .clk        (clk),
+        .we         (push),
+        .addr       (addr),
+        .din        (if_din),
+        .dout       (if_dout)
+    );
+//------------------------Task and function--------------
+
+//------------------------Body---------------------------
+    // num_data_valid 
+    assign if_num_data_valid = mOutPtr;
+    assign if_fifo_cap       = DEPTH;
+
+    // almost full/empty 
+
+    // program full/empty 
+
+    assign if_full_n  = full_n; 
+    assign if_empty_n = empty_n;
+
+    assign push       = full_n & if_write_ce & if_write;
+    assign pop        = empty_n & if_read_ce & if_read;
+
+    // addr
+    always @(posedge clk) begin
+        if (reset)
+            addr <= {SRL_AWIDTH{1'b0}};
+        else if (push & ~pop && empty_n)
+            addr <= addr + 1'b1;
+        else if (~push & pop && (mOutPtr != 1))
+            addr <= addr - 1'b1;
+    end
+
+    // mOutPtr
+    always @(posedge clk) begin
+        if (reset)
+            mOutPtr <= {SRL_AWIDTH+1{1'b0}};
+        else if (push & ~pop)
+            mOutPtr <= mOutPtr + 1'b1;
+        else if (~push & pop)
+            mOutPtr <= mOutPtr - 1'b1;
+    end
+
+    // full_n
+    always @(posedge clk) begin
+        if (reset)
+            full_n <= 1'b1;
+        else if ((push & ~pop) && (mOutPtr == DEPTH - 1))
+            full_n <= 1'b0;
+        else if (~push & pop)
+            full_n <= 1'b1;
+    end
+
+    // empty_n
+    always @(posedge clk) begin
+        if (reset)
+            empty_n <= 1'b0;
+        else if (push & ~pop)
+            empty_n <= 1'b1;
+        else if ((~push & pop) && (mOutPtr == 1))
+            empty_n <= 1'b0;
+    end
+
+    // almost_full_n 
+
+    // almost_empty_n 
+
+    // prog_full_n 
+ 
+    // prog_empty_n 
+
+endmodule  
+
+
+module myproject_fifo_w16_d64_S_ShiftReg
+#(parameter
+    DATA_WIDTH  = 16,
+    ADDR_WIDTH  = 6,
+    DEPTH       = 64)
+(
+    input  wire                  clk,
+    input  wire                  we,
+    input  wire [ADDR_WIDTH-1:0] addr,
+    input  wire [DATA_WIDTH-1:0] din,
+    output wire [DATA_WIDTH-1:0] dout
+);
+
+    reg [DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
+    integer i;
+
+    always @(posedge clk) begin
+        if (we) begin
+            for (i=0; i<DEPTH-1; i=i+1)
+                SRL_SIG[i+1] <= SRL_SIG[i];
+            SRL_SIG[0] <= din;
+        end
+    end
+
+    assign dout = SRL_SIG[addr];
+
+endmodule

myproject_prj/solution1/impl/verilog/myproject_fifo_w320_d4096_A.v

@@ -0,0 +1,237 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+//RAW latency 2 
+
+module myproject_fifo_w320_d4096_A
+#(parameter
+    MEM_STYLE    = "auto",
+    DATA_WIDTH   = 320,
+    ADDR_WIDTH   = 12,
+    DEPTH        = 4096)
+(
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+    
+    // read 
+    output wire [ADDR_WIDTH:0]   if_num_data_valid, // for FRP
+    output wire [ADDR_WIDTH:0]   if_fifo_cap,       // for FRP
+
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+localparam 
+    MEM_DEPTH    = DEPTH - 1,
+    MEM_AWIDTH   = clog2(MEM_DEPTH);
+//------------------------Local signal-------------------
+    reg  [MEM_AWIDTH-1:0] waddr;
+    reg  [MEM_AWIDTH-1:0] raddr;
+    wire [MEM_AWIDTH-1:0] wnext;
+    wire [MEM_AWIDTH-1:0] rnext;
+    wire                  push;
+    wire                  pop;
+    reg  [MEM_AWIDTH:0]   mOutPtr;
+    reg                   empty_n = 1'b0;
+    reg                   full_n = 1'b1;
+    // has num_data_valid? 
+    wire                  num_extra_words;//yes
+    reg  [ADDR_WIDTH:0]   num_data_valid; //yes 
+
+    wire                  pop_dout;
+    reg  [ADDR_WIDTH:0]   num_data_cnt;
+    reg                   dout_vld = 1'b0;
+
+//------------------------Instantiation------------------
+    myproject_fifo_w320_d4096_A_ram 
+    #(  .MEM_STYLE  (MEM_STYLE),
+        .DATA_WIDTH (DATA_WIDTH),
+        .ADDR_WIDTH (MEM_AWIDTH),
+        .DEPTH      (MEM_DEPTH)
+    ) U_myproject_fifo_w320_d4096_A_ram (
+        .clk        (clk),
+        .reset      (reset),
+        .we         (push),
+        .waddr      (waddr),
+        .din        (if_din),
+        .raddr      (raddr),
+        .rden       (pop),
+        .dout       (if_dout)
+    );
+
+//------------------------Task and function--------------
+    function integer clog2;
+        input integer x;
+        integer n, m;
+    begin
+        n = 1;
+        m = 2;
+        while (m < x) begin
+            n = n + 1;
+            m = m * 2;
+        end
+        clog2 = n;
+    end
+    endfunction
+//------------------------Body---------------------------
+    // num_data_valid 
+    assign if_num_data_valid = num_data_valid;
+    assign if_fifo_cap = DEPTH;
+
+    // almost full/empty 
+
+    // program full/empty 
+
+    assign if_full_n  = full_n;
+    assign if_empty_n = dout_vld;
+
+    assign push       = full_n & if_write_ce & if_write;
+    assign pop        = empty_n & (pop_dout | ~dout_vld);
+    assign pop_dout   = dout_vld & if_read_ce & if_read;
+    
+    assign wnext      = !push                    ? waddr :
+                        (waddr == MEM_DEPTH - 1) ? 1'b0  :
+                        waddr + 1'b1;
+    assign rnext      = !pop                     ? raddr :
+                        (raddr == MEM_DEPTH - 1) ? 1'b0  :
+                        raddr + 1'b1;
+
+    // waddr
+    always @(posedge clk) begin
+        if (reset)
+            waddr <= {MEM_AWIDTH{1'b0}};
+        else
+            waddr <= wnext;
+    end
+
+    // raddr
+    always @(posedge clk) begin
+        if (reset)
+            raddr <= {MEM_AWIDTH{1'b0}};
+        else
+            raddr <= rnext;
+    end
+
+    // mOutPtr
+    always @(posedge clk) begin
+        if (reset)
+            mOutPtr <= {MEM_AWIDTH+1{1'b0}};
+        else if (push & ~pop)
+            mOutPtr <= mOutPtr + 1'b1;
+        else if (~push & pop)
+            mOutPtr <= mOutPtr - 1'b1;
+    end
+
+    // full_n 
+    always @(posedge clk) begin
+        if (reset)
+            full_n <= 1'b1;
+        else if ((push & ~pop_dout) && (num_data_cnt == DEPTH - 1))
+            full_n <= 1'b0;
+        else if (~push & pop_dout)
+            full_n <= 1'b1;
+    end
+
+    // empty_n
+    always @(posedge clk) begin
+        if (reset)
+            empty_n <= 1'b0;
+        else if (push & ~pop)
+            empty_n <= 1'b1;
+        else if ((~push & pop) && (mOutPtr == 1))
+            empty_n <= 1'b0;
+    end
+
+    // almost_full_n 
+
+    // almost_empty_n 
+
+    // prog_full_n 
+
+    // prog_empty_n 
+
+    // num_data_cnt
+    always @(posedge clk) begin
+        if (reset)
+            num_data_cnt <= {ADDR_WIDTH+1{1'b0}};
+        else if ( push & ~pop_dout)
+            num_data_cnt <= num_data_cnt + 1'b1;
+        else if (~push & pop_dout)
+            num_data_cnt <= num_data_cnt - 1'b1;
+    end
+
+    // num_data_valid 
+    assign num_extra_words = (dout_vld & ~pop_dout) ? 1 : 0;
+                             
+    always @(posedge clk) begin
+        if (reset)
+            num_data_valid <= {ADDR_WIDTH+1{1'b0}};
+        else if (empty_n | (dout_vld & ~pop_dout))
+            num_data_valid <= push + mOutPtr + num_extra_words;
+        else
+            num_data_valid <= num_extra_words;
+    end // 
+
+    // dout_vld
+    always @(posedge clk) begin
+        if (reset)
+            dout_vld <= 1'b0;
+        else if (pop)
+            dout_vld <= 1'b1;
+        else if (pop_dout)
+            dout_vld <= 1'b0;
+    end
+
+endmodule
+
+
+module myproject_fifo_w320_d4096_A_ram
+#(parameter
+    MEM_STYLE   = "auto",
+    DATA_WIDTH  = 320,
+    ADDR_WIDTH  = 12,
+    DEPTH       = 4096)
+(
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  we,
+    input  wire [ADDR_WIDTH-1:0] waddr,
+    input  wire [DATA_WIDTH-1:0] din,
+    input  wire [ADDR_WIDTH-1:0] raddr,
+    input  wire                  rden,
+    output wire [DATA_WIDTH-1:0] dout
+);
+
+    (* ram_style = MEM_STYLE *)
+    reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+    reg  [DATA_WIDTH-1:0] mem_reg;
+
+    always @(posedge clk) begin
+        if (we)
+            mem[waddr] <= din;
+    end
+
+    always @(posedge clk) begin
+        if (reset)
+            mem_reg <= 0;
+        else if (rden)
+            mem_reg <= mem[raddr];
+    end
+    
+    assign dout = mem_reg;
+
+endmodule

myproject_prj/solution1/impl/verilog/myproject_fifo_w328_d4096_A.v

@@ -0,0 +1,237 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+//RAW latency 2 
+
+module myproject_fifo_w328_d4096_A
+#(parameter
+    MEM_STYLE    = "auto",
+    DATA_WIDTH   = 328,
+    ADDR_WIDTH   = 12,
+    DEPTH        = 4096)
+(
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+    
+    // read 
+    output wire [ADDR_WIDTH:0]   if_num_data_valid, // for FRP
+    output wire [ADDR_WIDTH:0]   if_fifo_cap,       // for FRP
+
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+localparam 
+    MEM_DEPTH    = DEPTH - 1,
+    MEM_AWIDTH   = clog2(MEM_DEPTH);
+//------------------------Local signal-------------------
+    reg  [MEM_AWIDTH-1:0] waddr;
+    reg  [MEM_AWIDTH-1:0] raddr;
+    wire [MEM_AWIDTH-1:0] wnext;
+    wire [MEM_AWIDTH-1:0] rnext;
+    wire                  push;
+    wire                  pop;
+    reg  [MEM_AWIDTH:0]   mOutPtr;
+    reg                   empty_n = 1'b0;
+    reg                   full_n = 1'b1;
+    // has num_data_valid? 
+    wire                  num_extra_words;//yes
+    reg  [ADDR_WIDTH:0]   num_data_valid; //yes 
+
+    wire                  pop_dout;
+    reg  [ADDR_WIDTH:0]   num_data_cnt;
+    reg                   dout_vld = 1'b0;
+
+//------------------------Instantiation------------------
+    myproject_fifo_w328_d4096_A_ram 
+    #(  .MEM_STYLE  (MEM_STYLE),
+        .DATA_WIDTH (DATA_WIDTH),
+        .ADDR_WIDTH (MEM_AWIDTH),
+        .DEPTH      (MEM_DEPTH)
+    ) U_myproject_fifo_w328_d4096_A_ram (
+        .clk        (clk),
+        .reset      (reset),
+        .we         (push),
+        .waddr      (waddr),
+        .din        (if_din),
+        .raddr      (raddr),
+        .rden       (pop),
+        .dout       (if_dout)
+    );
+
+//------------------------Task and function--------------
+    function integer clog2;
+        input integer x;
+        integer n, m;
+    begin
+        n = 1;
+        m = 2;
+        while (m < x) begin
+            n = n + 1;
+            m = m * 2;
+        end
+        clog2 = n;
+    end
+    endfunction
+//------------------------Body---------------------------
+    // num_data_valid 
+    assign if_num_data_valid = num_data_valid;
+    assign if_fifo_cap = DEPTH;
+
+    // almost full/empty 
+
+    // program full/empty 
+
+    assign if_full_n  = full_n;
+    assign if_empty_n = dout_vld;
+
+    assign push       = full_n & if_write_ce & if_write;
+    assign pop        = empty_n & (pop_dout | ~dout_vld);
+    assign pop_dout   = dout_vld & if_read_ce & if_read;
+    
+    assign wnext      = !push                    ? waddr :
+                        (waddr == MEM_DEPTH - 1) ? 1'b0  :
+                        waddr + 1'b1;
+    assign rnext      = !pop                     ? raddr :
+                        (raddr == MEM_DEPTH - 1) ? 1'b0  :
+                        raddr + 1'b1;
+
+    // waddr
+    always @(posedge clk) begin
+        if (reset)
+            waddr <= {MEM_AWIDTH{1'b0}};
+        else
+            waddr <= wnext;
+    end
+
+    // raddr
+    always @(posedge clk) begin
+        if (reset)
+            raddr <= {MEM_AWIDTH{1'b0}};
+        else
+            raddr <= rnext;
+    end
+
+    // mOutPtr
+    always @(posedge clk) begin
+        if (reset)
+            mOutPtr <= {MEM_AWIDTH+1{1'b0}};
+        else if (push & ~pop)
+            mOutPtr <= mOutPtr + 1'b1;
+        else if (~push & pop)
+            mOutPtr <= mOutPtr - 1'b1;
+    end
+
+    // full_n 
+    always @(posedge clk) begin
+        if (reset)
+            full_n <= 1'b1;
+        else if ((push & ~pop_dout) && (num_data_cnt == DEPTH - 1))
+            full_n <= 1'b0;
+        else if (~push & pop_dout)
+            full_n <= 1'b1;
+    end
+
+    // empty_n
+    always @(posedge clk) begin
+        if (reset)
+            empty_n <= 1'b0;
+        else if (push & ~pop)
+            empty_n <= 1'b1;
+        else if ((~push & pop) && (mOutPtr == 1))
+            empty_n <= 1'b0;
+    end
+
+    // almost_full_n 
+
+    // almost_empty_n 
+
+    // prog_full_n 
+
+    // prog_empty_n 
+
+    // num_data_cnt
+    always @(posedge clk) begin
+        if (reset)
+            num_data_cnt <= {ADDR_WIDTH+1{1'b0}};
+        else if ( push & ~pop_dout)
+            num_data_cnt <= num_data_cnt + 1'b1;
+        else if (~push & pop_dout)
+            num_data_cnt <= num_data_cnt - 1'b1;
+    end
+
+    // num_data_valid 
+    assign num_extra_words = (dout_vld & ~pop_dout) ? 1 : 0;
+                             
+    always @(posedge clk) begin
+        if (reset)
+            num_data_valid <= {ADDR_WIDTH+1{1'b0}};
+        else if (empty_n | (dout_vld & ~pop_dout))
+            num_data_valid <= push + mOutPtr + num_extra_words;
+        else
+            num_data_valid <= num_extra_words;
+    end // 
+
+    // dout_vld
+    always @(posedge clk) begin
+        if (reset)
+            dout_vld <= 1'b0;
+        else if (pop)
+            dout_vld <= 1'b1;
+        else if (pop_dout)
+            dout_vld <= 1'b0;
+    end
+
+endmodule
+
+
+module myproject_fifo_w328_d4096_A_ram
+#(parameter
+    MEM_STYLE   = "auto",
+    DATA_WIDTH  = 328,
+    ADDR_WIDTH  = 12,
+    DEPTH       = 4096)
+(
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  we,
+    input  wire [ADDR_WIDTH-1:0] waddr,
+    input  wire [DATA_WIDTH-1:0] din,
+    input  wire [ADDR_WIDTH-1:0] raddr,
+    input  wire                  rden,
+    output wire [DATA_WIDTH-1:0] dout
+);
+
+    (* ram_style = MEM_STYLE *)
+    reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+    reg  [DATA_WIDTH-1:0] mem_reg;
+
+    always @(posedge clk) begin
+        if (we)
+            mem[waddr] <= din;
+    end
+
+    always @(posedge clk) begin
+        if (reset)
+            mem_reg <= 0;
+        else if (rden)
+            mem_reg <= mem[raddr];
+    end
+    
+    assign dout = mem_reg;
+
+endmodule

myproject_prj/solution1/impl/verilog/myproject_fifo_w36_d4096_A.v

@@ -0,0 +1,237 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+//RAW latency 2 
+
+module myproject_fifo_w36_d4096_A
+#(parameter
+    MEM_STYLE    = "auto",
+    DATA_WIDTH   = 36,
+    ADDR_WIDTH   = 12,
+    DEPTH        = 4096)
+(
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+    
+    // read 
+    output wire [ADDR_WIDTH:0]   if_num_data_valid, // for FRP
+    output wire [ADDR_WIDTH:0]   if_fifo_cap,       // for FRP
+
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+localparam 
+    MEM_DEPTH    = DEPTH - 1,
+    MEM_AWIDTH   = clog2(MEM_DEPTH);
+//------------------------Local signal-------------------
+    reg  [MEM_AWIDTH-1:0] waddr;
+    reg  [MEM_AWIDTH-1:0] raddr;
+    wire [MEM_AWIDTH-1:0] wnext;
+    wire [MEM_AWIDTH-1:0] rnext;
+    wire                  push;
+    wire                  pop;
+    reg  [MEM_AWIDTH:0]   mOutPtr;
+    reg                   empty_n = 1'b0;
+    reg                   full_n = 1'b1;
+    // has num_data_valid? 
+    wire                  num_extra_words;//yes
+    reg  [ADDR_WIDTH:0]   num_data_valid; //yes 
+
+    wire                  pop_dout;
+    reg  [ADDR_WIDTH:0]   num_data_cnt;
+    reg                   dout_vld = 1'b0;
+
+//------------------------Instantiation------------------
+    myproject_fifo_w36_d4096_A_ram 
+    #(  .MEM_STYLE  (MEM_STYLE),
+        .DATA_WIDTH (DATA_WIDTH),
+        .ADDR_WIDTH (MEM_AWIDTH),
+        .DEPTH      (MEM_DEPTH)
+    ) U_myproject_fifo_w36_d4096_A_ram (
+        .clk        (clk),
+        .reset      (reset),
+        .we         (push),
+        .waddr      (waddr),
+        .din        (if_din),
+        .raddr      (raddr),
+        .rden       (pop),
+        .dout       (if_dout)
+    );
+
+//------------------------Task and function--------------
+    function integer clog2;
+        input integer x;
+        integer n, m;
+    begin
+        n = 1;
+        m = 2;
+        while (m < x) begin
+            n = n + 1;
+            m = m * 2;
+        end
+        clog2 = n;
+    end
+    endfunction
+//------------------------Body---------------------------
+    // num_data_valid 
+    assign if_num_data_valid = num_data_valid;
+    assign if_fifo_cap = DEPTH;
+
+    // almost full/empty 
+
+    // program full/empty 
+
+    assign if_full_n  = full_n;
+    assign if_empty_n = dout_vld;
+
+    assign push       = full_n & if_write_ce & if_write;
+    assign pop        = empty_n & (pop_dout | ~dout_vld);
+    assign pop_dout   = dout_vld & if_read_ce & if_read;
+    
+    assign wnext      = !push                    ? waddr :
+                        (waddr == MEM_DEPTH - 1) ? 1'b0  :
+                        waddr + 1'b1;
+    assign rnext      = !pop                     ? raddr :
+                        (raddr == MEM_DEPTH - 1) ? 1'b0  :
+                        raddr + 1'b1;
+
+    // waddr
+    always @(posedge clk) begin
+        if (reset)
+            waddr <= {MEM_AWIDTH{1'b0}};
+        else
+            waddr <= wnext;
+    end
+
+    // raddr
+    always @(posedge clk) begin
+        if (reset)
+            raddr <= {MEM_AWIDTH{1'b0}};
+        else
+            raddr <= rnext;
+    end
+
+    // mOutPtr
+    always @(posedge clk) begin
+        if (reset)
+            mOutPtr <= {MEM_AWIDTH+1{1'b0}};
+        else if (push & ~pop)
+            mOutPtr <= mOutPtr + 1'b1;
+        else if (~push & pop)
+            mOutPtr <= mOutPtr - 1'b1;
+    end
+
+    // full_n 
+    always @(posedge clk) begin
+        if (reset)
+            full_n <= 1'b1;
+        else if ((push & ~pop_dout) && (num_data_cnt == DEPTH - 1))
+            full_n <= 1'b0;
+        else if (~push & pop_dout)
+            full_n <= 1'b1;
+    end
+
+    // empty_n
+    always @(posedge clk) begin
+        if (reset)
+            empty_n <= 1'b0;
+        else if (push & ~pop)
+            empty_n <= 1'b1;
+        else if ((~push & pop) && (mOutPtr == 1))
+            empty_n <= 1'b0;
+    end
+
+    // almost_full_n 
+
+    // almost_empty_n 
+
+    // prog_full_n 
+
+    // prog_empty_n 
+
+    // num_data_cnt
+    always @(posedge clk) begin
+        if (reset)
+            num_data_cnt <= {ADDR_WIDTH+1{1'b0}};
+        else if ( push & ~pop_dout)
+            num_data_cnt <= num_data_cnt + 1'b1;
+        else if (~push & pop_dout)
+            num_data_cnt <= num_data_cnt - 1'b1;
+    end
+
+    // num_data_valid 
+    assign num_extra_words = (dout_vld & ~pop_dout) ? 1 : 0;
+                             
+    always @(posedge clk) begin
+        if (reset)
+            num_data_valid <= {ADDR_WIDTH+1{1'b0}};
+        else if (empty_n | (dout_vld & ~pop_dout))
+            num_data_valid <= push + mOutPtr + num_extra_words;
+        else
+            num_data_valid <= num_extra_words;
+    end // 
+
+    // dout_vld
+    always @(posedge clk) begin
+        if (reset)
+            dout_vld <= 1'b0;
+        else if (pop)
+            dout_vld <= 1'b1;
+        else if (pop_dout)
+            dout_vld <= 1'b0;
+    end
+
+endmodule
+
+
+module myproject_fifo_w36_d4096_A_ram
+#(parameter
+    MEM_STYLE   = "auto",
+    DATA_WIDTH  = 36,
+    ADDR_WIDTH  = 12,
+    DEPTH       = 4096)
+(
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  we,
+    input  wire [ADDR_WIDTH-1:0] waddr,
+    input  wire [DATA_WIDTH-1:0] din,
+    input  wire [ADDR_WIDTH-1:0] raddr,
+    input  wire                  rden,
+    output wire [DATA_WIDTH-1:0] dout
+);
+
+    (* ram_style = MEM_STYLE *)
+    reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+    reg  [DATA_WIDTH-1:0] mem_reg;
+
+    always @(posedge clk) begin
+        if (we)
+            mem[waddr] <= din;
+    end
+
+    always @(posedge clk) begin
+        if (reset)
+            mem_reg <= 0;
+        else if (rden)
+            mem_reg <= mem[raddr];
+    end
+    
+    assign dout = mem_reg;
+
+endmodule

myproject_prj/solution1/impl/verilog/myproject_fifo_w384_d4096_A.v

@@ -0,0 +1,237 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+//RAW latency 2 
+
+module myproject_fifo_w384_d4096_A
+#(parameter
+    MEM_STYLE    = "auto",
+    DATA_WIDTH   = 384,
+    ADDR_WIDTH   = 12,
+    DEPTH        = 4096)
+(
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+    
+    // read 
+    output wire [ADDR_WIDTH:0]   if_num_data_valid, // for FRP
+    output wire [ADDR_WIDTH:0]   if_fifo_cap,       // for FRP
+
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+localparam 
+    MEM_DEPTH    = DEPTH - 1,
+    MEM_AWIDTH   = clog2(MEM_DEPTH);
+//------------------------Local signal-------------------
+    reg  [MEM_AWIDTH-1:0] waddr;
+    reg  [MEM_AWIDTH-1:0] raddr;
+    wire [MEM_AWIDTH-1:0] wnext;
+    wire [MEM_AWIDTH-1:0] rnext;
+    wire                  push;
+    wire                  pop;
+    reg  [MEM_AWIDTH:0]   mOutPtr;
+    reg                   empty_n = 1'b0;
+    reg                   full_n = 1'b1;
+    // has num_data_valid? 
+    wire                  num_extra_words;//yes
+    reg  [ADDR_WIDTH:0]   num_data_valid; //yes 
+
+    wire                  pop_dout;
+    reg  [ADDR_WIDTH:0]   num_data_cnt;
+    reg                   dout_vld = 1'b0;
+
+//------------------------Instantiation------------------
+    myproject_fifo_w384_d4096_A_ram 
+    #(  .MEM_STYLE  (MEM_STYLE),
+        .DATA_WIDTH (DATA_WIDTH),
+        .ADDR_WIDTH (MEM_AWIDTH),
+        .DEPTH      (MEM_DEPTH)
+    ) U_myproject_fifo_w384_d4096_A_ram (
+        .clk        (clk),
+        .reset      (reset),
+        .we         (push),
+        .waddr      (waddr),
+        .din        (if_din),
+        .raddr      (raddr),
+        .rden       (pop),
+        .dout       (if_dout)
+    );
+
+//------------------------Task and function--------------
+    function integer clog2;
+        input integer x;
+        integer n, m;
+    begin
+        n = 1;
+        m = 2;
+        while (m < x) begin
+            n = n + 1;
+            m = m * 2;
+        end
+        clog2 = n;
+    end
+    endfunction
+//------------------------Body---------------------------
+    // num_data_valid 
+    assign if_num_data_valid = num_data_valid;
+    assign if_fifo_cap = DEPTH;
+
+    // almost full/empty 
+
+    // program full/empty 
+
+    assign if_full_n  = full_n;
+    assign if_empty_n = dout_vld;
+
+    assign push       = full_n & if_write_ce & if_write;
+    assign pop        = empty_n & (pop_dout | ~dout_vld);
+    assign pop_dout   = dout_vld & if_read_ce & if_read;
+    
+    assign wnext      = !push                    ? waddr :
+                        (waddr == MEM_DEPTH - 1) ? 1'b0  :
+                        waddr + 1'b1;
+    assign rnext      = !pop                     ? raddr :
+                        (raddr == MEM_DEPTH - 1) ? 1'b0  :
+                        raddr + 1'b1;
+
+    // waddr
+    always @(posedge clk) begin
+        if (reset)
+            waddr <= {MEM_AWIDTH{1'b0}};
+        else
+            waddr <= wnext;
+    end
+
+    // raddr
+    always @(posedge clk) begin
+        if (reset)
+            raddr <= {MEM_AWIDTH{1'b0}};
+        else
+            raddr <= rnext;
+    end
+
+    // mOutPtr
+    always @(posedge clk) begin
+        if (reset)
+            mOutPtr <= {MEM_AWIDTH+1{1'b0}};
+        else if (push & ~pop)
+            mOutPtr <= mOutPtr + 1'b1;
+        else if (~push & pop)
+            mOutPtr <= mOutPtr - 1'b1;
+    end
+
+    // full_n 
+    always @(posedge clk) begin
+        if (reset)
+            full_n <= 1'b1;
+        else if ((push & ~pop_dout) && (num_data_cnt == DEPTH - 1))
+            full_n <= 1'b0;
+        else if (~push & pop_dout)
+            full_n <= 1'b1;
+    end
+
+    // empty_n
+    always @(posedge clk) begin
+        if (reset)
+            empty_n <= 1'b0;
+        else if (push & ~pop)
+            empty_n <= 1'b1;
+        else if ((~push & pop) && (mOutPtr == 1))
+            empty_n <= 1'b0;
+    end
+
+    // almost_full_n 
+
+    // almost_empty_n 
+
+    // prog_full_n 
+
+    // prog_empty_n 
+
+    // num_data_cnt
+    always @(posedge clk) begin
+        if (reset)
+            num_data_cnt <= {ADDR_WIDTH+1{1'b0}};
+        else if ( push & ~pop_dout)
+            num_data_cnt <= num_data_cnt + 1'b1;
+        else if (~push & pop_dout)
+            num_data_cnt <= num_data_cnt - 1'b1;
+    end
+
+    // num_data_valid 
+    assign num_extra_words = (dout_vld & ~pop_dout) ? 1 : 0;
+                             
+    always @(posedge clk) begin
+        if (reset)
+            num_data_valid <= {ADDR_WIDTH+1{1'b0}};
+        else if (empty_n | (dout_vld & ~pop_dout))
+            num_data_valid <= push + mOutPtr + num_extra_words;
+        else
+            num_data_valid <= num_extra_words;
+    end // 
+
+    // dout_vld
+    always @(posedge clk) begin
+        if (reset)
+            dout_vld <= 1'b0;
+        else if (pop)
+            dout_vld <= 1'b1;
+        else if (pop_dout)
+            dout_vld <= 1'b0;
+    end
+
+endmodule
+
+
+module myproject_fifo_w384_d4096_A_ram
+#(parameter
+    MEM_STYLE   = "auto",
+    DATA_WIDTH  = 384,
+    ADDR_WIDTH  = 12,
+    DEPTH       = 4096)
+(
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  we,
+    input  wire [ADDR_WIDTH-1:0] waddr,
+    input  wire [DATA_WIDTH-1:0] din,
+    input  wire [ADDR_WIDTH-1:0] raddr,
+    input  wire                  rden,
+    output wire [DATA_WIDTH-1:0] dout
+);
+
+    (* ram_style = MEM_STYLE *)
+    reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+    reg  [DATA_WIDTH-1:0] mem_reg;
+
+    always @(posedge clk) begin
+        if (we)
+            mem[waddr] <= din;
+    end
+
+    always @(posedge clk) begin
+        if (reset)
+            mem_reg <= 0;
+        else if (rden)
+            mem_reg <= mem[raddr];
+    end
+    
+    assign dout = mem_reg;
+
+endmodule

myproject_prj/solution1/impl/verilog/myproject_fifo_w512_d256_A.v

@@ -0,0 +1,237 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+//RAW latency 2 
+
+module myproject_fifo_w512_d256_A
+#(parameter
+    MEM_STYLE    = "auto",
+    DATA_WIDTH   = 512,
+    ADDR_WIDTH   = 8,
+    DEPTH        = 256)
+(
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+    
+    // read 
+    output wire [ADDR_WIDTH:0]   if_num_data_valid, // for FRP
+    output wire [ADDR_WIDTH:0]   if_fifo_cap,       // for FRP
+
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+localparam 
+    MEM_DEPTH    = DEPTH - 1,
+    MEM_AWIDTH   = clog2(MEM_DEPTH);
+//------------------------Local signal-------------------
+    reg  [MEM_AWIDTH-1:0] waddr;
+    reg  [MEM_AWIDTH-1:0] raddr;
+    wire [MEM_AWIDTH-1:0] wnext;
+    wire [MEM_AWIDTH-1:0] rnext;
+    wire                  push;
+    wire                  pop;
+    reg  [MEM_AWIDTH:0]   mOutPtr;
+    reg                   empty_n = 1'b0;
+    reg                   full_n = 1'b1;
+    // has num_data_valid? 
+    wire                  num_extra_words;//yes
+    reg  [ADDR_WIDTH:0]   num_data_valid; //yes 
+
+    wire                  pop_dout;
+    reg  [ADDR_WIDTH:0]   num_data_cnt;
+    reg                   dout_vld = 1'b0;
+
+//------------------------Instantiation------------------
+    myproject_fifo_w512_d256_A_ram 
+    #(  .MEM_STYLE  (MEM_STYLE),
+        .DATA_WIDTH (DATA_WIDTH),
+        .ADDR_WIDTH (MEM_AWIDTH),
+        .DEPTH      (MEM_DEPTH)
+    ) U_myproject_fifo_w512_d256_A_ram (
+        .clk        (clk),
+        .reset      (reset),
+        .we         (push),
+        .waddr      (waddr),
+        .din        (if_din),
+        .raddr      (raddr),
+        .rden       (pop),
+        .dout       (if_dout)
+    );
+
+//------------------------Task and function--------------
+    function integer clog2;
+        input integer x;
+        integer n, m;
+    begin
+        n = 1;
+        m = 2;
+        while (m < x) begin
+            n = n + 1;
+            m = m * 2;
+        end
+        clog2 = n;
+    end
+    endfunction
+//------------------------Body---------------------------
+    // num_data_valid 
+    assign if_num_data_valid = num_data_valid;
+    assign if_fifo_cap = DEPTH;
+
+    // almost full/empty 
+
+    // program full/empty 
+
+    assign if_full_n  = full_n;
+    assign if_empty_n = dout_vld;
+
+    assign push       = full_n & if_write_ce & if_write;
+    assign pop        = empty_n & (pop_dout | ~dout_vld);
+    assign pop_dout   = dout_vld & if_read_ce & if_read;
+    
+    assign wnext      = !push                    ? waddr :
+                        (waddr == MEM_DEPTH - 1) ? 1'b0  :
+                        waddr + 1'b1;
+    assign rnext      = !pop                     ? raddr :
+                        (raddr == MEM_DEPTH - 1) ? 1'b0  :
+                        raddr + 1'b1;
+
+    // waddr
+    always @(posedge clk) begin
+        if (reset)
+            waddr <= {MEM_AWIDTH{1'b0}};
+        else
+            waddr <= wnext;
+    end
+
+    // raddr
+    always @(posedge clk) begin
+        if (reset)
+            raddr <= {MEM_AWIDTH{1'b0}};
+        else
+            raddr <= rnext;
+    end
+
+    // mOutPtr
+    always @(posedge clk) begin
+        if (reset)
+            mOutPtr <= {MEM_AWIDTH+1{1'b0}};
+        else if (push & ~pop)
+            mOutPtr <= mOutPtr + 1'b1;
+        else if (~push & pop)
+            mOutPtr <= mOutPtr - 1'b1;
+    end
+
+    // full_n 
+    always @(posedge clk) begin
+        if (reset)
+            full_n <= 1'b1;
+        else if ((push & ~pop_dout) && (num_data_cnt == DEPTH - 1))
+            full_n <= 1'b0;
+        else if (~push & pop_dout)
+            full_n <= 1'b1;
+    end
+
+    // empty_n
+    always @(posedge clk) begin
+        if (reset)
+            empty_n <= 1'b0;
+        else if (push & ~pop)
+            empty_n <= 1'b1;
+        else if ((~push & pop) && (mOutPtr == 1))
+            empty_n <= 1'b0;
+    end
+
+    // almost_full_n 
+
+    // almost_empty_n 
+
+    // prog_full_n 
+
+    // prog_empty_n 
+
+    // num_data_cnt
+    always @(posedge clk) begin
+        if (reset)
+            num_data_cnt <= {ADDR_WIDTH+1{1'b0}};
+        else if ( push & ~pop_dout)
+            num_data_cnt <= num_data_cnt + 1'b1;
+        else if (~push & pop_dout)
+            num_data_cnt <= num_data_cnt - 1'b1;
+    end
+
+    // num_data_valid 
+    assign num_extra_words = (dout_vld & ~pop_dout) ? 1 : 0;
+                             
+    always @(posedge clk) begin
+        if (reset)
+            num_data_valid <= {ADDR_WIDTH+1{1'b0}};
+        else if (empty_n | (dout_vld & ~pop_dout))
+            num_data_valid <= push + mOutPtr + num_extra_words;
+        else
+            num_data_valid <= num_extra_words;
+    end // 
+
+    // dout_vld
+    always @(posedge clk) begin
+        if (reset)
+            dout_vld <= 1'b0;
+        else if (pop)
+            dout_vld <= 1'b1;
+        else if (pop_dout)
+            dout_vld <= 1'b0;
+    end
+
+endmodule
+
+
+module myproject_fifo_w512_d256_A_ram
+#(parameter
+    MEM_STYLE   = "auto",
+    DATA_WIDTH  = 512,
+    ADDR_WIDTH  = 8,
+    DEPTH       = 256)
+(
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  we,
+    input  wire [ADDR_WIDTH-1:0] waddr,
+    input  wire [DATA_WIDTH-1:0] din,
+    input  wire [ADDR_WIDTH-1:0] raddr,
+    input  wire                  rden,
+    output wire [DATA_WIDTH-1:0] dout
+);
+
+    (* ram_style = MEM_STYLE *)
+    reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+    reg  [DATA_WIDTH-1:0] mem_reg;
+
+    always @(posedge clk) begin
+        if (we)
+            mem[waddr] <= din;
+    end
+
+    always @(posedge clk) begin
+        if (reset)
+            mem_reg <= 0;
+        else if (rden)
+            mem_reg <= mem[raddr];
+    end
+    
+    assign dout = mem_reg;
+
+endmodule

myproject_prj/solution1/impl/verilog/myproject_fifo_w768_d1024_A.v

@@ -0,0 +1,237 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+//RAW latency 2 
+
+module myproject_fifo_w768_d1024_A
+#(parameter
+    MEM_STYLE    = "auto",
+    DATA_WIDTH   = 768,
+    ADDR_WIDTH   = 10,
+    DEPTH        = 1024)
+(
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+    
+    // read 
+    output wire [ADDR_WIDTH:0]   if_num_data_valid, // for FRP
+    output wire [ADDR_WIDTH:0]   if_fifo_cap,       // for FRP
+
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+localparam 
+    MEM_DEPTH    = DEPTH - 1,
+    MEM_AWIDTH   = clog2(MEM_DEPTH);
+//------------------------Local signal-------------------
+    reg  [MEM_AWIDTH-1:0] waddr;
+    reg  [MEM_AWIDTH-1:0] raddr;
+    wire [MEM_AWIDTH-1:0] wnext;
+    wire [MEM_AWIDTH-1:0] rnext;
+    wire                  push;
+    wire                  pop;
+    reg  [MEM_AWIDTH:0]   mOutPtr;
+    reg                   empty_n = 1'b0;
+    reg                   full_n = 1'b1;
+    // has num_data_valid? 
+    wire                  num_extra_words;//yes
+    reg  [ADDR_WIDTH:0]   num_data_valid; //yes 
+
+    wire                  pop_dout;
+    reg  [ADDR_WIDTH:0]   num_data_cnt;
+    reg                   dout_vld = 1'b0;
+
+//------------------------Instantiation------------------
+    myproject_fifo_w768_d1024_A_ram 
+    #(  .MEM_STYLE  (MEM_STYLE),
+        .DATA_WIDTH (DATA_WIDTH),
+        .ADDR_WIDTH (MEM_AWIDTH),
+        .DEPTH      (MEM_DEPTH)
+    ) U_myproject_fifo_w768_d1024_A_ram (
+        .clk        (clk),
+        .reset      (reset),
+        .we         (push),
+        .waddr      (waddr),
+        .din        (if_din),
+        .raddr      (raddr),
+        .rden       (pop),
+        .dout       (if_dout)
+    );
+
+//------------------------Task and function--------------
+    function integer clog2;
+        input integer x;
+        integer n, m;
+    begin
+        n = 1;
+        m = 2;
+        while (m < x) begin
+            n = n + 1;
+            m = m * 2;
+        end
+        clog2 = n;
+    end
+    endfunction
+//------------------------Body---------------------------
+    // num_data_valid 
+    assign if_num_data_valid = num_data_valid;
+    assign if_fifo_cap = DEPTH;
+
+    // almost full/empty 
+
+    // program full/empty 
+
+    assign if_full_n  = full_n;
+    assign if_empty_n = dout_vld;
+
+    assign push       = full_n & if_write_ce & if_write;
+    assign pop        = empty_n & (pop_dout | ~dout_vld);
+    assign pop_dout   = dout_vld & if_read_ce & if_read;
+    
+    assign wnext      = !push                    ? waddr :
+                        (waddr == MEM_DEPTH - 1) ? 1'b0  :
+                        waddr + 1'b1;
+    assign rnext      = !pop                     ? raddr :
+                        (raddr == MEM_DEPTH - 1) ? 1'b0  :
+                        raddr + 1'b1;
+
+    // waddr
+    always @(posedge clk) begin
+        if (reset)
+            waddr <= {MEM_AWIDTH{1'b0}};
+        else
+            waddr <= wnext;
+    end
+
+    // raddr
+    always @(posedge clk) begin
+        if (reset)
+            raddr <= {MEM_AWIDTH{1'b0}};
+        else
+            raddr <= rnext;
+    end
+
+    // mOutPtr
+    always @(posedge clk) begin
+        if (reset)
+            mOutPtr <= {MEM_AWIDTH+1{1'b0}};
+        else if (push & ~pop)
+            mOutPtr <= mOutPtr + 1'b1;
+        else if (~push & pop)
+            mOutPtr <= mOutPtr - 1'b1;
+    end
+
+    // full_n 
+    always @(posedge clk) begin
+        if (reset)
+            full_n <= 1'b1;
+        else if ((push & ~pop_dout) && (num_data_cnt == DEPTH - 1))
+            full_n <= 1'b0;
+        else if (~push & pop_dout)
+            full_n <= 1'b1;
+    end
+
+    // empty_n
+    always @(posedge clk) begin
+        if (reset)
+            empty_n <= 1'b0;
+        else if (push & ~pop)
+            empty_n <= 1'b1;
+        else if ((~push & pop) && (mOutPtr == 1))
+            empty_n <= 1'b0;
+    end
+
+    // almost_full_n 
+
+    // almost_empty_n 
+
+    // prog_full_n 
+
+    // prog_empty_n 
+
+    // num_data_cnt
+    always @(posedge clk) begin
+        if (reset)
+            num_data_cnt <= {ADDR_WIDTH+1{1'b0}};
+        else if ( push & ~pop_dout)
+            num_data_cnt <= num_data_cnt + 1'b1;
+        else if (~push & pop_dout)
+            num_data_cnt <= num_data_cnt - 1'b1;
+    end
+
+    // num_data_valid 
+    assign num_extra_words = (dout_vld & ~pop_dout) ? 1 : 0;
+                             
+    always @(posedge clk) begin
+        if (reset)
+            num_data_valid <= {ADDR_WIDTH+1{1'b0}};
+        else if (empty_n | (dout_vld & ~pop_dout))
+            num_data_valid <= push + mOutPtr + num_extra_words;
+        else
+            num_data_valid <= num_extra_words;
+    end // 
+
+    // dout_vld
+    always @(posedge clk) begin
+        if (reset)
+            dout_vld <= 1'b0;
+        else if (pop)
+            dout_vld <= 1'b1;
+        else if (pop_dout)
+            dout_vld <= 1'b0;
+    end
+
+endmodule
+
+
+module myproject_fifo_w768_d1024_A_ram
+#(parameter
+    MEM_STYLE   = "auto",
+    DATA_WIDTH  = 768,
+    ADDR_WIDTH  = 10,
+    DEPTH       = 1024)
+(
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire                  we,
+    input  wire [ADDR_WIDTH-1:0] waddr,
+    input  wire [DATA_WIDTH-1:0] din,
+    input  wire [ADDR_WIDTH-1:0] raddr,
+    input  wire                  rden,
+    output wire [DATA_WIDTH-1:0] dout
+);
+
+    (* ram_style = MEM_STYLE *)
+    reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
+    reg  [DATA_WIDTH-1:0] mem_reg;
+
+    always @(posedge clk) begin
+        if (we)
+            mem[waddr] <= din;
+    end
+
+    always @(posedge clk) begin
+        if (reset)
+            mem_reg <= 0;
+        else if (rden)
+            mem_reg <= mem[raddr];
+    end
+    
+    assign dout = mem_reg;
+
+endmodule

myproject_prj/solution1/impl/verilog/myproject_flow_control_loop_pipe_no_ap_cont.v

@@ -0,0 +1,104 @@
+// ==============================================================
+// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2024.1 (64-bit)
+// Tool Version Limit: 2024.05
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// 
+// ==============================================================
+
+`timescale 1 ns / 1 ps
+
+module myproject_flow_control_loop_pipe_no_ap_cont(
+        ap_clk,
+        ap_rst,
+        ap_start,
+        ap_ready,
+        ap_done,
+        ap_start_int,
+        ap_ready_int,
+        ap_done_int,
+        ap_continue_int,
+        ap_loop_init,
+        ap_loop_exit_ready,
+        ap_loop_exit_done
+);
+
+input   ap_clk;
+input   ap_rst;
+
+//Block level handshake with outside loop
+input   ap_start;
+output  ap_ready;
+output  ap_done;
+
+//Block level handshake with loop body
+output  ap_start_int;
+input   ap_ready_int;
+input   ap_done_int;
+output  ap_continue_int;
+
+//Init live in variables
+output   ap_loop_init;
+reg ap_loop_init;
+reg ap_done;
+reg ap_done_cache;
+
+//Exit signal from loop body
+input   ap_loop_exit_ready;
+input   ap_loop_exit_done;
+
+// power-on initialization
+initial begin
+#0 ap_loop_init = 1'b1;
+#0 ap_done_cache = 1'b0;
+end
+
+assign ap_start_int = ap_start;
+
+assign ap_continue_int = 1'b1;
+
+assign ap_ready = ap_loop_exit_ready;
+
+//ap_loop_init is valid for the first II
+//of the first loop run so as to enable
+//the init block ops which are pushed into
+//the first state of the pipeline region
+always @ (posedge ap_clk)
+begin
+    if (ap_rst == 1'b1) begin
+        ap_loop_init <= 1'b1;
+    end else if(ap_loop_exit_ready == 1'b1) begin
+        ap_loop_init <= 1'b1;
+    end else if(ap_ready_int == 1'b1) begin
+        ap_loop_init <= 1'b0;
+    end
+end
+
+// if no ap_continue port and current module is not top module, 
+// ap_done handshakes with ap_start. Internally, flow control sends out 
+// ap_conintue_int = 1'b1 so the ap_done_int is asserted high for 1 clock cycle.
+// ap_done_cache is used to record ap_done_int, and de-assert if ap_start_int
+// is asserted, so DUT can start the next run
+always @(posedge ap_clk)
+begin
+    if (ap_rst == 1'b1) begin
+        ap_done_cache <= 1'b0;
+    end else if (ap_done_int == 1'b1) begin
+        ap_done_cache <= 1'b1;
+    end else if (ap_start_int == 1'b1) begin
+        ap_done_cache <= 1'b0;
+    end
+end
+
+// if no ap_continue port and current module is not top module, ap_done handshakes with ap_start
+always @(*)
+begin
+    if ((ap_done_int == 1'b1) || ((ap_done_cache == 1'b1) && (ap_start_int == 1'b0))) begin
+        ap_done = 1'b1;
+    end else begin
+        ap_done = 1'b0;
+    end
+end
+
+endmodule
+        

myproject_prj/solution1/impl/verilog/myproject_mac_muladd_16s_10s_33s_33_1_1.v

@@ -0,0 +1,66 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+//   
+//   
+//   
+`timescale 1 ns / 1 ps
+// 
+module myproject_mac_muladd_16s_10s_33s_33_1_1_DSP48_0(
+    input  [16 - 1:0] in0,
+    input  [10 - 1:0] in1,
+    input  [33 - 1:0] in2,
+    output [33 - 1:0]  dout);
+
+wire signed [27 - 1:0]     a;
+wire signed [18 - 1:0]     b;
+wire signed [48 - 1:0]     c;
+wire signed [45 - 1:0]     m;
+wire signed [48 - 1:0]     p;
+
+assign a  = $signed(in0);
+assign b  = $signed(in1);
+assign c  = $signed(in2);
+
+assign m  = a * b;
+// 
+assign p  = m + c;
+// 
+assign dout = p;
+
+endmodule
+// 
+
+module myproject_mac_muladd_16s_10s_33s_33_1_1(
+// 
+    din0,
+    din1,
+    din2,
+    dout);
+
+parameter ID = 32'd1;
+parameter NUM_STAGE = 32'd1;
+parameter din0_WIDTH = 32'd1;
+parameter din1_WIDTH = 32'd1;
+parameter din2_WIDTH = 32'd1;
+parameter dout_WIDTH = 32'd1;
+// 
+input[din0_WIDTH - 1:0] din0;
+input[din1_WIDTH - 1:0] din1;
+input[din2_WIDTH - 1:0] din2;
+output[dout_WIDTH - 1:0] dout;
+
+
+myproject_mac_muladd_16s_10s_33s_33_1_1_DSP48_0 myproject_mac_muladd_16s_10s_33s_33_1_1_DSP48_0_U(
+// 
+    .in0( din0 ),
+    .in1( din1 ),
+    .in2( din2 ),
+    .dout( dout ));
+
+endmodule
+
+

myproject_prj/solution1/impl/verilog/myproject_mac_muladd_16s_16s_33s_33_1_1.v

@@ -0,0 +1,66 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+//   
+//   
+//   
+`timescale 1 ns / 1 ps
+// 
+module myproject_mac_muladd_16s_16s_33s_33_1_1_DSP48_0(
+    input  [16 - 1:0] in0,
+    input  [16 - 1:0] in1,
+    input  [33 - 1:0] in2,
+    output [33 - 1:0]  dout);
+
+wire signed [27 - 1:0]     a;
+wire signed [18 - 1:0]     b;
+wire signed [48 - 1:0]     c;
+wire signed [45 - 1:0]     m;
+wire signed [48 - 1:0]     p;
+
+assign a  = $signed(in0);
+assign b  = $signed(in1);
+assign c  = $signed(in2);
+
+assign m  = a * b;
+// 
+assign p  = m + c;
+// 
+assign dout = p;
+
+endmodule
+// 
+
+module myproject_mac_muladd_16s_16s_33s_33_1_1(
+// 
+    din0,
+    din1,
+    din2,
+    dout);
+
+parameter ID = 32'd1;
+parameter NUM_STAGE = 32'd1;
+parameter din0_WIDTH = 32'd1;
+parameter din1_WIDTH = 32'd1;
+parameter din2_WIDTH = 32'd1;
+parameter dout_WIDTH = 32'd1;
+// 
+input[din0_WIDTH - 1:0] din0;
+input[din1_WIDTH - 1:0] din1;
+input[din2_WIDTH - 1:0] din2;
+output[dout_WIDTH - 1:0] dout;
+
+
+myproject_mac_muladd_16s_16s_33s_33_1_1_DSP48_0 myproject_mac_muladd_16s_16s_33s_33_1_1_DSP48_0_U(
+// 
+    .in0( din0 ),
+    .in1( din1 ),
+    .in2( din2 ),
+    .dout( dout ));
+
+endmodule
+
+

myproject_prj/solution1/impl/verilog/myproject_mac_muladd_16s_16s_40s_41_1_1.v

@@ -0,0 +1,66 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+//   
+//   
+//   
+`timescale 1 ns / 1 ps
+// 
+module myproject_mac_muladd_16s_16s_40s_41_1_1_DSP48_0(
+    input  [16 - 1:0] in0,
+    input  [16 - 1:0] in1,
+    input  [40 - 1:0] in2,
+    output [41 - 1:0]  dout);
+
+wire signed [27 - 1:0]     a;
+wire signed [18 - 1:0]     b;
+wire signed [48 - 1:0]     c;
+wire signed [45 - 1:0]     m;
+wire signed [48 - 1:0]     p;
+
+assign a  = $signed(in0);
+assign b  = $signed(in1);
+assign c  = $signed(in2);
+
+assign m  = a * b;
+// 
+assign p  = m + c;
+// 
+assign dout = p;
+
+endmodule
+// 
+
+module myproject_mac_muladd_16s_16s_40s_41_1_1(
+// 
+    din0,
+    din1,
+    din2,
+    dout);
+
+parameter ID = 32'd1;
+parameter NUM_STAGE = 32'd1;
+parameter din0_WIDTH = 32'd1;
+parameter din1_WIDTH = 32'd1;
+parameter din2_WIDTH = 32'd1;
+parameter dout_WIDTH = 32'd1;
+// 
+input[din0_WIDTH - 1:0] din0;
+input[din1_WIDTH - 1:0] din1;
+input[din2_WIDTH - 1:0] din2;
+output[dout_WIDTH - 1:0] dout;
+
+
+myproject_mac_muladd_16s_16s_40s_41_1_1_DSP48_0 myproject_mac_muladd_16s_16s_40s_41_1_1_DSP48_0_U(
+// 
+    .in0( din0 ),
+    .in1( din1 ),
+    .in2( din2 ),
+    .dout( dout ));
+
+endmodule
+
+

myproject_prj/solution1/impl/verilog/myproject_mac_muladd_16s_16s_41s_42_1_1.v

@@ -0,0 +1,66 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+//   
+//   
+//   
+`timescale 1 ns / 1 ps
+// 
+module myproject_mac_muladd_16s_16s_41s_42_1_1_DSP48_0(
+    input  [16 - 1:0] in0,
+    input  [16 - 1:0] in1,
+    input  [41 - 1:0] in2,
+    output [42 - 1:0]  dout);
+
+wire signed [27 - 1:0]     a;
+wire signed [18 - 1:0]     b;
+wire signed [48 - 1:0]     c;
+wire signed [45 - 1:0]     m;
+wire signed [48 - 1:0]     p;
+
+assign a  = $signed(in0);
+assign b  = $signed(in1);
+assign c  = $signed(in2);
+
+assign m  = a * b;
+// 
+assign p  = m + c;
+// 
+assign dout = p;
+
+endmodule
+// 
+
+module myproject_mac_muladd_16s_16s_41s_42_1_1(
+// 
+    din0,
+    din1,
+    din2,
+    dout);
+
+parameter ID = 32'd1;
+parameter NUM_STAGE = 32'd1;
+parameter din0_WIDTH = 32'd1;
+parameter din1_WIDTH = 32'd1;
+parameter din2_WIDTH = 32'd1;
+parameter dout_WIDTH = 32'd1;
+// 
+input[din0_WIDTH - 1:0] din0;
+input[din1_WIDTH - 1:0] din1;
+input[din2_WIDTH - 1:0] din2;
+output[dout_WIDTH - 1:0] dout;
+
+
+myproject_mac_muladd_16s_16s_41s_42_1_1_DSP48_0 myproject_mac_muladd_16s_16s_41s_42_1_1_DSP48_0_U(
+// 
+    .in0( din0 ),
+    .in1( din1 ),
+    .in2( din2 ),
+    .dout( dout ));
+
+endmodule
+
+

myproject_prj/solution1/impl/verilog/myproject_mac_muladd_16s_9s_31s_31_1_1.v

@@ -0,0 +1,66 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+//   
+//   
+//   
+`timescale 1 ns / 1 ps
+// 
+module myproject_mac_muladd_16s_9s_31s_31_1_1_DSP48_0(
+    input  [16 - 1:0] in0,
+    input  [9 - 1:0] in1,
+    input  [31 - 1:0] in2,
+    output [31 - 1:0]  dout);
+
+wire signed [27 - 1:0]     a;
+wire signed [18 - 1:0]     b;
+wire signed [48 - 1:0]     c;
+wire signed [45 - 1:0]     m;
+wire signed [48 - 1:0]     p;
+
+assign a  = $signed(in0);
+assign b  = $signed(in1);
+assign c  = $signed(in2);
+
+assign m  = a * b;
+// 
+assign p  = m + c;
+// 
+assign dout = p;
+
+endmodule
+// 
+
+module myproject_mac_muladd_16s_9s_31s_31_1_1(
+// 
+    din0,
+    din1,
+    din2,
+    dout);
+
+parameter ID = 32'd1;
+parameter NUM_STAGE = 32'd1;
+parameter din0_WIDTH = 32'd1;
+parameter din1_WIDTH = 32'd1;
+parameter din2_WIDTH = 32'd1;
+parameter dout_WIDTH = 32'd1;
+// 
+input[din0_WIDTH - 1:0] din0;
+input[din1_WIDTH - 1:0] din1;
+input[din2_WIDTH - 1:0] din2;
+output[dout_WIDTH - 1:0] dout;
+
+
+myproject_mac_muladd_16s_9s_31s_31_1_1_DSP48_0 myproject_mac_muladd_16s_9s_31s_31_1_1_DSP48_0_U(
+// 
+    .in0( din0 ),
+    .in1( din1 ),
+    .in2( din2 ),
+    .dout( dout ));
+
+endmodule
+
+

myproject_prj/solution1/impl/verilog/myproject_mac_muladd_16s_9s_34s_34_1_1.v

@@ -0,0 +1,66 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+//   
+//   
+//   
+`timescale 1 ns / 1 ps
+// 
+module myproject_mac_muladd_16s_9s_34s_34_1_1_DSP48_0(
+    input  [16 - 1:0] in0,
+    input  [9 - 1:0] in1,
+    input  [34 - 1:0] in2,
+    output [34 - 1:0]  dout);
+
+wire signed [27 - 1:0]     a;
+wire signed [18 - 1:0]     b;
+wire signed [48 - 1:0]     c;
+wire signed [45 - 1:0]     m;
+wire signed [48 - 1:0]     p;
+
+assign a  = $signed(in0);
+assign b  = $signed(in1);
+assign c  = $signed(in2);
+
+assign m  = a * b;
+// 
+assign p  = m + c;
+// 
+assign dout = p;
+
+endmodule
+// 
+
+module myproject_mac_muladd_16s_9s_34s_34_1_1(
+// 
+    din0,
+    din1,
+    din2,
+    dout);
+
+parameter ID = 32'd1;
+parameter NUM_STAGE = 32'd1;
+parameter din0_WIDTH = 32'd1;
+parameter din1_WIDTH = 32'd1;
+parameter din2_WIDTH = 32'd1;
+parameter dout_WIDTH = 32'd1;
+// 
+input[din0_WIDTH - 1:0] din0;
+input[din1_WIDTH - 1:0] din1;
+input[din2_WIDTH - 1:0] din2;
+output[dout_WIDTH - 1:0] dout;
+
+
+myproject_mac_muladd_16s_9s_34s_34_1_1_DSP48_0 myproject_mac_muladd_16s_9s_34s_34_1_1_DSP48_0_U(
+// 
+    .in0( din0 ),
+    .in1( din1 ),
+    .in2( din2 ),
+    .dout( dout ));
+
+endmodule
+
+

myproject_prj/solution1/impl/verilog/myproject_mac_muladd_16s_9s_43s_44_1_1.v

@@ -0,0 +1,66 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+//   
+//   
+//   
+`timescale 1 ns / 1 ps
+// 
+module myproject_mac_muladd_16s_9s_43s_44_1_1_DSP48_0(
+    input  [16 - 1:0] in0,
+    input  [9 - 1:0] in1,
+    input  [43 - 1:0] in2,
+    output [44 - 1:0]  dout);
+
+wire signed [27 - 1:0]     a;
+wire signed [18 - 1:0]     b;
+wire signed [48 - 1:0]     c;
+wire signed [45 - 1:0]     m;
+wire signed [48 - 1:0]     p;
+
+assign a  = $signed(in0);
+assign b  = $signed(in1);
+assign c  = $signed(in2);
+
+assign m  = a * b;
+// 
+assign p  = m + c;
+// 
+assign dout = p;
+
+endmodule
+// 
+
+module myproject_mac_muladd_16s_9s_43s_44_1_1(
+// 
+    din0,
+    din1,
+    din2,
+    dout);
+
+parameter ID = 32'd1;
+parameter NUM_STAGE = 32'd1;
+parameter din0_WIDTH = 32'd1;
+parameter din1_WIDTH = 32'd1;
+parameter din2_WIDTH = 32'd1;
+parameter dout_WIDTH = 32'd1;
+// 
+input[din0_WIDTH - 1:0] din0;
+input[din1_WIDTH - 1:0] din1;
+input[din2_WIDTH - 1:0] din2;
+output[dout_WIDTH - 1:0] dout;
+
+
+myproject_mac_muladd_16s_9s_43s_44_1_1_DSP48_0 myproject_mac_muladd_16s_9s_43s_44_1_1_DSP48_0_U(
+// 
+    .in0( din0 ),
+    .in1( din1 ),
+    .in2( din2 ),
+    .dout( dout ));
+
+endmodule
+
+

myproject_prj/solution1/impl/verilog/myproject_mul_16s_16s_32_1_1.v

@@ -0,0 +1,75 @@
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1 ns / 1 ps
+
+ module myproject_mul_16s_16s_32_1_1(din0, din1, dout);
+parameter ID = 1;
+parameter NUM_STAGE = 0;
+parameter din0_WIDTH = 14;
+parameter din1_WIDTH = 12;
+parameter dout_WIDTH = 26;
+
+input [din0_WIDTH - 1 : 0] din0; 
+input [din1_WIDTH - 1 : 0] din1; 
+output [dout_WIDTH - 1 : 0] dout;
+
+wire signed [dout_WIDTH - 1 : 0] tmp_product;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+assign tmp_product = $signed(din0) * $signed(din1);
+
+
+
+
+
+
+
+
+assign dout = tmp_product;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+endmodule

myproject_prj/solution1/impl/verilog/myproject_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_s.v

@@ -0,0 +1,473 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+
+`timescale 1 ns / 1 ps 
+
+module myproject_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_s (
+        ap_clk,
+        ap_rst,
+        ap_start,
+        start_full_n,
+        ap_done,
+        ap_continue,
+        ap_idle,
+        ap_ready,
+        layer29_out_dout,
+        layer29_out_num_data_valid,
+        layer29_out_fifo_cap,
+        layer29_out_empty_n,
+        layer29_out_read,
+        layer30_out_din,
+        layer30_out_num_data_valid,
+        layer30_out_fifo_cap,
+        layer30_out_full_n,
+        layer30_out_write,
+        start_out,
+        start_write
+);
+
+parameter    ap_ST_fsm_state1 = 1'd1;
+
+input   ap_clk;
+input   ap_rst;
+input   ap_start;
+input   start_full_n;
+output   ap_done;
+input   ap_continue;
+output   ap_idle;
+output   ap_ready;
+input  [671:0] layer29_out_dout;
+input  [10:0] layer29_out_num_data_valid;
+input  [10:0] layer29_out_fifo_cap;
+input   layer29_out_empty_n;
+output   layer29_out_read;
+output  [255:0] layer30_out_din;
+input  [10:0] layer30_out_num_data_valid;
+input  [10:0] layer30_out_fifo_cap;
+input   layer30_out_full_n;
+output   layer30_out_write;
+output   start_out;
+output   start_write;
+
+reg ap_idle;
+reg start_write;
+
+reg    real_start;
+reg    start_once_reg;
+(* fsm_encoding = "none" *) reg   [0:0] ap_CS_fsm;
+wire    ap_CS_fsm_state1;
+wire    internal_ap_ready;
+reg    ap_done_reg;
+reg    ap_block_state1_pp0_stage0_iter0;
+wire   [0:0] icmp_ln41_fu_776_p2;
+reg    ap_condition_exit_pp0_iter0_stage0;
+wire    ap_loop_exit_ready;
+reg    ap_ready_int;
+reg    layer29_out_blk_n;
+reg    layer30_out_blk_n;
+reg   [9:0] i1_fu_170;
+wire   [9:0] i_fu_770_p2;
+wire    ap_loop_init;
+reg   [9:0] ap_sig_allocacmp_i1_load;
+reg    layer29_out_read_local;
+wire   [255:0] or_ln57_s_fu_733_p17;
+reg    layer30_out_write_local;
+wire   [41:0] trunc_ln44_fu_195_p1;
+wire   [0:0] icmp_ln51_fu_349_p2;
+wire   [15:0] out_data_fu_355_p4;
+wire   [41:0] trunc_ln44_220_fu_199_p4;
+wire   [0:0] icmp_ln51_220_fu_373_p2;
+wire   [15:0] out_data_82_fu_379_p4;
+wire   [41:0] trunc_ln44_221_fu_209_p4;
+wire   [0:0] icmp_ln51_221_fu_397_p2;
+wire   [15:0] out_data_84_fu_403_p4;
+wire   [41:0] trunc_ln44_222_fu_219_p4;
+wire   [0:0] icmp_ln51_222_fu_421_p2;
+wire   [15:0] out_data_86_fu_427_p4;
+wire   [41:0] trunc_ln44_223_fu_229_p4;
+wire   [0:0] icmp_ln51_223_fu_445_p2;
+wire   [15:0] trunc_ln_fu_451_p4;
+wire   [41:0] trunc_ln44_224_fu_239_p4;
+wire   [0:0] icmp_ln51_224_fu_469_p2;
+wire   [15:0] trunc_ln52_200_fu_475_p4;
+wire   [41:0] trunc_ln44_225_fu_249_p4;
+wire   [0:0] icmp_ln51_225_fu_493_p2;
+wire   [15:0] trunc_ln52_201_fu_499_p4;
+wire   [41:0] trunc_ln44_226_fu_259_p4;
+wire   [0:0] icmp_ln51_226_fu_517_p2;
+wire   [15:0] trunc_ln52_202_fu_523_p4;
+wire   [41:0] trunc_ln44_227_fu_269_p4;
+wire   [0:0] icmp_ln51_227_fu_541_p2;
+wire   [15:0] trunc_ln52_203_fu_547_p4;
+wire   [41:0] trunc_ln44_228_fu_279_p4;
+wire   [0:0] icmp_ln51_228_fu_565_p2;
+wire   [15:0] trunc_ln52_204_fu_571_p4;
+wire   [41:0] trunc_ln44_229_fu_289_p4;
+wire   [0:0] icmp_ln51_229_fu_589_p2;
+wire   [15:0] trunc_ln52_205_fu_595_p4;
+wire   [41:0] trunc_ln44_230_fu_299_p4;
+wire   [0:0] icmp_ln51_230_fu_613_p2;
+wire   [15:0] trunc_ln52_206_fu_619_p4;
+wire   [41:0] trunc_ln44_231_fu_309_p4;
+wire   [0:0] icmp_ln51_231_fu_637_p2;
+wire   [15:0] trunc_ln52_207_fu_643_p4;
+wire   [41:0] trunc_ln44_232_fu_319_p4;
+wire   [0:0] icmp_ln51_232_fu_661_p2;
+wire   [15:0] trunc_ln52_208_fu_667_p4;
+wire   [41:0] trunc_ln44_233_fu_329_p4;
+wire   [0:0] icmp_ln51_233_fu_685_p2;
+wire   [15:0] trunc_ln52_209_fu_691_p4;
+wire   [41:0] trunc_ln44_234_fu_339_p4;
+wire   [0:0] icmp_ln51_234_fu_709_p2;
+wire   [15:0] trunc_ln52_210_fu_715_p4;
+wire   [15:0] select_ln51_210_fu_725_p3;
+wire   [15:0] select_ln51_209_fu_701_p3;
+wire   [15:0] select_ln51_208_fu_677_p3;
+wire   [15:0] select_ln51_207_fu_653_p3;
+wire   [15:0] select_ln51_206_fu_629_p3;
+wire   [15:0] select_ln51_205_fu_605_p3;
+wire   [15:0] select_ln51_204_fu_581_p3;
+wire   [15:0] select_ln51_203_fu_557_p3;
+wire   [15:0] select_ln51_202_fu_533_p3;
+wire   [15:0] select_ln51_201_fu_509_p3;
+wire   [15:0] select_ln51_200_fu_485_p3;
+wire   [15:0] select_ln51_fu_461_p3;
+wire   [15:0] out_data_87_fu_437_p3;
+wire   [15:0] out_data_85_fu_413_p3;
+wire   [15:0] out_data_83_fu_389_p3;
+wire   [15:0] out_data_81_fu_365_p3;
+wire    ap_continue_int;
+reg    ap_done_int;
+reg   [0:0] ap_NS_fsm;
+reg    ap_ST_fsm_state1_blk;
+wire    ap_start_int;
+wire    ap_done_sig;
+wire    ap_ce_reg;
+
+// power-on initialization
+initial begin
+#0 start_once_reg = 1'b0;
+#0 ap_CS_fsm = 1'd1;
+#0 ap_done_reg = 1'b0;
+#0 i1_fu_170 = 10'd0;
+end
+
+myproject_flow_control_loop_pipe flow_control_loop_pipe_U(
+    .ap_clk(ap_clk),
+    .ap_rst(ap_rst),
+    .ap_start(real_start),
+    .ap_ready(internal_ap_ready),
+    .ap_done(ap_done_sig),
+    .ap_start_int(ap_start_int),
+    .ap_loop_init(ap_loop_init),
+    .ap_ready_int(ap_ready_int),
+    .ap_loop_exit_ready(ap_condition_exit_pp0_iter0_stage0),
+    .ap_loop_exit_done(ap_done_int),
+    .ap_continue_int(ap_continue_int),
+    .ap_done_int(ap_done_int),
+    .ap_continue(ap_continue)
+);
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_CS_fsm <= ap_ST_fsm_state1;
+    end else begin
+        ap_CS_fsm <= ap_NS_fsm;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_done_reg <= 1'b0;
+    end else begin
+        if ((ap_continue_int == 1'b1)) begin
+            ap_done_reg <= 1'b0;
+        end else if (((ap_loop_exit_ready == 1'b1) & (1'b0 == ap_block_state1_pp0_stage0_iter0) & (1'b1 == ap_CS_fsm_state1))) begin
+            ap_done_reg <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        start_once_reg <= 1'b0;
+    end else begin
+        if (((real_start == 1'b1) & (internal_ap_ready == 1'b0))) begin
+            start_once_reg <= 1'b1;
+        end else if ((internal_ap_ready == 1'b1)) begin
+            start_once_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_state1_pp0_stage0_iter0) & (1'b1 == ap_CS_fsm_state1))) begin
+        i1_fu_170 <= i_fu_770_p2;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_block_state1_pp0_stage0_iter0)) begin
+        ap_ST_fsm_state1_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state1_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln41_fu_776_p2 == 1'd1) & (1'b0 == ap_block_state1_pp0_stage0_iter0) & (1'b1 == ap_CS_fsm_state1))) begin
+        ap_condition_exit_pp0_iter0_stage0 = 1'b1;
+    end else begin
+        ap_condition_exit_pp0_iter0_stage0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_loop_exit_ready == 1'b1) & (1'b0 == ap_block_state1_pp0_stage0_iter0) & (1'b1 == ap_CS_fsm_state1))) begin
+        ap_done_int = 1'b1;
+    end else begin
+        ap_done_int = ap_done_reg;
+    end
+end
+
+always @ (*) begin
+    if (((ap_start_int == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
+        ap_idle = 1'b1;
+    end else begin
+        ap_idle = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state1_pp0_stage0_iter0) & (1'b1 == ap_CS_fsm_state1))) begin
+        ap_ready_int = 1'b1;
+    end else begin
+        ap_ready_int = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_loop_init == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+        ap_sig_allocacmp_i1_load = 10'd0;
+    end else begin
+        ap_sig_allocacmp_i1_load = i1_fu_170;
+    end
+end
+
+always @ (*) begin
+    if ((~((ap_start_int == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
+        layer29_out_blk_n = layer29_out_empty_n;
+    end else begin
+        layer29_out_blk_n = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state1_pp0_stage0_iter0) & (1'b1 == ap_CS_fsm_state1))) begin
+        layer29_out_read_local = 1'b1;
+    end else begin
+        layer29_out_read_local = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((~((ap_start_int == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
+        layer30_out_blk_n = layer30_out_full_n;
+    end else begin
+        layer30_out_blk_n = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state1_pp0_stage0_iter0) & (1'b1 == ap_CS_fsm_state1))) begin
+        layer30_out_write_local = 1'b1;
+    end else begin
+        layer30_out_write_local = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((start_full_n == 1'b0) & (start_once_reg == 1'b0))) begin
+        real_start = 1'b0;
+    end else begin
+        real_start = ap_start;
+    end
+end
+
+always @ (*) begin
+    if (((real_start == 1'b1) & (start_once_reg == 1'b0))) begin
+        start_write = 1'b1;
+    end else begin
+        start_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    case (ap_CS_fsm)
+        ap_ST_fsm_state1 : begin
+            ap_NS_fsm = ap_ST_fsm_state1;
+        end
+        default : begin
+            ap_NS_fsm = 'bx;
+        end
+    endcase
+end
+
+assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
+
+always @ (*) begin
+    ap_block_state1_pp0_stage0_iter0 = ((ap_start_int == 1'b0) | (ap_done_reg == 1'b1) | (layer30_out_full_n == 1'b0) | (layer29_out_empty_n == 1'b0));
+end
+
+assign ap_done = ap_done_sig;
+
+assign ap_loop_exit_ready = ap_condition_exit_pp0_iter0_stage0;
+
+assign ap_ready = internal_ap_ready;
+
+assign i_fu_770_p2 = (ap_sig_allocacmp_i1_load + 10'd1);
+
+assign icmp_ln41_fu_776_p2 = ((ap_sig_allocacmp_i1_load == 10'd1023) ? 1'b1 : 1'b0);
+
+assign icmp_ln51_220_fu_373_p2 = (($signed(trunc_ln44_220_fu_199_p4) > $signed(42'd0)) ? 1'b1 : 1'b0);
+
+assign icmp_ln51_221_fu_397_p2 = (($signed(trunc_ln44_221_fu_209_p4) > $signed(42'd0)) ? 1'b1 : 1'b0);
+
+assign icmp_ln51_222_fu_421_p2 = (($signed(trunc_ln44_222_fu_219_p4) > $signed(42'd0)) ? 1'b1 : 1'b0);
+
+assign icmp_ln51_223_fu_445_p2 = (($signed(trunc_ln44_223_fu_229_p4) > $signed(42'd0)) ? 1'b1 : 1'b0);
+
+assign icmp_ln51_224_fu_469_p2 = (($signed(trunc_ln44_224_fu_239_p4) > $signed(42'd0)) ? 1'b1 : 1'b0);
+
+assign icmp_ln51_225_fu_493_p2 = (($signed(trunc_ln44_225_fu_249_p4) > $signed(42'd0)) ? 1'b1 : 1'b0);
+
+assign icmp_ln51_226_fu_517_p2 = (($signed(trunc_ln44_226_fu_259_p4) > $signed(42'd0)) ? 1'b1 : 1'b0);
+
+assign icmp_ln51_227_fu_541_p2 = (($signed(trunc_ln44_227_fu_269_p4) > $signed(42'd0)) ? 1'b1 : 1'b0);
+
+assign icmp_ln51_228_fu_565_p2 = (($signed(trunc_ln44_228_fu_279_p4) > $signed(42'd0)) ? 1'b1 : 1'b0);
+
+assign icmp_ln51_229_fu_589_p2 = (($signed(trunc_ln44_229_fu_289_p4) > $signed(42'd0)) ? 1'b1 : 1'b0);
+
+assign icmp_ln51_230_fu_613_p2 = (($signed(trunc_ln44_230_fu_299_p4) > $signed(42'd0)) ? 1'b1 : 1'b0);
+
+assign icmp_ln51_231_fu_637_p2 = (($signed(trunc_ln44_231_fu_309_p4) > $signed(42'd0)) ? 1'b1 : 1'b0);
+
+assign icmp_ln51_232_fu_661_p2 = (($signed(trunc_ln44_232_fu_319_p4) > $signed(42'd0)) ? 1'b1 : 1'b0);
+
+assign icmp_ln51_233_fu_685_p2 = (($signed(trunc_ln44_233_fu_329_p4) > $signed(42'd0)) ? 1'b1 : 1'b0);
+
+assign icmp_ln51_234_fu_709_p2 = (($signed(trunc_ln44_234_fu_339_p4) > $signed(42'd0)) ? 1'b1 : 1'b0);
+
+assign icmp_ln51_fu_349_p2 = (($signed(trunc_ln44_fu_195_p1) > $signed(42'd0)) ? 1'b1 : 1'b0);
+
+assign layer29_out_read = layer29_out_read_local;
+
+assign layer30_out_din = or_ln57_s_fu_733_p17;
+
+assign layer30_out_write = layer30_out_write_local;
+
+assign or_ln57_s_fu_733_p17 = {{{{{{{{{{{{{{{{select_ln51_210_fu_725_p3}, {select_ln51_209_fu_701_p3}}, {select_ln51_208_fu_677_p3}}, {select_ln51_207_fu_653_p3}}, {select_ln51_206_fu_629_p3}}, {select_ln51_205_fu_605_p3}}, {select_ln51_204_fu_581_p3}}, {select_ln51_203_fu_557_p3}}, {select_ln51_202_fu_533_p3}}, {select_ln51_201_fu_509_p3}}, {select_ln51_200_fu_485_p3}}, {select_ln51_fu_461_p3}}, {out_data_87_fu_437_p3}}, {out_data_85_fu_413_p3}}, {out_data_83_fu_389_p3}}, {out_data_81_fu_365_p3}};
+
+assign out_data_81_fu_365_p3 = ((icmp_ln51_fu_349_p2[0:0] == 1'b1) ? out_data_fu_355_p4 : 16'd0);
+
+assign out_data_82_fu_379_p4 = {{layer29_out_dout[67:52]}};
+
+assign out_data_83_fu_389_p3 = ((icmp_ln51_220_fu_373_p2[0:0] == 1'b1) ? out_data_82_fu_379_p4 : 16'd0);
+
+assign out_data_84_fu_403_p4 = {{layer29_out_dout[109:94]}};
+
+assign out_data_85_fu_413_p3 = ((icmp_ln51_221_fu_397_p2[0:0] == 1'b1) ? out_data_84_fu_403_p4 : 16'd0);
+
+assign out_data_86_fu_427_p4 = {{layer29_out_dout[151:136]}};
+
+assign out_data_87_fu_437_p3 = ((icmp_ln51_222_fu_421_p2[0:0] == 1'b1) ? out_data_86_fu_427_p4 : 16'd0);
+
+assign out_data_fu_355_p4 = {{layer29_out_dout[25:10]}};
+
+assign select_ln51_200_fu_485_p3 = ((icmp_ln51_224_fu_469_p2[0:0] == 1'b1) ? trunc_ln52_200_fu_475_p4 : 16'd0);
+
+assign select_ln51_201_fu_509_p3 = ((icmp_ln51_225_fu_493_p2[0:0] == 1'b1) ? trunc_ln52_201_fu_499_p4 : 16'd0);
+
+assign select_ln51_202_fu_533_p3 = ((icmp_ln51_226_fu_517_p2[0:0] == 1'b1) ? trunc_ln52_202_fu_523_p4 : 16'd0);
+
+assign select_ln51_203_fu_557_p3 = ((icmp_ln51_227_fu_541_p2[0:0] == 1'b1) ? trunc_ln52_203_fu_547_p4 : 16'd0);
+
+assign select_ln51_204_fu_581_p3 = ((icmp_ln51_228_fu_565_p2[0:0] == 1'b1) ? trunc_ln52_204_fu_571_p4 : 16'd0);
+
+assign select_ln51_205_fu_605_p3 = ((icmp_ln51_229_fu_589_p2[0:0] == 1'b1) ? trunc_ln52_205_fu_595_p4 : 16'd0);
+
+assign select_ln51_206_fu_629_p3 = ((icmp_ln51_230_fu_613_p2[0:0] == 1'b1) ? trunc_ln52_206_fu_619_p4 : 16'd0);
+
+assign select_ln51_207_fu_653_p3 = ((icmp_ln51_231_fu_637_p2[0:0] == 1'b1) ? trunc_ln52_207_fu_643_p4 : 16'd0);
+
+assign select_ln51_208_fu_677_p3 = ((icmp_ln51_232_fu_661_p2[0:0] == 1'b1) ? trunc_ln52_208_fu_667_p4 : 16'd0);
+
+assign select_ln51_209_fu_701_p3 = ((icmp_ln51_233_fu_685_p2[0:0] == 1'b1) ? trunc_ln52_209_fu_691_p4 : 16'd0);
+
+assign select_ln51_210_fu_725_p3 = ((icmp_ln51_234_fu_709_p2[0:0] == 1'b1) ? trunc_ln52_210_fu_715_p4 : 16'd0);
+
+assign select_ln51_fu_461_p3 = ((icmp_ln51_223_fu_445_p2[0:0] == 1'b1) ? trunc_ln_fu_451_p4 : 16'd0);
+
+assign start_out = real_start;
+
+assign trunc_ln44_220_fu_199_p4 = {{layer29_out_dout[83:42]}};
+
+assign trunc_ln44_221_fu_209_p4 = {{layer29_out_dout[125:84]}};
+
+assign trunc_ln44_222_fu_219_p4 = {{layer29_out_dout[167:126]}};
+
+assign trunc_ln44_223_fu_229_p4 = {{layer29_out_dout[209:168]}};
+
+assign trunc_ln44_224_fu_239_p4 = {{layer29_out_dout[251:210]}};
+
+assign trunc_ln44_225_fu_249_p4 = {{layer29_out_dout[293:252]}};
+
+assign trunc_ln44_226_fu_259_p4 = {{layer29_out_dout[335:294]}};
+
+assign trunc_ln44_227_fu_269_p4 = {{layer29_out_dout[377:336]}};
+
+assign trunc_ln44_228_fu_279_p4 = {{layer29_out_dout[419:378]}};
+
+assign trunc_ln44_229_fu_289_p4 = {{layer29_out_dout[461:420]}};
+
+assign trunc_ln44_230_fu_299_p4 = {{layer29_out_dout[503:462]}};
+
+assign trunc_ln44_231_fu_309_p4 = {{layer29_out_dout[545:504]}};
+
+assign trunc_ln44_232_fu_319_p4 = {{layer29_out_dout[587:546]}};
+
+assign trunc_ln44_233_fu_329_p4 = {{layer29_out_dout[629:588]}};
+
+assign trunc_ln44_234_fu_339_p4 = {{layer29_out_dout[671:630]}};
+
+assign trunc_ln44_fu_195_p1 = layer29_out_dout[41:0];
+
+assign trunc_ln52_200_fu_475_p4 = {{layer29_out_dout[235:220]}};
+
+assign trunc_ln52_201_fu_499_p4 = {{layer29_out_dout[277:262]}};
+
+assign trunc_ln52_202_fu_523_p4 = {{layer29_out_dout[319:304]}};
+
+assign trunc_ln52_203_fu_547_p4 = {{layer29_out_dout[361:346]}};
+
+assign trunc_ln52_204_fu_571_p4 = {{layer29_out_dout[403:388]}};
+
+assign trunc_ln52_205_fu_595_p4 = {{layer29_out_dout[445:430]}};
+
+assign trunc_ln52_206_fu_619_p4 = {{layer29_out_dout[487:472]}};
+
+assign trunc_ln52_207_fu_643_p4 = {{layer29_out_dout[529:514]}};
+
+assign trunc_ln52_208_fu_667_p4 = {{layer29_out_dout[571:556]}};
+
+assign trunc_ln52_209_fu_691_p4 = {{layer29_out_dout[613:598]}};
+
+assign trunc_ln52_210_fu_715_p4 = {{layer29_out_dout[655:640]}};
+
+assign trunc_ln_fu_451_p4 = {{layer29_out_dout[193:178]}};
+
+endmodule //myproject_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30_s

myproject_prj/solution1/impl/verilog/myproject_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s.v

@@ -0,0 +1,352 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+
+`timescale 1 ns / 1 ps 
+
+module myproject_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s (
+        ap_clk,
+        ap_rst,
+        ap_start,
+        ap_done,
+        ap_idle,
+        ap_ready,
+        in_elem_0_0_0_0_0_val,
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_175_i,
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_175_o,
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_175_o_ap_vld,
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_176,
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_176_ap_vld,
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_172_i,
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_172_o,
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_172_o_ap_vld,
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_173,
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_173_ap_vld,
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_169_i,
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_169_o,
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_169_o_ap_vld,
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_170,
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_170_ap_vld,
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_174_i,
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_174_o,
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_174_o_ap_vld,
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_171_i,
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_171_o,
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_171_o_ap_vld,
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_168_i,
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_168_o,
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_168_o_ap_vld
+);
+
+parameter    ap_ST_fsm_state1 = 1'd1;
+
+input   ap_clk;
+input   ap_rst;
+input   ap_start;
+output   ap_done;
+output   ap_idle;
+output   ap_ready;
+input  [15:0] in_elem_0_0_0_0_0_val;
+input  [15:0] void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_175_i;
+output  [15:0] void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_175_o;
+output   void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_175_o_ap_vld;
+output  [15:0] void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_176;
+output   void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_176_ap_vld;
+input  [15:0] void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_172_i;
+output  [15:0] void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_172_o;
+output   void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_172_o_ap_vld;
+output  [15:0] void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_173;
+output   void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_173_ap_vld;
+input  [15:0] void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_169_i;
+output  [15:0] void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_169_o;
+output   void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_169_o_ap_vld;
+output  [15:0] void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_170;
+output   void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_170_ap_vld;
+input  [15:0] void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_174_i;
+output  [15:0] void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_174_o;
+output   void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_174_o_ap_vld;
+input  [15:0] void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_171_i;
+output  [15:0] void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_171_o;
+output   void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_171_o_ap_vld;
+input  [15:0] void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_168_i;
+output  [15:0] void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_168_o;
+output   void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_168_o_ap_vld;
+
+reg ap_done;
+reg ap_idle;
+reg ap_ready;
+reg[15:0] void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_175_o;
+reg void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_175_o_ap_vld;
+reg void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_176_ap_vld;
+reg[15:0] void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_172_o;
+reg void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_172_o_ap_vld;
+reg void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_173_ap_vld;
+reg[15:0] void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_169_o;
+reg void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_169_o_ap_vld;
+reg void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_170_ap_vld;
+reg[15:0] void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_174_o;
+reg void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_174_o_ap_vld;
+reg[15:0] void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_171_o;
+reg void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_171_o_ap_vld;
+reg[15:0] void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_168_o;
+reg void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_168_o_ap_vld;
+
+(* fsm_encoding = "none" *) reg   [0:0] ap_CS_fsm;
+wire    ap_CS_fsm_state1;
+reg    void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_ce0;
+reg    void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_we0;
+wire   [15:0] void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_q0;
+reg    void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_1_ce0;
+reg    void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_1_we0;
+wire   [15:0] void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_1_q0;
+reg   [0:0] ap_NS_fsm;
+reg    ap_ST_fsm_state1_blk;
+wire    ap_ce_reg;
+
+// power-on initialization
+initial begin
+#0 ap_CS_fsm = 1'd1;
+end
+
+myproject_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb #(
+    .DataWidth( 16 ),
+    .AddressRange( 66 ),
+    .AddressWidth( 7 ))
+void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_U(
+    .clk(ap_clk),
+    .reset(ap_rst),
+    .address0(7'd65),
+    .ce0(void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_ce0),
+    .we0(void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_we0),
+    .d0(in_elem_0_0_0_0_0_val),
+    .q0(void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_q0)
+);
+
+myproject_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s_void_conv_2d_buffer_bkb #(
+    .DataWidth( 16 ),
+    .AddressRange( 66 ),
+    .AddressWidth( 7 ))
+void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_1_U(
+    .clk(ap_clk),
+    .reset(ap_rst),
+    .address0(7'd65),
+    .ce0(void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_1_ce0),
+    .we0(void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_1_we0),
+    .d0(void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_q0),
+    .q0(void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_1_q0)
+);
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_CS_fsm <= ap_ST_fsm_state1;
+    end else begin
+        ap_CS_fsm <= ap_NS_fsm;
+    end
+end
+
+always @ (*) begin
+    if ((ap_start == 1'b0)) begin
+        ap_ST_fsm_state1_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state1_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1)) | ((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1)))) begin
+        ap_done = 1'b1;
+    end else begin
+        ap_done = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
+        ap_idle = 1'b1;
+    end else begin
+        ap_idle = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+        ap_ready = 1'b1;
+    end else begin
+        ap_ready = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state1)) begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_168_o = in_elem_0_0_0_0_0_val;
+    end else begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_168_o = void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_168_i;
+    end
+end
+
+always @ (*) begin
+    if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_168_o_ap_vld = 1'b1;
+    end else begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_168_o_ap_vld = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state1)) begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_169_o = void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_168_i;
+    end else begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_169_o = void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_169_i;
+    end
+end
+
+always @ (*) begin
+    if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_169_o_ap_vld = 1'b1;
+    end else begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_169_o_ap_vld = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_170_ap_vld = 1'b1;
+    end else begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_170_ap_vld = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state1)) begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_171_o = void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_q0;
+    end else begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_171_o = void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_171_i;
+    end
+end
+
+always @ (*) begin
+    if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_171_o_ap_vld = 1'b1;
+    end else begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_171_o_ap_vld = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state1)) begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_172_o = void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_171_i;
+    end else begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_172_o = void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_172_i;
+    end
+end
+
+always @ (*) begin
+    if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_172_o_ap_vld = 1'b1;
+    end else begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_172_o_ap_vld = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_173_ap_vld = 1'b1;
+    end else begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_173_ap_vld = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state1)) begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_174_o = void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_1_q0;
+    end else begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_174_o = void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_174_i;
+    end
+end
+
+always @ (*) begin
+    if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_174_o_ap_vld = 1'b1;
+    end else begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_174_o_ap_vld = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state1)) begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_175_o = void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_174_i;
+    end else begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_175_o = void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_175_i;
+    end
+end
+
+always @ (*) begin
+    if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_175_o_ap_vld = 1'b1;
+    end else begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_175_o_ap_vld = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_176_ap_vld = 1'b1;
+    end else begin
+        void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_176_ap_vld = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+        void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_1_ce0 = 1'd1;
+    end else begin
+        void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_1_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+        void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_1_we0 = 1'd1;
+    end else begin
+        void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_1_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+        void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_ce0 = 1'd1;
+    end else begin
+        void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_ce0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+        void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_we0 = 1'd1;
+    end else begin
+        void_conv_2d_buffer_resource_cl_stream_stream_weight_t_bias_t_line_buffer_we0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    case (ap_CS_fsm)
+        ap_ST_fsm_state1 : begin
+            ap_NS_fsm = ap_ST_fsm_state1;
+        end
+        default : begin
+            ap_NS_fsm = 'bx;
+        end
+    endcase
+end
+
+assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
+
+assign void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_170 = void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_169_i;
+
+assign void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_173 = void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_172_i;
+
+assign void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_176 = void_compute_output_buffer_2d_array_const_ap_shift_reg_n_chan_stream_weig_175_i;
+
+endmodule //myproject_shift_line_buffer_array_ap_fixed_16_6_5_3_0_1u_config2_s

myproject_prj/solution1/impl/verilog/myproject_shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dOK.v

@@ -0,0 +1,88 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+
+`timescale 1 ns / 1 ps
+
+module myproject_shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dOK_core (
+    clk,
+    ce,
+    din,
+    addr,
+    dout);
+
+parameter DATA_WIDTH = 16;
+parameter ADDR_WIDTH = 4;
+parameter DEPTH = 10;
+
+input clk;
+input ce;
+input [DATA_WIDTH-1:0] din;
+input [ADDR_WIDTH-1:0] addr;
+output [DATA_WIDTH-1:0] dout;
+
+reg[DATA_WIDTH-1:0] ShiftRegMem[0:DEPTH-1];
+
+integer i;
+
+
+initial
+begin
+    for(i=0;i<DEPTH;i=i+1)
+        ShiftRegMem[i] <= {DATA_WIDTH{1'b0}};
+end
+
+always @ (posedge clk)
+begin
+    if (ce)
+    begin
+        for(i=0;i<DEPTH-1;i=i+1)
+            ShiftRegMem[i+1] <= ShiftRegMem[i];
+        ShiftRegMem[0] <= din;
+    end
+end
+
+
+assign dout = ShiftRegMem[addr];
+
+
+
+
+endmodule
+
+module myproject_shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dOK (
+    clk,
+    reset,
+    address0,
+    ce0,
+    we0,
+    d0,
+    q0);
+
+parameter DataWidth = 16;
+parameter AddressRange = 10;
+parameter AddressWidth = 4;
+
+input clk;
+input reset;
+input [AddressWidth-1:0] address0;
+input ce0;
+input we0;
+input [DataWidth-1:0] d0;
+output [DataWidth-1:0] q0;
+
+myproject_shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dOK_core #(
+    .DATA_WIDTH( DataWidth ),
+    .ADDR_WIDTH( AddressWidth ),
+    .DEPTH( AddressRange ))
+myproject_shift_line_buffer_array_ap_fixed_16_6_5_3_0_32u_config17_s_p_ZZN4nnet26conv_2dOK_core_U(
+    .clk(clk),
+    .ce(we0),
+    .din(d0),
+    .addr(address0),
+    .dout(q0)
+);
+
+endmodule

myproject_prj/solution1/impl/verilog/myproject_start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384oqc.v

@@ -0,0 +1,151 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+//RAW latency 1 
+
+module myproject_start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384oqc
+#(parameter
+    MEM_STYLE    = "shiftReg",
+    DATA_WIDTH   = 1,
+    ADDR_WIDTH   = 1,
+    DEPTH        = 2)
+(
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+    
+    // read 
+
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+localparam 
+    SRL_DEPTH    = DEPTH,
+    SRL_AWIDTH   = ADDR_WIDTH;
+//------------------------Local signal-------------------
+    reg  [SRL_AWIDTH-1:0] addr;
+    wire                  push;
+    wire                  pop;
+    reg  [SRL_AWIDTH:0]   mOutPtr;
+    reg                   empty_n = 1'b0;
+    reg                   full_n = 1'b1; 
+
+//------------------------Instantiation------------------
+    myproject_start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384oqc_ShiftReg 
+    #(  .DATA_WIDTH (DATA_WIDTH),
+        .ADDR_WIDTH (SRL_AWIDTH),
+        .DEPTH      (SRL_DEPTH))
+    U_myproject_start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384oqc_ShiftReg (
+        .clk        (clk),
+        .we         (push),
+        .addr       (addr),
+        .din        (if_din),
+        .dout       (if_dout)
+    );
+//------------------------Task and function--------------
+
+//------------------------Body---------------------------
+    // num_data_valid 
+
+    // almost full/empty 
+
+    // program full/empty 
+
+    assign if_full_n  = full_n; 
+    assign if_empty_n = empty_n;
+
+    assign push       = full_n & if_write_ce & if_write;
+    assign pop        = empty_n & if_read_ce & if_read;
+
+    // addr
+    always @(posedge clk) begin
+        if (reset)
+            addr <= {SRL_AWIDTH{1'b0}};
+        else if (push & ~pop && empty_n)
+            addr <= addr + 1'b1;
+        else if (~push & pop && (mOutPtr != 1))
+            addr <= addr - 1'b1;
+    end
+
+    // mOutPtr
+    always @(posedge clk) begin
+        if (reset)
+            mOutPtr <= {SRL_AWIDTH+1{1'b0}};
+        else if (push & ~pop)
+            mOutPtr <= mOutPtr + 1'b1;
+        else if (~push & pop)
+            mOutPtr <= mOutPtr - 1'b1;
+    end
+
+    // full_n
+    always @(posedge clk) begin
+        if (reset)
+            full_n <= 1'b1;
+        else if ((push & ~pop) && (mOutPtr == DEPTH - 1))
+            full_n <= 1'b0;
+        else if (~push & pop)
+            full_n <= 1'b1;
+    end
+
+    // empty_n
+    always @(posedge clk) begin
+        if (reset)
+            empty_n <= 1'b0;
+        else if (push & ~pop)
+            empty_n <= 1'b1;
+        else if ((~push & pop) && (mOutPtr == 1))
+            empty_n <= 1'b0;
+    end
+
+    // almost_full_n 
+
+    // almost_empty_n 
+
+    // prog_full_n 
+ 
+    // prog_empty_n 
+
+endmodule  
+
+
+module myproject_start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384oqc_ShiftReg
+#(parameter
+    DATA_WIDTH  = 1,
+    ADDR_WIDTH  = 1,
+    DEPTH       = 2)
+(
+    input  wire                  clk,
+    input  wire                  we,
+    input  wire [ADDR_WIDTH-1:0] addr,
+    input  wire [DATA_WIDTH-1:0] din,
+    output wire [DATA_WIDTH-1:0] dout
+);
+
+    reg [DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
+    integer i;
+
+    always @(posedge clk) begin
+        if (we) begin
+            for (i=0; i<DEPTH-1; i=i+1)
+                SRL_SIG[i+1] <= SRL_SIG[i];
+            SRL_SIG[0] <= din;
+        end
+    end
+
+    assign dout = SRL_SIG[addr];
+
+endmodule

myproject_prj/solution1/impl/verilog/myproject_start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3ozc.v

@@ -0,0 +1,151 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+//RAW latency 1 
+
+module myproject_start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3ozc
+#(parameter
+    MEM_STYLE    = "shiftReg",
+    DATA_WIDTH   = 1,
+    ADDR_WIDTH   = 1,
+    DEPTH        = 2)
+(
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+    
+    // read 
+
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+localparam 
+    SRL_DEPTH    = DEPTH,
+    SRL_AWIDTH   = ADDR_WIDTH;
+//------------------------Local signal-------------------
+    reg  [SRL_AWIDTH-1:0] addr;
+    wire                  push;
+    wire                  pop;
+    reg  [SRL_AWIDTH:0]   mOutPtr;
+    reg                   empty_n = 1'b0;
+    reg                   full_n = 1'b1; 
+
+//------------------------Instantiation------------------
+    myproject_start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3ozc_ShiftReg 
+    #(  .DATA_WIDTH (DATA_WIDTH),
+        .ADDR_WIDTH (SRL_AWIDTH),
+        .DEPTH      (SRL_DEPTH))
+    U_myproject_start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3ozc_ShiftReg (
+        .clk        (clk),
+        .we         (push),
+        .addr       (addr),
+        .din        (if_din),
+        .dout       (if_dout)
+    );
+//------------------------Task and function--------------
+
+//------------------------Body---------------------------
+    // num_data_valid 
+
+    // almost full/empty 
+
+    // program full/empty 
+
+    assign if_full_n  = full_n; 
+    assign if_empty_n = empty_n;
+
+    assign push       = full_n & if_write_ce & if_write;
+    assign pop        = empty_n & if_read_ce & if_read;
+
+    // addr
+    always @(posedge clk) begin
+        if (reset)
+            addr <= {SRL_AWIDTH{1'b0}};
+        else if (push & ~pop && empty_n)
+            addr <= addr + 1'b1;
+        else if (~push & pop && (mOutPtr != 1))
+            addr <= addr - 1'b1;
+    end
+
+    // mOutPtr
+    always @(posedge clk) begin
+        if (reset)
+            mOutPtr <= {SRL_AWIDTH+1{1'b0}};
+        else if (push & ~pop)
+            mOutPtr <= mOutPtr + 1'b1;
+        else if (~push & pop)
+            mOutPtr <= mOutPtr - 1'b1;
+    end
+
+    // full_n
+    always @(posedge clk) begin
+        if (reset)
+            full_n <= 1'b1;
+        else if ((push & ~pop) && (mOutPtr == DEPTH - 1))
+            full_n <= 1'b0;
+        else if (~push & pop)
+            full_n <= 1'b1;
+    end
+
+    // empty_n
+    always @(posedge clk) begin
+        if (reset)
+            empty_n <= 1'b0;
+        else if (push & ~pop)
+            empty_n <= 1'b1;
+        else if ((~push & pop) && (mOutPtr == 1))
+            empty_n <= 1'b0;
+    end
+
+    // almost_full_n 
+
+    // almost_empty_n 
+
+    // prog_full_n 
+ 
+    // prog_empty_n 
+
+endmodule  
+
+
+module myproject_start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3ozc_ShiftReg
+#(parameter
+    DATA_WIDTH  = 1,
+    ADDR_WIDTH  = 1,
+    DEPTH       = 2)
+(
+    input  wire                  clk,
+    input  wire                  we,
+    input  wire [ADDR_WIDTH-1:0] addr,
+    input  wire [DATA_WIDTH-1:0] din,
+    output wire [DATA_WIDTH-1:0] dout
+);
+
+    reg [DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
+    integer i;
+
+    always @(posedge clk) begin
+        if (we) begin
+            for (i=0; i<DEPTH-1; i=i+1)
+                SRL_SIG[i+1] <= SRL_SIG[i];
+            SRL_SIG[0] <= din;
+        end
+    end
+
+    assign dout = SRL_SIG[addr];
+
+endmodule

myproject_prj/solution1/impl/verilog/myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7okc.v

@@ -0,0 +1,151 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+//RAW latency 1 
+
+module myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7okc
+#(parameter
+    MEM_STYLE    = "shiftReg",
+    DATA_WIDTH   = 1,
+    ADDR_WIDTH   = 1,
+    DEPTH        = 2)
+(
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+    
+    // read 
+
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+localparam 
+    SRL_DEPTH    = DEPTH,
+    SRL_AWIDTH   = ADDR_WIDTH;
+//------------------------Local signal-------------------
+    reg  [SRL_AWIDTH-1:0] addr;
+    wire                  push;
+    wire                  pop;
+    reg  [SRL_AWIDTH:0]   mOutPtr;
+    reg                   empty_n = 1'b0;
+    reg                   full_n = 1'b1; 
+
+//------------------------Instantiation------------------
+    myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7okc_ShiftReg 
+    #(  .DATA_WIDTH (DATA_WIDTH),
+        .ADDR_WIDTH (SRL_AWIDTH),
+        .DEPTH      (SRL_DEPTH))
+    U_myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7okc_ShiftReg (
+        .clk        (clk),
+        .we         (push),
+        .addr       (addr),
+        .din        (if_din),
+        .dout       (if_dout)
+    );
+//------------------------Task and function--------------
+
+//------------------------Body---------------------------
+    // num_data_valid 
+
+    // almost full/empty 
+
+    // program full/empty 
+
+    assign if_full_n  = full_n; 
+    assign if_empty_n = empty_n;
+
+    assign push       = full_n & if_write_ce & if_write;
+    assign pop        = empty_n & if_read_ce & if_read;
+
+    // addr
+    always @(posedge clk) begin
+        if (reset)
+            addr <= {SRL_AWIDTH{1'b0}};
+        else if (push & ~pop && empty_n)
+            addr <= addr + 1'b1;
+        else if (~push & pop && (mOutPtr != 1))
+            addr <= addr - 1'b1;
+    end
+
+    // mOutPtr
+    always @(posedge clk) begin
+        if (reset)
+            mOutPtr <= {SRL_AWIDTH+1{1'b0}};
+        else if (push & ~pop)
+            mOutPtr <= mOutPtr + 1'b1;
+        else if (~push & pop)
+            mOutPtr <= mOutPtr - 1'b1;
+    end
+
+    // full_n
+    always @(posedge clk) begin
+        if (reset)
+            full_n <= 1'b1;
+        else if ((push & ~pop) && (mOutPtr == DEPTH - 1))
+            full_n <= 1'b0;
+        else if (~push & pop)
+            full_n <= 1'b1;
+    end
+
+    // empty_n
+    always @(posedge clk) begin
+        if (reset)
+            empty_n <= 1'b0;
+        else if (push & ~pop)
+            empty_n <= 1'b1;
+        else if ((~push & pop) && (mOutPtr == 1))
+            empty_n <= 1'b0;
+    end
+
+    // almost_full_n 
+
+    // almost_empty_n 
+
+    // prog_full_n 
+ 
+    // prog_empty_n 
+
+endmodule  
+
+
+module myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7okc_ShiftReg
+#(parameter
+    DATA_WIDTH  = 1,
+    ADDR_WIDTH  = 1,
+    DEPTH       = 2)
+(
+    input  wire                  clk,
+    input  wire                  we,
+    input  wire [ADDR_WIDTH-1:0] addr,
+    input  wire [DATA_WIDTH-1:0] din,
+    output wire [DATA_WIDTH-1:0] dout
+);
+
+    reg [DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
+    integer i;
+
+    always @(posedge clk) begin
+        if (we) begin
+            for (i=0; i<DEPTH-1; i=i+1)
+                SRL_SIG[i+1] <= SRL_SIG[i];
+            SRL_SIG[0] <= din;
+        end
+    end
+
+    assign dout = SRL_SIG[addr];
+
+endmodule

myproject_prj/solution1/impl/verilog/myproject_start_for_conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_U0.v

@@ -0,0 +1,151 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+//RAW latency 1 
+
+module myproject_start_for_conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_U0
+#(parameter
+    MEM_STYLE    = "shiftReg",
+    DATA_WIDTH   = 1,
+    ADDR_WIDTH   = 1,
+    DEPTH        = 2)
+(
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+    
+    // read 
+
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+localparam 
+    SRL_DEPTH    = DEPTH,
+    SRL_AWIDTH   = ADDR_WIDTH;
+//------------------------Local signal-------------------
+    reg  [SRL_AWIDTH-1:0] addr;
+    wire                  push;
+    wire                  pop;
+    reg  [SRL_AWIDTH:0]   mOutPtr;
+    reg                   empty_n = 1'b0;
+    reg                   full_n = 1'b1; 
+
+//------------------------Instantiation------------------
+    myproject_start_for_conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_U0_ShiftReg 
+    #(  .DATA_WIDTH (DATA_WIDTH),
+        .ADDR_WIDTH (SRL_AWIDTH),
+        .DEPTH      (SRL_DEPTH))
+    U_myproject_start_for_conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_U0_ShiftReg (
+        .clk        (clk),
+        .we         (push),
+        .addr       (addr),
+        .din        (if_din),
+        .dout       (if_dout)
+    );
+//------------------------Task and function--------------
+
+//------------------------Body---------------------------
+    // num_data_valid 
+
+    // almost full/empty 
+
+    // program full/empty 
+
+    assign if_full_n  = full_n; 
+    assign if_empty_n = empty_n;
+
+    assign push       = full_n & if_write_ce & if_write;
+    assign pop        = empty_n & if_read_ce & if_read;
+
+    // addr
+    always @(posedge clk) begin
+        if (reset)
+            addr <= {SRL_AWIDTH{1'b0}};
+        else if (push & ~pop && empty_n)
+            addr <= addr + 1'b1;
+        else if (~push & pop && (mOutPtr != 1))
+            addr <= addr - 1'b1;
+    end
+
+    // mOutPtr
+    always @(posedge clk) begin
+        if (reset)
+            mOutPtr <= {SRL_AWIDTH+1{1'b0}};
+        else if (push & ~pop)
+            mOutPtr <= mOutPtr + 1'b1;
+        else if (~push & pop)
+            mOutPtr <= mOutPtr - 1'b1;
+    end
+
+    // full_n
+    always @(posedge clk) begin
+        if (reset)
+            full_n <= 1'b1;
+        else if ((push & ~pop) && (mOutPtr == DEPTH - 1))
+            full_n <= 1'b0;
+        else if (~push & pop)
+            full_n <= 1'b1;
+    end
+
+    // empty_n
+    always @(posedge clk) begin
+        if (reset)
+            empty_n <= 1'b0;
+        else if (push & ~pop)
+            empty_n <= 1'b1;
+        else if ((~push & pop) && (mOutPtr == 1))
+            empty_n <= 1'b0;
+    end
+
+    // almost_full_n 
+
+    // almost_empty_n 
+
+    // prog_full_n 
+ 
+    // prog_empty_n 
+
+endmodule  
+
+
+module myproject_start_for_conv_2d_cl_array_array_ap_fixed_43_23_5_3_0_32u_config23_U0_ShiftReg
+#(parameter
+    DATA_WIDTH  = 1,
+    ADDR_WIDTH  = 1,
+    DEPTH       = 2)
+(
+    input  wire                  clk,
+    input  wire                  we,
+    input  wire [ADDR_WIDTH-1:0] addr,
+    input  wire [DATA_WIDTH-1:0] din,
+    output wire [DATA_WIDTH-1:0] dout
+);
+
+    reg [DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
+    integer i;
+
+    always @(posedge clk) begin
+        if (we) begin
+            for (i=0; i<DEPTH-1; i=i+1)
+                SRL_SIG[i+1] <= SRL_SIG[i];
+            SRL_SIG[0] <= din;
+        end
+    end
+
+    assign dout = SRL_SIG[addr];
+
+endmodule

myproject_prj/solution1/impl/verilog/myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32ovc.v

@@ -0,0 +1,151 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+//RAW latency 1 
+
+module myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32ovc
+#(parameter
+    MEM_STYLE    = "shiftReg",
+    DATA_WIDTH   = 1,
+    ADDR_WIDTH   = 1,
+    DEPTH        = 2)
+(
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+    
+    // read 
+
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+localparam 
+    SRL_DEPTH    = DEPTH,
+    SRL_AWIDTH   = ADDR_WIDTH;
+//------------------------Local signal-------------------
+    reg  [SRL_AWIDTH-1:0] addr;
+    wire                  push;
+    wire                  pop;
+    reg  [SRL_AWIDTH:0]   mOutPtr;
+    reg                   empty_n = 1'b0;
+    reg                   full_n = 1'b1; 
+
+//------------------------Instantiation------------------
+    myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32ovc_ShiftReg 
+    #(  .DATA_WIDTH (DATA_WIDTH),
+        .ADDR_WIDTH (SRL_AWIDTH),
+        .DEPTH      (SRL_DEPTH))
+    U_myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32ovc_ShiftReg (
+        .clk        (clk),
+        .we         (push),
+        .addr       (addr),
+        .din        (if_din),
+        .dout       (if_dout)
+    );
+//------------------------Task and function--------------
+
+//------------------------Body---------------------------
+    // num_data_valid 
+
+    // almost full/empty 
+
+    // program full/empty 
+
+    assign if_full_n  = full_n; 
+    assign if_empty_n = empty_n;
+
+    assign push       = full_n & if_write_ce & if_write;
+    assign pop        = empty_n & if_read_ce & if_read;
+
+    // addr
+    always @(posedge clk) begin
+        if (reset)
+            addr <= {SRL_AWIDTH{1'b0}};
+        else if (push & ~pop && empty_n)
+            addr <= addr + 1'b1;
+        else if (~push & pop && (mOutPtr != 1))
+            addr <= addr - 1'b1;
+    end
+
+    // mOutPtr
+    always @(posedge clk) begin
+        if (reset)
+            mOutPtr <= {SRL_AWIDTH+1{1'b0}};
+        else if (push & ~pop)
+            mOutPtr <= mOutPtr + 1'b1;
+        else if (~push & pop)
+            mOutPtr <= mOutPtr - 1'b1;
+    end
+
+    // full_n
+    always @(posedge clk) begin
+        if (reset)
+            full_n <= 1'b1;
+        else if ((push & ~pop) && (mOutPtr == DEPTH - 1))
+            full_n <= 1'b0;
+        else if (~push & pop)
+            full_n <= 1'b1;
+    end
+
+    // empty_n
+    always @(posedge clk) begin
+        if (reset)
+            empty_n <= 1'b0;
+        else if (push & ~pop)
+            empty_n <= 1'b1;
+        else if ((~push & pop) && (mOutPtr == 1))
+            empty_n <= 1'b0;
+    end
+
+    // almost_full_n 
+
+    // almost_empty_n 
+
+    // prog_full_n 
+ 
+    // prog_empty_n 
+
+endmodule  
+
+
+module myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config32ovc_ShiftReg
+#(parameter
+    DATA_WIDTH  = 1,
+    ADDR_WIDTH  = 1,
+    DEPTH       = 2)
+(
+    input  wire                  clk,
+    input  wire                  we,
+    input  wire [ADDR_WIDTH-1:0] addr,
+    input  wire [DATA_WIDTH-1:0] din,
+    output wire [DATA_WIDTH-1:0] dout
+);
+
+    reg [DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
+    integer i;
+
+    always @(posedge clk) begin
+        if (we) begin
+            for (i=0; i<DEPTH-1; i=i+1)
+                SRL_SIG[i+1] <= SRL_SIG[i];
+            SRL_SIG[0] <= din;
+        end
+    end
+
+    assign dout = SRL_SIG[addr];
+
+endmodule

myproject_prj/solution1/impl/verilog/myproject_start_for_zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config4ohc.v

@@ -0,0 +1,151 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+//RAW latency 1 
+
+module myproject_start_for_zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config4ohc
+#(parameter
+    MEM_STYLE    = "shiftReg",
+    DATA_WIDTH   = 1,
+    ADDR_WIDTH   = 1,
+    DEPTH        = 2)
+(
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+    
+    // read 
+
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+localparam 
+    SRL_DEPTH    = DEPTH,
+    SRL_AWIDTH   = ADDR_WIDTH;
+//------------------------Local signal-------------------
+    reg  [SRL_AWIDTH-1:0] addr;
+    wire                  push;
+    wire                  pop;
+    reg  [SRL_AWIDTH:0]   mOutPtr;
+    reg                   empty_n = 1'b0;
+    reg                   full_n = 1'b1; 
+
+//------------------------Instantiation------------------
+    myproject_start_for_zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config4ohc_ShiftReg 
+    #(  .DATA_WIDTH (DATA_WIDTH),
+        .ADDR_WIDTH (SRL_AWIDTH),
+        .DEPTH      (SRL_DEPTH))
+    U_myproject_start_for_zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config4ohc_ShiftReg (
+        .clk        (clk),
+        .we         (push),
+        .addr       (addr),
+        .din        (if_din),
+        .dout       (if_dout)
+    );
+//------------------------Task and function--------------
+
+//------------------------Body---------------------------
+    // num_data_valid 
+
+    // almost full/empty 
+
+    // program full/empty 
+
+    assign if_full_n  = full_n; 
+    assign if_empty_n = empty_n;
+
+    assign push       = full_n & if_write_ce & if_write;
+    assign pop        = empty_n & if_read_ce & if_read;
+
+    // addr
+    always @(posedge clk) begin
+        if (reset)
+            addr <= {SRL_AWIDTH{1'b0}};
+        else if (push & ~pop && empty_n)
+            addr <= addr + 1'b1;
+        else if (~push & pop && (mOutPtr != 1))
+            addr <= addr - 1'b1;
+    end
+
+    // mOutPtr
+    always @(posedge clk) begin
+        if (reset)
+            mOutPtr <= {SRL_AWIDTH+1{1'b0}};
+        else if (push & ~pop)
+            mOutPtr <= mOutPtr + 1'b1;
+        else if (~push & pop)
+            mOutPtr <= mOutPtr - 1'b1;
+    end
+
+    // full_n
+    always @(posedge clk) begin
+        if (reset)
+            full_n <= 1'b1;
+        else if ((push & ~pop) && (mOutPtr == DEPTH - 1))
+            full_n <= 1'b0;
+        else if (~push & pop)
+            full_n <= 1'b1;
+    end
+
+    // empty_n
+    always @(posedge clk) begin
+        if (reset)
+            empty_n <= 1'b0;
+        else if (push & ~pop)
+            empty_n <= 1'b1;
+        else if ((~push & pop) && (mOutPtr == 1))
+            empty_n <= 1'b0;
+    end
+
+    // almost_full_n 
+
+    // almost_empty_n 
+
+    // prog_full_n 
+ 
+    // prog_empty_n 
+
+endmodule  
+
+
+module myproject_start_for_zeropad2d_cl_array_ap_fixed_1u_array_ap_fixed_16_6_5_3_0_1u_config4ohc_ShiftReg
+#(parameter
+    DATA_WIDTH  = 1,
+    ADDR_WIDTH  = 1,
+    DEPTH       = 2)
+(
+    input  wire                  clk,
+    input  wire                  we,
+    input  wire [ADDR_WIDTH-1:0] addr,
+    input  wire [DATA_WIDTH-1:0] din,
+    output wire [DATA_WIDTH-1:0] dout
+);
+
+    reg [DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
+    integer i;
+
+    always @(posedge clk) begin
+        if (we) begin
+            for (i=0; i<DEPTH-1; i=i+1)
+                SRL_SIG[i+1] <= SRL_SIG[i];
+            SRL_SIG[0] <= din;
+        end
+    end
+
+    assign dout = SRL_SIG[addr];
+
+endmodule

myproject_prj/solution1/impl/verilog/myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_U0.v

@@ -0,0 +1,151 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+//RAW latency 1 
+
+module myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_U0
+#(parameter
+    MEM_STYLE    = "shiftReg",
+    DATA_WIDTH   = 1,
+    ADDR_WIDTH   = 1,
+    DEPTH        = 2)
+(
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+    
+    // read 
+
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+localparam 
+    SRL_DEPTH    = DEPTH,
+    SRL_AWIDTH   = ADDR_WIDTH;
+//------------------------Local signal-------------------
+    reg  [SRL_AWIDTH-1:0] addr;
+    wire                  push;
+    wire                  pop;
+    reg  [SRL_AWIDTH:0]   mOutPtr;
+    reg                   empty_n = 1'b0;
+    reg                   full_n = 1'b1; 
+
+//------------------------Instantiation------------------
+    myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_U0_ShiftReg 
+    #(  .DATA_WIDTH (DATA_WIDTH),
+        .ADDR_WIDTH (SRL_AWIDTH),
+        .DEPTH      (SRL_DEPTH))
+    U_myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_U0_ShiftReg (
+        .clk        (clk),
+        .we         (push),
+        .addr       (addr),
+        .din        (if_din),
+        .dout       (if_dout)
+    );
+//------------------------Task and function--------------
+
+//------------------------Body---------------------------
+    // num_data_valid 
+
+    // almost full/empty 
+
+    // program full/empty 
+
+    assign if_full_n  = full_n; 
+    assign if_empty_n = empty_n;
+
+    assign push       = full_n & if_write_ce & if_write;
+    assign pop        = empty_n & if_read_ce & if_read;
+
+    // addr
+    always @(posedge clk) begin
+        if (reset)
+            addr <= {SRL_AWIDTH{1'b0}};
+        else if (push & ~pop && empty_n)
+            addr <= addr + 1'b1;
+        else if (~push & pop && (mOutPtr != 1))
+            addr <= addr - 1'b1;
+    end
+
+    // mOutPtr
+    always @(posedge clk) begin
+        if (reset)
+            mOutPtr <= {SRL_AWIDTH+1{1'b0}};
+        else if (push & ~pop)
+            mOutPtr <= mOutPtr + 1'b1;
+        else if (~push & pop)
+            mOutPtr <= mOutPtr - 1'b1;
+    end
+
+    // full_n
+    always @(posedge clk) begin
+        if (reset)
+            full_n <= 1'b1;
+        else if ((push & ~pop) && (mOutPtr == DEPTH - 1))
+            full_n <= 1'b0;
+        else if (~push & pop)
+            full_n <= 1'b1;
+    end
+
+    // empty_n
+    always @(posedge clk) begin
+        if (reset)
+            empty_n <= 1'b0;
+        else if (push & ~pop)
+            empty_n <= 1'b1;
+        else if ((~push & pop) && (mOutPtr == 1))
+            empty_n <= 1'b0;
+    end
+
+    // almost_full_n 
+
+    // almost_empty_n 
+
+    // prog_full_n 
+ 
+    // prog_empty_n 
+
+endmodule  
+
+
+module myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config50_U0_ShiftReg
+#(parameter
+    DATA_WIDTH  = 1,
+    ADDR_WIDTH  = 1,
+    DEPTH       = 2)
+(
+    input  wire                  clk,
+    input  wire                  we,
+    input  wire [ADDR_WIDTH-1:0] addr,
+    input  wire [DATA_WIDTH-1:0] din,
+    output wire [DATA_WIDTH-1:0] dout
+);
+
+    reg [DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
+    integer i;
+
+    always @(posedge clk) begin
+        if (we) begin
+            for (i=0; i<DEPTH-1; i=i+1)
+                SRL_SIG[i+1] <= SRL_SIG[i];
+            SRL_SIG[0] <= din;
+        end
+    end
+
+    assign dout = SRL_SIG[addr];
+
+endmodule

myproject_prj/solution1/impl/verilog/myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config52_U0.v

@@ -0,0 +1,151 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+//RAW latency 1 
+
+module myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config52_U0
+#(parameter
+    MEM_STYLE    = "shiftReg",
+    DATA_WIDTH   = 1,
+    ADDR_WIDTH   = 1,
+    DEPTH        = 2)
+(
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+    
+    // read 
+
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+localparam 
+    SRL_DEPTH    = DEPTH,
+    SRL_AWIDTH   = ADDR_WIDTH;
+//------------------------Local signal-------------------
+    reg  [SRL_AWIDTH-1:0] addr;
+    wire                  push;
+    wire                  pop;
+    reg  [SRL_AWIDTH:0]   mOutPtr;
+    reg                   empty_n = 1'b0;
+    reg                   full_n = 1'b1; 
+
+//------------------------Instantiation------------------
+    myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config52_U0_ShiftReg 
+    #(  .DATA_WIDTH (DATA_WIDTH),
+        .ADDR_WIDTH (SRL_AWIDTH),
+        .DEPTH      (SRL_DEPTH))
+    U_myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config52_U0_ShiftReg (
+        .clk        (clk),
+        .we         (push),
+        .addr       (addr),
+        .din        (if_din),
+        .dout       (if_dout)
+    );
+//------------------------Task and function--------------
+
+//------------------------Body---------------------------
+    // num_data_valid 
+
+    // almost full/empty 
+
+    // program full/empty 
+
+    assign if_full_n  = full_n; 
+    assign if_empty_n = empty_n;
+
+    assign push       = full_n & if_write_ce & if_write;
+    assign pop        = empty_n & if_read_ce & if_read;
+
+    // addr
+    always @(posedge clk) begin
+        if (reset)
+            addr <= {SRL_AWIDTH{1'b0}};
+        else if (push & ~pop && empty_n)
+            addr <= addr + 1'b1;
+        else if (~push & pop && (mOutPtr != 1))
+            addr <= addr - 1'b1;
+    end
+
+    // mOutPtr
+    always @(posedge clk) begin
+        if (reset)
+            mOutPtr <= {SRL_AWIDTH+1{1'b0}};
+        else if (push & ~pop)
+            mOutPtr <= mOutPtr + 1'b1;
+        else if (~push & pop)
+            mOutPtr <= mOutPtr - 1'b1;
+    end
+
+    // full_n
+    always @(posedge clk) begin
+        if (reset)
+            full_n <= 1'b1;
+        else if ((push & ~pop) && (mOutPtr == DEPTH - 1))
+            full_n <= 1'b0;
+        else if (~push & pop)
+            full_n <= 1'b1;
+    end
+
+    // empty_n
+    always @(posedge clk) begin
+        if (reset)
+            empty_n <= 1'b0;
+        else if (push & ~pop)
+            empty_n <= 1'b1;
+        else if ((~push & pop) && (mOutPtr == 1))
+            empty_n <= 1'b0;
+    end
+
+    // almost_full_n 
+
+    // almost_empty_n 
+
+    // prog_full_n 
+ 
+    // prog_empty_n 
+
+endmodule  
+
+
+module myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config52_U0_ShiftReg
+#(parameter
+    DATA_WIDTH  = 1,
+    ADDR_WIDTH  = 1,
+    DEPTH       = 2)
+(
+    input  wire                  clk,
+    input  wire                  we,
+    input  wire [ADDR_WIDTH-1:0] addr,
+    input  wire [DATA_WIDTH-1:0] din,
+    output wire [DATA_WIDTH-1:0] dout
+);
+
+    reg [DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
+    integer i;
+
+    always @(posedge clk) begin
+        if (we) begin
+            for (i=0; i<DEPTH-1; i=i+1)
+                SRL_SIG[i+1] <= SRL_SIG[i];
+            SRL_SIG[0] <= din;
+        end
+    end
+
+    assign dout = SRL_SIG[addr];
+
+endmodule

myproject_prj/solution1/impl/verilog/myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config56_U0.v

@@ -0,0 +1,151 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+`timescale 1ns/1ps
+//RAW latency 1 
+
+module myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config56_U0
+#(parameter
+    MEM_STYLE    = "shiftReg",
+    DATA_WIDTH   = 1,
+    ADDR_WIDTH   = 1,
+    DEPTH        = 2)
+(
+    // system signal
+    input  wire                  clk,
+    input  wire                  reset,
+
+    // write
+    output wire                  if_full_n,
+    input  wire                  if_write_ce,
+    input  wire                  if_write,
+    input  wire [DATA_WIDTH-1:0] if_din,
+    
+    // read 
+
+    output wire                  if_empty_n,
+    input  wire                  if_read_ce,
+    input  wire                  if_read,
+    output wire [DATA_WIDTH-1:0] if_dout
+);
+//------------------------Parameter----------------------
+localparam 
+    SRL_DEPTH    = DEPTH,
+    SRL_AWIDTH   = ADDR_WIDTH;
+//------------------------Local signal-------------------
+    reg  [SRL_AWIDTH-1:0] addr;
+    wire                  push;
+    wire                  pop;
+    reg  [SRL_AWIDTH:0]   mOutPtr;
+    reg                   empty_n = 1'b0;
+    reg                   full_n = 1'b1; 
+
+//------------------------Instantiation------------------
+    myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config56_U0_ShiftReg 
+    #(  .DATA_WIDTH (DATA_WIDTH),
+        .ADDR_WIDTH (SRL_AWIDTH),
+        .DEPTH      (SRL_DEPTH))
+    U_myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config56_U0_ShiftReg (
+        .clk        (clk),
+        .we         (push),
+        .addr       (addr),
+        .din        (if_din),
+        .dout       (if_dout)
+    );
+//------------------------Task and function--------------
+
+//------------------------Body---------------------------
+    // num_data_valid 
+
+    // almost full/empty 
+
+    // program full/empty 
+
+    assign if_full_n  = full_n; 
+    assign if_empty_n = empty_n;
+
+    assign push       = full_n & if_write_ce & if_write;
+    assign pop        = empty_n & if_read_ce & if_read;
+
+    // addr
+    always @(posedge clk) begin
+        if (reset)
+            addr <= {SRL_AWIDTH{1'b0}};
+        else if (push & ~pop && empty_n)
+            addr <= addr + 1'b1;
+        else if (~push & pop && (mOutPtr != 1))
+            addr <= addr - 1'b1;
+    end
+
+    // mOutPtr
+    always @(posedge clk) begin
+        if (reset)
+            mOutPtr <= {SRL_AWIDTH+1{1'b0}};
+        else if (push & ~pop)
+            mOutPtr <= mOutPtr + 1'b1;
+        else if (~push & pop)
+            mOutPtr <= mOutPtr - 1'b1;
+    end
+
+    // full_n
+    always @(posedge clk) begin
+        if (reset)
+            full_n <= 1'b1;
+        else if ((push & ~pop) && (mOutPtr == DEPTH - 1))
+            full_n <= 1'b0;
+        else if (~push & pop)
+            full_n <= 1'b1;
+    end
+
+    // empty_n
+    always @(posedge clk) begin
+        if (reset)
+            empty_n <= 1'b0;
+        else if (push & ~pop)
+            empty_n <= 1'b1;
+        else if ((~push & pop) && (mOutPtr == 1))
+            empty_n <= 1'b0;
+    end
+
+    // almost_full_n 
+
+    // almost_empty_n 
+
+    // prog_full_n 
+ 
+    // prog_empty_n 
+
+endmodule  
+
+
+module myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_48u_config56_U0_ShiftReg
+#(parameter
+    DATA_WIDTH  = 1,
+    ADDR_WIDTH  = 1,
+    DEPTH       = 2)
+(
+    input  wire                  clk,
+    input  wire                  we,
+    input  wire [ADDR_WIDTH-1:0] addr,
+    input  wire [DATA_WIDTH-1:0] din,
+    output wire [DATA_WIDTH-1:0] dout
+);
+
+    reg [DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
+    integer i;
+
+    always @(posedge clk) begin
+        if (we) begin
+            for (i=0; i<DEPTH-1; i=i+1)
+                SRL_SIG[i+1] <= SRL_SIG[i];
+            SRL_SIG[0] <= din;
+        end
+    end
+
+    assign dout = SRL_SIG[addr];
+
+endmodule

myproject_prj/solution1/impl/verilog/myproject_transpose_array_array_ap_fixed_1u_config41_Pipeline_VITIS_LOOP_45_1.v

@@ -0,0 +1,230 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+
+`timescale 1 ns / 1 ps 
+
+module myproject_transpose_array_array_ap_fixed_1u_config41_Pipeline_VITIS_LOOP_45_1 (
+        ap_clk,
+        ap_rst,
+        ap_start,
+        ap_done,
+        ap_idle,
+        ap_ready,
+        x_TVALID,
+        x_TDATA,
+        x_TREADY,
+        p_0_0_0209_out,
+        p_0_0_0209_out_ap_vld
+);
+
+parameter    ap_ST_fsm_state1 = 1'd1;
+
+input   ap_clk;
+input   ap_rst;
+input   ap_start;
+output   ap_done;
+output   ap_idle;
+output   ap_ready;
+input   x_TVALID;
+input  [1023:0] x_TDATA;
+output   x_TREADY;
+output  [15:0] p_0_0_0209_out;
+output   p_0_0_0209_out_ap_vld;
+
+reg ap_idle;
+reg x_TREADY;
+reg p_0_0_0209_out_ap_vld;
+
+(* fsm_encoding = "none" *) reg   [0:0] ap_CS_fsm;
+wire    ap_CS_fsm_state1;
+wire   [0:0] icmp_ln45_fu_193_p2;
+reg    ap_block_state1_pp0_stage0_iter0;
+reg    ap_condition_exit_pp0_iter0_stage0;
+wire    ap_loop_exit_ready;
+reg    ap_ready_int;
+reg    x_TDATA_blk_n;
+reg   [6:0] i_fu_164;
+wire   [6:0] add_ln45_fu_199_p2;
+wire    ap_loop_init;
+reg   [6:0] ap_sig_allocacmp_i_32;
+reg   [15:0] p_0_0_0209_fu_168;
+wire   [15:0] data_array_fu_209_p1;
+wire   [5:0] trunc_ln45_fu_205_p1;
+reg    ap_done_reg;
+wire    ap_continue_int;
+reg    ap_done_int;
+reg   [0:0] ap_NS_fsm;
+reg    ap_ST_fsm_state1_blk;
+wire    ap_start_int;
+wire    ap_ready_sig;
+wire    ap_done_sig;
+wire    ap_ce_reg;
+
+// power-on initialization
+initial begin
+#0 ap_CS_fsm = 1'd1;
+#0 i_fu_164 = 7'd0;
+#0 p_0_0_0209_fu_168 = 16'd0;
+#0 ap_done_reg = 1'b0;
+end
+
+myproject_flow_control_loop_pipe_sequential_init flow_control_loop_pipe_sequential_init_U(
+    .ap_clk(ap_clk),
+    .ap_rst(ap_rst),
+    .ap_start(ap_start),
+    .ap_ready(ap_ready_sig),
+    .ap_done(ap_done_sig),
+    .ap_start_int(ap_start_int),
+    .ap_loop_init(ap_loop_init),
+    .ap_ready_int(ap_ready_int),
+    .ap_loop_exit_ready(ap_condition_exit_pp0_iter0_stage0),
+    .ap_loop_exit_done(ap_done_int),
+    .ap_continue_int(ap_continue_int),
+    .ap_done_int(ap_done_int)
+);
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_CS_fsm <= ap_ST_fsm_state1;
+    end else begin
+        ap_CS_fsm <= ap_NS_fsm;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_done_reg <= 1'b0;
+    end else begin
+        if ((ap_continue_int == 1'b1)) begin
+            ap_done_reg <= 1'b0;
+        end else if (((ap_loop_exit_ready == 1'b1) & (1'b0 == ap_block_state1_pp0_stage0_iter0) & (1'b1 == ap_CS_fsm_state1))) begin
+            ap_done_reg <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((1'b0 == ap_block_state1_pp0_stage0_iter0) & (1'b1 == ap_CS_fsm_state1))) begin
+        if ((icmp_ln45_fu_193_p2 == 1'd0)) begin
+            i_fu_164 <= add_ln45_fu_199_p2;
+        end else if ((ap_loop_init == 1'b1)) begin
+            i_fu_164 <= 7'd0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (((trunc_ln45_fu_205_p1 == 6'd0) & (1'b0 == ap_block_state1_pp0_stage0_iter0) & (icmp_ln45_fu_193_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin
+        p_0_0_0209_fu_168 <= data_array_fu_209_p1;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_block_state1_pp0_stage0_iter0)) begin
+        ap_ST_fsm_state1_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state1_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state1_pp0_stage0_iter0) & (icmp_ln45_fu_193_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin
+        ap_condition_exit_pp0_iter0_stage0 = 1'b1;
+    end else begin
+        ap_condition_exit_pp0_iter0_stage0 = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_loop_exit_ready == 1'b1) & (1'b0 == ap_block_state1_pp0_stage0_iter0) & (1'b1 == ap_CS_fsm_state1))) begin
+        ap_done_int = 1'b1;
+    end else begin
+        ap_done_int = ap_done_reg;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b0))) begin
+        ap_idle = 1'b1;
+    end else begin
+        ap_idle = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state1_pp0_stage0_iter0) & (1'b1 == ap_CS_fsm_state1))) begin
+        ap_ready_int = 1'b1;
+    end else begin
+        ap_ready_int = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((ap_loop_init == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
+        ap_sig_allocacmp_i_32 = 7'd0;
+    end else begin
+        ap_sig_allocacmp_i_32 = i_fu_164;
+    end
+end
+
+always @ (*) begin
+    if (((ap_loop_exit_ready == 1'b1) & (1'b0 == ap_block_state1_pp0_stage0_iter0) & (icmp_ln45_fu_193_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state1))) begin
+        p_0_0_0209_out_ap_vld = 1'b1;
+    end else begin
+        p_0_0_0209_out_ap_vld = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((icmp_ln45_fu_193_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1) & (ap_start_int == 1'b1))) begin
+        x_TDATA_blk_n = x_TVALID;
+    end else begin
+        x_TDATA_blk_n = 1'b1;
+    end
+end
+
+always @ (*) begin
+    if (((1'b0 == ap_block_state1_pp0_stage0_iter0) & (icmp_ln45_fu_193_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state1))) begin
+        x_TREADY = 1'b1;
+    end else begin
+        x_TREADY = 1'b0;
+    end
+end
+
+always @ (*) begin
+    case (ap_CS_fsm)
+        ap_ST_fsm_state1 : begin
+            ap_NS_fsm = ap_ST_fsm_state1;
+        end
+        default : begin
+            ap_NS_fsm = 'bx;
+        end
+    endcase
+end
+
+assign add_ln45_fu_199_p2 = (ap_sig_allocacmp_i_32 + 7'd1);
+
+assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
+
+always @ (*) begin
+    ap_block_state1_pp0_stage0_iter0 = ((ap_start_int == 1'b0) | ((icmp_ln45_fu_193_p2 == 1'd0) & (x_TVALID == 1'b0)));
+end
+
+assign ap_done = ap_done_sig;
+
+assign ap_loop_exit_ready = ap_condition_exit_pp0_iter0_stage0;
+
+assign ap_ready = ap_ready_sig;
+
+assign data_array_fu_209_p1 = x_TDATA[15:0];
+
+assign icmp_ln45_fu_193_p2 = ((ap_sig_allocacmp_i_32 == 7'd64) ? 1'b1 : 1'b0);
+
+assign p_0_0_0209_out = p_0_0_0209_fu_168;
+
+assign trunc_ln45_fu_205_p1 = ap_sig_allocacmp_i_32[5:0];
+
+endmodule //myproject_transpose_array_array_ap_fixed_1u_config41_Pipeline_VITIS_LOOP_45_1

myproject_prj/solution1/impl/verilog/myproject_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config47_s.v

@@ -0,0 +1,430 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+
+`timescale 1 ns / 1 ps 
+
+module myproject_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config47_s (
+        ap_clk,
+        ap_rst,
+        ap_start,
+        start_full_n,
+        ap_done,
+        ap_continue,
+        ap_idle,
+        ap_ready,
+        start_out,
+        start_write,
+        layer3_out_dout,
+        layer3_out_num_data_valid,
+        layer3_out_fifo_cap,
+        layer3_out_empty_n,
+        layer3_out_read,
+        layer47_out_din,
+        layer47_out_num_data_valid,
+        layer47_out_fifo_cap,
+        layer47_out_full_n,
+        layer47_out_write
+);
+
+parameter    ap_ST_fsm_state1 = 8'd1;
+parameter    ap_ST_fsm_state2 = 8'd2;
+parameter    ap_ST_fsm_state3 = 8'd4;
+parameter    ap_ST_fsm_state4 = 8'd8;
+parameter    ap_ST_fsm_state5 = 8'd16;
+parameter    ap_ST_fsm_state6 = 8'd32;
+parameter    ap_ST_fsm_state7 = 8'd64;
+parameter    ap_ST_fsm_state8 = 8'd128;
+
+input   ap_clk;
+input   ap_rst;
+input   ap_start;
+input   start_full_n;
+output   ap_done;
+input   ap_continue;
+output   ap_idle;
+output   ap_ready;
+output   start_out;
+output   start_write;
+input  [127:0] layer3_out_dout;
+input  [12:0] layer3_out_num_data_valid;
+input  [12:0] layer3_out_fifo_cap;
+input   layer3_out_empty_n;
+output   layer3_out_read;
+output  [127:0] layer47_out_din;
+input  [13:0] layer47_out_num_data_valid;
+input  [13:0] layer47_out_fifo_cap;
+input   layer47_out_full_n;
+output   layer47_out_write;
+
+reg ap_done;
+reg ap_idle;
+reg start_write;
+reg layer3_out_read;
+reg[127:0] layer47_out_din;
+reg layer47_out_write;
+
+reg    real_start;
+reg    start_once_reg;
+reg    ap_done_reg;
+(* fsm_encoding = "none" *) reg   [7:0] ap_CS_fsm;
+wire    ap_CS_fsm_state1;
+reg    internal_ap_ready;
+wire    grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadTopWidth_fu_22_ap_start;
+wire    grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadTopWidth_fu_22_ap_done;
+wire    grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadTopWidth_fu_22_ap_idle;
+wire    grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadTopWidth_fu_22_ap_ready;
+wire   [127:0] grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadTopWidth_fu_22_layer47_out_din;
+wire    grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadTopWidth_fu_22_layer47_out_write;
+wire    grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain_fu_28_ap_start;
+wire    grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain_fu_28_ap_done;
+wire    grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain_fu_28_ap_idle;
+wire    grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain_fu_28_ap_ready;
+wire   [127:0] grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain_fu_28_layer47_out_din;
+wire    grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain_fu_28_layer47_out_write;
+wire    grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain_fu_28_layer3_out_read;
+wire    grp_zeropad2d_cl_array_array_ap_fixed_8u_config47_Pipeline_PadBottomWidth_fu_36_ap_start;
+wire    grp_zeropad2d_cl_array_array_ap_fixed_8u_config47_Pipeline_PadBottomWidth_fu_36_ap_done;
+wire    grp_zeropad2d_cl_array_array_ap_fixed_8u_config47_Pipeline_PadBottomWidth_fu_36_ap_idle;
+wire    grp_zeropad2d_cl_array_array_ap_fixed_8u_config47_Pipeline_PadBottomWidth_fu_36_ap_ready;
+wire   [127:0] grp_zeropad2d_cl_array_array_ap_fixed_8u_config47_Pipeline_PadBottomWidth_fu_36_layer47_out_din;
+wire    grp_zeropad2d_cl_array_array_ap_fixed_8u_config47_Pipeline_PadBottomWidth_fu_36_layer47_out_write;
+reg    grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadTopWidth_fu_22_ap_start_reg;
+reg    ap_block_state1_ignore_call3;
+wire    ap_CS_fsm_state2;
+reg    grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain_fu_28_ap_start_reg;
+wire    ap_CS_fsm_state4;
+wire    ap_CS_fsm_state5;
+reg    grp_zeropad2d_cl_array_array_ap_fixed_8u_config47_Pipeline_PadBottomWidth_fu_36_ap_start_reg;
+wire    ap_CS_fsm_state7;
+wire    ap_CS_fsm_state8;
+reg   [7:0] ap_NS_fsm;
+reg    ap_block_state1;
+reg    ap_ST_fsm_state1_blk;
+reg    ap_ST_fsm_state2_blk;
+wire    ap_ST_fsm_state3_blk;
+wire    ap_ST_fsm_state4_blk;
+reg    ap_ST_fsm_state5_blk;
+wire    ap_ST_fsm_state6_blk;
+wire    ap_ST_fsm_state7_blk;
+reg    ap_ST_fsm_state8_blk;
+wire    ap_ce_reg;
+
+// power-on initialization
+initial begin
+#0 start_once_reg = 1'b0;
+#0 ap_done_reg = 1'b0;
+#0 ap_CS_fsm = 8'd1;
+#0 grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadTopWidth_fu_22_ap_start_reg = 1'b0;
+#0 grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain_fu_28_ap_start_reg = 1'b0;
+#0 grp_zeropad2d_cl_array_array_ap_fixed_8u_config47_Pipeline_PadBottomWidth_fu_36_ap_start_reg = 1'b0;
+end
+
+myproject_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadTopWidth grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadTopWidth_fu_22(
+    .ap_clk(ap_clk),
+    .ap_rst(ap_rst),
+    .ap_start(grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadTopWidth_fu_22_ap_start),
+    .ap_done(grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadTopWidth_fu_22_ap_done),
+    .ap_idle(grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadTopWidth_fu_22_ap_idle),
+    .ap_ready(grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadTopWidth_fu_22_ap_ready),
+    .layer47_out_din(grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadTopWidth_fu_22_layer47_out_din),
+    .layer47_out_num_data_valid(14'd0),
+    .layer47_out_fifo_cap(14'd0),
+    .layer47_out_full_n(layer47_out_full_n),
+    .layer47_out_write(grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadTopWidth_fu_22_layer47_out_write)
+);
+
+myproject_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain_fu_28(
+    .ap_clk(ap_clk),
+    .ap_rst(ap_rst),
+    .ap_start(grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain_fu_28_ap_start),
+    .ap_done(grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain_fu_28_ap_done),
+    .ap_idle(grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain_fu_28_ap_idle),
+    .ap_ready(grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain_fu_28_ap_ready),
+    .layer47_out_din(grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain_fu_28_layer47_out_din),
+    .layer47_out_num_data_valid(14'd0),
+    .layer47_out_fifo_cap(14'd0),
+    .layer47_out_full_n(layer47_out_full_n),
+    .layer47_out_write(grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain_fu_28_layer47_out_write),
+    .layer3_out_dout(layer3_out_dout),
+    .layer3_out_num_data_valid(13'd0),
+    .layer3_out_fifo_cap(13'd0),
+    .layer3_out_empty_n(layer3_out_empty_n),
+    .layer3_out_read(grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain_fu_28_layer3_out_read)
+);
+
+myproject_zeropad2d_cl_array_array_ap_fixed_8u_config47_Pipeline_PadBottomWidth grp_zeropad2d_cl_array_array_ap_fixed_8u_config47_Pipeline_PadBottomWidth_fu_36(
+    .ap_clk(ap_clk),
+    .ap_rst(ap_rst),
+    .ap_start(grp_zeropad2d_cl_array_array_ap_fixed_8u_config47_Pipeline_PadBottomWidth_fu_36_ap_start),
+    .ap_done(grp_zeropad2d_cl_array_array_ap_fixed_8u_config47_Pipeline_PadBottomWidth_fu_36_ap_done),
+    .ap_idle(grp_zeropad2d_cl_array_array_ap_fixed_8u_config47_Pipeline_PadBottomWidth_fu_36_ap_idle),
+    .ap_ready(grp_zeropad2d_cl_array_array_ap_fixed_8u_config47_Pipeline_PadBottomWidth_fu_36_ap_ready),
+    .layer47_out_din(grp_zeropad2d_cl_array_array_ap_fixed_8u_config47_Pipeline_PadBottomWidth_fu_36_layer47_out_din),
+    .layer47_out_num_data_valid(14'd0),
+    .layer47_out_fifo_cap(14'd0),
+    .layer47_out_full_n(layer47_out_full_n),
+    .layer47_out_write(grp_zeropad2d_cl_array_array_ap_fixed_8u_config47_Pipeline_PadBottomWidth_fu_36_layer47_out_write)
+);
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_CS_fsm <= ap_ST_fsm_state1;
+    end else begin
+        ap_CS_fsm <= ap_NS_fsm;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_done_reg <= 1'b0;
+    end else begin
+        if ((ap_continue == 1'b1)) begin
+            ap_done_reg <= 1'b0;
+        end else if (((grp_zeropad2d_cl_array_array_ap_fixed_8u_config47_Pipeline_PadBottomWidth_fu_36_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state8))) begin
+            ap_done_reg <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain_fu_28_ap_start_reg <= 1'b0;
+    end else begin
+        if ((1'b1 == ap_CS_fsm_state4)) begin
+            grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain_fu_28_ap_start_reg <= 1'b1;
+        end else if ((grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain_fu_28_ap_ready == 1'b1)) begin
+            grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain_fu_28_ap_start_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadTopWidth_fu_22_ap_start_reg <= 1'b0;
+    end else begin
+        if (((1'b1 == ap_CS_fsm_state1) & (1'b0 == ap_block_state1_ignore_call3))) begin
+            grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadTopWidth_fu_22_ap_start_reg <= 1'b1;
+        end else if ((grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadTopWidth_fu_22_ap_ready == 1'b1)) begin
+            grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadTopWidth_fu_22_ap_start_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        grp_zeropad2d_cl_array_array_ap_fixed_8u_config47_Pipeline_PadBottomWidth_fu_36_ap_start_reg <= 1'b0;
+    end else begin
+        if ((1'b1 == ap_CS_fsm_state7)) begin
+            grp_zeropad2d_cl_array_array_ap_fixed_8u_config47_Pipeline_PadBottomWidth_fu_36_ap_start_reg <= 1'b1;
+        end else if ((grp_zeropad2d_cl_array_array_ap_fixed_8u_config47_Pipeline_PadBottomWidth_fu_36_ap_ready == 1'b1)) begin
+            grp_zeropad2d_cl_array_array_ap_fixed_8u_config47_Pipeline_PadBottomWidth_fu_36_ap_start_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        start_once_reg <= 1'b0;
+    end else begin
+        if (((internal_ap_ready == 1'b0) & (real_start == 1'b1))) begin
+            start_once_reg <= 1'b1;
+        end else if ((internal_ap_ready == 1'b1)) begin
+            start_once_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_block_state1)) begin
+        ap_ST_fsm_state1_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state1_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadTopWidth_fu_22_ap_done == 1'b0)) begin
+        ap_ST_fsm_state2_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state2_blk = 1'b0;
+    end
+end
+
+assign ap_ST_fsm_state3_blk = 1'b0;
+
+assign ap_ST_fsm_state4_blk = 1'b0;
+
+always @ (*) begin
+    if ((grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain_fu_28_ap_done == 1'b0)) begin
+        ap_ST_fsm_state5_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state5_blk = 1'b0;
+    end
+end
+
+assign ap_ST_fsm_state6_blk = 1'b0;
+
+assign ap_ST_fsm_state7_blk = 1'b0;
+
+always @ (*) begin
+    if ((grp_zeropad2d_cl_array_array_ap_fixed_8u_config47_Pipeline_PadBottomWidth_fu_36_ap_done == 1'b0)) begin
+        ap_ST_fsm_state8_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state8_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((grp_zeropad2d_cl_array_array_ap_fixed_8u_config47_Pipeline_PadBottomWidth_fu_36_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state8))) begin
+        ap_done = 1'b1;
+    end else begin
+        ap_done = ap_done_reg;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state1) & (real_start == 1'b0))) begin
+        ap_idle = 1'b1;
+    end else begin
+        ap_idle = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((grp_zeropad2d_cl_array_array_ap_fixed_8u_config47_Pipeline_PadBottomWidth_fu_36_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state8))) begin
+        internal_ap_ready = 1'b1;
+    end else begin
+        internal_ap_ready = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state5)) begin
+        layer3_out_read = grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain_fu_28_layer3_out_read;
+    end else begin
+        layer3_out_read = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state8)) begin
+        layer47_out_din = grp_zeropad2d_cl_array_array_ap_fixed_8u_config47_Pipeline_PadBottomWidth_fu_36_layer47_out_din;
+    end else if ((1'b1 == ap_CS_fsm_state5)) begin
+        layer47_out_din = grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain_fu_28_layer47_out_din;
+    end else if ((1'b1 == ap_CS_fsm_state2)) begin
+        layer47_out_din = grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadTopWidth_fu_22_layer47_out_din;
+    end else begin
+        layer47_out_din = grp_zeropad2d_cl_array_array_ap_fixed_8u_config47_Pipeline_PadBottomWidth_fu_36_layer47_out_din;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state8)) begin
+        layer47_out_write = grp_zeropad2d_cl_array_array_ap_fixed_8u_config47_Pipeline_PadBottomWidth_fu_36_layer47_out_write;
+    end else if ((1'b1 == ap_CS_fsm_state5)) begin
+        layer47_out_write = grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain_fu_28_layer47_out_write;
+    end else if ((1'b1 == ap_CS_fsm_state2)) begin
+        layer47_out_write = grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadTopWidth_fu_22_layer47_out_write;
+    end else begin
+        layer47_out_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((start_once_reg == 1'b0) & (start_full_n == 1'b0))) begin
+        real_start = 1'b0;
+    end else begin
+        real_start = ap_start;
+    end
+end
+
+always @ (*) begin
+    if (((start_once_reg == 1'b0) & (real_start == 1'b1))) begin
+        start_write = 1'b1;
+    end else begin
+        start_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    case (ap_CS_fsm)
+        ap_ST_fsm_state1 : begin
+            if (((1'b1 == ap_CS_fsm_state1) & (1'b0 == ap_block_state1))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end
+        end
+        ap_ST_fsm_state2 : begin
+            if (((grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadTopWidth_fu_22_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state2))) begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end
+        end
+        ap_ST_fsm_state3 : begin
+            ap_NS_fsm = ap_ST_fsm_state4;
+        end
+        ap_ST_fsm_state4 : begin
+            ap_NS_fsm = ap_ST_fsm_state5;
+        end
+        ap_ST_fsm_state5 : begin
+            if (((grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain_fu_28_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state5))) begin
+                ap_NS_fsm = ap_ST_fsm_state6;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state5;
+            end
+        end
+        ap_ST_fsm_state6 : begin
+            ap_NS_fsm = ap_ST_fsm_state7;
+        end
+        ap_ST_fsm_state7 : begin
+            ap_NS_fsm = ap_ST_fsm_state8;
+        end
+        ap_ST_fsm_state8 : begin
+            if (((grp_zeropad2d_cl_array_array_ap_fixed_8u_config47_Pipeline_PadBottomWidth_fu_36_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state8))) begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state8;
+            end
+        end
+        default : begin
+            ap_NS_fsm = 'bx;
+        end
+    endcase
+end
+
+assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
+
+assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
+
+assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3];
+
+assign ap_CS_fsm_state5 = ap_CS_fsm[32'd4];
+
+assign ap_CS_fsm_state7 = ap_CS_fsm[32'd6];
+
+assign ap_CS_fsm_state8 = ap_CS_fsm[32'd7];
+
+always @ (*) begin
+    ap_block_state1 = ((ap_done_reg == 1'b1) | (real_start == 1'b0));
+end
+
+always @ (*) begin
+    ap_block_state1_ignore_call3 = ((ap_done_reg == 1'b1) | (real_start == 1'b0));
+end
+
+assign ap_ready = internal_ap_ready;
+
+assign grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain_fu_28_ap_start = grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadMain_fu_28_ap_start_reg;
+
+assign grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadTopWidth_fu_22_ap_start = grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config47_Pipeline_PadTopWidth_fu_22_ap_start_reg;
+
+assign grp_zeropad2d_cl_array_array_ap_fixed_8u_config47_Pipeline_PadBottomWidth_fu_36_ap_start = grp_zeropad2d_cl_array_array_ap_fixed_8u_config47_Pipeline_PadBottomWidth_fu_36_ap_start_reg;
+
+assign start_out = real_start;
+
+endmodule //myproject_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config47_s

myproject_prj/solution1/impl/verilog/myproject_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config48_s.v

@@ -0,0 +1,430 @@
+// ==============================================================
+// Generated by Vitis HLS v2024.1
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// ==============================================================
+
+`timescale 1 ns / 1 ps 
+
+module myproject_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config48_s (
+        ap_clk,
+        ap_rst,
+        ap_start,
+        start_full_n,
+        ap_done,
+        ap_continue,
+        ap_idle,
+        ap_ready,
+        start_out,
+        start_write,
+        layer6_out_dout,
+        layer6_out_num_data_valid,
+        layer6_out_fifo_cap,
+        layer6_out_empty_n,
+        layer6_out_read,
+        layer48_out_din,
+        layer48_out_num_data_valid,
+        layer48_out_fifo_cap,
+        layer48_out_full_n,
+        layer48_out_write
+);
+
+parameter    ap_ST_fsm_state1 = 8'd1;
+parameter    ap_ST_fsm_state2 = 8'd2;
+parameter    ap_ST_fsm_state3 = 8'd4;
+parameter    ap_ST_fsm_state4 = 8'd8;
+parameter    ap_ST_fsm_state5 = 8'd16;
+parameter    ap_ST_fsm_state6 = 8'd32;
+parameter    ap_ST_fsm_state7 = 8'd64;
+parameter    ap_ST_fsm_state8 = 8'd128;
+
+input   ap_clk;
+input   ap_rst;
+input   ap_start;
+input   start_full_n;
+output   ap_done;
+input   ap_continue;
+output   ap_idle;
+output   ap_ready;
+output   start_out;
+output   start_write;
+input  [127:0] layer6_out_dout;
+input  [10:0] layer6_out_num_data_valid;
+input  [10:0] layer6_out_fifo_cap;
+input   layer6_out_empty_n;
+output   layer6_out_read;
+output  [127:0] layer48_out_din;
+input  [11:0] layer48_out_num_data_valid;
+input  [11:0] layer48_out_fifo_cap;
+input   layer48_out_full_n;
+output   layer48_out_write;
+
+reg ap_done;
+reg ap_idle;
+reg start_write;
+reg layer6_out_read;
+reg[127:0] layer48_out_din;
+reg layer48_out_write;
+
+reg    real_start;
+reg    start_once_reg;
+reg    ap_done_reg;
+(* fsm_encoding = "none" *) reg   [7:0] ap_CS_fsm;
+wire    ap_CS_fsm_state1;
+reg    internal_ap_ready;
+wire    grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadTopWidth_fu_22_ap_start;
+wire    grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadTopWidth_fu_22_ap_done;
+wire    grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadTopWidth_fu_22_ap_idle;
+wire    grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadTopWidth_fu_22_ap_ready;
+wire   [127:0] grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadTopWidth_fu_22_layer48_out_din;
+wire    grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadTopWidth_fu_22_layer48_out_write;
+wire    grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain_fu_28_ap_start;
+wire    grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain_fu_28_ap_done;
+wire    grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain_fu_28_ap_idle;
+wire    grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain_fu_28_ap_ready;
+wire   [127:0] grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain_fu_28_layer48_out_din;
+wire    grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain_fu_28_layer48_out_write;
+wire    grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain_fu_28_layer6_out_read;
+wire    grp_zeropad2d_cl_array_array_ap_fixed_8u_config48_Pipeline_PadBottomWidth_fu_36_ap_start;
+wire    grp_zeropad2d_cl_array_array_ap_fixed_8u_config48_Pipeline_PadBottomWidth_fu_36_ap_done;
+wire    grp_zeropad2d_cl_array_array_ap_fixed_8u_config48_Pipeline_PadBottomWidth_fu_36_ap_idle;
+wire    grp_zeropad2d_cl_array_array_ap_fixed_8u_config48_Pipeline_PadBottomWidth_fu_36_ap_ready;
+wire   [127:0] grp_zeropad2d_cl_array_array_ap_fixed_8u_config48_Pipeline_PadBottomWidth_fu_36_layer48_out_din;
+wire    grp_zeropad2d_cl_array_array_ap_fixed_8u_config48_Pipeline_PadBottomWidth_fu_36_layer48_out_write;
+reg    grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadTopWidth_fu_22_ap_start_reg;
+reg    ap_block_state1_ignore_call3;
+wire    ap_CS_fsm_state2;
+reg    grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain_fu_28_ap_start_reg;
+wire    ap_CS_fsm_state4;
+wire    ap_CS_fsm_state5;
+reg    grp_zeropad2d_cl_array_array_ap_fixed_8u_config48_Pipeline_PadBottomWidth_fu_36_ap_start_reg;
+wire    ap_CS_fsm_state7;
+wire    ap_CS_fsm_state8;
+reg   [7:0] ap_NS_fsm;
+reg    ap_block_state1;
+reg    ap_ST_fsm_state1_blk;
+reg    ap_ST_fsm_state2_blk;
+wire    ap_ST_fsm_state3_blk;
+wire    ap_ST_fsm_state4_blk;
+reg    ap_ST_fsm_state5_blk;
+wire    ap_ST_fsm_state6_blk;
+wire    ap_ST_fsm_state7_blk;
+reg    ap_ST_fsm_state8_blk;
+wire    ap_ce_reg;
+
+// power-on initialization
+initial begin
+#0 start_once_reg = 1'b0;
+#0 ap_done_reg = 1'b0;
+#0 ap_CS_fsm = 8'd1;
+#0 grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadTopWidth_fu_22_ap_start_reg = 1'b0;
+#0 grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain_fu_28_ap_start_reg = 1'b0;
+#0 grp_zeropad2d_cl_array_array_ap_fixed_8u_config48_Pipeline_PadBottomWidth_fu_36_ap_start_reg = 1'b0;
+end
+
+myproject_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadTopWidth grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadTopWidth_fu_22(
+    .ap_clk(ap_clk),
+    .ap_rst(ap_rst),
+    .ap_start(grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadTopWidth_fu_22_ap_start),
+    .ap_done(grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadTopWidth_fu_22_ap_done),
+    .ap_idle(grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadTopWidth_fu_22_ap_idle),
+    .ap_ready(grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadTopWidth_fu_22_ap_ready),
+    .layer48_out_din(grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadTopWidth_fu_22_layer48_out_din),
+    .layer48_out_num_data_valid(12'd0),
+    .layer48_out_fifo_cap(12'd0),
+    .layer48_out_full_n(layer48_out_full_n),
+    .layer48_out_write(grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadTopWidth_fu_22_layer48_out_write)
+);
+
+myproject_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain_fu_28(
+    .ap_clk(ap_clk),
+    .ap_rst(ap_rst),
+    .ap_start(grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain_fu_28_ap_start),
+    .ap_done(grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain_fu_28_ap_done),
+    .ap_idle(grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain_fu_28_ap_idle),
+    .ap_ready(grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain_fu_28_ap_ready),
+    .layer48_out_din(grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain_fu_28_layer48_out_din),
+    .layer48_out_num_data_valid(12'd0),
+    .layer48_out_fifo_cap(12'd0),
+    .layer48_out_full_n(layer48_out_full_n),
+    .layer48_out_write(grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain_fu_28_layer48_out_write),
+    .layer6_out_dout(layer6_out_dout),
+    .layer6_out_num_data_valid(11'd0),
+    .layer6_out_fifo_cap(11'd0),
+    .layer6_out_empty_n(layer6_out_empty_n),
+    .layer6_out_read(grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain_fu_28_layer6_out_read)
+);
+
+myproject_zeropad2d_cl_array_array_ap_fixed_8u_config48_Pipeline_PadBottomWidth grp_zeropad2d_cl_array_array_ap_fixed_8u_config48_Pipeline_PadBottomWidth_fu_36(
+    .ap_clk(ap_clk),
+    .ap_rst(ap_rst),
+    .ap_start(grp_zeropad2d_cl_array_array_ap_fixed_8u_config48_Pipeline_PadBottomWidth_fu_36_ap_start),
+    .ap_done(grp_zeropad2d_cl_array_array_ap_fixed_8u_config48_Pipeline_PadBottomWidth_fu_36_ap_done),
+    .ap_idle(grp_zeropad2d_cl_array_array_ap_fixed_8u_config48_Pipeline_PadBottomWidth_fu_36_ap_idle),
+    .ap_ready(grp_zeropad2d_cl_array_array_ap_fixed_8u_config48_Pipeline_PadBottomWidth_fu_36_ap_ready),
+    .layer48_out_din(grp_zeropad2d_cl_array_array_ap_fixed_8u_config48_Pipeline_PadBottomWidth_fu_36_layer48_out_din),
+    .layer48_out_num_data_valid(12'd0),
+    .layer48_out_fifo_cap(12'd0),
+    .layer48_out_full_n(layer48_out_full_n),
+    .layer48_out_write(grp_zeropad2d_cl_array_array_ap_fixed_8u_config48_Pipeline_PadBottomWidth_fu_36_layer48_out_write)
+);
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_CS_fsm <= ap_ST_fsm_state1;
+    end else begin
+        ap_CS_fsm <= ap_NS_fsm;
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        ap_done_reg <= 1'b0;
+    end else begin
+        if ((ap_continue == 1'b1)) begin
+            ap_done_reg <= 1'b0;
+        end else if (((grp_zeropad2d_cl_array_array_ap_fixed_8u_config48_Pipeline_PadBottomWidth_fu_36_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state8))) begin
+            ap_done_reg <= 1'b1;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain_fu_28_ap_start_reg <= 1'b0;
+    end else begin
+        if ((1'b1 == ap_CS_fsm_state4)) begin
+            grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain_fu_28_ap_start_reg <= 1'b1;
+        end else if ((grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain_fu_28_ap_ready == 1'b1)) begin
+            grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain_fu_28_ap_start_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadTopWidth_fu_22_ap_start_reg <= 1'b0;
+    end else begin
+        if (((1'b1 == ap_CS_fsm_state1) & (1'b0 == ap_block_state1_ignore_call3))) begin
+            grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadTopWidth_fu_22_ap_start_reg <= 1'b1;
+        end else if ((grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadTopWidth_fu_22_ap_ready == 1'b1)) begin
+            grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadTopWidth_fu_22_ap_start_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        grp_zeropad2d_cl_array_array_ap_fixed_8u_config48_Pipeline_PadBottomWidth_fu_36_ap_start_reg <= 1'b0;
+    end else begin
+        if ((1'b1 == ap_CS_fsm_state7)) begin
+            grp_zeropad2d_cl_array_array_ap_fixed_8u_config48_Pipeline_PadBottomWidth_fu_36_ap_start_reg <= 1'b1;
+        end else if ((grp_zeropad2d_cl_array_array_ap_fixed_8u_config48_Pipeline_PadBottomWidth_fu_36_ap_ready == 1'b1)) begin
+            grp_zeropad2d_cl_array_array_ap_fixed_8u_config48_Pipeline_PadBottomWidth_fu_36_ap_start_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (posedge ap_clk) begin
+    if (ap_rst == 1'b1) begin
+        start_once_reg <= 1'b0;
+    end else begin
+        if (((internal_ap_ready == 1'b0) & (real_start == 1'b1))) begin
+            start_once_reg <= 1'b1;
+        end else if ((internal_ap_ready == 1'b1)) begin
+            start_once_reg <= 1'b0;
+        end
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_block_state1)) begin
+        ap_ST_fsm_state1_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state1_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadTopWidth_fu_22_ap_done == 1'b0)) begin
+        ap_ST_fsm_state2_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state2_blk = 1'b0;
+    end
+end
+
+assign ap_ST_fsm_state3_blk = 1'b0;
+
+assign ap_ST_fsm_state4_blk = 1'b0;
+
+always @ (*) begin
+    if ((grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain_fu_28_ap_done == 1'b0)) begin
+        ap_ST_fsm_state5_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state5_blk = 1'b0;
+    end
+end
+
+assign ap_ST_fsm_state6_blk = 1'b0;
+
+assign ap_ST_fsm_state7_blk = 1'b0;
+
+always @ (*) begin
+    if ((grp_zeropad2d_cl_array_array_ap_fixed_8u_config48_Pipeline_PadBottomWidth_fu_36_ap_done == 1'b0)) begin
+        ap_ST_fsm_state8_blk = 1'b1;
+    end else begin
+        ap_ST_fsm_state8_blk = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((grp_zeropad2d_cl_array_array_ap_fixed_8u_config48_Pipeline_PadBottomWidth_fu_36_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state8))) begin
+        ap_done = 1'b1;
+    end else begin
+        ap_done = ap_done_reg;
+    end
+end
+
+always @ (*) begin
+    if (((1'b1 == ap_CS_fsm_state1) & (real_start == 1'b0))) begin
+        ap_idle = 1'b1;
+    end else begin
+        ap_idle = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((grp_zeropad2d_cl_array_array_ap_fixed_8u_config48_Pipeline_PadBottomWidth_fu_36_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state8))) begin
+        internal_ap_ready = 1'b1;
+    end else begin
+        internal_ap_ready = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state8)) begin
+        layer48_out_din = grp_zeropad2d_cl_array_array_ap_fixed_8u_config48_Pipeline_PadBottomWidth_fu_36_layer48_out_din;
+    end else if ((1'b1 == ap_CS_fsm_state5)) begin
+        layer48_out_din = grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain_fu_28_layer48_out_din;
+    end else if ((1'b1 == ap_CS_fsm_state2)) begin
+        layer48_out_din = grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadTopWidth_fu_22_layer48_out_din;
+    end else begin
+        layer48_out_din = grp_zeropad2d_cl_array_array_ap_fixed_8u_config48_Pipeline_PadBottomWidth_fu_36_layer48_out_din;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state8)) begin
+        layer48_out_write = grp_zeropad2d_cl_array_array_ap_fixed_8u_config48_Pipeline_PadBottomWidth_fu_36_layer48_out_write;
+    end else if ((1'b1 == ap_CS_fsm_state5)) begin
+        layer48_out_write = grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain_fu_28_layer48_out_write;
+    end else if ((1'b1 == ap_CS_fsm_state2)) begin
+        layer48_out_write = grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadTopWidth_fu_22_layer48_out_write;
+    end else begin
+        layer48_out_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if ((1'b1 == ap_CS_fsm_state5)) begin
+        layer6_out_read = grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain_fu_28_layer6_out_read;
+    end else begin
+        layer6_out_read = 1'b0;
+    end
+end
+
+always @ (*) begin
+    if (((start_once_reg == 1'b0) & (start_full_n == 1'b0))) begin
+        real_start = 1'b0;
+    end else begin
+        real_start = ap_start;
+    end
+end
+
+always @ (*) begin
+    if (((start_once_reg == 1'b0) & (real_start == 1'b1))) begin
+        start_write = 1'b1;
+    end else begin
+        start_write = 1'b0;
+    end
+end
+
+always @ (*) begin
+    case (ap_CS_fsm)
+        ap_ST_fsm_state1 : begin
+            if (((1'b1 == ap_CS_fsm_state1) & (1'b0 == ap_block_state1))) begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end
+        end
+        ap_ST_fsm_state2 : begin
+            if (((grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadTopWidth_fu_22_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state2))) begin
+                ap_NS_fsm = ap_ST_fsm_state3;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state2;
+            end
+        end
+        ap_ST_fsm_state3 : begin
+            ap_NS_fsm = ap_ST_fsm_state4;
+        end
+        ap_ST_fsm_state4 : begin
+            ap_NS_fsm = ap_ST_fsm_state5;
+        end
+        ap_ST_fsm_state5 : begin
+            if (((grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain_fu_28_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state5))) begin
+                ap_NS_fsm = ap_ST_fsm_state6;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state5;
+            end
+        end
+        ap_ST_fsm_state6 : begin
+            ap_NS_fsm = ap_ST_fsm_state7;
+        end
+        ap_ST_fsm_state7 : begin
+            ap_NS_fsm = ap_ST_fsm_state8;
+        end
+        ap_ST_fsm_state8 : begin
+            if (((grp_zeropad2d_cl_array_array_ap_fixed_8u_config48_Pipeline_PadBottomWidth_fu_36_ap_done == 1'b1) & (1'b1 == ap_CS_fsm_state8))) begin
+                ap_NS_fsm = ap_ST_fsm_state1;
+            end else begin
+                ap_NS_fsm = ap_ST_fsm_state8;
+            end
+        end
+        default : begin
+            ap_NS_fsm = 'bx;
+        end
+    endcase
+end
+
+assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
+
+assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
+
+assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3];
+
+assign ap_CS_fsm_state5 = ap_CS_fsm[32'd4];
+
+assign ap_CS_fsm_state7 = ap_CS_fsm[32'd6];
+
+assign ap_CS_fsm_state8 = ap_CS_fsm[32'd7];
+
+always @ (*) begin
+    ap_block_state1 = ((ap_done_reg == 1'b1) | (real_start == 1'b0));
+end
+
+always @ (*) begin
+    ap_block_state1_ignore_call3 = ((ap_done_reg == 1'b1) | (real_start == 1'b0));
+end
+
+assign ap_ready = internal_ap_ready;
+
+assign grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain_fu_28_ap_start = grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadMain_fu_28_ap_start_reg;
+
+assign grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadTopWidth_fu_22_ap_start = grp_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_8u_config48_Pipeline_PadTopWidth_fu_22_ap_start_reg;
+
+assign grp_zeropad2d_cl_array_array_ap_fixed_8u_config48_Pipeline_PadBottomWidth_fu_36_ap_start = grp_zeropad2d_cl_array_array_ap_fixed_8u_config48_Pipeline_PadBottomWidth_fu_36_ap_start_reg;
+
+assign start_out = real_start;
+
+endmodule //myproject_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config48_s