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myproject_prj/solution1/.autopilot/db/vhdl/myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_w4_ROMvdy.vhd

@@ -0,0 +1,90 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+library ieee; 
+use ieee.std_logic_1164.all; 
+use ieee.std_logic_unsigned.all;
+
+entity myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_w4_ROMvdy is 
+    generic(
+             DataWidth     : integer := 120; 
+             AddressWidth     : integer := 7; 
+             AddressRange    : integer := 72
+    ); 
+    port (
+ 
+          address0        : in std_logic_vector(AddressWidth-1 downto 0); 
+          ce0             : in std_logic; 
+          q0              : out std_logic_vector(DataWidth-1 downto 0);
+
+          reset               : in std_logic;
+          clk                 : in std_logic
+    ); 
+end entity; 
+
+
+architecture rtl of myproject_dense_resource_rf_leq_nin_ap_fixed_ap_fixed_40_20_5_3_0_config4_mult_s_w4_ROMvdy is 
+ 
+signal address0_tmp : std_logic_vector(AddressWidth-1 downto 0); 
+
+type mem_array is array (0 to AddressRange-1) of std_logic_vector (DataWidth-1 downto 0); 
+
+signal mem0 : mem_array := (
+    0 => "111101110000000000000101111111111111010011111111100101010000000100110010111111111100111100000000100001111111111011001101", 1 => "010001100000000000110101111111111110101011111111101101111111111100110110111111100001010011111111010110101111111100110011", 2 => "001011101111111111100101000000000000010011111111110100111111111110000011111111011001000111111111101001111111111001110010", 3 => "000011001111111111011101111111111011011100000000011010011111111110101111111111111110010111111111111100011111111101110110", 
+    4 => "000100010000000000000111111111110110010100000000001010100000000100010101111111111001010100000000010001010000000010101101", 5 => "110111111111111111111010000000000110000111111111101110000000000000110100111111010101101100000001011100011111111010100110", 6 => "001110110000000000000001000000001001100100000000001111111111111111010000000000000001011100000000011100111111111010110000", 7 => "001101110000000000100110111111111011000100000000000110011111111111000010111111101100011100000000001001001111111011011000", 
+    8 => "111001111111111111100101111111111101111100000001001101100000000001111100000000010111011100000000011110110000000000000010", 9 => "010100110000000001001110111111111111010111111111111111101111111101100010000000000001110111111111001110001111111110100100", 10 => "001011110000000000011111000000000011101111111110110001011111111100110101111111111110001111111111000101110000000000011011", 11 => "000111011111111110111110000000000010100000000000110011110000000011100000111111111111001100000001000000101111111000110101", 
+    12 => "000100000000000000000001111111111010110000000000110001000000000000101010111111111010110011111111000111101111111010110010", 13 => "000011011111111110111110000000000100110011111110111000111111111101000001000000000000111100000000100100001111110101010011", 14 => "111110111111111111101001000000001000001000000000001001010000000001001001000000001110001000000000011010001111111110101100", 15 => "001001100000000001001101111111111001100000000000001010111111111111100101111111111111010000000000011110101111111100000010", 
+    16 => "111110100000000000001010000000001010001111111110111010001111111110011010111111111110101111111111110101011111111101001011", 17 => "001010010000000001010011111111111111010011111111000001011111111111000111000000010011001011111111101001011111111110000101", 18 => "001010101111111111100011000000000100111111111110110011001111111111001100000000011010100111111111101111001111111011011000", 19 => "111111111111111111000010111111111100111100000000101110010000000111100011000000000001111011111111111000011111111000010101", 
+    20 => "111110110000000000001010111111110111010011111110100011110000000001100100111111111001101000000000010010011111111111100011", 21 => "111100001111111111000101000000000100000011111111100011001111111111101111000000000010101000000000110111010000000011000010", 22 => "110010110000000000000010000000000011100000000000110001010000000010100011000000001010110011111111111000100000000011111110", 23 => "000010110000000000111010111111111111000111111111010010010000000000010100111111111101011000000000101100111111111101000110", 
+    24 => "010001001111111111111001111111111011110111111111100110101111111110010110111111110001000100000000111110101111111111001000", 25 => "010101010000000000110100111111110101001000000000000110001111111110111100111111101110000011111111011100000000000001010111", 26 => "001011001111111111101010111111111100010100000000100100001111111111001010111111100111010100000000010001101111111111101110", 27 => "000100001111111111101000111111111110001100000000011010011111110110101111000000001000101111111111001011000000000001010000", 
+    28 => "000011111111111111101010111111111100011011111111100101100000000001010111111111101000001011111111011101100000000010001110", 29 => "000101100000000000100000000000000011010111111111011101100000000000000100000000000101101000000000011011100000000000111001", 30 => "010110000000000000100000000000000111001100000000101000100000000001001100111111001000101100000000011101001111111111111101", 31 => "010101110000000001000010000000000001000100000000000000010000000000011111111111100110001111111111011111100000000011000101", 
+    32 => "010000001111111111011111000000000000101100000000101000001111111110011101000000010101001111111111100011100000000000010100", 33 => "011000000000000001100001111111111010001011111111111010111111111111111111000000001010010011111111111011110000000011110111", 34 => "010001010000000001001110000000000010100111111111101010100000000000100011000000000000000111111111010111001111111111101111", 35 => "000100001111111111101001000000000011001111111111010101101111111001011110111111101010100000000001011010110000000010001001", 
+    36 => "000101011111111111010010111111111010110100000000000100001111111111010010111111111011010100000000011111100000000001111000", 37 => "000101101111111111010110111111111000111100000000011100000000000010111011111111011100110100000000010000001111111101100011", 38 => "000110010000000000100101000000001001010100000000000000100000000000000110000000011011011100000000011010001111111111000000", 39 => "001000110000000001111101111111111101110011111111110011101111111110011000000000000110000111111111011011000000000101101101", 
+    40 => "001000101111111111110100111111111101100111111111010000111111111111011010111111100111000000000000001110010000000111100100", 41 => "000110100000000001000101111111111010011011111111010111000000000010001011000000000111010000000000010100010000000100100001", 42 => "001000000000000000001010111111111111011011111111000110100000000010011010000000010100110011111111101100011111111111000110", 43 => "000001101111111111100100000000000000000100000000110000010000000001100100000000011110100000000000101101010000000010011000", 
+    44 => "000011011111111111011001111111111010010111111111110010110000000100000010000000001001010000000000000000000000001010001101", 45 => "111011011111111111011010000000001100110111111110111100010000000110100110111111100101000000000001100011111111111110010100", 46 => "111101110000000000101101000000001110000100000000010110001111111111110010111111011101101100000000010110001111111001101100", 47 => "111011010000000001101011000000000000111011111111000110001111111011001011111111111010100111111111110110011111111111101111", 
+    48 => "000100101111111111111001111111111011010000000000101010011111111111010011000000010111100011111111011010101111111100010100", 49 => "011001010000000001100010111111111101101000000000000101111111111111001111111111101010111011111111100110000000000011000101", 50 => "000110101111111111010111000000000101101100000000010011011111111011111011111111100000011011111111101101000000000001111101", 51 => "000101101111111111101000111111111011000100000000001100000000000010001011000000101101001011111110101100011111111101010010", 
+    52 => "001000111111111111110110000000000001000000000000011001101111111101011100000000100100011111111110110101110000000011011010", 53 => "001010011111111111101101111111111111110000000000000110111111111111011001111111100100010000000000111001000000000011011000", 54 => "001100001111111111100001000000000111100000000000001101100000000010010001111111000101000111111111110101000000000011011111", 55 => "001010111111111111111110000000000111010000000000000010101111111110111100111111101101000111111110111110001111111101110111", 
+    56 => "001101011111111111011011111111111010111000000000010001000000000001001000111111101111011011111111001111111111111110000001", 57 => "010000010000000010000010111111111100100111111111110001011111111111010001111111111100100111111111111000010000000010100001", 58 => "111001010000000000010101000000000110111111111111111111101111111101001001000000000010011111111111101010000000001000000010", 59 => "001100101111111101111000000000000001111100000000011101100000000000100001000000001010010111111110101010001111110110111001", 
+    60 => "001110110000000000001111111111111011111000000000010000010000000000000101111111110001111000000000010101001111111011110001", 61 => "001110011111111101110101111111111001101011111111111011001111111110011011111111110010001100000001000000111111110110110001", 62 => "111011011111111111100100000000000111001100000000011001110000000010000110000000100111000111111111001001110000000111110000", 63 => "000111110000000000010101000000000000101011111111100110001111111101101000111111110101011111111111011111001111111100110011", 
+    64 => "001000011111111111011011111111111110001011111110110100111111111001101101111111110100110100000000110110101111111011000111", 65 => "111101100000000001110101111111111101111111111111011110000000000000011110000000000110001011111111111101010000000010111101", 66 => "110111011111111111010110000000001000100111111111110000100000000000010101000000010011011111111111011001000000000001010101", 67 => "001011001111111101101000111111111001011100000000000100100000000111011000000000001011000111111111011011001111110111111000", 
+    68 => "001010111111111111110110111111111001110011111111010000100000000000110011000000010101001100000000011000001111111111100110", 69 => "111010011111111101010000000000001000000011111111011001010000000001000111111111111011000100000000101010010000000011011000", 70 => "110100110000000000011111000000000111001000000000100100000000000001100000111111011111101011111111101001011111111101000100", 71 => "111100100000000000100110000000000010100011111110101011101111111000000100111111110100100100000000001001111111111010111000");
+
+
+
+attribute syn_rom_style : string;
+
+attribute syn_rom_style of mem0 : signal is "block_rom"; 
+attribute ROM_STYLE : string;
+
+attribute ROM_STYLE of mem0 : signal is "block";
+
+begin 
+
+ 
+memory_access_guard_0: process (address0) 
+begin
+      address0_tmp <= address0;
+--synthesis translate_off
+      if (CONV_INTEGER(address0) > AddressRange-1) then
+           address0_tmp <= (others => '0');
+      else 
+           address0_tmp <= address0;
+      end if;
+--synthesis translate_on
+end process;
+
+p_rom_access: process (clk)  
+begin 
+    if (clk'event and clk = '1') then
+ 
+        if (ce0 = '1') then  
+            q0 <= mem0(CONV_INTEGER(address0_tmp)); 
+        end if;
+
+end if;
+end process;
+
+end rtl;
+

myproject_prj/solution1/.autopilot/db/vhdl/myproject_fifo_w1024_d256_A.vhd

@@ -0,0 +1,305 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--RAW latency 2 
+ 
+entity myproject_fifo_w1024_d256_A is
+    generic (
+        MEM_STYLE         : string  := "auto";
+        DATA_WIDTH        : integer := 1024;
+        ADDR_WIDTH        : integer := 8;
+        DEPTH             : integer := 256);
+    port (
+        clk               : in  std_logic;
+        reset             : in  std_logic;
+
+        -- write
+        if_full_n         : out std_logic;
+        if_write_ce       : in  std_logic;
+        if_write          : in  std_logic;
+        if_din            : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+        -- read 
+        if_num_data_valid : out std_logic_vector(ADDR_WIDTH downto 0); -- for FRP
+        if_fifo_cap       : out std_logic_vector(ADDR_WIDTH downto 0); -- for FRP
+
+        if_empty_n        : out std_logic;
+        if_read_ce        : in  std_logic;
+        if_read           : in  std_logic;
+        if_dout           : out std_logic_vector(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture arch of myproject_fifo_w1024_d256_A is
+------------------------Task and function--------------
+    function clog2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 1;
+        m := 2;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function clog2;
+    ------------------------Parameter----------------------
+    constant MEM_DEPTH  : INTEGER := DEPTH - 1;
+    constant MEM_AWIDTH : INTEGER := clog2(MEM_DEPTH);
+    ------------------------Component----------------------
+    component myproject_fifo_w1024_d256_A_ram is
+    generic (
+        MEM_STYLE  : string  := "auto";
+        DATA_WIDTH : integer := 1024;
+        ADDR_WIDTH : integer := 8;
+        DEPTH      : integer := 256);
+    port (
+        clk        : in std_logic;
+        reset      : in std_logic;
+        we         : in std_logic;
+        waddr      : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH - 1 downto 0);
+        raddr      : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
+        rden       : in std_logic;
+        dout       : out std_logic_vector(DATA_WIDTH - 1 downto 0));
+    end component;
+------------------------Local signal-------------------
+    signal waddr    : unsigned(MEM_AWIDTH - 1 downto 0) := (others => '0');
+    signal raddr    : unsigned(MEM_AWIDTH - 1 downto 0) := (others => '0');
+    signal wnext    : unsigned(MEM_AWIDTH - 1 downto 0);
+    signal rnext    : unsigned(MEM_AWIDTH - 1 downto 0);
+    signal push     : std_logic;
+    signal pop      : std_logic;
+    signal mOutPtr  : unsigned(MEM_AWIDTH downto 0) := (others => '0');
+    signal empty_n  : std_logic := '0';
+    signal full_n   : std_logic := '1';
+    -- has num_data_valid ? 
+    signal num_extra_words: UNSIGNED(0 downto 0); -- yes
+    signal num_data_valid : UNSIGNED(ADDR_WIDTH downto 0); -- yes 
+
+    signal pop_dout : std_logic;
+    signal num_data_cnt : UNSIGNED(ADDR_WIDTH downto 0);
+    signal dout_vld : std_logic := '0';
+begin
+----------------------- Instantiation -----------------------
+    U_myproject_fifo_w1024_d256_A_ram : myproject_fifo_w1024_d256_A_ram
+    generic map (
+        MEM_STYLE  => MEM_STYLE,
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => MEM_AWIDTH,
+        DEPTH => MEM_DEPTH)
+    port map (
+        clk   => clk,
+        reset => reset,
+        we    => push,
+        waddr => std_logic_vector(waddr),
+        din   => if_din,
+        raddr => std_logic_vector(raddr),
+        rden  => pop,
+        dout  => if_dout);
+
+--------------------------- Body ----------------------------
+    -- has num_data_valid ?  
+    if_num_data_valid <= STD_LOGIC_VECTOR(num_data_valid); -- yes
+    if_fifo_cap       <= STD_LOGIC_VECTOR(TO_UNSIGNED(DEPTH, ADDR_WIDTH + 1)); -- yes 
+
+    -- almost full/empty  
+
+    -- program full/empty  
+    
+    if_full_n  <= full_n;
+    if_empty_n <= dout_vld;
+
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and (not dout_vld or pop_dout);
+    pop_dout   <= dout_vld and if_read_ce and if_read;
+    
+    wnext      <= waddr           when push = '0'            else
+                  (others => '0') when waddr = MEM_DEPTH - 1 else
+                  waddr + 1;
+    rnext      <= raddr           when pop = '0'             else
+                  (others => '0') when raddr = MEM_DEPTH - 1 else
+                  raddr + 1;
+
+    -- waddr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                waddr <= (others => '0');
+            else
+                waddr <= wnext;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- raddr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                raddr <= (others => '0');
+            else
+                raddr <= rnext;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- mOutPtr
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '0');
+            elsif push = '1' and pop = '0' then
+                mOutPtr <= mOutPtr + 1;
+            elsif push = '0' and pop = '1' then
+                mOutPtr <= mOutPtr - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- full_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif push = '1' and pop_dout = '0' and num_data_cnt = DEPTH - 1 then
+                full_n <= '0';
+            elsif push = '0' and pop_dout = '1' then
+                full_n <= '1';
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif push = '1' and pop = '0' then
+                empty_n <= '1';
+            elsif push = '0' and pop = '1' and mOutPtr = 1 then
+                empty_n <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- almost_full_n
+
+    -- almost_empty_n
+
+    -- prog_full_n 
+
+    -- prog_empty_n 
+
+    -- num_data_cnt
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                num_data_cnt <= (others => '0');
+            elsif push = '1' and pop_dout = '0' then
+                num_data_cnt <= num_data_cnt + 1;
+            elsif push = '0' and pop_dout = '1' then
+                num_data_cnt <= num_data_cnt - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- num_data_valid  
+    num_extra_words <= TO_UNSIGNED(1,1) when (dout_vld and not pop_dout) = '1' else (others=>'0');
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                num_data_valid <= (others => '0');
+            elsif (empty_n or (dout_vld and not pop_dout)) = '1' then
+                if (push = '1') then
+                    num_data_valid <= RESIZE(mOutPtr, ADDR_WIDTH + 1) + 1 + num_extra_words;
+                else
+                    num_data_valid <= RESIZE(mOutPtr, ADDR_WIDTH + 1) + num_extra_words;
+                end if;
+            else
+                num_data_valid <= RESIZE(num_extra_words, ADDR_WIDTH + 1);
+            end if;
+        end if; -- sync end 
+    end process; -- 
+
+    -- dout_vld
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_vld <= '0';
+            elsif pop = '1' then
+                dout_vld <= '1';
+            elsif pop_dout = '1' then
+                dout_vld <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+end architecture;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity myproject_fifo_w1024_d256_A_ram is
+    generic (
+        MEM_STYLE   : string  := "auto";
+        DATA_WIDTH  : integer := 1024;
+        ADDR_WIDTH  : integer := 8;
+        DEPTH       : integer := 256);
+    port (
+        clk         : in std_logic;
+        reset       : in std_logic;
+        we          : in std_logic;
+        waddr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din         : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        raddr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        rden        : in std_logic;
+        dout        : out std_logic_vector(DATA_WIDTH-1 downto 0)
+    );
+end entity;
+
+architecture arch of myproject_fifo_w1024_d256_A_ram is
+    type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
+    signal mem : memtype;
+    attribute ram_style: string;
+    attribute ram_style of mem: signal is MEM_STYLE;
+    signal mem_reg  : std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+begin
+    dout <= mem_reg;
+
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mem_reg <= ( others=> '0');
+            elsif (rden = '1') then
+                mem_reg <= mem(conv_integer(raddr));
+            end if;
+        end if; -- sync end 
+    end process;
+
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if we = '1' then
+                mem(conv_integer(waddr)) <= din;
+            end if;
+        end if;
+    end process;
+
+end architecture;

myproject_prj/solution1/.autopilot/db/vhdl/myproject_fifo_w1344_d256_A.vhd

@@ -0,0 +1,305 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--RAW latency 2 
+ 
+entity myproject_fifo_w1344_d256_A is
+    generic (
+        MEM_STYLE         : string  := "auto";
+        DATA_WIDTH        : integer := 1344;
+        ADDR_WIDTH        : integer := 8;
+        DEPTH             : integer := 256);
+    port (
+        clk               : in  std_logic;
+        reset             : in  std_logic;
+
+        -- write
+        if_full_n         : out std_logic;
+        if_write_ce       : in  std_logic;
+        if_write          : in  std_logic;
+        if_din            : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+        -- read 
+        if_num_data_valid : out std_logic_vector(ADDR_WIDTH downto 0); -- for FRP
+        if_fifo_cap       : out std_logic_vector(ADDR_WIDTH downto 0); -- for FRP
+
+        if_empty_n        : out std_logic;
+        if_read_ce        : in  std_logic;
+        if_read           : in  std_logic;
+        if_dout           : out std_logic_vector(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture arch of myproject_fifo_w1344_d256_A is
+------------------------Task and function--------------
+    function clog2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 1;
+        m := 2;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function clog2;
+    ------------------------Parameter----------------------
+    constant MEM_DEPTH  : INTEGER := DEPTH - 1;
+    constant MEM_AWIDTH : INTEGER := clog2(MEM_DEPTH);
+    ------------------------Component----------------------
+    component myproject_fifo_w1344_d256_A_ram is
+    generic (
+        MEM_STYLE  : string  := "auto";
+        DATA_WIDTH : integer := 1344;
+        ADDR_WIDTH : integer := 8;
+        DEPTH      : integer := 256);
+    port (
+        clk        : in std_logic;
+        reset      : in std_logic;
+        we         : in std_logic;
+        waddr      : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH - 1 downto 0);
+        raddr      : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
+        rden       : in std_logic;
+        dout       : out std_logic_vector(DATA_WIDTH - 1 downto 0));
+    end component;
+------------------------Local signal-------------------
+    signal waddr    : unsigned(MEM_AWIDTH - 1 downto 0) := (others => '0');
+    signal raddr    : unsigned(MEM_AWIDTH - 1 downto 0) := (others => '0');
+    signal wnext    : unsigned(MEM_AWIDTH - 1 downto 0);
+    signal rnext    : unsigned(MEM_AWIDTH - 1 downto 0);
+    signal push     : std_logic;
+    signal pop      : std_logic;
+    signal mOutPtr  : unsigned(MEM_AWIDTH downto 0) := (others => '0');
+    signal empty_n  : std_logic := '0';
+    signal full_n   : std_logic := '1';
+    -- has num_data_valid ? 
+    signal num_extra_words: UNSIGNED(0 downto 0); -- yes
+    signal num_data_valid : UNSIGNED(ADDR_WIDTH downto 0); -- yes 
+
+    signal pop_dout : std_logic;
+    signal num_data_cnt : UNSIGNED(ADDR_WIDTH downto 0);
+    signal dout_vld : std_logic := '0';
+begin
+----------------------- Instantiation -----------------------
+    U_myproject_fifo_w1344_d256_A_ram : myproject_fifo_w1344_d256_A_ram
+    generic map (
+        MEM_STYLE  => MEM_STYLE,
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => MEM_AWIDTH,
+        DEPTH => MEM_DEPTH)
+    port map (
+        clk   => clk,
+        reset => reset,
+        we    => push,
+        waddr => std_logic_vector(waddr),
+        din   => if_din,
+        raddr => std_logic_vector(raddr),
+        rden  => pop,
+        dout  => if_dout);
+
+--------------------------- Body ----------------------------
+    -- has num_data_valid ?  
+    if_num_data_valid <= STD_LOGIC_VECTOR(num_data_valid); -- yes
+    if_fifo_cap       <= STD_LOGIC_VECTOR(TO_UNSIGNED(DEPTH, ADDR_WIDTH + 1)); -- yes 
+
+    -- almost full/empty  
+
+    -- program full/empty  
+    
+    if_full_n  <= full_n;
+    if_empty_n <= dout_vld;
+
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and (not dout_vld or pop_dout);
+    pop_dout   <= dout_vld and if_read_ce and if_read;
+    
+    wnext      <= waddr           when push = '0'            else
+                  (others => '0') when waddr = MEM_DEPTH - 1 else
+                  waddr + 1;
+    rnext      <= raddr           when pop = '0'             else
+                  (others => '0') when raddr = MEM_DEPTH - 1 else
+                  raddr + 1;
+
+    -- waddr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                waddr <= (others => '0');
+            else
+                waddr <= wnext;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- raddr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                raddr <= (others => '0');
+            else
+                raddr <= rnext;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- mOutPtr
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '0');
+            elsif push = '1' and pop = '0' then
+                mOutPtr <= mOutPtr + 1;
+            elsif push = '0' and pop = '1' then
+                mOutPtr <= mOutPtr - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- full_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif push = '1' and pop_dout = '0' and num_data_cnt = DEPTH - 1 then
+                full_n <= '0';
+            elsif push = '0' and pop_dout = '1' then
+                full_n <= '1';
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif push = '1' and pop = '0' then
+                empty_n <= '1';
+            elsif push = '0' and pop = '1' and mOutPtr = 1 then
+                empty_n <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- almost_full_n
+
+    -- almost_empty_n
+
+    -- prog_full_n 
+
+    -- prog_empty_n 
+
+    -- num_data_cnt
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                num_data_cnt <= (others => '0');
+            elsif push = '1' and pop_dout = '0' then
+                num_data_cnt <= num_data_cnt + 1;
+            elsif push = '0' and pop_dout = '1' then
+                num_data_cnt <= num_data_cnt - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- num_data_valid  
+    num_extra_words <= TO_UNSIGNED(1,1) when (dout_vld and not pop_dout) = '1' else (others=>'0');
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                num_data_valid <= (others => '0');
+            elsif (empty_n or (dout_vld and not pop_dout)) = '1' then
+                if (push = '1') then
+                    num_data_valid <= RESIZE(mOutPtr, ADDR_WIDTH + 1) + 1 + num_extra_words;
+                else
+                    num_data_valid <= RESIZE(mOutPtr, ADDR_WIDTH + 1) + num_extra_words;
+                end if;
+            else
+                num_data_valid <= RESIZE(num_extra_words, ADDR_WIDTH + 1);
+            end if;
+        end if; -- sync end 
+    end process; -- 
+
+    -- dout_vld
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_vld <= '0';
+            elsif pop = '1' then
+                dout_vld <= '1';
+            elsif pop_dout = '1' then
+                dout_vld <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+end architecture;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity myproject_fifo_w1344_d256_A_ram is
+    generic (
+        MEM_STYLE   : string  := "auto";
+        DATA_WIDTH  : integer := 1344;
+        ADDR_WIDTH  : integer := 8;
+        DEPTH       : integer := 256);
+    port (
+        clk         : in std_logic;
+        reset       : in std_logic;
+        we          : in std_logic;
+        waddr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din         : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        raddr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        rden        : in std_logic;
+        dout        : out std_logic_vector(DATA_WIDTH-1 downto 0)
+    );
+end entity;
+
+architecture arch of myproject_fifo_w1344_d256_A_ram is
+    type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
+    signal mem : memtype;
+    attribute ram_style: string;
+    attribute ram_style of mem: signal is MEM_STYLE;
+    signal mem_reg  : std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+begin
+    dout <= mem_reg;
+
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mem_reg <= ( others=> '0');
+            elsif (rden = '1') then
+                mem_reg <= mem(conv_integer(raddr));
+            end if;
+        end if; -- sync end 
+    end process;
+
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if we = '1' then
+                mem(conv_integer(waddr)) <= din;
+            end if;
+        end if;
+    end process;
+
+end architecture;

myproject_prj/solution1/.autopilot/db/vhdl/myproject_fifo_w1536_d256_A.vhd

@@ -0,0 +1,305 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--RAW latency 2 
+ 
+entity myproject_fifo_w1536_d256_A is
+    generic (
+        MEM_STYLE         : string  := "auto";
+        DATA_WIDTH        : integer := 1536;
+        ADDR_WIDTH        : integer := 8;
+        DEPTH             : integer := 256);
+    port (
+        clk               : in  std_logic;
+        reset             : in  std_logic;
+
+        -- write
+        if_full_n         : out std_logic;
+        if_write_ce       : in  std_logic;
+        if_write          : in  std_logic;
+        if_din            : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+        -- read 
+        if_num_data_valid : out std_logic_vector(ADDR_WIDTH downto 0); -- for FRP
+        if_fifo_cap       : out std_logic_vector(ADDR_WIDTH downto 0); -- for FRP
+
+        if_empty_n        : out std_logic;
+        if_read_ce        : in  std_logic;
+        if_read           : in  std_logic;
+        if_dout           : out std_logic_vector(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture arch of myproject_fifo_w1536_d256_A is
+------------------------Task and function--------------
+    function clog2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 1;
+        m := 2;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function clog2;
+    ------------------------Parameter----------------------
+    constant MEM_DEPTH  : INTEGER := DEPTH - 1;
+    constant MEM_AWIDTH : INTEGER := clog2(MEM_DEPTH);
+    ------------------------Component----------------------
+    component myproject_fifo_w1536_d256_A_ram is
+    generic (
+        MEM_STYLE  : string  := "auto";
+        DATA_WIDTH : integer := 1536;
+        ADDR_WIDTH : integer := 8;
+        DEPTH      : integer := 256);
+    port (
+        clk        : in std_logic;
+        reset      : in std_logic;
+        we         : in std_logic;
+        waddr      : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH - 1 downto 0);
+        raddr      : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
+        rden       : in std_logic;
+        dout       : out std_logic_vector(DATA_WIDTH - 1 downto 0));
+    end component;
+------------------------Local signal-------------------
+    signal waddr    : unsigned(MEM_AWIDTH - 1 downto 0) := (others => '0');
+    signal raddr    : unsigned(MEM_AWIDTH - 1 downto 0) := (others => '0');
+    signal wnext    : unsigned(MEM_AWIDTH - 1 downto 0);
+    signal rnext    : unsigned(MEM_AWIDTH - 1 downto 0);
+    signal push     : std_logic;
+    signal pop      : std_logic;
+    signal mOutPtr  : unsigned(MEM_AWIDTH downto 0) := (others => '0');
+    signal empty_n  : std_logic := '0';
+    signal full_n   : std_logic := '1';
+    -- has num_data_valid ? 
+    signal num_extra_words: UNSIGNED(0 downto 0); -- yes
+    signal num_data_valid : UNSIGNED(ADDR_WIDTH downto 0); -- yes 
+
+    signal pop_dout : std_logic;
+    signal num_data_cnt : UNSIGNED(ADDR_WIDTH downto 0);
+    signal dout_vld : std_logic := '0';
+begin
+----------------------- Instantiation -----------------------
+    U_myproject_fifo_w1536_d256_A_ram : myproject_fifo_w1536_d256_A_ram
+    generic map (
+        MEM_STYLE  => MEM_STYLE,
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => MEM_AWIDTH,
+        DEPTH => MEM_DEPTH)
+    port map (
+        clk   => clk,
+        reset => reset,
+        we    => push,
+        waddr => std_logic_vector(waddr),
+        din   => if_din,
+        raddr => std_logic_vector(raddr),
+        rden  => pop,
+        dout  => if_dout);
+
+--------------------------- Body ----------------------------
+    -- has num_data_valid ?  
+    if_num_data_valid <= STD_LOGIC_VECTOR(num_data_valid); -- yes
+    if_fifo_cap       <= STD_LOGIC_VECTOR(TO_UNSIGNED(DEPTH, ADDR_WIDTH + 1)); -- yes 
+
+    -- almost full/empty  
+
+    -- program full/empty  
+    
+    if_full_n  <= full_n;
+    if_empty_n <= dout_vld;
+
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and (not dout_vld or pop_dout);
+    pop_dout   <= dout_vld and if_read_ce and if_read;
+    
+    wnext      <= waddr           when push = '0'            else
+                  (others => '0') when waddr = MEM_DEPTH - 1 else
+                  waddr + 1;
+    rnext      <= raddr           when pop = '0'             else
+                  (others => '0') when raddr = MEM_DEPTH - 1 else
+                  raddr + 1;
+
+    -- waddr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                waddr <= (others => '0');
+            else
+                waddr <= wnext;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- raddr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                raddr <= (others => '0');
+            else
+                raddr <= rnext;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- mOutPtr
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '0');
+            elsif push = '1' and pop = '0' then
+                mOutPtr <= mOutPtr + 1;
+            elsif push = '0' and pop = '1' then
+                mOutPtr <= mOutPtr - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- full_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif push = '1' and pop_dout = '0' and num_data_cnt = DEPTH - 1 then
+                full_n <= '0';
+            elsif push = '0' and pop_dout = '1' then
+                full_n <= '1';
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif push = '1' and pop = '0' then
+                empty_n <= '1';
+            elsif push = '0' and pop = '1' and mOutPtr = 1 then
+                empty_n <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- almost_full_n
+
+    -- almost_empty_n
+
+    -- prog_full_n 
+
+    -- prog_empty_n 
+
+    -- num_data_cnt
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                num_data_cnt <= (others => '0');
+            elsif push = '1' and pop_dout = '0' then
+                num_data_cnt <= num_data_cnt + 1;
+            elsif push = '0' and pop_dout = '1' then
+                num_data_cnt <= num_data_cnt - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- num_data_valid  
+    num_extra_words <= TO_UNSIGNED(1,1) when (dout_vld and not pop_dout) = '1' else (others=>'0');
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                num_data_valid <= (others => '0');
+            elsif (empty_n or (dout_vld and not pop_dout)) = '1' then
+                if (push = '1') then
+                    num_data_valid <= RESIZE(mOutPtr, ADDR_WIDTH + 1) + 1 + num_extra_words;
+                else
+                    num_data_valid <= RESIZE(mOutPtr, ADDR_WIDTH + 1) + num_extra_words;
+                end if;
+            else
+                num_data_valid <= RESIZE(num_extra_words, ADDR_WIDTH + 1);
+            end if;
+        end if; -- sync end 
+    end process; -- 
+
+    -- dout_vld
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_vld <= '0';
+            elsif pop = '1' then
+                dout_vld <= '1';
+            elsif pop_dout = '1' then
+                dout_vld <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+end architecture;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity myproject_fifo_w1536_d256_A_ram is
+    generic (
+        MEM_STYLE   : string  := "auto";
+        DATA_WIDTH  : integer := 1536;
+        ADDR_WIDTH  : integer := 8;
+        DEPTH       : integer := 256);
+    port (
+        clk         : in std_logic;
+        reset       : in std_logic;
+        we          : in std_logic;
+        waddr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din         : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        raddr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        rden        : in std_logic;
+        dout        : out std_logic_vector(DATA_WIDTH-1 downto 0)
+    );
+end entity;
+
+architecture arch of myproject_fifo_w1536_d256_A_ram is
+    type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
+    signal mem : memtype;
+    attribute ram_style: string;
+    attribute ram_style of mem: signal is MEM_STYLE;
+    signal mem_reg  : std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+begin
+    dout <= mem_reg;
+
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mem_reg <= ( others=> '0');
+            elsif (rden = '1') then
+                mem_reg <= mem(conv_integer(raddr));
+            end if;
+        end if; -- sync end 
+    end process;
+
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if we = '1' then
+                mem(conv_integer(waddr)) <= din;
+            end if;
+        end if;
+    end process;
+
+end architecture;

myproject_prj/solution1/.autopilot/db/vhdl/myproject_fifo_w16_d4356_A.vhd

@@ -0,0 +1,305 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--RAW latency 2 
+ 
+entity myproject_fifo_w16_d4356_A is
+    generic (
+        MEM_STYLE         : string  := "auto";
+        DATA_WIDTH        : integer := 16;
+        ADDR_WIDTH        : integer := 13;
+        DEPTH             : integer := 4356);
+    port (
+        clk               : in  std_logic;
+        reset             : in  std_logic;
+
+        -- write
+        if_full_n         : out std_logic;
+        if_write_ce       : in  std_logic;
+        if_write          : in  std_logic;
+        if_din            : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+        -- read 
+        if_num_data_valid : out std_logic_vector(ADDR_WIDTH downto 0); -- for FRP
+        if_fifo_cap       : out std_logic_vector(ADDR_WIDTH downto 0); -- for FRP
+
+        if_empty_n        : out std_logic;
+        if_read_ce        : in  std_logic;
+        if_read           : in  std_logic;
+        if_dout           : out std_logic_vector(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture arch of myproject_fifo_w16_d4356_A is
+------------------------Task and function--------------
+    function clog2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 1;
+        m := 2;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function clog2;
+    ------------------------Parameter----------------------
+    constant MEM_DEPTH  : INTEGER := DEPTH - 1;
+    constant MEM_AWIDTH : INTEGER := clog2(MEM_DEPTH);
+    ------------------------Component----------------------
+    component myproject_fifo_w16_d4356_A_ram is
+    generic (
+        MEM_STYLE  : string  := "auto";
+        DATA_WIDTH : integer := 16;
+        ADDR_WIDTH : integer := 13;
+        DEPTH      : integer := 4356);
+    port (
+        clk        : in std_logic;
+        reset      : in std_logic;
+        we         : in std_logic;
+        waddr      : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH - 1 downto 0);
+        raddr      : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
+        rden       : in std_logic;
+        dout       : out std_logic_vector(DATA_WIDTH - 1 downto 0));
+    end component;
+------------------------Local signal-------------------
+    signal waddr    : unsigned(MEM_AWIDTH - 1 downto 0) := (others => '0');
+    signal raddr    : unsigned(MEM_AWIDTH - 1 downto 0) := (others => '0');
+    signal wnext    : unsigned(MEM_AWIDTH - 1 downto 0);
+    signal rnext    : unsigned(MEM_AWIDTH - 1 downto 0);
+    signal push     : std_logic;
+    signal pop      : std_logic;
+    signal mOutPtr  : unsigned(MEM_AWIDTH downto 0) := (others => '0');
+    signal empty_n  : std_logic := '0';
+    signal full_n   : std_logic := '1';
+    -- has num_data_valid ? 
+    signal num_extra_words: UNSIGNED(0 downto 0); -- yes
+    signal num_data_valid : UNSIGNED(ADDR_WIDTH downto 0); -- yes 
+
+    signal pop_dout : std_logic;
+    signal num_data_cnt : UNSIGNED(ADDR_WIDTH downto 0);
+    signal dout_vld : std_logic := '0';
+begin
+----------------------- Instantiation -----------------------
+    U_myproject_fifo_w16_d4356_A_ram : myproject_fifo_w16_d4356_A_ram
+    generic map (
+        MEM_STYLE  => MEM_STYLE,
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => MEM_AWIDTH,
+        DEPTH => MEM_DEPTH)
+    port map (
+        clk   => clk,
+        reset => reset,
+        we    => push,
+        waddr => std_logic_vector(waddr),
+        din   => if_din,
+        raddr => std_logic_vector(raddr),
+        rden  => pop,
+        dout  => if_dout);
+
+--------------------------- Body ----------------------------
+    -- has num_data_valid ?  
+    if_num_data_valid <= STD_LOGIC_VECTOR(num_data_valid); -- yes
+    if_fifo_cap       <= STD_LOGIC_VECTOR(TO_UNSIGNED(DEPTH, ADDR_WIDTH + 1)); -- yes 
+
+    -- almost full/empty  
+
+    -- program full/empty  
+    
+    if_full_n  <= full_n;
+    if_empty_n <= dout_vld;
+
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and (not dout_vld or pop_dout);
+    pop_dout   <= dout_vld and if_read_ce and if_read;
+    
+    wnext      <= waddr           when push = '0'            else
+                  (others => '0') when waddr = MEM_DEPTH - 1 else
+                  waddr + 1;
+    rnext      <= raddr           when pop = '0'             else
+                  (others => '0') when raddr = MEM_DEPTH - 1 else
+                  raddr + 1;
+
+    -- waddr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                waddr <= (others => '0');
+            else
+                waddr <= wnext;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- raddr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                raddr <= (others => '0');
+            else
+                raddr <= rnext;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- mOutPtr
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '0');
+            elsif push = '1' and pop = '0' then
+                mOutPtr <= mOutPtr + 1;
+            elsif push = '0' and pop = '1' then
+                mOutPtr <= mOutPtr - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- full_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif push = '1' and pop_dout = '0' and num_data_cnt = DEPTH - 1 then
+                full_n <= '0';
+            elsif push = '0' and pop_dout = '1' then
+                full_n <= '1';
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif push = '1' and pop = '0' then
+                empty_n <= '1';
+            elsif push = '0' and pop = '1' and mOutPtr = 1 then
+                empty_n <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- almost_full_n
+
+    -- almost_empty_n
+
+    -- prog_full_n 
+
+    -- prog_empty_n 
+
+    -- num_data_cnt
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                num_data_cnt <= (others => '0');
+            elsif push = '1' and pop_dout = '0' then
+                num_data_cnt <= num_data_cnt + 1;
+            elsif push = '0' and pop_dout = '1' then
+                num_data_cnt <= num_data_cnt - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- num_data_valid  
+    num_extra_words <= TO_UNSIGNED(1,1) when (dout_vld and not pop_dout) = '1' else (others=>'0');
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                num_data_valid <= (others => '0');
+            elsif (empty_n or (dout_vld and not pop_dout)) = '1' then
+                if (push = '1') then
+                    num_data_valid <= RESIZE(mOutPtr, ADDR_WIDTH + 1) + 1 + num_extra_words;
+                else
+                    num_data_valid <= RESIZE(mOutPtr, ADDR_WIDTH + 1) + num_extra_words;
+                end if;
+            else
+                num_data_valid <= RESIZE(num_extra_words, ADDR_WIDTH + 1);
+            end if;
+        end if; -- sync end 
+    end process; -- 
+
+    -- dout_vld
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_vld <= '0';
+            elsif pop = '1' then
+                dout_vld <= '1';
+            elsif pop_dout = '1' then
+                dout_vld <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+end architecture;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity myproject_fifo_w16_d4356_A_ram is
+    generic (
+        MEM_STYLE   : string  := "auto";
+        DATA_WIDTH  : integer := 16;
+        ADDR_WIDTH  : integer := 13;
+        DEPTH       : integer := 4356);
+    port (
+        clk         : in std_logic;
+        reset       : in std_logic;
+        we          : in std_logic;
+        waddr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din         : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        raddr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        rden        : in std_logic;
+        dout        : out std_logic_vector(DATA_WIDTH-1 downto 0)
+    );
+end entity;
+
+architecture arch of myproject_fifo_w16_d4356_A_ram is
+    type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
+    signal mem : memtype;
+    attribute ram_style: string;
+    attribute ram_style of mem: signal is MEM_STYLE;
+    signal mem_reg  : std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+begin
+    dout <= mem_reg;
+
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mem_reg <= ( others=> '0');
+            elsif (rden = '1') then
+                mem_reg <= mem(conv_integer(raddr));
+            end if;
+        end if; -- sync end 
+    end process;
+
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if we = '1' then
+                mem(conv_integer(waddr)) <= din;
+            end if;
+        end if;
+    end process;
+
+end architecture;

myproject_prj/solution1/.autopilot/db/vhdl/myproject_fifo_w16_d64_S.vhd

@@ -0,0 +1,195 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--RAW latency 1 
+ 
+entity myproject_fifo_w16_d64_S is 
+    generic (
+        MEM_STYLE         : string  := "shiftReg";
+        DATA_WIDTH        : integer := 16;
+        ADDR_WIDTH        : integer := 6;
+        DEPTH             : integer := 64);
+    port (
+        clk               : in  std_logic;
+        reset             : in  std_logic;
+
+        -- write
+        if_full_n         : out std_logic;
+        if_write_ce       : in  std_logic;
+        if_write          : in  std_logic;
+        if_din            : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+        -- read 
+        if_num_data_valid : out std_logic_vector(ADDR_WIDTH downto 0); -- for FRP
+        if_fifo_cap       : out std_logic_vector(ADDR_WIDTH downto 0); -- for FRP
+
+        if_empty_n        : out std_logic;
+        if_read_ce        : in  std_logic;
+        if_read           : in  std_logic;
+        if_dout           : out std_logic_vector(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture rtl of myproject_fifo_w16_d64_S is
+------------------------Task and function--------------
+------------------------Parameter----------------------
+constant SRL_DEPTH  : INTEGER := DEPTH;
+constant SRL_AWIDTH : INTEGER := ADDR_WIDTH;
+------------------------Component----------------------
+    component myproject_fifo_w16_d64_S_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 16;
+        ADDR_WIDTH : integer := 6;
+        DEPTH      : integer := 64);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+    end component;
+
+    signal addr    : UNSIGNED(SRL_AWIDTH - 1 downto 0);
+    signal push    : STD_LOGIC;
+    signal pop     : STD_LOGIC;
+    signal mOutPtr : UNSIGNED(SRL_AWIDTH downto 0) := (others => '0');
+    signal empty_n : STD_LOGIC := '0';
+    signal full_n   : std_logic := '1';   
+    -- has num_data_valid?
+    signal num_data_valid: UNSIGNED(ADDR_WIDTH downto 0); -- yes 
+begin
+----------------------- Instantiation -----------------------
+    U_myproject_fifo_w16_d64_S_ShiftReg : myproject_fifo_w16_d64_S_ShiftReg
+    generic map (
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => SRL_AWIDTH,
+        DEPTH      => SRL_DEPTH)
+    port map (
+        clk        => clk,
+        we         => push,
+        addr       => STD_LOGIC_VECTOR(addr),
+        din        => if_din,
+        dout       => if_dout);
+--------------------------- Body ----------------------------
+    -- has num_data_valid ? 
+    if_num_data_valid <= STD_LOGIC_VECTOR(mOutPtr); -- yes
+    if_fifo_cap <= STD_LOGIC_VECTOR(TO_UNSIGNED(DEPTH, ADDR_WIDTH + 1)); --yes 
+
+    -- almost full/empty  
+
+    -- program full/empty  
+
+    if_full_n  <= full_n;
+    if_empty_n <= empty_n;
+
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and if_read;
+
+    -- addr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                addr <= (others => '0');
+            elsif push = '1' and pop = '0' and empty_n = '1' then
+                addr <= addr + 1;
+            elsif push = '0' and pop = '1' and mOutPtr /= 1 then
+                addr <= addr - 1;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- mOutPtr
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '0');
+            elsif push = '1' and pop = '0' then
+                mOutPtr <= mOutPtr + 1;
+            elsif push = '0' and pop = '1' then
+                mOutPtr <= mOutPtr - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- full_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif push = '1' and pop = '0' and mOutPtr = DEPTH - 1 then
+                full_n <= '0';
+            elsif push = '0' and pop = '1' then
+                full_n <= '1';
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif push = '1' and pop = '0' then
+                empty_n <= '1';
+            elsif push = '0' and pop = '1' and mOutPtr = 1 then
+                empty_n <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- almost_full_n
+
+    -- almost_empty_n
+
+    -- prog_full_n 
+
+    -- prog_empty_n 
+
+end architecture rtl;
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity myproject_fifo_w16_d64_S_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 16;
+        ADDR_WIDTH : integer := 6;
+        DEPTH      : integer := 64);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+end myproject_fifo_w16_d64_S_ShiftReg;
+
+architecture rtl of myproject_fifo_w16_d64_S_ShiftReg is
+type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
+signal SRL_SIG : SRL_ARRAY;
+
+begin
+    dout <= SRL_SIG(conv_integer(addr));
+
+    process (clk)
+    begin
+        if (clk'event and clk = '1') then
+            if (we = '1') then
+                SRL_SIG <= din & SRL_SIG(0 to DEPTH-2);
+            end if;
+        end if;
+    end process;
+
+end architecture rtl;

myproject_prj/solution1/.autopilot/db/vhdl/myproject_fifo_w384_d4096_A.vhd

@@ -0,0 +1,305 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--RAW latency 2 
+ 
+entity myproject_fifo_w384_d4096_A is
+    generic (
+        MEM_STYLE         : string  := "auto";
+        DATA_WIDTH        : integer := 384;
+        ADDR_WIDTH        : integer := 12;
+        DEPTH             : integer := 4096);
+    port (
+        clk               : in  std_logic;
+        reset             : in  std_logic;
+
+        -- write
+        if_full_n         : out std_logic;
+        if_write_ce       : in  std_logic;
+        if_write          : in  std_logic;
+        if_din            : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+        -- read 
+        if_num_data_valid : out std_logic_vector(ADDR_WIDTH downto 0); -- for FRP
+        if_fifo_cap       : out std_logic_vector(ADDR_WIDTH downto 0); -- for FRP
+
+        if_empty_n        : out std_logic;
+        if_read_ce        : in  std_logic;
+        if_read           : in  std_logic;
+        if_dout           : out std_logic_vector(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture arch of myproject_fifo_w384_d4096_A is
+------------------------Task and function--------------
+    function clog2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 1;
+        m := 2;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function clog2;
+    ------------------------Parameter----------------------
+    constant MEM_DEPTH  : INTEGER := DEPTH - 1;
+    constant MEM_AWIDTH : INTEGER := clog2(MEM_DEPTH);
+    ------------------------Component----------------------
+    component myproject_fifo_w384_d4096_A_ram is
+    generic (
+        MEM_STYLE  : string  := "auto";
+        DATA_WIDTH : integer := 384;
+        ADDR_WIDTH : integer := 12;
+        DEPTH      : integer := 4096);
+    port (
+        clk        : in std_logic;
+        reset      : in std_logic;
+        we         : in std_logic;
+        waddr      : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH - 1 downto 0);
+        raddr      : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
+        rden       : in std_logic;
+        dout       : out std_logic_vector(DATA_WIDTH - 1 downto 0));
+    end component;
+------------------------Local signal-------------------
+    signal waddr    : unsigned(MEM_AWIDTH - 1 downto 0) := (others => '0');
+    signal raddr    : unsigned(MEM_AWIDTH - 1 downto 0) := (others => '0');
+    signal wnext    : unsigned(MEM_AWIDTH - 1 downto 0);
+    signal rnext    : unsigned(MEM_AWIDTH - 1 downto 0);
+    signal push     : std_logic;
+    signal pop      : std_logic;
+    signal mOutPtr  : unsigned(MEM_AWIDTH downto 0) := (others => '0');
+    signal empty_n  : std_logic := '0';
+    signal full_n   : std_logic := '1';
+    -- has num_data_valid ? 
+    signal num_extra_words: UNSIGNED(0 downto 0); -- yes
+    signal num_data_valid : UNSIGNED(ADDR_WIDTH downto 0); -- yes 
+
+    signal pop_dout : std_logic;
+    signal num_data_cnt : UNSIGNED(ADDR_WIDTH downto 0);
+    signal dout_vld : std_logic := '0';
+begin
+----------------------- Instantiation -----------------------
+    U_myproject_fifo_w384_d4096_A_ram : myproject_fifo_w384_d4096_A_ram
+    generic map (
+        MEM_STYLE  => MEM_STYLE,
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => MEM_AWIDTH,
+        DEPTH => MEM_DEPTH)
+    port map (
+        clk   => clk,
+        reset => reset,
+        we    => push,
+        waddr => std_logic_vector(waddr),
+        din   => if_din,
+        raddr => std_logic_vector(raddr),
+        rden  => pop,
+        dout  => if_dout);
+
+--------------------------- Body ----------------------------
+    -- has num_data_valid ?  
+    if_num_data_valid <= STD_LOGIC_VECTOR(num_data_valid); -- yes
+    if_fifo_cap       <= STD_LOGIC_VECTOR(TO_UNSIGNED(DEPTH, ADDR_WIDTH + 1)); -- yes 
+
+    -- almost full/empty  
+
+    -- program full/empty  
+    
+    if_full_n  <= full_n;
+    if_empty_n <= dout_vld;
+
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and (not dout_vld or pop_dout);
+    pop_dout   <= dout_vld and if_read_ce and if_read;
+    
+    wnext      <= waddr           when push = '0'            else
+                  (others => '0') when waddr = MEM_DEPTH - 1 else
+                  waddr + 1;
+    rnext      <= raddr           when pop = '0'             else
+                  (others => '0') when raddr = MEM_DEPTH - 1 else
+                  raddr + 1;
+
+    -- waddr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                waddr <= (others => '0');
+            else
+                waddr <= wnext;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- raddr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                raddr <= (others => '0');
+            else
+                raddr <= rnext;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- mOutPtr
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '0');
+            elsif push = '1' and pop = '0' then
+                mOutPtr <= mOutPtr + 1;
+            elsif push = '0' and pop = '1' then
+                mOutPtr <= mOutPtr - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- full_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif push = '1' and pop_dout = '0' and num_data_cnt = DEPTH - 1 then
+                full_n <= '0';
+            elsif push = '0' and pop_dout = '1' then
+                full_n <= '1';
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif push = '1' and pop = '0' then
+                empty_n <= '1';
+            elsif push = '0' and pop = '1' and mOutPtr = 1 then
+                empty_n <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- almost_full_n
+
+    -- almost_empty_n
+
+    -- prog_full_n 
+
+    -- prog_empty_n 
+
+    -- num_data_cnt
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                num_data_cnt <= (others => '0');
+            elsif push = '1' and pop_dout = '0' then
+                num_data_cnt <= num_data_cnt + 1;
+            elsif push = '0' and pop_dout = '1' then
+                num_data_cnt <= num_data_cnt - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- num_data_valid  
+    num_extra_words <= TO_UNSIGNED(1,1) when (dout_vld and not pop_dout) = '1' else (others=>'0');
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                num_data_valid <= (others => '0');
+            elsif (empty_n or (dout_vld and not pop_dout)) = '1' then
+                if (push = '1') then
+                    num_data_valid <= RESIZE(mOutPtr, ADDR_WIDTH + 1) + 1 + num_extra_words;
+                else
+                    num_data_valid <= RESIZE(mOutPtr, ADDR_WIDTH + 1) + num_extra_words;
+                end if;
+            else
+                num_data_valid <= RESIZE(num_extra_words, ADDR_WIDTH + 1);
+            end if;
+        end if; -- sync end 
+    end process; -- 
+
+    -- dout_vld
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_vld <= '0';
+            elsif pop = '1' then
+                dout_vld <= '1';
+            elsif pop_dout = '1' then
+                dout_vld <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+end architecture;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity myproject_fifo_w384_d4096_A_ram is
+    generic (
+        MEM_STYLE   : string  := "auto";
+        DATA_WIDTH  : integer := 384;
+        ADDR_WIDTH  : integer := 12;
+        DEPTH       : integer := 4096);
+    port (
+        clk         : in std_logic;
+        reset       : in std_logic;
+        we          : in std_logic;
+        waddr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din         : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        raddr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        rden        : in std_logic;
+        dout        : out std_logic_vector(DATA_WIDTH-1 downto 0)
+    );
+end entity;
+
+architecture arch of myproject_fifo_w384_d4096_A_ram is
+    type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
+    signal mem : memtype;
+    attribute ram_style: string;
+    attribute ram_style of mem: signal is MEM_STYLE;
+    signal mem_reg  : std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+begin
+    dout <= mem_reg;
+
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mem_reg <= ( others=> '0');
+            elsif (rden = '1') then
+                mem_reg <= mem(conv_integer(raddr));
+            end if;
+        end if; -- sync end 
+    end process;
+
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if we = '1' then
+                mem(conv_integer(waddr)) <= din;
+            end if;
+        end if;
+    end process;
+
+end architecture;

myproject_prj/solution1/.autopilot/db/vhdl/myproject_fifo_w512_d1024_A.vhd

@@ -0,0 +1,305 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--RAW latency 2 
+ 
+entity myproject_fifo_w512_d1024_A is
+    generic (
+        MEM_STYLE         : string  := "auto";
+        DATA_WIDTH        : integer := 512;
+        ADDR_WIDTH        : integer := 10;
+        DEPTH             : integer := 1024);
+    port (
+        clk               : in  std_logic;
+        reset             : in  std_logic;
+
+        -- write
+        if_full_n         : out std_logic;
+        if_write_ce       : in  std_logic;
+        if_write          : in  std_logic;
+        if_din            : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+        -- read 
+        if_num_data_valid : out std_logic_vector(ADDR_WIDTH downto 0); -- for FRP
+        if_fifo_cap       : out std_logic_vector(ADDR_WIDTH downto 0); -- for FRP
+
+        if_empty_n        : out std_logic;
+        if_read_ce        : in  std_logic;
+        if_read           : in  std_logic;
+        if_dout           : out std_logic_vector(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture arch of myproject_fifo_w512_d1024_A is
+------------------------Task and function--------------
+    function clog2 (x : INTEGER) return INTEGER is
+        variable n, m : INTEGER;
+    begin
+        n := 1;
+        m := 2;
+        while m < x loop
+            n := n + 1;
+            m := m * 2;
+        end loop;
+        return n;
+    end function clog2;
+    ------------------------Parameter----------------------
+    constant MEM_DEPTH  : INTEGER := DEPTH - 1;
+    constant MEM_AWIDTH : INTEGER := clog2(MEM_DEPTH);
+    ------------------------Component----------------------
+    component myproject_fifo_w512_d1024_A_ram is
+    generic (
+        MEM_STYLE  : string  := "auto";
+        DATA_WIDTH : integer := 512;
+        ADDR_WIDTH : integer := 10;
+        DEPTH      : integer := 1024);
+    port (
+        clk        : in std_logic;
+        reset      : in std_logic;
+        we         : in std_logic;
+        waddr      : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH - 1 downto 0);
+        raddr      : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
+        rden       : in std_logic;
+        dout       : out std_logic_vector(DATA_WIDTH - 1 downto 0));
+    end component;
+------------------------Local signal-------------------
+    signal waddr    : unsigned(MEM_AWIDTH - 1 downto 0) := (others => '0');
+    signal raddr    : unsigned(MEM_AWIDTH - 1 downto 0) := (others => '0');
+    signal wnext    : unsigned(MEM_AWIDTH - 1 downto 0);
+    signal rnext    : unsigned(MEM_AWIDTH - 1 downto 0);
+    signal push     : std_logic;
+    signal pop      : std_logic;
+    signal mOutPtr  : unsigned(MEM_AWIDTH downto 0) := (others => '0');
+    signal empty_n  : std_logic := '0';
+    signal full_n   : std_logic := '1';
+    -- has num_data_valid ? 
+    signal num_extra_words: UNSIGNED(0 downto 0); -- yes
+    signal num_data_valid : UNSIGNED(ADDR_WIDTH downto 0); -- yes 
+
+    signal pop_dout : std_logic;
+    signal num_data_cnt : UNSIGNED(ADDR_WIDTH downto 0);
+    signal dout_vld : std_logic := '0';
+begin
+----------------------- Instantiation -----------------------
+    U_myproject_fifo_w512_d1024_A_ram : myproject_fifo_w512_d1024_A_ram
+    generic map (
+        MEM_STYLE  => MEM_STYLE,
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => MEM_AWIDTH,
+        DEPTH => MEM_DEPTH)
+    port map (
+        clk   => clk,
+        reset => reset,
+        we    => push,
+        waddr => std_logic_vector(waddr),
+        din   => if_din,
+        raddr => std_logic_vector(raddr),
+        rden  => pop,
+        dout  => if_dout);
+
+--------------------------- Body ----------------------------
+    -- has num_data_valid ?  
+    if_num_data_valid <= STD_LOGIC_VECTOR(num_data_valid); -- yes
+    if_fifo_cap       <= STD_LOGIC_VECTOR(TO_UNSIGNED(DEPTH, ADDR_WIDTH + 1)); -- yes 
+
+    -- almost full/empty  
+
+    -- program full/empty  
+    
+    if_full_n  <= full_n;
+    if_empty_n <= dout_vld;
+
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and (not dout_vld or pop_dout);
+    pop_dout   <= dout_vld and if_read_ce and if_read;
+    
+    wnext      <= waddr           when push = '0'            else
+                  (others => '0') when waddr = MEM_DEPTH - 1 else
+                  waddr + 1;
+    rnext      <= raddr           when pop = '0'             else
+                  (others => '0') when raddr = MEM_DEPTH - 1 else
+                  raddr + 1;
+
+    -- waddr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                waddr <= (others => '0');
+            else
+                waddr <= wnext;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- raddr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                raddr <= (others => '0');
+            else
+                raddr <= rnext;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- mOutPtr
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '0');
+            elsif push = '1' and pop = '0' then
+                mOutPtr <= mOutPtr + 1;
+            elsif push = '0' and pop = '1' then
+                mOutPtr <= mOutPtr - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- full_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif push = '1' and pop_dout = '0' and num_data_cnt = DEPTH - 1 then
+                full_n <= '0';
+            elsif push = '0' and pop_dout = '1' then
+                full_n <= '1';
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif push = '1' and pop = '0' then
+                empty_n <= '1';
+            elsif push = '0' and pop = '1' and mOutPtr = 1 then
+                empty_n <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- almost_full_n
+
+    -- almost_empty_n
+
+    -- prog_full_n 
+
+    -- prog_empty_n 
+
+    -- num_data_cnt
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                num_data_cnt <= (others => '0');
+            elsif push = '1' and pop_dout = '0' then
+                num_data_cnt <= num_data_cnt + 1;
+            elsif push = '0' and pop_dout = '1' then
+                num_data_cnt <= num_data_cnt - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- num_data_valid  
+    num_extra_words <= TO_UNSIGNED(1,1) when (dout_vld and not pop_dout) = '1' else (others=>'0');
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                num_data_valid <= (others => '0');
+            elsif (empty_n or (dout_vld and not pop_dout)) = '1' then
+                if (push = '1') then
+                    num_data_valid <= RESIZE(mOutPtr, ADDR_WIDTH + 1) + 1 + num_extra_words;
+                else
+                    num_data_valid <= RESIZE(mOutPtr, ADDR_WIDTH + 1) + num_extra_words;
+                end if;
+            else
+                num_data_valid <= RESIZE(num_extra_words, ADDR_WIDTH + 1);
+            end if;
+        end if; -- sync end 
+    end process; -- 
+
+    -- dout_vld
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                dout_vld <= '0';
+            elsif pop = '1' then
+                dout_vld <= '1';
+            elsif pop_dout = '1' then
+                dout_vld <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+end architecture;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity myproject_fifo_w512_d1024_A_ram is
+    generic (
+        MEM_STYLE   : string  := "auto";
+        DATA_WIDTH  : integer := 512;
+        ADDR_WIDTH  : integer := 10;
+        DEPTH       : integer := 1024);
+    port (
+        clk         : in std_logic;
+        reset       : in std_logic;
+        we          : in std_logic;
+        waddr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din         : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        raddr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        rden        : in std_logic;
+        dout        : out std_logic_vector(DATA_WIDTH-1 downto 0)
+    );
+end entity;
+
+architecture arch of myproject_fifo_w512_d1024_A_ram is
+    type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
+    signal mem : memtype;
+    attribute ram_style: string;
+    attribute ram_style of mem: signal is MEM_STYLE;
+    signal mem_reg  : std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+begin
+    dout <= mem_reg;
+
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mem_reg <= ( others=> '0');
+            elsif (rden = '1') then
+                mem_reg <= mem(conv_integer(raddr));
+            end if;
+        end if; -- sync end 
+    end process;
+
+    process (clk) begin
+        if clk'event and clk = '1' then
+            if we = '1' then
+                mem(conv_integer(waddr)) <= din;
+            end if;
+        end if;
+    end process;
+
+end architecture;

myproject_prj/solution1/.autopilot/db/vhdl/myproject_mac_muladd_16s_11s_40s_41_1_1.vhd

@@ -0,0 +1,84 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+--   
+--   
+--   
+-- 
+entity myproject_mac_muladd_16s_11s_40s_41_1_1_DSP48_0 is
+port (
+    in0:  in  std_logic_vector(16 - 1 downto 0);
+    in1:  in  std_logic_vector(11 - 1 downto 0);
+    in2:  in  std_logic_vector(40 - 1 downto 0);
+    dout: out std_logic_vector(41 - 1 downto 0));
+
+end entity;
+
+architecture behav of myproject_mac_muladd_16s_11s_40s_41_1_1_DSP48_0 is
+    signal a       : signed(27-1 downto 0);
+    signal b       : signed(18-1 downto 0);
+    signal c       : signed(48-1 downto 0);
+    signal m       : signed(45-1 downto 0);
+    signal p       : signed(48-1 downto 0);
+begin
+a  <= signed(resize(signed(in0), 27));
+b  <= signed(resize(signed(in1), 18));
+c  <= signed(resize(signed(in2), 48));
+
+m  <= a * b;
+-- 
+p  <= m + c;
+-- 
+
+dout <= std_logic_vector(resize(unsigned(p), 41));
+
+end architecture;
+-- 
+
+Library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity myproject_mac_muladd_16s_11s_40s_41_1_1 is
+    generic (
+        ID : INTEGER;
+        NUM_STAGE : INTEGER;
+        din0_WIDTH : INTEGER;
+        din1_WIDTH : INTEGER;
+        din2_WIDTH : INTEGER;
+        dout_WIDTH : INTEGER);
+    port (
+-- 
+        din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
+        din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
+        din2 : IN STD_LOGIC_VECTOR(din2_WIDTH - 1 DOWNTO 0);
+        dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
+end entity;
+
+architecture arch of myproject_mac_muladd_16s_11s_40s_41_1_1 is
+    component myproject_mac_muladd_16s_11s_40s_41_1_1_DSP48_0 is
+        port (
+-- 
+            in0 : IN STD_LOGIC_VECTOR;
+            in1 : IN STD_LOGIC_VECTOR;
+            in2 : IN STD_LOGIC_VECTOR;
+            dout : OUT STD_LOGIC_VECTOR);
+    end component;
+
+
+
+begin
+    myproject_mac_muladd_16s_11s_40s_41_1_1_DSP48_0_U :  component myproject_mac_muladd_16s_11s_40s_41_1_1_DSP48_0
+    port map (
+-- 
+        in0 => din0,
+        in1 => din1,
+        in2 => din2,
+        dout => dout);
+
+end architecture;

myproject_prj/solution1/.autopilot/db/vhdl/myproject_mac_muladd_16s_9s_32s_32_1_1.vhd

@@ -0,0 +1,84 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+--   
+--   
+--   
+-- 
+entity myproject_mac_muladd_16s_9s_32s_32_1_1_DSP48_0 is
+port (
+    in0:  in  std_logic_vector(16 - 1 downto 0);
+    in1:  in  std_logic_vector(9 - 1 downto 0);
+    in2:  in  std_logic_vector(32 - 1 downto 0);
+    dout: out std_logic_vector(32 - 1 downto 0));
+
+end entity;
+
+architecture behav of myproject_mac_muladd_16s_9s_32s_32_1_1_DSP48_0 is
+    signal a       : signed(27-1 downto 0);
+    signal b       : signed(18-1 downto 0);
+    signal c       : signed(48-1 downto 0);
+    signal m       : signed(45-1 downto 0);
+    signal p       : signed(48-1 downto 0);
+begin
+a  <= signed(resize(signed(in0), 27));
+b  <= signed(resize(signed(in1), 18));
+c  <= signed(resize(signed(in2), 48));
+
+m  <= a * b;
+-- 
+p  <= m + c;
+-- 
+
+dout <= std_logic_vector(resize(unsigned(p), 32));
+
+end architecture;
+-- 
+
+Library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity myproject_mac_muladd_16s_9s_32s_32_1_1 is
+    generic (
+        ID : INTEGER;
+        NUM_STAGE : INTEGER;
+        din0_WIDTH : INTEGER;
+        din1_WIDTH : INTEGER;
+        din2_WIDTH : INTEGER;
+        dout_WIDTH : INTEGER);
+    port (
+-- 
+        din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
+        din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
+        din2 : IN STD_LOGIC_VECTOR(din2_WIDTH - 1 DOWNTO 0);
+        dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
+end entity;
+
+architecture arch of myproject_mac_muladd_16s_9s_32s_32_1_1 is
+    component myproject_mac_muladd_16s_9s_32s_32_1_1_DSP48_0 is
+        port (
+-- 
+            in0 : IN STD_LOGIC_VECTOR;
+            in1 : IN STD_LOGIC_VECTOR;
+            in2 : IN STD_LOGIC_VECTOR;
+            dout : OUT STD_LOGIC_VECTOR);
+    end component;
+
+
+
+begin
+    myproject_mac_muladd_16s_9s_32s_32_1_1_DSP48_0_U :  component myproject_mac_muladd_16s_9s_32s_32_1_1_DSP48_0
+    port map (
+-- 
+        in0 => din0,
+        in1 => din1,
+        in2 => din2,
+        dout => dout);
+
+end architecture;

myproject_prj/solution1/.autopilot/db/vhdl/myproject_mac_muladd_16s_9s_41s_42_1_1.vhd

@@ -0,0 +1,84 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+--   
+--   
+--   
+-- 
+entity myproject_mac_muladd_16s_9s_41s_42_1_1_DSP48_0 is
+port (
+    in0:  in  std_logic_vector(16 - 1 downto 0);
+    in1:  in  std_logic_vector(9 - 1 downto 0);
+    in2:  in  std_logic_vector(41 - 1 downto 0);
+    dout: out std_logic_vector(42 - 1 downto 0));
+
+end entity;
+
+architecture behav of myproject_mac_muladd_16s_9s_41s_42_1_1_DSP48_0 is
+    signal a       : signed(27-1 downto 0);
+    signal b       : signed(18-1 downto 0);
+    signal c       : signed(48-1 downto 0);
+    signal m       : signed(45-1 downto 0);
+    signal p       : signed(48-1 downto 0);
+begin
+a  <= signed(resize(signed(in0), 27));
+b  <= signed(resize(signed(in1), 18));
+c  <= signed(resize(signed(in2), 48));
+
+m  <= a * b;
+-- 
+p  <= m + c;
+-- 
+
+dout <= std_logic_vector(resize(unsigned(p), 42));
+
+end architecture;
+-- 
+
+Library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity myproject_mac_muladd_16s_9s_41s_42_1_1 is
+    generic (
+        ID : INTEGER;
+        NUM_STAGE : INTEGER;
+        din0_WIDTH : INTEGER;
+        din1_WIDTH : INTEGER;
+        din2_WIDTH : INTEGER;
+        dout_WIDTH : INTEGER);
+    port (
+-- 
+        din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
+        din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
+        din2 : IN STD_LOGIC_VECTOR(din2_WIDTH - 1 DOWNTO 0);
+        dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
+end entity;
+
+architecture arch of myproject_mac_muladd_16s_9s_41s_42_1_1 is
+    component myproject_mac_muladd_16s_9s_41s_42_1_1_DSP48_0 is
+        port (
+-- 
+            in0 : IN STD_LOGIC_VECTOR;
+            in1 : IN STD_LOGIC_VECTOR;
+            in2 : IN STD_LOGIC_VECTOR;
+            dout : OUT STD_LOGIC_VECTOR);
+    end component;
+
+
+
+begin
+    myproject_mac_muladd_16s_9s_41s_42_1_1_DSP48_0_U :  component myproject_mac_muladd_16s_9s_41s_42_1_1_DSP48_0
+    port map (
+-- 
+        in0 => din0,
+        in1 => din1,
+        in2 => din2,
+        dout => dout);
+
+end architecture;

myproject_prj/solution1/.autopilot/db/vhdl/myproject_mul_16s_16s_32_1_1.vhd

@@ -0,0 +1,87 @@
+-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+
+entity myproject_mul_16s_16s_32_1_1 is
+generic (
+    ID : INTEGER := 1;
+    NUM_STAGE : INTEGER := 0;
+    din0_WIDTH : INTEGER := 14;
+    din1_WIDTH : INTEGER := 12;
+    dout_WIDTH : INTEGER := 26);
+port (
+
+    din0: in std_logic_vector(din0_WIDTH - 1 downto 0);
+    din1: in std_logic_vector(din1_WIDTH - 1 downto 0);
+    dout: out std_logic_vector(dout_WIDTH - 1 downto 0));
+
+
+end entity;
+
+architecture behav of myproject_mul_16s_16s_32_1_1 is
+    signal tmp_product : std_logic_vector(dout_WIDTH - 1 downto 0);
+    signal a_i : std_logic_vector(din0_WIDTH - 1 downto 0);
+    signal b_i : std_logic_vector(din1_WIDTH - 1 downto 0);
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+        
+        
+        
+        
+        
+        
+        
+        
+        
+              
+begin
+    a_i <= din0;
+    b_i <= din1;
+
+
+
+
+
+
+    tmp_product <= std_logic_vector(resize(unsigned(std_logic_vector(signed(a_i) * signed(b_i))), dout_WIDTH));
+
+
+
+
+
+
+    dout <= tmp_product;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+end architecture;

myproject_prj/solution1/.autopilot/db/vhdl/myproject_start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384oqc.vhd

@@ -0,0 +1,190 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--RAW latency 1 
+ 
+entity myproject_start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384oqc is 
+    generic (
+        MEM_STYLE         : string  := "shiftReg";
+        DATA_WIDTH        : integer := 1;
+        ADDR_WIDTH        : integer := 1;
+        DEPTH             : integer := 2);
+    port (
+        clk               : in  std_logic;
+        reset             : in  std_logic;
+
+        -- write
+        if_full_n         : out std_logic;
+        if_write_ce       : in  std_logic;
+        if_write          : in  std_logic;
+        if_din            : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+        -- read 
+
+        if_empty_n        : out std_logic;
+        if_read_ce        : in  std_logic;
+        if_read           : in  std_logic;
+        if_dout           : out std_logic_vector(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture rtl of myproject_start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384oqc is
+------------------------Task and function--------------
+------------------------Parameter----------------------
+constant SRL_DEPTH  : INTEGER := DEPTH;
+constant SRL_AWIDTH : INTEGER := ADDR_WIDTH;
+------------------------Component----------------------
+    component myproject_start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384oqc_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+    end component;
+
+    signal addr    : UNSIGNED(SRL_AWIDTH - 1 downto 0);
+    signal push    : STD_LOGIC;
+    signal pop     : STD_LOGIC;
+    signal mOutPtr : UNSIGNED(SRL_AWIDTH downto 0) := (others => '0');
+    signal empty_n : STD_LOGIC := '0';
+    signal full_n   : std_logic := '1';   
+    -- has num_data_valid? no 
+begin
+----------------------- Instantiation -----------------------
+    U_myproject_start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384oqc_ShiftReg : myproject_start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384oqc_ShiftReg
+    generic map (
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => SRL_AWIDTH,
+        DEPTH      => SRL_DEPTH)
+    port map (
+        clk        => clk,
+        we         => push,
+        addr       => STD_LOGIC_VECTOR(addr),
+        din        => if_din,
+        dout       => if_dout);
+--------------------------- Body ----------------------------
+    -- has num_data_valid ?  no 
+
+    -- almost full/empty  
+
+    -- program full/empty  
+
+    if_full_n  <= full_n;
+    if_empty_n <= empty_n;
+
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and if_read;
+
+    -- addr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                addr <= (others => '0');
+            elsif push = '1' and pop = '0' and empty_n = '1' then
+                addr <= addr + 1;
+            elsif push = '0' and pop = '1' and mOutPtr /= 1 then
+                addr <= addr - 1;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- mOutPtr
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '0');
+            elsif push = '1' and pop = '0' then
+                mOutPtr <= mOutPtr + 1;
+            elsif push = '0' and pop = '1' then
+                mOutPtr <= mOutPtr - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- full_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif push = '1' and pop = '0' and mOutPtr = DEPTH - 1 then
+                full_n <= '0';
+            elsif push = '0' and pop = '1' then
+                full_n <= '1';
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif push = '1' and pop = '0' then
+                empty_n <= '1';
+            elsif push = '0' and pop = '1' and mOutPtr = 1 then
+                empty_n <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- almost_full_n
+
+    -- almost_empty_n
+
+    -- prog_full_n 
+
+    -- prog_empty_n 
+
+end architecture rtl;
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity myproject_start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384oqc_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+end myproject_start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384oqc_ShiftReg;
+
+architecture rtl of myproject_start_for_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384oqc_ShiftReg is
+type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
+signal SRL_SIG : SRL_ARRAY;
+
+begin
+    dout <= SRL_SIG(conv_integer(addr));
+
+    process (clk)
+    begin
+        if (clk'event and clk = '1') then
+            if (we = '1') then
+                SRL_SIG <= din & SRL_SIG(0 to DEPTH-2);
+            end if;
+        end if;
+    end process;
+
+end architecture rtl;

myproject_prj/solution1/.autopilot/db/vhdl/myproject_start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_configomc.vhd

@@ -0,0 +1,190 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--RAW latency 1 
+ 
+entity myproject_start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_configomc is 
+    generic (
+        MEM_STYLE         : string  := "shiftReg";
+        DATA_WIDTH        : integer := 1;
+        ADDR_WIDTH        : integer := 1;
+        DEPTH             : integer := 2);
+    port (
+        clk               : in  std_logic;
+        reset             : in  std_logic;
+
+        -- write
+        if_full_n         : out std_logic;
+        if_write_ce       : in  std_logic;
+        if_write          : in  std_logic;
+        if_din            : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+        -- read 
+
+        if_empty_n        : out std_logic;
+        if_read_ce        : in  std_logic;
+        if_read           : in  std_logic;
+        if_dout           : out std_logic_vector(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture rtl of myproject_start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_configomc is
+------------------------Task and function--------------
+------------------------Parameter----------------------
+constant SRL_DEPTH  : INTEGER := DEPTH;
+constant SRL_AWIDTH : INTEGER := ADDR_WIDTH;
+------------------------Component----------------------
+    component myproject_start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_configomc_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+    end component;
+
+    signal addr    : UNSIGNED(SRL_AWIDTH - 1 downto 0);
+    signal push    : STD_LOGIC;
+    signal pop     : STD_LOGIC;
+    signal mOutPtr : UNSIGNED(SRL_AWIDTH downto 0) := (others => '0');
+    signal empty_n : STD_LOGIC := '0';
+    signal full_n   : std_logic := '1';   
+    -- has num_data_valid? no 
+begin
+----------------------- Instantiation -----------------------
+    U_myproject_start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_configomc_ShiftReg : myproject_start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_configomc_ShiftReg
+    generic map (
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => SRL_AWIDTH,
+        DEPTH      => SRL_DEPTH)
+    port map (
+        clk        => clk,
+        we         => push,
+        addr       => STD_LOGIC_VECTOR(addr),
+        din        => if_din,
+        dout       => if_dout);
+--------------------------- Body ----------------------------
+    -- has num_data_valid ?  no 
+
+    -- almost full/empty  
+
+    -- program full/empty  
+
+    if_full_n  <= full_n;
+    if_empty_n <= empty_n;
+
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and if_read;
+
+    -- addr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                addr <= (others => '0');
+            elsif push = '1' and pop = '0' and empty_n = '1' then
+                addr <= addr + 1;
+            elsif push = '0' and pop = '1' and mOutPtr /= 1 then
+                addr <= addr - 1;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- mOutPtr
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '0');
+            elsif push = '1' and pop = '0' then
+                mOutPtr <= mOutPtr + 1;
+            elsif push = '0' and pop = '1' then
+                mOutPtr <= mOutPtr - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- full_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif push = '1' and pop = '0' and mOutPtr = DEPTH - 1 then
+                full_n <= '0';
+            elsif push = '0' and pop = '1' then
+                full_n <= '1';
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif push = '1' and pop = '0' then
+                empty_n <= '1';
+            elsif push = '0' and pop = '1' and mOutPtr = 1 then
+                empty_n <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- almost_full_n
+
+    -- almost_empty_n
+
+    -- prog_full_n 
+
+    -- prog_empty_n 
+
+end architecture rtl;
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity myproject_start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_configomc_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+end myproject_start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_configomc_ShiftReg;
+
+architecture rtl of myproject_start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_configomc_ShiftReg is
+type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
+signal SRL_SIG : SRL_ARRAY;
+
+begin
+    dout <= SRL_SIG(conv_integer(addr));
+
+    process (clk)
+    begin
+        if (clk'event and clk = '1') then
+            if (we = '1') then
+                SRL_SIG <= din & SRL_SIG(0 to DEPTH-2);
+            end if;
+        end if;
+    end process;
+
+end architecture rtl;

myproject_prj/solution1/.autopilot/db/vhdl/myproject_start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_configooc.vhd

@@ -0,0 +1,190 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--RAW latency 1 
+ 
+entity myproject_start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_configooc is 
+    generic (
+        MEM_STYLE         : string  := "shiftReg";
+        DATA_WIDTH        : integer := 1;
+        ADDR_WIDTH        : integer := 1;
+        DEPTH             : integer := 2);
+    port (
+        clk               : in  std_logic;
+        reset             : in  std_logic;
+
+        -- write
+        if_full_n         : out std_logic;
+        if_write_ce       : in  std_logic;
+        if_write          : in  std_logic;
+        if_din            : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+        -- read 
+
+        if_empty_n        : out std_logic;
+        if_read_ce        : in  std_logic;
+        if_read           : in  std_logic;
+        if_dout           : out std_logic_vector(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture rtl of myproject_start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_configooc is
+------------------------Task and function--------------
+------------------------Parameter----------------------
+constant SRL_DEPTH  : INTEGER := DEPTH;
+constant SRL_AWIDTH : INTEGER := ADDR_WIDTH;
+------------------------Component----------------------
+    component myproject_start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_configooc_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+    end component;
+
+    signal addr    : UNSIGNED(SRL_AWIDTH - 1 downto 0);
+    signal push    : STD_LOGIC;
+    signal pop     : STD_LOGIC;
+    signal mOutPtr : UNSIGNED(SRL_AWIDTH downto 0) := (others => '0');
+    signal empty_n : STD_LOGIC := '0';
+    signal full_n   : std_logic := '1';   
+    -- has num_data_valid? no 
+begin
+----------------------- Instantiation -----------------------
+    U_myproject_start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_configooc_ShiftReg : myproject_start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_configooc_ShiftReg
+    generic map (
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => SRL_AWIDTH,
+        DEPTH      => SRL_DEPTH)
+    port map (
+        clk        => clk,
+        we         => push,
+        addr       => STD_LOGIC_VECTOR(addr),
+        din        => if_din,
+        dout       => if_dout);
+--------------------------- Body ----------------------------
+    -- has num_data_valid ?  no 
+
+    -- almost full/empty  
+
+    -- program full/empty  
+
+    if_full_n  <= full_n;
+    if_empty_n <= empty_n;
+
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and if_read;
+
+    -- addr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                addr <= (others => '0');
+            elsif push = '1' and pop = '0' and empty_n = '1' then
+                addr <= addr + 1;
+            elsif push = '0' and pop = '1' and mOutPtr /= 1 then
+                addr <= addr - 1;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- mOutPtr
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '0');
+            elsif push = '1' and pop = '0' then
+                mOutPtr <= mOutPtr + 1;
+            elsif push = '0' and pop = '1' then
+                mOutPtr <= mOutPtr - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- full_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif push = '1' and pop = '0' and mOutPtr = DEPTH - 1 then
+                full_n <= '0';
+            elsif push = '0' and pop = '1' then
+                full_n <= '1';
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif push = '1' and pop = '0' then
+                empty_n <= '1';
+            elsif push = '0' and pop = '1' and mOutPtr = 1 then
+                empty_n <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- almost_full_n
+
+    -- almost_empty_n
+
+    -- prog_full_n 
+
+    -- prog_empty_n 
+
+end architecture rtl;
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity myproject_start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_configooc_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+end myproject_start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_configooc_ShiftReg;
+
+architecture rtl of myproject_start_for_conv_2d_cl_array_ap_fixed_16u_array_ap_fixed_41_21_5_3_0_16u_configooc_ShiftReg is
+type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
+signal SRL_SIG : SRL_ARRAY;
+
+begin
+    dout <= SRL_SIG(conv_integer(addr));
+
+    process (clk)
+    begin
+        if (clk'event and clk = '1') then
+            if (we = '1') then
+                SRL_SIG <= din & SRL_SIG(0 to DEPTH-2);
+            end if;
+        end if;
+    end process;
+
+end architecture rtl;

myproject_prj/solution1/.autopilot/db/vhdl/myproject_start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3owc.vhd

@@ -0,0 +1,190 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--RAW latency 1 
+ 
+entity myproject_start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3owc is 
+    generic (
+        MEM_STYLE         : string  := "shiftReg";
+        DATA_WIDTH        : integer := 1;
+        ADDR_WIDTH        : integer := 1;
+        DEPTH             : integer := 2);
+    port (
+        clk               : in  std_logic;
+        reset             : in  std_logic;
+
+        -- write
+        if_full_n         : out std_logic;
+        if_write_ce       : in  std_logic;
+        if_write          : in  std_logic;
+        if_din            : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+        -- read 
+
+        if_empty_n        : out std_logic;
+        if_read_ce        : in  std_logic;
+        if_read           : in  std_logic;
+        if_dout           : out std_logic_vector(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture rtl of myproject_start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3owc is
+------------------------Task and function--------------
+------------------------Parameter----------------------
+constant SRL_DEPTH  : INTEGER := DEPTH;
+constant SRL_AWIDTH : INTEGER := ADDR_WIDTH;
+------------------------Component----------------------
+    component myproject_start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3owc_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+    end component;
+
+    signal addr    : UNSIGNED(SRL_AWIDTH - 1 downto 0);
+    signal push    : STD_LOGIC;
+    signal pop     : STD_LOGIC;
+    signal mOutPtr : UNSIGNED(SRL_AWIDTH downto 0) := (others => '0');
+    signal empty_n : STD_LOGIC := '0';
+    signal full_n   : std_logic := '1';   
+    -- has num_data_valid? no 
+begin
+----------------------- Instantiation -----------------------
+    U_myproject_start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3owc_ShiftReg : myproject_start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3owc_ShiftReg
+    generic map (
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => SRL_AWIDTH,
+        DEPTH      => SRL_DEPTH)
+    port map (
+        clk        => clk,
+        we         => push,
+        addr       => STD_LOGIC_VECTOR(addr),
+        din        => if_din,
+        dout       => if_dout);
+--------------------------- Body ----------------------------
+    -- has num_data_valid ?  no 
+
+    -- almost full/empty  
+
+    -- program full/empty  
+
+    if_full_n  <= full_n;
+    if_empty_n <= empty_n;
+
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and if_read;
+
+    -- addr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                addr <= (others => '0');
+            elsif push = '1' and pop = '0' and empty_n = '1' then
+                addr <= addr + 1;
+            elsif push = '0' and pop = '1' and mOutPtr /= 1 then
+                addr <= addr - 1;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- mOutPtr
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '0');
+            elsif push = '1' and pop = '0' then
+                mOutPtr <= mOutPtr + 1;
+            elsif push = '0' and pop = '1' then
+                mOutPtr <= mOutPtr - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- full_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif push = '1' and pop = '0' and mOutPtr = DEPTH - 1 then
+                full_n <= '0';
+            elsif push = '0' and pop = '1' then
+                full_n <= '1';
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif push = '1' and pop = '0' then
+                empty_n <= '1';
+            elsif push = '0' and pop = '1' and mOutPtr = 1 then
+                empty_n <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- almost_full_n
+
+    -- almost_empty_n
+
+    -- prog_full_n 
+
+    -- prog_empty_n 
+
+end architecture rtl;
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity myproject_start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3owc_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+end myproject_start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3owc_ShiftReg;
+
+architecture rtl of myproject_start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3owc_ShiftReg is
+type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
+signal SRL_SIG : SRL_ARRAY;
+
+begin
+    dout <= SRL_SIG(conv_integer(addr));
+
+    process (clk)
+    begin
+        if (clk'event and clk = '1') then
+            if (we = '1') then
+                SRL_SIG <= din & SRL_SIG(0 to DEPTH-2);
+            end if;
+        end if;
+    end process;
+
+end architecture rtl;

myproject_prj/solution1/.autopilot/db/vhdl/myproject_start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3ozc.vhd

@@ -0,0 +1,190 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--RAW latency 1 
+ 
+entity myproject_start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3ozc is 
+    generic (
+        MEM_STYLE         : string  := "shiftReg";
+        DATA_WIDTH        : integer := 1;
+        ADDR_WIDTH        : integer := 1;
+        DEPTH             : integer := 2);
+    port (
+        clk               : in  std_logic;
+        reset             : in  std_logic;
+
+        -- write
+        if_full_n         : out std_logic;
+        if_write_ce       : in  std_logic;
+        if_write          : in  std_logic;
+        if_din            : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+        -- read 
+
+        if_empty_n        : out std_logic;
+        if_read_ce        : in  std_logic;
+        if_read           : in  std_logic;
+        if_dout           : out std_logic_vector(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture rtl of myproject_start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3ozc is
+------------------------Task and function--------------
+------------------------Parameter----------------------
+constant SRL_DEPTH  : INTEGER := DEPTH;
+constant SRL_AWIDTH : INTEGER := ADDR_WIDTH;
+------------------------Component----------------------
+    component myproject_start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3ozc_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+    end component;
+
+    signal addr    : UNSIGNED(SRL_AWIDTH - 1 downto 0);
+    signal push    : STD_LOGIC;
+    signal pop     : STD_LOGIC;
+    signal mOutPtr : UNSIGNED(SRL_AWIDTH downto 0) := (others => '0');
+    signal empty_n : STD_LOGIC := '0';
+    signal full_n   : std_logic := '1';   
+    -- has num_data_valid? no 
+begin
+----------------------- Instantiation -----------------------
+    U_myproject_start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3ozc_ShiftReg : myproject_start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3ozc_ShiftReg
+    generic map (
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => SRL_AWIDTH,
+        DEPTH      => SRL_DEPTH)
+    port map (
+        clk        => clk,
+        we         => push,
+        addr       => STD_LOGIC_VECTOR(addr),
+        din        => if_din,
+        dout       => if_dout);
+--------------------------- Body ----------------------------
+    -- has num_data_valid ?  no 
+
+    -- almost full/empty  
+
+    -- program full/empty  
+
+    if_full_n  <= full_n;
+    if_empty_n <= empty_n;
+
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and if_read;
+
+    -- addr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                addr <= (others => '0');
+            elsif push = '1' and pop = '0' and empty_n = '1' then
+                addr <= addr + 1;
+            elsif push = '0' and pop = '1' and mOutPtr /= 1 then
+                addr <= addr - 1;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- mOutPtr
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '0');
+            elsif push = '1' and pop = '0' then
+                mOutPtr <= mOutPtr + 1;
+            elsif push = '0' and pop = '1' then
+                mOutPtr <= mOutPtr - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- full_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif push = '1' and pop = '0' and mOutPtr = DEPTH - 1 then
+                full_n <= '0';
+            elsif push = '0' and pop = '1' then
+                full_n <= '1';
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif push = '1' and pop = '0' then
+                empty_n <= '1';
+            elsif push = '0' and pop = '1' and mOutPtr = 1 then
+                empty_n <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- almost_full_n
+
+    -- almost_empty_n
+
+    -- prog_full_n 
+
+    -- prog_empty_n 
+
+end architecture rtl;
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity myproject_start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3ozc_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+end myproject_start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3ozc_ShiftReg;
+
+architecture rtl of myproject_start_for_conv_2d_cl_array_ap_fixed_24u_array_ap_fixed_41_21_5_3_0_8u_config3ozc_ShiftReg is
+type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
+signal SRL_SIG : SRL_ARRAY;
+
+begin
+    dout <= SRL_SIG(conv_integer(addr));
+
+    process (clk)
+    begin
+        if (clk'event and clk = '1') then
+            if (we = '1') then
+                SRL_SIG <= din & SRL_SIG(0 to DEPTH-2);
+            end if;
+        end if;
+    end process;
+
+end architecture rtl;

myproject_prj/solution1/.autopilot/db/vhdl/myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7okc.vhd

@@ -0,0 +1,190 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--RAW latency 1 
+ 
+entity myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7okc is 
+    generic (
+        MEM_STYLE         : string  := "shiftReg";
+        DATA_WIDTH        : integer := 1;
+        ADDR_WIDTH        : integer := 1;
+        DEPTH             : integer := 2);
+    port (
+        clk               : in  std_logic;
+        reset             : in  std_logic;
+
+        -- write
+        if_full_n         : out std_logic;
+        if_write_ce       : in  std_logic;
+        if_write          : in  std_logic;
+        if_din            : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+        -- read 
+
+        if_empty_n        : out std_logic;
+        if_read_ce        : in  std_logic;
+        if_read           : in  std_logic;
+        if_dout           : out std_logic_vector(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture rtl of myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7okc is
+------------------------Task and function--------------
+------------------------Parameter----------------------
+constant SRL_DEPTH  : INTEGER := DEPTH;
+constant SRL_AWIDTH : INTEGER := ADDR_WIDTH;
+------------------------Component----------------------
+    component myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7okc_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+    end component;
+
+    signal addr    : UNSIGNED(SRL_AWIDTH - 1 downto 0);
+    signal push    : STD_LOGIC;
+    signal pop     : STD_LOGIC;
+    signal mOutPtr : UNSIGNED(SRL_AWIDTH downto 0) := (others => '0');
+    signal empty_n : STD_LOGIC := '0';
+    signal full_n   : std_logic := '1';   
+    -- has num_data_valid? no 
+begin
+----------------------- Instantiation -----------------------
+    U_myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7okc_ShiftReg : myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7okc_ShiftReg
+    generic map (
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => SRL_AWIDTH,
+        DEPTH      => SRL_DEPTH)
+    port map (
+        clk        => clk,
+        we         => push,
+        addr       => STD_LOGIC_VECTOR(addr),
+        din        => if_din,
+        dout       => if_dout);
+--------------------------- Body ----------------------------
+    -- has num_data_valid ?  no 
+
+    -- almost full/empty  
+
+    -- program full/empty  
+
+    if_full_n  <= full_n;
+    if_empty_n <= empty_n;
+
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and if_read;
+
+    -- addr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                addr <= (others => '0');
+            elsif push = '1' and pop = '0' and empty_n = '1' then
+                addr <= addr + 1;
+            elsif push = '0' and pop = '1' and mOutPtr /= 1 then
+                addr <= addr - 1;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- mOutPtr
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '0');
+            elsif push = '1' and pop = '0' then
+                mOutPtr <= mOutPtr + 1;
+            elsif push = '0' and pop = '1' then
+                mOutPtr <= mOutPtr - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- full_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif push = '1' and pop = '0' and mOutPtr = DEPTH - 1 then
+                full_n <= '0';
+            elsif push = '0' and pop = '1' then
+                full_n <= '1';
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif push = '1' and pop = '0' then
+                empty_n <= '1';
+            elsif push = '0' and pop = '1' and mOutPtr = 1 then
+                empty_n <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- almost_full_n
+
+    -- almost_empty_n
+
+    -- prog_full_n 
+
+    -- prog_empty_n 
+
+end architecture rtl;
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7okc_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+end myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7okc_ShiftReg;
+
+architecture rtl of myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7okc_ShiftReg is
+type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
+signal SRL_SIG : SRL_ARRAY;
+
+begin
+    dout <= SRL_SIG(conv_integer(addr));
+
+    process (clk)
+    begin
+        if (clk'event and clk = '1') then
+            if (we = '1') then
+                SRL_SIG <= din & SRL_SIG(0 to DEPTH-2);
+            end if;
+        end if;
+    end process;
+
+end architecture rtl;

myproject_prj/solution1/.autopilot/db/vhdl/myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7olc.vhd

@@ -0,0 +1,190 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--RAW latency 1 
+ 
+entity myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7olc is 
+    generic (
+        MEM_STYLE         : string  := "shiftReg";
+        DATA_WIDTH        : integer := 1;
+        ADDR_WIDTH        : integer := 1;
+        DEPTH             : integer := 2);
+    port (
+        clk               : in  std_logic;
+        reset             : in  std_logic;
+
+        -- write
+        if_full_n         : out std_logic;
+        if_write_ce       : in  std_logic;
+        if_write          : in  std_logic;
+        if_din            : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+        -- read 
+
+        if_empty_n        : out std_logic;
+        if_read_ce        : in  std_logic;
+        if_read           : in  std_logic;
+        if_dout           : out std_logic_vector(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture rtl of myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7olc is
+------------------------Task and function--------------
+------------------------Parameter----------------------
+constant SRL_DEPTH  : INTEGER := DEPTH;
+constant SRL_AWIDTH : INTEGER := ADDR_WIDTH;
+------------------------Component----------------------
+    component myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7olc_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+    end component;
+
+    signal addr    : UNSIGNED(SRL_AWIDTH - 1 downto 0);
+    signal push    : STD_LOGIC;
+    signal pop     : STD_LOGIC;
+    signal mOutPtr : UNSIGNED(SRL_AWIDTH downto 0) := (others => '0');
+    signal empty_n : STD_LOGIC := '0';
+    signal full_n   : std_logic := '1';   
+    -- has num_data_valid? no 
+begin
+----------------------- Instantiation -----------------------
+    U_myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7olc_ShiftReg : myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7olc_ShiftReg
+    generic map (
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => SRL_AWIDTH,
+        DEPTH      => SRL_DEPTH)
+    port map (
+        clk        => clk,
+        we         => push,
+        addr       => STD_LOGIC_VECTOR(addr),
+        din        => if_din,
+        dout       => if_dout);
+--------------------------- Body ----------------------------
+    -- has num_data_valid ?  no 
+
+    -- almost full/empty  
+
+    -- program full/empty  
+
+    if_full_n  <= full_n;
+    if_empty_n <= empty_n;
+
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and if_read;
+
+    -- addr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                addr <= (others => '0');
+            elsif push = '1' and pop = '0' and empty_n = '1' then
+                addr <= addr + 1;
+            elsif push = '0' and pop = '1' and mOutPtr /= 1 then
+                addr <= addr - 1;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- mOutPtr
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '0');
+            elsif push = '1' and pop = '0' then
+                mOutPtr <= mOutPtr + 1;
+            elsif push = '0' and pop = '1' then
+                mOutPtr <= mOutPtr - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- full_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif push = '1' and pop = '0' and mOutPtr = DEPTH - 1 then
+                full_n <= '0';
+            elsif push = '0' and pop = '1' then
+                full_n <= '1';
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif push = '1' and pop = '0' then
+                empty_n <= '1';
+            elsif push = '0' and pop = '1' and mOutPtr = 1 then
+                empty_n <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- almost_full_n
+
+    -- almost_empty_n
+
+    -- prog_full_n 
+
+    -- prog_empty_n 
+
+end architecture rtl;
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7olc_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+end myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7olc_ShiftReg;
+
+architecture rtl of myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7olc_ShiftReg is
+type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
+signal SRL_SIG : SRL_ARRAY;
+
+begin
+    dout <= SRL_SIG(conv_integer(addr));
+
+    process (clk)
+    begin
+        if (clk'event and clk = '1') then
+            if (we = '1') then
+                SRL_SIG <= din & SRL_SIG(0 to DEPTH-2);
+            end if;
+        end if;
+    end process;
+
+end architecture rtl;

myproject_prj/solution1/.autopilot/db/vhdl/myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7onc.vhd

@@ -0,0 +1,190 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--RAW latency 1 
+ 
+entity myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7onc is 
+    generic (
+        MEM_STYLE         : string  := "shiftReg";
+        DATA_WIDTH        : integer := 1;
+        ADDR_WIDTH        : integer := 1;
+        DEPTH             : integer := 2);
+    port (
+        clk               : in  std_logic;
+        reset             : in  std_logic;
+
+        -- write
+        if_full_n         : out std_logic;
+        if_write_ce       : in  std_logic;
+        if_write          : in  std_logic;
+        if_din            : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+        -- read 
+
+        if_empty_n        : out std_logic;
+        if_read_ce        : in  std_logic;
+        if_read           : in  std_logic;
+        if_dout           : out std_logic_vector(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture rtl of myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7onc is
+------------------------Task and function--------------
+------------------------Parameter----------------------
+constant SRL_DEPTH  : INTEGER := DEPTH;
+constant SRL_AWIDTH : INTEGER := ADDR_WIDTH;
+------------------------Component----------------------
+    component myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7onc_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+    end component;
+
+    signal addr    : UNSIGNED(SRL_AWIDTH - 1 downto 0);
+    signal push    : STD_LOGIC;
+    signal pop     : STD_LOGIC;
+    signal mOutPtr : UNSIGNED(SRL_AWIDTH downto 0) := (others => '0');
+    signal empty_n : STD_LOGIC := '0';
+    signal full_n   : std_logic := '1';   
+    -- has num_data_valid? no 
+begin
+----------------------- Instantiation -----------------------
+    U_myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7onc_ShiftReg : myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7onc_ShiftReg
+    generic map (
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => SRL_AWIDTH,
+        DEPTH      => SRL_DEPTH)
+    port map (
+        clk        => clk,
+        we         => push,
+        addr       => STD_LOGIC_VECTOR(addr),
+        din        => if_din,
+        dout       => if_dout);
+--------------------------- Body ----------------------------
+    -- has num_data_valid ?  no 
+
+    -- almost full/empty  
+
+    -- program full/empty  
+
+    if_full_n  <= full_n;
+    if_empty_n <= empty_n;
+
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and if_read;
+
+    -- addr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                addr <= (others => '0');
+            elsif push = '1' and pop = '0' and empty_n = '1' then
+                addr <= addr + 1;
+            elsif push = '0' and pop = '1' and mOutPtr /= 1 then
+                addr <= addr - 1;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- mOutPtr
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '0');
+            elsif push = '1' and pop = '0' then
+                mOutPtr <= mOutPtr + 1;
+            elsif push = '0' and pop = '1' then
+                mOutPtr <= mOutPtr - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- full_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif push = '1' and pop = '0' and mOutPtr = DEPTH - 1 then
+                full_n <= '0';
+            elsif push = '0' and pop = '1' then
+                full_n <= '1';
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif push = '1' and pop = '0' then
+                empty_n <= '1';
+            elsif push = '0' and pop = '1' and mOutPtr = 1 then
+                empty_n <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- almost_full_n
+
+    -- almost_empty_n
+
+    -- prog_full_n 
+
+    -- prog_empty_n 
+
+end architecture rtl;
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7onc_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+end myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7onc_ShiftReg;
+
+architecture rtl of myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7onc_ShiftReg is
+type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
+signal SRL_SIG : SRL_ARRAY;
+
+begin
+    dout <= SRL_SIG(conv_integer(addr));
+
+    process (clk)
+    begin
+        if (clk'event and clk = '1') then
+            if (we = '1') then
+                SRL_SIG <= din & SRL_SIG(0 to DEPTH-2);
+            end if;
+        end if;
+    end process;
+
+end architecture rtl;

myproject_prj/solution1/.autopilot/db/vhdl/myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7otc.vhd

@@ -0,0 +1,190 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--RAW latency 1 
+ 
+entity myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7otc is 
+    generic (
+        MEM_STYLE         : string  := "shiftReg";
+        DATA_WIDTH        : integer := 1;
+        ADDR_WIDTH        : integer := 1;
+        DEPTH             : integer := 2);
+    port (
+        clk               : in  std_logic;
+        reset             : in  std_logic;
+
+        -- write
+        if_full_n         : out std_logic;
+        if_write_ce       : in  std_logic;
+        if_write          : in  std_logic;
+        if_din            : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+        -- read 
+
+        if_empty_n        : out std_logic;
+        if_read_ce        : in  std_logic;
+        if_read           : in  std_logic;
+        if_dout           : out std_logic_vector(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture rtl of myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7otc is
+------------------------Task and function--------------
+------------------------Parameter----------------------
+constant SRL_DEPTH  : INTEGER := DEPTH;
+constant SRL_AWIDTH : INTEGER := ADDR_WIDTH;
+------------------------Component----------------------
+    component myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7otc_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+    end component;
+
+    signal addr    : UNSIGNED(SRL_AWIDTH - 1 downto 0);
+    signal push    : STD_LOGIC;
+    signal pop     : STD_LOGIC;
+    signal mOutPtr : UNSIGNED(SRL_AWIDTH downto 0) := (others => '0');
+    signal empty_n : STD_LOGIC := '0';
+    signal full_n   : std_logic := '1';   
+    -- has num_data_valid? no 
+begin
+----------------------- Instantiation -----------------------
+    U_myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7otc_ShiftReg : myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7otc_ShiftReg
+    generic map (
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => SRL_AWIDTH,
+        DEPTH      => SRL_DEPTH)
+    port map (
+        clk        => clk,
+        we         => push,
+        addr       => STD_LOGIC_VECTOR(addr),
+        din        => if_din,
+        dout       => if_dout);
+--------------------------- Body ----------------------------
+    -- has num_data_valid ?  no 
+
+    -- almost full/empty  
+
+    -- program full/empty  
+
+    if_full_n  <= full_n;
+    if_empty_n <= empty_n;
+
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and if_read;
+
+    -- addr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                addr <= (others => '0');
+            elsif push = '1' and pop = '0' and empty_n = '1' then
+                addr <= addr + 1;
+            elsif push = '0' and pop = '1' and mOutPtr /= 1 then
+                addr <= addr - 1;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- mOutPtr
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '0');
+            elsif push = '1' and pop = '0' then
+                mOutPtr <= mOutPtr + 1;
+            elsif push = '0' and pop = '1' then
+                mOutPtr <= mOutPtr - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- full_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif push = '1' and pop = '0' and mOutPtr = DEPTH - 1 then
+                full_n <= '0';
+            elsif push = '0' and pop = '1' then
+                full_n <= '1';
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif push = '1' and pop = '0' then
+                empty_n <= '1';
+            elsif push = '0' and pop = '1' and mOutPtr = 1 then
+                empty_n <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- almost_full_n
+
+    -- almost_empty_n
+
+    -- prog_full_n 
+
+    -- prog_empty_n 
+
+end architecture rtl;
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7otc_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+end myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7otc_ShiftReg;
+
+architecture rtl of myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7otc_ShiftReg is
+type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
+signal SRL_SIG : SRL_ARRAY;
+
+begin
+    dout <= SRL_SIG(conv_integer(addr));
+
+    process (clk)
+    begin
+        if (clk'event and clk = '1') then
+            if (we = '1') then
+                SRL_SIG <= din & SRL_SIG(0 to DEPTH-2);
+            end if;
+        end if;
+    end process;
+
+end architecture rtl;

myproject_prj/solution1/.autopilot/db/vhdl/myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37ozc.vhd

@@ -0,0 +1,190 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--RAW latency 1 
+ 
+entity myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37ozc is 
+    generic (
+        MEM_STYLE         : string  := "shiftReg";
+        DATA_WIDTH        : integer := 1;
+        ADDR_WIDTH        : integer := 1;
+        DEPTH             : integer := 2);
+    port (
+        clk               : in  std_logic;
+        reset             : in  std_logic;
+
+        -- write
+        if_full_n         : out std_logic;
+        if_write_ce       : in  std_logic;
+        if_write          : in  std_logic;
+        if_din            : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+        -- read 
+
+        if_empty_n        : out std_logic;
+        if_read_ce        : in  std_logic;
+        if_read           : in  std_logic;
+        if_dout           : out std_logic_vector(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture rtl of myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37ozc is
+------------------------Task and function--------------
+------------------------Parameter----------------------
+constant SRL_DEPTH  : INTEGER := DEPTH;
+constant SRL_AWIDTH : INTEGER := ADDR_WIDTH;
+------------------------Component----------------------
+    component myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37ozc_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+    end component;
+
+    signal addr    : UNSIGNED(SRL_AWIDTH - 1 downto 0);
+    signal push    : STD_LOGIC;
+    signal pop     : STD_LOGIC;
+    signal mOutPtr : UNSIGNED(SRL_AWIDTH downto 0) := (others => '0');
+    signal empty_n : STD_LOGIC := '0';
+    signal full_n   : std_logic := '1';   
+    -- has num_data_valid? no 
+begin
+----------------------- Instantiation -----------------------
+    U_myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37ozc_ShiftReg : myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37ozc_ShiftReg
+    generic map (
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => SRL_AWIDTH,
+        DEPTH      => SRL_DEPTH)
+    port map (
+        clk        => clk,
+        we         => push,
+        addr       => STD_LOGIC_VECTOR(addr),
+        din        => if_din,
+        dout       => if_dout);
+--------------------------- Body ----------------------------
+    -- has num_data_valid ?  no 
+
+    -- almost full/empty  
+
+    -- program full/empty  
+
+    if_full_n  <= full_n;
+    if_empty_n <= empty_n;
+
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and if_read;
+
+    -- addr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                addr <= (others => '0');
+            elsif push = '1' and pop = '0' and empty_n = '1' then
+                addr <= addr + 1;
+            elsif push = '0' and pop = '1' and mOutPtr /= 1 then
+                addr <= addr - 1;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- mOutPtr
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '0');
+            elsif push = '1' and pop = '0' then
+                mOutPtr <= mOutPtr + 1;
+            elsif push = '0' and pop = '1' then
+                mOutPtr <= mOutPtr - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- full_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif push = '1' and pop = '0' and mOutPtr = DEPTH - 1 then
+                full_n <= '0';
+            elsif push = '0' and pop = '1' then
+                full_n <= '1';
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif push = '1' and pop = '0' then
+                empty_n <= '1';
+            elsif push = '0' and pop = '1' and mOutPtr = 1 then
+                empty_n <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- almost_full_n
+
+    -- almost_empty_n
+
+    -- prog_full_n 
+
+    -- prog_empty_n 
+
+end architecture rtl;
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37ozc_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+end myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37ozc_ShiftReg;
+
+architecture rtl of myproject_start_for_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_8u_config37ozc_ShiftReg is
+type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
+signal SRL_SIG : SRL_ARRAY;
+
+begin
+    dout <= SRL_SIG(conv_integer(addr));
+
+    process (clk)
+    begin
+        if (clk'event and clk = '1') then
+            if (we = '1') then
+                SRL_SIG <= din & SRL_SIG(0 to DEPTH-2);
+            end if;
+        end if;
+    end process;
+
+end architecture rtl;

myproject_prj/solution1/.autopilot/db/vhdl/myproject_start_for_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_U0.vhd

@@ -0,0 +1,190 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--RAW latency 1 
+ 
+entity myproject_start_for_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_U0 is 
+    generic (
+        MEM_STYLE         : string  := "shiftReg";
+        DATA_WIDTH        : integer := 1;
+        ADDR_WIDTH        : integer := 1;
+        DEPTH             : integer := 2);
+    port (
+        clk               : in  std_logic;
+        reset             : in  std_logic;
+
+        -- write
+        if_full_n         : out std_logic;
+        if_write_ce       : in  std_logic;
+        if_write          : in  std_logic;
+        if_din            : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+        -- read 
+
+        if_empty_n        : out std_logic;
+        if_read_ce        : in  std_logic;
+        if_read           : in  std_logic;
+        if_dout           : out std_logic_vector(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture rtl of myproject_start_for_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_U0 is
+------------------------Task and function--------------
+------------------------Parameter----------------------
+constant SRL_DEPTH  : INTEGER := DEPTH;
+constant SRL_AWIDTH : INTEGER := ADDR_WIDTH;
+------------------------Component----------------------
+    component myproject_start_for_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_U0_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+    end component;
+
+    signal addr    : UNSIGNED(SRL_AWIDTH - 1 downto 0);
+    signal push    : STD_LOGIC;
+    signal pop     : STD_LOGIC;
+    signal mOutPtr : UNSIGNED(SRL_AWIDTH downto 0) := (others => '0');
+    signal empty_n : STD_LOGIC := '0';
+    signal full_n   : std_logic := '1';   
+    -- has num_data_valid? no 
+begin
+----------------------- Instantiation -----------------------
+    U_myproject_start_for_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_U0_ShiftReg : myproject_start_for_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_U0_ShiftReg
+    generic map (
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => SRL_AWIDTH,
+        DEPTH      => SRL_DEPTH)
+    port map (
+        clk        => clk,
+        we         => push,
+        addr       => STD_LOGIC_VECTOR(addr),
+        din        => if_din,
+        dout       => if_dout);
+--------------------------- Body ----------------------------
+    -- has num_data_valid ?  no 
+
+    -- almost full/empty  
+
+    -- program full/empty  
+
+    if_full_n  <= full_n;
+    if_empty_n <= empty_n;
+
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and if_read;
+
+    -- addr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                addr <= (others => '0');
+            elsif push = '1' and pop = '0' and empty_n = '1' then
+                addr <= addr + 1;
+            elsif push = '0' and pop = '1' and mOutPtr /= 1 then
+                addr <= addr - 1;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- mOutPtr
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '0');
+            elsif push = '1' and pop = '0' then
+                mOutPtr <= mOutPtr + 1;
+            elsif push = '0' and pop = '1' then
+                mOutPtr <= mOutPtr - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- full_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif push = '1' and pop = '0' and mOutPtr = DEPTH - 1 then
+                full_n <= '0';
+            elsif push = '0' and pop = '1' then
+                full_n <= '1';
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif push = '1' and pop = '0' then
+                empty_n <= '1';
+            elsif push = '0' and pop = '1' and mOutPtr = 1 then
+                empty_n <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- almost_full_n
+
+    -- almost_empty_n
+
+    -- prog_full_n 
+
+    -- prog_empty_n 
+
+end architecture rtl;
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity myproject_start_for_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_U0_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+end myproject_start_for_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_U0_ShiftReg;
+
+architecture rtl of myproject_start_for_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_32u_config12_U0_ShiftReg is
+type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
+signal SRL_SIG : SRL_ARRAY;
+
+begin
+    dout <= SRL_SIG(conv_integer(addr));
+
+    process (clk)
+    begin
+        if (clk'event and clk = '1') then
+            if (we = '1') then
+                SRL_SIG <= din & SRL_SIG(0 to DEPTH-2);
+            end if;
+        end if;
+    end process;
+
+end architecture rtl;

myproject_prj/solution1/.autopilot/db/vhdl/myproject_start_for_pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config60_U0.vhd

@@ -0,0 +1,190 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--RAW latency 1 
+ 
+entity myproject_start_for_pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config60_U0 is 
+    generic (
+        MEM_STYLE         : string  := "shiftReg";
+        DATA_WIDTH        : integer := 1;
+        ADDR_WIDTH        : integer := 1;
+        DEPTH             : integer := 2);
+    port (
+        clk               : in  std_logic;
+        reset             : in  std_logic;
+
+        -- write
+        if_full_n         : out std_logic;
+        if_write_ce       : in  std_logic;
+        if_write          : in  std_logic;
+        if_din            : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+        -- read 
+
+        if_empty_n        : out std_logic;
+        if_read_ce        : in  std_logic;
+        if_read           : in  std_logic;
+        if_dout           : out std_logic_vector(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture rtl of myproject_start_for_pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config60_U0 is
+------------------------Task and function--------------
+------------------------Parameter----------------------
+constant SRL_DEPTH  : INTEGER := DEPTH;
+constant SRL_AWIDTH : INTEGER := ADDR_WIDTH;
+------------------------Component----------------------
+    component myproject_start_for_pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config60_U0_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+    end component;
+
+    signal addr    : UNSIGNED(SRL_AWIDTH - 1 downto 0);
+    signal push    : STD_LOGIC;
+    signal pop     : STD_LOGIC;
+    signal mOutPtr : UNSIGNED(SRL_AWIDTH downto 0) := (others => '0');
+    signal empty_n : STD_LOGIC := '0';
+    signal full_n   : std_logic := '1';   
+    -- has num_data_valid? no 
+begin
+----------------------- Instantiation -----------------------
+    U_myproject_start_for_pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config60_U0_ShiftReg : myproject_start_for_pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config60_U0_ShiftReg
+    generic map (
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => SRL_AWIDTH,
+        DEPTH      => SRL_DEPTH)
+    port map (
+        clk        => clk,
+        we         => push,
+        addr       => STD_LOGIC_VECTOR(addr),
+        din        => if_din,
+        dout       => if_dout);
+--------------------------- Body ----------------------------
+    -- has num_data_valid ?  no 
+
+    -- almost full/empty  
+
+    -- program full/empty  
+
+    if_full_n  <= full_n;
+    if_empty_n <= empty_n;
+
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and if_read;
+
+    -- addr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                addr <= (others => '0');
+            elsif push = '1' and pop = '0' and empty_n = '1' then
+                addr <= addr + 1;
+            elsif push = '0' and pop = '1' and mOutPtr /= 1 then
+                addr <= addr - 1;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- mOutPtr
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '0');
+            elsif push = '1' and pop = '0' then
+                mOutPtr <= mOutPtr + 1;
+            elsif push = '0' and pop = '1' then
+                mOutPtr <= mOutPtr - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- full_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif push = '1' and pop = '0' and mOutPtr = DEPTH - 1 then
+                full_n <= '0';
+            elsif push = '0' and pop = '1' then
+                full_n <= '1';
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif push = '1' and pop = '0' then
+                empty_n <= '1';
+            elsif push = '0' and pop = '1' and mOutPtr = 1 then
+                empty_n <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- almost_full_n
+
+    -- almost_empty_n
+
+    -- prog_full_n 
+
+    -- prog_empty_n 
+
+end architecture rtl;
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity myproject_start_for_pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config60_U0_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+end myproject_start_for_pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config60_U0_ShiftReg;
+
+architecture rtl of myproject_start_for_pointwise_conv_2d_cl_array_array_ap_fixed_36_16_5_3_0_1u_config60_U0_ShiftReg is
+type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
+signal SRL_SIG : SRL_ARRAY;
+
+begin
+    dout <= SRL_SIG(conv_integer(addr));
+
+    process (clk)
+    begin
+        if (clk'event and clk = '1') then
+            if (we = '1') then
+                SRL_SIG <= din & SRL_SIG(0 to DEPTH-2);
+            end if;
+        end if;
+    end process;
+
+end architecture rtl;

myproject_prj/solution1/.autopilot/db/vhdl/myproject_start_for_pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6oic.vhd

@@ -0,0 +1,190 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--RAW latency 1 
+ 
+entity myproject_start_for_pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6oic is 
+    generic (
+        MEM_STYLE         : string  := "shiftReg";
+        DATA_WIDTH        : integer := 1;
+        ADDR_WIDTH        : integer := 1;
+        DEPTH             : integer := 2);
+    port (
+        clk               : in  std_logic;
+        reset             : in  std_logic;
+
+        -- write
+        if_full_n         : out std_logic;
+        if_write_ce       : in  std_logic;
+        if_write          : in  std_logic;
+        if_din            : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+        -- read 
+
+        if_empty_n        : out std_logic;
+        if_read_ce        : in  std_logic;
+        if_read           : in  std_logic;
+        if_dout           : out std_logic_vector(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture rtl of myproject_start_for_pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6oic is
+------------------------Task and function--------------
+------------------------Parameter----------------------
+constant SRL_DEPTH  : INTEGER := DEPTH;
+constant SRL_AWIDTH : INTEGER := ADDR_WIDTH;
+------------------------Component----------------------
+    component myproject_start_for_pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6oic_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+    end component;
+
+    signal addr    : UNSIGNED(SRL_AWIDTH - 1 downto 0);
+    signal push    : STD_LOGIC;
+    signal pop     : STD_LOGIC;
+    signal mOutPtr : UNSIGNED(SRL_AWIDTH downto 0) := (others => '0');
+    signal empty_n : STD_LOGIC := '0';
+    signal full_n   : std_logic := '1';   
+    -- has num_data_valid? no 
+begin
+----------------------- Instantiation -----------------------
+    U_myproject_start_for_pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6oic_ShiftReg : myproject_start_for_pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6oic_ShiftReg
+    generic map (
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => SRL_AWIDTH,
+        DEPTH      => SRL_DEPTH)
+    port map (
+        clk        => clk,
+        we         => push,
+        addr       => STD_LOGIC_VECTOR(addr),
+        din        => if_din,
+        dout       => if_dout);
+--------------------------- Body ----------------------------
+    -- has num_data_valid ?  no 
+
+    -- almost full/empty  
+
+    -- program full/empty  
+
+    if_full_n  <= full_n;
+    if_empty_n <= empty_n;
+
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and if_read;
+
+    -- addr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                addr <= (others => '0');
+            elsif push = '1' and pop = '0' and empty_n = '1' then
+                addr <= addr + 1;
+            elsif push = '0' and pop = '1' and mOutPtr /= 1 then
+                addr <= addr - 1;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- mOutPtr
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '0');
+            elsif push = '1' and pop = '0' then
+                mOutPtr <= mOutPtr + 1;
+            elsif push = '0' and pop = '1' then
+                mOutPtr <= mOutPtr - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- full_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif push = '1' and pop = '0' and mOutPtr = DEPTH - 1 then
+                full_n <= '0';
+            elsif push = '0' and pop = '1' then
+                full_n <= '1';
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif push = '1' and pop = '0' then
+                empty_n <= '1';
+            elsif push = '0' and pop = '1' and mOutPtr = 1 then
+                empty_n <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- almost_full_n
+
+    -- almost_empty_n
+
+    -- prog_full_n 
+
+    -- prog_empty_n 
+
+end architecture rtl;
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity myproject_start_for_pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6oic_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+end myproject_start_for_pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6oic_ShiftReg;
+
+architecture rtl of myproject_start_for_pooling2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config6oic_ShiftReg is
+type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
+signal SRL_SIG : SRL_ARRAY;
+
+begin
+    dout <= SRL_SIG(conv_integer(addr));
+
+    process (clk)
+    begin
+        if (clk'event and clk = '1') then
+            if (we = '1') then
+                SRL_SIG <= din & SRL_SIG(0 to DEPTH-2);
+            end if;
+        end if;
+    end process;
+
+end architecture rtl;

myproject_prj/solution1/.autopilot/db/vhdl/myproject_start_for_pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_U0.vhd

@@ -0,0 +1,190 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--RAW latency 1 
+ 
+entity myproject_start_for_pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_U0 is 
+    generic (
+        MEM_STYLE         : string  := "shiftReg";
+        DATA_WIDTH        : integer := 1;
+        ADDR_WIDTH        : integer := 1;
+        DEPTH             : integer := 2);
+    port (
+        clk               : in  std_logic;
+        reset             : in  std_logic;
+
+        -- write
+        if_full_n         : out std_logic;
+        if_write_ce       : in  std_logic;
+        if_write          : in  std_logic;
+        if_din            : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+        -- read 
+
+        if_empty_n        : out std_logic;
+        if_read_ce        : in  std_logic;
+        if_read           : in  std_logic;
+        if_dout           : out std_logic_vector(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture rtl of myproject_start_for_pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_U0 is
+------------------------Task and function--------------
+------------------------Parameter----------------------
+constant SRL_DEPTH  : INTEGER := DEPTH;
+constant SRL_AWIDTH : INTEGER := ADDR_WIDTH;
+------------------------Component----------------------
+    component myproject_start_for_pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_U0_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+    end component;
+
+    signal addr    : UNSIGNED(SRL_AWIDTH - 1 downto 0);
+    signal push    : STD_LOGIC;
+    signal pop     : STD_LOGIC;
+    signal mOutPtr : UNSIGNED(SRL_AWIDTH downto 0) := (others => '0');
+    signal empty_n : STD_LOGIC := '0';
+    signal full_n   : std_logic := '1';   
+    -- has num_data_valid? no 
+begin
+----------------------- Instantiation -----------------------
+    U_myproject_start_for_pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_U0_ShiftReg : myproject_start_for_pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_U0_ShiftReg
+    generic map (
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => SRL_AWIDTH,
+        DEPTH      => SRL_DEPTH)
+    port map (
+        clk        => clk,
+        we         => push,
+        addr       => STD_LOGIC_VECTOR(addr),
+        din        => if_din,
+        dout       => if_dout);
+--------------------------- Body ----------------------------
+    -- has num_data_valid ?  no 
+
+    -- almost full/empty  
+
+    -- program full/empty  
+
+    if_full_n  <= full_n;
+    if_empty_n <= empty_n;
+
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and if_read;
+
+    -- addr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                addr <= (others => '0');
+            elsif push = '1' and pop = '0' and empty_n = '1' then
+                addr <= addr + 1;
+            elsif push = '0' and pop = '1' and mOutPtr /= 1 then
+                addr <= addr - 1;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- mOutPtr
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '0');
+            elsif push = '1' and pop = '0' then
+                mOutPtr <= mOutPtr + 1;
+            elsif push = '0' and pop = '1' then
+                mOutPtr <= mOutPtr - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- full_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif push = '1' and pop = '0' and mOutPtr = DEPTH - 1 then
+                full_n <= '0';
+            elsif push = '0' and pop = '1' then
+                full_n <= '1';
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif push = '1' and pop = '0' then
+                empty_n <= '1';
+            elsif push = '0' and pop = '1' and mOutPtr = 1 then
+                empty_n <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- almost_full_n
+
+    -- almost_empty_n
+
+    -- prog_full_n 
+
+    -- prog_empty_n 
+
+end architecture rtl;
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity myproject_start_for_pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_U0_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+end myproject_start_for_pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_U0_ShiftReg;
+
+architecture rtl of myproject_start_for_pooling2d_cl_array_array_ap_fixed_16_6_5_3_0_16u_config11_U0_ShiftReg is
+type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
+signal SRL_SIG : SRL_ARRAY;
+
+begin
+    dout <= SRL_SIG(conv_integer(addr));
+
+    process (clk)
+    begin
+        if (clk'event and clk = '1') then
+            if (we = '1') then
+                SRL_SIG <= din & SRL_SIG(0 to DEPTH-2);
+            end if;
+        end if;
+    end process;
+
+end architecture rtl;

myproject_prj/solution1/.autopilot/db/vhdl/myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30oDc.vhd

@@ -0,0 +1,190 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--RAW latency 1 
+ 
+entity myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30oDc is 
+    generic (
+        MEM_STYLE         : string  := "shiftReg";
+        DATA_WIDTH        : integer := 1;
+        ADDR_WIDTH        : integer := 1;
+        DEPTH             : integer := 2);
+    port (
+        clk               : in  std_logic;
+        reset             : in  std_logic;
+
+        -- write
+        if_full_n         : out std_logic;
+        if_write_ce       : in  std_logic;
+        if_write          : in  std_logic;
+        if_din            : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+        -- read 
+
+        if_empty_n        : out std_logic;
+        if_read_ce        : in  std_logic;
+        if_read           : in  std_logic;
+        if_dout           : out std_logic_vector(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture rtl of myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30oDc is
+------------------------Task and function--------------
+------------------------Parameter----------------------
+constant SRL_DEPTH  : INTEGER := DEPTH;
+constant SRL_AWIDTH : INTEGER := ADDR_WIDTH;
+------------------------Component----------------------
+    component myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30oDc_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+    end component;
+
+    signal addr    : UNSIGNED(SRL_AWIDTH - 1 downto 0);
+    signal push    : STD_LOGIC;
+    signal pop     : STD_LOGIC;
+    signal mOutPtr : UNSIGNED(SRL_AWIDTH downto 0) := (others => '0');
+    signal empty_n : STD_LOGIC := '0';
+    signal full_n   : std_logic := '1';   
+    -- has num_data_valid? no 
+begin
+----------------------- Instantiation -----------------------
+    U_myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30oDc_ShiftReg : myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30oDc_ShiftReg
+    generic map (
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => SRL_AWIDTH,
+        DEPTH      => SRL_DEPTH)
+    port map (
+        clk        => clk,
+        we         => push,
+        addr       => STD_LOGIC_VECTOR(addr),
+        din        => if_din,
+        dout       => if_dout);
+--------------------------- Body ----------------------------
+    -- has num_data_valid ?  no 
+
+    -- almost full/empty  
+
+    -- program full/empty  
+
+    if_full_n  <= full_n;
+    if_empty_n <= empty_n;
+
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and if_read;
+
+    -- addr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                addr <= (others => '0');
+            elsif push = '1' and pop = '0' and empty_n = '1' then
+                addr <= addr + 1;
+            elsif push = '0' and pop = '1' and mOutPtr /= 1 then
+                addr <= addr - 1;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- mOutPtr
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '0');
+            elsif push = '1' and pop = '0' then
+                mOutPtr <= mOutPtr + 1;
+            elsif push = '0' and pop = '1' then
+                mOutPtr <= mOutPtr - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- full_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif push = '1' and pop = '0' and mOutPtr = DEPTH - 1 then
+                full_n <= '0';
+            elsif push = '0' and pop = '1' then
+                full_n <= '1';
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif push = '1' and pop = '0' then
+                empty_n <= '1';
+            elsif push = '0' and pop = '1' and mOutPtr = 1 then
+                empty_n <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- almost_full_n
+
+    -- almost_empty_n
+
+    -- prog_full_n 
+
+    -- prog_empty_n 
+
+end architecture rtl;
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30oDc_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+end myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30oDc_ShiftReg;
+
+architecture rtl of myproject_start_for_relu_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_relu_config30oDc_ShiftReg is
+type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
+signal SRL_SIG : SRL_ARRAY;
+
+begin
+    dout <= SRL_SIG(conv_integer(addr));
+
+    process (clk)
+    begin
+        if (clk'event and clk = '1') then
+            if (we = '1') then
+                SRL_SIG <= din & SRL_SIG(0 to DEPTH-2);
+            end if;
+        end if;
+    end process;
+
+end architecture rtl;

myproject_prj/solution1/.autopilot/db/vhdl/myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13oxc.vhd

@@ -0,0 +1,190 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--RAW latency 1 
+ 
+entity myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13oxc is 
+    generic (
+        MEM_STYLE         : string  := "shiftReg";
+        DATA_WIDTH        : integer := 1;
+        ADDR_WIDTH        : integer := 1;
+        DEPTH             : integer := 2);
+    port (
+        clk               : in  std_logic;
+        reset             : in  std_logic;
+
+        -- write
+        if_full_n         : out std_logic;
+        if_write_ce       : in  std_logic;
+        if_write          : in  std_logic;
+        if_din            : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+        -- read 
+
+        if_empty_n        : out std_logic;
+        if_read_ce        : in  std_logic;
+        if_read           : in  std_logic;
+        if_dout           : out std_logic_vector(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture rtl of myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13oxc is
+------------------------Task and function--------------
+------------------------Parameter----------------------
+constant SRL_DEPTH  : INTEGER := DEPTH;
+constant SRL_AWIDTH : INTEGER := ADDR_WIDTH;
+------------------------Component----------------------
+    component myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13oxc_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+    end component;
+
+    signal addr    : UNSIGNED(SRL_AWIDTH - 1 downto 0);
+    signal push    : STD_LOGIC;
+    signal pop     : STD_LOGIC;
+    signal mOutPtr : UNSIGNED(SRL_AWIDTH downto 0) := (others => '0');
+    signal empty_n : STD_LOGIC := '0';
+    signal full_n   : std_logic := '1';   
+    -- has num_data_valid? no 
+begin
+----------------------- Instantiation -----------------------
+    U_myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13oxc_ShiftReg : myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13oxc_ShiftReg
+    generic map (
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => SRL_AWIDTH,
+        DEPTH      => SRL_DEPTH)
+    port map (
+        clk        => clk,
+        we         => push,
+        addr       => STD_LOGIC_VECTOR(addr),
+        din        => if_din,
+        dout       => if_dout);
+--------------------------- Body ----------------------------
+    -- has num_data_valid ?  no 
+
+    -- almost full/empty  
+
+    -- program full/empty  
+
+    if_full_n  <= full_n;
+    if_empty_n <= empty_n;
+
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and if_read;
+
+    -- addr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                addr <= (others => '0');
+            elsif push = '1' and pop = '0' and empty_n = '1' then
+                addr <= addr + 1;
+            elsif push = '0' and pop = '1' and mOutPtr /= 1 then
+                addr <= addr - 1;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- mOutPtr
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '0');
+            elsif push = '1' and pop = '0' then
+                mOutPtr <= mOutPtr + 1;
+            elsif push = '0' and pop = '1' then
+                mOutPtr <= mOutPtr - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- full_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif push = '1' and pop = '0' and mOutPtr = DEPTH - 1 then
+                full_n <= '0';
+            elsif push = '0' and pop = '1' then
+                full_n <= '1';
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif push = '1' and pop = '0' then
+                empty_n <= '1';
+            elsif push = '0' and pop = '1' and mOutPtr = 1 then
+                empty_n <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- almost_full_n
+
+    -- almost_empty_n
+
+    -- prog_full_n 
+
+    -- prog_empty_n 
+
+end architecture rtl;
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13oxc_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+end myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13oxc_ShiftReg;
+
+architecture rtl of myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config13oxc_ShiftReg is
+type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
+signal SRL_SIG : SRL_ARRAY;
+
+begin
+    dout <= SRL_SIG(conv_integer(addr));
+
+    process (clk)
+    begin
+        if (clk'event and clk = '1') then
+            if (we = '1') then
+                SRL_SIG <= din & SRL_SIG(0 to DEPTH-2);
+            end if;
+        end if;
+    end process;
+
+end architecture rtl;

myproject_prj/solution1/.autopilot/db/vhdl/myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26otc.vhd

@@ -0,0 +1,190 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--RAW latency 1 
+ 
+entity myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26otc is 
+    generic (
+        MEM_STYLE         : string  := "shiftReg";
+        DATA_WIDTH        : integer := 1;
+        ADDR_WIDTH        : integer := 1;
+        DEPTH             : integer := 2);
+    port (
+        clk               : in  std_logic;
+        reset             : in  std_logic;
+
+        -- write
+        if_full_n         : out std_logic;
+        if_write_ce       : in  std_logic;
+        if_write          : in  std_logic;
+        if_din            : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+        -- read 
+
+        if_empty_n        : out std_logic;
+        if_read_ce        : in  std_logic;
+        if_read           : in  std_logic;
+        if_dout           : out std_logic_vector(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture rtl of myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26otc is
+------------------------Task and function--------------
+------------------------Parameter----------------------
+constant SRL_DEPTH  : INTEGER := DEPTH;
+constant SRL_AWIDTH : INTEGER := ADDR_WIDTH;
+------------------------Component----------------------
+    component myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26otc_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+    end component;
+
+    signal addr    : UNSIGNED(SRL_AWIDTH - 1 downto 0);
+    signal push    : STD_LOGIC;
+    signal pop     : STD_LOGIC;
+    signal mOutPtr : UNSIGNED(SRL_AWIDTH downto 0) := (others => '0');
+    signal empty_n : STD_LOGIC := '0';
+    signal full_n   : std_logic := '1';   
+    -- has num_data_valid? no 
+begin
+----------------------- Instantiation -----------------------
+    U_myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26otc_ShiftReg : myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26otc_ShiftReg
+    generic map (
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => SRL_AWIDTH,
+        DEPTH      => SRL_DEPTH)
+    port map (
+        clk        => clk,
+        we         => push,
+        addr       => STD_LOGIC_VECTOR(addr),
+        din        => if_din,
+        dout       => if_dout);
+--------------------------- Body ----------------------------
+    -- has num_data_valid ?  no 
+
+    -- almost full/empty  
+
+    -- program full/empty  
+
+    if_full_n  <= full_n;
+    if_empty_n <= empty_n;
+
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and if_read;
+
+    -- addr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                addr <= (others => '0');
+            elsif push = '1' and pop = '0' and empty_n = '1' then
+                addr <= addr + 1;
+            elsif push = '0' and pop = '1' and mOutPtr /= 1 then
+                addr <= addr - 1;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- mOutPtr
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '0');
+            elsif push = '1' and pop = '0' then
+                mOutPtr <= mOutPtr + 1;
+            elsif push = '0' and pop = '1' then
+                mOutPtr <= mOutPtr - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- full_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif push = '1' and pop = '0' and mOutPtr = DEPTH - 1 then
+                full_n <= '0';
+            elsif push = '0' and pop = '1' then
+                full_n <= '1';
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif push = '1' and pop = '0' then
+                empty_n <= '1';
+            elsif push = '0' and pop = '1' and mOutPtr = 1 then
+                empty_n <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- almost_full_n
+
+    -- almost_empty_n
+
+    -- prog_full_n 
+
+    -- prog_empty_n 
+
+end architecture rtl;
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26otc_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+end myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26otc_ShiftReg;
+
+architecture rtl of myproject_start_for_relu_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_relu_config26otc_ShiftReg is
+type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
+signal SRL_SIG : SRL_ARRAY;
+
+begin
+    dout <= SRL_SIG(conv_integer(addr));
+
+    process (clk)
+    begin
+        if (clk'event and clk = '1') then
+            if (we = '1') then
+                SRL_SIG <= din & SRL_SIG(0 to DEPTH-2);
+            end if;
+        end if;
+    end process;
+
+end architecture rtl;

myproject_prj/solution1/.autopilot/db/vhdl/myproject_start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18oqc.vhd

@@ -0,0 +1,190 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--RAW latency 1 
+ 
+entity myproject_start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18oqc is 
+    generic (
+        MEM_STYLE         : string  := "shiftReg";
+        DATA_WIDTH        : integer := 1;
+        ADDR_WIDTH        : integer := 1;
+        DEPTH             : integer := 2);
+    port (
+        clk               : in  std_logic;
+        reset             : in  std_logic;
+
+        -- write
+        if_full_n         : out std_logic;
+        if_write_ce       : in  std_logic;
+        if_write          : in  std_logic;
+        if_din            : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+        -- read 
+
+        if_empty_n        : out std_logic;
+        if_read_ce        : in  std_logic;
+        if_read           : in  std_logic;
+        if_dout           : out std_logic_vector(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture rtl of myproject_start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18oqc is
+------------------------Task and function--------------
+------------------------Parameter----------------------
+constant SRL_DEPTH  : INTEGER := DEPTH;
+constant SRL_AWIDTH : INTEGER := ADDR_WIDTH;
+------------------------Component----------------------
+    component myproject_start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18oqc_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+    end component;
+
+    signal addr    : UNSIGNED(SRL_AWIDTH - 1 downto 0);
+    signal push    : STD_LOGIC;
+    signal pop     : STD_LOGIC;
+    signal mOutPtr : UNSIGNED(SRL_AWIDTH downto 0) := (others => '0');
+    signal empty_n : STD_LOGIC := '0';
+    signal full_n   : std_logic := '1';   
+    -- has num_data_valid? no 
+begin
+----------------------- Instantiation -----------------------
+    U_myproject_start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18oqc_ShiftReg : myproject_start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18oqc_ShiftReg
+    generic map (
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => SRL_AWIDTH,
+        DEPTH      => SRL_DEPTH)
+    port map (
+        clk        => clk,
+        we         => push,
+        addr       => STD_LOGIC_VECTOR(addr),
+        din        => if_din,
+        dout       => if_dout);
+--------------------------- Body ----------------------------
+    -- has num_data_valid ?  no 
+
+    -- almost full/empty  
+
+    -- program full/empty  
+
+    if_full_n  <= full_n;
+    if_empty_n <= empty_n;
+
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and if_read;
+
+    -- addr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                addr <= (others => '0');
+            elsif push = '1' and pop = '0' and empty_n = '1' then
+                addr <= addr + 1;
+            elsif push = '0' and pop = '1' and mOutPtr /= 1 then
+                addr <= addr - 1;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- mOutPtr
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '0');
+            elsif push = '1' and pop = '0' then
+                mOutPtr <= mOutPtr + 1;
+            elsif push = '0' and pop = '1' then
+                mOutPtr <= mOutPtr - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- full_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif push = '1' and pop = '0' and mOutPtr = DEPTH - 1 then
+                full_n <= '0';
+            elsif push = '0' and pop = '1' then
+                full_n <= '1';
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif push = '1' and pop = '0' then
+                empty_n <= '1';
+            elsif push = '0' and pop = '1' and mOutPtr = 1 then
+                empty_n <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- almost_full_n
+
+    -- almost_empty_n
+
+    -- prog_full_n 
+
+    -- prog_empty_n 
+
+end architecture rtl;
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity myproject_start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18oqc_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+end myproject_start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18oqc_ShiftReg;
+
+architecture rtl of myproject_start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config18oqc_ShiftReg is
+type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
+signal SRL_SIG : SRL_ARRAY;
+
+begin
+    dout <= SRL_SIG(conv_integer(addr));
+
+    process (clk)
+    begin
+        if (clk'event and clk = '1') then
+            if (we = '1') then
+                SRL_SIG <= din & SRL_SIG(0 to DEPTH-2);
+            end if;
+        end if;
+    end process;
+
+end architecture rtl;

myproject_prj/solution1/.autopilot/db/vhdl/myproject_start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20osc.vhd

@@ -0,0 +1,190 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--RAW latency 1 
+ 
+entity myproject_start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20osc is 
+    generic (
+        MEM_STYLE         : string  := "shiftReg";
+        DATA_WIDTH        : integer := 1;
+        ADDR_WIDTH        : integer := 1;
+        DEPTH             : integer := 2);
+    port (
+        clk               : in  std_logic;
+        reset             : in  std_logic;
+
+        -- write
+        if_full_n         : out std_logic;
+        if_write_ce       : in  std_logic;
+        if_write          : in  std_logic;
+        if_din            : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+        -- read 
+
+        if_empty_n        : out std_logic;
+        if_read_ce        : in  std_logic;
+        if_read           : in  std_logic;
+        if_dout           : out std_logic_vector(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture rtl of myproject_start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20osc is
+------------------------Task and function--------------
+------------------------Parameter----------------------
+constant SRL_DEPTH  : INTEGER := DEPTH;
+constant SRL_AWIDTH : INTEGER := ADDR_WIDTH;
+------------------------Component----------------------
+    component myproject_start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20osc_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+    end component;
+
+    signal addr    : UNSIGNED(SRL_AWIDTH - 1 downto 0);
+    signal push    : STD_LOGIC;
+    signal pop     : STD_LOGIC;
+    signal mOutPtr : UNSIGNED(SRL_AWIDTH downto 0) := (others => '0');
+    signal empty_n : STD_LOGIC := '0';
+    signal full_n   : std_logic := '1';   
+    -- has num_data_valid? no 
+begin
+----------------------- Instantiation -----------------------
+    U_myproject_start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20osc_ShiftReg : myproject_start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20osc_ShiftReg
+    generic map (
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => SRL_AWIDTH,
+        DEPTH      => SRL_DEPTH)
+    port map (
+        clk        => clk,
+        we         => push,
+        addr       => STD_LOGIC_VECTOR(addr),
+        din        => if_din,
+        dout       => if_dout);
+--------------------------- Body ----------------------------
+    -- has num_data_valid ?  no 
+
+    -- almost full/empty  
+
+    -- program full/empty  
+
+    if_full_n  <= full_n;
+    if_empty_n <= empty_n;
+
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and if_read;
+
+    -- addr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                addr <= (others => '0');
+            elsif push = '1' and pop = '0' and empty_n = '1' then
+                addr <= addr + 1;
+            elsif push = '0' and pop = '1' and mOutPtr /= 1 then
+                addr <= addr - 1;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- mOutPtr
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '0');
+            elsif push = '1' and pop = '0' then
+                mOutPtr <= mOutPtr + 1;
+            elsif push = '0' and pop = '1' then
+                mOutPtr <= mOutPtr - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- full_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif push = '1' and pop = '0' and mOutPtr = DEPTH - 1 then
+                full_n <= '0';
+            elsif push = '0' and pop = '1' then
+                full_n <= '1';
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif push = '1' and pop = '0' then
+                empty_n <= '1';
+            elsif push = '0' and pop = '1' and mOutPtr = 1 then
+                empty_n <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- almost_full_n
+
+    -- almost_empty_n
+
+    -- prog_full_n 
+
+    -- prog_empty_n 
+
+end architecture rtl;
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity myproject_start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20osc_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+end myproject_start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20osc_ShiftReg;
+
+architecture rtl of myproject_start_for_relu_array_ap_fixed_64u_array_ap_fixed_16_6_5_3_0_64u_relu_config20osc_ShiftReg is
+type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
+signal SRL_SIG : SRL_ARRAY;
+
+begin
+    dout <= SRL_SIG(conv_integer(addr));
+
+    process (clk)
+    begin
+        if (clk'event and clk = '1') then
+            if (we = '1') then
+                SRL_SIG <= din & SRL_SIG(0 to DEPTH-2);
+            end if;
+        end if;
+    end process;
+
+end architecture rtl;

myproject_prj/solution1/.autopilot/db/vhdl/myproject_start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_U0.vhd

@@ -0,0 +1,190 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--RAW latency 1 
+ 
+entity myproject_start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_U0 is 
+    generic (
+        MEM_STYLE         : string  := "shiftReg";
+        DATA_WIDTH        : integer := 1;
+        ADDR_WIDTH        : integer := 1;
+        DEPTH             : integer := 2);
+    port (
+        clk               : in  std_logic;
+        reset             : in  std_logic;
+
+        -- write
+        if_full_n         : out std_logic;
+        if_write_ce       : in  std_logic;
+        if_write          : in  std_logic;
+        if_din            : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+        -- read 
+
+        if_empty_n        : out std_logic;
+        if_read_ce        : in  std_logic;
+        if_read           : in  std_logic;
+        if_dout           : out std_logic_vector(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture rtl of myproject_start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_U0 is
+------------------------Task and function--------------
+------------------------Parameter----------------------
+constant SRL_DEPTH  : INTEGER := DEPTH;
+constant SRL_AWIDTH : INTEGER := ADDR_WIDTH;
+------------------------Component----------------------
+    component myproject_start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_U0_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+    end component;
+
+    signal addr    : UNSIGNED(SRL_AWIDTH - 1 downto 0);
+    signal push    : STD_LOGIC;
+    signal pop     : STD_LOGIC;
+    signal mOutPtr : UNSIGNED(SRL_AWIDTH downto 0) := (others => '0');
+    signal empty_n : STD_LOGIC := '0';
+    signal full_n   : std_logic := '1';   
+    -- has num_data_valid? no 
+begin
+----------------------- Instantiation -----------------------
+    U_myproject_start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_U0_ShiftReg : myproject_start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_U0_ShiftReg
+    generic map (
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => SRL_AWIDTH,
+        DEPTH      => SRL_DEPTH)
+    port map (
+        clk        => clk,
+        we         => push,
+        addr       => STD_LOGIC_VECTOR(addr),
+        din        => if_din,
+        dout       => if_dout);
+--------------------------- Body ----------------------------
+    -- has num_data_valid ?  no 
+
+    -- almost full/empty  
+
+    -- program full/empty  
+
+    if_full_n  <= full_n;
+    if_empty_n <= empty_n;
+
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and if_read;
+
+    -- addr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                addr <= (others => '0');
+            elsif push = '1' and pop = '0' and empty_n = '1' then
+                addr <= addr + 1;
+            elsif push = '0' and pop = '1' and mOutPtr /= 1 then
+                addr <= addr - 1;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- mOutPtr
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '0');
+            elsif push = '1' and pop = '0' then
+                mOutPtr <= mOutPtr + 1;
+            elsif push = '0' and pop = '1' then
+                mOutPtr <= mOutPtr - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- full_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif push = '1' and pop = '0' and mOutPtr = DEPTH - 1 then
+                full_n <= '0';
+            elsif push = '0' and pop = '1' then
+                full_n <= '1';
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif push = '1' and pop = '0' then
+                empty_n <= '1';
+            elsif push = '0' and pop = '1' and mOutPtr = 1 then
+                empty_n <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- almost_full_n
+
+    -- almost_empty_n
+
+    -- prog_full_n 
+
+    -- prog_empty_n 
+
+end architecture rtl;
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity myproject_start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_U0_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+end myproject_start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_U0_ShiftReg;
+
+architecture rtl of myproject_start_for_relu_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_relu_config3_U0_ShiftReg is
+type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
+signal SRL_SIG : SRL_ARRAY;
+
+begin
+    dout <= SRL_SIG(conv_integer(addr));
+
+    process (clk)
+    begin
+        if (clk'event and clk = '1') then
+            if (we = '1') then
+                SRL_SIG <= din & SRL_SIG(0 to DEPTH-2);
+            end if;
+        end if;
+    end process;
+
+end architecture rtl;

myproject_prj/solution1/.autopilot/db/vhdl/myproject_start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4ojc.vhd

@@ -0,0 +1,190 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--RAW latency 1 
+ 
+entity myproject_start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4ojc is 
+    generic (
+        MEM_STYLE         : string  := "shiftReg";
+        DATA_WIDTH        : integer := 1;
+        ADDR_WIDTH        : integer := 1;
+        DEPTH             : integer := 2);
+    port (
+        clk               : in  std_logic;
+        reset             : in  std_logic;
+
+        -- write
+        if_full_n         : out std_logic;
+        if_write_ce       : in  std_logic;
+        if_write          : in  std_logic;
+        if_din            : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+        -- read 
+
+        if_empty_n        : out std_logic;
+        if_read_ce        : in  std_logic;
+        if_read           : in  std_logic;
+        if_dout           : out std_logic_vector(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture rtl of myproject_start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4ojc is
+------------------------Task and function--------------
+------------------------Parameter----------------------
+constant SRL_DEPTH  : INTEGER := DEPTH;
+constant SRL_AWIDTH : INTEGER := ADDR_WIDTH;
+------------------------Component----------------------
+    component myproject_start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4ojc_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+    end component;
+
+    signal addr    : UNSIGNED(SRL_AWIDTH - 1 downto 0);
+    signal push    : STD_LOGIC;
+    signal pop     : STD_LOGIC;
+    signal mOutPtr : UNSIGNED(SRL_AWIDTH downto 0) := (others => '0');
+    signal empty_n : STD_LOGIC := '0';
+    signal full_n   : std_logic := '1';   
+    -- has num_data_valid? no 
+begin
+----------------------- Instantiation -----------------------
+    U_myproject_start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4ojc_ShiftReg : myproject_start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4ojc_ShiftReg
+    generic map (
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => SRL_AWIDTH,
+        DEPTH      => SRL_DEPTH)
+    port map (
+        clk        => clk,
+        we         => push,
+        addr       => STD_LOGIC_VECTOR(addr),
+        din        => if_din,
+        dout       => if_dout);
+--------------------------- Body ----------------------------
+    -- has num_data_valid ?  no 
+
+    -- almost full/empty  
+
+    -- program full/empty  
+
+    if_full_n  <= full_n;
+    if_empty_n <= empty_n;
+
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and if_read;
+
+    -- addr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                addr <= (others => '0');
+            elsif push = '1' and pop = '0' and empty_n = '1' then
+                addr <= addr + 1;
+            elsif push = '0' and pop = '1' and mOutPtr /= 1 then
+                addr <= addr - 1;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- mOutPtr
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '0');
+            elsif push = '1' and pop = '0' then
+                mOutPtr <= mOutPtr + 1;
+            elsif push = '0' and pop = '1' then
+                mOutPtr <= mOutPtr - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- full_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif push = '1' and pop = '0' and mOutPtr = DEPTH - 1 then
+                full_n <= '0';
+            elsif push = '0' and pop = '1' then
+                full_n <= '1';
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif push = '1' and pop = '0' then
+                empty_n <= '1';
+            elsif push = '0' and pop = '1' and mOutPtr = 1 then
+                empty_n <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- almost_full_n
+
+    -- almost_empty_n
+
+    -- prog_full_n 
+
+    -- prog_empty_n 
+
+end architecture rtl;
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity myproject_start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4ojc_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+end myproject_start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4ojc_ShiftReg;
+
+architecture rtl of myproject_start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4ojc_ShiftReg is
+type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
+signal SRL_SIG : SRL_ARRAY;
+
+begin
+    dout <= SRL_SIG(conv_integer(addr));
+
+    process (clk)
+    begin
+        if (clk'event and clk = '1') then
+            if (we = '1') then
+                SRL_SIG <= din & SRL_SIG(0 to DEPTH-2);
+            end if;
+        end if;
+    end process;
+
+end architecture rtl;

myproject_prj/solution1/.autopilot/db/vhdl/myproject_start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4oqc.vhd

@@ -0,0 +1,190 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--RAW latency 1 
+ 
+entity myproject_start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4oqc is 
+    generic (
+        MEM_STYLE         : string  := "shiftReg";
+        DATA_WIDTH        : integer := 1;
+        ADDR_WIDTH        : integer := 1;
+        DEPTH             : integer := 2);
+    port (
+        clk               : in  std_logic;
+        reset             : in  std_logic;
+
+        -- write
+        if_full_n         : out std_logic;
+        if_write_ce       : in  std_logic;
+        if_write          : in  std_logic;
+        if_din            : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+        -- read 
+
+        if_empty_n        : out std_logic;
+        if_read_ce        : in  std_logic;
+        if_read           : in  std_logic;
+        if_dout           : out std_logic_vector(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture rtl of myproject_start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4oqc is
+------------------------Task and function--------------
+------------------------Parameter----------------------
+constant SRL_DEPTH  : INTEGER := DEPTH;
+constant SRL_AWIDTH : INTEGER := ADDR_WIDTH;
+------------------------Component----------------------
+    component myproject_start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4oqc_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+    end component;
+
+    signal addr    : UNSIGNED(SRL_AWIDTH - 1 downto 0);
+    signal push    : STD_LOGIC;
+    signal pop     : STD_LOGIC;
+    signal mOutPtr : UNSIGNED(SRL_AWIDTH downto 0) := (others => '0');
+    signal empty_n : STD_LOGIC := '0';
+    signal full_n   : std_logic := '1';   
+    -- has num_data_valid? no 
+begin
+----------------------- Instantiation -----------------------
+    U_myproject_start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4oqc_ShiftReg : myproject_start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4oqc_ShiftReg
+    generic map (
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => SRL_AWIDTH,
+        DEPTH      => SRL_DEPTH)
+    port map (
+        clk        => clk,
+        we         => push,
+        addr       => STD_LOGIC_VECTOR(addr),
+        din        => if_din,
+        dout       => if_dout);
+--------------------------- Body ----------------------------
+    -- has num_data_valid ?  no 
+
+    -- almost full/empty  
+
+    -- program full/empty  
+
+    if_full_n  <= full_n;
+    if_empty_n <= empty_n;
+
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and if_read;
+
+    -- addr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                addr <= (others => '0');
+            elsif push = '1' and pop = '0' and empty_n = '1' then
+                addr <= addr + 1;
+            elsif push = '0' and pop = '1' and mOutPtr /= 1 then
+                addr <= addr - 1;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- mOutPtr
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '0');
+            elsif push = '1' and pop = '0' then
+                mOutPtr <= mOutPtr + 1;
+            elsif push = '0' and pop = '1' then
+                mOutPtr <= mOutPtr - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- full_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif push = '1' and pop = '0' and mOutPtr = DEPTH - 1 then
+                full_n <= '0';
+            elsif push = '0' and pop = '1' then
+                full_n <= '1';
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif push = '1' and pop = '0' then
+                empty_n <= '1';
+            elsif push = '0' and pop = '1' and mOutPtr = 1 then
+                empty_n <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- almost_full_n
+
+    -- almost_empty_n
+
+    -- prog_full_n 
+
+    -- prog_empty_n 
+
+end architecture rtl;
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity myproject_start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4oqc_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+end myproject_start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4oqc_ShiftReg;
+
+architecture rtl of myproject_start_for_zeropad2d_cl_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_config4oqc_ShiftReg is
+type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
+signal SRL_SIG : SRL_ARRAY;
+
+begin
+    dout <= SRL_SIG(conv_integer(addr));
+
+    process (clk)
+    begin
+        if (clk'event and clk = '1') then
+            if (we = '1') then
+                SRL_SIG <= din & SRL_SIG(0 to DEPTH-2);
+            end if;
+        end if;
+    end process;
+
+end architecture rtl;

myproject_prj/solution1/.autopilot/db/vhdl/myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_U0.vhd

@@ -0,0 +1,190 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--RAW latency 1 
+ 
+entity myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_U0 is 
+    generic (
+        MEM_STYLE         : string  := "shiftReg";
+        DATA_WIDTH        : integer := 1;
+        ADDR_WIDTH        : integer := 1;
+        DEPTH             : integer := 2);
+    port (
+        clk               : in  std_logic;
+        reset             : in  std_logic;
+
+        -- write
+        if_full_n         : out std_logic;
+        if_write_ce       : in  std_logic;
+        if_write          : in  std_logic;
+        if_din            : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+        -- read 
+
+        if_empty_n        : out std_logic;
+        if_read_ce        : in  std_logic;
+        if_read           : in  std_logic;
+        if_dout           : out std_logic_vector(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture rtl of myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_U0 is
+------------------------Task and function--------------
+------------------------Parameter----------------------
+constant SRL_DEPTH  : INTEGER := DEPTH;
+constant SRL_AWIDTH : INTEGER := ADDR_WIDTH;
+------------------------Component----------------------
+    component myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_U0_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+    end component;
+
+    signal addr    : UNSIGNED(SRL_AWIDTH - 1 downto 0);
+    signal push    : STD_LOGIC;
+    signal pop     : STD_LOGIC;
+    signal mOutPtr : UNSIGNED(SRL_AWIDTH downto 0) := (others => '0');
+    signal empty_n : STD_LOGIC := '0';
+    signal full_n   : std_logic := '1';   
+    -- has num_data_valid? no 
+begin
+----------------------- Instantiation -----------------------
+    U_myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_U0_ShiftReg : myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_U0_ShiftReg
+    generic map (
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => SRL_AWIDTH,
+        DEPTH      => SRL_DEPTH)
+    port map (
+        clk        => clk,
+        we         => push,
+        addr       => STD_LOGIC_VECTOR(addr),
+        din        => if_din,
+        dout       => if_dout);
+--------------------------- Body ----------------------------
+    -- has num_data_valid ?  no 
+
+    -- almost full/empty  
+
+    -- program full/empty  
+
+    if_full_n  <= full_n;
+    if_empty_n <= empty_n;
+
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and if_read;
+
+    -- addr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                addr <= (others => '0');
+            elsif push = '1' and pop = '0' and empty_n = '1' then
+                addr <= addr + 1;
+            elsif push = '0' and pop = '1' and mOutPtr /= 1 then
+                addr <= addr - 1;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- mOutPtr
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '0');
+            elsif push = '1' and pop = '0' then
+                mOutPtr <= mOutPtr + 1;
+            elsif push = '0' and pop = '1' then
+                mOutPtr <= mOutPtr - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- full_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif push = '1' and pop = '0' and mOutPtr = DEPTH - 1 then
+                full_n <= '0';
+            elsif push = '0' and pop = '1' then
+                full_n <= '1';
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif push = '1' and pop = '0' then
+                empty_n <= '1';
+            elsif push = '0' and pop = '1' and mOutPtr = 1 then
+                empty_n <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- almost_full_n
+
+    -- almost_empty_n
+
+    -- prog_full_n 
+
+    -- prog_empty_n 
+
+end architecture rtl;
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_U0_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+end myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_U0_ShiftReg;
+
+architecture rtl of myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config49_U0_ShiftReg is
+type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
+signal SRL_SIG : SRL_ARRAY;
+
+begin
+    dout <= SRL_SIG(conv_integer(addr));
+
+    process (clk)
+    begin
+        if (clk'event and clk = '1') then
+            if (we = '1') then
+                SRL_SIG <= din & SRL_SIG(0 to DEPTH-2);
+            end if;
+        end if;
+    end process;
+
+end architecture rtl;

myproject_prj/solution1/.autopilot/db/vhdl/myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config52_U0.vhd

@@ -0,0 +1,190 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--RAW latency 1 
+ 
+entity myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config52_U0 is 
+    generic (
+        MEM_STYLE         : string  := "shiftReg";
+        DATA_WIDTH        : integer := 1;
+        ADDR_WIDTH        : integer := 1;
+        DEPTH             : integer := 2);
+    port (
+        clk               : in  std_logic;
+        reset             : in  std_logic;
+
+        -- write
+        if_full_n         : out std_logic;
+        if_write_ce       : in  std_logic;
+        if_write          : in  std_logic;
+        if_din            : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+        -- read 
+
+        if_empty_n        : out std_logic;
+        if_read_ce        : in  std_logic;
+        if_read           : in  std_logic;
+        if_dout           : out std_logic_vector(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture rtl of myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config52_U0 is
+------------------------Task and function--------------
+------------------------Parameter----------------------
+constant SRL_DEPTH  : INTEGER := DEPTH;
+constant SRL_AWIDTH : INTEGER := ADDR_WIDTH;
+------------------------Component----------------------
+    component myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config52_U0_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+    end component;
+
+    signal addr    : UNSIGNED(SRL_AWIDTH - 1 downto 0);
+    signal push    : STD_LOGIC;
+    signal pop     : STD_LOGIC;
+    signal mOutPtr : UNSIGNED(SRL_AWIDTH downto 0) := (others => '0');
+    signal empty_n : STD_LOGIC := '0';
+    signal full_n   : std_logic := '1';   
+    -- has num_data_valid? no 
+begin
+----------------------- Instantiation -----------------------
+    U_myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config52_U0_ShiftReg : myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config52_U0_ShiftReg
+    generic map (
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => SRL_AWIDTH,
+        DEPTH      => SRL_DEPTH)
+    port map (
+        clk        => clk,
+        we         => push,
+        addr       => STD_LOGIC_VECTOR(addr),
+        din        => if_din,
+        dout       => if_dout);
+--------------------------- Body ----------------------------
+    -- has num_data_valid ?  no 
+
+    -- almost full/empty  
+
+    -- program full/empty  
+
+    if_full_n  <= full_n;
+    if_empty_n <= empty_n;
+
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and if_read;
+
+    -- addr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                addr <= (others => '0');
+            elsif push = '1' and pop = '0' and empty_n = '1' then
+                addr <= addr + 1;
+            elsif push = '0' and pop = '1' and mOutPtr /= 1 then
+                addr <= addr - 1;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- mOutPtr
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '0');
+            elsif push = '1' and pop = '0' then
+                mOutPtr <= mOutPtr + 1;
+            elsif push = '0' and pop = '1' then
+                mOutPtr <= mOutPtr - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- full_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif push = '1' and pop = '0' and mOutPtr = DEPTH - 1 then
+                full_n <= '0';
+            elsif push = '0' and pop = '1' then
+                full_n <= '1';
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif push = '1' and pop = '0' then
+                empty_n <= '1';
+            elsif push = '0' and pop = '1' and mOutPtr = 1 then
+                empty_n <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- almost_full_n
+
+    -- almost_empty_n
+
+    -- prog_full_n 
+
+    -- prog_empty_n 
+
+end architecture rtl;
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config52_U0_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+end myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config52_U0_ShiftReg;
+
+architecture rtl of myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_32u_config52_U0_ShiftReg is
+type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
+signal SRL_SIG : SRL_ARRAY;
+
+begin
+    dout <= SRL_SIG(conv_integer(addr));
+
+    process (clk)
+    begin
+        if (clk'event and clk = '1') then
+            if (we = '1') then
+                SRL_SIG <= din & SRL_SIG(0 to DEPTH-2);
+            end if;
+        end if;
+    end process;
+
+end architecture rtl;

myproject_prj/solution1/.autopilot/db/vhdl/myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config53_U0.vhd

@@ -0,0 +1,190 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--RAW latency 1 
+ 
+entity myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config53_U0 is 
+    generic (
+        MEM_STYLE         : string  := "shiftReg";
+        DATA_WIDTH        : integer := 1;
+        ADDR_WIDTH        : integer := 1;
+        DEPTH             : integer := 2);
+    port (
+        clk               : in  std_logic;
+        reset             : in  std_logic;
+
+        -- write
+        if_full_n         : out std_logic;
+        if_write_ce       : in  std_logic;
+        if_write          : in  std_logic;
+        if_din            : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+        -- read 
+
+        if_empty_n        : out std_logic;
+        if_read_ce        : in  std_logic;
+        if_read           : in  std_logic;
+        if_dout           : out std_logic_vector(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture rtl of myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config53_U0 is
+------------------------Task and function--------------
+------------------------Parameter----------------------
+constant SRL_DEPTH  : INTEGER := DEPTH;
+constant SRL_AWIDTH : INTEGER := ADDR_WIDTH;
+------------------------Component----------------------
+    component myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config53_U0_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+    end component;
+
+    signal addr    : UNSIGNED(SRL_AWIDTH - 1 downto 0);
+    signal push    : STD_LOGIC;
+    signal pop     : STD_LOGIC;
+    signal mOutPtr : UNSIGNED(SRL_AWIDTH downto 0) := (others => '0');
+    signal empty_n : STD_LOGIC := '0';
+    signal full_n   : std_logic := '1';   
+    -- has num_data_valid? no 
+begin
+----------------------- Instantiation -----------------------
+    U_myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config53_U0_ShiftReg : myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config53_U0_ShiftReg
+    generic map (
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => SRL_AWIDTH,
+        DEPTH      => SRL_DEPTH)
+    port map (
+        clk        => clk,
+        we         => push,
+        addr       => STD_LOGIC_VECTOR(addr),
+        din        => if_din,
+        dout       => if_dout);
+--------------------------- Body ----------------------------
+    -- has num_data_valid ?  no 
+
+    -- almost full/empty  
+
+    -- program full/empty  
+
+    if_full_n  <= full_n;
+    if_empty_n <= empty_n;
+
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and if_read;
+
+    -- addr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                addr <= (others => '0');
+            elsif push = '1' and pop = '0' and empty_n = '1' then
+                addr <= addr + 1;
+            elsif push = '0' and pop = '1' and mOutPtr /= 1 then
+                addr <= addr - 1;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- mOutPtr
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '0');
+            elsif push = '1' and pop = '0' then
+                mOutPtr <= mOutPtr + 1;
+            elsif push = '0' and pop = '1' then
+                mOutPtr <= mOutPtr - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- full_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif push = '1' and pop = '0' and mOutPtr = DEPTH - 1 then
+                full_n <= '0';
+            elsif push = '0' and pop = '1' then
+                full_n <= '1';
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif push = '1' and pop = '0' then
+                empty_n <= '1';
+            elsif push = '0' and pop = '1' and mOutPtr = 1 then
+                empty_n <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- almost_full_n
+
+    -- almost_empty_n
+
+    -- prog_full_n 
+
+    -- prog_empty_n 
+
+end architecture rtl;
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config53_U0_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+end myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config53_U0_ShiftReg;
+
+architecture rtl of myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_64u_config53_U0_ShiftReg is
+type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
+signal SRL_SIG : SRL_ARRAY;
+
+begin
+    dout <= SRL_SIG(conv_integer(addr));
+
+    process (clk)
+    begin
+        if (clk'event and clk = '1') then
+            if (we = '1') then
+                SRL_SIG <= din & SRL_SIG(0 to DEPTH-2);
+            end if;
+        end if;
+    end process;
+
+end architecture rtl;

myproject_prj/solution1/.autopilot/db/vhdl/myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config54_U0.vhd

@@ -0,0 +1,190 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--RAW latency 1 
+ 
+entity myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config54_U0 is 
+    generic (
+        MEM_STYLE         : string  := "shiftReg";
+        DATA_WIDTH        : integer := 1;
+        ADDR_WIDTH        : integer := 1;
+        DEPTH             : integer := 2);
+    port (
+        clk               : in  std_logic;
+        reset             : in  std_logic;
+
+        -- write
+        if_full_n         : out std_logic;
+        if_write_ce       : in  std_logic;
+        if_write          : in  std_logic;
+        if_din            : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
+
+        -- read 
+
+        if_empty_n        : out std_logic;
+        if_read_ce        : in  std_logic;
+        if_read           : in  std_logic;
+        if_dout           : out std_logic_vector(DATA_WIDTH - 1 downto 0)
+    );
+end entity;
+
+architecture rtl of myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config54_U0 is
+------------------------Task and function--------------
+------------------------Parameter----------------------
+constant SRL_DEPTH  : INTEGER := DEPTH;
+constant SRL_AWIDTH : INTEGER := ADDR_WIDTH;
+------------------------Component----------------------
+    component myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config54_U0_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+    end component;
+
+    signal addr    : UNSIGNED(SRL_AWIDTH - 1 downto 0);
+    signal push    : STD_LOGIC;
+    signal pop     : STD_LOGIC;
+    signal mOutPtr : UNSIGNED(SRL_AWIDTH downto 0) := (others => '0');
+    signal empty_n : STD_LOGIC := '0';
+    signal full_n   : std_logic := '1';   
+    -- has num_data_valid? no 
+begin
+----------------------- Instantiation -----------------------
+    U_myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config54_U0_ShiftReg : myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config54_U0_ShiftReg
+    generic map (
+        DATA_WIDTH => DATA_WIDTH,
+        ADDR_WIDTH => SRL_AWIDTH,
+        DEPTH      => SRL_DEPTH)
+    port map (
+        clk        => clk,
+        we         => push,
+        addr       => STD_LOGIC_VECTOR(addr),
+        din        => if_din,
+        dout       => if_dout);
+--------------------------- Body ----------------------------
+    -- has num_data_valid ?  no 
+
+    -- almost full/empty  
+
+    -- program full/empty  
+
+    if_full_n  <= full_n;
+    if_empty_n <= empty_n;
+
+    push       <= full_n and if_write_ce and if_write;
+    pop        <= empty_n and if_read_ce and if_read;
+
+    -- addr
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                addr <= (others => '0');
+            elsif push = '1' and pop = '0' and empty_n = '1' then
+                addr <= addr + 1;
+            elsif push = '0' and pop = '1' and mOutPtr /= 1 then
+                addr <= addr - 1;
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- mOutPtr
+    process (clk) begin
+        -- reset  sync 
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                mOutPtr <= (others => '0');
+            elsif push = '1' and pop = '0' then
+                mOutPtr <= mOutPtr + 1;
+            elsif push = '0' and pop = '1' then
+                mOutPtr <= mOutPtr - 1;
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- full_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                full_n <= '1';
+            elsif push = '1' and pop = '0' and mOutPtr = DEPTH - 1 then
+                full_n <= '0';
+            elsif push = '0' and pop = '1' then
+                full_n <= '1';
+            end if;
+        end if; -- sync end
+    end process;
+
+    -- empty_n
+    process (clk) begin
+        -- reset  sync
+        if clk'event and clk = '1' then
+            if reset = '1' then
+                empty_n <= '0';
+            elsif push = '1' and pop = '0' then
+                empty_n <= '1';
+            elsif push = '0' and pop = '1' and mOutPtr = 1 then
+                empty_n <= '0';
+            end if;
+        end if; -- sync end 
+    end process;
+
+    -- almost_full_n
+
+    -- almost_empty_n
+
+    -- prog_full_n 
+
+    -- prog_empty_n 
+
+end architecture rtl;
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config54_U0_ShiftReg is
+    generic (
+        DATA_WIDTH : integer := 1;
+        ADDR_WIDTH : integer := 1;
+        DEPTH      : integer := 2);
+    port (
+        clk        : in std_logic;
+        we         : in std_logic;
+        addr       : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+        din        : in std_logic_vector(DATA_WIDTH-1 downto 0);
+        dout       : out std_logic_vector(DATA_WIDTH-1 downto 0));
+end myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config54_U0_ShiftReg;
+
+architecture rtl of myproject_start_for_zeropad2d_cl_array_array_ap_fixed_16_6_5_3_0_96u_config54_U0_ShiftReg is
+type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
+signal SRL_SIG : SRL_ARRAY;
+
+begin
+    dout <= SRL_SIG(conv_integer(addr));
+
+    process (clk)
+    begin
+        if (clk'event and clk = '1') then
+            if (we = '1') then
+                SRL_SIG <= din & SRL_SIG(0 to DEPTH-2);
+            end if;
+        end if;
+    end process;
+
+end architecture rtl;

myproject_prj/solution1/impl/vhdl/myproject_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_s.vhd

@@ -0,0 +1,346 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity myproject_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_s is
+port (
+    ap_clk : IN STD_LOGIC;
+    ap_rst : IN STD_LOGIC;
+    ap_start : IN STD_LOGIC;
+    start_full_n : IN STD_LOGIC;
+    ap_done : OUT STD_LOGIC;
+    ap_continue : IN STD_LOGIC;
+    ap_idle : OUT STD_LOGIC;
+    ap_ready : OUT STD_LOGIC;
+    layer10_out_dout : IN STD_LOGIC_VECTOR (255 downto 0);
+    layer10_out_num_data_valid : IN STD_LOGIC_VECTOR (10 downto 0);
+    layer10_out_fifo_cap : IN STD_LOGIC_VECTOR (10 downto 0);
+    layer10_out_empty_n : IN STD_LOGIC;
+    layer10_out_read : OUT STD_LOGIC;
+    layer44_cpy1_din : OUT STD_LOGIC_VECTOR (255 downto 0);
+    layer44_cpy1_num_data_valid : IN STD_LOGIC_VECTOR (10 downto 0);
+    layer44_cpy1_fifo_cap : IN STD_LOGIC_VECTOR (10 downto 0);
+    layer44_cpy1_full_n : IN STD_LOGIC;
+    layer44_cpy1_write : OUT STD_LOGIC;
+    layer44_cpy2_din : OUT STD_LOGIC_VECTOR (255 downto 0);
+    layer44_cpy2_num_data_valid : IN STD_LOGIC_VECTOR (10 downto 0);
+    layer44_cpy2_fifo_cap : IN STD_LOGIC_VECTOR (10 downto 0);
+    layer44_cpy2_full_n : IN STD_LOGIC;
+    layer44_cpy2_write : OUT STD_LOGIC;
+    start_out : OUT STD_LOGIC;
+    start_write : OUT STD_LOGIC );
+end;
+
+
+architecture behav of myproject_clone_stream_array_ap_fixed_16u_array_ap_fixed_16_6_5_3_0_16u_16384_s is 
+    constant ap_const_logic_1 : STD_LOGIC := '1';
+    constant ap_const_logic_0 : STD_LOGIC := '0';
+    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
+    constant ap_const_boolean_1 : BOOLEAN := true;
+    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
+    constant ap_const_boolean_0 : BOOLEAN := false;
+    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
+    constant ap_const_lv10_0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000";
+    constant ap_const_lv10_1 : STD_LOGIC_VECTOR (9 downto 0) := "0000000001";
+    constant ap_const_lv10_3FF : STD_LOGIC_VECTOR (9 downto 0) := "1111111111";
+
+attribute shreg_extract : string;
+    signal real_start : STD_LOGIC;
+    signal start_once_reg : STD_LOGIC := '0';
+    signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "1";
+    attribute fsm_encoding : string;
+    attribute fsm_encoding of ap_CS_fsm : signal is "none";
+    signal ap_CS_fsm_state1 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
+    signal internal_ap_ready : STD_LOGIC;
+    signal ap_done_reg : STD_LOGIC := '0';
+    signal ap_block_state1_pp0_stage0_iter0 : BOOLEAN;
+    signal icmp_ln22_fu_78_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal ap_condition_exit_pp0_iter0_stage0 : STD_LOGIC;
+    signal ap_loop_exit_ready : STD_LOGIC;
+    signal ap_ready_int : STD_LOGIC;
+    signal layer10_out_blk_n : STD_LOGIC;
+    signal layer44_cpy1_blk_n : STD_LOGIC;
+    signal layer44_cpy2_blk_n : STD_LOGIC;
+    signal i_0101_fu_38 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000";
+    signal i_fu_72_p2 : STD_LOGIC_VECTOR (9 downto 0);
+    signal ap_loop_init : STD_LOGIC;
+    signal ap_sig_allocacmp_i_0101_load : STD_LOGIC_VECTOR (9 downto 0);
+    signal layer10_out_read_local : STD_LOGIC;
+    signal layer44_cpy1_write_local : STD_LOGIC;
+    signal layer44_cpy2_write_local : STD_LOGIC;
+    signal ap_continue_int : STD_LOGIC;
+    signal ap_done_int : STD_LOGIC;
+    signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
+    signal ap_ST_fsm_state1_blk : STD_LOGIC;
+    signal ap_start_int : STD_LOGIC;
+    signal ap_done_sig : STD_LOGIC;
+    signal ap_ce_reg : STD_LOGIC;
+
+    component myproject_flow_control_loop_pipe IS
+    port (
+        ap_clk : IN STD_LOGIC;
+        ap_rst : IN STD_LOGIC;
+        ap_start : IN STD_LOGIC;
+        ap_ready : OUT STD_LOGIC;
+        ap_done : OUT STD_LOGIC;
+        ap_start_int : OUT STD_LOGIC;
+        ap_loop_init : OUT STD_LOGIC;
+        ap_ready_int : IN STD_LOGIC;
+        ap_loop_exit_ready : IN STD_LOGIC;
+        ap_loop_exit_done : IN STD_LOGIC;
+        ap_continue_int : OUT STD_LOGIC;
+        ap_done_int : IN STD_LOGIC;
+        ap_continue : IN STD_LOGIC );
+    end component;
+
+
+
+begin
+    flow_control_loop_pipe_U : component myproject_flow_control_loop_pipe
+    port map (
+        ap_clk => ap_clk,
+        ap_rst => ap_rst,
+        ap_start => real_start,
+        ap_ready => internal_ap_ready,
+        ap_done => ap_done_sig,
+        ap_start_int => ap_start_int,
+        ap_loop_init => ap_loop_init,
+        ap_ready_int => ap_ready_int,
+        ap_loop_exit_ready => ap_condition_exit_pp0_iter0_stage0,
+        ap_loop_exit_done => ap_done_int,
+        ap_continue_int => ap_continue_int,
+        ap_done_int => ap_done_int,
+        ap_continue => ap_continue);
+
+
+
+
+
+    ap_CS_fsm_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_CS_fsm <= ap_ST_fsm_state1;
+            else
+                ap_CS_fsm <= ap_NS_fsm;
+            end if;
+        end if;
+    end process;
+
+
+    ap_done_reg_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_done_reg <= ap_const_logic_0;
+            else
+                if ((ap_continue_int = ap_const_logic_1)) then 
+                    ap_done_reg <= ap_const_logic_0;
+                elsif (((ap_loop_exit_ready = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_state1_pp0_stage0_iter0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+                    ap_done_reg <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    start_once_reg_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                start_once_reg <= ap_const_logic_0;
+            else
+                if (((real_start = ap_const_logic_1) and (internal_ap_ready = ap_const_logic_0))) then 
+                    start_once_reg <= ap_const_logic_1;
+                elsif ((internal_ap_ready = ap_const_logic_1)) then 
+                    start_once_reg <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    i_0101_fu_38_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_state1_pp0_stage0_iter0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                i_0101_fu_38 <= i_fu_72_p2;
+            end if;
+        end if;
+    end process;
+
+    ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_CS_fsm_state1, ap_block_state1_pp0_stage0_iter0)
+    begin
+        case ap_CS_fsm is
+            when ap_ST_fsm_state1 => 
+                ap_NS_fsm <= ap_ST_fsm_state1;
+            when others =>  
+                ap_NS_fsm <= "X";
+        end case;
+    end process;
+    ap_CS_fsm_state1 <= ap_CS_fsm(0);
+
+    ap_ST_fsm_state1_blk_assign_proc : process(ap_block_state1_pp0_stage0_iter0)
+    begin
+        if ((ap_const_boolean_1 = ap_block_state1_pp0_stage0_iter0)) then 
+            ap_ST_fsm_state1_blk <= ap_const_logic_1;
+        else 
+            ap_ST_fsm_state1_blk <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_block_state1_pp0_stage0_iter0_assign_proc : process(layer10_out_empty_n, layer44_cpy1_full_n, layer44_cpy2_full_n, ap_done_reg, ap_start_int)
+    begin
+                ap_block_state1_pp0_stage0_iter0 <= ((ap_done_reg = ap_const_logic_1) or (layer44_cpy2_full_n = ap_const_logic_0) or (layer44_cpy1_full_n = ap_const_logic_0) or (layer10_out_empty_n = ap_const_logic_0) or (ap_start_int = ap_const_logic_0));
+    end process;
+
+
+    ap_condition_exit_pp0_iter0_stage0_assign_proc : process(ap_CS_fsm_state1, ap_block_state1_pp0_stage0_iter0, icmp_ln22_fu_78_p2)
+    begin
+        if (((icmp_ln22_fu_78_p2 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_state1_pp0_stage0_iter0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            ap_condition_exit_pp0_iter0_stage0 <= ap_const_logic_1;
+        else 
+            ap_condition_exit_pp0_iter0_stage0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    ap_done <= ap_done_sig;
+
+    ap_done_int_assign_proc : process(ap_CS_fsm_state1, ap_done_reg, ap_block_state1_pp0_stage0_iter0, ap_loop_exit_ready)
+    begin
+        if (((ap_loop_exit_ready = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_state1_pp0_stage0_iter0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            ap_done_int <= ap_const_logic_1;
+        else 
+            ap_done_int <= ap_done_reg;
+        end if; 
+    end process;
+
+
+    ap_idle_assign_proc : process(ap_CS_fsm_state1, ap_start_int)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start_int = ap_const_logic_0))) then 
+            ap_idle <= ap_const_logic_1;
+        else 
+            ap_idle <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    ap_loop_exit_ready <= ap_condition_exit_pp0_iter0_stage0;
+    ap_ready <= internal_ap_ready;
+
+    ap_ready_int_assign_proc : process(ap_CS_fsm_state1, ap_block_state1_pp0_stage0_iter0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_state1_pp0_stage0_iter0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            ap_ready_int <= ap_const_logic_1;
+        else 
+            ap_ready_int <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_sig_allocacmp_i_0101_load_assign_proc : process(ap_CS_fsm_state1, i_0101_fu_38, ap_loop_init)
+    begin
+        if (((ap_loop_init = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            ap_sig_allocacmp_i_0101_load <= ap_const_lv10_0;
+        else 
+            ap_sig_allocacmp_i_0101_load <= i_0101_fu_38;
+        end if; 
+    end process;
+
+    i_fu_72_p2 <= std_logic_vector(unsigned(ap_sig_allocacmp_i_0101_load) + unsigned(ap_const_lv10_1));
+    icmp_ln22_fu_78_p2 <= "1" when (ap_sig_allocacmp_i_0101_load = ap_const_lv10_3FF) else "0";
+
+    layer10_out_blk_n_assign_proc : process(ap_CS_fsm_state1, layer10_out_empty_n, ap_done_reg, ap_start_int)
+    begin
+        if ((not(((ap_done_reg = ap_const_logic_1) or (ap_start_int = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            layer10_out_blk_n <= layer10_out_empty_n;
+        else 
+            layer10_out_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    layer10_out_read <= layer10_out_read_local;
+
+    layer10_out_read_local_assign_proc : process(ap_CS_fsm_state1, ap_block_state1_pp0_stage0_iter0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_state1_pp0_stage0_iter0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            layer10_out_read_local <= ap_const_logic_1;
+        else 
+            layer10_out_read_local <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    layer44_cpy1_blk_n_assign_proc : process(ap_CS_fsm_state1, layer44_cpy1_full_n, ap_done_reg, ap_start_int)
+    begin
+        if ((not(((ap_done_reg = ap_const_logic_1) or (ap_start_int = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            layer44_cpy1_blk_n <= layer44_cpy1_full_n;
+        else 
+            layer44_cpy1_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    layer44_cpy1_din <= layer10_out_dout;
+    layer44_cpy1_write <= layer44_cpy1_write_local;
+
+    layer44_cpy1_write_local_assign_proc : process(ap_CS_fsm_state1, ap_block_state1_pp0_stage0_iter0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_state1_pp0_stage0_iter0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            layer44_cpy1_write_local <= ap_const_logic_1;
+        else 
+            layer44_cpy1_write_local <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    layer44_cpy2_blk_n_assign_proc : process(ap_CS_fsm_state1, layer44_cpy2_full_n, ap_done_reg, ap_start_int)
+    begin
+        if ((not(((ap_done_reg = ap_const_logic_1) or (ap_start_int = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            layer44_cpy2_blk_n <= layer44_cpy2_full_n;
+        else 
+            layer44_cpy2_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    layer44_cpy2_din <= layer10_out_dout;
+    layer44_cpy2_write <= layer44_cpy2_write_local;
+
+    layer44_cpy2_write_local_assign_proc : process(ap_CS_fsm_state1, ap_block_state1_pp0_stage0_iter0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_state1_pp0_stage0_iter0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            layer44_cpy2_write_local <= ap_const_logic_1;
+        else 
+            layer44_cpy2_write_local <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    real_start_assign_proc : process(ap_start, start_full_n, start_once_reg)
+    begin
+        if (((start_full_n = ap_const_logic_0) and (start_once_reg = ap_const_logic_0))) then 
+            real_start <= ap_const_logic_0;
+        else 
+            real_start <= ap_start;
+        end if; 
+    end process;
+
+    start_out <= real_start;
+
+    start_write_assign_proc : process(real_start, start_once_reg)
+    begin
+        if (((real_start = ap_const_logic_1) and (start_once_reg = ap_const_logic_0))) then 
+            start_write <= ap_const_logic_1;
+        else 
+            start_write <= ap_const_logic_0;
+        end if; 
+    end process;
+
+end behav;

myproject_prj/solution1/impl/vhdl/myproject_clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_s.vhd

@@ -0,0 +1,346 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity myproject_clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_s is
+port (
+    ap_clk : IN STD_LOGIC;
+    ap_rst : IN STD_LOGIC;
+    ap_start : IN STD_LOGIC;
+    start_full_n : IN STD_LOGIC;
+    ap_done : OUT STD_LOGIC;
+    ap_continue : IN STD_LOGIC;
+    ap_idle : OUT STD_LOGIC;
+    ap_ready : OUT STD_LOGIC;
+    layer15_out_dout : IN STD_LOGIC_VECTOR (511 downto 0);
+    layer15_out_num_data_valid : IN STD_LOGIC_VECTOR (8 downto 0);
+    layer15_out_fifo_cap : IN STD_LOGIC_VECTOR (8 downto 0);
+    layer15_out_empty_n : IN STD_LOGIC;
+    layer15_out_read : OUT STD_LOGIC;
+    layer45_cpy1_din : OUT STD_LOGIC_VECTOR (511 downto 0);
+    layer45_cpy1_num_data_valid : IN STD_LOGIC_VECTOR (8 downto 0);
+    layer45_cpy1_fifo_cap : IN STD_LOGIC_VECTOR (8 downto 0);
+    layer45_cpy1_full_n : IN STD_LOGIC;
+    layer45_cpy1_write : OUT STD_LOGIC;
+    layer45_cpy2_din : OUT STD_LOGIC_VECTOR (511 downto 0);
+    layer45_cpy2_num_data_valid : IN STD_LOGIC_VECTOR (8 downto 0);
+    layer45_cpy2_fifo_cap : IN STD_LOGIC_VECTOR (8 downto 0);
+    layer45_cpy2_full_n : IN STD_LOGIC;
+    layer45_cpy2_write : OUT STD_LOGIC;
+    start_out : OUT STD_LOGIC;
+    start_write : OUT STD_LOGIC );
+end;
+
+
+architecture behav of myproject_clone_stream_array_ap_fixed_32u_array_ap_fixed_16_6_5_3_0_32u_8192_s is 
+    constant ap_const_logic_1 : STD_LOGIC := '1';
+    constant ap_const_logic_0 : STD_LOGIC := '0';
+    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
+    constant ap_const_boolean_1 : BOOLEAN := true;
+    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
+    constant ap_const_boolean_0 : BOOLEAN := false;
+    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
+    constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
+    constant ap_const_lv8_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
+    constant ap_const_lv8_FF : STD_LOGIC_VECTOR (7 downto 0) := "11111111";
+
+attribute shreg_extract : string;
+    signal real_start : STD_LOGIC;
+    signal start_once_reg : STD_LOGIC := '0';
+    signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "1";
+    attribute fsm_encoding : string;
+    attribute fsm_encoding of ap_CS_fsm : signal is "none";
+    signal ap_CS_fsm_state1 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
+    signal internal_ap_ready : STD_LOGIC;
+    signal ap_done_reg : STD_LOGIC := '0';
+    signal ap_block_state1_pp0_stage0_iter0 : BOOLEAN;
+    signal icmp_ln22_fu_78_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal ap_condition_exit_pp0_iter0_stage0 : STD_LOGIC;
+    signal ap_loop_exit_ready : STD_LOGIC;
+    signal ap_ready_int : STD_LOGIC;
+    signal layer15_out_blk_n : STD_LOGIC;
+    signal layer45_cpy1_blk_n : STD_LOGIC;
+    signal layer45_cpy2_blk_n : STD_LOGIC;
+    signal i_0101_fu_38 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
+    signal i_fu_72_p2 : STD_LOGIC_VECTOR (7 downto 0);
+    signal ap_loop_init : STD_LOGIC;
+    signal ap_sig_allocacmp_i_0101_load : STD_LOGIC_VECTOR (7 downto 0);
+    signal layer15_out_read_local : STD_LOGIC;
+    signal layer45_cpy1_write_local : STD_LOGIC;
+    signal layer45_cpy2_write_local : STD_LOGIC;
+    signal ap_continue_int : STD_LOGIC;
+    signal ap_done_int : STD_LOGIC;
+    signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
+    signal ap_ST_fsm_state1_blk : STD_LOGIC;
+    signal ap_start_int : STD_LOGIC;
+    signal ap_done_sig : STD_LOGIC;
+    signal ap_ce_reg : STD_LOGIC;
+
+    component myproject_flow_control_loop_pipe IS
+    port (
+        ap_clk : IN STD_LOGIC;
+        ap_rst : IN STD_LOGIC;
+        ap_start : IN STD_LOGIC;
+        ap_ready : OUT STD_LOGIC;
+        ap_done : OUT STD_LOGIC;
+        ap_start_int : OUT STD_LOGIC;
+        ap_loop_init : OUT STD_LOGIC;
+        ap_ready_int : IN STD_LOGIC;
+        ap_loop_exit_ready : IN STD_LOGIC;
+        ap_loop_exit_done : IN STD_LOGIC;
+        ap_continue_int : OUT STD_LOGIC;
+        ap_done_int : IN STD_LOGIC;
+        ap_continue : IN STD_LOGIC );
+    end component;
+
+
+
+begin
+    flow_control_loop_pipe_U : component myproject_flow_control_loop_pipe
+    port map (
+        ap_clk => ap_clk,
+        ap_rst => ap_rst,
+        ap_start => real_start,
+        ap_ready => internal_ap_ready,
+        ap_done => ap_done_sig,
+        ap_start_int => ap_start_int,
+        ap_loop_init => ap_loop_init,
+        ap_ready_int => ap_ready_int,
+        ap_loop_exit_ready => ap_condition_exit_pp0_iter0_stage0,
+        ap_loop_exit_done => ap_done_int,
+        ap_continue_int => ap_continue_int,
+        ap_done_int => ap_done_int,
+        ap_continue => ap_continue);
+
+
+
+
+
+    ap_CS_fsm_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_CS_fsm <= ap_ST_fsm_state1;
+            else
+                ap_CS_fsm <= ap_NS_fsm;
+            end if;
+        end if;
+    end process;
+
+
+    ap_done_reg_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_done_reg <= ap_const_logic_0;
+            else
+                if ((ap_continue_int = ap_const_logic_1)) then 
+                    ap_done_reg <= ap_const_logic_0;
+                elsif (((ap_loop_exit_ready = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_state1_pp0_stage0_iter0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+                    ap_done_reg <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    start_once_reg_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                start_once_reg <= ap_const_logic_0;
+            else
+                if (((real_start = ap_const_logic_1) and (internal_ap_ready = ap_const_logic_0))) then 
+                    start_once_reg <= ap_const_logic_1;
+                elsif ((internal_ap_ready = ap_const_logic_1)) then 
+                    start_once_reg <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    i_0101_fu_38_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_state1_pp0_stage0_iter0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                i_0101_fu_38 <= i_fu_72_p2;
+            end if;
+        end if;
+    end process;
+
+    ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_CS_fsm_state1, ap_block_state1_pp0_stage0_iter0)
+    begin
+        case ap_CS_fsm is
+            when ap_ST_fsm_state1 => 
+                ap_NS_fsm <= ap_ST_fsm_state1;
+            when others =>  
+                ap_NS_fsm <= "X";
+        end case;
+    end process;
+    ap_CS_fsm_state1 <= ap_CS_fsm(0);
+
+    ap_ST_fsm_state1_blk_assign_proc : process(ap_block_state1_pp0_stage0_iter0)
+    begin
+        if ((ap_const_boolean_1 = ap_block_state1_pp0_stage0_iter0)) then 
+            ap_ST_fsm_state1_blk <= ap_const_logic_1;
+        else 
+            ap_ST_fsm_state1_blk <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_block_state1_pp0_stage0_iter0_assign_proc : process(layer15_out_empty_n, layer45_cpy1_full_n, layer45_cpy2_full_n, ap_done_reg, ap_start_int)
+    begin
+                ap_block_state1_pp0_stage0_iter0 <= ((ap_done_reg = ap_const_logic_1) or (layer45_cpy2_full_n = ap_const_logic_0) or (layer45_cpy1_full_n = ap_const_logic_0) or (layer15_out_empty_n = ap_const_logic_0) or (ap_start_int = ap_const_logic_0));
+    end process;
+
+
+    ap_condition_exit_pp0_iter0_stage0_assign_proc : process(ap_CS_fsm_state1, ap_block_state1_pp0_stage0_iter0, icmp_ln22_fu_78_p2)
+    begin
+        if (((icmp_ln22_fu_78_p2 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_state1_pp0_stage0_iter0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            ap_condition_exit_pp0_iter0_stage0 <= ap_const_logic_1;
+        else 
+            ap_condition_exit_pp0_iter0_stage0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    ap_done <= ap_done_sig;
+
+    ap_done_int_assign_proc : process(ap_CS_fsm_state1, ap_done_reg, ap_block_state1_pp0_stage0_iter0, ap_loop_exit_ready)
+    begin
+        if (((ap_loop_exit_ready = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_state1_pp0_stage0_iter0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            ap_done_int <= ap_const_logic_1;
+        else 
+            ap_done_int <= ap_done_reg;
+        end if; 
+    end process;
+
+
+    ap_idle_assign_proc : process(ap_CS_fsm_state1, ap_start_int)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start_int = ap_const_logic_0))) then 
+            ap_idle <= ap_const_logic_1;
+        else 
+            ap_idle <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    ap_loop_exit_ready <= ap_condition_exit_pp0_iter0_stage0;
+    ap_ready <= internal_ap_ready;
+
+    ap_ready_int_assign_proc : process(ap_CS_fsm_state1, ap_block_state1_pp0_stage0_iter0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_state1_pp0_stage0_iter0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            ap_ready_int <= ap_const_logic_1;
+        else 
+            ap_ready_int <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_sig_allocacmp_i_0101_load_assign_proc : process(ap_CS_fsm_state1, i_0101_fu_38, ap_loop_init)
+    begin
+        if (((ap_loop_init = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            ap_sig_allocacmp_i_0101_load <= ap_const_lv8_0;
+        else 
+            ap_sig_allocacmp_i_0101_load <= i_0101_fu_38;
+        end if; 
+    end process;
+
+    i_fu_72_p2 <= std_logic_vector(unsigned(ap_sig_allocacmp_i_0101_load) + unsigned(ap_const_lv8_1));
+    icmp_ln22_fu_78_p2 <= "1" when (ap_sig_allocacmp_i_0101_load = ap_const_lv8_FF) else "0";
+
+    layer15_out_blk_n_assign_proc : process(ap_CS_fsm_state1, layer15_out_empty_n, ap_done_reg, ap_start_int)
+    begin
+        if ((not(((ap_done_reg = ap_const_logic_1) or (ap_start_int = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            layer15_out_blk_n <= layer15_out_empty_n;
+        else 
+            layer15_out_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    layer15_out_read <= layer15_out_read_local;
+
+    layer15_out_read_local_assign_proc : process(ap_CS_fsm_state1, ap_block_state1_pp0_stage0_iter0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_state1_pp0_stage0_iter0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            layer15_out_read_local <= ap_const_logic_1;
+        else 
+            layer15_out_read_local <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    layer45_cpy1_blk_n_assign_proc : process(ap_CS_fsm_state1, layer45_cpy1_full_n, ap_done_reg, ap_start_int)
+    begin
+        if ((not(((ap_done_reg = ap_const_logic_1) or (ap_start_int = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            layer45_cpy1_blk_n <= layer45_cpy1_full_n;
+        else 
+            layer45_cpy1_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    layer45_cpy1_din <= layer15_out_dout;
+    layer45_cpy1_write <= layer45_cpy1_write_local;
+
+    layer45_cpy1_write_local_assign_proc : process(ap_CS_fsm_state1, ap_block_state1_pp0_stage0_iter0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_state1_pp0_stage0_iter0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            layer45_cpy1_write_local <= ap_const_logic_1;
+        else 
+            layer45_cpy1_write_local <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    layer45_cpy2_blk_n_assign_proc : process(ap_CS_fsm_state1, layer45_cpy2_full_n, ap_done_reg, ap_start_int)
+    begin
+        if ((not(((ap_done_reg = ap_const_logic_1) or (ap_start_int = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            layer45_cpy2_blk_n <= layer45_cpy2_full_n;
+        else 
+            layer45_cpy2_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    layer45_cpy2_din <= layer15_out_dout;
+    layer45_cpy2_write <= layer45_cpy2_write_local;
+
+    layer45_cpy2_write_local_assign_proc : process(ap_CS_fsm_state1, ap_block_state1_pp0_stage0_iter0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_state1_pp0_stage0_iter0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            layer45_cpy2_write_local <= ap_const_logic_1;
+        else 
+            layer45_cpy2_write_local <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    real_start_assign_proc : process(ap_start, start_full_n, start_once_reg)
+    begin
+        if (((start_full_n = ap_const_logic_0) and (start_once_reg = ap_const_logic_0))) then 
+            real_start <= ap_const_logic_0;
+        else 
+            real_start <= ap_start;
+        end if; 
+    end process;
+
+    start_out <= real_start;
+
+    start_write_assign_proc : process(real_start, start_once_reg)
+    begin
+        if (((real_start = ap_const_logic_1) and (start_once_reg = ap_const_logic_0))) then 
+            start_write <= ap_const_logic_1;
+        else 
+            start_write <= ap_const_logic_0;
+        end if; 
+    end process;
+
+end behav;

myproject_prj/solution1/impl/vhdl/myproject_clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_s.vhd

@@ -0,0 +1,346 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity myproject_clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_s is
+port (
+    ap_clk : IN STD_LOGIC;
+    ap_rst : IN STD_LOGIC;
+    ap_start : IN STD_LOGIC;
+    start_full_n : IN STD_LOGIC;
+    ap_done : OUT STD_LOGIC;
+    ap_continue : IN STD_LOGIC;
+    ap_idle : OUT STD_LOGIC;
+    ap_ready : OUT STD_LOGIC;
+    layer5_out_dout : IN STD_LOGIC_VECTOR (127 downto 0);
+    layer5_out_num_data_valid : IN STD_LOGIC_VECTOR (12 downto 0);
+    layer5_out_fifo_cap : IN STD_LOGIC_VECTOR (12 downto 0);
+    layer5_out_empty_n : IN STD_LOGIC;
+    layer5_out_read : OUT STD_LOGIC;
+    layer43_cpy1_din : OUT STD_LOGIC_VECTOR (127 downto 0);
+    layer43_cpy1_num_data_valid : IN STD_LOGIC_VECTOR (12 downto 0);
+    layer43_cpy1_fifo_cap : IN STD_LOGIC_VECTOR (12 downto 0);
+    layer43_cpy1_full_n : IN STD_LOGIC;
+    layer43_cpy1_write : OUT STD_LOGIC;
+    layer43_cpy2_din : OUT STD_LOGIC_VECTOR (127 downto 0);
+    layer43_cpy2_num_data_valid : IN STD_LOGIC_VECTOR (12 downto 0);
+    layer43_cpy2_fifo_cap : IN STD_LOGIC_VECTOR (12 downto 0);
+    layer43_cpy2_full_n : IN STD_LOGIC;
+    layer43_cpy2_write : OUT STD_LOGIC;
+    start_out : OUT STD_LOGIC;
+    start_write : OUT STD_LOGIC );
+end;
+
+
+architecture behav of myproject_clone_stream_array_ap_fixed_8u_array_ap_fixed_16_6_5_3_0_8u_32768_s is 
+    constant ap_const_logic_1 : STD_LOGIC := '1';
+    constant ap_const_logic_0 : STD_LOGIC := '0';
+    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
+    constant ap_const_boolean_1 : BOOLEAN := true;
+    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
+    constant ap_const_boolean_0 : BOOLEAN := false;
+    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
+    constant ap_const_lv12_0 : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
+    constant ap_const_lv12_1 : STD_LOGIC_VECTOR (11 downto 0) := "000000000001";
+    constant ap_const_lv12_FFF : STD_LOGIC_VECTOR (11 downto 0) := "111111111111";
+
+attribute shreg_extract : string;
+    signal real_start : STD_LOGIC;
+    signal start_once_reg : STD_LOGIC := '0';
+    signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "1";
+    attribute fsm_encoding : string;
+    attribute fsm_encoding of ap_CS_fsm : signal is "none";
+    signal ap_CS_fsm_state1 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
+    signal internal_ap_ready : STD_LOGIC;
+    signal ap_done_reg : STD_LOGIC := '0';
+    signal ap_block_state1_pp0_stage0_iter0 : BOOLEAN;
+    signal icmp_ln22_fu_78_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal ap_condition_exit_pp0_iter0_stage0 : STD_LOGIC;
+    signal ap_loop_exit_ready : STD_LOGIC;
+    signal ap_ready_int : STD_LOGIC;
+    signal layer5_out_blk_n : STD_LOGIC;
+    signal layer43_cpy1_blk_n : STD_LOGIC;
+    signal layer43_cpy2_blk_n : STD_LOGIC;
+    signal i_0101_fu_38 : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
+    signal i_fu_72_p2 : STD_LOGIC_VECTOR (11 downto 0);
+    signal ap_loop_init : STD_LOGIC;
+    signal ap_sig_allocacmp_i_0101_load : STD_LOGIC_VECTOR (11 downto 0);
+    signal layer5_out_read_local : STD_LOGIC;
+    signal layer43_cpy1_write_local : STD_LOGIC;
+    signal layer43_cpy2_write_local : STD_LOGIC;
+    signal ap_continue_int : STD_LOGIC;
+    signal ap_done_int : STD_LOGIC;
+    signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
+    signal ap_ST_fsm_state1_blk : STD_LOGIC;
+    signal ap_start_int : STD_LOGIC;
+    signal ap_done_sig : STD_LOGIC;
+    signal ap_ce_reg : STD_LOGIC;
+
+    component myproject_flow_control_loop_pipe IS
+    port (
+        ap_clk : IN STD_LOGIC;
+        ap_rst : IN STD_LOGIC;
+        ap_start : IN STD_LOGIC;
+        ap_ready : OUT STD_LOGIC;
+        ap_done : OUT STD_LOGIC;
+        ap_start_int : OUT STD_LOGIC;
+        ap_loop_init : OUT STD_LOGIC;
+        ap_ready_int : IN STD_LOGIC;
+        ap_loop_exit_ready : IN STD_LOGIC;
+        ap_loop_exit_done : IN STD_LOGIC;
+        ap_continue_int : OUT STD_LOGIC;
+        ap_done_int : IN STD_LOGIC;
+        ap_continue : IN STD_LOGIC );
+    end component;
+
+
+
+begin
+    flow_control_loop_pipe_U : component myproject_flow_control_loop_pipe
+    port map (
+        ap_clk => ap_clk,
+        ap_rst => ap_rst,
+        ap_start => real_start,
+        ap_ready => internal_ap_ready,
+        ap_done => ap_done_sig,
+        ap_start_int => ap_start_int,
+        ap_loop_init => ap_loop_init,
+        ap_ready_int => ap_ready_int,
+        ap_loop_exit_ready => ap_condition_exit_pp0_iter0_stage0,
+        ap_loop_exit_done => ap_done_int,
+        ap_continue_int => ap_continue_int,
+        ap_done_int => ap_done_int,
+        ap_continue => ap_continue);
+
+
+
+
+
+    ap_CS_fsm_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_CS_fsm <= ap_ST_fsm_state1;
+            else
+                ap_CS_fsm <= ap_NS_fsm;
+            end if;
+        end if;
+    end process;
+
+
+    ap_done_reg_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_done_reg <= ap_const_logic_0;
+            else
+                if ((ap_continue_int = ap_const_logic_1)) then 
+                    ap_done_reg <= ap_const_logic_0;
+                elsif (((ap_loop_exit_ready = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_state1_pp0_stage0_iter0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+                    ap_done_reg <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    start_once_reg_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                start_once_reg <= ap_const_logic_0;
+            else
+                if (((real_start = ap_const_logic_1) and (internal_ap_ready = ap_const_logic_0))) then 
+                    start_once_reg <= ap_const_logic_1;
+                elsif ((internal_ap_ready = ap_const_logic_1)) then 
+                    start_once_reg <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    i_0101_fu_38_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_state1_pp0_stage0_iter0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                i_0101_fu_38 <= i_fu_72_p2;
+            end if;
+        end if;
+    end process;
+
+    ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_CS_fsm_state1, ap_block_state1_pp0_stage0_iter0)
+    begin
+        case ap_CS_fsm is
+            when ap_ST_fsm_state1 => 
+                ap_NS_fsm <= ap_ST_fsm_state1;
+            when others =>  
+                ap_NS_fsm <= "X";
+        end case;
+    end process;
+    ap_CS_fsm_state1 <= ap_CS_fsm(0);
+
+    ap_ST_fsm_state1_blk_assign_proc : process(ap_block_state1_pp0_stage0_iter0)
+    begin
+        if ((ap_const_boolean_1 = ap_block_state1_pp0_stage0_iter0)) then 
+            ap_ST_fsm_state1_blk <= ap_const_logic_1;
+        else 
+            ap_ST_fsm_state1_blk <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_block_state1_pp0_stage0_iter0_assign_proc : process(layer5_out_empty_n, layer43_cpy1_full_n, layer43_cpy2_full_n, ap_done_reg, ap_start_int)
+    begin
+                ap_block_state1_pp0_stage0_iter0 <= ((ap_done_reg = ap_const_logic_1) or (layer43_cpy2_full_n = ap_const_logic_0) or (layer43_cpy1_full_n = ap_const_logic_0) or (layer5_out_empty_n = ap_const_logic_0) or (ap_start_int = ap_const_logic_0));
+    end process;
+
+
+    ap_condition_exit_pp0_iter0_stage0_assign_proc : process(ap_CS_fsm_state1, ap_block_state1_pp0_stage0_iter0, icmp_ln22_fu_78_p2)
+    begin
+        if (((icmp_ln22_fu_78_p2 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_state1_pp0_stage0_iter0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            ap_condition_exit_pp0_iter0_stage0 <= ap_const_logic_1;
+        else 
+            ap_condition_exit_pp0_iter0_stage0 <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    ap_done <= ap_done_sig;
+
+    ap_done_int_assign_proc : process(ap_CS_fsm_state1, ap_done_reg, ap_block_state1_pp0_stage0_iter0, ap_loop_exit_ready)
+    begin
+        if (((ap_loop_exit_ready = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_state1_pp0_stage0_iter0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            ap_done_int <= ap_const_logic_1;
+        else 
+            ap_done_int <= ap_done_reg;
+        end if; 
+    end process;
+
+
+    ap_idle_assign_proc : process(ap_CS_fsm_state1, ap_start_int)
+    begin
+        if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start_int = ap_const_logic_0))) then 
+            ap_idle <= ap_const_logic_1;
+        else 
+            ap_idle <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    ap_loop_exit_ready <= ap_condition_exit_pp0_iter0_stage0;
+    ap_ready <= internal_ap_ready;
+
+    ap_ready_int_assign_proc : process(ap_CS_fsm_state1, ap_block_state1_pp0_stage0_iter0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_state1_pp0_stage0_iter0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            ap_ready_int <= ap_const_logic_1;
+        else 
+            ap_ready_int <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_sig_allocacmp_i_0101_load_assign_proc : process(ap_CS_fsm_state1, i_0101_fu_38, ap_loop_init)
+    begin
+        if (((ap_loop_init = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            ap_sig_allocacmp_i_0101_load <= ap_const_lv12_0;
+        else 
+            ap_sig_allocacmp_i_0101_load <= i_0101_fu_38;
+        end if; 
+    end process;
+
+    i_fu_72_p2 <= std_logic_vector(unsigned(ap_sig_allocacmp_i_0101_load) + unsigned(ap_const_lv12_1));
+    icmp_ln22_fu_78_p2 <= "1" when (ap_sig_allocacmp_i_0101_load = ap_const_lv12_FFF) else "0";
+
+    layer43_cpy1_blk_n_assign_proc : process(ap_CS_fsm_state1, layer43_cpy1_full_n, ap_done_reg, ap_start_int)
+    begin
+        if ((not(((ap_done_reg = ap_const_logic_1) or (ap_start_int = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            layer43_cpy1_blk_n <= layer43_cpy1_full_n;
+        else 
+            layer43_cpy1_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    layer43_cpy1_din <= layer5_out_dout;
+    layer43_cpy1_write <= layer43_cpy1_write_local;
+
+    layer43_cpy1_write_local_assign_proc : process(ap_CS_fsm_state1, ap_block_state1_pp0_stage0_iter0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_state1_pp0_stage0_iter0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            layer43_cpy1_write_local <= ap_const_logic_1;
+        else 
+            layer43_cpy1_write_local <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    layer43_cpy2_blk_n_assign_proc : process(ap_CS_fsm_state1, layer43_cpy2_full_n, ap_done_reg, ap_start_int)
+    begin
+        if ((not(((ap_done_reg = ap_const_logic_1) or (ap_start_int = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            layer43_cpy2_blk_n <= layer43_cpy2_full_n;
+        else 
+            layer43_cpy2_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    layer43_cpy2_din <= layer5_out_dout;
+    layer43_cpy2_write <= layer43_cpy2_write_local;
+
+    layer43_cpy2_write_local_assign_proc : process(ap_CS_fsm_state1, ap_block_state1_pp0_stage0_iter0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_state1_pp0_stage0_iter0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            layer43_cpy2_write_local <= ap_const_logic_1;
+        else 
+            layer43_cpy2_write_local <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    layer5_out_blk_n_assign_proc : process(ap_CS_fsm_state1, layer5_out_empty_n, ap_done_reg, ap_start_int)
+    begin
+        if ((not(((ap_done_reg = ap_const_logic_1) or (ap_start_int = ap_const_logic_0))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            layer5_out_blk_n <= layer5_out_empty_n;
+        else 
+            layer5_out_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    layer5_out_read <= layer5_out_read_local;
+
+    layer5_out_read_local_assign_proc : process(ap_CS_fsm_state1, ap_block_state1_pp0_stage0_iter0)
+    begin
+        if (((ap_const_boolean_0 = ap_block_state1_pp0_stage0_iter0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            layer5_out_read_local <= ap_const_logic_1;
+        else 
+            layer5_out_read_local <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    real_start_assign_proc : process(ap_start, start_full_n, start_once_reg)
+    begin
+        if (((start_full_n = ap_const_logic_0) and (start_once_reg = ap_const_logic_0))) then 
+            real_start <= ap_const_logic_0;
+        else 
+            real_start <= ap_start;
+        end if; 
+    end process;
+
+    start_out <= real_start;
+
+    start_write_assign_proc : process(real_start, start_once_reg)
+    begin
+        if (((real_start = ap_const_logic_1) and (start_once_reg = ap_const_logic_0))) then 
+            start_write <= ap_const_logic_1;
+        else 
+            start_write <= ap_const_logic_0;
+        end if; 
+    end process;
+
+end behav;

myproject_prj/solution1/impl/vhdl/myproject_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s.vhd

@@ -0,0 +1,333 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity myproject_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s is
+port (
+    ap_clk : IN STD_LOGIC;
+    ap_rst : IN STD_LOGIC;
+    ap_start : IN STD_LOGIC;
+    start_full_n : IN STD_LOGIC;
+    ap_done : OUT STD_LOGIC;
+    ap_continue : IN STD_LOGIC;
+    ap_idle : OUT STD_LOGIC;
+    ap_ready : OUT STD_LOGIC;
+    start_out : OUT STD_LOGIC;
+    start_write : OUT STD_LOGIC;
+    layer33_out_dout : IN STD_LOGIC_VECTOR (255 downto 0);
+    layer33_out_num_data_valid : IN STD_LOGIC_VECTOR (12 downto 0);
+    layer33_out_fifo_cap : IN STD_LOGIC_VECTOR (12 downto 0);
+    layer33_out_empty_n : IN STD_LOGIC;
+    layer33_out_read : OUT STD_LOGIC;
+    layer43_cpy2_dout : IN STD_LOGIC_VECTOR (127 downto 0);
+    layer43_cpy2_num_data_valid : IN STD_LOGIC_VECTOR (12 downto 0);
+    layer43_cpy2_fifo_cap : IN STD_LOGIC_VECTOR (12 downto 0);
+    layer43_cpy2_empty_n : IN STD_LOGIC;
+    layer43_cpy2_read : OUT STD_LOGIC;
+    layer34_out_din : OUT STD_LOGIC_VECTOR (383 downto 0);
+    layer34_out_num_data_valid : IN STD_LOGIC_VECTOR (12 downto 0);
+    layer34_out_fifo_cap : IN STD_LOGIC_VECTOR (12 downto 0);
+    layer34_out_full_n : IN STD_LOGIC;
+    layer34_out_write : OUT STD_LOGIC );
+end;
+
+
+architecture behav of myproject_concatenate3d_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s is 
+    constant ap_const_logic_1 : STD_LOGIC := '1';
+    constant ap_const_logic_0 : STD_LOGIC := '0';
+    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
+    constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
+    constant ap_const_boolean_1 : BOOLEAN := true;
+    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
+    constant ap_const_boolean_0 : BOOLEAN := false;
+    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
+    constant ap_const_lv13_0 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000000";
+
+attribute shreg_extract : string;
+    signal real_start : STD_LOGIC;
+    signal start_once_reg : STD_LOGIC := '0';
+    signal ap_done_reg : STD_LOGIC := '0';
+    signal ap_CS_fsm : STD_LOGIC_VECTOR (1 downto 0) := "01";
+    attribute fsm_encoding : string;
+    attribute fsm_encoding of ap_CS_fsm : signal is "none";
+    signal ap_CS_fsm_state1 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
+    signal internal_ap_ready : STD_LOGIC;
+    signal grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_start : STD_LOGIC;
+    signal grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_done : STD_LOGIC;
+    signal grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_idle : STD_LOGIC;
+    signal grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_ready : STD_LOGIC;
+    signal grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_layer33_out_read : STD_LOGIC;
+    signal grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_layer43_cpy2_read : STD_LOGIC;
+    signal grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_layer34_out_din : STD_LOGIC_VECTOR (383 downto 0);
+    signal grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_layer34_out_write : STD_LOGIC;
+    signal grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_start_reg : STD_LOGIC := '0';
+    signal ap_block_state1_ignore_call3 : BOOLEAN;
+    signal ap_CS_fsm_state2 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
+    signal ap_NS_fsm : STD_LOGIC_VECTOR (1 downto 0);
+    signal ap_block_state1 : BOOLEAN;
+    signal ap_ST_fsm_state1_blk : STD_LOGIC;
+    signal ap_ST_fsm_state2_blk : STD_LOGIC;
+    signal ap_ce_reg : STD_LOGIC;
+
+    component myproject_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s IS
+    port (
+        ap_clk : IN STD_LOGIC;
+        ap_rst : IN STD_LOGIC;
+        ap_start : IN STD_LOGIC;
+        ap_done : OUT STD_LOGIC;
+        ap_idle : OUT STD_LOGIC;
+        ap_ready : OUT STD_LOGIC;
+        layer33_out_dout : IN STD_LOGIC_VECTOR (255 downto 0);
+        layer33_out_num_data_valid : IN STD_LOGIC_VECTOR (12 downto 0);
+        layer33_out_fifo_cap : IN STD_LOGIC_VECTOR (12 downto 0);
+        layer33_out_empty_n : IN STD_LOGIC;
+        layer33_out_read : OUT STD_LOGIC;
+        layer43_cpy2_dout : IN STD_LOGIC_VECTOR (127 downto 0);
+        layer43_cpy2_num_data_valid : IN STD_LOGIC_VECTOR (12 downto 0);
+        layer43_cpy2_fifo_cap : IN STD_LOGIC_VECTOR (12 downto 0);
+        layer43_cpy2_empty_n : IN STD_LOGIC;
+        layer43_cpy2_read : OUT STD_LOGIC;
+        layer34_out_din : OUT STD_LOGIC_VECTOR (383 downto 0);
+        layer34_out_num_data_valid : IN STD_LOGIC_VECTOR (12 downto 0);
+        layer34_out_fifo_cap : IN STD_LOGIC_VECTOR (12 downto 0);
+        layer34_out_full_n : IN STD_LOGIC;
+        layer34_out_write : OUT STD_LOGIC );
+    end component;
+
+
+
+begin
+    grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18 : component myproject_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s
+    port map (
+        ap_clk => ap_clk,
+        ap_rst => ap_rst,
+        ap_start => grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_start,
+        ap_done => grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_done,
+        ap_idle => grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_idle,
+        ap_ready => grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_ready,
+        layer33_out_dout => layer33_out_dout,
+        layer33_out_num_data_valid => ap_const_lv13_0,
+        layer33_out_fifo_cap => ap_const_lv13_0,
+        layer33_out_empty_n => layer33_out_empty_n,
+        layer33_out_read => grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_layer33_out_read,
+        layer43_cpy2_dout => layer43_cpy2_dout,
+        layer43_cpy2_num_data_valid => ap_const_lv13_0,
+        layer43_cpy2_fifo_cap => ap_const_lv13_0,
+        layer43_cpy2_empty_n => layer43_cpy2_empty_n,
+        layer43_cpy2_read => grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_layer43_cpy2_read,
+        layer34_out_din => grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_layer34_out_din,
+        layer34_out_num_data_valid => ap_const_lv13_0,
+        layer34_out_fifo_cap => ap_const_lv13_0,
+        layer34_out_full_n => layer34_out_full_n,
+        layer34_out_write => grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_layer34_out_write);
+
+
+
+
+
+    ap_CS_fsm_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_CS_fsm <= ap_ST_fsm_state1;
+            else
+                ap_CS_fsm <= ap_NS_fsm;
+            end if;
+        end if;
+    end process;
+
+
+    ap_done_reg_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_done_reg <= ap_const_logic_0;
+            else
+                if ((ap_continue = ap_const_logic_1)) then 
+                    ap_done_reg <= ap_const_logic_0;
+                elsif (((grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_done = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+                    ap_done_reg <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_start_reg_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_start_reg <= ap_const_logic_0;
+            else
+                if (((ap_const_boolean_0 = ap_block_state1_ignore_call3) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+                    grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_start_reg <= ap_const_logic_1;
+                elsif ((grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_ready = ap_const_logic_1)) then 
+                    grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_start_reg <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    start_once_reg_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                start_once_reg <= ap_const_logic_0;
+            else
+                if (((real_start = ap_const_logic_1) and (internal_ap_ready = ap_const_logic_0))) then 
+                    start_once_reg <= ap_const_logic_1;
+                elsif ((internal_ap_ready = ap_const_logic_1)) then 
+                    start_once_reg <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_CS_fsm_state1, grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_done, ap_CS_fsm_state2, ap_block_state1)
+    begin
+        case ap_CS_fsm is
+            when ap_ST_fsm_state1 => 
+                if (((ap_const_boolean_0 = ap_block_state1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                    ap_NS_fsm <= ap_ST_fsm_state2;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state1;
+                end if;
+            when ap_ST_fsm_state2 => 
+                if (((grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_done = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
+                    ap_NS_fsm <= ap_ST_fsm_state1;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state2;
+                end if;
+            when others =>  
+                ap_NS_fsm <= "XX";
+        end case;
+    end process;
+    ap_CS_fsm_state1 <= ap_CS_fsm(0);
+    ap_CS_fsm_state2 <= ap_CS_fsm(1);
+
+    ap_ST_fsm_state1_blk_assign_proc : process(ap_block_state1)
+    begin
+        if ((ap_const_boolean_1 = ap_block_state1)) then 
+            ap_ST_fsm_state1_blk <= ap_const_logic_1;
+        else 
+            ap_ST_fsm_state1_blk <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_ST_fsm_state2_blk_assign_proc : process(grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_done)
+    begin
+        if ((grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_done = ap_const_logic_0)) then 
+            ap_ST_fsm_state2_blk <= ap_const_logic_1;
+        else 
+            ap_ST_fsm_state2_blk <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_block_state1_assign_proc : process(real_start, ap_done_reg)
+    begin
+                ap_block_state1 <= ((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
+    end process;
+
+
+    ap_block_state1_ignore_call3_assign_proc : process(real_start, ap_done_reg)
+    begin
+                ap_block_state1_ignore_call3 <= ((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
+    end process;
+
+
+    ap_done_assign_proc : process(ap_done_reg, grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_done, ap_CS_fsm_state2)
+    begin
+        if (((grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_done = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+            ap_done <= ap_const_logic_1;
+        else 
+            ap_done <= ap_done_reg;
+        end if; 
+    end process;
+
+
+    ap_idle_assign_proc : process(real_start, ap_CS_fsm_state1)
+    begin
+        if (((real_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            ap_idle <= ap_const_logic_1;
+        else 
+            ap_idle <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    ap_ready <= internal_ap_ready;
+    grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_start <= grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_start_reg;
+
+    internal_ap_ready_assign_proc : process(grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_done, ap_CS_fsm_state2)
+    begin
+        if (((grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_ap_done = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+            internal_ap_ready <= ap_const_logic_1;
+        else 
+            internal_ap_ready <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    layer33_out_read_assign_proc : process(grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_layer33_out_read, ap_CS_fsm_state2)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+            layer33_out_read <= grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_layer33_out_read;
+        else 
+            layer33_out_read <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    layer34_out_din <= grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_layer34_out_din;
+
+    layer34_out_write_assign_proc : process(grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_layer34_out_write, ap_CS_fsm_state2)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+            layer34_out_write <= grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_layer34_out_write;
+        else 
+            layer34_out_write <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    layer43_cpy2_read_assign_proc : process(grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_layer43_cpy2_read, ap_CS_fsm_state2)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state2)) then 
+            layer43_cpy2_read <= grp_concatenate3d_2_array_array_array_ap_fixed_16_6_5_3_0_24u_config34_s_fu_18_layer43_cpy2_read;
+        else 
+            layer43_cpy2_read <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    real_start_assign_proc : process(ap_start, start_full_n, start_once_reg)
+    begin
+        if (((start_full_n = ap_const_logic_0) and (start_once_reg = ap_const_logic_0))) then 
+            real_start <= ap_const_logic_0;
+        else 
+            real_start <= ap_start;
+        end if; 
+    end process;
+
+    start_out <= real_start;
+
+    start_write_assign_proc : process(real_start, start_once_reg)
+    begin
+        if (((real_start = ap_const_logic_1) and (start_once_reg = ap_const_logic_0))) then 
+            start_write <= ap_const_logic_1;
+        else 
+            start_write <= ap_const_logic_0;
+        end if; 
+    end process;
+
+end behav;

myproject_prj/solution1/impl/vhdl/myproject_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_s.vhd

@@ -0,0 +1,415 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity myproject_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_s is
+port (
+    ap_clk : IN STD_LOGIC;
+    ap_rst : IN STD_LOGIC;
+    ap_start : IN STD_LOGIC;
+    start_full_n : IN STD_LOGIC;
+    ap_done : OUT STD_LOGIC;
+    ap_continue : IN STD_LOGIC;
+    ap_idle : OUT STD_LOGIC;
+    ap_ready : OUT STD_LOGIC;
+    start_out : OUT STD_LOGIC;
+    start_write : OUT STD_LOGIC;
+    layer48_out_dout : IN STD_LOGIC_VECTOR (127 downto 0);
+    layer48_out_num_data_valid : IN STD_LOGIC_VECTOR (11 downto 0);
+    layer48_out_fifo_cap : IN STD_LOGIC_VECTOR (11 downto 0);
+    layer48_out_empty_n : IN STD_LOGIC;
+    layer48_out_read : OUT STD_LOGIC;
+    layer7_out_din : OUT STD_LOGIC_VECTOR (639 downto 0);
+    layer7_out_num_data_valid : IN STD_LOGIC_VECTOR (10 downto 0);
+    layer7_out_fifo_cap : IN STD_LOGIC_VECTOR (10 downto 0);
+    layer7_out_full_n : IN STD_LOGIC;
+    layer7_out_write : OUT STD_LOGIC );
+end;
+
+
+architecture behav of myproject_conv_2d_cl_array_ap_fixed_8u_array_ap_fixed_40_20_5_3_0_16u_config7_s is 
+    constant ap_const_logic_1 : STD_LOGIC := '1';
+    constant ap_const_logic_0 : STD_LOGIC := '0';
+    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (2 downto 0) := "001";
+    constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (2 downto 0) := "010";
+    constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (2 downto 0) := "100";
+    constant ap_const_boolean_1 : BOOLEAN := true;
+    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
+    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
+    constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
+    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
+    constant ap_const_boolean_0 : BOOLEAN := false;
+    constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
+    constant ap_const_lv11_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000000";
+    constant ap_const_lv11_484 : STD_LOGIC_VECTOR (10 downto 0) := "10010000100";
+    constant ap_const_lv11_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
+    constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
+    constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
+    constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
+    constant ap_const_lv32_2F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101111";
+    constant ap_const_lv32_30 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110000";
+    constant ap_const_lv32_3F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111111";
+    constant ap_const_lv32_40 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000000";
+    constant ap_const_lv32_4F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001111";
+    constant ap_const_lv32_50 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010000";
+    constant ap_const_lv32_5F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011111";
+    constant ap_const_lv32_60 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100000";
+    constant ap_const_lv32_6F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001101111";
+    constant ap_const_lv32_70 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110000";
+    constant ap_const_lv32_7F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111111";
+
+attribute shreg_extract : string;
+    signal real_start : STD_LOGIC;
+    signal start_once_reg : STD_LOGIC := '0';
+    signal ap_done_reg : STD_LOGIC := '0';
+    signal ap_CS_fsm : STD_LOGIC_VECTOR (2 downto 0) := "001";
+    attribute fsm_encoding : string;
+    attribute fsm_encoding of ap_CS_fsm : signal is "none";
+    signal ap_CS_fsm_state1 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
+    signal internal_ap_ready : STD_LOGIC;
+    signal layer48_out_blk_n : STD_LOGIC;
+    signal ap_CS_fsm_state2 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
+    signal icmp_ln52_fu_468_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal trunc_ln58_fu_480_p1 : STD_LOGIC_VECTOR (15 downto 0);
+    signal trunc_ln58_reg_577 : STD_LOGIC_VECTOR (15 downto 0);
+    signal ap_block_state2 : BOOLEAN;
+    signal trunc_ln58_s_reg_582 : STD_LOGIC_VECTOR (15 downto 0);
+    signal trunc_ln58_4_reg_587 : STD_LOGIC_VECTOR (15 downto 0);
+    signal trunc_ln58_5_reg_592 : STD_LOGIC_VECTOR (15 downto 0);
+    signal trunc_ln58_6_reg_597 : STD_LOGIC_VECTOR (15 downto 0);
+    signal trunc_ln58_7_reg_602 : STD_LOGIC_VECTOR (15 downto 0);
+    signal trunc_ln58_8_reg_607 : STD_LOGIC_VECTOR (15 downto 0);
+    signal trunc_ln58_9_reg_612 : STD_LOGIC_VECTOR (15 downto 0);
+    signal grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s_fu_260_ap_start : STD_LOGIC;
+    signal grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s_fu_260_ap_done : STD_LOGIC;
+    signal grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s_fu_260_ap_idle : STD_LOGIC;
+    signal grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s_fu_260_ap_ready : STD_LOGIC;
+    signal grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s_fu_260_layer7_out_din : STD_LOGIC_VECTOR (639 downto 0);
+    signal grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s_fu_260_layer7_out_write : STD_LOGIC;
+    signal grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s_fu_260_ap_start_reg : STD_LOGIC := '0';
+    signal ap_block_state2_ignore_call11 : BOOLEAN;
+    signal ap_CS_fsm_state3 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
+    signal indvar_flatten_fu_250 : STD_LOGIC_VECTOR (10 downto 0) := "00000000000";
+    signal add_ln52_fu_474_p2 : STD_LOGIC_VECTOR (10 downto 0);
+    signal ap_block_state1 : BOOLEAN;
+    signal layer48_out_read_local : STD_LOGIC;
+    signal ap_NS_fsm : STD_LOGIC_VECTOR (2 downto 0);
+    signal ap_ST_fsm_state1_blk : STD_LOGIC;
+    signal ap_ST_fsm_state2_blk : STD_LOGIC;
+    signal ap_ST_fsm_state3_blk : STD_LOGIC;
+    signal ap_ce_reg : STD_LOGIC;
+
+    component myproject_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s IS
+    port (
+        ap_clk : IN STD_LOGIC;
+        ap_rst : IN STD_LOGIC;
+        ap_start : IN STD_LOGIC;
+        ap_done : OUT STD_LOGIC;
+        ap_idle : OUT STD_LOGIC;
+        ap_ready : OUT STD_LOGIC;
+        p_read : IN STD_LOGIC_VECTOR (15 downto 0);
+        p_read1 : IN STD_LOGIC_VECTOR (15 downto 0);
+        p_read2 : IN STD_LOGIC_VECTOR (15 downto 0);
+        p_read3 : IN STD_LOGIC_VECTOR (15 downto 0);
+        p_read4 : IN STD_LOGIC_VECTOR (15 downto 0);
+        p_read5 : IN STD_LOGIC_VECTOR (15 downto 0);
+        p_read6 : IN STD_LOGIC_VECTOR (15 downto 0);
+        p_read7 : IN STD_LOGIC_VECTOR (15 downto 0);
+        layer7_out_din : OUT STD_LOGIC_VECTOR (639 downto 0);
+        layer7_out_num_data_valid : IN STD_LOGIC_VECTOR (10 downto 0);
+        layer7_out_fifo_cap : IN STD_LOGIC_VECTOR (10 downto 0);
+        layer7_out_full_n : IN STD_LOGIC;
+        layer7_out_write : OUT STD_LOGIC );
+    end component;
+
+
+
+begin
+    grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s_fu_260 : component myproject_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s
+    port map (
+        ap_clk => ap_clk,
+        ap_rst => ap_rst,
+        ap_start => grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s_fu_260_ap_start,
+        ap_done => grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s_fu_260_ap_done,
+        ap_idle => grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s_fu_260_ap_idle,
+        ap_ready => grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s_fu_260_ap_ready,
+        p_read => trunc_ln58_reg_577,
+        p_read1 => trunc_ln58_s_reg_582,
+        p_read2 => trunc_ln58_4_reg_587,
+        p_read3 => trunc_ln58_5_reg_592,
+        p_read4 => trunc_ln58_6_reg_597,
+        p_read5 => trunc_ln58_7_reg_602,
+        p_read6 => trunc_ln58_8_reg_607,
+        p_read7 => trunc_ln58_9_reg_612,
+        layer7_out_din => grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s_fu_260_layer7_out_din,
+        layer7_out_num_data_valid => ap_const_lv11_0,
+        layer7_out_fifo_cap => ap_const_lv11_0,
+        layer7_out_full_n => layer7_out_full_n,
+        layer7_out_write => grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s_fu_260_layer7_out_write);
+
+
+
+
+
+    ap_CS_fsm_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_CS_fsm <= ap_ST_fsm_state1;
+            else
+                ap_CS_fsm <= ap_NS_fsm;
+            end if;
+        end if;
+    end process;
+
+
+    ap_done_reg_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_done_reg <= ap_const_logic_0;
+            else
+                if ((ap_continue = ap_const_logic_1)) then 
+                    ap_done_reg <= ap_const_logic_0;
+                elsif (((ap_const_boolean_0 = ap_block_state2) and (icmp_ln52_fu_468_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+                    ap_done_reg <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s_fu_260_ap_start_reg_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s_fu_260_ap_start_reg <= ap_const_logic_0;
+            else
+                if (((ap_const_boolean_0 = ap_block_state2_ignore_call11) and (icmp_ln52_fu_468_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+                    grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s_fu_260_ap_start_reg <= ap_const_logic_1;
+                elsif ((grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s_fu_260_ap_ready = ap_const_logic_1)) then 
+                    grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s_fu_260_ap_start_reg <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    start_once_reg_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                start_once_reg <= ap_const_logic_0;
+            else
+                if (((real_start = ap_const_logic_1) and (internal_ap_ready = ap_const_logic_0))) then 
+                    start_once_reg <= ap_const_logic_1;
+                elsif ((internal_ap_ready = ap_const_logic_1)) then 
+                    start_once_reg <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    indvar_flatten_fu_250_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_state1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+                indvar_flatten_fu_250 <= ap_const_lv11_0;
+            elsif (((ap_const_boolean_0 = ap_block_state2) and (icmp_ln52_fu_468_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+                indvar_flatten_fu_250 <= add_ln52_fu_474_p2;
+            end if; 
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_state2) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
+                trunc_ln58_4_reg_587 <= layer48_out_dout(47 downto 32);
+                trunc_ln58_5_reg_592 <= layer48_out_dout(63 downto 48);
+                trunc_ln58_6_reg_597 <= layer48_out_dout(79 downto 64);
+                trunc_ln58_7_reg_602 <= layer48_out_dout(95 downto 80);
+                trunc_ln58_8_reg_607 <= layer48_out_dout(111 downto 96);
+                trunc_ln58_9_reg_612 <= layer48_out_dout(127 downto 112);
+                trunc_ln58_reg_577 <= trunc_ln58_fu_480_p1;
+                trunc_ln58_s_reg_582 <= layer48_out_dout(31 downto 16);
+            end if;
+        end if;
+    end process;
+
+    ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_CS_fsm_state1, ap_CS_fsm_state2, icmp_ln52_fu_468_p2, ap_block_state2, grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s_fu_260_ap_done, ap_CS_fsm_state3, ap_block_state1)
+    begin
+        case ap_CS_fsm is
+            when ap_ST_fsm_state1 => 
+                if (((ap_const_boolean_0 = ap_block_state1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                    ap_NS_fsm <= ap_ST_fsm_state2;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state1;
+                end if;
+            when ap_ST_fsm_state2 => 
+                if (((ap_const_boolean_0 = ap_block_state2) and (icmp_ln52_fu_468_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
+                    ap_NS_fsm <= ap_ST_fsm_state1;
+                elsif (((ap_const_boolean_0 = ap_block_state2) and (icmp_ln52_fu_468_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
+                    ap_NS_fsm <= ap_ST_fsm_state3;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state2;
+                end if;
+            when ap_ST_fsm_state3 => 
+                if (((grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s_fu_260_ap_done = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
+                    ap_NS_fsm <= ap_ST_fsm_state2;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state3;
+                end if;
+            when others =>  
+                ap_NS_fsm <= "XXX";
+        end case;
+    end process;
+    add_ln52_fu_474_p2 <= std_logic_vector(unsigned(indvar_flatten_fu_250) + unsigned(ap_const_lv11_1));
+    ap_CS_fsm_state1 <= ap_CS_fsm(0);
+    ap_CS_fsm_state2 <= ap_CS_fsm(1);
+    ap_CS_fsm_state3 <= ap_CS_fsm(2);
+
+    ap_ST_fsm_state1_blk_assign_proc : process(ap_block_state1)
+    begin
+        if ((ap_const_boolean_1 = ap_block_state1)) then 
+            ap_ST_fsm_state1_blk <= ap_const_logic_1;
+        else 
+            ap_ST_fsm_state1_blk <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_ST_fsm_state2_blk_assign_proc : process(ap_block_state2)
+    begin
+        if ((ap_const_boolean_1 = ap_block_state2)) then 
+            ap_ST_fsm_state2_blk <= ap_const_logic_1;
+        else 
+            ap_ST_fsm_state2_blk <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_ST_fsm_state3_blk_assign_proc : process(grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s_fu_260_ap_done)
+    begin
+        if ((grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s_fu_260_ap_done = ap_const_logic_0)) then 
+            ap_ST_fsm_state3_blk <= ap_const_logic_1;
+        else 
+            ap_ST_fsm_state3_blk <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_block_state1_assign_proc : process(real_start, ap_done_reg)
+    begin
+                ap_block_state1 <= ((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
+    end process;
+
+
+    ap_block_state2_assign_proc : process(layer48_out_empty_n, icmp_ln52_fu_468_p2)
+    begin
+                ap_block_state2 <= ((icmp_ln52_fu_468_p2 = ap_const_lv1_0) and (layer48_out_empty_n = ap_const_logic_0));
+    end process;
+
+
+    ap_block_state2_ignore_call11_assign_proc : process(layer48_out_empty_n, icmp_ln52_fu_468_p2)
+    begin
+                ap_block_state2_ignore_call11 <= ((icmp_ln52_fu_468_p2 = ap_const_lv1_0) and (layer48_out_empty_n = ap_const_logic_0));
+    end process;
+
+
+    ap_done_assign_proc : process(ap_done_reg, ap_CS_fsm_state2, icmp_ln52_fu_468_p2, ap_block_state2)
+    begin
+        if (((ap_const_boolean_0 = ap_block_state2) and (icmp_ln52_fu_468_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+            ap_done <= ap_const_logic_1;
+        else 
+            ap_done <= ap_done_reg;
+        end if; 
+    end process;
+
+
+    ap_idle_assign_proc : process(real_start, ap_CS_fsm_state1)
+    begin
+        if (((real_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            ap_idle <= ap_const_logic_1;
+        else 
+            ap_idle <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    ap_ready <= internal_ap_ready;
+    grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s_fu_260_ap_start <= grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s_fu_260_ap_start_reg;
+    icmp_ln52_fu_468_p2 <= "1" when (indvar_flatten_fu_250 = ap_const_lv11_484) else "0";
+
+    internal_ap_ready_assign_proc : process(ap_CS_fsm_state2, icmp_ln52_fu_468_p2, ap_block_state2)
+    begin
+        if (((ap_const_boolean_0 = ap_block_state2) and (icmp_ln52_fu_468_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+            internal_ap_ready <= ap_const_logic_1;
+        else 
+            internal_ap_ready <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    layer48_out_blk_n_assign_proc : process(layer48_out_empty_n, ap_CS_fsm_state2, icmp_ln52_fu_468_p2)
+    begin
+        if (((icmp_ln52_fu_468_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+            layer48_out_blk_n <= layer48_out_empty_n;
+        else 
+            layer48_out_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    layer48_out_read <= layer48_out_read_local;
+
+    layer48_out_read_local_assign_proc : process(ap_CS_fsm_state2, icmp_ln52_fu_468_p2, ap_block_state2)
+    begin
+        if (((ap_const_boolean_0 = ap_block_state2) and (icmp_ln52_fu_468_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+            layer48_out_read_local <= ap_const_logic_1;
+        else 
+            layer48_out_read_local <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    layer7_out_din <= grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s_fu_260_layer7_out_din;
+
+    layer7_out_write_assign_proc : process(grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s_fu_260_layer7_out_write, ap_CS_fsm_state3)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state3)) then 
+            layer7_out_write <= grp_compute_output_buffer_2d_array_array_ap_fixed_40_20_5_3_0_16u_config7_s_fu_260_layer7_out_write;
+        else 
+            layer7_out_write <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    real_start_assign_proc : process(ap_start, start_full_n, start_once_reg)
+    begin
+        if (((start_once_reg = ap_const_logic_0) and (start_full_n = ap_const_logic_0))) then 
+            real_start <= ap_const_logic_0;
+        else 
+            real_start <= ap_start;
+        end if; 
+    end process;
+
+    start_out <= real_start;
+
+    start_write_assign_proc : process(real_start, start_once_reg)
+    begin
+        if (((real_start = ap_const_logic_1) and (start_once_reg = ap_const_logic_0))) then 
+            start_write <= ap_const_logic_1;
+        else 
+            start_write <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    trunc_ln58_fu_480_p1 <= layer48_out_dout(16 - 1 downto 0);
+end behav;

myproject_prj/solution1/impl/vhdl/myproject_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_s.vhd

@@ -0,0 +1,463 @@
+-- ==============================================================
+-- Generated by Vitis HLS v2024.1
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- ==============================================================
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity myproject_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_s is
+port (
+    ap_clk : IN STD_LOGIC;
+    ap_rst : IN STD_LOGIC;
+    ap_start : IN STD_LOGIC;
+    start_full_n : IN STD_LOGIC;
+    ap_done : OUT STD_LOGIC;
+    ap_continue : IN STD_LOGIC;
+    ap_idle : OUT STD_LOGIC;
+    ap_ready : OUT STD_LOGIC;
+    start_out : OUT STD_LOGIC;
+    start_write : OUT STD_LOGIC;
+    layer57_out_dout : IN STD_LOGIC_VECTOR (255 downto 0);
+    layer57_out_num_data_valid : IN STD_LOGIC_VECTOR (11 downto 0);
+    layer57_out_fifo_cap : IN STD_LOGIC_VECTOR (11 downto 0);
+    layer57_out_empty_n : IN STD_LOGIC;
+    layer57_out_read : OUT STD_LOGIC;
+    layer31_out_din : OUT STD_LOGIC_VECTOR (655 downto 0);
+    layer31_out_num_data_valid : IN STD_LOGIC_VECTOR (10 downto 0);
+    layer31_out_fifo_cap : IN STD_LOGIC_VECTOR (10 downto 0);
+    layer31_out_full_n : IN STD_LOGIC;
+    layer31_out_write : OUT STD_LOGIC );
+end;
+
+
+architecture behav of myproject_conv_2d_cl_array_array_ap_fixed_41_21_5_3_0_16u_config31_s is 
+    constant ap_const_logic_1 : STD_LOGIC := '1';
+    constant ap_const_logic_0 : STD_LOGIC := '0';
+    constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (2 downto 0) := "001";
+    constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (2 downto 0) := "010";
+    constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (2 downto 0) := "100";
+    constant ap_const_boolean_1 : BOOLEAN := true;
+    constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
+    constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
+    constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
+    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
+    constant ap_const_boolean_0 : BOOLEAN := false;
+    constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
+    constant ap_const_lv11_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000000";
+    constant ap_const_lv11_484 : STD_LOGIC_VECTOR (10 downto 0) := "10010000100";
+    constant ap_const_lv11_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
+    constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
+    constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
+    constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
+    constant ap_const_lv32_2F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101111";
+    constant ap_const_lv32_30 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110000";
+    constant ap_const_lv32_3F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111111";
+    constant ap_const_lv32_40 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000000";
+    constant ap_const_lv32_4F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001111";
+    constant ap_const_lv32_50 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010000";
+    constant ap_const_lv32_5F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011111";
+    constant ap_const_lv32_60 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100000";
+    constant ap_const_lv32_6F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001101111";
+    constant ap_const_lv32_70 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110000";
+    constant ap_const_lv32_7F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111111";
+    constant ap_const_lv32_80 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010000000";
+    constant ap_const_lv32_8F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001111";
+    constant ap_const_lv32_90 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010000";
+    constant ap_const_lv32_9F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011111";
+    constant ap_const_lv32_A0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010100000";
+    constant ap_const_lv32_AF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010101111";
+    constant ap_const_lv32_B0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010110000";
+    constant ap_const_lv32_BF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010111111";
+    constant ap_const_lv32_C0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011000000";
+    constant ap_const_lv32_CF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011001111";
+    constant ap_const_lv32_D0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011010000";
+    constant ap_const_lv32_DF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011011111";
+    constant ap_const_lv32_E0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011100000";
+    constant ap_const_lv32_EF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011101111";
+    constant ap_const_lv32_F0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011110000";
+    constant ap_const_lv32_FF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011111111";
+
+attribute shreg_extract : string;
+    signal real_start : STD_LOGIC;
+    signal start_once_reg : STD_LOGIC := '0';
+    signal ap_done_reg : STD_LOGIC := '0';
+    signal ap_CS_fsm : STD_LOGIC_VECTOR (2 downto 0) := "001";
+    attribute fsm_encoding : string;
+    attribute fsm_encoding of ap_CS_fsm : signal is "none";
+    signal ap_CS_fsm_state1 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
+    signal internal_ap_ready : STD_LOGIC;
+    signal layer57_out_blk_n : STD_LOGIC;
+    signal ap_CS_fsm_state2 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
+    signal icmp_ln52_fu_860_p2 : STD_LOGIC_VECTOR (0 downto 0);
+    signal trunc_ln58_fu_872_p1 : STD_LOGIC_VECTOR (15 downto 0);
+    signal trunc_ln58_reg_1057 : STD_LOGIC_VECTOR (15 downto 0);
+    signal ap_block_state2 : BOOLEAN;
+    signal trunc_ln58_s_reg_1062 : STD_LOGIC_VECTOR (15 downto 0);
+    signal trunc_ln58_240_reg_1067 : STD_LOGIC_VECTOR (15 downto 0);
+    signal trunc_ln58_241_reg_1072 : STD_LOGIC_VECTOR (15 downto 0);
+    signal trunc_ln58_242_reg_1077 : STD_LOGIC_VECTOR (15 downto 0);
+    signal trunc_ln58_243_reg_1082 : STD_LOGIC_VECTOR (15 downto 0);
+    signal trunc_ln58_244_reg_1087 : STD_LOGIC_VECTOR (15 downto 0);
+    signal trunc_ln58_245_reg_1092 : STD_LOGIC_VECTOR (15 downto 0);
+    signal trunc_ln58_246_reg_1097 : STD_LOGIC_VECTOR (15 downto 0);
+    signal trunc_ln58_247_reg_1102 : STD_LOGIC_VECTOR (15 downto 0);
+    signal trunc_ln58_248_reg_1107 : STD_LOGIC_VECTOR (15 downto 0);
+    signal trunc_ln58_249_reg_1112 : STD_LOGIC_VECTOR (15 downto 0);
+    signal trunc_ln58_250_reg_1117 : STD_LOGIC_VECTOR (15 downto 0);
+    signal trunc_ln58_251_reg_1122 : STD_LOGIC_VECTOR (15 downto 0);
+    signal trunc_ln58_252_reg_1127 : STD_LOGIC_VECTOR (15 downto 0);
+    signal trunc_ln58_253_reg_1132 : STD_LOGIC_VECTOR (15 downto 0);
+    signal grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s_fu_468_ap_start : STD_LOGIC;
+    signal grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s_fu_468_ap_done : STD_LOGIC;
+    signal grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s_fu_468_ap_idle : STD_LOGIC;
+    signal grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s_fu_468_ap_ready : STD_LOGIC;
+    signal grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s_fu_468_layer31_out_din : STD_LOGIC_VECTOR (655 downto 0);
+    signal grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s_fu_468_layer31_out_write : STD_LOGIC;
+    signal grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s_fu_468_ap_start_reg : STD_LOGIC := '0';
+    signal ap_block_state2_ignore_call19 : BOOLEAN;
+    signal ap_CS_fsm_state3 : STD_LOGIC;
+    attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
+    signal indvar_flatten_fu_458 : STD_LOGIC_VECTOR (10 downto 0) := "00000000000";
+    signal add_ln52_fu_866_p2 : STD_LOGIC_VECTOR (10 downto 0);
+    signal ap_block_state1 : BOOLEAN;
+    signal layer57_out_read_local : STD_LOGIC;
+    signal ap_NS_fsm : STD_LOGIC_VECTOR (2 downto 0);
+    signal ap_ST_fsm_state1_blk : STD_LOGIC;
+    signal ap_ST_fsm_state2_blk : STD_LOGIC;
+    signal ap_ST_fsm_state3_blk : STD_LOGIC;
+    signal ap_ce_reg : STD_LOGIC;
+
+    component myproject_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s IS
+    port (
+        ap_clk : IN STD_LOGIC;
+        ap_rst : IN STD_LOGIC;
+        ap_start : IN STD_LOGIC;
+        ap_done : OUT STD_LOGIC;
+        ap_idle : OUT STD_LOGIC;
+        ap_ready : OUT STD_LOGIC;
+        p_read : IN STD_LOGIC_VECTOR (15 downto 0);
+        p_read1 : IN STD_LOGIC_VECTOR (15 downto 0);
+        p_read2 : IN STD_LOGIC_VECTOR (15 downto 0);
+        p_read3 : IN STD_LOGIC_VECTOR (15 downto 0);
+        p_read4 : IN STD_LOGIC_VECTOR (15 downto 0);
+        p_read5 : IN STD_LOGIC_VECTOR (15 downto 0);
+        p_read6 : IN STD_LOGIC_VECTOR (15 downto 0);
+        p_read7 : IN STD_LOGIC_VECTOR (15 downto 0);
+        p_read8 : IN STD_LOGIC_VECTOR (15 downto 0);
+        p_read9 : IN STD_LOGIC_VECTOR (15 downto 0);
+        p_read10 : IN STD_LOGIC_VECTOR (15 downto 0);
+        p_read11 : IN STD_LOGIC_VECTOR (15 downto 0);
+        p_read12 : IN STD_LOGIC_VECTOR (15 downto 0);
+        p_read13 : IN STD_LOGIC_VECTOR (15 downto 0);
+        p_read14 : IN STD_LOGIC_VECTOR (15 downto 0);
+        p_read15 : IN STD_LOGIC_VECTOR (15 downto 0);
+        layer31_out_din : OUT STD_LOGIC_VECTOR (655 downto 0);
+        layer31_out_num_data_valid : IN STD_LOGIC_VECTOR (10 downto 0);
+        layer31_out_fifo_cap : IN STD_LOGIC_VECTOR (10 downto 0);
+        layer31_out_full_n : IN STD_LOGIC;
+        layer31_out_write : OUT STD_LOGIC );
+    end component;
+
+
+
+begin
+    grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s_fu_468 : component myproject_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s
+    port map (
+        ap_clk => ap_clk,
+        ap_rst => ap_rst,
+        ap_start => grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s_fu_468_ap_start,
+        ap_done => grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s_fu_468_ap_done,
+        ap_idle => grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s_fu_468_ap_idle,
+        ap_ready => grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s_fu_468_ap_ready,
+        p_read => trunc_ln58_reg_1057,
+        p_read1 => trunc_ln58_s_reg_1062,
+        p_read2 => trunc_ln58_240_reg_1067,
+        p_read3 => trunc_ln58_241_reg_1072,
+        p_read4 => trunc_ln58_242_reg_1077,
+        p_read5 => trunc_ln58_243_reg_1082,
+        p_read6 => trunc_ln58_244_reg_1087,
+        p_read7 => trunc_ln58_245_reg_1092,
+        p_read8 => trunc_ln58_246_reg_1097,
+        p_read9 => trunc_ln58_247_reg_1102,
+        p_read10 => trunc_ln58_248_reg_1107,
+        p_read11 => trunc_ln58_249_reg_1112,
+        p_read12 => trunc_ln58_250_reg_1117,
+        p_read13 => trunc_ln58_251_reg_1122,
+        p_read14 => trunc_ln58_252_reg_1127,
+        p_read15 => trunc_ln58_253_reg_1132,
+        layer31_out_din => grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s_fu_468_layer31_out_din,
+        layer31_out_num_data_valid => ap_const_lv11_0,
+        layer31_out_fifo_cap => ap_const_lv11_0,
+        layer31_out_full_n => layer31_out_full_n,
+        layer31_out_write => grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s_fu_468_layer31_out_write);
+
+
+
+
+
+    ap_CS_fsm_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_CS_fsm <= ap_ST_fsm_state1;
+            else
+                ap_CS_fsm <= ap_NS_fsm;
+            end if;
+        end if;
+    end process;
+
+
+    ap_done_reg_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                ap_done_reg <= ap_const_logic_0;
+            else
+                if ((ap_continue = ap_const_logic_1)) then 
+                    ap_done_reg <= ap_const_logic_0;
+                elsif (((ap_const_boolean_0 = ap_block_state2) and (icmp_ln52_fu_860_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+                    ap_done_reg <= ap_const_logic_1;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s_fu_468_ap_start_reg_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s_fu_468_ap_start_reg <= ap_const_logic_0;
+            else
+                if (((ap_const_boolean_0 = ap_block_state2_ignore_call19) and (icmp_ln52_fu_860_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+                    grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s_fu_468_ap_start_reg <= ap_const_logic_1;
+                elsif ((grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s_fu_468_ap_ready = ap_const_logic_1)) then 
+                    grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s_fu_468_ap_start_reg <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    start_once_reg_assign_proc : process(ap_clk)
+    begin
+        if (ap_clk'event and ap_clk =  '1') then
+            if (ap_rst = '1') then
+                start_once_reg <= ap_const_logic_0;
+            else
+                if (((real_start = ap_const_logic_1) and (internal_ap_ready = ap_const_logic_0))) then 
+                    start_once_reg <= ap_const_logic_1;
+                elsif ((internal_ap_ready = ap_const_logic_1)) then 
+                    start_once_reg <= ap_const_logic_0;
+                end if; 
+            end if;
+        end if;
+    end process;
+
+
+    indvar_flatten_fu_458_assign_proc : process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_state1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+                indvar_flatten_fu_458 <= ap_const_lv11_0;
+            elsif (((ap_const_boolean_0 = ap_block_state2) and (icmp_ln52_fu_860_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+                indvar_flatten_fu_458 <= add_ln52_fu_866_p2;
+            end if; 
+        end if;
+    end process;
+    process (ap_clk)
+    begin
+        if (ap_clk'event and ap_clk = '1') then
+            if (((ap_const_boolean_0 = ap_block_state2) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
+                trunc_ln58_240_reg_1067 <= layer57_out_dout(47 downto 32);
+                trunc_ln58_241_reg_1072 <= layer57_out_dout(63 downto 48);
+                trunc_ln58_242_reg_1077 <= layer57_out_dout(79 downto 64);
+                trunc_ln58_243_reg_1082 <= layer57_out_dout(95 downto 80);
+                trunc_ln58_244_reg_1087 <= layer57_out_dout(111 downto 96);
+                trunc_ln58_245_reg_1092 <= layer57_out_dout(127 downto 112);
+                trunc_ln58_246_reg_1097 <= layer57_out_dout(143 downto 128);
+                trunc_ln58_247_reg_1102 <= layer57_out_dout(159 downto 144);
+                trunc_ln58_248_reg_1107 <= layer57_out_dout(175 downto 160);
+                trunc_ln58_249_reg_1112 <= layer57_out_dout(191 downto 176);
+                trunc_ln58_250_reg_1117 <= layer57_out_dout(207 downto 192);
+                trunc_ln58_251_reg_1122 <= layer57_out_dout(223 downto 208);
+                trunc_ln58_252_reg_1127 <= layer57_out_dout(239 downto 224);
+                trunc_ln58_253_reg_1132 <= layer57_out_dout(255 downto 240);
+                trunc_ln58_reg_1057 <= trunc_ln58_fu_872_p1;
+                trunc_ln58_s_reg_1062 <= layer57_out_dout(31 downto 16);
+            end if;
+        end if;
+    end process;
+
+    ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_CS_fsm_state1, ap_CS_fsm_state2, icmp_ln52_fu_860_p2, ap_block_state2, grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s_fu_468_ap_done, ap_CS_fsm_state3, ap_block_state1)
+    begin
+        case ap_CS_fsm is
+            when ap_ST_fsm_state1 => 
+                if (((ap_const_boolean_0 = ap_block_state1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
+                    ap_NS_fsm <= ap_ST_fsm_state2;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state1;
+                end if;
+            when ap_ST_fsm_state2 => 
+                if (((ap_const_boolean_0 = ap_block_state2) and (icmp_ln52_fu_860_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
+                    ap_NS_fsm <= ap_ST_fsm_state1;
+                elsif (((ap_const_boolean_0 = ap_block_state2) and (icmp_ln52_fu_860_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
+                    ap_NS_fsm <= ap_ST_fsm_state3;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state2;
+                end if;
+            when ap_ST_fsm_state3 => 
+                if (((ap_const_logic_1 = ap_CS_fsm_state3) and (grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s_fu_468_ap_done = ap_const_logic_1))) then
+                    ap_NS_fsm <= ap_ST_fsm_state2;
+                else
+                    ap_NS_fsm <= ap_ST_fsm_state3;
+                end if;
+            when others =>  
+                ap_NS_fsm <= "XXX";
+        end case;
+    end process;
+    add_ln52_fu_866_p2 <= std_logic_vector(unsigned(indvar_flatten_fu_458) + unsigned(ap_const_lv11_1));
+    ap_CS_fsm_state1 <= ap_CS_fsm(0);
+    ap_CS_fsm_state2 <= ap_CS_fsm(1);
+    ap_CS_fsm_state3 <= ap_CS_fsm(2);
+
+    ap_ST_fsm_state1_blk_assign_proc : process(ap_block_state1)
+    begin
+        if ((ap_const_boolean_1 = ap_block_state1)) then 
+            ap_ST_fsm_state1_blk <= ap_const_logic_1;
+        else 
+            ap_ST_fsm_state1_blk <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_ST_fsm_state2_blk_assign_proc : process(ap_block_state2)
+    begin
+        if ((ap_const_boolean_1 = ap_block_state2)) then 
+            ap_ST_fsm_state2_blk <= ap_const_logic_1;
+        else 
+            ap_ST_fsm_state2_blk <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_ST_fsm_state3_blk_assign_proc : process(grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s_fu_468_ap_done)
+    begin
+        if ((grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s_fu_468_ap_done = ap_const_logic_0)) then 
+            ap_ST_fsm_state3_blk <= ap_const_logic_1;
+        else 
+            ap_ST_fsm_state3_blk <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    ap_block_state1_assign_proc : process(real_start, ap_done_reg)
+    begin
+                ap_block_state1 <= ((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
+    end process;
+
+
+    ap_block_state2_assign_proc : process(layer57_out_empty_n, icmp_ln52_fu_860_p2)
+    begin
+                ap_block_state2 <= ((icmp_ln52_fu_860_p2 = ap_const_lv1_0) and (layer57_out_empty_n = ap_const_logic_0));
+    end process;
+
+
+    ap_block_state2_ignore_call19_assign_proc : process(layer57_out_empty_n, icmp_ln52_fu_860_p2)
+    begin
+                ap_block_state2_ignore_call19 <= ((icmp_ln52_fu_860_p2 = ap_const_lv1_0) and (layer57_out_empty_n = ap_const_logic_0));
+    end process;
+
+
+    ap_done_assign_proc : process(ap_done_reg, ap_CS_fsm_state2, icmp_ln52_fu_860_p2, ap_block_state2)
+    begin
+        if (((ap_const_boolean_0 = ap_block_state2) and (icmp_ln52_fu_860_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+            ap_done <= ap_const_logic_1;
+        else 
+            ap_done <= ap_done_reg;
+        end if; 
+    end process;
+
+
+    ap_idle_assign_proc : process(real_start, ap_CS_fsm_state1)
+    begin
+        if (((real_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then 
+            ap_idle <= ap_const_logic_1;
+        else 
+            ap_idle <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    ap_ready <= internal_ap_ready;
+    grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s_fu_468_ap_start <= grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s_fu_468_ap_start_reg;
+    icmp_ln52_fu_860_p2 <= "1" when (indvar_flatten_fu_458 = ap_const_lv11_484) else "0";
+
+    internal_ap_ready_assign_proc : process(ap_CS_fsm_state2, icmp_ln52_fu_860_p2, ap_block_state2)
+    begin
+        if (((ap_const_boolean_0 = ap_block_state2) and (icmp_ln52_fu_860_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+            internal_ap_ready <= ap_const_logic_1;
+        else 
+            internal_ap_ready <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    layer31_out_din <= grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s_fu_468_layer31_out_din;
+
+    layer31_out_write_assign_proc : process(grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s_fu_468_layer31_out_write, ap_CS_fsm_state3)
+    begin
+        if ((ap_const_logic_1 = ap_CS_fsm_state3)) then 
+            layer31_out_write <= grp_compute_output_buffer_2d_array_array_ap_fixed_41_21_5_3_0_16u_config31_s_fu_468_layer31_out_write;
+        else 
+            layer31_out_write <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    layer57_out_blk_n_assign_proc : process(layer57_out_empty_n, ap_CS_fsm_state2, icmp_ln52_fu_860_p2)
+    begin
+        if (((icmp_ln52_fu_860_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+            layer57_out_blk_n <= layer57_out_empty_n;
+        else 
+            layer57_out_blk_n <= ap_const_logic_1;
+        end if; 
+    end process;
+
+    layer57_out_read <= layer57_out_read_local;
+
+    layer57_out_read_local_assign_proc : process(ap_CS_fsm_state2, icmp_ln52_fu_860_p2, ap_block_state2)
+    begin
+        if (((ap_const_boolean_0 = ap_block_state2) and (icmp_ln52_fu_860_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then 
+            layer57_out_read_local <= ap_const_logic_1;
+        else 
+            layer57_out_read_local <= ap_const_logic_0;
+        end if; 
+    end process;
+
+
+    real_start_assign_proc : process(ap_start, start_full_n, start_once_reg)
+    begin
+        if (((start_once_reg = ap_const_logic_0) and (start_full_n = ap_const_logic_0))) then 
+            real_start <= ap_const_logic_0;
+        else 
+            real_start <= ap_start;
+        end if; 
+    end process;
+
+    start_out <= real_start;
+
+    start_write_assign_proc : process(real_start, start_once_reg)
+    begin
+        if (((real_start = ap_const_logic_1) and (start_once_reg = ap_const_logic_0))) then 
+            start_write <= ap_const_logic_1;
+        else 
+            start_write <= ap_const_logic_0;
+        end if; 
+    end process;
+
+    trunc_ln58_fu_872_p1 <= layer57_out_dout(16 - 1 downto 0);
+end behav;