shailja
/

fine-tuned-codegen-6B-Verilog

Text Generation

Eval Results (legacy)

Model card Files Files and versions

fine-tuned-codegen-6B-Verilog

Commit History

Adding `safetensors` variant of this model

fbe1d37
verified

SFconvertbot commited on Apr 2, 2024

Create README.md

a3489e4

shailja commited on Aug 30, 2023

Create LICENCE

5900223

shailja commited on Feb 10, 2023

Upload fine-tuned-codegen-6B-1gpu.tar.zst

22eb0de

shailja commited on Nov 24, 2022

Upload fine-tuned-codegen-6B-1gpu.tar.zst

d4eb8af

shailja commited on Nov 16, 2022

Upload 3 files

a0106f3

shailja commited on Nov 7, 2022

Upload CodeGenForCausalLM

bd9ca6b

shailja commited on Sep 18, 2022

initial commit

16cca11

shailja commited on Sep 18, 2022