Commit ·
7ff4caf
1
Parent(s): f8862a3
debugging for app gradio verilog display issues
Browse files
app.py
CHANGED
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@@ -281,7 +281,7 @@ with gr.Blocks(title="DeepRAG for RTL (Model-Agnostic)") as demo:
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gr.Markdown("**Output**")
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out_code = gr.Code(
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label="Generated Verilog (copy-ready)",
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-
language="
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interactive=False,
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lines=28
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)
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gr.Markdown("**Output**")
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out_code = gr.Code(
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label="Generated Verilog (copy-ready)",
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+
language="text",
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interactive=False,
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lines=28
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)
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