| import fs from 'fs'; |
| import { ESP32 } from '../web/js/soc.js'; |
| import { Syms } from './sym.mjs'; |
| const romDir = new URL('../web/rom/', import.meta.url).pathname; |
| const soc = new ESP32({ slice: parseInt(process.env.SLICE || "256") }); |
| soc.loadRoms(fs.readFileSync(romDir + 'esp32-v3-rom.bin'), fs.readFileSync(romDir + 'esp32-v3-rom-app.bin')); |
| soc.setFlash(fs.readFileSync(process.argv[2])); soc.enablePsram(false); |
| soc.reset('power'); |
| const syms = new Syms(['/tmp/opencode/vgademo.syms', '/tmp/opencode/rom.syms']); |
| let logging = false; |
| for (const c of soc.cpus) { |
| const ti = c.takeInterrupt.bind(c); |
| c.takeInterrupt = function (pc) { const lv = this.pendingLevel(); const pend = (this.intPins | this.intSet) & this.intenable; if (logging && (pend & ((1 << 19) | (1 << 2)))) console.log(`cpu${this.id} irq level ${lv} pend ${(pend>>>0).toString(16)} at pc ${(pc>>>0).toString(16)} ${syms.name(pc)}`); return ti(pc); }; |
| } |
| const ow = soc.rtc.ulpWake.bind(soc.rtc); |
| soc.rtc.ulpWake = () => { if (logging) console.log('--- ulpWake at', (soc.timeNs/1e6).toFixed(2)); return ow(); }; |
| const orr = soc.rtc.read.bind(soc.rtc); |
| soc.rtc.read = (off) => { if (logging && off === 0x44) { const c = soc.cpus[soc.curCpu]; console.log(' INT_ST read by cpu', soc.curCpu, syms.name(c.pc), (soc.timeNs/1e6).toFixed(3)); } return orr(off); }; |
| const oc = soc.rtc.write.bind(soc.rtc); |
| soc.rtc.write = (off, v) => { if (logging && off === 0x48) console.log(' INT_CLR write', v.toString(16), 'cpu', soc.curCpu, syms.name(soc.cpus[soc.curCpu].pc), (soc.timeNs/1e6).toFixed(3)); return oc(off, v); }; |
| while (soc.timeNs < 3.49e9) soc.run(20000); |
| logging = true; soc.ps2.kbd.key('KeyH', true); |
| while (soc.timeNs < 3.53e9) soc.run(2000); |
|
|
