LoRa Car Radio Evaluation Board Test Report

Design Reference: AE104193-001 Rev V2

Revision: V0.1 – Draft

Prepared By: Aeronix Engineering

1775 West Hibiscus Blvd., Suite 200, Melbourne FL 32901

(321) 984-1671

AERONIX PROPRIETARY - COMPETITION SENSITIVE

Table of Contents

# Section Page
1 SCOPE 1
2 Referenced Documents 2
3 Test Execution and Recording 3
4 Procedure 4
A Test Datasheet 14

1. SCOPE

This test plan validates the LoRa Car Radio Evaluation Board (design reference AE104193-001 Rev V2) in accordance with the PCB Manual requirements. The plan covers:

  • Visual inspection
  • Electrical continuity/short-circuit checks
  • Power-rail verification
  • Functional verification of major subsystems (MCU, USB debug port, LoRa radio, external I/O header, power-monitoring)
  • Placeholder environmental-stress sequence

2. Referenced Documents

Ref No. Document Revision Page
2-1 PCB Manual – AE104193-001 V2 1-9
2-2 Component Datasheets (SX1276, NCP1117, LP2985-33, ATMEGA328P, etc.) latest –
2-3 IPC-610 Class 2 Visual-Inspection Standard 2023 –
2-4 IEC 60730-1 (Environmental Test Guidelines) 2022 –
2-5 Test Equipment Calibration Certificates – –

3. Test Execution and Recording

3.1 Datasheet Reporting

All measured values shall be recorded on the Test Datasheet (Appendix A). For each test case record:

  • Actual Result – numeric value or observation.
  • Pass/Fail (P/F) – "P" if within tolerance, "F" otherwise.

If a test does not apply to a particular board revision, mark N/A.

3.2 Test Equipment

Item # Equipment Model / Spec Calibration Due
1 DC Power Supply (programmable) Keysight E36313A, 0-5 V, 1 A 12 months
2 Digital Multimeter (continuity/voltage) Fluke 8845A 12 months
3 4-Channel Oscilloscope Tektronix MDO3014, 350 MHz 12 months
4 USB-to-UART Bridge FTDI FT232RL 12 months
5 JTAG / SWD Programmer Segger J-Link JTAG 12 months
6 USB 2.0 Host PC (Windows 10) – –
7 Temperature Chamber (optional) – –
8 X-Y Table for visual inspection – –
9 Magnification Lamp (≥ 30×) – –
10 ESD-safe workstation with wrist strap – –

4. Procedure

NOTE – The procedure must be executed in the order presented. A failure at any step requires corrective action and a re-run from the beginning of the procedure.

4.1 Visual Inspection

Test-ID Description Acceptance Criteria (Expected Result) Actual Result Pass/Fail
V-001 Verify that the board is clean, free of flux residues, and conforms to IPC-610 Class 2. No visible solder balls, splatter, or residues; surface free of scratches.

4.2 Electrical Continuity & Shorts

Test-ID Description Expected Result Actual Result Pass/Fail
C-001 Continuity from Barrel-Jack GND (J3-2) to Ground Pad TP2 and to All GND pins on the external I/O header. ≤ 0.1 Ω resistance (continuous).