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@@ -38,3 +38,6 @@ obj_dir/verilated.o filter=lfs diff=lfs merge=lfs -text
 obj_dir/verilated_vcd_c.o filter=lfs diff=lfs merge=lfs -text
 server/tasks/easy/01_inverter_semicolon/obj_dir/Vdesign filter=lfs diff=lfs merge=lfs -text
 server/tasks/easy/01_inverter_semicolon/obj_dir/verilated.o filter=lfs diff=lfs merge=lfs -text
+dist/openenv_chipforge-0.1.0-py3-none-any.whl filter=lfs diff=lfs merge=lfs -text
+server/tasks/hard/01_priority_encoder_latch/obj_dir/Vdesign filter=lfs diff=lfs merge=lfs -text
+server/tasks/hard/01_priority_encoder_latch/obj_dir/verilated.o filter=lfs diff=lfs merge=lfs -text

MANIFEST.in

@@ -0,0 +1 @@
+recursive-include server/tasks *

dist/openenv_chipforge-0.1.0-py3-none-any.whl

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:dfad2246acd7f6f7234746ac3ca9995cb8a1350f157d5e951ed697478fb8c58a
+size 491069

dist/openenv_chipforge-0.1.0.tar.gz

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:0f92238bfb2f8edd6bafb3bdb389455402760d7ff2e994a07267daa3e4e4c0f1
+size 456458

openenv_chipforge.egg-info/SOURCES.txt

@@ -1,3 +1,4 @@
+MANIFEST.in
 README.md
 __init__.py
 client.py
@@ -16,4 +17,103 @@ openenv_chipforge.egg-info/requires.txt
 openenv_chipforge.egg-info/top_level.txt
 server/__init__.py
 server/app.py
-server/chipforge_environment.py
+server/chipforge_environment.py
+server/tasks/easy/01_inverter_semicolon/design.v
+server/tasks/easy/01_inverter_semicolon/design_buggy.v
+server/tasks/easy/01_inverter_semicolon/design_golden.v
+server/tasks/easy/01_inverter_semicolon/task.json
+server/tasks/easy/01_inverter_semicolon/testbench.v
+server/tasks/easy/01_inverter_semicolon/obj_dir/Vdesign
+server/tasks/easy/01_inverter_semicolon/obj_dir/Vdesign.cpp
+server/tasks/easy/01_inverter_semicolon/obj_dir/Vdesign.h
+server/tasks/easy/01_inverter_semicolon/obj_dir/Vdesign.mk
+server/tasks/easy/01_inverter_semicolon/obj_dir/Vdesign__ALL.a
+server/tasks/easy/01_inverter_semicolon/obj_dir/Vdesign__ALL.cpp
+server/tasks/easy/01_inverter_semicolon/obj_dir/Vdesign__ALL.d
+server/tasks/easy/01_inverter_semicolon/obj_dir/Vdesign__ALL.o
+server/tasks/easy/01_inverter_semicolon/obj_dir/Vdesign__Syms.h
+server/tasks/easy/01_inverter_semicolon/obj_dir/Vdesign__Syms__Slow.cpp
+server/tasks/easy/01_inverter_semicolon/obj_dir/Vdesign___024root.h
+server/tasks/easy/01_inverter_semicolon/obj_dir/Vdesign___024root__0.cpp
+server/tasks/easy/01_inverter_semicolon/obj_dir/Vdesign___024root__0__Slow.cpp
+server/tasks/easy/01_inverter_semicolon/obj_dir/Vdesign___024root__Slow.cpp
+server/tasks/easy/01_inverter_semicolon/obj_dir/Vdesign__main.cpp
+server/tasks/easy/01_inverter_semicolon/obj_dir/Vdesign__pch.h
+server/tasks/easy/01_inverter_semicolon/obj_dir/Vdesign__ver.d
+server/tasks/easy/01_inverter_semicolon/obj_dir/Vdesign__verFiles.dat
+server/tasks/easy/01_inverter_semicolon/obj_dir/Vdesign_classes.mk
+server/tasks/easy/01_inverter_semicolon/obj_dir/verilated.d
+server/tasks/easy/01_inverter_semicolon/obj_dir/verilated.o
+server/tasks/easy/01_inverter_semicolon/obj_dir/verilated_threads.d
+server/tasks/easy/01_inverter_semicolon/obj_dir/verilated_threads.o
+server/tasks/easy/01_inverter_semicolon/obj_dir/verilated_timing.d
+server/tasks/easy/01_inverter_semicolon/obj_dir/verilated_timing.o
+server/tasks/easy/02_and_missing_paren/design_buggy.v
+server/tasks/easy/02_and_missing_paren/design_golden.v
+server/tasks/easy/02_and_missing_paren/task.json
+server/tasks/easy/02_and_missing_paren/testbench.v
+server/tasks/easy/03_write_testbench_from_prompt/design_buggy.v
+server/tasks/easy/03_write_testbench_from_prompt/task.json
+server/tasks/hard/01_priority_encoder_latch/design.v
+server/tasks/hard/01_priority_encoder_latch/design_buggy.v
+server/tasks/hard/01_priority_encoder_latch/design_golden.v
+server/tasks/hard/01_priority_encoder_latch/task.json
+server/tasks/hard/01_priority_encoder_latch/testbench.v
+server/tasks/hard/01_priority_encoder_latch/obj_dir/Vdesign
+server/tasks/hard/01_priority_encoder_latch/obj_dir/Vdesign.cpp
+server/tasks/hard/01_priority_encoder_latch/obj_dir/Vdesign.h
+server/tasks/hard/01_priority_encoder_latch/obj_dir/Vdesign.mk
+server/tasks/hard/01_priority_encoder_latch/obj_dir/Vdesign__ALL.a
+server/tasks/hard/01_priority_encoder_latch/obj_dir/Vdesign__ALL.cpp
+server/tasks/hard/01_priority_encoder_latch/obj_dir/Vdesign__ALL.d
+server/tasks/hard/01_priority_encoder_latch/obj_dir/Vdesign__ALL.o
+server/tasks/hard/01_priority_encoder_latch/obj_dir/Vdesign__Syms.h
+server/tasks/hard/01_priority_encoder_latch/obj_dir/Vdesign__Syms__Slow.cpp
+server/tasks/hard/01_priority_encoder_latch/obj_dir/Vdesign___024root.h
+server/tasks/hard/01_priority_encoder_latch/obj_dir/Vdesign___024root__0.cpp
+server/tasks/hard/01_priority_encoder_latch/obj_dir/Vdesign___024root__0__Slow.cpp
+server/tasks/hard/01_priority_encoder_latch/obj_dir/Vdesign___024root__Slow.cpp
+server/tasks/hard/01_priority_encoder_latch/obj_dir/Vdesign__main.cpp
+server/tasks/hard/01_priority_encoder_latch/obj_dir/Vdesign__pch.h
+server/tasks/hard/01_priority_encoder_latch/obj_dir/Vdesign__ver.d
+server/tasks/hard/01_priority_encoder_latch/obj_dir/Vdesign__verFiles.dat
+server/tasks/hard/01_priority_encoder_latch/obj_dir/Vdesign_classes.mk
+server/tasks/hard/01_priority_encoder_latch/obj_dir/verilated.d
+server/tasks/hard/01_priority_encoder_latch/obj_dir/verilated.o
+server/tasks/hard/01_priority_encoder_latch/obj_dir/verilated_threads.d
+server/tasks/hard/01_priority_encoder_latch/obj_dir/verilated_threads.o
+server/tasks/hard/01_priority_encoder_latch/obj_dir/verilated_timing.d
+server/tasks/hard/01_priority_encoder_latch/obj_dir/verilated_timing.o
+server/tasks/hard/02_alu_incomplete_case/design_buggy.v
+server/tasks/hard/02_alu_incomplete_case/design_golden.v
+server/tasks/hard/02_alu_incomplete_case/task.json
+server/tasks/hard/02_alu_incomplete_case/testbench.v
+server/tasks/medium/01_half_subtractor_logic/design_buggy.v
+server/tasks/medium/01_half_subtractor_logic/design_golden.v
+server/tasks/medium/01_half_subtractor_logic/task.json
+server/tasks/medium/01_half_subtractor_logic/testbench.v
+server/tasks/medium/02_decoder_logic/design_buggy.v
+server/tasks/medium/02_decoder_logic/design_golden.v
+server/tasks/medium/02_decoder_logic/task.json
+server/tasks/medium/02_decoder_logic/testbench.v
+server/tasks/medium/03_write_design_and_testbench_from_prompt/task.json
+server/tasks/task_easy_missing_semicolon/design_buggy.v
+server/tasks/task_easy_missing_semicolon/design_golden.v
+server/tasks/task_easy_missing_semicolon/task.json
+server/tasks/task_easy_missing_semicolon/testbench.v
+server/tasks/task_easy_syntax/design_buggy.v
+server/tasks/task_easy_syntax/design_golden.v
+server/tasks/task_easy_syntax/task.json
+server/tasks/task_easy_syntax/testbench.v
+server/tasks/task_hard_latch_inference/design_buggy.v
+server/tasks/task_hard_latch_inference/design_golden.v
+server/tasks/task_hard_latch_inference/task.json
+server/tasks/task_hard_latch_inference/testbench.v
+server/tasks/task_medium_logic_bug/design_buggy.v
+server/tasks/task_medium_logic_bug/design_golden.v
+server/tasks/task_medium_logic_bug/task.json
+server/tasks/task_medium_logic_bug/testbench.v
+server/tasks/task_medium_wrong_operator/design_buggy.v
+server/tasks/task_medium_wrong_operator/design_golden.v
+server/tasks/task_medium_wrong_operator/task.json
+server/tasks/task_medium_wrong_operator/testbench.v

server/tasks/hard/01_priority_encoder_latch/design.v

@@ -0,0 +1,207 @@
+module priority_encoder3 (
+    input req2,
+    input req1,
+    input req0,
+    output reg valid,
+    output reg [1:0] code
+);
+
+wire pad00;
+wire pad01;
+wire pad02;
+wire pad03;
+wire pad04;
+wire pad05;
+wire pad06;
+wire pad07;
+wire pad08;
+wire pad09;
+wire pad10;
+wire pad11;
+wire pad12;
+wire pad13;
+wire pad14;
+wire pad15;
+wire pad16;
+wire pad17;
+wire pad18;
+wire pad19;
+wire pad20;
+wire pad21;
+wire pad22;
+wire pad23;
+wire pad24;
+wire pad25;
+wire pad26;
+wire pad27;
+wire pad28;
+wire pad29;
+wire pad30;
+wire pad31;
+wire pad32;
+wire pad33;
+wire pad34;
+wire pad35;
+wire pad36;
+wire pad37;
+wire pad38;
+wire pad39;
+wire pad40;
+wire pad41;
+wire pad42;
+wire pad43;
+wire pad44;
+wire pad45;
+wire pad46;
+wire pad47;
+wire pad48;
+wire pad49;
+wire pad50;
+wire pad51;
+wire pad52;
+wire pad53;
+wire pad54;
+wire pad55;
+wire pad56;
+wire pad57;
+wire pad58;
+wire pad59;
+wire pad60;
+wire pad61;
+wire pad62;
+wire pad63;
+wire pad64;
+wire pad65;
+wire pad66;
+wire pad67;
+wire pad68;
+wire pad69;
+wire pad70;
+wire pad71;
+wire pad72;
+wire pad73;
+wire pad74;
+wire pad75;
+wire pad76;
+wire pad77;
+wire pad78;
+wire pad79;
+wire pad80;
+wire pad81;
+wire pad82;
+wire pad83;
+wire pad84;
+wire pad85;
+wire pad86;
+wire pad87;
+wire pad88;
+wire pad89;
+
+assign pad00 = req0;
+assign pad01 = pad00;
+assign pad02 = pad01;
+assign pad03 = pad02;
+assign pad04 = pad03;
+assign pad05 = pad04;
+assign pad06 = pad05;
+assign pad07 = pad06;
+assign pad08 = pad07;
+assign pad09 = pad08;
+assign pad10 = pad09;
+assign pad11 = pad10;
+assign pad12 = pad11;
+assign pad13 = pad12;
+assign pad14 = pad13;
+assign pad15 = pad14;
+assign pad16 = pad15;
+assign pad17 = pad16;
+assign pad18 = pad17;
+assign pad19 = pad18;
+assign pad20 = pad19;
+assign pad21 = pad20;
+assign pad22 = pad21;
+assign pad23 = pad22;
+assign pad24 = pad23;
+assign pad25 = pad24;
+assign pad26 = pad25;
+assign pad27 = pad26;
+assign pad28 = pad27;
+assign pad29 = pad28;
+assign pad30 = pad29;
+assign pad31 = pad30;
+assign pad32 = pad31;
+assign pad33 = pad32;
+assign pad34 = pad33;
+assign pad35 = pad34;
+assign pad36 = pad35;
+assign pad37 = pad36;
+assign pad38 = pad37;
+assign pad39 = pad38;
+assign pad40 = pad39;
+assign pad41 = pad40;
+assign pad42 = pad41;
+assign pad43 = pad42;
+assign pad44 = pad43;
+assign pad45 = pad44;
+assign pad46 = pad45;
+assign pad47 = pad46;
+assign pad48 = pad47;
+assign pad49 = pad48;
+assign pad50 = pad49;
+assign pad51 = pad50;
+assign pad52 = pad51;
+assign pad53 = pad52;
+assign pad54 = pad53;
+assign pad55 = pad54;
+assign pad56 = pad55;
+assign pad57 = pad56;
+assign pad58 = pad57;
+assign pad59 = pad58;
+assign pad60 = pad59;
+assign pad61 = pad60;
+assign pad62 = pad61;
+assign pad63 = pad62;
+assign pad64 = pad63;
+assign pad65 = pad64;
+assign pad66 = pad65;
+assign pad67 = pad66;
+assign pad68 = pad67;
+assign pad69 = pad68;
+assign pad70 = pad69;
+assign pad71 = pad70;
+assign pad72 = pad71;
+assign pad73 = pad72;
+assign pad74 = pad73;
+assign pad75 = pad74;
+assign pad76 = pad75;
+assign pad77 = pad76;
+assign pad78 = pad77;
+assign pad79 = pad78;
+assign pad80 = pad79;
+assign pad81 = pad80;
+assign pad82 = pad81;
+assign pad83 = pad82;
+assign pad84 = pad83;
+assign pad85 = pad84;
+assign pad86 = pad85;
+assign pad87 = pad86;
+assign pad88 = pad87;
+assign pad89 = pad88;
+
+always @(*) begin
+    valid = 1'b0;
+    code = 2'b00;
+
+    if (req2) begin
+        valid = 1'b1;
+        code = 2'b10;
+    end else if (req1) begin
+        valid = 1'b1;
+        code = 2'b01;
+    end else if (req0) begin
+        valid = 1'b1;
+        code = 2'b00;
+    end
+end
+
+endmodule

server/tasks/hard/01_priority_encoder_latch/obj_dir/Vdesign

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:cf420ed0f34211a52e32fbf542bbd288d958af45b713a18bbef76b751b085960
+size 274672

server/tasks/hard/01_priority_encoder_latch/obj_dir/Vdesign.cpp

@@ -0,0 +1,94 @@
+// Verilated -*- C++ -*-
+// DESCRIPTION: Verilator output: Model implementation (design independent parts)
+
+#include "Vdesign__pch.h"
+
+//============================================================
+// Constructors
+
+Vdesign::Vdesign(VerilatedContext* _vcontextp__, const char* _vcname__)
+    : VerilatedModel{*_vcontextp__}
+    , vlSymsp{new Vdesign__Syms(contextp(), _vcname__, this)}
+    , rootp{&(vlSymsp->TOP)}
+{
+    // Register model with the context
+    contextp()->addModel(this);
+}
+
+Vdesign::Vdesign(const char* _vcname__)
+    : Vdesign(Verilated::threadContextp(), _vcname__)
+{
+}
+
+//============================================================
+// Destructor
+
+Vdesign::~Vdesign() {
+    delete vlSymsp;
+}
+
+//============================================================
+// Evaluation function
+
+#ifdef VL_DEBUG
+void Vdesign___024root___eval_debug_assertions(Vdesign___024root* vlSelf);
+#endif  // VL_DEBUG
+void Vdesign___024root___eval_static(Vdesign___024root* vlSelf);
+void Vdesign___024root___eval_initial(Vdesign___024root* vlSelf);
+void Vdesign___024root___eval_settle(Vdesign___024root* vlSelf);
+void Vdesign___024root___eval(Vdesign___024root* vlSelf);
+
+void Vdesign::eval_step() {
+    VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate Vdesign::eval_step\n"); );
+#ifdef VL_DEBUG
+    // Debug assertions
+    Vdesign___024root___eval_debug_assertions(&(vlSymsp->TOP));
+#endif  // VL_DEBUG
+    vlSymsp->__Vm_deleter.deleteAll();
+    if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) {
+        VL_DEBUG_IF(VL_DBG_MSGF("+ Initial\n"););
+        Vdesign___024root___eval_static(&(vlSymsp->TOP));
+        Vdesign___024root___eval_initial(&(vlSymsp->TOP));
+        Vdesign___024root___eval_settle(&(vlSymsp->TOP));
+        vlSymsp->__Vm_didInit = true;
+    }
+    VL_DEBUG_IF(VL_DBG_MSGF("+ Eval\n"););
+    Vdesign___024root___eval(&(vlSymsp->TOP));
+    // Evaluate cleanup
+    Verilated::endOfEval(vlSymsp->__Vm_evalMsgQp);
+}
+
+//============================================================
+// Events and timing
+bool Vdesign::eventsPending() { return !vlSymsp->TOP.__VdlySched.empty() && !contextp()->gotFinish(); }
+
+uint64_t Vdesign::nextTimeSlot() { return vlSymsp->TOP.__VdlySched.nextTimeSlot(); }
+
+//============================================================
+// Utilities
+
+const char* Vdesign::name() const {
+    return vlSymsp->name();
+}
+
+//============================================================
+// Invoke final blocks
+
+void Vdesign___024root___eval_final(Vdesign___024root* vlSelf);
+
+VL_ATTR_COLD void Vdesign::final() {
+    contextp()->executingFinal(true);
+    Vdesign___024root___eval_final(&(vlSymsp->TOP));
+    contextp()->executingFinal(false);
+}
+
+//============================================================
+// Implementations of abstract methods from VerilatedModel
+
+const char* Vdesign::hierName() const { return vlSymsp->name(); }
+const char* Vdesign::modelName() const { return "Vdesign"; }
+unsigned Vdesign::threads() const { return 1; }
+void Vdesign::prepareClone() const { contextp()->prepareClone(); }
+void Vdesign::atClone() const {
+    contextp()->threadPoolpOnClone();
+}

server/tasks/hard/01_priority_encoder_latch/obj_dir/Vdesign.h

@@ -0,0 +1,87 @@
+// Verilated -*- C++ -*-
+// DESCRIPTION: Verilator output: Primary model header
+//
+// This header should be included by all source files instantiating the design.
+// The class here is then constructed to instantiate the design.
+// See the Verilator manual for examples.
+
+#ifndef VERILATED_VDESIGN_H_
+#define VERILATED_VDESIGN_H_  // guard
+
+#include "verilated.h"
+
+class Vdesign__Syms;
+class Vdesign___024root;
+
+// This class is the main interface to the Verilated model
+class alignas(VL_CACHE_LINE_BYTES) Vdesign VL_NOT_FINAL : public VerilatedModel {
+  private:
+    // Symbol table holding complete model state (owned by this class)
+    Vdesign__Syms* const vlSymsp;
+
+  public:
+
+    // CONSTEXPR CAPABILITIES
+    // Verilated with --trace?
+    static constexpr bool traceCapable = false;
+
+    // PORTS
+    // The application code writes and reads these signals to
+    // propagate new values into/out from the Verilated model.
+
+    // CELLS
+    // Public to allow access to /* verilator public */ items.
+    // Otherwise the application code can consider these internals.
+
+    // Root instance pointer to allow access to model internals,
+    // including inlined /* verilator public_flat_* */ items.
+    Vdesign___024root* const rootp;
+
+    // CONSTRUCTORS
+    /// Construct the model; called by application code
+    /// If contextp is null, then the model will use the default global context
+    /// If name is "", then makes a wrapper with a
+    /// single model invisible with respect to DPI scope names.
+    explicit Vdesign(VerilatedContext* contextp, const char* name = "TOP");
+    explicit Vdesign(const char* name = "TOP");
+    /// Destroy the model; called (often implicitly) by application code
+    virtual ~Vdesign();
+  private:
+    VL_UNCOPYABLE(Vdesign);  ///< Copying not allowed
+
+  public:
+    // API METHODS
+    /// Evaluate the model.  Application must call when inputs change.
+    void eval() { eval_step(); }
+    /// Evaluate when calling multiple units/models per time step.
+    void eval_step();
+    /// Evaluate at end of a timestep for tracing, when using eval_step().
+    /// Application must call after all eval() and before time changes.
+    void eval_end_step() {}
+    /// Simulation complete, run final blocks.  Application must call on completion.
+    void final();
+    /// Are there scheduled events to handle?
+    bool eventsPending();
+    /// Returns time at next time slot. Aborts if !eventsPending()
+    uint64_t nextTimeSlot();
+    /// Trace signals in the model; called by application code
+    void trace(VerilatedTraceBaseC* tfp, int levels, int options = 0) { contextp()->trace(tfp, levels, options); }
+    /// Retrieve name of this model instance (as passed to constructor).
+    const char* name() const;
+
+    // Abstract methods from VerilatedModel
+    const char* hierName() const override final;
+    const char* modelName() const override final;
+    unsigned threads() const override final;
+    /// Prepare for cloning the model at the process level (e.g. fork in Linux)
+    /// Release necessary resources. Called before cloning.
+    void prepareClone() const;
+    /// Re-init after cloning the model at the process level (e.g. fork in Linux)
+    /// Re-allocate necessary resources. Called after cloning.
+    void atClone() const;
+  private:
+    // Internal functions - trace registration
+    void traceBaseModel(VerilatedTraceBaseC* tfp, int levels, int options);
+};
+
+#endif  // guard

server/tasks/hard/01_priority_encoder_latch/obj_dir/Vdesign.mk

@@ -0,0 +1,66 @@
+# Verilated -*- Makefile -*-
+# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable
+#
+# Execute this makefile from the object directory:
+#    make -f Vdesign.mk
+
+default: Vdesign
+
+### Constants...
+# Perl executable (from $PERL, defaults to 'perl' if not set)
+PERL = perl
+# Python3 executable (from $PYTHON3, defaults to 'python3' if not set)
+PYTHON3 = python3
+# Path to Verilator kit (from $VERILATOR_ROOT)
+VERILATOR_ROOT = /opt/oss-cad-suite/share/verilator
+# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
+SYSTEMC_INCLUDE ?=
+# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)
+SYSTEMC_LIBDIR ?=
+
+### Switches...
+# C++ code coverage  0/1 (from --prof-c)
+VM_PROFC = 0
+# SystemC output mode?  0/1 (from --sc)
+VM_SC = 0
+# Legacy or SystemC output mode?  0/1 (from --sc)
+VM_SP_OR_SC = $(VM_SC)
+# Deprecated
+VM_PCLI = 1
+# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH)
+VM_SC_TARGET_ARCH = linux
+
+### Vars...
+# Design prefix (from --prefix)
+VM_PREFIX = Vdesign
+# Module prefix (from --prefix)
+VM_MODPREFIX = Vdesign
+# User CFLAGS (from -CFLAGS on Verilator command line)
+VM_USER_CFLAGS = \
+  -DVL_TIME_CONTEXT \
+
+# User LDLIBS (from -LDFLAGS on Verilator command line)
+VM_USER_LDLIBS = \
+
+# User .cpp files (from .cpp's on Verilator command line)
+VM_USER_CLASSES = \
+
+# User .cpp directories (from .cpp's on Verilator command line)
+VM_USER_DIR = \
+  .. \
+
+### Default rules...
+# Include list of all generated classes
+include Vdesign_classes.mk
+# Include global rules
+include $(VERILATOR_ROOT)/include/verilated.mk
+
+### Executable rules... (from --exe)
+VPATH += $(VM_USER_DIR)
+
+
+### Link rules... (from --exe)
+Vdesign: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a
+	$(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) $(LIBS) $(SC_LIBS) -o $@
+
+# Verilated -*- Makefile -*-

server/tasks/hard/01_priority_encoder_latch/obj_dir/Vdesign__ALL.cpp

@@ -0,0 +1,8 @@
+// DESCRIPTION: Generated by verilator_includer via makefile
+#define VL_INCLUDE_OPT include
+#include "Vdesign.cpp"
+#include "Vdesign___024root__0.cpp"
+#include "Vdesign__main.cpp"
+#include "Vdesign___024root__Slow.cpp"
+#include "Vdesign___024root__0__Slow.cpp"
+#include "Vdesign__Syms__Slow.cpp"

server/tasks/hard/01_priority_encoder_latch/obj_dir/Vdesign__ALL.d

@@ -0,0 +1,11 @@
+Vdesign__ALL.o: Vdesign__ALL.cpp Vdesign.cpp Vdesign__pch.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_config.h \
+ /opt/oss-cad-suite/share/verilator/include/verilatedos.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_types.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_funcs.h \
+ Vdesign__Syms.h Vdesign.h Vdesign___024root.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_timing.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated.h \
+ Vdesign___024root__0.cpp Vdesign__main.cpp Vdesign___024root__Slow.cpp \
+ Vdesign___024root__0__Slow.cpp Vdesign__Syms__Slow.cpp

server/tasks/hard/01_priority_encoder_latch/obj_dir/Vdesign__Syms.h

@@ -0,0 +1,38 @@
+// Verilated -*- C++ -*-
+// DESCRIPTION: Verilator output: Symbol table internal header
+//
+// Internal details; most calling programs do not need this header,
+// unless using verilator public meta comments.
+
+#ifndef VERILATED_VDESIGN__SYMS_H_
+#define VERILATED_VDESIGN__SYMS_H_  // guard
+
+#include "verilated.h"
+
+// INCLUDE MODEL CLASS
+
+#include "Vdesign.h"
+
+// INCLUDE MODULE CLASSES
+#include "Vdesign___024root.h"
+
+// SYMS CLASS (contains all model state)
+class alignas(VL_CACHE_LINE_BYTES) Vdesign__Syms final : public VerilatedSyms {
+  public:
+    // INTERNAL STATE
+    Vdesign* const __Vm_modelp;
+    VlDeleter __Vm_deleter;
+    bool __Vm_didInit = false;
+
+    // MODULE INSTANCE STATE
+    Vdesign___024root              TOP;
+
+    // CONSTRUCTORS
+    Vdesign__Syms(VerilatedContext* contextp, const char* namep, Vdesign* modelp);
+    ~Vdesign__Syms();
+
+    // METHODS
+    const char* name() const { return TOP.vlNamep; }
+};
+
+#endif  // guard

server/tasks/hard/01_priority_encoder_latch/obj_dir/Vdesign__Syms__Slow.cpp

@@ -0,0 +1,28 @@
+// Verilated -*- C++ -*-
+// DESCRIPTION: Verilator output: Symbol table implementation internals
+
+#include "Vdesign__pch.h"
+
+Vdesign__Syms::Vdesign__Syms(VerilatedContext* contextp, const char* namep, Vdesign* modelp)
+    : VerilatedSyms{contextp}
+    // Setup internal state of the Syms class
+    , __Vm_modelp{modelp}
+    // Setup top module instance
+    , TOP{this, namep}
+{
+    // Check resources
+    Verilated::stackCheck(256);
+    // Setup sub module instances
+    // Configure time unit / time precision
+    _vm_contextp__->timeunit(-9);
+    _vm_contextp__->timeprecision(-12);
+    // Setup each module's pointers to their submodules
+    // Setup each module's pointer back to symbol table (for public functions)
+    TOP.__Vconfigure(true);
+    // Setup scopes
+}
+
+Vdesign__Syms::~Vdesign__Syms() {
+    // Tear down scopes
+    // Tear down sub module instances
+}

server/tasks/hard/01_priority_encoder_latch/obj_dir/Vdesign___024root.h

@@ -0,0 +1,51 @@
+// Verilated -*- C++ -*-
+// DESCRIPTION: Verilator output: Design internal header
+// See Vdesign.h for the primary calling header
+
+#ifndef VERILATED_VDESIGN___024ROOT_H_
+#define VERILATED_VDESIGN___024ROOT_H_  // guard
+
+#include "verilated.h"
+#include "verilated_timing.h"
+
+
+class Vdesign__Syms;
+
+class alignas(VL_CACHE_LINE_BYTES) Vdesign___024root final {
+  public:
+
+    // DESIGN SPECIFIC STATE
+    CData/*0:0*/ tb_priority_encoder3__DOT__req2;
+    CData/*0:0*/ tb_priority_encoder3__DOT__req1;
+    CData/*0:0*/ tb_priority_encoder3__DOT__req0;
+    CData/*0:0*/ tb_priority_encoder3__DOT__valid;
+    CData/*1:0*/ tb_priority_encoder3__DOT__code;
+    CData/*0:0*/ __VstlFirstIteration;
+    CData/*0:0*/ __VstlPhaseResult;
+    CData/*0:0*/ __VactPhaseResult;
+    CData/*0:0*/ __VinactPhaseResult;
+    CData/*0:0*/ __VnbaPhaseResult;
+    IData/*31:0*/ __VactIterCount;
+    IData/*31:0*/ __VinactIterCount;
+    IData/*31:0*/ __Vi;
+    VlUnpacked<QData/*63:0*/, 1> __VstlTriggered;
+    VlUnpacked<QData/*63:0*/, 1> __VactTriggered;
+    VlUnpacked<QData/*63:0*/, 1> __VactTriggeredAcc;
+    VlUnpacked<QData/*63:0*/, 1> __VnbaTriggered;
+    VlDelayScheduler __VdlySched;
+
+    // INTERNAL VARIABLES
+    Vdesign__Syms* vlSymsp;
+    const char* vlNamep;
+
+    // CONSTRUCTORS
+    Vdesign___024root(Vdesign__Syms* symsp, const char* namep);
+    ~Vdesign___024root();
+    VL_UNCOPYABLE(Vdesign___024root);
+
+    // INTERNAL METHODS
+    void __Vconfigure(bool first);
+};
+
+
+#endif  // guard

server/tasks/hard/01_priority_encoder_latch/obj_dir/Vdesign___024root__0.cpp

@@ -0,0 +1,361 @@
+// Verilated -*- C++ -*-
+// DESCRIPTION: Verilator output: Design implementation internals
+// See Vdesign.h for the primary calling header
+
+#include "Vdesign__pch.h"
+
+VlCoroutine Vdesign___024root___eval_initial__TOP__Vtiming__0(Vdesign___024root* vlSelf);
+
+void Vdesign___024root___eval_initial(Vdesign___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vdesign___024root___eval_initial\n"); );
+    Vdesign__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Body
+    Vdesign___024root___eval_initial__TOP__Vtiming__0(vlSelf);
+}
+
+VlCoroutine Vdesign___024root___eval_initial__TOP__Vtiming__0(Vdesign___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vdesign___024root___eval_initial__TOP__Vtiming__0\n"); );
+    Vdesign__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Body
+    VL_WRITEF_NX("req2 req1 req0 | valid code\n-------------------------\n",0);
+    vlSelfRef.tb_priority_encoder3__DOT__req2 = 0U;
+    vlSelfRef.tb_priority_encoder3__DOT__req1 = 0U;
+    vlSelfRef.tb_priority_encoder3__DOT__req0 = 0U;
+    co_await vlSelfRef.__VdlySched.delay(0x0000000000002710ULL, 
+                                         nullptr, "testbench.v", 
+                                         23);
+    VL_WRITEF_NX(" %b    %b    %b  |   %b    %b%b\n",6
+                 , '#',1,vlSelfRef.tb_priority_encoder3__DOT__req2
+                 , '#',1,(IData)(vlSelfRef.tb_priority_encoder3__DOT__req1)
+                 , '#',1,vlSelfRef.tb_priority_encoder3__DOT__req0
+                 , '#',1,(IData)(vlSelfRef.tb_priority_encoder3__DOT__valid)
+                 , '#',1,(1U & ((IData)(vlSelfRef.tb_priority_encoder3__DOT__code) 
+                                >> 1U)), '#',1,(1U 
+                                                & (IData)(vlSelfRef.tb_priority_encoder3__DOT__code)));
+    vlSelfRef.tb_priority_encoder3__DOT__req2 = 0U;
+    vlSelfRef.tb_priority_encoder3__DOT__req1 = 0U;
+    vlSelfRef.tb_priority_encoder3__DOT__req0 = 1U;
+    co_await vlSelfRef.__VdlySched.delay(0x0000000000002710ULL, 
+                                         nullptr, "testbench.v", 
+                                         24);
+    VL_WRITEF_NX(" %b    %b    %b  |   %b    %b%b\n",6
+                 , '#',1,vlSelfRef.tb_priority_encoder3__DOT__req2
+                 , '#',1,(IData)(vlSelfRef.tb_priority_encoder3__DOT__req1)
+                 , '#',1,vlSelfRef.tb_priority_encoder3__DOT__req0
+                 , '#',1,(IData)(vlSelfRef.tb_priority_encoder3__DOT__valid)
+                 , '#',1,(1U & ((IData)(vlSelfRef.tb_priority_encoder3__DOT__code) 
+                                >> 1U)), '#',1,(1U 
+                                                & (IData)(vlSelfRef.tb_priority_encoder3__DOT__code)));
+    vlSelfRef.tb_priority_encoder3__DOT__req2 = 0U;
+    vlSelfRef.tb_priority_encoder3__DOT__req1 = 1U;
+    vlSelfRef.tb_priority_encoder3__DOT__req0 = 0U;
+    co_await vlSelfRef.__VdlySched.delay(0x0000000000002710ULL, 
+                                         nullptr, "testbench.v", 
+                                         25);
+    VL_WRITEF_NX(" %b    %b    %b  |   %b    %b%b\n",6
+                 , '#',1,vlSelfRef.tb_priority_encoder3__DOT__req2
+                 , '#',1,(IData)(vlSelfRef.tb_priority_encoder3__DOT__req1)
+                 , '#',1,vlSelfRef.tb_priority_encoder3__DOT__req0
+                 , '#',1,(IData)(vlSelfRef.tb_priority_encoder3__DOT__valid)
+                 , '#',1,(1U & ((IData)(vlSelfRef.tb_priority_encoder3__DOT__code) 
+                                >> 1U)), '#',1,(1U 
+                                                & (IData)(vlSelfRef.tb_priority_encoder3__DOT__code)));
+    vlSelfRef.tb_priority_encoder3__DOT__req2 = 0U;
+    vlSelfRef.tb_priority_encoder3__DOT__req1 = 1U;
+    vlSelfRef.tb_priority_encoder3__DOT__req0 = 1U;
+    co_await vlSelfRef.__VdlySched.delay(0x0000000000002710ULL, 
+                                         nullptr, "testbench.v", 
+                                         26);
+    VL_WRITEF_NX(" %b    %b    %b  |   %b    %b%b\n",6
+                 , '#',1,vlSelfRef.tb_priority_encoder3__DOT__req2
+                 , '#',1,(IData)(vlSelfRef.tb_priority_encoder3__DOT__req1)
+                 , '#',1,vlSelfRef.tb_priority_encoder3__DOT__req0
+                 , '#',1,(IData)(vlSelfRef.tb_priority_encoder3__DOT__valid)
+                 , '#',1,(1U & ((IData)(vlSelfRef.tb_priority_encoder3__DOT__code) 
+                                >> 1U)), '#',1,(1U 
+                                                & (IData)(vlSelfRef.tb_priority_encoder3__DOT__code)));
+    vlSelfRef.tb_priority_encoder3__DOT__req2 = 1U;
+    vlSelfRef.tb_priority_encoder3__DOT__req1 = 0U;
+    vlSelfRef.tb_priority_encoder3__DOT__req0 = 0U;
+    co_await vlSelfRef.__VdlySched.delay(0x0000000000002710ULL, 
+                                         nullptr, "testbench.v", 
+                                         27);
+    VL_WRITEF_NX(" %b    %b    %b  |   %b    %b%b\n",6
+                 , '#',1,vlSelfRef.tb_priority_encoder3__DOT__req2
+                 , '#',1,(IData)(vlSelfRef.tb_priority_encoder3__DOT__req1)
+                 , '#',1,vlSelfRef.tb_priority_encoder3__DOT__req0
+                 , '#',1,(IData)(vlSelfRef.tb_priority_encoder3__DOT__valid)
+                 , '#',1,(1U & ((IData)(vlSelfRef.tb_priority_encoder3__DOT__code) 
+                                >> 1U)), '#',1,(1U 
+                                                & (IData)(vlSelfRef.tb_priority_encoder3__DOT__code)));
+    vlSelfRef.tb_priority_encoder3__DOT__req2 = 1U;
+    vlSelfRef.tb_priority_encoder3__DOT__req1 = 0U;
+    vlSelfRef.tb_priority_encoder3__DOT__req0 = 1U;
+    co_await vlSelfRef.__VdlySched.delay(0x0000000000002710ULL, 
+                                         nullptr, "testbench.v", 
+                                         28);
+    VL_WRITEF_NX(" %b    %b    %b  |   %b    %b%b\n",6
+                 , '#',1,vlSelfRef.tb_priority_encoder3__DOT__req2
+                 , '#',1,(IData)(vlSelfRef.tb_priority_encoder3__DOT__req1)
+                 , '#',1,vlSelfRef.tb_priority_encoder3__DOT__req0
+                 , '#',1,(IData)(vlSelfRef.tb_priority_encoder3__DOT__valid)
+                 , '#',1,(1U & ((IData)(vlSelfRef.tb_priority_encoder3__DOT__code) 
+                                >> 1U)), '#',1,(1U 
+                                                & (IData)(vlSelfRef.tb_priority_encoder3__DOT__code)));
+    vlSelfRef.tb_priority_encoder3__DOT__req2 = 1U;
+    vlSelfRef.tb_priority_encoder3__DOT__req1 = 1U;
+    vlSelfRef.tb_priority_encoder3__DOT__req0 = 0U;
+    co_await vlSelfRef.__VdlySched.delay(0x0000000000002710ULL, 
+                                         nullptr, "testbench.v", 
+                                         29);
+    VL_WRITEF_NX(" %b    %b    %b  |   %b    %b%b\n",6
+                 , '#',1,vlSelfRef.tb_priority_encoder3__DOT__req2
+                 , '#',1,(IData)(vlSelfRef.tb_priority_encoder3__DOT__req1)
+                 , '#',1,vlSelfRef.tb_priority_encoder3__DOT__req0
+                 , '#',1,(IData)(vlSelfRef.tb_priority_encoder3__DOT__valid)
+                 , '#',1,(1U & ((IData)(vlSelfRef.tb_priority_encoder3__DOT__code) 
+                                >> 1U)), '#',1,(1U 
+                                                & (IData)(vlSelfRef.tb_priority_encoder3__DOT__code)));
+    vlSelfRef.tb_priority_encoder3__DOT__req2 = 1U;
+    vlSelfRef.tb_priority_encoder3__DOT__req1 = 1U;
+    vlSelfRef.tb_priority_encoder3__DOT__req0 = 1U;
+    co_await vlSelfRef.__VdlySched.delay(0x0000000000002710ULL, 
+                                         nullptr, "testbench.v", 
+                                         30);
+    VL_WRITEF_NX(" %b    %b    %b  |   %b    %b%b\n",6
+                 , '#',1,vlSelfRef.tb_priority_encoder3__DOT__req2
+                 , '#',1,(IData)(vlSelfRef.tb_priority_encoder3__DOT__req1)
+                 , '#',1,vlSelfRef.tb_priority_encoder3__DOT__req0
+                 , '#',1,(IData)(vlSelfRef.tb_priority_encoder3__DOT__valid)
+                 , '#',1,(1U & ((IData)(vlSelfRef.tb_priority_encoder3__DOT__code) 
+                                >> 1U)), '#',1,(1U 
+                                                & (IData)(vlSelfRef.tb_priority_encoder3__DOT__code)));
+    VL_FINISH_MT("testbench.v", 32, "");
+    co_return;
+}
+
+void Vdesign___024root___eval_triggers_vec__act(Vdesign___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vdesign___024root___eval_triggers_vec__act\n"); );
+    Vdesign__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Body
+    vlSelfRef.__VactTriggered[0U] = (QData)((IData)(vlSelfRef.__VdlySched.awaitingCurrentTime()));
+}
+
+bool Vdesign___024root___trigger_anySet__act(const VlUnpacked<QData/*63:0*/, 1> &in) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vdesign___024root___trigger_anySet__act\n"); );
+    // Locals
+    IData/*31:0*/ n;
+    // Body
+    n = 0U;
+    do {
+        if (in[n]) {
+            return (1U);
+        }
+        n = ((IData)(1U) + n);
+    } while ((1U > n));
+    return (0U);
+}
+
+void Vdesign___024root___act_sequent__TOP__0(Vdesign___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vdesign___024root___act_sequent__TOP__0\n"); );
+    Vdesign__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Body
+    vlSelfRef.tb_priority_encoder3__DOT__valid = 0U;
+    vlSelfRef.tb_priority_encoder3__DOT__code = 0U;
+    if (vlSelfRef.tb_priority_encoder3__DOT__req2) {
+        vlSelfRef.tb_priority_encoder3__DOT__valid = 1U;
+        vlSelfRef.tb_priority_encoder3__DOT__code = 2U;
+    } else if (vlSelfRef.tb_priority_encoder3__DOT__req1) {
+        vlSelfRef.tb_priority_encoder3__DOT__valid = 1U;
+        vlSelfRef.tb_priority_encoder3__DOT__code = 1U;
+    } else if (vlSelfRef.tb_priority_encoder3__DOT__req0) {
+        vlSelfRef.tb_priority_encoder3__DOT__valid = 1U;
+        vlSelfRef.tb_priority_encoder3__DOT__code = 0U;
+    }
+}
+
+void Vdesign___024root___eval_act(Vdesign___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vdesign___024root___eval_act\n"); );
+    Vdesign__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Body
+    if ((1ULL & vlSelfRef.__VactTriggered[0U])) {
+        vlSelfRef.tb_priority_encoder3__DOT__valid = 0U;
+        vlSelfRef.tb_priority_encoder3__DOT__code = 0U;
+        if (vlSelfRef.tb_priority_encoder3__DOT__req2) {
+            vlSelfRef.tb_priority_encoder3__DOT__valid = 1U;
+            vlSelfRef.tb_priority_encoder3__DOT__code = 2U;
+        } else if (vlSelfRef.tb_priority_encoder3__DOT__req1) {
+            vlSelfRef.tb_priority_encoder3__DOT__valid = 1U;
+            vlSelfRef.tb_priority_encoder3__DOT__code = 1U;
+        } else if (vlSelfRef.tb_priority_encoder3__DOT__req0) {
+            vlSelfRef.tb_priority_encoder3__DOT__valid = 1U;
+            vlSelfRef.tb_priority_encoder3__DOT__code = 0U;
+        }
+    }
+}
+
+void Vdesign___024root___eval_nba(Vdesign___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vdesign___024root___eval_nba\n"); );
+    Vdesign__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Body
+    if ((1ULL & vlSelfRef.__VnbaTriggered[0U])) {
+        vlSelfRef.tb_priority_encoder3__DOT__valid = 0U;
+        vlSelfRef.tb_priority_encoder3__DOT__code = 0U;
+        if (vlSelfRef.tb_priority_encoder3__DOT__req2) {
+            vlSelfRef.tb_priority_encoder3__DOT__valid = 1U;
+            vlSelfRef.tb_priority_encoder3__DOT__code = 2U;
+        } else if (vlSelfRef.tb_priority_encoder3__DOT__req1) {
+            vlSelfRef.tb_priority_encoder3__DOT__valid = 1U;
+            vlSelfRef.tb_priority_encoder3__DOT__code = 1U;
+        } else if (vlSelfRef.tb_priority_encoder3__DOT__req0) {
+            vlSelfRef.tb_priority_encoder3__DOT__valid = 1U;
+            vlSelfRef.tb_priority_encoder3__DOT__code = 0U;
+        }
+    }
+}
+
+void Vdesign___024root___timing_resume(Vdesign___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vdesign___024root___timing_resume\n"); );
+    Vdesign__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Body
+    if ((1ULL & vlSelfRef.__VactTriggered[0U])) {
+        vlSelfRef.__VdlySched.resume();
+    }
+}
+
+void Vdesign___024root___trigger_orInto__act_vec_vec(VlUnpacked<QData/*63:0*/, 1> &out, const VlUnpacked<QData/*63:0*/, 1> &in) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vdesign___024root___trigger_orInto__act_vec_vec\n"); );
+    // Locals
+    IData/*31:0*/ n;
+    // Body
+    n = 0U;
+    do {
+        out[n] = (out[n] | in[n]);
+        n = ((IData)(1U) + n);
+    } while ((0U >= n));
+}
+
+#ifdef VL_DEBUG
+VL_ATTR_COLD void Vdesign___024root___dump_triggers__act(const VlUnpacked<QData/*63:0*/, 1> &triggers, const std::string &tag);
+#endif  // VL_DEBUG
+
+bool Vdesign___024root___eval_phase__act(Vdesign___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vdesign___024root___eval_phase__act\n"); );
+    Vdesign__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Locals
+    CData/*0:0*/ __VactExecute;
+    // Body
+    Vdesign___024root___eval_triggers_vec__act(vlSelf);
+    Vdesign___024root___trigger_orInto__act_vec_vec(vlSelfRef.__VactTriggered, vlSelfRef.__VactTriggeredAcc);
+#ifdef VL_DEBUG
+    if (VL_UNLIKELY(vlSymsp->_vm_contextp__->debug())) {
+        Vdesign___024root___dump_triggers__act(vlSelfRef.__VactTriggered, "act"s);
+    }
+#endif
+    Vdesign___024root___trigger_orInto__act_vec_vec(vlSelfRef.__VnbaTriggered, vlSelfRef.__VactTriggered);
+    __VactExecute = Vdesign___024root___trigger_anySet__act(vlSelfRef.__VactTriggered);
+    if (__VactExecute) {
+        vlSelfRef.__VactTriggeredAcc.fill(0ULL);
+        Vdesign___024root___timing_resume(vlSelf);
+        Vdesign___024root___eval_act(vlSelf);
+    }
+    return (__VactExecute);
+}
+
+bool Vdesign___024root___eval_phase__inact(Vdesign___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vdesign___024root___eval_phase__inact\n"); );
+    Vdesign__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Locals
+    CData/*0:0*/ __VinactExecute;
+    // Body
+    __VinactExecute = vlSelfRef.__VdlySched.awaitingZeroDelay();
+    if (__VinactExecute) {
+        VL_FATAL_MT("testbench.v", 3, "", "ZERODLY: Design Verilated with '--no-sched-zero-delay', but #0 delay executed at runtime");
+    }
+    return (__VinactExecute);
+}
+
+void Vdesign___024root___trigger_clear__act(VlUnpacked<QData/*63:0*/, 1> &out) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vdesign___024root___trigger_clear__act\n"); );
+    // Locals
+    IData/*31:0*/ n;
+    // Body
+    n = 0U;
+    do {
+        out[n] = 0ULL;
+        n = ((IData)(1U) + n);
+    } while ((1U > n));
+}
+
+bool Vdesign___024root___eval_phase__nba(Vdesign___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vdesign___024root___eval_phase__nba\n"); );
+    Vdesign__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Locals
+    CData/*0:0*/ __VnbaExecute;
+    // Body
+    __VnbaExecute = Vdesign___024root___trigger_anySet__act(vlSelfRef.__VnbaTriggered);
+    if (__VnbaExecute) {
+        Vdesign___024root___eval_nba(vlSelf);
+        Vdesign___024root___trigger_clear__act(vlSelfRef.__VnbaTriggered);
+    }
+    return (__VnbaExecute);
+}
+
+void Vdesign___024root___eval(Vdesign___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vdesign___024root___eval\n"); );
+    Vdesign__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Locals
+    IData/*31:0*/ __VnbaIterCount;
+    // Body
+    __VnbaIterCount = 0U;
+    do {
+        if (VL_UNLIKELY(((0x00002710U < __VnbaIterCount)))) {
+#ifdef VL_DEBUG
+            Vdesign___024root___dump_triggers__act(vlSelfRef.__VnbaTriggered, "nba"s);
+#endif
+            VL_FATAL_MT("testbench.v", 3, "", "DIDNOTCONVERGE: NBA region did not converge after '--converge-limit' of 10000 tries");
+        }
+        __VnbaIterCount = ((IData)(1U) + __VnbaIterCount);
+        vlSelfRef.__VinactIterCount = 0U;
+        do {
+            if (VL_UNLIKELY(((0x00002710U < vlSelfRef.__VinactIterCount)))) {
+                VL_FATAL_MT("testbench.v", 3, "", "DIDNOTCONVERGE: Inactive region did not converge after '--converge-limit' of 10000 tries");
+            }
+            vlSelfRef.__VinactIterCount = ((IData)(1U) 
+                                           + vlSelfRef.__VinactIterCount);
+            vlSelfRef.__VactIterCount = 0U;
+            do {
+                if (VL_UNLIKELY(((0x00002710U < vlSelfRef.__VactIterCount)))) {
+#ifdef VL_DEBUG
+                    Vdesign___024root___dump_triggers__act(vlSelfRef.__VactTriggered, "act"s);
+#endif
+                    VL_FATAL_MT("testbench.v", 3, "", "DIDNOTCONVERGE: Active region did not converge after '--converge-limit' of 10000 tries");
+                }
+                vlSelfRef.__VactIterCount = ((IData)(1U) 
+                                             + vlSelfRef.__VactIterCount);
+                vlSelfRef.__VactPhaseResult = Vdesign___024root___eval_phase__act(vlSelf);
+            } while (vlSelfRef.__VactPhaseResult);
+            vlSelfRef.__VinactPhaseResult = Vdesign___024root___eval_phase__inact(vlSelf);
+        } while (vlSelfRef.__VinactPhaseResult);
+        vlSelfRef.__VnbaPhaseResult = Vdesign___024root___eval_phase__nba(vlSelf);
+    } while (vlSelfRef.__VnbaPhaseResult);
+}
+
+#ifdef VL_DEBUG
+void Vdesign___024root___eval_debug_assertions(Vdesign___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vdesign___024root___eval_debug_assertions\n"); );
+    Vdesign__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+}
+#endif  // VL_DEBUG

server/tasks/hard/01_priority_encoder_latch/obj_dir/Vdesign___024root__0__Slow.cpp

@@ -0,0 +1,172 @@
+// Verilated -*- C++ -*-
+// DESCRIPTION: Verilator output: Design implementation internals
+// See Vdesign.h for the primary calling header
+
+#include "Vdesign__pch.h"
+
+VL_ATTR_COLD void Vdesign___024root___eval_static(Vdesign___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vdesign___024root___eval_static\n"); );
+    Vdesign__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Body
+    do {
+        vlSelfRef.__VactTriggeredAcc[vlSelfRef.__Vi] 
+            = vlSelfRef.__VactTriggered[vlSelfRef.__Vi];
+        vlSelfRef.__Vi = ((IData)(1U) + vlSelfRef.__Vi);
+    } while ((0U >= vlSelfRef.__Vi));
+}
+
+VL_ATTR_COLD void Vdesign___024root___eval_final(Vdesign___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vdesign___024root___eval_final\n"); );
+    Vdesign__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+}
+
+#ifdef VL_DEBUG
+VL_ATTR_COLD void Vdesign___024root___dump_triggers__stl(const VlUnpacked<QData/*63:0*/, 1> &triggers, const std::string &tag);
+#endif  // VL_DEBUG
+VL_ATTR_COLD bool Vdesign___024root___eval_phase__stl(Vdesign___024root* vlSelf);
+
+VL_ATTR_COLD void Vdesign___024root___eval_settle(Vdesign___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vdesign___024root___eval_settle\n"); );
+    Vdesign__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Locals
+    IData/*31:0*/ __VstlIterCount;
+    // Body
+    __VstlIterCount = 0U;
+    vlSelfRef.__VstlFirstIteration = 1U;
+    do {
+        if (VL_UNLIKELY(((0x00002710U < __VstlIterCount)))) {
+#ifdef VL_DEBUG
+            Vdesign___024root___dump_triggers__stl(vlSelfRef.__VstlTriggered, "stl"s);
+#endif
+            VL_FATAL_MT("testbench.v", 3, "", "DIDNOTCONVERGE: Settle region did not converge after '--converge-limit' of 10000 tries");
+        }
+        __VstlIterCount = ((IData)(1U) + __VstlIterCount);
+        vlSelfRef.__VstlPhaseResult = Vdesign___024root___eval_phase__stl(vlSelf);
+        vlSelfRef.__VstlFirstIteration = 0U;
+    } while (vlSelfRef.__VstlPhaseResult);
+}
+
+VL_ATTR_COLD void Vdesign___024root___eval_triggers_vec__stl(Vdesign___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vdesign___024root___eval_triggers_vec__stl\n"); );
+    Vdesign__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Body
+    vlSelfRef.__VstlTriggered[0U] = ((0xfffffffffffffffeULL 
+                                      & vlSelfRef.__VstlTriggered[0U]) 
+                                     | (IData)((IData)(vlSelfRef.__VstlFirstIteration)));
+}
+
+VL_ATTR_COLD bool Vdesign___024root___trigger_anySet__stl(const VlUnpacked<QData/*63:0*/, 1> &in);
+
+#ifdef VL_DEBUG
+VL_ATTR_COLD void Vdesign___024root___dump_triggers__stl(const VlUnpacked<QData/*63:0*/, 1> &triggers, const std::string &tag) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vdesign___024root___dump_triggers__stl\n"); );
+    // Body
+    if ((1U & (~ (IData)(Vdesign___024root___trigger_anySet__stl(triggers))))) {
+        VL_DBG_MSGS("         No '" + tag + "' region triggers active\n");
+    }
+    if ((1U & (IData)(triggers[0U]))) {
+        VL_DBG_MSGS("         '" + tag + "' region trigger index 0 is active: Internal 'stl' trigger - first iteration\n");
+    }
+}
+#endif  // VL_DEBUG
+
+VL_ATTR_COLD bool Vdesign___024root___trigger_anySet__stl(const VlUnpacked<QData/*63:0*/, 1> &in) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vdesign___024root___trigger_anySet__stl\n"); );
+    // Locals
+    IData/*31:0*/ n;
+    // Body
+    n = 0U;
+    do {
+        if (in[n]) {
+            return (1U);
+        }
+        n = ((IData)(1U) + n);
+    } while ((1U > n));
+    return (0U);
+}
+
+VL_ATTR_COLD void Vdesign___024root___eval_stl(Vdesign___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vdesign___024root___eval_stl\n"); );
+    Vdesign__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Body
+    if ((1ULL & vlSelfRef.__VstlTriggered[0U])) {
+        vlSelfRef.tb_priority_encoder3__DOT__valid = 0U;
+        vlSelfRef.tb_priority_encoder3__DOT__code = 0U;
+        if (vlSelfRef.tb_priority_encoder3__DOT__req2) {
+            vlSelfRef.tb_priority_encoder3__DOT__valid = 1U;
+            vlSelfRef.tb_priority_encoder3__DOT__code = 2U;
+        } else if (vlSelfRef.tb_priority_encoder3__DOT__req1) {
+            vlSelfRef.tb_priority_encoder3__DOT__valid = 1U;
+            vlSelfRef.tb_priority_encoder3__DOT__code = 1U;
+        } else if (vlSelfRef.tb_priority_encoder3__DOT__req0) {
+            vlSelfRef.tb_priority_encoder3__DOT__valid = 1U;
+            vlSelfRef.tb_priority_encoder3__DOT__code = 0U;
+        }
+    }
+}
+
+VL_ATTR_COLD bool Vdesign___024root___eval_phase__stl(Vdesign___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vdesign___024root___eval_phase__stl\n"); );
+    Vdesign__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Locals
+    CData/*0:0*/ __VstlExecute;
+    // Body
+    Vdesign___024root___eval_triggers_vec__stl(vlSelf);
+#ifdef VL_DEBUG
+    if (VL_UNLIKELY(vlSymsp->_vm_contextp__->debug())) {
+        Vdesign___024root___dump_triggers__stl(vlSelfRef.__VstlTriggered, "stl"s);
+    }
+#endif
+    __VstlExecute = Vdesign___024root___trigger_anySet__stl(vlSelfRef.__VstlTriggered);
+    if (__VstlExecute) {
+        Vdesign___024root___eval_stl(vlSelf);
+    }
+    return (__VstlExecute);
+}
+
+bool Vdesign___024root___trigger_anySet__act(const VlUnpacked<QData/*63:0*/, 1> &in);
+
+#ifdef VL_DEBUG
+VL_ATTR_COLD void Vdesign___024root___dump_triggers__act(const VlUnpacked<QData/*63:0*/, 1> &triggers, const std::string &tag) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vdesign___024root___dump_triggers__act\n"); );
+    // Body
+    if ((1U & (~ (IData)(Vdesign___024root___trigger_anySet__act(triggers))))) {
+        VL_DBG_MSGS("         No '" + tag + "' region triggers active\n");
+    }
+    if ((1U & (IData)(triggers[0U]))) {
+        VL_DBG_MSGS("         '" + tag + "' region trigger index 0 is active: @([true] __VdlySched.awaitingCurrentTime())\n");
+    }
+}
+#endif  // VL_DEBUG
+
+VL_ATTR_COLD void Vdesign___024root___ctor_var_reset(Vdesign___024root* vlSelf) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    Vdesign___024root___ctor_var_reset\n"); );
+    Vdesign__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
+    auto& vlSelfRef = std::ref(*vlSelf).get();
+    // Body
+    const uint64_t __VscopeHash = VL_MURMUR64_HASH(vlSelf->vlNamep);
+    vlSelf->tb_priority_encoder3__DOT__req2 = VL_SCOPED_RAND_RESET_I(1, __VscopeHash, 9943119845136453460ull);
+    vlSelf->tb_priority_encoder3__DOT__req1 = VL_SCOPED_RAND_RESET_I(1, __VscopeHash, 18060180862738191540ull);
+    vlSelf->tb_priority_encoder3__DOT__req0 = VL_SCOPED_RAND_RESET_I(1, __VscopeHash, 687725623710860105ull);
+    vlSelf->tb_priority_encoder3__DOT__valid = VL_SCOPED_RAND_RESET_I(1, __VscopeHash, 17636183473393224740ull);
+    vlSelf->tb_priority_encoder3__DOT__code = VL_SCOPED_RAND_RESET_I(2, __VscopeHash, 15448362772404662925ull);
+    for (int __Vi0 = 0; __Vi0 < 1; ++__Vi0) {
+        vlSelf->__VstlTriggered[__Vi0] = 0;
+    }
+    for (int __Vi0 = 0; __Vi0 < 1; ++__Vi0) {
+        vlSelf->__VactTriggered[__Vi0] = 0;
+    }
+    for (int __Vi0 = 0; __Vi0 < 1; ++__Vi0) {
+        vlSelf->__VactTriggeredAcc[__Vi0] = 0;
+    }
+    for (int __Vi0 = 0; __Vi0 < 1; ++__Vi0) {
+        vlSelf->__VnbaTriggered[__Vi0] = 0;
+    }
+    vlSelf->__Vi = 0;
+}

server/tasks/hard/01_priority_encoder_latch/obj_dir/Vdesign___024root__Slow.cpp

@@ -0,0 +1,24 @@
+// Verilated -*- C++ -*-
+// DESCRIPTION: Verilator output: Design implementation internals
+// See Vdesign.h for the primary calling header
+
+#include "Vdesign__pch.h"
+
+void Vdesign___024root___ctor_var_reset(Vdesign___024root* vlSelf);
+
+Vdesign___024root::Vdesign___024root(Vdesign__Syms* symsp, const char* namep)
+    : __VdlySched{*symsp->_vm_contextp__}
+ {
+    vlSymsp = symsp;
+    vlNamep = strdup(namep);
+    // Reset structure values
+    Vdesign___024root___ctor_var_reset(this);
+}
+
+void Vdesign___024root::__Vconfigure(bool first) {
+    (void)first;  // Prevent unused variable warning
+}
+
+Vdesign___024root::~Vdesign___024root() {
+    VL_DO_DANGLING(std::free(const_cast<char*>(vlNamep)), vlNamep);
+}

server/tasks/hard/01_priority_encoder_latch/obj_dir/Vdesign__main.cpp

@@ -0,0 +1,39 @@
+// Verilated -*- C++ -*-
+// DESCRIPTION: Verilator output: main() simulation loop, created with --main
+
+#include "verilated.h"
+#include "Vdesign.h"
+
+//======================
+
+int main(int argc, char** argv, char**) {
+    // Setup context, defaults, and parse command line
+    Verilated::debug(0);
+    const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
+    contextp->threads(1);
+    contextp->commandArgs(argc, argv);
+
+    // Construct the Verilated model, from Vtop.h generated from Verilating
+    const std::unique_ptr<Vdesign> topp{new Vdesign{contextp.get(), ""}};
+
+    // Simulate until $finish
+    while (VL_LIKELY(!contextp->gotFinish())) {
+        // Evaluate model
+        topp->eval();
+        // Advance time
+        if (!topp->eventsPending()) break;
+        contextp->time(topp->nextTimeSlot());
+    }
+
+    if (VL_LIKELY(!contextp->gotFinish())) {
+        VL_DEBUG_IF(VL_PRINTF("+ Exiting without $finish; no events left\n"););
+    }
+
+    // Execute 'final' processes
+    topp->final();
+
+    // Print statistical summary report
+    contextp->statsPrintSummary();
+
+    return 0;
+}

server/tasks/hard/01_priority_encoder_latch/obj_dir/Vdesign__pch.h

@@ -0,0 +1,27 @@
+// Verilated -*- C++ -*-
+// DESCRIPTION: Verilator output: Precompiled header
+//
+// Internal details; most user sources do not need this header,
+// unless using verilator public meta comments.
+// Suggest use Vdesign.h instead.
+
+#ifndef VERILATED_VDESIGN__PCH_H_
+#define VERILATED_VDESIGN__PCH_H_  // guard
+
+// GCC and Clang only will precompile headers (PCH) for the first header.
+// So, make sure this is the one and only PCH.
+// If multiple module's includes are needed, use individual includes.
+#ifdef VL_PCH_INCLUDED
+# error "Including multiple precompiled header files"
+#endif
+#define VL_PCH_INCLUDED
+
+
+#include "verilated.h"
+
+#include "Vdesign__Syms.h"
+#include "Vdesign.h"
+
+// Additional include files added using '--compiler-include'
+
+#endif  // guard

server/tasks/hard/01_priority_encoder_latch/obj_dir/Vdesign__ver.d

@@ -0,0 +1 @@
+obj_dir/Vdesign.cpp obj_dir/Vdesign.h obj_dir/Vdesign.mk obj_dir/Vdesign__Syms.h obj_dir/Vdesign__Syms__Slow.cpp obj_dir/Vdesign___024root.h obj_dir/Vdesign___024root__0.cpp obj_dir/Vdesign___024root__0__Slow.cpp obj_dir/Vdesign___024root__Slow.cpp obj_dir/Vdesign__main.cpp obj_dir/Vdesign__pch.h obj_dir/Vdesign__ver.d obj_dir/Vdesign_classes.mk  : /opt/oss-cad-suite/libexec/verilator_bin /opt/oss-cad-suite/libexec/verilator_bin /opt/oss-cad-suite/share/verilator/include/verilated_std.sv /opt/oss-cad-suite/share/verilator/include/verilated_std_waiver.vlt design.v testbench.v 

server/tasks/hard/01_priority_encoder_latch/obj_dir/Vdesign__verFiles.dat

@@ -0,0 +1,21 @@
+# DESCRIPTION: Verilator output: Timestamp data for --skip-identical.  Delete at will.
+C "-Wall --cc --binary --build-jobs 0 --build --quiet-build -Wno-fatal --timescale 1ns/1ns design.v testbench.v"
+S  15470064   408335  1775589273   781926010  1775535881           0 "unhashed" "/opt/oss-cad-suite/libexec/verilator_bin"
+S      7905   417104  1775589275   228926010  1775535881           0 "vaoJo7Sb62R3p7xvCJKmh57f4Cpmx2GHt7zuj5gO" "/opt/oss-cad-suite/share/verilator/include/verilated_std.sv"
+S      3224   417105  1775589275   228926010  1775535881           0 "Hydzkv9X77JH03JyZeFi7tBFnQaHV7yknXQxBZFr" "/opt/oss-cad-suite/share/verilator/include/verilated_std_waiver.vlt"
+S      3476     2246  1775653914   953249303  1775653914   953249303 "L54YBOTSWlZzA8XUc7Y6yejsxfiSAZUYTjl3XBdK" "design.v"
+T      3092     2251  1775653914   992730269  1775653914   992730269 "unhashed" "obj_dir/Vdesign.cpp"
+T      3431     2250  1775653914   992489978  1775653914   992489978 "unhashed" "obj_dir/Vdesign.h"
+T      1868     2259  1775653914   995424142  1775653914   995424142 "unhashed" "obj_dir/Vdesign.mk"
+T       947     2249  1775653914   992164936  1775653914   992164936 "unhashed" "obj_dir/Vdesign__Syms.h"
+T       869     2248  1775653914   991858062  1775653914   991858062 "unhashed" "obj_dir/Vdesign__Syms__Slow.cpp"
+T      1478     2253  1775653914   993146602  1775653914   993146602 "unhashed" "obj_dir/Vdesign___024root.h"
+T     18016     2256  1775653914   994400351  1775653914   994400351 "unhashed" "obj_dir/Vdesign___024root__0.cpp"
+T      7576     2255  1775653914   993895226  1775653914   993895226 "unhashed" "obj_dir/Vdesign___024root__0__Slow.cpp"
+T       707     2254  1775653914   993471518  1775653914   993471518 "unhashed" "obj_dir/Vdesign___024root__Slow.cpp"
+T      1113     2257  1775653914   994648809  1775653914   994648809 "unhashed" "obj_dir/Vdesign__main.cpp"
+T       760     2252  1775653914   992919769  1775653914   992919769 "unhashed" "obj_dir/Vdesign__pch.h"
+T       583     2260  1775653914   995824225  1775653914   995824225 "unhashed" "obj_dir/Vdesign__ver.d"
+T         0        0  1775653914   995964683  1775653914   995964683 "unhashed" "obj_dir/Vdesign__verFiles.dat"
+T      1672     2258  1775653914   995140267  1775653914   995140267 "unhashed" "obj_dir/Vdesign_classes.mk"
+S      1324       70  1775648367   130973431  1775648367   130973431 "SyGOBpqu1wHLnWY7OyVQCbE3yNLu6Z96GARVmXqC" "testbench.v"

server/tasks/hard/01_priority_encoder_latch/obj_dir/Vdesign_classes.mk

@@ -0,0 +1,53 @@
+# Verilated -*- Makefile -*-
+# DESCRIPTION: Verilator output: Make include file with class lists
+#
+# This file lists generated Verilated files, for including in higher level makefiles.
+# See Vdesign.mk for the caller.
+
+### Switches...
+# C11 constructs required?  0/1 (always on now)
+VM_C11 = 1
+# Timing enabled?  0/1
+VM_TIMING = 1
+# Coverage output mode?  0/1 (from --coverage)
+VM_COVERAGE = 0
+# Parallel builds?  0/1 (from --output-split)
+VM_PARALLEL_BUILDS = 0
+# Tracing output mode?  0/1 (from --trace-fst/--trace-saif/--trace-vcd)
+VM_TRACE = 0
+# Tracing output mode in FST format?  0/1 (from --trace-fst)
+VM_TRACE_FST = 0
+# Tracing output mode in SAIF format?  0/1 (from --trace-saif)
+VM_TRACE_SAIF = 0
+# Tracing output mode in VCD format?  0/1 (from --trace-vcd)
+VM_TRACE_VCD = 0
+
+### Object file lists...
+# Generated module classes, fast-path, compile with highest optimization
+VM_CLASSES_FAST += \
+  Vdesign \
+  Vdesign___024root__0 \
+  Vdesign__main \
+
+# Generated module classes, non-fast-path, compile with low/medium optimization
+VM_CLASSES_SLOW += \
+  Vdesign___024root__Slow \
+  Vdesign___024root__0__Slow \
+
+# Generated support classes, fast-path, compile with highest optimization
+VM_SUPPORT_FAST += \
+
+# Generated support classes, non-fast-path, compile with low/medium optimization
+VM_SUPPORT_SLOW += \
+  Vdesign__Syms__Slow \
+
+# Global classes, need linked once per executable, fast-path, compile with highest optimization
+VM_GLOBAL_FAST += \
+  verilated \
+  verilated_timing \
+  verilated_threads \
+
+# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization
+VM_GLOBAL_SLOW += \
+
+# Verilated -*- Makefile -*-

server/tasks/hard/01_priority_encoder_latch/obj_dir/verilated.d

@@ -0,0 +1,12 @@
+verilated.o: /opt/oss-cad-suite/share/verilator/include/verilated.cpp \
+ /opt/oss-cad-suite/share/verilator/include/verilated_config.h \
+ /opt/oss-cad-suite/share/verilator/include/verilatedos.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_types.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_funcs.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_imp.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_syms.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_sym_props.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_threads.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_trace.h \
+ /opt/oss-cad-suite/share/verilator/include/verilatedos_c.h

server/tasks/hard/01_priority_encoder_latch/obj_dir/verilated.o

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
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server/tasks/hard/01_priority_encoder_latch/obj_dir/verilated_threads.d

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+verilated_threads.o: \
+ /opt/oss-cad-suite/share/verilator/include/verilated_threads.cpp \
+ /opt/oss-cad-suite/share/verilator/include/verilatedos.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_threads.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_config.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_types.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_funcs.h

server/tasks/hard/01_priority_encoder_latch/obj_dir/verilated_timing.d

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+verilated_timing.o: \
+ /opt/oss-cad-suite/share/verilator/include/verilated_timing.cpp \
+ /opt/oss-cad-suite/share/verilator/include/verilated_timing.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_config.h \
+ /opt/oss-cad-suite/share/verilator/include/verilatedos.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_types.h \
+ /opt/oss-cad-suite/share/verilator/include/verilated_funcs.h